From: Luke Kenneth Casson Leighton Date: Sat, 20 Feb 2021 15:24:02 +0000 (+0000) Subject: increase core size to 50000 (DFF SRAMs) X-Git-Tag: LS180_RC3~188^2~1 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9a6706823770bffc0c49ed43f8bfdb869dffd922;p=soclayout.git increase core size to 50000 (DFF SRAMs) --- diff --git a/experiments9/doDesign.py b/experiments9/doDesign.py index 0253e78..a136d5a 100644 --- a/experiments9/doDesign.py +++ b/experiments9/doDesign.py @@ -25,7 +25,7 @@ def scriptMain (**kw): """The mandatory function to be called by Coriolis CGT/Unicorn.""" global af rvalue = True - coreSize = 28000 + coreSize = 50000 cwd = os.path.split( os.path.abspath(__file__) )[0] ioSpecs = IoSpecs() ioSpecs.loadFromPinmux( '{}/ls180/litex_pinpads.json'.format(cwd) ) diff --git a/experiments9/non_generated/full_core_4_4ksram_ls180.il b/experiments9/non_generated/full_core_4_4ksram_ls180.il new file mode 100644 index 0000000..1d9192a --- /dev/null +++ b/experiments9/non_generated/full_core_4_4ksram_ls180.il @@ -0,0 +1,432512 @@ +# Generated by Yosys 0.9+3578 (git sha1 c6ff947f, clang 9.0.1-12 -fPIC -Os) +autoidx 15288 +attribute \src "libresoc.v:5.1-333.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec.ALU_dec19" +attribute \generator "nMigen" +module \ALU_dec19 + attribute \src "libresoc.v:282.3-291.6" + wire width 3 $0\ALU_dec19_cr_in[2:0] + attribute \src "libresoc.v:292.3-301.6" + wire width 3 $0\ALU_dec19_cr_out[2:0] + attribute \src "libresoc.v:322.3-331.6" + wire width 2 $0\ALU_dec19_cry_in[1:0] + attribute \src "libresoc.v:222.3-231.6" + wire $0\ALU_dec19_cry_out[0:0] + attribute \src "libresoc.v:192.3-201.6" + wire width 13 $0\ALU_dec19_function_unit[12:0] + attribute \src "libresoc.v:262.3-271.6" + wire width 3 $0\ALU_dec19_in1_sel[2:0] + attribute \src "libresoc.v:272.3-281.6" + wire width 4 $0\ALU_dec19_in2_sel[3:0] + attribute \src "libresoc.v:252.3-261.6" + wire width 7 $0\ALU_dec19_internal_op[6:0] + attribute \src "libresoc.v:202.3-211.6" + wire $0\ALU_dec19_inv_a[0:0] + attribute \src "libresoc.v:212.3-221.6" + wire $0\ALU_dec19_inv_out[0:0] + attribute \src "libresoc.v:232.3-241.6" + wire $0\ALU_dec19_is_32b[0:0] + attribute \src "libresoc.v:302.3-311.6" + wire width 4 $0\ALU_dec19_ldst_len[3:0] + attribute \src "libresoc.v:312.3-321.6" + wire width 2 $0\ALU_dec19_rc_sel[1:0] + attribute \src "libresoc.v:242.3-251.6" + wire $0\ALU_dec19_sgn[0:0] + attribute \src "libresoc.v:6.7-6.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:282.3-291.6" + wire width 3 $1\ALU_dec19_cr_in[2:0] + attribute \src "libresoc.v:292.3-301.6" + wire width 3 $1\ALU_dec19_cr_out[2:0] + attribute \src "libresoc.v:322.3-331.6" + wire width 2 $1\ALU_dec19_cry_in[1:0] + attribute \src "libresoc.v:222.3-231.6" + wire $1\ALU_dec19_cry_out[0:0] + attribute \src "libresoc.v:192.3-201.6" + wire width 13 $1\ALU_dec19_function_unit[12:0] + attribute \src "libresoc.v:262.3-271.6" + wire width 3 $1\ALU_dec19_in1_sel[2:0] + attribute \src "libresoc.v:272.3-281.6" + wire width 4 $1\ALU_dec19_in2_sel[3:0] + attribute \src "libresoc.v:252.3-261.6" + wire width 7 $1\ALU_dec19_internal_op[6:0] + attribute \src "libresoc.v:202.3-211.6" + wire $1\ALU_dec19_inv_a[0:0] + attribute \src "libresoc.v:212.3-221.6" + wire $1\ALU_dec19_inv_out[0:0] + attribute \src "libresoc.v:232.3-241.6" + wire $1\ALU_dec19_is_32b[0:0] + attribute \src "libresoc.v:302.3-311.6" + wire width 4 $1\ALU_dec19_ldst_len[3:0] + attribute \src "libresoc.v:312.3-321.6" + wire width 2 $1\ALU_dec19_rc_sel[1:0] + attribute \src "libresoc.v:242.3-251.6" + wire $1\ALU_dec19_sgn[0:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 5 \ALU_dec19_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 6 \ALU_dec19_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 9 \ALU_dec19_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 12 \ALU_dec19_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 13 output 1 \ALU_dec19_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 3 \ALU_dec19_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 4 \ALU_dec19_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 output 2 \ALU_dec19_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 10 \ALU_dec19_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 11 \ALU_dec19_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 13 \ALU_dec19_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 7 \ALU_dec19_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 8 \ALU_dec19_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 14 \ALU_dec19_sgn + attribute \src "libresoc.v:6.7-6.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + wire width 32 input 15 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + wire width 10 \opcode_switch + attribute \src "libresoc.v:192.3-201.6" + process $proc$libresoc.v:192$1 + assign { } { } + assign { } { } + assign $0\ALU_dec19_function_unit[12:0] $1\ALU_dec19_function_unit[12:0] + attribute \src "libresoc.v:193.5-193.29" + switch \initial + attribute \src "libresoc.v:193.9-193.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\ALU_dec19_function_unit[12:0] 13'0000000000010 + case + assign $1\ALU_dec19_function_unit[12:0] 13'0000000000000 + end + sync always + update \ALU_dec19_function_unit $0\ALU_dec19_function_unit[12:0] + end + attribute \src "libresoc.v:202.3-211.6" + process $proc$libresoc.v:202$2 + assign { } { } + assign { } { } + assign $0\ALU_dec19_inv_a[0:0] $1\ALU_dec19_inv_a[0:0] + attribute \src "libresoc.v:203.5-203.29" + switch \initial + attribute \src "libresoc.v:203.9-203.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\ALU_dec19_inv_a[0:0] 1'0 + case + assign $1\ALU_dec19_inv_a[0:0] 1'0 + end + sync always + update \ALU_dec19_inv_a $0\ALU_dec19_inv_a[0:0] + end + attribute \src "libresoc.v:212.3-221.6" + process $proc$libresoc.v:212$3 + assign { } { } + assign { } { } + assign $0\ALU_dec19_inv_out[0:0] $1\ALU_dec19_inv_out[0:0] + attribute \src "libresoc.v:213.5-213.29" + switch \initial + attribute \src "libresoc.v:213.9-213.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\ALU_dec19_inv_out[0:0] 1'0 + case + assign $1\ALU_dec19_inv_out[0:0] 1'0 + end + sync always + update \ALU_dec19_inv_out $0\ALU_dec19_inv_out[0:0] + end + attribute \src "libresoc.v:222.3-231.6" + process $proc$libresoc.v:222$4 + assign { } { } + assign { } { } + assign $0\ALU_dec19_cry_out[0:0] $1\ALU_dec19_cry_out[0:0] + attribute \src "libresoc.v:223.5-223.29" + switch \initial + attribute \src "libresoc.v:223.9-223.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\ALU_dec19_cry_out[0:0] 1'0 + case + assign $1\ALU_dec19_cry_out[0:0] 1'0 + end + sync always + update \ALU_dec19_cry_out $0\ALU_dec19_cry_out[0:0] + end + attribute \src "libresoc.v:232.3-241.6" + process $proc$libresoc.v:232$5 + assign { } { } + assign { } { } + assign $0\ALU_dec19_is_32b[0:0] $1\ALU_dec19_is_32b[0:0] + attribute \src "libresoc.v:233.5-233.29" + switch \initial + attribute \src "libresoc.v:233.9-233.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\ALU_dec19_is_32b[0:0] 1'0 + case + assign $1\ALU_dec19_is_32b[0:0] 1'0 + end + sync always + update \ALU_dec19_is_32b $0\ALU_dec19_is_32b[0:0] + end + attribute \src "libresoc.v:242.3-251.6" + process $proc$libresoc.v:242$6 + assign { } { } + assign { } { } + assign $0\ALU_dec19_sgn[0:0] $1\ALU_dec19_sgn[0:0] + attribute \src "libresoc.v:243.5-243.29" + switch \initial + attribute \src "libresoc.v:243.9-243.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\ALU_dec19_sgn[0:0] 1'0 + case + assign $1\ALU_dec19_sgn[0:0] 1'0 + end + sync always + update \ALU_dec19_sgn $0\ALU_dec19_sgn[0:0] + end + attribute \src "libresoc.v:252.3-261.6" + process $proc$libresoc.v:252$7 + assign { } { } + assign { } { } + assign $0\ALU_dec19_internal_op[6:0] $1\ALU_dec19_internal_op[6:0] + attribute \src "libresoc.v:253.5-253.29" + switch \initial + attribute \src "libresoc.v:253.9-253.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\ALU_dec19_internal_op[6:0] 7'0100100 + case + assign $1\ALU_dec19_internal_op[6:0] 7'0000000 + end + sync always + update \ALU_dec19_internal_op $0\ALU_dec19_internal_op[6:0] + end + attribute \src "libresoc.v:262.3-271.6" + process $proc$libresoc.v:262$8 + assign { } { } + assign { } { } + assign $0\ALU_dec19_in1_sel[2:0] $1\ALU_dec19_in1_sel[2:0] + attribute \src "libresoc.v:263.5-263.29" + switch \initial + attribute \src "libresoc.v:263.9-263.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\ALU_dec19_in1_sel[2:0] 3'000 + case + assign $1\ALU_dec19_in1_sel[2:0] 3'000 + end + sync always + update \ALU_dec19_in1_sel $0\ALU_dec19_in1_sel[2:0] + end + attribute \src "libresoc.v:272.3-281.6" + process $proc$libresoc.v:272$9 + assign { } { } + assign { } { } + assign $0\ALU_dec19_in2_sel[3:0] $1\ALU_dec19_in2_sel[3:0] + attribute \src "libresoc.v:273.5-273.29" + switch \initial + attribute \src "libresoc.v:273.9-273.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\ALU_dec19_in2_sel[3:0] 4'0000 + case + assign $1\ALU_dec19_in2_sel[3:0] 4'0000 + end + sync always + update \ALU_dec19_in2_sel $0\ALU_dec19_in2_sel[3:0] + end + attribute \src "libresoc.v:282.3-291.6" + process $proc$libresoc.v:282$10 + assign { } { } + assign { } { } + assign $0\ALU_dec19_cr_in[2:0] $1\ALU_dec19_cr_in[2:0] + attribute \src "libresoc.v:283.5-283.29" + switch \initial + attribute \src "libresoc.v:283.9-283.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\ALU_dec19_cr_in[2:0] 3'000 + case + assign $1\ALU_dec19_cr_in[2:0] 3'000 + end + sync always + update \ALU_dec19_cr_in $0\ALU_dec19_cr_in[2:0] + end + attribute \src "libresoc.v:292.3-301.6" + process $proc$libresoc.v:292$11 + assign { } { } + assign { } { } + assign $0\ALU_dec19_cr_out[2:0] $1\ALU_dec19_cr_out[2:0] + attribute \src "libresoc.v:293.5-293.29" + switch \initial + attribute \src "libresoc.v:293.9-293.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\ALU_dec19_cr_out[2:0] 3'000 + case + assign $1\ALU_dec19_cr_out[2:0] 3'000 + end + sync always + update \ALU_dec19_cr_out $0\ALU_dec19_cr_out[2:0] + end + attribute \src "libresoc.v:302.3-311.6" + process $proc$libresoc.v:302$12 + assign { } { } + assign { } { } + assign $0\ALU_dec19_ldst_len[3:0] $1\ALU_dec19_ldst_len[3:0] + attribute \src "libresoc.v:303.5-303.29" + switch \initial + attribute \src "libresoc.v:303.9-303.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\ALU_dec19_ldst_len[3:0] 4'0000 + case + assign $1\ALU_dec19_ldst_len[3:0] 4'0000 + end + sync always + update \ALU_dec19_ldst_len $0\ALU_dec19_ldst_len[3:0] + end + attribute \src "libresoc.v:312.3-321.6" + process $proc$libresoc.v:312$13 + assign { } { } + assign { } { } + assign $0\ALU_dec19_rc_sel[1:0] $1\ALU_dec19_rc_sel[1:0] + attribute \src "libresoc.v:313.5-313.29" + switch \initial + attribute \src "libresoc.v:313.9-313.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\ALU_dec19_rc_sel[1:0] 2'00 + case + assign $1\ALU_dec19_rc_sel[1:0] 2'00 + end + sync always + update \ALU_dec19_rc_sel $0\ALU_dec19_rc_sel[1:0] + end + attribute \src "libresoc.v:322.3-331.6" + process $proc$libresoc.v:322$14 + assign { } { } + assign { } { } + assign $0\ALU_dec19_cry_in[1:0] $1\ALU_dec19_cry_in[1:0] + attribute \src "libresoc.v:323.5-323.29" + switch \initial + attribute \src "libresoc.v:323.9-323.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\ALU_dec19_cry_in[1:0] 2'00 + case + assign $1\ALU_dec19_cry_in[1:0] 2'00 + end + sync always + update \ALU_dec19_cry_in $0\ALU_dec19_cry_in[1:0] + end + attribute \src "libresoc.v:6.7-6.20" + process $proc$libresoc.v:6$15 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + connect \opcode_switch \opcode_in [10:1] +end +attribute \src "libresoc.v:337.1-1771.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec.ALU_dec31" +attribute \generator "nMigen" +module \ALU_dec31 + attribute \src "libresoc.v:1478.3-1499.6" + wire width 3 $0\ALU_dec31_cr_in[2:0] + attribute \src "libresoc.v:1500.3-1521.6" + wire width 3 $0\ALU_dec31_cr_out[2:0] + attribute \src "libresoc.v:1566.3-1587.6" + wire width 2 $0\ALU_dec31_cry_in[1:0] + attribute \src "libresoc.v:1632.3-1653.6" + wire $0\ALU_dec31_cry_out[0:0] + attribute \src "libresoc.v:1698.3-1719.6" + wire width 13 $0\ALU_dec31_function_unit[12:0] + attribute \src "libresoc.v:1742.3-1763.6" + wire width 3 $0\ALU_dec31_in1_sel[2:0] + attribute \src "libresoc.v:1456.3-1477.6" + wire width 4 $0\ALU_dec31_in2_sel[3:0] + attribute \src "libresoc.v:1720.3-1741.6" + wire width 7 $0\ALU_dec31_internal_op[6:0] + attribute \src "libresoc.v:1588.3-1609.6" + wire $0\ALU_dec31_inv_a[0:0] + attribute \src "libresoc.v:1610.3-1631.6" + wire $0\ALU_dec31_inv_out[0:0] + attribute \src "libresoc.v:1654.3-1675.6" + wire $0\ALU_dec31_is_32b[0:0] + attribute \src "libresoc.v:1522.3-1543.6" + wire width 4 $0\ALU_dec31_ldst_len[3:0] + attribute \src "libresoc.v:1544.3-1565.6" + wire width 2 $0\ALU_dec31_rc_sel[1:0] + attribute \src "libresoc.v:1676.3-1697.6" + wire $0\ALU_dec31_sgn[0:0] + attribute \src "libresoc.v:338.7-338.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:1478.3-1499.6" + wire width 3 $1\ALU_dec31_cr_in[2:0] + attribute \src "libresoc.v:1500.3-1521.6" + wire width 3 $1\ALU_dec31_cr_out[2:0] + attribute \src "libresoc.v:1566.3-1587.6" + wire width 2 $1\ALU_dec31_cry_in[1:0] + attribute \src "libresoc.v:1632.3-1653.6" + wire $1\ALU_dec31_cry_out[0:0] + attribute \src "libresoc.v:1698.3-1719.6" + wire width 13 $1\ALU_dec31_function_unit[12:0] + attribute \src "libresoc.v:1742.3-1763.6" + wire width 3 $1\ALU_dec31_in1_sel[2:0] + attribute \src "libresoc.v:1456.3-1477.6" + wire width 4 $1\ALU_dec31_in2_sel[3:0] + attribute \src "libresoc.v:1720.3-1741.6" + wire width 7 $1\ALU_dec31_internal_op[6:0] + attribute \src "libresoc.v:1588.3-1609.6" + wire $1\ALU_dec31_inv_a[0:0] + attribute \src "libresoc.v:1610.3-1631.6" + wire $1\ALU_dec31_inv_out[0:0] + attribute \src "libresoc.v:1654.3-1675.6" + wire $1\ALU_dec31_is_32b[0:0] + attribute \src "libresoc.v:1522.3-1543.6" + wire width 4 $1\ALU_dec31_ldst_len[3:0] + attribute \src "libresoc.v:1544.3-1565.6" + wire width 2 $1\ALU_dec31_rc_sel[1:0] + attribute \src "libresoc.v:1676.3-1697.6" + wire $1\ALU_dec31_sgn[0:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 5 \ALU_dec31_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 6 \ALU_dec31_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 9 \ALU_dec31_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 12 \ALU_dec31_cry_out + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 13 \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + wire width 32 \ALU_dec31_dec_sub0_opcode_in + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 13 \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute 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32 \ALU_dec31_dec_sub26_opcode_in + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 13 \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + wire width 32 \ALU_dec31_dec_sub8_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 13 output 1 \ALU_dec31_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 3 \ALU_dec31_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 4 \ALU_dec31_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 output 2 \ALU_dec31_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 10 \ALU_dec31_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 11 \ALU_dec31_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 13 \ALU_dec31_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 7 \ALU_dec31_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 8 \ALU_dec31_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 14 \ALU_dec31_sgn + attribute \src "libresoc.v:338.7-338.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:347" + wire width 5 \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + wire width 32 input 15 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + wire width 10 \opcode_switch + attribute \module_not_derived 1 + attribute \src "libresoc.v:1371.22-1387.4" + cell \ALU_dec31_dec_sub0 \ALU_dec31_dec_sub0 + connect \ALU_dec31_dec_sub0_cr_in \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cr_in + connect \ALU_dec31_dec_sub0_cr_out \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cr_out + connect \ALU_dec31_dec_sub0_cry_in \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cry_in + connect \ALU_dec31_dec_sub0_cry_out \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cry_out + connect \ALU_dec31_dec_sub0_function_unit \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_function_unit + connect \ALU_dec31_dec_sub0_in1_sel \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_in1_sel + connect \ALU_dec31_dec_sub0_in2_sel \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_in2_sel + connect \ALU_dec31_dec_sub0_internal_op \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_internal_op + connect \ALU_dec31_dec_sub0_inv_a \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_inv_a + connect \ALU_dec31_dec_sub0_inv_out \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_inv_out + connect \ALU_dec31_dec_sub0_is_32b \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_is_32b + connect \ALU_dec31_dec_sub0_ldst_len \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_ldst_len + connect \ALU_dec31_dec_sub0_rc_sel \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_rc_sel + connect \ALU_dec31_dec_sub0_sgn \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_sgn + connect \opcode_in \ALU_dec31_dec_sub0_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:1388.23-1404.4" + cell \ALU_dec31_dec_sub10 \ALU_dec31_dec_sub10 + connect \ALU_dec31_dec_sub10_cr_in \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cr_in + connect \ALU_dec31_dec_sub10_cr_out \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cr_out + connect \ALU_dec31_dec_sub10_cry_in \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cry_in + connect \ALU_dec31_dec_sub10_cry_out \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cry_out + connect \ALU_dec31_dec_sub10_function_unit \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_function_unit + connect \ALU_dec31_dec_sub10_in1_sel \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_in1_sel + connect \ALU_dec31_dec_sub10_in2_sel \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_in2_sel + connect \ALU_dec31_dec_sub10_internal_op \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_internal_op + connect \ALU_dec31_dec_sub10_inv_a \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_inv_a + connect \ALU_dec31_dec_sub10_inv_out \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_inv_out + connect \ALU_dec31_dec_sub10_is_32b \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_is_32b + connect \ALU_dec31_dec_sub10_ldst_len \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_ldst_len + connect \ALU_dec31_dec_sub10_rc_sel \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_rc_sel + connect \ALU_dec31_dec_sub10_sgn \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_sgn + connect \opcode_in \ALU_dec31_dec_sub10_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:1405.23-1421.4" + cell \ALU_dec31_dec_sub22 \ALU_dec31_dec_sub22 + connect \ALU_dec31_dec_sub22_cr_in \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_cr_in + connect \ALU_dec31_dec_sub22_cr_out \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_cr_out + connect \ALU_dec31_dec_sub22_cry_in \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_cry_in + connect \ALU_dec31_dec_sub22_cry_out \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_cry_out + connect \ALU_dec31_dec_sub22_function_unit \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_function_unit + connect \ALU_dec31_dec_sub22_in1_sel \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_in1_sel + connect \ALU_dec31_dec_sub22_in2_sel \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_in2_sel + connect \ALU_dec31_dec_sub22_internal_op \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_internal_op + connect \ALU_dec31_dec_sub22_inv_a \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_inv_a + connect \ALU_dec31_dec_sub22_inv_out \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_inv_out + connect \ALU_dec31_dec_sub22_is_32b \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_is_32b + connect \ALU_dec31_dec_sub22_ldst_len \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_ldst_len + connect \ALU_dec31_dec_sub22_rc_sel \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_rc_sel + connect \ALU_dec31_dec_sub22_sgn \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_sgn + connect \opcode_in \ALU_dec31_dec_sub22_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:1422.23-1438.4" + cell \ALU_dec31_dec_sub26 \ALU_dec31_dec_sub26 + connect \ALU_dec31_dec_sub26_cr_in \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_cr_in + connect \ALU_dec31_dec_sub26_cr_out \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_cr_out + connect \ALU_dec31_dec_sub26_cry_in \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_cry_in + connect \ALU_dec31_dec_sub26_cry_out \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_cry_out + connect \ALU_dec31_dec_sub26_function_unit \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_function_unit + connect \ALU_dec31_dec_sub26_in1_sel \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_in1_sel + connect \ALU_dec31_dec_sub26_in2_sel \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_in2_sel + connect \ALU_dec31_dec_sub26_internal_op \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_internal_op + connect \ALU_dec31_dec_sub26_inv_a \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_inv_a + connect \ALU_dec31_dec_sub26_inv_out \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_inv_out + connect \ALU_dec31_dec_sub26_is_32b \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_is_32b + connect \ALU_dec31_dec_sub26_ldst_len \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_ldst_len + connect \ALU_dec31_dec_sub26_rc_sel \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_rc_sel + connect \ALU_dec31_dec_sub26_sgn \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_sgn + connect \opcode_in \ALU_dec31_dec_sub26_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:1439.22-1455.4" + cell \ALU_dec31_dec_sub8 \ALU_dec31_dec_sub8 + connect \ALU_dec31_dec_sub8_cr_in \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_cr_in + connect \ALU_dec31_dec_sub8_cr_out \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_cr_out + connect \ALU_dec31_dec_sub8_cry_in \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_cry_in + connect \ALU_dec31_dec_sub8_cry_out \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_cry_out + connect \ALU_dec31_dec_sub8_function_unit \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_function_unit + connect \ALU_dec31_dec_sub8_in1_sel \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_in1_sel + connect \ALU_dec31_dec_sub8_in2_sel \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_in2_sel + connect \ALU_dec31_dec_sub8_internal_op \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_internal_op + connect \ALU_dec31_dec_sub8_inv_a \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_inv_a + connect \ALU_dec31_dec_sub8_inv_out \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_inv_out + connect \ALU_dec31_dec_sub8_is_32b \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_is_32b + connect \ALU_dec31_dec_sub8_ldst_len \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_ldst_len + connect \ALU_dec31_dec_sub8_rc_sel \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_rc_sel + connect \ALU_dec31_dec_sub8_sgn \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_sgn + connect \opcode_in \ALU_dec31_dec_sub8_opcode_in + end + attribute \src "libresoc.v:1456.3-1477.6" + process $proc$libresoc.v:1456$16 + assign { } { } + assign { } { } + assign $0\ALU_dec31_in2_sel[3:0] $1\ALU_dec31_in2_sel[3:0] + attribute \src "libresoc.v:1457.5-1457.29" + switch \initial + attribute \src "libresoc.v:1457.9-1457.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\ALU_dec31_in2_sel[3:0] \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_in2_sel[3:0] \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\ALU_dec31_in2_sel[3:0] \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_in2_sel[3:0] \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_in2_sel[3:0] \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_in2_sel + case + assign $1\ALU_dec31_in2_sel[3:0] 4'0000 + end + sync always + update \ALU_dec31_in2_sel $0\ALU_dec31_in2_sel[3:0] + end + attribute \src "libresoc.v:1478.3-1499.6" + process $proc$libresoc.v:1478$17 + assign { } { } + assign { } { } + assign $0\ALU_dec31_cr_in[2:0] $1\ALU_dec31_cr_in[2:0] + attribute \src "libresoc.v:1479.5-1479.29" + switch \initial + attribute \src "libresoc.v:1479.9-1479.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\ALU_dec31_cr_in[2:0] \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_cr_in[2:0] \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\ALU_dec31_cr_in[2:0] \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_cr_in[2:0] \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_cr_in[2:0] \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_cr_in + case + assign $1\ALU_dec31_cr_in[2:0] 3'000 + end + sync always + update \ALU_dec31_cr_in $0\ALU_dec31_cr_in[2:0] + end + attribute \src "libresoc.v:1500.3-1521.6" + process $proc$libresoc.v:1500$18 + assign { } { } + assign { } { } + assign $0\ALU_dec31_cr_out[2:0] $1\ALU_dec31_cr_out[2:0] + attribute \src "libresoc.v:1501.5-1501.29" + switch \initial + attribute \src "libresoc.v:1501.9-1501.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\ALU_dec31_cr_out[2:0] \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_cr_out[2:0] \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\ALU_dec31_cr_out[2:0] \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_cr_out[2:0] \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_cr_out[2:0] \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_cr_out + case + assign $1\ALU_dec31_cr_out[2:0] 3'000 + end + sync always + update \ALU_dec31_cr_out $0\ALU_dec31_cr_out[2:0] + end + attribute \src "libresoc.v:1522.3-1543.6" + process $proc$libresoc.v:1522$19 + assign { } { } + assign { } { } + assign $0\ALU_dec31_ldst_len[3:0] $1\ALU_dec31_ldst_len[3:0] + attribute \src "libresoc.v:1523.5-1523.29" + switch \initial + attribute \src "libresoc.v:1523.9-1523.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\ALU_dec31_ldst_len[3:0] \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_ldst_len[3:0] \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\ALU_dec31_ldst_len[3:0] \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_ldst_len[3:0] \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_ldst_len[3:0] \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_ldst_len + case + assign $1\ALU_dec31_ldst_len[3:0] 4'0000 + end + sync always + update \ALU_dec31_ldst_len $0\ALU_dec31_ldst_len[3:0] + end + attribute \src "libresoc.v:1544.3-1565.6" + process $proc$libresoc.v:1544$20 + assign { } { } + assign { } { } + assign $0\ALU_dec31_rc_sel[1:0] $1\ALU_dec31_rc_sel[1:0] + attribute \src "libresoc.v:1545.5-1545.29" + switch \initial + attribute \src "libresoc.v:1545.9-1545.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\ALU_dec31_rc_sel[1:0] \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_rc_sel[1:0] \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\ALU_dec31_rc_sel[1:0] \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_rc_sel[1:0] \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_rc_sel[1:0] \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_rc_sel + case + assign $1\ALU_dec31_rc_sel[1:0] 2'00 + end + sync always + update \ALU_dec31_rc_sel $0\ALU_dec31_rc_sel[1:0] + end + attribute \src "libresoc.v:1566.3-1587.6" + process $proc$libresoc.v:1566$21 + assign { } { } + assign { } { } + assign $0\ALU_dec31_cry_in[1:0] $1\ALU_dec31_cry_in[1:0] + attribute \src "libresoc.v:1567.5-1567.29" + switch \initial + attribute \src "libresoc.v:1567.9-1567.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\ALU_dec31_cry_in[1:0] \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_cry_in[1:0] \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\ALU_dec31_cry_in[1:0] \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_cry_in[1:0] \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_cry_in[1:0] \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_cry_in + case + assign $1\ALU_dec31_cry_in[1:0] 2'00 + end + sync always + update \ALU_dec31_cry_in $0\ALU_dec31_cry_in[1:0] + end + attribute \src "libresoc.v:1588.3-1609.6" + process $proc$libresoc.v:1588$22 + assign { } { } + assign { } { } + assign $0\ALU_dec31_inv_a[0:0] $1\ALU_dec31_inv_a[0:0] + attribute \src "libresoc.v:1589.5-1589.29" + switch \initial + attribute \src "libresoc.v:1589.9-1589.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\ALU_dec31_inv_a[0:0] \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_inv_a[0:0] \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\ALU_dec31_inv_a[0:0] \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_inv_a[0:0] \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_inv_a[0:0] \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_inv_a + case + assign $1\ALU_dec31_inv_a[0:0] 1'0 + end + sync always + update \ALU_dec31_inv_a $0\ALU_dec31_inv_a[0:0] + end + attribute \src "libresoc.v:1610.3-1631.6" + process $proc$libresoc.v:1610$23 + assign { } { } + assign { } { } + assign $0\ALU_dec31_inv_out[0:0] $1\ALU_dec31_inv_out[0:0] + attribute \src "libresoc.v:1611.5-1611.29" + switch \initial + attribute \src "libresoc.v:1611.9-1611.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\ALU_dec31_inv_out[0:0] \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_inv_out[0:0] \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\ALU_dec31_inv_out[0:0] \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_inv_out[0:0] \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_inv_out[0:0] \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_inv_out + case + assign $1\ALU_dec31_inv_out[0:0] 1'0 + end + sync always + update \ALU_dec31_inv_out $0\ALU_dec31_inv_out[0:0] + end + attribute \src "libresoc.v:1632.3-1653.6" + process $proc$libresoc.v:1632$24 + assign { } { } + assign { } { } + assign $0\ALU_dec31_cry_out[0:0] $1\ALU_dec31_cry_out[0:0] + attribute \src "libresoc.v:1633.5-1633.29" + switch \initial + attribute \src "libresoc.v:1633.9-1633.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\ALU_dec31_cry_out[0:0] \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_cry_out[0:0] \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\ALU_dec31_cry_out[0:0] \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_cry_out[0:0] \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_cry_out[0:0] \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_cry_out + case + assign $1\ALU_dec31_cry_out[0:0] 1'0 + end + sync always + update \ALU_dec31_cry_out $0\ALU_dec31_cry_out[0:0] + end + attribute \src "libresoc.v:1654.3-1675.6" + process $proc$libresoc.v:1654$25 + assign { } { } + assign { } { } + assign $0\ALU_dec31_is_32b[0:0] $1\ALU_dec31_is_32b[0:0] + attribute \src "libresoc.v:1655.5-1655.29" + switch \initial + attribute \src "libresoc.v:1655.9-1655.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\ALU_dec31_is_32b[0:0] \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_is_32b[0:0] \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\ALU_dec31_is_32b[0:0] \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_is_32b[0:0] \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_is_32b[0:0] \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_is_32b + case + assign $1\ALU_dec31_is_32b[0:0] 1'0 + end + sync always + update \ALU_dec31_is_32b $0\ALU_dec31_is_32b[0:0] + end + attribute \src "libresoc.v:1676.3-1697.6" + process $proc$libresoc.v:1676$26 + assign { } { } + assign { } { } + assign $0\ALU_dec31_sgn[0:0] $1\ALU_dec31_sgn[0:0] + attribute \src "libresoc.v:1677.5-1677.29" + switch \initial + attribute \src "libresoc.v:1677.9-1677.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\ALU_dec31_sgn[0:0] \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_sgn[0:0] \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\ALU_dec31_sgn[0:0] \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_sgn[0:0] \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_sgn[0:0] \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_sgn + case + assign $1\ALU_dec31_sgn[0:0] 1'0 + end + sync always + update \ALU_dec31_sgn $0\ALU_dec31_sgn[0:0] + end + attribute \src "libresoc.v:1698.3-1719.6" + process $proc$libresoc.v:1698$27 + assign { } { } + assign { } { } + assign $0\ALU_dec31_function_unit[12:0] $1\ALU_dec31_function_unit[12:0] + attribute \src "libresoc.v:1699.5-1699.29" + switch \initial + attribute \src "libresoc.v:1699.9-1699.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\ALU_dec31_function_unit[12:0] \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_function_unit[12:0] \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\ALU_dec31_function_unit[12:0] \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_function_unit[12:0] \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_function_unit[12:0] \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_function_unit + case + assign $1\ALU_dec31_function_unit[12:0] 13'0000000000000 + end + sync always + update \ALU_dec31_function_unit $0\ALU_dec31_function_unit[12:0] + end + attribute \src "libresoc.v:1720.3-1741.6" + process $proc$libresoc.v:1720$28 + assign { } { } + assign { } { } + assign $0\ALU_dec31_internal_op[6:0] $1\ALU_dec31_internal_op[6:0] + attribute \src "libresoc.v:1721.5-1721.29" + switch \initial + attribute \src "libresoc.v:1721.9-1721.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\ALU_dec31_internal_op[6:0] \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_internal_op[6:0] \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\ALU_dec31_internal_op[6:0] \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_internal_op[6:0] \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_internal_op[6:0] \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_internal_op + case + assign $1\ALU_dec31_internal_op[6:0] 7'0000000 + end + sync always + update \ALU_dec31_internal_op $0\ALU_dec31_internal_op[6:0] + end + attribute \src "libresoc.v:1742.3-1763.6" + process $proc$libresoc.v:1742$29 + assign { } { } + assign { } { } + assign $0\ALU_dec31_in1_sel[2:0] $1\ALU_dec31_in1_sel[2:0] + attribute \src "libresoc.v:1743.5-1743.29" + switch \initial + attribute \src "libresoc.v:1743.9-1743.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\ALU_dec31_in1_sel[2:0] \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_in1_sel[2:0] \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\ALU_dec31_in1_sel[2:0] \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_in1_sel[2:0] \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_in1_sel[2:0] \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_in1_sel + case + assign $1\ALU_dec31_in1_sel[2:0] 3'000 + end + sync always + update \ALU_dec31_in1_sel $0\ALU_dec31_in1_sel[2:0] + end + attribute \src "libresoc.v:338.7-338.20" + process $proc$libresoc.v:338$30 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + connect \ALU_dec31_dec_sub8_opcode_in \opcode_in + connect \ALU_dec31_dec_sub22_opcode_in \opcode_in + connect \ALU_dec31_dec_sub26_opcode_in \opcode_in + connect \ALU_dec31_dec_sub0_opcode_in \opcode_in + connect \ALU_dec31_dec_sub10_opcode_in \opcode_in + connect \opc_in \opcode_switch [4:0] + connect \opcode_switch \opcode_in [10:1] +end +attribute \src "libresoc.v:1775.1-2187.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec.ALU_dec31.ALU_dec31_dec_sub0" +attribute \generator "nMigen" +module \ALU_dec31_dec_sub0 + attribute \src "libresoc.v:2106.3-2121.6" + wire width 3 $0\ALU_dec31_dec_sub0_cr_in[2:0] + attribute \src "libresoc.v:2122.3-2137.6" + wire width 3 $0\ALU_dec31_dec_sub0_cr_out[2:0] + attribute \src "libresoc.v:2170.3-2185.6" + wire width 2 $0\ALU_dec31_dec_sub0_cry_in[1:0] + attribute \src "libresoc.v:2010.3-2025.6" + wire $0\ALU_dec31_dec_sub0_cry_out[0:0] + attribute \src "libresoc.v:1962.3-1977.6" + wire width 13 $0\ALU_dec31_dec_sub0_function_unit[12:0] + attribute \src "libresoc.v:2074.3-2089.6" + wire width 3 $0\ALU_dec31_dec_sub0_in1_sel[2:0] + attribute \src "libresoc.v:2090.3-2105.6" + wire width 4 $0\ALU_dec31_dec_sub0_in2_sel[3:0] + attribute \src "libresoc.v:2058.3-2073.6" + wire width 7 $0\ALU_dec31_dec_sub0_internal_op[6:0] + attribute \src "libresoc.v:1978.3-1993.6" + wire $0\ALU_dec31_dec_sub0_inv_a[0:0] + attribute \src "libresoc.v:1994.3-2009.6" + wire $0\ALU_dec31_dec_sub0_inv_out[0:0] + attribute \src "libresoc.v:2026.3-2041.6" + wire $0\ALU_dec31_dec_sub0_is_32b[0:0] + attribute \src "libresoc.v:2138.3-2153.6" + wire width 4 $0\ALU_dec31_dec_sub0_ldst_len[3:0] + attribute \src "libresoc.v:2154.3-2169.6" + wire width 2 $0\ALU_dec31_dec_sub0_rc_sel[1:0] + attribute \src "libresoc.v:2042.3-2057.6" + wire $0\ALU_dec31_dec_sub0_sgn[0:0] + attribute \src "libresoc.v:1776.7-1776.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:2106.3-2121.6" + wire width 3 $1\ALU_dec31_dec_sub0_cr_in[2:0] + attribute \src "libresoc.v:2122.3-2137.6" + wire width 3 $1\ALU_dec31_dec_sub0_cr_out[2:0] + attribute \src "libresoc.v:2170.3-2185.6" + wire width 2 $1\ALU_dec31_dec_sub0_cry_in[1:0] + attribute \src "libresoc.v:2010.3-2025.6" + wire $1\ALU_dec31_dec_sub0_cry_out[0:0] + attribute \src "libresoc.v:1962.3-1977.6" + wire width 13 $1\ALU_dec31_dec_sub0_function_unit[12:0] + attribute \src "libresoc.v:2074.3-2089.6" + wire width 3 $1\ALU_dec31_dec_sub0_in1_sel[2:0] + attribute \src "libresoc.v:2090.3-2105.6" + wire width 4 $1\ALU_dec31_dec_sub0_in2_sel[3:0] + attribute \src "libresoc.v:2058.3-2073.6" + wire width 7 $1\ALU_dec31_dec_sub0_internal_op[6:0] + attribute \src "libresoc.v:1978.3-1993.6" + wire $1\ALU_dec31_dec_sub0_inv_a[0:0] + attribute \src "libresoc.v:1994.3-2009.6" + wire $1\ALU_dec31_dec_sub0_inv_out[0:0] + attribute \src "libresoc.v:2026.3-2041.6" + wire $1\ALU_dec31_dec_sub0_is_32b[0:0] + attribute \src "libresoc.v:2138.3-2153.6" + wire width 4 $1\ALU_dec31_dec_sub0_ldst_len[3:0] + attribute \src "libresoc.v:2154.3-2169.6" + wire width 2 $1\ALU_dec31_dec_sub0_rc_sel[1:0] + attribute \src "libresoc.v:2042.3-2057.6" + wire $1\ALU_dec31_dec_sub0_sgn[0:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 5 \ALU_dec31_dec_sub0_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 6 \ALU_dec31_dec_sub0_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 9 \ALU_dec31_dec_sub0_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 12 \ALU_dec31_dec_sub0_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 13 output 1 \ALU_dec31_dec_sub0_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 3 \ALU_dec31_dec_sub0_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 4 \ALU_dec31_dec_sub0_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 output 2 \ALU_dec31_dec_sub0_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 10 \ALU_dec31_dec_sub0_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 11 \ALU_dec31_dec_sub0_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 13 \ALU_dec31_dec_sub0_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 7 \ALU_dec31_dec_sub0_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 8 \ALU_dec31_dec_sub0_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 14 \ALU_dec31_dec_sub0_sgn + attribute \src "libresoc.v:1776.7-1776.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + wire width 32 input 15 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + wire width 5 \opcode_switch + attribute \src "libresoc.v:1776.7-1776.20" + process $proc$libresoc.v:1776$45 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:1962.3-1977.6" + process $proc$libresoc.v:1962$31 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub0_function_unit[12:0] $1\ALU_dec31_dec_sub0_function_unit[12:0] + attribute \src "libresoc.v:1963.5-1963.29" + switch \initial + attribute \src "libresoc.v:1963.9-1963.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub0_function_unit[12:0] 13'0000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub0_function_unit[12:0] 13'0000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub0_function_unit[12:0] 13'0000000000010 + case + assign $1\ALU_dec31_dec_sub0_function_unit[12:0] 13'0000000000000 + end + sync always + update \ALU_dec31_dec_sub0_function_unit $0\ALU_dec31_dec_sub0_function_unit[12:0] + end + attribute \src "libresoc.v:1978.3-1993.6" + process $proc$libresoc.v:1978$32 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub0_inv_a[0:0] $1\ALU_dec31_dec_sub0_inv_a[0:0] + attribute \src "libresoc.v:1979.5-1979.29" + switch \initial + attribute \src "libresoc.v:1979.9-1979.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub0_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub0_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub0_inv_a[0:0] 1'1 + case + assign $1\ALU_dec31_dec_sub0_inv_a[0:0] 1'0 + end + sync always + update \ALU_dec31_dec_sub0_inv_a $0\ALU_dec31_dec_sub0_inv_a[0:0] + end + attribute \src "libresoc.v:1994.3-2009.6" + process $proc$libresoc.v:1994$33 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub0_inv_out[0:0] $1\ALU_dec31_dec_sub0_inv_out[0:0] + attribute \src "libresoc.v:1995.5-1995.29" + switch \initial + attribute \src "libresoc.v:1995.9-1995.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub0_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub0_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub0_inv_out[0:0] 1'0 + case + assign $1\ALU_dec31_dec_sub0_inv_out[0:0] 1'0 + end + sync always + update \ALU_dec31_dec_sub0_inv_out $0\ALU_dec31_dec_sub0_inv_out[0:0] + end + attribute \src "libresoc.v:2010.3-2025.6" + process $proc$libresoc.v:2010$34 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub0_cry_out[0:0] $1\ALU_dec31_dec_sub0_cry_out[0:0] + attribute \src "libresoc.v:2011.5-2011.29" + switch \initial + attribute \src "libresoc.v:2011.9-2011.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub0_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub0_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub0_cry_out[0:0] 1'0 + case + assign $1\ALU_dec31_dec_sub0_cry_out[0:0] 1'0 + end + sync always + update \ALU_dec31_dec_sub0_cry_out $0\ALU_dec31_dec_sub0_cry_out[0:0] + end + attribute \src "libresoc.v:2026.3-2041.6" + process $proc$libresoc.v:2026$35 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub0_is_32b[0:0] $1\ALU_dec31_dec_sub0_is_32b[0:0] + attribute \src "libresoc.v:2027.5-2027.29" + switch \initial + attribute \src "libresoc.v:2027.9-2027.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub0_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub0_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub0_is_32b[0:0] 1'0 + case + assign $1\ALU_dec31_dec_sub0_is_32b[0:0] 1'0 + end + sync always + update \ALU_dec31_dec_sub0_is_32b $0\ALU_dec31_dec_sub0_is_32b[0:0] + end + attribute \src "libresoc.v:2042.3-2057.6" + process $proc$libresoc.v:2042$36 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub0_sgn[0:0] $1\ALU_dec31_dec_sub0_sgn[0:0] + attribute \src "libresoc.v:2043.5-2043.29" + switch \initial + attribute \src "libresoc.v:2043.9-2043.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub0_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub0_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub0_sgn[0:0] 1'0 + case + assign $1\ALU_dec31_dec_sub0_sgn[0:0] 1'0 + end + sync always + update \ALU_dec31_dec_sub0_sgn $0\ALU_dec31_dec_sub0_sgn[0:0] + end + attribute \src "libresoc.v:2058.3-2073.6" + process $proc$libresoc.v:2058$37 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub0_internal_op[6:0] $1\ALU_dec31_dec_sub0_internal_op[6:0] + attribute \src "libresoc.v:2059.5-2059.29" + switch \initial + attribute \src "libresoc.v:2059.9-2059.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub0_internal_op[6:0] 7'0001010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub0_internal_op[6:0] 7'0001100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub0_internal_op[6:0] 7'0001010 + case + assign $1\ALU_dec31_dec_sub0_internal_op[6:0] 7'0000000 + end + sync always + update \ALU_dec31_dec_sub0_internal_op $0\ALU_dec31_dec_sub0_internal_op[6:0] + end + attribute \src "libresoc.v:2074.3-2089.6" + process $proc$libresoc.v:2074$38 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub0_in1_sel[2:0] $1\ALU_dec31_dec_sub0_in1_sel[2:0] + attribute \src "libresoc.v:2075.5-2075.29" + switch \initial + attribute \src "libresoc.v:2075.9-2075.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub0_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub0_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub0_in1_sel[2:0] 3'001 + case + assign $1\ALU_dec31_dec_sub0_in1_sel[2:0] 3'000 + end + sync always + update \ALU_dec31_dec_sub0_in1_sel $0\ALU_dec31_dec_sub0_in1_sel[2:0] + end + attribute \src "libresoc.v:2090.3-2105.6" + process $proc$libresoc.v:2090$39 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub0_in2_sel[3:0] $1\ALU_dec31_dec_sub0_in2_sel[3:0] + attribute \src "libresoc.v:2091.5-2091.29" + switch \initial + attribute \src "libresoc.v:2091.9-2091.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub0_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub0_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub0_in2_sel[3:0] 4'0001 + case + assign $1\ALU_dec31_dec_sub0_in2_sel[3:0] 4'0000 + end + sync always + update \ALU_dec31_dec_sub0_in2_sel $0\ALU_dec31_dec_sub0_in2_sel[3:0] + end + attribute \src "libresoc.v:2106.3-2121.6" + process $proc$libresoc.v:2106$40 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub0_cr_in[2:0] $1\ALU_dec31_dec_sub0_cr_in[2:0] + attribute \src "libresoc.v:2107.5-2107.29" + switch \initial + attribute \src "libresoc.v:2107.9-2107.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub0_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub0_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub0_cr_in[2:0] 3'000 + case + assign $1\ALU_dec31_dec_sub0_cr_in[2:0] 3'000 + end + sync always + update \ALU_dec31_dec_sub0_cr_in $0\ALU_dec31_dec_sub0_cr_in[2:0] + end + attribute \src "libresoc.v:2122.3-2137.6" + process $proc$libresoc.v:2122$41 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub0_cr_out[2:0] $1\ALU_dec31_dec_sub0_cr_out[2:0] + attribute \src "libresoc.v:2123.5-2123.29" + switch \initial + attribute \src "libresoc.v:2123.9-2123.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub0_cr_out[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub0_cr_out[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub0_cr_out[2:0] 3'010 + case + assign $1\ALU_dec31_dec_sub0_cr_out[2:0] 3'000 + end + sync always + update \ALU_dec31_dec_sub0_cr_out $0\ALU_dec31_dec_sub0_cr_out[2:0] + end + attribute \src "libresoc.v:2138.3-2153.6" + process $proc$libresoc.v:2138$42 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub0_ldst_len[3:0] $1\ALU_dec31_dec_sub0_ldst_len[3:0] + attribute \src "libresoc.v:2139.5-2139.29" + switch \initial + attribute \src "libresoc.v:2139.9-2139.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub0_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub0_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub0_ldst_len[3:0] 4'0000 + case + assign $1\ALU_dec31_dec_sub0_ldst_len[3:0] 4'0000 + end + sync always + update \ALU_dec31_dec_sub0_ldst_len $0\ALU_dec31_dec_sub0_ldst_len[3:0] + end + attribute \src "libresoc.v:2154.3-2169.6" + process $proc$libresoc.v:2154$43 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub0_rc_sel[1:0] $1\ALU_dec31_dec_sub0_rc_sel[1:0] + attribute \src "libresoc.v:2155.5-2155.29" + switch \initial + attribute \src "libresoc.v:2155.9-2155.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub0_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub0_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub0_rc_sel[1:0] 2'00 + case + assign $1\ALU_dec31_dec_sub0_rc_sel[1:0] 2'00 + end + sync always + update \ALU_dec31_dec_sub0_rc_sel $0\ALU_dec31_dec_sub0_rc_sel[1:0] + end + attribute \src "libresoc.v:2170.3-2185.6" + process $proc$libresoc.v:2170$44 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub0_cry_in[1:0] $1\ALU_dec31_dec_sub0_cry_in[1:0] + attribute \src "libresoc.v:2171.5-2171.29" + switch \initial + attribute \src "libresoc.v:2171.9-2171.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub0_cry_in[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub0_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub0_cry_in[1:0] 2'01 + case + assign $1\ALU_dec31_dec_sub0_cry_in[1:0] 2'00 + end + sync always + update \ALU_dec31_dec_sub0_cry_in $0\ALU_dec31_dec_sub0_cry_in[1:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:2191.1-2897.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec.ALU_dec31.ALU_dec31_dec_sub10" +attribute \generator "nMigen" +module \ALU_dec31_dec_sub10 + attribute \src "libresoc.v:2711.3-2747.6" + wire width 3 $0\ALU_dec31_dec_sub10_cr_in[2:0] + attribute \src "libresoc.v:2748.3-2784.6" + wire width 3 $0\ALU_dec31_dec_sub10_cr_out[2:0] + attribute \src "libresoc.v:2859.3-2895.6" + wire width 2 $0\ALU_dec31_dec_sub10_cry_in[1:0] + attribute \src "libresoc.v:2489.3-2525.6" + wire $0\ALU_dec31_dec_sub10_cry_out[0:0] + attribute \src "libresoc.v:2378.3-2414.6" + wire width 13 $0\ALU_dec31_dec_sub10_function_unit[12:0] + attribute \src "libresoc.v:2637.3-2673.6" + wire width 3 $0\ALU_dec31_dec_sub10_in1_sel[2:0] + attribute \src "libresoc.v:2674.3-2710.6" + wire width 4 $0\ALU_dec31_dec_sub10_in2_sel[3:0] + attribute \src "libresoc.v:2600.3-2636.6" + wire width 7 $0\ALU_dec31_dec_sub10_internal_op[6:0] + attribute \src "libresoc.v:2415.3-2451.6" + wire $0\ALU_dec31_dec_sub10_inv_a[0:0] + attribute \src "libresoc.v:2452.3-2488.6" + wire $0\ALU_dec31_dec_sub10_inv_out[0:0] + attribute \src "libresoc.v:2526.3-2562.6" + wire $0\ALU_dec31_dec_sub10_is_32b[0:0] + attribute \src "libresoc.v:2785.3-2821.6" + wire width 4 $0\ALU_dec31_dec_sub10_ldst_len[3:0] + attribute \src "libresoc.v:2822.3-2858.6" + wire width 2 $0\ALU_dec31_dec_sub10_rc_sel[1:0] + attribute \src "libresoc.v:2563.3-2599.6" + wire $0\ALU_dec31_dec_sub10_sgn[0:0] + attribute \src "libresoc.v:2192.7-2192.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:2711.3-2747.6" + wire width 3 $1\ALU_dec31_dec_sub10_cr_in[2:0] + attribute \src "libresoc.v:2748.3-2784.6" + wire width 3 $1\ALU_dec31_dec_sub10_cr_out[2:0] + attribute \src "libresoc.v:2859.3-2895.6" + wire width 2 $1\ALU_dec31_dec_sub10_cry_in[1:0] + attribute \src "libresoc.v:2489.3-2525.6" + wire $1\ALU_dec31_dec_sub10_cry_out[0:0] + attribute \src "libresoc.v:2378.3-2414.6" + wire width 13 $1\ALU_dec31_dec_sub10_function_unit[12:0] + attribute \src "libresoc.v:2637.3-2673.6" + wire width 3 $1\ALU_dec31_dec_sub10_in1_sel[2:0] + attribute \src "libresoc.v:2674.3-2710.6" + wire width 4 $1\ALU_dec31_dec_sub10_in2_sel[3:0] + attribute \src "libresoc.v:2600.3-2636.6" + wire width 7 $1\ALU_dec31_dec_sub10_internal_op[6:0] + attribute \src "libresoc.v:2415.3-2451.6" + wire $1\ALU_dec31_dec_sub10_inv_a[0:0] + attribute \src "libresoc.v:2452.3-2488.6" + wire $1\ALU_dec31_dec_sub10_inv_out[0:0] + attribute \src "libresoc.v:2526.3-2562.6" + wire $1\ALU_dec31_dec_sub10_is_32b[0:0] + attribute \src "libresoc.v:2785.3-2821.6" + wire width 4 $1\ALU_dec31_dec_sub10_ldst_len[3:0] + attribute \src "libresoc.v:2822.3-2858.6" + wire width 2 $1\ALU_dec31_dec_sub10_rc_sel[1:0] + attribute \src "libresoc.v:2563.3-2599.6" + wire $1\ALU_dec31_dec_sub10_sgn[0:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 5 \ALU_dec31_dec_sub10_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 6 \ALU_dec31_dec_sub10_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 9 \ALU_dec31_dec_sub10_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 12 \ALU_dec31_dec_sub10_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 13 output 1 \ALU_dec31_dec_sub10_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 3 \ALU_dec31_dec_sub10_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 4 \ALU_dec31_dec_sub10_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 output 2 \ALU_dec31_dec_sub10_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 10 \ALU_dec31_dec_sub10_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 11 \ALU_dec31_dec_sub10_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 13 \ALU_dec31_dec_sub10_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 7 \ALU_dec31_dec_sub10_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 8 \ALU_dec31_dec_sub10_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 14 \ALU_dec31_dec_sub10_sgn + attribute \src "libresoc.v:2192.7-2192.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + wire width 32 input 15 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + wire width 5 \opcode_switch + attribute \src "libresoc.v:2192.7-2192.20" + process $proc$libresoc.v:2192$60 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:2378.3-2414.6" + process $proc$libresoc.v:2378$46 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub10_function_unit[12:0] $1\ALU_dec31_dec_sub10_function_unit[12:0] + attribute \src "libresoc.v:2379.5-2379.29" + switch \initial + attribute \src "libresoc.v:2379.9-2379.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_function_unit[12:0] 13'0000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_function_unit[12:0] 13'0000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_function_unit[12:0] 13'0000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_function_unit[12:0] 13'0000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\ALU_dec31_dec_sub10_function_unit[12:0] 13'0000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\ALU_dec31_dec_sub10_function_unit[12:0] 13'0000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub10_function_unit[12:0] 13'0000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\ALU_dec31_dec_sub10_function_unit[12:0] 13'0000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\ALU_dec31_dec_sub10_function_unit[12:0] 13'0000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_dec_sub10_function_unit[12:0] 13'0000000000010 + case + assign $1\ALU_dec31_dec_sub10_function_unit[12:0] 13'0000000000000 + end + sync always + update \ALU_dec31_dec_sub10_function_unit $0\ALU_dec31_dec_sub10_function_unit[12:0] + end + attribute \src "libresoc.v:2415.3-2451.6" + process $proc$libresoc.v:2415$47 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub10_inv_a[0:0] $1\ALU_dec31_dec_sub10_inv_a[0:0] + attribute \src "libresoc.v:2416.5-2416.29" + switch \initial + attribute \src "libresoc.v:2416.9-2416.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\ALU_dec31_dec_sub10_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\ALU_dec31_dec_sub10_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub10_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\ALU_dec31_dec_sub10_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\ALU_dec31_dec_sub10_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_dec_sub10_inv_a[0:0] 1'0 + case + assign $1\ALU_dec31_dec_sub10_inv_a[0:0] 1'0 + end + sync always + update \ALU_dec31_dec_sub10_inv_a $0\ALU_dec31_dec_sub10_inv_a[0:0] + end + attribute \src "libresoc.v:2452.3-2488.6" + process $proc$libresoc.v:2452$48 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub10_inv_out[0:0] $1\ALU_dec31_dec_sub10_inv_out[0:0] + attribute \src "libresoc.v:2453.5-2453.29" + switch \initial + attribute \src "libresoc.v:2453.9-2453.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\ALU_dec31_dec_sub10_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\ALU_dec31_dec_sub10_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub10_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\ALU_dec31_dec_sub10_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\ALU_dec31_dec_sub10_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_dec_sub10_inv_out[0:0] 1'0 + case + assign $1\ALU_dec31_dec_sub10_inv_out[0:0] 1'0 + end + sync always + update \ALU_dec31_dec_sub10_inv_out $0\ALU_dec31_dec_sub10_inv_out[0:0] + end + attribute \src "libresoc.v:2489.3-2525.6" + process $proc$libresoc.v:2489$49 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub10_cry_out[0:0] $1\ALU_dec31_dec_sub10_cry_out[0:0] + attribute \src "libresoc.v:2490.5-2490.29" + switch \initial + attribute \src "libresoc.v:2490.9-2490.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cry_out[0:0] 1'1 + case + assign $1\ALU_dec31_dec_sub10_cry_out[0:0] 1'0 + end + sync always + update \ALU_dec31_dec_sub10_cry_out $0\ALU_dec31_dec_sub10_cry_out[0:0] + end + attribute \src "libresoc.v:2526.3-2562.6" + process $proc$libresoc.v:2526$50 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub10_is_32b[0:0] $1\ALU_dec31_dec_sub10_is_32b[0:0] + attribute \src "libresoc.v:2527.5-2527.29" + switch \initial + attribute \src "libresoc.v:2527.9-2527.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\ALU_dec31_dec_sub10_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\ALU_dec31_dec_sub10_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub10_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\ALU_dec31_dec_sub10_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\ALU_dec31_dec_sub10_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_dec_sub10_is_32b[0:0] 1'0 + case + assign $1\ALU_dec31_dec_sub10_is_32b[0:0] 1'0 + end + sync always + update \ALU_dec31_dec_sub10_is_32b $0\ALU_dec31_dec_sub10_is_32b[0:0] + end + attribute \src "libresoc.v:2563.3-2599.6" + process $proc$libresoc.v:2563$51 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub10_sgn[0:0] $1\ALU_dec31_dec_sub10_sgn[0:0] + attribute \src "libresoc.v:2564.5-2564.29" + switch \initial + attribute \src "libresoc.v:2564.9-2564.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\ALU_dec31_dec_sub10_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\ALU_dec31_dec_sub10_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub10_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\ALU_dec31_dec_sub10_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\ALU_dec31_dec_sub10_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_dec_sub10_sgn[0:0] 1'0 + case + assign $1\ALU_dec31_dec_sub10_sgn[0:0] 1'0 + end + sync always + update \ALU_dec31_dec_sub10_sgn $0\ALU_dec31_dec_sub10_sgn[0:0] + end + attribute \src "libresoc.v:2600.3-2636.6" + process $proc$libresoc.v:2600$52 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub10_internal_op[6:0] $1\ALU_dec31_dec_sub10_internal_op[6:0] + attribute \src "libresoc.v:2601.5-2601.29" + switch \initial + attribute \src "libresoc.v:2601.9-2601.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\ALU_dec31_dec_sub10_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\ALU_dec31_dec_sub10_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub10_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\ALU_dec31_dec_sub10_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\ALU_dec31_dec_sub10_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_dec_sub10_internal_op[6:0] 7'0000010 + case + assign $1\ALU_dec31_dec_sub10_internal_op[6:0] 7'0000000 + end + sync always + update \ALU_dec31_dec_sub10_internal_op $0\ALU_dec31_dec_sub10_internal_op[6:0] + end + attribute \src "libresoc.v:2637.3-2673.6" + process $proc$libresoc.v:2637$53 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub10_in1_sel[2:0] $1\ALU_dec31_dec_sub10_in1_sel[2:0] + attribute \src "libresoc.v:2638.5-2638.29" + switch \initial + attribute \src "libresoc.v:2638.9-2638.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\ALU_dec31_dec_sub10_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\ALU_dec31_dec_sub10_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub10_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\ALU_dec31_dec_sub10_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\ALU_dec31_dec_sub10_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_dec_sub10_in1_sel[2:0] 3'001 + case + assign $1\ALU_dec31_dec_sub10_in1_sel[2:0] 3'000 + end + sync always + update \ALU_dec31_dec_sub10_in1_sel $0\ALU_dec31_dec_sub10_in1_sel[2:0] + end + attribute \src "libresoc.v:2674.3-2710.6" + process $proc$libresoc.v:2674$54 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub10_in2_sel[3:0] $1\ALU_dec31_dec_sub10_in2_sel[3:0] + attribute \src "libresoc.v:2675.5-2675.29" + switch \initial + attribute \src "libresoc.v:2675.9-2675.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\ALU_dec31_dec_sub10_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\ALU_dec31_dec_sub10_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub10_in2_sel[3:0] 4'1001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\ALU_dec31_dec_sub10_in2_sel[3:0] 4'1001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\ALU_dec31_dec_sub10_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_dec_sub10_in2_sel[3:0] 4'0000 + case + assign $1\ALU_dec31_dec_sub10_in2_sel[3:0] 4'0000 + end + sync always + update \ALU_dec31_dec_sub10_in2_sel $0\ALU_dec31_dec_sub10_in2_sel[3:0] + end + attribute \src "libresoc.v:2711.3-2747.6" + process $proc$libresoc.v:2711$55 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub10_cr_in[2:0] $1\ALU_dec31_dec_sub10_cr_in[2:0] + attribute \src "libresoc.v:2712.5-2712.29" + switch \initial + attribute \src "libresoc.v:2712.9-2712.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cr_in[2:0] 3'000 + case + assign $1\ALU_dec31_dec_sub10_cr_in[2:0] 3'000 + end + sync always + update \ALU_dec31_dec_sub10_cr_in $0\ALU_dec31_dec_sub10_cr_in[2:0] + end + attribute \src "libresoc.v:2748.3-2784.6" + process $proc$libresoc.v:2748$56 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub10_cr_out[2:0] $1\ALU_dec31_dec_sub10_cr_out[2:0] + attribute \src "libresoc.v:2749.5-2749.29" + switch \initial + attribute \src "libresoc.v:2749.9-2749.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cr_out[2:0] 3'001 + case + assign $1\ALU_dec31_dec_sub10_cr_out[2:0] 3'000 + end + sync always + update \ALU_dec31_dec_sub10_cr_out $0\ALU_dec31_dec_sub10_cr_out[2:0] + end + attribute \src "libresoc.v:2785.3-2821.6" + process $proc$libresoc.v:2785$57 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub10_ldst_len[3:0] $1\ALU_dec31_dec_sub10_ldst_len[3:0] + attribute \src "libresoc.v:2786.5-2786.29" + switch \initial + attribute \src "libresoc.v:2786.9-2786.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\ALU_dec31_dec_sub10_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\ALU_dec31_dec_sub10_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub10_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\ALU_dec31_dec_sub10_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\ALU_dec31_dec_sub10_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_dec_sub10_ldst_len[3:0] 4'0000 + case + assign $1\ALU_dec31_dec_sub10_ldst_len[3:0] 4'0000 + end + sync always + update \ALU_dec31_dec_sub10_ldst_len $0\ALU_dec31_dec_sub10_ldst_len[3:0] + end + attribute \src "libresoc.v:2822.3-2858.6" + process $proc$libresoc.v:2822$58 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub10_rc_sel[1:0] $1\ALU_dec31_dec_sub10_rc_sel[1:0] + attribute \src "libresoc.v:2823.5-2823.29" + switch \initial + attribute \src "libresoc.v:2823.9-2823.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\ALU_dec31_dec_sub10_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\ALU_dec31_dec_sub10_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub10_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\ALU_dec31_dec_sub10_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\ALU_dec31_dec_sub10_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_dec_sub10_rc_sel[1:0] 2'10 + case + assign $1\ALU_dec31_dec_sub10_rc_sel[1:0] 2'00 + end + sync always + update \ALU_dec31_dec_sub10_rc_sel $0\ALU_dec31_dec_sub10_rc_sel[1:0] + end + attribute \src "libresoc.v:2859.3-2895.6" + process $proc$libresoc.v:2859$59 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub10_cry_in[1:0] $1\ALU_dec31_dec_sub10_cry_in[1:0] + attribute \src "libresoc.v:2860.5-2860.29" + switch \initial + attribute \src "libresoc.v:2860.9-2860.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cry_in[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cry_in[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cry_in[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cry_in[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cry_in[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cry_in[1:0] 2'10 + case + assign $1\ALU_dec31_dec_sub10_cry_in[1:0] 2'00 + end + sync always + update \ALU_dec31_dec_sub10_cry_in $0\ALU_dec31_dec_sub10_cry_in[1:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:2901.1-3481.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec.ALU_dec31.ALU_dec31_dec_sub22" +attribute \generator "nMigen" +module \ALU_dec31_dec_sub22 + attribute \src "libresoc.v:3340.3-3367.6" + wire width 3 $0\ALU_dec31_dec_sub22_cr_in[2:0] + attribute \src "libresoc.v:3368.3-3395.6" + wire width 3 $0\ALU_dec31_dec_sub22_cr_out[2:0] + attribute \src "libresoc.v:3452.3-3479.6" + wire width 2 $0\ALU_dec31_dec_sub22_cry_in[1:0] + attribute \src "libresoc.v:3172.3-3199.6" + wire $0\ALU_dec31_dec_sub22_cry_out[0:0] + attribute \src "libresoc.v:3088.3-3115.6" + wire width 13 $0\ALU_dec31_dec_sub22_function_unit[12:0] + attribute \src "libresoc.v:3284.3-3311.6" + wire width 3 $0\ALU_dec31_dec_sub22_in1_sel[2:0] + attribute \src "libresoc.v:3312.3-3339.6" + wire width 4 $0\ALU_dec31_dec_sub22_in2_sel[3:0] + attribute \src "libresoc.v:3256.3-3283.6" + wire width 7 $0\ALU_dec31_dec_sub22_internal_op[6:0] + attribute \src "libresoc.v:3116.3-3143.6" + wire $0\ALU_dec31_dec_sub22_inv_a[0:0] + attribute \src "libresoc.v:3144.3-3171.6" + wire $0\ALU_dec31_dec_sub22_inv_out[0:0] + attribute \src "libresoc.v:3200.3-3227.6" + wire $0\ALU_dec31_dec_sub22_is_32b[0:0] + attribute \src "libresoc.v:3396.3-3423.6" + wire width 4 $0\ALU_dec31_dec_sub22_ldst_len[3:0] + attribute \src "libresoc.v:3424.3-3451.6" + wire width 2 $0\ALU_dec31_dec_sub22_rc_sel[1:0] + attribute \src "libresoc.v:3228.3-3255.6" + wire $0\ALU_dec31_dec_sub22_sgn[0:0] + attribute \src "libresoc.v:2902.7-2902.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:3340.3-3367.6" + wire width 3 $1\ALU_dec31_dec_sub22_cr_in[2:0] + attribute \src "libresoc.v:3368.3-3395.6" + wire width 3 $1\ALU_dec31_dec_sub22_cr_out[2:0] + attribute \src "libresoc.v:3452.3-3479.6" + wire width 2 $1\ALU_dec31_dec_sub22_cry_in[1:0] + attribute \src "libresoc.v:3172.3-3199.6" + wire $1\ALU_dec31_dec_sub22_cry_out[0:0] + attribute \src "libresoc.v:3088.3-3115.6" + wire width 13 $1\ALU_dec31_dec_sub22_function_unit[12:0] + attribute \src "libresoc.v:3284.3-3311.6" + wire width 3 $1\ALU_dec31_dec_sub22_in1_sel[2:0] + attribute \src "libresoc.v:3312.3-3339.6" + wire width 4 $1\ALU_dec31_dec_sub22_in2_sel[3:0] + attribute \src "libresoc.v:3256.3-3283.6" + wire width 7 $1\ALU_dec31_dec_sub22_internal_op[6:0] + attribute \src "libresoc.v:3116.3-3143.6" + wire $1\ALU_dec31_dec_sub22_inv_a[0:0] + attribute \src "libresoc.v:3144.3-3171.6" + wire $1\ALU_dec31_dec_sub22_inv_out[0:0] + attribute \src "libresoc.v:3200.3-3227.6" + wire $1\ALU_dec31_dec_sub22_is_32b[0:0] + attribute \src "libresoc.v:3396.3-3423.6" + wire width 4 $1\ALU_dec31_dec_sub22_ldst_len[3:0] + attribute \src "libresoc.v:3424.3-3451.6" + wire width 2 $1\ALU_dec31_dec_sub22_rc_sel[1:0] + attribute \src "libresoc.v:3228.3-3255.6" + wire $1\ALU_dec31_dec_sub22_sgn[0:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 5 \ALU_dec31_dec_sub22_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 6 \ALU_dec31_dec_sub22_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 9 \ALU_dec31_dec_sub22_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 12 \ALU_dec31_dec_sub22_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 13 output 1 \ALU_dec31_dec_sub22_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 3 \ALU_dec31_dec_sub22_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 4 \ALU_dec31_dec_sub22_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 output 2 \ALU_dec31_dec_sub22_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 10 \ALU_dec31_dec_sub22_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 11 \ALU_dec31_dec_sub22_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 13 \ALU_dec31_dec_sub22_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 7 \ALU_dec31_dec_sub22_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 8 \ALU_dec31_dec_sub22_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 14 \ALU_dec31_dec_sub22_sgn + attribute \src "libresoc.v:2902.7-2902.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + wire width 32 input 15 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + wire width 5 \opcode_switch + attribute \src "libresoc.v:2902.7-2902.20" + process $proc$libresoc.v:2902$75 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:3088.3-3115.6" + process $proc$libresoc.v:3088$61 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub22_function_unit[12:0] $1\ALU_dec31_dec_sub22_function_unit[12:0] + attribute \src "libresoc.v:3089.5-3089.29" + switch \initial + attribute \src "libresoc.v:3089.9-3089.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\ALU_dec31_dec_sub22_function_unit[12:0] 13'0000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub22_function_unit[12:0] 13'0000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_dec_sub22_function_unit[12:0] 13'0000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub22_function_unit[12:0] 13'0000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\ALU_dec31_dec_sub22_function_unit[12:0] 13'0000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub22_function_unit[12:0] 13'0000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\ALU_dec31_dec_sub22_function_unit[12:0] 13'0000000000010 + case + assign $1\ALU_dec31_dec_sub22_function_unit[12:0] 13'0000000000000 + end + sync always + update \ALU_dec31_dec_sub22_function_unit $0\ALU_dec31_dec_sub22_function_unit[12:0] + end + attribute \src "libresoc.v:3116.3-3143.6" + process $proc$libresoc.v:3116$62 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub22_inv_a[0:0] $1\ALU_dec31_dec_sub22_inv_a[0:0] + attribute \src "libresoc.v:3117.5-3117.29" + switch \initial + attribute \src "libresoc.v:3117.9-3117.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\ALU_dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\ALU_dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\ALU_dec31_dec_sub22_inv_a[0:0] 1'0 + case + assign $1\ALU_dec31_dec_sub22_inv_a[0:0] 1'0 + end + sync always + update \ALU_dec31_dec_sub22_inv_a $0\ALU_dec31_dec_sub22_inv_a[0:0] + end + attribute \src "libresoc.v:3144.3-3171.6" + process $proc$libresoc.v:3144$63 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub22_inv_out[0:0] $1\ALU_dec31_dec_sub22_inv_out[0:0] + attribute \src "libresoc.v:3145.5-3145.29" + switch \initial + attribute \src "libresoc.v:3145.9-3145.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\ALU_dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\ALU_dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\ALU_dec31_dec_sub22_inv_out[0:0] 1'0 + case + assign $1\ALU_dec31_dec_sub22_inv_out[0:0] 1'0 + end + sync always + update \ALU_dec31_dec_sub22_inv_out $0\ALU_dec31_dec_sub22_inv_out[0:0] + end + attribute \src "libresoc.v:3172.3-3199.6" + process $proc$libresoc.v:3172$64 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub22_cry_out[0:0] $1\ALU_dec31_dec_sub22_cry_out[0:0] + attribute \src "libresoc.v:3173.5-3173.29" + switch \initial + attribute \src "libresoc.v:3173.9-3173.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\ALU_dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\ALU_dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\ALU_dec31_dec_sub22_cry_out[0:0] 1'0 + case + assign $1\ALU_dec31_dec_sub22_cry_out[0:0] 1'0 + end + sync always + update \ALU_dec31_dec_sub22_cry_out $0\ALU_dec31_dec_sub22_cry_out[0:0] + end + attribute \src "libresoc.v:3200.3-3227.6" + process $proc$libresoc.v:3200$65 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub22_is_32b[0:0] $1\ALU_dec31_dec_sub22_is_32b[0:0] + attribute \src "libresoc.v:3201.5-3201.29" + switch \initial + attribute \src "libresoc.v:3201.9-3201.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\ALU_dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\ALU_dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\ALU_dec31_dec_sub22_is_32b[0:0] 1'0 + case + assign $1\ALU_dec31_dec_sub22_is_32b[0:0] 1'0 + end + sync always + update \ALU_dec31_dec_sub22_is_32b $0\ALU_dec31_dec_sub22_is_32b[0:0] + end + attribute \src "libresoc.v:3228.3-3255.6" + process $proc$libresoc.v:3228$66 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub22_sgn[0:0] $1\ALU_dec31_dec_sub22_sgn[0:0] + attribute \src "libresoc.v:3229.5-3229.29" + switch \initial + attribute \src "libresoc.v:3229.9-3229.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\ALU_dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\ALU_dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\ALU_dec31_dec_sub22_sgn[0:0] 1'0 + case + assign $1\ALU_dec31_dec_sub22_sgn[0:0] 1'0 + end + sync always + update \ALU_dec31_dec_sub22_sgn $0\ALU_dec31_dec_sub22_sgn[0:0] + end + attribute \src "libresoc.v:3256.3-3283.6" + process $proc$libresoc.v:3256$67 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub22_internal_op[6:0] $1\ALU_dec31_dec_sub22_internal_op[6:0] + attribute \src "libresoc.v:3257.5-3257.29" + switch \initial + attribute \src "libresoc.v:3257.9-3257.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\ALU_dec31_dec_sub22_internal_op[6:0] 7'0000001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub22_internal_op[6:0] 7'0000001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_dec_sub22_internal_op[6:0] 7'0000001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub22_internal_op[6:0] 7'0000001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\ALU_dec31_dec_sub22_internal_op[6:0] 7'0100001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub22_internal_op[6:0] 7'0000001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\ALU_dec31_dec_sub22_internal_op[6:0] 7'0000001 + case + assign $1\ALU_dec31_dec_sub22_internal_op[6:0] 7'0000000 + end + sync always + update \ALU_dec31_dec_sub22_internal_op $0\ALU_dec31_dec_sub22_internal_op[6:0] + end + attribute \src "libresoc.v:3284.3-3311.6" + process $proc$libresoc.v:3284$68 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub22_in1_sel[2:0] $1\ALU_dec31_dec_sub22_in1_sel[2:0] + attribute \src "libresoc.v:3285.5-3285.29" + switch \initial + attribute \src "libresoc.v:3285.9-3285.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\ALU_dec31_dec_sub22_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub22_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_dec_sub22_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub22_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\ALU_dec31_dec_sub22_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub22_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\ALU_dec31_dec_sub22_in1_sel[2:0] 3'000 + case + assign $1\ALU_dec31_dec_sub22_in1_sel[2:0] 3'000 + end + sync always + update \ALU_dec31_dec_sub22_in1_sel $0\ALU_dec31_dec_sub22_in1_sel[2:0] + end + attribute \src "libresoc.v:3312.3-3339.6" + process $proc$libresoc.v:3312$69 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub22_in2_sel[3:0] $1\ALU_dec31_dec_sub22_in2_sel[3:0] + attribute \src "libresoc.v:3313.5-3313.29" + switch \initial + attribute \src "libresoc.v:3313.9-3313.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\ALU_dec31_dec_sub22_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub22_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_dec_sub22_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub22_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\ALU_dec31_dec_sub22_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub22_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\ALU_dec31_dec_sub22_in2_sel[3:0] 4'0000 + case + assign $1\ALU_dec31_dec_sub22_in2_sel[3:0] 4'0000 + end + sync always + update \ALU_dec31_dec_sub22_in2_sel $0\ALU_dec31_dec_sub22_in2_sel[3:0] + end + attribute \src "libresoc.v:3340.3-3367.6" + process $proc$libresoc.v:3340$70 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub22_cr_in[2:0] $1\ALU_dec31_dec_sub22_cr_in[2:0] + attribute \src "libresoc.v:3341.5-3341.29" + switch \initial + attribute \src "libresoc.v:3341.9-3341.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\ALU_dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\ALU_dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\ALU_dec31_dec_sub22_cr_in[2:0] 3'000 + case + assign $1\ALU_dec31_dec_sub22_cr_in[2:0] 3'000 + end + sync always + update \ALU_dec31_dec_sub22_cr_in $0\ALU_dec31_dec_sub22_cr_in[2:0] + end + attribute \src "libresoc.v:3368.3-3395.6" + process $proc$libresoc.v:3368$71 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub22_cr_out[2:0] $1\ALU_dec31_dec_sub22_cr_out[2:0] + attribute \src "libresoc.v:3369.5-3369.29" + switch \initial + attribute \src "libresoc.v:3369.9-3369.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\ALU_dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\ALU_dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\ALU_dec31_dec_sub22_cr_out[2:0] 3'000 + case + assign $1\ALU_dec31_dec_sub22_cr_out[2:0] 3'000 + end + sync always + update \ALU_dec31_dec_sub22_cr_out $0\ALU_dec31_dec_sub22_cr_out[2:0] + end + attribute \src "libresoc.v:3396.3-3423.6" + process $proc$libresoc.v:3396$72 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub22_ldst_len[3:0] $1\ALU_dec31_dec_sub22_ldst_len[3:0] + attribute \src "libresoc.v:3397.5-3397.29" + switch \initial + attribute \src "libresoc.v:3397.9-3397.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\ALU_dec31_dec_sub22_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub22_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_dec_sub22_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub22_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\ALU_dec31_dec_sub22_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub22_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\ALU_dec31_dec_sub22_ldst_len[3:0] 4'0000 + case + assign $1\ALU_dec31_dec_sub22_ldst_len[3:0] 4'0000 + end + sync always + update \ALU_dec31_dec_sub22_ldst_len $0\ALU_dec31_dec_sub22_ldst_len[3:0] + end + attribute \src "libresoc.v:3424.3-3451.6" + process $proc$libresoc.v:3424$73 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub22_rc_sel[1:0] $1\ALU_dec31_dec_sub22_rc_sel[1:0] + attribute \src "libresoc.v:3425.5-3425.29" + switch \initial + attribute \src "libresoc.v:3425.9-3425.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\ALU_dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\ALU_dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\ALU_dec31_dec_sub22_rc_sel[1:0] 2'00 + case + assign $1\ALU_dec31_dec_sub22_rc_sel[1:0] 2'00 + end + sync always + update \ALU_dec31_dec_sub22_rc_sel $0\ALU_dec31_dec_sub22_rc_sel[1:0] + end + attribute \src "libresoc.v:3452.3-3479.6" + process $proc$libresoc.v:3452$74 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub22_cry_in[1:0] $1\ALU_dec31_dec_sub22_cry_in[1:0] + attribute \src "libresoc.v:3453.5-3453.29" + switch \initial + attribute \src "libresoc.v:3453.9-3453.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\ALU_dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\ALU_dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\ALU_dec31_dec_sub22_cry_in[1:0] 2'00 + case + assign $1\ALU_dec31_dec_sub22_cry_in[1:0] 2'00 + end + sync always + update \ALU_dec31_dec_sub22_cry_in $0\ALU_dec31_dec_sub22_cry_in[1:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:3485.1-3897.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec.ALU_dec31.ALU_dec31_dec_sub26" +attribute \generator "nMigen" +module \ALU_dec31_dec_sub26 + attribute \src "libresoc.v:3816.3-3831.6" + wire width 3 $0\ALU_dec31_dec_sub26_cr_in[2:0] + attribute \src "libresoc.v:3832.3-3847.6" + wire width 3 $0\ALU_dec31_dec_sub26_cr_out[2:0] + attribute \src "libresoc.v:3880.3-3895.6" + wire width 2 $0\ALU_dec31_dec_sub26_cry_in[1:0] + attribute \src "libresoc.v:3720.3-3735.6" + wire $0\ALU_dec31_dec_sub26_cry_out[0:0] + attribute \src "libresoc.v:3672.3-3687.6" + wire width 13 $0\ALU_dec31_dec_sub26_function_unit[12:0] + attribute \src "libresoc.v:3784.3-3799.6" + wire width 3 $0\ALU_dec31_dec_sub26_in1_sel[2:0] + attribute \src "libresoc.v:3800.3-3815.6" + wire width 4 $0\ALU_dec31_dec_sub26_in2_sel[3:0] + attribute \src "libresoc.v:3768.3-3783.6" + wire width 7 $0\ALU_dec31_dec_sub26_internal_op[6:0] + attribute \src "libresoc.v:3688.3-3703.6" + wire $0\ALU_dec31_dec_sub26_inv_a[0:0] + attribute \src "libresoc.v:3704.3-3719.6" + wire $0\ALU_dec31_dec_sub26_inv_out[0:0] + attribute \src "libresoc.v:3736.3-3751.6" + wire $0\ALU_dec31_dec_sub26_is_32b[0:0] + attribute \src "libresoc.v:3848.3-3863.6" + wire width 4 $0\ALU_dec31_dec_sub26_ldst_len[3:0] + attribute \src "libresoc.v:3864.3-3879.6" + wire width 2 $0\ALU_dec31_dec_sub26_rc_sel[1:0] + attribute \src "libresoc.v:3752.3-3767.6" + wire $0\ALU_dec31_dec_sub26_sgn[0:0] + attribute \src "libresoc.v:3486.7-3486.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:3816.3-3831.6" + wire width 3 $1\ALU_dec31_dec_sub26_cr_in[2:0] + attribute \src "libresoc.v:3832.3-3847.6" + wire width 3 $1\ALU_dec31_dec_sub26_cr_out[2:0] + attribute \src "libresoc.v:3880.3-3895.6" + wire width 2 $1\ALU_dec31_dec_sub26_cry_in[1:0] + attribute \src "libresoc.v:3720.3-3735.6" + wire $1\ALU_dec31_dec_sub26_cry_out[0:0] + attribute \src "libresoc.v:3672.3-3687.6" + wire width 13 $1\ALU_dec31_dec_sub26_function_unit[12:0] + attribute \src "libresoc.v:3784.3-3799.6" + wire width 3 $1\ALU_dec31_dec_sub26_in1_sel[2:0] + attribute \src "libresoc.v:3800.3-3815.6" + wire width 4 $1\ALU_dec31_dec_sub26_in2_sel[3:0] + attribute \src "libresoc.v:3768.3-3783.6" + wire width 7 $1\ALU_dec31_dec_sub26_internal_op[6:0] + attribute \src "libresoc.v:3688.3-3703.6" + wire $1\ALU_dec31_dec_sub26_inv_a[0:0] + attribute \src "libresoc.v:3704.3-3719.6" + wire $1\ALU_dec31_dec_sub26_inv_out[0:0] + attribute \src "libresoc.v:3736.3-3751.6" + wire $1\ALU_dec31_dec_sub26_is_32b[0:0] + attribute \src "libresoc.v:3848.3-3863.6" + wire width 4 $1\ALU_dec31_dec_sub26_ldst_len[3:0] + attribute \src "libresoc.v:3864.3-3879.6" + wire width 2 $1\ALU_dec31_dec_sub26_rc_sel[1:0] + attribute \src "libresoc.v:3752.3-3767.6" + wire $1\ALU_dec31_dec_sub26_sgn[0:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 5 \ALU_dec31_dec_sub26_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 6 \ALU_dec31_dec_sub26_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 9 \ALU_dec31_dec_sub26_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 12 \ALU_dec31_dec_sub26_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 13 output 1 \ALU_dec31_dec_sub26_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 3 \ALU_dec31_dec_sub26_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 4 \ALU_dec31_dec_sub26_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 output 2 \ALU_dec31_dec_sub26_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 10 \ALU_dec31_dec_sub26_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 11 \ALU_dec31_dec_sub26_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 13 \ALU_dec31_dec_sub26_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 7 \ALU_dec31_dec_sub26_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 8 \ALU_dec31_dec_sub26_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 14 \ALU_dec31_dec_sub26_sgn + attribute \src "libresoc.v:3486.7-3486.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + wire width 32 input 15 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + wire width 5 \opcode_switch + attribute \src "libresoc.v:3486.7-3486.20" + process $proc$libresoc.v:3486$90 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:3672.3-3687.6" + process $proc$libresoc.v:3672$76 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub26_function_unit[12:0] $1\ALU_dec31_dec_sub26_function_unit[12:0] + attribute \src "libresoc.v:3673.5-3673.29" + switch \initial + attribute \src "libresoc.v:3673.9-3673.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\ALU_dec31_dec_sub26_function_unit[12:0] 13'0000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\ALU_dec31_dec_sub26_function_unit[12:0] 13'0000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\ALU_dec31_dec_sub26_function_unit[12:0] 13'0000000000010 + case + assign $1\ALU_dec31_dec_sub26_function_unit[12:0] 13'0000000000000 + end + sync always + update \ALU_dec31_dec_sub26_function_unit $0\ALU_dec31_dec_sub26_function_unit[12:0] + end + attribute \src "libresoc.v:3688.3-3703.6" + process $proc$libresoc.v:3688$77 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub26_inv_a[0:0] $1\ALU_dec31_dec_sub26_inv_a[0:0] + attribute \src "libresoc.v:3689.5-3689.29" + switch \initial + attribute \src "libresoc.v:3689.9-3689.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\ALU_dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\ALU_dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\ALU_dec31_dec_sub26_inv_a[0:0] 1'0 + case + assign $1\ALU_dec31_dec_sub26_inv_a[0:0] 1'0 + end + sync always + update \ALU_dec31_dec_sub26_inv_a $0\ALU_dec31_dec_sub26_inv_a[0:0] + end + attribute \src "libresoc.v:3704.3-3719.6" + process $proc$libresoc.v:3704$78 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub26_inv_out[0:0] $1\ALU_dec31_dec_sub26_inv_out[0:0] + attribute \src "libresoc.v:3705.5-3705.29" + switch \initial + attribute \src "libresoc.v:3705.9-3705.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\ALU_dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\ALU_dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\ALU_dec31_dec_sub26_inv_out[0:0] 1'0 + case + assign $1\ALU_dec31_dec_sub26_inv_out[0:0] 1'0 + end + sync always + update \ALU_dec31_dec_sub26_inv_out $0\ALU_dec31_dec_sub26_inv_out[0:0] + end + attribute \src "libresoc.v:3720.3-3735.6" + process $proc$libresoc.v:3720$79 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub26_cry_out[0:0] $1\ALU_dec31_dec_sub26_cry_out[0:0] + attribute \src "libresoc.v:3721.5-3721.29" + switch \initial + attribute \src "libresoc.v:3721.9-3721.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\ALU_dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\ALU_dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\ALU_dec31_dec_sub26_cry_out[0:0] 1'0 + case + assign $1\ALU_dec31_dec_sub26_cry_out[0:0] 1'0 + end + sync always + update \ALU_dec31_dec_sub26_cry_out $0\ALU_dec31_dec_sub26_cry_out[0:0] + end + attribute \src "libresoc.v:3736.3-3751.6" + process $proc$libresoc.v:3736$80 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub26_is_32b[0:0] $1\ALU_dec31_dec_sub26_is_32b[0:0] + attribute \src "libresoc.v:3737.5-3737.29" + switch \initial + attribute \src "libresoc.v:3737.9-3737.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\ALU_dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\ALU_dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\ALU_dec31_dec_sub26_is_32b[0:0] 1'0 + case + assign $1\ALU_dec31_dec_sub26_is_32b[0:0] 1'0 + end + sync always + update \ALU_dec31_dec_sub26_is_32b $0\ALU_dec31_dec_sub26_is_32b[0:0] + end + attribute \src "libresoc.v:3752.3-3767.6" + process $proc$libresoc.v:3752$81 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub26_sgn[0:0] $1\ALU_dec31_dec_sub26_sgn[0:0] + attribute \src "libresoc.v:3753.5-3753.29" + switch \initial + attribute \src "libresoc.v:3753.9-3753.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\ALU_dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\ALU_dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\ALU_dec31_dec_sub26_sgn[0:0] 1'0 + case + assign $1\ALU_dec31_dec_sub26_sgn[0:0] 1'0 + end + sync always + update \ALU_dec31_dec_sub26_sgn $0\ALU_dec31_dec_sub26_sgn[0:0] + end + attribute \src "libresoc.v:3768.3-3783.6" + process $proc$libresoc.v:3768$82 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub26_internal_op[6:0] $1\ALU_dec31_dec_sub26_internal_op[6:0] + attribute \src "libresoc.v:3769.5-3769.29" + switch \initial + attribute \src "libresoc.v:3769.9-3769.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\ALU_dec31_dec_sub26_internal_op[6:0] 7'0011111 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\ALU_dec31_dec_sub26_internal_op[6:0] 7'0011111 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\ALU_dec31_dec_sub26_internal_op[6:0] 7'0011111 + case + assign $1\ALU_dec31_dec_sub26_internal_op[6:0] 7'0000000 + end + sync always + update \ALU_dec31_dec_sub26_internal_op $0\ALU_dec31_dec_sub26_internal_op[6:0] + end + attribute \src "libresoc.v:3784.3-3799.6" + process $proc$libresoc.v:3784$83 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub26_in1_sel[2:0] $1\ALU_dec31_dec_sub26_in1_sel[2:0] + attribute \src "libresoc.v:3785.5-3785.29" + switch \initial + attribute \src "libresoc.v:3785.9-3785.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\ALU_dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\ALU_dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\ALU_dec31_dec_sub26_in1_sel[2:0] 3'100 + case + assign $1\ALU_dec31_dec_sub26_in1_sel[2:0] 3'000 + end + sync always + update \ALU_dec31_dec_sub26_in1_sel $0\ALU_dec31_dec_sub26_in1_sel[2:0] + end + attribute \src "libresoc.v:3800.3-3815.6" + process $proc$libresoc.v:3800$84 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub26_in2_sel[3:0] $1\ALU_dec31_dec_sub26_in2_sel[3:0] + attribute \src "libresoc.v:3801.5-3801.29" + switch \initial + attribute \src "libresoc.v:3801.9-3801.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\ALU_dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\ALU_dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\ALU_dec31_dec_sub26_in2_sel[3:0] 4'0000 + case + assign $1\ALU_dec31_dec_sub26_in2_sel[3:0] 4'0000 + end + sync always + update \ALU_dec31_dec_sub26_in2_sel $0\ALU_dec31_dec_sub26_in2_sel[3:0] + end + attribute \src "libresoc.v:3816.3-3831.6" + process $proc$libresoc.v:3816$85 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub26_cr_in[2:0] $1\ALU_dec31_dec_sub26_cr_in[2:0] + attribute \src "libresoc.v:3817.5-3817.29" + switch \initial + attribute \src "libresoc.v:3817.9-3817.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\ALU_dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\ALU_dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\ALU_dec31_dec_sub26_cr_in[2:0] 3'000 + case + assign $1\ALU_dec31_dec_sub26_cr_in[2:0] 3'000 + end + sync always + update \ALU_dec31_dec_sub26_cr_in $0\ALU_dec31_dec_sub26_cr_in[2:0] + end + attribute \src "libresoc.v:3832.3-3847.6" + process $proc$libresoc.v:3832$86 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub26_cr_out[2:0] $1\ALU_dec31_dec_sub26_cr_out[2:0] + attribute \src "libresoc.v:3833.5-3833.29" + switch \initial + attribute \src "libresoc.v:3833.9-3833.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\ALU_dec31_dec_sub26_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\ALU_dec31_dec_sub26_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\ALU_dec31_dec_sub26_cr_out[2:0] 3'001 + case + assign $1\ALU_dec31_dec_sub26_cr_out[2:0] 3'000 + end + sync always + update \ALU_dec31_dec_sub26_cr_out $0\ALU_dec31_dec_sub26_cr_out[2:0] + end + attribute \src "libresoc.v:3848.3-3863.6" + process $proc$libresoc.v:3848$87 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub26_ldst_len[3:0] $1\ALU_dec31_dec_sub26_ldst_len[3:0] + attribute \src "libresoc.v:3849.5-3849.29" + switch \initial + attribute \src "libresoc.v:3849.9-3849.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\ALU_dec31_dec_sub26_ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\ALU_dec31_dec_sub26_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\ALU_dec31_dec_sub26_ldst_len[3:0] 4'0100 + case + assign $1\ALU_dec31_dec_sub26_ldst_len[3:0] 4'0000 + end + sync always + update \ALU_dec31_dec_sub26_ldst_len $0\ALU_dec31_dec_sub26_ldst_len[3:0] + end + attribute \src "libresoc.v:3864.3-3879.6" + process $proc$libresoc.v:3864$88 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub26_rc_sel[1:0] $1\ALU_dec31_dec_sub26_rc_sel[1:0] + attribute \src "libresoc.v:3865.5-3865.29" + switch \initial + attribute \src "libresoc.v:3865.9-3865.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\ALU_dec31_dec_sub26_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\ALU_dec31_dec_sub26_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\ALU_dec31_dec_sub26_rc_sel[1:0] 2'10 + case + assign $1\ALU_dec31_dec_sub26_rc_sel[1:0] 2'00 + end + sync always + update \ALU_dec31_dec_sub26_rc_sel $0\ALU_dec31_dec_sub26_rc_sel[1:0] + end + attribute \src "libresoc.v:3880.3-3895.6" + process $proc$libresoc.v:3880$89 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub26_cry_in[1:0] $1\ALU_dec31_dec_sub26_cry_in[1:0] + attribute \src "libresoc.v:3881.5-3881.29" + switch \initial + attribute \src "libresoc.v:3881.9-3881.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\ALU_dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\ALU_dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\ALU_dec31_dec_sub26_cry_in[1:0] 2'00 + case + assign $1\ALU_dec31_dec_sub26_cry_in[1:0] 2'00 + end + sync always + update \ALU_dec31_dec_sub26_cry_in $0\ALU_dec31_dec_sub26_cry_in[1:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:3901.1-4691.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec.ALU_dec31.ALU_dec31_dec_sub8" +attribute \generator "nMigen" +module \ALU_dec31_dec_sub8 + attribute \src "libresoc.v:4475.3-4517.6" + wire width 3 $0\ALU_dec31_dec_sub8_cr_in[2:0] + attribute \src "libresoc.v:4518.3-4560.6" + wire width 3 $0\ALU_dec31_dec_sub8_cr_out[2:0] + attribute \src "libresoc.v:4647.3-4689.6" + wire width 2 $0\ALU_dec31_dec_sub8_cry_in[1:0] + attribute \src "libresoc.v:4217.3-4259.6" + wire $0\ALU_dec31_dec_sub8_cry_out[0:0] + attribute \src "libresoc.v:4088.3-4130.6" + wire width 13 $0\ALU_dec31_dec_sub8_function_unit[12:0] + attribute \src "libresoc.v:4389.3-4431.6" + wire width 3 $0\ALU_dec31_dec_sub8_in1_sel[2:0] + attribute \src "libresoc.v:4432.3-4474.6" + wire width 4 $0\ALU_dec31_dec_sub8_in2_sel[3:0] + attribute \src "libresoc.v:4346.3-4388.6" + wire width 7 $0\ALU_dec31_dec_sub8_internal_op[6:0] + attribute \src "libresoc.v:4131.3-4173.6" + wire $0\ALU_dec31_dec_sub8_inv_a[0:0] + attribute \src "libresoc.v:4174.3-4216.6" + wire $0\ALU_dec31_dec_sub8_inv_out[0:0] + attribute \src "libresoc.v:4260.3-4302.6" + wire $0\ALU_dec31_dec_sub8_is_32b[0:0] + attribute \src "libresoc.v:4561.3-4603.6" + wire width 4 $0\ALU_dec31_dec_sub8_ldst_len[3:0] + attribute \src "libresoc.v:4604.3-4646.6" + wire width 2 $0\ALU_dec31_dec_sub8_rc_sel[1:0] + attribute \src "libresoc.v:4303.3-4345.6" + wire $0\ALU_dec31_dec_sub8_sgn[0:0] + attribute \src "libresoc.v:3902.7-3902.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:4475.3-4517.6" + wire width 3 $1\ALU_dec31_dec_sub8_cr_in[2:0] + attribute \src "libresoc.v:4518.3-4560.6" + wire width 3 $1\ALU_dec31_dec_sub8_cr_out[2:0] + attribute \src "libresoc.v:4647.3-4689.6" + wire width 2 $1\ALU_dec31_dec_sub8_cry_in[1:0] + attribute \src "libresoc.v:4217.3-4259.6" + wire $1\ALU_dec31_dec_sub8_cry_out[0:0] + attribute \src "libresoc.v:4088.3-4130.6" + wire width 13 $1\ALU_dec31_dec_sub8_function_unit[12:0] + attribute \src "libresoc.v:4389.3-4431.6" + wire width 3 $1\ALU_dec31_dec_sub8_in1_sel[2:0] + attribute \src "libresoc.v:4432.3-4474.6" + wire width 4 $1\ALU_dec31_dec_sub8_in2_sel[3:0] + attribute \src "libresoc.v:4346.3-4388.6" + wire width 7 $1\ALU_dec31_dec_sub8_internal_op[6:0] + attribute \src "libresoc.v:4131.3-4173.6" + wire $1\ALU_dec31_dec_sub8_inv_a[0:0] + attribute \src "libresoc.v:4174.3-4216.6" + wire $1\ALU_dec31_dec_sub8_inv_out[0:0] + attribute \src "libresoc.v:4260.3-4302.6" + wire $1\ALU_dec31_dec_sub8_is_32b[0:0] + attribute \src "libresoc.v:4561.3-4603.6" + wire width 4 $1\ALU_dec31_dec_sub8_ldst_len[3:0] + attribute \src "libresoc.v:4604.3-4646.6" + wire width 2 $1\ALU_dec31_dec_sub8_rc_sel[1:0] + attribute \src "libresoc.v:4303.3-4345.6" + wire $1\ALU_dec31_dec_sub8_sgn[0:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 5 \ALU_dec31_dec_sub8_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 6 \ALU_dec31_dec_sub8_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 9 \ALU_dec31_dec_sub8_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 12 \ALU_dec31_dec_sub8_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 13 output 1 \ALU_dec31_dec_sub8_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 3 \ALU_dec31_dec_sub8_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 4 \ALU_dec31_dec_sub8_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 output 2 \ALU_dec31_dec_sub8_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 10 \ALU_dec31_dec_sub8_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 11 \ALU_dec31_dec_sub8_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 13 \ALU_dec31_dec_sub8_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 7 \ALU_dec31_dec_sub8_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 8 \ALU_dec31_dec_sub8_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 14 \ALU_dec31_dec_sub8_sgn + attribute \src "libresoc.v:3902.7-3902.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + wire width 32 input 15 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + wire width 5 \opcode_switch + attribute \src "libresoc.v:3902.7-3902.20" + process $proc$libresoc.v:3902$105 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:4088.3-4130.6" + process $proc$libresoc.v:4088$91 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub8_function_unit[12:0] $1\ALU_dec31_dec_sub8_function_unit[12:0] + attribute \src "libresoc.v:4089.5-4089.29" + switch \initial + attribute \src "libresoc.v:4089.9-4089.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\ALU_dec31_dec_sub8_function_unit[12:0] 13'0000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\ALU_dec31_dec_sub8_function_unit[12:0] 13'0000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub8_function_unit[12:0] 13'0000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\ALU_dec31_dec_sub8_function_unit[12:0] 13'0000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub8_function_unit[12:0] 13'0000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\ALU_dec31_dec_sub8_function_unit[12:0] 13'0000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\ALU_dec31_dec_sub8_function_unit[12:0] 13'0000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\ALU_dec31_dec_sub8_function_unit[12:0] 13'0000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub8_function_unit[12:0] 13'0000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\ALU_dec31_dec_sub8_function_unit[12:0] 13'0000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\ALU_dec31_dec_sub8_function_unit[12:0] 13'0000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_dec_sub8_function_unit[12:0] 13'0000000000010 + case + assign $1\ALU_dec31_dec_sub8_function_unit[12:0] 13'0000000000000 + end + sync always + update \ALU_dec31_dec_sub8_function_unit $0\ALU_dec31_dec_sub8_function_unit[12:0] + end + attribute \src "libresoc.v:4131.3-4173.6" + process $proc$libresoc.v:4131$92 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub8_inv_a[0:0] $1\ALU_dec31_dec_sub8_inv_a[0:0] + attribute \src "libresoc.v:4132.5-4132.29" + switch \initial + attribute \src "libresoc.v:4132.9-4132.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\ALU_dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\ALU_dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\ALU_dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\ALU_dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\ALU_dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\ALU_dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\ALU_dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\ALU_dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_dec_sub8_inv_a[0:0] 1'1 + case + assign $1\ALU_dec31_dec_sub8_inv_a[0:0] 1'0 + end + sync always + update \ALU_dec31_dec_sub8_inv_a $0\ALU_dec31_dec_sub8_inv_a[0:0] + end + attribute \src "libresoc.v:4174.3-4216.6" + process $proc$libresoc.v:4174$93 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub8_inv_out[0:0] $1\ALU_dec31_dec_sub8_inv_out[0:0] + attribute \src "libresoc.v:4175.5-4175.29" + switch \initial + attribute \src "libresoc.v:4175.9-4175.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\ALU_dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\ALU_dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\ALU_dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\ALU_dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\ALU_dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\ALU_dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\ALU_dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\ALU_dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_dec_sub8_inv_out[0:0] 1'0 + case + assign $1\ALU_dec31_dec_sub8_inv_out[0:0] 1'0 + end + sync always + update \ALU_dec31_dec_sub8_inv_out $0\ALU_dec31_dec_sub8_inv_out[0:0] + end + attribute \src "libresoc.v:4217.3-4259.6" + process $proc$libresoc.v:4217$94 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub8_cry_out[0:0] $1\ALU_dec31_dec_sub8_cry_out[0:0] + attribute \src "libresoc.v:4218.5-4218.29" + switch \initial + attribute \src "libresoc.v:4218.9-4218.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cry_out[0:0] 1'1 + case + assign $1\ALU_dec31_dec_sub8_cry_out[0:0] 1'0 + end + sync always + update \ALU_dec31_dec_sub8_cry_out $0\ALU_dec31_dec_sub8_cry_out[0:0] + end + attribute \src "libresoc.v:4260.3-4302.6" + process $proc$libresoc.v:4260$95 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub8_is_32b[0:0] $1\ALU_dec31_dec_sub8_is_32b[0:0] + attribute \src "libresoc.v:4261.5-4261.29" + switch \initial + attribute \src "libresoc.v:4261.9-4261.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\ALU_dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\ALU_dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\ALU_dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\ALU_dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\ALU_dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\ALU_dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\ALU_dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\ALU_dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_dec_sub8_is_32b[0:0] 1'0 + case + assign $1\ALU_dec31_dec_sub8_is_32b[0:0] 1'0 + end + sync always + update \ALU_dec31_dec_sub8_is_32b $0\ALU_dec31_dec_sub8_is_32b[0:0] + end + attribute \src "libresoc.v:4303.3-4345.6" + process $proc$libresoc.v:4303$96 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub8_sgn[0:0] $1\ALU_dec31_dec_sub8_sgn[0:0] + attribute \src "libresoc.v:4304.5-4304.29" + switch \initial + attribute \src "libresoc.v:4304.9-4304.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\ALU_dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\ALU_dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\ALU_dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\ALU_dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\ALU_dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\ALU_dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\ALU_dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\ALU_dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_dec_sub8_sgn[0:0] 1'0 + case + assign $1\ALU_dec31_dec_sub8_sgn[0:0] 1'0 + end + sync always + update \ALU_dec31_dec_sub8_sgn $0\ALU_dec31_dec_sub8_sgn[0:0] + end + attribute \src "libresoc.v:4346.3-4388.6" + process $proc$libresoc.v:4346$97 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub8_internal_op[6:0] $1\ALU_dec31_dec_sub8_internal_op[6:0] + attribute \src "libresoc.v:4347.5-4347.29" + switch \initial + attribute \src "libresoc.v:4347.9-4347.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\ALU_dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\ALU_dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\ALU_dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\ALU_dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\ALU_dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\ALU_dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\ALU_dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\ALU_dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_dec_sub8_internal_op[6:0] 7'0000010 + case + assign $1\ALU_dec31_dec_sub8_internal_op[6:0] 7'0000000 + end + sync always + update \ALU_dec31_dec_sub8_internal_op $0\ALU_dec31_dec_sub8_internal_op[6:0] + end + attribute \src "libresoc.v:4389.3-4431.6" + process $proc$libresoc.v:4389$98 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub8_in1_sel[2:0] $1\ALU_dec31_dec_sub8_in1_sel[2:0] + attribute \src "libresoc.v:4390.5-4390.29" + switch \initial + attribute \src "libresoc.v:4390.9-4390.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\ALU_dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\ALU_dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\ALU_dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\ALU_dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\ALU_dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\ALU_dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\ALU_dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\ALU_dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_dec_sub8_in1_sel[2:0] 3'001 + case + assign $1\ALU_dec31_dec_sub8_in1_sel[2:0] 3'000 + end + sync always + update \ALU_dec31_dec_sub8_in1_sel $0\ALU_dec31_dec_sub8_in1_sel[2:0] + end + attribute \src "libresoc.v:4432.3-4474.6" + process $proc$libresoc.v:4432$99 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub8_in2_sel[3:0] $1\ALU_dec31_dec_sub8_in2_sel[3:0] + attribute \src "libresoc.v:4433.5-4433.29" + switch \initial + attribute \src "libresoc.v:4433.9-4433.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\ALU_dec31_dec_sub8_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\ALU_dec31_dec_sub8_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub8_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\ALU_dec31_dec_sub8_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub8_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\ALU_dec31_dec_sub8_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\ALU_dec31_dec_sub8_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\ALU_dec31_dec_sub8_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub8_in2_sel[3:0] 4'1001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\ALU_dec31_dec_sub8_in2_sel[3:0] 4'1001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\ALU_dec31_dec_sub8_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_dec_sub8_in2_sel[3:0] 4'0000 + case + assign $1\ALU_dec31_dec_sub8_in2_sel[3:0] 4'0000 + end + sync always + update \ALU_dec31_dec_sub8_in2_sel $0\ALU_dec31_dec_sub8_in2_sel[3:0] + end + attribute \src "libresoc.v:4475.3-4517.6" + process $proc$libresoc.v:4475$100 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub8_cr_in[2:0] $1\ALU_dec31_dec_sub8_cr_in[2:0] + attribute \src "libresoc.v:4476.5-4476.29" + switch \initial + attribute \src "libresoc.v:4476.9-4476.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cr_in[2:0] 3'000 + case + assign $1\ALU_dec31_dec_sub8_cr_in[2:0] 3'000 + end + sync always + update \ALU_dec31_dec_sub8_cr_in $0\ALU_dec31_dec_sub8_cr_in[2:0] + end + attribute \src "libresoc.v:4518.3-4560.6" + process $proc$libresoc.v:4518$101 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub8_cr_out[2:0] $1\ALU_dec31_dec_sub8_cr_out[2:0] + attribute \src "libresoc.v:4519.5-4519.29" + switch \initial + attribute \src "libresoc.v:4519.9-4519.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cr_out[2:0] 3'001 + case + assign $1\ALU_dec31_dec_sub8_cr_out[2:0] 3'000 + end + sync always + update \ALU_dec31_dec_sub8_cr_out $0\ALU_dec31_dec_sub8_cr_out[2:0] + end + attribute \src "libresoc.v:4561.3-4603.6" + process $proc$libresoc.v:4561$102 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub8_ldst_len[3:0] $1\ALU_dec31_dec_sub8_ldst_len[3:0] + attribute \src "libresoc.v:4562.5-4562.29" + switch \initial + attribute \src "libresoc.v:4562.9-4562.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\ALU_dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\ALU_dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\ALU_dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\ALU_dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\ALU_dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\ALU_dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\ALU_dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\ALU_dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_dec_sub8_ldst_len[3:0] 4'0000 + case + assign $1\ALU_dec31_dec_sub8_ldst_len[3:0] 4'0000 + end + sync always + update \ALU_dec31_dec_sub8_ldst_len $0\ALU_dec31_dec_sub8_ldst_len[3:0] + end + attribute \src "libresoc.v:4604.3-4646.6" + process $proc$libresoc.v:4604$103 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub8_rc_sel[1:0] $1\ALU_dec31_dec_sub8_rc_sel[1:0] + attribute \src "libresoc.v:4605.5-4605.29" + switch \initial + attribute \src "libresoc.v:4605.9-4605.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\ALU_dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\ALU_dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\ALU_dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\ALU_dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\ALU_dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\ALU_dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\ALU_dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\ALU_dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_dec_sub8_rc_sel[1:0] 2'10 + case + assign $1\ALU_dec31_dec_sub8_rc_sel[1:0] 2'00 + end + sync always + update \ALU_dec31_dec_sub8_rc_sel $0\ALU_dec31_dec_sub8_rc_sel[1:0] + end + attribute \src "libresoc.v:4647.3-4689.6" + process $proc$libresoc.v:4647$104 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub8_cry_in[1:0] $1\ALU_dec31_dec_sub8_cry_in[1:0] + attribute \src "libresoc.v:4648.5-4648.29" + switch \initial + attribute \src "libresoc.v:4648.9-4648.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cry_in[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cry_in[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cry_in[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cry_in[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cry_in[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cry_in[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cry_in[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cry_in[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cry_in[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cry_in[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cry_in[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cry_in[1:0] 2'10 + case + assign $1\ALU_dec31_dec_sub8_cry_in[1:0] 2'00 + end + sync always + update \ALU_dec31_dec_sub8_cry_in $0\ALU_dec31_dec_sub8_cry_in[1:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:4695.1-4977.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_BRANCH.dec.BRANCH_dec19" +attribute \generator "nMigen" +module \BRANCH_dec19 + attribute \src "libresoc.v:4896.3-4911.6" + wire width 3 $0\BRANCH_dec19_cr_in[2:0] + attribute \src "libresoc.v:4912.3-4927.6" + wire width 3 $0\BRANCH_dec19_cr_out[2:0] + attribute \src "libresoc.v:4848.3-4863.6" + wire width 13 $0\BRANCH_dec19_function_unit[12:0] + attribute \src "libresoc.v:4880.3-4895.6" + wire width 4 $0\BRANCH_dec19_in2_sel[3:0] + attribute \src "libresoc.v:4864.3-4879.6" + wire width 7 $0\BRANCH_dec19_internal_op[6:0] + attribute \src "libresoc.v:4944.3-4959.6" + wire $0\BRANCH_dec19_is_32b[0:0] + attribute \src "libresoc.v:4960.3-4975.6" + wire $0\BRANCH_dec19_lk[0:0] + attribute \src "libresoc.v:4928.3-4943.6" + wire width 2 $0\BRANCH_dec19_rc_sel[1:0] + attribute \src "libresoc.v:4696.7-4696.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:4896.3-4911.6" + wire width 3 $1\BRANCH_dec19_cr_in[2:0] + attribute \src "libresoc.v:4912.3-4927.6" + wire width 3 $1\BRANCH_dec19_cr_out[2:0] + attribute \src "libresoc.v:4848.3-4863.6" + wire width 13 $1\BRANCH_dec19_function_unit[12:0] + attribute \src "libresoc.v:4880.3-4895.6" + wire width 4 $1\BRANCH_dec19_in2_sel[3:0] + attribute \src "libresoc.v:4864.3-4879.6" + wire width 7 $1\BRANCH_dec19_internal_op[6:0] + attribute \src "libresoc.v:4944.3-4959.6" + wire $1\BRANCH_dec19_is_32b[0:0] + attribute \src "libresoc.v:4960.3-4975.6" + wire $1\BRANCH_dec19_lk[0:0] + attribute \src "libresoc.v:4928.3-4943.6" + wire width 2 $1\BRANCH_dec19_rc_sel[1:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 4 \BRANCH_dec19_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 5 \BRANCH_dec19_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 13 output 1 \BRANCH_dec19_function_unit + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 3 \BRANCH_dec19_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 output 2 \BRANCH_dec19_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 7 \BRANCH_dec19_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 8 \BRANCH_dec19_lk + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 6 \BRANCH_dec19_rc_sel + attribute \src "libresoc.v:4696.7-4696.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + wire width 32 input 9 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + wire width 10 \opcode_switch + attribute \src "libresoc.v:4696.7-4696.20" + process $proc$libresoc.v:4696$114 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:4848.3-4863.6" + process $proc$libresoc.v:4848$106 + assign { } { } + assign { } { } + assign $0\BRANCH_dec19_function_unit[12:0] $1\BRANCH_dec19_function_unit[12:0] + attribute \src "libresoc.v:4849.5-4849.29" + switch \initial + attribute \src "libresoc.v:4849.9-4849.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\BRANCH_dec19_function_unit[12:0] 13'0000000100000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\BRANCH_dec19_function_unit[12:0] 13'0000000100000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\BRANCH_dec19_function_unit[12:0] 13'0000000100000 + case + assign $1\BRANCH_dec19_function_unit[12:0] 13'0000000000000 + end + sync always + update \BRANCH_dec19_function_unit $0\BRANCH_dec19_function_unit[12:0] + end + attribute \src "libresoc.v:4864.3-4879.6" + process $proc$libresoc.v:4864$107 + assign { } { } + assign { } { } + assign $0\BRANCH_dec19_internal_op[6:0] $1\BRANCH_dec19_internal_op[6:0] + attribute \src "libresoc.v:4865.5-4865.29" + switch \initial + attribute \src "libresoc.v:4865.9-4865.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\BRANCH_dec19_internal_op[6:0] 7'0001000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\BRANCH_dec19_internal_op[6:0] 7'0001000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\BRANCH_dec19_internal_op[6:0] 7'0001000 + case + assign $1\BRANCH_dec19_internal_op[6:0] 7'0000000 + end + sync always + update \BRANCH_dec19_internal_op $0\BRANCH_dec19_internal_op[6:0] + end + attribute \src "libresoc.v:4880.3-4895.6" + process $proc$libresoc.v:4880$108 + assign { } { } + assign { } { } + assign $0\BRANCH_dec19_in2_sel[3:0] $1\BRANCH_dec19_in2_sel[3:0] + attribute \src "libresoc.v:4881.5-4881.29" + switch \initial + attribute \src "libresoc.v:4881.9-4881.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\BRANCH_dec19_in2_sel[3:0] 4'1100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\BRANCH_dec19_in2_sel[3:0] 4'1100 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\BRANCH_dec19_in2_sel[3:0] 4'1100 + case + assign $1\BRANCH_dec19_in2_sel[3:0] 4'0000 + end + sync always + update \BRANCH_dec19_in2_sel $0\BRANCH_dec19_in2_sel[3:0] + end + attribute \src "libresoc.v:4896.3-4911.6" + process $proc$libresoc.v:4896$109 + assign { } { } + assign { } { } + assign $0\BRANCH_dec19_cr_in[2:0] $1\BRANCH_dec19_cr_in[2:0] + attribute \src "libresoc.v:4897.5-4897.29" + switch \initial + attribute \src "libresoc.v:4897.9-4897.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\BRANCH_dec19_cr_in[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\BRANCH_dec19_cr_in[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\BRANCH_dec19_cr_in[2:0] 3'010 + case + assign $1\BRANCH_dec19_cr_in[2:0] 3'000 + end + sync always + update \BRANCH_dec19_cr_in $0\BRANCH_dec19_cr_in[2:0] + end + attribute \src "libresoc.v:4912.3-4927.6" + process $proc$libresoc.v:4912$110 + assign { } { } + assign { } { } + assign $0\BRANCH_dec19_cr_out[2:0] $1\BRANCH_dec19_cr_out[2:0] + attribute \src "libresoc.v:4913.5-4913.29" + switch \initial + attribute \src "libresoc.v:4913.9-4913.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\BRANCH_dec19_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\BRANCH_dec19_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\BRANCH_dec19_cr_out[2:0] 3'000 + case + assign $1\BRANCH_dec19_cr_out[2:0] 3'000 + end + sync always + update \BRANCH_dec19_cr_out $0\BRANCH_dec19_cr_out[2:0] + end + attribute \src "libresoc.v:4928.3-4943.6" + process $proc$libresoc.v:4928$111 + assign { } { } + assign { } { } + assign $0\BRANCH_dec19_rc_sel[1:0] $1\BRANCH_dec19_rc_sel[1:0] + attribute \src "libresoc.v:4929.5-4929.29" + switch \initial + attribute \src "libresoc.v:4929.9-4929.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\BRANCH_dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\BRANCH_dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\BRANCH_dec19_rc_sel[1:0] 2'00 + case + assign $1\BRANCH_dec19_rc_sel[1:0] 2'00 + end + sync always + update \BRANCH_dec19_rc_sel $0\BRANCH_dec19_rc_sel[1:0] + end + attribute \src "libresoc.v:4944.3-4959.6" + process $proc$libresoc.v:4944$112 + assign { } { } + assign { } { } + assign $0\BRANCH_dec19_is_32b[0:0] $1\BRANCH_dec19_is_32b[0:0] + attribute \src "libresoc.v:4945.5-4945.29" + switch \initial + attribute \src "libresoc.v:4945.9-4945.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\BRANCH_dec19_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\BRANCH_dec19_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\BRANCH_dec19_is_32b[0:0] 1'0 + case + assign $1\BRANCH_dec19_is_32b[0:0] 1'0 + end + sync always + update \BRANCH_dec19_is_32b $0\BRANCH_dec19_is_32b[0:0] + end + attribute \src "libresoc.v:4960.3-4975.6" + process $proc$libresoc.v:4960$113 + assign { } { } + assign { } { } + assign $0\BRANCH_dec19_lk[0:0] $1\BRANCH_dec19_lk[0:0] + attribute \src "libresoc.v:4961.5-4961.29" + switch \initial + attribute \src "libresoc.v:4961.9-4961.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\BRANCH_dec19_lk[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\BRANCH_dec19_lk[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\BRANCH_dec19_lk[0:0] 1'1 + case + assign $1\BRANCH_dec19_lk[0:0] 1'0 + end + sync always + update \BRANCH_dec19_lk $0\BRANCH_dec19_lk[0:0] + end + connect \opcode_switch \opcode_in [10:1] +end +attribute \src "libresoc.v:4981.1-5281.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_CR.dec.CR_dec19" +attribute \generator "nMigen" +module \CR_dec19 + attribute \src "libresoc.v:5178.3-5211.6" + wire width 3 $0\CR_dec19_cr_in[2:0] + attribute \src "libresoc.v:5212.3-5245.6" + wire width 3 $0\CR_dec19_cr_out[2:0] + attribute \src "libresoc.v:5110.3-5143.6" + wire width 13 $0\CR_dec19_function_unit[12:0] + attribute \src "libresoc.v:5144.3-5177.6" + wire width 7 $0\CR_dec19_internal_op[6:0] + attribute \src "libresoc.v:5246.3-5279.6" + wire width 2 $0\CR_dec19_rc_sel[1:0] + attribute \src "libresoc.v:4982.7-4982.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:5178.3-5211.6" + wire width 3 $1\CR_dec19_cr_in[2:0] + attribute \src "libresoc.v:5212.3-5245.6" + wire width 3 $1\CR_dec19_cr_out[2:0] + attribute \src "libresoc.v:5110.3-5143.6" + wire width 13 $1\CR_dec19_function_unit[12:0] + attribute \src "libresoc.v:5144.3-5177.6" + wire width 7 $1\CR_dec19_internal_op[6:0] + attribute \src "libresoc.v:5246.3-5279.6" + wire width 2 $1\CR_dec19_rc_sel[1:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 3 \CR_dec19_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 4 \CR_dec19_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 13 output 1 \CR_dec19_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 output 2 \CR_dec19_internal_op + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 5 \CR_dec19_rc_sel + attribute \src "libresoc.v:4982.7-4982.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + wire width 32 input 6 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + wire width 10 \opcode_switch + attribute \src "libresoc.v:4982.7-4982.20" + process $proc$libresoc.v:4982$120 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:5110.3-5143.6" + process $proc$libresoc.v:5110$115 + assign { } { } + assign { } { } + assign $0\CR_dec19_function_unit[12:0] $1\CR_dec19_function_unit[12:0] + attribute \src "libresoc.v:5111.5-5111.29" + switch \initial + attribute \src "libresoc.v:5111.9-5111.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\CR_dec19_function_unit[12:0] 13'0000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\CR_dec19_function_unit[12:0] 13'0000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\CR_dec19_function_unit[12:0] 13'0000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\CR_dec19_function_unit[12:0] 13'0000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\CR_dec19_function_unit[12:0] 13'0000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\CR_dec19_function_unit[12:0] 13'0000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\CR_dec19_function_unit[12:0] 13'0000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\CR_dec19_function_unit[12:0] 13'0000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\CR_dec19_function_unit[12:0] 13'0000001000000 + case + assign $1\CR_dec19_function_unit[12:0] 13'0000000000000 + end + sync always + update \CR_dec19_function_unit $0\CR_dec19_function_unit[12:0] + end + attribute \src "libresoc.v:5144.3-5177.6" + process $proc$libresoc.v:5144$116 + assign { } { } + assign { } { } + assign $0\CR_dec19_internal_op[6:0] $1\CR_dec19_internal_op[6:0] + attribute \src "libresoc.v:5145.5-5145.29" + switch \initial + attribute \src "libresoc.v:5145.9-5145.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\CR_dec19_internal_op[6:0] 7'0101010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\CR_dec19_internal_op[6:0] 7'1000101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\CR_dec19_internal_op[6:0] 7'1000101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\CR_dec19_internal_op[6:0] 7'1000101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\CR_dec19_internal_op[6:0] 7'1000101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\CR_dec19_internal_op[6:0] 7'1000101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\CR_dec19_internal_op[6:0] 7'1000101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\CR_dec19_internal_op[6:0] 7'1000101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\CR_dec19_internal_op[6:0] 7'1000101 + case + assign $1\CR_dec19_internal_op[6:0] 7'0000000 + end + sync always + update \CR_dec19_internal_op $0\CR_dec19_internal_op[6:0] + end + attribute \src "libresoc.v:5178.3-5211.6" + process $proc$libresoc.v:5178$117 + assign { } { } + assign { } { } + assign $0\CR_dec19_cr_in[2:0] $1\CR_dec19_cr_in[2:0] + attribute \src "libresoc.v:5179.5-5179.29" + switch \initial + attribute \src "libresoc.v:5179.9-5179.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\CR_dec19_cr_in[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\CR_dec19_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\CR_dec19_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\CR_dec19_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\CR_dec19_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\CR_dec19_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\CR_dec19_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\CR_dec19_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\CR_dec19_cr_in[2:0] 3'100 + case + assign $1\CR_dec19_cr_in[2:0] 3'000 + end + sync always + update \CR_dec19_cr_in $0\CR_dec19_cr_in[2:0] + end + attribute \src "libresoc.v:5212.3-5245.6" + process $proc$libresoc.v:5212$118 + assign { } { } + assign { } { } + assign $0\CR_dec19_cr_out[2:0] $1\CR_dec19_cr_out[2:0] + attribute \src "libresoc.v:5213.5-5213.29" + switch \initial + attribute \src "libresoc.v:5213.9-5213.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\CR_dec19_cr_out[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\CR_dec19_cr_out[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\CR_dec19_cr_out[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\CR_dec19_cr_out[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\CR_dec19_cr_out[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\CR_dec19_cr_out[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\CR_dec19_cr_out[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\CR_dec19_cr_out[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\CR_dec19_cr_out[2:0] 3'011 + case + assign $1\CR_dec19_cr_out[2:0] 3'000 + end + sync always + update \CR_dec19_cr_out $0\CR_dec19_cr_out[2:0] + end + attribute \src "libresoc.v:5246.3-5279.6" + process $proc$libresoc.v:5246$119 + assign { } { } + assign { } { } + assign $0\CR_dec19_rc_sel[1:0] $1\CR_dec19_rc_sel[1:0] + attribute \src "libresoc.v:5247.5-5247.29" + switch \initial + attribute \src "libresoc.v:5247.9-5247.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\CR_dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\CR_dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\CR_dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\CR_dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\CR_dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\CR_dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\CR_dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\CR_dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\CR_dec19_rc_sel[1:0] 2'00 + case + assign $1\CR_dec19_rc_sel[1:0] 2'00 + end + sync always + update \CR_dec19_rc_sel $0\CR_dec19_rc_sel[1:0] + end + connect \opcode_switch \opcode_in [10:1] +end +attribute \src "libresoc.v:5285.1-6029.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_CR.dec.CR_dec31" +attribute \generator "nMigen" +module \CR_dec31 + attribute \src "libresoc.v:5985.3-6003.6" + wire width 3 $0\CR_dec31_cr_in[2:0] + attribute \src "libresoc.v:6004.3-6022.6" + wire width 3 $0\CR_dec31_cr_out[2:0] + attribute \src "libresoc.v:5947.3-5965.6" + wire width 13 $0\CR_dec31_function_unit[12:0] + attribute \src "libresoc.v:5966.3-5984.6" + wire width 7 $0\CR_dec31_internal_op[6:0] + attribute \src "libresoc.v:5928.3-5946.6" + wire width 2 $0\CR_dec31_rc_sel[1:0] + attribute \src "libresoc.v:5286.7-5286.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:5985.3-6003.6" + wire width 3 $1\CR_dec31_cr_in[2:0] + attribute \src "libresoc.v:6004.3-6022.6" + wire width 3 $1\CR_dec31_cr_out[2:0] + attribute \src "libresoc.v:5947.3-5965.6" + wire width 13 $1\CR_dec31_function_unit[12:0] + attribute \src "libresoc.v:5966.3-5984.6" + wire width 7 $1\CR_dec31_internal_op[6:0] + attribute \src "libresoc.v:5928.3-5946.6" + wire width 2 $1\CR_dec31_rc_sel[1:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 3 \CR_dec31_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 4 \CR_dec31_cr_out + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \CR_dec31_dec_sub0_CR_dec31_dec_sub0_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \CR_dec31_dec_sub0_CR_dec31_dec_sub0_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 13 \CR_dec31_dec_sub0_CR_dec31_dec_sub0_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 \CR_dec31_dec_sub0_CR_dec31_dec_sub0_internal_op + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \CR_dec31_dec_sub0_CR_dec31_dec_sub0_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + wire width 32 \CR_dec31_dec_sub0_opcode_in + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \CR_dec31_dec_sub15_CR_dec31_dec_sub15_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \CR_dec31_dec_sub15_CR_dec31_dec_sub15_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 13 \CR_dec31_dec_sub15_CR_dec31_dec_sub15_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 \CR_dec31_dec_sub15_CR_dec31_dec_sub15_internal_op + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \CR_dec31_dec_sub15_CR_dec31_dec_sub15_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + wire width 32 \CR_dec31_dec_sub15_opcode_in + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \CR_dec31_dec_sub16_CR_dec31_dec_sub16_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \CR_dec31_dec_sub16_CR_dec31_dec_sub16_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 13 \CR_dec31_dec_sub16_CR_dec31_dec_sub16_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 \CR_dec31_dec_sub16_CR_dec31_dec_sub16_internal_op + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \CR_dec31_dec_sub16_CR_dec31_dec_sub16_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + wire width 32 \CR_dec31_dec_sub16_opcode_in + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \CR_dec31_dec_sub19_CR_dec31_dec_sub19_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \CR_dec31_dec_sub19_CR_dec31_dec_sub19_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 13 \CR_dec31_dec_sub19_CR_dec31_dec_sub19_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 \CR_dec31_dec_sub19_CR_dec31_dec_sub19_internal_op + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \CR_dec31_dec_sub19_CR_dec31_dec_sub19_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + wire width 32 \CR_dec31_dec_sub19_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 13 output 1 \CR_dec31_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 output 2 \CR_dec31_internal_op + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 5 \CR_dec31_rc_sel + attribute \src "libresoc.v:5286.7-5286.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:347" + wire width 5 \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + wire width 32 input 6 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + wire width 10 \opcode_switch + attribute \module_not_derived 1 + attribute \src "libresoc.v:5896.21-5903.4" + cell \CR_dec31_dec_sub0 \CR_dec31_dec_sub0 + connect \CR_dec31_dec_sub0_cr_in \CR_dec31_dec_sub0_CR_dec31_dec_sub0_cr_in + connect \CR_dec31_dec_sub0_cr_out \CR_dec31_dec_sub0_CR_dec31_dec_sub0_cr_out + connect \CR_dec31_dec_sub0_function_unit \CR_dec31_dec_sub0_CR_dec31_dec_sub0_function_unit + connect \CR_dec31_dec_sub0_internal_op \CR_dec31_dec_sub0_CR_dec31_dec_sub0_internal_op + connect \CR_dec31_dec_sub0_rc_sel \CR_dec31_dec_sub0_CR_dec31_dec_sub0_rc_sel + connect \opcode_in \CR_dec31_dec_sub0_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:5904.22-5911.4" + cell \CR_dec31_dec_sub15 \CR_dec31_dec_sub15 + connect \CR_dec31_dec_sub15_cr_in \CR_dec31_dec_sub15_CR_dec31_dec_sub15_cr_in + connect \CR_dec31_dec_sub15_cr_out \CR_dec31_dec_sub15_CR_dec31_dec_sub15_cr_out + connect \CR_dec31_dec_sub15_function_unit \CR_dec31_dec_sub15_CR_dec31_dec_sub15_function_unit + connect \CR_dec31_dec_sub15_internal_op \CR_dec31_dec_sub15_CR_dec31_dec_sub15_internal_op + connect \CR_dec31_dec_sub15_rc_sel \CR_dec31_dec_sub15_CR_dec31_dec_sub15_rc_sel + connect \opcode_in \CR_dec31_dec_sub15_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:5912.22-5919.4" + cell \CR_dec31_dec_sub16 \CR_dec31_dec_sub16 + connect \CR_dec31_dec_sub16_cr_in \CR_dec31_dec_sub16_CR_dec31_dec_sub16_cr_in + connect \CR_dec31_dec_sub16_cr_out \CR_dec31_dec_sub16_CR_dec31_dec_sub16_cr_out + connect \CR_dec31_dec_sub16_function_unit \CR_dec31_dec_sub16_CR_dec31_dec_sub16_function_unit + connect \CR_dec31_dec_sub16_internal_op \CR_dec31_dec_sub16_CR_dec31_dec_sub16_internal_op + connect \CR_dec31_dec_sub16_rc_sel \CR_dec31_dec_sub16_CR_dec31_dec_sub16_rc_sel + connect \opcode_in \CR_dec31_dec_sub16_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:5920.22-5927.4" + cell \CR_dec31_dec_sub19 \CR_dec31_dec_sub19 + connect \CR_dec31_dec_sub19_cr_in \CR_dec31_dec_sub19_CR_dec31_dec_sub19_cr_in + connect \CR_dec31_dec_sub19_cr_out \CR_dec31_dec_sub19_CR_dec31_dec_sub19_cr_out + connect \CR_dec31_dec_sub19_function_unit \CR_dec31_dec_sub19_CR_dec31_dec_sub19_function_unit + connect \CR_dec31_dec_sub19_internal_op \CR_dec31_dec_sub19_CR_dec31_dec_sub19_internal_op + connect \CR_dec31_dec_sub19_rc_sel \CR_dec31_dec_sub19_CR_dec31_dec_sub19_rc_sel + connect \opcode_in \CR_dec31_dec_sub19_opcode_in + end + attribute \src "libresoc.v:5286.7-5286.20" + process $proc$libresoc.v:5286$126 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:5928.3-5946.6" + process $proc$libresoc.v:5928$121 + assign { } { } + assign { } { } + assign $0\CR_dec31_rc_sel[1:0] $1\CR_dec31_rc_sel[1:0] + attribute \src "libresoc.v:5929.5-5929.29" + switch \initial + attribute \src "libresoc.v:5929.9-5929.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\CR_dec31_rc_sel[1:0] \CR_dec31_dec_sub0_CR_dec31_dec_sub0_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\CR_dec31_rc_sel[1:0] \CR_dec31_dec_sub19_CR_dec31_dec_sub19_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\CR_dec31_rc_sel[1:0] \CR_dec31_dec_sub15_CR_dec31_dec_sub15_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\CR_dec31_rc_sel[1:0] \CR_dec31_dec_sub16_CR_dec31_dec_sub16_rc_sel + case + assign $1\CR_dec31_rc_sel[1:0] 2'00 + end + sync always + update \CR_dec31_rc_sel $0\CR_dec31_rc_sel[1:0] + end + attribute \src "libresoc.v:5947.3-5965.6" + process $proc$libresoc.v:5947$122 + assign { } { } + assign { } { } + assign $0\CR_dec31_function_unit[12:0] $1\CR_dec31_function_unit[12:0] + attribute \src "libresoc.v:5948.5-5948.29" + switch \initial + attribute \src "libresoc.v:5948.9-5948.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\CR_dec31_function_unit[12:0] \CR_dec31_dec_sub0_CR_dec31_dec_sub0_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\CR_dec31_function_unit[12:0] \CR_dec31_dec_sub19_CR_dec31_dec_sub19_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\CR_dec31_function_unit[12:0] \CR_dec31_dec_sub15_CR_dec31_dec_sub15_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\CR_dec31_function_unit[12:0] \CR_dec31_dec_sub16_CR_dec31_dec_sub16_function_unit + case + assign $1\CR_dec31_function_unit[12:0] 13'0000000000000 + end + sync always + update \CR_dec31_function_unit $0\CR_dec31_function_unit[12:0] + end + attribute \src "libresoc.v:5966.3-5984.6" + process $proc$libresoc.v:5966$123 + assign { } { } + assign { } { } + assign $0\CR_dec31_internal_op[6:0] $1\CR_dec31_internal_op[6:0] + attribute \src "libresoc.v:5967.5-5967.29" + switch \initial + attribute \src "libresoc.v:5967.9-5967.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\CR_dec31_internal_op[6:0] \CR_dec31_dec_sub0_CR_dec31_dec_sub0_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\CR_dec31_internal_op[6:0] \CR_dec31_dec_sub19_CR_dec31_dec_sub19_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\CR_dec31_internal_op[6:0] \CR_dec31_dec_sub15_CR_dec31_dec_sub15_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\CR_dec31_internal_op[6:0] \CR_dec31_dec_sub16_CR_dec31_dec_sub16_internal_op + case + assign $1\CR_dec31_internal_op[6:0] 7'0000000 + end + sync always + update \CR_dec31_internal_op $0\CR_dec31_internal_op[6:0] + end + attribute \src "libresoc.v:5985.3-6003.6" + process $proc$libresoc.v:5985$124 + assign { } { } + assign { } { } + assign $0\CR_dec31_cr_in[2:0] $1\CR_dec31_cr_in[2:0] + attribute \src "libresoc.v:5986.5-5986.29" + switch \initial + attribute \src "libresoc.v:5986.9-5986.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\CR_dec31_cr_in[2:0] \CR_dec31_dec_sub0_CR_dec31_dec_sub0_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\CR_dec31_cr_in[2:0] \CR_dec31_dec_sub19_CR_dec31_dec_sub19_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\CR_dec31_cr_in[2:0] \CR_dec31_dec_sub15_CR_dec31_dec_sub15_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\CR_dec31_cr_in[2:0] \CR_dec31_dec_sub16_CR_dec31_dec_sub16_cr_in + case + assign $1\CR_dec31_cr_in[2:0] 3'000 + end + sync always + update \CR_dec31_cr_in $0\CR_dec31_cr_in[2:0] + end + attribute \src "libresoc.v:6004.3-6022.6" + process $proc$libresoc.v:6004$125 + assign { } { } + assign { } { } + assign $0\CR_dec31_cr_out[2:0] $1\CR_dec31_cr_out[2:0] + attribute \src "libresoc.v:6005.5-6005.29" + switch \initial + attribute \src "libresoc.v:6005.9-6005.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\CR_dec31_cr_out[2:0] \CR_dec31_dec_sub0_CR_dec31_dec_sub0_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\CR_dec31_cr_out[2:0] \CR_dec31_dec_sub19_CR_dec31_dec_sub19_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\CR_dec31_cr_out[2:0] \CR_dec31_dec_sub15_CR_dec31_dec_sub15_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\CR_dec31_cr_out[2:0] \CR_dec31_dec_sub16_CR_dec31_dec_sub16_cr_out + case + assign $1\CR_dec31_cr_out[2:0] 3'000 + end + sync always + update \CR_dec31_cr_out $0\CR_dec31_cr_out[2:0] + end + connect \CR_dec31_dec_sub16_opcode_in \opcode_in + connect \CR_dec31_dec_sub15_opcode_in \opcode_in + connect \CR_dec31_dec_sub19_opcode_in \opcode_in + connect \CR_dec31_dec_sub0_opcode_in \opcode_in + connect \opc_in \opcode_switch [4:0] + connect \opcode_switch \opcode_in [10:1] +end +attribute \src "libresoc.v:6033.1-6213.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_CR.dec.CR_dec31.CR_dec31_dec_sub0" +attribute \generator "nMigen" +module \CR_dec31_dec_sub0 + attribute \src "libresoc.v:6182.3-6191.6" + wire width 3 $0\CR_dec31_dec_sub0_cr_in[2:0] + attribute \src "libresoc.v:6192.3-6201.6" + wire width 3 $0\CR_dec31_dec_sub0_cr_out[2:0] + attribute \src "libresoc.v:6162.3-6171.6" + wire width 13 $0\CR_dec31_dec_sub0_function_unit[12:0] + attribute \src "libresoc.v:6172.3-6181.6" + wire width 7 $0\CR_dec31_dec_sub0_internal_op[6:0] + attribute \src "libresoc.v:6202.3-6211.6" + wire width 2 $0\CR_dec31_dec_sub0_rc_sel[1:0] + attribute \src "libresoc.v:6034.7-6034.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:6182.3-6191.6" + wire width 3 $1\CR_dec31_dec_sub0_cr_in[2:0] + attribute \src "libresoc.v:6192.3-6201.6" + wire width 3 $1\CR_dec31_dec_sub0_cr_out[2:0] + attribute \src "libresoc.v:6162.3-6171.6" + wire width 13 $1\CR_dec31_dec_sub0_function_unit[12:0] + attribute \src "libresoc.v:6172.3-6181.6" + wire width 7 $1\CR_dec31_dec_sub0_internal_op[6:0] + attribute \src "libresoc.v:6202.3-6211.6" + wire width 2 $1\CR_dec31_dec_sub0_rc_sel[1:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 3 \CR_dec31_dec_sub0_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 4 \CR_dec31_dec_sub0_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 13 output 1 \CR_dec31_dec_sub0_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 output 2 \CR_dec31_dec_sub0_internal_op + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 5 \CR_dec31_dec_sub0_rc_sel + attribute \src "libresoc.v:6034.7-6034.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + wire width 32 input 6 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + wire width 5 \opcode_switch + attribute \src "libresoc.v:6034.7-6034.20" + process $proc$libresoc.v:6034$132 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:6162.3-6171.6" + process $proc$libresoc.v:6162$127 + assign { } { } + assign { } { } + assign $0\CR_dec31_dec_sub0_function_unit[12:0] $1\CR_dec31_dec_sub0_function_unit[12:0] + attribute \src "libresoc.v:6163.5-6163.29" + switch \initial + attribute \src "libresoc.v:6163.9-6163.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\CR_dec31_dec_sub0_function_unit[12:0] 13'0000001000000 + case + assign $1\CR_dec31_dec_sub0_function_unit[12:0] 13'0000000000000 + end + sync always + update \CR_dec31_dec_sub0_function_unit $0\CR_dec31_dec_sub0_function_unit[12:0] + end + attribute \src "libresoc.v:6172.3-6181.6" + process $proc$libresoc.v:6172$128 + assign { } { } + assign { } { } + assign $0\CR_dec31_dec_sub0_internal_op[6:0] $1\CR_dec31_dec_sub0_internal_op[6:0] + attribute \src "libresoc.v:6173.5-6173.29" + switch \initial + attribute \src "libresoc.v:6173.9-6173.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\CR_dec31_dec_sub0_internal_op[6:0] 7'0111011 + case + assign $1\CR_dec31_dec_sub0_internal_op[6:0] 7'0000000 + end + sync always + update \CR_dec31_dec_sub0_internal_op $0\CR_dec31_dec_sub0_internal_op[6:0] + end + attribute \src "libresoc.v:6182.3-6191.6" + process $proc$libresoc.v:6182$129 + assign { } { } + assign { } { } + assign $0\CR_dec31_dec_sub0_cr_in[2:0] $1\CR_dec31_dec_sub0_cr_in[2:0] + attribute \src "libresoc.v:6183.5-6183.29" + switch \initial + attribute \src "libresoc.v:6183.9-6183.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\CR_dec31_dec_sub0_cr_in[2:0] 3'011 + case + assign $1\CR_dec31_dec_sub0_cr_in[2:0] 3'000 + end + sync always + update \CR_dec31_dec_sub0_cr_in $0\CR_dec31_dec_sub0_cr_in[2:0] + end + attribute \src "libresoc.v:6192.3-6201.6" + process $proc$libresoc.v:6192$130 + assign { } { } + assign { } { } + assign $0\CR_dec31_dec_sub0_cr_out[2:0] $1\CR_dec31_dec_sub0_cr_out[2:0] + attribute \src "libresoc.v:6193.5-6193.29" + switch \initial + attribute \src "libresoc.v:6193.9-6193.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\CR_dec31_dec_sub0_cr_out[2:0] 3'000 + case + assign $1\CR_dec31_dec_sub0_cr_out[2:0] 3'000 + end + sync always + update \CR_dec31_dec_sub0_cr_out $0\CR_dec31_dec_sub0_cr_out[2:0] + end + attribute \src "libresoc.v:6202.3-6211.6" + process $proc$libresoc.v:6202$131 + assign { } { } + assign { } { } + assign $0\CR_dec31_dec_sub0_rc_sel[1:0] $1\CR_dec31_dec_sub0_rc_sel[1:0] + attribute \src "libresoc.v:6203.5-6203.29" + switch \initial + attribute \src "libresoc.v:6203.9-6203.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\CR_dec31_dec_sub0_rc_sel[1:0] 2'00 + case + assign $1\CR_dec31_dec_sub0_rc_sel[1:0] 2'00 + end + sync always + update \CR_dec31_dec_sub0_rc_sel $0\CR_dec31_dec_sub0_rc_sel[1:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:6217.1-6862.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_CR.dec.CR_dec31.CR_dec31_dec_sub15" +attribute \generator "nMigen" +module \CR_dec31_dec_sub15 + attribute \src "libresoc.v:6552.3-6654.6" + wire width 3 $0\CR_dec31_dec_sub15_cr_in[2:0] + attribute \src "libresoc.v:6655.3-6757.6" + wire width 3 $0\CR_dec31_dec_sub15_cr_out[2:0] + attribute \src "libresoc.v:6346.3-6448.6" + wire width 13 $0\CR_dec31_dec_sub15_function_unit[12:0] + attribute \src "libresoc.v:6449.3-6551.6" + wire width 7 $0\CR_dec31_dec_sub15_internal_op[6:0] + attribute \src "libresoc.v:6758.3-6860.6" + wire width 2 $0\CR_dec31_dec_sub15_rc_sel[1:0] + attribute \src "libresoc.v:6218.7-6218.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:6552.3-6654.6" + wire width 3 $1\CR_dec31_dec_sub15_cr_in[2:0] + attribute \src "libresoc.v:6655.3-6757.6" + wire width 3 $1\CR_dec31_dec_sub15_cr_out[2:0] + attribute \src "libresoc.v:6346.3-6448.6" + wire width 13 $1\CR_dec31_dec_sub15_function_unit[12:0] + attribute \src "libresoc.v:6449.3-6551.6" + wire width 7 $1\CR_dec31_dec_sub15_internal_op[6:0] + attribute \src "libresoc.v:6758.3-6860.6" + wire width 2 $1\CR_dec31_dec_sub15_rc_sel[1:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 3 \CR_dec31_dec_sub15_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 4 \CR_dec31_dec_sub15_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 13 output 1 \CR_dec31_dec_sub15_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 output 2 \CR_dec31_dec_sub15_internal_op + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 5 \CR_dec31_dec_sub15_rc_sel + attribute \src "libresoc.v:6218.7-6218.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + wire width 32 input 6 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + wire width 5 \opcode_switch + attribute \src "libresoc.v:6218.7-6218.20" + process $proc$libresoc.v:6218$138 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:6346.3-6448.6" + process $proc$libresoc.v:6346$133 + assign { } { } + assign { } { } + assign $0\CR_dec31_dec_sub15_function_unit[12:0] $1\CR_dec31_dec_sub15_function_unit[12:0] + attribute \src "libresoc.v:6347.5-6347.29" + switch \initial + attribute \src "libresoc.v:6347.9-6347.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[12:0] 13'0000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[12:0] 13'0000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[12:0] 13'0000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[12:0] 13'0000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[12:0] 13'0000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[12:0] 13'0000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[12:0] 13'0000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[12:0] 13'0000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[12:0] 13'0000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[12:0] 13'0000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[12:0] 13'0000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[12:0] 13'0000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[12:0] 13'0000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[12:0] 13'0000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[12:0] 13'0000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[12:0] 13'0000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[12:0] 13'0000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[12:0] 13'0000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[12:0] 13'0000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[12:0] 13'0000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[12:0] 13'0000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[12:0] 13'0000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[12:0] 13'0000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[12:0] 13'0000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[12:0] 13'0000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[12:0] 13'0000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[12:0] 13'0000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[12:0] 13'0000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[12:0] 13'0000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[12:0] 13'0000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[12:0] 13'0000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[12:0] 13'0000001000000 + case + assign $1\CR_dec31_dec_sub15_function_unit[12:0] 13'0000000000000 + end + sync always + update \CR_dec31_dec_sub15_function_unit $0\CR_dec31_dec_sub15_function_unit[12:0] + end + attribute \src "libresoc.v:6449.3-6551.6" + process $proc$libresoc.v:6449$134 + assign { } { } + assign { } { } + assign $0\CR_dec31_dec_sub15_internal_op[6:0] $1\CR_dec31_dec_sub15_internal_op[6:0] + attribute \src "libresoc.v:6450.5-6450.29" + switch \initial + attribute \src "libresoc.v:6450.9-6450.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + case + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0000000 + end + sync always + update \CR_dec31_dec_sub15_internal_op $0\CR_dec31_dec_sub15_internal_op[6:0] + end + attribute \src "libresoc.v:6552.3-6654.6" + process $proc$libresoc.v:6552$135 + assign { } { } + assign { } { } + assign $0\CR_dec31_dec_sub15_cr_in[2:0] $1\CR_dec31_dec_sub15_cr_in[2:0] + attribute \src "libresoc.v:6553.5-6553.29" + switch \initial + attribute \src "libresoc.v:6553.9-6553.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + case + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'000 + end + sync always + update \CR_dec31_dec_sub15_cr_in $0\CR_dec31_dec_sub15_cr_in[2:0] + end + attribute \src "libresoc.v:6655.3-6757.6" + process $proc$libresoc.v:6655$136 + assign { } { } + assign { } { } + assign $0\CR_dec31_dec_sub15_cr_out[2:0] $1\CR_dec31_dec_sub15_cr_out[2:0] + attribute \src "libresoc.v:6656.5-6656.29" + switch \initial + attribute \src "libresoc.v:6656.9-6656.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + case + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + end + sync always + update \CR_dec31_dec_sub15_cr_out $0\CR_dec31_dec_sub15_cr_out[2:0] + end + attribute \src "libresoc.v:6758.3-6860.6" + process $proc$libresoc.v:6758$137 + assign { } { } + assign { } { } + assign $0\CR_dec31_dec_sub15_rc_sel[1:0] $1\CR_dec31_dec_sub15_rc_sel[1:0] + attribute \src "libresoc.v:6759.5-6759.29" + switch \initial + attribute \src "libresoc.v:6759.9-6759.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + case + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + end + sync always + update \CR_dec31_dec_sub15_rc_sel $0\CR_dec31_dec_sub15_rc_sel[1:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:6866.1-7046.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_CR.dec.CR_dec31.CR_dec31_dec_sub16" +attribute \generator "nMigen" +module \CR_dec31_dec_sub16 + attribute \src "libresoc.v:7015.3-7024.6" + wire width 3 $0\CR_dec31_dec_sub16_cr_in[2:0] + attribute \src "libresoc.v:7025.3-7034.6" + wire width 3 $0\CR_dec31_dec_sub16_cr_out[2:0] + attribute \src "libresoc.v:6995.3-7004.6" + wire width 13 $0\CR_dec31_dec_sub16_function_unit[12:0] + attribute \src "libresoc.v:7005.3-7014.6" + wire width 7 $0\CR_dec31_dec_sub16_internal_op[6:0] + attribute \src "libresoc.v:7035.3-7044.6" + wire width 2 $0\CR_dec31_dec_sub16_rc_sel[1:0] + attribute \src "libresoc.v:6867.7-6867.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:7015.3-7024.6" + wire width 3 $1\CR_dec31_dec_sub16_cr_in[2:0] + attribute \src "libresoc.v:7025.3-7034.6" + wire width 3 $1\CR_dec31_dec_sub16_cr_out[2:0] + attribute \src "libresoc.v:6995.3-7004.6" + wire width 13 $1\CR_dec31_dec_sub16_function_unit[12:0] + attribute \src "libresoc.v:7005.3-7014.6" + wire width 7 $1\CR_dec31_dec_sub16_internal_op[6:0] + attribute \src "libresoc.v:7035.3-7044.6" + wire width 2 $1\CR_dec31_dec_sub16_rc_sel[1:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 3 \CR_dec31_dec_sub16_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 4 \CR_dec31_dec_sub16_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 13 output 1 \CR_dec31_dec_sub16_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 output 2 \CR_dec31_dec_sub16_internal_op + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 5 \CR_dec31_dec_sub16_rc_sel + attribute \src "libresoc.v:6867.7-6867.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + wire width 32 input 6 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + wire width 5 \opcode_switch + attribute \src "libresoc.v:6867.7-6867.20" + process $proc$libresoc.v:6867$144 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:6995.3-7004.6" + process $proc$libresoc.v:6995$139 + assign { } { } + assign { } { } + assign $0\CR_dec31_dec_sub16_function_unit[12:0] $1\CR_dec31_dec_sub16_function_unit[12:0] + attribute \src "libresoc.v:6996.5-6996.29" + switch \initial + attribute \src "libresoc.v:6996.9-6996.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\CR_dec31_dec_sub16_function_unit[12:0] 13'0000001000000 + case + assign $1\CR_dec31_dec_sub16_function_unit[12:0] 13'0000000000000 + end + sync always + update \CR_dec31_dec_sub16_function_unit $0\CR_dec31_dec_sub16_function_unit[12:0] + end + attribute \src "libresoc.v:7005.3-7014.6" + process $proc$libresoc.v:7005$140 + assign { } { } + assign { } { } + assign $0\CR_dec31_dec_sub16_internal_op[6:0] $1\CR_dec31_dec_sub16_internal_op[6:0] + attribute \src "libresoc.v:7006.5-7006.29" + switch \initial + attribute \src "libresoc.v:7006.9-7006.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\CR_dec31_dec_sub16_internal_op[6:0] 7'0110000 + case + assign $1\CR_dec31_dec_sub16_internal_op[6:0] 7'0000000 + end + sync always + update \CR_dec31_dec_sub16_internal_op $0\CR_dec31_dec_sub16_internal_op[6:0] + end + attribute \src "libresoc.v:7015.3-7024.6" + process $proc$libresoc.v:7015$141 + assign { } { } + assign { } { } + assign $0\CR_dec31_dec_sub16_cr_in[2:0] $1\CR_dec31_dec_sub16_cr_in[2:0] + attribute \src "libresoc.v:7016.5-7016.29" + switch \initial + attribute \src "libresoc.v:7016.9-7016.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\CR_dec31_dec_sub16_cr_in[2:0] 3'110 + case + assign $1\CR_dec31_dec_sub16_cr_in[2:0] 3'000 + end + sync always + update \CR_dec31_dec_sub16_cr_in $0\CR_dec31_dec_sub16_cr_in[2:0] + end + attribute \src "libresoc.v:7025.3-7034.6" + process $proc$libresoc.v:7025$142 + assign { } { } + assign { } { } + assign $0\CR_dec31_dec_sub16_cr_out[2:0] $1\CR_dec31_dec_sub16_cr_out[2:0] + attribute \src "libresoc.v:7026.5-7026.29" + switch \initial + attribute \src "libresoc.v:7026.9-7026.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\CR_dec31_dec_sub16_cr_out[2:0] 3'100 + case + assign $1\CR_dec31_dec_sub16_cr_out[2:0] 3'000 + end + sync always + update \CR_dec31_dec_sub16_cr_out $0\CR_dec31_dec_sub16_cr_out[2:0] + end + attribute \src "libresoc.v:7035.3-7044.6" + process $proc$libresoc.v:7035$143 + assign { } { } + assign { } { } + assign $0\CR_dec31_dec_sub16_rc_sel[1:0] $1\CR_dec31_dec_sub16_rc_sel[1:0] + attribute \src "libresoc.v:7036.5-7036.29" + switch \initial + attribute \src "libresoc.v:7036.9-7036.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\CR_dec31_dec_sub16_rc_sel[1:0] 2'00 + case + assign $1\CR_dec31_dec_sub16_rc_sel[1:0] 2'00 + end + sync always + update \CR_dec31_dec_sub16_rc_sel $0\CR_dec31_dec_sub16_rc_sel[1:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:7050.1-7230.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_CR.dec.CR_dec31.CR_dec31_dec_sub19" +attribute \generator "nMigen" +module \CR_dec31_dec_sub19 + attribute \src "libresoc.v:7199.3-7208.6" + wire width 3 $0\CR_dec31_dec_sub19_cr_in[2:0] + attribute \src "libresoc.v:7209.3-7218.6" + wire width 3 $0\CR_dec31_dec_sub19_cr_out[2:0] + attribute \src "libresoc.v:7179.3-7188.6" + wire width 13 $0\CR_dec31_dec_sub19_function_unit[12:0] + attribute \src "libresoc.v:7189.3-7198.6" + wire width 7 $0\CR_dec31_dec_sub19_internal_op[6:0] + attribute \src "libresoc.v:7219.3-7228.6" + wire width 2 $0\CR_dec31_dec_sub19_rc_sel[1:0] + attribute \src "libresoc.v:7051.7-7051.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:7199.3-7208.6" + wire width 3 $1\CR_dec31_dec_sub19_cr_in[2:0] + attribute \src "libresoc.v:7209.3-7218.6" + wire width 3 $1\CR_dec31_dec_sub19_cr_out[2:0] + attribute \src "libresoc.v:7179.3-7188.6" + wire width 13 $1\CR_dec31_dec_sub19_function_unit[12:0] + attribute \src "libresoc.v:7189.3-7198.6" + wire width 7 $1\CR_dec31_dec_sub19_internal_op[6:0] + attribute \src "libresoc.v:7219.3-7228.6" + wire width 2 $1\CR_dec31_dec_sub19_rc_sel[1:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 3 \CR_dec31_dec_sub19_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 4 \CR_dec31_dec_sub19_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 13 output 1 \CR_dec31_dec_sub19_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 output 2 \CR_dec31_dec_sub19_internal_op + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 5 \CR_dec31_dec_sub19_rc_sel + attribute \src "libresoc.v:7051.7-7051.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + wire width 32 input 6 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + wire width 5 \opcode_switch + attribute \src "libresoc.v:7051.7-7051.20" + process $proc$libresoc.v:7051$150 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:7179.3-7188.6" + process $proc$libresoc.v:7179$145 + assign { } { } + assign { } { } + assign $0\CR_dec31_dec_sub19_function_unit[12:0] $1\CR_dec31_dec_sub19_function_unit[12:0] + attribute \src "libresoc.v:7180.5-7180.29" + switch \initial + attribute \src "libresoc.v:7180.9-7180.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\CR_dec31_dec_sub19_function_unit[12:0] 13'0000001000000 + case + assign $1\CR_dec31_dec_sub19_function_unit[12:0] 13'0000000000000 + end + sync always + update \CR_dec31_dec_sub19_function_unit $0\CR_dec31_dec_sub19_function_unit[12:0] + end + attribute \src "libresoc.v:7189.3-7198.6" + process $proc$libresoc.v:7189$146 + assign { } { } + assign { } { } + assign $0\CR_dec31_dec_sub19_internal_op[6:0] $1\CR_dec31_dec_sub19_internal_op[6:0] + attribute \src "libresoc.v:7190.5-7190.29" + switch \initial + attribute \src "libresoc.v:7190.9-7190.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\CR_dec31_dec_sub19_internal_op[6:0] 7'0101101 + case + assign $1\CR_dec31_dec_sub19_internal_op[6:0] 7'0000000 + end + sync always + update \CR_dec31_dec_sub19_internal_op $0\CR_dec31_dec_sub19_internal_op[6:0] + end + attribute \src "libresoc.v:7199.3-7208.6" + process $proc$libresoc.v:7199$147 + assign { } { } + assign { } { } + assign $0\CR_dec31_dec_sub19_cr_in[2:0] $1\CR_dec31_dec_sub19_cr_in[2:0] + attribute \src "libresoc.v:7200.5-7200.29" + switch \initial + attribute \src "libresoc.v:7200.9-7200.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\CR_dec31_dec_sub19_cr_in[2:0] 3'110 + case + assign $1\CR_dec31_dec_sub19_cr_in[2:0] 3'000 + end + sync always + update \CR_dec31_dec_sub19_cr_in $0\CR_dec31_dec_sub19_cr_in[2:0] + end + attribute \src "libresoc.v:7209.3-7218.6" + process $proc$libresoc.v:7209$148 + assign { } { } + assign { } { } + assign $0\CR_dec31_dec_sub19_cr_out[2:0] $1\CR_dec31_dec_sub19_cr_out[2:0] + attribute \src "libresoc.v:7210.5-7210.29" + switch \initial + attribute \src "libresoc.v:7210.9-7210.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\CR_dec31_dec_sub19_cr_out[2:0] 3'000 + case + assign $1\CR_dec31_dec_sub19_cr_out[2:0] 3'000 + end + sync always + update \CR_dec31_dec_sub19_cr_out $0\CR_dec31_dec_sub19_cr_out[2:0] + end + attribute \src "libresoc.v:7219.3-7228.6" + process $proc$libresoc.v:7219$149 + assign { } { } + assign { } { } + assign $0\CR_dec31_dec_sub19_rc_sel[1:0] $1\CR_dec31_dec_sub19_rc_sel[1:0] + attribute \src "libresoc.v:7220.5-7220.29" + switch \initial + attribute \src "libresoc.v:7220.9-7220.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\CR_dec31_dec_sub19_rc_sel[1:0] 2'00 + case + assign $1\CR_dec31_dec_sub19_rc_sel[1:0] 2'00 + end + sync always + update \CR_dec31_dec_sub19_rc_sel $0\CR_dec31_dec_sub19_rc_sel[1:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:7234.1-7981.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_DIV.dec.DIV_dec31" +attribute \generator "nMigen" +module \DIV_dec31 + attribute \src "libresoc.v:7951.3-7963.6" + wire width 3 $0\DIV_dec31_cr_in[2:0] + attribute \src "libresoc.v:7964.3-7976.6" + wire width 3 $0\DIV_dec31_cr_out[2:0] + attribute \src "libresoc.v:7821.3-7833.6" + wire width 2 $0\DIV_dec31_cry_in[1:0] + attribute \src "libresoc.v:7860.3-7872.6" + wire $0\DIV_dec31_cry_out[0:0] + attribute \src "libresoc.v:7899.3-7911.6" + wire width 13 $0\DIV_dec31_function_unit[12:0] + attribute \src "libresoc.v:7925.3-7937.6" + wire width 3 $0\DIV_dec31_in1_sel[2:0] + attribute \src "libresoc.v:7938.3-7950.6" + wire width 4 $0\DIV_dec31_in2_sel[3:0] + attribute \src "libresoc.v:7912.3-7924.6" + wire width 7 $0\DIV_dec31_internal_op[6:0] + attribute \src "libresoc.v:7834.3-7846.6" + wire $0\DIV_dec31_inv_a[0:0] + attribute \src "libresoc.v:7847.3-7859.6" + wire $0\DIV_dec31_inv_out[0:0] + attribute \src "libresoc.v:7873.3-7885.6" + wire $0\DIV_dec31_is_32b[0:0] + attribute \src "libresoc.v:7795.3-7807.6" + wire width 4 $0\DIV_dec31_ldst_len[3:0] + attribute \src "libresoc.v:7808.3-7820.6" + wire width 2 $0\DIV_dec31_rc_sel[1:0] + attribute \src "libresoc.v:7886.3-7898.6" + wire $0\DIV_dec31_sgn[0:0] + attribute \src "libresoc.v:7235.7-7235.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:7951.3-7963.6" + wire width 3 $1\DIV_dec31_cr_in[2:0] + attribute \src "libresoc.v:7964.3-7976.6" + wire width 3 $1\DIV_dec31_cr_out[2:0] + attribute \src "libresoc.v:7821.3-7833.6" + wire width 2 $1\DIV_dec31_cry_in[1:0] + attribute \src "libresoc.v:7860.3-7872.6" + wire $1\DIV_dec31_cry_out[0:0] + attribute \src "libresoc.v:7899.3-7911.6" + wire width 13 $1\DIV_dec31_function_unit[12:0] + attribute \src "libresoc.v:7925.3-7937.6" + wire width 3 $1\DIV_dec31_in1_sel[2:0] + attribute \src "libresoc.v:7938.3-7950.6" + wire width 4 $1\DIV_dec31_in2_sel[3:0] + attribute \src "libresoc.v:7912.3-7924.6" + wire width 7 $1\DIV_dec31_internal_op[6:0] + attribute \src "libresoc.v:7834.3-7846.6" + wire $1\DIV_dec31_inv_a[0:0] + attribute \src "libresoc.v:7847.3-7859.6" + wire $1\DIV_dec31_inv_out[0:0] + attribute \src "libresoc.v:7873.3-7885.6" + wire $1\DIV_dec31_is_32b[0:0] + attribute \src "libresoc.v:7795.3-7807.6" + wire width 4 $1\DIV_dec31_ldst_len[3:0] + attribute \src "libresoc.v:7808.3-7820.6" + wire width 2 $1\DIV_dec31_rc_sel[1:0] + attribute \src "libresoc.v:7886.3-7898.6" + wire $1\DIV_dec31_sgn[0:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 5 \DIV_dec31_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 6 \DIV_dec31_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 9 \DIV_dec31_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 12 \DIV_dec31_cry_out + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 13 \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_function_unit + attribute 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attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute 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\enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 output 2 \DIV_dec31_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 10 \DIV_dec31_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 11 \DIV_dec31_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 13 \DIV_dec31_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 7 \DIV_dec31_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 8 \DIV_dec31_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 14 \DIV_dec31_sgn + attribute \src "libresoc.v:7235.7-7235.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:347" + wire width 5 \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + wire width 32 input 15 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + wire width 10 \opcode_switch + attribute \module_not_derived 1 + attribute \src "libresoc.v:7761.23-7777.4" + cell \DIV_dec31_dec_sub11 \DIV_dec31_dec_sub11 + connect \DIV_dec31_dec_sub11_cr_in \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cr_in + connect \DIV_dec31_dec_sub11_cr_out \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cr_out + connect \DIV_dec31_dec_sub11_cry_in \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cry_in + connect \DIV_dec31_dec_sub11_cry_out \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cry_out + connect \DIV_dec31_dec_sub11_function_unit \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_function_unit + connect \DIV_dec31_dec_sub11_in1_sel \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_in1_sel + connect \DIV_dec31_dec_sub11_in2_sel \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_in2_sel + connect \DIV_dec31_dec_sub11_internal_op \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_internal_op + connect \DIV_dec31_dec_sub11_inv_a \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_inv_a + connect \DIV_dec31_dec_sub11_inv_out \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_inv_out + connect \DIV_dec31_dec_sub11_is_32b \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_is_32b + connect \DIV_dec31_dec_sub11_ldst_len \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_ldst_len + connect \DIV_dec31_dec_sub11_rc_sel \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_rc_sel + connect \DIV_dec31_dec_sub11_sgn \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_sgn + connect \opcode_in \DIV_dec31_dec_sub11_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:7778.22-7794.4" + cell \DIV_dec31_dec_sub9 \DIV_dec31_dec_sub9 + connect \DIV_dec31_dec_sub9_cr_in \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cr_in + connect \DIV_dec31_dec_sub9_cr_out \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cr_out + connect \DIV_dec31_dec_sub9_cry_in \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cry_in + connect \DIV_dec31_dec_sub9_cry_out \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cry_out + connect \DIV_dec31_dec_sub9_function_unit \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_function_unit + connect \DIV_dec31_dec_sub9_in1_sel \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_in1_sel + connect \DIV_dec31_dec_sub9_in2_sel \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_in2_sel + connect \DIV_dec31_dec_sub9_internal_op \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_internal_op + connect \DIV_dec31_dec_sub9_inv_a \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_inv_a + connect \DIV_dec31_dec_sub9_inv_out \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_inv_out + connect \DIV_dec31_dec_sub9_is_32b \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_is_32b + connect \DIV_dec31_dec_sub9_ldst_len \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_ldst_len + connect \DIV_dec31_dec_sub9_rc_sel \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_rc_sel + connect \DIV_dec31_dec_sub9_sgn \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_sgn + connect \opcode_in \DIV_dec31_dec_sub9_opcode_in + end + attribute \src "libresoc.v:7235.7-7235.20" + process $proc$libresoc.v:7235$165 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:7795.3-7807.6" + process $proc$libresoc.v:7795$151 + assign { } { } + assign { } { } + assign $0\DIV_dec31_ldst_len[3:0] $1\DIV_dec31_ldst_len[3:0] + attribute \src "libresoc.v:7796.5-7796.29" + switch \initial + attribute \src "libresoc.v:7796.9-7796.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\DIV_dec31_ldst_len[3:0] \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\DIV_dec31_ldst_len[3:0] \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_ldst_len + case + assign $1\DIV_dec31_ldst_len[3:0] 4'0000 + end + sync always + update \DIV_dec31_ldst_len $0\DIV_dec31_ldst_len[3:0] + end + attribute \src "libresoc.v:7808.3-7820.6" + process $proc$libresoc.v:7808$152 + assign { } { } + assign { } { } + assign $0\DIV_dec31_rc_sel[1:0] $1\DIV_dec31_rc_sel[1:0] + attribute \src "libresoc.v:7809.5-7809.29" + switch \initial + attribute \src "libresoc.v:7809.9-7809.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\DIV_dec31_rc_sel[1:0] \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\DIV_dec31_rc_sel[1:0] \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_rc_sel + case + assign $1\DIV_dec31_rc_sel[1:0] 2'00 + end + sync always + update \DIV_dec31_rc_sel $0\DIV_dec31_rc_sel[1:0] + end + attribute \src "libresoc.v:7821.3-7833.6" + process $proc$libresoc.v:7821$153 + assign { } { } + assign { } { } + assign $0\DIV_dec31_cry_in[1:0] $1\DIV_dec31_cry_in[1:0] + attribute \src "libresoc.v:7822.5-7822.29" + switch \initial + attribute \src "libresoc.v:7822.9-7822.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\DIV_dec31_cry_in[1:0] \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\DIV_dec31_cry_in[1:0] \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cry_in + case + assign $1\DIV_dec31_cry_in[1:0] 2'00 + end + sync always + update \DIV_dec31_cry_in $0\DIV_dec31_cry_in[1:0] + end + attribute \src "libresoc.v:7834.3-7846.6" + process $proc$libresoc.v:7834$154 + assign { } { } + assign { } { } + assign $0\DIV_dec31_inv_a[0:0] $1\DIV_dec31_inv_a[0:0] + attribute \src "libresoc.v:7835.5-7835.29" + switch \initial + attribute \src "libresoc.v:7835.9-7835.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\DIV_dec31_inv_a[0:0] \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\DIV_dec31_inv_a[0:0] \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_inv_a + case + assign $1\DIV_dec31_inv_a[0:0] 1'0 + end + sync always + update \DIV_dec31_inv_a $0\DIV_dec31_inv_a[0:0] + end + attribute \src "libresoc.v:7847.3-7859.6" + process $proc$libresoc.v:7847$155 + assign { } { } + assign { } { } + assign $0\DIV_dec31_inv_out[0:0] $1\DIV_dec31_inv_out[0:0] + attribute \src "libresoc.v:7848.5-7848.29" + switch \initial + attribute \src "libresoc.v:7848.9-7848.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\DIV_dec31_inv_out[0:0] \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\DIV_dec31_inv_out[0:0] \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_inv_out + case + assign $1\DIV_dec31_inv_out[0:0] 1'0 + end + sync always + update \DIV_dec31_inv_out $0\DIV_dec31_inv_out[0:0] + end + attribute \src "libresoc.v:7860.3-7872.6" + process $proc$libresoc.v:7860$156 + assign { } { } + assign { } { } + assign $0\DIV_dec31_cry_out[0:0] $1\DIV_dec31_cry_out[0:0] + attribute \src "libresoc.v:7861.5-7861.29" + switch \initial + attribute \src "libresoc.v:7861.9-7861.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\DIV_dec31_cry_out[0:0] \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\DIV_dec31_cry_out[0:0] \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cry_out + case + assign $1\DIV_dec31_cry_out[0:0] 1'0 + end + sync always + update \DIV_dec31_cry_out $0\DIV_dec31_cry_out[0:0] + end + attribute \src "libresoc.v:7873.3-7885.6" + process $proc$libresoc.v:7873$157 + assign { } { } + assign { } { } + assign $0\DIV_dec31_is_32b[0:0] $1\DIV_dec31_is_32b[0:0] + attribute \src "libresoc.v:7874.5-7874.29" + switch \initial + attribute \src "libresoc.v:7874.9-7874.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\DIV_dec31_is_32b[0:0] \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\DIV_dec31_is_32b[0:0] \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_is_32b + case + assign $1\DIV_dec31_is_32b[0:0] 1'0 + end + sync always + update \DIV_dec31_is_32b $0\DIV_dec31_is_32b[0:0] + end + attribute \src "libresoc.v:7886.3-7898.6" + process $proc$libresoc.v:7886$158 + assign { } { } + assign { } { } + assign $0\DIV_dec31_sgn[0:0] $1\DIV_dec31_sgn[0:0] + attribute \src "libresoc.v:7887.5-7887.29" + switch \initial + attribute \src "libresoc.v:7887.9-7887.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\DIV_dec31_sgn[0:0] \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\DIV_dec31_sgn[0:0] \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_sgn + case + assign $1\DIV_dec31_sgn[0:0] 1'0 + end + sync always + update \DIV_dec31_sgn $0\DIV_dec31_sgn[0:0] + end + attribute \src "libresoc.v:7899.3-7911.6" + process $proc$libresoc.v:7899$159 + assign { } { } + assign { } { } + assign $0\DIV_dec31_function_unit[12:0] $1\DIV_dec31_function_unit[12:0] + attribute \src "libresoc.v:7900.5-7900.29" + switch \initial + attribute \src "libresoc.v:7900.9-7900.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\DIV_dec31_function_unit[12:0] \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\DIV_dec31_function_unit[12:0] \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_function_unit + case + assign $1\DIV_dec31_function_unit[12:0] 13'0000000000000 + end + sync always + update \DIV_dec31_function_unit $0\DIV_dec31_function_unit[12:0] + end + attribute \src "libresoc.v:7912.3-7924.6" + process $proc$libresoc.v:7912$160 + assign { } { } + assign { } { } + assign $0\DIV_dec31_internal_op[6:0] $1\DIV_dec31_internal_op[6:0] + attribute \src "libresoc.v:7913.5-7913.29" + switch \initial + attribute \src "libresoc.v:7913.9-7913.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\DIV_dec31_internal_op[6:0] \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\DIV_dec31_internal_op[6:0] \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_internal_op + case + assign $1\DIV_dec31_internal_op[6:0] 7'0000000 + end + sync always + update \DIV_dec31_internal_op $0\DIV_dec31_internal_op[6:0] + end + attribute \src "libresoc.v:7925.3-7937.6" + process $proc$libresoc.v:7925$161 + assign { } { } + assign { } { } + assign $0\DIV_dec31_in1_sel[2:0] $1\DIV_dec31_in1_sel[2:0] + attribute \src "libresoc.v:7926.5-7926.29" + switch \initial + attribute \src "libresoc.v:7926.9-7926.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\DIV_dec31_in1_sel[2:0] \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\DIV_dec31_in1_sel[2:0] \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_in1_sel + case + assign $1\DIV_dec31_in1_sel[2:0] 3'000 + end + sync always + update \DIV_dec31_in1_sel $0\DIV_dec31_in1_sel[2:0] + end + attribute \src "libresoc.v:7938.3-7950.6" + process $proc$libresoc.v:7938$162 + assign { } { } + assign { } { } + assign $0\DIV_dec31_in2_sel[3:0] $1\DIV_dec31_in2_sel[3:0] + attribute \src "libresoc.v:7939.5-7939.29" + switch \initial + attribute \src "libresoc.v:7939.9-7939.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\DIV_dec31_in2_sel[3:0] \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\DIV_dec31_in2_sel[3:0] \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_in2_sel + case + assign $1\DIV_dec31_in2_sel[3:0] 4'0000 + end + sync always + update \DIV_dec31_in2_sel $0\DIV_dec31_in2_sel[3:0] + end + attribute \src "libresoc.v:7951.3-7963.6" + process $proc$libresoc.v:7951$163 + assign { } { } + assign { } { } + assign $0\DIV_dec31_cr_in[2:0] $1\DIV_dec31_cr_in[2:0] + attribute \src "libresoc.v:7952.5-7952.29" + switch \initial + attribute \src "libresoc.v:7952.9-7952.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\DIV_dec31_cr_in[2:0] \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\DIV_dec31_cr_in[2:0] \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cr_in + case + assign $1\DIV_dec31_cr_in[2:0] 3'000 + end + sync always + update \DIV_dec31_cr_in $0\DIV_dec31_cr_in[2:0] + end + attribute \src "libresoc.v:7964.3-7976.6" + process $proc$libresoc.v:7964$164 + assign { } { } + assign { } { } + assign $0\DIV_dec31_cr_out[2:0] $1\DIV_dec31_cr_out[2:0] + attribute \src "libresoc.v:7965.5-7965.29" + switch \initial + attribute \src "libresoc.v:7965.9-7965.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\DIV_dec31_cr_out[2:0] \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\DIV_dec31_cr_out[2:0] \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cr_out + case + assign $1\DIV_dec31_cr_out[2:0] 3'000 + end + sync always + update \DIV_dec31_cr_out $0\DIV_dec31_cr_out[2:0] + end + connect \DIV_dec31_dec_sub11_opcode_in \opcode_in + connect \DIV_dec31_dec_sub9_opcode_in \opcode_in + connect \opc_in \opcode_switch [4:0] + connect \opcode_switch \opcode_in [10:1] +end +attribute \src "libresoc.v:7985.1-8691.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_DIV.dec.DIV_dec31.DIV_dec31_dec_sub11" +attribute \generator "nMigen" +module \DIV_dec31_dec_sub11 + attribute \src "libresoc.v:8505.3-8541.6" + wire width 3 $0\DIV_dec31_dec_sub11_cr_in[2:0] + attribute \src "libresoc.v:8542.3-8578.6" + wire width 3 $0\DIV_dec31_dec_sub11_cr_out[2:0] + attribute \src "libresoc.v:8653.3-8689.6" + wire width 2 $0\DIV_dec31_dec_sub11_cry_in[1:0] + attribute \src "libresoc.v:8283.3-8319.6" + wire $0\DIV_dec31_dec_sub11_cry_out[0:0] + attribute \src "libresoc.v:8172.3-8208.6" + wire width 13 $0\DIV_dec31_dec_sub11_function_unit[12:0] + attribute \src "libresoc.v:8431.3-8467.6" + wire width 3 $0\DIV_dec31_dec_sub11_in1_sel[2:0] + attribute \src "libresoc.v:8468.3-8504.6" + wire width 4 $0\DIV_dec31_dec_sub11_in2_sel[3:0] + attribute \src "libresoc.v:8394.3-8430.6" + wire width 7 $0\DIV_dec31_dec_sub11_internal_op[6:0] + attribute \src "libresoc.v:8209.3-8245.6" + wire $0\DIV_dec31_dec_sub11_inv_a[0:0] + attribute \src "libresoc.v:8246.3-8282.6" + wire $0\DIV_dec31_dec_sub11_inv_out[0:0] + attribute \src "libresoc.v:8320.3-8356.6" + wire $0\DIV_dec31_dec_sub11_is_32b[0:0] + attribute \src "libresoc.v:8579.3-8615.6" + wire width 4 $0\DIV_dec31_dec_sub11_ldst_len[3:0] + attribute \src "libresoc.v:8616.3-8652.6" + wire width 2 $0\DIV_dec31_dec_sub11_rc_sel[1:0] + attribute \src "libresoc.v:8357.3-8393.6" + wire $0\DIV_dec31_dec_sub11_sgn[0:0] + attribute \src "libresoc.v:7986.7-7986.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:8505.3-8541.6" + wire width 3 $1\DIV_dec31_dec_sub11_cr_in[2:0] + attribute \src "libresoc.v:8542.3-8578.6" + wire width 3 $1\DIV_dec31_dec_sub11_cr_out[2:0] + attribute \src "libresoc.v:8653.3-8689.6" + wire width 2 $1\DIV_dec31_dec_sub11_cry_in[1:0] + attribute \src "libresoc.v:8283.3-8319.6" + wire $1\DIV_dec31_dec_sub11_cry_out[0:0] + attribute \src "libresoc.v:8172.3-8208.6" + wire width 13 $1\DIV_dec31_dec_sub11_function_unit[12:0] + attribute \src "libresoc.v:8431.3-8467.6" + wire width 3 $1\DIV_dec31_dec_sub11_in1_sel[2:0] + attribute \src "libresoc.v:8468.3-8504.6" + wire width 4 $1\DIV_dec31_dec_sub11_in2_sel[3:0] + attribute \src "libresoc.v:8394.3-8430.6" + wire width 7 $1\DIV_dec31_dec_sub11_internal_op[6:0] + attribute \src "libresoc.v:8209.3-8245.6" + wire $1\DIV_dec31_dec_sub11_inv_a[0:0] + attribute \src "libresoc.v:8246.3-8282.6" + wire $1\DIV_dec31_dec_sub11_inv_out[0:0] + attribute \src "libresoc.v:8320.3-8356.6" + wire $1\DIV_dec31_dec_sub11_is_32b[0:0] + attribute \src "libresoc.v:8579.3-8615.6" + wire width 4 $1\DIV_dec31_dec_sub11_ldst_len[3:0] + attribute \src "libresoc.v:8616.3-8652.6" + wire width 2 $1\DIV_dec31_dec_sub11_rc_sel[1:0] + attribute \src "libresoc.v:8357.3-8393.6" + wire $1\DIV_dec31_dec_sub11_sgn[0:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 5 \DIV_dec31_dec_sub11_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 6 \DIV_dec31_dec_sub11_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 9 \DIV_dec31_dec_sub11_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 12 \DIV_dec31_dec_sub11_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 13 output 1 \DIV_dec31_dec_sub11_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 3 \DIV_dec31_dec_sub11_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 4 \DIV_dec31_dec_sub11_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 output 2 \DIV_dec31_dec_sub11_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 10 \DIV_dec31_dec_sub11_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 11 \DIV_dec31_dec_sub11_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 13 \DIV_dec31_dec_sub11_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 7 \DIV_dec31_dec_sub11_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 8 \DIV_dec31_dec_sub11_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 14 \DIV_dec31_dec_sub11_sgn + attribute \src "libresoc.v:7986.7-7986.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + wire width 32 input 15 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + wire width 5 \opcode_switch + attribute \src "libresoc.v:7986.7-7986.20" + process $proc$libresoc.v:7986$180 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:8172.3-8208.6" + process $proc$libresoc.v:8172$166 + assign { } { } + assign { } { } + assign $0\DIV_dec31_dec_sub11_function_unit[12:0] $1\DIV_dec31_dec_sub11_function_unit[12:0] + attribute \src "libresoc.v:8173.5-8173.29" + switch \initial + attribute \src "libresoc.v:8173.9-8173.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\DIV_dec31_dec_sub11_function_unit[12:0] 13'0001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\DIV_dec31_dec_sub11_function_unit[12:0] 13'0001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\DIV_dec31_dec_sub11_function_unit[12:0] 13'0001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\DIV_dec31_dec_sub11_function_unit[12:0] 13'0001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\DIV_dec31_dec_sub11_function_unit[12:0] 13'0001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\DIV_dec31_dec_sub11_function_unit[12:0] 13'0001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\DIV_dec31_dec_sub11_function_unit[12:0] 13'0001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\DIV_dec31_dec_sub11_function_unit[12:0] 13'0001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\DIV_dec31_dec_sub11_function_unit[12:0] 13'0001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\DIV_dec31_dec_sub11_function_unit[12:0] 13'0001000000000 + case + assign $1\DIV_dec31_dec_sub11_function_unit[12:0] 13'0000000000000 + end + sync always + update \DIV_dec31_dec_sub11_function_unit $0\DIV_dec31_dec_sub11_function_unit[12:0] + end + attribute \src "libresoc.v:8209.3-8245.6" + process $proc$libresoc.v:8209$167 + assign { } { } + assign { } { } + assign $0\DIV_dec31_dec_sub11_inv_a[0:0] $1\DIV_dec31_dec_sub11_inv_a[0:0] + attribute \src "libresoc.v:8210.5-8210.29" + switch \initial + attribute \src "libresoc.v:8210.9-8210.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\DIV_dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\DIV_dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\DIV_dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\DIV_dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\DIV_dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\DIV_dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\DIV_dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\DIV_dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\DIV_dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\DIV_dec31_dec_sub11_inv_a[0:0] 1'0 + case + assign $1\DIV_dec31_dec_sub11_inv_a[0:0] 1'0 + end + sync always + update \DIV_dec31_dec_sub11_inv_a $0\DIV_dec31_dec_sub11_inv_a[0:0] + end + attribute \src "libresoc.v:8246.3-8282.6" + process $proc$libresoc.v:8246$168 + assign { } { } + assign { } { } + assign $0\DIV_dec31_dec_sub11_inv_out[0:0] $1\DIV_dec31_dec_sub11_inv_out[0:0] + attribute \src "libresoc.v:8247.5-8247.29" + switch \initial + attribute \src "libresoc.v:8247.9-8247.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\DIV_dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\DIV_dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\DIV_dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\DIV_dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\DIV_dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\DIV_dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\DIV_dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\DIV_dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\DIV_dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\DIV_dec31_dec_sub11_inv_out[0:0] 1'0 + case + assign $1\DIV_dec31_dec_sub11_inv_out[0:0] 1'0 + end + sync always + update \DIV_dec31_dec_sub11_inv_out $0\DIV_dec31_dec_sub11_inv_out[0:0] + end + attribute \src "libresoc.v:8283.3-8319.6" + process $proc$libresoc.v:8283$169 + assign { } { } + assign { } { } + assign $0\DIV_dec31_dec_sub11_cry_out[0:0] $1\DIV_dec31_dec_sub11_cry_out[0:0] + attribute \src "libresoc.v:8284.5-8284.29" + switch \initial + attribute \src "libresoc.v:8284.9-8284.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cry_out[0:0] 1'0 + case + assign $1\DIV_dec31_dec_sub11_cry_out[0:0] 1'0 + end + sync always + update \DIV_dec31_dec_sub11_cry_out $0\DIV_dec31_dec_sub11_cry_out[0:0] + end + attribute \src "libresoc.v:8320.3-8356.6" + process $proc$libresoc.v:8320$170 + assign { } { } + assign { } { } + assign $0\DIV_dec31_dec_sub11_is_32b[0:0] $1\DIV_dec31_dec_sub11_is_32b[0:0] + attribute \src "libresoc.v:8321.5-8321.29" + switch \initial + attribute \src "libresoc.v:8321.9-8321.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\DIV_dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\DIV_dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\DIV_dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\DIV_dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\DIV_dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\DIV_dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\DIV_dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\DIV_dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\DIV_dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\DIV_dec31_dec_sub11_is_32b[0:0] 1'1 + case + assign $1\DIV_dec31_dec_sub11_is_32b[0:0] 1'0 + end + sync always + update \DIV_dec31_dec_sub11_is_32b $0\DIV_dec31_dec_sub11_is_32b[0:0] + end + attribute \src "libresoc.v:8357.3-8393.6" + process $proc$libresoc.v:8357$171 + assign { } { } + assign { } { } + assign $0\DIV_dec31_dec_sub11_sgn[0:0] $1\DIV_dec31_dec_sub11_sgn[0:0] + attribute \src "libresoc.v:8358.5-8358.29" + switch \initial + attribute \src "libresoc.v:8358.9-8358.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\DIV_dec31_dec_sub11_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\DIV_dec31_dec_sub11_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\DIV_dec31_dec_sub11_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\DIV_dec31_dec_sub11_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\DIV_dec31_dec_sub11_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\DIV_dec31_dec_sub11_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\DIV_dec31_dec_sub11_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\DIV_dec31_dec_sub11_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\DIV_dec31_dec_sub11_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\DIV_dec31_dec_sub11_sgn[0:0] 1'1 + case + assign $1\DIV_dec31_dec_sub11_sgn[0:0] 1'0 + end + sync always + update \DIV_dec31_dec_sub11_sgn $0\DIV_dec31_dec_sub11_sgn[0:0] + end + attribute \src "libresoc.v:8394.3-8430.6" + process $proc$libresoc.v:8394$172 + assign { } { } + assign { } { } + assign $0\DIV_dec31_dec_sub11_internal_op[6:0] $1\DIV_dec31_dec_sub11_internal_op[6:0] + attribute \src "libresoc.v:8395.5-8395.29" + switch \initial + attribute \src "libresoc.v:8395.9-8395.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\DIV_dec31_dec_sub11_internal_op[6:0] 7'0011110 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\DIV_dec31_dec_sub11_internal_op[6:0] 7'0011110 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\DIV_dec31_dec_sub11_internal_op[6:0] 7'0011110 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\DIV_dec31_dec_sub11_internal_op[6:0] 7'0011110 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\DIV_dec31_dec_sub11_internal_op[6:0] 7'0011101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\DIV_dec31_dec_sub11_internal_op[6:0] 7'0011101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\DIV_dec31_dec_sub11_internal_op[6:0] 7'0011101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\DIV_dec31_dec_sub11_internal_op[6:0] 7'0011101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\DIV_dec31_dec_sub11_internal_op[6:0] 7'0101111 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\DIV_dec31_dec_sub11_internal_op[6:0] 7'0101111 + case + assign $1\DIV_dec31_dec_sub11_internal_op[6:0] 7'0000000 + end + sync always + update \DIV_dec31_dec_sub11_internal_op $0\DIV_dec31_dec_sub11_internal_op[6:0] + end + attribute \src "libresoc.v:8431.3-8467.6" + process $proc$libresoc.v:8431$173 + assign { } { } + assign { } { } + assign $0\DIV_dec31_dec_sub11_in1_sel[2:0] $1\DIV_dec31_dec_sub11_in1_sel[2:0] + attribute \src "libresoc.v:8432.5-8432.29" + switch \initial + attribute \src "libresoc.v:8432.9-8432.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\DIV_dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\DIV_dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\DIV_dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\DIV_dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\DIV_dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\DIV_dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\DIV_dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\DIV_dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\DIV_dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\DIV_dec31_dec_sub11_in1_sel[2:0] 3'001 + case + assign $1\DIV_dec31_dec_sub11_in1_sel[2:0] 3'000 + end + sync always + update \DIV_dec31_dec_sub11_in1_sel $0\DIV_dec31_dec_sub11_in1_sel[2:0] + end + attribute \src "libresoc.v:8468.3-8504.6" + process $proc$libresoc.v:8468$174 + assign { } { } + assign { } { } + assign $0\DIV_dec31_dec_sub11_in2_sel[3:0] $1\DIV_dec31_dec_sub11_in2_sel[3:0] + attribute \src "libresoc.v:8469.5-8469.29" + switch \initial + attribute \src "libresoc.v:8469.9-8469.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\DIV_dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\DIV_dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\DIV_dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\DIV_dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\DIV_dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\DIV_dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\DIV_dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\DIV_dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\DIV_dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\DIV_dec31_dec_sub11_in2_sel[3:0] 4'0001 + case + assign $1\DIV_dec31_dec_sub11_in2_sel[3:0] 4'0000 + end + sync always + update \DIV_dec31_dec_sub11_in2_sel $0\DIV_dec31_dec_sub11_in2_sel[3:0] + end + attribute \src "libresoc.v:8505.3-8541.6" + process $proc$libresoc.v:8505$175 + assign { } { } + assign { } { } + assign $0\DIV_dec31_dec_sub11_cr_in[2:0] $1\DIV_dec31_dec_sub11_cr_in[2:0] + attribute \src "libresoc.v:8506.5-8506.29" + switch \initial + attribute \src "libresoc.v:8506.9-8506.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cr_in[2:0] 3'000 + case + assign $1\DIV_dec31_dec_sub11_cr_in[2:0] 3'000 + end + sync always + update \DIV_dec31_dec_sub11_cr_in $0\DIV_dec31_dec_sub11_cr_in[2:0] + end + attribute \src "libresoc.v:8542.3-8578.6" + process $proc$libresoc.v:8542$176 + assign { } { } + assign { } { } + assign $0\DIV_dec31_dec_sub11_cr_out[2:0] $1\DIV_dec31_dec_sub11_cr_out[2:0] + attribute \src "libresoc.v:8543.5-8543.29" + switch \initial + attribute \src "libresoc.v:8543.9-8543.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cr_out[2:0] 3'000 + case + assign $1\DIV_dec31_dec_sub11_cr_out[2:0] 3'000 + end + sync always + update \DIV_dec31_dec_sub11_cr_out $0\DIV_dec31_dec_sub11_cr_out[2:0] + end + attribute \src "libresoc.v:8579.3-8615.6" + process $proc$libresoc.v:8579$177 + assign { } { } + assign { } { } + assign $0\DIV_dec31_dec_sub11_ldst_len[3:0] $1\DIV_dec31_dec_sub11_ldst_len[3:0] + attribute \src "libresoc.v:8580.5-8580.29" + switch \initial + attribute \src "libresoc.v:8580.9-8580.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\DIV_dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\DIV_dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\DIV_dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\DIV_dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\DIV_dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\DIV_dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\DIV_dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\DIV_dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\DIV_dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\DIV_dec31_dec_sub11_ldst_len[3:0] 4'0000 + case + assign $1\DIV_dec31_dec_sub11_ldst_len[3:0] 4'0000 + end + sync always + update \DIV_dec31_dec_sub11_ldst_len $0\DIV_dec31_dec_sub11_ldst_len[3:0] + end + attribute \src "libresoc.v:8616.3-8652.6" + process $proc$libresoc.v:8616$178 + assign { } { } + assign { } { } + assign $0\DIV_dec31_dec_sub11_rc_sel[1:0] $1\DIV_dec31_dec_sub11_rc_sel[1:0] + attribute \src "libresoc.v:8617.5-8617.29" + switch \initial + attribute \src "libresoc.v:8617.9-8617.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\DIV_dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\DIV_dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\DIV_dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\DIV_dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\DIV_dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\DIV_dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\DIV_dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\DIV_dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\DIV_dec31_dec_sub11_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\DIV_dec31_dec_sub11_rc_sel[1:0] 2'00 + case + assign $1\DIV_dec31_dec_sub11_rc_sel[1:0] 2'00 + end + sync always + update \DIV_dec31_dec_sub11_rc_sel $0\DIV_dec31_dec_sub11_rc_sel[1:0] + end + attribute \src "libresoc.v:8653.3-8689.6" + process $proc$libresoc.v:8653$179 + assign { } { } + assign { } { } + assign $0\DIV_dec31_dec_sub11_cry_in[1:0] $1\DIV_dec31_dec_sub11_cry_in[1:0] + attribute \src "libresoc.v:8654.5-8654.29" + switch \initial + attribute \src "libresoc.v:8654.9-8654.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cry_in[1:0] 2'00 + case + assign $1\DIV_dec31_dec_sub11_cry_in[1:0] 2'00 + end + sync always + update \DIV_dec31_dec_sub11_cry_in $0\DIV_dec31_dec_sub11_cry_in[1:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:8695.1-9401.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_DIV.dec.DIV_dec31.DIV_dec31_dec_sub9" +attribute \generator "nMigen" +module \DIV_dec31_dec_sub9 + attribute \src "libresoc.v:9215.3-9251.6" + wire width 3 $0\DIV_dec31_dec_sub9_cr_in[2:0] + attribute \src "libresoc.v:9252.3-9288.6" + wire width 3 $0\DIV_dec31_dec_sub9_cr_out[2:0] + attribute \src "libresoc.v:9363.3-9399.6" + wire width 2 $0\DIV_dec31_dec_sub9_cry_in[1:0] + attribute \src "libresoc.v:8993.3-9029.6" + wire $0\DIV_dec31_dec_sub9_cry_out[0:0] + attribute \src "libresoc.v:8882.3-8918.6" + wire width 13 $0\DIV_dec31_dec_sub9_function_unit[12:0] + attribute \src "libresoc.v:9141.3-9177.6" + wire width 3 $0\DIV_dec31_dec_sub9_in1_sel[2:0] + attribute \src "libresoc.v:9178.3-9214.6" + wire width 4 $0\DIV_dec31_dec_sub9_in2_sel[3:0] + attribute \src "libresoc.v:9104.3-9140.6" + wire width 7 $0\DIV_dec31_dec_sub9_internal_op[6:0] + attribute \src "libresoc.v:8919.3-8955.6" + wire $0\DIV_dec31_dec_sub9_inv_a[0:0] + attribute \src "libresoc.v:8956.3-8992.6" + wire $0\DIV_dec31_dec_sub9_inv_out[0:0] + attribute \src "libresoc.v:9030.3-9066.6" + wire $0\DIV_dec31_dec_sub9_is_32b[0:0] + attribute \src "libresoc.v:9289.3-9325.6" + wire width 4 $0\DIV_dec31_dec_sub9_ldst_len[3:0] + attribute \src "libresoc.v:9326.3-9362.6" + wire width 2 $0\DIV_dec31_dec_sub9_rc_sel[1:0] + attribute \src "libresoc.v:9067.3-9103.6" + wire $0\DIV_dec31_dec_sub9_sgn[0:0] + attribute \src "libresoc.v:8696.7-8696.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:9215.3-9251.6" + wire width 3 $1\DIV_dec31_dec_sub9_cr_in[2:0] + attribute \src "libresoc.v:9252.3-9288.6" + wire width 3 $1\DIV_dec31_dec_sub9_cr_out[2:0] + attribute \src "libresoc.v:9363.3-9399.6" + wire width 2 $1\DIV_dec31_dec_sub9_cry_in[1:0] + attribute \src "libresoc.v:8993.3-9029.6" + wire $1\DIV_dec31_dec_sub9_cry_out[0:0] + attribute \src "libresoc.v:8882.3-8918.6" + wire width 13 $1\DIV_dec31_dec_sub9_function_unit[12:0] + attribute \src "libresoc.v:9141.3-9177.6" + wire width 3 $1\DIV_dec31_dec_sub9_in1_sel[2:0] + attribute \src "libresoc.v:9178.3-9214.6" + wire width 4 $1\DIV_dec31_dec_sub9_in2_sel[3:0] + attribute \src "libresoc.v:9104.3-9140.6" + wire width 7 $1\DIV_dec31_dec_sub9_internal_op[6:0] + attribute \src "libresoc.v:8919.3-8955.6" + wire $1\DIV_dec31_dec_sub9_inv_a[0:0] + attribute \src "libresoc.v:8956.3-8992.6" + wire $1\DIV_dec31_dec_sub9_inv_out[0:0] + attribute \src "libresoc.v:9030.3-9066.6" + wire $1\DIV_dec31_dec_sub9_is_32b[0:0] + attribute \src "libresoc.v:9289.3-9325.6" + wire width 4 $1\DIV_dec31_dec_sub9_ldst_len[3:0] + attribute \src "libresoc.v:9326.3-9362.6" + wire width 2 $1\DIV_dec31_dec_sub9_rc_sel[1:0] + attribute \src "libresoc.v:9067.3-9103.6" + wire $1\DIV_dec31_dec_sub9_sgn[0:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 5 \DIV_dec31_dec_sub9_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 6 \DIV_dec31_dec_sub9_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 9 \DIV_dec31_dec_sub9_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 12 \DIV_dec31_dec_sub9_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 13 output 1 \DIV_dec31_dec_sub9_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 3 \DIV_dec31_dec_sub9_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 4 \DIV_dec31_dec_sub9_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 output 2 \DIV_dec31_dec_sub9_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 10 \DIV_dec31_dec_sub9_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 11 \DIV_dec31_dec_sub9_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 13 \DIV_dec31_dec_sub9_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 7 \DIV_dec31_dec_sub9_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 8 \DIV_dec31_dec_sub9_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 14 \DIV_dec31_dec_sub9_sgn + attribute \src "libresoc.v:8696.7-8696.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + wire width 32 input 15 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + wire width 5 \opcode_switch + attribute \src "libresoc.v:8696.7-8696.20" + process $proc$libresoc.v:8696$195 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:8882.3-8918.6" + process $proc$libresoc.v:8882$181 + assign { } { } + assign { } { } + assign $0\DIV_dec31_dec_sub9_function_unit[12:0] $1\DIV_dec31_dec_sub9_function_unit[12:0] + attribute \src "libresoc.v:8883.5-8883.29" + switch \initial + attribute \src "libresoc.v:8883.9-8883.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\DIV_dec31_dec_sub9_function_unit[12:0] 13'0001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\DIV_dec31_dec_sub9_function_unit[12:0] 13'0001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\DIV_dec31_dec_sub9_function_unit[12:0] 13'0001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\DIV_dec31_dec_sub9_function_unit[12:0] 13'0001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\DIV_dec31_dec_sub9_function_unit[12:0] 13'0001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\DIV_dec31_dec_sub9_function_unit[12:0] 13'0001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\DIV_dec31_dec_sub9_function_unit[12:0] 13'0001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\DIV_dec31_dec_sub9_function_unit[12:0] 13'0001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\DIV_dec31_dec_sub9_function_unit[12:0] 13'0001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\DIV_dec31_dec_sub9_function_unit[12:0] 13'0001000000000 + case + assign $1\DIV_dec31_dec_sub9_function_unit[12:0] 13'0000000000000 + end + sync always + update \DIV_dec31_dec_sub9_function_unit $0\DIV_dec31_dec_sub9_function_unit[12:0] + end + attribute \src "libresoc.v:8919.3-8955.6" + process $proc$libresoc.v:8919$182 + assign { } { } + assign { } { } + assign $0\DIV_dec31_dec_sub9_inv_a[0:0] $1\DIV_dec31_dec_sub9_inv_a[0:0] + attribute \src "libresoc.v:8920.5-8920.29" + switch \initial + attribute \src "libresoc.v:8920.9-8920.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\DIV_dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\DIV_dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\DIV_dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\DIV_dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\DIV_dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\DIV_dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\DIV_dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\DIV_dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\DIV_dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\DIV_dec31_dec_sub9_inv_a[0:0] 1'0 + case + assign $1\DIV_dec31_dec_sub9_inv_a[0:0] 1'0 + end + sync always + update \DIV_dec31_dec_sub9_inv_a $0\DIV_dec31_dec_sub9_inv_a[0:0] + end + attribute \src "libresoc.v:8956.3-8992.6" + process $proc$libresoc.v:8956$183 + assign { } { } + assign { } { } + assign $0\DIV_dec31_dec_sub9_inv_out[0:0] $1\DIV_dec31_dec_sub9_inv_out[0:0] + attribute \src "libresoc.v:8957.5-8957.29" + switch \initial + attribute \src "libresoc.v:8957.9-8957.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\DIV_dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\DIV_dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\DIV_dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\DIV_dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\DIV_dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\DIV_dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\DIV_dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\DIV_dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\DIV_dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\DIV_dec31_dec_sub9_inv_out[0:0] 1'0 + case + assign $1\DIV_dec31_dec_sub9_inv_out[0:0] 1'0 + end + sync always + update \DIV_dec31_dec_sub9_inv_out $0\DIV_dec31_dec_sub9_inv_out[0:0] + end + attribute \src "libresoc.v:8993.3-9029.6" + process $proc$libresoc.v:8993$184 + assign { } { } + assign { } { } + assign $0\DIV_dec31_dec_sub9_cry_out[0:0] $1\DIV_dec31_dec_sub9_cry_out[0:0] + attribute \src "libresoc.v:8994.5-8994.29" + switch \initial + attribute \src "libresoc.v:8994.9-8994.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cry_out[0:0] 1'0 + case + assign $1\DIV_dec31_dec_sub9_cry_out[0:0] 1'0 + end + sync always + update \DIV_dec31_dec_sub9_cry_out $0\DIV_dec31_dec_sub9_cry_out[0:0] + end + attribute \src "libresoc.v:9030.3-9066.6" + process $proc$libresoc.v:9030$185 + assign { } { } + assign { } { } + assign $0\DIV_dec31_dec_sub9_is_32b[0:0] $1\DIV_dec31_dec_sub9_is_32b[0:0] + attribute \src "libresoc.v:9031.5-9031.29" + switch \initial + attribute \src "libresoc.v:9031.9-9031.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\DIV_dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\DIV_dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\DIV_dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\DIV_dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\DIV_dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\DIV_dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\DIV_dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\DIV_dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\DIV_dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\DIV_dec31_dec_sub9_is_32b[0:0] 1'0 + case + assign $1\DIV_dec31_dec_sub9_is_32b[0:0] 1'0 + end + sync always + update \DIV_dec31_dec_sub9_is_32b $0\DIV_dec31_dec_sub9_is_32b[0:0] + end + attribute \src "libresoc.v:9067.3-9103.6" + process $proc$libresoc.v:9067$186 + assign { } { } + assign { } { } + assign $0\DIV_dec31_dec_sub9_sgn[0:0] $1\DIV_dec31_dec_sub9_sgn[0:0] + attribute \src "libresoc.v:9068.5-9068.29" + switch \initial + attribute \src "libresoc.v:9068.9-9068.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\DIV_dec31_dec_sub9_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\DIV_dec31_dec_sub9_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\DIV_dec31_dec_sub9_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\DIV_dec31_dec_sub9_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\DIV_dec31_dec_sub9_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\DIV_dec31_dec_sub9_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\DIV_dec31_dec_sub9_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\DIV_dec31_dec_sub9_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\DIV_dec31_dec_sub9_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\DIV_dec31_dec_sub9_sgn[0:0] 1'1 + case + assign $1\DIV_dec31_dec_sub9_sgn[0:0] 1'0 + end + sync always + update \DIV_dec31_dec_sub9_sgn $0\DIV_dec31_dec_sub9_sgn[0:0] + end + attribute \src "libresoc.v:9104.3-9140.6" + process $proc$libresoc.v:9104$187 + assign { } { } + assign { } { } + assign $0\DIV_dec31_dec_sub9_internal_op[6:0] $1\DIV_dec31_dec_sub9_internal_op[6:0] + attribute \src "libresoc.v:9105.5-9105.29" + switch \initial + attribute \src "libresoc.v:9105.9-9105.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\DIV_dec31_dec_sub9_internal_op[6:0] 7'0011110 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\DIV_dec31_dec_sub9_internal_op[6:0] 7'0011110 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\DIV_dec31_dec_sub9_internal_op[6:0] 7'0011110 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\DIV_dec31_dec_sub9_internal_op[6:0] 7'0011110 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\DIV_dec31_dec_sub9_internal_op[6:0] 7'0011101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\DIV_dec31_dec_sub9_internal_op[6:0] 7'0011101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\DIV_dec31_dec_sub9_internal_op[6:0] 7'0011101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\DIV_dec31_dec_sub9_internal_op[6:0] 7'0011101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\DIV_dec31_dec_sub9_internal_op[6:0] 7'0101111 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\DIV_dec31_dec_sub9_internal_op[6:0] 7'0101111 + case + assign $1\DIV_dec31_dec_sub9_internal_op[6:0] 7'0000000 + end + sync always + update \DIV_dec31_dec_sub9_internal_op $0\DIV_dec31_dec_sub9_internal_op[6:0] + end + attribute \src "libresoc.v:9141.3-9177.6" + process $proc$libresoc.v:9141$188 + assign { } { } + assign { } { } + assign $0\DIV_dec31_dec_sub9_in1_sel[2:0] $1\DIV_dec31_dec_sub9_in1_sel[2:0] + attribute \src "libresoc.v:9142.5-9142.29" + switch \initial + attribute \src "libresoc.v:9142.9-9142.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\DIV_dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\DIV_dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\DIV_dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\DIV_dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\DIV_dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\DIV_dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\DIV_dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\DIV_dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\DIV_dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\DIV_dec31_dec_sub9_in1_sel[2:0] 3'001 + case + assign $1\DIV_dec31_dec_sub9_in1_sel[2:0] 3'000 + end + sync always + update \DIV_dec31_dec_sub9_in1_sel $0\DIV_dec31_dec_sub9_in1_sel[2:0] + end + attribute \src "libresoc.v:9178.3-9214.6" + process $proc$libresoc.v:9178$189 + assign { } { } + assign { } { } + assign $0\DIV_dec31_dec_sub9_in2_sel[3:0] $1\DIV_dec31_dec_sub9_in2_sel[3:0] + attribute \src "libresoc.v:9179.5-9179.29" + switch \initial + attribute \src "libresoc.v:9179.9-9179.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\DIV_dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\DIV_dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\DIV_dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\DIV_dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\DIV_dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\DIV_dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\DIV_dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\DIV_dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\DIV_dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\DIV_dec31_dec_sub9_in2_sel[3:0] 4'0001 + case + assign $1\DIV_dec31_dec_sub9_in2_sel[3:0] 4'0000 + end + sync always + update \DIV_dec31_dec_sub9_in2_sel $0\DIV_dec31_dec_sub9_in2_sel[3:0] + end + attribute \src "libresoc.v:9215.3-9251.6" + process $proc$libresoc.v:9215$190 + assign { } { } + assign { } { } + assign $0\DIV_dec31_dec_sub9_cr_in[2:0] $1\DIV_dec31_dec_sub9_cr_in[2:0] + attribute \src "libresoc.v:9216.5-9216.29" + switch \initial + attribute \src "libresoc.v:9216.9-9216.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cr_in[2:0] 3'000 + case + assign $1\DIV_dec31_dec_sub9_cr_in[2:0] 3'000 + end + sync always + update \DIV_dec31_dec_sub9_cr_in $0\DIV_dec31_dec_sub9_cr_in[2:0] + end + attribute \src "libresoc.v:9252.3-9288.6" + process $proc$libresoc.v:9252$191 + assign { } { } + assign { } { } + assign $0\DIV_dec31_dec_sub9_cr_out[2:0] $1\DIV_dec31_dec_sub9_cr_out[2:0] + attribute \src "libresoc.v:9253.5-9253.29" + switch \initial + attribute \src "libresoc.v:9253.9-9253.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cr_out[2:0] 3'000 + case + assign $1\DIV_dec31_dec_sub9_cr_out[2:0] 3'000 + end + sync always + update \DIV_dec31_dec_sub9_cr_out $0\DIV_dec31_dec_sub9_cr_out[2:0] + end + attribute \src "libresoc.v:9289.3-9325.6" + process $proc$libresoc.v:9289$192 + assign { } { } + assign { } { } + assign $0\DIV_dec31_dec_sub9_ldst_len[3:0] $1\DIV_dec31_dec_sub9_ldst_len[3:0] + attribute \src "libresoc.v:9290.5-9290.29" + switch \initial + attribute \src "libresoc.v:9290.9-9290.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\DIV_dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\DIV_dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\DIV_dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\DIV_dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\DIV_dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\DIV_dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\DIV_dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\DIV_dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\DIV_dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\DIV_dec31_dec_sub9_ldst_len[3:0] 4'0000 + case + assign $1\DIV_dec31_dec_sub9_ldst_len[3:0] 4'0000 + end + sync always + update \DIV_dec31_dec_sub9_ldst_len $0\DIV_dec31_dec_sub9_ldst_len[3:0] + end + attribute \src "libresoc.v:9326.3-9362.6" + process $proc$libresoc.v:9326$193 + assign { } { } + assign { } { } + assign $0\DIV_dec31_dec_sub9_rc_sel[1:0] $1\DIV_dec31_dec_sub9_rc_sel[1:0] + attribute \src "libresoc.v:9327.5-9327.29" + switch \initial + attribute \src "libresoc.v:9327.9-9327.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\DIV_dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\DIV_dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\DIV_dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\DIV_dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\DIV_dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\DIV_dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\DIV_dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\DIV_dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\DIV_dec31_dec_sub9_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\DIV_dec31_dec_sub9_rc_sel[1:0] 2'00 + case + assign $1\DIV_dec31_dec_sub9_rc_sel[1:0] 2'00 + end + sync always + update \DIV_dec31_dec_sub9_rc_sel $0\DIV_dec31_dec_sub9_rc_sel[1:0] + end + attribute \src "libresoc.v:9363.3-9399.6" + process $proc$libresoc.v:9363$194 + assign { } { } + assign { } { } + assign $0\DIV_dec31_dec_sub9_cry_in[1:0] $1\DIV_dec31_dec_sub9_cry_in[1:0] + attribute \src "libresoc.v:9364.5-9364.29" + switch \initial + attribute \src "libresoc.v:9364.9-9364.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cry_in[1:0] 2'00 + case + assign $1\DIV_dec31_dec_sub9_cry_in[1:0] 2'00 + end + sync always + update \DIV_dec31_dec_sub9_cry_in $0\DIV_dec31_dec_sub9_cry_in[1:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:9405.1-10581.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec.LDST_dec31" +attribute \generator "nMigen" +module \LDST_dec31 + attribute \src "libresoc.v:10423.3-10441.6" + wire $0\LDST_dec31_br[0:0] + attribute \src "libresoc.v:10328.3-10346.6" + wire width 3 $0\LDST_dec31_cr_in[2:0] + attribute \src "libresoc.v:10347.3-10365.6" + wire width 3 $0\LDST_dec31_cr_out[2:0] + attribute \src "libresoc.v:10499.3-10517.6" + wire width 13 $0\LDST_dec31_function_unit[12:0] + attribute \src "libresoc.v:10537.3-10555.6" + wire width 3 $0\LDST_dec31_in1_sel[2:0] + attribute \src "libresoc.v:10556.3-10574.6" + wire width 4 $0\LDST_dec31_in2_sel[3:0] + attribute \src "libresoc.v:10518.3-10536.6" + wire width 7 $0\LDST_dec31_internal_op[6:0] + attribute \src "libresoc.v:10461.3-10479.6" + wire $0\LDST_dec31_is_32b[0:0] + attribute \src "libresoc.v:10366.3-10384.6" + wire width 4 $0\LDST_dec31_ldst_len[3:0] + attribute \src "libresoc.v:10404.3-10422.6" + wire width 2 $0\LDST_dec31_rc_sel[1:0] + attribute \src "libresoc.v:10480.3-10498.6" + wire $0\LDST_dec31_sgn[0:0] + attribute \src "libresoc.v:10442.3-10460.6" + wire $0\LDST_dec31_sgn_ext[0:0] + attribute \src "libresoc.v:10385.3-10403.6" + wire width 2 $0\LDST_dec31_upd[1:0] + attribute \src "libresoc.v:9406.7-9406.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:10423.3-10441.6" + wire $1\LDST_dec31_br[0:0] + attribute \src "libresoc.v:10328.3-10346.6" + wire width 3 $1\LDST_dec31_cr_in[2:0] + attribute \src "libresoc.v:10347.3-10365.6" + wire width 3 $1\LDST_dec31_cr_out[2:0] + attribute \src "libresoc.v:10499.3-10517.6" + wire width 13 $1\LDST_dec31_function_unit[12:0] + attribute \src "libresoc.v:10537.3-10555.6" + wire width 3 $1\LDST_dec31_in1_sel[2:0] + attribute \src "libresoc.v:10556.3-10574.6" + wire width 4 $1\LDST_dec31_in2_sel[3:0] + attribute \src "libresoc.v:10518.3-10536.6" + wire width 7 $1\LDST_dec31_internal_op[6:0] + attribute \src "libresoc.v:10461.3-10479.6" + wire $1\LDST_dec31_is_32b[0:0] + attribute \src "libresoc.v:10366.3-10384.6" + wire width 4 $1\LDST_dec31_ldst_len[3:0] + attribute \src "libresoc.v:10404.3-10422.6" + wire width 2 $1\LDST_dec31_rc_sel[1:0] + attribute \src "libresoc.v:10480.3-10498.6" + wire $1\LDST_dec31_sgn[0:0] + attribute \src "libresoc.v:10442.3-10460.6" + wire $1\LDST_dec31_sgn_ext[0:0] + attribute \src "libresoc.v:10385.3-10403.6" + wire width 2 $1\LDST_dec31_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 10 \LDST_dec31_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 5 \LDST_dec31_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 6 \LDST_dec31_cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 13 \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute 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"OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute 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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + wire width 32 \LDST_dec31_dec_sub23_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" 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"OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute 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attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 7 \LDST_dec31_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 9 \LDST_dec31_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 13 \LDST_dec31_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 11 \LDST_dec31_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src 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\LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_function_unit + connect \LDST_dec31_dec_sub20_in1_sel \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_in1_sel + connect \LDST_dec31_dec_sub20_in2_sel \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_in2_sel + connect \LDST_dec31_dec_sub20_internal_op \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_internal_op + connect \LDST_dec31_dec_sub20_is_32b \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_is_32b + connect \LDST_dec31_dec_sub20_ldst_len \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_ldst_len + connect \LDST_dec31_dec_sub20_rc_sel \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_rc_sel + connect \LDST_dec31_dec_sub20_sgn \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_sgn + connect \LDST_dec31_dec_sub20_sgn_ext \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_sgn_ext + connect \LDST_dec31_dec_sub20_upd \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_upd + connect \opcode_in \LDST_dec31_dec_sub20_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:10280.24-10295.4" + cell \LDST_dec31_dec_sub21 \LDST_dec31_dec_sub21 + connect \LDST_dec31_dec_sub21_br \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_br + connect \LDST_dec31_dec_sub21_cr_in \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_cr_in + connect \LDST_dec31_dec_sub21_cr_out \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_cr_out + connect \LDST_dec31_dec_sub21_function_unit \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_function_unit + connect \LDST_dec31_dec_sub21_in1_sel \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_in1_sel + connect \LDST_dec31_dec_sub21_in2_sel \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_in2_sel + connect \LDST_dec31_dec_sub21_internal_op \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_internal_op + connect \LDST_dec31_dec_sub21_is_32b \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_is_32b + connect \LDST_dec31_dec_sub21_ldst_len \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_ldst_len + connect \LDST_dec31_dec_sub21_rc_sel \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_rc_sel + connect \LDST_dec31_dec_sub21_sgn \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_sgn + connect \LDST_dec31_dec_sub21_sgn_ext \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_sgn_ext + connect \LDST_dec31_dec_sub21_upd \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_upd + connect \opcode_in \LDST_dec31_dec_sub21_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:10296.24-10311.4" + cell \LDST_dec31_dec_sub22 \LDST_dec31_dec_sub22 + connect \LDST_dec31_dec_sub22_br \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_br + connect \LDST_dec31_dec_sub22_cr_in \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_cr_in + connect \LDST_dec31_dec_sub22_cr_out \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_cr_out + connect \LDST_dec31_dec_sub22_function_unit \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_function_unit + connect \LDST_dec31_dec_sub22_in1_sel \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_in1_sel + connect \LDST_dec31_dec_sub22_in2_sel \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_in2_sel + connect \LDST_dec31_dec_sub22_internal_op \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_internal_op + connect \LDST_dec31_dec_sub22_is_32b \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_is_32b + connect \LDST_dec31_dec_sub22_ldst_len \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_ldst_len + connect \LDST_dec31_dec_sub22_rc_sel \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_rc_sel + connect \LDST_dec31_dec_sub22_sgn \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_sgn + connect \LDST_dec31_dec_sub22_sgn_ext \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_sgn_ext + connect \LDST_dec31_dec_sub22_upd \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_upd + connect \opcode_in \LDST_dec31_dec_sub22_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:10312.24-10327.4" + cell \LDST_dec31_dec_sub23 \LDST_dec31_dec_sub23 + connect \LDST_dec31_dec_sub23_br \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_br + connect \LDST_dec31_dec_sub23_cr_in \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_cr_in + connect \LDST_dec31_dec_sub23_cr_out \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_cr_out + connect \LDST_dec31_dec_sub23_function_unit \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_function_unit + connect \LDST_dec31_dec_sub23_in1_sel \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_in1_sel + connect \LDST_dec31_dec_sub23_in2_sel \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_in2_sel + connect \LDST_dec31_dec_sub23_internal_op \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_internal_op + connect \LDST_dec31_dec_sub23_is_32b \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_is_32b + connect \LDST_dec31_dec_sub23_ldst_len \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_ldst_len + connect \LDST_dec31_dec_sub23_rc_sel \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_rc_sel + connect \LDST_dec31_dec_sub23_sgn \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_sgn + connect \LDST_dec31_dec_sub23_sgn_ext \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_sgn_ext + connect \LDST_dec31_dec_sub23_upd \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_upd + connect \opcode_in \LDST_dec31_dec_sub23_opcode_in + end + attribute \src "libresoc.v:10328.3-10346.6" + process $proc$libresoc.v:10328$196 + assign { } { } + assign { } { } + assign $0\LDST_dec31_cr_in[2:0] $1\LDST_dec31_cr_in[2:0] + attribute \src "libresoc.v:10329.5-10329.29" + switch \initial + attribute \src "libresoc.v:10329.9-10329.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\LDST_dec31_cr_in[2:0] \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_cr_in[2:0] \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\LDST_dec31_cr_in[2:0] \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\LDST_dec31_cr_in[2:0] \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_cr_in + case + assign $1\LDST_dec31_cr_in[2:0] 3'000 + end + sync always + update \LDST_dec31_cr_in $0\LDST_dec31_cr_in[2:0] + end + attribute \src "libresoc.v:10347.3-10365.6" + process $proc$libresoc.v:10347$197 + assign { } { } + assign { } { } + assign $0\LDST_dec31_cr_out[2:0] $1\LDST_dec31_cr_out[2:0] + attribute \src "libresoc.v:10348.5-10348.29" + switch \initial + attribute \src "libresoc.v:10348.9-10348.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\LDST_dec31_cr_out[2:0] \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_cr_out[2:0] \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\LDST_dec31_cr_out[2:0] \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\LDST_dec31_cr_out[2:0] \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_cr_out + case + assign $1\LDST_dec31_cr_out[2:0] 3'000 + end + sync always + update \LDST_dec31_cr_out $0\LDST_dec31_cr_out[2:0] + end + attribute \src "libresoc.v:10366.3-10384.6" + process $proc$libresoc.v:10366$198 + assign { } { } + assign { } { } + assign $0\LDST_dec31_ldst_len[3:0] $1\LDST_dec31_ldst_len[3:0] + attribute \src "libresoc.v:10367.5-10367.29" + switch \initial + attribute \src "libresoc.v:10367.9-10367.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\LDST_dec31_ldst_len[3:0] \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_ldst_len[3:0] \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\LDST_dec31_ldst_len[3:0] \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\LDST_dec31_ldst_len[3:0] \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_ldst_len + case + assign $1\LDST_dec31_ldst_len[3:0] 4'0000 + end + sync always + update \LDST_dec31_ldst_len $0\LDST_dec31_ldst_len[3:0] + end + attribute \src "libresoc.v:10385.3-10403.6" + process $proc$libresoc.v:10385$199 + assign { } { } + assign { } { } + assign $0\LDST_dec31_upd[1:0] $1\LDST_dec31_upd[1:0] + attribute \src "libresoc.v:10386.5-10386.29" + switch \initial + attribute \src "libresoc.v:10386.9-10386.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\LDST_dec31_upd[1:0] \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_upd[1:0] \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\LDST_dec31_upd[1:0] \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\LDST_dec31_upd[1:0] \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_upd + case + assign $1\LDST_dec31_upd[1:0] 2'00 + end + sync always + update \LDST_dec31_upd $0\LDST_dec31_upd[1:0] + end + attribute \src "libresoc.v:10404.3-10422.6" + process $proc$libresoc.v:10404$200 + assign { } { } + assign { } { } + assign $0\LDST_dec31_rc_sel[1:0] $1\LDST_dec31_rc_sel[1:0] + attribute \src "libresoc.v:10405.5-10405.29" + switch \initial + attribute \src "libresoc.v:10405.9-10405.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\LDST_dec31_rc_sel[1:0] \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_rc_sel[1:0] \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\LDST_dec31_rc_sel[1:0] \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\LDST_dec31_rc_sel[1:0] \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_rc_sel + case + assign $1\LDST_dec31_rc_sel[1:0] 2'00 + end + sync always + update \LDST_dec31_rc_sel $0\LDST_dec31_rc_sel[1:0] + end + attribute \src "libresoc.v:10423.3-10441.6" + process $proc$libresoc.v:10423$201 + assign { } { } + assign { } { } + assign $0\LDST_dec31_br[0:0] $1\LDST_dec31_br[0:0] + attribute \src "libresoc.v:10424.5-10424.29" + switch \initial + attribute \src "libresoc.v:10424.9-10424.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\LDST_dec31_br[0:0] \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_br + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_br[0:0] \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_br + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\LDST_dec31_br[0:0] \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_br + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\LDST_dec31_br[0:0] \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_br + case + assign $1\LDST_dec31_br[0:0] 1'0 + end + sync always + update \LDST_dec31_br $0\LDST_dec31_br[0:0] + end + attribute \src "libresoc.v:10442.3-10460.6" + process $proc$libresoc.v:10442$202 + assign { } { } + assign { } { } + assign $0\LDST_dec31_sgn_ext[0:0] $1\LDST_dec31_sgn_ext[0:0] + attribute \src "libresoc.v:10443.5-10443.29" + switch \initial + attribute \src "libresoc.v:10443.9-10443.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\LDST_dec31_sgn_ext[0:0] \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_sgn_ext[0:0] \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\LDST_dec31_sgn_ext[0:0] \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\LDST_dec31_sgn_ext[0:0] \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_sgn_ext + case + assign $1\LDST_dec31_sgn_ext[0:0] 1'0 + end + sync always + update \LDST_dec31_sgn_ext $0\LDST_dec31_sgn_ext[0:0] + end + attribute \src "libresoc.v:10461.3-10479.6" + process $proc$libresoc.v:10461$203 + assign { } { } + assign { } { } + assign $0\LDST_dec31_is_32b[0:0] $1\LDST_dec31_is_32b[0:0] + attribute \src "libresoc.v:10462.5-10462.29" + switch \initial + attribute \src "libresoc.v:10462.9-10462.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\LDST_dec31_is_32b[0:0] \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_is_32b[0:0] \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\LDST_dec31_is_32b[0:0] \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\LDST_dec31_is_32b[0:0] \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_is_32b + case + assign $1\LDST_dec31_is_32b[0:0] 1'0 + end + sync always + update \LDST_dec31_is_32b $0\LDST_dec31_is_32b[0:0] + end + attribute \src "libresoc.v:10480.3-10498.6" + process $proc$libresoc.v:10480$204 + assign { } { } + assign { } { } + assign $0\LDST_dec31_sgn[0:0] $1\LDST_dec31_sgn[0:0] + attribute \src "libresoc.v:10481.5-10481.29" + switch \initial + attribute \src "libresoc.v:10481.9-10481.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\LDST_dec31_sgn[0:0] \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_sgn[0:0] \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\LDST_dec31_sgn[0:0] \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\LDST_dec31_sgn[0:0] \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_sgn + case + assign $1\LDST_dec31_sgn[0:0] 1'0 + end + sync always + update \LDST_dec31_sgn $0\LDST_dec31_sgn[0:0] + end + attribute \src "libresoc.v:10499.3-10517.6" + process $proc$libresoc.v:10499$205 + assign { } { } + assign { } { } + assign $0\LDST_dec31_function_unit[12:0] $1\LDST_dec31_function_unit[12:0] + attribute \src "libresoc.v:10500.5-10500.29" + switch \initial + attribute \src "libresoc.v:10500.9-10500.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\LDST_dec31_function_unit[12:0] \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_function_unit[12:0] \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\LDST_dec31_function_unit[12:0] \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\LDST_dec31_function_unit[12:0] \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_function_unit + case + assign $1\LDST_dec31_function_unit[12:0] 13'0000000000000 + end + sync always + update \LDST_dec31_function_unit $0\LDST_dec31_function_unit[12:0] + end + attribute \src "libresoc.v:10518.3-10536.6" + process $proc$libresoc.v:10518$206 + assign { } { } + assign { } { } + assign $0\LDST_dec31_internal_op[6:0] $1\LDST_dec31_internal_op[6:0] + attribute \src "libresoc.v:10519.5-10519.29" + switch \initial + attribute \src "libresoc.v:10519.9-10519.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\LDST_dec31_internal_op[6:0] \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_internal_op[6:0] \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\LDST_dec31_internal_op[6:0] \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\LDST_dec31_internal_op[6:0] \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_internal_op + case + assign $1\LDST_dec31_internal_op[6:0] 7'0000000 + end + sync always + update \LDST_dec31_internal_op $0\LDST_dec31_internal_op[6:0] + end + attribute \src "libresoc.v:10537.3-10555.6" + process $proc$libresoc.v:10537$207 + assign { } { } + assign { } { } + assign $0\LDST_dec31_in1_sel[2:0] $1\LDST_dec31_in1_sel[2:0] + attribute \src "libresoc.v:10538.5-10538.29" + switch \initial + attribute \src "libresoc.v:10538.9-10538.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\LDST_dec31_in1_sel[2:0] \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_in1_sel[2:0] \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\LDST_dec31_in1_sel[2:0] \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\LDST_dec31_in1_sel[2:0] \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_in1_sel + case + assign $1\LDST_dec31_in1_sel[2:0] 3'000 + end + sync always + update \LDST_dec31_in1_sel $0\LDST_dec31_in1_sel[2:0] + end + attribute \src "libresoc.v:10556.3-10574.6" + process $proc$libresoc.v:10556$208 + assign { } { } + assign { } { } + assign $0\LDST_dec31_in2_sel[3:0] $1\LDST_dec31_in2_sel[3:0] + attribute \src "libresoc.v:10557.5-10557.29" + switch \initial + attribute \src "libresoc.v:10557.9-10557.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\LDST_dec31_in2_sel[3:0] \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_in2_sel[3:0] \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\LDST_dec31_in2_sel[3:0] \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\LDST_dec31_in2_sel[3:0] \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_in2_sel + case + assign $1\LDST_dec31_in2_sel[3:0] 4'0000 + end + sync always + update \LDST_dec31_in2_sel $0\LDST_dec31_in2_sel[3:0] + end + attribute \src "libresoc.v:9406.7-9406.20" + process $proc$libresoc.v:9406$209 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + connect \LDST_dec31_dec_sub23_opcode_in \opcode_in + connect \LDST_dec31_dec_sub21_opcode_in \opcode_in + connect \LDST_dec31_dec_sub20_opcode_in \opcode_in + connect \LDST_dec31_dec_sub22_opcode_in \opcode_in + connect \opc_in \opcode_switch [4:0] + connect \opcode_switch \opcode_in [10:1] +end +attribute \src "libresoc.v:10585.1-11096.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec.LDST_dec31.LDST_dec31_dec_sub20" +attribute \generator "nMigen" +module \LDST_dec31_dec_sub20 + attribute \src "libresoc.v:10795.3-10819.6" + wire $0\LDST_dec31_dec_sub20_br[0:0] + attribute \src "libresoc.v:10970.3-10994.6" + wire width 3 $0\LDST_dec31_dec_sub20_cr_in[2:0] + attribute \src "libresoc.v:10995.3-11019.6" + wire width 3 $0\LDST_dec31_dec_sub20_cr_out[2:0] + attribute \src "libresoc.v:10770.3-10794.6" + wire width 13 $0\LDST_dec31_dec_sub20_function_unit[12:0] + attribute \src "libresoc.v:10920.3-10944.6" + wire width 3 $0\LDST_dec31_dec_sub20_in1_sel[2:0] + attribute \src "libresoc.v:10945.3-10969.6" + wire width 4 $0\LDST_dec31_dec_sub20_in2_sel[3:0] + attribute \src "libresoc.v:10895.3-10919.6" + wire width 7 $0\LDST_dec31_dec_sub20_internal_op[6:0] + attribute \src "libresoc.v:10845.3-10869.6" + wire $0\LDST_dec31_dec_sub20_is_32b[0:0] + attribute \src "libresoc.v:11020.3-11044.6" + wire width 4 $0\LDST_dec31_dec_sub20_ldst_len[3:0] + attribute \src "libresoc.v:11070.3-11094.6" + wire width 2 $0\LDST_dec31_dec_sub20_rc_sel[1:0] + attribute \src "libresoc.v:10870.3-10894.6" + wire $0\LDST_dec31_dec_sub20_sgn[0:0] + attribute \src "libresoc.v:10820.3-10844.6" + wire $0\LDST_dec31_dec_sub20_sgn_ext[0:0] + attribute \src "libresoc.v:11045.3-11069.6" + wire width 2 $0\LDST_dec31_dec_sub20_upd[1:0] + attribute \src "libresoc.v:10586.7-10586.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:10795.3-10819.6" + wire $1\LDST_dec31_dec_sub20_br[0:0] + attribute \src "libresoc.v:10970.3-10994.6" + wire width 3 $1\LDST_dec31_dec_sub20_cr_in[2:0] + attribute \src "libresoc.v:10995.3-11019.6" + wire width 3 $1\LDST_dec31_dec_sub20_cr_out[2:0] + attribute \src "libresoc.v:10770.3-10794.6" + wire width 13 $1\LDST_dec31_dec_sub20_function_unit[12:0] + attribute \src "libresoc.v:10920.3-10944.6" + wire width 3 $1\LDST_dec31_dec_sub20_in1_sel[2:0] + attribute \src "libresoc.v:10945.3-10969.6" + wire width 4 $1\LDST_dec31_dec_sub20_in2_sel[3:0] + attribute \src "libresoc.v:10895.3-10919.6" + wire width 7 $1\LDST_dec31_dec_sub20_internal_op[6:0] + attribute \src "libresoc.v:10845.3-10869.6" + wire $1\LDST_dec31_dec_sub20_is_32b[0:0] + attribute \src "libresoc.v:11020.3-11044.6" + wire width 4 $1\LDST_dec31_dec_sub20_ldst_len[3:0] + attribute \src "libresoc.v:11070.3-11094.6" + wire width 2 $1\LDST_dec31_dec_sub20_rc_sel[1:0] + attribute \src "libresoc.v:10870.3-10894.6" + wire $1\LDST_dec31_dec_sub20_sgn[0:0] + attribute \src "libresoc.v:10820.3-10844.6" + wire $1\LDST_dec31_dec_sub20_sgn_ext[0:0] + attribute \src "libresoc.v:11045.3-11069.6" + wire width 2 $1\LDST_dec31_dec_sub20_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 10 \LDST_dec31_dec_sub20_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 5 \LDST_dec31_dec_sub20_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 6 \LDST_dec31_dec_sub20_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 13 output 1 \LDST_dec31_dec_sub20_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 3 \LDST_dec31_dec_sub20_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 4 \LDST_dec31_dec_sub20_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 output 2 \LDST_dec31_dec_sub20_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 12 \LDST_dec31_dec_sub20_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 7 \LDST_dec31_dec_sub20_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 9 \LDST_dec31_dec_sub20_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 13 \LDST_dec31_dec_sub20_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 11 \LDST_dec31_dec_sub20_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 8 \LDST_dec31_dec_sub20_upd + attribute \src "libresoc.v:10586.7-10586.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + wire width 32 input 14 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + wire width 5 \opcode_switch + attribute \src "libresoc.v:10586.7-10586.20" + process $proc$libresoc.v:10586$223 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:10770.3-10794.6" + process $proc$libresoc.v:10770$210 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub20_function_unit[12:0] $1\LDST_dec31_dec_sub20_function_unit[12:0] + attribute \src "libresoc.v:10771.5-10771.29" + switch \initial + attribute \src "libresoc.v:10771.9-10771.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub20_function_unit[12:0] 13'0000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\LDST_dec31_dec_sub20_function_unit[12:0] 13'0000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LDST_dec31_dec_sub20_function_unit[12:0] 13'0000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LDST_dec31_dec_sub20_function_unit[12:0] 13'0000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub20_function_unit[12:0] 13'0000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_dec_sub20_function_unit[12:0] 13'0000000000100 + case + assign $1\LDST_dec31_dec_sub20_function_unit[12:0] 13'0000000000000 + end + sync always + update \LDST_dec31_dec_sub20_function_unit $0\LDST_dec31_dec_sub20_function_unit[12:0] + end + attribute \src "libresoc.v:10795.3-10819.6" + process $proc$libresoc.v:10795$211 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub20_br[0:0] $1\LDST_dec31_dec_sub20_br[0:0] + attribute \src "libresoc.v:10796.5-10796.29" + switch \initial + attribute \src "libresoc.v:10796.9-10796.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub20_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\LDST_dec31_dec_sub20_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LDST_dec31_dec_sub20_br[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LDST_dec31_dec_sub20_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub20_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_dec_sub20_br[0:0] 1'1 + case + assign $1\LDST_dec31_dec_sub20_br[0:0] 1'0 + end + sync always + update \LDST_dec31_dec_sub20_br $0\LDST_dec31_dec_sub20_br[0:0] + end + attribute \src "libresoc.v:10820.3-10844.6" + process $proc$libresoc.v:10820$212 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub20_sgn_ext[0:0] $1\LDST_dec31_dec_sub20_sgn_ext[0:0] + attribute \src "libresoc.v:10821.5-10821.29" + switch \initial + attribute \src "libresoc.v:10821.9-10821.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub20_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\LDST_dec31_dec_sub20_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LDST_dec31_dec_sub20_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LDST_dec31_dec_sub20_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub20_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_dec_sub20_sgn_ext[0:0] 1'0 + case + assign $1\LDST_dec31_dec_sub20_sgn_ext[0:0] 1'0 + end + sync always + update \LDST_dec31_dec_sub20_sgn_ext $0\LDST_dec31_dec_sub20_sgn_ext[0:0] + end + attribute \src "libresoc.v:10845.3-10869.6" + process $proc$libresoc.v:10845$213 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub20_is_32b[0:0] $1\LDST_dec31_dec_sub20_is_32b[0:0] + attribute \src "libresoc.v:10846.5-10846.29" + switch \initial + attribute \src "libresoc.v:10846.9-10846.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub20_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\LDST_dec31_dec_sub20_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LDST_dec31_dec_sub20_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LDST_dec31_dec_sub20_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub20_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_dec_sub20_is_32b[0:0] 1'0 + case + assign $1\LDST_dec31_dec_sub20_is_32b[0:0] 1'0 + end + sync always + update \LDST_dec31_dec_sub20_is_32b $0\LDST_dec31_dec_sub20_is_32b[0:0] + end + attribute \src "libresoc.v:10870.3-10894.6" + process $proc$libresoc.v:10870$214 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub20_sgn[0:0] $1\LDST_dec31_dec_sub20_sgn[0:0] + attribute \src "libresoc.v:10871.5-10871.29" + switch \initial + attribute \src "libresoc.v:10871.9-10871.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub20_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\LDST_dec31_dec_sub20_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LDST_dec31_dec_sub20_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LDST_dec31_dec_sub20_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub20_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_dec_sub20_sgn[0:0] 1'0 + case + assign $1\LDST_dec31_dec_sub20_sgn[0:0] 1'0 + end + sync always + update \LDST_dec31_dec_sub20_sgn $0\LDST_dec31_dec_sub20_sgn[0:0] + end + attribute \src "libresoc.v:10895.3-10919.6" + process $proc$libresoc.v:10895$215 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub20_internal_op[6:0] $1\LDST_dec31_dec_sub20_internal_op[6:0] + attribute \src "libresoc.v:10896.5-10896.29" + switch \initial + attribute \src "libresoc.v:10896.9-10896.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub20_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\LDST_dec31_dec_sub20_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LDST_dec31_dec_sub20_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LDST_dec31_dec_sub20_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub20_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_dec_sub20_internal_op[6:0] 7'0100110 + case + assign $1\LDST_dec31_dec_sub20_internal_op[6:0] 7'0000000 + end + sync always + update \LDST_dec31_dec_sub20_internal_op $0\LDST_dec31_dec_sub20_internal_op[6:0] + end + attribute \src "libresoc.v:10920.3-10944.6" + process $proc$libresoc.v:10920$216 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub20_in1_sel[2:0] $1\LDST_dec31_dec_sub20_in1_sel[2:0] + attribute \src "libresoc.v:10921.5-10921.29" + switch \initial + attribute \src "libresoc.v:10921.9-10921.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub20_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\LDST_dec31_dec_sub20_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LDST_dec31_dec_sub20_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LDST_dec31_dec_sub20_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub20_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_dec_sub20_in1_sel[2:0] 3'010 + case + assign $1\LDST_dec31_dec_sub20_in1_sel[2:0] 3'000 + end + sync always + update \LDST_dec31_dec_sub20_in1_sel $0\LDST_dec31_dec_sub20_in1_sel[2:0] + end + attribute \src "libresoc.v:10945.3-10969.6" + process $proc$libresoc.v:10945$217 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub20_in2_sel[3:0] $1\LDST_dec31_dec_sub20_in2_sel[3:0] + attribute \src "libresoc.v:10946.5-10946.29" + switch \initial + attribute \src "libresoc.v:10946.9-10946.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub20_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\LDST_dec31_dec_sub20_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LDST_dec31_dec_sub20_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LDST_dec31_dec_sub20_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub20_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_dec_sub20_in2_sel[3:0] 4'0001 + case + assign $1\LDST_dec31_dec_sub20_in2_sel[3:0] 4'0000 + end + sync always + update \LDST_dec31_dec_sub20_in2_sel $0\LDST_dec31_dec_sub20_in2_sel[3:0] + end + attribute \src "libresoc.v:10970.3-10994.6" + process $proc$libresoc.v:10970$218 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub20_cr_in[2:0] $1\LDST_dec31_dec_sub20_cr_in[2:0] + attribute \src "libresoc.v:10971.5-10971.29" + switch \initial + attribute \src "libresoc.v:10971.9-10971.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub20_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\LDST_dec31_dec_sub20_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LDST_dec31_dec_sub20_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LDST_dec31_dec_sub20_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub20_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_dec_sub20_cr_in[2:0] 3'000 + case + assign $1\LDST_dec31_dec_sub20_cr_in[2:0] 3'000 + end + sync always + update \LDST_dec31_dec_sub20_cr_in $0\LDST_dec31_dec_sub20_cr_in[2:0] + end + attribute \src "libresoc.v:10995.3-11019.6" + process $proc$libresoc.v:10995$219 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub20_cr_out[2:0] $1\LDST_dec31_dec_sub20_cr_out[2:0] + attribute \src "libresoc.v:10996.5-10996.29" + switch \initial + attribute \src "libresoc.v:10996.9-10996.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub20_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\LDST_dec31_dec_sub20_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LDST_dec31_dec_sub20_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LDST_dec31_dec_sub20_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub20_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_dec_sub20_cr_out[2:0] 3'000 + case + assign $1\LDST_dec31_dec_sub20_cr_out[2:0] 3'000 + end + sync always + update \LDST_dec31_dec_sub20_cr_out $0\LDST_dec31_dec_sub20_cr_out[2:0] + end + attribute \src "libresoc.v:11020.3-11044.6" + process $proc$libresoc.v:11020$220 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub20_ldst_len[3:0] $1\LDST_dec31_dec_sub20_ldst_len[3:0] + attribute \src "libresoc.v:11021.5-11021.29" + switch \initial + attribute \src "libresoc.v:11021.9-11021.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub20_ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\LDST_dec31_dec_sub20_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LDST_dec31_dec_sub20_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LDST_dec31_dec_sub20_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub20_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_dec_sub20_ldst_len[3:0] 4'1000 + case + assign $1\LDST_dec31_dec_sub20_ldst_len[3:0] 4'0000 + end + sync always + update \LDST_dec31_dec_sub20_ldst_len $0\LDST_dec31_dec_sub20_ldst_len[3:0] + end + attribute \src "libresoc.v:11045.3-11069.6" + process $proc$libresoc.v:11045$221 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub20_upd[1:0] $1\LDST_dec31_dec_sub20_upd[1:0] + attribute \src "libresoc.v:11046.5-11046.29" + switch \initial + attribute \src "libresoc.v:11046.9-11046.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub20_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\LDST_dec31_dec_sub20_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LDST_dec31_dec_sub20_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LDST_dec31_dec_sub20_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub20_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_dec_sub20_upd[1:0] 2'00 + case + assign $1\LDST_dec31_dec_sub20_upd[1:0] 2'00 + end + sync always + update \LDST_dec31_dec_sub20_upd $0\LDST_dec31_dec_sub20_upd[1:0] + end + attribute \src "libresoc.v:11070.3-11094.6" + process $proc$libresoc.v:11070$222 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub20_rc_sel[1:0] $1\LDST_dec31_dec_sub20_rc_sel[1:0] + attribute \src "libresoc.v:11071.5-11071.29" + switch \initial + attribute \src "libresoc.v:11071.9-11071.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub20_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\LDST_dec31_dec_sub20_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LDST_dec31_dec_sub20_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LDST_dec31_dec_sub20_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub20_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_dec_sub20_rc_sel[1:0] 2'00 + case + assign $1\LDST_dec31_dec_sub20_rc_sel[1:0] 2'00 + end + sync always + update \LDST_dec31_dec_sub20_rc_sel $0\LDST_dec31_dec_sub20_rc_sel[1:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:11100.1-11923.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec.LDST_dec31.LDST_dec31_dec_sub21" +attribute \generator "nMigen" +module \LDST_dec31_dec_sub21 + attribute \src "libresoc.v:11334.3-11382.6" + wire $0\LDST_dec31_dec_sub21_br[0:0] + attribute \src "libresoc.v:11677.3-11725.6" + wire width 3 $0\LDST_dec31_dec_sub21_cr_in[2:0] + attribute \src "libresoc.v:11726.3-11774.6" + wire width 3 $0\LDST_dec31_dec_sub21_cr_out[2:0] + attribute \src "libresoc.v:11285.3-11333.6" + wire width 13 $0\LDST_dec31_dec_sub21_function_unit[12:0] + attribute \src "libresoc.v:11579.3-11627.6" + wire width 3 $0\LDST_dec31_dec_sub21_in1_sel[2:0] + attribute \src "libresoc.v:11628.3-11676.6" + wire width 4 $0\LDST_dec31_dec_sub21_in2_sel[3:0] + attribute \src "libresoc.v:11530.3-11578.6" + wire width 7 $0\LDST_dec31_dec_sub21_internal_op[6:0] + attribute \src "libresoc.v:11432.3-11480.6" + wire $0\LDST_dec31_dec_sub21_is_32b[0:0] + attribute \src "libresoc.v:11775.3-11823.6" + wire width 4 $0\LDST_dec31_dec_sub21_ldst_len[3:0] + attribute \src "libresoc.v:11873.3-11921.6" + wire width 2 $0\LDST_dec31_dec_sub21_rc_sel[1:0] + attribute \src "libresoc.v:11481.3-11529.6" + wire $0\LDST_dec31_dec_sub21_sgn[0:0] + attribute \src "libresoc.v:11383.3-11431.6" + wire $0\LDST_dec31_dec_sub21_sgn_ext[0:0] + attribute \src "libresoc.v:11824.3-11872.6" + wire width 2 $0\LDST_dec31_dec_sub21_upd[1:0] + attribute \src "libresoc.v:11101.7-11101.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:11334.3-11382.6" + wire $1\LDST_dec31_dec_sub21_br[0:0] + attribute \src "libresoc.v:11677.3-11725.6" + wire width 3 $1\LDST_dec31_dec_sub21_cr_in[2:0] + attribute \src "libresoc.v:11726.3-11774.6" + wire width 3 $1\LDST_dec31_dec_sub21_cr_out[2:0] + attribute \src "libresoc.v:11285.3-11333.6" + wire width 13 $1\LDST_dec31_dec_sub21_function_unit[12:0] + attribute \src "libresoc.v:11579.3-11627.6" + wire width 3 $1\LDST_dec31_dec_sub21_in1_sel[2:0] + attribute \src "libresoc.v:11628.3-11676.6" + wire width 4 $1\LDST_dec31_dec_sub21_in2_sel[3:0] + attribute \src "libresoc.v:11530.3-11578.6" + wire width 7 $1\LDST_dec31_dec_sub21_internal_op[6:0] + attribute \src "libresoc.v:11432.3-11480.6" + wire $1\LDST_dec31_dec_sub21_is_32b[0:0] + attribute \src "libresoc.v:11775.3-11823.6" + wire width 4 $1\LDST_dec31_dec_sub21_ldst_len[3:0] + attribute \src "libresoc.v:11873.3-11921.6" + wire width 2 $1\LDST_dec31_dec_sub21_rc_sel[1:0] + attribute \src "libresoc.v:11481.3-11529.6" + wire $1\LDST_dec31_dec_sub21_sgn[0:0] + attribute \src "libresoc.v:11383.3-11431.6" + wire $1\LDST_dec31_dec_sub21_sgn_ext[0:0] + attribute \src "libresoc.v:11824.3-11872.6" + wire width 2 $1\LDST_dec31_dec_sub21_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 10 \LDST_dec31_dec_sub21_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 5 \LDST_dec31_dec_sub21_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 6 \LDST_dec31_dec_sub21_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 13 output 1 \LDST_dec31_dec_sub21_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 3 \LDST_dec31_dec_sub21_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 4 \LDST_dec31_dec_sub21_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 output 2 \LDST_dec31_dec_sub21_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 12 \LDST_dec31_dec_sub21_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 7 \LDST_dec31_dec_sub21_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 9 \LDST_dec31_dec_sub21_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 13 \LDST_dec31_dec_sub21_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 11 \LDST_dec31_dec_sub21_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 8 \LDST_dec31_dec_sub21_upd + attribute \src "libresoc.v:11101.7-11101.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + wire width 32 input 14 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + wire width 5 \opcode_switch + attribute \src "libresoc.v:11101.7-11101.20" + process $proc$libresoc.v:11101$237 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:11285.3-11333.6" + process $proc$libresoc.v:11285$224 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub21_function_unit[12:0] $1\LDST_dec31_dec_sub21_function_unit[12:0] + attribute \src "libresoc.v:11286.5-11286.29" + switch \initial + attribute \src "libresoc.v:11286.9-11286.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\LDST_dec31_dec_sub21_function_unit[12:0] 13'0000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\LDST_dec31_dec_sub21_function_unit[12:0] 13'0000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub21_function_unit[12:0] 13'0000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub21_function_unit[12:0] 13'0000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\LDST_dec31_dec_sub21_function_unit[12:0] 13'0000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LDST_dec31_dec_sub21_function_unit[12:0] 13'0000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\LDST_dec31_dec_sub21_function_unit[12:0] 13'0000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\LDST_dec31_dec_sub21_function_unit[12:0] 13'0000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\LDST_dec31_dec_sub21_function_unit[12:0] 13'0000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\LDST_dec31_dec_sub21_function_unit[12:0] 13'0000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LDST_dec31_dec_sub21_function_unit[12:0] 13'0000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub21_function_unit[12:0] 13'0000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\LDST_dec31_dec_sub21_function_unit[12:0] 13'0000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LDST_dec31_dec_sub21_function_unit[12:0] 13'0000000000100 + case + assign $1\LDST_dec31_dec_sub21_function_unit[12:0] 13'0000000000000 + end + sync always + update \LDST_dec31_dec_sub21_function_unit $0\LDST_dec31_dec_sub21_function_unit[12:0] + end + attribute \src "libresoc.v:11334.3-11382.6" + process $proc$libresoc.v:11334$225 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub21_br[0:0] $1\LDST_dec31_dec_sub21_br[0:0] + attribute \src "libresoc.v:11335.5-11335.29" + switch \initial + attribute \src "libresoc.v:11335.9-11335.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\LDST_dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\LDST_dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\LDST_dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LDST_dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\LDST_dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\LDST_dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\LDST_dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\LDST_dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LDST_dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\LDST_dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LDST_dec31_dec_sub21_br[0:0] 1'0 + case + assign $1\LDST_dec31_dec_sub21_br[0:0] 1'0 + end + sync always + update \LDST_dec31_dec_sub21_br $0\LDST_dec31_dec_sub21_br[0:0] + end + attribute \src "libresoc.v:11383.3-11431.6" + process $proc$libresoc.v:11383$226 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub21_sgn_ext[0:0] $1\LDST_dec31_dec_sub21_sgn_ext[0:0] + attribute \src "libresoc.v:11384.5-11384.29" + switch \initial + attribute \src "libresoc.v:11384.9-11384.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\LDST_dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\LDST_dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\LDST_dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LDST_dec31_dec_sub21_sgn_ext[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\LDST_dec31_dec_sub21_sgn_ext[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\LDST_dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\LDST_dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\LDST_dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LDST_dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\LDST_dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LDST_dec31_dec_sub21_sgn_ext[0:0] 1'0 + case + assign $1\LDST_dec31_dec_sub21_sgn_ext[0:0] 1'0 + end + sync always + update \LDST_dec31_dec_sub21_sgn_ext $0\LDST_dec31_dec_sub21_sgn_ext[0:0] + end + attribute \src "libresoc.v:11432.3-11480.6" + process $proc$libresoc.v:11432$227 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub21_is_32b[0:0] $1\LDST_dec31_dec_sub21_is_32b[0:0] + attribute \src "libresoc.v:11433.5-11433.29" + switch \initial + attribute \src "libresoc.v:11433.9-11433.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\LDST_dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\LDST_dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\LDST_dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LDST_dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\LDST_dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\LDST_dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\LDST_dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\LDST_dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LDST_dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\LDST_dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LDST_dec31_dec_sub21_is_32b[0:0] 1'0 + case + assign $1\LDST_dec31_dec_sub21_is_32b[0:0] 1'0 + end + sync always + update \LDST_dec31_dec_sub21_is_32b $0\LDST_dec31_dec_sub21_is_32b[0:0] + end + attribute \src "libresoc.v:11481.3-11529.6" + process $proc$libresoc.v:11481$228 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub21_sgn[0:0] $1\LDST_dec31_dec_sub21_sgn[0:0] + attribute \src "libresoc.v:11482.5-11482.29" + switch \initial + attribute \src "libresoc.v:11482.9-11482.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\LDST_dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\LDST_dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\LDST_dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LDST_dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\LDST_dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\LDST_dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\LDST_dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\LDST_dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LDST_dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\LDST_dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LDST_dec31_dec_sub21_sgn[0:0] 1'0 + case + assign $1\LDST_dec31_dec_sub21_sgn[0:0] 1'0 + end + sync always + update \LDST_dec31_dec_sub21_sgn $0\LDST_dec31_dec_sub21_sgn[0:0] + end + attribute \src "libresoc.v:11530.3-11578.6" + process $proc$libresoc.v:11530$229 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub21_internal_op[6:0] $1\LDST_dec31_dec_sub21_internal_op[6:0] + attribute \src "libresoc.v:11531.5-11531.29" + switch \initial + attribute \src "libresoc.v:11531.9-11531.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\LDST_dec31_dec_sub21_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\LDST_dec31_dec_sub21_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub21_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub21_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\LDST_dec31_dec_sub21_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LDST_dec31_dec_sub21_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\LDST_dec31_dec_sub21_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\LDST_dec31_dec_sub21_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\LDST_dec31_dec_sub21_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\LDST_dec31_dec_sub21_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LDST_dec31_dec_sub21_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub21_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\LDST_dec31_dec_sub21_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LDST_dec31_dec_sub21_internal_op[6:0] 7'0100110 + case + assign $1\LDST_dec31_dec_sub21_internal_op[6:0] 7'0000000 + end + sync always + update \LDST_dec31_dec_sub21_internal_op $0\LDST_dec31_dec_sub21_internal_op[6:0] + end + attribute \src "libresoc.v:11579.3-11627.6" + process $proc$libresoc.v:11579$230 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub21_in1_sel[2:0] $1\LDST_dec31_dec_sub21_in1_sel[2:0] + attribute \src "libresoc.v:11580.5-11580.29" + switch \initial + attribute \src "libresoc.v:11580.9-11580.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\LDST_dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\LDST_dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\LDST_dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LDST_dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\LDST_dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\LDST_dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\LDST_dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\LDST_dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LDST_dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\LDST_dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LDST_dec31_dec_sub21_in1_sel[2:0] 3'010 + case + assign $1\LDST_dec31_dec_sub21_in1_sel[2:0] 3'000 + end + sync always + update \LDST_dec31_dec_sub21_in1_sel $0\LDST_dec31_dec_sub21_in1_sel[2:0] + end + attribute \src "libresoc.v:11628.3-11676.6" + process $proc$libresoc.v:11628$231 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub21_in2_sel[3:0] $1\LDST_dec31_dec_sub21_in2_sel[3:0] + attribute \src "libresoc.v:11629.5-11629.29" + switch \initial + attribute \src "libresoc.v:11629.9-11629.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\LDST_dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\LDST_dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\LDST_dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LDST_dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\LDST_dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\LDST_dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\LDST_dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\LDST_dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LDST_dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\LDST_dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LDST_dec31_dec_sub21_in2_sel[3:0] 4'0001 + case + assign $1\LDST_dec31_dec_sub21_in2_sel[3:0] 4'0000 + end + sync always + update \LDST_dec31_dec_sub21_in2_sel $0\LDST_dec31_dec_sub21_in2_sel[3:0] + end + attribute \src "libresoc.v:11677.3-11725.6" + process $proc$libresoc.v:11677$232 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub21_cr_in[2:0] $1\LDST_dec31_dec_sub21_cr_in[2:0] + attribute \src "libresoc.v:11678.5-11678.29" + switch \initial + attribute \src "libresoc.v:11678.9-11678.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\LDST_dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\LDST_dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\LDST_dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LDST_dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\LDST_dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\LDST_dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\LDST_dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\LDST_dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LDST_dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\LDST_dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LDST_dec31_dec_sub21_cr_in[2:0] 3'000 + case + assign $1\LDST_dec31_dec_sub21_cr_in[2:0] 3'000 + end + sync always + update \LDST_dec31_dec_sub21_cr_in $0\LDST_dec31_dec_sub21_cr_in[2:0] + end + attribute \src "libresoc.v:11726.3-11774.6" + process $proc$libresoc.v:11726$233 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub21_cr_out[2:0] $1\LDST_dec31_dec_sub21_cr_out[2:0] + attribute \src "libresoc.v:11727.5-11727.29" + switch \initial + attribute \src "libresoc.v:11727.9-11727.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\LDST_dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\LDST_dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\LDST_dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LDST_dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\LDST_dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\LDST_dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\LDST_dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\LDST_dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LDST_dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\LDST_dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LDST_dec31_dec_sub21_cr_out[2:0] 3'000 + case + assign $1\LDST_dec31_dec_sub21_cr_out[2:0] 3'000 + end + sync always + update \LDST_dec31_dec_sub21_cr_out $0\LDST_dec31_dec_sub21_cr_out[2:0] + end + attribute \src "libresoc.v:11775.3-11823.6" + process $proc$libresoc.v:11775$234 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub21_ldst_len[3:0] $1\LDST_dec31_dec_sub21_ldst_len[3:0] + attribute \src "libresoc.v:11776.5-11776.29" + switch \initial + attribute \src "libresoc.v:11776.9-11776.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\LDST_dec31_dec_sub21_ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\LDST_dec31_dec_sub21_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub21_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub21_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\LDST_dec31_dec_sub21_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LDST_dec31_dec_sub21_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\LDST_dec31_dec_sub21_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\LDST_dec31_dec_sub21_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\LDST_dec31_dec_sub21_ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\LDST_dec31_dec_sub21_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LDST_dec31_dec_sub21_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub21_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\LDST_dec31_dec_sub21_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LDST_dec31_dec_sub21_ldst_len[3:0] 4'0100 + case + assign $1\LDST_dec31_dec_sub21_ldst_len[3:0] 4'0000 + end + sync always + update \LDST_dec31_dec_sub21_ldst_len $0\LDST_dec31_dec_sub21_ldst_len[3:0] + end + attribute \src "libresoc.v:11824.3-11872.6" + process $proc$libresoc.v:11824$235 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub21_upd[1:0] $1\LDST_dec31_dec_sub21_upd[1:0] + attribute \src "libresoc.v:11825.5-11825.29" + switch \initial + attribute \src "libresoc.v:11825.9-11825.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\LDST_dec31_dec_sub21_upd[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\LDST_dec31_dec_sub21_upd[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub21_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub21_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\LDST_dec31_dec_sub21_upd[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LDST_dec31_dec_sub21_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\LDST_dec31_dec_sub21_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\LDST_dec31_dec_sub21_upd[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\LDST_dec31_dec_sub21_upd[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\LDST_dec31_dec_sub21_upd[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LDST_dec31_dec_sub21_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub21_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\LDST_dec31_dec_sub21_upd[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LDST_dec31_dec_sub21_upd[1:0] 2'10 + case + assign $1\LDST_dec31_dec_sub21_upd[1:0] 2'00 + end + sync always + update \LDST_dec31_dec_sub21_upd $0\LDST_dec31_dec_sub21_upd[1:0] + end + attribute \src "libresoc.v:11873.3-11921.6" + process $proc$libresoc.v:11873$236 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub21_rc_sel[1:0] $1\LDST_dec31_dec_sub21_rc_sel[1:0] + attribute \src "libresoc.v:11874.5-11874.29" + switch \initial + attribute \src "libresoc.v:11874.9-11874.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\LDST_dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\LDST_dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\LDST_dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LDST_dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\LDST_dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\LDST_dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\LDST_dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\LDST_dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LDST_dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\LDST_dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LDST_dec31_dec_sub21_rc_sel[1:0] 2'00 + case + assign $1\LDST_dec31_dec_sub21_rc_sel[1:0] 2'00 + end + sync always + update \LDST_dec31_dec_sub21_rc_sel $0\LDST_dec31_dec_sub21_rc_sel[1:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:11927.1-12516.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec.LDST_dec31.LDST_dec31_dec_sub22" +attribute \generator "nMigen" +module \LDST_dec31_dec_sub22 + attribute \src "libresoc.v:12143.3-12173.6" + wire $0\LDST_dec31_dec_sub22_br[0:0] + attribute \src "libresoc.v:12360.3-12390.6" + wire width 3 $0\LDST_dec31_dec_sub22_cr_in[2:0] + attribute \src "libresoc.v:12391.3-12421.6" + wire width 3 $0\LDST_dec31_dec_sub22_cr_out[2:0] + attribute \src "libresoc.v:12112.3-12142.6" + wire width 13 $0\LDST_dec31_dec_sub22_function_unit[12:0] + attribute \src "libresoc.v:12298.3-12328.6" + wire width 3 $0\LDST_dec31_dec_sub22_in1_sel[2:0] + attribute \src "libresoc.v:12329.3-12359.6" + wire width 4 $0\LDST_dec31_dec_sub22_in2_sel[3:0] + attribute \src "libresoc.v:12267.3-12297.6" + wire width 7 $0\LDST_dec31_dec_sub22_internal_op[6:0] + attribute \src "libresoc.v:12205.3-12235.6" + wire $0\LDST_dec31_dec_sub22_is_32b[0:0] + attribute \src "libresoc.v:12422.3-12452.6" + wire width 4 $0\LDST_dec31_dec_sub22_ldst_len[3:0] + attribute \src "libresoc.v:12484.3-12514.6" + wire width 2 $0\LDST_dec31_dec_sub22_rc_sel[1:0] + attribute \src "libresoc.v:12236.3-12266.6" + wire $0\LDST_dec31_dec_sub22_sgn[0:0] + attribute \src "libresoc.v:12174.3-12204.6" + wire $0\LDST_dec31_dec_sub22_sgn_ext[0:0] + attribute \src "libresoc.v:12453.3-12483.6" + wire width 2 $0\LDST_dec31_dec_sub22_upd[1:0] + attribute \src "libresoc.v:11928.7-11928.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:12143.3-12173.6" + wire $1\LDST_dec31_dec_sub22_br[0:0] + attribute \src "libresoc.v:12360.3-12390.6" + wire width 3 $1\LDST_dec31_dec_sub22_cr_in[2:0] + attribute \src "libresoc.v:12391.3-12421.6" + wire width 3 $1\LDST_dec31_dec_sub22_cr_out[2:0] + attribute \src "libresoc.v:12112.3-12142.6" + wire width 13 $1\LDST_dec31_dec_sub22_function_unit[12:0] + attribute \src "libresoc.v:12298.3-12328.6" + wire width 3 $1\LDST_dec31_dec_sub22_in1_sel[2:0] + attribute \src "libresoc.v:12329.3-12359.6" + wire width 4 $1\LDST_dec31_dec_sub22_in2_sel[3:0] + attribute \src "libresoc.v:12267.3-12297.6" + wire width 7 $1\LDST_dec31_dec_sub22_internal_op[6:0] + attribute \src "libresoc.v:12205.3-12235.6" + wire $1\LDST_dec31_dec_sub22_is_32b[0:0] + attribute \src "libresoc.v:12422.3-12452.6" + wire width 4 $1\LDST_dec31_dec_sub22_ldst_len[3:0] + attribute \src "libresoc.v:12484.3-12514.6" + wire width 2 $1\LDST_dec31_dec_sub22_rc_sel[1:0] + attribute \src "libresoc.v:12236.3-12266.6" + wire $1\LDST_dec31_dec_sub22_sgn[0:0] + attribute \src "libresoc.v:12174.3-12204.6" + wire $1\LDST_dec31_dec_sub22_sgn_ext[0:0] + attribute \src "libresoc.v:12453.3-12483.6" + wire width 2 $1\LDST_dec31_dec_sub22_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 10 \LDST_dec31_dec_sub22_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 5 \LDST_dec31_dec_sub22_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 6 \LDST_dec31_dec_sub22_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 13 output 1 \LDST_dec31_dec_sub22_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 3 \LDST_dec31_dec_sub22_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 4 \LDST_dec31_dec_sub22_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 output 2 \LDST_dec31_dec_sub22_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 12 \LDST_dec31_dec_sub22_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 7 \LDST_dec31_dec_sub22_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 9 \LDST_dec31_dec_sub22_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 13 \LDST_dec31_dec_sub22_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 11 \LDST_dec31_dec_sub22_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 8 \LDST_dec31_dec_sub22_upd + attribute \src "libresoc.v:11928.7-11928.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + wire width 32 input 14 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + wire width 5 \opcode_switch + attribute \src "libresoc.v:11928.7-11928.20" + process $proc$libresoc.v:11928$251 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:12112.3-12142.6" + process $proc$libresoc.v:12112$238 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub22_function_unit[12:0] $1\LDST_dec31_dec_sub22_function_unit[12:0] + attribute \src "libresoc.v:12113.5-12113.29" + switch \initial + attribute \src "libresoc.v:12113.9-12113.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\LDST_dec31_dec_sub22_function_unit[12:0] 13'0000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LDST_dec31_dec_sub22_function_unit[12:0] 13'0000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\LDST_dec31_dec_sub22_function_unit[12:0] 13'0000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\LDST_dec31_dec_sub22_function_unit[12:0] 13'0000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_function_unit[12:0] 13'0000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\LDST_dec31_dec_sub22_function_unit[12:0] 13'0000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_function_unit[12:0] 13'0000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_function_unit[12:0] 13'0000000000100 + case + assign $1\LDST_dec31_dec_sub22_function_unit[12:0] 13'0000000000000 + end + sync always + update \LDST_dec31_dec_sub22_function_unit $0\LDST_dec31_dec_sub22_function_unit[12:0] + end + attribute \src "libresoc.v:12143.3-12173.6" + process $proc$libresoc.v:12143$239 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub22_br[0:0] $1\LDST_dec31_dec_sub22_br[0:0] + attribute \src "libresoc.v:12144.5-12144.29" + switch \initial + attribute \src "libresoc.v:12144.9-12144.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\LDST_dec31_dec_sub22_br[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LDST_dec31_dec_sub22_br[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\LDST_dec31_dec_sub22_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\LDST_dec31_dec_sub22_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_br[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\LDST_dec31_dec_sub22_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_br[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_br[0:0] 1'0 + case + assign $1\LDST_dec31_dec_sub22_br[0:0] 1'0 + end + sync always + update \LDST_dec31_dec_sub22_br $0\LDST_dec31_dec_sub22_br[0:0] + end + attribute \src "libresoc.v:12174.3-12204.6" + process $proc$libresoc.v:12174$240 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub22_sgn_ext[0:0] $1\LDST_dec31_dec_sub22_sgn_ext[0:0] + attribute \src "libresoc.v:12175.5-12175.29" + switch \initial + attribute \src "libresoc.v:12175.9-12175.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\LDST_dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LDST_dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\LDST_dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\LDST_dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\LDST_dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_sgn_ext[0:0] 1'0 + case + assign $1\LDST_dec31_dec_sub22_sgn_ext[0:0] 1'0 + end + sync always + update \LDST_dec31_dec_sub22_sgn_ext $0\LDST_dec31_dec_sub22_sgn_ext[0:0] + end + attribute \src "libresoc.v:12205.3-12235.6" + process $proc$libresoc.v:12205$241 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub22_is_32b[0:0] $1\LDST_dec31_dec_sub22_is_32b[0:0] + attribute \src "libresoc.v:12206.5-12206.29" + switch \initial + attribute \src "libresoc.v:12206.9-12206.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\LDST_dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LDST_dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\LDST_dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\LDST_dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\LDST_dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_is_32b[0:0] 1'0 + case + assign $1\LDST_dec31_dec_sub22_is_32b[0:0] 1'0 + end + sync always + update \LDST_dec31_dec_sub22_is_32b $0\LDST_dec31_dec_sub22_is_32b[0:0] + end + attribute \src "libresoc.v:12236.3-12266.6" + process $proc$libresoc.v:12236$242 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub22_sgn[0:0] $1\LDST_dec31_dec_sub22_sgn[0:0] + attribute \src "libresoc.v:12237.5-12237.29" + switch \initial + attribute \src "libresoc.v:12237.9-12237.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\LDST_dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LDST_dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\LDST_dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\LDST_dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\LDST_dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_sgn[0:0] 1'0 + case + assign $1\LDST_dec31_dec_sub22_sgn[0:0] 1'0 + end + sync always + update \LDST_dec31_dec_sub22_sgn $0\LDST_dec31_dec_sub22_sgn[0:0] + end + attribute \src "libresoc.v:12267.3-12297.6" + process $proc$libresoc.v:12267$243 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub22_internal_op[6:0] $1\LDST_dec31_dec_sub22_internal_op[6:0] + attribute \src "libresoc.v:12268.5-12268.29" + switch \initial + attribute \src "libresoc.v:12268.9-12268.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\LDST_dec31_dec_sub22_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LDST_dec31_dec_sub22_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\LDST_dec31_dec_sub22_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\LDST_dec31_dec_sub22_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\LDST_dec31_dec_sub22_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_internal_op[6:0] 7'0100110 + case + assign $1\LDST_dec31_dec_sub22_internal_op[6:0] 7'0000000 + end + sync always + update \LDST_dec31_dec_sub22_internal_op $0\LDST_dec31_dec_sub22_internal_op[6:0] + end + attribute \src "libresoc.v:12298.3-12328.6" + process $proc$libresoc.v:12298$244 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub22_in1_sel[2:0] $1\LDST_dec31_dec_sub22_in1_sel[2:0] + attribute \src "libresoc.v:12299.5-12299.29" + switch \initial + attribute \src "libresoc.v:12299.9-12299.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\LDST_dec31_dec_sub22_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LDST_dec31_dec_sub22_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\LDST_dec31_dec_sub22_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\LDST_dec31_dec_sub22_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\LDST_dec31_dec_sub22_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_in1_sel[2:0] 3'010 + case + assign $1\LDST_dec31_dec_sub22_in1_sel[2:0] 3'000 + end + sync always + update \LDST_dec31_dec_sub22_in1_sel $0\LDST_dec31_dec_sub22_in1_sel[2:0] + end + attribute \src "libresoc.v:12329.3-12359.6" + process $proc$libresoc.v:12329$245 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub22_in2_sel[3:0] $1\LDST_dec31_dec_sub22_in2_sel[3:0] + attribute \src "libresoc.v:12330.5-12330.29" + switch \initial + attribute \src "libresoc.v:12330.9-12330.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\LDST_dec31_dec_sub22_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LDST_dec31_dec_sub22_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\LDST_dec31_dec_sub22_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\LDST_dec31_dec_sub22_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\LDST_dec31_dec_sub22_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_in2_sel[3:0] 4'0001 + case + assign $1\LDST_dec31_dec_sub22_in2_sel[3:0] 4'0000 + end + sync always + update \LDST_dec31_dec_sub22_in2_sel $0\LDST_dec31_dec_sub22_in2_sel[3:0] + end + attribute \src "libresoc.v:12360.3-12390.6" + process $proc$libresoc.v:12360$246 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub22_cr_in[2:0] $1\LDST_dec31_dec_sub22_cr_in[2:0] + attribute \src "libresoc.v:12361.5-12361.29" + switch \initial + attribute \src "libresoc.v:12361.9-12361.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\LDST_dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LDST_dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\LDST_dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\LDST_dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\LDST_dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_cr_in[2:0] 3'000 + case + assign $1\LDST_dec31_dec_sub22_cr_in[2:0] 3'000 + end + sync always + update \LDST_dec31_dec_sub22_cr_in $0\LDST_dec31_dec_sub22_cr_in[2:0] + end + attribute \src "libresoc.v:12391.3-12421.6" + process $proc$libresoc.v:12391$247 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub22_cr_out[2:0] $1\LDST_dec31_dec_sub22_cr_out[2:0] + attribute \src "libresoc.v:12392.5-12392.29" + switch \initial + attribute \src "libresoc.v:12392.9-12392.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\LDST_dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LDST_dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\LDST_dec31_dec_sub22_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\LDST_dec31_dec_sub22_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\LDST_dec31_dec_sub22_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_cr_out[2:0] 3'001 + case + assign $1\LDST_dec31_dec_sub22_cr_out[2:0] 3'000 + end + sync always + update \LDST_dec31_dec_sub22_cr_out $0\LDST_dec31_dec_sub22_cr_out[2:0] + end + attribute \src "libresoc.v:12422.3-12452.6" + process $proc$libresoc.v:12422$248 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub22_ldst_len[3:0] $1\LDST_dec31_dec_sub22_ldst_len[3:0] + attribute \src "libresoc.v:12423.5-12423.29" + switch \initial + attribute \src "libresoc.v:12423.9-12423.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\LDST_dec31_dec_sub22_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LDST_dec31_dec_sub22_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\LDST_dec31_dec_sub22_ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\LDST_dec31_dec_sub22_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\LDST_dec31_dec_sub22_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_ldst_len[3:0] 4'0100 + case + assign $1\LDST_dec31_dec_sub22_ldst_len[3:0] 4'0000 + end + sync always + update \LDST_dec31_dec_sub22_ldst_len $0\LDST_dec31_dec_sub22_ldst_len[3:0] + end + attribute \src "libresoc.v:12453.3-12483.6" + process $proc$libresoc.v:12453$249 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub22_upd[1:0] $1\LDST_dec31_dec_sub22_upd[1:0] + attribute \src "libresoc.v:12454.5-12454.29" + switch \initial + attribute \src "libresoc.v:12454.9-12454.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\LDST_dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LDST_dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\LDST_dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\LDST_dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\LDST_dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_upd[1:0] 2'00 + case + assign $1\LDST_dec31_dec_sub22_upd[1:0] 2'00 + end + sync always + update \LDST_dec31_dec_sub22_upd $0\LDST_dec31_dec_sub22_upd[1:0] + end + attribute \src "libresoc.v:12484.3-12514.6" + process $proc$libresoc.v:12484$250 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub22_rc_sel[1:0] $1\LDST_dec31_dec_sub22_rc_sel[1:0] + attribute \src "libresoc.v:12485.5-12485.29" + switch \initial + attribute \src "libresoc.v:12485.9-12485.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\LDST_dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LDST_dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\LDST_dec31_dec_sub22_rc_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\LDST_dec31_dec_sub22_rc_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\LDST_dec31_dec_sub22_rc_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_rc_sel[1:0] 2'01 + case + assign $1\LDST_dec31_dec_sub22_rc_sel[1:0] 2'00 + end + sync always + update \LDST_dec31_dec_sub22_rc_sel $0\LDST_dec31_dec_sub22_rc_sel[1:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:12520.1-13343.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec.LDST_dec31.LDST_dec31_dec_sub23" +attribute \generator "nMigen" +module \LDST_dec31_dec_sub23 + attribute \src "libresoc.v:12754.3-12802.6" + wire $0\LDST_dec31_dec_sub23_br[0:0] + attribute \src "libresoc.v:13097.3-13145.6" + wire width 3 $0\LDST_dec31_dec_sub23_cr_in[2:0] + attribute \src "libresoc.v:13146.3-13194.6" + wire width 3 $0\LDST_dec31_dec_sub23_cr_out[2:0] + attribute \src "libresoc.v:12705.3-12753.6" + wire width 13 $0\LDST_dec31_dec_sub23_function_unit[12:0] + attribute \src "libresoc.v:12999.3-13047.6" + wire width 3 $0\LDST_dec31_dec_sub23_in1_sel[2:0] + attribute \src "libresoc.v:13048.3-13096.6" + wire width 4 $0\LDST_dec31_dec_sub23_in2_sel[3:0] + attribute \src "libresoc.v:12950.3-12998.6" + wire width 7 $0\LDST_dec31_dec_sub23_internal_op[6:0] + attribute \src "libresoc.v:12852.3-12900.6" + wire $0\LDST_dec31_dec_sub23_is_32b[0:0] + attribute \src "libresoc.v:13195.3-13243.6" + wire width 4 $0\LDST_dec31_dec_sub23_ldst_len[3:0] + attribute \src "libresoc.v:13293.3-13341.6" + wire width 2 $0\LDST_dec31_dec_sub23_rc_sel[1:0] + attribute \src "libresoc.v:12901.3-12949.6" + wire $0\LDST_dec31_dec_sub23_sgn[0:0] + attribute \src "libresoc.v:12803.3-12851.6" + wire $0\LDST_dec31_dec_sub23_sgn_ext[0:0] + attribute \src "libresoc.v:13244.3-13292.6" + wire width 2 $0\LDST_dec31_dec_sub23_upd[1:0] + attribute \src "libresoc.v:12521.7-12521.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:12754.3-12802.6" + wire $1\LDST_dec31_dec_sub23_br[0:0] + attribute \src "libresoc.v:13097.3-13145.6" + wire width 3 $1\LDST_dec31_dec_sub23_cr_in[2:0] + attribute \src "libresoc.v:13146.3-13194.6" + wire width 3 $1\LDST_dec31_dec_sub23_cr_out[2:0] + attribute \src "libresoc.v:12705.3-12753.6" + wire width 13 $1\LDST_dec31_dec_sub23_function_unit[12:0] + attribute \src "libresoc.v:12999.3-13047.6" + wire width 3 $1\LDST_dec31_dec_sub23_in1_sel[2:0] + attribute \src "libresoc.v:13048.3-13096.6" + wire width 4 $1\LDST_dec31_dec_sub23_in2_sel[3:0] + attribute \src "libresoc.v:12950.3-12998.6" + wire width 7 $1\LDST_dec31_dec_sub23_internal_op[6:0] + attribute \src "libresoc.v:12852.3-12900.6" + wire $1\LDST_dec31_dec_sub23_is_32b[0:0] + attribute \src "libresoc.v:13195.3-13243.6" + wire width 4 $1\LDST_dec31_dec_sub23_ldst_len[3:0] + attribute \src "libresoc.v:13293.3-13341.6" + wire width 2 $1\LDST_dec31_dec_sub23_rc_sel[1:0] + attribute \src "libresoc.v:12901.3-12949.6" + wire $1\LDST_dec31_dec_sub23_sgn[0:0] + attribute \src "libresoc.v:12803.3-12851.6" + wire $1\LDST_dec31_dec_sub23_sgn_ext[0:0] + attribute \src "libresoc.v:13244.3-13292.6" + wire width 2 $1\LDST_dec31_dec_sub23_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 10 \LDST_dec31_dec_sub23_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 5 \LDST_dec31_dec_sub23_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 6 \LDST_dec31_dec_sub23_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 13 output 1 \LDST_dec31_dec_sub23_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 3 \LDST_dec31_dec_sub23_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 4 \LDST_dec31_dec_sub23_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 output 2 \LDST_dec31_dec_sub23_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 12 \LDST_dec31_dec_sub23_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 7 \LDST_dec31_dec_sub23_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 9 \LDST_dec31_dec_sub23_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 13 \LDST_dec31_dec_sub23_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 11 \LDST_dec31_dec_sub23_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 8 \LDST_dec31_dec_sub23_upd + attribute \src "libresoc.v:12521.7-12521.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + wire width 32 input 14 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + wire width 5 \opcode_switch + attribute \src "libresoc.v:12521.7-12521.20" + process $proc$libresoc.v:12521$265 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:12705.3-12753.6" + process $proc$libresoc.v:12705$252 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub23_function_unit[12:0] $1\LDST_dec31_dec_sub23_function_unit[12:0] + attribute \src "libresoc.v:12706.5-12706.29" + switch \initial + attribute \src "libresoc.v:12706.9-12706.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LDST_dec31_dec_sub23_function_unit[12:0] 13'0000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\LDST_dec31_dec_sub23_function_unit[12:0] 13'0000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LDST_dec31_dec_sub23_function_unit[12:0] 13'0000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\LDST_dec31_dec_sub23_function_unit[12:0] 13'0000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\LDST_dec31_dec_sub23_function_unit[12:0] 13'0000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\LDST_dec31_dec_sub23_function_unit[12:0] 13'0000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub23_function_unit[12:0] 13'0000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub23_function_unit[12:0] 13'0000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\LDST_dec31_dec_sub23_function_unit[12:0] 13'0000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\LDST_dec31_dec_sub23_function_unit[12:0] 13'0000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\LDST_dec31_dec_sub23_function_unit[12:0] 13'0000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\LDST_dec31_dec_sub23_function_unit[12:0] 13'0000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LDST_dec31_dec_sub23_function_unit[12:0] 13'0000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub23_function_unit[12:0] 13'0000000000100 + case + assign $1\LDST_dec31_dec_sub23_function_unit[12:0] 13'0000000000000 + end + sync always + update \LDST_dec31_dec_sub23_function_unit $0\LDST_dec31_dec_sub23_function_unit[12:0] + end + attribute \src "libresoc.v:12754.3-12802.6" + process $proc$libresoc.v:12754$253 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub23_br[0:0] $1\LDST_dec31_dec_sub23_br[0:0] + attribute \src "libresoc.v:12755.5-12755.29" + switch \initial + attribute \src "libresoc.v:12755.9-12755.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LDST_dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\LDST_dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LDST_dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\LDST_dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\LDST_dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\LDST_dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\LDST_dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\LDST_dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\LDST_dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\LDST_dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LDST_dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub23_br[0:0] 1'0 + case + assign $1\LDST_dec31_dec_sub23_br[0:0] 1'0 + end + sync always + update \LDST_dec31_dec_sub23_br $0\LDST_dec31_dec_sub23_br[0:0] + end + attribute \src "libresoc.v:12803.3-12851.6" + process $proc$libresoc.v:12803$254 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub23_sgn_ext[0:0] $1\LDST_dec31_dec_sub23_sgn_ext[0:0] + attribute \src "libresoc.v:12804.5-12804.29" + switch \initial + attribute \src "libresoc.v:12804.9-12804.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LDST_dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\LDST_dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LDST_dec31_dec_sub23_sgn_ext[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\LDST_dec31_dec_sub23_sgn_ext[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\LDST_dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\LDST_dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\LDST_dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\LDST_dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\LDST_dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\LDST_dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LDST_dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub23_sgn_ext[0:0] 1'0 + case + assign $1\LDST_dec31_dec_sub23_sgn_ext[0:0] 1'0 + end + sync always + update \LDST_dec31_dec_sub23_sgn_ext $0\LDST_dec31_dec_sub23_sgn_ext[0:0] + end + attribute \src "libresoc.v:12852.3-12900.6" + process $proc$libresoc.v:12852$255 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub23_is_32b[0:0] $1\LDST_dec31_dec_sub23_is_32b[0:0] + attribute \src "libresoc.v:12853.5-12853.29" + switch \initial + attribute \src "libresoc.v:12853.9-12853.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LDST_dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\LDST_dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LDST_dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\LDST_dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\LDST_dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\LDST_dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\LDST_dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\LDST_dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\LDST_dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\LDST_dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LDST_dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub23_is_32b[0:0] 1'0 + case + assign $1\LDST_dec31_dec_sub23_is_32b[0:0] 1'0 + end + sync always + update \LDST_dec31_dec_sub23_is_32b $0\LDST_dec31_dec_sub23_is_32b[0:0] + end + attribute \src "libresoc.v:12901.3-12949.6" + process $proc$libresoc.v:12901$256 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub23_sgn[0:0] $1\LDST_dec31_dec_sub23_sgn[0:0] + attribute \src "libresoc.v:12902.5-12902.29" + switch \initial + attribute \src "libresoc.v:12902.9-12902.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LDST_dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\LDST_dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LDST_dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\LDST_dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\LDST_dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\LDST_dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\LDST_dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\LDST_dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\LDST_dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\LDST_dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LDST_dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub23_sgn[0:0] 1'0 + case + assign $1\LDST_dec31_dec_sub23_sgn[0:0] 1'0 + end + sync always + update \LDST_dec31_dec_sub23_sgn $0\LDST_dec31_dec_sub23_sgn[0:0] + end + attribute \src "libresoc.v:12950.3-12998.6" + process $proc$libresoc.v:12950$257 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub23_internal_op[6:0] $1\LDST_dec31_dec_sub23_internal_op[6:0] + attribute \src "libresoc.v:12951.5-12951.29" + switch \initial + attribute \src "libresoc.v:12951.9-12951.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LDST_dec31_dec_sub23_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\LDST_dec31_dec_sub23_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LDST_dec31_dec_sub23_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\LDST_dec31_dec_sub23_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\LDST_dec31_dec_sub23_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\LDST_dec31_dec_sub23_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub23_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub23_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\LDST_dec31_dec_sub23_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\LDST_dec31_dec_sub23_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\LDST_dec31_dec_sub23_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\LDST_dec31_dec_sub23_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LDST_dec31_dec_sub23_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub23_internal_op[6:0] 7'0100110 + case + assign $1\LDST_dec31_dec_sub23_internal_op[6:0] 7'0000000 + end + sync always + update \LDST_dec31_dec_sub23_internal_op $0\LDST_dec31_dec_sub23_internal_op[6:0] + end + attribute \src "libresoc.v:12999.3-13047.6" + process $proc$libresoc.v:12999$258 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub23_in1_sel[2:0] $1\LDST_dec31_dec_sub23_in1_sel[2:0] + attribute \src "libresoc.v:13000.5-13000.29" + switch \initial + attribute \src "libresoc.v:13000.9-13000.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LDST_dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\LDST_dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LDST_dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\LDST_dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\LDST_dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\LDST_dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\LDST_dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\LDST_dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\LDST_dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\LDST_dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LDST_dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub23_in1_sel[2:0] 3'010 + case + assign $1\LDST_dec31_dec_sub23_in1_sel[2:0] 3'000 + end + sync always + update \LDST_dec31_dec_sub23_in1_sel $0\LDST_dec31_dec_sub23_in1_sel[2:0] + end + attribute \src "libresoc.v:13048.3-13096.6" + process $proc$libresoc.v:13048$259 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub23_in2_sel[3:0] $1\LDST_dec31_dec_sub23_in2_sel[3:0] + attribute \src "libresoc.v:13049.5-13049.29" + switch \initial + attribute \src "libresoc.v:13049.9-13049.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LDST_dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\LDST_dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LDST_dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\LDST_dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\LDST_dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\LDST_dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\LDST_dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\LDST_dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\LDST_dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\LDST_dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LDST_dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub23_in2_sel[3:0] 4'0001 + case + assign $1\LDST_dec31_dec_sub23_in2_sel[3:0] 4'0000 + end + sync always + update \LDST_dec31_dec_sub23_in2_sel $0\LDST_dec31_dec_sub23_in2_sel[3:0] + end + attribute \src "libresoc.v:13097.3-13145.6" + process $proc$libresoc.v:13097$260 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub23_cr_in[2:0] $1\LDST_dec31_dec_sub23_cr_in[2:0] + attribute \src "libresoc.v:13098.5-13098.29" + switch \initial + attribute \src "libresoc.v:13098.9-13098.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LDST_dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\LDST_dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LDST_dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\LDST_dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\LDST_dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\LDST_dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\LDST_dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\LDST_dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\LDST_dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\LDST_dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LDST_dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub23_cr_in[2:0] 3'000 + case + assign $1\LDST_dec31_dec_sub23_cr_in[2:0] 3'000 + end + sync always + update \LDST_dec31_dec_sub23_cr_in $0\LDST_dec31_dec_sub23_cr_in[2:0] + end + attribute \src "libresoc.v:13146.3-13194.6" + process $proc$libresoc.v:13146$261 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub23_cr_out[2:0] $1\LDST_dec31_dec_sub23_cr_out[2:0] + attribute \src "libresoc.v:13147.5-13147.29" + switch \initial + attribute \src "libresoc.v:13147.9-13147.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LDST_dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\LDST_dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LDST_dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\LDST_dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\LDST_dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\LDST_dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\LDST_dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\LDST_dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\LDST_dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\LDST_dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LDST_dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub23_cr_out[2:0] 3'000 + case + assign $1\LDST_dec31_dec_sub23_cr_out[2:0] 3'000 + end + sync always + update \LDST_dec31_dec_sub23_cr_out $0\LDST_dec31_dec_sub23_cr_out[2:0] + end + attribute \src "libresoc.v:13195.3-13243.6" + process $proc$libresoc.v:13195$262 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub23_ldst_len[3:0] $1\LDST_dec31_dec_sub23_ldst_len[3:0] + attribute \src "libresoc.v:13196.5-13196.29" + switch \initial + attribute \src "libresoc.v:13196.9-13196.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LDST_dec31_dec_sub23_ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\LDST_dec31_dec_sub23_ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LDST_dec31_dec_sub23_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\LDST_dec31_dec_sub23_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\LDST_dec31_dec_sub23_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\LDST_dec31_dec_sub23_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub23_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub23_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\LDST_dec31_dec_sub23_ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\LDST_dec31_dec_sub23_ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\LDST_dec31_dec_sub23_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\LDST_dec31_dec_sub23_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LDST_dec31_dec_sub23_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub23_ldst_len[3:0] 4'0100 + case + assign $1\LDST_dec31_dec_sub23_ldst_len[3:0] 4'0000 + end + sync always + update \LDST_dec31_dec_sub23_ldst_len $0\LDST_dec31_dec_sub23_ldst_len[3:0] + end + attribute \src "libresoc.v:13244.3-13292.6" + process $proc$libresoc.v:13244$263 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub23_upd[1:0] $1\LDST_dec31_dec_sub23_upd[1:0] + attribute \src "libresoc.v:13245.5-13245.29" + switch \initial + attribute \src "libresoc.v:13245.9-13245.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LDST_dec31_dec_sub23_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\LDST_dec31_dec_sub23_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LDST_dec31_dec_sub23_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\LDST_dec31_dec_sub23_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\LDST_dec31_dec_sub23_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\LDST_dec31_dec_sub23_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub23_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub23_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\LDST_dec31_dec_sub23_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\LDST_dec31_dec_sub23_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\LDST_dec31_dec_sub23_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\LDST_dec31_dec_sub23_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LDST_dec31_dec_sub23_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub23_upd[1:0] 2'00 + case + assign $1\LDST_dec31_dec_sub23_upd[1:0] 2'00 + end + sync always + update \LDST_dec31_dec_sub23_upd $0\LDST_dec31_dec_sub23_upd[1:0] + end + attribute \src "libresoc.v:13293.3-13341.6" + process $proc$libresoc.v:13293$264 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub23_rc_sel[1:0] $1\LDST_dec31_dec_sub23_rc_sel[1:0] + attribute \src "libresoc.v:13294.5-13294.29" + switch \initial + attribute \src "libresoc.v:13294.9-13294.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LDST_dec31_dec_sub23_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\LDST_dec31_dec_sub23_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LDST_dec31_dec_sub23_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\LDST_dec31_dec_sub23_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\LDST_dec31_dec_sub23_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\LDST_dec31_dec_sub23_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub23_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub23_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\LDST_dec31_dec_sub23_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\LDST_dec31_dec_sub23_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\LDST_dec31_dec_sub23_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\LDST_dec31_dec_sub23_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LDST_dec31_dec_sub23_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub23_rc_sel[1:0] 2'00 + case + assign $1\LDST_dec31_dec_sub23_rc_sel[1:0] 2'00 + end + sync always + update \LDST_dec31_dec_sub23_rc_sel $0\LDST_dec31_dec_sub23_rc_sel[1:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:13347.1-13741.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec.LDST_dec58" +attribute \generator "nMigen" +module \LDST_dec58 + attribute \src "libresoc.v:13548.3-13563.6" + wire $0\LDST_dec58_br[0:0] + attribute \src "libresoc.v:13660.3-13675.6" + wire width 3 $0\LDST_dec58_cr_in[2:0] + attribute \src "libresoc.v:13676.3-13691.6" + wire width 3 $0\LDST_dec58_cr_out[2:0] + attribute \src "libresoc.v:13532.3-13547.6" + wire width 13 $0\LDST_dec58_function_unit[12:0] + attribute \src "libresoc.v:13628.3-13643.6" + wire width 3 $0\LDST_dec58_in1_sel[2:0] + attribute \src "libresoc.v:13644.3-13659.6" + wire width 4 $0\LDST_dec58_in2_sel[3:0] + attribute \src "libresoc.v:13612.3-13627.6" + wire width 7 $0\LDST_dec58_internal_op[6:0] + attribute \src "libresoc.v:13580.3-13595.6" + wire $0\LDST_dec58_is_32b[0:0] + attribute \src "libresoc.v:13692.3-13707.6" + wire width 4 $0\LDST_dec58_ldst_len[3:0] + attribute \src "libresoc.v:13724.3-13739.6" + wire width 2 $0\LDST_dec58_rc_sel[1:0] + attribute \src "libresoc.v:13596.3-13611.6" + wire $0\LDST_dec58_sgn[0:0] + attribute \src "libresoc.v:13564.3-13579.6" + wire $0\LDST_dec58_sgn_ext[0:0] + attribute \src "libresoc.v:13708.3-13723.6" + wire width 2 $0\LDST_dec58_upd[1:0] + attribute \src "libresoc.v:13348.7-13348.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:13548.3-13563.6" + wire $1\LDST_dec58_br[0:0] + attribute \src "libresoc.v:13660.3-13675.6" + wire width 3 $1\LDST_dec58_cr_in[2:0] + attribute \src "libresoc.v:13676.3-13691.6" + wire width 3 $1\LDST_dec58_cr_out[2:0] + attribute \src "libresoc.v:13532.3-13547.6" + wire width 13 $1\LDST_dec58_function_unit[12:0] + attribute \src "libresoc.v:13628.3-13643.6" + wire width 3 $1\LDST_dec58_in1_sel[2:0] + attribute \src "libresoc.v:13644.3-13659.6" + wire width 4 $1\LDST_dec58_in2_sel[3:0] + attribute \src "libresoc.v:13612.3-13627.6" + wire width 7 $1\LDST_dec58_internal_op[6:0] + attribute \src "libresoc.v:13580.3-13595.6" + wire $1\LDST_dec58_is_32b[0:0] + attribute \src "libresoc.v:13692.3-13707.6" + wire width 4 $1\LDST_dec58_ldst_len[3:0] + attribute \src "libresoc.v:13724.3-13739.6" + wire width 2 $1\LDST_dec58_rc_sel[1:0] + attribute \src "libresoc.v:13596.3-13611.6" + wire $1\LDST_dec58_sgn[0:0] + attribute \src "libresoc.v:13564.3-13579.6" + wire $1\LDST_dec58_sgn_ext[0:0] + attribute \src "libresoc.v:13708.3-13723.6" + wire width 2 $1\LDST_dec58_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 10 \LDST_dec58_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 5 \LDST_dec58_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 6 \LDST_dec58_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 13 output 1 \LDST_dec58_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 3 \LDST_dec58_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 4 \LDST_dec58_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 output 2 \LDST_dec58_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 12 \LDST_dec58_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 7 \LDST_dec58_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 9 \LDST_dec58_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 13 \LDST_dec58_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 11 \LDST_dec58_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 8 \LDST_dec58_upd + attribute \src "libresoc.v:13348.7-13348.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + wire width 32 input 14 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + wire width 2 \opcode_switch + attribute \src "libresoc.v:13348.7-13348.20" + process $proc$libresoc.v:13348$279 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:13532.3-13547.6" + process $proc$libresoc.v:13532$266 + assign { } { } + assign { } { } + assign $0\LDST_dec58_function_unit[12:0] $1\LDST_dec58_function_unit[12:0] + attribute \src "libresoc.v:13533.5-13533.29" + switch \initial + attribute \src "libresoc.v:13533.9-13533.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\LDST_dec58_function_unit[12:0] 13'0000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\LDST_dec58_function_unit[12:0] 13'0000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\LDST_dec58_function_unit[12:0] 13'0000000000100 + case + assign $1\LDST_dec58_function_unit[12:0] 13'0000000000000 + end + sync always + update \LDST_dec58_function_unit $0\LDST_dec58_function_unit[12:0] + end + attribute \src "libresoc.v:13548.3-13563.6" + process $proc$libresoc.v:13548$267 + assign { } { } + assign { } { } + assign $0\LDST_dec58_br[0:0] $1\LDST_dec58_br[0:0] + attribute \src "libresoc.v:13549.5-13549.29" + switch \initial + attribute \src "libresoc.v:13549.9-13549.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\LDST_dec58_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\LDST_dec58_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\LDST_dec58_br[0:0] 1'0 + case + assign $1\LDST_dec58_br[0:0] 1'0 + end + sync always + update \LDST_dec58_br $0\LDST_dec58_br[0:0] + end + attribute \src "libresoc.v:13564.3-13579.6" + process $proc$libresoc.v:13564$268 + assign { } { } + assign { } { } + assign $0\LDST_dec58_sgn_ext[0:0] $1\LDST_dec58_sgn_ext[0:0] + attribute \src "libresoc.v:13565.5-13565.29" + switch \initial + attribute \src "libresoc.v:13565.9-13565.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\LDST_dec58_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\LDST_dec58_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\LDST_dec58_sgn_ext[0:0] 1'1 + case + assign $1\LDST_dec58_sgn_ext[0:0] 1'0 + end + sync always + update \LDST_dec58_sgn_ext $0\LDST_dec58_sgn_ext[0:0] + end + attribute \src "libresoc.v:13580.3-13595.6" + process $proc$libresoc.v:13580$269 + assign { } { } + assign { } { } + assign $0\LDST_dec58_is_32b[0:0] $1\LDST_dec58_is_32b[0:0] + attribute \src "libresoc.v:13581.5-13581.29" + switch \initial + attribute \src "libresoc.v:13581.9-13581.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\LDST_dec58_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\LDST_dec58_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\LDST_dec58_is_32b[0:0] 1'0 + case + assign $1\LDST_dec58_is_32b[0:0] 1'0 + end + sync always + update \LDST_dec58_is_32b $0\LDST_dec58_is_32b[0:0] + end + attribute \src "libresoc.v:13596.3-13611.6" + process $proc$libresoc.v:13596$270 + assign { } { } + assign { } { } + assign $0\LDST_dec58_sgn[0:0] $1\LDST_dec58_sgn[0:0] + attribute \src "libresoc.v:13597.5-13597.29" + switch \initial + attribute \src "libresoc.v:13597.9-13597.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\LDST_dec58_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\LDST_dec58_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\LDST_dec58_sgn[0:0] 1'0 + case + assign $1\LDST_dec58_sgn[0:0] 1'0 + end + sync always + update \LDST_dec58_sgn $0\LDST_dec58_sgn[0:0] + end + attribute \src "libresoc.v:13612.3-13627.6" + process $proc$libresoc.v:13612$271 + assign { } { } + assign { } { } + assign $0\LDST_dec58_internal_op[6:0] $1\LDST_dec58_internal_op[6:0] + attribute \src "libresoc.v:13613.5-13613.29" + switch \initial + attribute \src "libresoc.v:13613.9-13613.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\LDST_dec58_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\LDST_dec58_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\LDST_dec58_internal_op[6:0] 7'0100101 + case + assign $1\LDST_dec58_internal_op[6:0] 7'0000000 + end + sync always + update \LDST_dec58_internal_op $0\LDST_dec58_internal_op[6:0] + end + attribute \src "libresoc.v:13628.3-13643.6" + process $proc$libresoc.v:13628$272 + assign { } { } + assign { } { } + assign $0\LDST_dec58_in1_sel[2:0] $1\LDST_dec58_in1_sel[2:0] + attribute \src "libresoc.v:13629.5-13629.29" + switch \initial + attribute \src "libresoc.v:13629.9-13629.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\LDST_dec58_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\LDST_dec58_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\LDST_dec58_in1_sel[2:0] 3'010 + case + assign $1\LDST_dec58_in1_sel[2:0] 3'000 + end + sync always + update \LDST_dec58_in1_sel $0\LDST_dec58_in1_sel[2:0] + end + attribute \src "libresoc.v:13644.3-13659.6" + process $proc$libresoc.v:13644$273 + assign { } { } + assign { } { } + assign $0\LDST_dec58_in2_sel[3:0] $1\LDST_dec58_in2_sel[3:0] + attribute \src "libresoc.v:13645.5-13645.29" + switch \initial + attribute \src "libresoc.v:13645.9-13645.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\LDST_dec58_in2_sel[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\LDST_dec58_in2_sel[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\LDST_dec58_in2_sel[3:0] 4'1000 + case + assign $1\LDST_dec58_in2_sel[3:0] 4'0000 + end + sync always + update \LDST_dec58_in2_sel $0\LDST_dec58_in2_sel[3:0] + end + attribute \src "libresoc.v:13660.3-13675.6" + process $proc$libresoc.v:13660$274 + assign { } { } + assign { } { } + assign $0\LDST_dec58_cr_in[2:0] $1\LDST_dec58_cr_in[2:0] + attribute \src "libresoc.v:13661.5-13661.29" + switch \initial + attribute \src "libresoc.v:13661.9-13661.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\LDST_dec58_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\LDST_dec58_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\LDST_dec58_cr_in[2:0] 3'000 + case + assign $1\LDST_dec58_cr_in[2:0] 3'000 + end + sync always + update \LDST_dec58_cr_in $0\LDST_dec58_cr_in[2:0] + end + attribute \src "libresoc.v:13676.3-13691.6" + process $proc$libresoc.v:13676$275 + assign { } { } + assign { } { } + assign $0\LDST_dec58_cr_out[2:0] $1\LDST_dec58_cr_out[2:0] + attribute \src "libresoc.v:13677.5-13677.29" + switch \initial + attribute \src "libresoc.v:13677.9-13677.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\LDST_dec58_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\LDST_dec58_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\LDST_dec58_cr_out[2:0] 3'000 + case + assign $1\LDST_dec58_cr_out[2:0] 3'000 + end + sync always + update \LDST_dec58_cr_out $0\LDST_dec58_cr_out[2:0] + end + attribute \src "libresoc.v:13692.3-13707.6" + process $proc$libresoc.v:13692$276 + assign { } { } + assign { } { } + assign $0\LDST_dec58_ldst_len[3:0] $1\LDST_dec58_ldst_len[3:0] + attribute \src "libresoc.v:13693.5-13693.29" + switch \initial + attribute \src "libresoc.v:13693.9-13693.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\LDST_dec58_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\LDST_dec58_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\LDST_dec58_ldst_len[3:0] 4'0100 + case + assign $1\LDST_dec58_ldst_len[3:0] 4'0000 + end + sync always + update \LDST_dec58_ldst_len $0\LDST_dec58_ldst_len[3:0] + end + attribute \src "libresoc.v:13708.3-13723.6" + process $proc$libresoc.v:13708$277 + assign { } { } + assign { } { } + assign $0\LDST_dec58_upd[1:0] $1\LDST_dec58_upd[1:0] + attribute \src "libresoc.v:13709.5-13709.29" + switch \initial + attribute \src "libresoc.v:13709.9-13709.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\LDST_dec58_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\LDST_dec58_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\LDST_dec58_upd[1:0] 2'00 + case + assign $1\LDST_dec58_upd[1:0] 2'00 + end + sync always + update \LDST_dec58_upd $0\LDST_dec58_upd[1:0] + end + attribute \src "libresoc.v:13724.3-13739.6" + process $proc$libresoc.v:13724$278 + assign { } { } + assign { } { } + assign $0\LDST_dec58_rc_sel[1:0] $1\LDST_dec58_rc_sel[1:0] + attribute \src "libresoc.v:13725.5-13725.29" + switch \initial + attribute \src "libresoc.v:13725.9-13725.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\LDST_dec58_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\LDST_dec58_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\LDST_dec58_rc_sel[1:0] 2'00 + case + assign $1\LDST_dec58_rc_sel[1:0] 2'00 + end + sync always + update \LDST_dec58_rc_sel $0\LDST_dec58_rc_sel[1:0] + end + connect \opcode_switch \opcode_in [1:0] +end +attribute \src "libresoc.v:13745.1-14100.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec.LDST_dec62" +attribute \generator "nMigen" +module \LDST_dec62 + attribute \src "libresoc.v:13943.3-13955.6" + wire $0\LDST_dec62_br[0:0] + attribute \src "libresoc.v:14034.3-14046.6" + wire width 3 $0\LDST_dec62_cr_in[2:0] + attribute \src "libresoc.v:14047.3-14059.6" + wire width 3 $0\LDST_dec62_cr_out[2:0] + attribute \src "libresoc.v:13930.3-13942.6" + wire width 13 $0\LDST_dec62_function_unit[12:0] + attribute \src "libresoc.v:14008.3-14020.6" + wire width 3 $0\LDST_dec62_in1_sel[2:0] + attribute \src "libresoc.v:14021.3-14033.6" + wire width 4 $0\LDST_dec62_in2_sel[3:0] + attribute \src "libresoc.v:13995.3-14007.6" + wire width 7 $0\LDST_dec62_internal_op[6:0] + attribute \src "libresoc.v:13969.3-13981.6" + wire $0\LDST_dec62_is_32b[0:0] + attribute \src "libresoc.v:14060.3-14072.6" + wire width 4 $0\LDST_dec62_ldst_len[3:0] + attribute \src "libresoc.v:14086.3-14098.6" + wire width 2 $0\LDST_dec62_rc_sel[1:0] + attribute \src "libresoc.v:13982.3-13994.6" + wire $0\LDST_dec62_sgn[0:0] + attribute \src "libresoc.v:13956.3-13968.6" + wire $0\LDST_dec62_sgn_ext[0:0] + attribute \src "libresoc.v:14073.3-14085.6" + wire width 2 $0\LDST_dec62_upd[1:0] + attribute \src "libresoc.v:13746.7-13746.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:13943.3-13955.6" + wire $1\LDST_dec62_br[0:0] + attribute \src "libresoc.v:14034.3-14046.6" + wire width 3 $1\LDST_dec62_cr_in[2:0] + attribute \src "libresoc.v:14047.3-14059.6" + wire width 3 $1\LDST_dec62_cr_out[2:0] + attribute \src "libresoc.v:13930.3-13942.6" + wire width 13 $1\LDST_dec62_function_unit[12:0] + attribute \src "libresoc.v:14008.3-14020.6" + wire width 3 $1\LDST_dec62_in1_sel[2:0] + attribute \src "libresoc.v:14021.3-14033.6" + wire width 4 $1\LDST_dec62_in2_sel[3:0] + attribute \src "libresoc.v:13995.3-14007.6" + wire width 7 $1\LDST_dec62_internal_op[6:0] + attribute \src "libresoc.v:13969.3-13981.6" + wire $1\LDST_dec62_is_32b[0:0] + attribute \src "libresoc.v:14060.3-14072.6" + wire width 4 $1\LDST_dec62_ldst_len[3:0] + attribute \src "libresoc.v:14086.3-14098.6" + wire width 2 $1\LDST_dec62_rc_sel[1:0] + attribute \src "libresoc.v:13982.3-13994.6" + wire $1\LDST_dec62_sgn[0:0] + attribute \src "libresoc.v:13956.3-13968.6" + wire $1\LDST_dec62_sgn_ext[0:0] + attribute \src "libresoc.v:14073.3-14085.6" + wire width 2 $1\LDST_dec62_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 10 \LDST_dec62_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 5 \LDST_dec62_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 6 \LDST_dec62_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 13 output 1 \LDST_dec62_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 3 \LDST_dec62_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 4 \LDST_dec62_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 output 2 \LDST_dec62_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 12 \LDST_dec62_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 7 \LDST_dec62_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 9 \LDST_dec62_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 13 \LDST_dec62_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 11 \LDST_dec62_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 8 \LDST_dec62_upd + attribute \src "libresoc.v:13746.7-13746.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + wire width 32 input 14 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + wire width 2 \opcode_switch + attribute \src "libresoc.v:13746.7-13746.20" + process $proc$libresoc.v:13746$293 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:13930.3-13942.6" + process $proc$libresoc.v:13930$280 + assign { } { } + assign { } { } + assign $0\LDST_dec62_function_unit[12:0] $1\LDST_dec62_function_unit[12:0] + attribute \src "libresoc.v:13931.5-13931.29" + switch \initial + attribute \src "libresoc.v:13931.9-13931.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\LDST_dec62_function_unit[12:0] 13'0000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\LDST_dec62_function_unit[12:0] 13'0000000000100 + case + assign $1\LDST_dec62_function_unit[12:0] 13'0000000000000 + end + sync always + update \LDST_dec62_function_unit $0\LDST_dec62_function_unit[12:0] + end + attribute \src "libresoc.v:13943.3-13955.6" + process $proc$libresoc.v:13943$281 + assign { } { } + assign { } { } + assign $0\LDST_dec62_br[0:0] $1\LDST_dec62_br[0:0] + attribute \src "libresoc.v:13944.5-13944.29" + switch \initial + attribute \src "libresoc.v:13944.9-13944.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\LDST_dec62_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\LDST_dec62_br[0:0] 1'0 + case + assign $1\LDST_dec62_br[0:0] 1'0 + end + sync always + update \LDST_dec62_br $0\LDST_dec62_br[0:0] + end + attribute \src "libresoc.v:13956.3-13968.6" + process $proc$libresoc.v:13956$282 + assign { } { } + assign { } { } + assign $0\LDST_dec62_sgn_ext[0:0] $1\LDST_dec62_sgn_ext[0:0] + attribute \src "libresoc.v:13957.5-13957.29" + switch \initial + attribute \src "libresoc.v:13957.9-13957.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\LDST_dec62_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\LDST_dec62_sgn_ext[0:0] 1'0 + case + assign $1\LDST_dec62_sgn_ext[0:0] 1'0 + end + sync always + update \LDST_dec62_sgn_ext $0\LDST_dec62_sgn_ext[0:0] + end + attribute \src "libresoc.v:13969.3-13981.6" + process $proc$libresoc.v:13969$283 + assign { } { } + assign { } { } + assign $0\LDST_dec62_is_32b[0:0] $1\LDST_dec62_is_32b[0:0] + attribute \src "libresoc.v:13970.5-13970.29" + switch \initial + attribute \src "libresoc.v:13970.9-13970.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\LDST_dec62_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\LDST_dec62_is_32b[0:0] 1'0 + case + assign $1\LDST_dec62_is_32b[0:0] 1'0 + end + sync always + update \LDST_dec62_is_32b $0\LDST_dec62_is_32b[0:0] + end + attribute \src "libresoc.v:13982.3-13994.6" + process $proc$libresoc.v:13982$284 + assign { } { } + assign { } { } + assign $0\LDST_dec62_sgn[0:0] $1\LDST_dec62_sgn[0:0] + attribute \src "libresoc.v:13983.5-13983.29" + switch \initial + attribute \src "libresoc.v:13983.9-13983.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\LDST_dec62_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\LDST_dec62_sgn[0:0] 1'0 + case + assign $1\LDST_dec62_sgn[0:0] 1'0 + end + sync always + update \LDST_dec62_sgn $0\LDST_dec62_sgn[0:0] + end + attribute \src "libresoc.v:13995.3-14007.6" + process $proc$libresoc.v:13995$285 + assign { } { } + assign { } { } + assign $0\LDST_dec62_internal_op[6:0] $1\LDST_dec62_internal_op[6:0] + attribute \src "libresoc.v:13996.5-13996.29" + switch \initial + attribute \src "libresoc.v:13996.9-13996.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\LDST_dec62_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\LDST_dec62_internal_op[6:0] 7'0100110 + case + assign $1\LDST_dec62_internal_op[6:0] 7'0000000 + end + sync always + update \LDST_dec62_internal_op $0\LDST_dec62_internal_op[6:0] + end + attribute \src "libresoc.v:14008.3-14020.6" + process $proc$libresoc.v:14008$286 + assign { } { } + assign { } { } + assign $0\LDST_dec62_in1_sel[2:0] $1\LDST_dec62_in1_sel[2:0] + attribute \src "libresoc.v:14009.5-14009.29" + switch \initial + attribute \src "libresoc.v:14009.9-14009.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\LDST_dec62_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\LDST_dec62_in1_sel[2:0] 3'010 + case + assign $1\LDST_dec62_in1_sel[2:0] 3'000 + end + sync always + update \LDST_dec62_in1_sel $0\LDST_dec62_in1_sel[2:0] + end + attribute \src "libresoc.v:14021.3-14033.6" + process $proc$libresoc.v:14021$287 + assign { } { } + assign { } { } + assign $0\LDST_dec62_in2_sel[3:0] $1\LDST_dec62_in2_sel[3:0] + attribute \src "libresoc.v:14022.5-14022.29" + switch \initial + attribute \src "libresoc.v:14022.9-14022.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\LDST_dec62_in2_sel[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\LDST_dec62_in2_sel[3:0] 4'1000 + case + assign $1\LDST_dec62_in2_sel[3:0] 4'0000 + end + sync always + update \LDST_dec62_in2_sel $0\LDST_dec62_in2_sel[3:0] + end + attribute \src "libresoc.v:14034.3-14046.6" + process $proc$libresoc.v:14034$288 + assign { } { } + assign { } { } + assign $0\LDST_dec62_cr_in[2:0] $1\LDST_dec62_cr_in[2:0] + attribute \src "libresoc.v:14035.5-14035.29" + switch \initial + attribute \src "libresoc.v:14035.9-14035.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\LDST_dec62_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\LDST_dec62_cr_in[2:0] 3'000 + case + assign $1\LDST_dec62_cr_in[2:0] 3'000 + end + sync always + update \LDST_dec62_cr_in $0\LDST_dec62_cr_in[2:0] + end + attribute \src "libresoc.v:14047.3-14059.6" + process $proc$libresoc.v:14047$289 + assign { } { } + assign { } { } + assign $0\LDST_dec62_cr_out[2:0] $1\LDST_dec62_cr_out[2:0] + attribute \src "libresoc.v:14048.5-14048.29" + switch \initial + attribute \src "libresoc.v:14048.9-14048.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\LDST_dec62_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\LDST_dec62_cr_out[2:0] 3'000 + case + assign $1\LDST_dec62_cr_out[2:0] 3'000 + end + sync always + update \LDST_dec62_cr_out $0\LDST_dec62_cr_out[2:0] + end + attribute \src "libresoc.v:14060.3-14072.6" + process $proc$libresoc.v:14060$290 + assign { } { } + assign { } { } + assign $0\LDST_dec62_ldst_len[3:0] $1\LDST_dec62_ldst_len[3:0] + attribute \src "libresoc.v:14061.5-14061.29" + switch \initial + attribute \src "libresoc.v:14061.9-14061.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\LDST_dec62_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\LDST_dec62_ldst_len[3:0] 4'1000 + case + assign $1\LDST_dec62_ldst_len[3:0] 4'0000 + end + sync always + update \LDST_dec62_ldst_len $0\LDST_dec62_ldst_len[3:0] + end + attribute \src "libresoc.v:14073.3-14085.6" + process $proc$libresoc.v:14073$291 + assign { } { } + assign { } { } + assign $0\LDST_dec62_upd[1:0] $1\LDST_dec62_upd[1:0] + attribute \src "libresoc.v:14074.5-14074.29" + switch \initial + attribute \src "libresoc.v:14074.9-14074.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\LDST_dec62_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\LDST_dec62_upd[1:0] 2'01 + case + assign $1\LDST_dec62_upd[1:0] 2'00 + end + sync always + update \LDST_dec62_upd $0\LDST_dec62_upd[1:0] + end + attribute \src "libresoc.v:14086.3-14098.6" + process $proc$libresoc.v:14086$292 + assign { } { } + assign { } { } + assign $0\LDST_dec62_rc_sel[1:0] $1\LDST_dec62_rc_sel[1:0] + attribute \src "libresoc.v:14087.5-14087.29" + switch \initial + attribute \src "libresoc.v:14087.9-14087.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\LDST_dec62_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\LDST_dec62_rc_sel[1:0] 2'00 + case + assign $1\LDST_dec62_rc_sel[1:0] 2'00 + end + sync always + update \LDST_dec62_rc_sel $0\LDST_dec62_rc_sel[1:0] + end + connect \opcode_switch \opcode_in [1:0] +end +attribute \src "libresoc.v:14104.1-14851.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LOGICAL.dec.LOGICAL_dec31" +attribute \generator "nMigen" +module \LOGICAL_dec31 + attribute \src "libresoc.v:14821.3-14833.6" + wire width 3 $0\LOGICAL_dec31_cr_in[2:0] + attribute \src "libresoc.v:14834.3-14846.6" + wire width 3 $0\LOGICAL_dec31_cr_out[2:0] + attribute \src "libresoc.v:14691.3-14703.6" + wire width 2 $0\LOGICAL_dec31_cry_in[1:0] + attribute \src "libresoc.v:14730.3-14742.6" + wire $0\LOGICAL_dec31_cry_out[0:0] + attribute \src "libresoc.v:14769.3-14781.6" + wire width 13 $0\LOGICAL_dec31_function_unit[12:0] + attribute \src "libresoc.v:14795.3-14807.6" + wire width 3 $0\LOGICAL_dec31_in1_sel[2:0] + attribute \src "libresoc.v:14808.3-14820.6" + wire width 4 $0\LOGICAL_dec31_in2_sel[3:0] + attribute \src "libresoc.v:14782.3-14794.6" + wire width 7 $0\LOGICAL_dec31_internal_op[6:0] + attribute \src "libresoc.v:14704.3-14716.6" + wire $0\LOGICAL_dec31_inv_a[0:0] + attribute \src "libresoc.v:14717.3-14729.6" + wire $0\LOGICAL_dec31_inv_out[0:0] + attribute \src "libresoc.v:14743.3-14755.6" + wire $0\LOGICAL_dec31_is_32b[0:0] + attribute \src "libresoc.v:14665.3-14677.6" + wire width 4 $0\LOGICAL_dec31_ldst_len[3:0] + attribute \src "libresoc.v:14678.3-14690.6" + wire width 2 $0\LOGICAL_dec31_rc_sel[1:0] + attribute \src "libresoc.v:14756.3-14768.6" + wire $0\LOGICAL_dec31_sgn[0:0] + attribute \src "libresoc.v:14105.7-14105.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:14821.3-14833.6" + wire width 3 $1\LOGICAL_dec31_cr_in[2:0] + attribute \src "libresoc.v:14834.3-14846.6" + wire width 3 $1\LOGICAL_dec31_cr_out[2:0] + attribute \src "libresoc.v:14691.3-14703.6" + wire width 2 $1\LOGICAL_dec31_cry_in[1:0] + attribute \src "libresoc.v:14730.3-14742.6" + wire $1\LOGICAL_dec31_cry_out[0:0] + attribute \src "libresoc.v:14769.3-14781.6" + wire width 13 $1\LOGICAL_dec31_function_unit[12:0] + attribute \src "libresoc.v:14795.3-14807.6" + wire width 3 $1\LOGICAL_dec31_in1_sel[2:0] + attribute \src "libresoc.v:14808.3-14820.6" + wire width 4 $1\LOGICAL_dec31_in2_sel[3:0] + attribute \src "libresoc.v:14782.3-14794.6" + wire width 7 $1\LOGICAL_dec31_internal_op[6:0] + attribute \src "libresoc.v:14704.3-14716.6" + wire $1\LOGICAL_dec31_inv_a[0:0] + attribute \src "libresoc.v:14717.3-14729.6" + wire $1\LOGICAL_dec31_inv_out[0:0] + attribute \src "libresoc.v:14743.3-14755.6" + wire $1\LOGICAL_dec31_is_32b[0:0] + attribute \src "libresoc.v:14665.3-14677.6" + wire width 4 $1\LOGICAL_dec31_ldst_len[3:0] + attribute \src "libresoc.v:14678.3-14690.6" + wire width 2 $1\LOGICAL_dec31_rc_sel[1:0] + attribute \src "libresoc.v:14756.3-14768.6" + wire $1\LOGICAL_dec31_sgn[0:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 5 \LOGICAL_dec31_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 6 \LOGICAL_dec31_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 9 \LOGICAL_dec31_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 12 \LOGICAL_dec31_cry_out + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 13 \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + wire width 32 \LOGICAL_dec31_dec_sub26_opcode_in + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute 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width 3 \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + wire width 32 \LOGICAL_dec31_dec_sub28_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 13 output 1 \LOGICAL_dec31_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 3 \LOGICAL_dec31_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 4 \LOGICAL_dec31_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 output 2 \LOGICAL_dec31_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 10 \LOGICAL_dec31_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 11 \LOGICAL_dec31_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 13 \LOGICAL_dec31_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 7 \LOGICAL_dec31_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 8 \LOGICAL_dec31_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 14 \LOGICAL_dec31_sgn + attribute \src "libresoc.v:14105.7-14105.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:347" + wire width 5 \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + wire width 32 input 15 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + wire width 10 \opcode_switch + attribute \module_not_derived 1 + attribute \src "libresoc.v:14631.27-14647.4" + cell \LOGICAL_dec31_dec_sub26 \LOGICAL_dec31_dec_sub26 + connect \LOGICAL_dec31_dec_sub26_cr_in \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cr_in + connect \LOGICAL_dec31_dec_sub26_cr_out \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cr_out + connect \LOGICAL_dec31_dec_sub26_cry_in \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cry_in + connect \LOGICAL_dec31_dec_sub26_cry_out \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cry_out + connect \LOGICAL_dec31_dec_sub26_function_unit \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_function_unit + connect \LOGICAL_dec31_dec_sub26_in1_sel \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_in1_sel + connect \LOGICAL_dec31_dec_sub26_in2_sel \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_in2_sel + connect \LOGICAL_dec31_dec_sub26_internal_op \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_internal_op + connect \LOGICAL_dec31_dec_sub26_inv_a \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_inv_a + connect \LOGICAL_dec31_dec_sub26_inv_out \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_inv_out + connect \LOGICAL_dec31_dec_sub26_is_32b \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_is_32b + connect \LOGICAL_dec31_dec_sub26_ldst_len \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_ldst_len + connect \LOGICAL_dec31_dec_sub26_rc_sel \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_rc_sel + connect \LOGICAL_dec31_dec_sub26_sgn \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_sgn + connect \opcode_in \LOGICAL_dec31_dec_sub26_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:14648.27-14664.4" + cell \LOGICAL_dec31_dec_sub28 \LOGICAL_dec31_dec_sub28 + connect \LOGICAL_dec31_dec_sub28_cr_in \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cr_in + connect \LOGICAL_dec31_dec_sub28_cr_out \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cr_out + connect \LOGICAL_dec31_dec_sub28_cry_in \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cry_in + connect \LOGICAL_dec31_dec_sub28_cry_out \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cry_out + connect \LOGICAL_dec31_dec_sub28_function_unit \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_function_unit + connect \LOGICAL_dec31_dec_sub28_in1_sel \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_in1_sel + connect \LOGICAL_dec31_dec_sub28_in2_sel \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_in2_sel + connect \LOGICAL_dec31_dec_sub28_internal_op \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_internal_op + connect \LOGICAL_dec31_dec_sub28_inv_a \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_inv_a + connect \LOGICAL_dec31_dec_sub28_inv_out \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_inv_out + connect \LOGICAL_dec31_dec_sub28_is_32b \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_is_32b + connect \LOGICAL_dec31_dec_sub28_ldst_len \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_ldst_len + connect \LOGICAL_dec31_dec_sub28_rc_sel \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_rc_sel + connect \LOGICAL_dec31_dec_sub28_sgn \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_sgn + connect \opcode_in \LOGICAL_dec31_dec_sub28_opcode_in + end + attribute \src "libresoc.v:14105.7-14105.20" + process $proc$libresoc.v:14105$308 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:14665.3-14677.6" + process $proc$libresoc.v:14665$294 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_ldst_len[3:0] $1\LOGICAL_dec31_ldst_len[3:0] + attribute \src "libresoc.v:14666.5-14666.29" + switch \initial + attribute \src "libresoc.v:14666.9-14666.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LOGICAL_dec31_ldst_len[3:0] \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\LOGICAL_dec31_ldst_len[3:0] \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_ldst_len + case + assign $1\LOGICAL_dec31_ldst_len[3:0] 4'0000 + end + sync always + update \LOGICAL_dec31_ldst_len $0\LOGICAL_dec31_ldst_len[3:0] + end + attribute \src "libresoc.v:14678.3-14690.6" + process $proc$libresoc.v:14678$295 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_rc_sel[1:0] $1\LOGICAL_dec31_rc_sel[1:0] + attribute \src "libresoc.v:14679.5-14679.29" + switch \initial + attribute \src "libresoc.v:14679.9-14679.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LOGICAL_dec31_rc_sel[1:0] \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\LOGICAL_dec31_rc_sel[1:0] \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_rc_sel + case + assign $1\LOGICAL_dec31_rc_sel[1:0] 2'00 + end + sync always + update \LOGICAL_dec31_rc_sel $0\LOGICAL_dec31_rc_sel[1:0] + end + attribute \src "libresoc.v:14691.3-14703.6" + process $proc$libresoc.v:14691$296 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_cry_in[1:0] $1\LOGICAL_dec31_cry_in[1:0] + attribute \src "libresoc.v:14692.5-14692.29" + switch \initial + attribute \src "libresoc.v:14692.9-14692.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LOGICAL_dec31_cry_in[1:0] \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\LOGICAL_dec31_cry_in[1:0] \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cry_in + case + assign $1\LOGICAL_dec31_cry_in[1:0] 2'00 + end + sync always + update \LOGICAL_dec31_cry_in $0\LOGICAL_dec31_cry_in[1:0] + end + attribute \src "libresoc.v:14704.3-14716.6" + process $proc$libresoc.v:14704$297 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_inv_a[0:0] $1\LOGICAL_dec31_inv_a[0:0] + attribute \src "libresoc.v:14705.5-14705.29" + switch \initial + attribute \src "libresoc.v:14705.9-14705.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LOGICAL_dec31_inv_a[0:0] \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\LOGICAL_dec31_inv_a[0:0] \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_inv_a + case + assign $1\LOGICAL_dec31_inv_a[0:0] 1'0 + end + sync always + update \LOGICAL_dec31_inv_a $0\LOGICAL_dec31_inv_a[0:0] + end + attribute \src "libresoc.v:14717.3-14729.6" + process $proc$libresoc.v:14717$298 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_inv_out[0:0] $1\LOGICAL_dec31_inv_out[0:0] + attribute \src "libresoc.v:14718.5-14718.29" + switch \initial + attribute \src "libresoc.v:14718.9-14718.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LOGICAL_dec31_inv_out[0:0] \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\LOGICAL_dec31_inv_out[0:0] \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_inv_out + case + assign $1\LOGICAL_dec31_inv_out[0:0] 1'0 + end + sync always + update \LOGICAL_dec31_inv_out $0\LOGICAL_dec31_inv_out[0:0] + end + attribute \src "libresoc.v:14730.3-14742.6" + process $proc$libresoc.v:14730$299 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_cry_out[0:0] $1\LOGICAL_dec31_cry_out[0:0] + attribute \src "libresoc.v:14731.5-14731.29" + switch \initial + attribute \src "libresoc.v:14731.9-14731.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LOGICAL_dec31_cry_out[0:0] \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\LOGICAL_dec31_cry_out[0:0] \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cry_out + case + assign $1\LOGICAL_dec31_cry_out[0:0] 1'0 + end + sync always + update \LOGICAL_dec31_cry_out $0\LOGICAL_dec31_cry_out[0:0] + end + attribute \src "libresoc.v:14743.3-14755.6" + process $proc$libresoc.v:14743$300 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_is_32b[0:0] $1\LOGICAL_dec31_is_32b[0:0] + attribute \src "libresoc.v:14744.5-14744.29" + switch \initial + attribute \src "libresoc.v:14744.9-14744.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LOGICAL_dec31_is_32b[0:0] \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\LOGICAL_dec31_is_32b[0:0] \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_is_32b + case + assign $1\LOGICAL_dec31_is_32b[0:0] 1'0 + end + sync always + update \LOGICAL_dec31_is_32b $0\LOGICAL_dec31_is_32b[0:0] + end + attribute \src "libresoc.v:14756.3-14768.6" + process $proc$libresoc.v:14756$301 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_sgn[0:0] $1\LOGICAL_dec31_sgn[0:0] + attribute \src "libresoc.v:14757.5-14757.29" + switch \initial + attribute \src "libresoc.v:14757.9-14757.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LOGICAL_dec31_sgn[0:0] \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\LOGICAL_dec31_sgn[0:0] \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_sgn + case + assign $1\LOGICAL_dec31_sgn[0:0] 1'0 + end + sync always + update \LOGICAL_dec31_sgn $0\LOGICAL_dec31_sgn[0:0] + end + attribute \src "libresoc.v:14769.3-14781.6" + process $proc$libresoc.v:14769$302 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_function_unit[12:0] $1\LOGICAL_dec31_function_unit[12:0] + attribute \src "libresoc.v:14770.5-14770.29" + switch \initial + attribute \src "libresoc.v:14770.9-14770.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LOGICAL_dec31_function_unit[12:0] \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\LOGICAL_dec31_function_unit[12:0] \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_function_unit + case + assign $1\LOGICAL_dec31_function_unit[12:0] 13'0000000000000 + end + sync always + update \LOGICAL_dec31_function_unit $0\LOGICAL_dec31_function_unit[12:0] + end + attribute \src "libresoc.v:14782.3-14794.6" + process $proc$libresoc.v:14782$303 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_internal_op[6:0] $1\LOGICAL_dec31_internal_op[6:0] + attribute \src "libresoc.v:14783.5-14783.29" + switch \initial + attribute \src "libresoc.v:14783.9-14783.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LOGICAL_dec31_internal_op[6:0] \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\LOGICAL_dec31_internal_op[6:0] \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_internal_op + case + assign $1\LOGICAL_dec31_internal_op[6:0] 7'0000000 + end + sync always + update \LOGICAL_dec31_internal_op $0\LOGICAL_dec31_internal_op[6:0] + end + attribute \src "libresoc.v:14795.3-14807.6" + process $proc$libresoc.v:14795$304 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_in1_sel[2:0] $1\LOGICAL_dec31_in1_sel[2:0] + attribute \src "libresoc.v:14796.5-14796.29" + switch \initial + attribute \src "libresoc.v:14796.9-14796.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LOGICAL_dec31_in1_sel[2:0] \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\LOGICAL_dec31_in1_sel[2:0] \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_in1_sel + case + assign $1\LOGICAL_dec31_in1_sel[2:0] 3'000 + end + sync always + update \LOGICAL_dec31_in1_sel $0\LOGICAL_dec31_in1_sel[2:0] + end + attribute \src "libresoc.v:14808.3-14820.6" + process $proc$libresoc.v:14808$305 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_in2_sel[3:0] $1\LOGICAL_dec31_in2_sel[3:0] + attribute \src "libresoc.v:14809.5-14809.29" + switch \initial + attribute \src "libresoc.v:14809.9-14809.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LOGICAL_dec31_in2_sel[3:0] \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\LOGICAL_dec31_in2_sel[3:0] \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_in2_sel + case + assign $1\LOGICAL_dec31_in2_sel[3:0] 4'0000 + end + sync always + update \LOGICAL_dec31_in2_sel $0\LOGICAL_dec31_in2_sel[3:0] + end + attribute \src "libresoc.v:14821.3-14833.6" + process $proc$libresoc.v:14821$306 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_cr_in[2:0] $1\LOGICAL_dec31_cr_in[2:0] + attribute \src "libresoc.v:14822.5-14822.29" + switch \initial + attribute \src "libresoc.v:14822.9-14822.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LOGICAL_dec31_cr_in[2:0] \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\LOGICAL_dec31_cr_in[2:0] \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cr_in + case + assign $1\LOGICAL_dec31_cr_in[2:0] 3'000 + end + sync always + update \LOGICAL_dec31_cr_in $0\LOGICAL_dec31_cr_in[2:0] + end + attribute \src "libresoc.v:14834.3-14846.6" + process $proc$libresoc.v:14834$307 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_cr_out[2:0] $1\LOGICAL_dec31_cr_out[2:0] + attribute \src "libresoc.v:14835.5-14835.29" + switch \initial + attribute \src "libresoc.v:14835.9-14835.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LOGICAL_dec31_cr_out[2:0] \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\LOGICAL_dec31_cr_out[2:0] \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cr_out + case + assign $1\LOGICAL_dec31_cr_out[2:0] 3'000 + end + sync always + update \LOGICAL_dec31_cr_out $0\LOGICAL_dec31_cr_out[2:0] + end + connect \LOGICAL_dec31_dec_sub26_opcode_in \opcode_in + connect \LOGICAL_dec31_dec_sub28_opcode_in \opcode_in + connect \opc_in \opcode_switch [4:0] + connect \opcode_switch \opcode_in [10:1] +end +attribute \src "libresoc.v:14855.1-15519.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LOGICAL.dec.LOGICAL_dec31.LOGICAL_dec31_dec_sub26" +attribute \generator "nMigen" +module \LOGICAL_dec31_dec_sub26 + attribute \src "libresoc.v:15348.3-15381.6" + wire width 3 $0\LOGICAL_dec31_dec_sub26_cr_in[2:0] + attribute \src "libresoc.v:15382.3-15415.6" + wire width 3 $0\LOGICAL_dec31_dec_sub26_cr_out[2:0] + attribute \src "libresoc.v:15484.3-15517.6" + wire width 2 $0\LOGICAL_dec31_dec_sub26_cry_in[1:0] + attribute \src "libresoc.v:15144.3-15177.6" + wire $0\LOGICAL_dec31_dec_sub26_cry_out[0:0] + attribute \src "libresoc.v:15042.3-15075.6" + wire width 13 $0\LOGICAL_dec31_dec_sub26_function_unit[12:0] + attribute \src "libresoc.v:15280.3-15313.6" + wire width 3 $0\LOGICAL_dec31_dec_sub26_in1_sel[2:0] + attribute \src "libresoc.v:15314.3-15347.6" + wire width 4 $0\LOGICAL_dec31_dec_sub26_in2_sel[3:0] + attribute \src "libresoc.v:15246.3-15279.6" + wire width 7 $0\LOGICAL_dec31_dec_sub26_internal_op[6:0] + attribute \src "libresoc.v:15076.3-15109.6" + wire $0\LOGICAL_dec31_dec_sub26_inv_a[0:0] + attribute \src "libresoc.v:15110.3-15143.6" + wire $0\LOGICAL_dec31_dec_sub26_inv_out[0:0] + attribute \src "libresoc.v:15178.3-15211.6" + wire $0\LOGICAL_dec31_dec_sub26_is_32b[0:0] + attribute \src "libresoc.v:15416.3-15449.6" + wire width 4 $0\LOGICAL_dec31_dec_sub26_ldst_len[3:0] + attribute \src "libresoc.v:15450.3-15483.6" + wire width 2 $0\LOGICAL_dec31_dec_sub26_rc_sel[1:0] + attribute \src "libresoc.v:15212.3-15245.6" + wire $0\LOGICAL_dec31_dec_sub26_sgn[0:0] + attribute \src "libresoc.v:14856.7-14856.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:15348.3-15381.6" + wire width 3 $1\LOGICAL_dec31_dec_sub26_cr_in[2:0] + attribute \src "libresoc.v:15382.3-15415.6" + wire width 3 $1\LOGICAL_dec31_dec_sub26_cr_out[2:0] + attribute \src "libresoc.v:15484.3-15517.6" + wire width 2 $1\LOGICAL_dec31_dec_sub26_cry_in[1:0] + attribute \src "libresoc.v:15144.3-15177.6" + wire $1\LOGICAL_dec31_dec_sub26_cry_out[0:0] + attribute \src "libresoc.v:15042.3-15075.6" + wire width 13 $1\LOGICAL_dec31_dec_sub26_function_unit[12:0] + attribute \src "libresoc.v:15280.3-15313.6" + wire width 3 $1\LOGICAL_dec31_dec_sub26_in1_sel[2:0] + attribute \src "libresoc.v:15314.3-15347.6" + wire width 4 $1\LOGICAL_dec31_dec_sub26_in2_sel[3:0] + attribute \src "libresoc.v:15246.3-15279.6" + wire width 7 $1\LOGICAL_dec31_dec_sub26_internal_op[6:0] + attribute \src "libresoc.v:15076.3-15109.6" + wire $1\LOGICAL_dec31_dec_sub26_inv_a[0:0] + attribute \src "libresoc.v:15110.3-15143.6" + wire $1\LOGICAL_dec31_dec_sub26_inv_out[0:0] + attribute \src "libresoc.v:15178.3-15211.6" + wire $1\LOGICAL_dec31_dec_sub26_is_32b[0:0] + attribute \src "libresoc.v:15416.3-15449.6" + wire width 4 $1\LOGICAL_dec31_dec_sub26_ldst_len[3:0] + attribute \src "libresoc.v:15450.3-15483.6" + wire width 2 $1\LOGICAL_dec31_dec_sub26_rc_sel[1:0] + attribute \src "libresoc.v:15212.3-15245.6" + wire $1\LOGICAL_dec31_dec_sub26_sgn[0:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 5 \LOGICAL_dec31_dec_sub26_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 6 \LOGICAL_dec31_dec_sub26_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 9 \LOGICAL_dec31_dec_sub26_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 12 \LOGICAL_dec31_dec_sub26_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 13 output 1 \LOGICAL_dec31_dec_sub26_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 3 \LOGICAL_dec31_dec_sub26_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 4 \LOGICAL_dec31_dec_sub26_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 output 2 \LOGICAL_dec31_dec_sub26_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 10 \LOGICAL_dec31_dec_sub26_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 11 \LOGICAL_dec31_dec_sub26_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 13 \LOGICAL_dec31_dec_sub26_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 7 \LOGICAL_dec31_dec_sub26_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 8 \LOGICAL_dec31_dec_sub26_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 14 \LOGICAL_dec31_dec_sub26_sgn + attribute \src "libresoc.v:14856.7-14856.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + wire width 32 input 15 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + wire width 5 \opcode_switch + attribute \src "libresoc.v:14856.7-14856.20" + process $proc$libresoc.v:14856$323 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:15042.3-15075.6" + process $proc$libresoc.v:15042$309 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_dec_sub26_function_unit[12:0] $1\LOGICAL_dec31_dec_sub26_function_unit[12:0] + attribute \src "libresoc.v:15043.5-15043.29" + switch \initial + attribute \src "libresoc.v:15043.9-15043.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_function_unit[12:0] 13'0000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_function_unit[12:0] 13'0000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_function_unit[12:0] 13'0000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_function_unit[12:0] 13'0000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_function_unit[12:0] 13'0000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_function_unit[12:0] 13'0000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_function_unit[12:0] 13'0000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_function_unit[12:0] 13'0000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_function_unit[12:0] 13'0000000010000 + case + assign $1\LOGICAL_dec31_dec_sub26_function_unit[12:0] 13'0000000000000 + end + sync always + update \LOGICAL_dec31_dec_sub26_function_unit $0\LOGICAL_dec31_dec_sub26_function_unit[12:0] + end + attribute \src "libresoc.v:15076.3-15109.6" + process $proc$libresoc.v:15076$310 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_dec_sub26_inv_a[0:0] $1\LOGICAL_dec31_dec_sub26_inv_a[0:0] + attribute \src "libresoc.v:15077.5-15077.29" + switch \initial + attribute \src "libresoc.v:15077.9-15077.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_inv_a[0:0] 1'0 + case + assign $1\LOGICAL_dec31_dec_sub26_inv_a[0:0] 1'0 + end + sync always + update \LOGICAL_dec31_dec_sub26_inv_a $0\LOGICAL_dec31_dec_sub26_inv_a[0:0] + end + attribute \src "libresoc.v:15110.3-15143.6" + process $proc$libresoc.v:15110$311 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_dec_sub26_inv_out[0:0] $1\LOGICAL_dec31_dec_sub26_inv_out[0:0] + attribute \src "libresoc.v:15111.5-15111.29" + switch \initial + attribute \src "libresoc.v:15111.9-15111.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_inv_out[0:0] 1'0 + case + assign $1\LOGICAL_dec31_dec_sub26_inv_out[0:0] 1'0 + end + sync always + update \LOGICAL_dec31_dec_sub26_inv_out $0\LOGICAL_dec31_dec_sub26_inv_out[0:0] + end + attribute \src "libresoc.v:15144.3-15177.6" + process $proc$libresoc.v:15144$312 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_dec_sub26_cry_out[0:0] $1\LOGICAL_dec31_dec_sub26_cry_out[0:0] + attribute \src "libresoc.v:15145.5-15145.29" + switch \initial + attribute \src "libresoc.v:15145.9-15145.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cry_out[0:0] 1'0 + case + assign $1\LOGICAL_dec31_dec_sub26_cry_out[0:0] 1'0 + end + sync always + update \LOGICAL_dec31_dec_sub26_cry_out $0\LOGICAL_dec31_dec_sub26_cry_out[0:0] + end + attribute \src "libresoc.v:15178.3-15211.6" + process $proc$libresoc.v:15178$313 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_dec_sub26_is_32b[0:0] $1\LOGICAL_dec31_dec_sub26_is_32b[0:0] + attribute \src "libresoc.v:15179.5-15179.29" + switch \initial + attribute \src "libresoc.v:15179.9-15179.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_is_32b[0:0] 1'0 + case + assign $1\LOGICAL_dec31_dec_sub26_is_32b[0:0] 1'0 + end + sync always + update \LOGICAL_dec31_dec_sub26_is_32b $0\LOGICAL_dec31_dec_sub26_is_32b[0:0] + end + attribute \src "libresoc.v:15212.3-15245.6" + process $proc$libresoc.v:15212$314 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_dec_sub26_sgn[0:0] $1\LOGICAL_dec31_dec_sub26_sgn[0:0] + attribute \src "libresoc.v:15213.5-15213.29" + switch \initial + attribute \src "libresoc.v:15213.9-15213.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_sgn[0:0] 1'0 + case + assign $1\LOGICAL_dec31_dec_sub26_sgn[0:0] 1'0 + end + sync always + update \LOGICAL_dec31_dec_sub26_sgn $0\LOGICAL_dec31_dec_sub26_sgn[0:0] + end + attribute \src "libresoc.v:15246.3-15279.6" + process $proc$libresoc.v:15246$315 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_dec_sub26_internal_op[6:0] $1\LOGICAL_dec31_dec_sub26_internal_op[6:0] + attribute \src "libresoc.v:15247.5-15247.29" + switch \initial + attribute \src "libresoc.v:15247.9-15247.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_internal_op[6:0] 7'0001110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_internal_op[6:0] 7'0001110 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_internal_op[6:0] 7'0001110 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_internal_op[6:0] 7'0001110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_internal_op[6:0] 7'0110110 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_internal_op[6:0] 7'0110110 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_internal_op[6:0] 7'0110110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_internal_op[6:0] 7'0110111 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_internal_op[6:0] 7'0110111 + case + assign $1\LOGICAL_dec31_dec_sub26_internal_op[6:0] 7'0000000 + end + sync always + update \LOGICAL_dec31_dec_sub26_internal_op $0\LOGICAL_dec31_dec_sub26_internal_op[6:0] + end + attribute \src "libresoc.v:15280.3-15313.6" + process $proc$libresoc.v:15280$316 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_dec_sub26_in1_sel[2:0] $1\LOGICAL_dec31_dec_sub26_in1_sel[2:0] + attribute \src "libresoc.v:15281.5-15281.29" + switch \initial + attribute \src "libresoc.v:15281.9-15281.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_in1_sel[2:0] 3'100 + case + assign $1\LOGICAL_dec31_dec_sub26_in1_sel[2:0] 3'000 + end + sync always + update \LOGICAL_dec31_dec_sub26_in1_sel $0\LOGICAL_dec31_dec_sub26_in1_sel[2:0] + end + attribute \src "libresoc.v:15314.3-15347.6" + process $proc$libresoc.v:15314$317 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_dec_sub26_in2_sel[3:0] $1\LOGICAL_dec31_dec_sub26_in2_sel[3:0] + attribute \src "libresoc.v:15315.5-15315.29" + switch \initial + attribute \src "libresoc.v:15315.9-15315.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_in2_sel[3:0] 4'0000 + case + assign $1\LOGICAL_dec31_dec_sub26_in2_sel[3:0] 4'0000 + end + sync always + update \LOGICAL_dec31_dec_sub26_in2_sel $0\LOGICAL_dec31_dec_sub26_in2_sel[3:0] + end + attribute \src "libresoc.v:15348.3-15381.6" + process $proc$libresoc.v:15348$318 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_dec_sub26_cr_in[2:0] $1\LOGICAL_dec31_dec_sub26_cr_in[2:0] + attribute \src "libresoc.v:15349.5-15349.29" + switch \initial + attribute \src "libresoc.v:15349.9-15349.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cr_in[2:0] 3'000 + case + assign $1\LOGICAL_dec31_dec_sub26_cr_in[2:0] 3'000 + end + sync always + update \LOGICAL_dec31_dec_sub26_cr_in $0\LOGICAL_dec31_dec_sub26_cr_in[2:0] + end + attribute \src "libresoc.v:15382.3-15415.6" + process $proc$libresoc.v:15382$319 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_dec_sub26_cr_out[2:0] $1\LOGICAL_dec31_dec_sub26_cr_out[2:0] + attribute \src "libresoc.v:15383.5-15383.29" + switch \initial + attribute \src "libresoc.v:15383.9-15383.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cr_out[2:0] 3'000 + case + assign $1\LOGICAL_dec31_dec_sub26_cr_out[2:0] 3'000 + end + sync always + update \LOGICAL_dec31_dec_sub26_cr_out $0\LOGICAL_dec31_dec_sub26_cr_out[2:0] + end + attribute \src "libresoc.v:15416.3-15449.6" + process $proc$libresoc.v:15416$320 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_dec_sub26_ldst_len[3:0] $1\LOGICAL_dec31_dec_sub26_ldst_len[3:0] + attribute \src "libresoc.v:15417.5-15417.29" + switch \initial + attribute \src "libresoc.v:15417.9-15417.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_ldst_len[3:0] 4'0100 + case + assign $1\LOGICAL_dec31_dec_sub26_ldst_len[3:0] 4'0000 + end + sync always + update \LOGICAL_dec31_dec_sub26_ldst_len $0\LOGICAL_dec31_dec_sub26_ldst_len[3:0] + end + attribute \src "libresoc.v:15450.3-15483.6" + process $proc$libresoc.v:15450$321 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_dec_sub26_rc_sel[1:0] $1\LOGICAL_dec31_dec_sub26_rc_sel[1:0] + attribute \src "libresoc.v:15451.5-15451.29" + switch \initial + attribute \src "libresoc.v:15451.9-15451.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_rc_sel[1:0] 2'00 + case + assign $1\LOGICAL_dec31_dec_sub26_rc_sel[1:0] 2'00 + end + sync always + update \LOGICAL_dec31_dec_sub26_rc_sel $0\LOGICAL_dec31_dec_sub26_rc_sel[1:0] + end + attribute \src "libresoc.v:15484.3-15517.6" + process $proc$libresoc.v:15484$322 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_dec_sub26_cry_in[1:0] $1\LOGICAL_dec31_dec_sub26_cry_in[1:0] + attribute \src "libresoc.v:15485.5-15485.29" + switch \initial + attribute \src "libresoc.v:15485.9-15485.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cry_in[1:0] 2'00 + case + assign $1\LOGICAL_dec31_dec_sub26_cry_in[1:0] 2'00 + end + sync always + update \LOGICAL_dec31_dec_sub26_cry_in $0\LOGICAL_dec31_dec_sub26_cry_in[1:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:15523.1-16229.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LOGICAL.dec.LOGICAL_dec31.LOGICAL_dec31_dec_sub28" +attribute \generator "nMigen" +module \LOGICAL_dec31_dec_sub28 + attribute \src "libresoc.v:16043.3-16079.6" + wire width 3 $0\LOGICAL_dec31_dec_sub28_cr_in[2:0] + attribute \src "libresoc.v:16080.3-16116.6" + wire width 3 $0\LOGICAL_dec31_dec_sub28_cr_out[2:0] + attribute \src "libresoc.v:16191.3-16227.6" + wire width 2 $0\LOGICAL_dec31_dec_sub28_cry_in[1:0] + attribute \src "libresoc.v:15821.3-15857.6" + wire $0\LOGICAL_dec31_dec_sub28_cry_out[0:0] + attribute \src "libresoc.v:15710.3-15746.6" + wire width 13 $0\LOGICAL_dec31_dec_sub28_function_unit[12:0] + attribute \src "libresoc.v:15969.3-16005.6" + wire width 3 $0\LOGICAL_dec31_dec_sub28_in1_sel[2:0] + attribute \src "libresoc.v:16006.3-16042.6" + wire width 4 $0\LOGICAL_dec31_dec_sub28_in2_sel[3:0] + attribute \src "libresoc.v:15932.3-15968.6" + wire width 7 $0\LOGICAL_dec31_dec_sub28_internal_op[6:0] + attribute \src "libresoc.v:15747.3-15783.6" + wire $0\LOGICAL_dec31_dec_sub28_inv_a[0:0] + attribute \src "libresoc.v:15784.3-15820.6" + wire $0\LOGICAL_dec31_dec_sub28_inv_out[0:0] + attribute \src "libresoc.v:15858.3-15894.6" + wire $0\LOGICAL_dec31_dec_sub28_is_32b[0:0] + attribute \src "libresoc.v:16117.3-16153.6" + wire width 4 $0\LOGICAL_dec31_dec_sub28_ldst_len[3:0] + attribute \src "libresoc.v:16154.3-16190.6" + wire width 2 $0\LOGICAL_dec31_dec_sub28_rc_sel[1:0] + attribute \src "libresoc.v:15895.3-15931.6" + wire $0\LOGICAL_dec31_dec_sub28_sgn[0:0] + attribute \src "libresoc.v:15524.7-15524.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:16043.3-16079.6" + wire width 3 $1\LOGICAL_dec31_dec_sub28_cr_in[2:0] + attribute \src "libresoc.v:16080.3-16116.6" + wire width 3 $1\LOGICAL_dec31_dec_sub28_cr_out[2:0] + attribute \src "libresoc.v:16191.3-16227.6" + wire width 2 $1\LOGICAL_dec31_dec_sub28_cry_in[1:0] + attribute \src "libresoc.v:15821.3-15857.6" + wire $1\LOGICAL_dec31_dec_sub28_cry_out[0:0] + attribute \src "libresoc.v:15710.3-15746.6" + wire width 13 $1\LOGICAL_dec31_dec_sub28_function_unit[12:0] + attribute \src "libresoc.v:15969.3-16005.6" + wire width 3 $1\LOGICAL_dec31_dec_sub28_in1_sel[2:0] + attribute \src "libresoc.v:16006.3-16042.6" + wire width 4 $1\LOGICAL_dec31_dec_sub28_in2_sel[3:0] + attribute \src "libresoc.v:15932.3-15968.6" + wire width 7 $1\LOGICAL_dec31_dec_sub28_internal_op[6:0] + attribute \src "libresoc.v:15747.3-15783.6" + wire $1\LOGICAL_dec31_dec_sub28_inv_a[0:0] + attribute \src "libresoc.v:15784.3-15820.6" + wire $1\LOGICAL_dec31_dec_sub28_inv_out[0:0] + attribute \src "libresoc.v:15858.3-15894.6" + wire $1\LOGICAL_dec31_dec_sub28_is_32b[0:0] + attribute \src "libresoc.v:16117.3-16153.6" + wire width 4 $1\LOGICAL_dec31_dec_sub28_ldst_len[3:0] + attribute \src "libresoc.v:16154.3-16190.6" + wire width 2 $1\LOGICAL_dec31_dec_sub28_rc_sel[1:0] + attribute \src "libresoc.v:15895.3-15931.6" + wire $1\LOGICAL_dec31_dec_sub28_sgn[0:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 5 \LOGICAL_dec31_dec_sub28_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 6 \LOGICAL_dec31_dec_sub28_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 9 \LOGICAL_dec31_dec_sub28_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 12 \LOGICAL_dec31_dec_sub28_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 13 output 1 \LOGICAL_dec31_dec_sub28_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 3 \LOGICAL_dec31_dec_sub28_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 4 \LOGICAL_dec31_dec_sub28_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 output 2 \LOGICAL_dec31_dec_sub28_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 10 \LOGICAL_dec31_dec_sub28_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 11 \LOGICAL_dec31_dec_sub28_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 13 \LOGICAL_dec31_dec_sub28_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 7 \LOGICAL_dec31_dec_sub28_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 8 \LOGICAL_dec31_dec_sub28_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 14 \LOGICAL_dec31_dec_sub28_sgn + attribute \src "libresoc.v:15524.7-15524.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + wire width 32 input 15 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + wire width 5 \opcode_switch + attribute \src "libresoc.v:15524.7-15524.20" + process $proc$libresoc.v:15524$338 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:15710.3-15746.6" + process $proc$libresoc.v:15710$324 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_dec_sub28_function_unit[12:0] $1\LOGICAL_dec31_dec_sub28_function_unit[12:0] + attribute \src "libresoc.v:15711.5-15711.29" + switch \initial + attribute \src "libresoc.v:15711.9-15711.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_function_unit[12:0] 13'0000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_function_unit[12:0] 13'0000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_function_unit[12:0] 13'0000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_function_unit[12:0] 13'0000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_function_unit[12:0] 13'0000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_function_unit[12:0] 13'0000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_function_unit[12:0] 13'0000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_function_unit[12:0] 13'0000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_function_unit[12:0] 13'0000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_function_unit[12:0] 13'0000000010000 + case + assign $1\LOGICAL_dec31_dec_sub28_function_unit[12:0] 13'0000000000000 + end + sync always + update \LOGICAL_dec31_dec_sub28_function_unit $0\LOGICAL_dec31_dec_sub28_function_unit[12:0] + end + attribute \src "libresoc.v:15747.3-15783.6" + process $proc$libresoc.v:15747$325 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_dec_sub28_inv_a[0:0] $1\LOGICAL_dec31_dec_sub28_inv_a[0:0] + attribute \src "libresoc.v:15748.5-15748.29" + switch \initial + attribute \src "libresoc.v:15748.9-15748.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_inv_a[0:0] 1'0 + case + assign $1\LOGICAL_dec31_dec_sub28_inv_a[0:0] 1'0 + end + sync always + update \LOGICAL_dec31_dec_sub28_inv_a $0\LOGICAL_dec31_dec_sub28_inv_a[0:0] + end + attribute \src "libresoc.v:15784.3-15820.6" + process $proc$libresoc.v:15784$326 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_dec_sub28_inv_out[0:0] $1\LOGICAL_dec31_dec_sub28_inv_out[0:0] + attribute \src "libresoc.v:15785.5-15785.29" + switch \initial + attribute \src "libresoc.v:15785.9-15785.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_inv_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_inv_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_inv_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_inv_out[0:0] 1'0 + case + assign $1\LOGICAL_dec31_dec_sub28_inv_out[0:0] 1'0 + end + sync always + update \LOGICAL_dec31_dec_sub28_inv_out $0\LOGICAL_dec31_dec_sub28_inv_out[0:0] + end + attribute \src "libresoc.v:15821.3-15857.6" + process $proc$libresoc.v:15821$327 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_dec_sub28_cry_out[0:0] $1\LOGICAL_dec31_dec_sub28_cry_out[0:0] + attribute \src "libresoc.v:15822.5-15822.29" + switch \initial + attribute \src "libresoc.v:15822.9-15822.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cry_out[0:0] 1'0 + case + assign $1\LOGICAL_dec31_dec_sub28_cry_out[0:0] 1'0 + end + sync always + update \LOGICAL_dec31_dec_sub28_cry_out $0\LOGICAL_dec31_dec_sub28_cry_out[0:0] + end + attribute \src "libresoc.v:15858.3-15894.6" + process $proc$libresoc.v:15858$328 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_dec_sub28_is_32b[0:0] $1\LOGICAL_dec31_dec_sub28_is_32b[0:0] + attribute \src "libresoc.v:15859.5-15859.29" + switch \initial + attribute \src "libresoc.v:15859.9-15859.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_is_32b[0:0] 1'0 + case + assign $1\LOGICAL_dec31_dec_sub28_is_32b[0:0] 1'0 + end + sync always + update \LOGICAL_dec31_dec_sub28_is_32b $0\LOGICAL_dec31_dec_sub28_is_32b[0:0] + end + attribute \src "libresoc.v:15895.3-15931.6" + process $proc$libresoc.v:15895$329 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_dec_sub28_sgn[0:0] $1\LOGICAL_dec31_dec_sub28_sgn[0:0] + attribute \src "libresoc.v:15896.5-15896.29" + switch \initial + attribute \src "libresoc.v:15896.9-15896.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_sgn[0:0] 1'0 + case + assign $1\LOGICAL_dec31_dec_sub28_sgn[0:0] 1'0 + end + sync always + update \LOGICAL_dec31_dec_sub28_sgn $0\LOGICAL_dec31_dec_sub28_sgn[0:0] + end + attribute \src "libresoc.v:15932.3-15968.6" + process $proc$libresoc.v:15932$330 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_dec_sub28_internal_op[6:0] $1\LOGICAL_dec31_dec_sub28_internal_op[6:0] + attribute \src "libresoc.v:15933.5-15933.29" + switch \initial + attribute \src "libresoc.v:15933.9-15933.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_internal_op[6:0] 7'0000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_internal_op[6:0] 7'0000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_internal_op[6:0] 7'0001001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_internal_op[6:0] 7'0001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_internal_op[6:0] 7'1000011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_internal_op[6:0] 7'0000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_internal_op[6:0] 7'0110101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_internal_op[6:0] 7'0110101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_internal_op[6:0] 7'0110101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_internal_op[6:0] 7'1000011 + case + assign $1\LOGICAL_dec31_dec_sub28_internal_op[6:0] 7'0000000 + end + sync always + update \LOGICAL_dec31_dec_sub28_internal_op $0\LOGICAL_dec31_dec_sub28_internal_op[6:0] + end + attribute \src "libresoc.v:15969.3-16005.6" + process $proc$libresoc.v:15969$331 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_dec_sub28_in1_sel[2:0] $1\LOGICAL_dec31_dec_sub28_in1_sel[2:0] + attribute \src "libresoc.v:15970.5-15970.29" + switch \initial + attribute \src "libresoc.v:15970.9-15970.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_in1_sel[2:0] 3'100 + case + assign $1\LOGICAL_dec31_dec_sub28_in1_sel[2:0] 3'000 + end + sync always + update \LOGICAL_dec31_dec_sub28_in1_sel $0\LOGICAL_dec31_dec_sub28_in1_sel[2:0] + end + attribute \src "libresoc.v:16006.3-16042.6" + process $proc$libresoc.v:16006$332 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_dec_sub28_in2_sel[3:0] $1\LOGICAL_dec31_dec_sub28_in2_sel[3:0] + attribute \src "libresoc.v:16007.5-16007.29" + switch \initial + attribute \src "libresoc.v:16007.9-16007.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_in2_sel[3:0] 4'0001 + case + assign $1\LOGICAL_dec31_dec_sub28_in2_sel[3:0] 4'0000 + end + sync always + update \LOGICAL_dec31_dec_sub28_in2_sel $0\LOGICAL_dec31_dec_sub28_in2_sel[3:0] + end + attribute \src "libresoc.v:16043.3-16079.6" + process $proc$libresoc.v:16043$333 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_dec_sub28_cr_in[2:0] $1\LOGICAL_dec31_dec_sub28_cr_in[2:0] + attribute \src "libresoc.v:16044.5-16044.29" + switch \initial + attribute \src "libresoc.v:16044.9-16044.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cr_in[2:0] 3'000 + case + assign $1\LOGICAL_dec31_dec_sub28_cr_in[2:0] 3'000 + end + sync always + update \LOGICAL_dec31_dec_sub28_cr_in $0\LOGICAL_dec31_dec_sub28_cr_in[2:0] + end + attribute \src "libresoc.v:16080.3-16116.6" + process $proc$libresoc.v:16080$334 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_dec_sub28_cr_out[2:0] $1\LOGICAL_dec31_dec_sub28_cr_out[2:0] + attribute \src "libresoc.v:16081.5-16081.29" + switch \initial + attribute \src "libresoc.v:16081.9-16081.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cr_out[2:0] 3'001 + case + assign $1\LOGICAL_dec31_dec_sub28_cr_out[2:0] 3'000 + end + sync always + update \LOGICAL_dec31_dec_sub28_cr_out $0\LOGICAL_dec31_dec_sub28_cr_out[2:0] + end + attribute \src "libresoc.v:16117.3-16153.6" + process $proc$libresoc.v:16117$335 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_dec_sub28_ldst_len[3:0] $1\LOGICAL_dec31_dec_sub28_ldst_len[3:0] + attribute \src "libresoc.v:16118.5-16118.29" + switch \initial + attribute \src "libresoc.v:16118.9-16118.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_ldst_len[3:0] 4'0000 + case + assign $1\LOGICAL_dec31_dec_sub28_ldst_len[3:0] 4'0000 + end + sync always + update \LOGICAL_dec31_dec_sub28_ldst_len $0\LOGICAL_dec31_dec_sub28_ldst_len[3:0] + end + attribute \src "libresoc.v:16154.3-16190.6" + process $proc$libresoc.v:16154$336 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_dec_sub28_rc_sel[1:0] $1\LOGICAL_dec31_dec_sub28_rc_sel[1:0] + attribute \src "libresoc.v:16155.5-16155.29" + switch \initial + attribute \src "libresoc.v:16155.9-16155.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_rc_sel[1:0] 2'10 + case + assign $1\LOGICAL_dec31_dec_sub28_rc_sel[1:0] 2'00 + end + sync always + update \LOGICAL_dec31_dec_sub28_rc_sel $0\LOGICAL_dec31_dec_sub28_rc_sel[1:0] + end + attribute \src "libresoc.v:16191.3-16227.6" + process $proc$libresoc.v:16191$337 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_dec_sub28_cry_in[1:0] $1\LOGICAL_dec31_dec_sub28_cry_in[1:0] + attribute \src "libresoc.v:16192.5-16192.29" + switch \initial + attribute \src "libresoc.v:16192.9-16192.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cry_in[1:0] 2'00 + case + assign $1\LOGICAL_dec31_dec_sub28_cry_in[1:0] 2'00 + end + sync always + update \LOGICAL_dec31_dec_sub28_cry_in $0\LOGICAL_dec31_dec_sub28_cry_in[1:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:16233.1-16800.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_MUL.dec.MUL_dec31" +attribute \generator "nMigen" +module \MUL_dec31 + attribute \src "libresoc.v:16757.3-16769.6" + wire width 3 $0\MUL_dec31_cr_in[2:0] + attribute \src "libresoc.v:16770.3-16782.6" + wire width 3 $0\MUL_dec31_cr_out[2:0] + attribute \src "libresoc.v:16718.3-16730.6" + wire width 13 $0\MUL_dec31_function_unit[12:0] + attribute \src "libresoc.v:16744.3-16756.6" + wire width 4 $0\MUL_dec31_in2_sel[3:0] + attribute \src "libresoc.v:16731.3-16743.6" + wire width 7 $0\MUL_dec31_internal_op[6:0] + attribute \src "libresoc.v:16692.3-16704.6" + wire $0\MUL_dec31_is_32b[0:0] + attribute \src "libresoc.v:16783.3-16795.6" + wire width 2 $0\MUL_dec31_rc_sel[1:0] + attribute \src "libresoc.v:16705.3-16717.6" + wire $0\MUL_dec31_sgn[0:0] + attribute \src "libresoc.v:16234.7-16234.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:16757.3-16769.6" + wire width 3 $1\MUL_dec31_cr_in[2:0] + attribute \src "libresoc.v:16770.3-16782.6" + wire width 3 $1\MUL_dec31_cr_out[2:0] + attribute \src "libresoc.v:16718.3-16730.6" + wire width 13 $1\MUL_dec31_function_unit[12:0] + attribute \src "libresoc.v:16744.3-16756.6" + wire width 4 $1\MUL_dec31_in2_sel[3:0] + attribute \src "libresoc.v:16731.3-16743.6" + wire width 7 $1\MUL_dec31_internal_op[6:0] + attribute \src "libresoc.v:16692.3-16704.6" + wire $1\MUL_dec31_is_32b[0:0] + attribute \src "libresoc.v:16783.3-16795.6" + wire width 2 $1\MUL_dec31_rc_sel[1:0] + attribute \src "libresoc.v:16705.3-16717.6" + wire $1\MUL_dec31_sgn[0:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 4 \MUL_dec31_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 5 \MUL_dec31_cr_out + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 13 \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_function_unit + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_is_32b + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + wire width 32 \MUL_dec31_dec_sub11_opcode_in + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 13 \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_function_unit + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_is_32b + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + wire width 32 \MUL_dec31_dec_sub9_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 13 output 1 \MUL_dec31_function_unit + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 3 \MUL_dec31_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 output 2 \MUL_dec31_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 7 \MUL_dec31_is_32b + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 6 \MUL_dec31_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 8 \MUL_dec31_sgn + attribute \src "libresoc.v:16234.7-16234.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:347" + wire width 5 \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + wire width 32 input 9 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + wire width 10 \opcode_switch + attribute \module_not_derived 1 + attribute \src "libresoc.v:16670.23-16680.4" + cell \MUL_dec31_dec_sub11 \MUL_dec31_dec_sub11 + connect \MUL_dec31_dec_sub11_cr_in \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_cr_in + connect \MUL_dec31_dec_sub11_cr_out \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_cr_out + connect \MUL_dec31_dec_sub11_function_unit \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_function_unit + connect \MUL_dec31_dec_sub11_in2_sel \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_in2_sel + connect \MUL_dec31_dec_sub11_internal_op \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_internal_op + connect \MUL_dec31_dec_sub11_is_32b \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_is_32b + connect \MUL_dec31_dec_sub11_rc_sel \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_rc_sel + connect \MUL_dec31_dec_sub11_sgn \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_sgn + connect \opcode_in \MUL_dec31_dec_sub11_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:16681.22-16691.4" + cell \MUL_dec31_dec_sub9 \MUL_dec31_dec_sub9 + connect \MUL_dec31_dec_sub9_cr_in \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_cr_in + connect \MUL_dec31_dec_sub9_cr_out \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_cr_out + connect \MUL_dec31_dec_sub9_function_unit \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_function_unit + connect \MUL_dec31_dec_sub9_in2_sel \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_in2_sel + connect \MUL_dec31_dec_sub9_internal_op \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_internal_op + connect \MUL_dec31_dec_sub9_is_32b \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_is_32b + connect \MUL_dec31_dec_sub9_rc_sel \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_rc_sel + connect \MUL_dec31_dec_sub9_sgn \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_sgn + connect \opcode_in \MUL_dec31_dec_sub9_opcode_in + end + attribute \src "libresoc.v:16234.7-16234.20" + process $proc$libresoc.v:16234$347 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:16692.3-16704.6" + process $proc$libresoc.v:16692$339 + assign { } { } + assign { } { } + assign $0\MUL_dec31_is_32b[0:0] $1\MUL_dec31_is_32b[0:0] + attribute \src "libresoc.v:16693.5-16693.29" + switch \initial + attribute \src "libresoc.v:16693.9-16693.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\MUL_dec31_is_32b[0:0] \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\MUL_dec31_is_32b[0:0] \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_is_32b + case + assign $1\MUL_dec31_is_32b[0:0] 1'0 + end + sync always + update \MUL_dec31_is_32b $0\MUL_dec31_is_32b[0:0] + end + attribute \src "libresoc.v:16705.3-16717.6" + process $proc$libresoc.v:16705$340 + assign { } { } + assign { } { } + assign $0\MUL_dec31_sgn[0:0] $1\MUL_dec31_sgn[0:0] + attribute \src "libresoc.v:16706.5-16706.29" + switch \initial + attribute \src "libresoc.v:16706.9-16706.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\MUL_dec31_sgn[0:0] \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\MUL_dec31_sgn[0:0] \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_sgn + case + assign $1\MUL_dec31_sgn[0:0] 1'0 + end + sync always + update \MUL_dec31_sgn $0\MUL_dec31_sgn[0:0] + end + attribute \src "libresoc.v:16718.3-16730.6" + process $proc$libresoc.v:16718$341 + assign { } { } + assign { } { } + assign $0\MUL_dec31_function_unit[12:0] $1\MUL_dec31_function_unit[12:0] + attribute \src "libresoc.v:16719.5-16719.29" + switch \initial + attribute \src "libresoc.v:16719.9-16719.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\MUL_dec31_function_unit[12:0] \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\MUL_dec31_function_unit[12:0] \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_function_unit + case + assign $1\MUL_dec31_function_unit[12:0] 13'0000000000000 + end + sync always + update \MUL_dec31_function_unit $0\MUL_dec31_function_unit[12:0] + end + attribute \src "libresoc.v:16731.3-16743.6" + process $proc$libresoc.v:16731$342 + assign { } { } + assign { } { } + assign $0\MUL_dec31_internal_op[6:0] $1\MUL_dec31_internal_op[6:0] + attribute \src "libresoc.v:16732.5-16732.29" + switch \initial + attribute \src "libresoc.v:16732.9-16732.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\MUL_dec31_internal_op[6:0] \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\MUL_dec31_internal_op[6:0] \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_internal_op + case + assign $1\MUL_dec31_internal_op[6:0] 7'0000000 + end + sync always + update \MUL_dec31_internal_op $0\MUL_dec31_internal_op[6:0] + end + attribute \src "libresoc.v:16744.3-16756.6" + process $proc$libresoc.v:16744$343 + assign { } { } + assign { } { } + assign $0\MUL_dec31_in2_sel[3:0] $1\MUL_dec31_in2_sel[3:0] + attribute \src "libresoc.v:16745.5-16745.29" + switch \initial + attribute \src "libresoc.v:16745.9-16745.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\MUL_dec31_in2_sel[3:0] \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\MUL_dec31_in2_sel[3:0] \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_in2_sel + case + assign $1\MUL_dec31_in2_sel[3:0] 4'0000 + end + sync always + update \MUL_dec31_in2_sel $0\MUL_dec31_in2_sel[3:0] + end + attribute \src "libresoc.v:16757.3-16769.6" + process $proc$libresoc.v:16757$344 + assign { } { } + assign { } { } + assign $0\MUL_dec31_cr_in[2:0] $1\MUL_dec31_cr_in[2:0] + attribute \src "libresoc.v:16758.5-16758.29" + switch \initial + attribute \src "libresoc.v:16758.9-16758.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\MUL_dec31_cr_in[2:0] \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\MUL_dec31_cr_in[2:0] \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_cr_in + case + assign $1\MUL_dec31_cr_in[2:0] 3'000 + end + sync always + update \MUL_dec31_cr_in $0\MUL_dec31_cr_in[2:0] + end + attribute \src "libresoc.v:16770.3-16782.6" + process $proc$libresoc.v:16770$345 + assign { } { } + assign { } { } + assign $0\MUL_dec31_cr_out[2:0] $1\MUL_dec31_cr_out[2:0] + attribute \src "libresoc.v:16771.5-16771.29" + switch \initial + attribute \src "libresoc.v:16771.9-16771.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\MUL_dec31_cr_out[2:0] \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\MUL_dec31_cr_out[2:0] \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_cr_out + case + assign $1\MUL_dec31_cr_out[2:0] 3'000 + end + sync always + update \MUL_dec31_cr_out $0\MUL_dec31_cr_out[2:0] + end + attribute \src "libresoc.v:16783.3-16795.6" + process $proc$libresoc.v:16783$346 + assign { } { } + assign { } { } + assign $0\MUL_dec31_rc_sel[1:0] $1\MUL_dec31_rc_sel[1:0] + attribute \src "libresoc.v:16784.5-16784.29" + switch \initial + attribute \src "libresoc.v:16784.9-16784.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\MUL_dec31_rc_sel[1:0] \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\MUL_dec31_rc_sel[1:0] \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_rc_sel + case + assign $1\MUL_dec31_rc_sel[1:0] 2'00 + end + sync always + update \MUL_dec31_rc_sel $0\MUL_dec31_rc_sel[1:0] + end + connect \MUL_dec31_dec_sub11_opcode_in \opcode_in + connect \MUL_dec31_dec_sub9_opcode_in \opcode_in + connect \opc_in \opcode_switch [4:0] + connect \opcode_switch \opcode_in [10:1] +end +attribute \src "libresoc.v:16804.1-17158.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_MUL.dec.MUL_dec31.MUL_dec31_dec_sub11" +attribute \generator "nMigen" +module \MUL_dec31_dec_sub11 + attribute \src "libresoc.v:17032.3-17056.6" + wire width 3 $0\MUL_dec31_dec_sub11_cr_in[2:0] + attribute \src "libresoc.v:17057.3-17081.6" + wire width 3 $0\MUL_dec31_dec_sub11_cr_out[2:0] + attribute \src "libresoc.v:16957.3-16981.6" + wire width 13 $0\MUL_dec31_dec_sub11_function_unit[12:0] + attribute \src "libresoc.v:17007.3-17031.6" + wire width 4 $0\MUL_dec31_dec_sub11_in2_sel[3:0] + attribute \src "libresoc.v:16982.3-17006.6" + wire width 7 $0\MUL_dec31_dec_sub11_internal_op[6:0] + attribute \src "libresoc.v:17107.3-17131.6" + wire $0\MUL_dec31_dec_sub11_is_32b[0:0] + attribute \src "libresoc.v:17082.3-17106.6" + wire width 2 $0\MUL_dec31_dec_sub11_rc_sel[1:0] + attribute \src "libresoc.v:17132.3-17156.6" + wire $0\MUL_dec31_dec_sub11_sgn[0:0] + attribute \src "libresoc.v:16805.7-16805.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:17032.3-17056.6" + wire width 3 $1\MUL_dec31_dec_sub11_cr_in[2:0] + attribute \src "libresoc.v:17057.3-17081.6" + wire width 3 $1\MUL_dec31_dec_sub11_cr_out[2:0] + attribute \src "libresoc.v:16957.3-16981.6" + wire width 13 $1\MUL_dec31_dec_sub11_function_unit[12:0] + attribute \src "libresoc.v:17007.3-17031.6" + wire width 4 $1\MUL_dec31_dec_sub11_in2_sel[3:0] + attribute \src "libresoc.v:16982.3-17006.6" + wire width 7 $1\MUL_dec31_dec_sub11_internal_op[6:0] + attribute \src "libresoc.v:17107.3-17131.6" + wire $1\MUL_dec31_dec_sub11_is_32b[0:0] + attribute \src "libresoc.v:17082.3-17106.6" + wire width 2 $1\MUL_dec31_dec_sub11_rc_sel[1:0] + attribute \src "libresoc.v:17132.3-17156.6" + wire $1\MUL_dec31_dec_sub11_sgn[0:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 4 \MUL_dec31_dec_sub11_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 5 \MUL_dec31_dec_sub11_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 13 output 1 \MUL_dec31_dec_sub11_function_unit + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 3 \MUL_dec31_dec_sub11_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 output 2 \MUL_dec31_dec_sub11_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 7 \MUL_dec31_dec_sub11_is_32b + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 6 \MUL_dec31_dec_sub11_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 8 \MUL_dec31_dec_sub11_sgn + attribute \src "libresoc.v:16805.7-16805.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + wire width 32 input 9 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + wire width 5 \opcode_switch + attribute \src "libresoc.v:16805.7-16805.20" + process $proc$libresoc.v:16805$356 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:16957.3-16981.6" + process $proc$libresoc.v:16957$348 + assign { } { } + assign { } { } + assign $0\MUL_dec31_dec_sub11_function_unit[12:0] $1\MUL_dec31_dec_sub11_function_unit[12:0] + attribute \src "libresoc.v:16958.5-16958.29" + switch \initial + attribute \src "libresoc.v:16958.9-16958.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\MUL_dec31_dec_sub11_function_unit[12:0] 13'0000100000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\MUL_dec31_dec_sub11_function_unit[12:0] 13'0000100000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\MUL_dec31_dec_sub11_function_unit[12:0] 13'0000100000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\MUL_dec31_dec_sub11_function_unit[12:0] 13'0000100000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\MUL_dec31_dec_sub11_function_unit[12:0] 13'0000100000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\MUL_dec31_dec_sub11_function_unit[12:0] 13'0000100000000 + case + assign $1\MUL_dec31_dec_sub11_function_unit[12:0] 13'0000000000000 + end + sync always + update \MUL_dec31_dec_sub11_function_unit $0\MUL_dec31_dec_sub11_function_unit[12:0] + end + attribute \src "libresoc.v:16982.3-17006.6" + process $proc$libresoc.v:16982$349 + assign { } { } + assign { } { } + assign $0\MUL_dec31_dec_sub11_internal_op[6:0] $1\MUL_dec31_dec_sub11_internal_op[6:0] + attribute \src "libresoc.v:16983.5-16983.29" + switch \initial + attribute \src "libresoc.v:16983.9-16983.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\MUL_dec31_dec_sub11_internal_op[6:0] 7'0110100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\MUL_dec31_dec_sub11_internal_op[6:0] 7'0110100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\MUL_dec31_dec_sub11_internal_op[6:0] 7'0110100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\MUL_dec31_dec_sub11_internal_op[6:0] 7'0110100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\MUL_dec31_dec_sub11_internal_op[6:0] 7'0110010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\MUL_dec31_dec_sub11_internal_op[6:0] 7'0110010 + case + assign $1\MUL_dec31_dec_sub11_internal_op[6:0] 7'0000000 + end + sync always + update \MUL_dec31_dec_sub11_internal_op $0\MUL_dec31_dec_sub11_internal_op[6:0] + end + attribute \src "libresoc.v:17007.3-17031.6" + process $proc$libresoc.v:17007$350 + assign { } { } + assign { } { } + assign $0\MUL_dec31_dec_sub11_in2_sel[3:0] $1\MUL_dec31_dec_sub11_in2_sel[3:0] + attribute \src "libresoc.v:17008.5-17008.29" + switch \initial + attribute \src "libresoc.v:17008.9-17008.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\MUL_dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\MUL_dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\MUL_dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\MUL_dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\MUL_dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\MUL_dec31_dec_sub11_in2_sel[3:0] 4'0001 + case + assign $1\MUL_dec31_dec_sub11_in2_sel[3:0] 4'0000 + end + sync always + update \MUL_dec31_dec_sub11_in2_sel $0\MUL_dec31_dec_sub11_in2_sel[3:0] + end + attribute \src "libresoc.v:17032.3-17056.6" + process $proc$libresoc.v:17032$351 + assign { } { } + assign { } { } + assign $0\MUL_dec31_dec_sub11_cr_in[2:0] $1\MUL_dec31_dec_sub11_cr_in[2:0] + attribute \src "libresoc.v:17033.5-17033.29" + switch \initial + attribute \src "libresoc.v:17033.9-17033.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\MUL_dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\MUL_dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\MUL_dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\MUL_dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\MUL_dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\MUL_dec31_dec_sub11_cr_in[2:0] 3'000 + case + assign $1\MUL_dec31_dec_sub11_cr_in[2:0] 3'000 + end + sync always + update \MUL_dec31_dec_sub11_cr_in $0\MUL_dec31_dec_sub11_cr_in[2:0] + end + attribute \src "libresoc.v:17057.3-17081.6" + process $proc$libresoc.v:17057$352 + assign { } { } + assign { } { } + assign $0\MUL_dec31_dec_sub11_cr_out[2:0] $1\MUL_dec31_dec_sub11_cr_out[2:0] + attribute \src "libresoc.v:17058.5-17058.29" + switch \initial + attribute \src "libresoc.v:17058.9-17058.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\MUL_dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\MUL_dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\MUL_dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\MUL_dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\MUL_dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\MUL_dec31_dec_sub11_cr_out[2:0] 3'001 + case + assign $1\MUL_dec31_dec_sub11_cr_out[2:0] 3'000 + end + sync always + update \MUL_dec31_dec_sub11_cr_out $0\MUL_dec31_dec_sub11_cr_out[2:0] + end + attribute \src "libresoc.v:17082.3-17106.6" + process $proc$libresoc.v:17082$353 + assign { } { } + assign { } { } + assign $0\MUL_dec31_dec_sub11_rc_sel[1:0] $1\MUL_dec31_dec_sub11_rc_sel[1:0] + attribute \src "libresoc.v:17083.5-17083.29" + switch \initial + attribute \src "libresoc.v:17083.9-17083.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\MUL_dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\MUL_dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\MUL_dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\MUL_dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\MUL_dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\MUL_dec31_dec_sub11_rc_sel[1:0] 2'10 + case + assign $1\MUL_dec31_dec_sub11_rc_sel[1:0] 2'00 + end + sync always + update \MUL_dec31_dec_sub11_rc_sel $0\MUL_dec31_dec_sub11_rc_sel[1:0] + end + attribute \src "libresoc.v:17107.3-17131.6" + process $proc$libresoc.v:17107$354 + assign { } { } + assign { } { } + assign $0\MUL_dec31_dec_sub11_is_32b[0:0] $1\MUL_dec31_dec_sub11_is_32b[0:0] + attribute \src "libresoc.v:17108.5-17108.29" + switch \initial + attribute \src "libresoc.v:17108.9-17108.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\MUL_dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\MUL_dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\MUL_dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\MUL_dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\MUL_dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\MUL_dec31_dec_sub11_is_32b[0:0] 1'1 + case + assign $1\MUL_dec31_dec_sub11_is_32b[0:0] 1'0 + end + sync always + update \MUL_dec31_dec_sub11_is_32b $0\MUL_dec31_dec_sub11_is_32b[0:0] + end + attribute \src "libresoc.v:17132.3-17156.6" + process $proc$libresoc.v:17132$355 + assign { } { } + assign { } { } + assign $0\MUL_dec31_dec_sub11_sgn[0:0] $1\MUL_dec31_dec_sub11_sgn[0:0] + attribute \src "libresoc.v:17133.5-17133.29" + switch \initial + attribute \src "libresoc.v:17133.9-17133.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\MUL_dec31_dec_sub11_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\MUL_dec31_dec_sub11_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\MUL_dec31_dec_sub11_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\MUL_dec31_dec_sub11_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\MUL_dec31_dec_sub11_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\MUL_dec31_dec_sub11_sgn[0:0] 1'1 + case + assign $1\MUL_dec31_dec_sub11_sgn[0:0] 1'0 + end + sync always + update \MUL_dec31_dec_sub11_sgn $0\MUL_dec31_dec_sub11_sgn[0:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:17162.1-17516.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_MUL.dec.MUL_dec31.MUL_dec31_dec_sub9" +attribute \generator "nMigen" +module \MUL_dec31_dec_sub9 + attribute \src "libresoc.v:17390.3-17414.6" + wire width 3 $0\MUL_dec31_dec_sub9_cr_in[2:0] + attribute \src "libresoc.v:17415.3-17439.6" + wire width 3 $0\MUL_dec31_dec_sub9_cr_out[2:0] + attribute \src "libresoc.v:17315.3-17339.6" + wire width 13 $0\MUL_dec31_dec_sub9_function_unit[12:0] + attribute \src "libresoc.v:17365.3-17389.6" + wire width 4 $0\MUL_dec31_dec_sub9_in2_sel[3:0] + attribute \src "libresoc.v:17340.3-17364.6" + wire width 7 $0\MUL_dec31_dec_sub9_internal_op[6:0] + attribute \src "libresoc.v:17465.3-17489.6" + wire $0\MUL_dec31_dec_sub9_is_32b[0:0] + attribute \src "libresoc.v:17440.3-17464.6" + wire width 2 $0\MUL_dec31_dec_sub9_rc_sel[1:0] + attribute \src "libresoc.v:17490.3-17514.6" + wire $0\MUL_dec31_dec_sub9_sgn[0:0] + attribute \src "libresoc.v:17163.7-17163.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:17390.3-17414.6" + wire width 3 $1\MUL_dec31_dec_sub9_cr_in[2:0] + attribute \src "libresoc.v:17415.3-17439.6" + wire width 3 $1\MUL_dec31_dec_sub9_cr_out[2:0] + attribute \src "libresoc.v:17315.3-17339.6" + wire width 13 $1\MUL_dec31_dec_sub9_function_unit[12:0] + attribute \src "libresoc.v:17365.3-17389.6" + wire width 4 $1\MUL_dec31_dec_sub9_in2_sel[3:0] + attribute \src "libresoc.v:17340.3-17364.6" + wire width 7 $1\MUL_dec31_dec_sub9_internal_op[6:0] + attribute \src "libresoc.v:17465.3-17489.6" + wire $1\MUL_dec31_dec_sub9_is_32b[0:0] + attribute \src "libresoc.v:17440.3-17464.6" + wire width 2 $1\MUL_dec31_dec_sub9_rc_sel[1:0] + attribute \src "libresoc.v:17490.3-17514.6" + wire $1\MUL_dec31_dec_sub9_sgn[0:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 4 \MUL_dec31_dec_sub9_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 5 \MUL_dec31_dec_sub9_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 13 output 1 \MUL_dec31_dec_sub9_function_unit + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 3 \MUL_dec31_dec_sub9_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 output 2 \MUL_dec31_dec_sub9_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 7 \MUL_dec31_dec_sub9_is_32b + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 6 \MUL_dec31_dec_sub9_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 8 \MUL_dec31_dec_sub9_sgn + attribute \src "libresoc.v:17163.7-17163.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + wire width 32 input 9 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + wire width 5 \opcode_switch + attribute \src "libresoc.v:17163.7-17163.20" + process $proc$libresoc.v:17163$365 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:17315.3-17339.6" + process $proc$libresoc.v:17315$357 + assign { } { } + assign { } { } + assign $0\MUL_dec31_dec_sub9_function_unit[12:0] $1\MUL_dec31_dec_sub9_function_unit[12:0] + attribute \src "libresoc.v:17316.5-17316.29" + switch \initial + attribute \src "libresoc.v:17316.9-17316.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\MUL_dec31_dec_sub9_function_unit[12:0] 13'0000100000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\MUL_dec31_dec_sub9_function_unit[12:0] 13'0000100000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\MUL_dec31_dec_sub9_function_unit[12:0] 13'0000100000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\MUL_dec31_dec_sub9_function_unit[12:0] 13'0000100000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\MUL_dec31_dec_sub9_function_unit[12:0] 13'0000100000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\MUL_dec31_dec_sub9_function_unit[12:0] 13'0000100000000 + case + assign $1\MUL_dec31_dec_sub9_function_unit[12:0] 13'0000000000000 + end + sync always + update \MUL_dec31_dec_sub9_function_unit $0\MUL_dec31_dec_sub9_function_unit[12:0] + end + attribute \src "libresoc.v:17340.3-17364.6" + process $proc$libresoc.v:17340$358 + assign { } { } + assign { } { } + assign $0\MUL_dec31_dec_sub9_internal_op[6:0] $1\MUL_dec31_dec_sub9_internal_op[6:0] + attribute \src "libresoc.v:17341.5-17341.29" + switch \initial + attribute \src "libresoc.v:17341.9-17341.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\MUL_dec31_dec_sub9_internal_op[6:0] 7'0110011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\MUL_dec31_dec_sub9_internal_op[6:0] 7'0110011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\MUL_dec31_dec_sub9_internal_op[6:0] 7'0110011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\MUL_dec31_dec_sub9_internal_op[6:0] 7'0110011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\MUL_dec31_dec_sub9_internal_op[6:0] 7'0110010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\MUL_dec31_dec_sub9_internal_op[6:0] 7'0110010 + case + assign $1\MUL_dec31_dec_sub9_internal_op[6:0] 7'0000000 + end + sync always + update \MUL_dec31_dec_sub9_internal_op $0\MUL_dec31_dec_sub9_internal_op[6:0] + end + attribute \src "libresoc.v:17365.3-17389.6" + process $proc$libresoc.v:17365$359 + assign { } { } + assign { } { } + assign $0\MUL_dec31_dec_sub9_in2_sel[3:0] $1\MUL_dec31_dec_sub9_in2_sel[3:0] + attribute \src "libresoc.v:17366.5-17366.29" + switch \initial + attribute \src "libresoc.v:17366.9-17366.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\MUL_dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\MUL_dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\MUL_dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\MUL_dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\MUL_dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\MUL_dec31_dec_sub9_in2_sel[3:0] 4'0001 + case + assign $1\MUL_dec31_dec_sub9_in2_sel[3:0] 4'0000 + end + sync always + update \MUL_dec31_dec_sub9_in2_sel $0\MUL_dec31_dec_sub9_in2_sel[3:0] + end + attribute \src "libresoc.v:17390.3-17414.6" + process $proc$libresoc.v:17390$360 + assign { } { } + assign { } { } + assign $0\MUL_dec31_dec_sub9_cr_in[2:0] $1\MUL_dec31_dec_sub9_cr_in[2:0] + attribute \src "libresoc.v:17391.5-17391.29" + switch \initial + attribute \src "libresoc.v:17391.9-17391.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\MUL_dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\MUL_dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\MUL_dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\MUL_dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\MUL_dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\MUL_dec31_dec_sub9_cr_in[2:0] 3'000 + case + assign $1\MUL_dec31_dec_sub9_cr_in[2:0] 3'000 + end + sync always + update \MUL_dec31_dec_sub9_cr_in $0\MUL_dec31_dec_sub9_cr_in[2:0] + end + attribute \src "libresoc.v:17415.3-17439.6" + process $proc$libresoc.v:17415$361 + assign { } { } + assign { } { } + assign $0\MUL_dec31_dec_sub9_cr_out[2:0] $1\MUL_dec31_dec_sub9_cr_out[2:0] + attribute \src "libresoc.v:17416.5-17416.29" + switch \initial + attribute \src "libresoc.v:17416.9-17416.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\MUL_dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\MUL_dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\MUL_dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\MUL_dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\MUL_dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\MUL_dec31_dec_sub9_cr_out[2:0] 3'001 + case + assign $1\MUL_dec31_dec_sub9_cr_out[2:0] 3'000 + end + sync always + update \MUL_dec31_dec_sub9_cr_out $0\MUL_dec31_dec_sub9_cr_out[2:0] + end + attribute \src "libresoc.v:17440.3-17464.6" + process $proc$libresoc.v:17440$362 + assign { } { } + assign { } { } + assign $0\MUL_dec31_dec_sub9_rc_sel[1:0] $1\MUL_dec31_dec_sub9_rc_sel[1:0] + attribute \src "libresoc.v:17441.5-17441.29" + switch \initial + attribute \src "libresoc.v:17441.9-17441.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\MUL_dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\MUL_dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\MUL_dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\MUL_dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\MUL_dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\MUL_dec31_dec_sub9_rc_sel[1:0] 2'10 + case + assign $1\MUL_dec31_dec_sub9_rc_sel[1:0] 2'00 + end + sync always + update \MUL_dec31_dec_sub9_rc_sel $0\MUL_dec31_dec_sub9_rc_sel[1:0] + end + attribute \src "libresoc.v:17465.3-17489.6" + process $proc$libresoc.v:17465$363 + assign { } { } + assign { } { } + assign $0\MUL_dec31_dec_sub9_is_32b[0:0] $1\MUL_dec31_dec_sub9_is_32b[0:0] + attribute \src "libresoc.v:17466.5-17466.29" + switch \initial + attribute \src "libresoc.v:17466.9-17466.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\MUL_dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\MUL_dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\MUL_dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\MUL_dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\MUL_dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\MUL_dec31_dec_sub9_is_32b[0:0] 1'0 + case + assign $1\MUL_dec31_dec_sub9_is_32b[0:0] 1'0 + end + sync always + update \MUL_dec31_dec_sub9_is_32b $0\MUL_dec31_dec_sub9_is_32b[0:0] + end + attribute \src "libresoc.v:17490.3-17514.6" + process $proc$libresoc.v:17490$364 + assign { } { } + assign { } { } + assign $0\MUL_dec31_dec_sub9_sgn[0:0] $1\MUL_dec31_dec_sub9_sgn[0:0] + attribute \src "libresoc.v:17491.5-17491.29" + switch \initial + attribute \src "libresoc.v:17491.9-17491.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\MUL_dec31_dec_sub9_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\MUL_dec31_dec_sub9_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\MUL_dec31_dec_sub9_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\MUL_dec31_dec_sub9_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\MUL_dec31_dec_sub9_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\MUL_dec31_dec_sub9_sgn[0:0] 1'1 + case + assign $1\MUL_dec31_dec_sub9_sgn[0:0] 1'0 + end + sync always + update \MUL_dec31_dec_sub9_sgn $0\MUL_dec31_dec_sub9_sgn[0:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:17520.1-18094.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SHIFT_ROT.dec.SHIFT_ROT_dec30" +attribute \generator "nMigen" +module \SHIFT_ROT_dec30 + attribute \src "libresoc.v:17871.3-17907.6" + wire width 3 $0\SHIFT_ROT_dec30_cr_in[2:0] + attribute \src "libresoc.v:17908.3-17944.6" + wire width 3 $0\SHIFT_ROT_dec30_cr_out[2:0] + attribute \src "libresoc.v:17982.3-18018.6" + wire width 2 $0\SHIFT_ROT_dec30_cry_in[1:0] + attribute \src "libresoc.v:18056.3-18092.6" + wire $0\SHIFT_ROT_dec30_cry_out[0:0] + attribute \src "libresoc.v:17686.3-17722.6" + wire width 13 $0\SHIFT_ROT_dec30_function_unit[12:0] + attribute \src "libresoc.v:17834.3-17870.6" + wire width 4 $0\SHIFT_ROT_dec30_in2_sel[3:0] + attribute \src "libresoc.v:17797.3-17833.6" + wire width 7 $0\SHIFT_ROT_dec30_internal_op[6:0] + attribute \src "libresoc.v:18019.3-18055.6" + wire $0\SHIFT_ROT_dec30_inv_a[0:0] + attribute \src "libresoc.v:17723.3-17759.6" + wire $0\SHIFT_ROT_dec30_is_32b[0:0] + attribute \src "libresoc.v:17945.3-17981.6" + wire width 2 $0\SHIFT_ROT_dec30_rc_sel[1:0] + attribute \src "libresoc.v:17760.3-17796.6" + wire $0\SHIFT_ROT_dec30_sgn[0:0] + attribute \src "libresoc.v:17521.7-17521.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:17871.3-17907.6" + wire width 3 $1\SHIFT_ROT_dec30_cr_in[2:0] + attribute \src "libresoc.v:17908.3-17944.6" + wire width 3 $1\SHIFT_ROT_dec30_cr_out[2:0] + attribute \src "libresoc.v:17982.3-18018.6" + wire width 2 $1\SHIFT_ROT_dec30_cry_in[1:0] + attribute \src "libresoc.v:18056.3-18092.6" + wire $1\SHIFT_ROT_dec30_cry_out[0:0] + attribute \src "libresoc.v:17686.3-17722.6" + wire width 13 $1\SHIFT_ROT_dec30_function_unit[12:0] + attribute \src "libresoc.v:17834.3-17870.6" + wire width 4 $1\SHIFT_ROT_dec30_in2_sel[3:0] + attribute \src "libresoc.v:17797.3-17833.6" + wire width 7 $1\SHIFT_ROT_dec30_internal_op[6:0] + attribute \src "libresoc.v:18019.3-18055.6" + wire $1\SHIFT_ROT_dec30_inv_a[0:0] + attribute \src "libresoc.v:17723.3-17759.6" + wire $1\SHIFT_ROT_dec30_is_32b[0:0] + attribute \src "libresoc.v:17945.3-17981.6" + wire width 2 $1\SHIFT_ROT_dec30_rc_sel[1:0] + attribute \src "libresoc.v:17760.3-17796.6" + wire $1\SHIFT_ROT_dec30_sgn[0:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 4 \SHIFT_ROT_dec30_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 5 \SHIFT_ROT_dec30_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 7 \SHIFT_ROT_dec30_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 9 \SHIFT_ROT_dec30_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 13 output 1 \SHIFT_ROT_dec30_function_unit + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 3 \SHIFT_ROT_dec30_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 output 2 \SHIFT_ROT_dec30_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 8 \SHIFT_ROT_dec30_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 10 \SHIFT_ROT_dec30_is_32b + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 6 \SHIFT_ROT_dec30_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 11 \SHIFT_ROT_dec30_sgn + attribute \src "libresoc.v:17521.7-17521.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + wire width 32 input 12 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + wire width 4 \opcode_switch + attribute \src "libresoc.v:17521.7-17521.20" + process $proc$libresoc.v:17521$377 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:17686.3-17722.6" + process $proc$libresoc.v:17686$366 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec30_function_unit[12:0] $1\SHIFT_ROT_dec30_function_unit[12:0] + attribute \src "libresoc.v:17687.5-17687.29" + switch \initial + attribute \src "libresoc.v:17687.9-17687.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\SHIFT_ROT_dec30_function_unit[12:0] 13'0000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\SHIFT_ROT_dec30_function_unit[12:0] 13'0000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\SHIFT_ROT_dec30_function_unit[12:0] 13'0000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\SHIFT_ROT_dec30_function_unit[12:0] 13'0000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\SHIFT_ROT_dec30_function_unit[12:0] 13'0000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\SHIFT_ROT_dec30_function_unit[12:0] 13'0000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\SHIFT_ROT_dec30_function_unit[12:0] 13'0000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\SHIFT_ROT_dec30_function_unit[12:0] 13'0000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\SHIFT_ROT_dec30_function_unit[12:0] 13'0000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\SHIFT_ROT_dec30_function_unit[12:0] 13'0000000001000 + case + assign $1\SHIFT_ROT_dec30_function_unit[12:0] 13'0000000000000 + end + sync always + update \SHIFT_ROT_dec30_function_unit $0\SHIFT_ROT_dec30_function_unit[12:0] + end + attribute \src "libresoc.v:17723.3-17759.6" + process $proc$libresoc.v:17723$367 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec30_is_32b[0:0] $1\SHIFT_ROT_dec30_is_32b[0:0] + attribute \src "libresoc.v:17724.5-17724.29" + switch \initial + attribute \src "libresoc.v:17724.9-17724.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\SHIFT_ROT_dec30_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\SHIFT_ROT_dec30_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\SHIFT_ROT_dec30_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\SHIFT_ROT_dec30_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\SHIFT_ROT_dec30_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\SHIFT_ROT_dec30_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\SHIFT_ROT_dec30_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\SHIFT_ROT_dec30_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\SHIFT_ROT_dec30_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\SHIFT_ROT_dec30_is_32b[0:0] 1'0 + case + assign $1\SHIFT_ROT_dec30_is_32b[0:0] 1'0 + end + sync always + update \SHIFT_ROT_dec30_is_32b $0\SHIFT_ROT_dec30_is_32b[0:0] + end + attribute \src "libresoc.v:17760.3-17796.6" + process $proc$libresoc.v:17760$368 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec30_sgn[0:0] $1\SHIFT_ROT_dec30_sgn[0:0] + attribute \src "libresoc.v:17761.5-17761.29" + switch \initial + attribute \src "libresoc.v:17761.9-17761.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\SHIFT_ROT_dec30_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\SHIFT_ROT_dec30_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\SHIFT_ROT_dec30_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\SHIFT_ROT_dec30_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\SHIFT_ROT_dec30_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\SHIFT_ROT_dec30_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\SHIFT_ROT_dec30_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\SHIFT_ROT_dec30_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\SHIFT_ROT_dec30_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\SHIFT_ROT_dec30_sgn[0:0] 1'0 + case + assign $1\SHIFT_ROT_dec30_sgn[0:0] 1'0 + end + sync always + update \SHIFT_ROT_dec30_sgn $0\SHIFT_ROT_dec30_sgn[0:0] + end + attribute \src "libresoc.v:17797.3-17833.6" + process $proc$libresoc.v:17797$369 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec30_internal_op[6:0] $1\SHIFT_ROT_dec30_internal_op[6:0] + attribute \src "libresoc.v:17798.5-17798.29" + switch \initial + attribute \src "libresoc.v:17798.9-17798.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\SHIFT_ROT_dec30_internal_op[6:0] 7'0111000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\SHIFT_ROT_dec30_internal_op[6:0] 7'0111000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\SHIFT_ROT_dec30_internal_op[6:0] 7'0111001 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\SHIFT_ROT_dec30_internal_op[6:0] 7'0111001 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\SHIFT_ROT_dec30_internal_op[6:0] 7'0111010 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\SHIFT_ROT_dec30_internal_op[6:0] 7'0111010 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\SHIFT_ROT_dec30_internal_op[6:0] 7'0111000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\SHIFT_ROT_dec30_internal_op[6:0] 7'0111000 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\SHIFT_ROT_dec30_internal_op[6:0] 7'0111001 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\SHIFT_ROT_dec30_internal_op[6:0] 7'0111010 + case + assign $1\SHIFT_ROT_dec30_internal_op[6:0] 7'0000000 + end + sync always + update \SHIFT_ROT_dec30_internal_op $0\SHIFT_ROT_dec30_internal_op[6:0] + end + attribute \src "libresoc.v:17834.3-17870.6" + process $proc$libresoc.v:17834$370 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec30_in2_sel[3:0] $1\SHIFT_ROT_dec30_in2_sel[3:0] + attribute \src "libresoc.v:17835.5-17835.29" + switch \initial + attribute \src "libresoc.v:17835.9-17835.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\SHIFT_ROT_dec30_in2_sel[3:0] 4'1010 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\SHIFT_ROT_dec30_in2_sel[3:0] 4'1010 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\SHIFT_ROT_dec30_in2_sel[3:0] 4'1010 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\SHIFT_ROT_dec30_in2_sel[3:0] 4'1010 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\SHIFT_ROT_dec30_in2_sel[3:0] 4'1010 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\SHIFT_ROT_dec30_in2_sel[3:0] 4'1010 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\SHIFT_ROT_dec30_in2_sel[3:0] 4'1010 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\SHIFT_ROT_dec30_in2_sel[3:0] 4'1010 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\SHIFT_ROT_dec30_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\SHIFT_ROT_dec30_in2_sel[3:0] 4'0001 + case + assign $1\SHIFT_ROT_dec30_in2_sel[3:0] 4'0000 + end + sync always + update \SHIFT_ROT_dec30_in2_sel $0\SHIFT_ROT_dec30_in2_sel[3:0] + end + attribute \src "libresoc.v:17871.3-17907.6" + process $proc$libresoc.v:17871$371 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec30_cr_in[2:0] $1\SHIFT_ROT_dec30_cr_in[2:0] + attribute \src "libresoc.v:17872.5-17872.29" + switch \initial + attribute \src "libresoc.v:17872.9-17872.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\SHIFT_ROT_dec30_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\SHIFT_ROT_dec30_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\SHIFT_ROT_dec30_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\SHIFT_ROT_dec30_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\SHIFT_ROT_dec30_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\SHIFT_ROT_dec30_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\SHIFT_ROT_dec30_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\SHIFT_ROT_dec30_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\SHIFT_ROT_dec30_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\SHIFT_ROT_dec30_cr_in[2:0] 3'000 + case + assign $1\SHIFT_ROT_dec30_cr_in[2:0] 3'000 + end + sync always + update \SHIFT_ROT_dec30_cr_in $0\SHIFT_ROT_dec30_cr_in[2:0] + end + attribute \src "libresoc.v:17908.3-17944.6" + process $proc$libresoc.v:17908$372 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec30_cr_out[2:0] $1\SHIFT_ROT_dec30_cr_out[2:0] + attribute \src "libresoc.v:17909.5-17909.29" + switch \initial + attribute \src "libresoc.v:17909.9-17909.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\SHIFT_ROT_dec30_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\SHIFT_ROT_dec30_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\SHIFT_ROT_dec30_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\SHIFT_ROT_dec30_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\SHIFT_ROT_dec30_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\SHIFT_ROT_dec30_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\SHIFT_ROT_dec30_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\SHIFT_ROT_dec30_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\SHIFT_ROT_dec30_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\SHIFT_ROT_dec30_cr_out[2:0] 3'001 + case + assign $1\SHIFT_ROT_dec30_cr_out[2:0] 3'000 + end + sync always + update \SHIFT_ROT_dec30_cr_out $0\SHIFT_ROT_dec30_cr_out[2:0] + end + attribute \src "libresoc.v:17945.3-17981.6" + process $proc$libresoc.v:17945$373 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec30_rc_sel[1:0] $1\SHIFT_ROT_dec30_rc_sel[1:0] + attribute \src "libresoc.v:17946.5-17946.29" + switch \initial + attribute \src "libresoc.v:17946.9-17946.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\SHIFT_ROT_dec30_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\SHIFT_ROT_dec30_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\SHIFT_ROT_dec30_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\SHIFT_ROT_dec30_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\SHIFT_ROT_dec30_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\SHIFT_ROT_dec30_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\SHIFT_ROT_dec30_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\SHIFT_ROT_dec30_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\SHIFT_ROT_dec30_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\SHIFT_ROT_dec30_rc_sel[1:0] 2'10 + case + assign $1\SHIFT_ROT_dec30_rc_sel[1:0] 2'00 + end + sync always + update \SHIFT_ROT_dec30_rc_sel $0\SHIFT_ROT_dec30_rc_sel[1:0] + end + attribute \src "libresoc.v:17982.3-18018.6" + process $proc$libresoc.v:17982$374 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec30_cry_in[1:0] $1\SHIFT_ROT_dec30_cry_in[1:0] + attribute \src "libresoc.v:17983.5-17983.29" + switch \initial + attribute \src "libresoc.v:17983.9-17983.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\SHIFT_ROT_dec30_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\SHIFT_ROT_dec30_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\SHIFT_ROT_dec30_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\SHIFT_ROT_dec30_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\SHIFT_ROT_dec30_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\SHIFT_ROT_dec30_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\SHIFT_ROT_dec30_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\SHIFT_ROT_dec30_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\SHIFT_ROT_dec30_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\SHIFT_ROT_dec30_cry_in[1:0] 2'00 + case + assign $1\SHIFT_ROT_dec30_cry_in[1:0] 2'00 + end + sync always + update \SHIFT_ROT_dec30_cry_in $0\SHIFT_ROT_dec30_cry_in[1:0] + end + attribute \src "libresoc.v:18019.3-18055.6" + process $proc$libresoc.v:18019$375 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec30_inv_a[0:0] $1\SHIFT_ROT_dec30_inv_a[0:0] + attribute \src "libresoc.v:18020.5-18020.29" + switch \initial + attribute \src "libresoc.v:18020.9-18020.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\SHIFT_ROT_dec30_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\SHIFT_ROT_dec30_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\SHIFT_ROT_dec30_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\SHIFT_ROT_dec30_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\SHIFT_ROT_dec30_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\SHIFT_ROT_dec30_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\SHIFT_ROT_dec30_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\SHIFT_ROT_dec30_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\SHIFT_ROT_dec30_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\SHIFT_ROT_dec30_inv_a[0:0] 1'0 + case + assign $1\SHIFT_ROT_dec30_inv_a[0:0] 1'0 + end + sync always + update \SHIFT_ROT_dec30_inv_a $0\SHIFT_ROT_dec30_inv_a[0:0] + end + attribute \src "libresoc.v:18056.3-18092.6" + process $proc$libresoc.v:18056$376 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec30_cry_out[0:0] $1\SHIFT_ROT_dec30_cry_out[0:0] + attribute \src "libresoc.v:18057.5-18057.29" + switch \initial + attribute \src "libresoc.v:18057.9-18057.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\SHIFT_ROT_dec30_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\SHIFT_ROT_dec30_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\SHIFT_ROT_dec30_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\SHIFT_ROT_dec30_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\SHIFT_ROT_dec30_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\SHIFT_ROT_dec30_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\SHIFT_ROT_dec30_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\SHIFT_ROT_dec30_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\SHIFT_ROT_dec30_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\SHIFT_ROT_dec30_cry_out[0:0] 1'0 + case + assign $1\SHIFT_ROT_dec30_cry_out[0:0] 1'0 + end + sync always + update \SHIFT_ROT_dec30_cry_out $0\SHIFT_ROT_dec30_cry_out[0:0] + end + connect \opcode_switch \opcode_in [4:1] +end +attribute \src "libresoc.v:18098.1-18942.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SHIFT_ROT.dec.SHIFT_ROT_dec31" +attribute \generator "nMigen" +module \SHIFT_ROT_dec31 + attribute \src "libresoc.v:18905.3-18920.6" + wire width 3 $0\SHIFT_ROT_dec31_cr_in[2:0] + attribute \src "libresoc.v:18921.3-18936.6" + wire width 3 $0\SHIFT_ROT_dec31_cr_out[2:0] + attribute \src "libresoc.v:18777.3-18792.6" + wire width 2 $0\SHIFT_ROT_dec31_cry_in[1:0] + attribute \src "libresoc.v:18809.3-18824.6" + wire $0\SHIFT_ROT_dec31_cry_out[0:0] + attribute \src "libresoc.v:18857.3-18872.6" + wire width 13 $0\SHIFT_ROT_dec31_function_unit[12:0] + attribute \src "libresoc.v:18889.3-18904.6" + wire width 4 $0\SHIFT_ROT_dec31_in2_sel[3:0] + attribute \src "libresoc.v:18873.3-18888.6" + wire width 7 $0\SHIFT_ROT_dec31_internal_op[6:0] + attribute \src "libresoc.v:18793.3-18808.6" + wire $0\SHIFT_ROT_dec31_inv_a[0:0] + attribute \src "libresoc.v:18825.3-18840.6" + wire $0\SHIFT_ROT_dec31_is_32b[0:0] + attribute \src "libresoc.v:18761.3-18776.6" + wire width 2 $0\SHIFT_ROT_dec31_rc_sel[1:0] + attribute \src "libresoc.v:18841.3-18856.6" + wire $0\SHIFT_ROT_dec31_sgn[0:0] + attribute \src "libresoc.v:18099.7-18099.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:18905.3-18920.6" + wire width 3 $1\SHIFT_ROT_dec31_cr_in[2:0] + attribute \src "libresoc.v:18921.3-18936.6" + wire width 3 $1\SHIFT_ROT_dec31_cr_out[2:0] + attribute \src "libresoc.v:18777.3-18792.6" + wire width 2 $1\SHIFT_ROT_dec31_cry_in[1:0] + attribute \src "libresoc.v:18809.3-18824.6" + wire $1\SHIFT_ROT_dec31_cry_out[0:0] + attribute \src "libresoc.v:18857.3-18872.6" + wire width 13 $1\SHIFT_ROT_dec31_function_unit[12:0] + attribute \src "libresoc.v:18889.3-18904.6" + wire width 4 $1\SHIFT_ROT_dec31_in2_sel[3:0] + attribute \src "libresoc.v:18873.3-18888.6" + wire width 7 $1\SHIFT_ROT_dec31_internal_op[6:0] + attribute \src "libresoc.v:18793.3-18808.6" + wire $1\SHIFT_ROT_dec31_inv_a[0:0] + attribute \src "libresoc.v:18825.3-18840.6" + wire $1\SHIFT_ROT_dec31_is_32b[0:0] + attribute \src "libresoc.v:18761.3-18776.6" + wire width 2 $1\SHIFT_ROT_dec31_rc_sel[1:0] + attribute \src "libresoc.v:18841.3-18856.6" + wire $1\SHIFT_ROT_dec31_sgn[0:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 4 \SHIFT_ROT_dec31_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 5 \SHIFT_ROT_dec31_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 7 \SHIFT_ROT_dec31_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 9 \SHIFT_ROT_dec31_cry_out + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 13 \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_function_unit + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_is_32b + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + wire width 32 \SHIFT_ROT_dec31_dec_sub24_opcode_in + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 13 \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_function_unit + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_is_32b + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + wire width 32 \SHIFT_ROT_dec31_dec_sub26_opcode_in + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 13 \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_function_unit + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_is_32b + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + wire width 32 \SHIFT_ROT_dec31_dec_sub27_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 13 output 1 \SHIFT_ROT_dec31_function_unit + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 3 \SHIFT_ROT_dec31_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 output 2 \SHIFT_ROT_dec31_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 8 \SHIFT_ROT_dec31_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 10 \SHIFT_ROT_dec31_is_32b + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 6 \SHIFT_ROT_dec31_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 11 \SHIFT_ROT_dec31_sgn + attribute \src "libresoc.v:18099.7-18099.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:347" + wire width 5 \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + wire width 32 input 12 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + wire width 10 \opcode_switch + attribute \module_not_derived 1 + attribute \src "libresoc.v:18719.29-18732.4" + cell \SHIFT_ROT_dec31_dec_sub24 \SHIFT_ROT_dec31_dec_sub24 + connect \SHIFT_ROT_dec31_dec_sub24_cr_in \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cr_in + connect \SHIFT_ROT_dec31_dec_sub24_cr_out \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cr_out + connect \SHIFT_ROT_dec31_dec_sub24_cry_in \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cry_in + connect \SHIFT_ROT_dec31_dec_sub24_cry_out \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cry_out + connect \SHIFT_ROT_dec31_dec_sub24_function_unit \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_function_unit + connect \SHIFT_ROT_dec31_dec_sub24_in2_sel \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_in2_sel + connect \SHIFT_ROT_dec31_dec_sub24_internal_op \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_internal_op + connect \SHIFT_ROT_dec31_dec_sub24_inv_a \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_inv_a + connect \SHIFT_ROT_dec31_dec_sub24_is_32b \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_is_32b + connect \SHIFT_ROT_dec31_dec_sub24_rc_sel \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_rc_sel + connect \SHIFT_ROT_dec31_dec_sub24_sgn \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_sgn + connect \opcode_in \SHIFT_ROT_dec31_dec_sub24_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:18733.29-18746.4" + cell \SHIFT_ROT_dec31_dec_sub26 \SHIFT_ROT_dec31_dec_sub26 + connect \SHIFT_ROT_dec31_dec_sub26_cr_in \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cr_in + connect \SHIFT_ROT_dec31_dec_sub26_cr_out \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cr_out + connect \SHIFT_ROT_dec31_dec_sub26_cry_in \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cry_in + connect \SHIFT_ROT_dec31_dec_sub26_cry_out \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cry_out + connect \SHIFT_ROT_dec31_dec_sub26_function_unit \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_function_unit + connect \SHIFT_ROT_dec31_dec_sub26_in2_sel \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_in2_sel + connect \SHIFT_ROT_dec31_dec_sub26_internal_op \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_internal_op + connect \SHIFT_ROT_dec31_dec_sub26_inv_a \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_inv_a + connect \SHIFT_ROT_dec31_dec_sub26_is_32b \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_is_32b + connect \SHIFT_ROT_dec31_dec_sub26_rc_sel \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_rc_sel + connect \SHIFT_ROT_dec31_dec_sub26_sgn \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_sgn + connect \opcode_in \SHIFT_ROT_dec31_dec_sub26_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:18747.29-18760.4" + cell \SHIFT_ROT_dec31_dec_sub27 \SHIFT_ROT_dec31_dec_sub27 + connect \SHIFT_ROT_dec31_dec_sub27_cr_in \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cr_in + connect \SHIFT_ROT_dec31_dec_sub27_cr_out \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cr_out + connect \SHIFT_ROT_dec31_dec_sub27_cry_in \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cry_in + connect \SHIFT_ROT_dec31_dec_sub27_cry_out \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cry_out + connect \SHIFT_ROT_dec31_dec_sub27_function_unit \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_function_unit + connect \SHIFT_ROT_dec31_dec_sub27_in2_sel \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_in2_sel + connect \SHIFT_ROT_dec31_dec_sub27_internal_op \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_internal_op + connect \SHIFT_ROT_dec31_dec_sub27_inv_a \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_inv_a + connect \SHIFT_ROT_dec31_dec_sub27_is_32b \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_is_32b + connect \SHIFT_ROT_dec31_dec_sub27_rc_sel \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_rc_sel + connect \SHIFT_ROT_dec31_dec_sub27_sgn \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_sgn + connect \opcode_in \SHIFT_ROT_dec31_dec_sub27_opcode_in + end + attribute \src "libresoc.v:18099.7-18099.20" + process $proc$libresoc.v:18099$389 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:18761.3-18776.6" + process $proc$libresoc.v:18761$378 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_rc_sel[1:0] $1\SHIFT_ROT_dec31_rc_sel[1:0] + attribute \src "libresoc.v:18762.5-18762.29" + switch \initial + attribute \src "libresoc.v:18762.9-18762.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\SHIFT_ROT_dec31_rc_sel[1:0] \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_rc_sel[1:0] \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_rc_sel[1:0] \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_rc_sel + case + assign $1\SHIFT_ROT_dec31_rc_sel[1:0] 2'00 + end + sync always + update \SHIFT_ROT_dec31_rc_sel $0\SHIFT_ROT_dec31_rc_sel[1:0] + end + attribute \src "libresoc.v:18777.3-18792.6" + process $proc$libresoc.v:18777$379 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_cry_in[1:0] $1\SHIFT_ROT_dec31_cry_in[1:0] + attribute \src "libresoc.v:18778.5-18778.29" + switch \initial + attribute \src "libresoc.v:18778.9-18778.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\SHIFT_ROT_dec31_cry_in[1:0] \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_cry_in[1:0] \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_cry_in[1:0] \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cry_in + case + assign $1\SHIFT_ROT_dec31_cry_in[1:0] 2'00 + end + sync always + update \SHIFT_ROT_dec31_cry_in $0\SHIFT_ROT_dec31_cry_in[1:0] + end + attribute \src "libresoc.v:18793.3-18808.6" + process $proc$libresoc.v:18793$380 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_inv_a[0:0] $1\SHIFT_ROT_dec31_inv_a[0:0] + attribute \src "libresoc.v:18794.5-18794.29" + switch \initial + attribute \src "libresoc.v:18794.9-18794.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\SHIFT_ROT_dec31_inv_a[0:0] \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_inv_a[0:0] \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_inv_a[0:0] \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_inv_a + case + assign $1\SHIFT_ROT_dec31_inv_a[0:0] 1'0 + end + sync always + update \SHIFT_ROT_dec31_inv_a $0\SHIFT_ROT_dec31_inv_a[0:0] + end + attribute \src "libresoc.v:18809.3-18824.6" + process $proc$libresoc.v:18809$381 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_cry_out[0:0] $1\SHIFT_ROT_dec31_cry_out[0:0] + attribute \src "libresoc.v:18810.5-18810.29" + switch \initial + attribute \src "libresoc.v:18810.9-18810.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\SHIFT_ROT_dec31_cry_out[0:0] \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_cry_out[0:0] \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_cry_out[0:0] \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cry_out + case + assign $1\SHIFT_ROT_dec31_cry_out[0:0] 1'0 + end + sync always + update \SHIFT_ROT_dec31_cry_out $0\SHIFT_ROT_dec31_cry_out[0:0] + end + attribute \src "libresoc.v:18825.3-18840.6" + process $proc$libresoc.v:18825$382 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_is_32b[0:0] $1\SHIFT_ROT_dec31_is_32b[0:0] + attribute \src "libresoc.v:18826.5-18826.29" + switch \initial + attribute \src "libresoc.v:18826.9-18826.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\SHIFT_ROT_dec31_is_32b[0:0] \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_is_32b[0:0] \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_is_32b[0:0] \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_is_32b + case + assign $1\SHIFT_ROT_dec31_is_32b[0:0] 1'0 + end + sync always + update \SHIFT_ROT_dec31_is_32b $0\SHIFT_ROT_dec31_is_32b[0:0] + end + attribute \src "libresoc.v:18841.3-18856.6" + process $proc$libresoc.v:18841$383 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_sgn[0:0] $1\SHIFT_ROT_dec31_sgn[0:0] + attribute \src "libresoc.v:18842.5-18842.29" + switch \initial + attribute \src "libresoc.v:18842.9-18842.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\SHIFT_ROT_dec31_sgn[0:0] \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_sgn[0:0] \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_sgn[0:0] \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_sgn + case + assign $1\SHIFT_ROT_dec31_sgn[0:0] 1'0 + end + sync always + update \SHIFT_ROT_dec31_sgn $0\SHIFT_ROT_dec31_sgn[0:0] + end + attribute \src "libresoc.v:18857.3-18872.6" + process $proc$libresoc.v:18857$384 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_function_unit[12:0] $1\SHIFT_ROT_dec31_function_unit[12:0] + attribute \src "libresoc.v:18858.5-18858.29" + switch \initial + attribute \src "libresoc.v:18858.9-18858.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\SHIFT_ROT_dec31_function_unit[12:0] \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_function_unit[12:0] \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_function_unit[12:0] \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_function_unit + case + assign $1\SHIFT_ROT_dec31_function_unit[12:0] 13'0000000000000 + end + sync always + update \SHIFT_ROT_dec31_function_unit $0\SHIFT_ROT_dec31_function_unit[12:0] + end + attribute \src "libresoc.v:18873.3-18888.6" + process $proc$libresoc.v:18873$385 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_internal_op[6:0] $1\SHIFT_ROT_dec31_internal_op[6:0] + attribute \src "libresoc.v:18874.5-18874.29" + switch \initial + attribute \src "libresoc.v:18874.9-18874.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\SHIFT_ROT_dec31_internal_op[6:0] \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_internal_op[6:0] \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_internal_op[6:0] \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_internal_op + case + assign $1\SHIFT_ROT_dec31_internal_op[6:0] 7'0000000 + end + sync always + update \SHIFT_ROT_dec31_internal_op $0\SHIFT_ROT_dec31_internal_op[6:0] + end + attribute \src "libresoc.v:18889.3-18904.6" + process $proc$libresoc.v:18889$386 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_in2_sel[3:0] $1\SHIFT_ROT_dec31_in2_sel[3:0] + attribute \src "libresoc.v:18890.5-18890.29" + switch \initial + attribute \src "libresoc.v:18890.9-18890.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\SHIFT_ROT_dec31_in2_sel[3:0] \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_in2_sel[3:0] \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_in2_sel[3:0] \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_in2_sel + case + assign $1\SHIFT_ROT_dec31_in2_sel[3:0] 4'0000 + end + sync always + update \SHIFT_ROT_dec31_in2_sel $0\SHIFT_ROT_dec31_in2_sel[3:0] + end + attribute \src "libresoc.v:18905.3-18920.6" + process $proc$libresoc.v:18905$387 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_cr_in[2:0] $1\SHIFT_ROT_dec31_cr_in[2:0] + attribute \src "libresoc.v:18906.5-18906.29" + switch \initial + attribute \src "libresoc.v:18906.9-18906.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\SHIFT_ROT_dec31_cr_in[2:0] \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_cr_in[2:0] \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_cr_in[2:0] \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cr_in + case + assign $1\SHIFT_ROT_dec31_cr_in[2:0] 3'000 + end + sync always + update \SHIFT_ROT_dec31_cr_in $0\SHIFT_ROT_dec31_cr_in[2:0] + end + attribute \src "libresoc.v:18921.3-18936.6" + process $proc$libresoc.v:18921$388 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_cr_out[2:0] $1\SHIFT_ROT_dec31_cr_out[2:0] + attribute \src "libresoc.v:18922.5-18922.29" + switch \initial + attribute \src "libresoc.v:18922.9-18922.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\SHIFT_ROT_dec31_cr_out[2:0] \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_cr_out[2:0] \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_cr_out[2:0] \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cr_out + case + assign $1\SHIFT_ROT_dec31_cr_out[2:0] 3'000 + end + sync always + update \SHIFT_ROT_dec31_cr_out $0\SHIFT_ROT_dec31_cr_out[2:0] + end + connect \SHIFT_ROT_dec31_dec_sub24_opcode_in \opcode_in + connect \SHIFT_ROT_dec31_dec_sub27_opcode_in \opcode_in + connect \SHIFT_ROT_dec31_dec_sub26_opcode_in \opcode_in + connect \opc_in \opcode_switch [4:0] + connect \opcode_switch \opcode_in [10:1] +end +attribute \src "libresoc.v:18946.1-19322.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SHIFT_ROT.dec.SHIFT_ROT_dec31.SHIFT_ROT_dec31_dec_sub24" +attribute \generator "nMigen" +module \SHIFT_ROT_dec31_dec_sub24 + attribute \src "libresoc.v:19207.3-19225.6" + wire width 3 $0\SHIFT_ROT_dec31_dec_sub24_cr_in[2:0] + attribute \src "libresoc.v:19226.3-19244.6" + wire width 3 $0\SHIFT_ROT_dec31_dec_sub24_cr_out[2:0] + attribute \src "libresoc.v:19264.3-19282.6" + wire width 2 $0\SHIFT_ROT_dec31_dec_sub24_cry_in[1:0] + attribute \src "libresoc.v:19302.3-19320.6" + wire $0\SHIFT_ROT_dec31_dec_sub24_cry_out[0:0] + attribute \src "libresoc.v:19112.3-19130.6" + wire width 13 $0\SHIFT_ROT_dec31_dec_sub24_function_unit[12:0] + attribute \src "libresoc.v:19188.3-19206.6" + wire width 4 $0\SHIFT_ROT_dec31_dec_sub24_in2_sel[3:0] + attribute \src "libresoc.v:19169.3-19187.6" + wire width 7 $0\SHIFT_ROT_dec31_dec_sub24_internal_op[6:0] + attribute \src "libresoc.v:19283.3-19301.6" + wire $0\SHIFT_ROT_dec31_dec_sub24_inv_a[0:0] + attribute \src "libresoc.v:19131.3-19149.6" + wire $0\SHIFT_ROT_dec31_dec_sub24_is_32b[0:0] + attribute \src "libresoc.v:19245.3-19263.6" + wire width 2 $0\SHIFT_ROT_dec31_dec_sub24_rc_sel[1:0] + attribute \src "libresoc.v:19150.3-19168.6" + wire $0\SHIFT_ROT_dec31_dec_sub24_sgn[0:0] + attribute \src "libresoc.v:18947.7-18947.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:19207.3-19225.6" + wire width 3 $1\SHIFT_ROT_dec31_dec_sub24_cr_in[2:0] + attribute \src "libresoc.v:19226.3-19244.6" + wire width 3 $1\SHIFT_ROT_dec31_dec_sub24_cr_out[2:0] + attribute \src "libresoc.v:19264.3-19282.6" + wire width 2 $1\SHIFT_ROT_dec31_dec_sub24_cry_in[1:0] + attribute \src "libresoc.v:19302.3-19320.6" + wire $1\SHIFT_ROT_dec31_dec_sub24_cry_out[0:0] + attribute \src "libresoc.v:19112.3-19130.6" + wire width 13 $1\SHIFT_ROT_dec31_dec_sub24_function_unit[12:0] + attribute \src "libresoc.v:19188.3-19206.6" + wire width 4 $1\SHIFT_ROT_dec31_dec_sub24_in2_sel[3:0] + attribute \src "libresoc.v:19169.3-19187.6" + wire width 7 $1\SHIFT_ROT_dec31_dec_sub24_internal_op[6:0] + attribute \src "libresoc.v:19283.3-19301.6" + wire $1\SHIFT_ROT_dec31_dec_sub24_inv_a[0:0] + attribute \src "libresoc.v:19131.3-19149.6" + wire $1\SHIFT_ROT_dec31_dec_sub24_is_32b[0:0] + attribute \src "libresoc.v:19245.3-19263.6" + wire width 2 $1\SHIFT_ROT_dec31_dec_sub24_rc_sel[1:0] + attribute \src "libresoc.v:19150.3-19168.6" + wire $1\SHIFT_ROT_dec31_dec_sub24_sgn[0:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 4 \SHIFT_ROT_dec31_dec_sub24_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 5 \SHIFT_ROT_dec31_dec_sub24_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 7 \SHIFT_ROT_dec31_dec_sub24_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 9 \SHIFT_ROT_dec31_dec_sub24_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 13 output 1 \SHIFT_ROT_dec31_dec_sub24_function_unit + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 3 \SHIFT_ROT_dec31_dec_sub24_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 output 2 \SHIFT_ROT_dec31_dec_sub24_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 8 \SHIFT_ROT_dec31_dec_sub24_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 10 \SHIFT_ROT_dec31_dec_sub24_is_32b + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 6 \SHIFT_ROT_dec31_dec_sub24_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 11 \SHIFT_ROT_dec31_dec_sub24_sgn + attribute \src "libresoc.v:18947.7-18947.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + wire width 32 input 12 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + wire width 5 \opcode_switch + attribute \src "libresoc.v:18947.7-18947.20" + process $proc$libresoc.v:18947$401 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:19112.3-19130.6" + process $proc$libresoc.v:19112$390 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub24_function_unit[12:0] $1\SHIFT_ROT_dec31_dec_sub24_function_unit[12:0] + attribute \src "libresoc.v:19113.5-19113.29" + switch \initial + attribute \src "libresoc.v:19113.9-19113.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_function_unit[12:0] 13'0000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_function_unit[12:0] 13'0000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_function_unit[12:0] 13'0000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_function_unit[12:0] 13'0000000001000 + case + assign $1\SHIFT_ROT_dec31_dec_sub24_function_unit[12:0] 13'0000000000000 + end + sync always + update \SHIFT_ROT_dec31_dec_sub24_function_unit $0\SHIFT_ROT_dec31_dec_sub24_function_unit[12:0] + end + attribute \src "libresoc.v:19131.3-19149.6" + process $proc$libresoc.v:19131$391 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub24_is_32b[0:0] $1\SHIFT_ROT_dec31_dec_sub24_is_32b[0:0] + attribute \src "libresoc.v:19132.5-19132.29" + switch \initial + attribute \src "libresoc.v:19132.9-19132.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_is_32b[0:0] 1'1 + case + assign $1\SHIFT_ROT_dec31_dec_sub24_is_32b[0:0] 1'0 + end + sync always + update \SHIFT_ROT_dec31_dec_sub24_is_32b $0\SHIFT_ROT_dec31_dec_sub24_is_32b[0:0] + end + attribute \src "libresoc.v:19150.3-19168.6" + process $proc$libresoc.v:19150$392 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub24_sgn[0:0] $1\SHIFT_ROT_dec31_dec_sub24_sgn[0:0] + attribute \src "libresoc.v:19151.5-19151.29" + switch \initial + attribute \src "libresoc.v:19151.9-19151.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_sgn[0:0] 1'0 + case + assign $1\SHIFT_ROT_dec31_dec_sub24_sgn[0:0] 1'0 + end + sync always + update \SHIFT_ROT_dec31_dec_sub24_sgn $0\SHIFT_ROT_dec31_dec_sub24_sgn[0:0] + end + attribute \src "libresoc.v:19169.3-19187.6" + process $proc$libresoc.v:19169$393 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub24_internal_op[6:0] $1\SHIFT_ROT_dec31_dec_sub24_internal_op[6:0] + attribute \src "libresoc.v:19170.5-19170.29" + switch \initial + attribute \src "libresoc.v:19170.9-19170.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_internal_op[6:0] 7'0111100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_internal_op[6:0] 7'0111101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_internal_op[6:0] 7'0111101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_internal_op[6:0] 7'0111101 + case + assign $1\SHIFT_ROT_dec31_dec_sub24_internal_op[6:0] 7'0000000 + end + sync always + update \SHIFT_ROT_dec31_dec_sub24_internal_op $0\SHIFT_ROT_dec31_dec_sub24_internal_op[6:0] + end + attribute \src "libresoc.v:19188.3-19206.6" + process $proc$libresoc.v:19188$394 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub24_in2_sel[3:0] $1\SHIFT_ROT_dec31_dec_sub24_in2_sel[3:0] + attribute \src "libresoc.v:19189.5-19189.29" + switch \initial + attribute \src "libresoc.v:19189.9-19189.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_in2_sel[3:0] 4'1011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_in2_sel[3:0] 4'0001 + case + assign $1\SHIFT_ROT_dec31_dec_sub24_in2_sel[3:0] 4'0000 + end + sync always + update \SHIFT_ROT_dec31_dec_sub24_in2_sel $0\SHIFT_ROT_dec31_dec_sub24_in2_sel[3:0] + end + attribute \src "libresoc.v:19207.3-19225.6" + process $proc$libresoc.v:19207$395 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub24_cr_in[2:0] $1\SHIFT_ROT_dec31_dec_sub24_cr_in[2:0] + attribute \src "libresoc.v:19208.5-19208.29" + switch \initial + attribute \src "libresoc.v:19208.9-19208.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_cr_in[2:0] 3'000 + case + assign $1\SHIFT_ROT_dec31_dec_sub24_cr_in[2:0] 3'000 + end + sync always + update \SHIFT_ROT_dec31_dec_sub24_cr_in $0\SHIFT_ROT_dec31_dec_sub24_cr_in[2:0] + end + attribute \src "libresoc.v:19226.3-19244.6" + process $proc$libresoc.v:19226$396 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub24_cr_out[2:0] $1\SHIFT_ROT_dec31_dec_sub24_cr_out[2:0] + attribute \src "libresoc.v:19227.5-19227.29" + switch \initial + attribute \src "libresoc.v:19227.9-19227.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_cr_out[2:0] 3'001 + case + assign $1\SHIFT_ROT_dec31_dec_sub24_cr_out[2:0] 3'000 + end + sync always + update \SHIFT_ROT_dec31_dec_sub24_cr_out $0\SHIFT_ROT_dec31_dec_sub24_cr_out[2:0] + end + attribute \src "libresoc.v:19245.3-19263.6" + process $proc$libresoc.v:19245$397 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub24_rc_sel[1:0] $1\SHIFT_ROT_dec31_dec_sub24_rc_sel[1:0] + attribute \src "libresoc.v:19246.5-19246.29" + switch \initial + attribute \src "libresoc.v:19246.9-19246.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_rc_sel[1:0] 2'10 + case + assign $1\SHIFT_ROT_dec31_dec_sub24_rc_sel[1:0] 2'00 + end + sync always + update \SHIFT_ROT_dec31_dec_sub24_rc_sel $0\SHIFT_ROT_dec31_dec_sub24_rc_sel[1:0] + end + attribute \src "libresoc.v:19264.3-19282.6" + process $proc$libresoc.v:19264$398 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub24_cry_in[1:0] $1\SHIFT_ROT_dec31_dec_sub24_cry_in[1:0] + attribute \src "libresoc.v:19265.5-19265.29" + switch \initial + attribute \src "libresoc.v:19265.9-19265.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_cry_in[1:0] 2'00 + case + assign $1\SHIFT_ROT_dec31_dec_sub24_cry_in[1:0] 2'00 + end + sync always + update \SHIFT_ROT_dec31_dec_sub24_cry_in $0\SHIFT_ROT_dec31_dec_sub24_cry_in[1:0] + end + attribute \src "libresoc.v:19283.3-19301.6" + process $proc$libresoc.v:19283$399 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub24_inv_a[0:0] $1\SHIFT_ROT_dec31_dec_sub24_inv_a[0:0] + attribute \src "libresoc.v:19284.5-19284.29" + switch \initial + attribute \src "libresoc.v:19284.9-19284.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_inv_a[0:0] 1'0 + case + assign $1\SHIFT_ROT_dec31_dec_sub24_inv_a[0:0] 1'0 + end + sync always + update \SHIFT_ROT_dec31_dec_sub24_inv_a $0\SHIFT_ROT_dec31_dec_sub24_inv_a[0:0] + end + attribute \src "libresoc.v:19302.3-19320.6" + process $proc$libresoc.v:19302$400 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub24_cry_out[0:0] $1\SHIFT_ROT_dec31_dec_sub24_cry_out[0:0] + attribute \src "libresoc.v:19303.5-19303.29" + switch \initial + attribute \src "libresoc.v:19303.9-19303.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_cry_out[0:0] 1'0 + case + assign $1\SHIFT_ROT_dec31_dec_sub24_cry_out[0:0] 1'0 + end + sync always + update \SHIFT_ROT_dec31_dec_sub24_cry_out $0\SHIFT_ROT_dec31_dec_sub24_cry_out[0:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:19326.1-19669.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SHIFT_ROT.dec.SHIFT_ROT_dec31.SHIFT_ROT_dec31_dec_sub26" +attribute \generator "nMigen" +module \SHIFT_ROT_dec31_dec_sub26 + attribute \src "libresoc.v:19572.3-19587.6" + wire width 3 $0\SHIFT_ROT_dec31_dec_sub26_cr_in[2:0] + attribute \src "libresoc.v:19588.3-19603.6" + wire width 3 $0\SHIFT_ROT_dec31_dec_sub26_cr_out[2:0] + attribute \src "libresoc.v:19620.3-19635.6" + wire width 2 $0\SHIFT_ROT_dec31_dec_sub26_cry_in[1:0] + attribute \src "libresoc.v:19652.3-19667.6" + wire $0\SHIFT_ROT_dec31_dec_sub26_cry_out[0:0] + attribute \src "libresoc.v:19492.3-19507.6" + wire width 13 $0\SHIFT_ROT_dec31_dec_sub26_function_unit[12:0] + attribute \src "libresoc.v:19556.3-19571.6" + wire width 4 $0\SHIFT_ROT_dec31_dec_sub26_in2_sel[3:0] + attribute \src "libresoc.v:19540.3-19555.6" + wire width 7 $0\SHIFT_ROT_dec31_dec_sub26_internal_op[6:0] + attribute \src "libresoc.v:19636.3-19651.6" + wire $0\SHIFT_ROT_dec31_dec_sub26_inv_a[0:0] + attribute \src "libresoc.v:19508.3-19523.6" + wire $0\SHIFT_ROT_dec31_dec_sub26_is_32b[0:0] + attribute \src "libresoc.v:19604.3-19619.6" + wire width 2 $0\SHIFT_ROT_dec31_dec_sub26_rc_sel[1:0] + attribute \src "libresoc.v:19524.3-19539.6" + wire $0\SHIFT_ROT_dec31_dec_sub26_sgn[0:0] + attribute \src "libresoc.v:19327.7-19327.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:19572.3-19587.6" + wire width 3 $1\SHIFT_ROT_dec31_dec_sub26_cr_in[2:0] + attribute \src "libresoc.v:19588.3-19603.6" + wire width 3 $1\SHIFT_ROT_dec31_dec_sub26_cr_out[2:0] + attribute \src "libresoc.v:19620.3-19635.6" + wire width 2 $1\SHIFT_ROT_dec31_dec_sub26_cry_in[1:0] + attribute \src "libresoc.v:19652.3-19667.6" + wire $1\SHIFT_ROT_dec31_dec_sub26_cry_out[0:0] + attribute \src "libresoc.v:19492.3-19507.6" + wire width 13 $1\SHIFT_ROT_dec31_dec_sub26_function_unit[12:0] + attribute \src "libresoc.v:19556.3-19571.6" + wire width 4 $1\SHIFT_ROT_dec31_dec_sub26_in2_sel[3:0] + attribute \src "libresoc.v:19540.3-19555.6" + wire width 7 $1\SHIFT_ROT_dec31_dec_sub26_internal_op[6:0] + attribute \src "libresoc.v:19636.3-19651.6" + wire $1\SHIFT_ROT_dec31_dec_sub26_inv_a[0:0] + attribute \src "libresoc.v:19508.3-19523.6" + wire $1\SHIFT_ROT_dec31_dec_sub26_is_32b[0:0] + attribute \src "libresoc.v:19604.3-19619.6" + wire width 2 $1\SHIFT_ROT_dec31_dec_sub26_rc_sel[1:0] + attribute \src "libresoc.v:19524.3-19539.6" + wire $1\SHIFT_ROT_dec31_dec_sub26_sgn[0:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 4 \SHIFT_ROT_dec31_dec_sub26_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 5 \SHIFT_ROT_dec31_dec_sub26_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 7 \SHIFT_ROT_dec31_dec_sub26_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 9 \SHIFT_ROT_dec31_dec_sub26_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 13 output 1 \SHIFT_ROT_dec31_dec_sub26_function_unit + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 3 \SHIFT_ROT_dec31_dec_sub26_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 output 2 \SHIFT_ROT_dec31_dec_sub26_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 8 \SHIFT_ROT_dec31_dec_sub26_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 10 \SHIFT_ROT_dec31_dec_sub26_is_32b + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 6 \SHIFT_ROT_dec31_dec_sub26_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 11 \SHIFT_ROT_dec31_dec_sub26_sgn + attribute \src "libresoc.v:19327.7-19327.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + wire width 32 input 12 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + wire width 5 \opcode_switch + attribute \src "libresoc.v:19327.7-19327.20" + process $proc$libresoc.v:19327$413 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:19492.3-19507.6" + process $proc$libresoc.v:19492$402 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub26_function_unit[12:0] $1\SHIFT_ROT_dec31_dec_sub26_function_unit[12:0] + attribute \src "libresoc.v:19493.5-19493.29" + switch \initial + attribute \src "libresoc.v:19493.9-19493.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_function_unit[12:0] 13'0000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_function_unit[12:0] 13'0000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_function_unit[12:0] 13'0000000001000 + case + assign $1\SHIFT_ROT_dec31_dec_sub26_function_unit[12:0] 13'0000000000000 + end + sync always + update \SHIFT_ROT_dec31_dec_sub26_function_unit $0\SHIFT_ROT_dec31_dec_sub26_function_unit[12:0] + end + attribute \src "libresoc.v:19508.3-19523.6" + process $proc$libresoc.v:19508$403 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub26_is_32b[0:0] $1\SHIFT_ROT_dec31_dec_sub26_is_32b[0:0] + attribute \src "libresoc.v:19509.5-19509.29" + switch \initial + attribute \src "libresoc.v:19509.9-19509.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_is_32b[0:0] 1'0 + case + assign $1\SHIFT_ROT_dec31_dec_sub26_is_32b[0:0] 1'0 + end + sync always + update \SHIFT_ROT_dec31_dec_sub26_is_32b $0\SHIFT_ROT_dec31_dec_sub26_is_32b[0:0] + end + attribute \src "libresoc.v:19524.3-19539.6" + process $proc$libresoc.v:19524$404 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub26_sgn[0:0] $1\SHIFT_ROT_dec31_dec_sub26_sgn[0:0] + attribute \src "libresoc.v:19525.5-19525.29" + switch \initial + attribute \src "libresoc.v:19525.9-19525.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_sgn[0:0] 1'1 + case + assign $1\SHIFT_ROT_dec31_dec_sub26_sgn[0:0] 1'0 + end + sync always + update \SHIFT_ROT_dec31_dec_sub26_sgn $0\SHIFT_ROT_dec31_dec_sub26_sgn[0:0] + end + attribute \src "libresoc.v:19540.3-19555.6" + process $proc$libresoc.v:19540$405 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub26_internal_op[6:0] $1\SHIFT_ROT_dec31_dec_sub26_internal_op[6:0] + attribute \src "libresoc.v:19541.5-19541.29" + switch \initial + attribute \src "libresoc.v:19541.9-19541.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_internal_op[6:0] 7'0100000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_internal_op[6:0] 7'0111101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_internal_op[6:0] 7'0111101 + case + assign $1\SHIFT_ROT_dec31_dec_sub26_internal_op[6:0] 7'0000000 + end + sync always + update \SHIFT_ROT_dec31_dec_sub26_internal_op $0\SHIFT_ROT_dec31_dec_sub26_internal_op[6:0] + end + attribute \src "libresoc.v:19556.3-19571.6" + process $proc$libresoc.v:19556$406 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub26_in2_sel[3:0] $1\SHIFT_ROT_dec31_dec_sub26_in2_sel[3:0] + attribute \src "libresoc.v:19557.5-19557.29" + switch \initial + attribute \src "libresoc.v:19557.9-19557.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_in2_sel[3:0] 4'1010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_in2_sel[3:0] 4'1010 + case + assign $1\SHIFT_ROT_dec31_dec_sub26_in2_sel[3:0] 4'0000 + end + sync always + update \SHIFT_ROT_dec31_dec_sub26_in2_sel $0\SHIFT_ROT_dec31_dec_sub26_in2_sel[3:0] + end + attribute \src "libresoc.v:19572.3-19587.6" + process $proc$libresoc.v:19572$407 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub26_cr_in[2:0] $1\SHIFT_ROT_dec31_dec_sub26_cr_in[2:0] + attribute \src "libresoc.v:19573.5-19573.29" + switch \initial + attribute \src "libresoc.v:19573.9-19573.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_cr_in[2:0] 3'000 + case + assign $1\SHIFT_ROT_dec31_dec_sub26_cr_in[2:0] 3'000 + end + sync always + update \SHIFT_ROT_dec31_dec_sub26_cr_in $0\SHIFT_ROT_dec31_dec_sub26_cr_in[2:0] + end + attribute \src "libresoc.v:19588.3-19603.6" + process $proc$libresoc.v:19588$408 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub26_cr_out[2:0] $1\SHIFT_ROT_dec31_dec_sub26_cr_out[2:0] + attribute \src "libresoc.v:19589.5-19589.29" + switch \initial + attribute \src "libresoc.v:19589.9-19589.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_cr_out[2:0] 3'001 + case + assign $1\SHIFT_ROT_dec31_dec_sub26_cr_out[2:0] 3'000 + end + sync always + update \SHIFT_ROT_dec31_dec_sub26_cr_out $0\SHIFT_ROT_dec31_dec_sub26_cr_out[2:0] + end + attribute \src "libresoc.v:19604.3-19619.6" + process $proc$libresoc.v:19604$409 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub26_rc_sel[1:0] $1\SHIFT_ROT_dec31_dec_sub26_rc_sel[1:0] + attribute \src "libresoc.v:19605.5-19605.29" + switch \initial + attribute \src "libresoc.v:19605.9-19605.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_rc_sel[1:0] 2'10 + case + assign $1\SHIFT_ROT_dec31_dec_sub26_rc_sel[1:0] 2'00 + end + sync always + update \SHIFT_ROT_dec31_dec_sub26_rc_sel $0\SHIFT_ROT_dec31_dec_sub26_rc_sel[1:0] + end + attribute \src "libresoc.v:19620.3-19635.6" + process $proc$libresoc.v:19620$410 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub26_cry_in[1:0] $1\SHIFT_ROT_dec31_dec_sub26_cry_in[1:0] + attribute \src "libresoc.v:19621.5-19621.29" + switch \initial + attribute \src "libresoc.v:19621.9-19621.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_cry_in[1:0] 2'00 + case + assign $1\SHIFT_ROT_dec31_dec_sub26_cry_in[1:0] 2'00 + end + sync always + update \SHIFT_ROT_dec31_dec_sub26_cry_in $0\SHIFT_ROT_dec31_dec_sub26_cry_in[1:0] + end + attribute \src "libresoc.v:19636.3-19651.6" + process $proc$libresoc.v:19636$411 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub26_inv_a[0:0] $1\SHIFT_ROT_dec31_dec_sub26_inv_a[0:0] + attribute \src "libresoc.v:19637.5-19637.29" + switch \initial + attribute \src "libresoc.v:19637.9-19637.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_inv_a[0:0] 1'0 + case + assign $1\SHIFT_ROT_dec31_dec_sub26_inv_a[0:0] 1'0 + end + sync always + update \SHIFT_ROT_dec31_dec_sub26_inv_a $0\SHIFT_ROT_dec31_dec_sub26_inv_a[0:0] + end + attribute \src "libresoc.v:19652.3-19667.6" + process $proc$libresoc.v:19652$412 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub26_cry_out[0:0] $1\SHIFT_ROT_dec31_dec_sub26_cry_out[0:0] + attribute \src "libresoc.v:19653.5-19653.29" + switch \initial + attribute \src "libresoc.v:19653.9-19653.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_cry_out[0:0] 1'1 + case + assign $1\SHIFT_ROT_dec31_dec_sub26_cry_out[0:0] 1'0 + end + sync always + update \SHIFT_ROT_dec31_dec_sub26_cry_out $0\SHIFT_ROT_dec31_dec_sub26_cry_out[0:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:19673.1-20049.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SHIFT_ROT.dec.SHIFT_ROT_dec31.SHIFT_ROT_dec31_dec_sub27" +attribute \generator "nMigen" +module \SHIFT_ROT_dec31_dec_sub27 + attribute \src "libresoc.v:19934.3-19952.6" + wire width 3 $0\SHIFT_ROT_dec31_dec_sub27_cr_in[2:0] + attribute \src "libresoc.v:19953.3-19971.6" + wire width 3 $0\SHIFT_ROT_dec31_dec_sub27_cr_out[2:0] + attribute \src "libresoc.v:19991.3-20009.6" + wire width 2 $0\SHIFT_ROT_dec31_dec_sub27_cry_in[1:0] + attribute \src "libresoc.v:20029.3-20047.6" + wire $0\SHIFT_ROT_dec31_dec_sub27_cry_out[0:0] + attribute \src "libresoc.v:19839.3-19857.6" + wire width 13 $0\SHIFT_ROT_dec31_dec_sub27_function_unit[12:0] + attribute \src "libresoc.v:19915.3-19933.6" + wire width 4 $0\SHIFT_ROT_dec31_dec_sub27_in2_sel[3:0] + attribute \src "libresoc.v:19896.3-19914.6" + wire width 7 $0\SHIFT_ROT_dec31_dec_sub27_internal_op[6:0] + attribute \src "libresoc.v:20010.3-20028.6" + wire $0\SHIFT_ROT_dec31_dec_sub27_inv_a[0:0] + attribute \src "libresoc.v:19858.3-19876.6" + wire $0\SHIFT_ROT_dec31_dec_sub27_is_32b[0:0] + attribute \src "libresoc.v:19972.3-19990.6" + wire width 2 $0\SHIFT_ROT_dec31_dec_sub27_rc_sel[1:0] + attribute \src "libresoc.v:19877.3-19895.6" + wire $0\SHIFT_ROT_dec31_dec_sub27_sgn[0:0] + attribute \src "libresoc.v:19674.7-19674.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:19934.3-19952.6" + wire width 3 $1\SHIFT_ROT_dec31_dec_sub27_cr_in[2:0] + attribute \src "libresoc.v:19953.3-19971.6" + wire width 3 $1\SHIFT_ROT_dec31_dec_sub27_cr_out[2:0] + attribute \src "libresoc.v:19991.3-20009.6" + wire width 2 $1\SHIFT_ROT_dec31_dec_sub27_cry_in[1:0] + attribute \src "libresoc.v:20029.3-20047.6" + wire $1\SHIFT_ROT_dec31_dec_sub27_cry_out[0:0] + attribute \src "libresoc.v:19839.3-19857.6" + wire width 13 $1\SHIFT_ROT_dec31_dec_sub27_function_unit[12:0] + attribute \src "libresoc.v:19915.3-19933.6" + wire width 4 $1\SHIFT_ROT_dec31_dec_sub27_in2_sel[3:0] + attribute \src "libresoc.v:19896.3-19914.6" + wire width 7 $1\SHIFT_ROT_dec31_dec_sub27_internal_op[6:0] + attribute \src "libresoc.v:20010.3-20028.6" + wire $1\SHIFT_ROT_dec31_dec_sub27_inv_a[0:0] + attribute \src "libresoc.v:19858.3-19876.6" + wire $1\SHIFT_ROT_dec31_dec_sub27_is_32b[0:0] + attribute \src "libresoc.v:19972.3-19990.6" + wire width 2 $1\SHIFT_ROT_dec31_dec_sub27_rc_sel[1:0] + attribute \src "libresoc.v:19877.3-19895.6" + wire $1\SHIFT_ROT_dec31_dec_sub27_sgn[0:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 4 \SHIFT_ROT_dec31_dec_sub27_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 5 \SHIFT_ROT_dec31_dec_sub27_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 7 \SHIFT_ROT_dec31_dec_sub27_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 9 \SHIFT_ROT_dec31_dec_sub27_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 13 output 1 \SHIFT_ROT_dec31_dec_sub27_function_unit + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 3 \SHIFT_ROT_dec31_dec_sub27_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 output 2 \SHIFT_ROT_dec31_dec_sub27_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 8 \SHIFT_ROT_dec31_dec_sub27_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 10 \SHIFT_ROT_dec31_dec_sub27_is_32b + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 6 \SHIFT_ROT_dec31_dec_sub27_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 11 \SHIFT_ROT_dec31_dec_sub27_sgn + attribute \src "libresoc.v:19674.7-19674.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + wire width 32 input 12 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + wire width 5 \opcode_switch + attribute \src "libresoc.v:19674.7-19674.20" + process $proc$libresoc.v:19674$425 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:19839.3-19857.6" + process $proc$libresoc.v:19839$414 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub27_function_unit[12:0] $1\SHIFT_ROT_dec31_dec_sub27_function_unit[12:0] + attribute \src "libresoc.v:19840.5-19840.29" + switch \initial + attribute \src "libresoc.v:19840.9-19840.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_function_unit[12:0] 13'0000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_function_unit[12:0] 13'0000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_function_unit[12:0] 13'0000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_function_unit[12:0] 13'0000000001000 + case + assign $1\SHIFT_ROT_dec31_dec_sub27_function_unit[12:0] 13'0000000000000 + end + sync always + update \SHIFT_ROT_dec31_dec_sub27_function_unit $0\SHIFT_ROT_dec31_dec_sub27_function_unit[12:0] + end + attribute \src "libresoc.v:19858.3-19876.6" + process $proc$libresoc.v:19858$415 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub27_is_32b[0:0] $1\SHIFT_ROT_dec31_dec_sub27_is_32b[0:0] + attribute \src "libresoc.v:19859.5-19859.29" + switch \initial + attribute \src "libresoc.v:19859.9-19859.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_is_32b[0:0] 1'0 + case + assign $1\SHIFT_ROT_dec31_dec_sub27_is_32b[0:0] 1'0 + end + sync always + update \SHIFT_ROT_dec31_dec_sub27_is_32b $0\SHIFT_ROT_dec31_dec_sub27_is_32b[0:0] + end + attribute \src "libresoc.v:19877.3-19895.6" + process $proc$libresoc.v:19877$416 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub27_sgn[0:0] $1\SHIFT_ROT_dec31_dec_sub27_sgn[0:0] + attribute \src "libresoc.v:19878.5-19878.29" + switch \initial + attribute \src "libresoc.v:19878.9-19878.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_sgn[0:0] 1'0 + case + assign $1\SHIFT_ROT_dec31_dec_sub27_sgn[0:0] 1'0 + end + sync always + update \SHIFT_ROT_dec31_dec_sub27_sgn $0\SHIFT_ROT_dec31_dec_sub27_sgn[0:0] + end + attribute \src "libresoc.v:19896.3-19914.6" + process $proc$libresoc.v:19896$417 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub27_internal_op[6:0] $1\SHIFT_ROT_dec31_dec_sub27_internal_op[6:0] + attribute \src "libresoc.v:19897.5-19897.29" + switch \initial + attribute \src "libresoc.v:19897.9-19897.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_internal_op[6:0] 7'0100000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_internal_op[6:0] 7'0111100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_internal_op[6:0] 7'0111101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_internal_op[6:0] 7'0111101 + case + assign $1\SHIFT_ROT_dec31_dec_sub27_internal_op[6:0] 7'0000000 + end + sync always + update \SHIFT_ROT_dec31_dec_sub27_internal_op $0\SHIFT_ROT_dec31_dec_sub27_internal_op[6:0] + end + attribute \src "libresoc.v:19915.3-19933.6" + process $proc$libresoc.v:19915$418 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub27_in2_sel[3:0] $1\SHIFT_ROT_dec31_dec_sub27_in2_sel[3:0] + attribute \src "libresoc.v:19916.5-19916.29" + switch \initial + attribute \src "libresoc.v:19916.9-19916.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_in2_sel[3:0] 4'1010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_in2_sel[3:0] 4'1010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_in2_sel[3:0] 4'0001 + case + assign $1\SHIFT_ROT_dec31_dec_sub27_in2_sel[3:0] 4'0000 + end + sync always + update \SHIFT_ROT_dec31_dec_sub27_in2_sel $0\SHIFT_ROT_dec31_dec_sub27_in2_sel[3:0] + end + attribute \src "libresoc.v:19934.3-19952.6" + process $proc$libresoc.v:19934$419 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub27_cr_in[2:0] $1\SHIFT_ROT_dec31_dec_sub27_cr_in[2:0] + attribute \src "libresoc.v:19935.5-19935.29" + switch \initial + attribute \src "libresoc.v:19935.9-19935.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_cr_in[2:0] 3'000 + case + assign $1\SHIFT_ROT_dec31_dec_sub27_cr_in[2:0] 3'000 + end + sync always + update \SHIFT_ROT_dec31_dec_sub27_cr_in $0\SHIFT_ROT_dec31_dec_sub27_cr_in[2:0] + end + attribute \src "libresoc.v:19953.3-19971.6" + process $proc$libresoc.v:19953$420 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub27_cr_out[2:0] $1\SHIFT_ROT_dec31_dec_sub27_cr_out[2:0] + attribute \src "libresoc.v:19954.5-19954.29" + switch \initial + attribute \src "libresoc.v:19954.9-19954.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_cr_out[2:0] 3'001 + case + assign $1\SHIFT_ROT_dec31_dec_sub27_cr_out[2:0] 3'000 + end + sync always + update \SHIFT_ROT_dec31_dec_sub27_cr_out $0\SHIFT_ROT_dec31_dec_sub27_cr_out[2:0] + end + attribute \src "libresoc.v:19972.3-19990.6" + process $proc$libresoc.v:19972$421 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub27_rc_sel[1:0] $1\SHIFT_ROT_dec31_dec_sub27_rc_sel[1:0] + attribute \src "libresoc.v:19973.5-19973.29" + switch \initial + attribute \src "libresoc.v:19973.9-19973.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_rc_sel[1:0] 2'10 + case + assign $1\SHIFT_ROT_dec31_dec_sub27_rc_sel[1:0] 2'00 + end + sync always + update \SHIFT_ROT_dec31_dec_sub27_rc_sel $0\SHIFT_ROT_dec31_dec_sub27_rc_sel[1:0] + end + attribute \src "libresoc.v:19991.3-20009.6" + process $proc$libresoc.v:19991$422 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub27_cry_in[1:0] $1\SHIFT_ROT_dec31_dec_sub27_cry_in[1:0] + attribute \src "libresoc.v:19992.5-19992.29" + switch \initial + attribute \src "libresoc.v:19992.9-19992.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_cry_in[1:0] 2'00 + case + assign $1\SHIFT_ROT_dec31_dec_sub27_cry_in[1:0] 2'00 + end + sync always + update \SHIFT_ROT_dec31_dec_sub27_cry_in $0\SHIFT_ROT_dec31_dec_sub27_cry_in[1:0] + end + attribute \src "libresoc.v:20010.3-20028.6" + process $proc$libresoc.v:20010$423 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub27_inv_a[0:0] $1\SHIFT_ROT_dec31_dec_sub27_inv_a[0:0] + attribute \src "libresoc.v:20011.5-20011.29" + switch \initial + attribute \src "libresoc.v:20011.9-20011.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_inv_a[0:0] 1'0 + case + assign $1\SHIFT_ROT_dec31_dec_sub27_inv_a[0:0] 1'0 + end + sync always + update \SHIFT_ROT_dec31_dec_sub27_inv_a $0\SHIFT_ROT_dec31_dec_sub27_inv_a[0:0] + end + attribute \src "libresoc.v:20029.3-20047.6" + process $proc$libresoc.v:20029$424 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub27_cry_out[0:0] $1\SHIFT_ROT_dec31_dec_sub27_cry_out[0:0] + attribute \src "libresoc.v:20030.5-20030.29" + switch \initial + attribute \src "libresoc.v:20030.9-20030.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_cry_out[0:0] 1'0 + case + assign $1\SHIFT_ROT_dec31_dec_sub27_cry_out[0:0] 1'0 + end + sync always + update \SHIFT_ROT_dec31_dec_sub27_cry_out $0\SHIFT_ROT_dec31_dec_sub27_cry_out[0:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:20053.1-20381.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SPR.dec.SPR_dec31" +attribute \generator "nMigen" +module \SPR_dec31 + attribute \src "libresoc.v:20338.3-20347.6" + wire width 3 $0\SPR_dec31_cr_in[2:0] + attribute \src "libresoc.v:20348.3-20357.6" + wire width 3 $0\SPR_dec31_cr_out[2:0] + attribute \src "libresoc.v:20318.3-20327.6" + wire width 13 $0\SPR_dec31_function_unit[12:0] + attribute \src "libresoc.v:20328.3-20337.6" + wire width 7 $0\SPR_dec31_internal_op[6:0] + attribute \src "libresoc.v:20368.3-20377.6" + wire $0\SPR_dec31_is_32b[0:0] + attribute \src "libresoc.v:20358.3-20367.6" + wire width 2 $0\SPR_dec31_rc_sel[1:0] + attribute \src "libresoc.v:20054.7-20054.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:20338.3-20347.6" + wire width 3 $1\SPR_dec31_cr_in[2:0] + attribute \src "libresoc.v:20348.3-20357.6" + wire width 3 $1\SPR_dec31_cr_out[2:0] + attribute \src "libresoc.v:20318.3-20327.6" + wire width 13 $1\SPR_dec31_function_unit[12:0] + attribute \src "libresoc.v:20328.3-20337.6" + wire width 7 $1\SPR_dec31_internal_op[6:0] + attribute \src "libresoc.v:20368.3-20377.6" + wire $1\SPR_dec31_is_32b[0:0] + attribute \src "libresoc.v:20358.3-20367.6" + wire width 2 $1\SPR_dec31_rc_sel[1:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 3 \SPR_dec31_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 4 \SPR_dec31_cr_out + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 13 \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_is_32b + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + wire width 32 \SPR_dec31_dec_sub19_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 13 output 1 \SPR_dec31_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 output 2 \SPR_dec31_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 6 \SPR_dec31_is_32b + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 5 \SPR_dec31_rc_sel + attribute \src "libresoc.v:20054.7-20054.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:347" + wire width 5 \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + wire width 32 input 7 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + wire width 10 \opcode_switch + attribute \module_not_derived 1 + attribute \src "libresoc.v:20309.23-20317.4" + cell \SPR_dec31_dec_sub19 \SPR_dec31_dec_sub19 + connect \SPR_dec31_dec_sub19_cr_in \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_cr_in + connect \SPR_dec31_dec_sub19_cr_out \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_cr_out + connect \SPR_dec31_dec_sub19_function_unit \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_function_unit + connect \SPR_dec31_dec_sub19_internal_op \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_internal_op + connect \SPR_dec31_dec_sub19_is_32b \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_is_32b + connect \SPR_dec31_dec_sub19_rc_sel \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_rc_sel + connect \opcode_in \SPR_dec31_dec_sub19_opcode_in + end + attribute \src "libresoc.v:20054.7-20054.20" + process $proc$libresoc.v:20054$432 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:20318.3-20327.6" + process $proc$libresoc.v:20318$426 + assign { } { } + assign { } { } + assign $0\SPR_dec31_function_unit[12:0] $1\SPR_dec31_function_unit[12:0] + attribute \src "libresoc.v:20319.5-20319.29" + switch \initial + attribute \src "libresoc.v:20319.9-20319.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\SPR_dec31_function_unit[12:0] \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_function_unit + case + assign $1\SPR_dec31_function_unit[12:0] 13'0000000000000 + end + sync always + update \SPR_dec31_function_unit $0\SPR_dec31_function_unit[12:0] + end + attribute \src "libresoc.v:20328.3-20337.6" + process $proc$libresoc.v:20328$427 + assign { } { } + assign { } { } + assign $0\SPR_dec31_internal_op[6:0] $1\SPR_dec31_internal_op[6:0] + attribute \src "libresoc.v:20329.5-20329.29" + switch \initial + attribute \src "libresoc.v:20329.9-20329.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\SPR_dec31_internal_op[6:0] \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_internal_op + case + assign $1\SPR_dec31_internal_op[6:0] 7'0000000 + end + sync always + update \SPR_dec31_internal_op $0\SPR_dec31_internal_op[6:0] + end + attribute \src "libresoc.v:20338.3-20347.6" + process $proc$libresoc.v:20338$428 + assign { } { } + assign { } { } + assign $0\SPR_dec31_cr_in[2:0] $1\SPR_dec31_cr_in[2:0] + attribute \src "libresoc.v:20339.5-20339.29" + switch \initial + attribute \src "libresoc.v:20339.9-20339.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\SPR_dec31_cr_in[2:0] \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_cr_in + case + assign $1\SPR_dec31_cr_in[2:0] 3'000 + end + sync always + update \SPR_dec31_cr_in $0\SPR_dec31_cr_in[2:0] + end + attribute \src "libresoc.v:20348.3-20357.6" + process $proc$libresoc.v:20348$429 + assign { } { } + assign { } { } + assign $0\SPR_dec31_cr_out[2:0] $1\SPR_dec31_cr_out[2:0] + attribute \src "libresoc.v:20349.5-20349.29" + switch \initial + attribute \src "libresoc.v:20349.9-20349.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\SPR_dec31_cr_out[2:0] \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_cr_out + case + assign $1\SPR_dec31_cr_out[2:0] 3'000 + end + sync always + update \SPR_dec31_cr_out $0\SPR_dec31_cr_out[2:0] + end + attribute \src "libresoc.v:20358.3-20367.6" + process $proc$libresoc.v:20358$430 + assign { } { } + assign { } { } + assign $0\SPR_dec31_rc_sel[1:0] $1\SPR_dec31_rc_sel[1:0] + attribute \src "libresoc.v:20359.5-20359.29" + switch \initial + attribute \src "libresoc.v:20359.9-20359.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\SPR_dec31_rc_sel[1:0] \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_rc_sel + case + assign $1\SPR_dec31_rc_sel[1:0] 2'00 + end + sync always + update \SPR_dec31_rc_sel $0\SPR_dec31_rc_sel[1:0] + end + attribute \src "libresoc.v:20368.3-20377.6" + process $proc$libresoc.v:20368$431 + assign { } { } + assign { } { } + assign $0\SPR_dec31_is_32b[0:0] $1\SPR_dec31_is_32b[0:0] + attribute \src "libresoc.v:20369.5-20369.29" + switch \initial + attribute \src "libresoc.v:20369.9-20369.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\SPR_dec31_is_32b[0:0] \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_is_32b + case + assign $1\SPR_dec31_is_32b[0:0] 1'0 + end + sync always + update \SPR_dec31_is_32b $0\SPR_dec31_is_32b[0:0] + end + connect \SPR_dec31_dec_sub19_opcode_in \opcode_in + connect \opc_in \opcode_switch [4:0] + connect \opcode_switch \opcode_in [10:1] +end +attribute \src "libresoc.v:20385.1-20596.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SPR.dec.SPR_dec31.SPR_dec31_dec_sub19" +attribute \generator "nMigen" +module \SPR_dec31_dec_sub19 + attribute \src "libresoc.v:20543.3-20555.6" + wire width 3 $0\SPR_dec31_dec_sub19_cr_in[2:0] + attribute \src "libresoc.v:20556.3-20568.6" + wire width 3 $0\SPR_dec31_dec_sub19_cr_out[2:0] + attribute \src "libresoc.v:20517.3-20529.6" + wire width 13 $0\SPR_dec31_dec_sub19_function_unit[12:0] + attribute \src "libresoc.v:20530.3-20542.6" + wire width 7 $0\SPR_dec31_dec_sub19_internal_op[6:0] + attribute \src "libresoc.v:20582.3-20594.6" + wire $0\SPR_dec31_dec_sub19_is_32b[0:0] + attribute \src "libresoc.v:20569.3-20581.6" + wire width 2 $0\SPR_dec31_dec_sub19_rc_sel[1:0] + attribute \src "libresoc.v:20386.7-20386.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:20543.3-20555.6" + wire width 3 $1\SPR_dec31_dec_sub19_cr_in[2:0] + attribute \src "libresoc.v:20556.3-20568.6" + wire width 3 $1\SPR_dec31_dec_sub19_cr_out[2:0] + attribute \src "libresoc.v:20517.3-20529.6" + wire width 13 $1\SPR_dec31_dec_sub19_function_unit[12:0] + attribute \src "libresoc.v:20530.3-20542.6" + wire width 7 $1\SPR_dec31_dec_sub19_internal_op[6:0] + attribute \src "libresoc.v:20582.3-20594.6" + wire $1\SPR_dec31_dec_sub19_is_32b[0:0] + attribute \src "libresoc.v:20569.3-20581.6" + wire width 2 $1\SPR_dec31_dec_sub19_rc_sel[1:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 3 \SPR_dec31_dec_sub19_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 4 \SPR_dec31_dec_sub19_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 13 output 1 \SPR_dec31_dec_sub19_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 output 2 \SPR_dec31_dec_sub19_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 6 \SPR_dec31_dec_sub19_is_32b + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 5 \SPR_dec31_dec_sub19_rc_sel + attribute \src "libresoc.v:20386.7-20386.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + wire width 32 input 7 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + wire width 5 \opcode_switch + attribute \src "libresoc.v:20386.7-20386.20" + process $proc$libresoc.v:20386$439 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:20517.3-20529.6" + process $proc$libresoc.v:20517$433 + assign { } { } + assign { } { } + assign $0\SPR_dec31_dec_sub19_function_unit[12:0] $1\SPR_dec31_dec_sub19_function_unit[12:0] + attribute \src "libresoc.v:20518.5-20518.29" + switch \initial + attribute \src "libresoc.v:20518.9-20518.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\SPR_dec31_dec_sub19_function_unit[12:0] 13'0010000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\SPR_dec31_dec_sub19_function_unit[12:0] 13'0010000000000 + case + assign $1\SPR_dec31_dec_sub19_function_unit[12:0] 13'0000000000000 + end + sync always + update \SPR_dec31_dec_sub19_function_unit $0\SPR_dec31_dec_sub19_function_unit[12:0] + end + attribute \src "libresoc.v:20530.3-20542.6" + process $proc$libresoc.v:20530$434 + assign { } { } + assign { } { } + assign $0\SPR_dec31_dec_sub19_internal_op[6:0] $1\SPR_dec31_dec_sub19_internal_op[6:0] + attribute \src "libresoc.v:20531.5-20531.29" + switch \initial + attribute \src "libresoc.v:20531.9-20531.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\SPR_dec31_dec_sub19_internal_op[6:0] 7'0101110 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\SPR_dec31_dec_sub19_internal_op[6:0] 7'0110001 + case + assign $1\SPR_dec31_dec_sub19_internal_op[6:0] 7'0000000 + end + sync always + update \SPR_dec31_dec_sub19_internal_op $0\SPR_dec31_dec_sub19_internal_op[6:0] + end + attribute \src "libresoc.v:20543.3-20555.6" + process $proc$libresoc.v:20543$435 + assign { } { } + assign { } { } + assign $0\SPR_dec31_dec_sub19_cr_in[2:0] $1\SPR_dec31_dec_sub19_cr_in[2:0] + attribute \src "libresoc.v:20544.5-20544.29" + switch \initial + attribute \src "libresoc.v:20544.9-20544.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\SPR_dec31_dec_sub19_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\SPR_dec31_dec_sub19_cr_in[2:0] 3'000 + case + assign $1\SPR_dec31_dec_sub19_cr_in[2:0] 3'000 + end + sync always + update \SPR_dec31_dec_sub19_cr_in $0\SPR_dec31_dec_sub19_cr_in[2:0] + end + attribute \src "libresoc.v:20556.3-20568.6" + process $proc$libresoc.v:20556$436 + assign { } { } + assign { } { } + assign $0\SPR_dec31_dec_sub19_cr_out[2:0] $1\SPR_dec31_dec_sub19_cr_out[2:0] + attribute \src "libresoc.v:20557.5-20557.29" + switch \initial + attribute \src "libresoc.v:20557.9-20557.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\SPR_dec31_dec_sub19_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\SPR_dec31_dec_sub19_cr_out[2:0] 3'000 + case + assign $1\SPR_dec31_dec_sub19_cr_out[2:0] 3'000 + end + sync always + update \SPR_dec31_dec_sub19_cr_out $0\SPR_dec31_dec_sub19_cr_out[2:0] + end + attribute \src "libresoc.v:20569.3-20581.6" + process $proc$libresoc.v:20569$437 + assign { } { } + assign { } { } + assign $0\SPR_dec31_dec_sub19_rc_sel[1:0] $1\SPR_dec31_dec_sub19_rc_sel[1:0] + attribute \src "libresoc.v:20570.5-20570.29" + switch \initial + attribute \src "libresoc.v:20570.9-20570.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\SPR_dec31_dec_sub19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\SPR_dec31_dec_sub19_rc_sel[1:0] 2'00 + case + assign $1\SPR_dec31_dec_sub19_rc_sel[1:0] 2'00 + end + sync always + update \SPR_dec31_dec_sub19_rc_sel $0\SPR_dec31_dec_sub19_rc_sel[1:0] + end + attribute \src "libresoc.v:20582.3-20594.6" + process $proc$libresoc.v:20582$438 + assign { } { } + assign { } { } + assign $0\SPR_dec31_dec_sub19_is_32b[0:0] $1\SPR_dec31_dec_sub19_is_32b[0:0] + attribute \src "libresoc.v:20583.5-20583.29" + switch \initial + attribute \src "libresoc.v:20583.9-20583.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\SPR_dec31_dec_sub19_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\SPR_dec31_dec_sub19_is_32b[0:0] 1'0 + case + assign $1\SPR_dec31_dec_sub19_is_32b[0:0] 1'0 + end + sync always + update \SPR_dec31_dec_sub19_is_32b $0\SPR_dec31_dec_sub19_is_32b[0:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:20600.1-20872.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.jtag._fsm" +attribute \generator "nMigen" +module \_fsm + attribute \src "libresoc.v:20720.3-20834.6" + wire width 4 $0\fsm_state$next[3:0]$464 + attribute \src "libresoc.v:20686.3-20687.35" + wire width 4 $0\fsm_state[3:0] + attribute \src "libresoc.v:20601.7-20601.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:20692.3-20719.6" + wire $0\isdr$next[0:0]$460 + attribute \src "libresoc.v:20688.3-20689.25" + wire $0\isdr[0:0] + attribute \src "libresoc.v:20835.3-20862.6" + wire $0\isir$next[0:0]$477 + attribute \src "libresoc.v:20690.3-20691.25" + wire $0\isir[0:0] + attribute \src "libresoc.v:20720.3-20834.6" + wire width 4 $10\fsm_state$next[3:0]$474 + attribute \src "libresoc.v:20720.3-20834.6" + wire width 4 $11\fsm_state$next[3:0]$475 + attribute \src "libresoc.v:20720.3-20834.6" + wire width 4 $1\fsm_state$next[3:0]$465 + attribute \src "libresoc.v:20641.13-20641.29" + wire width 4 $1\fsm_state[3:0] + attribute \src "libresoc.v:20692.3-20719.6" + wire $1\isdr$next[0:0]$461 + attribute \src "libresoc.v:20646.7-20646.18" + wire $1\isdr[0:0] + attribute \src "libresoc.v:20835.3-20862.6" + wire $1\isir$next[0:0]$478 + attribute \src "libresoc.v:20651.7-20651.18" + wire $1\isir[0:0] + attribute \src "libresoc.v:20720.3-20834.6" + wire width 4 $2\fsm_state$next[3:0]$466 + attribute \src "libresoc.v:20692.3-20719.6" + wire $2\isdr$next[0:0]$462 + attribute \src "libresoc.v:20835.3-20862.6" + wire $2\isir$next[0:0]$479 + attribute \src "libresoc.v:20720.3-20834.6" + wire width 4 $3\fsm_state$next[3:0]$467 + attribute \src "libresoc.v:20720.3-20834.6" + wire width 4 $4\fsm_state$next[3:0]$468 + attribute \src "libresoc.v:20720.3-20834.6" + wire width 4 $5\fsm_state$next[3:0]$469 + attribute \src "libresoc.v:20720.3-20834.6" + wire width 4 $6\fsm_state$next[3:0]$470 + attribute \src "libresoc.v:20720.3-20834.6" + wire width 4 $7\fsm_state$next[3:0]$471 + attribute \src "libresoc.v:20720.3-20834.6" + wire width 4 $8\fsm_state$next[3:0]$472 + attribute \src "libresoc.v:20720.3-20834.6" + wire width 4 $9\fsm_state$next[3:0]$473 + attribute \src "libresoc.v:20670.17-20670.110" + wire $eq$libresoc.v:20670$440_Y + attribute \src "libresoc.v:20671.18-20671.111" + wire $eq$libresoc.v:20671$441_Y + attribute \src "libresoc.v:20672.18-20672.111" + wire $eq$libresoc.v:20672$442_Y + attribute \src "libresoc.v:20673.18-20673.111" + wire $eq$libresoc.v:20673$443_Y + attribute \src "libresoc.v:20674.18-20674.111" + wire $eq$libresoc.v:20674$444_Y + attribute \src "libresoc.v:20675.17-20675.108" + wire $eq$libresoc.v:20675$445_Y + attribute \src "libresoc.v:20676.18-20676.111" + wire $eq$libresoc.v:20676$446_Y + attribute \src "libresoc.v:20677.18-20677.111" + wire $eq$libresoc.v:20677$447_Y + attribute \src "libresoc.v:20678.18-20678.111" + wire $eq$libresoc.v:20678$448_Y + attribute \src "libresoc.v:20679.18-20679.111" + wire $eq$libresoc.v:20679$449_Y + attribute \src "libresoc.v:20680.18-20680.111" + wire $eq$libresoc.v:20680$450_Y + attribute \src "libresoc.v:20681.18-20681.111" + wire $eq$libresoc.v:20681$451_Y + attribute \src "libresoc.v:20682.18-20682.112" + wire $eq$libresoc.v:20682$452_Y + attribute \src "libresoc.v:20683.17-20683.108" + wire $eq$libresoc.v:20683$453_Y + attribute \src "libresoc.v:20684.17-20684.108" + wire $eq$libresoc.v:20684$454_Y + attribute \src "libresoc.v:20685.17-20685.108" + wire $eq$libresoc.v:20685$455_Y + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:113" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:70" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:59" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:67" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:70" + wire \$17 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:76" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:82" + wire \$21 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:87" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:90" + wire \$25 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:95" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:98" + wire \$29 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:114" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:107" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:115" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:116" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:76" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" + wire input 9 \TAP_bus__tck + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" + wire input 10 \TAP_bus__tms + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:24" + wire output 1 \capture + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:52" + wire width 4 \fsm_state + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:52" + wire width 4 \fsm_state$next + attribute \src "libresoc.v:20601.7-20601.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:23" + wire output 11 \isdr + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:23" + wire \isdr$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:22" + wire output 4 \isir + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:22" + wire \isir$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:49" + wire \local_clk + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:29" + wire output 8 \negjtag_clk + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:29" + wire output 6 \negjtag_rst + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:28" + wire output 7 \posjtag_clk + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:28" + wire output 5 \posjtag_rst + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:36" + wire \rst + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:25" + wire output 2 \shift + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:26" + wire output 3 \update + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:76" + cell $eq $eq$libresoc.v:20670$440 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \TAP_bus__tms + connect \B 1'0 + connect \Y $eq$libresoc.v:20670$440_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:70" + cell $eq $eq$libresoc.v:20671$441 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \TAP_bus__tms + connect \B 1'0 + connect \Y $eq$libresoc.v:20671$441_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:59" + cell $eq $eq$libresoc.v:20672$442 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \TAP_bus__tms + connect \B 1'0 + connect \Y $eq$libresoc.v:20672$442_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:67" + cell $eq $eq$libresoc.v:20673$443 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \TAP_bus__tms + connect \B 1'1 + connect \Y $eq$libresoc.v:20673$443_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:70" + cell $eq $eq$libresoc.v:20674$444 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \TAP_bus__tms + connect \B 1'0 + connect \Y $eq$libresoc.v:20674$444_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:113" + cell $eq $eq$libresoc.v:20675$445 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fsm_state + connect \B 1'0 + connect \Y $eq$libresoc.v:20675$445_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:76" + cell $eq $eq$libresoc.v:20676$446 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \TAP_bus__tms + connect \B 1'0 + connect \Y $eq$libresoc.v:20676$446_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:82" + cell $eq $eq$libresoc.v:20677$447 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \TAP_bus__tms + connect \B 1'0 + connect \Y $eq$libresoc.v:20677$447_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:87" + cell $eq $eq$libresoc.v:20678$448 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \TAP_bus__tms + connect \B 1'1 + connect \Y $eq$libresoc.v:20678$448_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:90" + cell $eq $eq$libresoc.v:20679$449 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \TAP_bus__tms + connect \B 1'0 + connect \Y $eq$libresoc.v:20679$449_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:95" + cell $eq $eq$libresoc.v:20680$450 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \TAP_bus__tms + connect \B 1'1 + connect \Y $eq$libresoc.v:20680$450_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:98" + cell $eq $eq$libresoc.v:20681$451 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \TAP_bus__tms + connect \B 1'0 + connect \Y $eq$libresoc.v:20681$451_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:107" + cell $eq $eq$libresoc.v:20682$452 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \TAP_bus__tms + connect \B 1'0 + connect \Y $eq$libresoc.v:20682$452_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:114" + cell $eq $eq$libresoc.v:20683$453 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \fsm_state + connect \B 2'11 + connect \Y $eq$libresoc.v:20683$453_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:115" + cell $eq $eq$libresoc.v:20684$454 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \fsm_state + connect \B 3'101 + connect \Y $eq$libresoc.v:20684$454_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:116" + cell $eq $eq$libresoc.v:20685$455 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \fsm_state + connect \B 4'1000 + connect \Y $eq$libresoc.v:20685$455_Y + end + attribute \src "libresoc.v:20601.7-20601.20" + process $proc$libresoc.v:20601$480 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:20641.13-20641.29" + process $proc$libresoc.v:20641$481 + assign { } { } + assign $1\fsm_state[3:0] 4'0000 + sync always + sync init + update \fsm_state $1\fsm_state[3:0] + end + attribute \src "libresoc.v:20646.7-20646.18" + process $proc$libresoc.v:20646$482 + assign { } { } + assign $1\isdr[0:0] 1'0 + sync always + sync init + update \isdr $1\isdr[0:0] + end + attribute \src "libresoc.v:20651.7-20651.18" + process $proc$libresoc.v:20651$483 + assign { } { } + assign $1\isir[0:0] 1'0 + sync always + sync init + update \isir $1\isir[0:0] + end + attribute \src "libresoc.v:20686.3-20687.35" + process $proc$libresoc.v:20686$456 + assign { } { } + assign $0\fsm_state[3:0] \fsm_state$next + sync posedge \local_clk + update \fsm_state $0\fsm_state[3:0] + end + attribute \src "libresoc.v:20688.3-20689.25" + process $proc$libresoc.v:20688$457 + assign { } { } + assign $0\isdr[0:0] \isdr$next + sync posedge \local_clk + update \isdr $0\isdr[0:0] + end + attribute \src "libresoc.v:20690.3-20691.25" + process $proc$libresoc.v:20690$458 + assign { } { } + assign $0\isir[0:0] \isir$next + sync posedge \local_clk + update \isir $0\isir[0:0] + end + attribute \src "libresoc.v:20692.3-20719.6" + process $proc$libresoc.v:20692$459 + assign { } { } + assign { } { } + assign $0\isdr$next[0:0]$460 $1\isdr$next[0:0]$461 + attribute \src "libresoc.v:20693.5-20693.29" + switch \initial + attribute \src "libresoc.v:20693.9-20693.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:52" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\isdr$next[0:0]$461 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\isdr$next[0:0]$461 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\isdr$next[0:0]$461 $2\isdr$next[0:0]$462 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:70" + switch \$11 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\isdr$next[0:0]$462 1'1 + case + assign $2\isdr$next[0:0]$462 \isdr + end + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\isdr$next[0:0]$461 1'0 + case + assign $1\isdr$next[0:0]$461 \isdr + end + sync always + update \isdr$next $0\isdr$next[0:0]$460 + end + attribute \src "libresoc.v:20720.3-20834.6" + process $proc$libresoc.v:20720$463 + assign { } { } + assign { } { } + assign $0\fsm_state$next[3:0]$464 $1\fsm_state$next[3:0]$465 + attribute \src "libresoc.v:20721.5-20721.29" + switch \initial + attribute \src "libresoc.v:20721.9-20721.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:52" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\fsm_state$next[3:0]$465 $2\fsm_state$next[3:0]$466 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:59" + switch \$13 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\fsm_state$next[3:0]$466 4'0001 + case + assign $2\fsm_state$next[3:0]$466 \fsm_state + end + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\fsm_state$next[3:0]$465 $3\fsm_state$next[3:0]$467 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:67" + switch \$15 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fsm_state$next[3:0]$467 4'0010 + case + assign $3\fsm_state$next[3:0]$467 \fsm_state + end + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\fsm_state$next[3:0]$465 $4\fsm_state$next[3:0]$468 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:70" + switch \$17 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\fsm_state$next[3:0]$468 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $4\fsm_state$next[3:0]$468 4'0100 + end + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\fsm_state$next[3:0]$465 $5\fsm_state$next[3:0]$469 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:76" + switch \$19 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\fsm_state$next[3:0]$469 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $5\fsm_state$next[3:0]$469 4'0000 + end + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\fsm_state$next[3:0]$465 $6\fsm_state$next[3:0]$470 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:82" + switch \$21 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\fsm_state$next[3:0]$470 4'0101 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $6\fsm_state$next[3:0]$470 4'0110 + end + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\fsm_state$next[3:0]$465 $7\fsm_state$next[3:0]$471 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:87" + switch \$23 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\fsm_state$next[3:0]$471 4'0110 + case + assign $7\fsm_state$next[3:0]$471 \fsm_state + end + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\fsm_state$next[3:0]$465 $8\fsm_state$next[3:0]$472 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:90" + switch \$25 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $8\fsm_state$next[3:0]$472 4'0111 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $8\fsm_state$next[3:0]$472 4'1000 + end + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\fsm_state$next[3:0]$465 $9\fsm_state$next[3:0]$473 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:95" + switch \$27 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $9\fsm_state$next[3:0]$473 4'1001 + case + assign $9\fsm_state$next[3:0]$473 \fsm_state + end + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\fsm_state$next[3:0]$465 $10\fsm_state$next[3:0]$474 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:98" + switch \$29 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $10\fsm_state$next[3:0]$474 4'0101 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $10\fsm_state$next[3:0]$474 4'1000 + end + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\fsm_state$next[3:0]$465 $11\fsm_state$next[3:0]$475 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:107" + switch \$31 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $11\fsm_state$next[3:0]$475 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $11\fsm_state$next[3:0]$475 4'0010 + end + case + assign $1\fsm_state$next[3:0]$465 \fsm_state + end + sync always + update \fsm_state$next $0\fsm_state$next[3:0]$464 + end + attribute \src "libresoc.v:20835.3-20862.6" + process $proc$libresoc.v:20835$476 + assign { } { } + assign { } { } + assign $0\isir$next[0:0]$477 $1\isir$next[0:0]$478 + attribute \src "libresoc.v:20836.5-20836.29" + switch \initial + attribute \src "libresoc.v:20836.9-20836.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:52" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\isir$next[0:0]$478 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\isir$next[0:0]$478 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\isir$next[0:0]$478 $2\isir$next[0:0]$479 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:76" + switch \$9 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\isir$next[0:0]$479 1'1 + case + assign $2\isir$next[0:0]$479 \isir + end + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\isir$next[0:0]$478 1'0 + case + assign $1\isir$next[0:0]$478 \isir + end + sync always + update \isir$next $0\isir$next[0:0]$477 + end + connect \$9 $eq$libresoc.v:20670$440_Y + connect \$11 $eq$libresoc.v:20671$441_Y + connect \$13 $eq$libresoc.v:20672$442_Y + connect \$15 $eq$libresoc.v:20673$443_Y + connect \$17 $eq$libresoc.v:20674$444_Y + connect \$1 $eq$libresoc.v:20675$445_Y + connect \$19 $eq$libresoc.v:20676$446_Y + connect \$21 $eq$libresoc.v:20677$447_Y + connect \$23 $eq$libresoc.v:20678$448_Y + connect \$25 $eq$libresoc.v:20679$449_Y + connect \$27 $eq$libresoc.v:20680$450_Y + connect \$29 $eq$libresoc.v:20681$451_Y + connect \$31 $eq$libresoc.v:20682$452_Y + connect \$3 $eq$libresoc.v:20683$453_Y + connect \$5 $eq$libresoc.v:20684$454_Y + connect \$7 $eq$libresoc.v:20685$455_Y + connect \update \$7 + connect \shift \$5 + connect \capture \$3 + connect \rst \$1 + connect \local_clk \TAP_bus__tck + connect \negjtag_rst \rst + connect \negjtag_clk \TAP_bus__tck + connect \posjtag_rst \rst + connect \posjtag_clk \TAP_bus__tck +end +attribute \src "libresoc.v:20876.1-20948.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.jtag._idblock" +attribute \generator "nMigen" +module \_idblock + attribute \src "libresoc.v:20921.3-20941.6" + wire width 32 $0\TAP_id_sr$next[31:0]$489 + attribute \src "libresoc.v:20919.3-20920.35" + wire width 32 $0\TAP_id_sr[31:0] + attribute \src "libresoc.v:20877.7-20877.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:20921.3-20941.6" + wire width 32 $1\TAP_id_sr$next[31:0]$490 + attribute \src "libresoc.v:20887.14-20887.31" + wire width 32 $1\TAP_id_sr[31:0] + attribute \src "libresoc.v:20921.3-20941.6" + wire width 32 $2\TAP_id_sr$next[31:0]$491 + attribute \src "libresoc.v:20916.17-20916.110" + wire $and$libresoc.v:20916$484_Y + attribute \src "libresoc.v:20917.17-20917.108" + wire $and$libresoc.v:20917$485_Y + attribute \src "libresoc.v:20918.17-20918.109" + wire $and$libresoc.v:20918$486_Y + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:383" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:384" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:385" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" + wire input 5 \TAP_bus__tdi + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:236" + wire width 32 \TAP_id_sr + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:236" + wire width 32 \TAP_id_sr$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:225" + wire output 6 \TAP_id_tdo + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:243" + wire \_bypass + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:240" + wire \_capture + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:241" + wire \_shift + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:239" + wire \_tdi + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:242" + wire \_update + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:24" + wire input 2 \capture + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:375" + wire input 1 \id_bypass + attribute \src "libresoc.v:20877.7-20877.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:28" + wire input 8 \posjtag_clk + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:28" + wire input 7 \posjtag_rst + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:374" + wire input 9 \select_id + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:25" + wire input 3 \shift + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:26" + wire input 4 \update + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:383" + cell $and $and$libresoc.v:20916$484 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \select_id + connect \B \capture + connect \Y $and$libresoc.v:20916$484_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:384" + cell $and $and$libresoc.v:20917$485 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \select_id + connect \B \shift + connect \Y $and$libresoc.v:20917$485_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:385" + cell $and $and$libresoc.v:20918$486 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \select_id + connect \B \update + connect \Y $and$libresoc.v:20918$486_Y + end + attribute \src "libresoc.v:20877.7-20877.20" + process $proc$libresoc.v:20877$492 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:20887.14-20887.31" + process $proc$libresoc.v:20887$493 + assign { } { } + assign $1\TAP_id_sr[31:0] 0 + sync always + sync init + update \TAP_id_sr $1\TAP_id_sr[31:0] + end + attribute \src "libresoc.v:20919.3-20920.35" + process $proc$libresoc.v:20919$487 + assign { } { } + assign $0\TAP_id_sr[31:0] \TAP_id_sr$next + sync posedge \posjtag_clk + update \TAP_id_sr $0\TAP_id_sr[31:0] + end + attribute \src "libresoc.v:20921.3-20941.6" + process $proc$libresoc.v:20921$488 + assign { } { } + assign { } { } + assign $0\TAP_id_sr$next[31:0]$489 $1\TAP_id_sr$next[31:0]$490 + attribute \src "libresoc.v:20922.5-20922.29" + switch \initial + attribute \src "libresoc.v:20922.9-20922.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:254" + switch { \_shift \_capture } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\TAP_id_sr$next[31:0]$490 6399 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\TAP_id_sr$next[31:0]$490 $2\TAP_id_sr$next[31:0]$491 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:257" + switch \_bypass + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $2\TAP_id_sr$next[31:0]$491 [31:1] \TAP_id_sr [31:1] + assign $2\TAP_id_sr$next[31:0]$491 [0] \_tdi + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\TAP_id_sr$next[31:0]$491 { \_tdi \TAP_id_sr [31:1] } + end + case + assign $1\TAP_id_sr$next[31:0]$490 \TAP_id_sr + end + sync always + update \TAP_id_sr$next $0\TAP_id_sr$next[31:0]$489 + end + connect \$1 $and$libresoc.v:20916$484_Y + connect \$3 $and$libresoc.v:20917$485_Y + connect \$5 $and$libresoc.v:20918$486_Y + connect \TAP_id_tdo \TAP_id_sr [0] + connect \_bypass \id_bypass + connect \_update \$5 + connect \_shift \$3 + connect \_capture \$1 + connect \_tdi \TAP_bus__tdi +end +attribute \src "libresoc.v:20952.1-21036.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.jtag._irblock" +attribute \generator "nMigen" +module \_irblock + attribute \src "libresoc.v:20953.7-20953.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:21014.3-21034.6" + wire width 4 $0\ir$next[3:0]$506 + attribute \src "libresoc.v:20997.3-20998.21" + wire width 4 $0\ir[3:0] + attribute \src "libresoc.v:21001.3-21013.6" + wire width 4 $0\shift_ir$next[3:0]$503 + attribute \src "libresoc.v:20999.3-21000.33" + wire width 4 $0\shift_ir[3:0] + attribute \src "libresoc.v:21014.3-21034.6" + wire width 4 $1\ir$next[3:0]$507 + attribute \src "libresoc.v:20972.13-20972.22" + wire width 4 $1\ir[3:0] + attribute \src "libresoc.v:21001.3-21013.6" + wire width 4 $1\shift_ir$next[3:0]$504 + attribute \src "libresoc.v:20984.13-20984.28" + wire width 4 $1\shift_ir[3:0] + attribute \src "libresoc.v:21014.3-21034.6" + wire width 4 $2\ir$next[3:0]$508 + attribute \src "libresoc.v:20991.17-20991.103" + wire $and$libresoc.v:20991$494_Y + attribute \src "libresoc.v:20992.18-20992.105" + wire $and$libresoc.v:20992$495_Y + attribute \src "libresoc.v:20993.17-20993.105" + wire $and$libresoc.v:20993$496_Y + attribute \src "libresoc.v:20994.17-20994.103" + wire $and$libresoc.v:20994$497_Y + attribute \src "libresoc.v:20995.17-20995.104" + wire $and$libresoc.v:20995$498_Y + attribute \src "libresoc.v:20996.17-20996.105" + wire $and$libresoc.v:20996$499_Y + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:366" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:368" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:367" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:368" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:366" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:367" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" + wire input 4 \TAP_bus__tdi + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:24" + wire input 1 \capture + attribute \src "libresoc.v:20953.7-20953.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:127" + wire width 4 output 9 \ir + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:127" + wire width 4 \ir$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:22" + wire input 5 \isir + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:28" + wire input 8 \posjtag_clk + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:28" + wire input 7 \posjtag_rst + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:25" + wire input 2 \shift + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:138" + wire width 4 \shift_ir + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:138" + wire width 4 \shift_ir$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:128" + wire output 6 \tdo + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:26" + wire input 3 \update + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:367" + cell $and $and$libresoc.v:20991$494 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \isir + connect \B \shift + connect \Y $and$libresoc.v:20991$494_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:368" + cell $and $and$libresoc.v:20992$495 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \isir + connect \B \update + connect \Y $and$libresoc.v:20992$495_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:366" + cell $and $and$libresoc.v:20993$496 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \isir + connect \B \capture + connect \Y $and$libresoc.v:20993$496_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:367" + cell $and $and$libresoc.v:20994$497 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \isir + connect \B \shift + connect \Y $and$libresoc.v:20994$497_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:368" + cell $and $and$libresoc.v:20995$498 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \isir + connect \B \update + connect \Y $and$libresoc.v:20995$498_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:366" + cell $and $and$libresoc.v:20996$499 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \isir + connect \B \capture + connect \Y $and$libresoc.v:20996$499_Y + end + attribute \src "libresoc.v:20953.7-20953.20" + process $proc$libresoc.v:20953$509 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:20972.13-20972.22" + process $proc$libresoc.v:20972$510 + assign { } { } + assign $1\ir[3:0] 4'0001 + sync always + sync init + update \ir $1\ir[3:0] + end + attribute \src "libresoc.v:20984.13-20984.28" + process $proc$libresoc.v:20984$511 + assign { } { } + assign $1\shift_ir[3:0] 4'0000 + sync always + sync init + update \shift_ir $1\shift_ir[3:0] + end + attribute \src "libresoc.v:20997.3-20998.21" + process $proc$libresoc.v:20997$500 + assign { } { } + assign $0\ir[3:0] \ir$next + sync posedge \posjtag_clk + update \ir $0\ir[3:0] + end + attribute \src "libresoc.v:20999.3-21000.33" + process $proc$libresoc.v:20999$501 + assign { } { } + assign $0\shift_ir[3:0] \shift_ir$next + sync posedge \posjtag_clk + update \shift_ir $0\shift_ir[3:0] + end + attribute \src "libresoc.v:21001.3-21013.6" + process $proc$libresoc.v:21001$502 + assign { } { } + assign { } { } + assign $0\shift_ir$next[3:0]$503 $1\shift_ir$next[3:0]$504 + attribute \src "libresoc.v:21002.5-21002.29" + switch \initial + attribute \src "libresoc.v:21002.9-21002.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:141" + switch { \$5 \$3 \$1 } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign { } { } + assign $1\shift_ir$next[3:0]$504 \ir + attribute \src "libresoc.v:0.0-0.0" + case 3'-1- + assign { } { } + assign $1\shift_ir$next[3:0]$504 { \TAP_bus__tdi \shift_ir [3:1] } + case + assign $1\shift_ir$next[3:0]$504 \shift_ir + end + sync always + update \shift_ir$next $0\shift_ir$next[3:0]$503 + end + attribute \src "libresoc.v:21014.3-21034.6" + process $proc$libresoc.v:21014$505 + assign { } { } + assign { } { } + assign { } { } + assign $0\ir$next[3:0]$506 $2\ir$next[3:0]$508 + attribute \src "libresoc.v:21015.5-21015.29" + switch \initial + attribute \src "libresoc.v:21015.9-21015.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:141" + switch { \$11 \$9 \$7 } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign $1\ir$next[3:0]$507 \ir + attribute \src "libresoc.v:0.0-0.0" + case 3'-1- + assign $1\ir$next[3:0]$507 \ir + attribute \src "libresoc.v:0.0-0.0" + case 3'1-- + assign { } { } + assign $1\ir$next[3:0]$507 \shift_ir + case + assign $1\ir$next[3:0]$507 \ir + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \posjtag_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ir$next[3:0]$508 4'0001 + case + assign $2\ir$next[3:0]$508 $1\ir$next[3:0]$507 + end + sync always + update \ir$next $0\ir$next[3:0]$506 + end + connect \$9 $and$libresoc.v:20991$494_Y + connect \$11 $and$libresoc.v:20992$495_Y + connect \$1 $and$libresoc.v:20993$496_Y + connect \$3 $and$libresoc.v:20994$497_Y + connect \$5 $and$libresoc.v:20995$498_Y + connect \$7 $and$libresoc.v:20996$499_Y + connect \tdo \ir [0] +end +attribute \src "libresoc.v:21040.1-21098.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.adr_l" +attribute \generator "nMigen" +module \adr_l + attribute \src "libresoc.v:21041.7-21041.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:21086.3-21094.6" + wire $0\q_int$next[0:0]$522 + attribute \src "libresoc.v:21084.3-21085.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:21086.3-21094.6" + wire $1\q_int$next[0:0]$523 + attribute \src "libresoc.v:21065.7-21065.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:21076.17-21076.96" + wire $and$libresoc.v:21076$512_Y + attribute \src "libresoc.v:21081.17-21081.96" + wire $and$libresoc.v:21081$517_Y + attribute \src "libresoc.v:21078.18-21078.93" + wire $not$libresoc.v:21078$514_Y + attribute \src "libresoc.v:21080.17-21080.92" + wire $not$libresoc.v:21080$516_Y + attribute \src "libresoc.v:21083.17-21083.92" + wire $not$libresoc.v:21083$519_Y + attribute \src "libresoc.v:21077.18-21077.98" + wire $or$libresoc.v:21077$513_Y + attribute \src "libresoc.v:21079.18-21079.99" + wire $or$libresoc.v:21079$515_Y + attribute \src "libresoc.v:21082.17-21082.97" + wire $or$libresoc.v:21082$518_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 1 \coresync_rst + attribute \src "libresoc.v:21041.7-21041.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire output 4 \q_adr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" + wire \qlq_adr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \qn_adr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire input 3 \r_adr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire input 2 \s_adr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:21076$512 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:21076$512_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:21081$517 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:21081$517_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:21078$514 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_adr + connect \Y $not$libresoc.v:21078$514_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:21080$516 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_adr + connect \Y $not$libresoc.v:21080$516_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:21083$519 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_adr + connect \Y $not$libresoc.v:21083$519_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:21077$513 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_adr + connect \Y $or$libresoc.v:21077$513_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:21079$515 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_adr + connect \B \q_int + connect \Y $or$libresoc.v:21079$515_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:21082$518 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_adr + connect \Y $or$libresoc.v:21082$518_Y + end + attribute \src "libresoc.v:21041.7-21041.20" + process $proc$libresoc.v:21041$524 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:21065.7-21065.19" + process $proc$libresoc.v:21065$525 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:21084.3-21085.27" + process $proc$libresoc.v:21084$520 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:21086.3-21094.6" + process $proc$libresoc.v:21086$521 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$522 $1\q_int$next[0:0]$523 + attribute \src "libresoc.v:21087.5-21087.29" + switch \initial + attribute \src "libresoc.v:21087.9-21087.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$523 1'0 + case + assign $1\q_int$next[0:0]$523 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$522 + end + connect \$9 $and$libresoc.v:21076$512_Y + connect \$11 $or$libresoc.v:21077$513_Y + connect \$13 $not$libresoc.v:21078$514_Y + connect \$15 $or$libresoc.v:21079$515_Y + connect \$1 $not$libresoc.v:21080$516_Y + connect \$3 $and$libresoc.v:21081$517_Y + connect \$5 $or$libresoc.v:21082$518_Y + connect \$7 $not$libresoc.v:21083$519_Y + connect \qlq_adr \$15 + connect \qn_adr \$13 + connect \q_adr \$11 +end +attribute \src "libresoc.v:21102.1-21160.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem.adrok_l" +attribute \generator "nMigen" +module \adrok_l + attribute \src "libresoc.v:21103.7-21103.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:21148.3-21156.6" + wire $0\q_int$next[0:0]$536 + attribute \src "libresoc.v:21146.3-21147.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:21148.3-21156.6" + wire $1\q_int$next[0:0]$537 + attribute \src "libresoc.v:21127.7-21127.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:21138.17-21138.96" + wire $and$libresoc.v:21138$526_Y + attribute \src "libresoc.v:21143.17-21143.96" + wire $and$libresoc.v:21143$531_Y + attribute \src "libresoc.v:21140.18-21140.100" + wire $not$libresoc.v:21140$528_Y + attribute \src "libresoc.v:21142.17-21142.99" + wire $not$libresoc.v:21142$530_Y + attribute \src "libresoc.v:21145.17-21145.99" + wire $not$libresoc.v:21145$533_Y + attribute \src "libresoc.v:21139.18-21139.105" + wire $or$libresoc.v:21139$527_Y + attribute \src "libresoc.v:21141.18-21141.106" + wire $or$libresoc.v:21141$529_Y + attribute \src "libresoc.v:21144.17-21144.104" + wire $or$libresoc.v:21144$532_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 6 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 1 \coresync_rst + attribute \src "libresoc.v:21103.7-21103.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire output 5 \q_addr_acked + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" + wire \qlq_addr_acked + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire output 4 \qn_addr_acked + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire input 3 \r_addr_acked + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire input 2 \s_addr_acked + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:21138$526 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:21138$526_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:21143$531 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:21143$531_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:21140$528 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_addr_acked + connect \Y $not$libresoc.v:21140$528_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:21142$530 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_addr_acked + connect \Y $not$libresoc.v:21142$530_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:21145$533 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_addr_acked + connect \Y $not$libresoc.v:21145$533_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:21139$527 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_addr_acked + connect \Y $or$libresoc.v:21139$527_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:21141$529 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_addr_acked + connect \B \q_int + connect \Y $or$libresoc.v:21141$529_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:21144$532 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_addr_acked + connect \Y $or$libresoc.v:21144$532_Y + end + attribute \src "libresoc.v:21103.7-21103.20" + process $proc$libresoc.v:21103$538 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:21127.7-21127.19" + process $proc$libresoc.v:21127$539 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:21146.3-21147.27" + process $proc$libresoc.v:21146$534 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:21148.3-21156.6" + process $proc$libresoc.v:21148$535 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$536 $1\q_int$next[0:0]$537 + attribute \src "libresoc.v:21149.5-21149.29" + switch \initial + attribute \src "libresoc.v:21149.9-21149.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$537 1'0 + case + assign $1\q_int$next[0:0]$537 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$536 + end + connect \$9 $and$libresoc.v:21138$526_Y + connect \$11 $or$libresoc.v:21139$527_Y + connect \$13 $not$libresoc.v:21140$528_Y + connect \$15 $or$libresoc.v:21141$529_Y + connect \$1 $not$libresoc.v:21142$530_Y + connect \$3 $and$libresoc.v:21143$531_Y + connect \$5 $or$libresoc.v:21144$532_Y + connect \$7 $not$libresoc.v:21145$533_Y + connect \qlq_addr_acked \$15 + connect \qn_addr_acked \$13 + connect \q_addr_acked \$11 +end +attribute \src "libresoc.v:21164.1-22491.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0" +attribute \generator "nMigen" +module \alu0 + attribute \src "libresoc.v:22002.3-22003.25" + wire $0\all_rd_dly[0:0] + attribute \src "libresoc.v:22192.3-22230.6" + wire width 4 $0\alu_alu0_alu_op__data_len$next[3:0]$686 + attribute \src "libresoc.v:21974.3-21975.67" + wire width 4 $0\alu_alu0_alu_op__data_len[3:0] + attribute \src "libresoc.v:22192.3-22230.6" + wire width 13 $0\alu_alu0_alu_op__fn_unit$next[12:0]$687 + attribute \src "libresoc.v:21944.3-21945.65" + wire width 13 $0\alu_alu0_alu_op__fn_unit[12:0] + attribute \src "libresoc.v:22192.3-22230.6" + wire width 64 $0\alu_alu0_alu_op__imm_data__data$next[63:0]$688 + attribute \src "libresoc.v:21946.3-21947.79" + wire width 64 $0\alu_alu0_alu_op__imm_data__data[63:0] + attribute \src "libresoc.v:22192.3-22230.6" + wire $0\alu_alu0_alu_op__imm_data__ok$next[0:0]$689 + attribute \src "libresoc.v:21948.3-21949.75" + wire $0\alu_alu0_alu_op__imm_data__ok[0:0] + attribute \src "libresoc.v:22192.3-22230.6" + wire width 2 $0\alu_alu0_alu_op__input_carry$next[1:0]$690 + attribute \src "libresoc.v:21966.3-21967.73" + wire width 2 $0\alu_alu0_alu_op__input_carry[1:0] + attribute \src "libresoc.v:22192.3-22230.6" + wire width 32 $0\alu_alu0_alu_op__insn$next[31:0]$691 + attribute \src "libresoc.v:21976.3-21977.59" + wire width 32 $0\alu_alu0_alu_op__insn[31:0] + attribute \src "libresoc.v:22192.3-22230.6" + wire width 7 $0\alu_alu0_alu_op__insn_type$next[6:0]$692 + attribute \src "libresoc.v:21942.3-21943.69" + wire width 7 $0\alu_alu0_alu_op__insn_type[6:0] + attribute \src "libresoc.v:22192.3-22230.6" + wire $0\alu_alu0_alu_op__invert_in$next[0:0]$693 + attribute \src "libresoc.v:21958.3-21959.69" + wire $0\alu_alu0_alu_op__invert_in[0:0] + attribute \src "libresoc.v:22192.3-22230.6" + wire $0\alu_alu0_alu_op__invert_out$next[0:0]$694 + attribute \src "libresoc.v:21962.3-21963.71" + wire $0\alu_alu0_alu_op__invert_out[0:0] + attribute \src "libresoc.v:22192.3-22230.6" + wire $0\alu_alu0_alu_op__is_32bit$next[0:0]$695 + attribute \src "libresoc.v:21970.3-21971.67" + wire $0\alu_alu0_alu_op__is_32bit[0:0] + attribute \src "libresoc.v:22192.3-22230.6" + wire $0\alu_alu0_alu_op__is_signed$next[0:0]$696 + attribute \src "libresoc.v:21972.3-21973.69" + wire $0\alu_alu0_alu_op__is_signed[0:0] + attribute \src "libresoc.v:22192.3-22230.6" + wire $0\alu_alu0_alu_op__oe__oe$next[0:0]$697 + attribute \src "libresoc.v:21954.3-21955.63" + wire $0\alu_alu0_alu_op__oe__oe[0:0] + attribute \src "libresoc.v:22192.3-22230.6" + wire $0\alu_alu0_alu_op__oe__ok$next[0:0]$698 + attribute \src "libresoc.v:21956.3-21957.63" + wire $0\alu_alu0_alu_op__oe__ok[0:0] + attribute \src "libresoc.v:22192.3-22230.6" + wire $0\alu_alu0_alu_op__output_carry$next[0:0]$699 + attribute \src "libresoc.v:21968.3-21969.75" + wire $0\alu_alu0_alu_op__output_carry[0:0] + attribute \src "libresoc.v:22192.3-22230.6" + wire $0\alu_alu0_alu_op__rc__ok$next[0:0]$700 + attribute \src "libresoc.v:21952.3-21953.63" + wire $0\alu_alu0_alu_op__rc__ok[0:0] + attribute \src "libresoc.v:22192.3-22230.6" + wire $0\alu_alu0_alu_op__rc__rc$next[0:0]$701 + attribute \src "libresoc.v:21950.3-21951.63" + wire $0\alu_alu0_alu_op__rc__rc[0:0] + attribute \src "libresoc.v:22192.3-22230.6" + wire $0\alu_alu0_alu_op__write_cr0$next[0:0]$702 + attribute \src "libresoc.v:21964.3-21965.69" + wire $0\alu_alu0_alu_op__write_cr0[0:0] + attribute \src "libresoc.v:22192.3-22230.6" + wire $0\alu_alu0_alu_op__zero_a$next[0:0]$703 + attribute \src "libresoc.v:21960.3-21961.63" + wire $0\alu_alu0_alu_op__zero_a[0:0] + attribute \src "libresoc.v:22000.3-22001.40" + wire $0\alu_done_dly[0:0] + attribute \src "libresoc.v:22390.3-22398.6" + wire $0\alu_l_r_alu$next[0:0]$784 + attribute \src "libresoc.v:21910.3-21911.39" + wire $0\alu_l_r_alu[0:0] + attribute \src "libresoc.v:22381.3-22389.6" + wire $0\alui_l_r_alui$next[0:0]$781 + attribute \src "libresoc.v:21912.3-21913.43" + wire $0\alui_l_r_alui[0:0] + attribute \src "libresoc.v:22231.3-22252.6" + wire width 64 $0\data_r0__o$next[63:0]$729 + attribute \src "libresoc.v:21938.3-21939.37" + wire width 64 $0\data_r0__o[63:0] + attribute \src "libresoc.v:22231.3-22252.6" + wire $0\data_r0__o_ok$next[0:0]$730 + attribute \src "libresoc.v:21940.3-21941.43" + wire $0\data_r0__o_ok[0:0] + attribute \src "libresoc.v:22253.3-22274.6" + wire width 4 $0\data_r1__cr_a$next[3:0]$737 + attribute \src "libresoc.v:21934.3-21935.43" + wire width 4 $0\data_r1__cr_a[3:0] + attribute \src "libresoc.v:22253.3-22274.6" + wire $0\data_r1__cr_a_ok$next[0:0]$738 + attribute \src "libresoc.v:21936.3-21937.49" + wire $0\data_r1__cr_a_ok[0:0] + attribute \src "libresoc.v:22275.3-22296.6" + wire width 2 $0\data_r2__xer_ca$next[1:0]$745 + attribute \src "libresoc.v:21930.3-21931.47" + wire width 2 $0\data_r2__xer_ca[1:0] + attribute \src "libresoc.v:22275.3-22296.6" + wire $0\data_r2__xer_ca_ok$next[0:0]$746 + attribute \src "libresoc.v:21932.3-21933.53" + wire $0\data_r2__xer_ca_ok[0:0] + attribute \src "libresoc.v:22297.3-22318.6" + wire width 2 $0\data_r3__xer_ov$next[1:0]$753 + attribute \src "libresoc.v:21926.3-21927.47" + wire width 2 $0\data_r3__xer_ov[1:0] + attribute \src "libresoc.v:22297.3-22318.6" + wire $0\data_r3__xer_ov_ok$next[0:0]$754 + attribute \src "libresoc.v:21928.3-21929.53" + wire $0\data_r3__xer_ov_ok[0:0] + attribute \src "libresoc.v:22319.3-22340.6" + wire $0\data_r4__xer_so$next[0:0]$761 + attribute \src "libresoc.v:21922.3-21923.47" + wire $0\data_r4__xer_so[0:0] + attribute \src "libresoc.v:22319.3-22340.6" + wire $0\data_r4__xer_so_ok$next[0:0]$762 + attribute \src "libresoc.v:21924.3-21925.53" + wire $0\data_r4__xer_so_ok[0:0] + attribute \src "libresoc.v:22399.3-22408.6" + wire width 64 $0\dest1_o[63:0] + attribute \src "libresoc.v:22409.3-22418.6" + wire width 4 $0\dest2_o[3:0] + attribute \src "libresoc.v:22419.3-22428.6" + wire width 2 $0\dest3_o[1:0] + attribute \src "libresoc.v:22429.3-22438.6" + wire width 2 $0\dest4_o[1:0] + attribute \src "libresoc.v:22439.3-22448.6" + wire $0\dest5_o[0:0] + attribute \src "libresoc.v:21165.7-21165.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:22147.3-22155.6" + wire $0\opc_l_r_opc$next[0:0]$671 + attribute \src "libresoc.v:21986.3-21987.39" + wire $0\opc_l_r_opc[0:0] + attribute \src "libresoc.v:22138.3-22146.6" + wire $0\opc_l_s_opc$next[0:0]$668 + attribute \src "libresoc.v:21988.3-21989.39" + wire $0\opc_l_s_opc[0:0] + attribute \src "libresoc.v:22449.3-22457.6" + wire width 5 $0\prev_wr_go$next[4:0]$792 + attribute \src "libresoc.v:21998.3-21999.37" + wire width 5 $0\prev_wr_go[4:0] + attribute \src "libresoc.v:22092.3-22101.6" + wire $0\req_done[0:0] + attribute \src "libresoc.v:22183.3-22191.6" + wire width 5 $0\req_l_r_req$next[4:0]$683 + attribute \src "libresoc.v:21978.3-21979.39" + wire width 5 $0\req_l_r_req[4:0] + attribute \src "libresoc.v:22174.3-22182.6" + wire width 5 $0\req_l_s_req$next[4:0]$680 + attribute \src "libresoc.v:21980.3-21981.39" + wire width 5 $0\req_l_s_req[4:0] + attribute \src "libresoc.v:22111.3-22119.6" + wire $0\rok_l_r_rdok$next[0:0]$659 + attribute \src "libresoc.v:21994.3-21995.41" + wire $0\rok_l_r_rdok[0:0] + attribute \src "libresoc.v:22102.3-22110.6" + wire $0\rok_l_s_rdok$next[0:0]$656 + attribute \src "libresoc.v:21996.3-21997.41" + wire $0\rok_l_s_rdok[0:0] + attribute \src "libresoc.v:22129.3-22137.6" + wire $0\rst_l_r_rst$next[0:0]$665 + attribute \src "libresoc.v:21990.3-21991.39" + wire $0\rst_l_r_rst[0:0] + attribute \src "libresoc.v:22120.3-22128.6" + wire $0\rst_l_s_rst$next[0:0]$662 + attribute \src "libresoc.v:21992.3-21993.39" + wire $0\rst_l_s_rst[0:0] + attribute \src "libresoc.v:22165.3-22173.6" + wire width 4 $0\src_l_r_src$next[3:0]$677 + attribute \src "libresoc.v:21982.3-21983.39" + wire width 4 $0\src_l_r_src[3:0] + attribute \src "libresoc.v:22156.3-22164.6" + wire width 4 $0\src_l_s_src$next[3:0]$674 + attribute \src "libresoc.v:21984.3-21985.39" + wire width 4 $0\src_l_s_src[3:0] + attribute \src "libresoc.v:22341.3-22350.6" + wire width 64 $0\src_r0$next[63:0]$769 + attribute \src "libresoc.v:21920.3-21921.29" + wire width 64 $0\src_r0[63:0] + attribute \src "libresoc.v:22351.3-22360.6" + wire width 64 $0\src_r1$next[63:0]$772 + attribute \src "libresoc.v:21918.3-21919.29" + wire width 64 $0\src_r1[63:0] + attribute \src "libresoc.v:22361.3-22370.6" + wire $0\src_r2$next[0:0]$775 + attribute \src "libresoc.v:21916.3-21917.29" + wire $0\src_r2[0:0] + attribute \src "libresoc.v:22371.3-22380.6" + wire width 2 $0\src_r3$next[1:0]$778 + attribute \src "libresoc.v:21914.3-21915.29" + wire width 2 $0\src_r3[1:0] + attribute \src "libresoc.v:21303.7-21303.24" + wire $1\all_rd_dly[0:0] + attribute \src "libresoc.v:22192.3-22230.6" + wire width 4 $1\alu_alu0_alu_op__data_len$next[3:0]$704 + attribute \src "libresoc.v:21311.13-21311.45" + wire width 4 $1\alu_alu0_alu_op__data_len[3:0] + attribute \src "libresoc.v:22192.3-22230.6" + wire width 13 $1\alu_alu0_alu_op__fn_unit$next[12:0]$705 + attribute \src "libresoc.v:21329.14-21329.49" + wire width 13 $1\alu_alu0_alu_op__fn_unit[12:0] + attribute \src "libresoc.v:22192.3-22230.6" + wire width 64 $1\alu_alu0_alu_op__imm_data__data$next[63:0]$706 + attribute \src "libresoc.v:21333.14-21333.68" + wire width 64 $1\alu_alu0_alu_op__imm_data__data[63:0] + attribute \src "libresoc.v:22192.3-22230.6" + wire $1\alu_alu0_alu_op__imm_data__ok$next[0:0]$707 + attribute \src "libresoc.v:21337.7-21337.43" + wire $1\alu_alu0_alu_op__imm_data__ok[0:0] + attribute \src "libresoc.v:22192.3-22230.6" + wire width 2 $1\alu_alu0_alu_op__input_carry$next[1:0]$708 + attribute \src "libresoc.v:21345.13-21345.48" + wire width 2 $1\alu_alu0_alu_op__input_carry[1:0] + attribute \src "libresoc.v:22192.3-22230.6" + wire width 32 $1\alu_alu0_alu_op__insn$next[31:0]$709 + attribute \src "libresoc.v:21349.14-21349.43" + wire width 32 $1\alu_alu0_alu_op__insn[31:0] + attribute \src "libresoc.v:22192.3-22230.6" + wire width 7 $1\alu_alu0_alu_op__insn_type$next[6:0]$710 + attribute \src "libresoc.v:21427.13-21427.47" + wire width 7 $1\alu_alu0_alu_op__insn_type[6:0] + attribute \src "libresoc.v:22192.3-22230.6" + wire $1\alu_alu0_alu_op__invert_in$next[0:0]$711 + attribute \src "libresoc.v:21431.7-21431.40" + wire $1\alu_alu0_alu_op__invert_in[0:0] + attribute \src "libresoc.v:22192.3-22230.6" + wire $1\alu_alu0_alu_op__invert_out$next[0:0]$712 + attribute \src "libresoc.v:21435.7-21435.41" + wire $1\alu_alu0_alu_op__invert_out[0:0] + attribute \src "libresoc.v:22192.3-22230.6" + wire $1\alu_alu0_alu_op__is_32bit$next[0:0]$713 + attribute \src "libresoc.v:21439.7-21439.39" + wire $1\alu_alu0_alu_op__is_32bit[0:0] + attribute \src "libresoc.v:22192.3-22230.6" + wire $1\alu_alu0_alu_op__is_signed$next[0:0]$714 + attribute \src "libresoc.v:21443.7-21443.40" + wire $1\alu_alu0_alu_op__is_signed[0:0] + attribute \src "libresoc.v:22192.3-22230.6" + wire $1\alu_alu0_alu_op__oe__oe$next[0:0]$715 + attribute \src "libresoc.v:21447.7-21447.37" + wire $1\alu_alu0_alu_op__oe__oe[0:0] + attribute \src "libresoc.v:22192.3-22230.6" + wire $1\alu_alu0_alu_op__oe__ok$next[0:0]$716 + attribute \src "libresoc.v:21451.7-21451.37" + wire $1\alu_alu0_alu_op__oe__ok[0:0] + attribute \src "libresoc.v:22192.3-22230.6" + wire $1\alu_alu0_alu_op__output_carry$next[0:0]$717 + attribute \src "libresoc.v:21455.7-21455.43" + wire $1\alu_alu0_alu_op__output_carry[0:0] + attribute \src "libresoc.v:22192.3-22230.6" + wire $1\alu_alu0_alu_op__rc__ok$next[0:0]$718 + attribute \src "libresoc.v:21459.7-21459.37" + wire $1\alu_alu0_alu_op__rc__ok[0:0] + attribute \src "libresoc.v:22192.3-22230.6" + wire $1\alu_alu0_alu_op__rc__rc$next[0:0]$719 + attribute \src "libresoc.v:21463.7-21463.37" + wire $1\alu_alu0_alu_op__rc__rc[0:0] + attribute \src "libresoc.v:22192.3-22230.6" + wire $1\alu_alu0_alu_op__write_cr0$next[0:0]$720 + attribute \src "libresoc.v:21467.7-21467.40" + wire $1\alu_alu0_alu_op__write_cr0[0:0] + attribute \src "libresoc.v:22192.3-22230.6" + wire $1\alu_alu0_alu_op__zero_a$next[0:0]$721 + attribute \src "libresoc.v:21471.7-21471.37" + wire $1\alu_alu0_alu_op__zero_a[0:0] + attribute \src "libresoc.v:21503.7-21503.26" + wire $1\alu_done_dly[0:0] + attribute \src "libresoc.v:22390.3-22398.6" + wire $1\alu_l_r_alu$next[0:0]$785 + attribute \src "libresoc.v:21511.7-21511.25" + wire $1\alu_l_r_alu[0:0] + attribute \src "libresoc.v:22381.3-22389.6" + wire $1\alui_l_r_alui$next[0:0]$782 + attribute \src "libresoc.v:21523.7-21523.27" + wire $1\alui_l_r_alui[0:0] + attribute \src "libresoc.v:22231.3-22252.6" + wire width 64 $1\data_r0__o$next[63:0]$731 + attribute \src "libresoc.v:21557.14-21557.47" + wire width 64 $1\data_r0__o[63:0] + attribute \src "libresoc.v:22231.3-22252.6" + wire $1\data_r0__o_ok$next[0:0]$732 + attribute \src "libresoc.v:21561.7-21561.27" + wire $1\data_r0__o_ok[0:0] + attribute \src "libresoc.v:22253.3-22274.6" + wire width 4 $1\data_r1__cr_a$next[3:0]$739 + attribute \src "libresoc.v:21565.13-21565.33" + wire width 4 $1\data_r1__cr_a[3:0] + attribute \src "libresoc.v:22253.3-22274.6" + wire $1\data_r1__cr_a_ok$next[0:0]$740 + attribute \src "libresoc.v:21569.7-21569.30" + wire $1\data_r1__cr_a_ok[0:0] + attribute \src "libresoc.v:22275.3-22296.6" + wire width 2 $1\data_r2__xer_ca$next[1:0]$747 + attribute \src "libresoc.v:21573.13-21573.35" + wire width 2 $1\data_r2__xer_ca[1:0] + attribute \src "libresoc.v:22275.3-22296.6" + wire $1\data_r2__xer_ca_ok$next[0:0]$748 + attribute \src "libresoc.v:21577.7-21577.32" + wire $1\data_r2__xer_ca_ok[0:0] + attribute \src "libresoc.v:22297.3-22318.6" + wire width 2 $1\data_r3__xer_ov$next[1:0]$755 + attribute \src "libresoc.v:21581.13-21581.35" + wire width 2 $1\data_r3__xer_ov[1:0] + attribute \src "libresoc.v:22297.3-22318.6" + wire $1\data_r3__xer_ov_ok$next[0:0]$756 + attribute \src "libresoc.v:21585.7-21585.32" + wire $1\data_r3__xer_ov_ok[0:0] + attribute \src "libresoc.v:22319.3-22340.6" + wire $1\data_r4__xer_so$next[0:0]$763 + attribute \src "libresoc.v:21589.7-21589.29" + wire $1\data_r4__xer_so[0:0] + attribute \src "libresoc.v:22319.3-22340.6" + wire $1\data_r4__xer_so_ok$next[0:0]$764 + attribute \src "libresoc.v:21593.7-21593.32" + wire $1\data_r4__xer_so_ok[0:0] + attribute \src "libresoc.v:22399.3-22408.6" + wire width 64 $1\dest1_o[63:0] + attribute \src "libresoc.v:22409.3-22418.6" + wire width 4 $1\dest2_o[3:0] + attribute \src "libresoc.v:22419.3-22428.6" + wire width 2 $1\dest3_o[1:0] + attribute \src "libresoc.v:22429.3-22438.6" + wire width 2 $1\dest4_o[1:0] + attribute \src "libresoc.v:22439.3-22448.6" + wire $1\dest5_o[0:0] + attribute \src "libresoc.v:22147.3-22155.6" + wire $1\opc_l_r_opc$next[0:0]$672 + attribute \src "libresoc.v:21616.7-21616.25" + wire $1\opc_l_r_opc[0:0] + attribute \src "libresoc.v:22138.3-22146.6" + wire $1\opc_l_s_opc$next[0:0]$669 + attribute \src "libresoc.v:21620.7-21620.25" + wire $1\opc_l_s_opc[0:0] + attribute \src "libresoc.v:22449.3-22457.6" + wire width 5 $1\prev_wr_go$next[4:0]$793 + attribute \src "libresoc.v:21752.13-21752.31" + wire width 5 $1\prev_wr_go[4:0] + attribute \src "libresoc.v:22092.3-22101.6" + wire $1\req_done[0:0] + attribute \src "libresoc.v:22183.3-22191.6" + wire width 5 $1\req_l_r_req$next[4:0]$684 + attribute \src "libresoc.v:21760.13-21760.32" + wire width 5 $1\req_l_r_req[4:0] + attribute \src "libresoc.v:22174.3-22182.6" + wire width 5 $1\req_l_s_req$next[4:0]$681 + attribute \src "libresoc.v:21764.13-21764.32" + wire width 5 $1\req_l_s_req[4:0] + attribute \src "libresoc.v:22111.3-22119.6" + wire $1\rok_l_r_rdok$next[0:0]$660 + attribute \src "libresoc.v:21776.7-21776.26" + wire $1\rok_l_r_rdok[0:0] + attribute \src "libresoc.v:22102.3-22110.6" + wire $1\rok_l_s_rdok$next[0:0]$657 + attribute \src "libresoc.v:21780.7-21780.26" + wire $1\rok_l_s_rdok[0:0] + attribute \src "libresoc.v:22129.3-22137.6" + wire $1\rst_l_r_rst$next[0:0]$666 + attribute \src "libresoc.v:21784.7-21784.25" + wire $1\rst_l_r_rst[0:0] + attribute \src "libresoc.v:22120.3-22128.6" + wire $1\rst_l_s_rst$next[0:0]$663 + attribute \src "libresoc.v:21788.7-21788.25" + wire $1\rst_l_s_rst[0:0] + attribute \src "libresoc.v:22165.3-22173.6" + wire width 4 $1\src_l_r_src$next[3:0]$678 + attribute \src "libresoc.v:21804.13-21804.31" + wire width 4 $1\src_l_r_src[3:0] + attribute \src "libresoc.v:22156.3-22164.6" + wire width 4 $1\src_l_s_src$next[3:0]$675 + attribute \src "libresoc.v:21808.13-21808.31" + wire width 4 $1\src_l_s_src[3:0] + attribute \src "libresoc.v:22341.3-22350.6" + wire width 64 $1\src_r0$next[63:0]$770 + attribute \src "libresoc.v:21816.14-21816.43" + wire width 64 $1\src_r0[63:0] + attribute \src "libresoc.v:22351.3-22360.6" + wire width 64 $1\src_r1$next[63:0]$773 + attribute \src "libresoc.v:21820.14-21820.43" + wire width 64 $1\src_r1[63:0] + attribute \src "libresoc.v:22361.3-22370.6" + wire $1\src_r2$next[0:0]$776 + attribute \src "libresoc.v:21824.7-21824.20" + wire $1\src_r2[0:0] + attribute \src "libresoc.v:22371.3-22380.6" + wire width 2 $1\src_r3$next[1:0]$779 + attribute \src "libresoc.v:21828.13-21828.26" + wire width 2 $1\src_r3[1:0] + attribute \src "libresoc.v:22192.3-22230.6" + wire width 64 $2\alu_alu0_alu_op__imm_data__data$next[63:0]$722 + attribute \src "libresoc.v:22192.3-22230.6" + wire $2\alu_alu0_alu_op__imm_data__ok$next[0:0]$723 + attribute \src "libresoc.v:22192.3-22230.6" + wire $2\alu_alu0_alu_op__oe__oe$next[0:0]$724 + attribute \src "libresoc.v:22192.3-22230.6" + wire $2\alu_alu0_alu_op__oe__ok$next[0:0]$725 + attribute \src "libresoc.v:22192.3-22230.6" + wire $2\alu_alu0_alu_op__rc__ok$next[0:0]$726 + attribute \src "libresoc.v:22192.3-22230.6" + wire $2\alu_alu0_alu_op__rc__rc$next[0:0]$727 + attribute \src "libresoc.v:22231.3-22252.6" + wire width 64 $2\data_r0__o$next[63:0]$733 + attribute \src "libresoc.v:22231.3-22252.6" + wire $2\data_r0__o_ok$next[0:0]$734 + attribute \src "libresoc.v:22253.3-22274.6" + wire width 4 $2\data_r1__cr_a$next[3:0]$741 + attribute \src "libresoc.v:22253.3-22274.6" + wire $2\data_r1__cr_a_ok$next[0:0]$742 + attribute \src "libresoc.v:22275.3-22296.6" + wire width 2 $2\data_r2__xer_ca$next[1:0]$749 + attribute \src "libresoc.v:22275.3-22296.6" + wire $2\data_r2__xer_ca_ok$next[0:0]$750 + attribute \src "libresoc.v:22297.3-22318.6" + wire width 2 $2\data_r3__xer_ov$next[1:0]$757 + attribute \src "libresoc.v:22297.3-22318.6" + wire $2\data_r3__xer_ov_ok$next[0:0]$758 + attribute \src "libresoc.v:22319.3-22340.6" + wire $2\data_r4__xer_so$next[0:0]$765 + attribute \src "libresoc.v:22319.3-22340.6" + wire $2\data_r4__xer_so_ok$next[0:0]$766 + attribute \src "libresoc.v:22231.3-22252.6" + wire $3\data_r0__o_ok$next[0:0]$735 + attribute \src "libresoc.v:22253.3-22274.6" + wire $3\data_r1__cr_a_ok$next[0:0]$743 + attribute \src "libresoc.v:22275.3-22296.6" + wire $3\data_r2__xer_ca_ok$next[0:0]$751 + attribute \src "libresoc.v:22297.3-22318.6" + wire $3\data_r3__xer_ov_ok$next[0:0]$759 + attribute \src "libresoc.v:22319.3-22340.6" + wire $3\data_r4__xer_so_ok$next[0:0]$767 + attribute \src "libresoc.v:21844.18-21844.134" + wire $and$libresoc.v:21844$541_Y + attribute \src "libresoc.v:21845.19-21845.133" + wire $and$libresoc.v:21845$542_Y + attribute \src "libresoc.v:21846.19-21846.161" + wire width 4 $and$libresoc.v:21846$543_Y + attribute \src "libresoc.v:21849.19-21849.134" + wire width 4 $and$libresoc.v:21849$546_Y + attribute \src "libresoc.v:21851.19-21851.115" + wire width 4 $and$libresoc.v:21851$548_Y + attribute \src "libresoc.v:21852.19-21852.125" + wire $and$libresoc.v:21852$549_Y + attribute \src "libresoc.v:21853.19-21853.125" + wire $and$libresoc.v:21853$550_Y + attribute \src "libresoc.v:21854.18-21854.110" + wire $and$libresoc.v:21854$551_Y + attribute \src "libresoc.v:21855.19-21855.125" + wire $and$libresoc.v:21855$552_Y + attribute \src "libresoc.v:21856.19-21856.125" + wire $and$libresoc.v:21856$553_Y + attribute \src "libresoc.v:21857.19-21857.125" + wire $and$libresoc.v:21857$554_Y + attribute \src "libresoc.v:21858.19-21858.157" + wire width 5 $and$libresoc.v:21858$555_Y + attribute \src "libresoc.v:21859.19-21859.121" + wire width 5 $and$libresoc.v:21859$556_Y + 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"/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_alu0_alu_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_alu0_alu_op__rc__rc$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_alu0_alu_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_alu0_alu_op__write_cr0$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_alu0_alu_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_alu0_alu_op__zero_a$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \alu_alu0_cr_a + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire \alu_alu0_n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire \alu_alu0_n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \alu_alu0_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" + wire \alu_alu0_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" + wire \alu_alu0_p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \alu_alu0_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \alu_alu0_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \alu_alu0_xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 \alu_alu0_xer_ca$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \alu_alu0_xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \alu_alu0_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \alu_alu0_xer_so$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:196" + wire \alu_done + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" + wire \alu_done_dly + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" + wire \alu_done_dly$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" + wire \alu_done_rise + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire \alu_l_q_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \alu_l_r_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \alu_l_r_alu$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire \alu_l_s_alu + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:197" + wire \alu_pulse + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198" + wire width 5 \alu_pulsem + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire \alui_l_q_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \alui_l_r_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \alui_l_r_alui$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire \alui_l_s_alui + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 41 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 33 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" + wire output 21 \cu_busy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:108" + wire \cu_done_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:104" + wire \cu_go_die_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" + wire input 20 \cu_issue_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 4 input 24 \cu_rd__go_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 4 output 23 \cu_rd__rel_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" + wire width 4 input 22 \cu_rdmaskn_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:102" + wire \cu_shadown_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 5 input 31 \cu_wr__go_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 5 output 30 \cu_wr__rel_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:97" + wire width 5 \cu_wrmask_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 64 \data_r0__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 64 \data_r0__o$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r0__o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r0__o_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 4 \data_r1__cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 4 \data_r1__cr_a$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r1__cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r1__cr_a_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 2 \data_r2__xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 2 \data_r2__xer_ca$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r2__xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r2__xer_ca_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 2 \data_r3__xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 2 \data_r3__xer_ov$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r3__xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r3__xer_ov_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r4__xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r4__xer_so$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r4__xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r4__xer_so_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 32 \dest1_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 4 output 34 \dest2_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 2 output 36 \dest3_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 2 output 38 \dest4_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire output 40 \dest5_o + attribute \src "libresoc.v:21165.7-21165.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 29 \o_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire \opc_l_q_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \opc_l_r_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \opc_l_r_opc$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire \opc_l_s_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire \opc_l_s_opc$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 18 \oper_i_alu_alu0__data_len + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 input 3 \oper_i_alu_alu0__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 4 \oper_i_alu_alu0__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 5 \oper_i_alu_alu0__imm_data__ok + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 14 \oper_i_alu_alu0__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 19 \oper_i_alu_alu0__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute 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\oper_i_alu_alu0__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 16 \oper_i_alu_alu0__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 17 \oper_i_alu_alu0__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \oper_i_alu_alu0__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \oper_i_alu_alu0__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 15 \oper_i_alu_alu0__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 7 \oper_i_alu_alu0__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 6 \oper_i_alu_alu0__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \oper_i_alu_alu0__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 11 \oper_i_alu_alu0__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" + wire width 5 \prev_wr_go + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" + wire width 5 \prev_wr_go$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212" + wire \req_done + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire width 5 \req_l_q_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 5 \req_l_r_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 5 \req_l_r_req$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire width 5 \req_l_s_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire width 5 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\rst_l_r_rst$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire \rst_l_s_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire \rst_l_s_rst$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227" + wire \rst_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 25 \src1_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 26 \src2_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire input 27 \src3_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 2 input 28 \src4_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire width 4 \src_l_q_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 4 \src_l_r_src + attribute \src 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connect \A \cu_rdmaskn_i + connect \Y $not$libresoc.v:21850$547_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $not $not$libresoc.v:21865$562 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \all_rd_dly + connect \Y $not$libresoc.v:21865$562_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $not $not$libresoc.v:21867$564 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_done_dly + connect \Y $not$libresoc.v:21867$564_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $not $not$libresoc.v:21870$567 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \cu_wrmask_o + connect \Y $not$libresoc.v:21870$567_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $not $not$libresoc.v:21873$570 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$24 + connect \Y $not$libresoc.v:21873$570_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + cell $not $not$libresoc.v:21879$576 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_alu0_n_ready_i + connect \Y $not$libresoc.v:21879$576_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $not $not$libresoc.v:21894$591 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \cu_rd__rel_o + connect \Y $not$libresoc.v:21894$591_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $or $or$libresoc.v:21877$574 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$33 + connect \B \$35 + connect \Y $or$libresoc.v:21877$574_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" + cell $or $or$libresoc.v:21888$585 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \req_done + connect \B \cu_go_die_i + connect \Y $or$libresoc.v:21888$585_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" + cell $or $or$libresoc.v:21889$586 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_issue_i + connect \B \cu_go_die_i + connect \Y $or$libresoc.v:21889$586_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" + cell $or $or$libresoc.v:21890$587 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \cu_wr__go_i + connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } + connect \Y $or$libresoc.v:21890$587_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" + cell $or $or$libresoc.v:21891$588 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \cu_rd__go_i + connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } + connect \Y $or$libresoc.v:21891$588_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" + cell $or $or$libresoc.v:21895$592 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \reset_w + connect \B \prev_wr_go + connect \Y $or$libresoc.v:21895$592_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $or $or$libresoc.v:21904$601 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \$6 + connect \B \cu_rd__go_i + connect \Y $or$libresoc.v:21904$601_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $reduce_and $reduce_and$libresoc.v:21843$540 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $reduce_and$libresoc.v:21843$540_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $reduce_or $reduce_or$libresoc.v:21872$569 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \$27 + connect \Y $reduce_or$libresoc.v:21872$569_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $reduce_or $reduce_or$libresoc.v:21875$572 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \cu_wr__go_i + connect \Y $reduce_or$libresoc.v:21875$572_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $reduce_or $reduce_or$libresoc.v:21876$573 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \prev_wr_go + connect \Y $reduce_or$libresoc.v:21876$573_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" + cell $mux $ternary$libresoc.v:21901$598 + parameter \WIDTH 1 + connect \A \src_l_q_src [0] + connect \B \opc_l_q_opc + connect \S \alu_alu0_alu_op__zero_a + connect \Y $ternary$libresoc.v:21901$598_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" + cell $mux $ternary$libresoc.v:21902$599 + parameter \WIDTH 64 + connect \A \src1_i + connect \B 64'0000000000000000000000000000000000000000000000000000000000000000 + connect \S \alu_alu0_alu_op__zero_a + connect \Y $ternary$libresoc.v:21902$599_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" + cell $mux $ternary$libresoc.v:21903$600 + parameter \WIDTH 1 + connect \A \src_l_q_src [1] + connect \B \opc_l_q_opc + connect \S \alu_alu0_alu_op__imm_data__ok + connect \Y $ternary$libresoc.v:21903$600_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" + cell $mux $ternary$libresoc.v:21905$602 + parameter \WIDTH 64 + connect \A \src2_i + connect \B \alu_alu0_alu_op__imm_data__data + connect \S \alu_alu0_alu_op__imm_data__ok + connect \Y $ternary$libresoc.v:21905$602_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" + cell $mux $ternary$libresoc.v:21906$603 + parameter \WIDTH 64 + connect \A \src_r0 + connect \B \src_or_imm + connect \S \src_sel + connect \Y $ternary$libresoc.v:21906$603_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" + cell $mux $ternary$libresoc.v:21907$604 + parameter \WIDTH 64 + connect \A \src_r1 + connect \B \src_or_imm$88 + connect \S \src_sel$85 + connect \Y $ternary$libresoc.v:21907$604_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" + cell $mux $ternary$libresoc.v:21908$605 + parameter \WIDTH 1 + connect \A \src_r2 + connect \B \src3_i + connect \S \src_l_q_src [2] + connect \Y $ternary$libresoc.v:21908$605_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" + cell $mux $ternary$libresoc.v:21909$606 + parameter \WIDTH 2 + connect \A \src_r3 + connect \B \src4_i + connect \S \src_l_q_src [3] + connect \Y $ternary$libresoc.v:21909$606_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:22004.12-22043.4" + cell \alu_alu0 \alu_alu0 + connect \alu_op__data_len \alu_alu0_alu_op__data_len + connect \alu_op__fn_unit \alu_alu0_alu_op__fn_unit + connect \alu_op__imm_data__data \alu_alu0_alu_op__imm_data__data + connect \alu_op__imm_data__ok \alu_alu0_alu_op__imm_data__ok + connect \alu_op__input_carry \alu_alu0_alu_op__input_carry + connect \alu_op__insn \alu_alu0_alu_op__insn + connect \alu_op__insn_type \alu_alu0_alu_op__insn_type + connect \alu_op__invert_in \alu_alu0_alu_op__invert_in + connect \alu_op__invert_out \alu_alu0_alu_op__invert_out + connect \alu_op__is_32bit \alu_alu0_alu_op__is_32bit + connect \alu_op__is_signed \alu_alu0_alu_op__is_signed + connect \alu_op__oe__oe \alu_alu0_alu_op__oe__oe + connect \alu_op__oe__ok \alu_alu0_alu_op__oe__ok + connect \alu_op__output_carry \alu_alu0_alu_op__output_carry + connect \alu_op__rc__ok \alu_alu0_alu_op__rc__ok + connect \alu_op__rc__rc \alu_alu0_alu_op__rc__rc + connect \alu_op__write_cr0 \alu_alu0_alu_op__write_cr0 + connect \alu_op__zero_a \alu_alu0_alu_op__zero_a + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cr_a \alu_alu0_cr_a + connect \cr_a_ok \cr_a_ok + connect \n_ready_i \alu_alu0_n_ready_i + connect \n_valid_o \alu_alu0_n_valid_o + connect \o \alu_alu0_o + connect \o_ok \o_ok + connect \p_ready_o \alu_alu0_p_ready_o + connect \p_valid_i \alu_alu0_p_valid_i + connect \ra \alu_alu0_ra + connect \rb \alu_alu0_rb + connect \xer_ca \alu_alu0_xer_ca + connect \xer_ca$2 \alu_alu0_xer_ca$2 + connect \xer_ca_ok \xer_ca_ok + connect \xer_ov \alu_alu0_xer_ov + connect \xer_ov_ok \xer_ov_ok + connect \xer_so \alu_alu0_xer_so + connect \xer_so$1 \alu_alu0_xer_so$1 + connect \xer_so_ok \xer_so_ok + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:22044.9-22050.4" + cell \alu_l \alu_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_alu \alu_l_q_alu + connect \r_alu \alu_l_r_alu + connect \s_alu \alu_l_s_alu + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:22051.10-22057.4" + cell \alui_l \alui_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_alui \alui_l_q_alui + connect \r_alui \alui_l_r_alui + connect \s_alui \alui_l_s_alui + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:22058.9-22064.4" + cell \opc_l \opc_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_opc \opc_l_q_opc + connect \r_opc \opc_l_r_opc + connect \s_opc \opc_l_s_opc + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:22065.9-22071.4" + cell \req_l \req_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_req \req_l_q_req + connect \r_req \req_l_r_req + connect \s_req \req_l_s_req + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:22072.9-22078.4" + cell \rok_l \rok_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_rdok \rok_l_q_rdok + connect \r_rdok \rok_l_r_rdok + connect \s_rdok \rok_l_s_rdok + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:22079.9-22084.4" + cell \rst_l \rst_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \r_rst \rst_l_r_rst + connect \s_rst \rst_l_s_rst + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:22085.9-22091.4" + cell \src_l \src_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_src \src_l_q_src + connect \r_src \src_l_r_src + connect \s_src \src_l_s_src + end + attribute \src "libresoc.v:21165.7-21165.20" + process $proc$libresoc.v:21165$794 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:21303.7-21303.24" + process $proc$libresoc.v:21303$795 + assign { } { } + assign $1\all_rd_dly[0:0] 1'0 + sync always + sync init + update \all_rd_dly $1\all_rd_dly[0:0] + end + attribute \src "libresoc.v:21311.13-21311.45" + process $proc$libresoc.v:21311$796 + assign { } { } + assign $1\alu_alu0_alu_op__data_len[3:0] 4'0000 + sync always + sync init + update \alu_alu0_alu_op__data_len $1\alu_alu0_alu_op__data_len[3:0] + end + attribute \src "libresoc.v:21329.14-21329.49" + process $proc$libresoc.v:21329$797 + assign { } { } + assign $1\alu_alu0_alu_op__fn_unit[12:0] 13'0000000000000 + sync always + sync init + update \alu_alu0_alu_op__fn_unit $1\alu_alu0_alu_op__fn_unit[12:0] + end + attribute \src "libresoc.v:21333.14-21333.68" + process $proc$libresoc.v:21333$798 + assign { } { } + assign $1\alu_alu0_alu_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \alu_alu0_alu_op__imm_data__data $1\alu_alu0_alu_op__imm_data__data[63:0] + end + attribute \src "libresoc.v:21337.7-21337.43" + process $proc$libresoc.v:21337$799 + assign { } { } + assign $1\alu_alu0_alu_op__imm_data__ok[0:0] 1'0 + sync always + sync init + update \alu_alu0_alu_op__imm_data__ok $1\alu_alu0_alu_op__imm_data__ok[0:0] + end + attribute \src "libresoc.v:21345.13-21345.48" + process $proc$libresoc.v:21345$800 + assign { } { } + assign $1\alu_alu0_alu_op__input_carry[1:0] 2'00 + sync always + sync init + update \alu_alu0_alu_op__input_carry $1\alu_alu0_alu_op__input_carry[1:0] + end + attribute \src "libresoc.v:21349.14-21349.43" + process $proc$libresoc.v:21349$801 + assign { } { } + assign $1\alu_alu0_alu_op__insn[31:0] 0 + sync always + sync init + update \alu_alu0_alu_op__insn $1\alu_alu0_alu_op__insn[31:0] + end + attribute \src "libresoc.v:21427.13-21427.47" + process $proc$libresoc.v:21427$802 + assign { } { } + assign $1\alu_alu0_alu_op__insn_type[6:0] 7'0000000 + sync always + sync init + update \alu_alu0_alu_op__insn_type $1\alu_alu0_alu_op__insn_type[6:0] + end + attribute \src "libresoc.v:21431.7-21431.40" + process $proc$libresoc.v:21431$803 + assign { } { } + assign $1\alu_alu0_alu_op__invert_in[0:0] 1'0 + sync always + sync init + update \alu_alu0_alu_op__invert_in $1\alu_alu0_alu_op__invert_in[0:0] + end + attribute \src "libresoc.v:21435.7-21435.41" + process $proc$libresoc.v:21435$804 + assign { } { } + assign $1\alu_alu0_alu_op__invert_out[0:0] 1'0 + sync always + sync init + update \alu_alu0_alu_op__invert_out $1\alu_alu0_alu_op__invert_out[0:0] + end + attribute \src "libresoc.v:21439.7-21439.39" + process $proc$libresoc.v:21439$805 + assign { } { } + assign $1\alu_alu0_alu_op__is_32bit[0:0] 1'0 + sync always + sync init + update \alu_alu0_alu_op__is_32bit $1\alu_alu0_alu_op__is_32bit[0:0] + end + attribute \src "libresoc.v:21443.7-21443.40" + process $proc$libresoc.v:21443$806 + assign { } { } + assign $1\alu_alu0_alu_op__is_signed[0:0] 1'0 + sync always + sync init + update \alu_alu0_alu_op__is_signed $1\alu_alu0_alu_op__is_signed[0:0] + end + attribute \src "libresoc.v:21447.7-21447.37" + process $proc$libresoc.v:21447$807 + assign { } { } + assign $1\alu_alu0_alu_op__oe__oe[0:0] 1'0 + sync always + sync init + update \alu_alu0_alu_op__oe__oe $1\alu_alu0_alu_op__oe__oe[0:0] + end + attribute \src "libresoc.v:21451.7-21451.37" + process $proc$libresoc.v:21451$808 + assign { } { } + assign $1\alu_alu0_alu_op__oe__ok[0:0] 1'0 + sync always + sync init + update \alu_alu0_alu_op__oe__ok $1\alu_alu0_alu_op__oe__ok[0:0] + end + attribute \src "libresoc.v:21455.7-21455.43" + process $proc$libresoc.v:21455$809 + assign { } { } + assign $1\alu_alu0_alu_op__output_carry[0:0] 1'0 + sync always + sync init + update \alu_alu0_alu_op__output_carry $1\alu_alu0_alu_op__output_carry[0:0] + end + attribute \src "libresoc.v:21459.7-21459.37" + process $proc$libresoc.v:21459$810 + assign { } { } + assign $1\alu_alu0_alu_op__rc__ok[0:0] 1'0 + sync always + sync init + update \alu_alu0_alu_op__rc__ok $1\alu_alu0_alu_op__rc__ok[0:0] + end + attribute \src "libresoc.v:21463.7-21463.37" + process $proc$libresoc.v:21463$811 + assign { } { } + assign $1\alu_alu0_alu_op__rc__rc[0:0] 1'0 + sync always + sync init + update \alu_alu0_alu_op__rc__rc $1\alu_alu0_alu_op__rc__rc[0:0] + end + attribute \src "libresoc.v:21467.7-21467.40" + process $proc$libresoc.v:21467$812 + assign { } { } + assign $1\alu_alu0_alu_op__write_cr0[0:0] 1'0 + sync always + sync init + update \alu_alu0_alu_op__write_cr0 $1\alu_alu0_alu_op__write_cr0[0:0] + end + attribute \src "libresoc.v:21471.7-21471.37" + process $proc$libresoc.v:21471$813 + assign { } { } + assign $1\alu_alu0_alu_op__zero_a[0:0] 1'0 + sync always + sync init + update \alu_alu0_alu_op__zero_a $1\alu_alu0_alu_op__zero_a[0:0] + end + attribute \src "libresoc.v:21503.7-21503.26" + process $proc$libresoc.v:21503$814 + assign { } { } + assign $1\alu_done_dly[0:0] 1'0 + sync always + sync init + update \alu_done_dly $1\alu_done_dly[0:0] + end + attribute \src "libresoc.v:21511.7-21511.25" + process $proc$libresoc.v:21511$815 + assign { } { } + assign $1\alu_l_r_alu[0:0] 1'1 + sync always + sync init + update \alu_l_r_alu $1\alu_l_r_alu[0:0] + end + attribute \src "libresoc.v:21523.7-21523.27" + process $proc$libresoc.v:21523$816 + assign { } { } + assign $1\alui_l_r_alui[0:0] 1'1 + sync always + sync init + update \alui_l_r_alui $1\alui_l_r_alui[0:0] + end + attribute \src "libresoc.v:21557.14-21557.47" + process $proc$libresoc.v:21557$817 + assign { } { } + assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \data_r0__o $1\data_r0__o[63:0] + end + attribute \src "libresoc.v:21561.7-21561.27" + process $proc$libresoc.v:21561$818 + assign { } { } + assign $1\data_r0__o_ok[0:0] 1'0 + sync always + sync init + update \data_r0__o_ok $1\data_r0__o_ok[0:0] + end + attribute \src "libresoc.v:21565.13-21565.33" + process $proc$libresoc.v:21565$819 + assign { } { } + assign $1\data_r1__cr_a[3:0] 4'0000 + sync always + sync init + update \data_r1__cr_a $1\data_r1__cr_a[3:0] + end + attribute \src "libresoc.v:21569.7-21569.30" + process $proc$libresoc.v:21569$820 + assign { } { } + assign $1\data_r1__cr_a_ok[0:0] 1'0 + sync always + sync init + update \data_r1__cr_a_ok $1\data_r1__cr_a_ok[0:0] + end + attribute \src "libresoc.v:21573.13-21573.35" + process $proc$libresoc.v:21573$821 + assign { } { } + assign $1\data_r2__xer_ca[1:0] 2'00 + sync always + sync init + update \data_r2__xer_ca $1\data_r2__xer_ca[1:0] + end + attribute \src "libresoc.v:21577.7-21577.32" + process $proc$libresoc.v:21577$822 + assign { } { } + assign $1\data_r2__xer_ca_ok[0:0] 1'0 + sync always + sync init + update \data_r2__xer_ca_ok $1\data_r2__xer_ca_ok[0:0] + end + attribute \src "libresoc.v:21581.13-21581.35" + process $proc$libresoc.v:21581$823 + assign { } { } + assign $1\data_r3__xer_ov[1:0] 2'00 + sync always + sync init + update \data_r3__xer_ov $1\data_r3__xer_ov[1:0] + end + attribute \src "libresoc.v:21585.7-21585.32" + process $proc$libresoc.v:21585$824 + assign { } { } + assign $1\data_r3__xer_ov_ok[0:0] 1'0 + sync always + sync init + update \data_r3__xer_ov_ok $1\data_r3__xer_ov_ok[0:0] + end + attribute \src "libresoc.v:21589.7-21589.29" + process $proc$libresoc.v:21589$825 + assign { } { } + assign $1\data_r4__xer_so[0:0] 1'0 + sync always + sync init + update \data_r4__xer_so $1\data_r4__xer_so[0:0] + end + attribute \src "libresoc.v:21593.7-21593.32" + process $proc$libresoc.v:21593$826 + assign { } { } + assign $1\data_r4__xer_so_ok[0:0] 1'0 + sync always + sync init + update \data_r4__xer_so_ok $1\data_r4__xer_so_ok[0:0] + end + attribute \src "libresoc.v:21616.7-21616.25" + process $proc$libresoc.v:21616$827 + assign { } { } + assign $1\opc_l_r_opc[0:0] 1'1 + sync always + sync init + update \opc_l_r_opc $1\opc_l_r_opc[0:0] + end + attribute \src "libresoc.v:21620.7-21620.25" + process $proc$libresoc.v:21620$828 + assign { } { } + assign $1\opc_l_s_opc[0:0] 1'0 + sync always + sync init + update \opc_l_s_opc $1\opc_l_s_opc[0:0] + end + attribute \src "libresoc.v:21752.13-21752.31" + process $proc$libresoc.v:21752$829 + assign { } { } + assign $1\prev_wr_go[4:0] 5'00000 + sync always + sync init + update \prev_wr_go $1\prev_wr_go[4:0] + end + attribute \src "libresoc.v:21760.13-21760.32" + process $proc$libresoc.v:21760$830 + assign { } { } + assign $1\req_l_r_req[4:0] 5'11111 + sync always + sync init + update \req_l_r_req $1\req_l_r_req[4:0] + end + attribute \src "libresoc.v:21764.13-21764.32" + process $proc$libresoc.v:21764$831 + assign { } { } + assign $1\req_l_s_req[4:0] 5'00000 + sync always + sync init + update \req_l_s_req $1\req_l_s_req[4:0] + end + attribute \src "libresoc.v:21776.7-21776.26" + process $proc$libresoc.v:21776$832 + assign { } { } + assign $1\rok_l_r_rdok[0:0] 1'1 + sync always + sync init + update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] + end + attribute \src "libresoc.v:21780.7-21780.26" + process $proc$libresoc.v:21780$833 + assign { } { } + assign $1\rok_l_s_rdok[0:0] 1'0 + sync always + sync init + update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] + end + attribute \src "libresoc.v:21784.7-21784.25" + process $proc$libresoc.v:21784$834 + assign { } { } + assign $1\rst_l_r_rst[0:0] 1'1 + sync always + sync init + update \rst_l_r_rst $1\rst_l_r_rst[0:0] + end + attribute \src "libresoc.v:21788.7-21788.25" + process $proc$libresoc.v:21788$835 + assign { } { } + assign $1\rst_l_s_rst[0:0] 1'0 + sync always + sync init + update \rst_l_s_rst $1\rst_l_s_rst[0:0] + end + attribute \src "libresoc.v:21804.13-21804.31" + process $proc$libresoc.v:21804$836 + assign { } { } + assign $1\src_l_r_src[3:0] 4'1111 + sync always + sync init + update \src_l_r_src $1\src_l_r_src[3:0] + end + attribute \src "libresoc.v:21808.13-21808.31" + process $proc$libresoc.v:21808$837 + assign { } { } + assign $1\src_l_s_src[3:0] 4'0000 + sync always + sync init + update \src_l_s_src $1\src_l_s_src[3:0] + end + attribute \src "libresoc.v:21816.14-21816.43" + process $proc$libresoc.v:21816$838 + assign { } { } + assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \src_r0 $1\src_r0[63:0] + end + attribute \src "libresoc.v:21820.14-21820.43" + process $proc$libresoc.v:21820$839 + assign { } { } + assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \src_r1 $1\src_r1[63:0] + end + attribute \src "libresoc.v:21824.7-21824.20" + process $proc$libresoc.v:21824$840 + assign { } { } + assign $1\src_r2[0:0] 1'0 + sync always + sync init + update \src_r2 $1\src_r2[0:0] + end + attribute \src "libresoc.v:21828.13-21828.26" + process $proc$libresoc.v:21828$841 + assign { } { } + assign $1\src_r3[1:0] 2'00 + sync always + sync init + update \src_r3 $1\src_r3[1:0] + end + attribute \src "libresoc.v:21910.3-21911.39" + process $proc$libresoc.v:21910$607 + assign { } { } + assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next + sync posedge \coresync_clk + update \alu_l_r_alu $0\alu_l_r_alu[0:0] + end + attribute \src "libresoc.v:21912.3-21913.43" + process $proc$libresoc.v:21912$608 + assign { } { } + assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next + sync posedge \coresync_clk + update \alui_l_r_alui $0\alui_l_r_alui[0:0] + end + attribute \src "libresoc.v:21914.3-21915.29" + process $proc$libresoc.v:21914$609 + assign { } { } + assign $0\src_r3[1:0] \src_r3$next + sync posedge \coresync_clk + update \src_r3 $0\src_r3[1:0] + end + attribute \src "libresoc.v:21916.3-21917.29" + process $proc$libresoc.v:21916$610 + assign { } { } + assign $0\src_r2[0:0] \src_r2$next + sync posedge \coresync_clk + update \src_r2 $0\src_r2[0:0] + end + attribute \src "libresoc.v:21918.3-21919.29" + process $proc$libresoc.v:21918$611 + assign { } { } + assign $0\src_r1[63:0] \src_r1$next + sync posedge \coresync_clk + update \src_r1 $0\src_r1[63:0] + end + attribute \src "libresoc.v:21920.3-21921.29" + process $proc$libresoc.v:21920$612 + assign { } { } + assign $0\src_r0[63:0] \src_r0$next + sync posedge \coresync_clk + update \src_r0 $0\src_r0[63:0] + end + attribute \src "libresoc.v:21922.3-21923.47" + process $proc$libresoc.v:21922$613 + assign { } { } + assign $0\data_r4__xer_so[0:0] \data_r4__xer_so$next + sync posedge \coresync_clk + update \data_r4__xer_so $0\data_r4__xer_so[0:0] + end + attribute \src "libresoc.v:21924.3-21925.53" + process $proc$libresoc.v:21924$614 + assign { } { } + assign $0\data_r4__xer_so_ok[0:0] \data_r4__xer_so_ok$next + sync posedge \coresync_clk + update \data_r4__xer_so_ok $0\data_r4__xer_so_ok[0:0] + end + attribute \src "libresoc.v:21926.3-21927.47" + process $proc$libresoc.v:21926$615 + assign { } { } + assign $0\data_r3__xer_ov[1:0] \data_r3__xer_ov$next + sync posedge \coresync_clk + update \data_r3__xer_ov $0\data_r3__xer_ov[1:0] + end + attribute \src "libresoc.v:21928.3-21929.53" + process $proc$libresoc.v:21928$616 + assign { } { } + assign $0\data_r3__xer_ov_ok[0:0] \data_r3__xer_ov_ok$next + sync posedge \coresync_clk + update \data_r3__xer_ov_ok $0\data_r3__xer_ov_ok[0:0] + end + attribute \src "libresoc.v:21930.3-21931.47" + process $proc$libresoc.v:21930$617 + assign { } { } + assign $0\data_r2__xer_ca[1:0] \data_r2__xer_ca$next + sync posedge \coresync_clk + update \data_r2__xer_ca $0\data_r2__xer_ca[1:0] + end + attribute \src "libresoc.v:21932.3-21933.53" + process $proc$libresoc.v:21932$618 + assign { } { } + assign $0\data_r2__xer_ca_ok[0:0] \data_r2__xer_ca_ok$next + sync posedge \coresync_clk + update \data_r2__xer_ca_ok $0\data_r2__xer_ca_ok[0:0] + end + attribute \src "libresoc.v:21934.3-21935.43" + process $proc$libresoc.v:21934$619 + assign { } { } + assign $0\data_r1__cr_a[3:0] \data_r1__cr_a$next + sync posedge \coresync_clk + update \data_r1__cr_a $0\data_r1__cr_a[3:0] + end + attribute \src "libresoc.v:21936.3-21937.49" + process $proc$libresoc.v:21936$620 + assign { } { } + assign $0\data_r1__cr_a_ok[0:0] \data_r1__cr_a_ok$next + sync posedge \coresync_clk + update \data_r1__cr_a_ok $0\data_r1__cr_a_ok[0:0] + end + attribute \src "libresoc.v:21938.3-21939.37" + process $proc$libresoc.v:21938$621 + assign { } { } + assign $0\data_r0__o[63:0] \data_r0__o$next + sync posedge \coresync_clk + update \data_r0__o $0\data_r0__o[63:0] + end + attribute \src "libresoc.v:21940.3-21941.43" + process $proc$libresoc.v:21940$622 + assign { } { } + assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next + sync posedge \coresync_clk + update \data_r0__o_ok $0\data_r0__o_ok[0:0] + end + attribute \src "libresoc.v:21942.3-21943.69" + process $proc$libresoc.v:21942$623 + assign { } { } + assign $0\alu_alu0_alu_op__insn_type[6:0] \alu_alu0_alu_op__insn_type$next + sync posedge \coresync_clk + update \alu_alu0_alu_op__insn_type $0\alu_alu0_alu_op__insn_type[6:0] + end + attribute \src "libresoc.v:21944.3-21945.65" + process $proc$libresoc.v:21944$624 + assign { } { } + assign $0\alu_alu0_alu_op__fn_unit[12:0] \alu_alu0_alu_op__fn_unit$next + sync posedge \coresync_clk + update \alu_alu0_alu_op__fn_unit $0\alu_alu0_alu_op__fn_unit[12:0] + end + attribute \src "libresoc.v:21946.3-21947.79" + process $proc$libresoc.v:21946$625 + assign { } { } + assign $0\alu_alu0_alu_op__imm_data__data[63:0] \alu_alu0_alu_op__imm_data__data$next + sync posedge \coresync_clk + update \alu_alu0_alu_op__imm_data__data $0\alu_alu0_alu_op__imm_data__data[63:0] + end + attribute \src "libresoc.v:21948.3-21949.75" + process $proc$libresoc.v:21948$626 + assign { } { } + assign $0\alu_alu0_alu_op__imm_data__ok[0:0] \alu_alu0_alu_op__imm_data__ok$next + sync posedge \coresync_clk + update \alu_alu0_alu_op__imm_data__ok $0\alu_alu0_alu_op__imm_data__ok[0:0] + end + attribute \src "libresoc.v:21950.3-21951.63" + process $proc$libresoc.v:21950$627 + assign { } { } + assign $0\alu_alu0_alu_op__rc__rc[0:0] \alu_alu0_alu_op__rc__rc$next + sync posedge \coresync_clk + update \alu_alu0_alu_op__rc__rc $0\alu_alu0_alu_op__rc__rc[0:0] + end + attribute \src "libresoc.v:21952.3-21953.63" + process $proc$libresoc.v:21952$628 + assign { } { } + assign $0\alu_alu0_alu_op__rc__ok[0:0] \alu_alu0_alu_op__rc__ok$next + sync posedge \coresync_clk + update \alu_alu0_alu_op__rc__ok $0\alu_alu0_alu_op__rc__ok[0:0] + end + attribute \src "libresoc.v:21954.3-21955.63" + process $proc$libresoc.v:21954$629 + assign { } { } + assign $0\alu_alu0_alu_op__oe__oe[0:0] \alu_alu0_alu_op__oe__oe$next + sync posedge \coresync_clk + update \alu_alu0_alu_op__oe__oe $0\alu_alu0_alu_op__oe__oe[0:0] + end + attribute \src "libresoc.v:21956.3-21957.63" + process $proc$libresoc.v:21956$630 + assign { } { } + assign $0\alu_alu0_alu_op__oe__ok[0:0] \alu_alu0_alu_op__oe__ok$next + sync posedge \coresync_clk + update \alu_alu0_alu_op__oe__ok $0\alu_alu0_alu_op__oe__ok[0:0] + end + attribute \src "libresoc.v:21958.3-21959.69" + process $proc$libresoc.v:21958$631 + assign { } { } + assign $0\alu_alu0_alu_op__invert_in[0:0] \alu_alu0_alu_op__invert_in$next + sync posedge \coresync_clk + update \alu_alu0_alu_op__invert_in $0\alu_alu0_alu_op__invert_in[0:0] + end + attribute \src "libresoc.v:21960.3-21961.63" + process $proc$libresoc.v:21960$632 + assign { } { } + assign $0\alu_alu0_alu_op__zero_a[0:0] \alu_alu0_alu_op__zero_a$next + sync posedge \coresync_clk + update \alu_alu0_alu_op__zero_a $0\alu_alu0_alu_op__zero_a[0:0] + end + attribute \src "libresoc.v:21962.3-21963.71" + process $proc$libresoc.v:21962$633 + assign { } { } + assign $0\alu_alu0_alu_op__invert_out[0:0] \alu_alu0_alu_op__invert_out$next + sync posedge \coresync_clk + update \alu_alu0_alu_op__invert_out $0\alu_alu0_alu_op__invert_out[0:0] + end + attribute \src "libresoc.v:21964.3-21965.69" + process $proc$libresoc.v:21964$634 + assign { } { } + assign $0\alu_alu0_alu_op__write_cr0[0:0] \alu_alu0_alu_op__write_cr0$next + sync posedge \coresync_clk + update \alu_alu0_alu_op__write_cr0 $0\alu_alu0_alu_op__write_cr0[0:0] + end + attribute \src "libresoc.v:21966.3-21967.73" + process $proc$libresoc.v:21966$635 + assign { } { } + assign $0\alu_alu0_alu_op__input_carry[1:0] \alu_alu0_alu_op__input_carry$next + sync posedge \coresync_clk + update \alu_alu0_alu_op__input_carry $0\alu_alu0_alu_op__input_carry[1:0] + end + attribute \src "libresoc.v:21968.3-21969.75" + process $proc$libresoc.v:21968$636 + assign { } { } + assign $0\alu_alu0_alu_op__output_carry[0:0] \alu_alu0_alu_op__output_carry$next + sync posedge \coresync_clk + update \alu_alu0_alu_op__output_carry $0\alu_alu0_alu_op__output_carry[0:0] + end + attribute \src "libresoc.v:21970.3-21971.67" + process $proc$libresoc.v:21970$637 + assign { } { } + assign $0\alu_alu0_alu_op__is_32bit[0:0] \alu_alu0_alu_op__is_32bit$next + sync posedge \coresync_clk + update \alu_alu0_alu_op__is_32bit $0\alu_alu0_alu_op__is_32bit[0:0] + end + attribute \src "libresoc.v:21972.3-21973.69" + process $proc$libresoc.v:21972$638 + assign { } { } + assign $0\alu_alu0_alu_op__is_signed[0:0] \alu_alu0_alu_op__is_signed$next + sync posedge \coresync_clk + update \alu_alu0_alu_op__is_signed $0\alu_alu0_alu_op__is_signed[0:0] + end + attribute \src "libresoc.v:21974.3-21975.67" + process $proc$libresoc.v:21974$639 + assign { } { } + assign $0\alu_alu0_alu_op__data_len[3:0] \alu_alu0_alu_op__data_len$next + sync posedge \coresync_clk + update \alu_alu0_alu_op__data_len $0\alu_alu0_alu_op__data_len[3:0] + end + attribute \src "libresoc.v:21976.3-21977.59" + process $proc$libresoc.v:21976$640 + assign { } { } + assign $0\alu_alu0_alu_op__insn[31:0] \alu_alu0_alu_op__insn$next + sync posedge \coresync_clk + update \alu_alu0_alu_op__insn $0\alu_alu0_alu_op__insn[31:0] + end + attribute \src "libresoc.v:21978.3-21979.39" + process $proc$libresoc.v:21978$641 + assign { } { } + assign $0\req_l_r_req[4:0] \req_l_r_req$next + sync posedge \coresync_clk + update \req_l_r_req $0\req_l_r_req[4:0] + end + attribute \src "libresoc.v:21980.3-21981.39" + process $proc$libresoc.v:21980$642 + assign { } { } + assign $0\req_l_s_req[4:0] \req_l_s_req$next + sync posedge \coresync_clk + update \req_l_s_req $0\req_l_s_req[4:0] + end + attribute \src "libresoc.v:21982.3-21983.39" + process $proc$libresoc.v:21982$643 + assign { } { } + assign $0\src_l_r_src[3:0] \src_l_r_src$next + sync posedge \coresync_clk + update \src_l_r_src $0\src_l_r_src[3:0] + end + attribute \src "libresoc.v:21984.3-21985.39" + process $proc$libresoc.v:21984$644 + assign { } { } + assign $0\src_l_s_src[3:0] \src_l_s_src$next + sync posedge \coresync_clk + update \src_l_s_src $0\src_l_s_src[3:0] + end + attribute \src "libresoc.v:21986.3-21987.39" + process $proc$libresoc.v:21986$645 + assign { } { } + assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next + sync posedge \coresync_clk + update \opc_l_r_opc $0\opc_l_r_opc[0:0] + end + attribute \src "libresoc.v:21988.3-21989.39" + process $proc$libresoc.v:21988$646 + assign { } { } + assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next + sync posedge \coresync_clk + update \opc_l_s_opc $0\opc_l_s_opc[0:0] + end + attribute \src "libresoc.v:21990.3-21991.39" + process $proc$libresoc.v:21990$647 + assign { } { } + assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next + sync posedge \coresync_clk + update \rst_l_r_rst $0\rst_l_r_rst[0:0] + end + attribute \src "libresoc.v:21992.3-21993.39" + process $proc$libresoc.v:21992$648 + assign { } { } + assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next + sync posedge \coresync_clk + update \rst_l_s_rst $0\rst_l_s_rst[0:0] + end + attribute \src "libresoc.v:21994.3-21995.41" + process $proc$libresoc.v:21994$649 + assign { } { } + assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next + sync posedge \coresync_clk + update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] + end + attribute \src "libresoc.v:21996.3-21997.41" + process $proc$libresoc.v:21996$650 + assign { } { } + assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next + sync posedge \coresync_clk + update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] + end + attribute \src "libresoc.v:21998.3-21999.37" + process $proc$libresoc.v:21998$651 + assign { } { } + assign $0\prev_wr_go[4:0] \prev_wr_go$next + sync posedge \coresync_clk + update \prev_wr_go $0\prev_wr_go[4:0] + end + attribute \src "libresoc.v:22000.3-22001.40" + process $proc$libresoc.v:22000$652 + assign { } { } + assign $0\alu_done_dly[0:0] \alu_alu0_n_valid_o + sync posedge \coresync_clk + update \alu_done_dly $0\alu_done_dly[0:0] + end + attribute \src "libresoc.v:22002.3-22003.25" + process $proc$libresoc.v:22002$653 + assign { } { } + assign $0\all_rd_dly[0:0] \$11 + sync posedge \coresync_clk + update \all_rd_dly $0\all_rd_dly[0:0] + end + attribute \src "libresoc.v:22092.3-22101.6" + process $proc$libresoc.v:22092$654 + assign { } { } + assign { } { } + assign $0\req_done[0:0] $1\req_done[0:0] + attribute \src "libresoc.v:22093.5-22093.29" + switch \initial + attribute \src "libresoc.v:22093.9-22093.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + switch \$55 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\req_done[0:0] 1'1 + case + assign $1\req_done[0:0] \$47 + end + sync always + update \req_done $0\req_done[0:0] + end + attribute \src "libresoc.v:22102.3-22110.6" + process $proc$libresoc.v:22102$655 + assign { } { } + assign { } { } + assign $0\rok_l_s_rdok$next[0:0]$656 $1\rok_l_s_rdok$next[0:0]$657 + attribute \src "libresoc.v:22103.5-22103.29" + switch \initial + attribute \src "libresoc.v:22103.9-22103.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rok_l_s_rdok$next[0:0]$657 1'0 + case + assign $1\rok_l_s_rdok$next[0:0]$657 \cu_issue_i + end + sync always + update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$656 + end + attribute \src "libresoc.v:22111.3-22119.6" + process $proc$libresoc.v:22111$658 + assign { } { } + assign { } { } + assign $0\rok_l_r_rdok$next[0:0]$659 $1\rok_l_r_rdok$next[0:0]$660 + attribute \src "libresoc.v:22112.5-22112.29" + switch \initial + attribute \src "libresoc.v:22112.9-22112.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rok_l_r_rdok$next[0:0]$660 1'1 + case + assign $1\rok_l_r_rdok$next[0:0]$660 \$65 + end + sync always + update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$659 + end + attribute \src "libresoc.v:22120.3-22128.6" + process $proc$libresoc.v:22120$661 + assign { } { } + assign { } { } + assign $0\rst_l_s_rst$next[0:0]$662 $1\rst_l_s_rst$next[0:0]$663 + attribute \src "libresoc.v:22121.5-22121.29" + switch \initial + attribute \src "libresoc.v:22121.9-22121.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rst_l_s_rst$next[0:0]$663 1'0 + case + assign $1\rst_l_s_rst$next[0:0]$663 \all_rd + end + sync always + update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$662 + end + attribute \src "libresoc.v:22129.3-22137.6" + process $proc$libresoc.v:22129$664 + assign { } { } + assign { } { } + assign $0\rst_l_r_rst$next[0:0]$665 $1\rst_l_r_rst$next[0:0]$666 + attribute \src "libresoc.v:22130.5-22130.29" + switch \initial + attribute \src "libresoc.v:22130.9-22130.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rst_l_r_rst$next[0:0]$666 1'1 + case + assign $1\rst_l_r_rst$next[0:0]$666 \rst_r + end + sync always + update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$665 + end + attribute \src "libresoc.v:22138.3-22146.6" + process $proc$libresoc.v:22138$667 + assign { } { } + assign { } { } + assign $0\opc_l_s_opc$next[0:0]$668 $1\opc_l_s_opc$next[0:0]$669 + attribute \src "libresoc.v:22139.5-22139.29" + switch \initial + attribute \src "libresoc.v:22139.9-22139.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\opc_l_s_opc$next[0:0]$669 1'0 + case + assign $1\opc_l_s_opc$next[0:0]$669 \cu_issue_i + end + sync always + update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$668 + end + attribute \src "libresoc.v:22147.3-22155.6" + process $proc$libresoc.v:22147$670 + assign { } { } + assign { } { } + assign $0\opc_l_r_opc$next[0:0]$671 $1\opc_l_r_opc$next[0:0]$672 + attribute \src "libresoc.v:22148.5-22148.29" + switch \initial + attribute \src "libresoc.v:22148.9-22148.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\opc_l_r_opc$next[0:0]$672 1'1 + case + assign $1\opc_l_r_opc$next[0:0]$672 \req_done + end + sync always + update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$671 + end + attribute \src "libresoc.v:22156.3-22164.6" + process $proc$libresoc.v:22156$673 + assign { } { } + assign { } { } + assign $0\src_l_s_src$next[3:0]$674 $1\src_l_s_src$next[3:0]$675 + attribute \src "libresoc.v:22157.5-22157.29" + switch \initial + attribute \src "libresoc.v:22157.9-22157.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_l_s_src$next[3:0]$675 4'0000 + case + assign $1\src_l_s_src$next[3:0]$675 { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i } + end + sync always + update \src_l_s_src$next $0\src_l_s_src$next[3:0]$674 + end + attribute \src "libresoc.v:22165.3-22173.6" + process $proc$libresoc.v:22165$676 + assign { } { } + assign { } { } + assign $0\src_l_r_src$next[3:0]$677 $1\src_l_r_src$next[3:0]$678 + attribute \src "libresoc.v:22166.5-22166.29" + switch \initial + attribute \src "libresoc.v:22166.9-22166.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_l_r_src$next[3:0]$678 4'1111 + case + assign $1\src_l_r_src$next[3:0]$678 \reset_r + end + sync always + update \src_l_r_src$next $0\src_l_r_src$next[3:0]$677 + end + attribute \src "libresoc.v:22174.3-22182.6" + process $proc$libresoc.v:22174$679 + assign { } { } + assign { } { } + assign $0\req_l_s_req$next[4:0]$680 $1\req_l_s_req$next[4:0]$681 + attribute \src "libresoc.v:22175.5-22175.29" + switch \initial + attribute \src "libresoc.v:22175.9-22175.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\req_l_s_req$next[4:0]$681 5'00000 + case + assign $1\req_l_s_req$next[4:0]$681 \$67 + end + sync always + update \req_l_s_req$next $0\req_l_s_req$next[4:0]$680 + end + attribute \src "libresoc.v:22183.3-22191.6" + process $proc$libresoc.v:22183$682 + assign { } { } + assign { } { } + assign $0\req_l_r_req$next[4:0]$683 $1\req_l_r_req$next[4:0]$684 + attribute \src "libresoc.v:22184.5-22184.29" + switch \initial + attribute \src "libresoc.v:22184.9-22184.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\req_l_r_req$next[4:0]$684 5'11111 + case + assign $1\req_l_r_req$next[4:0]$684 \$69 + end + sync always + update \req_l_r_req$next $0\req_l_r_req$next[4:0]$683 + end + attribute \src "libresoc.v:22192.3-22230.6" + process $proc$libresoc.v:22192$685 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\alu_alu0_alu_op__data_len$next[3:0]$686 $1\alu_alu0_alu_op__data_len$next[3:0]$704 + assign $0\alu_alu0_alu_op__fn_unit$next[12:0]$687 $1\alu_alu0_alu_op__fn_unit$next[12:0]$705 + assign { } { } + assign { } { } + assign $0\alu_alu0_alu_op__input_carry$next[1:0]$690 $1\alu_alu0_alu_op__input_carry$next[1:0]$708 + assign $0\alu_alu0_alu_op__insn$next[31:0]$691 $1\alu_alu0_alu_op__insn$next[31:0]$709 + assign $0\alu_alu0_alu_op__insn_type$next[6:0]$692 $1\alu_alu0_alu_op__insn_type$next[6:0]$710 + assign $0\alu_alu0_alu_op__invert_in$next[0:0]$693 $1\alu_alu0_alu_op__invert_in$next[0:0]$711 + assign $0\alu_alu0_alu_op__invert_out$next[0:0]$694 $1\alu_alu0_alu_op__invert_out$next[0:0]$712 + assign $0\alu_alu0_alu_op__is_32bit$next[0:0]$695 $1\alu_alu0_alu_op__is_32bit$next[0:0]$713 + assign $0\alu_alu0_alu_op__is_signed$next[0:0]$696 $1\alu_alu0_alu_op__is_signed$next[0:0]$714 + assign { } { } + assign { } { } + assign $0\alu_alu0_alu_op__output_carry$next[0:0]$699 $1\alu_alu0_alu_op__output_carry$next[0:0]$717 + assign { } { } + assign { } { } + assign $0\alu_alu0_alu_op__write_cr0$next[0:0]$702 $1\alu_alu0_alu_op__write_cr0$next[0:0]$720 + assign $0\alu_alu0_alu_op__zero_a$next[0:0]$703 $1\alu_alu0_alu_op__zero_a$next[0:0]$721 + assign $0\alu_alu0_alu_op__imm_data__data$next[63:0]$688 $2\alu_alu0_alu_op__imm_data__data$next[63:0]$722 + assign $0\alu_alu0_alu_op__imm_data__ok$next[0:0]$689 $2\alu_alu0_alu_op__imm_data__ok$next[0:0]$723 + assign $0\alu_alu0_alu_op__oe__oe$next[0:0]$697 $2\alu_alu0_alu_op__oe__oe$next[0:0]$724 + assign $0\alu_alu0_alu_op__oe__ok$next[0:0]$698 $2\alu_alu0_alu_op__oe__ok$next[0:0]$725 + assign $0\alu_alu0_alu_op__rc__ok$next[0:0]$700 $2\alu_alu0_alu_op__rc__ok$next[0:0]$726 + assign $0\alu_alu0_alu_op__rc__rc$next[0:0]$701 $2\alu_alu0_alu_op__rc__rc$next[0:0]$727 + attribute \src "libresoc.v:22193.5-22193.29" + switch \initial + attribute \src "libresoc.v:22193.9-22193.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\alu_alu0_alu_op__insn$next[31:0]$709 $1\alu_alu0_alu_op__data_len$next[3:0]$704 $1\alu_alu0_alu_op__is_signed$next[0:0]$714 $1\alu_alu0_alu_op__is_32bit$next[0:0]$713 $1\alu_alu0_alu_op__output_carry$next[0:0]$717 $1\alu_alu0_alu_op__input_carry$next[1:0]$708 $1\alu_alu0_alu_op__write_cr0$next[0:0]$720 $1\alu_alu0_alu_op__invert_out$next[0:0]$712 $1\alu_alu0_alu_op__zero_a$next[0:0]$721 $1\alu_alu0_alu_op__invert_in$next[0:0]$711 $1\alu_alu0_alu_op__oe__ok$next[0:0]$716 $1\alu_alu0_alu_op__oe__oe$next[0:0]$715 $1\alu_alu0_alu_op__rc__ok$next[0:0]$718 $1\alu_alu0_alu_op__rc__rc$next[0:0]$719 $1\alu_alu0_alu_op__imm_data__ok$next[0:0]$707 $1\alu_alu0_alu_op__imm_data__data$next[63:0]$706 $1\alu_alu0_alu_op__fn_unit$next[12:0]$705 $1\alu_alu0_alu_op__insn_type$next[6:0]$710 } { \oper_i_alu_alu0__insn \oper_i_alu_alu0__data_len \oper_i_alu_alu0__is_signed \oper_i_alu_alu0__is_32bit \oper_i_alu_alu0__output_carry \oper_i_alu_alu0__input_carry \oper_i_alu_alu0__write_cr0 \oper_i_alu_alu0__invert_out \oper_i_alu_alu0__zero_a \oper_i_alu_alu0__invert_in \oper_i_alu_alu0__oe__ok \oper_i_alu_alu0__oe__oe \oper_i_alu_alu0__rc__ok \oper_i_alu_alu0__rc__rc \oper_i_alu_alu0__imm_data__ok \oper_i_alu_alu0__imm_data__data \oper_i_alu_alu0__fn_unit \oper_i_alu_alu0__insn_type } + case + assign $1\alu_alu0_alu_op__data_len$next[3:0]$704 \alu_alu0_alu_op__data_len + assign $1\alu_alu0_alu_op__fn_unit$next[12:0]$705 \alu_alu0_alu_op__fn_unit + assign $1\alu_alu0_alu_op__imm_data__data$next[63:0]$706 \alu_alu0_alu_op__imm_data__data + assign $1\alu_alu0_alu_op__imm_data__ok$next[0:0]$707 \alu_alu0_alu_op__imm_data__ok + assign $1\alu_alu0_alu_op__input_carry$next[1:0]$708 \alu_alu0_alu_op__input_carry + assign $1\alu_alu0_alu_op__insn$next[31:0]$709 \alu_alu0_alu_op__insn + assign $1\alu_alu0_alu_op__insn_type$next[6:0]$710 \alu_alu0_alu_op__insn_type + assign $1\alu_alu0_alu_op__invert_in$next[0:0]$711 \alu_alu0_alu_op__invert_in + assign $1\alu_alu0_alu_op__invert_out$next[0:0]$712 \alu_alu0_alu_op__invert_out + assign $1\alu_alu0_alu_op__is_32bit$next[0:0]$713 \alu_alu0_alu_op__is_32bit + assign $1\alu_alu0_alu_op__is_signed$next[0:0]$714 \alu_alu0_alu_op__is_signed + assign $1\alu_alu0_alu_op__oe__oe$next[0:0]$715 \alu_alu0_alu_op__oe__oe + assign $1\alu_alu0_alu_op__oe__ok$next[0:0]$716 \alu_alu0_alu_op__oe__ok + assign $1\alu_alu0_alu_op__output_carry$next[0:0]$717 \alu_alu0_alu_op__output_carry + assign $1\alu_alu0_alu_op__rc__ok$next[0:0]$718 \alu_alu0_alu_op__rc__ok + assign $1\alu_alu0_alu_op__rc__rc$next[0:0]$719 \alu_alu0_alu_op__rc__rc + assign $1\alu_alu0_alu_op__write_cr0$next[0:0]$720 \alu_alu0_alu_op__write_cr0 + assign $1\alu_alu0_alu_op__zero_a$next[0:0]$721 \alu_alu0_alu_op__zero_a + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $2\alu_alu0_alu_op__imm_data__data$next[63:0]$722 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\alu_alu0_alu_op__imm_data__ok$next[0:0]$723 1'0 + assign $2\alu_alu0_alu_op__rc__rc$next[0:0]$727 1'0 + assign $2\alu_alu0_alu_op__rc__ok$next[0:0]$726 1'0 + assign $2\alu_alu0_alu_op__oe__oe$next[0:0]$724 1'0 + assign $2\alu_alu0_alu_op__oe__ok$next[0:0]$725 1'0 + case + assign $2\alu_alu0_alu_op__imm_data__data$next[63:0]$722 $1\alu_alu0_alu_op__imm_data__data$next[63:0]$706 + assign $2\alu_alu0_alu_op__imm_data__ok$next[0:0]$723 $1\alu_alu0_alu_op__imm_data__ok$next[0:0]$707 + assign $2\alu_alu0_alu_op__oe__oe$next[0:0]$724 $1\alu_alu0_alu_op__oe__oe$next[0:0]$715 + assign $2\alu_alu0_alu_op__oe__ok$next[0:0]$725 $1\alu_alu0_alu_op__oe__ok$next[0:0]$716 + assign $2\alu_alu0_alu_op__rc__ok$next[0:0]$726 $1\alu_alu0_alu_op__rc__ok$next[0:0]$718 + assign $2\alu_alu0_alu_op__rc__rc$next[0:0]$727 $1\alu_alu0_alu_op__rc__rc$next[0:0]$719 + end + sync always + update \alu_alu0_alu_op__data_len$next $0\alu_alu0_alu_op__data_len$next[3:0]$686 + update \alu_alu0_alu_op__fn_unit$next $0\alu_alu0_alu_op__fn_unit$next[12:0]$687 + update \alu_alu0_alu_op__imm_data__data$next $0\alu_alu0_alu_op__imm_data__data$next[63:0]$688 + update \alu_alu0_alu_op__imm_data__ok$next $0\alu_alu0_alu_op__imm_data__ok$next[0:0]$689 + update \alu_alu0_alu_op__input_carry$next $0\alu_alu0_alu_op__input_carry$next[1:0]$690 + update \alu_alu0_alu_op__insn$next $0\alu_alu0_alu_op__insn$next[31:0]$691 + update \alu_alu0_alu_op__insn_type$next $0\alu_alu0_alu_op__insn_type$next[6:0]$692 + update \alu_alu0_alu_op__invert_in$next $0\alu_alu0_alu_op__invert_in$next[0:0]$693 + update \alu_alu0_alu_op__invert_out$next $0\alu_alu0_alu_op__invert_out$next[0:0]$694 + update \alu_alu0_alu_op__is_32bit$next $0\alu_alu0_alu_op__is_32bit$next[0:0]$695 + update \alu_alu0_alu_op__is_signed$next $0\alu_alu0_alu_op__is_signed$next[0:0]$696 + update \alu_alu0_alu_op__oe__oe$next $0\alu_alu0_alu_op__oe__oe$next[0:0]$697 + update \alu_alu0_alu_op__oe__ok$next $0\alu_alu0_alu_op__oe__ok$next[0:0]$698 + update \alu_alu0_alu_op__output_carry$next $0\alu_alu0_alu_op__output_carry$next[0:0]$699 + update \alu_alu0_alu_op__rc__ok$next $0\alu_alu0_alu_op__rc__ok$next[0:0]$700 + update \alu_alu0_alu_op__rc__rc$next $0\alu_alu0_alu_op__rc__rc$next[0:0]$701 + update \alu_alu0_alu_op__write_cr0$next $0\alu_alu0_alu_op__write_cr0$next[0:0]$702 + update \alu_alu0_alu_op__zero_a$next $0\alu_alu0_alu_op__zero_a$next[0:0]$703 + end + attribute \src "libresoc.v:22231.3-22252.6" + process $proc$libresoc.v:22231$728 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r0__o$next[63:0]$729 $2\data_r0__o$next[63:0]$733 + assign { } { } + assign $0\data_r0__o_ok$next[0:0]$730 $3\data_r0__o_ok$next[0:0]$735 + attribute \src "libresoc.v:22232.5-22232.29" + switch \initial + attribute \src "libresoc.v:22232.9-22232.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r0__o_ok$next[0:0]$732 $1\data_r0__o$next[63:0]$731 } { \o_ok \alu_alu0_o } + case + assign $1\data_r0__o$next[63:0]$731 \data_r0__o + assign $1\data_r0__o_ok$next[0:0]$732 \data_r0__o_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r0__o_ok$next[0:0]$734 $2\data_r0__o$next[63:0]$733 } 65'00000000000000000000000000000000000000000000000000000000000000000 + case + assign $2\data_r0__o$next[63:0]$733 $1\data_r0__o$next[63:0]$731 + assign $2\data_r0__o_ok$next[0:0]$734 $1\data_r0__o_ok$next[0:0]$732 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r0__o_ok$next[0:0]$735 1'0 + case + assign $3\data_r0__o_ok$next[0:0]$735 $2\data_r0__o_ok$next[0:0]$734 + end + sync always + update \data_r0__o$next $0\data_r0__o$next[63:0]$729 + update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$730 + end + attribute \src "libresoc.v:22253.3-22274.6" + process $proc$libresoc.v:22253$736 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r1__cr_a$next[3:0]$737 $2\data_r1__cr_a$next[3:0]$741 + assign { } { } + assign $0\data_r1__cr_a_ok$next[0:0]$738 $3\data_r1__cr_a_ok$next[0:0]$743 + attribute \src "libresoc.v:22254.5-22254.29" + switch \initial + attribute \src "libresoc.v:22254.9-22254.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r1__cr_a_ok$next[0:0]$740 $1\data_r1__cr_a$next[3:0]$739 } { \cr_a_ok \alu_alu0_cr_a } + case + assign $1\data_r1__cr_a$next[3:0]$739 \data_r1__cr_a + assign $1\data_r1__cr_a_ok$next[0:0]$740 \data_r1__cr_a_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r1__cr_a_ok$next[0:0]$742 $2\data_r1__cr_a$next[3:0]$741 } 5'00000 + case + assign $2\data_r1__cr_a$next[3:0]$741 $1\data_r1__cr_a$next[3:0]$739 + assign $2\data_r1__cr_a_ok$next[0:0]$742 $1\data_r1__cr_a_ok$next[0:0]$740 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r1__cr_a_ok$next[0:0]$743 1'0 + case + assign $3\data_r1__cr_a_ok$next[0:0]$743 $2\data_r1__cr_a_ok$next[0:0]$742 + end + sync always + update \data_r1__cr_a$next $0\data_r1__cr_a$next[3:0]$737 + update \data_r1__cr_a_ok$next $0\data_r1__cr_a_ok$next[0:0]$738 + end + attribute \src "libresoc.v:22275.3-22296.6" + process $proc$libresoc.v:22275$744 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r2__xer_ca$next[1:0]$745 $2\data_r2__xer_ca$next[1:0]$749 + assign { } { } + assign $0\data_r2__xer_ca_ok$next[0:0]$746 $3\data_r2__xer_ca_ok$next[0:0]$751 + attribute \src "libresoc.v:22276.5-22276.29" + switch \initial + attribute \src "libresoc.v:22276.9-22276.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r2__xer_ca_ok$next[0:0]$748 $1\data_r2__xer_ca$next[1:0]$747 } { \xer_ca_ok \alu_alu0_xer_ca } + case + assign $1\data_r2__xer_ca$next[1:0]$747 \data_r2__xer_ca + assign $1\data_r2__xer_ca_ok$next[0:0]$748 \data_r2__xer_ca_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r2__xer_ca_ok$next[0:0]$750 $2\data_r2__xer_ca$next[1:0]$749 } 3'000 + case + assign $2\data_r2__xer_ca$next[1:0]$749 $1\data_r2__xer_ca$next[1:0]$747 + assign $2\data_r2__xer_ca_ok$next[0:0]$750 $1\data_r2__xer_ca_ok$next[0:0]$748 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r2__xer_ca_ok$next[0:0]$751 1'0 + case + assign $3\data_r2__xer_ca_ok$next[0:0]$751 $2\data_r2__xer_ca_ok$next[0:0]$750 + end + sync always + update \data_r2__xer_ca$next $0\data_r2__xer_ca$next[1:0]$745 + update \data_r2__xer_ca_ok$next $0\data_r2__xer_ca_ok$next[0:0]$746 + end + attribute \src "libresoc.v:22297.3-22318.6" + process $proc$libresoc.v:22297$752 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r3__xer_ov$next[1:0]$753 $2\data_r3__xer_ov$next[1:0]$757 + assign { } { } + assign $0\data_r3__xer_ov_ok$next[0:0]$754 $3\data_r3__xer_ov_ok$next[0:0]$759 + attribute \src "libresoc.v:22298.5-22298.29" + switch \initial + attribute \src "libresoc.v:22298.9-22298.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r3__xer_ov_ok$next[0:0]$756 $1\data_r3__xer_ov$next[1:0]$755 } { \xer_ov_ok \alu_alu0_xer_ov } + case + assign $1\data_r3__xer_ov$next[1:0]$755 \data_r3__xer_ov + assign $1\data_r3__xer_ov_ok$next[0:0]$756 \data_r3__xer_ov_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r3__xer_ov_ok$next[0:0]$758 $2\data_r3__xer_ov$next[1:0]$757 } 3'000 + case + assign $2\data_r3__xer_ov$next[1:0]$757 $1\data_r3__xer_ov$next[1:0]$755 + assign $2\data_r3__xer_ov_ok$next[0:0]$758 $1\data_r3__xer_ov_ok$next[0:0]$756 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r3__xer_ov_ok$next[0:0]$759 1'0 + case + assign $3\data_r3__xer_ov_ok$next[0:0]$759 $2\data_r3__xer_ov_ok$next[0:0]$758 + end + sync always + update \data_r3__xer_ov$next $0\data_r3__xer_ov$next[1:0]$753 + update \data_r3__xer_ov_ok$next $0\data_r3__xer_ov_ok$next[0:0]$754 + end + attribute \src "libresoc.v:22319.3-22340.6" + process $proc$libresoc.v:22319$760 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r4__xer_so$next[0:0]$761 $2\data_r4__xer_so$next[0:0]$765 + assign { } { } + assign $0\data_r4__xer_so_ok$next[0:0]$762 $3\data_r4__xer_so_ok$next[0:0]$767 + attribute \src "libresoc.v:22320.5-22320.29" + switch \initial + attribute \src "libresoc.v:22320.9-22320.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r4__xer_so_ok$next[0:0]$764 $1\data_r4__xer_so$next[0:0]$763 } { \xer_so_ok \alu_alu0_xer_so } + case + assign $1\data_r4__xer_so$next[0:0]$763 \data_r4__xer_so + assign $1\data_r4__xer_so_ok$next[0:0]$764 \data_r4__xer_so_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r4__xer_so_ok$next[0:0]$766 $2\data_r4__xer_so$next[0:0]$765 } 2'00 + case + assign $2\data_r4__xer_so$next[0:0]$765 $1\data_r4__xer_so$next[0:0]$763 + assign $2\data_r4__xer_so_ok$next[0:0]$766 $1\data_r4__xer_so_ok$next[0:0]$764 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r4__xer_so_ok$next[0:0]$767 1'0 + case + assign $3\data_r4__xer_so_ok$next[0:0]$767 $2\data_r4__xer_so_ok$next[0:0]$766 + end + sync always + update \data_r4__xer_so$next $0\data_r4__xer_so$next[0:0]$761 + update \data_r4__xer_so_ok$next $0\data_r4__xer_so_ok$next[0:0]$762 + end + attribute \src "libresoc.v:22341.3-22350.6" + process $proc$libresoc.v:22341$768 + assign { } { } + assign { } { } + assign $0\src_r0$next[63:0]$769 $1\src_r0$next[63:0]$770 + attribute \src "libresoc.v:22342.5-22342.29" + switch \initial + attribute \src "libresoc.v:22342.9-22342.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" + switch \src_sel + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r0$next[63:0]$770 \src_or_imm + case + assign $1\src_r0$next[63:0]$770 \src_r0 + end + sync always + update \src_r0$next $0\src_r0$next[63:0]$769 + end + attribute \src "libresoc.v:22351.3-22360.6" + process $proc$libresoc.v:22351$771 + assign { } { } + assign { } { } + assign $0\src_r1$next[63:0]$772 $1\src_r1$next[63:0]$773 + attribute \src "libresoc.v:22352.5-22352.29" + switch \initial + attribute \src "libresoc.v:22352.9-22352.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" + switch \src_sel$85 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r1$next[63:0]$773 \src_or_imm$88 + case + assign $1\src_r1$next[63:0]$773 \src_r1 + end + sync always + update \src_r1$next $0\src_r1$next[63:0]$772 + end + attribute \src "libresoc.v:22361.3-22370.6" + process $proc$libresoc.v:22361$774 + assign { } { } + assign { } { } + assign $0\src_r2$next[0:0]$775 $1\src_r2$next[0:0]$776 + attribute \src "libresoc.v:22362.5-22362.29" + switch \initial + attribute \src "libresoc.v:22362.9-22362.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" + switch \src_l_q_src [2] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r2$next[0:0]$776 \src3_i + case + assign $1\src_r2$next[0:0]$776 \src_r2 + end + sync always + update \src_r2$next $0\src_r2$next[0:0]$775 + end + attribute \src "libresoc.v:22371.3-22380.6" + process $proc$libresoc.v:22371$777 + assign { } { } + assign { } { } + assign $0\src_r3$next[1:0]$778 $1\src_r3$next[1:0]$779 + attribute \src "libresoc.v:22372.5-22372.29" + switch \initial + attribute \src "libresoc.v:22372.9-22372.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" + switch \src_l_q_src [3] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign 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attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute 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\enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \alu_op__insn_type$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 17 \alu_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__invert_in$62 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 19 \alu_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__invert_out$64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 23 \alu_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__is_32bit$68 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 24 \alu_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__is_signed$69 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 15 \alu_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__oe__oe$60 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 16 \alu_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__oe__ok$61 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 22 \alu_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__output_carry$67 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \alu_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__rc__ok$59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \alu_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__rc__rc$58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 20 \alu_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__write_cr0$65 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 18 \alu_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__zero_a$63 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 38 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 output 28 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 3 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid$53 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire input 8 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire output 7 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 27 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 2 \o_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" + wire output 37 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" + wire input 36 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \pipe1_alu_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \pipe1_alu_op__data_len$20 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \pipe1_alu_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \pipe1_alu_op__fn_unit$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe1_alu_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe1_alu_op__imm_data__data$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_alu_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_alu_op__imm_data__ok$7 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \pipe1_alu_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \pipe1_alu_op__input_carry$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe1_alu_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe1_alu_op__insn$21 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe1_alu_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe1_alu_op__insn_type$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_alu_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_alu_op__invert_in$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_alu_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_alu_op__invert_out$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_alu_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_alu_op__is_32bit$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_alu_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_alu_op__is_signed$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_alu_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_alu_op__oe__oe$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_alu_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_alu_op__oe__ok$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_alu_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_alu_op__output_carry$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_alu_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_alu_op__rc__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_alu_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_alu_op__rc__rc$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_alu_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_alu_op__write_cr0$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_alu_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_alu_op__zero_a$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \pipe1_cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe1_cr_a_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \pipe1_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \pipe1_muxid$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire \pipe1_n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire \pipe1_n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \pipe1_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe1_o_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" + wire \pipe1_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" + wire \pipe1_p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe1_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe1_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \pipe1_xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 \pipe1_xer_ca$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe1_xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \pipe1_xer_ov + attribute \src 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attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \pipe2_alu_op__fn_unit$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe2_alu_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe2_alu_op__imm_data__data$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_alu_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_alu_op__imm_data__ok$28 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \pipe2_alu_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \pipe2_alu_op__input_carry$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe2_alu_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe2_alu_op__insn$42 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute 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attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute 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\enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe2_alu_op__insn_type$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_alu_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_alu_op__invert_in$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_alu_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_alu_op__invert_out$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_alu_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_alu_op__is_32bit$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_alu_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_alu_op__is_signed$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_alu_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_alu_op__oe__oe$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_alu_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_alu_op__oe__ok$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_alu_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_alu_op__output_carry$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_alu_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_alu_op__rc__ok$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_alu_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_alu_op__rc__rc$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_alu_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_alu_op__write_cr0$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_alu_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_alu_op__zero_a$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \pipe2_cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \pipe2_cr_a$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe2_cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe2_cr_a_ok$46 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \pipe2_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \pipe2_muxid$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire \pipe2_n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire \pipe2_n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \pipe2_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \pipe2_o$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe2_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe2_o_ok$44 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" + wire \pipe2_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" + wire \pipe2_p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \pipe2_xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \pipe2_xer_ca$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe2_xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe2_xer_ca_ok$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \pipe2_xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \pipe2_xer_ov$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe2_xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe2_xer_ov_ok$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe2_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe2_xer_so$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe2_xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe2_xer_so_ok$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 32 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 33 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 output 29 \xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 input 35 \xer_ca$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 4 \xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 output 30 \xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 5 \xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 31 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 34 \xer_so$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 6 \xer_so_ok + attribute \module_not_derived 1 + attribute \src "libresoc.v:23400.5-23403.4" + cell \n \n + connect \n_ready_i \n_ready_i + connect \n_valid_o \n_valid_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:23404.5-23407.4" + cell \p \p + connect \p_ready_o \p_ready_o + connect \p_valid_i \p_valid_i + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:23408.9-23467.4" + cell \pipe1 \pipe1 + connect \alu_op__data_len \pipe1_alu_op__data_len + connect \alu_op__data_len$18 \pipe1_alu_op__data_len$20 + connect \alu_op__fn_unit \pipe1_alu_op__fn_unit + connect \alu_op__fn_unit$3 \pipe1_alu_op__fn_unit$5 + connect \alu_op__imm_data__data \pipe1_alu_op__imm_data__data + connect \alu_op__imm_data__data$4 \pipe1_alu_op__imm_data__data$6 + connect \alu_op__imm_data__ok \pipe1_alu_op__imm_data__ok + connect \alu_op__imm_data__ok$5 \pipe1_alu_op__imm_data__ok$7 + connect \alu_op__input_carry \pipe1_alu_op__input_carry + connect \alu_op__input_carry$14 \pipe1_alu_op__input_carry$16 + connect \alu_op__insn \pipe1_alu_op__insn + connect \alu_op__insn$19 \pipe1_alu_op__insn$21 + connect \alu_op__insn_type \pipe1_alu_op__insn_type + connect \alu_op__insn_type$2 \pipe1_alu_op__insn_type$4 + connect \alu_op__invert_in \pipe1_alu_op__invert_in + connect \alu_op__invert_in$10 \pipe1_alu_op__invert_in$12 + connect \alu_op__invert_out \pipe1_alu_op__invert_out + connect \alu_op__invert_out$12 \pipe1_alu_op__invert_out$14 + connect \alu_op__is_32bit \pipe1_alu_op__is_32bit + connect \alu_op__is_32bit$16 \pipe1_alu_op__is_32bit$18 + connect \alu_op__is_signed \pipe1_alu_op__is_signed + connect \alu_op__is_signed$17 \pipe1_alu_op__is_signed$19 + connect \alu_op__oe__oe \pipe1_alu_op__oe__oe + connect \alu_op__oe__oe$8 \pipe1_alu_op__oe__oe$10 + connect \alu_op__oe__ok \pipe1_alu_op__oe__ok + connect \alu_op__oe__ok$9 \pipe1_alu_op__oe__ok$11 + connect \alu_op__output_carry \pipe1_alu_op__output_carry + connect \alu_op__output_carry$15 \pipe1_alu_op__output_carry$17 + connect \alu_op__rc__ok \pipe1_alu_op__rc__ok + connect \alu_op__rc__ok$7 \pipe1_alu_op__rc__ok$9 + connect \alu_op__rc__rc \pipe1_alu_op__rc__rc + connect \alu_op__rc__rc$6 \pipe1_alu_op__rc__rc$8 + connect \alu_op__write_cr0 \pipe1_alu_op__write_cr0 + connect \alu_op__write_cr0$13 \pipe1_alu_op__write_cr0$15 + connect \alu_op__zero_a \pipe1_alu_op__zero_a + connect \alu_op__zero_a$11 \pipe1_alu_op__zero_a$13 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cr_a \pipe1_cr_a + connect \cr_a_ok \pipe1_cr_a_ok + connect \muxid \pipe1_muxid + connect \muxid$1 \pipe1_muxid$3 + connect \n_ready_i \pipe1_n_ready_i + connect \n_valid_o \pipe1_n_valid_o + connect \o \pipe1_o + connect \o_ok \pipe1_o_ok + connect \p_ready_o \pipe1_p_ready_o + connect \p_valid_i \pipe1_p_valid_i + connect \ra \pipe1_ra + connect \rb \pipe1_rb + connect \xer_ca \pipe1_xer_ca + connect \xer_ca$21 \pipe1_xer_ca$23 + connect \xer_ca_ok \pipe1_xer_ca_ok + connect \xer_ov \pipe1_xer_ov + connect \xer_ov_ok \pipe1_xer_ov_ok + connect \xer_so \pipe1_xer_so + connect \xer_so$20 \pipe1_xer_so$22 + connect \xer_so_ok \pipe1_xer_so_ok + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:23468.9-23533.4" + cell \pipe2 \pipe2 + connect \alu_op__data_len \pipe2_alu_op__data_len + connect \alu_op__data_len$18 \pipe2_alu_op__data_len$41 + connect \alu_op__fn_unit \pipe2_alu_op__fn_unit + connect \alu_op__fn_unit$3 \pipe2_alu_op__fn_unit$26 + connect \alu_op__imm_data__data \pipe2_alu_op__imm_data__data + connect \alu_op__imm_data__data$4 \pipe2_alu_op__imm_data__data$27 + connect \alu_op__imm_data__ok \pipe2_alu_op__imm_data__ok + connect \alu_op__imm_data__ok$5 \pipe2_alu_op__imm_data__ok$28 + connect \alu_op__input_carry \pipe2_alu_op__input_carry + connect \alu_op__input_carry$14 \pipe2_alu_op__input_carry$37 + connect \alu_op__insn \pipe2_alu_op__insn + connect \alu_op__insn$19 \pipe2_alu_op__insn$42 + connect \alu_op__insn_type \pipe2_alu_op__insn_type + connect \alu_op__insn_type$2 \pipe2_alu_op__insn_type$25 + connect \alu_op__invert_in \pipe2_alu_op__invert_in + connect \alu_op__invert_in$10 \pipe2_alu_op__invert_in$33 + connect \alu_op__invert_out \pipe2_alu_op__invert_out + connect \alu_op__invert_out$12 \pipe2_alu_op__invert_out$35 + connect \alu_op__is_32bit \pipe2_alu_op__is_32bit + connect \alu_op__is_32bit$16 \pipe2_alu_op__is_32bit$39 + connect \alu_op__is_signed \pipe2_alu_op__is_signed + connect \alu_op__is_signed$17 \pipe2_alu_op__is_signed$40 + connect \alu_op__oe__oe \pipe2_alu_op__oe__oe + connect \alu_op__oe__oe$8 \pipe2_alu_op__oe__oe$31 + connect \alu_op__oe__ok \pipe2_alu_op__oe__ok + connect \alu_op__oe__ok$9 \pipe2_alu_op__oe__ok$32 + connect \alu_op__output_carry \pipe2_alu_op__output_carry + connect \alu_op__output_carry$15 \pipe2_alu_op__output_carry$38 + connect \alu_op__rc__ok \pipe2_alu_op__rc__ok + connect \alu_op__rc__ok$7 \pipe2_alu_op__rc__ok$30 + connect \alu_op__rc__rc \pipe2_alu_op__rc__rc + connect \alu_op__rc__rc$6 \pipe2_alu_op__rc__rc$29 + connect \alu_op__write_cr0 \pipe2_alu_op__write_cr0 + connect \alu_op__write_cr0$13 \pipe2_alu_op__write_cr0$36 + connect \alu_op__zero_a \pipe2_alu_op__zero_a + connect \alu_op__zero_a$11 \pipe2_alu_op__zero_a$34 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cr_a \pipe2_cr_a + connect \cr_a$22 \pipe2_cr_a$45 + connect \cr_a_ok \pipe2_cr_a_ok + connect \cr_a_ok$23 \pipe2_cr_a_ok$46 + connect \muxid \pipe2_muxid + connect \muxid$1 \pipe2_muxid$24 + connect \n_ready_i \pipe2_n_ready_i + connect \n_valid_o \pipe2_n_valid_o + connect \o \pipe2_o + connect \o$20 \pipe2_o$43 + connect \o_ok \pipe2_o_ok + connect \o_ok$21 \pipe2_o_ok$44 + connect \p_ready_o \pipe2_p_ready_o + connect \p_valid_i \pipe2_p_valid_i + connect \xer_ca \pipe2_xer_ca + connect \xer_ca$24 \pipe2_xer_ca$47 + connect \xer_ca_ok \pipe2_xer_ca_ok + connect \xer_ca_ok$25 \pipe2_xer_ca_ok$48 + connect \xer_ov \pipe2_xer_ov + connect \xer_ov$26 \pipe2_xer_ov$49 + connect \xer_ov_ok \pipe2_xer_ov_ok + connect \xer_ov_ok$27 \pipe2_xer_ov_ok$50 + connect \xer_so \pipe2_xer_so + connect \xer_so$28 \pipe2_xer_so$51 + connect \xer_so_ok \pipe2_xer_so_ok + connect \xer_so_ok$29 \pipe2_xer_so_ok$52 + end + connect \muxid 2'00 + connect { \xer_so_ok \xer_so } { \pipe2_xer_so_ok$52 \pipe2_xer_so$51 } + connect { \xer_ov_ok \xer_ov } { \pipe2_xer_ov_ok$50 \pipe2_xer_ov$49 } + connect { \xer_ca_ok \xer_ca } { \pipe2_xer_ca_ok$48 \pipe2_xer_ca$47 } + connect { \cr_a_ok \cr_a } { \pipe2_cr_a_ok$46 \pipe2_cr_a$45 } + connect { \o_ok \o } { \pipe2_o_ok$44 \pipe2_o$43 } + connect { \alu_op__insn$71 \alu_op__data_len$70 \alu_op__is_signed$69 \alu_op__is_32bit$68 \alu_op__output_carry$67 \alu_op__input_carry$66 \alu_op__write_cr0$65 \alu_op__invert_out$64 \alu_op__zero_a$63 \alu_op__invert_in$62 \alu_op__oe__ok$61 \alu_op__oe__oe$60 \alu_op__rc__ok$59 \alu_op__rc__rc$58 \alu_op__imm_data__ok$57 \alu_op__imm_data__data$56 \alu_op__fn_unit$55 \alu_op__insn_type$54 } { \pipe2_alu_op__insn$42 \pipe2_alu_op__data_len$41 \pipe2_alu_op__is_signed$40 \pipe2_alu_op__is_32bit$39 \pipe2_alu_op__output_carry$38 \pipe2_alu_op__input_carry$37 \pipe2_alu_op__write_cr0$36 \pipe2_alu_op__invert_out$35 \pipe2_alu_op__zero_a$34 \pipe2_alu_op__invert_in$33 \pipe2_alu_op__oe__ok$32 \pipe2_alu_op__oe__oe$31 \pipe2_alu_op__rc__ok$30 \pipe2_alu_op__rc__rc$29 \pipe2_alu_op__imm_data__ok$28 \pipe2_alu_op__imm_data__data$27 \pipe2_alu_op__fn_unit$26 \pipe2_alu_op__insn_type$25 } + connect \muxid$53 \pipe2_muxid$24 + connect \pipe2_n_ready_i \n_ready_i + connect \n_valid_o \pipe2_n_valid_o + connect \pipe1_xer_ca$23 \xer_ca$2 + connect \pipe1_xer_so$22 \xer_so$1 + connect \pipe1_rb \rb + connect \pipe1_ra \ra + connect { \pipe1_alu_op__insn$21 \pipe1_alu_op__data_len$20 \pipe1_alu_op__is_signed$19 \pipe1_alu_op__is_32bit$18 \pipe1_alu_op__output_carry$17 \pipe1_alu_op__input_carry$16 \pipe1_alu_op__write_cr0$15 \pipe1_alu_op__invert_out$14 \pipe1_alu_op__zero_a$13 \pipe1_alu_op__invert_in$12 \pipe1_alu_op__oe__ok$11 \pipe1_alu_op__oe__oe$10 \pipe1_alu_op__rc__ok$9 \pipe1_alu_op__rc__rc$8 \pipe1_alu_op__imm_data__ok$7 \pipe1_alu_op__imm_data__data$6 \pipe1_alu_op__fn_unit$5 \pipe1_alu_op__insn_type$4 } { \alu_op__insn \alu_op__data_len \alu_op__is_signed \alu_op__is_32bit \alu_op__output_carry \alu_op__input_carry \alu_op__write_cr0 \alu_op__invert_out \alu_op__zero_a \alu_op__invert_in \alu_op__oe__ok \alu_op__oe__oe \alu_op__rc__ok \alu_op__rc__rc \alu_op__imm_data__ok \alu_op__imm_data__data \alu_op__fn_unit \alu_op__insn_type } + connect \pipe1_muxid$3 2'00 + connect \p_ready_o \pipe1_p_ready_o + connect \pipe1_p_valid_i \p_valid_i + connect { \pipe2_xer_so_ok \pipe2_xer_so } { \pipe1_xer_so_ok \pipe1_xer_so } + connect { \pipe2_xer_ov_ok \pipe2_xer_ov } { \pipe1_xer_ov_ok \pipe1_xer_ov } + connect { \pipe2_xer_ca_ok \pipe2_xer_ca } { \pipe1_xer_ca_ok \pipe1_xer_ca } + connect { \pipe2_cr_a_ok \pipe2_cr_a } { \pipe1_cr_a_ok \pipe1_cr_a } + connect { \pipe2_o_ok \pipe2_o } { \pipe1_o_ok \pipe1_o } + connect { \pipe2_alu_op__insn \pipe2_alu_op__data_len \pipe2_alu_op__is_signed \pipe2_alu_op__is_32bit \pipe2_alu_op__output_carry \pipe2_alu_op__input_carry \pipe2_alu_op__write_cr0 \pipe2_alu_op__invert_out \pipe2_alu_op__zero_a \pipe2_alu_op__invert_in \pipe2_alu_op__oe__ok \pipe2_alu_op__oe__oe \pipe2_alu_op__rc__ok \pipe2_alu_op__rc__rc \pipe2_alu_op__imm_data__ok \pipe2_alu_op__imm_data__data \pipe2_alu_op__fn_unit \pipe2_alu_op__insn_type } { \pipe1_alu_op__insn \pipe1_alu_op__data_len \pipe1_alu_op__is_signed \pipe1_alu_op__is_32bit \pipe1_alu_op__output_carry \pipe1_alu_op__input_carry \pipe1_alu_op__write_cr0 \pipe1_alu_op__invert_out \pipe1_alu_op__zero_a \pipe1_alu_op__invert_in \pipe1_alu_op__oe__ok \pipe1_alu_op__oe__oe \pipe1_alu_op__rc__ok \pipe1_alu_op__rc__rc \pipe1_alu_op__imm_data__ok \pipe1_alu_op__imm_data__data \pipe1_alu_op__fn_unit \pipe1_alu_op__insn_type } + connect \pipe2_muxid \pipe1_muxid + connect \pipe1_n_ready_i \pipe2_p_ready_o + connect \pipe2_p_valid_i \pipe1_n_valid_o +end +attribute \src "libresoc.v:23565.1-24104.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.alu_branch0" +attribute \generator "nMigen" +module \alu_branch0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 7 \br_op__cia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \br_op__cia$15 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 input 9 \br_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \br_op__fn_unit$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 11 \br_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \br_op__imm_data__data$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \br_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \br_op__imm_data__ok$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 10 \br_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \br_op__insn$18 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 8 \br_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \br_op__insn_type$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \br_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \br_op__is_32bit$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \br_op__lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \br_op__lk$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 23 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 4 input 20 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 15 \fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 18 \fast1$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 2 \fast1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 16 \fast2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 19 \fast2$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 3 \fast2_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid$14 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire input 6 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire output 5 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 17 \nia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 4 \nia_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" + wire output 22 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" + wire input 21 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe_br_op__cia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe_br_op__cia$4 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \pipe_br_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \pipe_br_op__fn_unit$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe_br_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe_br_op__imm_data__data$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_br_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_br_op__imm_data__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe_br_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe_br_op__insn$7 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe_br_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe_br_op__insn_type$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_br_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_br_op__is_32bit$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_br_op__lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_br_op__lk$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 4 \pipe_cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \pipe_fast1$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe_fast1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_fast2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \pipe_fast2$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe_fast2_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \pipe_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \pipe_muxid$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire \pipe_n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire \pipe_n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \pipe_nia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe_nia_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" + wire \pipe_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" + wire \pipe_p_valid_i + attribute \module_not_derived 1 + attribute \src "libresoc.v:24046.10-24049.4" + cell \n$18 \n + connect \n_ready_i \n_ready_i + connect \n_valid_o \n_valid_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:24050.10-24053.4" + cell \p$17 \p + connect \p_ready_o \p_ready_o + connect \p_valid_i \p_valid_i + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:24054.13-24088.4" + cell \pipe$19 \pipe + connect \br_op__cia \pipe_br_op__cia + connect \br_op__cia$2 \pipe_br_op__cia$4 + connect \br_op__fn_unit \pipe_br_op__fn_unit + connect \br_op__fn_unit$4 \pipe_br_op__fn_unit$6 + connect \br_op__imm_data__data \pipe_br_op__imm_data__data + connect \br_op__imm_data__data$6 \pipe_br_op__imm_data__data$8 + connect \br_op__imm_data__ok \pipe_br_op__imm_data__ok + connect \br_op__imm_data__ok$7 \pipe_br_op__imm_data__ok$9 + connect \br_op__insn \pipe_br_op__insn + connect \br_op__insn$5 \pipe_br_op__insn$7 + connect \br_op__insn_type \pipe_br_op__insn_type + connect \br_op__insn_type$3 \pipe_br_op__insn_type$5 + connect \br_op__is_32bit \pipe_br_op__is_32bit + connect \br_op__is_32bit$9 \pipe_br_op__is_32bit$11 + connect \br_op__lk \pipe_br_op__lk + connect \br_op__lk$8 \pipe_br_op__lk$10 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cr_a \pipe_cr_a + connect \fast1 \pipe_fast1 + connect \fast1$10 \pipe_fast1$12 + connect \fast1_ok \pipe_fast1_ok + connect \fast2 \pipe_fast2 + connect \fast2$11 \pipe_fast2$13 + connect \fast2_ok \pipe_fast2_ok + connect \muxid \pipe_muxid + connect \muxid$1 \pipe_muxid$3 + connect \n_ready_i \pipe_n_ready_i + connect \n_valid_o \pipe_n_valid_o + connect \nia \pipe_nia + connect \nia_ok \pipe_nia_ok + connect \p_ready_o \pipe_p_ready_o + connect \p_valid_i \pipe_p_valid_i + end + connect \muxid 2'00 + connect { \nia_ok \nia } { \pipe_nia_ok \pipe_nia } + connect { \fast2_ok \fast2 } { \pipe_fast2_ok \pipe_fast2$13 } + connect { \fast1_ok \fast1 } { \pipe_fast1_ok \pipe_fast1$12 } + connect { \br_op__is_32bit$22 \br_op__lk$21 \br_op__imm_data__ok$20 \br_op__imm_data__data$19 \br_op__insn$18 \br_op__fn_unit$17 \br_op__insn_type$16 \br_op__cia$15 } { \pipe_br_op__is_32bit$11 \pipe_br_op__lk$10 \pipe_br_op__imm_data__ok$9 \pipe_br_op__imm_data__data$8 \pipe_br_op__insn$7 \pipe_br_op__fn_unit$6 \pipe_br_op__insn_type$5 \pipe_br_op__cia$4 } + connect \muxid$14 \pipe_muxid$3 + connect \pipe_n_ready_i \n_ready_i + connect \n_valid_o \pipe_n_valid_o + connect \pipe_cr_a \cr_a + connect \pipe_fast2 \fast2$2 + connect \pipe_fast1 \fast1$1 + connect { \pipe_br_op__is_32bit \pipe_br_op__lk \pipe_br_op__imm_data__ok \pipe_br_op__imm_data__data \pipe_br_op__insn \pipe_br_op__fn_unit \pipe_br_op__insn_type \pipe_br_op__cia } { \br_op__is_32bit \br_op__lk \br_op__imm_data__ok \br_op__imm_data__data \br_op__insn \br_op__fn_unit \br_op__insn_type \br_op__cia } + connect \pipe_muxid 2'00 + connect \p_ready_o \pipe_p_ready_o + connect \pipe_p_valid_i \p_valid_i +end +attribute \src "libresoc.v:24108.1-24615.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.alu_cr0" +attribute \generator "nMigen" +module \alu_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 21 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 output 12 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 4 input 16 \cr_a$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 4 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 4 input 17 \cr_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 4 input 18 \cr_c + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 input 8 \cr_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \cr_op__fn_unit$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 9 \cr_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \cr_op__insn$12 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 7 \cr_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \cr_op__insn_type$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 32 output 11 \full_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 32 input 15 \full_cr$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 3 \full_cr_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid$9 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire input 6 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire output 5 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 10 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 2 \o_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" + wire output 20 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" + wire input 19 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 4 \pipe_cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \pipe_cr_a$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe_cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 4 \pipe_cr_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 4 \pipe_cr_c + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \pipe_cr_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \pipe_cr_op__fn_unit$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe_cr_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe_cr_op__insn$6 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe_cr_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe_cr_op__insn_type$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 32 \pipe_full_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 32 \pipe_full_cr$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe_full_cr_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \pipe_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \pipe_muxid$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire \pipe_n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire \pipe_n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \pipe_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe_o_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" + wire \pipe_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" + wire \pipe_p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 13 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 14 \rb + attribute \module_not_derived 1 + attribute \src "libresoc.v:24561.9-24564.4" + cell \n$6 \n + connect \n_ready_i \n_ready_i + connect \n_valid_o \n_valid_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:24565.9-24568.4" + cell \p$5 \p + connect \p_ready_o \p_ready_o + connect \p_valid_i \p_valid_i + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:24569.8-24596.4" + cell \pipe \pipe + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cr_a \pipe_cr_a + connect \cr_a$6 \pipe_cr_a$8 + connect \cr_a_ok \pipe_cr_a_ok + connect \cr_b \pipe_cr_b + connect \cr_c \pipe_cr_c + connect \cr_op__fn_unit \pipe_cr_op__fn_unit + connect \cr_op__fn_unit$3 \pipe_cr_op__fn_unit$5 + connect \cr_op__insn \pipe_cr_op__insn + connect \cr_op__insn$4 \pipe_cr_op__insn$6 + connect \cr_op__insn_type \pipe_cr_op__insn_type + connect \cr_op__insn_type$2 \pipe_cr_op__insn_type$4 + connect \full_cr \pipe_full_cr + connect \full_cr$5 \pipe_full_cr$7 + connect \full_cr_ok \pipe_full_cr_ok + connect \muxid \pipe_muxid + connect \muxid$1 \pipe_muxid$3 + connect \n_ready_i \pipe_n_ready_i + connect \n_valid_o \pipe_n_valid_o + connect \o \pipe_o + connect \o_ok \pipe_o_ok + connect \p_ready_o \pipe_p_ready_o + connect \p_valid_i \pipe_p_valid_i + connect \ra \pipe_ra + connect \rb \pipe_rb + end + connect \muxid 2'00 + connect { \cr_a_ok \cr_a } { \pipe_cr_a_ok \pipe_cr_a$8 } + connect { \full_cr_ok \full_cr } { \pipe_full_cr_ok \pipe_full_cr$7 } + connect { \o_ok \o } { \pipe_o_ok \pipe_o } + connect { \cr_op__insn$12 \cr_op__fn_unit$11 \cr_op__insn_type$10 } { \pipe_cr_op__insn$6 \pipe_cr_op__fn_unit$5 \pipe_cr_op__insn_type$4 } + connect \muxid$9 \pipe_muxid$3 + connect \pipe_n_ready_i \n_ready_i + connect \n_valid_o \pipe_n_valid_o + connect \pipe_cr_c \cr_c + connect \pipe_cr_b \cr_b + connect \pipe_cr_a \cr_a$2 + connect \pipe_full_cr \full_cr$1 + connect \pipe_rb \rb + connect \pipe_ra \ra + connect { \pipe_cr_op__insn \pipe_cr_op__fn_unit \pipe_cr_op__insn_type } { \cr_op__insn \cr_op__fn_unit \cr_op__insn_type } + connect \pipe_muxid 2'00 + connect \p_ready_o \pipe_p_ready_o + connect \pipe_p_valid_i \p_valid_i +end +attribute \src "libresoc.v:24619.1-26068.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0" +attribute \generator "nMigen" +module \alu_div0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 35 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 output 27 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 3 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 24 \logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \logical_op__data_len$88 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 input 9 \logical_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \logical_op__fn_unit$73 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 10 \logical_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \logical_op__imm_data__data$74 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 11 \logical_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__imm_data__ok$75 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 18 \logical_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \logical_op__input_carry$82 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 25 \logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \logical_op__insn$89 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 8 \logical_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \logical_op__insn_type$72 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 16 \logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_in$80 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 19 \logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_out$83 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 22 \logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_32bit$86 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 23 \logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_signed$87 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__oe$78 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 15 \logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__ok$79 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 21 \logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__output_carry$85 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__ok$77 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__rc$76 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 20 \logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__write_cr0$84 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 17 \logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__zero_a$81 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid$71 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire input 7 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire output 6 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 26 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 2 \o_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" + wire output 34 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" + wire input 33 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \pipe_end_cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe_end_cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire \pipe_end_div_by_zero + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire \pipe_end_dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire \pipe_end_dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire \pipe_end_dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire \pipe_end_divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \pipe_end_logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \pipe_end_logical_op__data_len$68 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \pipe_end_logical_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \pipe_end_logical_op__fn_unit$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe_end_logical_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe_end_logical_op__imm_data__data$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_end_logical_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_end_logical_op__imm_data__ok$55 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \pipe_end_logical_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \pipe_end_logical_op__input_carry$62 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe_end_logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe_end_logical_op__insn$69 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe_end_logical_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe_end_logical_op__insn_type$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_end_logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_end_logical_op__invert_in$60 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_end_logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_end_logical_op__invert_out$63 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_end_logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_end_logical_op__is_32bit$66 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_end_logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_end_logical_op__is_signed$67 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_end_logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_end_logical_op__oe__oe$58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_end_logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_end_logical_op__oe__ok$59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_end_logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_end_logical_op__output_carry$65 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_end_logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_end_logical_op__rc__ok$57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_end_logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_end_logical_op__rc__rc$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_end_logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_end_logical_op__write_cr0$64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_end_logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_end_logical_op__zero_a$61 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \pipe_end_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \pipe_end_muxid$51 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire \pipe_end_n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire \pipe_end_n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \pipe_end_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe_end_o_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" + wire \pipe_end_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" + wire \pipe_end_p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40" + wire width 64 \pipe_end_quotient_root + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_end_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_end_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:41" + wire width 192 \pipe_end_remainder + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \pipe_end_xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe_end_xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \pipe_end_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe_end_xer_so$70 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe_end_xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire \pipe_middle_0_div_by_zero + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire \pipe_middle_0_div_by_zero$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire \pipe_middle_0_dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire \pipe_middle_0_dive_abs_ov32$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire \pipe_middle_0_dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire \pipe_middle_0_dive_abs_ov64$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" + wire width 128 \pipe_middle_0_dividend + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire \pipe_middle_0_dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire \pipe_middle_0_dividend_neg$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire \pipe_middle_0_divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire \pipe_middle_0_divisor_neg$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" + wire width 64 \pipe_middle_0_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \pipe_middle_0_logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \pipe_middle_0_logical_op__data_len$41 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \pipe_middle_0_logical_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \pipe_middle_0_logical_op__fn_unit$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe_middle_0_logical_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe_middle_0_logical_op__imm_data__data$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_middle_0_logical_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_middle_0_logical_op__imm_data__ok$28 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \pipe_middle_0_logical_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \pipe_middle_0_logical_op__input_carry$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe_middle_0_logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe_middle_0_logical_op__insn$42 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe_middle_0_logical_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe_middle_0_logical_op__insn_type$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_middle_0_logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_middle_0_logical_op__invert_in$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_middle_0_logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_middle_0_logical_op__invert_out$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_middle_0_logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_middle_0_logical_op__is_32bit$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_middle_0_logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_middle_0_logical_op__is_signed$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_middle_0_logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_middle_0_logical_op__oe__oe$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_middle_0_logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_middle_0_logical_op__oe__ok$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_middle_0_logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_middle_0_logical_op__output_carry$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_middle_0_logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_middle_0_logical_op__rc__ok$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_middle_0_logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_middle_0_logical_op__rc__rc$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_middle_0_logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_middle_0_logical_op__write_cr0$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_middle_0_logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_middle_0_logical_op__zero_a$34 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \pipe_middle_0_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \pipe_middle_0_muxid$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire \pipe_middle_0_n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire \pipe_middle_0_n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" + wire width 2 \pipe_middle_0_operation + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" + wire \pipe_middle_0_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" + wire \pipe_middle_0_p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40" + wire width 64 \pipe_middle_0_quotient_root + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_middle_0_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_middle_0_ra$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_middle_0_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_middle_0_rb$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:41" + wire width 192 \pipe_middle_0_remainder + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \pipe_middle_0_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \pipe_middle_0_xer_so$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire \pipe_start_div_by_zero + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire \pipe_start_dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire \pipe_start_dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" + wire width 128 \pipe_start_dividend + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire \pipe_start_dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire \pipe_start_divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" + wire width 64 \pipe_start_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \pipe_start_logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \pipe_start_logical_op__data_len$19 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \pipe_start_logical_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \pipe_start_logical_op__fn_unit$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe_start_logical_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe_start_logical_op__imm_data__data$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_start_logical_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_start_logical_op__imm_data__ok$6 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \pipe_start_logical_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \pipe_start_logical_op__input_carry$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe_start_logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe_start_logical_op__insn$20 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe_start_logical_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe_start_logical_op__insn_type$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_start_logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_start_logical_op__invert_in$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_start_logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_start_logical_op__invert_out$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_start_logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_start_logical_op__is_32bit$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_start_logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_start_logical_op__is_signed$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_start_logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_start_logical_op__oe__oe$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_start_logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_start_logical_op__oe__ok$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_start_logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_start_logical_op__output_carry$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_start_logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_start_logical_op__rc__ok$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_start_logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_start_logical_op__rc__rc$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_start_logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_start_logical_op__write_cr0$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_start_logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_start_logical_op__zero_a$12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \pipe_start_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \pipe_start_muxid$2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire \pipe_start_n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire \pipe_start_n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" + wire width 2 \pipe_start_operation + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" + wire \pipe_start_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" + wire \pipe_start_p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_start_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_start_ra$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_start_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_start_rb$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \pipe_start_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \pipe_start_xer_so$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 30 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 31 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 output 28 \xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 4 \xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 29 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 32 \xer_so$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 5 \xer_so_ok + attribute \module_not_derived 1 + attribute \src "libresoc.v:25824.10-25827.4" + cell \n$75 \n + connect \n_ready_i \n_ready_i + connect \n_valid_o \n_valid_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:25828.10-25831.4" + cell \p$74 \p + connect \p_ready_o \p_ready_o + connect \p_valid_i \p_valid_i + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:25832.12-25895.4" + cell \pipe_end \pipe_end + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cr_a \pipe_end_cr_a + connect \cr_a_ok \pipe_end_cr_a_ok + connect \div_by_zero \pipe_end_div_by_zero + connect \dive_abs_ov32 \pipe_end_dive_abs_ov32 + connect \dive_abs_ov64 \pipe_end_dive_abs_ov64 + connect \dividend_neg \pipe_end_dividend_neg + connect \divisor_neg \pipe_end_divisor_neg + connect \logical_op__data_len \pipe_end_logical_op__data_len + connect \logical_op__data_len$18 \pipe_end_logical_op__data_len$68 + connect \logical_op__fn_unit \pipe_end_logical_op__fn_unit + connect \logical_op__fn_unit$3 \pipe_end_logical_op__fn_unit$53 + connect \logical_op__imm_data__data \pipe_end_logical_op__imm_data__data + connect \logical_op__imm_data__data$4 \pipe_end_logical_op__imm_data__data$54 + connect \logical_op__imm_data__ok \pipe_end_logical_op__imm_data__ok + connect \logical_op__imm_data__ok$5 \pipe_end_logical_op__imm_data__ok$55 + connect \logical_op__input_carry \pipe_end_logical_op__input_carry + connect \logical_op__input_carry$12 \pipe_end_logical_op__input_carry$62 + connect \logical_op__insn \pipe_end_logical_op__insn + connect \logical_op__insn$19 \pipe_end_logical_op__insn$69 + connect \logical_op__insn_type \pipe_end_logical_op__insn_type + connect \logical_op__insn_type$2 \pipe_end_logical_op__insn_type$52 + connect \logical_op__invert_in \pipe_end_logical_op__invert_in + connect \logical_op__invert_in$10 \pipe_end_logical_op__invert_in$60 + connect \logical_op__invert_out \pipe_end_logical_op__invert_out + connect \logical_op__invert_out$13 \pipe_end_logical_op__invert_out$63 + connect \logical_op__is_32bit \pipe_end_logical_op__is_32bit + connect \logical_op__is_32bit$16 \pipe_end_logical_op__is_32bit$66 + connect \logical_op__is_signed \pipe_end_logical_op__is_signed + connect \logical_op__is_signed$17 \pipe_end_logical_op__is_signed$67 + connect \logical_op__oe__oe \pipe_end_logical_op__oe__oe + connect \logical_op__oe__oe$8 \pipe_end_logical_op__oe__oe$58 + connect \logical_op__oe__ok \pipe_end_logical_op__oe__ok + connect \logical_op__oe__ok$9 \pipe_end_logical_op__oe__ok$59 + connect \logical_op__output_carry \pipe_end_logical_op__output_carry + connect \logical_op__output_carry$15 \pipe_end_logical_op__output_carry$65 + connect \logical_op__rc__ok \pipe_end_logical_op__rc__ok + connect \logical_op__rc__ok$7 \pipe_end_logical_op__rc__ok$57 + connect \logical_op__rc__rc \pipe_end_logical_op__rc__rc + connect \logical_op__rc__rc$6 \pipe_end_logical_op__rc__rc$56 + connect \logical_op__write_cr0 \pipe_end_logical_op__write_cr0 + connect \logical_op__write_cr0$14 \pipe_end_logical_op__write_cr0$64 + connect \logical_op__zero_a \pipe_end_logical_op__zero_a + connect \logical_op__zero_a$11 \pipe_end_logical_op__zero_a$61 + connect \muxid \pipe_end_muxid + connect \muxid$1 \pipe_end_muxid$51 + connect \n_ready_i \pipe_end_n_ready_i + connect \n_valid_o \pipe_end_n_valid_o + connect \o \pipe_end_o + connect \o_ok \pipe_end_o_ok + connect \p_ready_o \pipe_end_p_ready_o + connect \p_valid_i \pipe_end_p_valid_i + connect \quotient_root \pipe_end_quotient_root + connect \ra \pipe_end_ra + connect \rb \pipe_end_rb + connect \remainder \pipe_end_remainder + connect \xer_ov \pipe_end_xer_ov + connect \xer_ov_ok \pipe_end_xer_ov_ok + connect \xer_so \pipe_end_xer_so + connect \xer_so$20 \pipe_end_xer_so$70 + connect \xer_so_ok \pipe_end_xer_so_ok + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:25896.17-25962.4" + cell \pipe_middle_0 \pipe_middle_0 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \div_by_zero \pipe_middle_0_div_by_zero + connect \div_by_zero$27 \pipe_middle_0_div_by_zero$50 + connect \dive_abs_ov32 \pipe_middle_0_dive_abs_ov32 + connect \dive_abs_ov32$25 \pipe_middle_0_dive_abs_ov32$48 + connect \dive_abs_ov64 \pipe_middle_0_dive_abs_ov64 + connect \dive_abs_ov64$26 \pipe_middle_0_dive_abs_ov64$49 + connect \dividend \pipe_middle_0_dividend + connect \dividend_neg \pipe_middle_0_dividend_neg + connect \dividend_neg$24 \pipe_middle_0_dividend_neg$47 + connect \divisor_neg \pipe_middle_0_divisor_neg + connect \divisor_neg$23 \pipe_middle_0_divisor_neg$46 + connect \divisor_radicand \pipe_middle_0_divisor_radicand + connect \logical_op__data_len \pipe_middle_0_logical_op__data_len + connect \logical_op__data_len$18 \pipe_middle_0_logical_op__data_len$41 + connect \logical_op__fn_unit \pipe_middle_0_logical_op__fn_unit + connect \logical_op__fn_unit$3 \pipe_middle_0_logical_op__fn_unit$26 + connect \logical_op__imm_data__data \pipe_middle_0_logical_op__imm_data__data + connect \logical_op__imm_data__data$4 \pipe_middle_0_logical_op__imm_data__data$27 + connect \logical_op__imm_data__ok \pipe_middle_0_logical_op__imm_data__ok + connect \logical_op__imm_data__ok$5 \pipe_middle_0_logical_op__imm_data__ok$28 + connect \logical_op__input_carry \pipe_middle_0_logical_op__input_carry + connect \logical_op__input_carry$12 \pipe_middle_0_logical_op__input_carry$35 + connect \logical_op__insn \pipe_middle_0_logical_op__insn + connect \logical_op__insn$19 \pipe_middle_0_logical_op__insn$42 + connect \logical_op__insn_type \pipe_middle_0_logical_op__insn_type + connect \logical_op__insn_type$2 \pipe_middle_0_logical_op__insn_type$25 + connect \logical_op__invert_in \pipe_middle_0_logical_op__invert_in + connect \logical_op__invert_in$10 \pipe_middle_0_logical_op__invert_in$33 + connect \logical_op__invert_out \pipe_middle_0_logical_op__invert_out + connect \logical_op__invert_out$13 \pipe_middle_0_logical_op__invert_out$36 + connect \logical_op__is_32bit \pipe_middle_0_logical_op__is_32bit + connect \logical_op__is_32bit$16 \pipe_middle_0_logical_op__is_32bit$39 + connect \logical_op__is_signed \pipe_middle_0_logical_op__is_signed + connect \logical_op__is_signed$17 \pipe_middle_0_logical_op__is_signed$40 + connect \logical_op__oe__oe \pipe_middle_0_logical_op__oe__oe + connect \logical_op__oe__oe$8 \pipe_middle_0_logical_op__oe__oe$31 + connect \logical_op__oe__ok \pipe_middle_0_logical_op__oe__ok + connect \logical_op__oe__ok$9 \pipe_middle_0_logical_op__oe__ok$32 + connect \logical_op__output_carry \pipe_middle_0_logical_op__output_carry + connect \logical_op__output_carry$15 \pipe_middle_0_logical_op__output_carry$38 + connect \logical_op__rc__ok \pipe_middle_0_logical_op__rc__ok + connect \logical_op__rc__ok$7 \pipe_middle_0_logical_op__rc__ok$30 + connect \logical_op__rc__rc \pipe_middle_0_logical_op__rc__rc + connect \logical_op__rc__rc$6 \pipe_middle_0_logical_op__rc__rc$29 + connect \logical_op__write_cr0 \pipe_middle_0_logical_op__write_cr0 + connect \logical_op__write_cr0$14 \pipe_middle_0_logical_op__write_cr0$37 + connect \logical_op__zero_a \pipe_middle_0_logical_op__zero_a + connect \logical_op__zero_a$11 \pipe_middle_0_logical_op__zero_a$34 + connect \muxid \pipe_middle_0_muxid + connect \muxid$1 \pipe_middle_0_muxid$24 + connect \n_ready_i \pipe_middle_0_n_ready_i + connect \n_valid_o \pipe_middle_0_n_valid_o + connect \operation \pipe_middle_0_operation + connect \p_ready_o \pipe_middle_0_p_ready_o + connect \p_valid_i \pipe_middle_0_p_valid_i + connect \quotient_root \pipe_middle_0_quotient_root + connect \ra \pipe_middle_0_ra + connect \ra$20 \pipe_middle_0_ra$43 + connect \rb \pipe_middle_0_rb + connect \rb$21 \pipe_middle_0_rb$44 + connect \remainder \pipe_middle_0_remainder + connect \xer_so \pipe_middle_0_xer_so + connect \xer_so$22 \pipe_middle_0_xer_so$45 + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:25963.14-26022.4" + cell \pipe_start \pipe_start + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \div_by_zero \pipe_start_div_by_zero + connect \dive_abs_ov32 \pipe_start_dive_abs_ov32 + connect \dive_abs_ov64 \pipe_start_dive_abs_ov64 + connect \dividend \pipe_start_dividend + connect \dividend_neg \pipe_start_dividend_neg + connect \divisor_neg \pipe_start_divisor_neg + connect \divisor_radicand \pipe_start_divisor_radicand + connect \logical_op__data_len \pipe_start_logical_op__data_len + connect \logical_op__data_len$18 \pipe_start_logical_op__data_len$19 + connect \logical_op__fn_unit \pipe_start_logical_op__fn_unit + connect \logical_op__fn_unit$3 \pipe_start_logical_op__fn_unit$4 + connect \logical_op__imm_data__data \pipe_start_logical_op__imm_data__data + connect \logical_op__imm_data__data$4 \pipe_start_logical_op__imm_data__data$5 + connect \logical_op__imm_data__ok \pipe_start_logical_op__imm_data__ok + connect \logical_op__imm_data__ok$5 \pipe_start_logical_op__imm_data__ok$6 + connect \logical_op__input_carry \pipe_start_logical_op__input_carry + connect \logical_op__input_carry$12 \pipe_start_logical_op__input_carry$13 + connect \logical_op__insn \pipe_start_logical_op__insn + connect \logical_op__insn$19 \pipe_start_logical_op__insn$20 + connect \logical_op__insn_type \pipe_start_logical_op__insn_type + connect \logical_op__insn_type$2 \pipe_start_logical_op__insn_type$3 + connect \logical_op__invert_in \pipe_start_logical_op__invert_in + connect \logical_op__invert_in$10 \pipe_start_logical_op__invert_in$11 + connect \logical_op__invert_out \pipe_start_logical_op__invert_out + connect \logical_op__invert_out$13 \pipe_start_logical_op__invert_out$14 + connect \logical_op__is_32bit \pipe_start_logical_op__is_32bit + connect \logical_op__is_32bit$16 \pipe_start_logical_op__is_32bit$17 + connect \logical_op__is_signed \pipe_start_logical_op__is_signed + connect \logical_op__is_signed$17 \pipe_start_logical_op__is_signed$18 + connect \logical_op__oe__oe \pipe_start_logical_op__oe__oe + connect \logical_op__oe__oe$8 \pipe_start_logical_op__oe__oe$9 + connect \logical_op__oe__ok \pipe_start_logical_op__oe__ok + connect \logical_op__oe__ok$9 \pipe_start_logical_op__oe__ok$10 + connect \logical_op__output_carry \pipe_start_logical_op__output_carry + connect \logical_op__output_carry$15 \pipe_start_logical_op__output_carry$16 + connect \logical_op__rc__ok \pipe_start_logical_op__rc__ok + connect \logical_op__rc__ok$7 \pipe_start_logical_op__rc__ok$8 + connect \logical_op__rc__rc \pipe_start_logical_op__rc__rc + connect \logical_op__rc__rc$6 \pipe_start_logical_op__rc__rc$7 + connect \logical_op__write_cr0 \pipe_start_logical_op__write_cr0 + connect \logical_op__write_cr0$14 \pipe_start_logical_op__write_cr0$15 + connect \logical_op__zero_a \pipe_start_logical_op__zero_a + connect \logical_op__zero_a$11 \pipe_start_logical_op__zero_a$12 + connect \muxid \pipe_start_muxid + connect \muxid$1 \pipe_start_muxid$2 + connect \n_ready_i \pipe_start_n_ready_i + connect \n_valid_o \pipe_start_n_valid_o + connect \operation \pipe_start_operation + connect \p_ready_o \pipe_start_p_ready_o + connect \p_valid_i \pipe_start_p_valid_i + connect \ra \pipe_start_ra + connect \ra$20 \pipe_start_ra$21 + connect \rb \pipe_start_rb + connect \rb$21 \pipe_start_rb$22 + connect \xer_so \pipe_start_xer_so + connect \xer_so$22 \pipe_start_xer_so$23 + end + connect \muxid 2'00 + connect { \xer_so_ok \xer_so } { \pipe_end_xer_so_ok \pipe_end_xer_so$70 } + connect { \xer_ov_ok \xer_ov } { \pipe_end_xer_ov_ok \pipe_end_xer_ov } + connect { \cr_a_ok \cr_a } { \pipe_end_cr_a_ok \pipe_end_cr_a } + connect { \o_ok \o } { \pipe_end_o_ok \pipe_end_o } + connect { \logical_op__insn$89 \logical_op__data_len$88 \logical_op__is_signed$87 \logical_op__is_32bit$86 \logical_op__output_carry$85 \logical_op__write_cr0$84 \logical_op__invert_out$83 \logical_op__input_carry$82 \logical_op__zero_a$81 \logical_op__invert_in$80 \logical_op__oe__ok$79 \logical_op__oe__oe$78 \logical_op__rc__ok$77 \logical_op__rc__rc$76 \logical_op__imm_data__ok$75 \logical_op__imm_data__data$74 \logical_op__fn_unit$73 \logical_op__insn_type$72 } { \pipe_end_logical_op__insn$69 \pipe_end_logical_op__data_len$68 \pipe_end_logical_op__is_signed$67 \pipe_end_logical_op__is_32bit$66 \pipe_end_logical_op__output_carry$65 \pipe_end_logical_op__write_cr0$64 \pipe_end_logical_op__invert_out$63 \pipe_end_logical_op__input_carry$62 \pipe_end_logical_op__zero_a$61 \pipe_end_logical_op__invert_in$60 \pipe_end_logical_op__oe__ok$59 \pipe_end_logical_op__oe__oe$58 \pipe_end_logical_op__rc__ok$57 \pipe_end_logical_op__rc__rc$56 \pipe_end_logical_op__imm_data__ok$55 \pipe_end_logical_op__imm_data__data$54 \pipe_end_logical_op__fn_unit$53 \pipe_end_logical_op__insn_type$52 } + connect \muxid$71 \pipe_end_muxid$51 + connect \pipe_end_n_ready_i \n_ready_i + connect \n_valid_o \pipe_end_n_valid_o + connect \pipe_start_xer_so$23 \xer_so$1 + connect \pipe_start_rb$22 \rb + connect \pipe_start_ra$21 \ra + connect { \pipe_start_logical_op__insn$20 \pipe_start_logical_op__data_len$19 \pipe_start_logical_op__is_signed$18 \pipe_start_logical_op__is_32bit$17 \pipe_start_logical_op__output_carry$16 \pipe_start_logical_op__write_cr0$15 \pipe_start_logical_op__invert_out$14 \pipe_start_logical_op__input_carry$13 \pipe_start_logical_op__zero_a$12 \pipe_start_logical_op__invert_in$11 \pipe_start_logical_op__oe__ok$10 \pipe_start_logical_op__oe__oe$9 \pipe_start_logical_op__rc__ok$8 \pipe_start_logical_op__rc__rc$7 \pipe_start_logical_op__imm_data__ok$6 \pipe_start_logical_op__imm_data__data$5 \pipe_start_logical_op__fn_unit$4 \pipe_start_logical_op__insn_type$3 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } + connect \pipe_start_muxid$2 2'00 + connect \p_ready_o \pipe_start_p_ready_o + connect \pipe_start_p_valid_i \p_valid_i + connect \pipe_end_remainder \pipe_middle_0_remainder + connect \pipe_end_quotient_root \pipe_middle_0_quotient_root + connect \pipe_end_div_by_zero \pipe_middle_0_div_by_zero$50 + connect \pipe_end_dive_abs_ov64 \pipe_middle_0_dive_abs_ov64$49 + connect \pipe_end_dive_abs_ov32 \pipe_middle_0_dive_abs_ov32$48 + connect \pipe_end_dividend_neg \pipe_middle_0_dividend_neg$47 + connect \pipe_end_divisor_neg \pipe_middle_0_divisor_neg$46 + connect \pipe_end_xer_so \pipe_middle_0_xer_so$45 + connect \pipe_end_rb \pipe_middle_0_rb$44 + connect \pipe_end_ra \pipe_middle_0_ra$43 + connect { \pipe_end_logical_op__insn \pipe_end_logical_op__data_len \pipe_end_logical_op__is_signed \pipe_end_logical_op__is_32bit \pipe_end_logical_op__output_carry \pipe_end_logical_op__write_cr0 \pipe_end_logical_op__invert_out \pipe_end_logical_op__input_carry \pipe_end_logical_op__zero_a \pipe_end_logical_op__invert_in \pipe_end_logical_op__oe__ok \pipe_end_logical_op__oe__oe \pipe_end_logical_op__rc__ok \pipe_end_logical_op__rc__rc \pipe_end_logical_op__imm_data__ok \pipe_end_logical_op__imm_data__data \pipe_end_logical_op__fn_unit \pipe_end_logical_op__insn_type } { \pipe_middle_0_logical_op__insn$42 \pipe_middle_0_logical_op__data_len$41 \pipe_middle_0_logical_op__is_signed$40 \pipe_middle_0_logical_op__is_32bit$39 \pipe_middle_0_logical_op__output_carry$38 \pipe_middle_0_logical_op__write_cr0$37 \pipe_middle_0_logical_op__invert_out$36 \pipe_middle_0_logical_op__input_carry$35 \pipe_middle_0_logical_op__zero_a$34 \pipe_middle_0_logical_op__invert_in$33 \pipe_middle_0_logical_op__oe__ok$32 \pipe_middle_0_logical_op__oe__oe$31 \pipe_middle_0_logical_op__rc__ok$30 \pipe_middle_0_logical_op__rc__rc$29 \pipe_middle_0_logical_op__imm_data__ok$28 \pipe_middle_0_logical_op__imm_data__data$27 \pipe_middle_0_logical_op__fn_unit$26 \pipe_middle_0_logical_op__insn_type$25 } + connect \pipe_end_muxid \pipe_middle_0_muxid$24 + connect \pipe_middle_0_n_ready_i \pipe_end_p_ready_o + connect \pipe_end_p_valid_i \pipe_middle_0_n_valid_o + connect \pipe_middle_0_operation \pipe_start_operation + connect \pipe_middle_0_divisor_radicand \pipe_start_divisor_radicand + connect \pipe_middle_0_dividend \pipe_start_dividend + connect \pipe_middle_0_div_by_zero \pipe_start_div_by_zero + connect \pipe_middle_0_dive_abs_ov64 \pipe_start_dive_abs_ov64 + connect \pipe_middle_0_dive_abs_ov32 \pipe_start_dive_abs_ov32 + connect \pipe_middle_0_dividend_neg \pipe_start_dividend_neg + connect \pipe_middle_0_divisor_neg \pipe_start_divisor_neg + connect \pipe_middle_0_xer_so \pipe_start_xer_so + connect \pipe_middle_0_rb \pipe_start_rb + connect \pipe_middle_0_ra \pipe_start_ra + connect { \pipe_middle_0_logical_op__insn \pipe_middle_0_logical_op__data_len \pipe_middle_0_logical_op__is_signed \pipe_middle_0_logical_op__is_32bit \pipe_middle_0_logical_op__output_carry \pipe_middle_0_logical_op__write_cr0 \pipe_middle_0_logical_op__invert_out \pipe_middle_0_logical_op__input_carry \pipe_middle_0_logical_op__zero_a \pipe_middle_0_logical_op__invert_in \pipe_middle_0_logical_op__oe__ok \pipe_middle_0_logical_op__oe__oe \pipe_middle_0_logical_op__rc__ok \pipe_middle_0_logical_op__rc__rc \pipe_middle_0_logical_op__imm_data__ok \pipe_middle_0_logical_op__imm_data__data \pipe_middle_0_logical_op__fn_unit \pipe_middle_0_logical_op__insn_type } { \pipe_start_logical_op__insn \pipe_start_logical_op__data_len \pipe_start_logical_op__is_signed \pipe_start_logical_op__is_32bit \pipe_start_logical_op__output_carry \pipe_start_logical_op__write_cr0 \pipe_start_logical_op__invert_out \pipe_start_logical_op__input_carry \pipe_start_logical_op__zero_a \pipe_start_logical_op__invert_in \pipe_start_logical_op__oe__ok \pipe_start_logical_op__oe__oe \pipe_start_logical_op__rc__ok \pipe_start_logical_op__rc__rc \pipe_start_logical_op__imm_data__ok \pipe_start_logical_op__imm_data__data \pipe_start_logical_op__fn_unit \pipe_start_logical_op__insn_type } + connect \pipe_middle_0_muxid \pipe_start_muxid + connect \pipe_start_n_ready_i \pipe_middle_0_p_ready_o + connect \pipe_middle_0_p_valid_i \pipe_start_n_valid_o +end +attribute \src "libresoc.v:26072.1-26130.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_l" +attribute \generator "nMigen" +module \alu_l + attribute \src "libresoc.v:26073.7-26073.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:26118.3-26126.6" + wire $0\q_int$next[0:0]$852 + attribute \src "libresoc.v:26116.3-26117.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:26118.3-26126.6" + wire $1\q_int$next[0:0]$853 + attribute \src "libresoc.v:26097.7-26097.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:26108.17-26108.96" + wire $and$libresoc.v:26108$842_Y + attribute \src "libresoc.v:26113.17-26113.96" + wire $and$libresoc.v:26113$847_Y + attribute \src "libresoc.v:26110.18-26110.93" + wire $not$libresoc.v:26110$844_Y + attribute \src "libresoc.v:26112.17-26112.92" + wire $not$libresoc.v:26112$846_Y + attribute \src "libresoc.v:26115.17-26115.92" + wire $not$libresoc.v:26115$849_Y + attribute \src "libresoc.v:26109.18-26109.98" + wire $or$libresoc.v:26109$843_Y + attribute \src "libresoc.v:26111.18-26111.99" + wire $or$libresoc.v:26111$845_Y + attribute \src "libresoc.v:26114.17-26114.97" + wire $or$libresoc.v:26114$848_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 1 \coresync_rst + attribute \src "libresoc.v:26073.7-26073.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire output 2 \q_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" + wire \qlq_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \qn_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire input 3 \r_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire input 4 \s_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:26108$842 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:26108$842_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:26113$847 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:26113$847_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:26110$844 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alu + connect \Y $not$libresoc.v:26110$844_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:26112$846 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alu + connect \Y $not$libresoc.v:26112$846_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:26115$849 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alu + connect \Y $not$libresoc.v:26115$849_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:26109$843 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_alu + connect \Y $or$libresoc.v:26109$843_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:26111$845 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alu + connect \B \q_int + connect \Y $or$libresoc.v:26111$845_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:26114$848 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_alu + connect \Y $or$libresoc.v:26114$848_Y + end + attribute \src "libresoc.v:26073.7-26073.20" + process $proc$libresoc.v:26073$854 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:26097.7-26097.19" + process $proc$libresoc.v:26097$855 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:26116.3-26117.27" + process $proc$libresoc.v:26116$850 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:26118.3-26126.6" + process $proc$libresoc.v:26118$851 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$852 $1\q_int$next[0:0]$853 + attribute \src "libresoc.v:26119.5-26119.29" + switch \initial + attribute \src "libresoc.v:26119.9-26119.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$853 1'0 + case + assign $1\q_int$next[0:0]$853 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$852 + end + connect \$9 $and$libresoc.v:26108$842_Y + connect \$11 $or$libresoc.v:26109$843_Y + connect \$13 $not$libresoc.v:26110$844_Y + connect \$15 $or$libresoc.v:26111$845_Y + connect \$1 $not$libresoc.v:26112$846_Y + connect \$3 $and$libresoc.v:26113$847_Y + connect \$5 $or$libresoc.v:26114$848_Y + connect \$7 $not$libresoc.v:26115$849_Y + connect \qlq_alu \$15 + connect \qn_alu \$13 + connect \q_alu \$11 +end +attribute \src "libresoc.v:26134.1-26192.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_l" +attribute \generator "nMigen" +module \alu_l$107 + attribute \src "libresoc.v:26135.7-26135.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:26180.3-26188.6" + wire $0\q_int$next[0:0]$866 + attribute \src "libresoc.v:26178.3-26179.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:26180.3-26188.6" + wire $1\q_int$next[0:0]$867 + attribute \src "libresoc.v:26159.7-26159.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:26170.17-26170.96" + wire $and$libresoc.v:26170$856_Y + attribute \src "libresoc.v:26175.17-26175.96" + wire $and$libresoc.v:26175$861_Y + attribute \src "libresoc.v:26172.18-26172.93" + wire $not$libresoc.v:26172$858_Y + attribute \src "libresoc.v:26174.17-26174.92" + wire $not$libresoc.v:26174$860_Y + attribute \src "libresoc.v:26177.17-26177.92" + wire $not$libresoc.v:26177$863_Y + attribute \src "libresoc.v:26171.18-26171.98" + wire $or$libresoc.v:26171$857_Y + attribute \src "libresoc.v:26173.18-26173.99" + wire $or$libresoc.v:26173$859_Y + attribute \src "libresoc.v:26176.17-26176.97" + wire $or$libresoc.v:26176$862_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 1 \coresync_rst + attribute \src "libresoc.v:26135.7-26135.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire output 2 \q_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" + wire \qlq_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \qn_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire input 3 \r_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire input 4 \s_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:26170$856 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:26170$856_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:26175$861 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:26175$861_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:26172$858 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alu + connect \Y $not$libresoc.v:26172$858_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:26174$860 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alu + connect \Y $not$libresoc.v:26174$860_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:26177$863 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alu + connect \Y $not$libresoc.v:26177$863_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:26171$857 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_alu + connect \Y $or$libresoc.v:26171$857_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:26173$859 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alu + connect \B \q_int + connect \Y $or$libresoc.v:26173$859_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:26176$862 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_alu + connect \Y $or$libresoc.v:26176$862_Y + end + attribute \src "libresoc.v:26135.7-26135.20" + process $proc$libresoc.v:26135$868 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:26159.7-26159.19" + process $proc$libresoc.v:26159$869 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:26178.3-26179.27" + process $proc$libresoc.v:26178$864 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:26180.3-26188.6" + process $proc$libresoc.v:26180$865 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$866 $1\q_int$next[0:0]$867 + attribute \src "libresoc.v:26181.5-26181.29" + switch \initial + attribute \src "libresoc.v:26181.9-26181.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$867 1'0 + case + assign $1\q_int$next[0:0]$867 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$866 + end + connect \$9 $and$libresoc.v:26170$856_Y + connect \$11 $or$libresoc.v:26171$857_Y + connect \$13 $not$libresoc.v:26172$858_Y + connect \$15 $or$libresoc.v:26173$859_Y + connect \$1 $not$libresoc.v:26174$860_Y + connect \$3 $and$libresoc.v:26175$861_Y + connect \$5 $or$libresoc.v:26176$862_Y + connect \$7 $not$libresoc.v:26177$863_Y + connect \qlq_alu \$15 + connect \qn_alu \$13 + connect \q_alu \$11 +end +attribute \src "libresoc.v:26196.1-26254.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_l" +attribute \generator "nMigen" +module \alu_l$125 + attribute \src "libresoc.v:26197.7-26197.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:26242.3-26250.6" + wire $0\q_int$next[0:0]$880 + attribute \src "libresoc.v:26240.3-26241.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:26242.3-26250.6" + wire $1\q_int$next[0:0]$881 + attribute \src "libresoc.v:26221.7-26221.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:26232.17-26232.96" + wire $and$libresoc.v:26232$870_Y + attribute \src "libresoc.v:26237.17-26237.96" + wire $and$libresoc.v:26237$875_Y + attribute \src "libresoc.v:26234.18-26234.93" + wire $not$libresoc.v:26234$872_Y + attribute \src "libresoc.v:26236.17-26236.92" + wire $not$libresoc.v:26236$874_Y + attribute \src "libresoc.v:26239.17-26239.92" + wire $not$libresoc.v:26239$877_Y + attribute \src "libresoc.v:26233.18-26233.98" + wire $or$libresoc.v:26233$871_Y + attribute \src "libresoc.v:26235.18-26235.99" + wire $or$libresoc.v:26235$873_Y + attribute \src "libresoc.v:26238.17-26238.97" + wire $or$libresoc.v:26238$876_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 1 \coresync_rst + attribute \src "libresoc.v:26197.7-26197.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire output 2 \q_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" + wire \qlq_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \qn_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire input 3 \r_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire input 4 \s_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:26232$870 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:26232$870_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:26237$875 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:26237$875_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:26234$872 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alu + connect \Y $not$libresoc.v:26234$872_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:26236$874 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alu + connect \Y $not$libresoc.v:26236$874_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:26239$877 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alu + connect \Y $not$libresoc.v:26239$877_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:26233$871 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_alu + connect \Y $or$libresoc.v:26233$871_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:26235$873 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alu + connect \B \q_int + connect \Y $or$libresoc.v:26235$873_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:26238$876 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_alu + connect \Y $or$libresoc.v:26238$876_Y + end + attribute \src "libresoc.v:26197.7-26197.20" + process $proc$libresoc.v:26197$882 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:26221.7-26221.19" + process $proc$libresoc.v:26221$883 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:26240.3-26241.27" + process $proc$libresoc.v:26240$878 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:26242.3-26250.6" + process $proc$libresoc.v:26242$879 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$880 $1\q_int$next[0:0]$881 + attribute \src "libresoc.v:26243.5-26243.29" + switch \initial + attribute \src "libresoc.v:26243.9-26243.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$881 1'0 + case + assign $1\q_int$next[0:0]$881 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$880 + end + connect \$9 $and$libresoc.v:26232$870_Y + connect \$11 $or$libresoc.v:26233$871_Y + connect \$13 $not$libresoc.v:26234$872_Y + connect \$15 $or$libresoc.v:26235$873_Y + connect \$1 $not$libresoc.v:26236$874_Y + connect \$3 $and$libresoc.v:26237$875_Y + connect \$5 $or$libresoc.v:26238$876_Y + connect \$7 $not$libresoc.v:26239$877_Y + connect \qlq_alu \$15 + connect \qn_alu \$13 + connect \q_alu \$11 +end +attribute \src "libresoc.v:26258.1-26316.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.alu_l" +attribute \generator "nMigen" +module \alu_l$128 + attribute \src "libresoc.v:26259.7-26259.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:26304.3-26312.6" + wire $0\q_int$next[0:0]$894 + attribute \src "libresoc.v:26302.3-26303.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:26304.3-26312.6" + wire $1\q_int$next[0:0]$895 + attribute \src "libresoc.v:26283.7-26283.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:26294.17-26294.96" + wire $and$libresoc.v:26294$884_Y + attribute \src "libresoc.v:26299.17-26299.96" + wire $and$libresoc.v:26299$889_Y + attribute \src "libresoc.v:26296.18-26296.93" + wire $not$libresoc.v:26296$886_Y + attribute \src "libresoc.v:26298.17-26298.92" + wire $not$libresoc.v:26298$888_Y + attribute \src "libresoc.v:26301.17-26301.92" + wire $not$libresoc.v:26301$891_Y + attribute \src "libresoc.v:26295.18-26295.98" + wire $or$libresoc.v:26295$885_Y + attribute \src "libresoc.v:26297.18-26297.99" + wire $or$libresoc.v:26297$887_Y + attribute \src "libresoc.v:26300.17-26300.97" + wire $or$libresoc.v:26300$890_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 1 \coresync_rst + attribute \src "libresoc.v:26259.7-26259.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire output 4 \q_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" + wire \qlq_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \qn_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire input 3 \r_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire input 2 \s_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:26294$884 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:26294$884_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:26299$889 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:26299$889_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:26296$886 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alu + connect \Y $not$libresoc.v:26296$886_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:26298$888 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alu + connect \Y $not$libresoc.v:26298$888_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:26301$891 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alu + connect \Y $not$libresoc.v:26301$891_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:26295$885 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_alu + connect \Y $or$libresoc.v:26295$885_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:26297$887 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alu + connect \B \q_int + connect \Y $or$libresoc.v:26297$887_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:26300$890 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_alu + connect \Y $or$libresoc.v:26300$890_Y + end + attribute \src "libresoc.v:26259.7-26259.20" + process $proc$libresoc.v:26259$896 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:26283.7-26283.19" + process $proc$libresoc.v:26283$897 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:26302.3-26303.27" + process $proc$libresoc.v:26302$892 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:26304.3-26312.6" + process $proc$libresoc.v:26304$893 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$894 $1\q_int$next[0:0]$895 + attribute \src "libresoc.v:26305.5-26305.29" + switch \initial + attribute \src "libresoc.v:26305.9-26305.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$895 1'0 + case + assign $1\q_int$next[0:0]$895 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$894 + end + connect \$9 $and$libresoc.v:26294$884_Y + connect \$11 $or$libresoc.v:26295$885_Y + connect \$13 $not$libresoc.v:26296$886_Y + connect \$15 $or$libresoc.v:26297$887_Y + connect \$1 $not$libresoc.v:26298$888_Y + connect \$3 $and$libresoc.v:26299$889_Y + connect \$5 $or$libresoc.v:26300$890_Y + connect \$7 $not$libresoc.v:26301$891_Y + connect \qlq_alu \$15 + connect \qn_alu \$13 + connect \q_alu \$11 +end +attribute \src "libresoc.v:26320.1-26378.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.alu_l" +attribute \generator "nMigen" +module \alu_l$16 + attribute \src "libresoc.v:26321.7-26321.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:26366.3-26374.6" + wire $0\q_int$next[0:0]$908 + attribute \src "libresoc.v:26364.3-26365.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:26366.3-26374.6" + wire $1\q_int$next[0:0]$909 + attribute \src "libresoc.v:26345.7-26345.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:26356.17-26356.96" + wire $and$libresoc.v:26356$898_Y + attribute \src "libresoc.v:26361.17-26361.96" + wire $and$libresoc.v:26361$903_Y + attribute \src "libresoc.v:26358.18-26358.93" + wire $not$libresoc.v:26358$900_Y + attribute \src "libresoc.v:26360.17-26360.92" + wire $not$libresoc.v:26360$902_Y + attribute \src "libresoc.v:26363.17-26363.92" + wire $not$libresoc.v:26363$905_Y + attribute \src "libresoc.v:26357.18-26357.98" + wire $or$libresoc.v:26357$899_Y + attribute \src "libresoc.v:26359.18-26359.99" + wire $or$libresoc.v:26359$901_Y + attribute \src "libresoc.v:26362.17-26362.97" + wire $or$libresoc.v:26362$904_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 1 \coresync_rst + attribute \src "libresoc.v:26321.7-26321.15" + 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"/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:26361$903 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:26361$903_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:26358$900 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alu + connect \Y $not$libresoc.v:26358$900_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:26360$902 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alu + connect \Y $not$libresoc.v:26360$902_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:26363$905 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alu + connect \Y $not$libresoc.v:26363$905_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:26357$899 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_alu + connect \Y $or$libresoc.v:26357$899_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:26359$901 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alu + connect \B \q_int + connect \Y $or$libresoc.v:26359$901_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:26362$904 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_alu + connect \Y $or$libresoc.v:26362$904_Y + end + attribute \src "libresoc.v:26321.7-26321.20" + process $proc$libresoc.v:26321$910 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:26345.7-26345.19" + process $proc$libresoc.v:26345$911 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:26364.3-26365.27" + process $proc$libresoc.v:26364$906 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:26366.3-26374.6" + process $proc$libresoc.v:26366$907 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$908 $1\q_int$next[0:0]$909 + attribute \src "libresoc.v:26367.5-26367.29" + switch \initial + attribute \src "libresoc.v:26367.9-26367.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$909 1'0 + case + assign $1\q_int$next[0:0]$909 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$908 + end + connect \$9 $and$libresoc.v:26356$898_Y + connect \$11 $or$libresoc.v:26357$899_Y + connect \$13 $not$libresoc.v:26358$900_Y + connect \$15 $or$libresoc.v:26359$901_Y + connect \$1 $not$libresoc.v:26360$902_Y + connect \$3 $and$libresoc.v:26361$903_Y + connect \$5 $or$libresoc.v:26362$904_Y + connect \$7 $not$libresoc.v:26363$905_Y + connect \qlq_alu \$15 + connect \qn_alu \$13 + connect \q_alu \$11 +end +attribute \src "libresoc.v:26382.1-26440.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.alu_l" +attribute \generator "nMigen" +module \alu_l$29 + attribute \src "libresoc.v:26383.7-26383.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:26428.3-26436.6" + wire $0\q_int$next[0:0]$922 + attribute \src "libresoc.v:26426.3-26427.27" + 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attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 1 \coresync_rst + attribute \src "libresoc.v:26383.7-26383.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire output 2 \q_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" + wire \qlq_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \qn_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire input 3 \r_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire input 4 \s_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:26418$912 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:26418$912_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:26423$917 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:26423$917_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:26420$914 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alu + connect \Y $not$libresoc.v:26420$914_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:26422$916 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alu + connect \Y $not$libresoc.v:26422$916_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:26425$919 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alu + connect \Y $not$libresoc.v:26425$919_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:26419$913 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_alu + connect \Y $or$libresoc.v:26419$913_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:26421$915 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alu + connect \B \q_int + connect \Y $or$libresoc.v:26421$915_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:26424$918 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_alu + connect \Y $or$libresoc.v:26424$918_Y + end + attribute \src "libresoc.v:26383.7-26383.20" + process $proc$libresoc.v:26383$924 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:26407.7-26407.19" + process $proc$libresoc.v:26407$925 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:26426.3-26427.27" + process $proc$libresoc.v:26426$920 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:26428.3-26436.6" + process $proc$libresoc.v:26428$921 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$922 $1\q_int$next[0:0]$923 + attribute \src "libresoc.v:26429.5-26429.29" + switch \initial + attribute \src "libresoc.v:26429.9-26429.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$923 1'0 + case + assign $1\q_int$next[0:0]$923 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$922 + end + connect \$9 $and$libresoc.v:26418$912_Y + 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$and$libresoc.v:26480$926_Y + attribute \src "libresoc.v:26485.17-26485.96" + wire $and$libresoc.v:26485$931_Y + attribute \src "libresoc.v:26482.18-26482.93" + wire $not$libresoc.v:26482$928_Y + attribute \src "libresoc.v:26484.17-26484.92" + wire $not$libresoc.v:26484$930_Y + attribute \src "libresoc.v:26487.17-26487.92" + wire $not$libresoc.v:26487$933_Y + attribute \src "libresoc.v:26481.18-26481.98" + wire $or$libresoc.v:26481$927_Y + attribute \src "libresoc.v:26483.18-26483.99" + wire $or$libresoc.v:26483$929_Y + attribute \src "libresoc.v:26486.17-26486.97" + wire $or$libresoc.v:26486$932_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + wire \$15 + attribute \src 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"/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \qn_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire input 3 \r_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire input 4 \s_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:26480$926 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:26480$926_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:26485$931 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:26485$931_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:26482$928 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alu + connect \Y $not$libresoc.v:26482$928_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:26484$930 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alu + connect \Y $not$libresoc.v:26484$930_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:26487$933 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alu + connect \Y $not$libresoc.v:26487$933_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:26481$927 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_alu + connect \Y $or$libresoc.v:26481$927_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:26483$929 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alu + connect \B \q_int + connect \Y $or$libresoc.v:26483$929_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:26486$932 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_alu + connect \Y $or$libresoc.v:26486$932_Y + end + attribute \src "libresoc.v:26445.7-26445.20" + process $proc$libresoc.v:26445$938 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:26469.7-26469.19" + process $proc$libresoc.v:26469$939 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:26488.3-26489.27" + process $proc$libresoc.v:26488$934 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:26490.3-26498.6" + process $proc$libresoc.v:26490$935 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$936 $1\q_int$next[0:0]$937 + attribute \src "libresoc.v:26491.5-26491.29" + switch \initial + attribute \src "libresoc.v:26491.9-26491.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$937 1'0 + case + assign $1\q_int$next[0:0]$937 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$936 + end + connect \$9 $and$libresoc.v:26480$926_Y + connect \$11 $or$libresoc.v:26481$927_Y + connect \$13 $not$libresoc.v:26482$928_Y + connect \$15 $or$libresoc.v:26483$929_Y + connect \$1 $not$libresoc.v:26484$930_Y + connect \$3 $and$libresoc.v:26485$931_Y + connect \$5 $or$libresoc.v:26486$932_Y + connect \$7 $not$libresoc.v:26487$933_Y + connect \qlq_alu \$15 + connect \qn_alu \$13 + connect \q_alu \$11 +end +attribute \src "libresoc.v:26506.1-26564.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_l" +attribute \generator "nMigen" +module \alu_l$61 + attribute \src "libresoc.v:26507.7-26507.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:26552.3-26560.6" + wire $0\q_int$next[0:0]$950 + attribute \src "libresoc.v:26550.3-26551.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:26552.3-26560.6" + wire $1\q_int$next[0:0]$951 + attribute \src "libresoc.v:26531.7-26531.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:26542.17-26542.96" + wire $and$libresoc.v:26542$940_Y + attribute \src "libresoc.v:26547.17-26547.96" + wire $and$libresoc.v:26547$945_Y + attribute \src "libresoc.v:26544.18-26544.93" + wire $not$libresoc.v:26544$942_Y + attribute \src "libresoc.v:26546.17-26546.92" + wire $not$libresoc.v:26546$944_Y + attribute \src "libresoc.v:26549.17-26549.92" + wire $not$libresoc.v:26549$947_Y + attribute \src "libresoc.v:26543.18-26543.98" + wire $or$libresoc.v:26543$941_Y + attribute \src "libresoc.v:26545.18-26545.99" + wire $or$libresoc.v:26545$943_Y + attribute \src "libresoc.v:26548.17-26548.97" + wire $or$libresoc.v:26548$946_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 1 \coresync_rst + attribute \src "libresoc.v:26507.7-26507.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire output 2 \q_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" + wire \qlq_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \qn_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire input 3 \r_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire input 4 \s_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:26542$940 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:26542$940_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:26547$945 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:26547$945_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:26544$942 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alu + connect \Y $not$libresoc.v:26544$942_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:26546$944 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alu + connect \Y $not$libresoc.v:26546$944_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:26549$947 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alu + connect \Y $not$libresoc.v:26549$947_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:26543$941 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_alu + connect \Y $or$libresoc.v:26543$941_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:26545$943 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alu + connect \B \q_int + connect \Y $or$libresoc.v:26545$943_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:26548$946 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_alu + connect \Y $or$libresoc.v:26548$946_Y + end + attribute \src "libresoc.v:26507.7-26507.20" + process $proc$libresoc.v:26507$952 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:26531.7-26531.19" + process $proc$libresoc.v:26531$953 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:26550.3-26551.27" + process $proc$libresoc.v:26550$948 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:26552.3-26560.6" + process $proc$libresoc.v:26552$949 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$950 $1\q_int$next[0:0]$951 + attribute \src "libresoc.v:26553.5-26553.29" + switch \initial + attribute \src "libresoc.v:26553.9-26553.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$951 1'0 + case + assign $1\q_int$next[0:0]$951 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$950 + end + connect \$9 $and$libresoc.v:26542$940_Y + connect \$11 $or$libresoc.v:26543$941_Y + connect \$13 $not$libresoc.v:26544$942_Y + connect \$15 $or$libresoc.v:26545$943_Y + connect \$1 $not$libresoc.v:26546$944_Y + connect \$3 $and$libresoc.v:26547$945_Y + connect \$5 $or$libresoc.v:26548$946_Y + connect \$7 $not$libresoc.v:26549$947_Y + connect \qlq_alu \$15 + connect \qn_alu \$13 + connect \q_alu \$11 +end +attribute \src "libresoc.v:26568.1-26626.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.alu_l" +attribute \generator "nMigen" +module \alu_l$73 + attribute \src "libresoc.v:26569.7-26569.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:26614.3-26622.6" + wire $0\q_int$next[0:0]$964 + attribute \src "libresoc.v:26612.3-26613.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:26614.3-26622.6" + wire $1\q_int$next[0:0]$965 + attribute \src "libresoc.v:26593.7-26593.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:26604.17-26604.96" + wire $and$libresoc.v:26604$954_Y + attribute \src "libresoc.v:26609.17-26609.96" + wire $and$libresoc.v:26609$959_Y + attribute \src "libresoc.v:26606.18-26606.93" + wire $not$libresoc.v:26606$956_Y + attribute \src "libresoc.v:26608.17-26608.92" + wire $not$libresoc.v:26608$958_Y + attribute \src "libresoc.v:26611.17-26611.92" + wire $not$libresoc.v:26611$961_Y + attribute \src "libresoc.v:26605.18-26605.98" + wire $or$libresoc.v:26605$955_Y + attribute \src "libresoc.v:26607.18-26607.99" + wire $or$libresoc.v:26607$957_Y + attribute \src "libresoc.v:26610.17-26610.97" + wire $or$libresoc.v:26610$960_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 1 \coresync_rst + attribute \src "libresoc.v:26569.7-26569.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire output 2 \q_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" + wire \qlq_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \qn_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire input 3 \r_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire input 4 \s_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:26604$954 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:26604$954_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:26609$959 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:26609$959_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:26606$956 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alu + connect \Y $not$libresoc.v:26606$956_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:26608$958 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alu + connect \Y $not$libresoc.v:26608$958_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:26611$961 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alu + connect \Y $not$libresoc.v:26611$961_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:26605$955 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_alu + connect \Y $or$libresoc.v:26605$955_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:26607$957 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alu + connect \B \q_int + connect \Y $or$libresoc.v:26607$957_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:26610$960 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_alu + connect \Y $or$libresoc.v:26610$960_Y + end + attribute \src "libresoc.v:26569.7-26569.20" + process $proc$libresoc.v:26569$966 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:26593.7-26593.19" + process $proc$libresoc.v:26593$967 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:26612.3-26613.27" + process $proc$libresoc.v:26612$962 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:26614.3-26622.6" + process $proc$libresoc.v:26614$963 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$964 $1\q_int$next[0:0]$965 + attribute \src "libresoc.v:26615.5-26615.29" + switch \initial + attribute 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"/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_in$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 17 \logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_out$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 20 \logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_32bit$59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 21 \logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_signed$60 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__oe$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__ok$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 19 \logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__output_carry$58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 11 \logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__ok$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__rc$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 18 \logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__write_cr0$57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 15 \logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__zero_a$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \logical_pipe1_cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \logical_pipe1_cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \logical_pipe1_logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \logical_pipe1_logical_op__data_len$18 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \logical_pipe1_logical_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \logical_pipe1_logical_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \logical_pipe1_logical_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \logical_pipe1_logical_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe1_logical_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe1_logical_op__imm_data__ok$5 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \logical_pipe1_logical_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \logical_pipe1_logical_op__input_carry$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \logical_pipe1_logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \logical_pipe1_logical_op__insn$19 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \logical_pipe1_logical_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \logical_pipe1_logical_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe1_logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe1_logical_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe1_logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe1_logical_op__invert_out$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe1_logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe1_logical_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe1_logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe1_logical_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe1_logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe1_logical_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe1_logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe1_logical_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe1_logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe1_logical_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe1_logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe1_logical_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe1_logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe1_logical_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe1_logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe1_logical_op__write_cr0$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe1_logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe1_logical_op__zero_a$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \logical_pipe1_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \logical_pipe1_muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire \logical_pipe1_n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire \logical_pipe1_n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \logical_pipe1_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \logical_pipe1_o_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" + wire \logical_pipe1_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" + wire \logical_pipe1_p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \logical_pipe1_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \logical_pipe1_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \logical_pipe1_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \logical_pipe1_xer_so$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \logical_pipe1_xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \logical_pipe2_cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \logical_pipe2_cr_a$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \logical_pipe2_cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \logical_pipe2_cr_a_ok$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \logical_pipe2_logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \logical_pipe2_logical_op__data_len$38 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \logical_pipe2_logical_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \logical_pipe2_logical_op__fn_unit$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \logical_pipe2_logical_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \logical_pipe2_logical_op__imm_data__data$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe2_logical_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe2_logical_op__imm_data__ok$25 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \logical_pipe2_logical_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \logical_pipe2_logical_op__input_carry$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \logical_pipe2_logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \logical_pipe2_logical_op__insn$39 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \logical_pipe2_logical_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \logical_pipe2_logical_op__insn_type$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe2_logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe2_logical_op__invert_in$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe2_logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe2_logical_op__invert_out$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe2_logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe2_logical_op__is_32bit$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe2_logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe2_logical_op__is_signed$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe2_logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe2_logical_op__oe__oe$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe2_logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe2_logical_op__oe__ok$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe2_logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe2_logical_op__output_carry$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe2_logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe2_logical_op__rc__ok$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe2_logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe2_logical_op__rc__rc$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe2_logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe2_logical_op__write_cr0$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe2_logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe2_logical_op__zero_a$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \logical_pipe2_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \logical_pipe2_muxid$21 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire \logical_pipe2_n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire \logical_pipe2_n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \logical_pipe2_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \logical_pipe2_o$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \logical_pipe2_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \logical_pipe2_o_ok$41 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" + wire \logical_pipe2_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" + wire \logical_pipe2_p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \logical_pipe2_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \logical_pipe2_xer_so_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid$44 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire input 5 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire output 4 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 24 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 2 \o_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" + wire output 30 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" + wire input 29 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 26 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 27 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 28 \xer_so + attribute \module_not_derived 1 + attribute \src "libresoc.v:27553.17-27607.4" + cell \logical_pipe1 \logical_pipe1 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cr_a \logical_pipe1_cr_a + connect \cr_a_ok \logical_pipe1_cr_a_ok + connect \logical_op__data_len \logical_pipe1_logical_op__data_len + connect \logical_op__data_len$18 \logical_pipe1_logical_op__data_len$18 + connect \logical_op__fn_unit \logical_pipe1_logical_op__fn_unit + connect \logical_op__fn_unit$3 \logical_pipe1_logical_op__fn_unit$3 + connect \logical_op__imm_data__data \logical_pipe1_logical_op__imm_data__data + connect \logical_op__imm_data__data$4 \logical_pipe1_logical_op__imm_data__data$4 + connect \logical_op__imm_data__ok \logical_pipe1_logical_op__imm_data__ok + connect \logical_op__imm_data__ok$5 \logical_pipe1_logical_op__imm_data__ok$5 + connect \logical_op__input_carry \logical_pipe1_logical_op__input_carry + connect \logical_op__input_carry$12 \logical_pipe1_logical_op__input_carry$12 + connect \logical_op__insn \logical_pipe1_logical_op__insn + connect \logical_op__insn$19 \logical_pipe1_logical_op__insn$19 + connect \logical_op__insn_type \logical_pipe1_logical_op__insn_type + connect \logical_op__insn_type$2 \logical_pipe1_logical_op__insn_type$2 + connect \logical_op__invert_in \logical_pipe1_logical_op__invert_in + connect \logical_op__invert_in$10 \logical_pipe1_logical_op__invert_in$10 + connect \logical_op__invert_out \logical_pipe1_logical_op__invert_out + connect \logical_op__invert_out$13 \logical_pipe1_logical_op__invert_out$13 + connect \logical_op__is_32bit \logical_pipe1_logical_op__is_32bit + connect \logical_op__is_32bit$16 \logical_pipe1_logical_op__is_32bit$16 + connect \logical_op__is_signed \logical_pipe1_logical_op__is_signed + connect \logical_op__is_signed$17 \logical_pipe1_logical_op__is_signed$17 + connect \logical_op__oe__oe \logical_pipe1_logical_op__oe__oe + connect \logical_op__oe__oe$8 \logical_pipe1_logical_op__oe__oe$8 + connect \logical_op__oe__ok \logical_pipe1_logical_op__oe__ok + connect \logical_op__oe__ok$9 \logical_pipe1_logical_op__oe__ok$9 + connect \logical_op__output_carry \logical_pipe1_logical_op__output_carry + connect \logical_op__output_carry$15 \logical_pipe1_logical_op__output_carry$15 + connect \logical_op__rc__ok \logical_pipe1_logical_op__rc__ok + connect \logical_op__rc__ok$7 \logical_pipe1_logical_op__rc__ok$7 + connect \logical_op__rc__rc \logical_pipe1_logical_op__rc__rc + connect \logical_op__rc__rc$6 \logical_pipe1_logical_op__rc__rc$6 + connect \logical_op__write_cr0 \logical_pipe1_logical_op__write_cr0 + connect \logical_op__write_cr0$14 \logical_pipe1_logical_op__write_cr0$14 + connect \logical_op__zero_a \logical_pipe1_logical_op__zero_a + connect \logical_op__zero_a$11 \logical_pipe1_logical_op__zero_a$11 + connect \muxid \logical_pipe1_muxid + connect \muxid$1 \logical_pipe1_muxid$1 + connect \n_ready_i \logical_pipe1_n_ready_i + connect \n_valid_o \logical_pipe1_n_valid_o + connect \o \logical_pipe1_o + connect \o_ok \logical_pipe1_o_ok + connect \p_ready_o \logical_pipe1_p_ready_o + connect \p_valid_i \logical_pipe1_p_valid_i + connect \ra \logical_pipe1_ra + connect \rb \logical_pipe1_rb + connect \xer_so \logical_pipe1_xer_so + connect \xer_so$20 \logical_pipe1_xer_so$20 + connect \xer_so_ok \logical_pipe1_xer_so_ok + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:27608.17-27663.4" + cell \logical_pipe2 \logical_pipe2 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cr_a \logical_pipe2_cr_a + connect \cr_a$22 \logical_pipe2_cr_a$42 + connect \cr_a_ok \logical_pipe2_cr_a_ok + connect \cr_a_ok$23 \logical_pipe2_cr_a_ok$43 + connect \logical_op__data_len \logical_pipe2_logical_op__data_len + connect \logical_op__data_len$18 \logical_pipe2_logical_op__data_len$38 + connect \logical_op__fn_unit \logical_pipe2_logical_op__fn_unit + connect \logical_op__fn_unit$3 \logical_pipe2_logical_op__fn_unit$23 + connect \logical_op__imm_data__data \logical_pipe2_logical_op__imm_data__data + connect \logical_op__imm_data__data$4 \logical_pipe2_logical_op__imm_data__data$24 + connect \logical_op__imm_data__ok \logical_pipe2_logical_op__imm_data__ok + connect \logical_op__imm_data__ok$5 \logical_pipe2_logical_op__imm_data__ok$25 + connect \logical_op__input_carry \logical_pipe2_logical_op__input_carry + connect \logical_op__input_carry$12 \logical_pipe2_logical_op__input_carry$32 + connect \logical_op__insn \logical_pipe2_logical_op__insn + connect \logical_op__insn$19 \logical_pipe2_logical_op__insn$39 + connect \logical_op__insn_type \logical_pipe2_logical_op__insn_type + connect \logical_op__insn_type$2 \logical_pipe2_logical_op__insn_type$22 + connect \logical_op__invert_in \logical_pipe2_logical_op__invert_in + connect \logical_op__invert_in$10 \logical_pipe2_logical_op__invert_in$30 + connect \logical_op__invert_out \logical_pipe2_logical_op__invert_out + connect \logical_op__invert_out$13 \logical_pipe2_logical_op__invert_out$33 + connect \logical_op__is_32bit \logical_pipe2_logical_op__is_32bit + connect \logical_op__is_32bit$16 \logical_pipe2_logical_op__is_32bit$36 + connect \logical_op__is_signed \logical_pipe2_logical_op__is_signed + connect \logical_op__is_signed$17 \logical_pipe2_logical_op__is_signed$37 + connect \logical_op__oe__oe \logical_pipe2_logical_op__oe__oe + connect \logical_op__oe__oe$8 \logical_pipe2_logical_op__oe__oe$28 + connect \logical_op__oe__ok \logical_pipe2_logical_op__oe__ok + connect \logical_op__oe__ok$9 \logical_pipe2_logical_op__oe__ok$29 + connect \logical_op__output_carry \logical_pipe2_logical_op__output_carry + connect \logical_op__output_carry$15 \logical_pipe2_logical_op__output_carry$35 + connect \logical_op__rc__ok \logical_pipe2_logical_op__rc__ok + connect \logical_op__rc__ok$7 \logical_pipe2_logical_op__rc__ok$27 + connect \logical_op__rc__rc \logical_pipe2_logical_op__rc__rc + connect \logical_op__rc__rc$6 \logical_pipe2_logical_op__rc__rc$26 + connect \logical_op__write_cr0 \logical_pipe2_logical_op__write_cr0 + connect \logical_op__write_cr0$14 \logical_pipe2_logical_op__write_cr0$34 + connect \logical_op__zero_a \logical_pipe2_logical_op__zero_a + connect \logical_op__zero_a$11 \logical_pipe2_logical_op__zero_a$31 + connect \muxid \logical_pipe2_muxid + connect \muxid$1 \logical_pipe2_muxid$21 + connect \n_ready_i \logical_pipe2_n_ready_i + connect \n_valid_o \logical_pipe2_n_valid_o + connect \o \logical_pipe2_o + connect \o$20 \logical_pipe2_o$40 + connect \o_ok \logical_pipe2_o_ok + connect \o_ok$21 \logical_pipe2_o_ok$41 + connect \p_ready_o \logical_pipe2_p_ready_o + connect \p_valid_i \logical_pipe2_p_valid_i + connect \xer_so \logical_pipe2_xer_so + connect \xer_so_ok \logical_pipe2_xer_so_ok + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:27664.10-27667.4" + cell \n$47 \n + connect \n_ready_i \n_ready_i + connect \n_valid_o \n_valid_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:27668.10-27671.4" + cell \p$46 \p + connect \p_ready_o \p_ready_o + connect \p_valid_i \p_valid_i + end + connect \muxid 2'00 + connect { \cr_a_ok \cr_a } { \logical_pipe2_cr_a_ok$43 \logical_pipe2_cr_a$42 } + connect { \o_ok \o } { \logical_pipe2_o_ok$41 \logical_pipe2_o$40 } + connect { \logical_op__insn$62 \logical_op__data_len$61 \logical_op__is_signed$60 \logical_op__is_32bit$59 \logical_op__output_carry$58 \logical_op__write_cr0$57 \logical_op__invert_out$56 \logical_op__input_carry$55 \logical_op__zero_a$54 \logical_op__invert_in$53 \logical_op__oe__ok$52 \logical_op__oe__oe$51 \logical_op__rc__ok$50 \logical_op__rc__rc$49 \logical_op__imm_data__ok$48 \logical_op__imm_data__data$47 \logical_op__fn_unit$46 \logical_op__insn_type$45 } { \logical_pipe2_logical_op__insn$39 \logical_pipe2_logical_op__data_len$38 \logical_pipe2_logical_op__is_signed$37 \logical_pipe2_logical_op__is_32bit$36 \logical_pipe2_logical_op__output_carry$35 \logical_pipe2_logical_op__write_cr0$34 \logical_pipe2_logical_op__invert_out$33 \logical_pipe2_logical_op__input_carry$32 \logical_pipe2_logical_op__zero_a$31 \logical_pipe2_logical_op__invert_in$30 \logical_pipe2_logical_op__oe__ok$29 \logical_pipe2_logical_op__oe__oe$28 \logical_pipe2_logical_op__rc__ok$27 \logical_pipe2_logical_op__rc__rc$26 \logical_pipe2_logical_op__imm_data__ok$25 \logical_pipe2_logical_op__imm_data__data$24 \logical_pipe2_logical_op__fn_unit$23 \logical_pipe2_logical_op__insn_type$22 } + connect \muxid$44 \logical_pipe2_muxid$21 + connect \logical_pipe2_n_ready_i \n_ready_i + connect \n_valid_o \logical_pipe2_n_valid_o + connect \logical_pipe1_xer_so$20 \xer_so + connect \logical_pipe1_rb \rb + connect \logical_pipe1_ra \ra + connect { \logical_pipe1_logical_op__insn$19 \logical_pipe1_logical_op__data_len$18 \logical_pipe1_logical_op__is_signed$17 \logical_pipe1_logical_op__is_32bit$16 \logical_pipe1_logical_op__output_carry$15 \logical_pipe1_logical_op__write_cr0$14 \logical_pipe1_logical_op__invert_out$13 \logical_pipe1_logical_op__input_carry$12 \logical_pipe1_logical_op__zero_a$11 \logical_pipe1_logical_op__invert_in$10 \logical_pipe1_logical_op__oe__ok$9 \logical_pipe1_logical_op__oe__oe$8 \logical_pipe1_logical_op__rc__ok$7 \logical_pipe1_logical_op__rc__rc$6 \logical_pipe1_logical_op__imm_data__ok$5 \logical_pipe1_logical_op__imm_data__data$4 \logical_pipe1_logical_op__fn_unit$3 \logical_pipe1_logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } + connect \logical_pipe1_muxid$1 2'00 + connect \p_ready_o \logical_pipe1_p_ready_o + connect \logical_pipe1_p_valid_i \p_valid_i + connect { \logical_pipe2_xer_so_ok \logical_pipe2_xer_so } { \logical_pipe1_xer_so_ok \logical_pipe1_xer_so } + connect { \logical_pipe2_cr_a_ok \logical_pipe2_cr_a } { \logical_pipe1_cr_a_ok \logical_pipe1_cr_a } + connect { \logical_pipe2_o_ok \logical_pipe2_o } { \logical_pipe1_o_ok \logical_pipe1_o } + connect { \logical_pipe2_logical_op__insn \logical_pipe2_logical_op__data_len \logical_pipe2_logical_op__is_signed \logical_pipe2_logical_op__is_32bit \logical_pipe2_logical_op__output_carry \logical_pipe2_logical_op__write_cr0 \logical_pipe2_logical_op__invert_out \logical_pipe2_logical_op__input_carry \logical_pipe2_logical_op__zero_a \logical_pipe2_logical_op__invert_in \logical_pipe2_logical_op__oe__ok \logical_pipe2_logical_op__oe__oe \logical_pipe2_logical_op__rc__ok \logical_pipe2_logical_op__rc__rc \logical_pipe2_logical_op__imm_data__ok \logical_pipe2_logical_op__imm_data__data \logical_pipe2_logical_op__fn_unit \logical_pipe2_logical_op__insn_type } { \logical_pipe1_logical_op__insn \logical_pipe1_logical_op__data_len \logical_pipe1_logical_op__is_signed \logical_pipe1_logical_op__is_32bit \logical_pipe1_logical_op__output_carry \logical_pipe1_logical_op__write_cr0 \logical_pipe1_logical_op__invert_out \logical_pipe1_logical_op__input_carry \logical_pipe1_logical_op__zero_a \logical_pipe1_logical_op__invert_in \logical_pipe1_logical_op__oe__ok \logical_pipe1_logical_op__oe__oe \logical_pipe1_logical_op__rc__ok \logical_pipe1_logical_op__rc__rc \logical_pipe1_logical_op__imm_data__ok \logical_pipe1_logical_op__imm_data__data \logical_pipe1_logical_op__fn_unit \logical_pipe1_logical_op__insn_type } + connect \logical_pipe2_muxid \logical_pipe1_muxid + connect \logical_pipe1_n_ready_i \logical_pipe2_p_ready_o + connect \logical_pipe2_p_valid_i \logical_pipe1_n_valid_o +end +attribute \src "libresoc.v:27697.1-28898.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0" +attribute \generator "nMigen" +module \alu_mul0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 29 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 output 21 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 3 \cr_a_ok + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 input 9 \mul_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \mul_op__fn_unit$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 10 \mul_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \mul_op__imm_data__data$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 11 \mul_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__imm_data__ok$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 19 \mul_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \mul_op__insn$61 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 8 \mul_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \mul_op__insn_type$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 17 \mul_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__is_32bit$59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 18 \mul_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__is_signed$60 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \mul_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__oe__oe$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 15 \mul_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__oe__ok$57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \mul_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__rc__ok$55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \mul_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__rc__rc$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 16 \mul_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__write_cr0$58 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \mul_pipe1_mul_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \mul_pipe1_mul_op__fn_unit$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \mul_pipe1_mul_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \mul_pipe1_mul_op__imm_data__data$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe1_mul_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe1_mul_op__imm_data__ok$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \mul_pipe1_mul_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \mul_pipe1_mul_op__insn$14 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \mul_pipe1_mul_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \mul_pipe1_mul_op__insn_type$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe1_mul_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe1_mul_op__is_32bit$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe1_mul_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe1_mul_op__is_signed$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe1_mul_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe1_mul_op__oe__oe$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe1_mul_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe1_mul_op__oe__ok$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe1_mul_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe1_mul_op__rc__ok$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe1_mul_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe1_mul_op__rc__rc$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe1_mul_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe1_mul_op__write_cr0$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \mul_pipe1_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \mul_pipe1_muxid$2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire \mul_pipe1_n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire \mul_pipe1_n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" + wire \mul_pipe1_neg_res + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" + wire \mul_pipe1_neg_res32 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" + wire \mul_pipe1_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" + wire \mul_pipe1_p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \mul_pipe1_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \mul_pipe1_ra$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \mul_pipe1_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \mul_pipe1_rb$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \mul_pipe1_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \mul_pipe1_xer_so$17 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \mul_pipe2_mul_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \mul_pipe2_mul_op__fn_unit$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \mul_pipe2_mul_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \mul_pipe2_mul_op__imm_data__data$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe2_mul_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe2_mul_op__imm_data__ok$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \mul_pipe2_mul_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \mul_pipe2_mul_op__insn$30 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \mul_pipe2_mul_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \mul_pipe2_mul_op__insn_type$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe2_mul_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe2_mul_op__is_32bit$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe2_mul_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe2_mul_op__is_signed$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe2_mul_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe2_mul_op__oe__oe$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe2_mul_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe2_mul_op__oe__ok$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe2_mul_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe2_mul_op__rc__ok$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe2_mul_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe2_mul_op__rc__rc$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe2_mul_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe2_mul_op__write_cr0$27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \mul_pipe2_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \mul_pipe2_muxid$18 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire \mul_pipe2_n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire \mul_pipe2_n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" + wire \mul_pipe2_neg_res + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" + wire \mul_pipe2_neg_res$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" + wire \mul_pipe2_neg_res32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24" + wire \mul_pipe2_neg_res32$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 129 \mul_pipe2_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" + wire \mul_pipe2_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" + wire \mul_pipe2_p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \mul_pipe2_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \mul_pipe2_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \mul_pipe2_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \mul_pipe2_xer_so$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \mul_pipe3_cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \mul_pipe3_cr_a_ok + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \mul_pipe3_mul_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \mul_pipe3_mul_op__fn_unit$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \mul_pipe3_mul_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \mul_pipe3_mul_op__imm_data__data$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe3_mul_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe3_mul_op__imm_data__ok$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \mul_pipe3_mul_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \mul_pipe3_mul_op__insn$46 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \mul_pipe3_mul_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \mul_pipe3_mul_op__insn_type$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe3_mul_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe3_mul_op__is_32bit$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe3_mul_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe3_mul_op__is_signed$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe3_mul_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe3_mul_op__oe__oe$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe3_mul_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe3_mul_op__oe__ok$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe3_mul_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe3_mul_op__rc__ok$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe3_mul_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe3_mul_op__rc__rc$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe3_mul_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe3_mul_op__write_cr0$43 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \mul_pipe3_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \mul_pipe3_muxid$34 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire \mul_pipe3_n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire \mul_pipe3_n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" + wire \mul_pipe3_neg_res + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24" + wire \mul_pipe3_neg_res32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 129 \mul_pipe3_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \mul_pipe3_o$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \mul_pipe3_o_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" + wire \mul_pipe3_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" + wire \mul_pipe3_p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \mul_pipe3_xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \mul_pipe3_xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \mul_pipe3_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \mul_pipe3_xer_so$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \mul_pipe3_xer_so_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid$49 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire input 7 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire output 6 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 20 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 2 \o_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" + wire output 28 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" + wire input 27 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 24 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 25 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 output 22 \xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 4 \xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 23 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 26 \xer_so$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 5 \xer_so_ok + attribute \module_not_derived 1 + attribute \src "libresoc.v:28726.13-28767.4" + cell \mul_pipe1 \mul_pipe1 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \mul_op__fn_unit \mul_pipe1_mul_op__fn_unit + connect \mul_op__fn_unit$3 \mul_pipe1_mul_op__fn_unit$4 + connect \mul_op__imm_data__data \mul_pipe1_mul_op__imm_data__data + connect \mul_op__imm_data__data$4 \mul_pipe1_mul_op__imm_data__data$5 + connect \mul_op__imm_data__ok \mul_pipe1_mul_op__imm_data__ok + connect \mul_op__imm_data__ok$5 \mul_pipe1_mul_op__imm_data__ok$6 + connect \mul_op__insn \mul_pipe1_mul_op__insn + connect \mul_op__insn$13 \mul_pipe1_mul_op__insn$14 + connect \mul_op__insn_type \mul_pipe1_mul_op__insn_type + connect \mul_op__insn_type$2 \mul_pipe1_mul_op__insn_type$3 + connect \mul_op__is_32bit \mul_pipe1_mul_op__is_32bit + connect \mul_op__is_32bit$11 \mul_pipe1_mul_op__is_32bit$12 + connect \mul_op__is_signed \mul_pipe1_mul_op__is_signed + connect \mul_op__is_signed$12 \mul_pipe1_mul_op__is_signed$13 + connect \mul_op__oe__oe \mul_pipe1_mul_op__oe__oe + connect \mul_op__oe__oe$8 \mul_pipe1_mul_op__oe__oe$9 + connect \mul_op__oe__ok \mul_pipe1_mul_op__oe__ok + connect \mul_op__oe__ok$9 \mul_pipe1_mul_op__oe__ok$10 + connect \mul_op__rc__ok \mul_pipe1_mul_op__rc__ok + connect \mul_op__rc__ok$7 \mul_pipe1_mul_op__rc__ok$8 + connect \mul_op__rc__rc \mul_pipe1_mul_op__rc__rc + connect \mul_op__rc__rc$6 \mul_pipe1_mul_op__rc__rc$7 + connect \mul_op__write_cr0 \mul_pipe1_mul_op__write_cr0 + connect \mul_op__write_cr0$10 \mul_pipe1_mul_op__write_cr0$11 + connect \muxid \mul_pipe1_muxid + connect \muxid$1 \mul_pipe1_muxid$2 + connect \n_ready_i \mul_pipe1_n_ready_i + connect \n_valid_o \mul_pipe1_n_valid_o + connect \neg_res \mul_pipe1_neg_res + connect \neg_res32 \mul_pipe1_neg_res32 + connect \p_ready_o \mul_pipe1_p_ready_o + connect \p_valid_i \mul_pipe1_p_valid_i + connect \ra \mul_pipe1_ra + connect \ra$14 \mul_pipe1_ra$15 + connect \rb \mul_pipe1_rb + connect \rb$15 \mul_pipe1_rb$16 + connect \xer_so \mul_pipe1_xer_so + connect \xer_so$16 \mul_pipe1_xer_so$17 + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:28768.13-28810.4" + cell \mul_pipe2 \mul_pipe2 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \mul_op__fn_unit \mul_pipe2_mul_op__fn_unit + connect \mul_op__fn_unit$3 \mul_pipe2_mul_op__fn_unit$20 + connect \mul_op__imm_data__data \mul_pipe2_mul_op__imm_data__data + connect \mul_op__imm_data__data$4 \mul_pipe2_mul_op__imm_data__data$21 + connect \mul_op__imm_data__ok \mul_pipe2_mul_op__imm_data__ok + connect \mul_op__imm_data__ok$5 \mul_pipe2_mul_op__imm_data__ok$22 + connect \mul_op__insn \mul_pipe2_mul_op__insn + connect \mul_op__insn$13 \mul_pipe2_mul_op__insn$30 + connect \mul_op__insn_type \mul_pipe2_mul_op__insn_type + connect \mul_op__insn_type$2 \mul_pipe2_mul_op__insn_type$19 + connect \mul_op__is_32bit \mul_pipe2_mul_op__is_32bit + connect \mul_op__is_32bit$11 \mul_pipe2_mul_op__is_32bit$28 + connect \mul_op__is_signed \mul_pipe2_mul_op__is_signed + connect \mul_op__is_signed$12 \mul_pipe2_mul_op__is_signed$29 + connect \mul_op__oe__oe \mul_pipe2_mul_op__oe__oe + connect \mul_op__oe__oe$8 \mul_pipe2_mul_op__oe__oe$25 + connect \mul_op__oe__ok \mul_pipe2_mul_op__oe__ok + connect \mul_op__oe__ok$9 \mul_pipe2_mul_op__oe__ok$26 + connect \mul_op__rc__ok \mul_pipe2_mul_op__rc__ok + connect \mul_op__rc__ok$7 \mul_pipe2_mul_op__rc__ok$24 + connect \mul_op__rc__rc \mul_pipe2_mul_op__rc__rc + connect \mul_op__rc__rc$6 \mul_pipe2_mul_op__rc__rc$23 + connect \mul_op__write_cr0 \mul_pipe2_mul_op__write_cr0 + connect \mul_op__write_cr0$10 \mul_pipe2_mul_op__write_cr0$27 + connect \muxid \mul_pipe2_muxid + connect \muxid$1 \mul_pipe2_muxid$18 + connect \n_ready_i \mul_pipe2_n_ready_i + connect \n_valid_o \mul_pipe2_n_valid_o + connect \neg_res \mul_pipe2_neg_res + connect \neg_res$15 \mul_pipe2_neg_res$32 + connect \neg_res32 \mul_pipe2_neg_res32 + connect \neg_res32$16 \mul_pipe2_neg_res32$33 + connect \o \mul_pipe2_o + connect \p_ready_o \mul_pipe2_p_ready_o + connect \p_valid_i \mul_pipe2_p_valid_i + connect \ra \mul_pipe2_ra + connect \rb \mul_pipe2_rb + connect \xer_so \mul_pipe2_xer_so + connect \xer_so$14 \mul_pipe2_xer_so$31 + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:28811.13-28856.4" + cell \mul_pipe3 \mul_pipe3 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cr_a \mul_pipe3_cr_a + connect \cr_a_ok \mul_pipe3_cr_a_ok + connect \mul_op__fn_unit \mul_pipe3_mul_op__fn_unit + connect \mul_op__fn_unit$3 \mul_pipe3_mul_op__fn_unit$36 + connect \mul_op__imm_data__data \mul_pipe3_mul_op__imm_data__data + connect \mul_op__imm_data__data$4 \mul_pipe3_mul_op__imm_data__data$37 + connect \mul_op__imm_data__ok \mul_pipe3_mul_op__imm_data__ok + connect \mul_op__imm_data__ok$5 \mul_pipe3_mul_op__imm_data__ok$38 + connect \mul_op__insn \mul_pipe3_mul_op__insn + connect \mul_op__insn$13 \mul_pipe3_mul_op__insn$46 + connect \mul_op__insn_type \mul_pipe3_mul_op__insn_type + connect \mul_op__insn_type$2 \mul_pipe3_mul_op__insn_type$35 + connect \mul_op__is_32bit \mul_pipe3_mul_op__is_32bit + connect \mul_op__is_32bit$11 \mul_pipe3_mul_op__is_32bit$44 + connect \mul_op__is_signed \mul_pipe3_mul_op__is_signed + connect \mul_op__is_signed$12 \mul_pipe3_mul_op__is_signed$45 + connect \mul_op__oe__oe \mul_pipe3_mul_op__oe__oe + connect \mul_op__oe__oe$8 \mul_pipe3_mul_op__oe__oe$41 + connect \mul_op__oe__ok \mul_pipe3_mul_op__oe__ok + connect \mul_op__oe__ok$9 \mul_pipe3_mul_op__oe__ok$42 + connect \mul_op__rc__ok \mul_pipe3_mul_op__rc__ok + connect \mul_op__rc__ok$7 \mul_pipe3_mul_op__rc__ok$40 + connect \mul_op__rc__rc \mul_pipe3_mul_op__rc__rc + connect \mul_op__rc__rc$6 \mul_pipe3_mul_op__rc__rc$39 + connect \mul_op__write_cr0 \mul_pipe3_mul_op__write_cr0 + connect \mul_op__write_cr0$10 \mul_pipe3_mul_op__write_cr0$43 + connect \muxid \mul_pipe3_muxid + connect \muxid$1 \mul_pipe3_muxid$34 + connect \n_ready_i \mul_pipe3_n_ready_i + connect \n_valid_o \mul_pipe3_n_valid_o + connect \neg_res \mul_pipe3_neg_res + connect \neg_res32 \mul_pipe3_neg_res32 + connect \o \mul_pipe3_o + connect \o$14 \mul_pipe3_o$47 + connect \o_ok \mul_pipe3_o_ok + connect \p_ready_o \mul_pipe3_p_ready_o + connect \p_valid_i \mul_pipe3_p_valid_i + connect \xer_ov \mul_pipe3_xer_ov + connect \xer_ov_ok \mul_pipe3_xer_ov_ok + connect \xer_so \mul_pipe3_xer_so + connect \xer_so$15 \mul_pipe3_xer_so$48 + connect \xer_so_ok \mul_pipe3_xer_so_ok + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:28857.10-28860.4" + cell \n$92 \n + connect \n_ready_i \n_ready_i + connect \n_valid_o \n_valid_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:28861.10-28864.4" + cell \p$91 \p + connect \p_ready_o \p_ready_o + connect \p_valid_i \p_valid_i + end + connect \muxid 2'00 + connect { \xer_so_ok \xer_so } { \mul_pipe3_xer_so_ok \mul_pipe3_xer_so$48 } + connect { \xer_ov_ok \xer_ov } { \mul_pipe3_xer_ov_ok \mul_pipe3_xer_ov } + connect { \cr_a_ok \cr_a } { \mul_pipe3_cr_a_ok \mul_pipe3_cr_a } + connect { \o_ok \o } { \mul_pipe3_o_ok \mul_pipe3_o$47 } + connect { \mul_op__insn$61 \mul_op__is_signed$60 \mul_op__is_32bit$59 \mul_op__write_cr0$58 \mul_op__oe__ok$57 \mul_op__oe__oe$56 \mul_op__rc__ok$55 \mul_op__rc__rc$54 \mul_op__imm_data__ok$53 \mul_op__imm_data__data$52 \mul_op__fn_unit$51 \mul_op__insn_type$50 } { \mul_pipe3_mul_op__insn$46 \mul_pipe3_mul_op__is_signed$45 \mul_pipe3_mul_op__is_32bit$44 \mul_pipe3_mul_op__write_cr0$43 \mul_pipe3_mul_op__oe__ok$42 \mul_pipe3_mul_op__oe__oe$41 \mul_pipe3_mul_op__rc__ok$40 \mul_pipe3_mul_op__rc__rc$39 \mul_pipe3_mul_op__imm_data__ok$38 \mul_pipe3_mul_op__imm_data__data$37 \mul_pipe3_mul_op__fn_unit$36 \mul_pipe3_mul_op__insn_type$35 } + connect \muxid$49 \mul_pipe3_muxid$34 + connect \mul_pipe3_n_ready_i \n_ready_i + connect \n_valid_o \mul_pipe3_n_valid_o + connect \mul_pipe1_xer_so$17 \xer_so$1 + connect \mul_pipe1_rb$16 \rb + connect \mul_pipe1_ra$15 \ra + connect { \mul_pipe1_mul_op__insn$14 \mul_pipe1_mul_op__is_signed$13 \mul_pipe1_mul_op__is_32bit$12 \mul_pipe1_mul_op__write_cr0$11 \mul_pipe1_mul_op__oe__ok$10 \mul_pipe1_mul_op__oe__oe$9 \mul_pipe1_mul_op__rc__ok$8 \mul_pipe1_mul_op__rc__rc$7 \mul_pipe1_mul_op__imm_data__ok$6 \mul_pipe1_mul_op__imm_data__data$5 \mul_pipe1_mul_op__fn_unit$4 \mul_pipe1_mul_op__insn_type$3 } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__oe__ok \mul_op__oe__oe \mul_op__rc__ok \mul_op__rc__rc \mul_op__imm_data__ok \mul_op__imm_data__data \mul_op__fn_unit \mul_op__insn_type } + connect \mul_pipe1_muxid$2 2'00 + connect \p_ready_o \mul_pipe1_p_ready_o + connect \mul_pipe1_p_valid_i \p_valid_i + connect \mul_pipe3_neg_res32 \mul_pipe2_neg_res32$33 + connect \mul_pipe3_neg_res \mul_pipe2_neg_res$32 + connect \mul_pipe3_xer_so \mul_pipe2_xer_so$31 + connect \mul_pipe3_o \mul_pipe2_o + connect { \mul_pipe3_mul_op__insn \mul_pipe3_mul_op__is_signed \mul_pipe3_mul_op__is_32bit \mul_pipe3_mul_op__write_cr0 \mul_pipe3_mul_op__oe__ok \mul_pipe3_mul_op__oe__oe \mul_pipe3_mul_op__rc__ok \mul_pipe3_mul_op__rc__rc \mul_pipe3_mul_op__imm_data__ok \mul_pipe3_mul_op__imm_data__data \mul_pipe3_mul_op__fn_unit \mul_pipe3_mul_op__insn_type } { \mul_pipe2_mul_op__insn$30 \mul_pipe2_mul_op__is_signed$29 \mul_pipe2_mul_op__is_32bit$28 \mul_pipe2_mul_op__write_cr0$27 \mul_pipe2_mul_op__oe__ok$26 \mul_pipe2_mul_op__oe__oe$25 \mul_pipe2_mul_op__rc__ok$24 \mul_pipe2_mul_op__rc__rc$23 \mul_pipe2_mul_op__imm_data__ok$22 \mul_pipe2_mul_op__imm_data__data$21 \mul_pipe2_mul_op__fn_unit$20 \mul_pipe2_mul_op__insn_type$19 } + connect \mul_pipe3_muxid \mul_pipe2_muxid$18 + connect \mul_pipe2_n_ready_i \mul_pipe3_p_ready_o + connect \mul_pipe3_p_valid_i \mul_pipe2_n_valid_o + connect \mul_pipe2_neg_res32 \mul_pipe1_neg_res32 + connect \mul_pipe2_neg_res \mul_pipe1_neg_res + connect \mul_pipe2_xer_so \mul_pipe1_xer_so + connect \mul_pipe2_rb \mul_pipe1_rb + connect \mul_pipe2_ra \mul_pipe1_ra + connect { \mul_pipe2_mul_op__insn \mul_pipe2_mul_op__is_signed \mul_pipe2_mul_op__is_32bit \mul_pipe2_mul_op__write_cr0 \mul_pipe2_mul_op__oe__ok \mul_pipe2_mul_op__oe__oe \mul_pipe2_mul_op__rc__ok \mul_pipe2_mul_op__rc__rc \mul_pipe2_mul_op__imm_data__ok \mul_pipe2_mul_op__imm_data__data \mul_pipe2_mul_op__fn_unit \mul_pipe2_mul_op__insn_type } { \mul_pipe1_mul_op__insn \mul_pipe1_mul_op__is_signed \mul_pipe1_mul_op__is_32bit \mul_pipe1_mul_op__write_cr0 \mul_pipe1_mul_op__oe__ok \mul_pipe1_mul_op__oe__oe \mul_pipe1_mul_op__rc__ok \mul_pipe1_mul_op__rc__rc \mul_pipe1_mul_op__imm_data__ok \mul_pipe1_mul_op__imm_data__data \mul_pipe1_mul_op__fn_unit \mul_pipe1_mul_op__insn_type } + connect \mul_pipe2_muxid \mul_pipe1_muxid + connect \mul_pipe1_n_ready_i \mul_pipe2_p_ready_o + connect \mul_pipe2_p_valid_i \mul_pipe1_n_valid_o +end +attribute \src "libresoc.v:28902.1-29923.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0" +attribute \generator "nMigen" +module \alu_shift_rot0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 34 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 output 25 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 3 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid$46 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire input 6 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire output 5 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 24 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 2 \o_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" + wire output 33 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" + wire input 32 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \pipe1_cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe1_cr_a_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \pipe1_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \pipe1_muxid$2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire \pipe1_n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire \pipe1_n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \pipe1_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe1_o_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" + wire \pipe1_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" + wire \pipe1_p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe1_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe1_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe1_rc + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \pipe1_sr_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \pipe1_sr_op__fn_unit$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe1_sr_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe1_sr_op__imm_data__data$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_sr_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_sr_op__imm_data__ok$6 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \pipe1_sr_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \pipe1_sr_op__input_carry$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_sr_op__input_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_sr_op__input_cr$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe1_sr_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe1_sr_op__insn$19 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe1_sr_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe1_sr_op__insn_type$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_sr_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_sr_op__invert_in$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_sr_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_sr_op__is_32bit$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_sr_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_sr_op__is_signed$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_sr_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_sr_op__oe__oe$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_sr_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_sr_op__oe__ok$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_sr_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_sr_op__output_carry$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_sr_op__output_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_sr_op__output_cr$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_sr_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_sr_op__rc__ok$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_sr_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_sr_op__rc__rc$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_sr_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_sr_op__write_cr0$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \pipe1_xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 \pipe1_xer_ca$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe1_xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe1_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \pipe1_xer_so$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe1_xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \pipe2_cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \pipe2_cr_a$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe2_cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe2_cr_a_ok$43 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \pipe2_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \pipe2_muxid$22 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire \pipe2_n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire \pipe2_n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \pipe2_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \pipe2_o$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe2_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe2_o_ok$41 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" + wire \pipe2_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" + wire \pipe2_p_valid_i + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \pipe2_sr_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \pipe2_sr_op__fn_unit$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe2_sr_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe2_sr_op__imm_data__data$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_sr_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_sr_op__imm_data__ok$26 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \pipe2_sr_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \pipe2_sr_op__input_carry$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_sr_op__input_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_sr_op__input_cr$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe2_sr_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe2_sr_op__insn$39 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe2_sr_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe2_sr_op__insn_type$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_sr_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_sr_op__invert_in$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_sr_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_sr_op__is_32bit$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_sr_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_sr_op__is_signed$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_sr_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_sr_op__oe__oe$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_sr_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_sr_op__oe__ok$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_sr_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_sr_op__output_carry$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_sr_op__output_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_sr_op__output_cr$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_sr_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_sr_op__rc__ok$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_sr_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_sr_op__rc__rc$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_sr_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_sr_op__write_cr0$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \pipe2_xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \pipe2_xer_ca$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe2_xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe2_xer_ca_ok$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe2_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe2_xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 27 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 28 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 29 \rc + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 input 8 \sr_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \sr_op__fn_unit$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 9 \sr_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \sr_op__imm_data__data$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \sr_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__imm_data__ok$50 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 17 \sr_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \sr_op__input_carry$57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 19 \sr_op__input_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__input_cr$59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 23 \sr_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \sr_op__insn$63 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 7 \sr_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \sr_op__insn_type$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 16 \sr_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__invert_in$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 21 \sr_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__is_32bit$61 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 22 \sr_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__is_signed$62 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \sr_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__oe__oe$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \sr_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__oe__ok$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 18 \sr_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__output_carry$58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 20 \sr_op__output_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__output_cr$60 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \sr_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__rc__ok$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 11 \sr_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__rc__rc$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 15 \sr_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__write_cr0$55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 output 26 \xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 input 31 \xer_ca$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 4 \xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 30 \xer_so + attribute \module_not_derived 1 + attribute \src "libresoc.v:29775.11-29778.4" + cell \n$109 \n + connect \n_ready_i \n_ready_i + connect \n_valid_o \n_valid_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:29779.11-29782.4" + cell \p$108 \p + connect \p_ready_o \p_ready_o + connect \p_valid_i \p_valid_i + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:29783.15-29839.4" + cell \pipe1$110 \pipe1 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cr_a \pipe1_cr_a + connect \cr_a_ok \pipe1_cr_a_ok + connect \muxid \pipe1_muxid + connect \muxid$1 \pipe1_muxid$2 + connect \n_ready_i \pipe1_n_ready_i + connect \n_valid_o \pipe1_n_valid_o + connect \o \pipe1_o + connect \o_ok \pipe1_o_ok + connect \p_ready_o \pipe1_p_ready_o + connect \p_valid_i \pipe1_p_valid_i + connect \ra \pipe1_ra + connect \rb \pipe1_rb + connect \rc \pipe1_rc + connect \sr_op__fn_unit \pipe1_sr_op__fn_unit + connect \sr_op__fn_unit$3 \pipe1_sr_op__fn_unit$4 + connect \sr_op__imm_data__data \pipe1_sr_op__imm_data__data + connect \sr_op__imm_data__data$4 \pipe1_sr_op__imm_data__data$5 + connect \sr_op__imm_data__ok \pipe1_sr_op__imm_data__ok + connect \sr_op__imm_data__ok$5 \pipe1_sr_op__imm_data__ok$6 + connect \sr_op__input_carry \pipe1_sr_op__input_carry + connect \sr_op__input_carry$12 \pipe1_sr_op__input_carry$13 + connect \sr_op__input_cr \pipe1_sr_op__input_cr + connect \sr_op__input_cr$14 \pipe1_sr_op__input_cr$15 + connect \sr_op__insn \pipe1_sr_op__insn + connect \sr_op__insn$18 \pipe1_sr_op__insn$19 + connect \sr_op__insn_type \pipe1_sr_op__insn_type + connect \sr_op__insn_type$2 \pipe1_sr_op__insn_type$3 + connect \sr_op__invert_in \pipe1_sr_op__invert_in + connect \sr_op__invert_in$11 \pipe1_sr_op__invert_in$12 + connect \sr_op__is_32bit \pipe1_sr_op__is_32bit + connect \sr_op__is_32bit$16 \pipe1_sr_op__is_32bit$17 + connect \sr_op__is_signed \pipe1_sr_op__is_signed + connect \sr_op__is_signed$17 \pipe1_sr_op__is_signed$18 + connect \sr_op__oe__oe \pipe1_sr_op__oe__oe + connect \sr_op__oe__oe$8 \pipe1_sr_op__oe__oe$9 + connect \sr_op__oe__ok \pipe1_sr_op__oe__ok + connect \sr_op__oe__ok$9 \pipe1_sr_op__oe__ok$10 + connect \sr_op__output_carry \pipe1_sr_op__output_carry + connect \sr_op__output_carry$13 \pipe1_sr_op__output_carry$14 + connect \sr_op__output_cr \pipe1_sr_op__output_cr + connect \sr_op__output_cr$15 \pipe1_sr_op__output_cr$16 + connect \sr_op__rc__ok \pipe1_sr_op__rc__ok + connect \sr_op__rc__ok$7 \pipe1_sr_op__rc__ok$8 + connect \sr_op__rc__rc \pipe1_sr_op__rc__rc + connect \sr_op__rc__rc$6 \pipe1_sr_op__rc__rc$7 + connect \sr_op__write_cr0 \pipe1_sr_op__write_cr0 + connect \sr_op__write_cr0$10 \pipe1_sr_op__write_cr0$11 + connect \xer_ca \pipe1_xer_ca + connect \xer_ca$20 \pipe1_xer_ca$21 + connect \xer_ca_ok \pipe1_xer_ca_ok + connect \xer_so \pipe1_xer_so + connect \xer_so$19 \pipe1_xer_so$20 + connect \xer_so_ok \pipe1_xer_so_ok + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:29840.15-29897.4" + cell \pipe2$115 \pipe2 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cr_a \pipe2_cr_a + connect \cr_a$21 \pipe2_cr_a$42 + connect \cr_a_ok \pipe2_cr_a_ok + connect \cr_a_ok$22 \pipe2_cr_a_ok$43 + connect \muxid \pipe2_muxid + connect \muxid$1 \pipe2_muxid$22 + connect \n_ready_i \pipe2_n_ready_i + connect \n_valid_o \pipe2_n_valid_o + connect \o \pipe2_o + connect \o$19 \pipe2_o$40 + connect \o_ok \pipe2_o_ok + connect \o_ok$20 \pipe2_o_ok$41 + connect \p_ready_o \pipe2_p_ready_o + connect \p_valid_i \pipe2_p_valid_i + connect \sr_op__fn_unit \pipe2_sr_op__fn_unit + connect \sr_op__fn_unit$3 \pipe2_sr_op__fn_unit$24 + connect \sr_op__imm_data__data \pipe2_sr_op__imm_data__data + connect \sr_op__imm_data__data$4 \pipe2_sr_op__imm_data__data$25 + connect \sr_op__imm_data__ok \pipe2_sr_op__imm_data__ok + connect \sr_op__imm_data__ok$5 \pipe2_sr_op__imm_data__ok$26 + connect \sr_op__input_carry \pipe2_sr_op__input_carry + connect \sr_op__input_carry$12 \pipe2_sr_op__input_carry$33 + connect \sr_op__input_cr \pipe2_sr_op__input_cr + connect \sr_op__input_cr$14 \pipe2_sr_op__input_cr$35 + connect \sr_op__insn \pipe2_sr_op__insn + connect \sr_op__insn$18 \pipe2_sr_op__insn$39 + connect \sr_op__insn_type \pipe2_sr_op__insn_type + connect \sr_op__insn_type$2 \pipe2_sr_op__insn_type$23 + connect \sr_op__invert_in \pipe2_sr_op__invert_in + connect \sr_op__invert_in$11 \pipe2_sr_op__invert_in$32 + connect \sr_op__is_32bit \pipe2_sr_op__is_32bit + connect \sr_op__is_32bit$16 \pipe2_sr_op__is_32bit$37 + connect \sr_op__is_signed \pipe2_sr_op__is_signed + connect \sr_op__is_signed$17 \pipe2_sr_op__is_signed$38 + connect \sr_op__oe__oe \pipe2_sr_op__oe__oe + connect \sr_op__oe__oe$8 \pipe2_sr_op__oe__oe$29 + connect \sr_op__oe__ok \pipe2_sr_op__oe__ok + connect \sr_op__oe__ok$9 \pipe2_sr_op__oe__ok$30 + connect \sr_op__output_carry \pipe2_sr_op__output_carry + connect \sr_op__output_carry$13 \pipe2_sr_op__output_carry$34 + connect \sr_op__output_cr \pipe2_sr_op__output_cr + connect \sr_op__output_cr$15 \pipe2_sr_op__output_cr$36 + connect \sr_op__rc__ok \pipe2_sr_op__rc__ok + connect \sr_op__rc__ok$7 \pipe2_sr_op__rc__ok$28 + connect \sr_op__rc__rc \pipe2_sr_op__rc__rc + connect \sr_op__rc__rc$6 \pipe2_sr_op__rc__rc$27 + connect \sr_op__write_cr0 \pipe2_sr_op__write_cr0 + connect \sr_op__write_cr0$10 \pipe2_sr_op__write_cr0$31 + connect \xer_ca \pipe2_xer_ca + connect \xer_ca$23 \pipe2_xer_ca$44 + connect \xer_ca_ok \pipe2_xer_ca_ok + connect \xer_ca_ok$24 \pipe2_xer_ca_ok$45 + connect \xer_so \pipe2_xer_so + connect \xer_so_ok \pipe2_xer_so_ok + end + connect \muxid 2'00 + connect { \xer_ca_ok \xer_ca } { \pipe2_xer_ca_ok$45 \pipe2_xer_ca$44 } + connect { \cr_a_ok \cr_a } { \pipe2_cr_a_ok$43 \pipe2_cr_a$42 } + connect { \o_ok \o } { \pipe2_o_ok$41 \pipe2_o$40 } + connect { \sr_op__insn$63 \sr_op__is_signed$62 \sr_op__is_32bit$61 \sr_op__output_cr$60 \sr_op__input_cr$59 \sr_op__output_carry$58 \sr_op__input_carry$57 \sr_op__invert_in$56 \sr_op__write_cr0$55 \sr_op__oe__ok$54 \sr_op__oe__oe$53 \sr_op__rc__ok$52 \sr_op__rc__rc$51 \sr_op__imm_data__ok$50 \sr_op__imm_data__data$49 \sr_op__fn_unit$48 \sr_op__insn_type$47 } { \pipe2_sr_op__insn$39 \pipe2_sr_op__is_signed$38 \pipe2_sr_op__is_32bit$37 \pipe2_sr_op__output_cr$36 \pipe2_sr_op__input_cr$35 \pipe2_sr_op__output_carry$34 \pipe2_sr_op__input_carry$33 \pipe2_sr_op__invert_in$32 \pipe2_sr_op__write_cr0$31 \pipe2_sr_op__oe__ok$30 \pipe2_sr_op__oe__oe$29 \pipe2_sr_op__rc__ok$28 \pipe2_sr_op__rc__rc$27 \pipe2_sr_op__imm_data__ok$26 \pipe2_sr_op__imm_data__data$25 \pipe2_sr_op__fn_unit$24 \pipe2_sr_op__insn_type$23 } + connect \muxid$46 \pipe2_muxid$22 + connect \pipe2_n_ready_i \n_ready_i + connect \n_valid_o \pipe2_n_valid_o + connect \pipe1_xer_ca$21 \xer_ca$1 + connect \pipe1_xer_so$20 \xer_so + connect \pipe1_rc \rc + connect \pipe1_rb \rb + connect \pipe1_ra \ra + connect { \pipe1_sr_op__insn$19 \pipe1_sr_op__is_signed$18 \pipe1_sr_op__is_32bit$17 \pipe1_sr_op__output_cr$16 \pipe1_sr_op__input_cr$15 \pipe1_sr_op__output_carry$14 \pipe1_sr_op__input_carry$13 \pipe1_sr_op__invert_in$12 \pipe1_sr_op__write_cr0$11 \pipe1_sr_op__oe__ok$10 \pipe1_sr_op__oe__oe$9 \pipe1_sr_op__rc__ok$8 \pipe1_sr_op__rc__rc$7 \pipe1_sr_op__imm_data__ok$6 \pipe1_sr_op__imm_data__data$5 \pipe1_sr_op__fn_unit$4 \pipe1_sr_op__insn_type$3 } { \sr_op__insn \sr_op__is_signed \sr_op__is_32bit \sr_op__output_cr \sr_op__input_cr \sr_op__output_carry \sr_op__input_carry \sr_op__invert_in \sr_op__write_cr0 \sr_op__oe__ok \sr_op__oe__oe \sr_op__rc__ok \sr_op__rc__rc \sr_op__imm_data__ok \sr_op__imm_data__data \sr_op__fn_unit \sr_op__insn_type } + connect \pipe1_muxid$2 2'00 + connect \p_ready_o \pipe1_p_ready_o + connect \pipe1_p_valid_i \p_valid_i + connect { \pipe2_xer_ca_ok \pipe2_xer_ca } { \pipe1_xer_ca_ok \pipe1_xer_ca } + connect { \pipe2_xer_so_ok \pipe2_xer_so } { \pipe1_xer_so_ok \pipe1_xer_so } + connect { \pipe2_cr_a_ok \pipe2_cr_a } { \pipe1_cr_a_ok \pipe1_cr_a } + connect { \pipe2_o_ok \pipe2_o } { \pipe1_o_ok \pipe1_o } + connect { \pipe2_sr_op__insn \pipe2_sr_op__is_signed \pipe2_sr_op__is_32bit \pipe2_sr_op__output_cr \pipe2_sr_op__input_cr \pipe2_sr_op__output_carry \pipe2_sr_op__input_carry \pipe2_sr_op__invert_in \pipe2_sr_op__write_cr0 \pipe2_sr_op__oe__ok \pipe2_sr_op__oe__oe \pipe2_sr_op__rc__ok \pipe2_sr_op__rc__rc \pipe2_sr_op__imm_data__ok \pipe2_sr_op__imm_data__data \pipe2_sr_op__fn_unit \pipe2_sr_op__insn_type } { \pipe1_sr_op__insn \pipe1_sr_op__is_signed \pipe1_sr_op__is_32bit \pipe1_sr_op__output_cr \pipe1_sr_op__input_cr \pipe1_sr_op__output_carry \pipe1_sr_op__input_carry \pipe1_sr_op__invert_in \pipe1_sr_op__write_cr0 \pipe1_sr_op__oe__ok \pipe1_sr_op__oe__oe \pipe1_sr_op__rc__ok \pipe1_sr_op__rc__rc \pipe1_sr_op__imm_data__ok \pipe1_sr_op__imm_data__data \pipe1_sr_op__fn_unit \pipe1_sr_op__insn_type } + connect \pipe2_muxid \pipe1_muxid + connect \pipe1_n_ready_i \pipe2_p_ready_o + connect \pipe2_p_valid_i \pipe1_n_valid_o +end +attribute \src "libresoc.v:29927.1-30477.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.alu_spr0" +attribute \generator "nMigen" +module \alu_spr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 28 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 16 \fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 22 \fast1$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 6 \fast1_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid$16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire input 9 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire output 8 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 14 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 2 \o_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" + wire output 27 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" + wire input 26 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \pipe_fast1$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe_fast1_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \pipe_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \pipe_muxid$6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire \pipe_n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire \pipe_n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \pipe_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe_o_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" + wire \pipe_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" + wire \pipe_p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_spr1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \pipe_spr1$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe_spr1_ok + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \pipe_spr_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \pipe_spr_op__fn_unit$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe_spr_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe_spr_op__insn$9 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe_spr_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe_spr_op__insn_type$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_spr_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_spr_op__is_32bit$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 \pipe_xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \pipe_xer_ca$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe_xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 \pipe_xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \pipe_xer_ov$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe_xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \pipe_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe_xer_so$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pipe_xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 20 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 15 \spr1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 21 \spr1$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 7 \spr1_ok + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 input 11 \spr_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \spr_op__fn_unit$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 12 \spr_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \spr_op__insn$19 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 10 \spr_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \spr_op__insn_type$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \spr_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \spr_op__is_32bit$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 output 19 \xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 input 25 \xer_ca$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 3 \xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 output 18 \xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 input 24 \xer_ov$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 4 \xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 17 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 23 \xer_so$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 5 \xer_so_ok + attribute \module_not_derived 1 + attribute \src "libresoc.v:30412.10-30415.4" + cell \n$63 \n + connect \n_ready_i \n_ready_i + connect \n_valid_o \n_valid_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:30416.10-30419.4" + cell \p$62 \p + connect \p_ready_o \p_ready_o + connect \p_valid_i \p_valid_i + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:30420.13-30455.4" + cell \pipe$64 \pipe + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \fast1 \pipe_fast1 + connect \fast1$7 \pipe_fast1$12 + connect \fast1_ok \pipe_fast1_ok + connect \muxid \pipe_muxid + connect \muxid$1 \pipe_muxid$6 + connect \n_ready_i \pipe_n_ready_i + connect \n_valid_o \pipe_n_valid_o + connect \o \pipe_o + connect \o_ok \pipe_o_ok + connect \p_ready_o \pipe_p_ready_o + connect \p_valid_i \pipe_p_valid_i + connect \ra \pipe_ra + connect \spr1 \pipe_spr1 + connect \spr1$6 \pipe_spr1$11 + connect \spr1_ok \pipe_spr1_ok + connect \spr_op__fn_unit \pipe_spr_op__fn_unit + connect \spr_op__fn_unit$3 \pipe_spr_op__fn_unit$8 + connect \spr_op__insn \pipe_spr_op__insn + connect \spr_op__insn$4 \pipe_spr_op__insn$9 + connect \spr_op__insn_type \pipe_spr_op__insn_type + connect \spr_op__insn_type$2 \pipe_spr_op__insn_type$7 + connect \spr_op__is_32bit \pipe_spr_op__is_32bit + connect \spr_op__is_32bit$5 \pipe_spr_op__is_32bit$10 + connect \xer_ca \pipe_xer_ca + connect \xer_ca$10 \pipe_xer_ca$15 + connect \xer_ca_ok \pipe_xer_ca_ok + connect \xer_ov \pipe_xer_ov + connect \xer_ov$9 \pipe_xer_ov$14 + connect \xer_ov_ok \pipe_xer_ov_ok + connect \xer_so \pipe_xer_so + connect \xer_so$8 \pipe_xer_so$13 + connect \xer_so_ok \pipe_xer_so_ok + end + connect \muxid 2'00 + connect { \xer_ca_ok \xer_ca } { \pipe_xer_ca_ok \pipe_xer_ca$15 } + connect { \xer_ov_ok \xer_ov } { \pipe_xer_ov_ok \pipe_xer_ov$14 } + connect { \xer_so_ok \xer_so } { \pipe_xer_so_ok \pipe_xer_so$13 } + connect { \fast1_ok \fast1 } { \pipe_fast1_ok \pipe_fast1$12 } + connect { \spr1_ok \spr1 } { \pipe_spr1_ok \pipe_spr1$11 } + connect { \o_ok \o } { \pipe_o_ok \pipe_o } + connect { \spr_op__is_32bit$20 \spr_op__insn$19 \spr_op__fn_unit$18 \spr_op__insn_type$17 } { \pipe_spr_op__is_32bit$10 \pipe_spr_op__insn$9 \pipe_spr_op__fn_unit$8 \pipe_spr_op__insn_type$7 } + connect \muxid$16 \pipe_muxid$6 + connect \pipe_n_ready_i \n_ready_i + connect \n_valid_o \pipe_n_valid_o + connect \pipe_xer_ca \xer_ca$5 + connect \pipe_xer_ov \xer_ov$4 + connect \pipe_xer_so \xer_so$3 + connect \pipe_fast1 \fast1$2 + connect \pipe_spr1 \spr1$1 + connect \pipe_ra \ra + connect { \pipe_spr_op__is_32bit \pipe_spr_op__insn \pipe_spr_op__fn_unit \pipe_spr_op__insn_type } { \spr_op__is_32bit \spr_op__insn \spr_op__fn_unit \spr_op__insn_type } + connect \pipe_muxid 2'00 + connect \p_ready_o \pipe_p_ready_o + connect \pipe_p_valid_i \p_valid_i +end +attribute \src "libresoc.v:30481.1-31342.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0" +attribute \generator "nMigen" +module \alu_trap0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 29 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 19 \fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 25 \fast1$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 3 \fast1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 20 \fast2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 26 \fast2$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 4 \fast2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 22 \msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 6 \msr_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid$29 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire input 8 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire output 7 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 21 \nia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 5 \nia_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 18 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 2 \o_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" + wire output 28 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" + wire input 27 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe1_fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe1_fast1$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe1_fast2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe1_fast2$16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \pipe1_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \pipe1_muxid$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire \pipe1_n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire \pipe1_n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" + wire \pipe1_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" + wire \pipe1_p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe1_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe1_ra$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe1_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe1_rb$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe1_trap_op__cia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe1_trap_op__cia$8 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \pipe1_trap_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute 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\enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe2_trap_op__insn_type$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_trap_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_trap_op__is_32bit$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 8 \pipe2_trap_op__ldst_exc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 8 \pipe2_trap_op__ldst_exc$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe2_trap_op__msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe2_trap_op__msr$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \pipe2_trap_op__trapaddr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \pipe2_trap_op__trapaddr$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 8 \pipe2_trap_op__traptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 8 \pipe2_trap_op__traptype$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 23 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 24 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 13 \trap_op__cia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \trap_op__cia$34 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 input 10 \trap_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \trap_op__fn_unit$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 11 \trap_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \trap_op__insn$32 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 9 \trap_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \trap_op__insn_type$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \trap_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \trap_op__is_32bit$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 8 input 17 \trap_op__ldst_exc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 8 \trap_op__ldst_exc$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 12 \trap_op__msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \trap_op__msr$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 input 16 \trap_op__trapaddr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \trap_op__trapaddr$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 8 input 15 \trap_op__traptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 8 \trap_op__traptype$36 + attribute \module_not_derived 1 + attribute \src "libresoc.v:31230.10-31233.4" + cell \n$31 \n + connect \n_ready_i \n_ready_i + connect \n_valid_o \n_valid_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:31234.10-31237.4" + cell \p$30 \p + connect \p_ready_o \p_ready_o + connect \p_valid_i \p_valid_i + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:31238.14-31273.4" + cell \pipe1$32 \pipe1 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \fast1 \pipe1_fast1 + connect \fast1$13 \pipe1_fast1$15 + connect \fast2 \pipe1_fast2 + connect \fast2$14 \pipe1_fast2$16 + connect \muxid \pipe1_muxid + connect \muxid$1 \pipe1_muxid$3 + connect \n_ready_i \pipe1_n_ready_i + connect \n_valid_o \pipe1_n_valid_o + connect \p_ready_o \pipe1_p_ready_o + connect \p_valid_i \pipe1_p_valid_i + connect \ra \pipe1_ra + connect \ra$11 \pipe1_ra$13 + connect \rb \pipe1_rb + connect \rb$12 \pipe1_rb$14 + connect \trap_op__cia \pipe1_trap_op__cia + connect \trap_op__cia$6 \pipe1_trap_op__cia$8 + connect \trap_op__fn_unit \pipe1_trap_op__fn_unit + connect \trap_op__fn_unit$3 \pipe1_trap_op__fn_unit$5 + connect \trap_op__insn \pipe1_trap_op__insn + connect \trap_op__insn$4 \pipe1_trap_op__insn$6 + connect \trap_op__insn_type \pipe1_trap_op__insn_type + connect \trap_op__insn_type$2 \pipe1_trap_op__insn_type$4 + connect \trap_op__is_32bit \pipe1_trap_op__is_32bit + connect \trap_op__is_32bit$7 \pipe1_trap_op__is_32bit$9 + connect \trap_op__ldst_exc \pipe1_trap_op__ldst_exc + connect \trap_op__ldst_exc$10 \pipe1_trap_op__ldst_exc$12 + connect \trap_op__msr \pipe1_trap_op__msr + connect \trap_op__msr$5 \pipe1_trap_op__msr$7 + connect \trap_op__trapaddr \pipe1_trap_op__trapaddr + connect \trap_op__trapaddr$9 \pipe1_trap_op__trapaddr$11 + connect \trap_op__traptype \pipe1_trap_op__traptype + connect \trap_op__traptype$8 \pipe1_trap_op__traptype$10 + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:31274.14-31315.4" + cell \pipe2$35 \pipe2 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \fast1 \pipe2_fast1 + connect \fast1$11 \pipe2_fast1$27 + connect \fast1_ok \pipe2_fast1_ok + connect \fast2 \pipe2_fast2 + connect \fast2$12 \pipe2_fast2$28 + connect \fast2_ok \pipe2_fast2_ok + connect \msr \pipe2_msr + connect \msr_ok \pipe2_msr_ok + connect \muxid \pipe2_muxid + connect \muxid$1 \pipe2_muxid$17 + connect \n_ready_i \pipe2_n_ready_i + connect \n_valid_o \pipe2_n_valid_o + connect \nia \pipe2_nia + connect \nia_ok \pipe2_nia_ok + connect \o \pipe2_o + connect \o_ok \pipe2_o_ok + connect \p_ready_o \pipe2_p_ready_o + connect \p_valid_i \pipe2_p_valid_i + connect \ra \pipe2_ra + connect \rb \pipe2_rb + connect \trap_op__cia \pipe2_trap_op__cia + connect \trap_op__cia$6 \pipe2_trap_op__cia$22 + connect \trap_op__fn_unit \pipe2_trap_op__fn_unit + connect \trap_op__fn_unit$3 \pipe2_trap_op__fn_unit$19 + connect \trap_op__insn \pipe2_trap_op__insn + connect \trap_op__insn$4 \pipe2_trap_op__insn$20 + connect \trap_op__insn_type \pipe2_trap_op__insn_type + connect \trap_op__insn_type$2 \pipe2_trap_op__insn_type$18 + connect \trap_op__is_32bit \pipe2_trap_op__is_32bit + connect \trap_op__is_32bit$7 \pipe2_trap_op__is_32bit$23 + connect \trap_op__ldst_exc \pipe2_trap_op__ldst_exc + connect \trap_op__ldst_exc$10 \pipe2_trap_op__ldst_exc$26 + connect \trap_op__msr \pipe2_trap_op__msr + connect \trap_op__msr$5 \pipe2_trap_op__msr$21 + connect \trap_op__trapaddr \pipe2_trap_op__trapaddr + connect \trap_op__trapaddr$9 \pipe2_trap_op__trapaddr$25 + connect \trap_op__traptype \pipe2_trap_op__traptype + connect \trap_op__traptype$8 \pipe2_trap_op__traptype$24 + end + connect \muxid 2'00 + connect { \msr_ok \msr } { \pipe2_msr_ok \pipe2_msr } + connect { \nia_ok \nia } { \pipe2_nia_ok \pipe2_nia } + connect { \fast2_ok \fast2 } { \pipe2_fast2_ok \pipe2_fast2$28 } + connect { \fast1_ok \fast1 } { \pipe2_fast1_ok \pipe2_fast1$27 } + connect { \o_ok \o } { \pipe2_o_ok \pipe2_o } + connect { \trap_op__ldst_exc$38 \trap_op__trapaddr$37 \trap_op__traptype$36 \trap_op__is_32bit$35 \trap_op__cia$34 \trap_op__msr$33 \trap_op__insn$32 \trap_op__fn_unit$31 \trap_op__insn_type$30 } { \pipe2_trap_op__ldst_exc$26 \pipe2_trap_op__trapaddr$25 \pipe2_trap_op__traptype$24 \pipe2_trap_op__is_32bit$23 \pipe2_trap_op__cia$22 \pipe2_trap_op__msr$21 \pipe2_trap_op__insn$20 \pipe2_trap_op__fn_unit$19 \pipe2_trap_op__insn_type$18 } + connect \muxid$29 \pipe2_muxid$17 + connect \pipe2_n_ready_i \n_ready_i + connect \n_valid_o \pipe2_n_valid_o + connect \pipe1_fast2$16 \fast2$2 + connect \pipe1_fast1$15 \fast1$1 + connect \pipe1_rb$14 \rb + connect \pipe1_ra$13 \ra + connect { \pipe1_trap_op__ldst_exc$12 \pipe1_trap_op__trapaddr$11 \pipe1_trap_op__traptype$10 \pipe1_trap_op__is_32bit$9 \pipe1_trap_op__cia$8 \pipe1_trap_op__msr$7 \pipe1_trap_op__insn$6 \pipe1_trap_op__fn_unit$5 \pipe1_trap_op__insn_type$4 } { \trap_op__ldst_exc \trap_op__trapaddr \trap_op__traptype \trap_op__is_32bit \trap_op__cia \trap_op__msr \trap_op__insn \trap_op__fn_unit \trap_op__insn_type } + connect \pipe1_muxid$3 2'00 + connect \p_ready_o \pipe1_p_ready_o + connect \pipe1_p_valid_i \p_valid_i + connect \pipe2_fast2 \pipe1_fast2 + connect \pipe2_fast1 \pipe1_fast1 + connect \pipe2_rb \pipe1_rb + connect \pipe2_ra \pipe1_ra + connect { \pipe2_trap_op__ldst_exc \pipe2_trap_op__trapaddr \pipe2_trap_op__traptype \pipe2_trap_op__is_32bit \pipe2_trap_op__cia \pipe2_trap_op__msr \pipe2_trap_op__insn \pipe2_trap_op__fn_unit \pipe2_trap_op__insn_type } { \pipe1_trap_op__ldst_exc \pipe1_trap_op__trapaddr \pipe1_trap_op__traptype \pipe1_trap_op__is_32bit \pipe1_trap_op__cia \pipe1_trap_op__msr \pipe1_trap_op__insn \pipe1_trap_op__fn_unit \pipe1_trap_op__insn_type } + connect \pipe2_muxid \pipe1_muxid + connect \pipe1_n_ready_i \pipe2_p_ready_o + connect \pipe2_p_valid_i \pipe1_n_valid_o +end +attribute \src "libresoc.v:31346.1-31404.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alui_l" +attribute \generator "nMigen" +module \alui_l + attribute \src "libresoc.v:31347.7-31347.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:31392.3-31400.6" + wire $0\q_int$next[0:0]$992 + attribute \src "libresoc.v:31390.3-31391.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:31392.3-31400.6" + wire $1\q_int$next[0:0]$993 + attribute \src "libresoc.v:31371.7-31371.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:31382.17-31382.96" + wire $and$libresoc.v:31382$982_Y + attribute \src "libresoc.v:31387.17-31387.96" + wire $and$libresoc.v:31387$987_Y + attribute \src "libresoc.v:31384.18-31384.94" + wire $not$libresoc.v:31384$984_Y + attribute \src "libresoc.v:31386.17-31386.93" + wire $not$libresoc.v:31386$986_Y + attribute \src "libresoc.v:31389.17-31389.93" + wire $not$libresoc.v:31389$989_Y + attribute \src "libresoc.v:31383.18-31383.99" + wire $or$libresoc.v:31383$983_Y + attribute \src "libresoc.v:31385.18-31385.100" + wire $or$libresoc.v:31385$985_Y + attribute \src "libresoc.v:31388.17-31388.98" + wire $or$libresoc.v:31388$988_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 1 \coresync_rst + attribute \src "libresoc.v:31347.7-31347.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire output 2 \q_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" + wire \qlq_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \qn_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire input 3 \r_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire input 4 \s_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:31382$982 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:31382$982_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:31387$987 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:31387$987_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:31384$984 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alui + connect \Y $not$libresoc.v:31384$984_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:31386$986 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alui + connect \Y $not$libresoc.v:31386$986_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:31389$989 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alui + connect \Y $not$libresoc.v:31389$989_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:31383$983 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_alui + connect \Y $or$libresoc.v:31383$983_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:31385$985 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alui + connect \B \q_int + connect \Y $or$libresoc.v:31385$985_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:31388$988 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_alui + connect \Y $or$libresoc.v:31388$988_Y + end + attribute \src "libresoc.v:31347.7-31347.20" + process $proc$libresoc.v:31347$994 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:31371.7-31371.19" + process $proc$libresoc.v:31371$995 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:31390.3-31391.27" + process $proc$libresoc.v:31390$990 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:31392.3-31400.6" + process $proc$libresoc.v:31392$991 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$992 $1\q_int$next[0:0]$993 + attribute \src "libresoc.v:31393.5-31393.29" + switch \initial + attribute \src "libresoc.v:31393.9-31393.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$993 1'0 + case + assign $1\q_int$next[0:0]$993 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$992 + end + connect \$9 $and$libresoc.v:31382$982_Y + connect \$11 $or$libresoc.v:31383$983_Y + connect \$13 $not$libresoc.v:31384$984_Y + connect \$15 $or$libresoc.v:31385$985_Y + connect \$1 $not$libresoc.v:31386$986_Y + connect \$3 $and$libresoc.v:31387$987_Y + connect \$5 $or$libresoc.v:31388$988_Y + connect \$7 $not$libresoc.v:31389$989_Y + connect \qlq_alui \$15 + connect \qn_alui \$13 + connect \q_alui \$11 +end +attribute \src "libresoc.v:31408.1-31466.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alui_l" +attribute \generator "nMigen" +module \alui_l$106 + attribute \src "libresoc.v:31409.7-31409.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:31454.3-31462.6" + wire $0\q_int$next[0:0]$1006 + attribute \src "libresoc.v:31452.3-31453.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:31454.3-31462.6" + wire $1\q_int$next[0:0]$1007 + attribute \src "libresoc.v:31433.7-31433.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:31444.17-31444.96" + wire $and$libresoc.v:31444$996_Y + attribute \src "libresoc.v:31449.17-31449.96" + wire $and$libresoc.v:31449$1001_Y + attribute \src "libresoc.v:31446.18-31446.94" + wire $not$libresoc.v:31446$998_Y + attribute \src "libresoc.v:31448.17-31448.93" + wire $not$libresoc.v:31448$1000_Y + attribute \src "libresoc.v:31451.17-31451.93" + wire $not$libresoc.v:31451$1003_Y + attribute \src "libresoc.v:31445.18-31445.99" + wire $or$libresoc.v:31445$997_Y + attribute \src "libresoc.v:31447.18-31447.100" + wire $or$libresoc.v:31447$999_Y + attribute \src "libresoc.v:31450.17-31450.98" + wire $or$libresoc.v:31450$1002_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 1 \coresync_rst + attribute \src "libresoc.v:31409.7-31409.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire output 2 \q_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" + wire \qlq_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \qn_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire input 3 \r_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire input 4 \s_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:31444$996 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:31444$996_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:31449$1001 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:31449$1001_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:31446$998 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alui + connect \Y $not$libresoc.v:31446$998_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:31448$1000 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alui + connect \Y $not$libresoc.v:31448$1000_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:31451$1003 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alui + connect \Y $not$libresoc.v:31451$1003_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:31445$997 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_alui + connect \Y $or$libresoc.v:31445$997_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:31447$999 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alui + connect \B \q_int + connect \Y $or$libresoc.v:31447$999_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:31450$1002 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_alui + connect \Y $or$libresoc.v:31450$1002_Y + end + attribute \src "libresoc.v:31409.7-31409.20" + process $proc$libresoc.v:31409$1008 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:31433.7-31433.19" + process $proc$libresoc.v:31433$1009 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:31452.3-31453.27" + process $proc$libresoc.v:31452$1004 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:31454.3-31462.6" + process $proc$libresoc.v:31454$1005 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$1006 $1\q_int$next[0:0]$1007 + attribute \src "libresoc.v:31455.5-31455.29" + switch \initial + attribute \src "libresoc.v:31455.9-31455.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$1007 1'0 + case + assign $1\q_int$next[0:0]$1007 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$1006 + end + connect \$9 $and$libresoc.v:31444$996_Y + connect \$11 $or$libresoc.v:31445$997_Y + connect \$13 $not$libresoc.v:31446$998_Y + connect \$15 $or$libresoc.v:31447$999_Y + connect \$1 $not$libresoc.v:31448$1000_Y + connect \$3 $and$libresoc.v:31449$1001_Y + connect \$5 $or$libresoc.v:31450$1002_Y + connect \$7 $not$libresoc.v:31451$1003_Y + connect \qlq_alui \$15 + connect \qn_alui \$13 + connect \q_alui \$11 +end +attribute \src "libresoc.v:31470.1-31528.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alui_l" +attribute \generator "nMigen" +module \alui_l$124 + attribute \src "libresoc.v:31471.7-31471.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:31516.3-31524.6" + wire $0\q_int$next[0:0]$1020 + attribute \src "libresoc.v:31514.3-31515.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:31516.3-31524.6" + wire $1\q_int$next[0:0]$1021 + attribute \src "libresoc.v:31495.7-31495.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:31506.17-31506.96" + wire $and$libresoc.v:31506$1010_Y + attribute \src "libresoc.v:31511.17-31511.96" + wire $and$libresoc.v:31511$1015_Y + attribute \src "libresoc.v:31508.18-31508.94" + wire $not$libresoc.v:31508$1012_Y + attribute \src "libresoc.v:31510.17-31510.93" + wire $not$libresoc.v:31510$1014_Y + attribute \src "libresoc.v:31513.17-31513.93" + wire $not$libresoc.v:31513$1017_Y + attribute \src "libresoc.v:31507.18-31507.99" + wire $or$libresoc.v:31507$1011_Y + attribute \src "libresoc.v:31509.18-31509.100" + wire $or$libresoc.v:31509$1013_Y + attribute \src "libresoc.v:31512.17-31512.98" + wire $or$libresoc.v:31512$1016_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 1 \coresync_rst + attribute \src "libresoc.v:31471.7-31471.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire output 2 \q_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" + wire \qlq_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \qn_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire input 3 \r_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire input 4 \s_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:31506$1010 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:31506$1010_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:31511$1015 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:31511$1015_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:31508$1012 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alui + connect \Y $not$libresoc.v:31508$1012_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:31510$1014 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alui + connect \Y $not$libresoc.v:31510$1014_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:31513$1017 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alui + connect \Y $not$libresoc.v:31513$1017_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:31507$1011 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_alui + connect \Y $or$libresoc.v:31507$1011_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:31509$1013 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alui + connect \B \q_int + connect \Y $or$libresoc.v:31509$1013_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:31512$1016 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_alui + connect \Y $or$libresoc.v:31512$1016_Y + end + attribute \src "libresoc.v:31471.7-31471.20" + process $proc$libresoc.v:31471$1022 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:31495.7-31495.19" + process $proc$libresoc.v:31495$1023 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:31514.3-31515.27" + process $proc$libresoc.v:31514$1018 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:31516.3-31524.6" + process $proc$libresoc.v:31516$1019 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$1020 $1\q_int$next[0:0]$1021 + attribute \src "libresoc.v:31517.5-31517.29" + switch \initial + attribute \src "libresoc.v:31517.9-31517.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$1021 1'0 + case + assign $1\q_int$next[0:0]$1021 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$1020 + end + connect \$9 $and$libresoc.v:31506$1010_Y + connect \$11 $or$libresoc.v:31507$1011_Y + connect \$13 $not$libresoc.v:31508$1012_Y + connect \$15 $or$libresoc.v:31509$1013_Y + connect \$1 $not$libresoc.v:31510$1014_Y + connect \$3 $and$libresoc.v:31511$1015_Y + connect \$5 $or$libresoc.v:31512$1016_Y + connect \$7 $not$libresoc.v:31513$1017_Y + connect \qlq_alui \$15 + connect \qn_alui \$13 + connect \q_alui \$11 +end +attribute \src "libresoc.v:31532.1-31590.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.alui_l" +attribute \generator "nMigen" +module \alui_l$15 + attribute \src "libresoc.v:31533.7-31533.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:31578.3-31586.6" + wire $0\q_int$next[0:0]$1034 + attribute \src "libresoc.v:31576.3-31577.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:31578.3-31586.6" + wire $1\q_int$next[0:0]$1035 + attribute \src "libresoc.v:31557.7-31557.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:31568.17-31568.96" + wire $and$libresoc.v:31568$1024_Y + attribute \src "libresoc.v:31573.17-31573.96" + wire $and$libresoc.v:31573$1029_Y + attribute \src "libresoc.v:31570.18-31570.94" + wire $not$libresoc.v:31570$1026_Y + attribute \src "libresoc.v:31572.17-31572.93" + wire $not$libresoc.v:31572$1028_Y + attribute \src "libresoc.v:31575.17-31575.93" + wire $not$libresoc.v:31575$1031_Y + attribute \src "libresoc.v:31569.18-31569.99" + wire $or$libresoc.v:31569$1025_Y + attribute \src "libresoc.v:31571.18-31571.100" + wire $or$libresoc.v:31571$1027_Y + attribute \src "libresoc.v:31574.17-31574.98" + wire $or$libresoc.v:31574$1030_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 1 \coresync_rst + attribute \src "libresoc.v:31533.7-31533.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire output 2 \q_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" + wire \qlq_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \qn_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire input 3 \r_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire input 4 \s_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:31568$1024 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:31568$1024_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:31573$1029 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:31573$1029_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:31570$1026 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alui + connect \Y $not$libresoc.v:31570$1026_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:31572$1028 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alui + connect \Y $not$libresoc.v:31572$1028_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:31575$1031 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alui + connect \Y $not$libresoc.v:31575$1031_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:31569$1025 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_alui + connect \Y $or$libresoc.v:31569$1025_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:31571$1027 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alui + connect \B \q_int + connect \Y $or$libresoc.v:31571$1027_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:31574$1030 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_alui + connect \Y $or$libresoc.v:31574$1030_Y + end + attribute \src "libresoc.v:31533.7-31533.20" + process $proc$libresoc.v:31533$1036 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:31557.7-31557.19" + process $proc$libresoc.v:31557$1037 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:31576.3-31577.27" + process $proc$libresoc.v:31576$1032 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:31578.3-31586.6" + process $proc$libresoc.v:31578$1033 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$1034 $1\q_int$next[0:0]$1035 + attribute \src "libresoc.v:31579.5-31579.29" + switch \initial + attribute \src "libresoc.v:31579.9-31579.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$1035 1'0 + case + assign $1\q_int$next[0:0]$1035 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$1034 + end + connect \$9 $and$libresoc.v:31568$1024_Y + connect \$11 $or$libresoc.v:31569$1025_Y + connect \$13 $not$libresoc.v:31570$1026_Y + connect \$15 $or$libresoc.v:31571$1027_Y + connect \$1 $not$libresoc.v:31572$1028_Y + connect \$3 $and$libresoc.v:31573$1029_Y + connect \$5 $or$libresoc.v:31574$1030_Y + connect \$7 $not$libresoc.v:31575$1031_Y + connect \qlq_alui \$15 + connect \qn_alui \$13 + connect \q_alui \$11 +end +attribute \src "libresoc.v:31594.1-31652.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.alui_l" +attribute \generator "nMigen" +module \alui_l$28 + attribute \src "libresoc.v:31595.7-31595.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:31640.3-31648.6" + wire $0\q_int$next[0:0]$1048 + attribute \src "libresoc.v:31638.3-31639.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:31640.3-31648.6" + wire $1\q_int$next[0:0]$1049 + attribute \src "libresoc.v:31619.7-31619.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:31630.17-31630.96" + wire $and$libresoc.v:31630$1038_Y + attribute \src "libresoc.v:31635.17-31635.96" + wire $and$libresoc.v:31635$1043_Y + attribute \src "libresoc.v:31632.18-31632.94" + wire $not$libresoc.v:31632$1040_Y + attribute \src "libresoc.v:31634.17-31634.93" + wire $not$libresoc.v:31634$1042_Y + attribute \src "libresoc.v:31637.17-31637.93" + wire $not$libresoc.v:31637$1045_Y + attribute \src "libresoc.v:31631.18-31631.99" + wire $or$libresoc.v:31631$1039_Y + attribute \src "libresoc.v:31633.18-31633.100" + wire $or$libresoc.v:31633$1041_Y + attribute \src "libresoc.v:31636.17-31636.98" + wire $or$libresoc.v:31636$1044_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 1 \coresync_rst + attribute \src "libresoc.v:31595.7-31595.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire output 2 \q_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" + wire \qlq_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \qn_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire input 3 \r_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire input 4 \s_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:31630$1038 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:31630$1038_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:31635$1043 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:31635$1043_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:31632$1040 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alui + connect \Y $not$libresoc.v:31632$1040_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:31634$1042 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alui + connect \Y $not$libresoc.v:31634$1042_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:31637$1045 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alui + connect \Y $not$libresoc.v:31637$1045_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:31631$1039 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_alui + connect \Y $or$libresoc.v:31631$1039_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:31633$1041 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alui + connect \B \q_int + connect \Y $or$libresoc.v:31633$1041_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:31636$1044 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_alui + connect \Y $or$libresoc.v:31636$1044_Y + end + attribute \src "libresoc.v:31595.7-31595.20" + process $proc$libresoc.v:31595$1050 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:31619.7-31619.19" + process $proc$libresoc.v:31619$1051 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:31638.3-31639.27" + process $proc$libresoc.v:31638$1046 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:31640.3-31648.6" + process $proc$libresoc.v:31640$1047 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$1048 $1\q_int$next[0:0]$1049 + attribute \src "libresoc.v:31641.5-31641.29" + switch \initial + attribute \src "libresoc.v:31641.9-31641.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$1049 1'0 + case + assign $1\q_int$next[0:0]$1049 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$1048 + end + connect \$9 $and$libresoc.v:31630$1038_Y + connect \$11 $or$libresoc.v:31631$1039_Y + connect \$13 $not$libresoc.v:31632$1040_Y + connect \$15 $or$libresoc.v:31633$1041_Y + connect \$1 $not$libresoc.v:31634$1042_Y + connect \$3 $and$libresoc.v:31635$1043_Y + connect \$5 $or$libresoc.v:31636$1044_Y + connect \$7 $not$libresoc.v:31637$1045_Y + connect \qlq_alui \$15 + connect \qn_alui \$13 + connect \q_alui \$11 +end +attribute \src "libresoc.v:31656.1-31714.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alui_l" +attribute \generator "nMigen" +module \alui_l$44 + attribute \src "libresoc.v:31657.7-31657.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:31702.3-31710.6" + wire $0\q_int$next[0:0]$1062 + attribute \src "libresoc.v:31700.3-31701.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:31702.3-31710.6" + wire $1\q_int$next[0:0]$1063 + attribute \src "libresoc.v:31681.7-31681.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:31692.17-31692.96" + wire $and$libresoc.v:31692$1052_Y + attribute \src "libresoc.v:31697.17-31697.96" + wire $and$libresoc.v:31697$1057_Y + attribute \src "libresoc.v:31694.18-31694.94" + wire $not$libresoc.v:31694$1054_Y + attribute \src "libresoc.v:31696.17-31696.93" + wire $not$libresoc.v:31696$1056_Y + attribute \src "libresoc.v:31699.17-31699.93" + wire $not$libresoc.v:31699$1059_Y + attribute \src "libresoc.v:31693.18-31693.99" + wire $or$libresoc.v:31693$1053_Y + attribute \src "libresoc.v:31695.18-31695.100" + wire $or$libresoc.v:31695$1055_Y + attribute \src "libresoc.v:31698.17-31698.98" + wire $or$libresoc.v:31698$1058_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 1 \coresync_rst + attribute \src "libresoc.v:31657.7-31657.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire output 2 \q_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" + wire \qlq_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \qn_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire input 3 \r_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire input 4 \s_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:31692$1052 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:31692$1052_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:31697$1057 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:31697$1057_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:31694$1054 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alui + connect \Y $not$libresoc.v:31694$1054_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:31696$1056 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alui + connect \Y $not$libresoc.v:31696$1056_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:31699$1059 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alui + connect \Y $not$libresoc.v:31699$1059_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:31693$1053 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_alui + connect \Y $or$libresoc.v:31693$1053_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:31695$1055 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alui + connect \B \q_int + connect \Y $or$libresoc.v:31695$1055_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:31698$1058 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_alui + connect \Y $or$libresoc.v:31698$1058_Y + end + attribute \src "libresoc.v:31657.7-31657.20" + process $proc$libresoc.v:31657$1064 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:31681.7-31681.19" + process $proc$libresoc.v:31681$1065 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:31700.3-31701.27" + process $proc$libresoc.v:31700$1060 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:31702.3-31710.6" + process $proc$libresoc.v:31702$1061 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$1062 $1\q_int$next[0:0]$1063 + attribute \src "libresoc.v:31703.5-31703.29" + switch \initial + attribute \src "libresoc.v:31703.9-31703.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$1063 1'0 + case + assign $1\q_int$next[0:0]$1063 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$1062 + end + connect \$9 $and$libresoc.v:31692$1052_Y + connect \$11 $or$libresoc.v:31693$1053_Y + connect \$13 $not$libresoc.v:31694$1054_Y + connect \$15 $or$libresoc.v:31695$1055_Y + connect \$1 $not$libresoc.v:31696$1056_Y + connect \$3 $and$libresoc.v:31697$1057_Y + connect \$5 $or$libresoc.v:31698$1058_Y + connect \$7 $not$libresoc.v:31699$1059_Y + connect \qlq_alui \$15 + connect \qn_alui \$13 + connect \q_alui \$11 +end +attribute \src "libresoc.v:31718.1-31776.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alui_l" +attribute \generator "nMigen" +module \alui_l$60 + attribute \src "libresoc.v:31719.7-31719.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:31764.3-31772.6" + wire $0\q_int$next[0:0]$1076 + attribute \src "libresoc.v:31762.3-31763.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:31764.3-31772.6" + wire $1\q_int$next[0:0]$1077 + attribute \src "libresoc.v:31743.7-31743.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:31754.17-31754.96" + wire $and$libresoc.v:31754$1066_Y + attribute \src "libresoc.v:31759.17-31759.96" + wire $and$libresoc.v:31759$1071_Y + attribute \src "libresoc.v:31756.18-31756.94" + wire $not$libresoc.v:31756$1068_Y + attribute \src "libresoc.v:31758.17-31758.93" + wire $not$libresoc.v:31758$1070_Y + attribute \src "libresoc.v:31761.17-31761.93" + wire $not$libresoc.v:31761$1073_Y + attribute \src "libresoc.v:31755.18-31755.99" + wire $or$libresoc.v:31755$1067_Y + attribute \src "libresoc.v:31757.18-31757.100" + wire $or$libresoc.v:31757$1069_Y + attribute \src "libresoc.v:31760.17-31760.98" + wire $or$libresoc.v:31760$1072_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 1 \coresync_rst + attribute \src "libresoc.v:31719.7-31719.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire output 2 \q_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" + wire \qlq_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \qn_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire input 3 \r_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire input 4 \s_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:31754$1066 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:31754$1066_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:31759$1071 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:31759$1071_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:31756$1068 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alui + connect \Y $not$libresoc.v:31756$1068_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:31758$1070 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alui + connect \Y $not$libresoc.v:31758$1070_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:31761$1073 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alui + connect \Y $not$libresoc.v:31761$1073_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:31755$1067 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_alui + connect \Y $or$libresoc.v:31755$1067_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:31757$1069 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alui + connect \B \q_int + connect \Y $or$libresoc.v:31757$1069_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:31760$1072 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_alui + connect \Y $or$libresoc.v:31760$1072_Y + end + attribute \src "libresoc.v:31719.7-31719.20" + process $proc$libresoc.v:31719$1078 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:31743.7-31743.19" + process $proc$libresoc.v:31743$1079 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:31762.3-31763.27" + process $proc$libresoc.v:31762$1074 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:31764.3-31772.6" + process $proc$libresoc.v:31764$1075 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$1076 $1\q_int$next[0:0]$1077 + attribute \src "libresoc.v:31765.5-31765.29" + switch \initial + attribute \src "libresoc.v:31765.9-31765.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$1077 1'0 + case + assign $1\q_int$next[0:0]$1077 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$1076 + end + connect \$9 $and$libresoc.v:31754$1066_Y + connect \$11 $or$libresoc.v:31755$1067_Y + connect \$13 $not$libresoc.v:31756$1068_Y + connect \$15 $or$libresoc.v:31757$1069_Y + connect \$1 $not$libresoc.v:31758$1070_Y + connect \$3 $and$libresoc.v:31759$1071_Y + connect \$5 $or$libresoc.v:31760$1072_Y + connect \$7 $not$libresoc.v:31761$1073_Y + connect \qlq_alui \$15 + connect \qn_alui \$13 + connect \q_alui \$11 +end +attribute \src "libresoc.v:31780.1-31838.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.alui_l" +attribute \generator "nMigen" +module \alui_l$72 + attribute \src "libresoc.v:31781.7-31781.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:31826.3-31834.6" + wire $0\q_int$next[0:0]$1090 + attribute \src "libresoc.v:31824.3-31825.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:31826.3-31834.6" + wire $1\q_int$next[0:0]$1091 + attribute \src "libresoc.v:31805.7-31805.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:31816.17-31816.96" + wire $and$libresoc.v:31816$1080_Y + attribute \src "libresoc.v:31821.17-31821.96" + wire $and$libresoc.v:31821$1085_Y + attribute \src "libresoc.v:31818.18-31818.94" + wire $not$libresoc.v:31818$1082_Y + attribute \src "libresoc.v:31820.17-31820.93" + wire $not$libresoc.v:31820$1084_Y + attribute \src "libresoc.v:31823.17-31823.93" + wire $not$libresoc.v:31823$1087_Y + attribute \src "libresoc.v:31817.18-31817.99" + wire $or$libresoc.v:31817$1081_Y + attribute \src "libresoc.v:31819.18-31819.100" + wire $or$libresoc.v:31819$1083_Y + attribute \src "libresoc.v:31822.17-31822.98" + wire $or$libresoc.v:31822$1086_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$5 + 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"/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_60 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_61 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_62 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_63 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:54" + wire width 64 input 3 \rs + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" + cell $lt $lt$libresoc.v:32074$1108 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \idx_4 + connect \B 7'1000000 + connect \Y $lt$libresoc.v:32074$1108_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" + cell $lt $lt$libresoc.v:32075$1109 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \idx_5 + connect \B 7'1000000 + connect \Y $lt$libresoc.v:32075$1109_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" + cell $lt $lt$libresoc.v:32076$1110 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \idx_6 + connect \B 7'1000000 + connect \Y $lt$libresoc.v:32076$1110_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" + cell $lt $lt$libresoc.v:32077$1111 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \idx_7 + connect \B 7'1000000 + connect \Y $lt$libresoc.v:32077$1111_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" + cell $lt $lt$libresoc.v:32078$1112 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \idx_0 + connect \B 7'1000000 + connect \Y $lt$libresoc.v:32078$1112_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" + cell $lt $lt$libresoc.v:32079$1113 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \idx_1 + connect \B 7'1000000 + connect \Y $lt$libresoc.v:32079$1113_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" + cell $lt $lt$libresoc.v:32080$1114 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \idx_2 + connect \B 7'1000000 + connect \Y $lt$libresoc.v:32080$1114_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" + cell $lt $lt$libresoc.v:32081$1115 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \idx_3 + connect \B 7'1000000 + connect \Y $lt$libresoc.v:32081$1115_Y + end + attribute \src "libresoc.v:31905.7-31905.20" + process $proc$libresoc.v:31905$1117 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:32082.3-33173.6" + process $proc$libresoc.v:32082$1116 + assign { } { } + assign $0\perm[63:0] [63:8] 56'00000000000000000000000000000000000000000000000000000000 + assign $0\perm[63:0] [0] $1\perm[0:0] + assign $0\perm[63:0] [1] $3\perm[1:1] + assign $0\perm[63:0] [2] $5\perm[2:2] + assign $0\perm[63:0] [3] $7\perm[3:3] + assign $0\perm[63:0] [4] $9\perm[4:4] + assign $0\perm[63:0] [5] $11\perm[5:5] + assign $0\perm[63:0] [6] $13\perm[6:6] + assign $0\perm[63:0] [7] $15\perm[7:7] + attribute \src "libresoc.v:32083.5-32083.29" + switch \initial + attribute \src "libresoc.v:32083.9-32083.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" + switch \$1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\perm[0:0] $2\perm[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:70" + switch \idx_0 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000000 + assign { } { } + assign $2\perm[0:0] \rb64_0 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000001 + assign { } { } + assign $2\perm[0:0] \rb64_1 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000010 + assign { } { } + assign $2\perm[0:0] \rb64_2 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000011 + assign { } { } + assign $2\perm[0:0] \rb64_3 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000100 + assign { } { } + assign $2\perm[0:0] \rb64_4 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000101 + assign { } { } + assign $2\perm[0:0] \rb64_5 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000110 + assign { } { } + assign $2\perm[0:0] \rb64_6 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000111 + assign { } { } + assign $2\perm[0:0] \rb64_7 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001000 + assign { } { } + assign $2\perm[0:0] \rb64_8 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001001 + assign { } { } + assign $2\perm[0:0] \rb64_9 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001010 + assign { } { } + assign $2\perm[0:0] \rb64_10 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001011 + assign { } { } + assign $2\perm[0:0] \rb64_11 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001100 + assign { } { } + assign $2\perm[0:0] \rb64_12 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001101 + assign { } { } + assign $2\perm[0:0] \rb64_13 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001110 + assign { } { } + assign $2\perm[0:0] \rb64_14 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001111 + assign { } { } + assign $2\perm[0:0] \rb64_15 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010000 + assign { } { } + assign $2\perm[0:0] \rb64_16 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010001 + assign { } { } + assign $2\perm[0:0] \rb64_17 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010010 + assign { } { } + assign $2\perm[0:0] \rb64_18 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010011 + assign { } { } + assign $2\perm[0:0] \rb64_19 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010100 + assign { } { } + assign $2\perm[0:0] \rb64_20 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010101 + assign { } { } + assign $2\perm[0:0] \rb64_21 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010110 + assign { } { } + assign $2\perm[0:0] \rb64_22 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010111 + assign { } { } + assign $2\perm[0:0] \rb64_23 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011000 + assign { } { } + assign $2\perm[0:0] \rb64_24 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011001 + assign { } { } + assign $2\perm[0:0] \rb64_25 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011010 + assign { } { } + assign $2\perm[0:0] \rb64_26 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011011 + assign { } { } + assign $2\perm[0:0] \rb64_27 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011100 + assign { } { } + assign $2\perm[0:0] \rb64_28 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011101 + assign { } { } + assign $2\perm[0:0] \rb64_29 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011110 + assign { } { } + assign $2\perm[0:0] \rb64_30 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011111 + assign { } { } + assign $2\perm[0:0] \rb64_31 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100000 + assign { } { } + assign $2\perm[0:0] \rb64_32 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100001 + assign { } { } + assign $2\perm[0:0] \rb64_33 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100010 + assign { } { } + assign $2\perm[0:0] \rb64_34 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100011 + assign { } { } + assign $2\perm[0:0] \rb64_35 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100100 + assign { } { } + assign $2\perm[0:0] \rb64_36 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100101 + assign { } { } + assign $2\perm[0:0] \rb64_37 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100110 + assign { } { } + assign $2\perm[0:0] \rb64_38 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100111 + assign { } { } + assign $2\perm[0:0] \rb64_39 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101000 + assign { } { } + assign $2\perm[0:0] \rb64_40 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101001 + assign { } { } + assign $2\perm[0:0] \rb64_41 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101010 + assign { } { } + assign $2\perm[0:0] \rb64_42 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101011 + assign { } { } + assign $2\perm[0:0] \rb64_43 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101100 + assign { } { } + assign $2\perm[0:0] \rb64_44 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101101 + assign { } { } + assign $2\perm[0:0] \rb64_45 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101110 + assign { } { } + assign $2\perm[0:0] \rb64_46 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101111 + assign { } { } + assign $2\perm[0:0] \rb64_47 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110000 + assign { } { } + assign $2\perm[0:0] \rb64_48 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110001 + assign { } { } + assign $2\perm[0:0] \rb64_49 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110010 + assign { } { } + assign $2\perm[0:0] \rb64_50 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110011 + assign { } { } + assign $2\perm[0:0] \rb64_51 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110100 + assign { } { } + assign $2\perm[0:0] \rb64_52 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110101 + assign { } { } + assign $2\perm[0:0] \rb64_53 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110110 + assign { } { } + assign $2\perm[0:0] \rb64_54 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110111 + assign { } { } + assign $2\perm[0:0] \rb64_55 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111000 + assign { } { } + assign $2\perm[0:0] \rb64_56 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111001 + assign { } { } + assign $2\perm[0:0] \rb64_57 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111010 + assign { } { } + assign $2\perm[0:0] \rb64_58 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111011 + assign { } { } + assign $2\perm[0:0] \rb64_59 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111100 + assign { } { } + assign $2\perm[0:0] \rb64_60 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111101 + assign { } { } + assign $2\perm[0:0] \rb64_61 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111110 + assign { } { } + assign $2\perm[0:0] \rb64_62 + attribute \src "libresoc.v:0.0-0.0" + case 8'-------- + assign { } { } + assign $2\perm[0:0] \rb64_63 + case + assign $2\perm[0:0] 1'0 + end + case + assign $1\perm[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\perm[1:1] $4\perm[1:1] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:70" + switch \idx_1 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000000 + assign { } { } + assign $4\perm[1:1] \rb64_0 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000001 + assign { } { } + assign $4\perm[1:1] \rb64_1 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000010 + assign { } { } + assign $4\perm[1:1] \rb64_2 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000011 + assign { } { } + assign $4\perm[1:1] \rb64_3 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000100 + assign { } { } + assign $4\perm[1:1] \rb64_4 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000101 + assign { } { } + assign $4\perm[1:1] \rb64_5 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000110 + assign { } { } + assign $4\perm[1:1] \rb64_6 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000111 + assign { } { } + assign $4\perm[1:1] \rb64_7 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001000 + assign { } { } + assign $4\perm[1:1] \rb64_8 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001001 + assign { } { } + assign $4\perm[1:1] \rb64_9 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001010 + assign { } { } + assign $4\perm[1:1] \rb64_10 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001011 + assign { } { } + assign $4\perm[1:1] \rb64_11 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001100 + assign { } { } + assign $4\perm[1:1] \rb64_12 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001101 + assign { } { } + assign $4\perm[1:1] \rb64_13 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001110 + assign { } { } + assign $4\perm[1:1] \rb64_14 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001111 + assign { } { } + assign $4\perm[1:1] \rb64_15 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010000 + assign { } { } + assign $4\perm[1:1] \rb64_16 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010001 + assign { } { } + assign $4\perm[1:1] \rb64_17 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010010 + assign { } { } + assign $4\perm[1:1] \rb64_18 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010011 + assign { } { } + assign $4\perm[1:1] \rb64_19 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010100 + assign { } { } + assign $4\perm[1:1] \rb64_20 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010101 + assign { } { } + assign $4\perm[1:1] \rb64_21 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010110 + assign { } { } + assign $4\perm[1:1] \rb64_22 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010111 + assign { } { } + assign $4\perm[1:1] \rb64_23 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011000 + assign { } { } + assign $4\perm[1:1] \rb64_24 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011001 + assign { } { } + assign $4\perm[1:1] \rb64_25 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011010 + assign { } { } + assign $4\perm[1:1] \rb64_26 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011011 + assign { } { } + assign $4\perm[1:1] \rb64_27 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011100 + assign { } { } + assign $4\perm[1:1] \rb64_28 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011101 + assign { } { } + assign $4\perm[1:1] \rb64_29 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011110 + assign { } { } + assign $4\perm[1:1] \rb64_30 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011111 + assign { } { } + assign $4\perm[1:1] \rb64_31 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100000 + assign { } { } + assign $4\perm[1:1] \rb64_32 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100001 + assign { } { } + assign $4\perm[1:1] \rb64_33 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100010 + assign { } { } + assign $4\perm[1:1] \rb64_34 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100011 + assign { } { } + assign $4\perm[1:1] \rb64_35 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100100 + assign { } { } + assign $4\perm[1:1] \rb64_36 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100101 + assign { } { } + assign $4\perm[1:1] \rb64_37 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100110 + assign { } { } + assign $4\perm[1:1] \rb64_38 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100111 + assign { } { } + assign $4\perm[1:1] \rb64_39 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101000 + assign { } { } + assign $4\perm[1:1] \rb64_40 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101001 + assign { } { } + assign $4\perm[1:1] \rb64_41 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101010 + assign { } { } + assign $4\perm[1:1] \rb64_42 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101011 + assign { } { } + assign $4\perm[1:1] \rb64_43 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101100 + assign { } { } + assign $4\perm[1:1] \rb64_44 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101101 + assign { } { } + assign $4\perm[1:1] \rb64_45 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101110 + assign { } { } + assign $4\perm[1:1] \rb64_46 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101111 + assign { } { } + assign $4\perm[1:1] \rb64_47 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110000 + assign { } { } + assign $4\perm[1:1] \rb64_48 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110001 + assign { } { } + assign $4\perm[1:1] \rb64_49 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110010 + assign { } { } + assign $4\perm[1:1] \rb64_50 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110011 + assign { } { } + assign $4\perm[1:1] \rb64_51 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110100 + assign { } { } + assign $4\perm[1:1] \rb64_52 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110101 + assign { } { } + assign $4\perm[1:1] \rb64_53 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110110 + assign { } { } + assign $4\perm[1:1] \rb64_54 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110111 + assign { } { } + assign $4\perm[1:1] \rb64_55 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111000 + assign { } { } + assign $4\perm[1:1] \rb64_56 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111001 + assign { } { } + assign $4\perm[1:1] \rb64_57 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111010 + assign { } { } + assign $4\perm[1:1] \rb64_58 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111011 + assign { } { } + assign $4\perm[1:1] \rb64_59 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111100 + assign { } { } + assign $4\perm[1:1] \rb64_60 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111101 + assign { } { } + assign $4\perm[1:1] \rb64_61 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111110 + assign { } { } + assign $4\perm[1:1] \rb64_62 + attribute \src "libresoc.v:0.0-0.0" + case 8'-------- + assign { } { } + assign $4\perm[1:1] \rb64_63 + case + assign $4\perm[1:1] 1'0 + end + case + assign $3\perm[1:1] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" + switch \$5 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\perm[2:2] $6\perm[2:2] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:70" + switch \idx_2 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000000 + assign { } { } + assign $6\perm[2:2] \rb64_0 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000001 + assign { } { } + assign $6\perm[2:2] \rb64_1 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000010 + assign { } { } + assign $6\perm[2:2] \rb64_2 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000011 + assign { } { } + assign $6\perm[2:2] \rb64_3 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000100 + assign { } { } + assign $6\perm[2:2] \rb64_4 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000101 + assign { } { } + assign $6\perm[2:2] \rb64_5 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000110 + assign { } { } + assign $6\perm[2:2] \rb64_6 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000111 + assign { } { } + assign $6\perm[2:2] \rb64_7 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001000 + assign { } { } + assign $6\perm[2:2] \rb64_8 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001001 + assign { } { } + assign $6\perm[2:2] \rb64_9 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001010 + assign { } { } + assign $6\perm[2:2] \rb64_10 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001011 + assign { } { } + assign $6\perm[2:2] \rb64_11 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001100 + assign { } { } + assign $6\perm[2:2] \rb64_12 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001101 + assign { } { } + assign $6\perm[2:2] \rb64_13 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001110 + assign { } { } + assign $6\perm[2:2] \rb64_14 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001111 + assign { } { } + assign $6\perm[2:2] \rb64_15 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010000 + assign { } { } + assign $6\perm[2:2] \rb64_16 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010001 + assign { } { } + assign $6\perm[2:2] \rb64_17 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010010 + assign { } { } + assign $6\perm[2:2] \rb64_18 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010011 + assign { } { } + assign $6\perm[2:2] \rb64_19 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010100 + assign { } { } + assign $6\perm[2:2] \rb64_20 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010101 + assign { } { } + assign $6\perm[2:2] \rb64_21 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010110 + assign { } { } + assign $6\perm[2:2] \rb64_22 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010111 + assign { } { } + assign $6\perm[2:2] \rb64_23 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011000 + assign { } { } + assign $6\perm[2:2] \rb64_24 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011001 + assign { } { } + assign $6\perm[2:2] \rb64_25 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011010 + assign { } { } + assign $6\perm[2:2] \rb64_26 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011011 + assign { } { } + assign $6\perm[2:2] \rb64_27 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011100 + assign { } { } + assign $6\perm[2:2] \rb64_28 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011101 + assign { } { } + assign $6\perm[2:2] \rb64_29 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011110 + assign { } { } + assign $6\perm[2:2] \rb64_30 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011111 + assign { } { } + assign $6\perm[2:2] \rb64_31 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100000 + assign { } { } + assign $6\perm[2:2] \rb64_32 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100001 + assign { } { } + assign $6\perm[2:2] \rb64_33 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100010 + assign { } { } + assign $6\perm[2:2] \rb64_34 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100011 + assign { } { } + assign $6\perm[2:2] \rb64_35 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100100 + assign { } { } + assign $6\perm[2:2] \rb64_36 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100101 + assign { } { } + assign $6\perm[2:2] \rb64_37 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100110 + assign { } { } + assign $6\perm[2:2] \rb64_38 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100111 + assign { } { } + assign $6\perm[2:2] \rb64_39 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101000 + assign { } { } + assign $6\perm[2:2] \rb64_40 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101001 + assign { } { } + assign $6\perm[2:2] \rb64_41 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101010 + assign { } { } + assign $6\perm[2:2] \rb64_42 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101011 + assign { } { } + assign $6\perm[2:2] \rb64_43 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101100 + assign { } { } + assign $6\perm[2:2] \rb64_44 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101101 + assign { } { } + assign $6\perm[2:2] \rb64_45 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101110 + assign { } { } + assign $6\perm[2:2] \rb64_46 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101111 + assign { } { } + assign $6\perm[2:2] \rb64_47 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110000 + assign { } { } + assign $6\perm[2:2] \rb64_48 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110001 + assign { } { } + assign $6\perm[2:2] \rb64_49 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110010 + assign { } { } + assign $6\perm[2:2] \rb64_50 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110011 + assign { } { } + assign $6\perm[2:2] \rb64_51 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110100 + assign { } { } + assign $6\perm[2:2] \rb64_52 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110101 + assign { } { } + assign $6\perm[2:2] \rb64_53 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110110 + assign { } { } + assign $6\perm[2:2] \rb64_54 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110111 + assign { } { } + assign $6\perm[2:2] \rb64_55 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111000 + assign { } { } + assign $6\perm[2:2] \rb64_56 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111001 + assign { } { } + assign $6\perm[2:2] \rb64_57 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111010 + assign { } { } + assign $6\perm[2:2] \rb64_58 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111011 + assign { } { } + assign $6\perm[2:2] \rb64_59 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111100 + assign { } { } + assign $6\perm[2:2] \rb64_60 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111101 + assign { } { } + assign $6\perm[2:2] \rb64_61 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111110 + assign { } { } + assign $6\perm[2:2] \rb64_62 + attribute \src "libresoc.v:0.0-0.0" + case 8'-------- + assign { } { } + assign $6\perm[2:2] \rb64_63 + case + assign $6\perm[2:2] 1'0 + end + case + assign $5\perm[2:2] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" + switch \$7 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\perm[3:3] $8\perm[3:3] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:70" + switch \idx_3 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000000 + assign { } { } + assign $8\perm[3:3] \rb64_0 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000001 + assign { } { } + assign $8\perm[3:3] \rb64_1 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000010 + assign { } { } + assign $8\perm[3:3] \rb64_2 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000011 + assign { } { } + assign $8\perm[3:3] \rb64_3 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000100 + assign { } { } + assign $8\perm[3:3] \rb64_4 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000101 + assign { } { } + assign $8\perm[3:3] \rb64_5 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000110 + assign { } { } + assign $8\perm[3:3] \rb64_6 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000111 + assign { } { } + assign $8\perm[3:3] \rb64_7 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001000 + assign { } { } + assign $8\perm[3:3] \rb64_8 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001001 + assign { } { } + assign $8\perm[3:3] \rb64_9 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001010 + assign { } { } + assign $8\perm[3:3] \rb64_10 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001011 + assign { } { } + assign $8\perm[3:3] \rb64_11 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001100 + assign { } { } + assign $8\perm[3:3] \rb64_12 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001101 + assign { } { } + assign $8\perm[3:3] \rb64_13 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001110 + assign { } { } + assign $8\perm[3:3] \rb64_14 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001111 + assign { } { } + assign $8\perm[3:3] \rb64_15 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010000 + assign { } { } + assign $8\perm[3:3] \rb64_16 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010001 + assign { } { } + assign $8\perm[3:3] \rb64_17 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010010 + assign { } { } + assign $8\perm[3:3] \rb64_18 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010011 + assign { } { } + assign $8\perm[3:3] \rb64_19 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010100 + assign { } { } + assign $8\perm[3:3] \rb64_20 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010101 + assign { } { } + assign $8\perm[3:3] \rb64_21 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010110 + assign { } { } + assign $8\perm[3:3] \rb64_22 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010111 + assign { } { } + assign $8\perm[3:3] \rb64_23 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011000 + assign { } { } + assign $8\perm[3:3] \rb64_24 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011001 + assign { } { } + assign $8\perm[3:3] \rb64_25 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011010 + assign { } { } + assign $8\perm[3:3] \rb64_26 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011011 + assign { } { } + assign $8\perm[3:3] \rb64_27 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011100 + assign { } { } + assign $8\perm[3:3] \rb64_28 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011101 + assign { } { } + assign $8\perm[3:3] \rb64_29 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011110 + assign { } { } + assign $8\perm[3:3] \rb64_30 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011111 + assign { } { } + assign $8\perm[3:3] \rb64_31 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100000 + assign { } { } + assign $8\perm[3:3] \rb64_32 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100001 + assign { } { } + assign $8\perm[3:3] \rb64_33 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100010 + assign { } { } + assign $8\perm[3:3] \rb64_34 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100011 + assign { } { } + assign $8\perm[3:3] \rb64_35 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100100 + assign { } { } + assign $8\perm[3:3] \rb64_36 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100101 + assign { } { } + assign $8\perm[3:3] \rb64_37 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100110 + assign { } { } + assign $8\perm[3:3] \rb64_38 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100111 + assign { } { } + assign $8\perm[3:3] \rb64_39 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101000 + assign { } { } + assign $8\perm[3:3] \rb64_40 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101001 + assign { } { } + assign $8\perm[3:3] \rb64_41 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101010 + assign { } { } + assign $8\perm[3:3] \rb64_42 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101011 + assign { } { } + assign $8\perm[3:3] \rb64_43 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101100 + assign { } { } + assign $8\perm[3:3] \rb64_44 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101101 + assign { } { } + assign $8\perm[3:3] \rb64_45 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101110 + assign { } { } + assign $8\perm[3:3] \rb64_46 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101111 + assign { } { } + assign $8\perm[3:3] \rb64_47 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110000 + assign { } { } + assign $8\perm[3:3] \rb64_48 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110001 + assign { } { } + assign $8\perm[3:3] \rb64_49 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110010 + assign { } { } + assign $8\perm[3:3] \rb64_50 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110011 + assign { } { } + assign $8\perm[3:3] \rb64_51 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110100 + assign { } { } + assign $8\perm[3:3] \rb64_52 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110101 + assign { } { } + assign $8\perm[3:3] \rb64_53 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110110 + assign { } { } + assign $8\perm[3:3] \rb64_54 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110111 + assign { } { } + assign $8\perm[3:3] \rb64_55 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111000 + assign { } { } + assign $8\perm[3:3] \rb64_56 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111001 + assign { } { } + assign $8\perm[3:3] \rb64_57 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111010 + assign { } { } + assign $8\perm[3:3] \rb64_58 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111011 + assign { } { } + assign $8\perm[3:3] \rb64_59 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111100 + assign { } { } + assign $8\perm[3:3] \rb64_60 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111101 + assign { } { } + assign $8\perm[3:3] \rb64_61 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111110 + assign { } { } + assign $8\perm[3:3] \rb64_62 + attribute \src "libresoc.v:0.0-0.0" + case 8'-------- + assign { } { } + assign $8\perm[3:3] \rb64_63 + case + assign $8\perm[3:3] 1'0 + end + case + assign $7\perm[3:3] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" + switch \$9 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $9\perm[4:4] $10\perm[4:4] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:70" + switch \idx_4 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000000 + assign { } { } + assign $10\perm[4:4] \rb64_0 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000001 + assign { } { } + assign $10\perm[4:4] \rb64_1 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000010 + assign { } { } + assign $10\perm[4:4] \rb64_2 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000011 + assign { } { } + assign $10\perm[4:4] \rb64_3 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000100 + assign { } { } + assign $10\perm[4:4] \rb64_4 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000101 + assign { } { } + assign $10\perm[4:4] \rb64_5 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000110 + assign { } { } + assign $10\perm[4:4] \rb64_6 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000111 + assign { } { } + assign $10\perm[4:4] \rb64_7 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001000 + assign { } { } + assign $10\perm[4:4] \rb64_8 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001001 + assign { } { } + assign $10\perm[4:4] \rb64_9 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001010 + assign { } { } + assign $10\perm[4:4] \rb64_10 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001011 + assign { } { } + assign $10\perm[4:4] \rb64_11 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001100 + assign { } { } + assign $10\perm[4:4] \rb64_12 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001101 + assign { } { } + assign $10\perm[4:4] \rb64_13 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001110 + assign { } { } + assign $10\perm[4:4] \rb64_14 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001111 + assign { } { } + assign $10\perm[4:4] \rb64_15 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010000 + assign { } { } + assign $10\perm[4:4] \rb64_16 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010001 + assign { } { } + assign $10\perm[4:4] \rb64_17 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010010 + assign { } { } + assign $10\perm[4:4] \rb64_18 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010011 + assign { } { } + assign $10\perm[4:4] \rb64_19 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010100 + assign { } { } + assign $10\perm[4:4] \rb64_20 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010101 + assign { } { } + assign $10\perm[4:4] \rb64_21 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010110 + assign { } { } + assign $10\perm[4:4] \rb64_22 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010111 + assign { } { } + assign $10\perm[4:4] \rb64_23 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011000 + assign { } { } + assign $10\perm[4:4] \rb64_24 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011001 + assign { } { } + assign $10\perm[4:4] \rb64_25 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011010 + assign { } { } + assign $10\perm[4:4] \rb64_26 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011011 + assign { } { } + assign $10\perm[4:4] \rb64_27 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011100 + assign { } { } + assign $10\perm[4:4] \rb64_28 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011101 + assign { } { } + assign $10\perm[4:4] \rb64_29 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011110 + assign { } { } + assign $10\perm[4:4] \rb64_30 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011111 + assign { } { } + assign $10\perm[4:4] \rb64_31 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100000 + assign { } { } + assign $10\perm[4:4] \rb64_32 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100001 + assign { } { } + assign $10\perm[4:4] \rb64_33 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100010 + assign { } { } + assign $10\perm[4:4] \rb64_34 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100011 + assign { } { } + assign $10\perm[4:4] \rb64_35 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100100 + assign { } { } + assign $10\perm[4:4] \rb64_36 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100101 + assign { } { } + assign $10\perm[4:4] \rb64_37 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100110 + assign { } { } + assign $10\perm[4:4] \rb64_38 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100111 + assign { } { } + assign $10\perm[4:4] \rb64_39 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101000 + assign { } { } + assign $10\perm[4:4] \rb64_40 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101001 + assign { } { } + assign $10\perm[4:4] \rb64_41 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101010 + assign { } { } + assign $10\perm[4:4] \rb64_42 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101011 + assign { } { } + assign $10\perm[4:4] \rb64_43 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101100 + assign { } { } + assign $10\perm[4:4] \rb64_44 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101101 + assign { } { } + assign $10\perm[4:4] \rb64_45 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101110 + assign { } { } + assign $10\perm[4:4] \rb64_46 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101111 + assign { } { } + assign $10\perm[4:4] \rb64_47 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110000 + assign { } { } + assign $10\perm[4:4] \rb64_48 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110001 + assign { } { } + assign $10\perm[4:4] \rb64_49 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110010 + assign { } { } + assign $10\perm[4:4] \rb64_50 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110011 + assign { } { } + assign $10\perm[4:4] \rb64_51 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110100 + assign { } { } + assign $10\perm[4:4] \rb64_52 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110101 + assign { } { } + assign $10\perm[4:4] \rb64_53 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110110 + assign { } { } + assign $10\perm[4:4] \rb64_54 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110111 + assign { } { } + assign $10\perm[4:4] \rb64_55 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111000 + assign { } { } + assign $10\perm[4:4] \rb64_56 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111001 + assign { } { } + assign $10\perm[4:4] \rb64_57 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111010 + assign { } { } + assign $10\perm[4:4] \rb64_58 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111011 + assign { } { } + assign $10\perm[4:4] \rb64_59 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111100 + assign { } { } + assign $10\perm[4:4] \rb64_60 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111101 + assign { } { } + assign $10\perm[4:4] \rb64_61 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111110 + assign { } { } + assign $10\perm[4:4] \rb64_62 + attribute \src "libresoc.v:0.0-0.0" + case 8'-------- + assign { } { } + assign $10\perm[4:4] \rb64_63 + case + assign $10\perm[4:4] 1'0 + end + case + assign $9\perm[4:4] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" + switch \$11 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $11\perm[5:5] $12\perm[5:5] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:70" + switch \idx_5 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000000 + assign { } { } + assign $12\perm[5:5] \rb64_0 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000001 + assign { } { } + assign $12\perm[5:5] \rb64_1 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000010 + assign { } { } + assign $12\perm[5:5] \rb64_2 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000011 + assign { } { } + assign $12\perm[5:5] \rb64_3 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000100 + assign { } { } + assign $12\perm[5:5] \rb64_4 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000101 + assign { } { } + assign $12\perm[5:5] \rb64_5 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000110 + assign { } { } + assign $12\perm[5:5] \rb64_6 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000111 + assign { } { } + assign $12\perm[5:5] \rb64_7 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001000 + assign { } { } + assign $12\perm[5:5] \rb64_8 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001001 + assign { } { } + assign $12\perm[5:5] \rb64_9 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001010 + assign { } { } + assign $12\perm[5:5] \rb64_10 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001011 + assign { } { } + assign $12\perm[5:5] \rb64_11 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001100 + assign { } { } + assign $12\perm[5:5] \rb64_12 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001101 + assign { } { } + assign $12\perm[5:5] \rb64_13 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001110 + assign { } { } + assign $12\perm[5:5] \rb64_14 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001111 + assign { } { } + assign $12\perm[5:5] \rb64_15 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010000 + assign { } { } + assign $12\perm[5:5] \rb64_16 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010001 + assign { } { } + assign $12\perm[5:5] \rb64_17 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010010 + assign { } { } + assign $12\perm[5:5] \rb64_18 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010011 + assign { } { } + assign $12\perm[5:5] \rb64_19 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010100 + assign { } { } + assign $12\perm[5:5] \rb64_20 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010101 + assign { } { } + assign $12\perm[5:5] \rb64_21 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010110 + assign { } { } + assign $12\perm[5:5] \rb64_22 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010111 + assign { } { } + assign $12\perm[5:5] \rb64_23 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011000 + assign { } { } + assign $12\perm[5:5] \rb64_24 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011001 + assign { } { } + assign $12\perm[5:5] \rb64_25 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011010 + assign { } { } + assign $12\perm[5:5] \rb64_26 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011011 + assign { } { } + assign $12\perm[5:5] \rb64_27 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011100 + assign { } { } + assign $12\perm[5:5] \rb64_28 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011101 + assign { } { } + assign $12\perm[5:5] \rb64_29 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011110 + assign { } { } + assign $12\perm[5:5] \rb64_30 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011111 + assign { } { } + assign $12\perm[5:5] \rb64_31 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100000 + assign { } { } + assign $12\perm[5:5] \rb64_32 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100001 + assign { } { } + assign $12\perm[5:5] \rb64_33 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100010 + assign { } { } + assign $12\perm[5:5] \rb64_34 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100011 + assign { } { } + assign $12\perm[5:5] \rb64_35 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100100 + assign { } { } + assign $12\perm[5:5] \rb64_36 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100101 + assign { } { } + assign $12\perm[5:5] \rb64_37 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100110 + assign { } { } + assign $12\perm[5:5] \rb64_38 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100111 + assign { } { } + assign $12\perm[5:5] \rb64_39 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101000 + assign { } { } + assign $12\perm[5:5] \rb64_40 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101001 + assign { } { } + assign $12\perm[5:5] \rb64_41 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101010 + assign { } { } + assign $12\perm[5:5] \rb64_42 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101011 + assign { } { } + assign $12\perm[5:5] \rb64_43 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101100 + assign { } { } + assign $12\perm[5:5] \rb64_44 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101101 + assign { } { } + assign $12\perm[5:5] \rb64_45 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101110 + assign { } { } + assign $12\perm[5:5] \rb64_46 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101111 + assign { } { } + assign $12\perm[5:5] \rb64_47 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110000 + assign { } { } + assign $12\perm[5:5] \rb64_48 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110001 + assign { } { } + assign $12\perm[5:5] \rb64_49 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110010 + assign { } { } + assign $12\perm[5:5] \rb64_50 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110011 + assign { } { } + assign $12\perm[5:5] \rb64_51 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110100 + assign { } { } + assign $12\perm[5:5] \rb64_52 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110101 + assign { } { } + assign $12\perm[5:5] \rb64_53 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110110 + assign { } { } + assign $12\perm[5:5] \rb64_54 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110111 + assign { } { } + assign $12\perm[5:5] \rb64_55 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111000 + assign { } { } + assign $12\perm[5:5] \rb64_56 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111001 + assign { } { } + assign $12\perm[5:5] \rb64_57 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111010 + assign { } { } + assign $12\perm[5:5] \rb64_58 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111011 + assign { } { } + assign $12\perm[5:5] \rb64_59 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111100 + assign { } { } + assign $12\perm[5:5] \rb64_60 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111101 + assign { } { } + assign $12\perm[5:5] \rb64_61 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111110 + assign { } { } + assign $12\perm[5:5] \rb64_62 + attribute \src "libresoc.v:0.0-0.0" + case 8'-------- + assign { } { } + assign $12\perm[5:5] \rb64_63 + case + assign $12\perm[5:5] 1'0 + end + case + assign $11\perm[5:5] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" + switch \$13 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $13\perm[6:6] $14\perm[6:6] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:70" + switch \idx_6 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000000 + assign { } { } + assign $14\perm[6:6] \rb64_0 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000001 + assign { } { } + assign $14\perm[6:6] \rb64_1 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000010 + assign { } { } + assign $14\perm[6:6] \rb64_2 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000011 + assign { } { } + assign $14\perm[6:6] \rb64_3 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000100 + assign { } { } + assign $14\perm[6:6] \rb64_4 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000101 + assign { } { } + assign $14\perm[6:6] \rb64_5 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000110 + assign { } { } + assign $14\perm[6:6] \rb64_6 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000111 + assign { } { } + assign $14\perm[6:6] \rb64_7 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001000 + assign { } { } + assign $14\perm[6:6] \rb64_8 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001001 + assign { } { } + assign $14\perm[6:6] \rb64_9 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001010 + assign { } { } + assign $14\perm[6:6] \rb64_10 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001011 + assign { } { } + assign $14\perm[6:6] \rb64_11 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001100 + assign { } { } + assign $14\perm[6:6] \rb64_12 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001101 + assign { } { } + assign $14\perm[6:6] \rb64_13 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001110 + assign { } { } + assign $14\perm[6:6] \rb64_14 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001111 + assign { } { } + assign $14\perm[6:6] \rb64_15 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010000 + assign { } { } + assign $14\perm[6:6] \rb64_16 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010001 + assign { } { } + assign $14\perm[6:6] \rb64_17 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010010 + assign { } { } + assign $14\perm[6:6] \rb64_18 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010011 + assign { } { } + assign $14\perm[6:6] \rb64_19 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010100 + assign { } { } + assign $14\perm[6:6] \rb64_20 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010101 + assign { } { } + assign $14\perm[6:6] \rb64_21 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010110 + assign { } { } + assign $14\perm[6:6] \rb64_22 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010111 + assign { } { } + assign $14\perm[6:6] \rb64_23 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011000 + assign { } { } + assign $14\perm[6:6] \rb64_24 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011001 + assign { } { } + assign $14\perm[6:6] \rb64_25 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011010 + assign { } { } + assign $14\perm[6:6] \rb64_26 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011011 + assign { } { } + assign $14\perm[6:6] \rb64_27 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011100 + assign { } { } + assign $14\perm[6:6] \rb64_28 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011101 + assign { } { } + assign $14\perm[6:6] \rb64_29 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011110 + assign { } { } + assign $14\perm[6:6] \rb64_30 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011111 + assign { } { } + assign $14\perm[6:6] \rb64_31 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100000 + assign { } { } + assign $14\perm[6:6] \rb64_32 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100001 + assign { } { } + assign $14\perm[6:6] \rb64_33 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100010 + assign { } { } + assign $14\perm[6:6] \rb64_34 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100011 + assign { } { } + assign $14\perm[6:6] \rb64_35 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100100 + assign { } { } + assign $14\perm[6:6] \rb64_36 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100101 + assign { } { } + assign $14\perm[6:6] \rb64_37 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100110 + assign { } { } + assign $14\perm[6:6] \rb64_38 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100111 + assign { } { } + assign $14\perm[6:6] \rb64_39 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101000 + assign { } { } + assign $14\perm[6:6] \rb64_40 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101001 + assign { } { } + assign $14\perm[6:6] \rb64_41 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101010 + assign { } { } + assign $14\perm[6:6] \rb64_42 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101011 + assign { } { } + assign $14\perm[6:6] \rb64_43 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101100 + assign { } { } + assign $14\perm[6:6] \rb64_44 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101101 + assign { } { } + assign $14\perm[6:6] \rb64_45 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101110 + assign { } { } + assign $14\perm[6:6] \rb64_46 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101111 + assign { } { } + assign $14\perm[6:6] \rb64_47 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110000 + assign { } { } + assign $14\perm[6:6] \rb64_48 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110001 + assign { } { } + assign $14\perm[6:6] \rb64_49 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110010 + assign { } { } + assign $14\perm[6:6] \rb64_50 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110011 + assign { } { } + assign $14\perm[6:6] \rb64_51 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110100 + assign { } { } + assign $14\perm[6:6] \rb64_52 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110101 + assign { } { } + assign $14\perm[6:6] \rb64_53 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110110 + assign { } { } + assign $14\perm[6:6] \rb64_54 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110111 + assign { } { } + assign $14\perm[6:6] \rb64_55 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111000 + assign { } { } + assign $14\perm[6:6] \rb64_56 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111001 + assign { } { } + assign $14\perm[6:6] \rb64_57 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111010 + assign { } { } + assign $14\perm[6:6] \rb64_58 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111011 + assign { } { } + assign $14\perm[6:6] \rb64_59 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111100 + assign { } { } + assign $14\perm[6:6] \rb64_60 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111101 + assign { } { } + assign $14\perm[6:6] \rb64_61 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111110 + assign { } { } + assign $14\perm[6:6] \rb64_62 + attribute \src "libresoc.v:0.0-0.0" + case 8'-------- + assign { } { } + assign $14\perm[6:6] \rb64_63 + case + assign $14\perm[6:6] 1'0 + end + case + assign $13\perm[6:6] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" + switch \$15 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $15\perm[7:7] $16\perm[7:7] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:70" + switch \idx_7 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000000 + assign { } { } + assign $16\perm[7:7] \rb64_0 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000001 + assign { } { } + assign $16\perm[7:7] \rb64_1 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000010 + assign { } { } + assign $16\perm[7:7] \rb64_2 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000011 + assign { } { } + assign $16\perm[7:7] \rb64_3 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000100 + assign { } { } + assign $16\perm[7:7] \rb64_4 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000101 + assign { } { } + assign $16\perm[7:7] \rb64_5 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000110 + assign { } { } + assign $16\perm[7:7] \rb64_6 + attribute \src "libresoc.v:0.0-0.0" + case 8'00000111 + assign { } { } + assign $16\perm[7:7] \rb64_7 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001000 + assign { } { } + assign $16\perm[7:7] \rb64_8 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001001 + assign { } { } + assign $16\perm[7:7] \rb64_9 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001010 + assign { } { } + assign $16\perm[7:7] \rb64_10 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001011 + assign { } { } + assign $16\perm[7:7] \rb64_11 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001100 + assign { } { } + assign $16\perm[7:7] \rb64_12 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001101 + assign { } { } + assign $16\perm[7:7] \rb64_13 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001110 + assign { } { } + assign $16\perm[7:7] \rb64_14 + attribute \src "libresoc.v:0.0-0.0" + case 8'00001111 + assign { } { } + assign $16\perm[7:7] \rb64_15 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010000 + assign { } { } + assign $16\perm[7:7] \rb64_16 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010001 + assign { } { } + assign $16\perm[7:7] \rb64_17 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010010 + assign { } { } + assign $16\perm[7:7] \rb64_18 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010011 + assign { } { } + assign $16\perm[7:7] \rb64_19 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010100 + assign { } { } + assign $16\perm[7:7] \rb64_20 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010101 + assign { } { } + assign $16\perm[7:7] \rb64_21 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010110 + assign { } { } + assign $16\perm[7:7] \rb64_22 + attribute \src "libresoc.v:0.0-0.0" + case 8'00010111 + assign { } { } + assign $16\perm[7:7] \rb64_23 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011000 + assign { } { } + assign $16\perm[7:7] \rb64_24 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011001 + assign { } { } + assign $16\perm[7:7] \rb64_25 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011010 + assign { } { } + assign $16\perm[7:7] \rb64_26 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011011 + assign { } { } + assign $16\perm[7:7] \rb64_27 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011100 + assign { } { } + assign $16\perm[7:7] \rb64_28 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011101 + assign { } { } + assign $16\perm[7:7] \rb64_29 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011110 + assign { } { } + assign $16\perm[7:7] \rb64_30 + attribute \src "libresoc.v:0.0-0.0" + case 8'00011111 + assign { } { } + assign $16\perm[7:7] \rb64_31 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100000 + assign { } { } + assign $16\perm[7:7] \rb64_32 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100001 + assign { } { } + assign $16\perm[7:7] \rb64_33 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100010 + assign { } { } + assign $16\perm[7:7] \rb64_34 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100011 + assign { } { } + assign $16\perm[7:7] \rb64_35 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100100 + assign { } { } + assign $16\perm[7:7] \rb64_36 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100101 + assign { } { } + assign $16\perm[7:7] \rb64_37 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100110 + assign { } { } + assign $16\perm[7:7] \rb64_38 + attribute \src "libresoc.v:0.0-0.0" + case 8'00100111 + assign { } { } + assign $16\perm[7:7] \rb64_39 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101000 + assign { } { } + assign $16\perm[7:7] \rb64_40 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101001 + assign { } { } + assign $16\perm[7:7] \rb64_41 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101010 + assign { } { } + assign $16\perm[7:7] \rb64_42 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101011 + assign { } { } + assign $16\perm[7:7] \rb64_43 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101100 + assign { } { } + assign $16\perm[7:7] \rb64_44 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101101 + assign { } { } + assign $16\perm[7:7] \rb64_45 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101110 + assign { } { } + assign $16\perm[7:7] \rb64_46 + attribute \src "libresoc.v:0.0-0.0" + case 8'00101111 + assign { } { } + assign $16\perm[7:7] \rb64_47 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110000 + assign { } { } + assign $16\perm[7:7] \rb64_48 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110001 + assign { } { } + assign $16\perm[7:7] \rb64_49 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110010 + assign { } { } + assign $16\perm[7:7] \rb64_50 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110011 + assign { } { } + assign $16\perm[7:7] \rb64_51 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110100 + assign { } { } + assign $16\perm[7:7] \rb64_52 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110101 + assign { } { } + assign $16\perm[7:7] \rb64_53 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110110 + assign { } { } + assign $16\perm[7:7] \rb64_54 + attribute \src "libresoc.v:0.0-0.0" + case 8'00110111 + assign { } { } + assign $16\perm[7:7] \rb64_55 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111000 + assign { } { } + assign $16\perm[7:7] \rb64_56 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111001 + assign { } { } + assign $16\perm[7:7] \rb64_57 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111010 + assign { } { } + assign $16\perm[7:7] \rb64_58 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111011 + assign { } { } + assign $16\perm[7:7] \rb64_59 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111100 + assign { } { } + assign $16\perm[7:7] \rb64_60 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111101 + assign { } { } + assign $16\perm[7:7] \rb64_61 + attribute \src "libresoc.v:0.0-0.0" + case 8'00111110 + assign { } { } + assign $16\perm[7:7] \rb64_62 + attribute \src "libresoc.v:0.0-0.0" + case 8'-------- + assign { } { } + assign $16\perm[7:7] \rb64_63 + case + assign $16\perm[7:7] 1'0 + end + case + assign $15\perm[7:7] 1'0 + end + sync always + update \perm $0\perm[63:0] + end + connect \$9 $lt$libresoc.v:32074$1108_Y + connect \$11 $lt$libresoc.v:32075$1109_Y + connect \$13 $lt$libresoc.v:32076$1110_Y + connect \$15 $lt$libresoc.v:32077$1111_Y + connect \$1 $lt$libresoc.v:32078$1112_Y + connect \$3 $lt$libresoc.v:32079$1113_Y + connect \$5 $lt$libresoc.v:32080$1114_Y + connect \$7 $lt$libresoc.v:32081$1115_Y + connect \ra [7:0] \perm [7:0] + connect \ra [63:8] 56'00000000000000000000000000000000000000000000000000000000 + connect \idx_7 \rs [63:56] + connect \idx_6 \rs [55:48] + connect \idx_5 \rs [47:40] + connect \idx_4 \rs [39:32] + connect \idx_3 \rs [31:24] + connect \idx_2 \rs [23:16] + connect \idx_1 \rs [15:8] + connect \idx_0 \rs [7:0] + connect \rb64_63 \rb [0] + connect \rb64_62 \rb [1] + connect \rb64_61 \rb [2] + connect \rb64_60 \rb [3] + connect \rb64_59 \rb [4] + connect \rb64_58 \rb [5] + connect \rb64_57 \rb [6] + connect \rb64_56 \rb [7] + connect \rb64_55 \rb [8] + connect \rb64_54 \rb [9] + connect \rb64_53 \rb [10] + connect \rb64_52 \rb [11] + connect \rb64_51 \rb [12] + connect \rb64_50 \rb [13] + connect \rb64_49 \rb [14] + connect \rb64_48 \rb [15] + connect \rb64_47 \rb [16] + connect \rb64_46 \rb [17] + connect \rb64_45 \rb [18] + connect \rb64_44 \rb [19] + connect \rb64_43 \rb [20] + connect \rb64_42 \rb [21] + connect \rb64_41 \rb [22] + connect \rb64_40 \rb [23] + connect \rb64_39 \rb [24] + connect \rb64_38 \rb [25] + connect \rb64_37 \rb [26] + connect \rb64_36 \rb [27] + connect \rb64_35 \rb [28] + connect \rb64_34 \rb [29] + connect \rb64_33 \rb [30] + connect \rb64_32 \rb [31] + connect \rb64_31 \rb [32] + connect \rb64_30 \rb [33] + connect \rb64_29 \rb [34] + connect \rb64_28 \rb [35] + connect \rb64_27 \rb [36] + connect \rb64_26 \rb [37] + connect \rb64_25 \rb [38] + connect \rb64_24 \rb [39] + connect \rb64_23 \rb [40] + connect \rb64_22 \rb [41] + connect \rb64_21 \rb [42] + connect \rb64_20 \rb [43] + connect \rb64_19 \rb [44] + connect \rb64_18 \rb [45] + connect \rb64_17 \rb [46] + connect \rb64_16 \rb [47] + connect \rb64_15 \rb [48] + connect \rb64_14 \rb [49] + connect \rb64_13 \rb [50] + connect \rb64_12 \rb [51] + connect \rb64_11 \rb [52] + connect \rb64_10 \rb [53] + connect \rb64_9 \rb [54] + connect \rb64_8 \rb [55] + connect \rb64_7 \rb [56] + connect \rb64_6 \rb [57] + connect \rb64_5 \rb [58] + connect \rb64_4 \rb [59] + connect \rb64_3 \rb [60] + connect \rb64_2 \rb [61] + connect \rb64_1 \rb [62] + connect \rb64_0 \rb [63] +end +attribute \src "libresoc.v:33252.1-34303.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0" +attribute \generator "nMigen" +module \branch0 + attribute \src "libresoc.v:33920.3-33921.25" + wire $0\all_rd_dly[0:0] + attribute \src "libresoc.v:34095.3-34119.6" + wire width 64 $0\alu_branch0_br_op__cia$next[63:0]$1239 + attribute \src "libresoc.v:33880.3-33881.61" + wire width 64 $0\alu_branch0_br_op__cia[63:0] + attribute \src "libresoc.v:34095.3-34119.6" + wire width 13 $0\alu_branch0_br_op__fn_unit$next[12:0]$1240 + attribute \src "libresoc.v:33884.3-33885.69" + wire width 13 $0\alu_branch0_br_op__fn_unit[12:0] + attribute \src "libresoc.v:34095.3-34119.6" + wire width 64 $0\alu_branch0_br_op__imm_data__data$next[63:0]$1241 + attribute \src "libresoc.v:33888.3-33889.83" + wire width 64 $0\alu_branch0_br_op__imm_data__data[63:0] + attribute \src "libresoc.v:34095.3-34119.6" + wire $0\alu_branch0_br_op__imm_data__ok$next[0:0]$1242 + attribute \src "libresoc.v:33890.3-33891.79" + wire $0\alu_branch0_br_op__imm_data__ok[0:0] + attribute \src "libresoc.v:34095.3-34119.6" + wire width 32 $0\alu_branch0_br_op__insn$next[31:0]$1243 + attribute \src "libresoc.v:33886.3-33887.63" + wire width 32 $0\alu_branch0_br_op__insn[31:0] + attribute \src "libresoc.v:34095.3-34119.6" + wire width 7 $0\alu_branch0_br_op__insn_type$next[6:0]$1244 + attribute \src "libresoc.v:33882.3-33883.73" + wire width 7 $0\alu_branch0_br_op__insn_type[6:0] + attribute \src "libresoc.v:34095.3-34119.6" + wire $0\alu_branch0_br_op__is_32bit$next[0:0]$1245 + attribute \src "libresoc.v:33894.3-33895.71" + wire $0\alu_branch0_br_op__is_32bit[0:0] + attribute \src "libresoc.v:34095.3-34119.6" + wire $0\alu_branch0_br_op__lk$next[0:0]$1246 + attribute \src "libresoc.v:33892.3-33893.59" + wire $0\alu_branch0_br_op__lk[0:0] + attribute \src "libresoc.v:33918.3-33919.43" + wire $0\alu_done_dly[0:0] + attribute \src "libresoc.v:34225.3-34233.6" + wire $0\alu_l_r_alu$next[0:0]$1294 + attribute \src "libresoc.v:33858.3-33859.39" + wire $0\alu_l_r_alu[0:0] + attribute \src "libresoc.v:34216.3-34224.6" + wire $0\alui_l_r_alui$next[0:0]$1291 + attribute \src "libresoc.v:33860.3-33861.43" + wire $0\alui_l_r_alui[0:0] + attribute \src "libresoc.v:34120.3-34141.6" + wire width 64 $0\data_r0__fast1$next[63:0]$1258 + attribute \src "libresoc.v:33876.3-33877.45" + wire width 64 $0\data_r0__fast1[63:0] + attribute \src "libresoc.v:34120.3-34141.6" + wire $0\data_r0__fast1_ok$next[0:0]$1259 + attribute \src "libresoc.v:33878.3-33879.51" + wire $0\data_r0__fast1_ok[0:0] + attribute \src "libresoc.v:34142.3-34163.6" + wire width 64 $0\data_r1__fast2$next[63:0]$1266 + attribute \src "libresoc.v:33872.3-33873.45" + wire width 64 $0\data_r1__fast2[63:0] + attribute \src "libresoc.v:34142.3-34163.6" + wire $0\data_r1__fast2_ok$next[0:0]$1267 + attribute \src "libresoc.v:33874.3-33875.51" + wire $0\data_r1__fast2_ok[0:0] + attribute \src "libresoc.v:34164.3-34185.6" + wire width 64 $0\data_r2__nia$next[63:0]$1274 + attribute \src "libresoc.v:33868.3-33869.41" + wire width 64 $0\data_r2__nia[63:0] + attribute \src "libresoc.v:34164.3-34185.6" + wire $0\data_r2__nia_ok$next[0:0]$1275 + attribute \src "libresoc.v:33870.3-33871.47" + wire $0\data_r2__nia_ok[0:0] + attribute \src "libresoc.v:34234.3-34243.6" + wire width 64 $0\dest1_o[63:0] + attribute \src "libresoc.v:34244.3-34253.6" + wire width 64 $0\dest2_o[63:0] + attribute \src "libresoc.v:34254.3-34263.6" + wire width 64 $0\dest3_o[63:0] + attribute \src "libresoc.v:33253.7-33253.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:34050.3-34058.6" + wire $0\opc_l_r_opc$next[0:0]$1224 + attribute \src "libresoc.v:33904.3-33905.39" + wire $0\opc_l_r_opc[0:0] + attribute \src "libresoc.v:34041.3-34049.6" + wire $0\opc_l_s_opc$next[0:0]$1221 + attribute \src "libresoc.v:33906.3-33907.39" + wire $0\opc_l_s_opc[0:0] + attribute \src "libresoc.v:34264.3-34272.6" + wire width 3 $0\prev_wr_go$next[2:0]$1300 + attribute \src "libresoc.v:33916.3-33917.37" + wire width 3 $0\prev_wr_go[2:0] + attribute \src "libresoc.v:33995.3-34004.6" + wire $0\req_done[0:0] + attribute \src "libresoc.v:34086.3-34094.6" + wire width 3 $0\req_l_r_req$next[2:0]$1236 + attribute \src "libresoc.v:33896.3-33897.39" + wire width 3 $0\req_l_r_req[2:0] + attribute \src "libresoc.v:34077.3-34085.6" + wire width 3 $0\req_l_s_req$next[2:0]$1233 + attribute \src "libresoc.v:33898.3-33899.39" + wire width 3 $0\req_l_s_req[2:0] + attribute \src "libresoc.v:34014.3-34022.6" + wire $0\rok_l_r_rdok$next[0:0]$1212 + attribute \src "libresoc.v:33912.3-33913.41" + wire $0\rok_l_r_rdok[0:0] + attribute \src "libresoc.v:34005.3-34013.6" + wire $0\rok_l_s_rdok$next[0:0]$1209 + attribute \src "libresoc.v:33914.3-33915.41" + wire $0\rok_l_s_rdok[0:0] + attribute \src "libresoc.v:34032.3-34040.6" + wire $0\rst_l_r_rst$next[0:0]$1218 + attribute \src "libresoc.v:33908.3-33909.39" + wire $0\rst_l_r_rst[0:0] + attribute \src "libresoc.v:34023.3-34031.6" + wire $0\rst_l_s_rst$next[0:0]$1215 + attribute \src "libresoc.v:33910.3-33911.39" + wire $0\rst_l_s_rst[0:0] + attribute \src "libresoc.v:34068.3-34076.6" + wire width 3 $0\src_l_r_src$next[2:0]$1230 + attribute \src "libresoc.v:33900.3-33901.39" + wire width 3 $0\src_l_r_src[2:0] + attribute \src "libresoc.v:34059.3-34067.6" + wire width 3 $0\src_l_s_src$next[2:0]$1227 + attribute \src "libresoc.v:33902.3-33903.39" + wire width 3 $0\src_l_s_src[2:0] + attribute \src "libresoc.v:34186.3-34195.6" + wire width 64 $0\src_r0$next[63:0]$1282 + attribute \src "libresoc.v:33866.3-33867.29" + wire width 64 $0\src_r0[63:0] + attribute \src "libresoc.v:34196.3-34205.6" + wire width 64 $0\src_r1$next[63:0]$1285 + attribute \src "libresoc.v:33864.3-33865.29" + wire width 64 $0\src_r1[63:0] + attribute \src "libresoc.v:34206.3-34215.6" + wire width 4 $0\src_r2$next[3:0]$1288 + attribute \src "libresoc.v:33862.3-33863.29" + wire width 4 $0\src_r2[3:0] + attribute \src "libresoc.v:33371.7-33371.24" + wire $1\all_rd_dly[0:0] + attribute \src "libresoc.v:34095.3-34119.6" + wire width 64 $1\alu_branch0_br_op__cia$next[63:0]$1247 + attribute \src "libresoc.v:33379.14-33379.59" + wire width 64 $1\alu_branch0_br_op__cia[63:0] + attribute \src "libresoc.v:34095.3-34119.6" + wire width 13 $1\alu_branch0_br_op__fn_unit$next[12:0]$1248 + attribute \src "libresoc.v:33397.14-33397.51" + wire width 13 $1\alu_branch0_br_op__fn_unit[12:0] + attribute \src "libresoc.v:34095.3-34119.6" + wire width 64 $1\alu_branch0_br_op__imm_data__data$next[63:0]$1249 + attribute \src "libresoc.v:33401.14-33401.70" + wire width 64 $1\alu_branch0_br_op__imm_data__data[63:0] + attribute \src "libresoc.v:34095.3-34119.6" + wire $1\alu_branch0_br_op__imm_data__ok$next[0:0]$1250 + attribute \src "libresoc.v:33405.7-33405.45" + wire $1\alu_branch0_br_op__imm_data__ok[0:0] + attribute \src "libresoc.v:34095.3-34119.6" + wire width 32 $1\alu_branch0_br_op__insn$next[31:0]$1251 + attribute \src "libresoc.v:33409.14-33409.45" + wire width 32 $1\alu_branch0_br_op__insn[31:0] + attribute \src "libresoc.v:34095.3-34119.6" + wire width 7 $1\alu_branch0_br_op__insn_type$next[6:0]$1252 + attribute \src "libresoc.v:33487.13-33487.49" + wire width 7 $1\alu_branch0_br_op__insn_type[6:0] + attribute \src "libresoc.v:34095.3-34119.6" + wire $1\alu_branch0_br_op__is_32bit$next[0:0]$1253 + attribute \src "libresoc.v:33491.7-33491.41" + wire $1\alu_branch0_br_op__is_32bit[0:0] + attribute \src "libresoc.v:34095.3-34119.6" + wire $1\alu_branch0_br_op__lk$next[0:0]$1254 + attribute \src "libresoc.v:33495.7-33495.35" + wire $1\alu_branch0_br_op__lk[0:0] + attribute \src "libresoc.v:33521.7-33521.26" + wire $1\alu_done_dly[0:0] + attribute \src "libresoc.v:34225.3-34233.6" + wire $1\alu_l_r_alu$next[0:0]$1295 + attribute \src "libresoc.v:33529.7-33529.25" + wire $1\alu_l_r_alu[0:0] + attribute \src "libresoc.v:34216.3-34224.6" + wire $1\alui_l_r_alui$next[0:0]$1292 + attribute \src "libresoc.v:33541.7-33541.27" + wire $1\alui_l_r_alui[0:0] + attribute \src "libresoc.v:34120.3-34141.6" + wire width 64 $1\data_r0__fast1$next[63:0]$1260 + attribute \src "libresoc.v:33573.14-33573.51" + wire width 64 $1\data_r0__fast1[63:0] + attribute \src "libresoc.v:34120.3-34141.6" + wire $1\data_r0__fast1_ok$next[0:0]$1261 + attribute \src "libresoc.v:33577.7-33577.31" + wire $1\data_r0__fast1_ok[0:0] + attribute \src "libresoc.v:34142.3-34163.6" + wire width 64 $1\data_r1__fast2$next[63:0]$1268 + attribute \src "libresoc.v:33581.14-33581.51" + wire width 64 $1\data_r1__fast2[63:0] + attribute \src "libresoc.v:34142.3-34163.6" + wire $1\data_r1__fast2_ok$next[0:0]$1269 + attribute \src "libresoc.v:33585.7-33585.31" + wire $1\data_r1__fast2_ok[0:0] + attribute \src "libresoc.v:34164.3-34185.6" + wire width 64 $1\data_r2__nia$next[63:0]$1276 + attribute \src "libresoc.v:33589.14-33589.49" + wire width 64 $1\data_r2__nia[63:0] + attribute \src "libresoc.v:34164.3-34185.6" + wire $1\data_r2__nia_ok$next[0:0]$1277 + attribute \src "libresoc.v:33593.7-33593.29" + wire $1\data_r2__nia_ok[0:0] + attribute \src "libresoc.v:34234.3-34243.6" + wire width 64 $1\dest1_o[63:0] + attribute \src "libresoc.v:34244.3-34253.6" + wire width 64 $1\dest2_o[63:0] + attribute \src "libresoc.v:34254.3-34263.6" + wire width 64 $1\dest3_o[63:0] + attribute \src "libresoc.v:34050.3-34058.6" + wire $1\opc_l_r_opc$next[0:0]$1225 + attribute \src "libresoc.v:33614.7-33614.25" + wire $1\opc_l_r_opc[0:0] + attribute \src "libresoc.v:34041.3-34049.6" + wire $1\opc_l_s_opc$next[0:0]$1222 + attribute \src "libresoc.v:33618.7-33618.25" + wire $1\opc_l_s_opc[0:0] + attribute \src "libresoc.v:34264.3-34272.6" + wire width 3 $1\prev_wr_go$next[2:0]$1301 + attribute \src "libresoc.v:33726.13-33726.30" + wire width 3 $1\prev_wr_go[2:0] + attribute \src "libresoc.v:33995.3-34004.6" + wire $1\req_done[0:0] + attribute \src "libresoc.v:34086.3-34094.6" + wire width 3 $1\req_l_r_req$next[2:0]$1237 + attribute \src "libresoc.v:33734.13-33734.31" + wire width 3 $1\req_l_r_req[2:0] + attribute \src "libresoc.v:34077.3-34085.6" + wire width 3 $1\req_l_s_req$next[2:0]$1234 + attribute \src "libresoc.v:33738.13-33738.31" + wire width 3 $1\req_l_s_req[2:0] + attribute \src "libresoc.v:34014.3-34022.6" + wire $1\rok_l_r_rdok$next[0:0]$1213 + attribute \src "libresoc.v:33750.7-33750.26" + wire $1\rok_l_r_rdok[0:0] + attribute \src "libresoc.v:34005.3-34013.6" + wire $1\rok_l_s_rdok$next[0:0]$1210 + attribute \src "libresoc.v:33754.7-33754.26" + wire $1\rok_l_s_rdok[0:0] + attribute \src "libresoc.v:34032.3-34040.6" + wire $1\rst_l_r_rst$next[0:0]$1219 + attribute \src "libresoc.v:33758.7-33758.25" + wire $1\rst_l_r_rst[0:0] + attribute \src "libresoc.v:34023.3-34031.6" + wire $1\rst_l_s_rst$next[0:0]$1216 + attribute \src "libresoc.v:33762.7-33762.25" + wire $1\rst_l_s_rst[0:0] + attribute \src "libresoc.v:34068.3-34076.6" + wire width 3 $1\src_l_r_src$next[2:0]$1231 + attribute \src "libresoc.v:33776.13-33776.31" + wire width 3 $1\src_l_r_src[2:0] + attribute \src "libresoc.v:34059.3-34067.6" + wire width 3 $1\src_l_s_src$next[2:0]$1228 + attribute \src "libresoc.v:33780.13-33780.31" + wire width 3 $1\src_l_s_src[2:0] + attribute \src "libresoc.v:34186.3-34195.6" + wire width 64 $1\src_r0$next[63:0]$1283 + attribute \src "libresoc.v:33786.14-33786.43" + wire width 64 $1\src_r0[63:0] + attribute \src "libresoc.v:34196.3-34205.6" + wire width 64 $1\src_r1$next[63:0]$1286 + attribute \src "libresoc.v:33790.14-33790.43" + wire width 64 $1\src_r1[63:0] + attribute \src "libresoc.v:34206.3-34215.6" + wire width 4 $1\src_r2$next[3:0]$1289 + attribute \src "libresoc.v:33794.13-33794.26" + wire width 4 $1\src_r2[3:0] + attribute \src "libresoc.v:34095.3-34119.6" + wire width 64 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"/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_branch0_br_op__lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_branch0_br_op__lk$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 4 \alu_branch0_cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \alu_branch0_fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \alu_branch0_fast1$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \alu_branch0_fast2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \alu_branch0_fast2$2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire \alu_branch0_n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire \alu_branch0_n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \alu_branch0_nia + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" + wire \alu_branch0_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" + wire \alu_branch0_p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:196" + wire \alu_done + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" + wire \alu_done_dly + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" + wire \alu_done_dly$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" + wire \alu_done_rise + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire \alu_l_q_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \alu_l_r_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \alu_l_r_alu$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire \alu_l_s_alu + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:197" + wire \alu_pulse + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198" + wire width 3 \alu_pulsem + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire \alui_l_q_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \alui_l_r_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \alui_l_r_alui$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire \alui_l_s_alui + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 26 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" + wire output 11 \cu_busy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:108" + wire \cu_done_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:104" + wire \cu_go_die_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" + wire input 10 \cu_issue_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 input 14 \cu_rd__go_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 output 13 \cu_rd__rel_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" + wire width 3 input 12 \cu_rdmaskn_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:102" + wire \cu_shadown_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 input 20 \cu_wr__go_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 output 19 \cu_wr__rel_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:97" + wire width 3 \cu_wrmask_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 64 \data_r0__fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 64 \data_r0__fast1$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r0__fast1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r0__fast1_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 64 \data_r1__fast2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 64 \data_r1__fast2$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r1__fast2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r1__fast2_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 64 \data_r2__nia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 64 \data_r2__nia$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r2__nia_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r2__nia_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 22 \dest1_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 23 \dest2_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 25 \dest3_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 18 \fast1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 21 \fast2_ok + attribute \src "libresoc.v:33253.7-33253.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 24 \nia_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire \opc_l_q_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \opc_l_r_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \opc_l_r_opc$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire \opc_l_s_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire \opc_l_s_opc$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 2 \oper_i_alu_branch0__cia + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 input 4 \oper_i_alu_branch0__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 6 \oper_i_alu_branch0__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 7 \oper_i_alu_branch0__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 5 \oper_i_alu_branch0__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute 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"/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" + wire width 3 \prev_wr_go$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212" + wire \req_done + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire width 3 \req_l_q_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 3 \req_l_r_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 3 \req_l_r_req$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire width 3 \req_l_s_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire width 3 \req_l_s_req$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226" + wire \reset + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:229" + wire width 3 \reset_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:228" + wire width 3 \reset_w + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire \rok_l_q_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \rok_l_r_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \rok_l_r_rdok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire \rok_l_s_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire \rok_l_s_rdok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \rst_l_r_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \rst_l_r_rst$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire \rst_l_s_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire \rst_l_s_rst$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227" + wire \rst_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 16 \src1_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 17 \src2_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 4 input 15 \src3_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire width 3 \src_l_q_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 3 \src_l_r_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 3 \src_l_r_src$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire width 3 \src_l_s_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire width 3 \src_l_s_src$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:166" + wire width 64 \src_or_imm + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" + wire width 64 \src_r0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" + wire width 64 \src_r0$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" + wire width 64 \src_r1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" + wire width 64 \src_r1$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" + wire width 4 \src_r2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" + wire width 4 \src_r2$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:167" + wire \src_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" + wire \wr_any + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + cell $and $and$libresoc.v:33802$1119 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \$95 + connect \B \$97 + connect \Y $and$libresoc.v:33802$1119_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + cell $and $and$libresoc.v:33803$1120 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_busy_o + connect \B \cu_shadown_i + connect \Y $and$libresoc.v:33803$1120_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + cell $and $and$libresoc.v:33804$1121 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_busy_o + connect \B \cu_shadown_i + connect \Y $and$libresoc.v:33804$1121_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + 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$and$libresoc.v:33810$1127_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $and $and$libresoc.v:33811$1128 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \$5 + connect \Y $and$libresoc.v:33811$1128_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $and $and$libresoc.v:33813$1130 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \all_rd + connect \B \$13 + connect \Y $and$libresoc.v:33813$1130_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $and $and$libresoc.v:33815$1132 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_done + connect \B \$17 + connect \Y $and$libresoc.v:33815$1132_Y + end + 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$and$libresoc.v:33821$1138_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" + cell $and $and$libresoc.v:33825$1142 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_busy_o + connect \B \rok_l_q_rdok + connect \Y $and$libresoc.v:33825$1142_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + cell $and $and$libresoc.v:33827$1144 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_any + connect \B \$39 + connect \Y $and$libresoc.v:33827$1144_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + cell $and $and$libresoc.v:33828$1145 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \req_l_q_req + connect \B \cu_wrmask_o + connect \Y $and$libresoc.v:33828$1145_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + cell $and $and$libresoc.v:33830$1147 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$41 + connect \B \$45 + connect \Y $and$libresoc.v:33830$1147_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + cell $and $and$libresoc.v:33832$1149 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$49 + connect \B \alu_branch0_n_ready_i + connect \Y $and$libresoc.v:33832$1149_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + cell $and $and$libresoc.v:33833$1150 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$51 + connect \B \alu_branch0_n_valid_o + connect \Y $and$libresoc.v:33833$1150_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + cell $and $and$libresoc.v:33834$1151 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$53 + connect \B \cu_busy_o + connect \Y $and$libresoc.v:33834$1151_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" + cell $and $and$libresoc.v:33839$1156 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_branch0_n_valid_o + connect \B \cu_busy_o + connect \Y $and$libresoc.v:33839$1156_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" + cell $and $and$libresoc.v:33840$1157 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \alu_pulsem + connect \B \cu_wrmask_o + connect \Y $and$libresoc.v:33840$1157_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + cell $and $and$libresoc.v:33843$1160 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fast1_ok + connect \B \cu_busy_o + connect \Y $and$libresoc.v:33843$1160_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + cell $and $and$libresoc.v:33844$1161 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fast2_ok + connect \B \cu_busy_o + connect \Y $and$libresoc.v:33844$1161_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + cell $and $and$libresoc.v:33845$1162 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \nia_ok + connect \B \cu_busy_o + connect \Y $and$libresoc.v:33845$1162_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" + cell $and $and$libresoc.v:33851$1168 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_branch0_p_ready_o + connect \B \alui_l_q_alui + connect \Y $and$libresoc.v:33851$1168_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" + cell $and $and$libresoc.v:33853$1170 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_branch0_n_valid_o + connect \B \alu_l_q_alu + connect \Y $and$libresoc.v:33853$1170_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + cell $and $and$libresoc.v:33854$1171 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \src_l_q_src + connect \B { \cu_busy_o \cu_busy_o \cu_busy_o } + connect \Y $and$libresoc.v:33854$1171_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + cell $and $and$libresoc.v:33856$1173 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \$91 + connect \B { 1'1 \$93 1'1 } + connect \Y $and$libresoc.v:33856$1173_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + cell $eq $eq$libresoc.v:33829$1146 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$43 + connect \B 1'0 + connect \Y $eq$libresoc.v:33829$1146_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + cell $eq $eq$libresoc.v:33831$1148 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_wrmask_o + connect \B 1'0 + connect \Y $eq$libresoc.v:33831$1148_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $not $not$libresoc.v:33812$1129 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \all_rd_dly + connect \Y $not$libresoc.v:33812$1129_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $not $not$libresoc.v:33814$1131 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_done_dly + connect \Y $not$libresoc.v:33814$1131_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $not $not$libresoc.v:33817$1134 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \cu_wrmask_o + connect \Y $not$libresoc.v:33817$1134_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $not $not$libresoc.v:33820$1137 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$24 + connect \Y $not$libresoc.v:33820$1137_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + cell $not $not$libresoc.v:33826$1143 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_branch0_n_ready_i + connect \Y $not$libresoc.v:33826$1143_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $not $not$libresoc.v:33841$1158 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \cu_rd__rel_o + connect \Y $not$libresoc.v:33841$1158_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" + cell $not $not$libresoc.v:33855$1172 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_branch0_br_op__imm_data__ok + connect \Y $not$libresoc.v:33855$1172_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + cell $not $not$libresoc.v:33857$1174 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \cu_rdmaskn_i + connect \Y $not$libresoc.v:33857$1174_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $or $or$libresoc.v:33824$1141 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$33 + connect \B \$35 + connect \Y $or$libresoc.v:33824$1141_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" + cell $or $or$libresoc.v:33835$1152 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \req_done + connect \B \cu_go_die_i + connect \Y $or$libresoc.v:33835$1152_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" + cell $or $or$libresoc.v:33836$1153 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_issue_i + connect \B \cu_go_die_i + connect \Y $or$libresoc.v:33836$1153_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" + cell $or $or$libresoc.v:33837$1154 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \cu_wr__go_i + connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } + connect \Y $or$libresoc.v:33837$1154_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" + cell $or $or$libresoc.v:33838$1155 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \cu_rd__go_i + connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } + connect \Y $or$libresoc.v:33838$1155_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" + cell $or $or$libresoc.v:33842$1159 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \reset_w + connect \B \prev_wr_go + connect \Y $or$libresoc.v:33842$1159_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $or $or$libresoc.v:33852$1169 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \$6 + connect \B \cu_rd__go_i + connect \Y $or$libresoc.v:33852$1169_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $reduce_and $reduce_and$libresoc.v:33801$1118 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $reduce_and$libresoc.v:33801$1118_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $reduce_or $reduce_or$libresoc.v:33819$1136 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \$27 + connect \Y $reduce_or$libresoc.v:33819$1136_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $reduce_or $reduce_or$libresoc.v:33822$1139 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \cu_wr__go_i + connect \Y $reduce_or$libresoc.v:33822$1139_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $reduce_or $reduce_or$libresoc.v:33823$1140 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \prev_wr_go + connect \Y $reduce_or$libresoc.v:33823$1140_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" + cell $mux $ternary$libresoc.v:33846$1163 + parameter \WIDTH 1 + connect \A \src_l_q_src [1] + connect \B \opc_l_q_opc + connect \S \alu_branch0_br_op__imm_data__ok + connect \Y $ternary$libresoc.v:33846$1163_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" + cell $mux $ternary$libresoc.v:33847$1164 + parameter \WIDTH 64 + connect \A \src2_i + connect \B \alu_branch0_br_op__imm_data__data + connect \S \alu_branch0_br_op__imm_data__ok + connect \Y $ternary$libresoc.v:33847$1164_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" + cell $mux $ternary$libresoc.v:33848$1165 + parameter \WIDTH 64 + connect \A \src_r0 + connect \B \src1_i + connect \S \src_l_q_src [0] + connect \Y $ternary$libresoc.v:33848$1165_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" + cell $mux $ternary$libresoc.v:33849$1166 + parameter \WIDTH 64 + connect \A \src_r1 + connect \B \src_or_imm + connect \S \src_sel + connect \Y $ternary$libresoc.v:33849$1166_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" + cell $mux $ternary$libresoc.v:33850$1167 + parameter \WIDTH 4 + connect \A \src_r2 + connect \B \src3_i + connect \S \src_l_q_src [2] + connect \Y $ternary$libresoc.v:33850$1167_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:33922.15-33946.4" + cell \alu_branch0 \alu_branch0 + connect \br_op__cia \alu_branch0_br_op__cia + connect \br_op__fn_unit \alu_branch0_br_op__fn_unit + connect \br_op__imm_data__data \alu_branch0_br_op__imm_data__data + connect \br_op__imm_data__ok \alu_branch0_br_op__imm_data__ok + connect \br_op__insn \alu_branch0_br_op__insn + connect \br_op__insn_type \alu_branch0_br_op__insn_type + connect \br_op__is_32bit \alu_branch0_br_op__is_32bit + connect \br_op__lk \alu_branch0_br_op__lk + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cr_a \alu_branch0_cr_a + connect \fast1 \alu_branch0_fast1 + connect \fast1$1 \alu_branch0_fast1$1 + connect \fast1_ok \fast1_ok + connect \fast2 \alu_branch0_fast2 + connect \fast2$2 \alu_branch0_fast2$2 + connect \fast2_ok \fast2_ok + connect \n_ready_i \alu_branch0_n_ready_i + connect \n_valid_o \alu_branch0_n_valid_o + connect \nia \alu_branch0_nia + connect \nia_ok \nia_ok + connect \p_ready_o \alu_branch0_p_ready_o + connect \p_valid_i \alu_branch0_p_valid_i + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:33947.14-33953.4" + cell \alu_l$29 \alu_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_alu \alu_l_q_alu + connect \r_alu \alu_l_r_alu + connect \s_alu \alu_l_s_alu + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:33954.15-33960.4" + cell \alui_l$28 \alui_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_alui \alui_l_q_alui + connect \r_alui \alui_l_r_alui + connect \s_alui \alui_l_s_alui + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:33961.14-33967.4" + cell \opc_l$24 \opc_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_opc \opc_l_q_opc + connect \r_opc \opc_l_r_opc + connect \s_opc \opc_l_s_opc + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:33968.14-33974.4" + cell \req_l$25 \req_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_req \req_l_q_req + connect \r_req \req_l_r_req + connect \s_req \req_l_s_req + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:33975.14-33981.4" + cell \rok_l$27 \rok_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_rdok \rok_l_q_rdok + connect \r_rdok \rok_l_r_rdok + connect \s_rdok \rok_l_s_rdok + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:33982.14-33987.4" + cell \rst_l$26 \rst_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \r_rst \rst_l_r_rst + connect \s_rst \rst_l_s_rst + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:33988.14-33994.4" + cell \src_l$23 \src_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_src \src_l_q_src + connect \r_src \src_l_r_src + connect \s_src \src_l_s_src + end + attribute \src "libresoc.v:33253.7-33253.20" + process $proc$libresoc.v:33253$1302 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:33371.7-33371.24" + process $proc$libresoc.v:33371$1303 + assign { } { } + assign $1\all_rd_dly[0:0] 1'0 + sync always + sync init + update \all_rd_dly $1\all_rd_dly[0:0] + end + attribute \src "libresoc.v:33379.14-33379.59" + process $proc$libresoc.v:33379$1304 + assign { } { } + assign $1\alu_branch0_br_op__cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \alu_branch0_br_op__cia $1\alu_branch0_br_op__cia[63:0] + end + attribute \src "libresoc.v:33397.14-33397.51" + process $proc$libresoc.v:33397$1305 + assign { } { } + assign $1\alu_branch0_br_op__fn_unit[12:0] 13'0000000000000 + sync always + sync init + update \alu_branch0_br_op__fn_unit $1\alu_branch0_br_op__fn_unit[12:0] + end + attribute \src "libresoc.v:33401.14-33401.70" + process $proc$libresoc.v:33401$1306 + assign { } { } + assign $1\alu_branch0_br_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \alu_branch0_br_op__imm_data__data $1\alu_branch0_br_op__imm_data__data[63:0] + end + attribute \src "libresoc.v:33405.7-33405.45" + process $proc$libresoc.v:33405$1307 + assign { } { } + assign $1\alu_branch0_br_op__imm_data__ok[0:0] 1'0 + sync always + sync init + update \alu_branch0_br_op__imm_data__ok $1\alu_branch0_br_op__imm_data__ok[0:0] + end + attribute \src "libresoc.v:33409.14-33409.45" + process $proc$libresoc.v:33409$1308 + assign { } { } + assign $1\alu_branch0_br_op__insn[31:0] 0 + sync always + sync init + update \alu_branch0_br_op__insn $1\alu_branch0_br_op__insn[31:0] + end + attribute \src "libresoc.v:33487.13-33487.49" + process $proc$libresoc.v:33487$1309 + assign { } { } + assign $1\alu_branch0_br_op__insn_type[6:0] 7'0000000 + sync always + sync init + update \alu_branch0_br_op__insn_type $1\alu_branch0_br_op__insn_type[6:0] + end + attribute \src "libresoc.v:33491.7-33491.41" + process $proc$libresoc.v:33491$1310 + assign { } { } + assign $1\alu_branch0_br_op__is_32bit[0:0] 1'0 + sync always + sync init + update \alu_branch0_br_op__is_32bit $1\alu_branch0_br_op__is_32bit[0:0] + end + attribute \src "libresoc.v:33495.7-33495.35" + process $proc$libresoc.v:33495$1311 + assign { } { } + assign $1\alu_branch0_br_op__lk[0:0] 1'0 + sync always + sync init + update \alu_branch0_br_op__lk $1\alu_branch0_br_op__lk[0:0] + end + attribute \src "libresoc.v:33521.7-33521.26" + process $proc$libresoc.v:33521$1312 + assign { } { } + assign $1\alu_done_dly[0:0] 1'0 + sync always + sync init + update \alu_done_dly $1\alu_done_dly[0:0] + end + attribute \src "libresoc.v:33529.7-33529.25" + process $proc$libresoc.v:33529$1313 + assign { } { } + assign $1\alu_l_r_alu[0:0] 1'1 + sync always + sync init + update \alu_l_r_alu $1\alu_l_r_alu[0:0] + end + attribute \src "libresoc.v:33541.7-33541.27" + process $proc$libresoc.v:33541$1314 + assign { } { } + assign $1\alui_l_r_alui[0:0] 1'1 + sync always + sync init + update \alui_l_r_alui $1\alui_l_r_alui[0:0] + end + attribute \src "libresoc.v:33573.14-33573.51" + process $proc$libresoc.v:33573$1315 + assign { } { } + assign $1\data_r0__fast1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \data_r0__fast1 $1\data_r0__fast1[63:0] + end + attribute \src "libresoc.v:33577.7-33577.31" + process $proc$libresoc.v:33577$1316 + assign { } { } + assign $1\data_r0__fast1_ok[0:0] 1'0 + sync always + sync init + update \data_r0__fast1_ok $1\data_r0__fast1_ok[0:0] + end + attribute \src "libresoc.v:33581.14-33581.51" + process $proc$libresoc.v:33581$1317 + assign { } { } + assign $1\data_r1__fast2[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \data_r1__fast2 $1\data_r1__fast2[63:0] + end + attribute \src "libresoc.v:33585.7-33585.31" + process $proc$libresoc.v:33585$1318 + assign { } { } + assign $1\data_r1__fast2_ok[0:0] 1'0 + sync always + sync init + update \data_r1__fast2_ok $1\data_r1__fast2_ok[0:0] + end + attribute \src "libresoc.v:33589.14-33589.49" + process $proc$libresoc.v:33589$1319 + assign { } { } + assign $1\data_r2__nia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \data_r2__nia $1\data_r2__nia[63:0] + end + attribute \src "libresoc.v:33593.7-33593.29" + process $proc$libresoc.v:33593$1320 + assign { } { } + assign $1\data_r2__nia_ok[0:0] 1'0 + sync always + sync init + update \data_r2__nia_ok $1\data_r2__nia_ok[0:0] + end + attribute \src "libresoc.v:33614.7-33614.25" + process $proc$libresoc.v:33614$1321 + assign { } { } + assign $1\opc_l_r_opc[0:0] 1'1 + sync always + sync init + update \opc_l_r_opc $1\opc_l_r_opc[0:0] + end + attribute \src "libresoc.v:33618.7-33618.25" + process $proc$libresoc.v:33618$1322 + assign { } { } + assign $1\opc_l_s_opc[0:0] 1'0 + sync always + sync init + update \opc_l_s_opc $1\opc_l_s_opc[0:0] + end + attribute \src "libresoc.v:33726.13-33726.30" + process $proc$libresoc.v:33726$1323 + assign { } { } + assign $1\prev_wr_go[2:0] 3'000 + sync always + sync init + update \prev_wr_go $1\prev_wr_go[2:0] + end + attribute \src "libresoc.v:33734.13-33734.31" + process $proc$libresoc.v:33734$1324 + assign { } { } + assign $1\req_l_r_req[2:0] 3'111 + sync always + sync init + update \req_l_r_req $1\req_l_r_req[2:0] + end + attribute \src "libresoc.v:33738.13-33738.31" + process $proc$libresoc.v:33738$1325 + assign { } { } + assign $1\req_l_s_req[2:0] 3'000 + sync always + sync init + update \req_l_s_req $1\req_l_s_req[2:0] + end + attribute \src "libresoc.v:33750.7-33750.26" + process $proc$libresoc.v:33750$1326 + assign { } { } + assign $1\rok_l_r_rdok[0:0] 1'1 + sync always + sync init + update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] + end + attribute \src "libresoc.v:33754.7-33754.26" + process $proc$libresoc.v:33754$1327 + assign { } { } + assign $1\rok_l_s_rdok[0:0] 1'0 + sync always + sync init + update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] + end + attribute \src "libresoc.v:33758.7-33758.25" + process $proc$libresoc.v:33758$1328 + assign { } { } + assign $1\rst_l_r_rst[0:0] 1'1 + sync always + sync init + update \rst_l_r_rst $1\rst_l_r_rst[0:0] + end + attribute \src "libresoc.v:33762.7-33762.25" + process $proc$libresoc.v:33762$1329 + assign { } { } + assign $1\rst_l_s_rst[0:0] 1'0 + sync always + sync init + update \rst_l_s_rst $1\rst_l_s_rst[0:0] + end + attribute \src "libresoc.v:33776.13-33776.31" + process $proc$libresoc.v:33776$1330 + assign { } { } + assign $1\src_l_r_src[2:0] 3'111 + sync always + sync init + update \src_l_r_src $1\src_l_r_src[2:0] + end + attribute \src "libresoc.v:33780.13-33780.31" + process $proc$libresoc.v:33780$1331 + assign { } { } + assign $1\src_l_s_src[2:0] 3'000 + sync always + sync init + update \src_l_s_src $1\src_l_s_src[2:0] + end + attribute \src "libresoc.v:33786.14-33786.43" + process $proc$libresoc.v:33786$1332 + assign { } { } + assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \src_r0 $1\src_r0[63:0] + end + attribute \src "libresoc.v:33790.14-33790.43" + process $proc$libresoc.v:33790$1333 + assign { } { } + assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \src_r1 $1\src_r1[63:0] + end + attribute \src "libresoc.v:33794.13-33794.26" + process $proc$libresoc.v:33794$1334 + assign { } { } + assign $1\src_r2[3:0] 4'0000 + sync always + sync init + update \src_r2 $1\src_r2[3:0] + end + attribute \src "libresoc.v:33858.3-33859.39" + process $proc$libresoc.v:33858$1175 + assign { } { } + assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next + sync posedge \coresync_clk + update \alu_l_r_alu $0\alu_l_r_alu[0:0] + end + attribute \src "libresoc.v:33860.3-33861.43" + process $proc$libresoc.v:33860$1176 + assign { } { } + assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next + sync posedge \coresync_clk + update \alui_l_r_alui $0\alui_l_r_alui[0:0] + end + attribute \src "libresoc.v:33862.3-33863.29" + process $proc$libresoc.v:33862$1177 + assign { } { } + assign $0\src_r2[3:0] \src_r2$next + sync posedge \coresync_clk + update \src_r2 $0\src_r2[3:0] + end + attribute \src "libresoc.v:33864.3-33865.29" + process $proc$libresoc.v:33864$1178 + assign { } { } + assign $0\src_r1[63:0] \src_r1$next + sync posedge \coresync_clk + update \src_r1 $0\src_r1[63:0] + end + attribute \src "libresoc.v:33866.3-33867.29" + process $proc$libresoc.v:33866$1179 + assign { } { } + assign $0\src_r0[63:0] \src_r0$next + sync posedge \coresync_clk + update \src_r0 $0\src_r0[63:0] + end + attribute \src "libresoc.v:33868.3-33869.41" + process $proc$libresoc.v:33868$1180 + assign { } { } + assign $0\data_r2__nia[63:0] \data_r2__nia$next + sync posedge \coresync_clk + update \data_r2__nia $0\data_r2__nia[63:0] + end + attribute \src "libresoc.v:33870.3-33871.47" + process $proc$libresoc.v:33870$1181 + assign { } { } + assign $0\data_r2__nia_ok[0:0] \data_r2__nia_ok$next + sync posedge \coresync_clk + update \data_r2__nia_ok $0\data_r2__nia_ok[0:0] + end + attribute \src "libresoc.v:33872.3-33873.45" + process $proc$libresoc.v:33872$1182 + assign { } { } + assign $0\data_r1__fast2[63:0] \data_r1__fast2$next + sync posedge \coresync_clk + update \data_r1__fast2 $0\data_r1__fast2[63:0] + end + attribute \src "libresoc.v:33874.3-33875.51" + process $proc$libresoc.v:33874$1183 + assign { } { } + assign $0\data_r1__fast2_ok[0:0] \data_r1__fast2_ok$next + sync posedge \coresync_clk + update \data_r1__fast2_ok $0\data_r1__fast2_ok[0:0] + end + attribute \src "libresoc.v:33876.3-33877.45" + process $proc$libresoc.v:33876$1184 + assign { } { } + assign $0\data_r0__fast1[63:0] \data_r0__fast1$next + sync posedge \coresync_clk + update \data_r0__fast1 $0\data_r0__fast1[63:0] + end + attribute \src "libresoc.v:33878.3-33879.51" + process $proc$libresoc.v:33878$1185 + assign { } { } + assign $0\data_r0__fast1_ok[0:0] \data_r0__fast1_ok$next + sync posedge \coresync_clk + update \data_r0__fast1_ok $0\data_r0__fast1_ok[0:0] + end + attribute \src "libresoc.v:33880.3-33881.61" + process $proc$libresoc.v:33880$1186 + assign { } { } + assign $0\alu_branch0_br_op__cia[63:0] \alu_branch0_br_op__cia$next + sync posedge \coresync_clk + update \alu_branch0_br_op__cia $0\alu_branch0_br_op__cia[63:0] + end + attribute \src "libresoc.v:33882.3-33883.73" + process $proc$libresoc.v:33882$1187 + assign { } { } + assign $0\alu_branch0_br_op__insn_type[6:0] \alu_branch0_br_op__insn_type$next + sync posedge \coresync_clk + update \alu_branch0_br_op__insn_type $0\alu_branch0_br_op__insn_type[6:0] + end + attribute \src "libresoc.v:33884.3-33885.69" + process $proc$libresoc.v:33884$1188 + assign { } { } + assign $0\alu_branch0_br_op__fn_unit[12:0] \alu_branch0_br_op__fn_unit$next + sync posedge \coresync_clk + update \alu_branch0_br_op__fn_unit $0\alu_branch0_br_op__fn_unit[12:0] + end + attribute \src "libresoc.v:33886.3-33887.63" + process $proc$libresoc.v:33886$1189 + assign { } { } + assign $0\alu_branch0_br_op__insn[31:0] \alu_branch0_br_op__insn$next + sync posedge \coresync_clk + update \alu_branch0_br_op__insn $0\alu_branch0_br_op__insn[31:0] + end + attribute \src "libresoc.v:33888.3-33889.83" + process $proc$libresoc.v:33888$1190 + assign { } { } + assign $0\alu_branch0_br_op__imm_data__data[63:0] \alu_branch0_br_op__imm_data__data$next + sync posedge \coresync_clk + update \alu_branch0_br_op__imm_data__data $0\alu_branch0_br_op__imm_data__data[63:0] + end + attribute \src "libresoc.v:33890.3-33891.79" + process $proc$libresoc.v:33890$1191 + assign { } { } + assign $0\alu_branch0_br_op__imm_data__ok[0:0] \alu_branch0_br_op__imm_data__ok$next + sync posedge \coresync_clk + update \alu_branch0_br_op__imm_data__ok $0\alu_branch0_br_op__imm_data__ok[0:0] + end + attribute \src "libresoc.v:33892.3-33893.59" + process $proc$libresoc.v:33892$1192 + assign { } { } + assign $0\alu_branch0_br_op__lk[0:0] \alu_branch0_br_op__lk$next + sync posedge \coresync_clk + update \alu_branch0_br_op__lk $0\alu_branch0_br_op__lk[0:0] + end + attribute \src "libresoc.v:33894.3-33895.71" + process $proc$libresoc.v:33894$1193 + assign { } { } + assign $0\alu_branch0_br_op__is_32bit[0:0] \alu_branch0_br_op__is_32bit$next + sync posedge \coresync_clk + update \alu_branch0_br_op__is_32bit $0\alu_branch0_br_op__is_32bit[0:0] + end + attribute \src "libresoc.v:33896.3-33897.39" + process $proc$libresoc.v:33896$1194 + assign { } { } + assign $0\req_l_r_req[2:0] \req_l_r_req$next + sync posedge \coresync_clk + update \req_l_r_req $0\req_l_r_req[2:0] + end + attribute \src "libresoc.v:33898.3-33899.39" + process $proc$libresoc.v:33898$1195 + assign { } { } + assign $0\req_l_s_req[2:0] \req_l_s_req$next + sync posedge \coresync_clk + update \req_l_s_req $0\req_l_s_req[2:0] + end + attribute \src "libresoc.v:33900.3-33901.39" + process $proc$libresoc.v:33900$1196 + assign { } { } + assign $0\src_l_r_src[2:0] \src_l_r_src$next + sync posedge \coresync_clk + update \src_l_r_src $0\src_l_r_src[2:0] + end + attribute \src "libresoc.v:33902.3-33903.39" + process $proc$libresoc.v:33902$1197 + assign { } { } + assign $0\src_l_s_src[2:0] \src_l_s_src$next + sync posedge \coresync_clk + update \src_l_s_src $0\src_l_s_src[2:0] + end + attribute \src "libresoc.v:33904.3-33905.39" + process $proc$libresoc.v:33904$1198 + assign { } { } + assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next + sync posedge \coresync_clk + update \opc_l_r_opc $0\opc_l_r_opc[0:0] + end + attribute \src "libresoc.v:33906.3-33907.39" + process $proc$libresoc.v:33906$1199 + assign { } { } + assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next + sync posedge \coresync_clk + update \opc_l_s_opc $0\opc_l_s_opc[0:0] + end + attribute \src "libresoc.v:33908.3-33909.39" + process $proc$libresoc.v:33908$1200 + assign { } { } + assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next + sync posedge \coresync_clk + update \rst_l_r_rst $0\rst_l_r_rst[0:0] + end + attribute \src "libresoc.v:33910.3-33911.39" + process $proc$libresoc.v:33910$1201 + assign { } { } + assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next + sync posedge \coresync_clk + update \rst_l_s_rst $0\rst_l_s_rst[0:0] + end + attribute \src "libresoc.v:33912.3-33913.41" + process $proc$libresoc.v:33912$1202 + assign { } { } + assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next + sync posedge \coresync_clk + update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] + end + attribute \src "libresoc.v:33914.3-33915.41" + process $proc$libresoc.v:33914$1203 + assign { } { } + assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next + sync posedge \coresync_clk + update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] + end + attribute \src "libresoc.v:33916.3-33917.37" + process $proc$libresoc.v:33916$1204 + assign { } { } + assign $0\prev_wr_go[2:0] \prev_wr_go$next + sync posedge \coresync_clk + update \prev_wr_go $0\prev_wr_go[2:0] + end + attribute \src "libresoc.v:33918.3-33919.43" + process $proc$libresoc.v:33918$1205 + assign { } { } + assign $0\alu_done_dly[0:0] \alu_branch0_n_valid_o + sync posedge \coresync_clk + update \alu_done_dly $0\alu_done_dly[0:0] + end + attribute \src "libresoc.v:33920.3-33921.25" + process $proc$libresoc.v:33920$1206 + assign { } { } + assign $0\all_rd_dly[0:0] \$11 + sync posedge \coresync_clk + update \all_rd_dly $0\all_rd_dly[0:0] + end + attribute \src "libresoc.v:33995.3-34004.6" + process $proc$libresoc.v:33995$1207 + assign { } { } + assign { } { } + assign $0\req_done[0:0] $1\req_done[0:0] + attribute \src "libresoc.v:33996.5-33996.29" + switch \initial + attribute \src "libresoc.v:33996.9-33996.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + switch \$55 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\req_done[0:0] 1'1 + case + assign $1\req_done[0:0] \$47 + end + sync always + update \req_done $0\req_done[0:0] + end + attribute \src "libresoc.v:34005.3-34013.6" + process $proc$libresoc.v:34005$1208 + assign { } { } + assign { } { } + assign $0\rok_l_s_rdok$next[0:0]$1209 $1\rok_l_s_rdok$next[0:0]$1210 + attribute \src "libresoc.v:34006.5-34006.29" + switch \initial + attribute \src "libresoc.v:34006.9-34006.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rok_l_s_rdok$next[0:0]$1210 1'0 + case + assign $1\rok_l_s_rdok$next[0:0]$1210 \cu_issue_i + end + sync always + update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$1209 + end + attribute \src "libresoc.v:34014.3-34022.6" + process $proc$libresoc.v:34014$1211 + assign { } { } + assign { } { } + assign $0\rok_l_r_rdok$next[0:0]$1212 $1\rok_l_r_rdok$next[0:0]$1213 + attribute \src "libresoc.v:34015.5-34015.29" + switch \initial + attribute \src "libresoc.v:34015.9-34015.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rok_l_r_rdok$next[0:0]$1213 1'1 + case + assign $1\rok_l_r_rdok$next[0:0]$1213 \$65 + end + sync always + update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$1212 + end + attribute \src "libresoc.v:34023.3-34031.6" + process $proc$libresoc.v:34023$1214 + assign { } { } + assign { } { } + assign $0\rst_l_s_rst$next[0:0]$1215 $1\rst_l_s_rst$next[0:0]$1216 + attribute \src "libresoc.v:34024.5-34024.29" + switch \initial + attribute \src "libresoc.v:34024.9-34024.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rst_l_s_rst$next[0:0]$1216 1'0 + case + assign $1\rst_l_s_rst$next[0:0]$1216 \all_rd + end + sync always + update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$1215 + end + attribute \src "libresoc.v:34032.3-34040.6" + process $proc$libresoc.v:34032$1217 + assign { } { } + assign { } { } + assign $0\rst_l_r_rst$next[0:0]$1218 $1\rst_l_r_rst$next[0:0]$1219 + attribute \src "libresoc.v:34033.5-34033.29" + switch \initial + attribute \src "libresoc.v:34033.9-34033.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rst_l_r_rst$next[0:0]$1219 1'1 + case + assign $1\rst_l_r_rst$next[0:0]$1219 \rst_r + end + sync always + update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$1218 + end + attribute \src "libresoc.v:34041.3-34049.6" + process $proc$libresoc.v:34041$1220 + assign { } { } + assign { } { } + assign $0\opc_l_s_opc$next[0:0]$1221 $1\opc_l_s_opc$next[0:0]$1222 + attribute \src "libresoc.v:34042.5-34042.29" + switch \initial + attribute \src "libresoc.v:34042.9-34042.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\opc_l_s_opc$next[0:0]$1222 1'0 + case + assign $1\opc_l_s_opc$next[0:0]$1222 \cu_issue_i + end + sync always + update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$1221 + end + attribute \src "libresoc.v:34050.3-34058.6" + process $proc$libresoc.v:34050$1223 + assign { } { } + assign { } { } + assign $0\opc_l_r_opc$next[0:0]$1224 $1\opc_l_r_opc$next[0:0]$1225 + attribute \src "libresoc.v:34051.5-34051.29" + switch \initial + attribute \src "libresoc.v:34051.9-34051.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\opc_l_r_opc$next[0:0]$1225 1'1 + case + assign $1\opc_l_r_opc$next[0:0]$1225 \req_done + end + sync always + update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$1224 + end + attribute \src "libresoc.v:34059.3-34067.6" + process $proc$libresoc.v:34059$1226 + assign { } { } + assign { } { } + assign $0\src_l_s_src$next[2:0]$1227 $1\src_l_s_src$next[2:0]$1228 + attribute \src "libresoc.v:34060.5-34060.29" + switch \initial + attribute \src "libresoc.v:34060.9-34060.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_l_s_src$next[2:0]$1228 3'000 + case + assign $1\src_l_s_src$next[2:0]$1228 { \cu_issue_i \cu_issue_i \cu_issue_i } + end + sync always + update \src_l_s_src$next $0\src_l_s_src$next[2:0]$1227 + end + attribute \src "libresoc.v:34068.3-34076.6" + process $proc$libresoc.v:34068$1229 + assign { } { } + assign { } { } + assign $0\src_l_r_src$next[2:0]$1230 $1\src_l_r_src$next[2:0]$1231 + attribute \src "libresoc.v:34069.5-34069.29" + switch \initial + attribute \src "libresoc.v:34069.9-34069.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_l_r_src$next[2:0]$1231 3'111 + case + assign $1\src_l_r_src$next[2:0]$1231 \reset_r + end + sync always + update \src_l_r_src$next $0\src_l_r_src$next[2:0]$1230 + end + attribute \src "libresoc.v:34077.3-34085.6" + process $proc$libresoc.v:34077$1232 + assign { } { } + assign { } { } + assign $0\req_l_s_req$next[2:0]$1233 $1\req_l_s_req$next[2:0]$1234 + attribute \src "libresoc.v:34078.5-34078.29" + switch \initial + attribute \src "libresoc.v:34078.9-34078.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\req_l_s_req$next[2:0]$1234 3'000 + case + assign $1\req_l_s_req$next[2:0]$1234 \$67 + end + sync always + update \req_l_s_req$next $0\req_l_s_req$next[2:0]$1233 + end + attribute \src "libresoc.v:34086.3-34094.6" + process $proc$libresoc.v:34086$1235 + assign { } { } + assign { } { } + assign $0\req_l_r_req$next[2:0]$1236 $1\req_l_r_req$next[2:0]$1237 + attribute \src "libresoc.v:34087.5-34087.29" + switch \initial + attribute \src "libresoc.v:34087.9-34087.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\req_l_r_req$next[2:0]$1237 3'111 + case + assign $1\req_l_r_req$next[2:0]$1237 \$69 + end + sync always + update \req_l_r_req$next $0\req_l_r_req$next[2:0]$1236 + end + attribute \src "libresoc.v:34095.3-34119.6" + process $proc$libresoc.v:34095$1238 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\alu_branch0_br_op__cia$next[63:0]$1239 $1\alu_branch0_br_op__cia$next[63:0]$1247 + assign $0\alu_branch0_br_op__fn_unit$next[12:0]$1240 $1\alu_branch0_br_op__fn_unit$next[12:0]$1248 + assign { } { } + assign { } { } + assign $0\alu_branch0_br_op__insn$next[31:0]$1243 $1\alu_branch0_br_op__insn$next[31:0]$1251 + assign $0\alu_branch0_br_op__insn_type$next[6:0]$1244 $1\alu_branch0_br_op__insn_type$next[6:0]$1252 + assign $0\alu_branch0_br_op__is_32bit$next[0:0]$1245 $1\alu_branch0_br_op__is_32bit$next[0:0]$1253 + assign $0\alu_branch0_br_op__lk$next[0:0]$1246 $1\alu_branch0_br_op__lk$next[0:0]$1254 + assign $0\alu_branch0_br_op__imm_data__data$next[63:0]$1241 $2\alu_branch0_br_op__imm_data__data$next[63:0]$1255 + assign $0\alu_branch0_br_op__imm_data__ok$next[0:0]$1242 $2\alu_branch0_br_op__imm_data__ok$next[0:0]$1256 + attribute \src "libresoc.v:34096.5-34096.29" + switch \initial + attribute \src "libresoc.v:34096.9-34096.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\alu_branch0_br_op__is_32bit$next[0:0]$1253 $1\alu_branch0_br_op__lk$next[0:0]$1254 $1\alu_branch0_br_op__imm_data__ok$next[0:0]$1250 $1\alu_branch0_br_op__imm_data__data$next[63:0]$1249 $1\alu_branch0_br_op__insn$next[31:0]$1251 $1\alu_branch0_br_op__fn_unit$next[12:0]$1248 $1\alu_branch0_br_op__insn_type$next[6:0]$1252 $1\alu_branch0_br_op__cia$next[63:0]$1247 } { \oper_i_alu_branch0__is_32bit \oper_i_alu_branch0__lk \oper_i_alu_branch0__imm_data__ok \oper_i_alu_branch0__imm_data__data \oper_i_alu_branch0__insn \oper_i_alu_branch0__fn_unit \oper_i_alu_branch0__insn_type \oper_i_alu_branch0__cia } + case + assign $1\alu_branch0_br_op__cia$next[63:0]$1247 \alu_branch0_br_op__cia + assign $1\alu_branch0_br_op__fn_unit$next[12:0]$1248 \alu_branch0_br_op__fn_unit + assign $1\alu_branch0_br_op__imm_data__data$next[63:0]$1249 \alu_branch0_br_op__imm_data__data + assign $1\alu_branch0_br_op__imm_data__ok$next[0:0]$1250 \alu_branch0_br_op__imm_data__ok + assign $1\alu_branch0_br_op__insn$next[31:0]$1251 \alu_branch0_br_op__insn + assign $1\alu_branch0_br_op__insn_type$next[6:0]$1252 \alu_branch0_br_op__insn_type + assign $1\alu_branch0_br_op__is_32bit$next[0:0]$1253 \alu_branch0_br_op__is_32bit + assign $1\alu_branch0_br_op__lk$next[0:0]$1254 \alu_branch0_br_op__lk + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $2\alu_branch0_br_op__imm_data__data$next[63:0]$1255 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\alu_branch0_br_op__imm_data__ok$next[0:0]$1256 1'0 + case + assign $2\alu_branch0_br_op__imm_data__data$next[63:0]$1255 $1\alu_branch0_br_op__imm_data__data$next[63:0]$1249 + assign $2\alu_branch0_br_op__imm_data__ok$next[0:0]$1256 $1\alu_branch0_br_op__imm_data__ok$next[0:0]$1250 + end + sync always + update \alu_branch0_br_op__cia$next $0\alu_branch0_br_op__cia$next[63:0]$1239 + update \alu_branch0_br_op__fn_unit$next $0\alu_branch0_br_op__fn_unit$next[12:0]$1240 + update \alu_branch0_br_op__imm_data__data$next $0\alu_branch0_br_op__imm_data__data$next[63:0]$1241 + update \alu_branch0_br_op__imm_data__ok$next $0\alu_branch0_br_op__imm_data__ok$next[0:0]$1242 + update \alu_branch0_br_op__insn$next $0\alu_branch0_br_op__insn$next[31:0]$1243 + update \alu_branch0_br_op__insn_type$next $0\alu_branch0_br_op__insn_type$next[6:0]$1244 + update \alu_branch0_br_op__is_32bit$next $0\alu_branch0_br_op__is_32bit$next[0:0]$1245 + update \alu_branch0_br_op__lk$next $0\alu_branch0_br_op__lk$next[0:0]$1246 + end + attribute \src "libresoc.v:34120.3-34141.6" + process $proc$libresoc.v:34120$1257 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r0__fast1$next[63:0]$1258 $2\data_r0__fast1$next[63:0]$1262 + assign { } { } + assign $0\data_r0__fast1_ok$next[0:0]$1259 $3\data_r0__fast1_ok$next[0:0]$1264 + attribute \src "libresoc.v:34121.5-34121.29" + switch \initial + attribute \src "libresoc.v:34121.9-34121.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r0__fast1_ok$next[0:0]$1261 $1\data_r0__fast1$next[63:0]$1260 } { \fast1_ok \alu_branch0_fast1 } + case + assign $1\data_r0__fast1$next[63:0]$1260 \data_r0__fast1 + assign $1\data_r0__fast1_ok$next[0:0]$1261 \data_r0__fast1_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r0__fast1_ok$next[0:0]$1263 $2\data_r0__fast1$next[63:0]$1262 } 65'00000000000000000000000000000000000000000000000000000000000000000 + case + assign $2\data_r0__fast1$next[63:0]$1262 $1\data_r0__fast1$next[63:0]$1260 + assign $2\data_r0__fast1_ok$next[0:0]$1263 $1\data_r0__fast1_ok$next[0:0]$1261 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r0__fast1_ok$next[0:0]$1264 1'0 + case + assign $3\data_r0__fast1_ok$next[0:0]$1264 $2\data_r0__fast1_ok$next[0:0]$1263 + end + sync always + update \data_r0__fast1$next $0\data_r0__fast1$next[63:0]$1258 + update \data_r0__fast1_ok$next $0\data_r0__fast1_ok$next[0:0]$1259 + end + attribute \src "libresoc.v:34142.3-34163.6" + process $proc$libresoc.v:34142$1265 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r1__fast2$next[63:0]$1266 $2\data_r1__fast2$next[63:0]$1270 + assign { } { } + assign $0\data_r1__fast2_ok$next[0:0]$1267 $3\data_r1__fast2_ok$next[0:0]$1272 + attribute \src "libresoc.v:34143.5-34143.29" + switch \initial + attribute \src "libresoc.v:34143.9-34143.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r1__fast2_ok$next[0:0]$1269 $1\data_r1__fast2$next[63:0]$1268 } { \fast2_ok \alu_branch0_fast2 } + case + assign $1\data_r1__fast2$next[63:0]$1268 \data_r1__fast2 + assign $1\data_r1__fast2_ok$next[0:0]$1269 \data_r1__fast2_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r1__fast2_ok$next[0:0]$1271 $2\data_r1__fast2$next[63:0]$1270 } 65'00000000000000000000000000000000000000000000000000000000000000000 + case + assign $2\data_r1__fast2$next[63:0]$1270 $1\data_r1__fast2$next[63:0]$1268 + assign $2\data_r1__fast2_ok$next[0:0]$1271 $1\data_r1__fast2_ok$next[0:0]$1269 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r1__fast2_ok$next[0:0]$1272 1'0 + case + assign $3\data_r1__fast2_ok$next[0:0]$1272 $2\data_r1__fast2_ok$next[0:0]$1271 + end + sync always + update \data_r1__fast2$next $0\data_r1__fast2$next[63:0]$1266 + update \data_r1__fast2_ok$next $0\data_r1__fast2_ok$next[0:0]$1267 + end + attribute \src "libresoc.v:34164.3-34185.6" + process $proc$libresoc.v:34164$1273 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r2__nia$next[63:0]$1274 $2\data_r2__nia$next[63:0]$1278 + assign { } { } + assign $0\data_r2__nia_ok$next[0:0]$1275 $3\data_r2__nia_ok$next[0:0]$1280 + attribute \src "libresoc.v:34165.5-34165.29" + switch \initial + attribute \src "libresoc.v:34165.9-34165.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r2__nia_ok$next[0:0]$1277 $1\data_r2__nia$next[63:0]$1276 } { \nia_ok \alu_branch0_nia } + case + assign $1\data_r2__nia$next[63:0]$1276 \data_r2__nia + assign $1\data_r2__nia_ok$next[0:0]$1277 \data_r2__nia_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r2__nia_ok$next[0:0]$1279 $2\data_r2__nia$next[63:0]$1278 } 65'00000000000000000000000000000000000000000000000000000000000000000 + case + assign $2\data_r2__nia$next[63:0]$1278 $1\data_r2__nia$next[63:0]$1276 + assign $2\data_r2__nia_ok$next[0:0]$1279 $1\data_r2__nia_ok$next[0:0]$1277 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r2__nia_ok$next[0:0]$1280 1'0 + case + assign $3\data_r2__nia_ok$next[0:0]$1280 $2\data_r2__nia_ok$next[0:0]$1279 + end + sync always + update \data_r2__nia$next $0\data_r2__nia$next[63:0]$1274 + update \data_r2__nia_ok$next $0\data_r2__nia_ok$next[0:0]$1275 + end + attribute \src "libresoc.v:34186.3-34195.6" + process $proc$libresoc.v:34186$1281 + assign { } { } + assign { } { } + assign $0\src_r0$next[63:0]$1282 $1\src_r0$next[63:0]$1283 + attribute \src "libresoc.v:34187.5-34187.29" + switch \initial + attribute \src "libresoc.v:34187.9-34187.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" + switch \src_l_q_src [0] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r0$next[63:0]$1283 \src1_i + case + assign $1\src_r0$next[63:0]$1283 \src_r0 + end + sync always + update \src_r0$next $0\src_r0$next[63:0]$1282 + end + attribute \src "libresoc.v:34196.3-34205.6" + process $proc$libresoc.v:34196$1284 + assign { } { } + assign { } { } + assign $0\src_r1$next[63:0]$1285 $1\src_r1$next[63:0]$1286 + attribute \src "libresoc.v:34197.5-34197.29" + switch \initial + attribute \src "libresoc.v:34197.9-34197.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" + switch \src_sel + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r1$next[63:0]$1286 \src_or_imm + case + assign $1\src_r1$next[63:0]$1286 \src_r1 + end + sync always + update \src_r1$next $0\src_r1$next[63:0]$1285 + end + attribute \src "libresoc.v:34206.3-34215.6" + process $proc$libresoc.v:34206$1287 + assign { } { } + assign { } { } + assign $0\src_r2$next[3:0]$1288 $1\src_r2$next[3:0]$1289 + attribute \src "libresoc.v:34207.5-34207.29" + switch \initial + attribute \src "libresoc.v:34207.9-34207.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" + switch \src_l_q_src [2] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r2$next[3:0]$1289 \src3_i + case + assign $1\src_r2$next[3:0]$1289 \src_r2 + end + sync always + update \src_r2$next $0\src_r2$next[3:0]$1288 + end + attribute \src "libresoc.v:34216.3-34224.6" + process $proc$libresoc.v:34216$1290 + assign { } { } + assign { } { } + assign $0\alui_l_r_alui$next[0:0]$1291 $1\alui_l_r_alui$next[0:0]$1292 + attribute \src "libresoc.v:34217.5-34217.29" + switch \initial + attribute \src "libresoc.v:34217.9-34217.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\alui_l_r_alui$next[0:0]$1292 1'1 + case + assign $1\alui_l_r_alui$next[0:0]$1292 \$87 + end + sync always + update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$1291 + end + attribute \src "libresoc.v:34225.3-34233.6" + process $proc$libresoc.v:34225$1293 + assign { } { } + assign { } { } + assign $0\alu_l_r_alu$next[0:0]$1294 $1\alu_l_r_alu$next[0:0]$1295 + attribute \src "libresoc.v:34226.5-34226.29" + switch \initial + attribute \src "libresoc.v:34226.9-34226.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\alu_l_r_alu$next[0:0]$1295 1'1 + case + assign $1\alu_l_r_alu$next[0:0]$1295 \$89 + end + sync always + update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$1294 + end + attribute \src "libresoc.v:34234.3-34243.6" + process $proc$libresoc.v:34234$1296 + assign { } { } + assign { } { } + assign $0\dest1_o[63:0] $1\dest1_o[63:0] + attribute \src "libresoc.v:34235.5-34235.29" + switch \initial + attribute \src "libresoc.v:34235.9-34235.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$111 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest1_o[63:0] \data_r0__fast1 + case + assign $1\dest1_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \dest1_o $0\dest1_o[63:0] + end + attribute \src "libresoc.v:34244.3-34253.6" + process $proc$libresoc.v:34244$1297 + assign { } { } + assign { } { } + assign $0\dest2_o[63:0] $1\dest2_o[63:0] + attribute \src "libresoc.v:34245.5-34245.29" + switch \initial + attribute \src "libresoc.v:34245.9-34245.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$113 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest2_o[63:0] \data_r1__fast2 + case + assign $1\dest2_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \dest2_o $0\dest2_o[63:0] + end + attribute \src "libresoc.v:34254.3-34263.6" + process $proc$libresoc.v:34254$1298 + assign { } { } + assign { } { } + assign $0\dest3_o[63:0] $1\dest3_o[63:0] + attribute \src "libresoc.v:34255.5-34255.29" + switch \initial + attribute \src "libresoc.v:34255.9-34255.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$115 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest3_o[63:0] \data_r2__nia + case + assign $1\dest3_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \dest3_o $0\dest3_o[63:0] + end + attribute \src "libresoc.v:34264.3-34272.6" + process $proc$libresoc.v:34264$1299 + assign { } { } + assign { } { } + assign $0\prev_wr_go$next[2:0]$1300 $1\prev_wr_go$next[2:0]$1301 + attribute \src "libresoc.v:34265.5-34265.29" + switch \initial + attribute \src "libresoc.v:34265.9-34265.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\prev_wr_go$next[2:0]$1301 3'000 + case + assign $1\prev_wr_go$next[2:0]$1301 \$21 + end + sync always + update \prev_wr_go$next $0\prev_wr_go$next[2:0]$1300 + end + connect \$5 $reduce_and$libresoc.v:33801$1118_Y + connect \$99 $and$libresoc.v:33802$1119_Y + connect \$101 $and$libresoc.v:33803$1120_Y + connect \$103 $and$libresoc.v:33804$1121_Y + connect \$105 $and$libresoc.v:33805$1122_Y + connect \$107 $and$libresoc.v:33806$1123_Y + connect \$109 $and$libresoc.v:33807$1124_Y + connect \$111 $and$libresoc.v:33808$1125_Y + connect \$113 $and$libresoc.v:33809$1126_Y + connect \$115 $and$libresoc.v:33810$1127_Y + connect \$11 $and$libresoc.v:33811$1128_Y + connect \$13 $not$libresoc.v:33812$1129_Y + connect \$15 $and$libresoc.v:33813$1130_Y + connect \$17 $not$libresoc.v:33814$1131_Y + connect \$19 $and$libresoc.v:33815$1132_Y + connect \$21 $and$libresoc.v:33816$1133_Y + connect \$25 $not$libresoc.v:33817$1134_Y + connect \$27 $and$libresoc.v:33818$1135_Y + connect \$24 $reduce_or$libresoc.v:33819$1136_Y + connect \$23 $not$libresoc.v:33820$1137_Y + connect \$31 $and$libresoc.v:33821$1138_Y + connect \$33 $reduce_or$libresoc.v:33822$1139_Y + connect \$35 $reduce_or$libresoc.v:33823$1140_Y + connect \$37 $or$libresoc.v:33824$1141_Y + connect \$3 $and$libresoc.v:33825$1142_Y + connect \$39 $not$libresoc.v:33826$1143_Y + connect \$41 $and$libresoc.v:33827$1144_Y + connect \$43 $and$libresoc.v:33828$1145_Y + connect \$45 $eq$libresoc.v:33829$1146_Y + connect \$47 $and$libresoc.v:33830$1147_Y + connect \$49 $eq$libresoc.v:33831$1148_Y + connect \$51 $and$libresoc.v:33832$1149_Y + connect \$53 $and$libresoc.v:33833$1150_Y + connect \$55 $and$libresoc.v:33834$1151_Y + connect \$57 $or$libresoc.v:33835$1152_Y + connect \$59 $or$libresoc.v:33836$1153_Y + connect \$61 $or$libresoc.v:33837$1154_Y + connect \$63 $or$libresoc.v:33838$1155_Y + connect \$65 $and$libresoc.v:33839$1156_Y + connect \$67 $and$libresoc.v:33840$1157_Y + connect \$6 $not$libresoc.v:33841$1158_Y + connect \$69 $or$libresoc.v:33842$1159_Y + connect \$71 $and$libresoc.v:33843$1160_Y + connect \$73 $and$libresoc.v:33844$1161_Y + connect \$75 $and$libresoc.v:33845$1162_Y + connect \$77 $ternary$libresoc.v:33846$1163_Y + connect \$79 $ternary$libresoc.v:33847$1164_Y + connect \$81 $ternary$libresoc.v:33848$1165_Y + connect \$83 $ternary$libresoc.v:33849$1166_Y + connect \$85 $ternary$libresoc.v:33850$1167_Y + connect \$87 $and$libresoc.v:33851$1168_Y + connect \$8 $or$libresoc.v:33852$1169_Y + connect \$89 $and$libresoc.v:33853$1170_Y + connect \$91 $and$libresoc.v:33854$1171_Y + connect \$93 $not$libresoc.v:33855$1172_Y + connect \$95 $and$libresoc.v:33856$1173_Y + connect \$97 $not$libresoc.v:33857$1174_Y + connect \cu_go_die_i 1'0 + connect \cu_shadown_i 1'1 + connect \cu_wr__rel_o \$109 + connect \cu_rd__rel_o \$99 + connect \cu_busy_o \opc_l_q_opc + connect \alu_l_s_alu \all_rd_pulse + connect \alu_branch0_n_ready_i \alu_l_q_alu + connect \alui_l_s_alui \all_rd_pulse + connect \alu_branch0_p_valid_i \alui_l_q_alui + connect \alu_branch0_cr_a \$85 + connect \alu_branch0_fast2$2 \$83 + connect \alu_branch0_fast1$1 \$81 + connect \src_or_imm \$79 + connect \src_sel \$77 + connect \cu_wrmask_o { \$75 \$73 \$71 } + connect \reset_r \$63 + connect \reset_w \$61 + connect \rst_r \$59 + connect \reset \$57 + connect \wr_any \$37 + connect \cu_done_o \$31 + connect \alu_pulsem { \alu_pulse \alu_pulse \alu_pulse } + connect \alu_pulse \alu_done_rise + connect \alu_done_rise \$19 + connect \alu_done_dly$next \alu_done + connect \alu_done \alu_branch0_n_valid_o + connect \all_rd_pulse \all_rd_rise + connect \all_rd_rise \$15 + connect \all_rd_dly$next \all_rd + connect \all_rd \$11 +end +attribute \src "libresoc.v:34307.1-34365.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem.busy_l" +attribute \generator "nMigen" +module \busy_l + attribute \src "libresoc.v:34308.7-34308.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:34353.3-34361.6" + wire $0\q_int$next[0:0]$1345 + attribute \src "libresoc.v:34351.3-34352.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:34353.3-34361.6" + wire $1\q_int$next[0:0]$1346 + attribute \src "libresoc.v:34332.7-34332.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:34343.17-34343.96" + wire $and$libresoc.v:34343$1335_Y + attribute \src "libresoc.v:34348.17-34348.96" + wire $and$libresoc.v:34348$1340_Y + attribute \src "libresoc.v:34345.18-34345.94" + wire $not$libresoc.v:34345$1337_Y + attribute \src "libresoc.v:34347.17-34347.93" + wire $not$libresoc.v:34347$1339_Y + attribute \src "libresoc.v:34350.17-34350.93" + wire $not$libresoc.v:34350$1342_Y + attribute \src "libresoc.v:34344.18-34344.99" + wire $or$libresoc.v:34344$1336_Y + attribute \src "libresoc.v:34346.18-34346.100" + wire $or$libresoc.v:34346$1338_Y + attribute \src "libresoc.v:34349.17-34349.98" + wire $or$libresoc.v:34349$1341_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 1 \coresync_rst + attribute \src "libresoc.v:34308.7-34308.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire output 4 \q_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" + wire \qlq_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \qn_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire input 3 \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire input 2 \s_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:34343$1335 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:34343$1335_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:34348$1340 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:34348$1340_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:34345$1337 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_busy + connect \Y $not$libresoc.v:34345$1337_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:34347$1339 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_busy + connect \Y $not$libresoc.v:34347$1339_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:34350$1342 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_busy + connect \Y $not$libresoc.v:34350$1342_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:34344$1336 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_busy + connect \Y $or$libresoc.v:34344$1336_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:34346$1338 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_busy + connect \B \q_int + connect \Y $or$libresoc.v:34346$1338_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:34349$1341 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_busy + connect \Y $or$libresoc.v:34349$1341_Y + end + attribute \src "libresoc.v:34308.7-34308.20" + process $proc$libresoc.v:34308$1347 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:34332.7-34332.19" + process $proc$libresoc.v:34332$1348 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:34351.3-34352.27" + process $proc$libresoc.v:34351$1343 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:34353.3-34361.6" + process $proc$libresoc.v:34353$1344 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$1345 $1\q_int$next[0:0]$1346 + attribute \src "libresoc.v:34354.5-34354.29" + switch \initial + attribute \src "libresoc.v:34354.9-34354.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$1346 1'0 + case + assign $1\q_int$next[0:0]$1346 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$1345 + end + connect \$9 $and$libresoc.v:34343$1335_Y + connect \$11 $or$libresoc.v:34344$1336_Y + connect \$13 $not$libresoc.v:34345$1337_Y + connect \$15 $or$libresoc.v:34346$1338_Y + connect \$1 $not$libresoc.v:34347$1339_Y + connect \$3 $and$libresoc.v:34348$1340_Y + connect \$5 $or$libresoc.v:34349$1341_Y + connect \$7 $not$libresoc.v:34350$1342_Y + connect \qlq_busy \$15 + connect \qn_busy \$13 + connect \q_busy \$11 +end +attribute \src "libresoc.v:34369.1-35977.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe1.main.clz" +attribute \generator "nMigen" +module \clz + attribute \src "libresoc.v:34844.3-34858.6" + wire width 2 $0\cnt_1_0[1:0] + attribute \src "libresoc.v:34934.3-34948.6" + wire width 2 $0\cnt_1_10[1:0] + attribute \src "libresoc.v:34949.3-34963.6" + wire width 2 $0\cnt_1_11[1:0] + attribute \src "libresoc.v:34964.3-34978.6" + wire width 2 $0\cnt_1_12[1:0] + attribute \src "libresoc.v:34979.3-34993.6" + wire width 2 $0\cnt_1_13[1:0] + attribute \src "libresoc.v:34994.3-35008.6" + wire width 2 $0\cnt_1_14[1:0] + attribute \src "libresoc.v:35024.3-35038.6" + wire width 2 $0\cnt_1_15[1:0] + attribute \src "libresoc.v:35039.3-35053.6" + wire width 2 $0\cnt_1_16[1:0] + attribute \src "libresoc.v:35054.3-35068.6" + wire width 2 $0\cnt_1_17[1:0] + attribute \src "libresoc.v:35069.3-35083.6" + wire width 2 $0\cnt_1_18[1:0] + attribute \src "libresoc.v:35084.3-35098.6" + wire width 2 $0\cnt_1_19[1:0] + attribute \src "libresoc.v:35009.3-35023.6" + wire width 2 $0\cnt_1_1[1:0] + attribute \src "libresoc.v:35099.3-35113.6" + wire width 2 $0\cnt_1_20[1:0] + attribute \src "libresoc.v:35114.3-35128.6" + wire width 2 $0\cnt_1_21[1:0] + attribute \src "libresoc.v:35129.3-35143.6" + wire width 2 $0\cnt_1_22[1:0] + attribute \src "libresoc.v:35144.3-35158.6" + wire width 2 $0\cnt_1_23[1:0] + attribute \src "libresoc.v:35159.3-35173.6" + wire width 2 $0\cnt_1_24[1:0] + attribute \src "libresoc.v:35189.3-35203.6" + wire width 2 $0\cnt_1_25[1:0] + attribute \src "libresoc.v:35204.3-35218.6" + wire width 2 $0\cnt_1_26[1:0] + attribute \src "libresoc.v:35219.3-35233.6" + wire width 2 $0\cnt_1_27[1:0] + attribute \src "libresoc.v:35234.3-35248.6" + wire width 2 $0\cnt_1_28[1:0] + attribute \src "libresoc.v:35249.3-35263.6" + wire width 2 $0\cnt_1_29[1:0] + attribute \src "libresoc.v:35174.3-35188.6" + wire width 2 $0\cnt_1_2[1:0] + attribute \src "libresoc.v:35264.3-35278.6" + wire width 2 $0\cnt_1_30[1:0] + attribute \src "libresoc.v:35279.3-35293.6" + wire width 2 $0\cnt_1_31[1:0] + attribute \src "libresoc.v:35414.3-35428.6" + wire width 2 $0\cnt_1_3[1:0] + attribute \src "libresoc.v:35829.3-35843.6" + wire width 2 $0\cnt_1_4[1:0] + attribute \src "libresoc.v:34859.3-34873.6" + wire width 2 $0\cnt_1_5[1:0] + attribute \src "libresoc.v:34874.3-34888.6" + wire width 2 $0\cnt_1_6[1:0] + attribute \src "libresoc.v:34889.3-34903.6" + wire width 2 $0\cnt_1_7[1:0] + attribute \src "libresoc.v:34904.3-34918.6" + wire width 2 $0\cnt_1_8[1:0] + attribute \src "libresoc.v:34919.3-34933.6" + wire width 2 $0\cnt_1_9[1:0] + attribute \src "libresoc.v:35294.3-35313.6" + wire width 3 $0\cnt_2_0[2:0] + attribute \src "libresoc.v:35394.3-35413.6" + wire width 3 $0\cnt_2_10[2:0] + attribute \src "libresoc.v:35429.3-35448.6" + wire width 3 $0\cnt_2_12[2:0] + attribute \src "libresoc.v:35449.3-35468.6" + wire width 3 $0\cnt_2_14[2:0] + attribute \src "libresoc.v:35469.3-35488.6" + wire width 3 $0\cnt_2_16[2:0] + attribute \src "libresoc.v:35489.3-35508.6" + wire width 3 $0\cnt_2_18[2:0] + attribute \src "libresoc.v:35509.3-35528.6" + wire width 3 $0\cnt_2_20[2:0] + attribute \src "libresoc.v:35529.3-35548.6" + wire width 3 $0\cnt_2_22[2:0] + attribute \src "libresoc.v:35549.3-35568.6" + wire width 3 $0\cnt_2_24[2:0] + attribute \src "libresoc.v:35569.3-35588.6" + wire width 3 $0\cnt_2_26[2:0] + attribute \src "libresoc.v:35589.3-35608.6" + wire width 3 $0\cnt_2_28[2:0] + attribute \src "libresoc.v:35314.3-35333.6" + wire width 3 $0\cnt_2_2[2:0] + attribute \src "libresoc.v:35609.3-35628.6" + wire width 3 $0\cnt_2_30[2:0] + attribute \src "libresoc.v:35334.3-35353.6" + wire width 3 $0\cnt_2_4[2:0] + attribute \src "libresoc.v:35354.3-35373.6" + wire width 3 $0\cnt_2_6[2:0] + attribute \src "libresoc.v:35374.3-35393.6" + wire width 3 $0\cnt_2_8[2:0] + attribute \src "libresoc.v:35629.3-35648.6" + wire width 4 $0\cnt_3_0[3:0] + attribute \src "libresoc.v:35729.3-35748.6" + wire width 4 $0\cnt_3_10[3:0] + attribute \src "libresoc.v:35749.3-35768.6" + wire width 4 $0\cnt_3_12[3:0] + attribute \src "libresoc.v:35769.3-35788.6" + wire width 4 $0\cnt_3_14[3:0] + attribute \src "libresoc.v:35649.3-35668.6" + wire width 4 $0\cnt_3_2[3:0] + attribute \src "libresoc.v:35669.3-35688.6" + wire width 4 $0\cnt_3_4[3:0] + attribute \src "libresoc.v:35689.3-35708.6" + wire width 4 $0\cnt_3_6[3:0] + attribute \src "libresoc.v:35709.3-35728.6" + wire width 4 $0\cnt_3_8[3:0] + attribute \src "libresoc.v:35789.3-35808.6" + wire width 5 $0\cnt_4_0[4:0] + attribute \src "libresoc.v:35809.3-35828.6" + wire width 5 $0\cnt_4_2[4:0] + attribute \src "libresoc.v:35844.3-35863.6" + wire width 5 $0\cnt_4_4[4:0] + attribute \src "libresoc.v:35864.3-35883.6" + wire width 5 $0\cnt_4_6[4:0] + attribute \src "libresoc.v:35884.3-35903.6" + wire width 6 $0\cnt_5_0[5:0] + attribute \src "libresoc.v:35904.3-35923.6" + wire width 6 $0\cnt_5_2[5:0] + attribute \src "libresoc.v:35924.3-35943.6" + wire width 7 $0\cnt_6_0[6:0] + attribute \src "libresoc.v:34370.7-34370.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:34844.3-34858.6" + wire width 2 $1\cnt_1_0[1:0] + attribute \src "libresoc.v:34934.3-34948.6" + wire width 2 $1\cnt_1_10[1:0] + attribute \src "libresoc.v:34949.3-34963.6" + wire width 2 $1\cnt_1_11[1:0] + attribute \src "libresoc.v:34964.3-34978.6" + wire width 2 $1\cnt_1_12[1:0] + attribute \src "libresoc.v:34979.3-34993.6" + wire width 2 $1\cnt_1_13[1:0] + attribute \src "libresoc.v:34994.3-35008.6" + wire width 2 $1\cnt_1_14[1:0] + attribute \src "libresoc.v:35024.3-35038.6" + wire width 2 $1\cnt_1_15[1:0] + attribute \src "libresoc.v:35039.3-35053.6" + wire width 2 $1\cnt_1_16[1:0] + attribute \src "libresoc.v:35054.3-35068.6" + wire width 2 $1\cnt_1_17[1:0] + attribute \src "libresoc.v:35069.3-35083.6" + wire width 2 $1\cnt_1_18[1:0] + attribute \src "libresoc.v:35084.3-35098.6" + wire width 2 $1\cnt_1_19[1:0] + attribute \src "libresoc.v:35009.3-35023.6" + wire width 2 $1\cnt_1_1[1:0] + attribute \src "libresoc.v:35099.3-35113.6" + wire width 2 $1\cnt_1_20[1:0] + attribute \src "libresoc.v:35114.3-35128.6" + wire width 2 $1\cnt_1_21[1:0] + attribute \src "libresoc.v:35129.3-35143.6" + wire width 2 $1\cnt_1_22[1:0] + attribute \src "libresoc.v:35144.3-35158.6" + wire width 2 $1\cnt_1_23[1:0] + attribute \src "libresoc.v:35159.3-35173.6" + wire width 2 $1\cnt_1_24[1:0] + attribute \src "libresoc.v:35189.3-35203.6" + wire width 2 $1\cnt_1_25[1:0] + attribute \src "libresoc.v:35204.3-35218.6" + wire width 2 $1\cnt_1_26[1:0] + attribute \src "libresoc.v:35219.3-35233.6" + wire width 2 $1\cnt_1_27[1:0] + attribute \src "libresoc.v:35234.3-35248.6" + wire width 2 $1\cnt_1_28[1:0] + attribute \src "libresoc.v:35249.3-35263.6" + wire width 2 $1\cnt_1_29[1:0] + attribute \src "libresoc.v:35174.3-35188.6" + wire width 2 $1\cnt_1_2[1:0] + attribute \src "libresoc.v:35264.3-35278.6" + wire width 2 $1\cnt_1_30[1:0] + attribute \src "libresoc.v:35279.3-35293.6" + wire width 2 $1\cnt_1_31[1:0] + attribute \src "libresoc.v:35414.3-35428.6" + wire width 2 $1\cnt_1_3[1:0] + attribute \src "libresoc.v:35829.3-35843.6" + wire width 2 $1\cnt_1_4[1:0] + attribute \src "libresoc.v:34859.3-34873.6" + wire width 2 $1\cnt_1_5[1:0] + attribute \src "libresoc.v:34874.3-34888.6" + wire width 2 $1\cnt_1_6[1:0] + attribute \src "libresoc.v:34889.3-34903.6" + wire width 2 $1\cnt_1_7[1:0] + attribute \src "libresoc.v:34904.3-34918.6" + wire width 2 $1\cnt_1_8[1:0] + attribute \src "libresoc.v:34919.3-34933.6" + wire width 2 $1\cnt_1_9[1:0] + attribute \src "libresoc.v:35294.3-35313.6" + wire width 3 $1\cnt_2_0[2:0] + attribute \src "libresoc.v:35394.3-35413.6" + wire width 3 $1\cnt_2_10[2:0] + attribute \src "libresoc.v:35429.3-35448.6" + wire width 3 $1\cnt_2_12[2:0] + attribute \src "libresoc.v:35449.3-35468.6" + wire width 3 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wire \$37 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + wire \$39 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" + wire width 3 \$41 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + wire \$43 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + wire \$45 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" + wire width 3 \$47 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + wire \$49 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" + wire width 3 \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + wire \$51 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" + wire width 3 \$53 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + wire \$55 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + wire \$57 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" + wire width 3 \$59 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + wire \$61 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + wire \$63 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" + wire width 3 \$65 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + wire \$67 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + wire \$69 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" + wire width 3 \$71 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + wire \$73 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + wire \$75 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" + wire width 3 \$77 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + wire \$79 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + wire \$81 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" + wire width 3 \$83 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + wire \$85 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + wire \$87 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" + wire width 3 \$89 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + wire \$91 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + wire \$93 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" + wire width 3 \$95 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + wire \$97 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + wire \$99 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" + wire width 2 \cnt_1_0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" + wire width 2 \cnt_1_1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" + wire width 2 \cnt_1_10 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" + wire width 2 \cnt_1_11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" + wire width 2 \cnt_1_12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" + wire width 2 \cnt_1_13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" + wire width 2 \cnt_1_14 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" + wire width 2 \cnt_1_15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" + wire width 2 \cnt_1_16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" + wire width 2 \cnt_1_17 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" + wire width 2 \cnt_1_18 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" + wire width 2 \cnt_1_19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" + wire width 2 \cnt_1_2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" + wire width 2 \cnt_1_20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" + wire width 2 \cnt_1_21 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" + wire width 2 \cnt_1_22 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" + wire width 2 \cnt_1_23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" + wire width 2 \cnt_1_24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" + wire width 2 \cnt_1_25 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" + wire width 2 \cnt_1_26 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" + wire width 2 \cnt_1_27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" + wire width 2 \cnt_1_28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" + wire width 2 \cnt_1_29 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" + wire width 2 \cnt_1_3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" + wire width 2 \cnt_1_30 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" + wire width 2 \cnt_1_31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" + wire width 2 \cnt_1_4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" + wire width 2 \cnt_1_5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" + wire width 2 \cnt_1_6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" + wire width 2 \cnt_1_7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" + wire width 2 \cnt_1_8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" + wire width 2 \cnt_1_9 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" + wire width 3 \cnt_2_0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" + wire width 3 \cnt_2_10 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" + wire width 3 \cnt_2_12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" + wire width 3 \cnt_2_14 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" + wire width 3 \cnt_2_16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" + wire width 3 \cnt_2_18 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" + wire width 3 \cnt_2_2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" + wire width 3 \cnt_2_20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" + wire width 3 \cnt_2_22 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" + wire width 3 \cnt_2_24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" + wire width 3 \cnt_2_26 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" + wire width 3 \cnt_2_28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" + wire width 3 \cnt_2_30 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" + wire width 3 \cnt_2_4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" + wire width 3 \cnt_2_6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" + wire width 3 \cnt_2_8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" + wire width 4 \cnt_3_0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" + wire width 4 \cnt_3_10 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" + wire width 4 \cnt_3_12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" + wire width 4 \cnt_3_14 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" + wire width 4 \cnt_3_2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" + wire width 4 \cnt_3_4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" + wire width 4 \cnt_3_6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" + wire width 4 \cnt_3_8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" + wire width 5 \cnt_4_0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" + wire width 5 \cnt_4_2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" + wire width 5 \cnt_4_4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" + wire width 5 \cnt_4_6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" + wire width 6 \cnt_5_0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" + wire width 6 \cnt_5_2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" + wire width 7 \cnt_6_0 + attribute \src "libresoc.v:34370.7-34370.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:18" + wire width 7 output 1 \lz + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" + wire width 2 \pair0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" + wire width 2 \pair10 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" + wire width 2 \pair12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" + wire width 2 \pair14 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" + wire width 2 \pair16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" + wire width 2 \pair18 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" + wire width 2 \pair2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" + wire width 2 \pair20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" + wire width 2 \pair22 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" + wire width 2 \pair24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" + wire width 2 \pair26 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" + wire width 2 \pair28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" + wire width 2 \pair30 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" + wire width 2 \pair32 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" + wire width 2 \pair34 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" + wire width 2 \pair36 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" + wire width 2 \pair38 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" + wire width 2 \pair4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" + wire width 2 \pair40 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" + wire width 2 \pair42 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" + wire width 2 \pair44 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" + wire width 2 \pair46 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" + wire width 2 \pair48 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" + wire width 2 \pair50 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" + wire width 2 \pair52 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" + wire width 2 \pair54 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" + wire width 2 \pair56 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" + wire width 2 \pair58 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" + wire width 2 \pair6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" + wire width 2 \pair60 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" + wire width 2 \pair62 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" + wire width 2 \pair8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:16" + wire width 64 input 2 \sig_in + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + cell $eq $eq$libresoc.v:34751$1349 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_2 [1] + connect \B 1'1 + connect \Y $eq$libresoc.v:34751$1349_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + cell $eq $eq$libresoc.v:34752$1350 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_2_0 [2] + connect \B 1'1 + connect \Y $eq$libresoc.v:34752$1350_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + cell $eq $eq$libresoc.v:34754$1352 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_2_6 [2] + connect \B 1'1 + connect \Y $eq$libresoc.v:34754$1352_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + cell $eq $eq$libresoc.v:34755$1353 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_2_4 [2] + connect \B 1'1 + connect \Y $eq$libresoc.v:34755$1353_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + cell $eq $eq$libresoc.v:34757$1355 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_2_10 [2] + connect \B 1'1 + connect \Y $eq$libresoc.v:34757$1355_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + cell $eq $eq$libresoc.v:34758$1356 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_2_8 [2] + connect \B 1'1 + connect \Y $eq$libresoc.v:34758$1356_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + cell $eq $eq$libresoc.v:34760$1358 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_2_14 [2] + connect \B 1'1 + connect \Y $eq$libresoc.v:34760$1358_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + cell $eq $eq$libresoc.v:34761$1359 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_2_12 [2] + connect \B 1'1 + connect \Y $eq$libresoc.v:34761$1359_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + cell $eq $eq$libresoc.v:34764$1362 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_2_18 [2] + connect \B 1'1 + connect \Y $eq$libresoc.v:34764$1362_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + cell $eq $eq$libresoc.v:34765$1363 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_2_16 [2] + connect \B 1'1 + connect \Y $eq$libresoc.v:34765$1363_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + cell $eq $eq$libresoc.v:34767$1365 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_2_22 [2] + connect \B 1'1 + connect \Y $eq$libresoc.v:34767$1365_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + cell $eq $eq$libresoc.v:34768$1366 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_2_20 [2] + connect \B 1'1 + connect \Y $eq$libresoc.v:34768$1366_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + cell $eq $eq$libresoc.v:34770$1368 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_2_26 [2] + connect \B 1'1 + connect \Y $eq$libresoc.v:34770$1368_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + cell $eq $eq$libresoc.v:34771$1369 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_2_24 [2] + connect \B 1'1 + connect \Y $eq$libresoc.v:34771$1369_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + cell $eq $eq$libresoc.v:34773$1371 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_5 [1] + connect \B 1'1 + connect \Y $eq$libresoc.v:34773$1371_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + cell $eq $eq$libresoc.v:34774$1372 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_2_30 [2] + connect \B 1'1 + connect \Y $eq$libresoc.v:34774$1372_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + cell $eq $eq$libresoc.v:34775$1373 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_2_28 [2] + connect \B 1'1 + connect \Y $eq$libresoc.v:34775$1373_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + cell $eq $eq$libresoc.v:34777$1375 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_3_2 [3] + connect \B 1'1 + connect \Y $eq$libresoc.v:34777$1375_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + cell $eq $eq$libresoc.v:34778$1376 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_3_0 [3] + connect \B 1'1 + connect \Y $eq$libresoc.v:34778$1376_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + cell $eq $eq$libresoc.v:34780$1378 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_3_6 [3] + connect \B 1'1 + connect \Y $eq$libresoc.v:34780$1378_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + cell $eq $eq$libresoc.v:34781$1379 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_3_4 [3] + connect \B 1'1 + connect \Y $eq$libresoc.v:34781$1379_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + cell $eq $eq$libresoc.v:34783$1381 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_3_10 [3] + connect \B 1'1 + connect \Y $eq$libresoc.v:34783$1381_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + cell $eq $eq$libresoc.v:34784$1382 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_4 [1] + connect \B 1'1 + connect \Y $eq$libresoc.v:34784$1382_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + cell $eq $eq$libresoc.v:34785$1383 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_3_8 [3] + connect \B 1'1 + connect \Y $eq$libresoc.v:34785$1383_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + cell $eq $eq$libresoc.v:34787$1385 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_3_14 [3] + connect \B 1'1 + connect \Y $eq$libresoc.v:34787$1385_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + cell $eq $eq$libresoc.v:34788$1386 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_3_12 [3] + connect \B 1'1 + connect \Y $eq$libresoc.v:34788$1386_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + cell $eq $eq$libresoc.v:34790$1388 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_4_2 [4] + connect \B 1'1 + connect \Y $eq$libresoc.v:34790$1388_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + cell $eq $eq$libresoc.v:34791$1389 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_4_0 [4] + connect \B 1'1 + connect \Y $eq$libresoc.v:34791$1389_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + cell $eq $eq$libresoc.v:34793$1391 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_4_6 [4] + connect \B 1'1 + connect \Y $eq$libresoc.v:34793$1391_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + cell $eq $eq$libresoc.v:34794$1392 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_4_4 [4] + connect \B 1'1 + connect \Y $eq$libresoc.v:34794$1392_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + cell $eq $eq$libresoc.v:34797$1395 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_5_2 [5] + connect \B 1'1 + connect \Y $eq$libresoc.v:34797$1395_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + cell $eq $eq$libresoc.v:34798$1396 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_5_0 [5] + connect \B 1'1 + connect \Y $eq$libresoc.v:34798$1396_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + cell $eq $eq$libresoc.v:34800$1398 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_1 [1] + connect \B 1'1 + connect \Y $eq$libresoc.v:34800$1398_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + cell $eq $eq$libresoc.v:34801$1399 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_7 [1] + connect \B 1'1 + connect \Y $eq$libresoc.v:34801$1399_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + cell $eq $eq$libresoc.v:34802$1400 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_6 [1] + connect \B 1'1 + connect \Y $eq$libresoc.v:34802$1400_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + cell $eq $eq$libresoc.v:34804$1402 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_9 [1] + connect \B 1'1 + connect \Y $eq$libresoc.v:34804$1402_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + cell $eq $eq$libresoc.v:34805$1403 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_8 [1] + connect \B 1'1 + connect \Y $eq$libresoc.v:34805$1403_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + cell $eq $eq$libresoc.v:34807$1405 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_11 [1] + connect \B 1'1 + connect \Y $eq$libresoc.v:34807$1405_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + cell $eq $eq$libresoc.v:34808$1406 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_10 [1] + connect \B 1'1 + connect \Y $eq$libresoc.v:34808$1406_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + cell $eq $eq$libresoc.v:34810$1408 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_13 [1] + connect \B 1'1 + connect \Y $eq$libresoc.v:34810$1408_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + cell $eq $eq$libresoc.v:34811$1409 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_0 [1] + connect \B 1'1 + connect \Y $eq$libresoc.v:34811$1409_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + cell $eq $eq$libresoc.v:34812$1410 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_12 [1] + connect \B 1'1 + connect \Y $eq$libresoc.v:34812$1410_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + cell $eq $eq$libresoc.v:34814$1412 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_15 [1] + connect \B 1'1 + connect \Y $eq$libresoc.v:34814$1412_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + cell $eq $eq$libresoc.v:34815$1413 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_14 [1] + connect \B 1'1 + connect \Y $eq$libresoc.v:34815$1413_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + cell $eq $eq$libresoc.v:34817$1415 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_17 [1] + connect \B 1'1 + connect \Y $eq$libresoc.v:34817$1415_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + cell $eq $eq$libresoc.v:34818$1416 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_16 [1] + connect \B 1'1 + connect \Y $eq$libresoc.v:34818$1416_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + cell $eq $eq$libresoc.v:34820$1418 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_19 [1] + connect \B 1'1 + connect \Y $eq$libresoc.v:34820$1418_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + cell $eq $eq$libresoc.v:34821$1419 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_18 [1] + connect \B 1'1 + connect \Y $eq$libresoc.v:34821$1419_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + cell $eq $eq$libresoc.v:34824$1422 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_21 [1] + connect \B 1'1 + connect \Y $eq$libresoc.v:34824$1422_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + cell $eq $eq$libresoc.v:34825$1423 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_20 [1] + connect \B 1'1 + connect \Y $eq$libresoc.v:34825$1423_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + cell $eq $eq$libresoc.v:34827$1425 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_23 [1] + connect \B 1'1 + connect \Y $eq$libresoc.v:34827$1425_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + cell $eq $eq$libresoc.v:34828$1426 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_22 [1] + connect \B 1'1 + connect \Y $eq$libresoc.v:34828$1426_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + cell $eq $eq$libresoc.v:34830$1428 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_25 [1] + connect \B 1'1 + connect \Y $eq$libresoc.v:34830$1428_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + cell $eq $eq$libresoc.v:34831$1429 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_24 [1] + connect \B 1'1 + connect \Y $eq$libresoc.v:34831$1429_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + cell $eq $eq$libresoc.v:34833$1431 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_3 [1] + connect \B 1'1 + connect \Y $eq$libresoc.v:34833$1431_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + cell $eq $eq$libresoc.v:34834$1432 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_27 [1] + connect \B 1'1 + connect \Y $eq$libresoc.v:34834$1432_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + cell $eq $eq$libresoc.v:34835$1433 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_26 [1] + connect \B 1'1 + connect \Y $eq$libresoc.v:34835$1433_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + cell $eq $eq$libresoc.v:34837$1435 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_29 [1] + connect \B 1'1 + connect \Y $eq$libresoc.v:34837$1435_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + cell $eq $eq$libresoc.v:34838$1436 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_28 [1] + connect \B 1'1 + connect \Y $eq$libresoc.v:34838$1436_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + cell $eq $eq$libresoc.v:34840$1438 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_31 [1] + connect \B 1'1 + connect \Y $eq$libresoc.v:34840$1438_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + cell $eq $eq$libresoc.v:34841$1439 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_30 [1] + connect \B 1'1 + connect \Y $eq$libresoc.v:34841$1439_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + cell $eq $eq$libresoc.v:34843$1441 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_2_2 [2] + connect \B 1'1 + connect \Y $eq$libresoc.v:34843$1441_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" + cell $pos $pos$libresoc.v:34753$1351 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A { 2'01 \cnt_2_0 [1:0] } + connect \Y $pos$libresoc.v:34753$1351_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" + cell $pos $pos$libresoc.v:34756$1354 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A { 2'01 \cnt_2_4 [1:0] } + connect \Y $pos$libresoc.v:34756$1354_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" + cell $pos $pos$libresoc.v:34759$1357 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A { 2'01 \cnt_2_8 [1:0] } + connect \Y $pos$libresoc.v:34759$1357_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" + cell $pos $pos$libresoc.v:34762$1360 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'01 \cnt_1_2 [0] } + connect \Y $pos$libresoc.v:34762$1360_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" + cell $pos $pos$libresoc.v:34763$1361 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A { 2'01 \cnt_2_12 [1:0] } + connect \Y $pos$libresoc.v:34763$1361_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" + cell $pos $pos$libresoc.v:34766$1364 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A { 2'01 \cnt_2_16 [1:0] } + connect \Y $pos$libresoc.v:34766$1364_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" + cell $pos $pos$libresoc.v:34769$1367 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A { 2'01 \cnt_2_20 [1:0] } + connect \Y $pos$libresoc.v:34769$1367_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" + cell $pos $pos$libresoc.v:34772$1370 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A { 2'01 \cnt_2_24 [1:0] } + connect \Y $pos$libresoc.v:34772$1370_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" + cell $pos $pos$libresoc.v:34776$1374 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A { 2'01 \cnt_2_28 [1:0] } + connect \Y $pos$libresoc.v:34776$1374_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" + cell $pos $pos$libresoc.v:34779$1377 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A { 2'01 \cnt_3_0 [2:0] } + connect \Y $pos$libresoc.v:34779$1377_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" + cell $pos $pos$libresoc.v:34782$1380 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A { 2'01 \cnt_3_4 [2:0] } + connect \Y $pos$libresoc.v:34782$1380_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" + cell $pos $pos$libresoc.v:34786$1384 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A { 2'01 \cnt_3_8 [2:0] } + connect \Y $pos$libresoc.v:34786$1384_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" + cell $pos $pos$libresoc.v:34789$1387 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A { 2'01 \cnt_3_12 [2:0] } + connect \Y $pos$libresoc.v:34789$1387_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" + cell $pos $pos$libresoc.v:34792$1390 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A { 2'01 \cnt_4_0 [3:0] } + connect \Y $pos$libresoc.v:34792$1390_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" + cell $pos $pos$libresoc.v:34795$1393 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'01 \cnt_1_4 [0] } + connect \Y $pos$libresoc.v:34795$1393_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" + cell $pos $pos$libresoc.v:34796$1394 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A { 2'01 \cnt_4_4 [3:0] } + connect \Y $pos$libresoc.v:34796$1394_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" + cell $pos $pos$libresoc.v:34799$1397 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 7 + connect \A { 2'01 \cnt_5_0 [4:0] } + connect \Y $pos$libresoc.v:34799$1397_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" + cell $pos $pos$libresoc.v:34803$1401 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'01 \cnt_1_6 [0] } + connect \Y $pos$libresoc.v:34803$1401_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" + cell $pos $pos$libresoc.v:34806$1404 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'01 \cnt_1_8 [0] } + connect \Y $pos$libresoc.v:34806$1404_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" + cell $pos $pos$libresoc.v:34809$1407 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'01 \cnt_1_10 [0] } + connect \Y $pos$libresoc.v:34809$1407_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" + cell $pos $pos$libresoc.v:34813$1411 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'01 \cnt_1_12 [0] } + connect \Y $pos$libresoc.v:34813$1411_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" + cell $pos $pos$libresoc.v:34816$1414 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'01 \cnt_1_14 [0] } + connect \Y $pos$libresoc.v:34816$1414_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" + cell $pos $pos$libresoc.v:34819$1417 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'01 \cnt_1_16 [0] } + connect \Y $pos$libresoc.v:34819$1417_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" + cell $pos $pos$libresoc.v:34822$1420 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'01 \cnt_1_0 [0] } + connect \Y $pos$libresoc.v:34822$1420_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" + cell $pos $pos$libresoc.v:34823$1421 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'01 \cnt_1_18 [0] } + connect \Y $pos$libresoc.v:34823$1421_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" + cell $pos $pos$libresoc.v:34826$1424 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'01 \cnt_1_20 [0] } + connect \Y $pos$libresoc.v:34826$1424_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" + cell $pos $pos$libresoc.v:34829$1427 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'01 \cnt_1_22 [0] } + connect \Y $pos$libresoc.v:34829$1427_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" + cell $pos $pos$libresoc.v:34832$1430 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'01 \cnt_1_24 [0] } + connect \Y $pos$libresoc.v:34832$1430_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" + cell $pos $pos$libresoc.v:34836$1434 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'01 \cnt_1_26 [0] } + connect \Y $pos$libresoc.v:34836$1434_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" + cell $pos $pos$libresoc.v:34839$1437 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'01 \cnt_1_28 [0] } + connect \Y $pos$libresoc.v:34839$1437_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" + cell $pos $pos$libresoc.v:34842$1440 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'01 \cnt_1_30 [0] } + connect \Y $pos$libresoc.v:34842$1440_Y + end + attribute \src "libresoc.v:34370.7-34370.20" + process $proc$libresoc.v:34370$1505 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:34844.3-34858.6" + process $proc$libresoc.v:34844$1442 + assign { } { } + assign $0\cnt_1_0[1:0] $1\cnt_1_0[1:0] + attribute \src "libresoc.v:34845.5-34845.29" + switch \initial + attribute \src "libresoc.v:34845.9-34845.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" + switch \pair0 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_0[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_0[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_0[1:0] 2'00 + end + sync always + update \cnt_1_0 $0\cnt_1_0[1:0] + end + attribute \src "libresoc.v:34859.3-34873.6" + process $proc$libresoc.v:34859$1443 + assign { } { } + assign $0\cnt_1_5[1:0] $1\cnt_1_5[1:0] + attribute \src "libresoc.v:34860.5-34860.29" + switch \initial + attribute \src "libresoc.v:34860.9-34860.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" + switch \pair10 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_5[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_5[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_5[1:0] 2'00 + end + sync always + update \cnt_1_5 $0\cnt_1_5[1:0] + end + attribute \src "libresoc.v:34874.3-34888.6" + process $proc$libresoc.v:34874$1444 + assign { } { } + assign $0\cnt_1_6[1:0] $1\cnt_1_6[1:0] + attribute \src "libresoc.v:34875.5-34875.29" + switch \initial + attribute \src "libresoc.v:34875.9-34875.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" + switch \pair12 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_6[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_6[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_6[1:0] 2'00 + end + sync always + update \cnt_1_6 $0\cnt_1_6[1:0] + end + attribute \src "libresoc.v:34889.3-34903.6" + process $proc$libresoc.v:34889$1445 + assign { } { } + assign $0\cnt_1_7[1:0] $1\cnt_1_7[1:0] + attribute \src "libresoc.v:34890.5-34890.29" + switch \initial + attribute \src "libresoc.v:34890.9-34890.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" + switch \pair14 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_7[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_7[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_7[1:0] 2'00 + end + sync always + update \cnt_1_7 $0\cnt_1_7[1:0] + end + attribute \src "libresoc.v:34904.3-34918.6" + process $proc$libresoc.v:34904$1446 + assign { } { } + assign $0\cnt_1_8[1:0] $1\cnt_1_8[1:0] + attribute \src "libresoc.v:34905.5-34905.29" + switch \initial + attribute \src "libresoc.v:34905.9-34905.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" + switch \pair16 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_8[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_8[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_8[1:0] 2'00 + end + sync always + update \cnt_1_8 $0\cnt_1_8[1:0] + end + attribute \src "libresoc.v:34919.3-34933.6" + process $proc$libresoc.v:34919$1447 + assign { } { } + assign $0\cnt_1_9[1:0] $1\cnt_1_9[1:0] + attribute \src "libresoc.v:34920.5-34920.29" + switch \initial + attribute \src "libresoc.v:34920.9-34920.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" + switch \pair18 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_9[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_9[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_9[1:0] 2'00 + end + sync always + update \cnt_1_9 $0\cnt_1_9[1:0] + end + attribute \src "libresoc.v:34934.3-34948.6" + process $proc$libresoc.v:34934$1448 + assign { } { } + assign $0\cnt_1_10[1:0] $1\cnt_1_10[1:0] + attribute \src "libresoc.v:34935.5-34935.29" + switch \initial + attribute \src "libresoc.v:34935.9-34935.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" + switch \pair20 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_10[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_10[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_10[1:0] 2'00 + end + sync always + update \cnt_1_10 $0\cnt_1_10[1:0] + end + attribute \src "libresoc.v:34949.3-34963.6" + process $proc$libresoc.v:34949$1449 + assign { } { } + assign $0\cnt_1_11[1:0] $1\cnt_1_11[1:0] + attribute \src "libresoc.v:34950.5-34950.29" + switch \initial + attribute \src "libresoc.v:34950.9-34950.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" + switch \pair22 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_11[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_11[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_11[1:0] 2'00 + end + sync always + update \cnt_1_11 $0\cnt_1_11[1:0] + end + attribute \src "libresoc.v:34964.3-34978.6" + process $proc$libresoc.v:34964$1450 + assign { } { } + assign $0\cnt_1_12[1:0] $1\cnt_1_12[1:0] + attribute \src "libresoc.v:34965.5-34965.29" + switch \initial + attribute \src "libresoc.v:34965.9-34965.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" + switch \pair24 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_12[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_12[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_12[1:0] 2'00 + end + sync always + update \cnt_1_12 $0\cnt_1_12[1:0] + end + attribute \src "libresoc.v:34979.3-34993.6" + process $proc$libresoc.v:34979$1451 + assign { } { } + assign $0\cnt_1_13[1:0] $1\cnt_1_13[1:0] + attribute \src "libresoc.v:34980.5-34980.29" + switch \initial + attribute \src "libresoc.v:34980.9-34980.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" + switch \pair26 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_13[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_13[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_13[1:0] 2'00 + end + sync always + update \cnt_1_13 $0\cnt_1_13[1:0] + end + attribute \src "libresoc.v:34994.3-35008.6" + process $proc$libresoc.v:34994$1452 + assign { } { } + assign $0\cnt_1_14[1:0] $1\cnt_1_14[1:0] + attribute \src "libresoc.v:34995.5-34995.29" + switch \initial + attribute \src "libresoc.v:34995.9-34995.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" + switch \pair28 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_14[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_14[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_14[1:0] 2'00 + end + sync always + update \cnt_1_14 $0\cnt_1_14[1:0] + end + attribute \src "libresoc.v:35009.3-35023.6" + process $proc$libresoc.v:35009$1453 + assign { } { } + assign $0\cnt_1_1[1:0] $1\cnt_1_1[1:0] + attribute \src "libresoc.v:35010.5-35010.29" + switch \initial + attribute \src "libresoc.v:35010.9-35010.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" + switch \pair2 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_1[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_1[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_1[1:0] 2'00 + end + sync always + update \cnt_1_1 $0\cnt_1_1[1:0] + end + attribute \src "libresoc.v:35024.3-35038.6" + process $proc$libresoc.v:35024$1454 + assign { } { } + assign $0\cnt_1_15[1:0] $1\cnt_1_15[1:0] + attribute \src "libresoc.v:35025.5-35025.29" + switch \initial + attribute \src "libresoc.v:35025.9-35025.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" + switch \pair30 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_15[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_15[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_15[1:0] 2'00 + end + sync always + update \cnt_1_15 $0\cnt_1_15[1:0] + end + attribute \src "libresoc.v:35039.3-35053.6" + process $proc$libresoc.v:35039$1455 + assign { } { } + assign $0\cnt_1_16[1:0] $1\cnt_1_16[1:0] + attribute \src "libresoc.v:35040.5-35040.29" + switch \initial + attribute \src "libresoc.v:35040.9-35040.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" + switch \pair32 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_16[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_16[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_16[1:0] 2'00 + end + sync always + update \cnt_1_16 $0\cnt_1_16[1:0] + end + attribute \src "libresoc.v:35054.3-35068.6" + process $proc$libresoc.v:35054$1456 + assign { } { } + assign $0\cnt_1_17[1:0] $1\cnt_1_17[1:0] + attribute \src "libresoc.v:35055.5-35055.29" + switch \initial + attribute \src "libresoc.v:35055.9-35055.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" + switch \pair34 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_17[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_17[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_17[1:0] 2'00 + end + sync always + update \cnt_1_17 $0\cnt_1_17[1:0] + end + attribute \src "libresoc.v:35069.3-35083.6" + process $proc$libresoc.v:35069$1457 + assign { } { } + assign $0\cnt_1_18[1:0] $1\cnt_1_18[1:0] + attribute \src "libresoc.v:35070.5-35070.29" + switch \initial + attribute \src "libresoc.v:35070.9-35070.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" + switch \pair36 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_18[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_18[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_18[1:0] 2'00 + end + sync always + update \cnt_1_18 $0\cnt_1_18[1:0] + end + attribute \src "libresoc.v:35084.3-35098.6" + process $proc$libresoc.v:35084$1458 + assign { } { } + assign $0\cnt_1_19[1:0] $1\cnt_1_19[1:0] + attribute \src "libresoc.v:35085.5-35085.29" + switch \initial + attribute \src "libresoc.v:35085.9-35085.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" + switch \pair38 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_19[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_19[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_19[1:0] 2'00 + end + sync always + update \cnt_1_19 $0\cnt_1_19[1:0] + end + attribute \src "libresoc.v:35099.3-35113.6" + process $proc$libresoc.v:35099$1459 + assign { } { } + assign $0\cnt_1_20[1:0] $1\cnt_1_20[1:0] + attribute \src "libresoc.v:35100.5-35100.29" + switch \initial + attribute \src "libresoc.v:35100.9-35100.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" + switch \pair40 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_20[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_20[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_20[1:0] 2'00 + end + sync always + update \cnt_1_20 $0\cnt_1_20[1:0] + end + attribute \src "libresoc.v:35114.3-35128.6" + process $proc$libresoc.v:35114$1460 + assign { } { } + assign $0\cnt_1_21[1:0] $1\cnt_1_21[1:0] + attribute \src "libresoc.v:35115.5-35115.29" + switch \initial + attribute \src "libresoc.v:35115.9-35115.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" + switch \pair42 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_21[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_21[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_21[1:0] 2'00 + end + sync always + update \cnt_1_21 $0\cnt_1_21[1:0] + end + attribute \src "libresoc.v:35129.3-35143.6" + process $proc$libresoc.v:35129$1461 + assign { } { } + assign $0\cnt_1_22[1:0] $1\cnt_1_22[1:0] + attribute \src "libresoc.v:35130.5-35130.29" + switch \initial + attribute \src "libresoc.v:35130.9-35130.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" + switch \pair44 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_22[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_22[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_22[1:0] 2'00 + end + sync always + update \cnt_1_22 $0\cnt_1_22[1:0] + end + attribute \src "libresoc.v:35144.3-35158.6" + process $proc$libresoc.v:35144$1462 + assign { } { } + assign $0\cnt_1_23[1:0] $1\cnt_1_23[1:0] + attribute \src "libresoc.v:35145.5-35145.29" + switch \initial + attribute \src "libresoc.v:35145.9-35145.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" + switch \pair46 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_23[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_23[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_23[1:0] 2'00 + end + sync always + update \cnt_1_23 $0\cnt_1_23[1:0] + end + attribute \src "libresoc.v:35159.3-35173.6" + process $proc$libresoc.v:35159$1463 + assign { } { } + assign $0\cnt_1_24[1:0] $1\cnt_1_24[1:0] + attribute \src "libresoc.v:35160.5-35160.29" + switch \initial + attribute \src "libresoc.v:35160.9-35160.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" + switch \pair48 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_24[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_24[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_24[1:0] 2'00 + end + sync always + update \cnt_1_24 $0\cnt_1_24[1:0] + end + attribute \src "libresoc.v:35174.3-35188.6" + process $proc$libresoc.v:35174$1464 + assign { } { } + assign $0\cnt_1_2[1:0] $1\cnt_1_2[1:0] + attribute \src "libresoc.v:35175.5-35175.29" + switch \initial + attribute \src "libresoc.v:35175.9-35175.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" + switch \pair4 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_2[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_2[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_2[1:0] 2'00 + end + sync always + update \cnt_1_2 $0\cnt_1_2[1:0] + end + attribute \src "libresoc.v:35189.3-35203.6" + process $proc$libresoc.v:35189$1465 + assign { } { } + assign $0\cnt_1_25[1:0] $1\cnt_1_25[1:0] + attribute \src "libresoc.v:35190.5-35190.29" + switch \initial + attribute \src "libresoc.v:35190.9-35190.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" + switch \pair50 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_25[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_25[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_25[1:0] 2'00 + end + sync always + update \cnt_1_25 $0\cnt_1_25[1:0] + end + attribute \src "libresoc.v:35204.3-35218.6" + process $proc$libresoc.v:35204$1466 + assign { } { } + assign $0\cnt_1_26[1:0] $1\cnt_1_26[1:0] + attribute \src "libresoc.v:35205.5-35205.29" + switch \initial + attribute \src "libresoc.v:35205.9-35205.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" + switch \pair52 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_26[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_26[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_26[1:0] 2'00 + end + sync always + update \cnt_1_26 $0\cnt_1_26[1:0] + end + attribute \src "libresoc.v:35219.3-35233.6" + process $proc$libresoc.v:35219$1467 + assign { } { } + assign $0\cnt_1_27[1:0] $1\cnt_1_27[1:0] + attribute \src "libresoc.v:35220.5-35220.29" + switch \initial + attribute \src "libresoc.v:35220.9-35220.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" + switch \pair54 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_27[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_27[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_27[1:0] 2'00 + end + sync always + update \cnt_1_27 $0\cnt_1_27[1:0] + end + attribute \src "libresoc.v:35234.3-35248.6" + process $proc$libresoc.v:35234$1468 + assign { } { } + assign $0\cnt_1_28[1:0] $1\cnt_1_28[1:0] + attribute \src "libresoc.v:35235.5-35235.29" + switch \initial + attribute \src "libresoc.v:35235.9-35235.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" + switch \pair56 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_28[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_28[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_28[1:0] 2'00 + end + sync always + update \cnt_1_28 $0\cnt_1_28[1:0] + end + attribute \src "libresoc.v:35249.3-35263.6" + process $proc$libresoc.v:35249$1469 + assign { } { } + assign $0\cnt_1_29[1:0] $1\cnt_1_29[1:0] + attribute \src "libresoc.v:35250.5-35250.29" + switch \initial + attribute \src "libresoc.v:35250.9-35250.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" + switch \pair58 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_29[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_29[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_29[1:0] 2'00 + end + sync always + update \cnt_1_29 $0\cnt_1_29[1:0] + end + attribute \src "libresoc.v:35264.3-35278.6" + process $proc$libresoc.v:35264$1470 + assign { } { } + assign $0\cnt_1_30[1:0] $1\cnt_1_30[1:0] + attribute \src "libresoc.v:35265.5-35265.29" + switch \initial + attribute \src "libresoc.v:35265.9-35265.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" + switch \pair60 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_30[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_30[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_30[1:0] 2'00 + end + sync always + update \cnt_1_30 $0\cnt_1_30[1:0] + end + attribute \src "libresoc.v:35279.3-35293.6" + process $proc$libresoc.v:35279$1471 + assign { } { } + assign $0\cnt_1_31[1:0] $1\cnt_1_31[1:0] + attribute \src "libresoc.v:35280.5-35280.29" + switch \initial + attribute \src "libresoc.v:35280.9-35280.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" + switch \pair62 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_31[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_31[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_31[1:0] 2'00 + end + sync always + update \cnt_1_31 $0\cnt_1_31[1:0] + end + attribute \src "libresoc.v:35294.3-35313.6" + process $proc$libresoc.v:35294$1472 + assign { } { } + assign $0\cnt_2_0[2:0] $1\cnt_2_0[2:0] + attribute \src "libresoc.v:35295.5-35295.29" + switch \initial + attribute \src "libresoc.v:35295.9-35295.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + switch \$1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_2_0[2:0] $2\cnt_2_0[2:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_2_0[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_2_0[2:0] \$5 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_2_0[2:0] { 1'0 \cnt_1_1 } + end + sync always + update \cnt_2_0 $0\cnt_2_0[2:0] + end + attribute \src "libresoc.v:35314.3-35333.6" + process $proc$libresoc.v:35314$1473 + assign { } { } + assign $0\cnt_2_2[2:0] $1\cnt_2_2[2:0] + attribute \src "libresoc.v:35315.5-35315.29" + switch \initial + attribute \src "libresoc.v:35315.9-35315.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + switch \$7 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_2_2[2:0] $2\cnt_2_2[2:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + switch \$9 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_2_2[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_2_2[2:0] \$11 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_2_2[2:0] { 1'0 \cnt_1_3 } + end + sync always + update \cnt_2_2 $0\cnt_2_2[2:0] + end + attribute \src "libresoc.v:35334.3-35353.6" + process $proc$libresoc.v:35334$1474 + assign { } { } + assign $0\cnt_2_4[2:0] $1\cnt_2_4[2:0] + attribute \src "libresoc.v:35335.5-35335.29" + switch \initial + attribute \src "libresoc.v:35335.9-35335.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + switch \$13 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_2_4[2:0] $2\cnt_2_4[2:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + switch \$15 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_2_4[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_2_4[2:0] \$17 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_2_4[2:0] { 1'0 \cnt_1_5 } + end + sync always + update \cnt_2_4 $0\cnt_2_4[2:0] + end + attribute \src "libresoc.v:35354.3-35373.6" + process $proc$libresoc.v:35354$1475 + assign { } { } + assign $0\cnt_2_6[2:0] $1\cnt_2_6[2:0] + attribute \src "libresoc.v:35355.5-35355.29" + switch \initial + attribute \src "libresoc.v:35355.9-35355.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + switch \$19 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_2_6[2:0] $2\cnt_2_6[2:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + switch \$21 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_2_6[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_2_6[2:0] \$23 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_2_6[2:0] { 1'0 \cnt_1_7 } + end + sync always + update \cnt_2_6 $0\cnt_2_6[2:0] + end + attribute \src "libresoc.v:35374.3-35393.6" + process $proc$libresoc.v:35374$1476 + assign { } { } + assign $0\cnt_2_8[2:0] $1\cnt_2_8[2:0] + attribute \src "libresoc.v:35375.5-35375.29" + switch \initial + attribute \src "libresoc.v:35375.9-35375.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + switch \$25 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_2_8[2:0] $2\cnt_2_8[2:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + switch \$27 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_2_8[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_2_8[2:0] \$29 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_2_8[2:0] { 1'0 \cnt_1_9 } + end + sync always + update \cnt_2_8 $0\cnt_2_8[2:0] + end + attribute \src "libresoc.v:35394.3-35413.6" + process $proc$libresoc.v:35394$1477 + assign { } { } + assign $0\cnt_2_10[2:0] $1\cnt_2_10[2:0] + attribute \src "libresoc.v:35395.5-35395.29" + switch \initial + attribute \src "libresoc.v:35395.9-35395.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + switch \$31 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_2_10[2:0] $2\cnt_2_10[2:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + switch \$33 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_2_10[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_2_10[2:0] \$35 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_2_10[2:0] { 1'0 \cnt_1_11 } + end + sync always + update \cnt_2_10 $0\cnt_2_10[2:0] + end + attribute \src "libresoc.v:35414.3-35428.6" + process $proc$libresoc.v:35414$1478 + assign { } { } + assign $0\cnt_1_3[1:0] $1\cnt_1_3[1:0] + attribute \src "libresoc.v:35415.5-35415.29" + switch \initial + attribute \src "libresoc.v:35415.9-35415.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" + switch \pair6 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_3[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_3[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_3[1:0] 2'00 + end + sync always + update \cnt_1_3 $0\cnt_1_3[1:0] + end + attribute \src "libresoc.v:35429.3-35448.6" + process $proc$libresoc.v:35429$1479 + assign { } { } + assign $0\cnt_2_12[2:0] $1\cnt_2_12[2:0] + attribute \src "libresoc.v:35430.5-35430.29" + switch \initial + attribute \src "libresoc.v:35430.9-35430.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + switch \$37 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_2_12[2:0] $2\cnt_2_12[2:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + switch \$39 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_2_12[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_2_12[2:0] \$41 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_2_12[2:0] { 1'0 \cnt_1_13 } + end + sync always + update \cnt_2_12 $0\cnt_2_12[2:0] + end + attribute \src "libresoc.v:35449.3-35468.6" + process $proc$libresoc.v:35449$1480 + assign { } { } + assign $0\cnt_2_14[2:0] $1\cnt_2_14[2:0] + attribute \src "libresoc.v:35450.5-35450.29" + switch \initial + attribute \src "libresoc.v:35450.9-35450.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + switch \$43 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_2_14[2:0] $2\cnt_2_14[2:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + switch \$45 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_2_14[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_2_14[2:0] \$47 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_2_14[2:0] { 1'0 \cnt_1_15 } + end + sync always + update \cnt_2_14 $0\cnt_2_14[2:0] + end + attribute \src "libresoc.v:35469.3-35488.6" + process $proc$libresoc.v:35469$1481 + assign { } { } + assign $0\cnt_2_16[2:0] $1\cnt_2_16[2:0] + attribute \src "libresoc.v:35470.5-35470.29" + switch \initial + attribute \src "libresoc.v:35470.9-35470.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + switch \$49 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_2_16[2:0] $2\cnt_2_16[2:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + switch \$51 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_2_16[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_2_16[2:0] \$53 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_2_16[2:0] { 1'0 \cnt_1_17 } + end + sync always + update \cnt_2_16 $0\cnt_2_16[2:0] + end + attribute \src "libresoc.v:35489.3-35508.6" + process $proc$libresoc.v:35489$1482 + assign { } { } + assign $0\cnt_2_18[2:0] $1\cnt_2_18[2:0] + attribute \src "libresoc.v:35490.5-35490.29" + switch \initial + attribute \src "libresoc.v:35490.9-35490.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + switch \$55 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_2_18[2:0] $2\cnt_2_18[2:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + switch \$57 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_2_18[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_2_18[2:0] \$59 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_2_18[2:0] { 1'0 \cnt_1_19 } + end + sync always + update \cnt_2_18 $0\cnt_2_18[2:0] + end + attribute \src "libresoc.v:35509.3-35528.6" + process $proc$libresoc.v:35509$1483 + assign { } { } + assign $0\cnt_2_20[2:0] $1\cnt_2_20[2:0] + attribute \src "libresoc.v:35510.5-35510.29" + switch \initial + attribute \src "libresoc.v:35510.9-35510.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + switch \$61 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_2_20[2:0] $2\cnt_2_20[2:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + switch \$63 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_2_20[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_2_20[2:0] \$65 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_2_20[2:0] { 1'0 \cnt_1_21 } + end + sync always + update \cnt_2_20 $0\cnt_2_20[2:0] + end + attribute \src "libresoc.v:35529.3-35548.6" + process $proc$libresoc.v:35529$1484 + assign { } { } + assign $0\cnt_2_22[2:0] $1\cnt_2_22[2:0] + attribute \src "libresoc.v:35530.5-35530.29" + switch \initial + attribute \src "libresoc.v:35530.9-35530.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + switch \$67 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_2_22[2:0] $2\cnt_2_22[2:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + switch \$69 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_2_22[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_2_22[2:0] \$71 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_2_22[2:0] { 1'0 \cnt_1_23 } + end + sync always + update \cnt_2_22 $0\cnt_2_22[2:0] + end + attribute \src "libresoc.v:35549.3-35568.6" + process $proc$libresoc.v:35549$1485 + assign { } { } + assign $0\cnt_2_24[2:0] $1\cnt_2_24[2:0] + attribute \src "libresoc.v:35550.5-35550.29" + switch \initial + attribute \src "libresoc.v:35550.9-35550.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + switch \$73 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_2_24[2:0] $2\cnt_2_24[2:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + switch \$75 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_2_24[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_2_24[2:0] \$77 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_2_24[2:0] { 1'0 \cnt_1_25 } + end + sync always + update \cnt_2_24 $0\cnt_2_24[2:0] + end + attribute \src "libresoc.v:35569.3-35588.6" + process $proc$libresoc.v:35569$1486 + assign { } { } + assign $0\cnt_2_26[2:0] $1\cnt_2_26[2:0] + attribute \src "libresoc.v:35570.5-35570.29" + switch \initial + attribute \src "libresoc.v:35570.9-35570.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + switch \$79 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_2_26[2:0] $2\cnt_2_26[2:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + switch \$81 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_2_26[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_2_26[2:0] \$83 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_2_26[2:0] { 1'0 \cnt_1_27 } + end + sync always + update \cnt_2_26 $0\cnt_2_26[2:0] + end + attribute \src "libresoc.v:35589.3-35608.6" + process $proc$libresoc.v:35589$1487 + assign { } { } + assign $0\cnt_2_28[2:0] $1\cnt_2_28[2:0] + attribute \src "libresoc.v:35590.5-35590.29" + switch \initial + attribute \src "libresoc.v:35590.9-35590.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + switch \$85 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_2_28[2:0] $2\cnt_2_28[2:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + switch \$87 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_2_28[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_2_28[2:0] \$89 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_2_28[2:0] { 1'0 \cnt_1_29 } + end + sync always + update \cnt_2_28 $0\cnt_2_28[2:0] + end + attribute \src "libresoc.v:35609.3-35628.6" + process $proc$libresoc.v:35609$1488 + assign { } { } + assign $0\cnt_2_30[2:0] $1\cnt_2_30[2:0] + attribute \src "libresoc.v:35610.5-35610.29" + switch \initial + attribute \src "libresoc.v:35610.9-35610.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + switch \$91 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_2_30[2:0] $2\cnt_2_30[2:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + switch \$93 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_2_30[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_2_30[2:0] \$95 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_2_30[2:0] { 1'0 \cnt_1_31 } + end + sync always + update \cnt_2_30 $0\cnt_2_30[2:0] + end + attribute \src "libresoc.v:35629.3-35648.6" + process $proc$libresoc.v:35629$1489 + assign { } { } + assign $0\cnt_3_0[3:0] $1\cnt_3_0[3:0] + attribute \src "libresoc.v:35630.5-35630.29" + switch \initial + attribute \src "libresoc.v:35630.9-35630.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + switch \$97 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_3_0[3:0] $2\cnt_3_0[3:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + switch \$99 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_3_0[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_3_0[3:0] \$101 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_3_0[3:0] { 1'0 \cnt_2_2 } + end + sync always + update \cnt_3_0 $0\cnt_3_0[3:0] + end + attribute \src "libresoc.v:35649.3-35668.6" + process $proc$libresoc.v:35649$1490 + assign { } { } + assign $0\cnt_3_2[3:0] $1\cnt_3_2[3:0] + attribute \src "libresoc.v:35650.5-35650.29" + switch \initial + attribute \src "libresoc.v:35650.9-35650.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + switch \$103 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_3_2[3:0] $2\cnt_3_2[3:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + switch \$105 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_3_2[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_3_2[3:0] \$107 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_3_2[3:0] { 1'0 \cnt_2_6 } + end + sync always + update \cnt_3_2 $0\cnt_3_2[3:0] + end + attribute \src "libresoc.v:35669.3-35688.6" + process $proc$libresoc.v:35669$1491 + assign { } { } + assign $0\cnt_3_4[3:0] $1\cnt_3_4[3:0] + attribute \src "libresoc.v:35670.5-35670.29" + switch \initial + attribute \src "libresoc.v:35670.9-35670.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + switch \$109 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_3_4[3:0] $2\cnt_3_4[3:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + switch \$111 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_3_4[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_3_4[3:0] \$113 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_3_4[3:0] { 1'0 \cnt_2_10 } + end + sync always + update \cnt_3_4 $0\cnt_3_4[3:0] + end + attribute \src "libresoc.v:35689.3-35708.6" + process $proc$libresoc.v:35689$1492 + assign { } { } + assign $0\cnt_3_6[3:0] $1\cnt_3_6[3:0] + attribute \src "libresoc.v:35690.5-35690.29" + switch \initial + attribute \src "libresoc.v:35690.9-35690.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + switch \$115 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_3_6[3:0] $2\cnt_3_6[3:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + switch \$117 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_3_6[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_3_6[3:0] \$119 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_3_6[3:0] { 1'0 \cnt_2_14 } + end + sync always + update \cnt_3_6 $0\cnt_3_6[3:0] + end + attribute \src "libresoc.v:35709.3-35728.6" + process $proc$libresoc.v:35709$1493 + assign { } { } + assign $0\cnt_3_8[3:0] $1\cnt_3_8[3:0] + attribute \src "libresoc.v:35710.5-35710.29" + switch \initial + attribute \src "libresoc.v:35710.9-35710.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + switch \$121 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_3_8[3:0] $2\cnt_3_8[3:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + switch \$123 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_3_8[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_3_8[3:0] \$125 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_3_8[3:0] { 1'0 \cnt_2_18 } + end + sync always + update \cnt_3_8 $0\cnt_3_8[3:0] + end + attribute \src "libresoc.v:35729.3-35748.6" + process $proc$libresoc.v:35729$1494 + assign { } { } + assign $0\cnt_3_10[3:0] $1\cnt_3_10[3:0] + attribute \src "libresoc.v:35730.5-35730.29" + switch \initial + attribute \src "libresoc.v:35730.9-35730.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + switch \$127 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_3_10[3:0] $2\cnt_3_10[3:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + switch \$129 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_3_10[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_3_10[3:0] \$131 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_3_10[3:0] { 1'0 \cnt_2_22 } + end + sync always + update \cnt_3_10 $0\cnt_3_10[3:0] + end + attribute \src "libresoc.v:35749.3-35768.6" + process $proc$libresoc.v:35749$1495 + assign { } { } + assign $0\cnt_3_12[3:0] $1\cnt_3_12[3:0] + attribute \src "libresoc.v:35750.5-35750.29" + switch \initial + attribute \src "libresoc.v:35750.9-35750.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + switch \$133 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_3_12[3:0] $2\cnt_3_12[3:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + switch \$135 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_3_12[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_3_12[3:0] \$137 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_3_12[3:0] { 1'0 \cnt_2_26 } + end + sync always + update \cnt_3_12 $0\cnt_3_12[3:0] + end + attribute \src "libresoc.v:35769.3-35788.6" + process $proc$libresoc.v:35769$1496 + assign { } { } + assign $0\cnt_3_14[3:0] $1\cnt_3_14[3:0] + attribute \src "libresoc.v:35770.5-35770.29" + switch \initial + attribute \src "libresoc.v:35770.9-35770.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + switch \$139 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_3_14[3:0] $2\cnt_3_14[3:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + switch \$141 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_3_14[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_3_14[3:0] \$143 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_3_14[3:0] { 1'0 \cnt_2_30 } + end + sync always + update \cnt_3_14 $0\cnt_3_14[3:0] + end + attribute \src "libresoc.v:35789.3-35808.6" + process $proc$libresoc.v:35789$1497 + assign { } { } + assign $0\cnt_4_0[4:0] $1\cnt_4_0[4:0] + attribute \src "libresoc.v:35790.5-35790.29" + switch \initial + attribute \src "libresoc.v:35790.9-35790.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + switch \$145 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_4_0[4:0] $2\cnt_4_0[4:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + switch \$147 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_4_0[4:0] 5'10000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_4_0[4:0] \$149 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_4_0[4:0] { 1'0 \cnt_3_2 } + end + sync always + update \cnt_4_0 $0\cnt_4_0[4:0] + end + attribute \src "libresoc.v:35809.3-35828.6" + process $proc$libresoc.v:35809$1498 + assign { } { } + assign $0\cnt_4_2[4:0] $1\cnt_4_2[4:0] + attribute \src "libresoc.v:35810.5-35810.29" + switch \initial + attribute \src "libresoc.v:35810.9-35810.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + switch \$151 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_4_2[4:0] $2\cnt_4_2[4:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + switch \$153 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_4_2[4:0] 5'10000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_4_2[4:0] \$155 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_4_2[4:0] { 1'0 \cnt_3_6 } + end + sync always + update \cnt_4_2 $0\cnt_4_2[4:0] + end + attribute \src "libresoc.v:35829.3-35843.6" + process $proc$libresoc.v:35829$1499 + assign { } { } + assign $0\cnt_1_4[1:0] $1\cnt_1_4[1:0] + attribute \src "libresoc.v:35830.5-35830.29" + switch \initial + attribute \src "libresoc.v:35830.9-35830.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" + switch \pair8 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_4[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_4[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_4[1:0] 2'00 + end + sync always + update \cnt_1_4 $0\cnt_1_4[1:0] + end + attribute \src "libresoc.v:35844.3-35863.6" + process $proc$libresoc.v:35844$1500 + assign { } { } + assign $0\cnt_4_4[4:0] $1\cnt_4_4[4:0] + attribute \src "libresoc.v:35845.5-35845.29" + switch \initial + attribute \src "libresoc.v:35845.9-35845.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + switch \$157 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_4_4[4:0] $2\cnt_4_4[4:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + switch \$159 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_4_4[4:0] 5'10000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_4_4[4:0] \$161 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_4_4[4:0] { 1'0 \cnt_3_10 } + end + sync always + update \cnt_4_4 $0\cnt_4_4[4:0] + end + attribute \src "libresoc.v:35864.3-35883.6" + process $proc$libresoc.v:35864$1501 + assign { } { } + assign $0\cnt_4_6[4:0] $1\cnt_4_6[4:0] + attribute \src "libresoc.v:35865.5-35865.29" + switch \initial + attribute \src "libresoc.v:35865.9-35865.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + switch \$163 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_4_6[4:0] $2\cnt_4_6[4:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + switch \$165 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_4_6[4:0] 5'10000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_4_6[4:0] \$167 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_4_6[4:0] { 1'0 \cnt_3_14 } + end + sync always + update \cnt_4_6 $0\cnt_4_6[4:0] + end + attribute \src "libresoc.v:35884.3-35903.6" + process $proc$libresoc.v:35884$1502 + assign { } { } + assign $0\cnt_5_0[5:0] $1\cnt_5_0[5:0] + attribute \src "libresoc.v:35885.5-35885.29" + switch \initial + attribute \src "libresoc.v:35885.9-35885.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + switch \$169 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_5_0[5:0] $2\cnt_5_0[5:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + switch \$171 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_5_0[5:0] 6'100000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_5_0[5:0] \$173 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_5_0[5:0] { 1'0 \cnt_4_2 } + end + sync always + update \cnt_5_0 $0\cnt_5_0[5:0] + end + attribute \src "libresoc.v:35904.3-35923.6" + process $proc$libresoc.v:35904$1503 + assign { } { } + assign $0\cnt_5_2[5:0] $1\cnt_5_2[5:0] + attribute \src "libresoc.v:35905.5-35905.29" + switch \initial + attribute \src "libresoc.v:35905.9-35905.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + switch \$175 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_5_2[5:0] $2\cnt_5_2[5:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + switch \$177 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_5_2[5:0] 6'100000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_5_2[5:0] \$179 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_5_2[5:0] { 1'0 \cnt_4_6 } + end + sync always + update \cnt_5_2 $0\cnt_5_2[5:0] + end + attribute \src "libresoc.v:35924.3-35943.6" + process $proc$libresoc.v:35924$1504 + assign { } { } + assign $0\cnt_6_0[6:0] $1\cnt_6_0[6:0] + attribute \src "libresoc.v:35925.5-35925.29" + switch \initial + attribute \src "libresoc.v:35925.9-35925.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" + switch \$181 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_6_0[6:0] $2\cnt_6_0[6:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" + switch \$183 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_6_0[6:0] 7'1000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_6_0[6:0] \$185 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_6_0[6:0] { 1'0 \cnt_5_2 } + end + sync always + update \cnt_6_0 $0\cnt_6_0[6:0] + end + connect \$9 $eq$libresoc.v:34751$1349_Y + connect \$99 $eq$libresoc.v:34752$1350_Y + connect \$101 $pos$libresoc.v:34753$1351_Y + connect \$103 $eq$libresoc.v:34754$1352_Y + connect \$105 $eq$libresoc.v:34755$1353_Y + connect \$107 $pos$libresoc.v:34756$1354_Y + connect \$109 $eq$libresoc.v:34757$1355_Y + connect \$111 $eq$libresoc.v:34758$1356_Y + connect \$113 $pos$libresoc.v:34759$1357_Y + connect \$115 $eq$libresoc.v:34760$1358_Y + connect \$117 $eq$libresoc.v:34761$1359_Y + connect \$11 $pos$libresoc.v:34762$1360_Y + connect \$119 $pos$libresoc.v:34763$1361_Y + connect \$121 $eq$libresoc.v:34764$1362_Y + connect \$123 $eq$libresoc.v:34765$1363_Y + connect \$125 $pos$libresoc.v:34766$1364_Y + connect \$127 $eq$libresoc.v:34767$1365_Y + connect \$129 $eq$libresoc.v:34768$1366_Y + connect \$131 $pos$libresoc.v:34769$1367_Y + connect \$133 $eq$libresoc.v:34770$1368_Y + connect \$135 $eq$libresoc.v:34771$1369_Y + connect \$137 $pos$libresoc.v:34772$1370_Y + connect \$13 $eq$libresoc.v:34773$1371_Y + connect \$139 $eq$libresoc.v:34774$1372_Y + connect \$141 $eq$libresoc.v:34775$1373_Y + connect \$143 $pos$libresoc.v:34776$1374_Y + connect \$145 $eq$libresoc.v:34777$1375_Y + connect \$147 $eq$libresoc.v:34778$1376_Y + connect \$149 $pos$libresoc.v:34779$1377_Y + connect \$151 $eq$libresoc.v:34780$1378_Y + connect \$153 $eq$libresoc.v:34781$1379_Y + connect \$155 $pos$libresoc.v:34782$1380_Y + connect \$157 $eq$libresoc.v:34783$1381_Y + connect \$15 $eq$libresoc.v:34784$1382_Y + connect \$159 $eq$libresoc.v:34785$1383_Y + connect \$161 $pos$libresoc.v:34786$1384_Y + connect \$163 $eq$libresoc.v:34787$1385_Y + connect \$165 $eq$libresoc.v:34788$1386_Y + connect \$167 $pos$libresoc.v:34789$1387_Y + connect \$169 $eq$libresoc.v:34790$1388_Y + connect \$171 $eq$libresoc.v:34791$1389_Y + connect \$173 $pos$libresoc.v:34792$1390_Y + connect \$175 $eq$libresoc.v:34793$1391_Y + connect \$177 $eq$libresoc.v:34794$1392_Y + connect \$17 $pos$libresoc.v:34795$1393_Y + connect \$179 $pos$libresoc.v:34796$1394_Y + connect \$181 $eq$libresoc.v:34797$1395_Y + connect \$183 $eq$libresoc.v:34798$1396_Y + connect \$185 $pos$libresoc.v:34799$1397_Y + connect \$1 $eq$libresoc.v:34800$1398_Y + connect \$19 $eq$libresoc.v:34801$1399_Y + connect \$21 $eq$libresoc.v:34802$1400_Y + connect \$23 $pos$libresoc.v:34803$1401_Y + connect \$25 $eq$libresoc.v:34804$1402_Y + connect \$27 $eq$libresoc.v:34805$1403_Y + connect \$29 $pos$libresoc.v:34806$1404_Y + connect \$31 $eq$libresoc.v:34807$1405_Y + connect \$33 $eq$libresoc.v:34808$1406_Y + connect \$35 $pos$libresoc.v:34809$1407_Y + connect \$37 $eq$libresoc.v:34810$1408_Y + connect \$3 $eq$libresoc.v:34811$1409_Y + connect \$39 $eq$libresoc.v:34812$1410_Y + connect \$41 $pos$libresoc.v:34813$1411_Y + connect \$43 $eq$libresoc.v:34814$1412_Y + connect \$45 $eq$libresoc.v:34815$1413_Y + connect \$47 $pos$libresoc.v:34816$1414_Y + connect \$49 $eq$libresoc.v:34817$1415_Y + connect \$51 $eq$libresoc.v:34818$1416_Y + connect \$53 $pos$libresoc.v:34819$1417_Y + connect \$55 $eq$libresoc.v:34820$1418_Y + connect \$57 $eq$libresoc.v:34821$1419_Y + connect \$5 $pos$libresoc.v:34822$1420_Y + connect \$59 $pos$libresoc.v:34823$1421_Y + connect \$61 $eq$libresoc.v:34824$1422_Y + connect \$63 $eq$libresoc.v:34825$1423_Y + connect \$65 $pos$libresoc.v:34826$1424_Y + connect \$67 $eq$libresoc.v:34827$1425_Y + connect \$69 $eq$libresoc.v:34828$1426_Y + connect \$71 $pos$libresoc.v:34829$1427_Y + connect \$73 $eq$libresoc.v:34830$1428_Y + connect \$75 $eq$libresoc.v:34831$1429_Y + connect \$77 $pos$libresoc.v:34832$1430_Y + connect \$7 $eq$libresoc.v:34833$1431_Y + connect \$79 $eq$libresoc.v:34834$1432_Y + connect \$81 $eq$libresoc.v:34835$1433_Y + connect \$83 $pos$libresoc.v:34836$1434_Y + connect \$85 $eq$libresoc.v:34837$1435_Y + connect \$87 $eq$libresoc.v:34838$1436_Y + connect \$89 $pos$libresoc.v:34839$1437_Y + connect \$91 $eq$libresoc.v:34840$1438_Y + connect \$93 $eq$libresoc.v:34841$1439_Y + connect \$95 $pos$libresoc.v:34842$1440_Y + connect \$97 $eq$libresoc.v:34843$1441_Y + connect \lz \cnt_6_0 + connect \pair62 \sig_in [63:62] + connect \pair60 \sig_in [61:60] + connect \pair58 \sig_in [59:58] + connect \pair56 \sig_in [57:56] + connect \pair54 \sig_in [55:54] + connect \pair52 \sig_in [53:52] + connect \pair50 \sig_in [51:50] + connect \pair48 \sig_in [49:48] + connect \pair46 \sig_in [47:46] + connect \pair44 \sig_in [45:44] + connect \pair42 \sig_in [43:42] + connect \pair40 \sig_in [41:40] + connect \pair38 \sig_in [39:38] + connect \pair36 \sig_in [37:36] + connect \pair34 \sig_in [35:34] + connect \pair32 \sig_in [33:32] + connect \pair30 \sig_in [31:30] + connect \pair28 \sig_in [29:28] + connect \pair26 \sig_in [27:26] + connect \pair24 \sig_in [25:24] + connect \pair22 \sig_in [23:22] + connect \pair20 \sig_in [21:20] + connect \pair18 \sig_in [19:18] + connect \pair16 \sig_in [17:16] + connect \pair14 \sig_in [15:14] + connect \pair12 \sig_in [13:12] + connect \pair10 \sig_in [11:10] + connect \pair8 \sig_in [9:8] + connect \pair6 \sig_in [7:6] + connect \pair4 \sig_in [5:4] + connect \pair2 \sig_in [3:2] + connect \pair0 \sig_in [1:0] +end +attribute \src "libresoc.v:35981.1-48834.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core" +attribute \generator "nMigen" +module \core + attribute \src "libresoc.v:45800.3-45820.6" + wire $0\core_terminate_o$next[0:0]$2588 + attribute \src "libresoc.v:42688.3-42689.49" + wire $0\core_terminate_o[0:0] + attribute \src "libresoc.v:45671.3-45761.6" + wire $0\corebusy_o[0:0] + attribute \src "libresoc.v:45625.3-45651.6" + wire width 2 $0\counter$next[1:0]$2565 + attribute \src "libresoc.v:42690.3-42691.31" + wire width 2 $0\counter[1:0] + attribute \src "libresoc.v:46110.3-46118.6" + wire $0\dp_CR_cr_a_branch0_1$next[0:0]$2647 + attribute \src "libresoc.v:42624.3-42625.57" + wire $0\dp_CR_cr_a_branch0_1[0:0] + attribute \src "libresoc.v:46091.3-46099.6" + wire $0\dp_CR_cr_a_cr0_0$next[0:0]$2641 + attribute \src "libresoc.v:42626.3-42627.49" + wire $0\dp_CR_cr_a_cr0_0[0:0] + attribute \src "libresoc.v:46129.3-46137.6" + wire $0\dp_CR_cr_b_cr0_0$next[0:0]$2653 + attribute \src "libresoc.v:42622.3-42623.49" + wire $0\dp_CR_cr_b_cr0_0[0:0] + attribute \src "libresoc.v:46178.3-46186.6" + wire $0\dp_CR_cr_c_cr0_0$next[0:0]$2660 + attribute \src "libresoc.v:42620.3-42621.49" + wire $0\dp_CR_cr_c_cr0_0[0:0] + attribute \src "libresoc.v:46042.3-46050.6" + wire $0\dp_CR_full_cr_cr0_0$next[0:0]$2634 + attribute \src "libresoc.v:42628.3-42629.55" + wire $0\dp_CR_full_cr_cr0_0[0:0] + attribute \src "libresoc.v:46197.3-46205.6" + wire $0\dp_FAST_fast1_branch0_0$next[0:0]$2666 + attribute \src "libresoc.v:42618.3-42619.63" + wire $0\dp_FAST_fast1_branch0_0[0:0] + attribute \src "libresoc.v:46264.3-46272.6" + wire $0\dp_FAST_fast1_spr0_2$next[0:0]$2679 + attribute \src "libresoc.v:42614.3-42615.57" + wire $0\dp_FAST_fast1_spr0_2[0:0] + attribute \src "libresoc.v:46216.3-46224.6" + wire $0\dp_FAST_fast1_trap0_1$next[0:0]$2672 + attribute \src "libresoc.v:42616.3-42617.59" + wire $0\dp_FAST_fast1_trap0_1[0:0] + attribute \src "libresoc.v:46312.3-46320.6" + wire $0\dp_FAST_fast2_branch0_0$next[0:0]$2686 + attribute \src "libresoc.v:42612.3-42613.63" + wire $0\dp_FAST_fast2_branch0_0[0:0] + attribute \src "libresoc.v:46331.3-46339.6" + wire $0\dp_FAST_fast2_trap0_1$next[0:0]$2692 + attribute \src "libresoc.v:42610.3-42611.59" + wire $0\dp_FAST_fast2_trap0_1[0:0] + attribute \src "libresoc.v:45264.3-45272.6" + wire $0\dp_INT_ra_alu0_0$next[0:0]$2457 + attribute \src "libresoc.v:42686.3-42687.49" + wire $0\dp_INT_ra_alu0_0[0:0] + attribute \src "libresoc.v:45283.3-45291.6" + wire $0\dp_INT_ra_cr0_1$next[0:0]$2461 + attribute \src "libresoc.v:42684.3-42685.47" + wire $0\dp_INT_ra_cr0_1[0:0] + attribute \src "libresoc.v:45359.3-45367.6" + wire $0\dp_INT_ra_div0_5$next[0:0]$2485 + attribute \src "libresoc.v:42676.3-42677.49" + wire $0\dp_INT_ra_div0_5[0:0] + attribute \src "libresoc.v:45416.3-45424.6" + wire $0\dp_INT_ra_ldst0_8$next[0:0]$2503 + attribute \src "libresoc.v:42670.3-42671.51" + wire $0\dp_INT_ra_ldst0_8[0:0] + attribute \src "libresoc.v:45321.3-45329.6" + wire $0\dp_INT_ra_logical0_3$next[0:0]$2473 + attribute \src "libresoc.v:42680.3-42681.57" + wire $0\dp_INT_ra_logical0_3[0:0] + attribute \src "libresoc.v:45378.3-45386.6" + wire $0\dp_INT_ra_mul0_6$next[0:0]$2491 + attribute \src "libresoc.v:42674.3-42675.49" + wire $0\dp_INT_ra_mul0_6[0:0] + attribute \src "libresoc.v:45397.3-45405.6" + wire $0\dp_INT_ra_shiftrot0_7$next[0:0]$2497 + attribute \src "libresoc.v:42672.3-42673.59" + wire $0\dp_INT_ra_shiftrot0_7[0:0] + attribute \src "libresoc.v:45340.3-45348.6" + wire $0\dp_INT_ra_spr0_4$next[0:0]$2479 + attribute \src "libresoc.v:42678.3-42679.49" + wire $0\dp_INT_ra_spr0_4[0:0] + attribute \src "libresoc.v:45302.3-45310.6" + wire $0\dp_INT_ra_trap0_2$next[0:0]$2467 + attribute \src "libresoc.v:42682.3-42683.51" + wire $0\dp_INT_ra_trap0_2[0:0] + attribute \src "libresoc.v:45435.3-45443.6" + wire $0\dp_INT_rb_alu0_0$next[0:0]$2509 + attribute \src "libresoc.v:42668.3-42669.49" + wire $0\dp_INT_rb_alu0_0[0:0] + attribute \src "libresoc.v:45454.3-45462.6" + wire $0\dp_INT_rb_cr0_1$next[0:0]$2513 + attribute \src "libresoc.v:42666.3-42667.47" + wire $0\dp_INT_rb_cr0_1[0:0] + attribute \src "libresoc.v:45511.3-45519.6" + wire $0\dp_INT_rb_div0_4$next[0:0]$2531 + attribute \src "libresoc.v:42660.3-42661.49" + wire $0\dp_INT_rb_div0_4[0:0] + attribute \src "libresoc.v:45568.3-45576.6" + wire $0\dp_INT_rb_ldst0_7$next[0:0]$2549 + attribute \src "libresoc.v:42654.3-42655.51" + wire $0\dp_INT_rb_ldst0_7[0:0] + attribute \src "libresoc.v:45492.3-45500.6" + wire $0\dp_INT_rb_logical0_3$next[0:0]$2525 + attribute \src "libresoc.v:42662.3-42663.57" + wire $0\dp_INT_rb_logical0_3[0:0] + attribute \src "libresoc.v:45530.3-45538.6" + wire $0\dp_INT_rb_mul0_5$next[0:0]$2537 + attribute \src "libresoc.v:42658.3-42659.49" + wire $0\dp_INT_rb_mul0_5[0:0] + attribute \src "libresoc.v:45549.3-45557.6" + wire $0\dp_INT_rb_shiftrot0_6$next[0:0]$2543 + attribute \src "libresoc.v:42656.3-42657.59" + wire $0\dp_INT_rb_shiftrot0_6[0:0] + attribute \src "libresoc.v:45473.3-45481.6" + wire $0\dp_INT_rb_trap0_2$next[0:0]$2519 + attribute \src "libresoc.v:42664.3-42665.51" + wire $0\dp_INT_rb_trap0_2[0:0] + attribute \src "libresoc.v:45606.3-45614.6" + wire $0\dp_INT_rc_ldst0_1$next[0:0]$2559 + attribute \src "libresoc.v:42650.3-42651.51" + wire $0\dp_INT_rc_ldst0_1[0:0] + attribute \src "libresoc.v:45587.3-45595.6" + wire $0\dp_INT_rc_shiftrot0_0$next[0:0]$2555 + attribute \src "libresoc.v:42652.3-42653.59" + wire $0\dp_INT_rc_shiftrot0_0[0:0] + attribute \src "libresoc.v:46379.3-46387.6" + wire $0\dp_SPR_spr1_spr0_0$next[0:0]$2699 + attribute \src "libresoc.v:42608.3-42609.53" + wire $0\dp_SPR_spr1_spr0_0[0:0] + attribute \src "libresoc.v:45907.3-45915.6" + wire $0\dp_XER_xer_ca_alu0_0$next[0:0]$2612 + attribute \src "libresoc.v:42636.3-42637.57" + wire $0\dp_XER_xer_ca_alu0_0[0:0] + attribute \src "libresoc.v:45974.3-45982.6" + wire $0\dp_XER_xer_ca_shiftrot0_2$next[0:0]$2623 + attribute \src "libresoc.v:42632.3-42633.67" + wire $0\dp_XER_xer_ca_shiftrot0_2[0:0] + attribute \src "libresoc.v:45955.3-45963.6" + wire $0\dp_XER_xer_ca_spr0_1$next[0:0]$2619 + attribute \src "libresoc.v:42634.3-42635.57" + wire $0\dp_XER_xer_ca_spr0_1[0:0] + attribute \src "libresoc.v:46023.3-46031.6" + wire $0\dp_XER_xer_ov_spr0_0$next[0:0]$2628 + attribute \src "libresoc.v:42630.3-42631.57" + wire $0\dp_XER_xer_ov_spr0_0[0:0] + attribute \src "libresoc.v:45652.3-45660.6" + wire $0\dp_XER_xer_so_alu0_0$next[0:0]$2571 + attribute \src "libresoc.v:42648.3-42649.57" + wire $0\dp_XER_xer_so_alu0_0[0:0] + attribute \src "libresoc.v:45821.3-45829.6" + wire $0\dp_XER_xer_so_div0_3$next[0:0]$2593 + attribute \src "libresoc.v:42642.3-42643.57" + wire $0\dp_XER_xer_so_div0_3[0:0] + attribute \src "libresoc.v:45762.3-45770.6" + wire $0\dp_XER_xer_so_logical0_1$next[0:0]$2578 + attribute \src "libresoc.v:42646.3-42647.65" + wire $0\dp_XER_xer_so_logical0_1[0:0] + attribute \src "libresoc.v:45840.3-45848.6" + wire $0\dp_XER_xer_so_mul0_4$next[0:0]$2599 + attribute \src "libresoc.v:42640.3-42641.57" + wire $0\dp_XER_xer_so_mul0_4[0:0] + attribute \src "libresoc.v:45888.3-45896.6" + wire $0\dp_XER_xer_so_shiftrot0_5$next[0:0]$2606 + attribute \src "libresoc.v:42638.3-42639.67" + wire $0\dp_XER_xer_so_shiftrot0_5[0:0] + attribute \src "libresoc.v:45781.3-45789.6" + wire $0\dp_XER_xer_so_spr0_2$next[0:0]$2584 + attribute \src "libresoc.v:42644.3-42645.57" + wire $0\dp_XER_xer_so_spr0_2[0:0] + attribute \src "libresoc.v:46899.3-46927.6" + wire $0\fus_cu_issue_i$13[0:0]$2768 + attribute \src "libresoc.v:47296.3-47324.6" + wire $0\fus_cu_issue_i$16[0:0]$2830 + attribute \src "libresoc.v:47660.3-47688.6" + wire $0\fus_cu_issue_i$19[0:0]$2864 + attribute \src "libresoc.v:48156.3-48184.6" + wire $0\fus_cu_issue_i$22[0:0]$2889 + attribute \src "libresoc.v:43483.3-43511.6" + wire $0\fus_cu_issue_i$25[0:0]$2356 + attribute \src "libresoc.v:43979.3-44007.6" + wire $0\fus_cu_issue_i$28[0:0]$2381 + attribute \src "libresoc.v:44301.3-44329.6" + wire $0\fus_cu_issue_i$31[0:0]$2400 + attribute \src "libresoc.v:44768.3-44796.6" + wire $0\fus_cu_issue_i$34[0:0]$2424 + attribute \src "libresoc.v:45206.3-45234.6" + wire $0\fus_cu_issue_i$37[0:0]$2447 + attribute \src "libresoc.v:46691.3-46719.6" + wire $0\fus_cu_issue_i[0:0] + attribute \src "libresoc.v:46937.3-46965.6" + wire width 6 $0\fus_cu_rdmaskn_i$15[5:0]$2776 + attribute \src "libresoc.v:47334.3-47362.6" + wire width 3 $0\fus_cu_rdmaskn_i$18[2:0]$2838 + attribute \src "libresoc.v:47689.3-47717.6" + wire width 4 $0\fus_cu_rdmaskn_i$21[3:0]$2869 + attribute \src "libresoc.v:48185.3-48213.6" + wire width 3 $0\fus_cu_rdmaskn_i$24[2:0]$2894 + attribute \src "libresoc.v:43512.3-43540.6" + wire width 6 $0\fus_cu_rdmaskn_i$27[5:0]$2361 + attribute \src "libresoc.v:44008.3-44036.6" + wire width 3 $0\fus_cu_rdmaskn_i$30[2:0]$2386 + attribute \src "libresoc.v:44330.3-44358.6" + wire width 3 $0\fus_cu_rdmaskn_i$33[2:0]$2405 + attribute \src "libresoc.v:44797.3-44825.6" + wire width 5 $0\fus_cu_rdmaskn_i$36[4:0]$2429 + attribute \src "libresoc.v:45235.3-45263.6" + wire width 3 $0\fus_cu_rdmaskn_i$39[2:0]$2452 + attribute \src "libresoc.v:46729.3-46757.6" + wire width 4 $0\fus_cu_rdmaskn_i[3:0] + attribute \src "libresoc.v:46606.3-46634.6" + wire width 4 $0\fus_oper_i_alu_alu0__data_len[3:0] + attribute \src "libresoc.v:45916.3-45944.6" + wire width 13 $0\fus_oper_i_alu_alu0__fn_unit[12:0] + attribute \src "libresoc.v:45983.3-46012.6" + wire width 64 $0\fus_oper_i_alu_alu0__imm_data__data[63:0] + attribute \src "libresoc.v:45983.3-46012.6" + wire $0\fus_oper_i_alu_alu0__imm_data__ok[0:0] + attribute \src "libresoc.v:46436.3-46464.6" + wire width 2 $0\fus_oper_i_alu_alu0__input_carry[1:0] + attribute \src "libresoc.v:46653.3-46681.6" + wire width 32 $0\fus_oper_i_alu_alu0__insn[31:0] + attribute \src "libresoc.v:45859.3-45887.6" + wire width 7 $0\fus_oper_i_alu_alu0__insn_type[6:0] + attribute \src "libresoc.v:46235.3-46263.6" + wire $0\fus_oper_i_alu_alu0__invert_in[0:0] + attribute \src "libresoc.v:46350.3-46378.6" + wire $0\fus_oper_i_alu_alu0__invert_out[0:0] + attribute \src "libresoc.v:46521.3-46549.6" + wire $0\fus_oper_i_alu_alu0__is_32bit[0:0] + attribute \src "libresoc.v:46568.3-46596.6" + wire $0\fus_oper_i_alu_alu0__is_signed[0:0] + attribute \src "libresoc.v:46148.3-46177.6" + wire $0\fus_oper_i_alu_alu0__oe__oe[0:0] + attribute \src "libresoc.v:46148.3-46177.6" + wire $0\fus_oper_i_alu_alu0__oe__ok[0:0] + attribute \src "libresoc.v:46483.3-46511.6" + wire $0\fus_oper_i_alu_alu0__output_carry[0:0] + attribute \src "libresoc.v:46061.3-46090.6" + wire $0\fus_oper_i_alu_alu0__rc__ok[0:0] + attribute \src "libresoc.v:46061.3-46090.6" + wire $0\fus_oper_i_alu_alu0__rc__rc[0:0] + attribute \src "libresoc.v:46398.3-46426.6" + wire $0\fus_oper_i_alu_alu0__write_cr0[0:0] + attribute \src "libresoc.v:46283.3-46311.6" + wire $0\fus_oper_i_alu_alu0__zero_a[0:0] + attribute \src "libresoc.v:46984.3-47012.6" + wire width 64 $0\fus_oper_i_alu_branch0__cia[63:0] + attribute \src "libresoc.v:47069.3-47097.6" + wire width 13 $0\fus_oper_i_alu_branch0__fn_unit[12:0] + attribute \src "libresoc.v:47154.3-47183.6" + wire width 64 $0\fus_oper_i_alu_branch0__imm_data__data[63:0] + attribute \src "libresoc.v:47154.3-47183.6" + wire $0\fus_oper_i_alu_branch0__imm_data__ok[0:0] + attribute \src "libresoc.v:47107.3-47135.6" + wire width 32 $0\fus_oper_i_alu_branch0__insn[31:0] + attribute \src "libresoc.v:47022.3-47050.6" + wire width 7 $0\fus_oper_i_alu_branch0__insn_type[6:0] + attribute \src "libresoc.v:47249.3-47277.6" + wire $0\fus_oper_i_alu_branch0__is_32bit[0:0] + attribute \src "libresoc.v:47211.3-47239.6" + wire $0\fus_oper_i_alu_branch0__lk[0:0] + attribute \src "libresoc.v:46814.3-46842.6" + wire width 13 $0\fus_oper_i_alu_cr0__fn_unit[12:0] + attribute \src "libresoc.v:46861.3-46889.6" + wire width 32 $0\fus_oper_i_alu_cr0__insn[31:0] + attribute \src "libresoc.v:46767.3-46795.6" + wire width 7 $0\fus_oper_i_alu_cr0__insn_type[6:0] + attribute \src "libresoc.v:43921.3-43949.6" + wire width 4 $0\fus_oper_i_alu_div0__data_len[3:0] + attribute \src "libresoc.v:43570.3-43598.6" + wire width 13 $0\fus_oper_i_alu_div0__fn_unit[12:0] + attribute \src "libresoc.v:43599.3-43628.6" + wire width 64 $0\fus_oper_i_alu_div0__imm_data__data[63:0] + attribute \src "libresoc.v:43599.3-43628.6" + wire $0\fus_oper_i_alu_div0__imm_data__ok[0:0] + attribute \src "libresoc.v:43747.3-43775.6" + wire width 2 $0\fus_oper_i_alu_div0__input_carry[1:0] + attribute \src "libresoc.v:43950.3-43978.6" + wire width 32 $0\fus_oper_i_alu_div0__insn[31:0] + attribute \src "libresoc.v:43541.3-43569.6" + wire width 7 $0\fus_oper_i_alu_div0__insn_type[6:0] + attribute \src "libresoc.v:43689.3-43717.6" + wire $0\fus_oper_i_alu_div0__invert_in[0:0] + attribute \src "libresoc.v:43776.3-43804.6" + wire $0\fus_oper_i_alu_div0__invert_out[0:0] + attribute \src "libresoc.v:43863.3-43891.6" + wire $0\fus_oper_i_alu_div0__is_32bit[0:0] + attribute \src "libresoc.v:43892.3-43920.6" + wire $0\fus_oper_i_alu_div0__is_signed[0:0] + attribute \src "libresoc.v:43659.3-43688.6" + wire $0\fus_oper_i_alu_div0__oe__oe[0:0] + attribute \src "libresoc.v:43659.3-43688.6" + wire $0\fus_oper_i_alu_div0__oe__ok[0:0] + attribute \src "libresoc.v:43834.3-43862.6" + wire $0\fus_oper_i_alu_div0__output_carry[0:0] + attribute \src "libresoc.v:43629.3-43658.6" + wire $0\fus_oper_i_alu_div0__rc__ok[0:0] + attribute \src "libresoc.v:43629.3-43658.6" + wire $0\fus_oper_i_alu_div0__rc__rc[0:0] + attribute \src "libresoc.v:43805.3-43833.6" + wire $0\fus_oper_i_alu_div0__write_cr0[0:0] + attribute \src "libresoc.v:43718.3-43746.6" + wire $0\fus_oper_i_alu_div0__zero_a[0:0] + attribute \src "libresoc.v:48098.3-48126.6" + wire width 4 $0\fus_oper_i_alu_logical0__data_len[3:0] + attribute \src "libresoc.v:47747.3-47775.6" + wire width 13 $0\fus_oper_i_alu_logical0__fn_unit[12:0] + attribute \src "libresoc.v:47776.3-47805.6" + wire width 64 $0\fus_oper_i_alu_logical0__imm_data__data[63:0] + attribute \src "libresoc.v:47776.3-47805.6" + wire $0\fus_oper_i_alu_logical0__imm_data__ok[0:0] + attribute \src "libresoc.v:47924.3-47952.6" + wire width 2 $0\fus_oper_i_alu_logical0__input_carry[1:0] + attribute \src "libresoc.v:48127.3-48155.6" + wire width 32 $0\fus_oper_i_alu_logical0__insn[31:0] + attribute \src "libresoc.v:47718.3-47746.6" + wire width 7 $0\fus_oper_i_alu_logical0__insn_type[6:0] + attribute \src "libresoc.v:47866.3-47894.6" + wire $0\fus_oper_i_alu_logical0__invert_in[0:0] + attribute \src "libresoc.v:47953.3-47981.6" + wire $0\fus_oper_i_alu_logical0__invert_out[0:0] + attribute \src "libresoc.v:48040.3-48068.6" + wire $0\fus_oper_i_alu_logical0__is_32bit[0:0] + attribute \src "libresoc.v:48069.3-48097.6" + wire $0\fus_oper_i_alu_logical0__is_signed[0:0] + attribute \src "libresoc.v:47836.3-47865.6" + wire $0\fus_oper_i_alu_logical0__oe__oe[0:0] + attribute \src "libresoc.v:47836.3-47865.6" + wire $0\fus_oper_i_alu_logical0__oe__ok[0:0] + attribute \src "libresoc.v:48011.3-48039.6" + wire $0\fus_oper_i_alu_logical0__output_carry[0:0] + attribute \src "libresoc.v:47806.3-47835.6" + wire $0\fus_oper_i_alu_logical0__rc__ok[0:0] + attribute \src "libresoc.v:47806.3-47835.6" + wire $0\fus_oper_i_alu_logical0__rc__rc[0:0] + attribute \src "libresoc.v:47982.3-48010.6" + wire $0\fus_oper_i_alu_logical0__write_cr0[0:0] + attribute \src "libresoc.v:47895.3-47923.6" + wire $0\fus_oper_i_alu_logical0__zero_a[0:0] + attribute \src "libresoc.v:44066.3-44094.6" + wire width 13 $0\fus_oper_i_alu_mul0__fn_unit[12:0] + attribute \src "libresoc.v:44095.3-44124.6" + wire width 64 $0\fus_oper_i_alu_mul0__imm_data__data[63:0] + attribute \src "libresoc.v:44095.3-44124.6" + wire $0\fus_oper_i_alu_mul0__imm_data__ok[0:0] + attribute \src "libresoc.v:44272.3-44300.6" + wire width 32 $0\fus_oper_i_alu_mul0__insn[31:0] + attribute \src "libresoc.v:44037.3-44065.6" + wire width 7 $0\fus_oper_i_alu_mul0__insn_type[6:0] + attribute \src "libresoc.v:44214.3-44242.6" + wire $0\fus_oper_i_alu_mul0__is_32bit[0:0] + attribute \src "libresoc.v:44243.3-44271.6" + wire $0\fus_oper_i_alu_mul0__is_signed[0:0] + attribute \src "libresoc.v:44155.3-44184.6" + wire $0\fus_oper_i_alu_mul0__oe__oe[0:0] + attribute \src "libresoc.v:44155.3-44184.6" + wire $0\fus_oper_i_alu_mul0__oe__ok[0:0] + attribute \src "libresoc.v:44125.3-44154.6" + wire $0\fus_oper_i_alu_mul0__rc__ok[0:0] + attribute \src "libresoc.v:44125.3-44154.6" + wire $0\fus_oper_i_alu_mul0__rc__rc[0:0] + attribute \src "libresoc.v:44185.3-44213.6" + wire $0\fus_oper_i_alu_mul0__write_cr0[0:0] + attribute \src "libresoc.v:44388.3-44416.6" + wire width 13 $0\fus_oper_i_alu_shift_rot0__fn_unit[12:0] + attribute \src "libresoc.v:44417.3-44446.6" + wire width 64 $0\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] + attribute \src "libresoc.v:44417.3-44446.6" + wire $0\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] + attribute \src "libresoc.v:44565.3-44593.6" + wire width 2 $0\fus_oper_i_alu_shift_rot0__input_carry[1:0] + attribute \src "libresoc.v:44623.3-44651.6" + wire $0\fus_oper_i_alu_shift_rot0__input_cr[0:0] + attribute \src "libresoc.v:44739.3-44767.6" + wire width 32 $0\fus_oper_i_alu_shift_rot0__insn[31:0] + attribute \src "libresoc.v:44359.3-44387.6" + wire width 7 $0\fus_oper_i_alu_shift_rot0__insn_type[6:0] + attribute \src "libresoc.v:44536.3-44564.6" + wire $0\fus_oper_i_alu_shift_rot0__invert_in[0:0] + attribute \src "libresoc.v:44681.3-44709.6" + wire $0\fus_oper_i_alu_shift_rot0__is_32bit[0:0] + attribute \src "libresoc.v:44710.3-44738.6" + wire $0\fus_oper_i_alu_shift_rot0__is_signed[0:0] + attribute \src "libresoc.v:44477.3-44506.6" + wire $0\fus_oper_i_alu_shift_rot0__oe__oe[0:0] + attribute \src "libresoc.v:44477.3-44506.6" + wire $0\fus_oper_i_alu_shift_rot0__oe__ok[0:0] + attribute \src "libresoc.v:44594.3-44622.6" + wire $0\fus_oper_i_alu_shift_rot0__output_carry[0:0] + attribute \src "libresoc.v:44652.3-44680.6" + wire $0\fus_oper_i_alu_shift_rot0__output_cr[0:0] + attribute \src "libresoc.v:44447.3-44476.6" + wire $0\fus_oper_i_alu_shift_rot0__rc__ok[0:0] + attribute \src "libresoc.v:44447.3-44476.6" + wire $0\fus_oper_i_alu_shift_rot0__rc__rc[0:0] + attribute \src "libresoc.v:44507.3-44535.6" + wire $0\fus_oper_i_alu_shift_rot0__write_cr0[0:0] + attribute \src "libresoc.v:48243.3-48271.6" + wire width 13 $0\fus_oper_i_alu_spr0__fn_unit[12:0] + attribute \src "libresoc.v:43425.3-43453.6" + wire width 32 $0\fus_oper_i_alu_spr0__insn[31:0] + attribute \src "libresoc.v:48214.3-48242.6" + wire width 7 $0\fus_oper_i_alu_spr0__insn_type[6:0] + attribute \src "libresoc.v:43454.3-43482.6" + wire $0\fus_oper_i_alu_spr0__is_32bit[0:0] + attribute \src "libresoc.v:47515.3-47543.6" + wire width 64 $0\fus_oper_i_alu_trap0__cia[63:0] + attribute \src "libresoc.v:47419.3-47447.6" + wire width 13 $0\fus_oper_i_alu_trap0__fn_unit[12:0] + attribute \src "libresoc.v:47457.3-47485.6" + wire width 32 $0\fus_oper_i_alu_trap0__insn[31:0] + attribute \src "libresoc.v:47372.3-47400.6" + wire width 7 $0\fus_oper_i_alu_trap0__insn_type[6:0] + attribute \src "libresoc.v:47544.3-47572.6" + wire $0\fus_oper_i_alu_trap0__is_32bit[0:0] + attribute \src "libresoc.v:47631.3-47659.6" + wire width 8 $0\fus_oper_i_alu_trap0__ldst_exc[7:0] + attribute \src "libresoc.v:47486.3-47514.6" + wire width 64 $0\fus_oper_i_alu_trap0__msr[63:0] + attribute \src "libresoc.v:47602.3-47630.6" + wire width 13 $0\fus_oper_i_alu_trap0__trapaddr[12:0] + attribute \src "libresoc.v:47573.3-47601.6" + wire width 8 $0\fus_oper_i_alu_trap0__traptype[7:0] + attribute \src "libresoc.v:45090.3-45118.6" + wire $0\fus_oper_i_ldst_ldst0__byte_reverse[0:0] + attribute \src "libresoc.v:45061.3-45089.6" + wire width 4 $0\fus_oper_i_ldst_ldst0__data_len[3:0] + attribute \src "libresoc.v:44855.3-44883.6" + wire width 13 $0\fus_oper_i_ldst_ldst0__fn_unit[12:0] + attribute \src "libresoc.v:44884.3-44913.6" + wire width 64 $0\fus_oper_i_ldst_ldst0__imm_data__data[63:0] + attribute \src "libresoc.v:44884.3-44913.6" + wire $0\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] + attribute \src "libresoc.v:45177.3-45205.6" + wire width 32 $0\fus_oper_i_ldst_ldst0__insn[31:0] + attribute \src "libresoc.v:44826.3-44854.6" + wire width 7 $0\fus_oper_i_ldst_ldst0__insn_type[6:0] + attribute \src "libresoc.v:45003.3-45031.6" + wire $0\fus_oper_i_ldst_ldst0__is_32bit[0:0] + attribute \src "libresoc.v:45032.3-45060.6" + wire $0\fus_oper_i_ldst_ldst0__is_signed[0:0] + attribute \src "libresoc.v:45148.3-45176.6" + wire width 2 $0\fus_oper_i_ldst_ldst0__ldst_mode[1:0] + attribute \src "libresoc.v:44973.3-45002.6" + wire $0\fus_oper_i_ldst_ldst0__oe__oe[0:0] + attribute \src "libresoc.v:44973.3-45002.6" + wire $0\fus_oper_i_ldst_ldst0__oe__ok[0:0] + attribute \src "libresoc.v:44943.3-44972.6" + wire $0\fus_oper_i_ldst_ldst0__rc__ok[0:0] + attribute \src "libresoc.v:44943.3-44972.6" + wire $0\fus_oper_i_ldst_ldst0__rc__rc[0:0] + attribute \src "libresoc.v:45119.3-45147.6" + wire $0\fus_oper_i_ldst_ldst0__sign_extend[0:0] + attribute \src "libresoc.v:44914.3-44942.6" + wire $0\fus_oper_i_ldst_ldst0__zero_a[0:0] + attribute \src "libresoc.v:45292.3-45301.6" + wire width 64 $0\fus_src1_i$42[63:0]$2464 + attribute \src "libresoc.v:45311.3-45320.6" + wire width 64 $0\fus_src1_i$45[63:0]$2470 + attribute \src "libresoc.v:45330.3-45339.6" + wire width 64 $0\fus_src1_i$48[63:0]$2476 + attribute \src "libresoc.v:45349.3-45358.6" + wire width 64 $0\fus_src1_i$51[63:0]$2482 + attribute \src "libresoc.v:45368.3-45377.6" + wire width 64 $0\fus_src1_i$54[63:0]$2488 + attribute \src "libresoc.v:45387.3-45396.6" + wire width 64 $0\fus_src1_i$57[63:0]$2494 + attribute \src "libresoc.v:45406.3-45415.6" + wire width 64 $0\fus_src1_i$60[63:0]$2500 + attribute \src "libresoc.v:45425.3-45434.6" + wire width 64 $0\fus_src1_i$63[63:0]$2506 + attribute \src "libresoc.v:46206.3-46215.6" + wire width 64 $0\fus_src1_i$86[63:0]$2669 + attribute \src "libresoc.v:45273.3-45282.6" + wire width 64 $0\fus_src1_i[63:0] + attribute \src "libresoc.v:45463.3-45472.6" + wire width 64 $0\fus_src2_i$64[63:0]$2516 + attribute \src "libresoc.v:45482.3-45491.6" + wire width 64 $0\fus_src2_i$65[63:0]$2522 + attribute \src "libresoc.v:45501.3-45510.6" + wire width 64 $0\fus_src2_i$66[63:0]$2528 + attribute \src "libresoc.v:45520.3-45529.6" + wire width 64 $0\fus_src2_i$67[63:0]$2534 + attribute \src "libresoc.v:45539.3-45548.6" + wire width 64 $0\fus_src2_i$68[63:0]$2540 + attribute \src "libresoc.v:45558.3-45567.6" + wire width 64 $0\fus_src2_i$69[63:0]$2546 + attribute \src "libresoc.v:45577.3-45586.6" + wire width 64 $0\fus_src2_i$70[63:0]$2552 + attribute \src "libresoc.v:46321.3-46330.6" + wire width 64 $0\fus_src2_i$89[63:0]$2689 + attribute \src "libresoc.v:46388.3-46397.6" + wire width 64 $0\fus_src2_i$91[63:0]$2702 + attribute \src "libresoc.v:45444.3-45453.6" + wire width 64 $0\fus_src2_i[63:0] + attribute \src "libresoc.v:45615.3-45624.6" + wire width 64 $0\fus_src3_i$71[63:0]$2562 + attribute \src "libresoc.v:45661.3-45670.6" + wire $0\fus_src3_i$72[0:0]$2574 + attribute \src "libresoc.v:45771.3-45780.6" + wire $0\fus_src3_i$73[0:0]$2581 + attribute \src "libresoc.v:45830.3-45839.6" + wire $0\fus_src3_i$74[0:0]$2596 + attribute \src "libresoc.v:45849.3-45858.6" + wire $0\fus_src3_i$75[0:0]$2602 + attribute \src "libresoc.v:46051.3-46060.6" + wire width 32 $0\fus_src3_i$79[31:0]$2637 + attribute \src "libresoc.v:46119.3-46128.6" + wire width 4 $0\fus_src3_i$83[3:0]$2650 + attribute \src "libresoc.v:46225.3-46234.6" + wire width 64 $0\fus_src3_i$87[63:0]$2675 + attribute \src "libresoc.v:46273.3-46282.6" + wire width 64 $0\fus_src3_i$88[63:0]$2682 + attribute \src "libresoc.v:45596.3-45605.6" + wire width 64 $0\fus_src3_i[63:0] + attribute \src "libresoc.v:45897.3-45906.6" + wire $0\fus_src4_i$76[0:0]$2609 + attribute \src "libresoc.v:45945.3-45954.6" + wire width 2 $0\fus_src4_i$77[1:0]$2616 + attribute \src "libresoc.v:46100.3-46109.6" + wire width 4 $0\fus_src4_i$80[3:0]$2644 + attribute \src "libresoc.v:46340.3-46349.6" + wire width 64 $0\fus_src4_i$90[63:0]$2695 + attribute \src "libresoc.v:45790.3-45799.6" + wire $0\fus_src4_i[0:0] + attribute \src "libresoc.v:46032.3-46041.6" + wire width 2 $0\fus_src5_i$78[1:0]$2631 + attribute \src "libresoc.v:46138.3-46147.6" + wire width 4 $0\fus_src5_i$84[3:0]$2656 + attribute \src "libresoc.v:46013.3-46022.6" + wire width 2 $0\fus_src5_i[1:0] + attribute \src "libresoc.v:46187.3-46196.6" + wire width 4 $0\fus_src6_i$85[3:0]$2663 + attribute \src "libresoc.v:45964.3-45973.6" + wire width 2 $0\fus_src6_i[1:0] + attribute \src "libresoc.v:35982.7-35982.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:46474.3-46482.6" + wire $0\wr_pick_dly$1005$next[0:0]$2713 + attribute \src "libresoc.v:42602.3-42603.51" + wire $0\wr_pick_dly$1005[0:0]$2307 + attribute \src "libresoc.v:41432.7-41432.32" + wire $0\wr_pick_dly$1005[0:0]$2945 + attribute \src "libresoc.v:46512.3-46520.6" + wire $0\wr_pick_dly$1026$next[0:0]$2717 + attribute \src "libresoc.v:42600.3-42601.51" + wire $0\wr_pick_dly$1026[0:0]$2305 + attribute \src "libresoc.v:41436.7-41436.32" + wire $0\wr_pick_dly$1026[0:0]$2947 + attribute \src "libresoc.v:46550.3-46558.6" + wire $0\wr_pick_dly$1044$next[0:0]$2721 + attribute \src "libresoc.v:42598.3-42599.51" + wire $0\wr_pick_dly$1044[0:0]$2303 + attribute \src "libresoc.v:41440.7-41440.32" + wire $0\wr_pick_dly$1044[0:0]$2949 + attribute \src "libresoc.v:46559.3-46567.6" + wire $0\wr_pick_dly$1066$next[0:0]$2724 + attribute \src "libresoc.v:42596.3-42597.51" + wire $0\wr_pick_dly$1066[0:0]$2301 + attribute \src "libresoc.v:41444.7-41444.32" + wire $0\wr_pick_dly$1066[0:0]$2951 + attribute \src "libresoc.v:46597.3-46605.6" + wire $0\wr_pick_dly$1086$next[0:0]$2728 + attribute \src "libresoc.v:42594.3-42595.51" + wire $0\wr_pick_dly$1086[0:0]$2299 + attribute \src "libresoc.v:41448.7-41448.32" + wire $0\wr_pick_dly$1086[0:0]$2953 + attribute \src "libresoc.v:46635.3-46643.6" + wire $0\wr_pick_dly$1106$next[0:0]$2732 + attribute \src "libresoc.v:42592.3-42593.51" + wire $0\wr_pick_dly$1106[0:0]$2297 + attribute \src "libresoc.v:41452.7-41452.32" + wire $0\wr_pick_dly$1106[0:0]$2955 + attribute \src "libresoc.v:46644.3-46652.6" + wire $0\wr_pick_dly$1125$next[0:0]$2735 + attribute \src "libresoc.v:42590.3-42591.51" + wire $0\wr_pick_dly$1125[0:0]$2295 + attribute \src "libresoc.v:41456.7-41456.32" + wire $0\wr_pick_dly$1125[0:0]$2957 + attribute \src "libresoc.v:46682.3-46690.6" + wire $0\wr_pick_dly$1143$next[0:0]$2739 + attribute \src "libresoc.v:42588.3-42589.51" + wire $0\wr_pick_dly$1143[0:0]$2293 + attribute \src "libresoc.v:41460.7-41460.32" + wire $0\wr_pick_dly$1143[0:0]$2959 + attribute \src "libresoc.v:46720.3-46728.6" + wire $0\wr_pick_dly$1217$next[0:0]$2743 + attribute \src "libresoc.v:42586.3-42587.51" + wire $0\wr_pick_dly$1217[0:0]$2291 + attribute \src "libresoc.v:41464.7-41464.32" + wire $0\wr_pick_dly$1217[0:0]$2961 + attribute \src "libresoc.v:46758.3-46766.6" + wire $0\wr_pick_dly$1245$next[0:0]$2747 + attribute \src "libresoc.v:42584.3-42585.51" + wire $0\wr_pick_dly$1245[0:0]$2289 + attribute \src "libresoc.v:41468.7-41468.32" + wire $0\wr_pick_dly$1245[0:0]$2963 + attribute \src "libresoc.v:46796.3-46804.6" + wire $0\wr_pick_dly$1265$next[0:0]$2751 + attribute \src "libresoc.v:42582.3-42583.51" + wire $0\wr_pick_dly$1265[0:0]$2287 + attribute \src "libresoc.v:41472.7-41472.32" + wire $0\wr_pick_dly$1265[0:0]$2965 + attribute \src "libresoc.v:46805.3-46813.6" + wire $0\wr_pick_dly$1285$next[0:0]$2754 + attribute \src "libresoc.v:42580.3-42581.51" + wire $0\wr_pick_dly$1285[0:0]$2285 + attribute \src "libresoc.v:41476.7-41476.32" + wire $0\wr_pick_dly$1285[0:0]$2967 + attribute \src "libresoc.v:46843.3-46851.6" + wire $0\wr_pick_dly$1305$next[0:0]$2758 + attribute \src "libresoc.v:42578.3-42579.51" + wire $0\wr_pick_dly$1305[0:0]$2283 + attribute \src "libresoc.v:41480.7-41480.32" + wire $0\wr_pick_dly$1305[0:0]$2969 + attribute \src "libresoc.v:46852.3-46860.6" + wire $0\wr_pick_dly$1325$next[0:0]$2761 + attribute \src "libresoc.v:42576.3-42577.51" + wire $0\wr_pick_dly$1325[0:0]$2281 + attribute \src "libresoc.v:41484.7-41484.32" + wire $0\wr_pick_dly$1325[0:0]$2971 + attribute \src "libresoc.v:46890.3-46898.6" + wire $0\wr_pick_dly$1345$next[0:0]$2765 + attribute \src "libresoc.v:42574.3-42575.51" + wire $0\wr_pick_dly$1345[0:0]$2279 + attribute \src "libresoc.v:41488.7-41488.32" + wire $0\wr_pick_dly$1345[0:0]$2973 + attribute \src "libresoc.v:46928.3-46936.6" + wire $0\wr_pick_dly$1392$next[0:0]$2773 + attribute \src "libresoc.v:42572.3-42573.51" + wire $0\wr_pick_dly$1392[0:0]$2277 + attribute \src "libresoc.v:41492.7-41492.32" + wire $0\wr_pick_dly$1392[0:0]$2975 + attribute \src "libresoc.v:46966.3-46974.6" + wire $0\wr_pick_dly$1408$next[0:0]$2781 + attribute \src "libresoc.v:42570.3-42571.51" + wire $0\wr_pick_dly$1408[0:0]$2275 + attribute \src "libresoc.v:41496.7-41496.32" + wire $0\wr_pick_dly$1408[0:0]$2977 + attribute \src "libresoc.v:46975.3-46983.6" + wire $0\wr_pick_dly$1424$next[0:0]$2784 + attribute \src "libresoc.v:42568.3-42569.51" + wire $0\wr_pick_dly$1424[0:0]$2273 + attribute \src "libresoc.v:41500.7-41500.32" + wire $0\wr_pick_dly$1424[0:0]$2979 + attribute \src "libresoc.v:47013.3-47021.6" + wire $0\wr_pick_dly$1458$next[0:0]$2788 + attribute \src "libresoc.v:42566.3-42567.51" + wire $0\wr_pick_dly$1458[0:0]$2271 + attribute \src "libresoc.v:41504.7-41504.32" + wire $0\wr_pick_dly$1458[0:0]$2981 + attribute \src "libresoc.v:47051.3-47059.6" + wire $0\wr_pick_dly$1474$next[0:0]$2792 + attribute \src "libresoc.v:42564.3-42565.51" + wire $0\wr_pick_dly$1474[0:0]$2269 + attribute \src "libresoc.v:41508.7-41508.32" + wire $0\wr_pick_dly$1474[0:0]$2983 + attribute \src "libresoc.v:47060.3-47068.6" + wire $0\wr_pick_dly$1490$next[0:0]$2795 + attribute \src "libresoc.v:42562.3-42563.51" + wire $0\wr_pick_dly$1490[0:0]$2267 + attribute \src "libresoc.v:41512.7-41512.32" + wire $0\wr_pick_dly$1490[0:0]$2985 + attribute \src "libresoc.v:47098.3-47106.6" + wire $0\wr_pick_dly$1506$next[0:0]$2799 + attribute \src "libresoc.v:42560.3-42561.51" + wire $0\wr_pick_dly$1506[0:0]$2265 + attribute \src "libresoc.v:41516.7-41516.32" + wire $0\wr_pick_dly$1506[0:0]$2987 + attribute \src "libresoc.v:47136.3-47144.6" + wire $0\wr_pick_dly$1542$next[0:0]$2803 + attribute \src "libresoc.v:42558.3-42559.51" + wire $0\wr_pick_dly$1542[0:0]$2263 + attribute \src "libresoc.v:41520.7-41520.32" + wire $0\wr_pick_dly$1542[0:0]$2989 + attribute \src "libresoc.v:47145.3-47153.6" + wire $0\wr_pick_dly$1558$next[0:0]$2806 + attribute \src "libresoc.v:42556.3-42557.51" + wire $0\wr_pick_dly$1558[0:0]$2261 + attribute \src "libresoc.v:41524.7-41524.32" + wire $0\wr_pick_dly$1558[0:0]$2991 + attribute \src "libresoc.v:47184.3-47192.6" + wire $0\wr_pick_dly$1574$next[0:0]$2810 + attribute \src "libresoc.v:42554.3-42555.51" + wire $0\wr_pick_dly$1574[0:0]$2259 + attribute \src "libresoc.v:41528.7-41528.32" + wire $0\wr_pick_dly$1574[0:0]$2993 + attribute \src "libresoc.v:47193.3-47201.6" + wire $0\wr_pick_dly$1590$next[0:0]$2813 + attribute \src "libresoc.v:42552.3-42553.51" + wire $0\wr_pick_dly$1590[0:0]$2257 + attribute \src "libresoc.v:41532.7-41532.32" + wire $0\wr_pick_dly$1590[0:0]$2995 + attribute \src "libresoc.v:47202.3-47210.6" + wire $0\wr_pick_dly$1632$next[0:0]$2816 + attribute \src "libresoc.v:42550.3-42551.51" + wire $0\wr_pick_dly$1632[0:0]$2255 + attribute \src "libresoc.v:41536.7-41536.32" + wire $0\wr_pick_dly$1632[0:0]$2997 + attribute \src "libresoc.v:47240.3-47248.6" + wire $0\wr_pick_dly$1651$next[0:0]$2820 + attribute \src "libresoc.v:42548.3-42549.51" + wire $0\wr_pick_dly$1651[0:0]$2253 + attribute \src "libresoc.v:41540.7-41540.32" + wire $0\wr_pick_dly$1651[0:0]$2999 + attribute \src "libresoc.v:47278.3-47286.6" + wire $0\wr_pick_dly$1667$next[0:0]$2824 + attribute \src "libresoc.v:42546.3-42547.51" + wire $0\wr_pick_dly$1667[0:0]$2251 + attribute \src "libresoc.v:41544.7-41544.32" + wire $0\wr_pick_dly$1667[0:0]$3001 + attribute \src "libresoc.v:47287.3-47295.6" + wire $0\wr_pick_dly$1683$next[0:0]$2827 + attribute \src "libresoc.v:42544.3-42545.51" + wire $0\wr_pick_dly$1683[0:0]$2249 + attribute \src "libresoc.v:41548.7-41548.32" + wire $0\wr_pick_dly$1683[0:0]$3003 + attribute \src "libresoc.v:47325.3-47333.6" + wire $0\wr_pick_dly$1699$next[0:0]$2835 + attribute \src "libresoc.v:42542.3-42543.51" + wire $0\wr_pick_dly$1699[0:0]$2247 + attribute \src "libresoc.v:41552.7-41552.32" + wire $0\wr_pick_dly$1699[0:0]$3005 + attribute \src "libresoc.v:47363.3-47371.6" + wire $0\wr_pick_dly$1743$next[0:0]$2843 + attribute \src "libresoc.v:42540.3-42541.51" + wire $0\wr_pick_dly$1743[0:0]$2245 + attribute \src "libresoc.v:41556.7-41556.32" + wire $0\wr_pick_dly$1743[0:0]$3007 + attribute \src "libresoc.v:47401.3-47409.6" + wire $0\wr_pick_dly$1759$next[0:0]$2847 + attribute \src "libresoc.v:42538.3-42539.51" + wire $0\wr_pick_dly$1759[0:0]$2243 + attribute \src "libresoc.v:41560.7-41560.32" + wire $0\wr_pick_dly$1759[0:0]$3009 + attribute \src "libresoc.v:47410.3-47418.6" + wire $0\wr_pick_dly$1783$next[0:0]$2850 + attribute \src "libresoc.v:42536.3-42537.51" + wire $0\wr_pick_dly$1783[0:0]$2241 + attribute \src "libresoc.v:41564.7-41564.32" + wire $0\wr_pick_dly$1783[0:0]$3011 + attribute \src "libresoc.v:47448.3-47456.6" + wire $0\wr_pick_dly$1803$next[0:0]$2854 + attribute \src "libresoc.v:42534.3-42535.51" + wire $0\wr_pick_dly$1803[0:0]$2239 + attribute \src "libresoc.v:41568.7-41568.32" + wire $0\wr_pick_dly$1803[0:0]$3013 + attribute \src "libresoc.v:46465.3-46473.6" + wire $0\wr_pick_dly$986$next[0:0]$2710 + attribute \src "libresoc.v:42604.3-42605.49" + wire $0\wr_pick_dly$986[0:0]$2309 + attribute \src "libresoc.v:41572.7-41572.31" + wire $0\wr_pick_dly$986[0:0]$3015 + attribute \src "libresoc.v:46427.3-46435.6" + wire $0\wr_pick_dly$next[0:0]$2706 + attribute \src "libresoc.v:42606.3-42607.39" + wire $0\wr_pick_dly[0:0] + attribute \src "libresoc.v:45671.3-45761.6" + wire $10\corebusy_o[0:0] + attribute \src "libresoc.v:45671.3-45761.6" + wire $11\corebusy_o[0:0] + attribute \src "libresoc.v:45671.3-45761.6" + wire $12\corebusy_o[0:0] + attribute \src "libresoc.v:45671.3-45761.6" + wire $13\corebusy_o[0:0] + attribute \src "libresoc.v:45800.3-45820.6" + wire $1\core_terminate_o$next[0:0]$2589 + attribute \src "libresoc.v:38027.7-38027.30" + wire $1\core_terminate_o[0:0] + attribute \src "libresoc.v:45671.3-45761.6" + wire $1\corebusy_o[0:0] + attribute \src "libresoc.v:45625.3-45651.6" + wire width 2 $1\counter$next[1:0]$2566 + attribute \src "libresoc.v:38040.13-38040.27" + wire width 2 $1\counter[1:0] + attribute \src "libresoc.v:46110.3-46118.6" + wire $1\dp_CR_cr_a_branch0_1$next[0:0]$2648 + attribute \src "libresoc.v:39181.7-39181.34" + wire $1\dp_CR_cr_a_branch0_1[0:0] + attribute \src "libresoc.v:46091.3-46099.6" + wire $1\dp_CR_cr_a_cr0_0$next[0:0]$2642 + attribute \src "libresoc.v:39185.7-39185.30" + wire $1\dp_CR_cr_a_cr0_0[0:0] + attribute \src "libresoc.v:46129.3-46137.6" + wire $1\dp_CR_cr_b_cr0_0$next[0:0]$2654 + attribute \src "libresoc.v:39189.7-39189.30" + wire $1\dp_CR_cr_b_cr0_0[0:0] + attribute \src "libresoc.v:46178.3-46186.6" + wire $1\dp_CR_cr_c_cr0_0$next[0:0]$2661 + attribute \src "libresoc.v:39193.7-39193.30" + wire $1\dp_CR_cr_c_cr0_0[0:0] + attribute \src "libresoc.v:46042.3-46050.6" + wire $1\dp_CR_full_cr_cr0_0$next[0:0]$2635 + attribute \src "libresoc.v:39197.7-39197.33" + wire $1\dp_CR_full_cr_cr0_0[0:0] + attribute \src "libresoc.v:46197.3-46205.6" + wire $1\dp_FAST_fast1_branch0_0$next[0:0]$2667 + attribute \src "libresoc.v:39201.7-39201.37" + wire $1\dp_FAST_fast1_branch0_0[0:0] + attribute \src "libresoc.v:46264.3-46272.6" + wire $1\dp_FAST_fast1_spr0_2$next[0:0]$2680 + attribute \src "libresoc.v:39205.7-39205.34" + wire $1\dp_FAST_fast1_spr0_2[0:0] + attribute \src "libresoc.v:46216.3-46224.6" + wire $1\dp_FAST_fast1_trap0_1$next[0:0]$2673 + attribute \src "libresoc.v:39209.7-39209.35" + wire $1\dp_FAST_fast1_trap0_1[0:0] + attribute \src "libresoc.v:46312.3-46320.6" + wire $1\dp_FAST_fast2_branch0_0$next[0:0]$2687 + attribute \src "libresoc.v:39213.7-39213.37" + wire $1\dp_FAST_fast2_branch0_0[0:0] + attribute \src "libresoc.v:46331.3-46339.6" + wire $1\dp_FAST_fast2_trap0_1$next[0:0]$2693 + attribute \src "libresoc.v:39217.7-39217.35" + wire $1\dp_FAST_fast2_trap0_1[0:0] + attribute \src "libresoc.v:45264.3-45272.6" + wire $1\dp_INT_ra_alu0_0$next[0:0]$2458 + attribute \src "libresoc.v:39221.7-39221.30" + wire $1\dp_INT_ra_alu0_0[0:0] + attribute \src "libresoc.v:45283.3-45291.6" + wire $1\dp_INT_ra_cr0_1$next[0:0]$2462 + attribute \src "libresoc.v:39225.7-39225.29" + wire $1\dp_INT_ra_cr0_1[0:0] + attribute \src "libresoc.v:45359.3-45367.6" + wire $1\dp_INT_ra_div0_5$next[0:0]$2486 + attribute \src "libresoc.v:39229.7-39229.30" + wire $1\dp_INT_ra_div0_5[0:0] + attribute \src "libresoc.v:45416.3-45424.6" + wire $1\dp_INT_ra_ldst0_8$next[0:0]$2504 + attribute \src "libresoc.v:39233.7-39233.31" + wire $1\dp_INT_ra_ldst0_8[0:0] + attribute \src "libresoc.v:45321.3-45329.6" + wire $1\dp_INT_ra_logical0_3$next[0:0]$2474 + attribute \src "libresoc.v:39237.7-39237.34" + wire $1\dp_INT_ra_logical0_3[0:0] + attribute \src "libresoc.v:45378.3-45386.6" + wire $1\dp_INT_ra_mul0_6$next[0:0]$2492 + attribute \src "libresoc.v:39241.7-39241.30" + wire $1\dp_INT_ra_mul0_6[0:0] + attribute \src "libresoc.v:45397.3-45405.6" + wire $1\dp_INT_ra_shiftrot0_7$next[0:0]$2498 + attribute \src "libresoc.v:39245.7-39245.35" + wire $1\dp_INT_ra_shiftrot0_7[0:0] + attribute \src "libresoc.v:45340.3-45348.6" + wire $1\dp_INT_ra_spr0_4$next[0:0]$2480 + attribute \src "libresoc.v:39249.7-39249.30" + wire $1\dp_INT_ra_spr0_4[0:0] + attribute \src "libresoc.v:45302.3-45310.6" + wire $1\dp_INT_ra_trap0_2$next[0:0]$2468 + attribute \src "libresoc.v:39253.7-39253.31" + wire $1\dp_INT_ra_trap0_2[0:0] + attribute \src "libresoc.v:45435.3-45443.6" + wire $1\dp_INT_rb_alu0_0$next[0:0]$2510 + attribute \src "libresoc.v:39257.7-39257.30" + wire $1\dp_INT_rb_alu0_0[0:0] + attribute \src "libresoc.v:45454.3-45462.6" + wire $1\dp_INT_rb_cr0_1$next[0:0]$2514 + attribute \src "libresoc.v:39261.7-39261.29" + wire $1\dp_INT_rb_cr0_1[0:0] + attribute \src "libresoc.v:45511.3-45519.6" + wire $1\dp_INT_rb_div0_4$next[0:0]$2532 + attribute \src "libresoc.v:39265.7-39265.30" + wire $1\dp_INT_rb_div0_4[0:0] + attribute \src "libresoc.v:45568.3-45576.6" + wire $1\dp_INT_rb_ldst0_7$next[0:0]$2550 + attribute \src "libresoc.v:39269.7-39269.31" + wire $1\dp_INT_rb_ldst0_7[0:0] + attribute \src "libresoc.v:45492.3-45500.6" + wire $1\dp_INT_rb_logical0_3$next[0:0]$2526 + attribute \src "libresoc.v:39273.7-39273.34" + wire $1\dp_INT_rb_logical0_3[0:0] + attribute \src "libresoc.v:45530.3-45538.6" + wire $1\dp_INT_rb_mul0_5$next[0:0]$2538 + attribute \src "libresoc.v:39277.7-39277.30" + wire $1\dp_INT_rb_mul0_5[0:0] + attribute \src "libresoc.v:45549.3-45557.6" + wire $1\dp_INT_rb_shiftrot0_6$next[0:0]$2544 + attribute \src "libresoc.v:39281.7-39281.35" + wire $1\dp_INT_rb_shiftrot0_6[0:0] + attribute \src "libresoc.v:45473.3-45481.6" + wire $1\dp_INT_rb_trap0_2$next[0:0]$2520 + attribute \src "libresoc.v:39285.7-39285.31" + wire $1\dp_INT_rb_trap0_2[0:0] + attribute \src "libresoc.v:45606.3-45614.6" + wire $1\dp_INT_rc_ldst0_1$next[0:0]$2560 + attribute \src "libresoc.v:39289.7-39289.31" + wire $1\dp_INT_rc_ldst0_1[0:0] + attribute \src "libresoc.v:45587.3-45595.6" + wire $1\dp_INT_rc_shiftrot0_0$next[0:0]$2556 + attribute \src "libresoc.v:39293.7-39293.35" + wire $1\dp_INT_rc_shiftrot0_0[0:0] + attribute \src "libresoc.v:46379.3-46387.6" + wire $1\dp_SPR_spr1_spr0_0$next[0:0]$2700 + attribute \src "libresoc.v:39297.7-39297.32" + wire $1\dp_SPR_spr1_spr0_0[0:0] + attribute \src "libresoc.v:45907.3-45915.6" + wire $1\dp_XER_xer_ca_alu0_0$next[0:0]$2613 + attribute \src "libresoc.v:39301.7-39301.34" + wire $1\dp_XER_xer_ca_alu0_0[0:0] + attribute \src "libresoc.v:45974.3-45982.6" + wire $1\dp_XER_xer_ca_shiftrot0_2$next[0:0]$2624 + attribute \src "libresoc.v:39305.7-39305.39" + wire $1\dp_XER_xer_ca_shiftrot0_2[0:0] + attribute \src "libresoc.v:45955.3-45963.6" + wire $1\dp_XER_xer_ca_spr0_1$next[0:0]$2620 + attribute \src "libresoc.v:39309.7-39309.34" + wire $1\dp_XER_xer_ca_spr0_1[0:0] + attribute \src "libresoc.v:46023.3-46031.6" + wire $1\dp_XER_xer_ov_spr0_0$next[0:0]$2629 + attribute \src "libresoc.v:39313.7-39313.34" + wire $1\dp_XER_xer_ov_spr0_0[0:0] + attribute \src "libresoc.v:45652.3-45660.6" + wire $1\dp_XER_xer_so_alu0_0$next[0:0]$2572 + attribute \src "libresoc.v:39317.7-39317.34" + wire $1\dp_XER_xer_so_alu0_0[0:0] + attribute \src "libresoc.v:45821.3-45829.6" + wire $1\dp_XER_xer_so_div0_3$next[0:0]$2594 + attribute \src "libresoc.v:39321.7-39321.34" + wire $1\dp_XER_xer_so_div0_3[0:0] + attribute \src "libresoc.v:45762.3-45770.6" + wire $1\dp_XER_xer_so_logical0_1$next[0:0]$2579 + attribute \src "libresoc.v:39325.7-39325.38" + wire $1\dp_XER_xer_so_logical0_1[0:0] + attribute \src "libresoc.v:45840.3-45848.6" + wire $1\dp_XER_xer_so_mul0_4$next[0:0]$2600 + attribute \src "libresoc.v:39329.7-39329.34" + wire $1\dp_XER_xer_so_mul0_4[0:0] + attribute \src "libresoc.v:45888.3-45896.6" + wire $1\dp_XER_xer_so_shiftrot0_5$next[0:0]$2607 + attribute \src "libresoc.v:39333.7-39333.39" + wire $1\dp_XER_xer_so_shiftrot0_5[0:0] + attribute \src "libresoc.v:45781.3-45789.6" + wire $1\dp_XER_xer_so_spr0_2$next[0:0]$2585 + attribute \src "libresoc.v:39337.7-39337.34" + wire $1\dp_XER_xer_so_spr0_2[0:0] + attribute \src "libresoc.v:46899.3-46927.6" + wire $1\fus_cu_issue_i$13[0:0]$2769 + attribute \src "libresoc.v:47296.3-47324.6" + wire $1\fus_cu_issue_i$16[0:0]$2831 + attribute \src "libresoc.v:47660.3-47688.6" + wire $1\fus_cu_issue_i$19[0:0]$2865 + attribute \src "libresoc.v:48156.3-48184.6" + wire $1\fus_cu_issue_i$22[0:0]$2890 + attribute \src "libresoc.v:43483.3-43511.6" + wire $1\fus_cu_issue_i$25[0:0]$2357 + attribute \src "libresoc.v:43979.3-44007.6" + wire $1\fus_cu_issue_i$28[0:0]$2382 + attribute \src "libresoc.v:44301.3-44329.6" + wire $1\fus_cu_issue_i$31[0:0]$2401 + attribute \src "libresoc.v:44768.3-44796.6" + wire $1\fus_cu_issue_i$34[0:0]$2425 + attribute \src "libresoc.v:45206.3-45234.6" + wire $1\fus_cu_issue_i$37[0:0]$2448 + attribute \src "libresoc.v:46691.3-46719.6" + wire $1\fus_cu_issue_i[0:0] + attribute \src "libresoc.v:46937.3-46965.6" + wire width 6 $1\fus_cu_rdmaskn_i$15[5:0]$2777 + attribute \src "libresoc.v:47334.3-47362.6" + wire width 3 $1\fus_cu_rdmaskn_i$18[2:0]$2839 + attribute \src "libresoc.v:47689.3-47717.6" + wire width 4 $1\fus_cu_rdmaskn_i$21[3:0]$2870 + attribute \src "libresoc.v:48185.3-48213.6" + wire width 3 $1\fus_cu_rdmaskn_i$24[2:0]$2895 + attribute \src "libresoc.v:43512.3-43540.6" + wire width 6 $1\fus_cu_rdmaskn_i$27[5:0]$2362 + attribute \src "libresoc.v:44008.3-44036.6" + wire width 3 $1\fus_cu_rdmaskn_i$30[2:0]$2387 + attribute \src "libresoc.v:44330.3-44358.6" + wire width 3 $1\fus_cu_rdmaskn_i$33[2:0]$2406 + attribute \src "libresoc.v:44797.3-44825.6" + wire width 5 $1\fus_cu_rdmaskn_i$36[4:0]$2430 + attribute \src "libresoc.v:45235.3-45263.6" + wire width 3 $1\fus_cu_rdmaskn_i$39[2:0]$2453 + attribute \src "libresoc.v:46729.3-46757.6" + wire width 4 $1\fus_cu_rdmaskn_i[3:0] + attribute \src "libresoc.v:46606.3-46634.6" + wire width 4 $1\fus_oper_i_alu_alu0__data_len[3:0] + attribute \src "libresoc.v:45916.3-45944.6" + wire width 13 $1\fus_oper_i_alu_alu0__fn_unit[12:0] + attribute \src "libresoc.v:45983.3-46012.6" + wire width 64 $1\fus_oper_i_alu_alu0__imm_data__data[63:0] + attribute \src "libresoc.v:45983.3-46012.6" + wire $1\fus_oper_i_alu_alu0__imm_data__ok[0:0] + attribute \src "libresoc.v:46436.3-46464.6" + wire width 2 $1\fus_oper_i_alu_alu0__input_carry[1:0] + attribute \src "libresoc.v:46653.3-46681.6" + wire width 32 $1\fus_oper_i_alu_alu0__insn[31:0] + attribute \src "libresoc.v:45859.3-45887.6" + wire width 7 $1\fus_oper_i_alu_alu0__insn_type[6:0] + attribute \src "libresoc.v:46235.3-46263.6" + wire $1\fus_oper_i_alu_alu0__invert_in[0:0] + attribute \src "libresoc.v:46350.3-46378.6" + wire $1\fus_oper_i_alu_alu0__invert_out[0:0] + attribute \src "libresoc.v:46521.3-46549.6" + wire $1\fus_oper_i_alu_alu0__is_32bit[0:0] + attribute \src "libresoc.v:46568.3-46596.6" + wire $1\fus_oper_i_alu_alu0__is_signed[0:0] + attribute \src "libresoc.v:46148.3-46177.6" + wire $1\fus_oper_i_alu_alu0__oe__oe[0:0] + attribute \src "libresoc.v:46148.3-46177.6" + wire $1\fus_oper_i_alu_alu0__oe__ok[0:0] + attribute \src "libresoc.v:46483.3-46511.6" + wire $1\fus_oper_i_alu_alu0__output_carry[0:0] + attribute \src "libresoc.v:46061.3-46090.6" + wire $1\fus_oper_i_alu_alu0__rc__ok[0:0] + attribute \src "libresoc.v:46061.3-46090.6" + wire $1\fus_oper_i_alu_alu0__rc__rc[0:0] + attribute \src "libresoc.v:46398.3-46426.6" + wire $1\fus_oper_i_alu_alu0__write_cr0[0:0] + attribute \src "libresoc.v:46283.3-46311.6" + wire $1\fus_oper_i_alu_alu0__zero_a[0:0] + attribute \src "libresoc.v:46984.3-47012.6" + wire width 64 $1\fus_oper_i_alu_branch0__cia[63:0] + attribute \src "libresoc.v:47069.3-47097.6" + wire width 13 $1\fus_oper_i_alu_branch0__fn_unit[12:0] + attribute \src "libresoc.v:47154.3-47183.6" + wire width 64 $1\fus_oper_i_alu_branch0__imm_data__data[63:0] + attribute \src "libresoc.v:47154.3-47183.6" + wire $1\fus_oper_i_alu_branch0__imm_data__ok[0:0] + attribute \src "libresoc.v:47107.3-47135.6" + wire width 32 $1\fus_oper_i_alu_branch0__insn[31:0] + attribute \src "libresoc.v:47022.3-47050.6" + wire width 7 $1\fus_oper_i_alu_branch0__insn_type[6:0] + attribute \src "libresoc.v:47249.3-47277.6" + wire $1\fus_oper_i_alu_branch0__is_32bit[0:0] + attribute \src "libresoc.v:47211.3-47239.6" + wire $1\fus_oper_i_alu_branch0__lk[0:0] + attribute \src "libresoc.v:46814.3-46842.6" + wire width 13 $1\fus_oper_i_alu_cr0__fn_unit[12:0] + attribute \src "libresoc.v:46861.3-46889.6" + wire width 32 $1\fus_oper_i_alu_cr0__insn[31:0] + attribute \src "libresoc.v:46767.3-46795.6" + wire width 7 $1\fus_oper_i_alu_cr0__insn_type[6:0] + attribute \src "libresoc.v:43921.3-43949.6" + wire width 4 $1\fus_oper_i_alu_div0__data_len[3:0] + attribute \src "libresoc.v:43570.3-43598.6" + wire width 13 $1\fus_oper_i_alu_div0__fn_unit[12:0] + attribute \src "libresoc.v:43599.3-43628.6" + wire width 64 $1\fus_oper_i_alu_div0__imm_data__data[63:0] + attribute \src "libresoc.v:43599.3-43628.6" + wire $1\fus_oper_i_alu_div0__imm_data__ok[0:0] + attribute \src "libresoc.v:43747.3-43775.6" + wire width 2 $1\fus_oper_i_alu_div0__input_carry[1:0] + attribute \src "libresoc.v:43950.3-43978.6" + wire width 32 $1\fus_oper_i_alu_div0__insn[31:0] + attribute \src "libresoc.v:43541.3-43569.6" + wire width 7 $1\fus_oper_i_alu_div0__insn_type[6:0] + attribute \src "libresoc.v:43689.3-43717.6" + wire $1\fus_oper_i_alu_div0__invert_in[0:0] + attribute \src "libresoc.v:43776.3-43804.6" + wire $1\fus_oper_i_alu_div0__invert_out[0:0] + attribute \src "libresoc.v:43863.3-43891.6" + wire $1\fus_oper_i_alu_div0__is_32bit[0:0] + attribute \src "libresoc.v:43892.3-43920.6" + wire $1\fus_oper_i_alu_div0__is_signed[0:0] + attribute \src "libresoc.v:43659.3-43688.6" + wire $1\fus_oper_i_alu_div0__oe__oe[0:0] + attribute \src "libresoc.v:43659.3-43688.6" + wire $1\fus_oper_i_alu_div0__oe__ok[0:0] + attribute \src "libresoc.v:43834.3-43862.6" + wire $1\fus_oper_i_alu_div0__output_carry[0:0] + attribute \src "libresoc.v:43629.3-43658.6" + wire $1\fus_oper_i_alu_div0__rc__ok[0:0] + attribute \src "libresoc.v:43629.3-43658.6" + wire $1\fus_oper_i_alu_div0__rc__rc[0:0] + attribute \src "libresoc.v:43805.3-43833.6" + wire $1\fus_oper_i_alu_div0__write_cr0[0:0] + attribute \src "libresoc.v:43718.3-43746.6" + wire $1\fus_oper_i_alu_div0__zero_a[0:0] + attribute \src "libresoc.v:48098.3-48126.6" + wire width 4 $1\fus_oper_i_alu_logical0__data_len[3:0] + attribute \src "libresoc.v:47747.3-47775.6" + wire width 13 $1\fus_oper_i_alu_logical0__fn_unit[12:0] + attribute \src "libresoc.v:47776.3-47805.6" + wire width 64 $1\fus_oper_i_alu_logical0__imm_data__data[63:0] + attribute \src "libresoc.v:47776.3-47805.6" + wire $1\fus_oper_i_alu_logical0__imm_data__ok[0:0] + attribute \src "libresoc.v:47924.3-47952.6" + wire width 2 $1\fus_oper_i_alu_logical0__input_carry[1:0] + attribute \src "libresoc.v:48127.3-48155.6" + wire width 32 $1\fus_oper_i_alu_logical0__insn[31:0] + attribute \src "libresoc.v:47718.3-47746.6" + wire width 7 $1\fus_oper_i_alu_logical0__insn_type[6:0] + attribute \src "libresoc.v:47866.3-47894.6" + wire $1\fus_oper_i_alu_logical0__invert_in[0:0] + attribute \src "libresoc.v:47953.3-47981.6" + wire $1\fus_oper_i_alu_logical0__invert_out[0:0] + attribute \src "libresoc.v:48040.3-48068.6" + wire $1\fus_oper_i_alu_logical0__is_32bit[0:0] + attribute \src "libresoc.v:48069.3-48097.6" + wire $1\fus_oper_i_alu_logical0__is_signed[0:0] + attribute \src "libresoc.v:47836.3-47865.6" + wire $1\fus_oper_i_alu_logical0__oe__oe[0:0] + attribute \src "libresoc.v:47836.3-47865.6" + wire $1\fus_oper_i_alu_logical0__oe__ok[0:0] + attribute \src "libresoc.v:48011.3-48039.6" + wire $1\fus_oper_i_alu_logical0__output_carry[0:0] + attribute \src "libresoc.v:47806.3-47835.6" + wire $1\fus_oper_i_alu_logical0__rc__ok[0:0] + attribute \src "libresoc.v:47806.3-47835.6" + wire $1\fus_oper_i_alu_logical0__rc__rc[0:0] + attribute \src "libresoc.v:47982.3-48010.6" + wire $1\fus_oper_i_alu_logical0__write_cr0[0:0] + attribute \src "libresoc.v:47895.3-47923.6" + wire $1\fus_oper_i_alu_logical0__zero_a[0:0] + attribute \src "libresoc.v:44066.3-44094.6" + wire width 13 $1\fus_oper_i_alu_mul0__fn_unit[12:0] + attribute \src "libresoc.v:44095.3-44124.6" + wire width 64 $1\fus_oper_i_alu_mul0__imm_data__data[63:0] + attribute \src "libresoc.v:44095.3-44124.6" + wire $1\fus_oper_i_alu_mul0__imm_data__ok[0:0] + attribute \src "libresoc.v:44272.3-44300.6" + wire width 32 $1\fus_oper_i_alu_mul0__insn[31:0] + attribute \src "libresoc.v:44037.3-44065.6" + wire width 7 $1\fus_oper_i_alu_mul0__insn_type[6:0] + attribute \src "libresoc.v:44214.3-44242.6" + wire $1\fus_oper_i_alu_mul0__is_32bit[0:0] + attribute \src "libresoc.v:44243.3-44271.6" + wire $1\fus_oper_i_alu_mul0__is_signed[0:0] + attribute \src "libresoc.v:44155.3-44184.6" + wire $1\fus_oper_i_alu_mul0__oe__oe[0:0] + attribute \src "libresoc.v:44155.3-44184.6" + wire $1\fus_oper_i_alu_mul0__oe__ok[0:0] + attribute \src "libresoc.v:44125.3-44154.6" + wire $1\fus_oper_i_alu_mul0__rc__ok[0:0] + attribute \src "libresoc.v:44125.3-44154.6" + wire $1\fus_oper_i_alu_mul0__rc__rc[0:0] + attribute \src "libresoc.v:44185.3-44213.6" + wire $1\fus_oper_i_alu_mul0__write_cr0[0:0] + attribute \src "libresoc.v:44388.3-44416.6" + wire width 13 $1\fus_oper_i_alu_shift_rot0__fn_unit[12:0] + attribute \src "libresoc.v:44417.3-44446.6" + wire width 64 $1\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] + attribute \src "libresoc.v:44417.3-44446.6" + wire $1\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] + attribute \src "libresoc.v:44565.3-44593.6" + wire width 2 $1\fus_oper_i_alu_shift_rot0__input_carry[1:0] + attribute \src "libresoc.v:44623.3-44651.6" + wire $1\fus_oper_i_alu_shift_rot0__input_cr[0:0] + attribute \src "libresoc.v:44739.3-44767.6" + wire width 32 $1\fus_oper_i_alu_shift_rot0__insn[31:0] + attribute \src "libresoc.v:44359.3-44387.6" + wire width 7 $1\fus_oper_i_alu_shift_rot0__insn_type[6:0] + attribute \src "libresoc.v:44536.3-44564.6" + wire $1\fus_oper_i_alu_shift_rot0__invert_in[0:0] + attribute \src "libresoc.v:44681.3-44709.6" + wire $1\fus_oper_i_alu_shift_rot0__is_32bit[0:0] + attribute \src "libresoc.v:44710.3-44738.6" + wire $1\fus_oper_i_alu_shift_rot0__is_signed[0:0] + attribute \src "libresoc.v:44477.3-44506.6" + wire $1\fus_oper_i_alu_shift_rot0__oe__oe[0:0] + attribute \src "libresoc.v:44477.3-44506.6" + wire $1\fus_oper_i_alu_shift_rot0__oe__ok[0:0] + attribute \src "libresoc.v:44594.3-44622.6" + wire $1\fus_oper_i_alu_shift_rot0__output_carry[0:0] + attribute \src "libresoc.v:44652.3-44680.6" + wire $1\fus_oper_i_alu_shift_rot0__output_cr[0:0] + attribute \src "libresoc.v:44447.3-44476.6" + wire $1\fus_oper_i_alu_shift_rot0__rc__ok[0:0] + attribute \src "libresoc.v:44447.3-44476.6" + wire $1\fus_oper_i_alu_shift_rot0__rc__rc[0:0] + attribute \src "libresoc.v:44507.3-44535.6" + wire $1\fus_oper_i_alu_shift_rot0__write_cr0[0:0] + attribute \src "libresoc.v:48243.3-48271.6" + wire width 13 $1\fus_oper_i_alu_spr0__fn_unit[12:0] + attribute \src "libresoc.v:43425.3-43453.6" + wire width 32 $1\fus_oper_i_alu_spr0__insn[31:0] + attribute \src "libresoc.v:48214.3-48242.6" + wire width 7 $1\fus_oper_i_alu_spr0__insn_type[6:0] + attribute \src "libresoc.v:43454.3-43482.6" + wire $1\fus_oper_i_alu_spr0__is_32bit[0:0] + attribute \src "libresoc.v:47515.3-47543.6" + wire width 64 $1\fus_oper_i_alu_trap0__cia[63:0] + attribute \src "libresoc.v:47419.3-47447.6" + wire width 13 $1\fus_oper_i_alu_trap0__fn_unit[12:0] + attribute \src "libresoc.v:47457.3-47485.6" + wire width 32 $1\fus_oper_i_alu_trap0__insn[31:0] + attribute \src "libresoc.v:47372.3-47400.6" + wire width 7 $1\fus_oper_i_alu_trap0__insn_type[6:0] + attribute \src "libresoc.v:47544.3-47572.6" + wire $1\fus_oper_i_alu_trap0__is_32bit[0:0] + attribute \src "libresoc.v:47631.3-47659.6" + wire width 8 $1\fus_oper_i_alu_trap0__ldst_exc[7:0] + attribute \src "libresoc.v:47486.3-47514.6" + wire width 64 $1\fus_oper_i_alu_trap0__msr[63:0] + attribute \src "libresoc.v:47602.3-47630.6" + wire width 13 $1\fus_oper_i_alu_trap0__trapaddr[12:0] + attribute \src "libresoc.v:47573.3-47601.6" + wire width 8 $1\fus_oper_i_alu_trap0__traptype[7:0] + attribute \src "libresoc.v:45090.3-45118.6" + wire $1\fus_oper_i_ldst_ldst0__byte_reverse[0:0] + attribute \src "libresoc.v:45061.3-45089.6" + wire width 4 $1\fus_oper_i_ldst_ldst0__data_len[3:0] + attribute \src "libresoc.v:44855.3-44883.6" + wire width 13 $1\fus_oper_i_ldst_ldst0__fn_unit[12:0] + attribute \src "libresoc.v:44884.3-44913.6" + wire width 64 $1\fus_oper_i_ldst_ldst0__imm_data__data[63:0] + attribute \src "libresoc.v:44884.3-44913.6" + wire $1\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] + attribute \src "libresoc.v:45177.3-45205.6" + wire width 32 $1\fus_oper_i_ldst_ldst0__insn[31:0] + attribute \src "libresoc.v:44826.3-44854.6" + wire width 7 $1\fus_oper_i_ldst_ldst0__insn_type[6:0] + attribute \src "libresoc.v:45003.3-45031.6" + wire $1\fus_oper_i_ldst_ldst0__is_32bit[0:0] + attribute \src "libresoc.v:45032.3-45060.6" + wire $1\fus_oper_i_ldst_ldst0__is_signed[0:0] + attribute \src "libresoc.v:45148.3-45176.6" + wire width 2 $1\fus_oper_i_ldst_ldst0__ldst_mode[1:0] + attribute \src "libresoc.v:44973.3-45002.6" + wire $1\fus_oper_i_ldst_ldst0__oe__oe[0:0] + attribute \src "libresoc.v:44973.3-45002.6" + wire $1\fus_oper_i_ldst_ldst0__oe__ok[0:0] + attribute \src "libresoc.v:44943.3-44972.6" + wire $1\fus_oper_i_ldst_ldst0__rc__ok[0:0] + attribute \src "libresoc.v:44943.3-44972.6" + wire $1\fus_oper_i_ldst_ldst0__rc__rc[0:0] + attribute \src "libresoc.v:45119.3-45147.6" + wire $1\fus_oper_i_ldst_ldst0__sign_extend[0:0] + attribute \src "libresoc.v:44914.3-44942.6" + wire $1\fus_oper_i_ldst_ldst0__zero_a[0:0] + attribute \src "libresoc.v:45292.3-45301.6" + wire width 64 $1\fus_src1_i$42[63:0]$2465 + attribute \src "libresoc.v:45311.3-45320.6" + wire width 64 $1\fus_src1_i$45[63:0]$2471 + attribute \src "libresoc.v:45330.3-45339.6" + wire width 64 $1\fus_src1_i$48[63:0]$2477 + attribute \src "libresoc.v:45349.3-45358.6" + wire width 64 $1\fus_src1_i$51[63:0]$2483 + attribute \src "libresoc.v:45368.3-45377.6" + wire width 64 $1\fus_src1_i$54[63:0]$2489 + attribute \src "libresoc.v:45387.3-45396.6" + wire width 64 $1\fus_src1_i$57[63:0]$2495 + attribute \src "libresoc.v:45406.3-45415.6" + wire width 64 $1\fus_src1_i$60[63:0]$2501 + attribute \src "libresoc.v:45425.3-45434.6" + wire width 64 $1\fus_src1_i$63[63:0]$2507 + attribute \src "libresoc.v:46206.3-46215.6" + wire width 64 $1\fus_src1_i$86[63:0]$2670 + attribute \src "libresoc.v:45273.3-45282.6" + wire width 64 $1\fus_src1_i[63:0] + attribute \src "libresoc.v:45463.3-45472.6" + wire width 64 $1\fus_src2_i$64[63:0]$2517 + attribute \src "libresoc.v:45482.3-45491.6" + wire width 64 $1\fus_src2_i$65[63:0]$2523 + attribute \src "libresoc.v:45501.3-45510.6" + wire width 64 $1\fus_src2_i$66[63:0]$2529 + attribute \src "libresoc.v:45520.3-45529.6" + wire width 64 $1\fus_src2_i$67[63:0]$2535 + attribute \src "libresoc.v:45539.3-45548.6" + wire width 64 $1\fus_src2_i$68[63:0]$2541 + attribute \src "libresoc.v:45558.3-45567.6" + wire width 64 $1\fus_src2_i$69[63:0]$2547 + attribute \src "libresoc.v:45577.3-45586.6" + wire width 64 $1\fus_src2_i$70[63:0]$2553 + attribute \src "libresoc.v:46321.3-46330.6" + wire width 64 $1\fus_src2_i$89[63:0]$2690 + attribute \src "libresoc.v:46388.3-46397.6" + wire width 64 $1\fus_src2_i$91[63:0]$2703 + attribute \src "libresoc.v:45444.3-45453.6" + wire width 64 $1\fus_src2_i[63:0] + attribute \src "libresoc.v:45615.3-45624.6" + wire width 64 $1\fus_src3_i$71[63:0]$2563 + attribute \src "libresoc.v:45661.3-45670.6" + wire $1\fus_src3_i$72[0:0]$2575 + attribute \src "libresoc.v:45771.3-45780.6" + wire $1\fus_src3_i$73[0:0]$2582 + attribute \src "libresoc.v:45830.3-45839.6" + wire $1\fus_src3_i$74[0:0]$2597 + attribute \src "libresoc.v:45849.3-45858.6" + wire $1\fus_src3_i$75[0:0]$2603 + attribute \src "libresoc.v:46051.3-46060.6" + wire width 32 $1\fus_src3_i$79[31:0]$2638 + attribute \src "libresoc.v:46119.3-46128.6" + wire width 4 $1\fus_src3_i$83[3:0]$2651 + attribute \src "libresoc.v:46225.3-46234.6" + wire width 64 $1\fus_src3_i$87[63:0]$2676 + attribute \src "libresoc.v:46273.3-46282.6" + wire width 64 $1\fus_src3_i$88[63:0]$2683 + attribute \src "libresoc.v:45596.3-45605.6" + wire width 64 $1\fus_src3_i[63:0] + attribute \src "libresoc.v:45897.3-45906.6" + wire $1\fus_src4_i$76[0:0]$2610 + attribute \src "libresoc.v:45945.3-45954.6" + wire width 2 $1\fus_src4_i$77[1:0]$2617 + attribute \src "libresoc.v:46100.3-46109.6" + wire width 4 $1\fus_src4_i$80[3:0]$2645 + attribute \src "libresoc.v:46340.3-46349.6" + wire width 64 $1\fus_src4_i$90[63:0]$2696 + attribute \src "libresoc.v:45790.3-45799.6" + wire $1\fus_src4_i[0:0] + attribute \src "libresoc.v:46032.3-46041.6" + wire width 2 $1\fus_src5_i$78[1:0]$2632 + attribute \src "libresoc.v:46138.3-46147.6" + wire width 4 $1\fus_src5_i$84[3:0]$2657 + attribute \src "libresoc.v:46013.3-46022.6" + wire width 2 $1\fus_src5_i[1:0] + attribute \src "libresoc.v:46187.3-46196.6" + wire width 4 $1\fus_src6_i$85[3:0]$2664 + attribute \src "libresoc.v:45964.3-45973.6" + wire width 2 $1\fus_src6_i[1:0] + attribute \src "libresoc.v:46474.3-46482.6" + wire $1\wr_pick_dly$1005$next[0:0]$2714 + attribute \src "libresoc.v:46512.3-46520.6" + wire $1\wr_pick_dly$1026$next[0:0]$2718 + attribute \src "libresoc.v:46550.3-46558.6" + wire $1\wr_pick_dly$1044$next[0:0]$2722 + attribute \src "libresoc.v:46559.3-46567.6" + wire $1\wr_pick_dly$1066$next[0:0]$2725 + attribute \src "libresoc.v:46597.3-46605.6" + wire $1\wr_pick_dly$1086$next[0:0]$2729 + attribute \src "libresoc.v:46635.3-46643.6" + wire $1\wr_pick_dly$1106$next[0:0]$2733 + attribute \src "libresoc.v:46644.3-46652.6" + wire $1\wr_pick_dly$1125$next[0:0]$2736 + attribute \src "libresoc.v:46682.3-46690.6" + wire $1\wr_pick_dly$1143$next[0:0]$2740 + attribute \src "libresoc.v:46720.3-46728.6" + wire $1\wr_pick_dly$1217$next[0:0]$2744 + attribute \src "libresoc.v:46758.3-46766.6" + wire $1\wr_pick_dly$1245$next[0:0]$2748 + attribute \src "libresoc.v:46796.3-46804.6" + wire $1\wr_pick_dly$1265$next[0:0]$2752 + attribute \src "libresoc.v:46805.3-46813.6" + wire $1\wr_pick_dly$1285$next[0:0]$2755 + attribute \src "libresoc.v:46843.3-46851.6" + wire $1\wr_pick_dly$1305$next[0:0]$2759 + attribute \src "libresoc.v:46852.3-46860.6" + wire $1\wr_pick_dly$1325$next[0:0]$2762 + attribute \src "libresoc.v:46890.3-46898.6" + wire $1\wr_pick_dly$1345$next[0:0]$2766 + attribute \src "libresoc.v:46928.3-46936.6" + wire $1\wr_pick_dly$1392$next[0:0]$2774 + attribute \src "libresoc.v:46966.3-46974.6" + wire $1\wr_pick_dly$1408$next[0:0]$2782 + attribute \src "libresoc.v:46975.3-46983.6" + wire $1\wr_pick_dly$1424$next[0:0]$2785 + attribute \src "libresoc.v:47013.3-47021.6" + wire $1\wr_pick_dly$1458$next[0:0]$2789 + attribute \src "libresoc.v:47051.3-47059.6" + wire $1\wr_pick_dly$1474$next[0:0]$2793 + attribute \src "libresoc.v:47060.3-47068.6" + wire $1\wr_pick_dly$1490$next[0:0]$2796 + attribute \src "libresoc.v:47098.3-47106.6" + wire $1\wr_pick_dly$1506$next[0:0]$2800 + attribute \src "libresoc.v:47136.3-47144.6" + wire $1\wr_pick_dly$1542$next[0:0]$2804 + attribute \src "libresoc.v:47145.3-47153.6" + wire $1\wr_pick_dly$1558$next[0:0]$2807 + attribute \src "libresoc.v:47184.3-47192.6" + wire $1\wr_pick_dly$1574$next[0:0]$2811 + attribute \src "libresoc.v:47193.3-47201.6" + wire $1\wr_pick_dly$1590$next[0:0]$2814 + attribute \src "libresoc.v:47202.3-47210.6" + wire $1\wr_pick_dly$1632$next[0:0]$2817 + attribute \src "libresoc.v:47240.3-47248.6" + wire $1\wr_pick_dly$1651$next[0:0]$2821 + attribute \src "libresoc.v:47278.3-47286.6" + wire $1\wr_pick_dly$1667$next[0:0]$2825 + attribute \src "libresoc.v:47287.3-47295.6" + wire $1\wr_pick_dly$1683$next[0:0]$2828 + attribute \src "libresoc.v:47325.3-47333.6" + wire $1\wr_pick_dly$1699$next[0:0]$2836 + attribute \src "libresoc.v:47363.3-47371.6" + wire $1\wr_pick_dly$1743$next[0:0]$2844 + attribute \src "libresoc.v:47401.3-47409.6" + wire $1\wr_pick_dly$1759$next[0:0]$2848 + attribute \src "libresoc.v:47410.3-47418.6" + wire $1\wr_pick_dly$1783$next[0:0]$2851 + attribute \src "libresoc.v:47448.3-47456.6" + wire $1\wr_pick_dly$1803$next[0:0]$2855 + attribute \src "libresoc.v:46465.3-46473.6" + wire $1\wr_pick_dly$986$next[0:0]$2711 + attribute \src "libresoc.v:46427.3-46435.6" + wire $1\wr_pick_dly$next[0:0]$2707 + attribute \src "libresoc.v:41430.7-41430.25" + wire $1\wr_pick_dly[0:0] + attribute \src "libresoc.v:45800.3-45820.6" + wire $2\core_terminate_o$next[0:0]$2590 + attribute \src "libresoc.v:45671.3-45761.6" + wire $2\corebusy_o[0:0] + attribute \src "libresoc.v:45625.3-45651.6" + wire width 2 $2\counter$next[1:0]$2567 + attribute \src "libresoc.v:46899.3-46927.6" + wire $2\fus_cu_issue_i$13[0:0]$2770 + attribute \src "libresoc.v:47296.3-47324.6" + wire $2\fus_cu_issue_i$16[0:0]$2832 + attribute \src "libresoc.v:47660.3-47688.6" + wire $2\fus_cu_issue_i$19[0:0]$2866 + attribute \src "libresoc.v:48156.3-48184.6" + wire $2\fus_cu_issue_i$22[0:0]$2891 + attribute \src "libresoc.v:43483.3-43511.6" + wire $2\fus_cu_issue_i$25[0:0]$2358 + attribute \src "libresoc.v:43979.3-44007.6" + wire $2\fus_cu_issue_i$28[0:0]$2383 + attribute \src "libresoc.v:44301.3-44329.6" + wire $2\fus_cu_issue_i$31[0:0]$2402 + attribute \src "libresoc.v:44768.3-44796.6" + wire $2\fus_cu_issue_i$34[0:0]$2426 + attribute \src "libresoc.v:45206.3-45234.6" + wire $2\fus_cu_issue_i$37[0:0]$2449 + attribute \src "libresoc.v:46691.3-46719.6" + wire $2\fus_cu_issue_i[0:0] + attribute \src "libresoc.v:46937.3-46965.6" + wire width 6 $2\fus_cu_rdmaskn_i$15[5:0]$2778 + attribute \src "libresoc.v:47334.3-47362.6" + wire width 3 $2\fus_cu_rdmaskn_i$18[2:0]$2840 + attribute \src "libresoc.v:47689.3-47717.6" + wire width 4 $2\fus_cu_rdmaskn_i$21[3:0]$2871 + attribute \src "libresoc.v:48185.3-48213.6" + wire width 3 $2\fus_cu_rdmaskn_i$24[2:0]$2896 + attribute \src "libresoc.v:43512.3-43540.6" + wire width 6 $2\fus_cu_rdmaskn_i$27[5:0]$2363 + attribute \src "libresoc.v:44008.3-44036.6" + wire width 3 $2\fus_cu_rdmaskn_i$30[2:0]$2388 + attribute \src "libresoc.v:44330.3-44358.6" + wire width 3 $2\fus_cu_rdmaskn_i$33[2:0]$2407 + attribute \src "libresoc.v:44797.3-44825.6" + wire width 5 $2\fus_cu_rdmaskn_i$36[4:0]$2431 + attribute \src "libresoc.v:45235.3-45263.6" + wire width 3 $2\fus_cu_rdmaskn_i$39[2:0]$2454 + attribute \src "libresoc.v:46729.3-46757.6" + wire width 4 $2\fus_cu_rdmaskn_i[3:0] + attribute \src "libresoc.v:46606.3-46634.6" + wire width 4 $2\fus_oper_i_alu_alu0__data_len[3:0] + attribute \src "libresoc.v:45916.3-45944.6" + wire width 13 $2\fus_oper_i_alu_alu0__fn_unit[12:0] + attribute \src "libresoc.v:45983.3-46012.6" + wire width 64 $2\fus_oper_i_alu_alu0__imm_data__data[63:0] + attribute \src "libresoc.v:45983.3-46012.6" + wire $2\fus_oper_i_alu_alu0__imm_data__ok[0:0] + attribute \src "libresoc.v:46436.3-46464.6" + wire width 2 $2\fus_oper_i_alu_alu0__input_carry[1:0] + attribute \src "libresoc.v:46653.3-46681.6" + wire width 32 $2\fus_oper_i_alu_alu0__insn[31:0] + attribute \src "libresoc.v:45859.3-45887.6" + wire width 7 $2\fus_oper_i_alu_alu0__insn_type[6:0] + attribute \src "libresoc.v:46235.3-46263.6" + wire $2\fus_oper_i_alu_alu0__invert_in[0:0] + attribute \src "libresoc.v:46350.3-46378.6" + wire $2\fus_oper_i_alu_alu0__invert_out[0:0] + attribute \src "libresoc.v:46521.3-46549.6" + wire $2\fus_oper_i_alu_alu0__is_32bit[0:0] + attribute \src "libresoc.v:46568.3-46596.6" + wire $2\fus_oper_i_alu_alu0__is_signed[0:0] + attribute \src "libresoc.v:46148.3-46177.6" + wire $2\fus_oper_i_alu_alu0__oe__oe[0:0] + attribute \src "libresoc.v:46148.3-46177.6" + wire $2\fus_oper_i_alu_alu0__oe__ok[0:0] + attribute \src "libresoc.v:46483.3-46511.6" + wire $2\fus_oper_i_alu_alu0__output_carry[0:0] + attribute \src "libresoc.v:46061.3-46090.6" + wire $2\fus_oper_i_alu_alu0__rc__ok[0:0] + attribute \src "libresoc.v:46061.3-46090.6" + wire $2\fus_oper_i_alu_alu0__rc__rc[0:0] + attribute \src "libresoc.v:46398.3-46426.6" + wire $2\fus_oper_i_alu_alu0__write_cr0[0:0] + attribute \src "libresoc.v:46283.3-46311.6" + wire $2\fus_oper_i_alu_alu0__zero_a[0:0] + attribute \src "libresoc.v:46984.3-47012.6" + wire width 64 $2\fus_oper_i_alu_branch0__cia[63:0] + attribute \src "libresoc.v:47069.3-47097.6" + wire width 13 $2\fus_oper_i_alu_branch0__fn_unit[12:0] + attribute \src "libresoc.v:47154.3-47183.6" + wire width 64 $2\fus_oper_i_alu_branch0__imm_data__data[63:0] + attribute \src "libresoc.v:47154.3-47183.6" + wire $2\fus_oper_i_alu_branch0__imm_data__ok[0:0] + attribute \src "libresoc.v:47107.3-47135.6" + wire width 32 $2\fus_oper_i_alu_branch0__insn[31:0] + attribute \src "libresoc.v:47022.3-47050.6" + wire width 7 $2\fus_oper_i_alu_branch0__insn_type[6:0] + attribute \src "libresoc.v:47249.3-47277.6" + wire $2\fus_oper_i_alu_branch0__is_32bit[0:0] + attribute \src "libresoc.v:47211.3-47239.6" + wire $2\fus_oper_i_alu_branch0__lk[0:0] + attribute \src "libresoc.v:46814.3-46842.6" + wire width 13 $2\fus_oper_i_alu_cr0__fn_unit[12:0] + attribute \src "libresoc.v:46861.3-46889.6" + wire width 32 $2\fus_oper_i_alu_cr0__insn[31:0] + attribute \src "libresoc.v:46767.3-46795.6" + wire width 7 $2\fus_oper_i_alu_cr0__insn_type[6:0] + attribute \src "libresoc.v:43921.3-43949.6" + wire width 4 $2\fus_oper_i_alu_div0__data_len[3:0] + attribute \src "libresoc.v:43570.3-43598.6" + wire width 13 $2\fus_oper_i_alu_div0__fn_unit[12:0] + attribute \src "libresoc.v:43599.3-43628.6" + wire width 64 $2\fus_oper_i_alu_div0__imm_data__data[63:0] + attribute \src "libresoc.v:43599.3-43628.6" + wire $2\fus_oper_i_alu_div0__imm_data__ok[0:0] + attribute \src "libresoc.v:43747.3-43775.6" + wire width 2 $2\fus_oper_i_alu_div0__input_carry[1:0] + attribute \src "libresoc.v:43950.3-43978.6" + wire width 32 $2\fus_oper_i_alu_div0__insn[31:0] + attribute \src "libresoc.v:43541.3-43569.6" + wire width 7 $2\fus_oper_i_alu_div0__insn_type[6:0] + attribute \src "libresoc.v:43689.3-43717.6" + wire $2\fus_oper_i_alu_div0__invert_in[0:0] + attribute \src "libresoc.v:43776.3-43804.6" + wire $2\fus_oper_i_alu_div0__invert_out[0:0] + attribute \src "libresoc.v:43863.3-43891.6" + wire $2\fus_oper_i_alu_div0__is_32bit[0:0] + attribute \src "libresoc.v:43892.3-43920.6" + wire $2\fus_oper_i_alu_div0__is_signed[0:0] + attribute \src "libresoc.v:43659.3-43688.6" + wire $2\fus_oper_i_alu_div0__oe__oe[0:0] + attribute \src "libresoc.v:43659.3-43688.6" + wire $2\fus_oper_i_alu_div0__oe__ok[0:0] + attribute \src "libresoc.v:43834.3-43862.6" + wire $2\fus_oper_i_alu_div0__output_carry[0:0] + attribute \src "libresoc.v:43629.3-43658.6" + wire $2\fus_oper_i_alu_div0__rc__ok[0:0] + attribute \src "libresoc.v:43629.3-43658.6" + wire $2\fus_oper_i_alu_div0__rc__rc[0:0] + attribute \src "libresoc.v:43805.3-43833.6" + wire $2\fus_oper_i_alu_div0__write_cr0[0:0] + attribute \src "libresoc.v:43718.3-43746.6" + wire $2\fus_oper_i_alu_div0__zero_a[0:0] + attribute \src "libresoc.v:48098.3-48126.6" + wire width 4 $2\fus_oper_i_alu_logical0__data_len[3:0] + attribute \src "libresoc.v:47747.3-47775.6" + wire width 13 $2\fus_oper_i_alu_logical0__fn_unit[12:0] + attribute \src "libresoc.v:47776.3-47805.6" + wire width 64 $2\fus_oper_i_alu_logical0__imm_data__data[63:0] + attribute \src "libresoc.v:47776.3-47805.6" + wire $2\fus_oper_i_alu_logical0__imm_data__ok[0:0] + attribute \src "libresoc.v:47924.3-47952.6" + wire width 2 $2\fus_oper_i_alu_logical0__input_carry[1:0] + attribute \src "libresoc.v:48127.3-48155.6" + wire width 32 $2\fus_oper_i_alu_logical0__insn[31:0] + attribute \src "libresoc.v:47718.3-47746.6" + wire width 7 $2\fus_oper_i_alu_logical0__insn_type[6:0] + attribute \src "libresoc.v:47866.3-47894.6" + wire $2\fus_oper_i_alu_logical0__invert_in[0:0] + attribute \src "libresoc.v:47953.3-47981.6" + wire $2\fus_oper_i_alu_logical0__invert_out[0:0] + attribute \src "libresoc.v:48040.3-48068.6" + wire $2\fus_oper_i_alu_logical0__is_32bit[0:0] + attribute \src "libresoc.v:48069.3-48097.6" + wire $2\fus_oper_i_alu_logical0__is_signed[0:0] + attribute \src "libresoc.v:47836.3-47865.6" + wire $2\fus_oper_i_alu_logical0__oe__oe[0:0] + attribute \src "libresoc.v:47836.3-47865.6" + wire $2\fus_oper_i_alu_logical0__oe__ok[0:0] + attribute \src "libresoc.v:48011.3-48039.6" + wire $2\fus_oper_i_alu_logical0__output_carry[0:0] + attribute \src "libresoc.v:47806.3-47835.6" + wire $2\fus_oper_i_alu_logical0__rc__ok[0:0] + attribute \src "libresoc.v:47806.3-47835.6" + wire $2\fus_oper_i_alu_logical0__rc__rc[0:0] + attribute \src "libresoc.v:47982.3-48010.6" + wire $2\fus_oper_i_alu_logical0__write_cr0[0:0] + attribute \src "libresoc.v:47895.3-47923.6" + wire $2\fus_oper_i_alu_logical0__zero_a[0:0] + attribute \src "libresoc.v:44066.3-44094.6" + wire width 13 $2\fus_oper_i_alu_mul0__fn_unit[12:0] + attribute \src "libresoc.v:44095.3-44124.6" + wire width 64 $2\fus_oper_i_alu_mul0__imm_data__data[63:0] + attribute \src "libresoc.v:44095.3-44124.6" + wire $2\fus_oper_i_alu_mul0__imm_data__ok[0:0] + attribute \src "libresoc.v:44272.3-44300.6" + wire width 32 $2\fus_oper_i_alu_mul0__insn[31:0] + attribute \src "libresoc.v:44037.3-44065.6" + wire width 7 $2\fus_oper_i_alu_mul0__insn_type[6:0] + attribute \src "libresoc.v:44214.3-44242.6" + wire $2\fus_oper_i_alu_mul0__is_32bit[0:0] + attribute \src "libresoc.v:44243.3-44271.6" + wire $2\fus_oper_i_alu_mul0__is_signed[0:0] + attribute \src "libresoc.v:44155.3-44184.6" + wire $2\fus_oper_i_alu_mul0__oe__oe[0:0] + attribute \src "libresoc.v:44155.3-44184.6" + wire $2\fus_oper_i_alu_mul0__oe__ok[0:0] + attribute \src "libresoc.v:44125.3-44154.6" + wire $2\fus_oper_i_alu_mul0__rc__ok[0:0] + attribute \src "libresoc.v:44125.3-44154.6" + wire $2\fus_oper_i_alu_mul0__rc__rc[0:0] + attribute \src "libresoc.v:44185.3-44213.6" + wire $2\fus_oper_i_alu_mul0__write_cr0[0:0] + attribute \src "libresoc.v:44388.3-44416.6" + wire width 13 $2\fus_oper_i_alu_shift_rot0__fn_unit[12:0] + attribute \src "libresoc.v:44417.3-44446.6" + wire width 64 $2\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] + attribute \src "libresoc.v:44417.3-44446.6" + wire $2\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] + attribute \src "libresoc.v:44565.3-44593.6" + wire width 2 $2\fus_oper_i_alu_shift_rot0__input_carry[1:0] + attribute \src "libresoc.v:44623.3-44651.6" + wire $2\fus_oper_i_alu_shift_rot0__input_cr[0:0] + attribute \src "libresoc.v:44739.3-44767.6" + wire width 32 $2\fus_oper_i_alu_shift_rot0__insn[31:0] + attribute \src "libresoc.v:44359.3-44387.6" + wire width 7 $2\fus_oper_i_alu_shift_rot0__insn_type[6:0] + attribute \src "libresoc.v:44536.3-44564.6" + wire $2\fus_oper_i_alu_shift_rot0__invert_in[0:0] + attribute \src "libresoc.v:44681.3-44709.6" + wire $2\fus_oper_i_alu_shift_rot0__is_32bit[0:0] + attribute \src "libresoc.v:44710.3-44738.6" + wire $2\fus_oper_i_alu_shift_rot0__is_signed[0:0] + attribute \src "libresoc.v:44477.3-44506.6" + wire $2\fus_oper_i_alu_shift_rot0__oe__oe[0:0] + attribute \src "libresoc.v:44477.3-44506.6" + wire $2\fus_oper_i_alu_shift_rot0__oe__ok[0:0] + attribute \src "libresoc.v:44594.3-44622.6" + wire $2\fus_oper_i_alu_shift_rot0__output_carry[0:0] + attribute \src "libresoc.v:44652.3-44680.6" + wire $2\fus_oper_i_alu_shift_rot0__output_cr[0:0] + attribute \src "libresoc.v:44447.3-44476.6" + wire $2\fus_oper_i_alu_shift_rot0__rc__ok[0:0] + attribute \src "libresoc.v:44447.3-44476.6" + wire $2\fus_oper_i_alu_shift_rot0__rc__rc[0:0] + attribute \src "libresoc.v:44507.3-44535.6" + wire $2\fus_oper_i_alu_shift_rot0__write_cr0[0:0] + attribute \src "libresoc.v:48243.3-48271.6" + wire width 13 $2\fus_oper_i_alu_spr0__fn_unit[12:0] + attribute \src "libresoc.v:43425.3-43453.6" + wire width 32 $2\fus_oper_i_alu_spr0__insn[31:0] + attribute \src "libresoc.v:48214.3-48242.6" + wire width 7 $2\fus_oper_i_alu_spr0__insn_type[6:0] + attribute \src "libresoc.v:43454.3-43482.6" + wire $2\fus_oper_i_alu_spr0__is_32bit[0:0] + attribute \src "libresoc.v:47515.3-47543.6" + wire width 64 $2\fus_oper_i_alu_trap0__cia[63:0] + attribute \src "libresoc.v:47419.3-47447.6" + wire width 13 $2\fus_oper_i_alu_trap0__fn_unit[12:0] + attribute \src "libresoc.v:47457.3-47485.6" + wire width 32 $2\fus_oper_i_alu_trap0__insn[31:0] + attribute \src "libresoc.v:47372.3-47400.6" + wire width 7 $2\fus_oper_i_alu_trap0__insn_type[6:0] + attribute \src "libresoc.v:47544.3-47572.6" + wire $2\fus_oper_i_alu_trap0__is_32bit[0:0] + attribute \src "libresoc.v:47631.3-47659.6" + wire width 8 $2\fus_oper_i_alu_trap0__ldst_exc[7:0] + attribute \src "libresoc.v:47486.3-47514.6" + wire width 64 $2\fus_oper_i_alu_trap0__msr[63:0] + attribute \src "libresoc.v:47602.3-47630.6" + wire width 13 $2\fus_oper_i_alu_trap0__trapaddr[12:0] + attribute \src "libresoc.v:47573.3-47601.6" + wire width 8 $2\fus_oper_i_alu_trap0__traptype[7:0] + attribute \src "libresoc.v:45090.3-45118.6" + wire $2\fus_oper_i_ldst_ldst0__byte_reverse[0:0] + attribute \src "libresoc.v:45061.3-45089.6" + wire width 4 $2\fus_oper_i_ldst_ldst0__data_len[3:0] + attribute \src "libresoc.v:44855.3-44883.6" + wire width 13 $2\fus_oper_i_ldst_ldst0__fn_unit[12:0] + attribute \src "libresoc.v:44884.3-44913.6" + wire width 64 $2\fus_oper_i_ldst_ldst0__imm_data__data[63:0] + attribute \src "libresoc.v:44884.3-44913.6" + wire $2\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] + attribute \src "libresoc.v:45177.3-45205.6" + wire width 32 $2\fus_oper_i_ldst_ldst0__insn[31:0] + attribute \src "libresoc.v:44826.3-44854.6" + wire width 7 $2\fus_oper_i_ldst_ldst0__insn_type[6:0] + attribute \src "libresoc.v:45003.3-45031.6" + wire $2\fus_oper_i_ldst_ldst0__is_32bit[0:0] + attribute \src "libresoc.v:45032.3-45060.6" + wire $2\fus_oper_i_ldst_ldst0__is_signed[0:0] + attribute \src "libresoc.v:45148.3-45176.6" + wire width 2 $2\fus_oper_i_ldst_ldst0__ldst_mode[1:0] + attribute \src "libresoc.v:44973.3-45002.6" + wire $2\fus_oper_i_ldst_ldst0__oe__oe[0:0] + attribute \src "libresoc.v:44973.3-45002.6" + wire $2\fus_oper_i_ldst_ldst0__oe__ok[0:0] + attribute \src "libresoc.v:44943.3-44972.6" + wire $2\fus_oper_i_ldst_ldst0__rc__ok[0:0] + attribute \src "libresoc.v:44943.3-44972.6" + wire $2\fus_oper_i_ldst_ldst0__rc__rc[0:0] + attribute \src "libresoc.v:45119.3-45147.6" + wire $2\fus_oper_i_ldst_ldst0__sign_extend[0:0] + attribute \src "libresoc.v:44914.3-44942.6" + wire $2\fus_oper_i_ldst_ldst0__zero_a[0:0] + attribute \src "libresoc.v:45800.3-45820.6" + wire $3\core_terminate_o$next[0:0]$2591 + attribute \src "libresoc.v:45671.3-45761.6" + wire $3\corebusy_o[0:0] + attribute \src "libresoc.v:45625.3-45651.6" + wire width 2 $3\counter$next[1:0]$2568 + attribute \src "libresoc.v:46899.3-46927.6" + wire $3\fus_cu_issue_i$13[0:0]$2771 + attribute \src "libresoc.v:47296.3-47324.6" + wire $3\fus_cu_issue_i$16[0:0]$2833 + attribute \src "libresoc.v:47660.3-47688.6" + wire $3\fus_cu_issue_i$19[0:0]$2867 + attribute \src "libresoc.v:48156.3-48184.6" + wire $3\fus_cu_issue_i$22[0:0]$2892 + attribute \src "libresoc.v:43483.3-43511.6" + wire $3\fus_cu_issue_i$25[0:0]$2359 + attribute \src "libresoc.v:43979.3-44007.6" + wire $3\fus_cu_issue_i$28[0:0]$2384 + attribute \src "libresoc.v:44301.3-44329.6" + wire $3\fus_cu_issue_i$31[0:0]$2403 + attribute \src "libresoc.v:44768.3-44796.6" + wire $3\fus_cu_issue_i$34[0:0]$2427 + attribute \src "libresoc.v:45206.3-45234.6" + wire $3\fus_cu_issue_i$37[0:0]$2450 + attribute \src "libresoc.v:46691.3-46719.6" + wire $3\fus_cu_issue_i[0:0] + attribute \src "libresoc.v:46937.3-46965.6" + wire width 6 $3\fus_cu_rdmaskn_i$15[5:0]$2779 + attribute \src "libresoc.v:47334.3-47362.6" + wire width 3 $3\fus_cu_rdmaskn_i$18[2:0]$2841 + attribute \src "libresoc.v:47689.3-47717.6" + wire width 4 $3\fus_cu_rdmaskn_i$21[3:0]$2872 + attribute \src "libresoc.v:48185.3-48213.6" + wire width 3 $3\fus_cu_rdmaskn_i$24[2:0]$2897 + attribute \src "libresoc.v:43512.3-43540.6" + wire width 6 $3\fus_cu_rdmaskn_i$27[5:0]$2364 + attribute \src "libresoc.v:44008.3-44036.6" + wire width 3 $3\fus_cu_rdmaskn_i$30[2:0]$2389 + attribute \src "libresoc.v:44330.3-44358.6" + wire width 3 $3\fus_cu_rdmaskn_i$33[2:0]$2408 + attribute \src "libresoc.v:44797.3-44825.6" + wire width 5 $3\fus_cu_rdmaskn_i$36[4:0]$2432 + attribute \src "libresoc.v:45235.3-45263.6" + wire width 3 $3\fus_cu_rdmaskn_i$39[2:0]$2455 + attribute \src "libresoc.v:46729.3-46757.6" + wire width 4 $3\fus_cu_rdmaskn_i[3:0] + attribute \src "libresoc.v:46606.3-46634.6" + wire width 4 $3\fus_oper_i_alu_alu0__data_len[3:0] + attribute \src "libresoc.v:45916.3-45944.6" + wire width 13 $3\fus_oper_i_alu_alu0__fn_unit[12:0] + attribute \src "libresoc.v:45983.3-46012.6" + wire width 64 $3\fus_oper_i_alu_alu0__imm_data__data[63:0] + attribute \src "libresoc.v:45983.3-46012.6" + wire $3\fus_oper_i_alu_alu0__imm_data__ok[0:0] + attribute \src "libresoc.v:46436.3-46464.6" + wire width 2 $3\fus_oper_i_alu_alu0__input_carry[1:0] + attribute \src "libresoc.v:46653.3-46681.6" + wire width 32 $3\fus_oper_i_alu_alu0__insn[31:0] + attribute \src "libresoc.v:45859.3-45887.6" + wire width 7 $3\fus_oper_i_alu_alu0__insn_type[6:0] + attribute \src "libresoc.v:46235.3-46263.6" + wire $3\fus_oper_i_alu_alu0__invert_in[0:0] + attribute \src "libresoc.v:46350.3-46378.6" + wire $3\fus_oper_i_alu_alu0__invert_out[0:0] + attribute \src "libresoc.v:46521.3-46549.6" + wire $3\fus_oper_i_alu_alu0__is_32bit[0:0] + attribute \src "libresoc.v:46568.3-46596.6" + wire $3\fus_oper_i_alu_alu0__is_signed[0:0] + attribute \src "libresoc.v:46148.3-46177.6" + wire $3\fus_oper_i_alu_alu0__oe__oe[0:0] + attribute \src "libresoc.v:46148.3-46177.6" + wire $3\fus_oper_i_alu_alu0__oe__ok[0:0] + attribute \src "libresoc.v:46483.3-46511.6" + wire $3\fus_oper_i_alu_alu0__output_carry[0:0] + attribute \src "libresoc.v:46061.3-46090.6" + wire $3\fus_oper_i_alu_alu0__rc__ok[0:0] + attribute \src "libresoc.v:46061.3-46090.6" + wire $3\fus_oper_i_alu_alu0__rc__rc[0:0] + attribute \src "libresoc.v:46398.3-46426.6" + wire $3\fus_oper_i_alu_alu0__write_cr0[0:0] + attribute \src "libresoc.v:46283.3-46311.6" + wire $3\fus_oper_i_alu_alu0__zero_a[0:0] + attribute \src "libresoc.v:46984.3-47012.6" + wire width 64 $3\fus_oper_i_alu_branch0__cia[63:0] + attribute \src "libresoc.v:47069.3-47097.6" + wire width 13 $3\fus_oper_i_alu_branch0__fn_unit[12:0] + attribute \src "libresoc.v:47154.3-47183.6" + wire width 64 $3\fus_oper_i_alu_branch0__imm_data__data[63:0] + attribute \src "libresoc.v:47154.3-47183.6" + wire $3\fus_oper_i_alu_branch0__imm_data__ok[0:0] + attribute \src "libresoc.v:47107.3-47135.6" + wire width 32 $3\fus_oper_i_alu_branch0__insn[31:0] + attribute \src "libresoc.v:47022.3-47050.6" + wire width 7 $3\fus_oper_i_alu_branch0__insn_type[6:0] + attribute \src "libresoc.v:47249.3-47277.6" + wire $3\fus_oper_i_alu_branch0__is_32bit[0:0] + attribute \src "libresoc.v:47211.3-47239.6" + wire $3\fus_oper_i_alu_branch0__lk[0:0] + attribute \src "libresoc.v:46814.3-46842.6" + wire width 13 $3\fus_oper_i_alu_cr0__fn_unit[12:0] + attribute \src "libresoc.v:46861.3-46889.6" + wire width 32 $3\fus_oper_i_alu_cr0__insn[31:0] + attribute \src "libresoc.v:46767.3-46795.6" + wire width 7 $3\fus_oper_i_alu_cr0__insn_type[6:0] + attribute \src "libresoc.v:43921.3-43949.6" + wire width 4 $3\fus_oper_i_alu_div0__data_len[3:0] + attribute \src "libresoc.v:43570.3-43598.6" + wire width 13 $3\fus_oper_i_alu_div0__fn_unit[12:0] + attribute \src "libresoc.v:43599.3-43628.6" + wire width 64 $3\fus_oper_i_alu_div0__imm_data__data[63:0] + attribute \src "libresoc.v:43599.3-43628.6" + wire $3\fus_oper_i_alu_div0__imm_data__ok[0:0] + attribute \src "libresoc.v:43747.3-43775.6" + wire width 2 $3\fus_oper_i_alu_div0__input_carry[1:0] + attribute \src "libresoc.v:43950.3-43978.6" + wire width 32 $3\fus_oper_i_alu_div0__insn[31:0] + attribute \src "libresoc.v:43541.3-43569.6" + wire width 7 $3\fus_oper_i_alu_div0__insn_type[6:0] + attribute \src "libresoc.v:43689.3-43717.6" + wire $3\fus_oper_i_alu_div0__invert_in[0:0] + attribute \src "libresoc.v:43776.3-43804.6" + wire $3\fus_oper_i_alu_div0__invert_out[0:0] + attribute \src "libresoc.v:43863.3-43891.6" + wire $3\fus_oper_i_alu_div0__is_32bit[0:0] + attribute \src "libresoc.v:43892.3-43920.6" + wire $3\fus_oper_i_alu_div0__is_signed[0:0] + attribute \src "libresoc.v:43659.3-43688.6" + wire $3\fus_oper_i_alu_div0__oe__oe[0:0] + attribute \src "libresoc.v:43659.3-43688.6" + wire $3\fus_oper_i_alu_div0__oe__ok[0:0] + attribute \src "libresoc.v:43834.3-43862.6" + wire $3\fus_oper_i_alu_div0__output_carry[0:0] + attribute \src "libresoc.v:43629.3-43658.6" + wire $3\fus_oper_i_alu_div0__rc__ok[0:0] + attribute \src "libresoc.v:43629.3-43658.6" + wire $3\fus_oper_i_alu_div0__rc__rc[0:0] + attribute \src "libresoc.v:43805.3-43833.6" + wire $3\fus_oper_i_alu_div0__write_cr0[0:0] + attribute \src "libresoc.v:43718.3-43746.6" + wire $3\fus_oper_i_alu_div0__zero_a[0:0] + attribute \src "libresoc.v:48098.3-48126.6" + wire width 4 $3\fus_oper_i_alu_logical0__data_len[3:0] + attribute \src "libresoc.v:47747.3-47775.6" + wire width 13 $3\fus_oper_i_alu_logical0__fn_unit[12:0] + attribute \src "libresoc.v:47776.3-47805.6" + wire width 64 $3\fus_oper_i_alu_logical0__imm_data__data[63:0] + attribute \src "libresoc.v:47776.3-47805.6" + wire $3\fus_oper_i_alu_logical0__imm_data__ok[0:0] + attribute \src "libresoc.v:47924.3-47952.6" + wire width 2 $3\fus_oper_i_alu_logical0__input_carry[1:0] + attribute \src "libresoc.v:48127.3-48155.6" + wire width 32 $3\fus_oper_i_alu_logical0__insn[31:0] + attribute \src "libresoc.v:47718.3-47746.6" + wire width 7 $3\fus_oper_i_alu_logical0__insn_type[6:0] + attribute \src "libresoc.v:47866.3-47894.6" + wire $3\fus_oper_i_alu_logical0__invert_in[0:0] + attribute \src "libresoc.v:47953.3-47981.6" + wire $3\fus_oper_i_alu_logical0__invert_out[0:0] + attribute \src "libresoc.v:48040.3-48068.6" + wire $3\fus_oper_i_alu_logical0__is_32bit[0:0] + attribute \src "libresoc.v:48069.3-48097.6" + wire $3\fus_oper_i_alu_logical0__is_signed[0:0] + attribute \src "libresoc.v:47836.3-47865.6" + wire $3\fus_oper_i_alu_logical0__oe__oe[0:0] + attribute \src "libresoc.v:47836.3-47865.6" + wire $3\fus_oper_i_alu_logical0__oe__ok[0:0] + attribute \src "libresoc.v:48011.3-48039.6" + wire $3\fus_oper_i_alu_logical0__output_carry[0:0] + attribute \src "libresoc.v:47806.3-47835.6" + wire $3\fus_oper_i_alu_logical0__rc__ok[0:0] + attribute \src "libresoc.v:47806.3-47835.6" + wire $3\fus_oper_i_alu_logical0__rc__rc[0:0] + attribute \src "libresoc.v:47982.3-48010.6" + wire $3\fus_oper_i_alu_logical0__write_cr0[0:0] + attribute \src "libresoc.v:47895.3-47923.6" + wire $3\fus_oper_i_alu_logical0__zero_a[0:0] + attribute \src "libresoc.v:44066.3-44094.6" + wire width 13 $3\fus_oper_i_alu_mul0__fn_unit[12:0] + attribute \src "libresoc.v:44095.3-44124.6" + wire width 64 $3\fus_oper_i_alu_mul0__imm_data__data[63:0] + attribute \src "libresoc.v:44095.3-44124.6" + wire $3\fus_oper_i_alu_mul0__imm_data__ok[0:0] + attribute \src "libresoc.v:44272.3-44300.6" + wire width 32 $3\fus_oper_i_alu_mul0__insn[31:0] + attribute \src "libresoc.v:44037.3-44065.6" + wire width 7 $3\fus_oper_i_alu_mul0__insn_type[6:0] + attribute \src "libresoc.v:44214.3-44242.6" + wire $3\fus_oper_i_alu_mul0__is_32bit[0:0] + attribute \src "libresoc.v:44243.3-44271.6" + wire $3\fus_oper_i_alu_mul0__is_signed[0:0] + attribute \src "libresoc.v:44155.3-44184.6" + wire $3\fus_oper_i_alu_mul0__oe__oe[0:0] + attribute \src "libresoc.v:44155.3-44184.6" + wire $3\fus_oper_i_alu_mul0__oe__ok[0:0] + attribute \src "libresoc.v:44125.3-44154.6" + wire $3\fus_oper_i_alu_mul0__rc__ok[0:0] + attribute \src "libresoc.v:44125.3-44154.6" + wire $3\fus_oper_i_alu_mul0__rc__rc[0:0] + attribute \src "libresoc.v:44185.3-44213.6" + wire $3\fus_oper_i_alu_mul0__write_cr0[0:0] + attribute \src "libresoc.v:44388.3-44416.6" + wire width 13 $3\fus_oper_i_alu_shift_rot0__fn_unit[12:0] + attribute \src "libresoc.v:44417.3-44446.6" + wire width 64 $3\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] + attribute \src "libresoc.v:44417.3-44446.6" + wire $3\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] + attribute \src "libresoc.v:44565.3-44593.6" + wire width 2 $3\fus_oper_i_alu_shift_rot0__input_carry[1:0] + attribute \src "libresoc.v:44623.3-44651.6" + wire $3\fus_oper_i_alu_shift_rot0__input_cr[0:0] + attribute \src "libresoc.v:44739.3-44767.6" + wire width 32 $3\fus_oper_i_alu_shift_rot0__insn[31:0] + attribute \src "libresoc.v:44359.3-44387.6" + wire width 7 $3\fus_oper_i_alu_shift_rot0__insn_type[6:0] + attribute \src "libresoc.v:44536.3-44564.6" + wire $3\fus_oper_i_alu_shift_rot0__invert_in[0:0] + attribute \src "libresoc.v:44681.3-44709.6" + wire $3\fus_oper_i_alu_shift_rot0__is_32bit[0:0] + attribute \src "libresoc.v:44710.3-44738.6" + wire $3\fus_oper_i_alu_shift_rot0__is_signed[0:0] + attribute \src "libresoc.v:44477.3-44506.6" + wire $3\fus_oper_i_alu_shift_rot0__oe__oe[0:0] + attribute \src "libresoc.v:44477.3-44506.6" + wire $3\fus_oper_i_alu_shift_rot0__oe__ok[0:0] + attribute \src "libresoc.v:44594.3-44622.6" + wire $3\fus_oper_i_alu_shift_rot0__output_carry[0:0] + attribute \src "libresoc.v:44652.3-44680.6" + wire $3\fus_oper_i_alu_shift_rot0__output_cr[0:0] + attribute \src "libresoc.v:44447.3-44476.6" + wire $3\fus_oper_i_alu_shift_rot0__rc__ok[0:0] + attribute \src "libresoc.v:44447.3-44476.6" + wire $3\fus_oper_i_alu_shift_rot0__rc__rc[0:0] + attribute \src "libresoc.v:44507.3-44535.6" + wire $3\fus_oper_i_alu_shift_rot0__write_cr0[0:0] + attribute \src "libresoc.v:48243.3-48271.6" + wire width 13 $3\fus_oper_i_alu_spr0__fn_unit[12:0] + attribute \src "libresoc.v:43425.3-43453.6" + wire width 32 $3\fus_oper_i_alu_spr0__insn[31:0] + attribute \src "libresoc.v:48214.3-48242.6" + wire width 7 $3\fus_oper_i_alu_spr0__insn_type[6:0] + attribute \src "libresoc.v:43454.3-43482.6" + wire $3\fus_oper_i_alu_spr0__is_32bit[0:0] + attribute \src "libresoc.v:47515.3-47543.6" + wire width 64 $3\fus_oper_i_alu_trap0__cia[63:0] + attribute \src "libresoc.v:47419.3-47447.6" + wire width 13 $3\fus_oper_i_alu_trap0__fn_unit[12:0] + attribute \src "libresoc.v:47457.3-47485.6" + wire width 32 $3\fus_oper_i_alu_trap0__insn[31:0] + attribute \src "libresoc.v:47372.3-47400.6" + wire width 7 $3\fus_oper_i_alu_trap0__insn_type[6:0] + attribute \src "libresoc.v:47544.3-47572.6" + wire $3\fus_oper_i_alu_trap0__is_32bit[0:0] + attribute \src "libresoc.v:47631.3-47659.6" + wire width 8 $3\fus_oper_i_alu_trap0__ldst_exc[7:0] + attribute \src "libresoc.v:47486.3-47514.6" + wire width 64 $3\fus_oper_i_alu_trap0__msr[63:0] + attribute \src "libresoc.v:47602.3-47630.6" + wire width 13 $3\fus_oper_i_alu_trap0__trapaddr[12:0] + attribute \src "libresoc.v:47573.3-47601.6" + wire width 8 $3\fus_oper_i_alu_trap0__traptype[7:0] + attribute \src "libresoc.v:45090.3-45118.6" + wire $3\fus_oper_i_ldst_ldst0__byte_reverse[0:0] + attribute \src "libresoc.v:45061.3-45089.6" + wire width 4 $3\fus_oper_i_ldst_ldst0__data_len[3:0] + attribute \src "libresoc.v:44855.3-44883.6" + wire width 13 $3\fus_oper_i_ldst_ldst0__fn_unit[12:0] + attribute \src "libresoc.v:44884.3-44913.6" + wire width 64 $3\fus_oper_i_ldst_ldst0__imm_data__data[63:0] + attribute \src "libresoc.v:44884.3-44913.6" + wire $3\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] + attribute \src "libresoc.v:45177.3-45205.6" + wire width 32 $3\fus_oper_i_ldst_ldst0__insn[31:0] + attribute \src "libresoc.v:44826.3-44854.6" + wire width 7 $3\fus_oper_i_ldst_ldst0__insn_type[6:0] + attribute \src "libresoc.v:45003.3-45031.6" + wire $3\fus_oper_i_ldst_ldst0__is_32bit[0:0] + attribute \src "libresoc.v:45032.3-45060.6" + wire $3\fus_oper_i_ldst_ldst0__is_signed[0:0] + attribute \src "libresoc.v:45148.3-45176.6" + wire width 2 $3\fus_oper_i_ldst_ldst0__ldst_mode[1:0] + attribute \src "libresoc.v:44973.3-45002.6" + wire $3\fus_oper_i_ldst_ldst0__oe__oe[0:0] + attribute \src "libresoc.v:44973.3-45002.6" + wire $3\fus_oper_i_ldst_ldst0__oe__ok[0:0] + attribute \src "libresoc.v:44943.3-44972.6" + wire $3\fus_oper_i_ldst_ldst0__rc__ok[0:0] + attribute \src "libresoc.v:44943.3-44972.6" + wire $3\fus_oper_i_ldst_ldst0__rc__rc[0:0] + attribute \src "libresoc.v:45119.3-45147.6" + wire $3\fus_oper_i_ldst_ldst0__sign_extend[0:0] + attribute \src "libresoc.v:44914.3-44942.6" + wire $3\fus_oper_i_ldst_ldst0__zero_a[0:0] + attribute \src "libresoc.v:45671.3-45761.6" + wire $4\corebusy_o[0:0] + attribute \src "libresoc.v:45625.3-45651.6" + wire width 2 $4\counter$next[1:0]$2569 + attribute \src "libresoc.v:45671.3-45761.6" + wire $5\corebusy_o[0:0] + attribute \src "libresoc.v:45671.3-45761.6" + wire $6\corebusy_o[0:0] + attribute \src "libresoc.v:45671.3-45761.6" + wire $7\corebusy_o[0:0] + attribute \src "libresoc.v:45671.3-45761.6" + wire $8\corebusy_o[0:0] + attribute \src "libresoc.v:45671.3-45761.6" + wire $9\corebusy_o[0:0] + attribute \src "libresoc.v:41809.20-41809.122" + wire $and$libresoc.v:41809$1506_Y + attribute \src "libresoc.v:41810.20-41810.126" + wire $and$libresoc.v:41810$1507_Y + attribute \src "libresoc.v:41812.20-41812.110" + wire $and$libresoc.v:41812$1509_Y + attribute \src "libresoc.v:41813.20-41813.123" + wire $and$libresoc.v:41813$1510_Y + attribute \src "libresoc.v:41815.20-41815.122" + wire $and$libresoc.v:41815$1512_Y + attribute \src "libresoc.v:41816.20-41816.126" + wire $and$libresoc.v:41816$1513_Y + attribute \src "libresoc.v:41818.20-41818.110" + wire $and$libresoc.v:41818$1515_Y + attribute \src "libresoc.v:41819.20-41819.123" + wire $and$libresoc.v:41819$1516_Y + attribute \src "libresoc.v:41821.20-41821.123" + wire $and$libresoc.v:41821$1518_Y + attribute \src "libresoc.v:41822.20-41822.126" + wire $and$libresoc.v:41822$1519_Y + attribute \src "libresoc.v:41824.20-41824.110" + wire $and$libresoc.v:41824$1521_Y + attribute \src "libresoc.v:41825.20-41825.123" + wire $and$libresoc.v:41825$1522_Y + attribute \src "libresoc.v:41827.20-41827.123" + wire $and$libresoc.v:41827$1524_Y + attribute \src "libresoc.v:41828.20-41828.126" + wire $and$libresoc.v:41828$1525_Y + attribute \src "libresoc.v:41830.20-41830.110" + wire $and$libresoc.v:41830$1527_Y + attribute \src "libresoc.v:41831.20-41831.123" + wire $and$libresoc.v:41831$1528_Y + attribute \src "libresoc.v:41833.20-41833.123" + wire $and$libresoc.v:41833$1530_Y + attribute \src "libresoc.v:41834.20-41834.126" + wire $and$libresoc.v:41834$1531_Y + attribute \src "libresoc.v:41836.20-41836.110" + wire $and$libresoc.v:41836$1533_Y + attribute \src "libresoc.v:41837.20-41837.123" + wire $and$libresoc.v:41837$1534_Y + attribute \src "libresoc.v:41839.20-41839.123" + wire $and$libresoc.v:41839$1536_Y + attribute \src "libresoc.v:41840.20-41840.126" + wire $and$libresoc.v:41840$1537_Y + attribute \src "libresoc.v:41842.20-41842.110" + wire $and$libresoc.v:41842$1539_Y + attribute \src "libresoc.v:41843.20-41843.123" + wire $and$libresoc.v:41843$1540_Y + attribute \src "libresoc.v:41845.20-41845.113" + wire $and$libresoc.v:41845$1542_Y + attribute \src "libresoc.v:41846.20-41846.126" + wire $and$libresoc.v:41846$1543_Y + attribute \src "libresoc.v:41848.20-41848.110" + wire $and$libresoc.v:41848$1545_Y + attribute \src "libresoc.v:41849.20-41849.123" + wire $and$libresoc.v:41849$1546_Y + attribute \src "libresoc.v:41851.20-41851.114" + wire $and$libresoc.v:41851$1548_Y + attribute \src "libresoc.v:41852.20-41852.126" + wire $and$libresoc.v:41852$1549_Y + attribute \src "libresoc.v:41854.20-41854.110" + wire $and$libresoc.v:41854$1551_Y + attribute \src "libresoc.v:41855.20-41855.123" + wire $and$libresoc.v:41855$1552_Y + attribute \src "libresoc.v:41884.20-41884.123" + wire $and$libresoc.v:41884$1581_Y + attribute \src "libresoc.v:41885.20-41885.128" + wire $and$libresoc.v:41885$1582_Y + attribute \src "libresoc.v:41886.20-41886.133" + wire $and$libresoc.v:41886$1583_Y + attribute \src "libresoc.v:41888.20-41888.110" + wire $and$libresoc.v:41888$1585_Y + attribute \src "libresoc.v:41889.20-41889.128" + wire $and$libresoc.v:41889$1586_Y + attribute \src "libresoc.v:41891.20-41891.116" + wire $and$libresoc.v:41891$1588_Y + attribute \src "libresoc.v:41892.20-41892.123" + wire $and$libresoc.v:41892$1589_Y + attribute \src "libresoc.v:41893.20-41893.128" + wire $and$libresoc.v:41893$1590_Y + attribute \src "libresoc.v:41894.20-41894.128" + wire $and$libresoc.v:41894$1591_Y + attribute \src "libresoc.v:41895.20-41895.129" + wire $and$libresoc.v:41895$1592_Y + attribute \src "libresoc.v:41896.20-41896.129" + wire $and$libresoc.v:41896$1593_Y + attribute \src "libresoc.v:41897.20-41897.129" + wire $and$libresoc.v:41897$1594_Y + attribute \src "libresoc.v:41898.20-41898.130" + wire $and$libresoc.v:41898$1595_Y + attribute \src "libresoc.v:41900.20-41900.110" + wire $and$libresoc.v:41900$1597_Y + attribute \src "libresoc.v:41901.20-41901.125" + wire $and$libresoc.v:41901$1598_Y + attribute \src "libresoc.v:41905.20-41905.126" + wire $and$libresoc.v:41905$1602_Y + attribute \src "libresoc.v:41906.20-41906.130" + wire $and$libresoc.v:41906$1603_Y + attribute \src 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"libresoc.v:42306.19-42306.127" + wire $and$libresoc.v:42306$2008_Y + attribute \src "libresoc.v:42308.19-42308.127" + wire $and$libresoc.v:42308$2010_Y + attribute \src "libresoc.v:42309.19-42309.112" + wire $and$libresoc.v:42309$2011_Y + attribute \src "libresoc.v:42311.19-42311.102" + wire $and$libresoc.v:42311$2013_Y + attribute \src "libresoc.v:42312.19-42312.127" + wire $and$libresoc.v:42312$2014_Y + attribute \src "libresoc.v:42314.19-42314.127" + wire $and$libresoc.v:42314$2016_Y + attribute \src "libresoc.v:42315.19-42315.112" + wire $and$libresoc.v:42315$2017_Y + attribute \src "libresoc.v:42317.19-42317.102" + wire $and$libresoc.v:42317$2019_Y + attribute \src "libresoc.v:42318.19-42318.127" + wire $and$libresoc.v:42318$2020_Y + attribute \src "libresoc.v:42320.19-42320.127" + wire $and$libresoc.v:42320$2022_Y + attribute \src "libresoc.v:42321.19-42321.112" + wire $and$libresoc.v:42321$2023_Y + attribute \src "libresoc.v:42323.19-42323.102" + wire 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$and$libresoc.v:42529$2233_Y + attribute \src "libresoc.v:42531.19-42531.107" + wire $and$libresoc.v:42531$2235_Y + attribute \src "libresoc.v:42532.19-42532.121" + wire $and$libresoc.v:42532$2236_Y + attribute \src "libresoc.v:42155.19-42155.115" + wire $eq$libresoc.v:42155$1857_Y + attribute \src "libresoc.v:42159.19-42159.130" + wire $eq$libresoc.v:42159$1861_Y + attribute \src "libresoc.v:42161.19-42161.115" + wire $eq$libresoc.v:42161$1863_Y + attribute \src "libresoc.v:42169.19-42169.115" + wire $eq$libresoc.v:42169$1871_Y + attribute \src "libresoc.v:42176.19-42176.115" + wire $eq$libresoc.v:42176$1878_Y + attribute \src "libresoc.v:42182.19-42182.115" + wire $eq$libresoc.v:42182$1884_Y + attribute \src "libresoc.v:42184.19-42184.130" + wire $eq$libresoc.v:42184$1886_Y + attribute \src "libresoc.v:42186.19-42186.115" + wire $eq$libresoc.v:42186$1888_Y + attribute \src "libresoc.v:42191.19-42191.115" + wire $eq$libresoc.v:42191$1893_Y + attribute \src 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"libresoc.v:42188.19-42188.159" + wire width 6 $not$libresoc.v:42188$1890_Y + attribute \src "libresoc.v:42195.19-42195.128" + wire width 3 $not$libresoc.v:42195$1897_Y + attribute \src "libresoc.v:42202.19-42202.128" + wire width 3 $not$libresoc.v:42202$1904_Y + attribute \src "libresoc.v:42213.19-42213.150" + wire width 5 $not$libresoc.v:42213$1915_Y + attribute \src "libresoc.v:42214.19-42214.134" + wire width 3 $not$libresoc.v:42214$1916_Y + attribute \src "libresoc.v:42217.19-42217.106" + wire $not$libresoc.v:42217$1919_Y + attribute \src "libresoc.v:42223.19-42223.105" + wire $not$libresoc.v:42223$1925_Y + attribute \src "libresoc.v:42229.19-42229.107" + wire $not$libresoc.v:42229$1931_Y + attribute \src "libresoc.v:42235.19-42235.110" + wire $not$libresoc.v:42235$1937_Y + attribute \src "libresoc.v:42241.19-42241.106" + wire $not$libresoc.v:42241$1943_Y + attribute \src "libresoc.v:42247.19-42247.106" + wire $not$libresoc.v:42247$1949_Y + attribute \src "libresoc.v:42253.19-42253.106" + wire $not$libresoc.v:42253$1955_Y + attribute \src "libresoc.v:42259.19-42259.111" + wire $not$libresoc.v:42259$1961_Y + attribute \src "libresoc.v:42265.19-42265.107" + wire $not$libresoc.v:42265$1967_Y + attribute \src "libresoc.v:42280.19-42280.106" + wire $not$libresoc.v:42280$1982_Y + attribute \src "libresoc.v:42286.19-42286.105" + wire $not$libresoc.v:42286$1988_Y + attribute \src "libresoc.v:42292.19-42292.107" + wire $not$libresoc.v:42292$1994_Y + attribute \src "libresoc.v:42298.19-42298.110" + wire $not$libresoc.v:42298$2000_Y + attribute \src "libresoc.v:42304.19-42304.106" + wire $not$libresoc.v:42304$2006_Y + attribute \src "libresoc.v:42310.19-42310.106" + wire $not$libresoc.v:42310$2012_Y + attribute \src "libresoc.v:42316.19-42316.111" + wire $not$libresoc.v:42316$2018_Y + attribute \src "libresoc.v:42322.19-42322.107" + wire $not$libresoc.v:42322$2024_Y + attribute \src "libresoc.v:42336.19-42336.111" + wire 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"libresoc.v:42433.19-42433.109" + wire $not$libresoc.v:42433$2137_Y + attribute \src "libresoc.v:42439.19-42439.106" + wire $not$libresoc.v:42439$2143_Y + attribute \src "libresoc.v:42447.19-42447.110" + wire $not$libresoc.v:42447$2151_Y + attribute \src "libresoc.v:42456.19-42456.106" + wire $not$libresoc.v:42456$2160_Y + attribute \src "libresoc.v:42464.19-42464.106" + wire $not$libresoc.v:42464$2168_Y + attribute \src "libresoc.v:42472.19-42472.113" + wire $not$libresoc.v:42472$2176_Y + attribute \src "libresoc.v:42478.19-42478.111" + wire $not$libresoc.v:42478$2182_Y + attribute \src "libresoc.v:42484.19-42484.110" + wire $not$libresoc.v:42484$2188_Y + attribute \src "libresoc.v:42493.19-42493.113" + wire $not$libresoc.v:42493$2197_Y + attribute \src "libresoc.v:42499.19-42499.111" + wire $not$libresoc.v:42499$2203_Y + attribute \src "libresoc.v:42507.19-42507.108" + wire $not$libresoc.v:42507$2211_Y + attribute \src "libresoc.v:42524.19-42524.99" + wire $not$libresoc.v:42524$2228_Y + attribute \src "libresoc.v:42530.19-42530.104" + wire $not$libresoc.v:42530$2234_Y + attribute \src "libresoc.v:41857.20-41857.117" + wire width 64 $or$libresoc.v:41857$1554_Y + attribute \src "libresoc.v:41858.20-41858.123" + wire width 64 $or$libresoc.v:41858$1555_Y + attribute \src "libresoc.v:41859.20-41859.113" + wire width 64 $or$libresoc.v:41859$1556_Y + attribute \src "libresoc.v:41860.20-41860.103" + wire width 64 $or$libresoc.v:41860$1557_Y + attribute \src "libresoc.v:41861.20-41861.123" + wire width 64 $or$libresoc.v:41861$1558_Y + attribute \src "libresoc.v:41862.20-41862.122" + wire width 65 $or$libresoc.v:41862$1559_Y + attribute \src "libresoc.v:41863.20-41863.113" + wire width 65 $or$libresoc.v:41863$1560_Y + attribute \src "libresoc.v:41864.20-41864.103" + wire width 65 $or$libresoc.v:41864$1561_Y + attribute \src "libresoc.v:41865.20-41865.103" + wire width 65 $or$libresoc.v:41865$1562_Y + attribute \src "libresoc.v:41866.20-41866.109" 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$or$libresoc.v:42010$1708_Y + attribute \src "libresoc.v:42011.20-42011.103" + wire width 2 $or$libresoc.v:42011$1709_Y + attribute \src "libresoc.v:42012.20-42012.117" + wire width 3 $or$libresoc.v:42012$1710_Y + attribute \src "libresoc.v:42013.20-42013.117" + wire width 3 $or$libresoc.v:42013$1711_Y + attribute \src "libresoc.v:42014.20-42014.103" + wire width 3 $or$libresoc.v:42014$1712_Y + attribute \src "libresoc.v:42043.20-42043.123" + wire $or$libresoc.v:42043$1741_Y + attribute \src "libresoc.v:42044.20-42044.123" + wire $or$libresoc.v:42044$1742_Y + attribute \src "libresoc.v:42045.20-42045.103" + wire $or$libresoc.v:42045$1743_Y + attribute \src "libresoc.v:42047.20-42047.117" + wire $or$libresoc.v:42047$1746_Y + attribute \src "libresoc.v:42048.20-42048.117" + wire $or$libresoc.v:42048$1747_Y + attribute \src "libresoc.v:42049.20-42049.103" + wire $or$libresoc.v:42049$1748_Y + attribute \src "libresoc.v:42086.20-42086.123" + wire width 64 $or$libresoc.v:42086$1786_Y + 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"libresoc.v:42112.20-42112.123" + wire width 64 $or$libresoc.v:42112$1812_Y + attribute \src "libresoc.v:42113.20-42113.117" + wire $or$libresoc.v:42113$1813_Y + attribute \src "libresoc.v:42156.19-42156.115" + wire $or$libresoc.v:42156$1858_Y + attribute \src "libresoc.v:42158.19-42158.115" + wire $or$libresoc.v:42158$1860_Y + attribute \src "libresoc.v:42162.19-42162.115" + wire $or$libresoc.v:42162$1864_Y + attribute \src "libresoc.v:42170.19-42170.115" + wire $or$libresoc.v:42170$1872_Y + attribute \src "libresoc.v:42172.19-42172.115" + wire $or$libresoc.v:42172$1874_Y + attribute \src "libresoc.v:42177.19-42177.115" + wire $or$libresoc.v:42177$1879_Y + attribute \src "libresoc.v:42179.19-42179.115" + wire $or$libresoc.v:42179$1881_Y + attribute \src "libresoc.v:42183.19-42183.115" + wire $or$libresoc.v:42183$1885_Y + attribute \src "libresoc.v:42187.19-42187.115" + wire $or$libresoc.v:42187$1889_Y + attribute \src "libresoc.v:42192.19-42192.115" + wire $or$libresoc.v:42192$1894_Y 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"/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \dec_ALU_ALU__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \dec_ALU_ALU__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_ALU_ALU__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_ALU_ALU__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_ALU_ALU__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_ALU_ALU__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_ALU_ALU__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_ALU_ALU__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_ALU_ALU__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_ALU_ALU__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_ALU_ALU__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_ALU_ALU__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_ALU_ALU__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" + wire \dec_ALU_bigendian + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 32 \dec_ALU_raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \dec_BRANCH_BRANCH__cia + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \dec_BRANCH_BRANCH__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \dec_BRANCH_BRANCH__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_BRANCH_BRANCH__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \dec_BRANCH_BRANCH__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \dec_BRANCH_BRANCH__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_BRANCH_BRANCH__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_BRANCH_BRANCH__lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" + wire \dec_BRANCH_bigendian + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 32 \dec_BRANCH_raw_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \dec_CR_CR__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \dec_CR_CR__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \dec_CR_CR__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" + wire \dec_CR_bigendian + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 32 \dec_CR_raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \dec_DIV_DIV__data_len + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \dec_DIV_DIV__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \dec_DIV_DIV__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_DIV_DIV__imm_data__ok + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \dec_DIV_DIV__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \dec_DIV_DIV__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \dec_DIV_DIV__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_DIV_DIV__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_DIV_DIV__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_DIV_DIV__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_DIV_DIV__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_DIV_DIV__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_DIV_DIV__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_DIV_DIV__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_DIV_DIV__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_DIV_DIV__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_DIV_DIV__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_DIV_DIV__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" + wire \dec_DIV_bigendian + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 32 \dec_DIV_raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_LDST_LDST__byte_reverse + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \dec_LDST_LDST__data_len + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" 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attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute 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\src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_LDST_LDST__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_LDST_LDST__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_LDST_LDST__sign_extend + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_LDST_LDST__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" + wire \dec_LDST_bigendian + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 32 \dec_LDST_raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \dec_LOGICAL_LOGICAL__data_len + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute 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attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute 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\dec_LOGICAL_LOGICAL__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_LOGICAL_LOGICAL__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_LOGICAL_LOGICAL__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_LOGICAL_LOGICAL__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_LOGICAL_LOGICAL__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_LOGICAL_LOGICAL__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_LOGICAL_LOGICAL__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_LOGICAL_LOGICAL__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" + wire \dec_LOGICAL_bigendian + attribute \src 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\enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \dec_MUL_MUL__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_MUL_MUL__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_MUL_MUL__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_MUL_MUL__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_MUL_MUL__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_MUL_MUL__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_MUL_MUL__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_MUL_MUL__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" + wire \dec_MUL_bigendian + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 32 \dec_MUL_raw_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \dec_SHIFT_ROT_SHIFT_ROT__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \dec_SHIFT_ROT_SHIFT_ROT__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_SHIFT_ROT_SHIFT_ROT__imm_data__ok + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \dec_SHIFT_ROT_SHIFT_ROT__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_SHIFT_ROT_SHIFT_ROT__input_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \dec_SHIFT_ROT_SHIFT_ROT__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \dec_SHIFT_ROT_SHIFT_ROT__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_SHIFT_ROT_SHIFT_ROT__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_SHIFT_ROT_SHIFT_ROT__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_SHIFT_ROT_SHIFT_ROT__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_SHIFT_ROT_SHIFT_ROT__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_SHIFT_ROT_SHIFT_ROT__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_SHIFT_ROT_SHIFT_ROT__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_SHIFT_ROT_SHIFT_ROT__output_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_SHIFT_ROT_SHIFT_ROT__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_SHIFT_ROT_SHIFT_ROT__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_SHIFT_ROT_SHIFT_ROT__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" + wire \dec_SHIFT_ROT_bigendian + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 32 \dec_SHIFT_ROT_raw_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \dec_SPR_SPR__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \dec_SPR_SPR__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \dec_SPR_SPR__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_SPR_SPR__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" + wire \dec_SPR_bigendian + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 32 \dec_SPR_raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 5 input 73 \dmi__addr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 output 75 \dmi__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 74 \dmi__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + wire \dp_CR_cr_a_branch0_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + wire \dp_CR_cr_a_branch0_1$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + wire \dp_CR_cr_a_cr0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + wire \dp_CR_cr_a_cr0_0$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + wire \dp_CR_cr_b_cr0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + wire \dp_CR_cr_b_cr0_0$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + wire \dp_CR_cr_c_cr0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + wire \dp_CR_cr_c_cr0_0$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + wire \dp_CR_full_cr_cr0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + wire \dp_CR_full_cr_cr0_0$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + wire \dp_FAST_fast1_branch0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + wire \dp_FAST_fast1_branch0_0$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + wire \dp_FAST_fast1_spr0_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + wire \dp_FAST_fast1_spr0_2$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + wire \dp_FAST_fast1_trap0_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + wire \dp_FAST_fast1_trap0_1$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + wire \dp_FAST_fast2_branch0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + wire \dp_FAST_fast2_branch0_0$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + wire \dp_FAST_fast2_trap0_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + wire \dp_FAST_fast2_trap0_1$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + wire \dp_INT_ra_alu0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + wire \dp_INT_ra_alu0_0$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + wire \dp_INT_ra_cr0_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + wire \dp_INT_ra_cr0_1$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + wire \dp_INT_ra_div0_5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + wire \dp_INT_ra_div0_5$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + wire \dp_INT_ra_ldst0_8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + wire \dp_INT_ra_ldst0_8$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + wire \dp_INT_ra_logical0_3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + wire \dp_INT_ra_logical0_3$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + wire \dp_INT_ra_mul0_6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + wire \dp_INT_ra_mul0_6$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + wire \dp_INT_ra_shiftrot0_7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + wire \dp_INT_ra_shiftrot0_7$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + wire \dp_INT_ra_spr0_4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + wire \dp_INT_ra_spr0_4$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + wire \dp_INT_ra_trap0_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + wire \dp_INT_ra_trap0_2$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + wire \dp_INT_rb_alu0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + wire \dp_INT_rb_alu0_0$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + wire \dp_INT_rb_cr0_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + wire \dp_INT_rb_cr0_1$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + wire \dp_INT_rb_div0_4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + wire \dp_INT_rb_div0_4$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + wire \dp_INT_rb_ldst0_7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + wire \dp_INT_rb_ldst0_7$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + wire \dp_INT_rb_logical0_3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + wire \dp_INT_rb_logical0_3$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + wire \dp_INT_rb_mul0_5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + wire \dp_INT_rb_mul0_5$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + wire \dp_INT_rb_shiftrot0_6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + wire \dp_INT_rb_shiftrot0_6$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + wire \dp_INT_rb_trap0_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + wire \dp_INT_rb_trap0_2$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + wire \dp_INT_rc_ldst0_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + wire \dp_INT_rc_ldst0_1$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + wire \dp_INT_rc_shiftrot0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + wire \dp_INT_rc_shiftrot0_0$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:272" + wire \dp_SPR_spr1_spr0_0 + attribute \src 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\fus_oper_i_alu_mul0__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_mul0__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_mul0__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_mul0__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_mul0__write_cr0 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \fus_oper_i_alu_shift_rot0__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \fus_oper_i_alu_shift_rot0__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_shift_rot0__imm_data__ok + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \fus_oper_i_alu_shift_rot0__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_shift_rot0__input_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \fus_oper_i_alu_shift_rot0__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute 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"/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_shift_rot0__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_shift_rot0__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_shift_rot0__output_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_shift_rot0__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_shift_rot0__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_shift_rot0__write_cr0 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \fus_oper_i_alu_spr0__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \fus_oper_i_alu_spr0__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \fus_oper_i_alu_spr0__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_spr0__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \fus_oper_i_alu_trap0__cia + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \fus_oper_i_alu_trap0__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \fus_oper_i_alu_trap0__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute 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"/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_ldst_ldst0__byte_reverse + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \fus_oper_i_ldst_ldst0__data_len + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \fus_oper_i_ldst_ldst0__fn_unit + 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parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 13 + connect \A \core_core_fn_unit + connect \B 2'10 + connect \Y $and$libresoc.v:42117$1818_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" + cell $and $and$libresoc.v:42118$1819 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wrpick_STATE_msr_o + connect \B \wrpick_STATE_msr_en_o + connect \Y $and$libresoc.v:42118$1819_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $and $and$libresoc.v:42120$1821 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_pick$1780 + connect \B \$1784 + connect \Y $and$libresoc.v:42120$1821_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" + cell $and $and$libresoc.v:42122$1823 + parameter \A_SIGNED 0 + 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end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + cell $mux $ternary$libresoc.v:41975$1672 + parameter \WIDTH 2 + connect \A 2'00 + connect \B 2'10 + connect \S \wp$1429 + connect \Y $ternary$libresoc.v:41975$1672_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + cell $mux $ternary$libresoc.v:41990$1688 + parameter \WIDTH 3 + connect \A 3'000 + connect \B 3'100 + connect \S \wp$1463 + connect \Y $ternary$libresoc.v:41990$1688_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + cell $mux $ternary$libresoc.v:41996$1694 + parameter \WIDTH 3 + connect \A 3'000 + connect \B 3'100 + connect \S \wp$1479 + connect \Y $ternary$libresoc.v:41996$1694_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + cell $mux $ternary$libresoc.v:42002$1700 + parameter \WIDTH 3 + connect \A 3'000 + connect \B 3'100 + connect \S \wp$1495 + connect \Y $ternary$libresoc.v:42002$1700_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + cell $mux $ternary$libresoc.v:42008$1706 + parameter \WIDTH 3 + connect \A 3'000 + connect \B 3'100 + connect \S \wp$1511 + connect \Y $ternary$libresoc.v:42008$1706_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + cell $mux $ternary$libresoc.v:42024$1722 + parameter \WIDTH 1 + connect \A 1'0 + connect \B 1'1 + connect \S \wp$1547 + connect \Y $ternary$libresoc.v:42024$1722_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + cell $mux $ternary$libresoc.v:42030$1728 + parameter \WIDTH 1 + connect \A 1'0 + connect \B 1'1 + connect \S \wp$1563 + connect \Y $ternary$libresoc.v:42030$1728_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + cell $mux $ternary$libresoc.v:42036$1734 + parameter \WIDTH 1 + connect \A 1'0 + connect \B 1'1 + connect \S \wp$1579 + connect \Y $ternary$libresoc.v:42036$1734_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + cell $mux $ternary$libresoc.v:42042$1740 + parameter \WIDTH 1 + connect \A 1'0 + connect \B 1'1 + connect \S \wp$1595 + connect \Y $ternary$libresoc.v:42042$1740_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + cell $mux $ternary$libresoc.v:42061$1761 + parameter \WIDTH 3 + connect \A 3'000 + connect \B \core_fasto1 + connect \S \wp$1640 + connect \Y $ternary$libresoc.v:42061$1761_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + cell $mux $ternary$libresoc.v:42067$1767 + parameter \WIDTH 3 + connect \A 3'000 + connect \B \core_fasto1 + connect \S \wp$1656 + connect \Y $ternary$libresoc.v:42067$1767_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + cell $mux $ternary$libresoc.v:42073$1773 + parameter \WIDTH 3 + connect \A 3'000 + connect \B \core_fasto1 + connect \S \wp$1672 + connect \Y $ternary$libresoc.v:42073$1773_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + cell $mux $ternary$libresoc.v:42079$1779 + parameter \WIDTH 3 + connect \A 3'000 + connect \B \core_fasto2 + connect \S \wp$1688 + connect \Y $ternary$libresoc.v:42079$1779_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + cell $mux $ternary$libresoc.v:42085$1785 + parameter \WIDTH 3 + connect \A 3'000 + connect \B \core_fasto2 + connect \S \wp$1704 + connect \Y $ternary$libresoc.v:42085$1785_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + cell $mux $ternary$libresoc.v:42105$1805 + parameter \WIDTH 1 + connect \A 1'0 + connect \B 1'1 + connect \S \wp$1748 + connect \Y $ternary$libresoc.v:42105$1805_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + cell $mux $ternary$libresoc.v:42111$1811 + parameter \WIDTH 1 + connect \A 1'0 + connect \B 1'1 + connect \S \wp$1764 + connect \Y $ternary$libresoc.v:42111$1811_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + cell $mux $ternary$libresoc.v:42123$1824 + parameter \WIDTH 2 + connect \A 2'00 + connect \B 2'10 + connect \S \wp$1788 + connect \Y $ternary$libresoc.v:42123$1824_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + cell $mux $ternary$libresoc.v:42131$1833 + parameter \WIDTH 10 + connect \A 10'0000000000 + connect \B \core_spro + connect \S \wp$1808 + connect \Y $ternary$libresoc.v:42131$1833_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283" + cell $mux $ternary$libresoc.v:42220$1922 + parameter \WIDTH 7 + connect \A 7'0000000 + connect \B \core_reg1 + connect \S \rp_INT_ra_alu0_0 + connect \Y $ternary$libresoc.v:42220$1922_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283" + cell $mux $ternary$libresoc.v:42226$1928 + parameter \WIDTH 7 + connect \A 7'0000000 + connect \B \core_reg1 + connect \S \rp_INT_ra_cr0_1 + connect \Y $ternary$libresoc.v:42226$1928_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283" + cell $mux $ternary$libresoc.v:42232$1934 + parameter \WIDTH 7 + connect \A 7'0000000 + connect \B \core_reg1 + connect \S \rp_INT_ra_trap0_2 + connect \Y $ternary$libresoc.v:42232$1934_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283" + cell $mux $ternary$libresoc.v:42238$1940 + parameter \WIDTH 7 + connect \A 7'0000000 + connect \B \core_reg1 + connect \S \rp_INT_ra_logical0_3 + connect \Y $ternary$libresoc.v:42238$1940_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283" + cell $mux $ternary$libresoc.v:42244$1946 + parameter \WIDTH 7 + connect \A 7'0000000 + connect \B \core_reg1 + connect \S \rp_INT_ra_spr0_4 + connect \Y $ternary$libresoc.v:42244$1946_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283" + cell $mux $ternary$libresoc.v:42250$1952 + parameter \WIDTH 7 + connect \A 7'0000000 + connect \B \core_reg1 + connect \S \rp_INT_ra_div0_5 + connect \Y $ternary$libresoc.v:42250$1952_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283" + cell $mux $ternary$libresoc.v:42256$1958 + parameter \WIDTH 7 + connect \A 7'0000000 + connect \B \core_reg1 + connect \S \rp_INT_ra_mul0_6 + connect \Y $ternary$libresoc.v:42256$1958_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283" + cell $mux $ternary$libresoc.v:42262$1964 + parameter \WIDTH 7 + connect \A 7'0000000 + connect \B \core_reg1 + connect \S \rp_INT_ra_shiftrot0_7 + connect \Y $ternary$libresoc.v:42262$1964_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283" + cell $mux $ternary$libresoc.v:42268$1970 + parameter \WIDTH 7 + connect \A 7'0000000 + connect \B \core_reg1 + connect \S \rp_INT_ra_ldst0_8 + connect \Y $ternary$libresoc.v:42268$1970_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283" + cell $mux $ternary$libresoc.v:42283$1985 + parameter \WIDTH 7 + connect \A 7'0000000 + connect \B \core_reg2 + connect \S \rp_INT_rb_alu0_0 + connect \Y $ternary$libresoc.v:42283$1985_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283" + cell $mux $ternary$libresoc.v:42289$1991 + parameter \WIDTH 7 + connect \A 7'0000000 + connect \B \core_reg2 + connect \S \rp_INT_rb_cr0_1 + connect \Y $ternary$libresoc.v:42289$1991_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283" + cell $mux $ternary$libresoc.v:42295$1997 + parameter \WIDTH 7 + connect \A 7'0000000 + connect \B \core_reg2 + connect \S \rp_INT_rb_trap0_2 + connect \Y $ternary$libresoc.v:42295$1997_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283" + cell $mux $ternary$libresoc.v:42301$2003 + parameter \WIDTH 7 + connect \A 7'0000000 + connect \B \core_reg2 + connect \S \rp_INT_rb_logical0_3 + connect \Y $ternary$libresoc.v:42301$2003_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283" + cell $mux $ternary$libresoc.v:42307$2009 + parameter \WIDTH 7 + connect \A 7'0000000 + connect \B \core_reg2 + connect \S \rp_INT_rb_div0_4 + connect \Y $ternary$libresoc.v:42307$2009_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283" + cell $mux $ternary$libresoc.v:42313$2015 + parameter \WIDTH 7 + connect \A 7'0000000 + connect \B \core_reg2 + connect \S \rp_INT_rb_mul0_5 + connect \Y $ternary$libresoc.v:42313$2015_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283" + cell $mux $ternary$libresoc.v:42319$2021 + parameter \WIDTH 7 + connect \A 7'0000000 + connect \B \core_reg2 + connect \S \rp_INT_rb_shiftrot0_6 + connect \Y $ternary$libresoc.v:42319$2021_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283" + cell $mux $ternary$libresoc.v:42325$2027 + parameter \WIDTH 7 + connect \A 7'0000000 + connect \B \core_reg2 + connect \S \rp_INT_rb_ldst0_7 + connect \Y $ternary$libresoc.v:42325$2027_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283" + cell $mux $ternary$libresoc.v:42339$2041 + parameter \WIDTH 7 + connect \A 7'0000000 + connect \B \core_reg3 + connect \S \rp_INT_rc_shiftrot0_0 + connect \Y $ternary$libresoc.v:42339$2041_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283" + cell $mux $ternary$libresoc.v:42345$2047 + parameter \WIDTH 7 + connect \A 7'0000000 + connect \B \core_reg3 + connect \S \rp_INT_rc_ldst0_1 + connect \Y $ternary$libresoc.v:42345$2047_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283" + cell $mux $ternary$libresoc.v:42359$2061 + parameter \WIDTH 1 + connect \A 1'0 + connect \B 1'1 + connect \S \rp_XER_xer_so_alu0_0 + connect \Y $ternary$libresoc.v:42359$2061_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283" + cell $mux $ternary$libresoc.v:42365$2067 + parameter \WIDTH 1 + connect \A 1'0 + connect \B 1'1 + connect \S \rp_XER_xer_so_logical0_1 + connect \Y $ternary$libresoc.v:42365$2067_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283" + cell $mux $ternary$libresoc.v:42371$2073 + parameter \WIDTH 1 + connect \A 1'0 + connect \B 1'1 + connect \S \rp_XER_xer_so_spr0_2 + connect \Y $ternary$libresoc.v:42371$2073_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283" + cell $mux $ternary$libresoc.v:42377$2079 + parameter \WIDTH 1 + connect \A 1'0 + connect \B 1'1 + connect \S \rp_XER_xer_so_div0_3 + connect \Y $ternary$libresoc.v:42377$2079_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283" + cell $mux $ternary$libresoc.v:42383$2085 + parameter \WIDTH 1 + connect \A 1'0 + connect \B 1'1 + connect \S \rp_XER_xer_so_mul0_4 + connect \Y $ternary$libresoc.v:42383$2085_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283" + cell $mux $ternary$libresoc.v:42389$2091 + parameter \WIDTH 1 + connect \A 1'0 + connect \B 1'1 + connect \S \rp_XER_xer_so_shiftrot0_5 + connect \Y $ternary$libresoc.v:42389$2091_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283" + cell $mux $ternary$libresoc.v:42405$2108 + parameter \WIDTH 2 + connect \A 2'00 + connect \B 2'10 + connect \S \rp_XER_xer_ca_alu0_0 + connect \Y $ternary$libresoc.v:42405$2108_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283" + cell $mux $ternary$libresoc.v:42411$2114 + parameter \WIDTH 2 + connect \A 2'00 + connect \B 2'10 + connect \S \rp_XER_xer_ca_spr0_1 + connect \Y $ternary$libresoc.v:42411$2114_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283" + cell $mux $ternary$libresoc.v:42417$2120 + parameter \WIDTH 2 + connect \A 2'00 + connect \B 2'10 + connect \S \rp_XER_xer_ca_shiftrot0_2 + connect \Y $ternary$libresoc.v:42417$2120_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283" + cell $mux $ternary$libresoc.v:42430$2134 + parameter \WIDTH 3 + connect \A 3'000 + connect \B 3'100 + connect \S \rp_XER_xer_ov_spr0_0 + connect \Y $ternary$libresoc.v:42430$2134_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283" + cell $mux $ternary$libresoc.v:42436$2140 + parameter \WIDTH 8 + connect \A 8'00000000 + connect \B \core_core_cr_rd + connect \S \rp_CR_full_cr_cr0_0 + connect \Y $ternary$libresoc.v:42436$2140_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283" + cell $mux $ternary$libresoc.v:42444$2148 + parameter \WIDTH 256 + connect \A 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + connect \B \$806 + connect \S \rp_CR_cr_a_cr0_0 + connect \Y $ternary$libresoc.v:42444$2148_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283" + cell $mux $ternary$libresoc.v:42452$2156 + parameter \WIDTH 256 + connect \A 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + connect \B \$822 + connect \S \rp_CR_cr_a_branch0_1 + connect \Y $ternary$libresoc.v:42452$2156_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283" + cell $mux $ternary$libresoc.v:42461$2165 + parameter \WIDTH 256 + connect \A 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + connect \B \$841 + connect \S \rp_CR_cr_b_cr0_0 + connect \Y $ternary$libresoc.v:42461$2165_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283" + cell $mux $ternary$libresoc.v:42469$2173 + parameter \WIDTH 256 + connect \A 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + connect \B \$857 + connect \S \rp_CR_cr_c_cr0_0 + connect \Y $ternary$libresoc.v:42469$2173_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283" + cell $mux $ternary$libresoc.v:42475$2179 + parameter \WIDTH 3 + connect \A 3'000 + connect \B \core_fast1 + connect \S \rp_FAST_fast1_branch0_0 + connect \Y $ternary$libresoc.v:42475$2179_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283" + cell $mux $ternary$libresoc.v:42481$2185 + parameter \WIDTH 3 + connect \A 3'000 + connect \B \core_fast1 + connect \S \rp_FAST_fast1_trap0_1 + connect \Y $ternary$libresoc.v:42481$2185_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283" + cell $mux $ternary$libresoc.v:42487$2191 + parameter \WIDTH 3 + connect \A 3'000 + connect \B \core_fast1 + connect \S \rp_FAST_fast1_spr0_2 + connect \Y $ternary$libresoc.v:42487$2191_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283" + cell $mux $ternary$libresoc.v:42496$2200 + parameter \WIDTH 3 + connect \A 3'000 + connect \B \core_fast2 + connect \S \rp_FAST_fast2_branch0_0 + connect \Y $ternary$libresoc.v:42496$2200_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283" + cell $mux $ternary$libresoc.v:42502$2206 + parameter \WIDTH 3 + connect \A 3'000 + connect \B \core_fast2 + connect \S \rp_FAST_fast2_trap0_1 + connect \Y $ternary$libresoc.v:42502$2206_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283" + cell $mux $ternary$libresoc.v:42510$2214 + parameter \WIDTH 10 + connect \A 10'0000000000 + connect \B \core_spr1 + connect \S \rp_SPR_spr1_spr0_0 + connect \Y $ternary$libresoc.v:42510$2214_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + cell $mux $ternary$libresoc.v:42527$2231 + parameter \WIDTH 7 + connect \A 7'0000000 + connect \B \core_rego + connect \S \wp + connect \Y $ternary$libresoc.v:42527$2231_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" + cell $mux $ternary$libresoc.v:42533$2237 + parameter \WIDTH 7 + connect \A 7'0000000 + connect \B \core_rego + connect \S \wp$994 + connect \Y $ternary$libresoc.v:42533$2237_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:42692.6-42709.4" + cell \cr \cr + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \data_i \cr_data_i + connect \full_rd2__data_o \full_rd2__data_o + connect \full_rd2__ren \full_rd2__ren + connect \full_rd__data_o \cr_full_rd__data_o + connect \full_rd__ren \cr_full_rd__ren + connect \full_wr__data_i \cr_full_wr__data_i + connect \full_wr__wen \cr_full_wr__wen + connect \src1__data_o \cr_src1__data_o + connect \src1__ren \cr_src1__ren + connect \src2__data_o \cr_src2__data_o + connect \src2__ren \cr_src2__ren + connect \src3__data_o \cr_src3__data_o + connect \src3__ren \cr_src3__ren + connect \wen \cr_wen + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:42710.11-42731.4" + cell \dec_ALU \dec_ALU + connect \ALU__data_len \dec_ALU_ALU__data_len + connect \ALU__fn_unit \dec_ALU_ALU__fn_unit + connect \ALU__imm_data__data \dec_ALU_ALU__imm_data__data + connect \ALU__imm_data__ok \dec_ALU_ALU__imm_data__ok + connect \ALU__input_carry \dec_ALU_ALU__input_carry + connect \ALU__insn \dec_ALU_ALU__insn + connect \ALU__insn_type \dec_ALU_ALU__insn_type + connect \ALU__invert_in \dec_ALU_ALU__invert_in + connect \ALU__invert_out \dec_ALU_ALU__invert_out + connect \ALU__is_32bit \dec_ALU_ALU__is_32bit + connect \ALU__is_signed \dec_ALU_ALU__is_signed + connect \ALU__oe__oe \dec_ALU_ALU__oe__oe + connect \ALU__oe__ok \dec_ALU_ALU__oe__ok + connect \ALU__output_carry \dec_ALU_ALU__output_carry + connect \ALU__rc__ok \dec_ALU_ALU__rc__ok + connect \ALU__rc__rc \dec_ALU_ALU__rc__rc + connect \ALU__write_cr0 \dec_ALU_ALU__write_cr0 + connect \ALU__zero_a \dec_ALU_ALU__zero_a + connect \bigendian \dec_ALU_bigendian + connect \raw_opcode_in \dec_ALU_raw_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:42732.14-42744.4" + cell \dec_BRANCH \dec_BRANCH + connect \BRANCH__cia \dec_BRANCH_BRANCH__cia + connect \BRANCH__fn_unit \dec_BRANCH_BRANCH__fn_unit + connect \BRANCH__imm_data__data \dec_BRANCH_BRANCH__imm_data__data + connect \BRANCH__imm_data__ok \dec_BRANCH_BRANCH__imm_data__ok + connect \BRANCH__insn \dec_BRANCH_BRANCH__insn + connect \BRANCH__insn_type \dec_BRANCH_BRANCH__insn_type + connect \BRANCH__is_32bit \dec_BRANCH_BRANCH__is_32bit + connect \BRANCH__lk \dec_BRANCH_BRANCH__lk + connect \bigendian \dec_BRANCH_bigendian + connect \core_pc \core_pc + connect \raw_opcode_in \dec_BRANCH_raw_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:42745.10-42751.4" + cell \dec_CR \dec_CR + connect \CR__fn_unit \dec_CR_CR__fn_unit + connect \CR__insn \dec_CR_CR__insn + connect \CR__insn_type \dec_CR_CR__insn_type + connect \bigendian \dec_CR_bigendian + connect \raw_opcode_in \dec_CR_raw_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:42752.11-42773.4" + cell \dec_DIV \dec_DIV + connect \DIV__data_len \dec_DIV_DIV__data_len + connect \DIV__fn_unit \dec_DIV_DIV__fn_unit + connect \DIV__imm_data__data \dec_DIV_DIV__imm_data__data + connect \DIV__imm_data__ok \dec_DIV_DIV__imm_data__ok + connect \DIV__input_carry \dec_DIV_DIV__input_carry + connect \DIV__insn \dec_DIV_DIV__insn + connect \DIV__insn_type \dec_DIV_DIV__insn_type + connect \DIV__invert_in \dec_DIV_DIV__invert_in + connect \DIV__invert_out \dec_DIV_DIV__invert_out + connect \DIV__is_32bit \dec_DIV_DIV__is_32bit + connect \DIV__is_signed \dec_DIV_DIV__is_signed + connect \DIV__oe__oe \dec_DIV_DIV__oe__oe + connect \DIV__oe__ok \dec_DIV_DIV__oe__ok + connect \DIV__output_carry \dec_DIV_DIV__output_carry + connect \DIV__rc__ok \dec_DIV_DIV__rc__ok + connect \DIV__rc__rc \dec_DIV_DIV__rc__rc + connect \DIV__write_cr0 \dec_DIV_DIV__write_cr0 + connect \DIV__zero_a \dec_DIV_DIV__zero_a + connect \bigendian \dec_DIV_bigendian + connect \raw_opcode_in \dec_DIV_raw_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:42774.12-42793.4" + cell \dec_LDST \dec_LDST + connect \LDST__byte_reverse \dec_LDST_LDST__byte_reverse + connect \LDST__data_len \dec_LDST_LDST__data_len + connect \LDST__fn_unit \dec_LDST_LDST__fn_unit + connect \LDST__imm_data__data \dec_LDST_LDST__imm_data__data + connect \LDST__imm_data__ok \dec_LDST_LDST__imm_data__ok + connect \LDST__insn \dec_LDST_LDST__insn + connect \LDST__insn_type \dec_LDST_LDST__insn_type + connect \LDST__is_32bit \dec_LDST_LDST__is_32bit + connect \LDST__is_signed \dec_LDST_LDST__is_signed + connect \LDST__ldst_mode \dec_LDST_LDST__ldst_mode + connect \LDST__oe__oe \dec_LDST_LDST__oe__oe + connect \LDST__oe__ok \dec_LDST_LDST__oe__ok + connect \LDST__rc__ok \dec_LDST_LDST__rc__ok + connect \LDST__rc__rc \dec_LDST_LDST__rc__rc + connect \LDST__sign_extend \dec_LDST_LDST__sign_extend + connect \LDST__zero_a \dec_LDST_LDST__zero_a + connect \bigendian \dec_LDST_bigendian + connect \raw_opcode_in \dec_LDST_raw_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:42794.15-42815.4" + cell \dec_LOGICAL \dec_LOGICAL + connect \LOGICAL__data_len \dec_LOGICAL_LOGICAL__data_len + connect \LOGICAL__fn_unit \dec_LOGICAL_LOGICAL__fn_unit + connect \LOGICAL__imm_data__data \dec_LOGICAL_LOGICAL__imm_data__data + connect \LOGICAL__imm_data__ok \dec_LOGICAL_LOGICAL__imm_data__ok + connect \LOGICAL__input_carry \dec_LOGICAL_LOGICAL__input_carry + connect \LOGICAL__insn \dec_LOGICAL_LOGICAL__insn + connect \LOGICAL__insn_type \dec_LOGICAL_LOGICAL__insn_type + connect \LOGICAL__invert_in \dec_LOGICAL_LOGICAL__invert_in + connect \LOGICAL__invert_out \dec_LOGICAL_LOGICAL__invert_out + connect \LOGICAL__is_32bit \dec_LOGICAL_LOGICAL__is_32bit + connect \LOGICAL__is_signed \dec_LOGICAL_LOGICAL__is_signed + connect \LOGICAL__oe__oe \dec_LOGICAL_LOGICAL__oe__oe + connect \LOGICAL__oe__ok \dec_LOGICAL_LOGICAL__oe__ok + connect \LOGICAL__output_carry \dec_LOGICAL_LOGICAL__output_carry + connect \LOGICAL__rc__ok \dec_LOGICAL_LOGICAL__rc__ok + connect \LOGICAL__rc__rc \dec_LOGICAL_LOGICAL__rc__rc + connect \LOGICAL__write_cr0 \dec_LOGICAL_LOGICAL__write_cr0 + connect \LOGICAL__zero_a \dec_LOGICAL_LOGICAL__zero_a + connect \bigendian \dec_LOGICAL_bigendian + connect \raw_opcode_in \dec_LOGICAL_raw_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:42816.11-42831.4" + cell \dec_MUL \dec_MUL + connect \MUL__fn_unit \dec_MUL_MUL__fn_unit + connect \MUL__imm_data__data \dec_MUL_MUL__imm_data__data + connect \MUL__imm_data__ok \dec_MUL_MUL__imm_data__ok + connect \MUL__insn \dec_MUL_MUL__insn + connect \MUL__insn_type \dec_MUL_MUL__insn_type + connect \MUL__is_32bit \dec_MUL_MUL__is_32bit + connect \MUL__is_signed \dec_MUL_MUL__is_signed + connect \MUL__oe__oe \dec_MUL_MUL__oe__oe + connect \MUL__oe__ok \dec_MUL_MUL__oe__ok + connect \MUL__rc__ok \dec_MUL_MUL__rc__ok + connect \MUL__rc__rc \dec_MUL_MUL__rc__rc + connect \MUL__write_cr0 \dec_MUL_MUL__write_cr0 + connect \bigendian \dec_MUL_bigendian + connect \raw_opcode_in \dec_MUL_raw_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:42832.17-42852.4" + cell \dec_SHIFT_ROT \dec_SHIFT_ROT + connect \SHIFT_ROT__fn_unit \dec_SHIFT_ROT_SHIFT_ROT__fn_unit + connect \SHIFT_ROT__imm_data__data \dec_SHIFT_ROT_SHIFT_ROT__imm_data__data + connect \SHIFT_ROT__imm_data__ok \dec_SHIFT_ROT_SHIFT_ROT__imm_data__ok + connect \SHIFT_ROT__input_carry \dec_SHIFT_ROT_SHIFT_ROT__input_carry + connect \SHIFT_ROT__input_cr \dec_SHIFT_ROT_SHIFT_ROT__input_cr + connect \SHIFT_ROT__insn \dec_SHIFT_ROT_SHIFT_ROT__insn + connect \SHIFT_ROT__insn_type \dec_SHIFT_ROT_SHIFT_ROT__insn_type + connect \SHIFT_ROT__invert_in \dec_SHIFT_ROT_SHIFT_ROT__invert_in + connect \SHIFT_ROT__is_32bit \dec_SHIFT_ROT_SHIFT_ROT__is_32bit + connect \SHIFT_ROT__is_signed \dec_SHIFT_ROT_SHIFT_ROT__is_signed + connect \SHIFT_ROT__oe__oe \dec_SHIFT_ROT_SHIFT_ROT__oe__oe + connect \SHIFT_ROT__oe__ok \dec_SHIFT_ROT_SHIFT_ROT__oe__ok + connect \SHIFT_ROT__output_carry \dec_SHIFT_ROT_SHIFT_ROT__output_carry + connect \SHIFT_ROT__output_cr \dec_SHIFT_ROT_SHIFT_ROT__output_cr + connect \SHIFT_ROT__rc__ok \dec_SHIFT_ROT_SHIFT_ROT__rc__ok + connect \SHIFT_ROT__rc__rc \dec_SHIFT_ROT_SHIFT_ROT__rc__rc + connect \SHIFT_ROT__write_cr0 \dec_SHIFT_ROT_SHIFT_ROT__write_cr0 + connect \bigendian \dec_SHIFT_ROT_bigendian + connect \raw_opcode_in \dec_SHIFT_ROT_raw_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:42853.11-42860.4" + cell \dec_SPR \dec_SPR + connect \SPR__fn_unit \dec_SPR_SPR__fn_unit + connect \SPR__insn \dec_SPR_SPR__insn + connect \SPR__insn_type \dec_SPR_SPR__insn_type + connect \SPR__is_32bit \dec_SPR_SPR__is_32bit + connect \bigendian \dec_SPR_bigendian + connect \raw_opcode_in \dec_SPR_raw_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:42861.8-42879.4" + cell \fast \fast + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \dest1__addr \fast_dest1__addr + connect \dest1__data_i \fast_dest1__data_i + connect \dest1__wen \fast_dest1__wen + connect \issue__addr \issue__addr + connect \issue__addr$1 \issue__addr$12 + connect \issue__data_i \issue__data_i + connect \issue__data_o \issue__data_o + connect \issue__ren \issue__ren + connect \issue__wen \issue__wen + connect \src1__addr \fast_src1__addr + connect \src1__data_o \fast_src1__data_o + connect \src1__ren \fast_src1__ren + connect \src2__addr \fast_src2__addr + connect \src2__data_o \fast_src2__data_o + connect \src2__ren \fast_src2__ren + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:42880.7-43211.4" + cell \fus \fus + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cr_a_ok \fus_cr_a_ok + connect \cr_a_ok$110 \fus_cr_a_ok$122 + connect \cr_a_ok$111 \fus_cr_a_ok$123 + connect \cr_a_ok$112 \fus_cr_a_ok$124 + connect \cr_a_ok$113 \fus_cr_a_ok$125 + connect \cr_a_ok$114 \fus_cr_a_ok$126 + connect \cu_ad__go_i \cu_ad__go_i + connect \cu_ad__rel_o \cu_ad__rel_o + connect \cu_busy_o \fus_cu_busy_o + connect \cu_busy_o$11 \fus_cu_busy_o$23 + connect \cu_busy_o$14 \fus_cu_busy_o$26 + connect \cu_busy_o$17 \fus_cu_busy_o$29 + connect \cu_busy_o$2 \fus_cu_busy_o$14 + connect \cu_busy_o$20 \fus_cu_busy_o$32 + connect \cu_busy_o$23 \fus_cu_busy_o$35 + connect \cu_busy_o$26 \fus_cu_busy_o$38 + connect \cu_busy_o$5 \fus_cu_busy_o$17 + connect \cu_busy_o$8 \fus_cu_busy_o$20 + connect \cu_issue_i \fus_cu_issue_i + connect \cu_issue_i$1 \fus_cu_issue_i$13 + connect \cu_issue_i$10 \fus_cu_issue_i$22 + connect \cu_issue_i$13 \fus_cu_issue_i$25 + connect \cu_issue_i$16 \fus_cu_issue_i$28 + connect \cu_issue_i$19 \fus_cu_issue_i$31 + connect \cu_issue_i$22 \fus_cu_issue_i$34 + connect \cu_issue_i$25 \fus_cu_issue_i$37 + connect \cu_issue_i$4 \fus_cu_issue_i$16 + connect \cu_issue_i$7 \fus_cu_issue_i$19 + connect \cu_rd__go_i \fus_cu_rd__go_i + connect \cu_rd__go_i$29 \fus_cu_rd__go_i$41 + connect \cu_rd__go_i$32 \fus_cu_rd__go_i$44 + connect \cu_rd__go_i$35 \fus_cu_rd__go_i$47 + connect \cu_rd__go_i$38 \fus_cu_rd__go_i$50 + connect \cu_rd__go_i$41 \fus_cu_rd__go_i$53 + connect \cu_rd__go_i$44 \fus_cu_rd__go_i$56 + connect \cu_rd__go_i$47 \fus_cu_rd__go_i$59 + connect \cu_rd__go_i$50 \fus_cu_rd__go_i$62 + connect \cu_rd__go_i$70 \fus_cu_rd__go_i$82 + connect \cu_rd__rel_o \fus_cu_rd__rel_o + connect \cu_rd__rel_o$28 \fus_cu_rd__rel_o$40 + connect \cu_rd__rel_o$31 \fus_cu_rd__rel_o$43 + connect \cu_rd__rel_o$34 \fus_cu_rd__rel_o$46 + connect \cu_rd__rel_o$37 \fus_cu_rd__rel_o$49 + connect \cu_rd__rel_o$40 \fus_cu_rd__rel_o$52 + connect \cu_rd__rel_o$43 \fus_cu_rd__rel_o$55 + connect \cu_rd__rel_o$46 \fus_cu_rd__rel_o$58 + connect \cu_rd__rel_o$49 \fus_cu_rd__rel_o$61 + connect \cu_rd__rel_o$69 \fus_cu_rd__rel_o$81 + connect \cu_rdmaskn_i \fus_cu_rdmaskn_i + connect \cu_rdmaskn_i$12 \fus_cu_rdmaskn_i$24 + connect \cu_rdmaskn_i$15 \fus_cu_rdmaskn_i$27 + connect \cu_rdmaskn_i$18 \fus_cu_rdmaskn_i$30 + connect \cu_rdmaskn_i$21 \fus_cu_rdmaskn_i$33 + connect \cu_rdmaskn_i$24 \fus_cu_rdmaskn_i$36 + connect \cu_rdmaskn_i$27 \fus_cu_rdmaskn_i$39 + connect \cu_rdmaskn_i$3 \fus_cu_rdmaskn_i$15 + connect \cu_rdmaskn_i$6 \fus_cu_rdmaskn_i$18 + connect \cu_rdmaskn_i$9 \fus_cu_rdmaskn_i$21 + connect \cu_st__go_i \cu_st__go_i + connect \cu_st__rel_o \cu_st__rel_o + connect \cu_wr__go_i \fus_cu_wr__go_i + connect \cu_wr__go_i$100 \fus_cu_wr__go_i$112 + connect \cu_wr__go_i$102 \fus_cu_wr__go_i$114 + connect \cu_wr__go_i$137 \fus_cu_wr__go_i$149 + connect \cu_wr__go_i$82 \fus_cu_wr__go_i$94 + connect \cu_wr__go_i$85 \fus_cu_wr__go_i$97 + connect \cu_wr__go_i$88 \fus_cu_wr__go_i$100 + connect \cu_wr__go_i$91 \fus_cu_wr__go_i$103 + connect \cu_wr__go_i$94 \fus_cu_wr__go_i$106 + connect \cu_wr__go_i$97 \fus_cu_wr__go_i$109 + connect \cu_wr__rel_o \fus_cu_wr__rel_o + connect \cu_wr__rel_o$101 \fus_cu_wr__rel_o$113 + connect \cu_wr__rel_o$136 \fus_cu_wr__rel_o$148 + connect \cu_wr__rel_o$81 \fus_cu_wr__rel_o$93 + connect \cu_wr__rel_o$84 \fus_cu_wr__rel_o$96 + connect \cu_wr__rel_o$87 \fus_cu_wr__rel_o$99 + connect \cu_wr__rel_o$90 \fus_cu_wr__rel_o$102 + connect \cu_wr__rel_o$93 \fus_cu_wr__rel_o$105 + connect \cu_wr__rel_o$96 \fus_cu_wr__rel_o$108 + connect \cu_wr__rel_o$99 \fus_cu_wr__rel_o$111 + connect \dest1_o \fus_dest1_o + connect \dest1_o$103 \fus_dest1_o$115 + connect \dest1_o$104 \fus_dest1_o$116 + connect \dest1_o$105 \fus_dest1_o$117 + connect \dest1_o$106 \fus_dest1_o$118 + connect \dest1_o$107 \fus_dest1_o$119 + connect \dest1_o$108 \fus_dest1_o$120 + connect \dest1_o$109 \fus_dest1_o$121 + connect \dest1_o$141 \fus_dest1_o$153 + connect \dest2_o \fus_dest2_o + connect \dest2_o$115 \fus_dest2_o$127 + connect \dest2_o$116 \fus_dest2_o$128 + connect \dest2_o$117 \fus_dest2_o$129 + connect \dest2_o$118 \fus_dest2_o$130 + connect \dest2_o$119 \fus_dest2_o$131 + connect \dest2_o$142 \fus_dest2_o$154 + connect \dest2_o$144 \fus_dest2_o$156 + connect \dest2_o$150 \fus_dest2_o$162 + connect \dest3_o \fus_dest3_o + connect \dest3_o$122 \fus_dest3_o$134 + connect \dest3_o$123 \fus_dest3_o$135 + connect \dest3_o$127 \fus_dest3_o$139 + connect \dest3_o$128 \fus_dest3_o$140 + connect \dest3_o$143 \fus_dest3_o$155 + connect \dest3_o$145 \fus_dest3_o$157 + connect \dest3_o$147 \fus_dest3_o$159 + connect \dest4_o \fus_dest4_o + connect \dest4_o$133 \fus_dest4_o$145 + connect \dest4_o$134 \fus_dest4_o$146 + connect \dest4_o$135 \fus_dest4_o$147 + connect \dest4_o$148 \fus_dest4_o$160 + connect \dest5_o \fus_dest5_o + connect \dest5_o$132 \fus_dest5_o$144 + connect \dest5_o$149 \fus_dest5_o$161 + connect \dest6_o \fus_dest6_o + connect \ea \fus_ea + connect \fast1_ok \fus_fast1_ok + connect \fast1_ok$138 \fus_fast1_ok$150 + connect \fast1_ok$139 \fus_fast1_ok$151 + connect \fast2_ok \fus_fast2_ok + connect \fast2_ok$140 \fus_fast2_ok$152 + connect \full_cr_ok \fus_full_cr_ok + connect \ldst_port0_addr_i \fus_ldst_port0_addr_i + connect \ldst_port0_addr_i_ok \fus_ldst_port0_addr_i_ok + connect \ldst_port0_addr_ok_o \fus_ldst_port0_addr_ok_o + connect \ldst_port0_busy_o \fus_ldst_port0_busy_o + connect \ldst_port0_data_len \fus_ldst_port0_data_len + connect \ldst_port0_exc_$signal \fus_ldst_port0_exc_$signal + connect \ldst_port0_exc_$signal$151 \fus_ldst_port0_exc_$signal$163 + connect \ldst_port0_exc_$signal$152 \fus_ldst_port0_exc_$signal$164 + connect \ldst_port0_exc_$signal$153 \fus_ldst_port0_exc_$signal$165 + connect \ldst_port0_exc_$signal$154 \fus_ldst_port0_exc_$signal$166 + connect \ldst_port0_exc_$signal$155 \fus_ldst_port0_exc_$signal$167 + connect \ldst_port0_exc_$signal$156 \fus_ldst_port0_exc_$signal$168 + connect \ldst_port0_exc_$signal$157 \fus_ldst_port0_exc_$signal$169 + connect \ldst_port0_is_ld_i \fus_ldst_port0_is_ld_i + connect \ldst_port0_is_st_i \fus_ldst_port0_is_st_i + connect \ldst_port0_ld_data_o \fus_ldst_port0_ld_data_o + connect \ldst_port0_ld_data_o_ok \fus_ldst_port0_ld_data_o_ok + connect \ldst_port0_st_data_i \fus_ldst_port0_st_data_i + connect \ldst_port0_st_data_i_ok \fus_ldst_port0_st_data_i_ok + connect \msr_ok \fus_msr_ok + connect \nia_ok \fus_nia_ok + connect \nia_ok$146 \fus_nia_ok$158 + connect \o \fus_o + connect \o_ok \fus_o_ok + connect \o_ok$80 \fus_o_ok$92 + connect \o_ok$83 \fus_o_ok$95 + connect \o_ok$86 \fus_o_ok$98 + connect \o_ok$89 \fus_o_ok$101 + connect \o_ok$92 \fus_o_ok$104 + connect \o_ok$95 \fus_o_ok$107 + connect \o_ok$98 \fus_o_ok$110 + connect \oper_i_alu_alu0__data_len \fus_oper_i_alu_alu0__data_len + connect \oper_i_alu_alu0__fn_unit \fus_oper_i_alu_alu0__fn_unit + connect \oper_i_alu_alu0__imm_data__data \fus_oper_i_alu_alu0__imm_data__data + connect \oper_i_alu_alu0__imm_data__ok \fus_oper_i_alu_alu0__imm_data__ok + connect \oper_i_alu_alu0__input_carry \fus_oper_i_alu_alu0__input_carry + connect \oper_i_alu_alu0__insn \fus_oper_i_alu_alu0__insn + connect \oper_i_alu_alu0__insn_type \fus_oper_i_alu_alu0__insn_type + connect \oper_i_alu_alu0__invert_in \fus_oper_i_alu_alu0__invert_in + connect \oper_i_alu_alu0__invert_out \fus_oper_i_alu_alu0__invert_out + connect \oper_i_alu_alu0__is_32bit \fus_oper_i_alu_alu0__is_32bit + connect \oper_i_alu_alu0__is_signed \fus_oper_i_alu_alu0__is_signed + connect \oper_i_alu_alu0__oe__oe \fus_oper_i_alu_alu0__oe__oe + connect \oper_i_alu_alu0__oe__ok \fus_oper_i_alu_alu0__oe__ok + connect \oper_i_alu_alu0__output_carry \fus_oper_i_alu_alu0__output_carry + connect \oper_i_alu_alu0__rc__ok \fus_oper_i_alu_alu0__rc__ok + connect \oper_i_alu_alu0__rc__rc \fus_oper_i_alu_alu0__rc__rc + connect \oper_i_alu_alu0__write_cr0 \fus_oper_i_alu_alu0__write_cr0 + connect \oper_i_alu_alu0__zero_a \fus_oper_i_alu_alu0__zero_a + connect \oper_i_alu_branch0__cia \fus_oper_i_alu_branch0__cia + connect \oper_i_alu_branch0__fn_unit \fus_oper_i_alu_branch0__fn_unit + connect \oper_i_alu_branch0__imm_data__data \fus_oper_i_alu_branch0__imm_data__data + connect \oper_i_alu_branch0__imm_data__ok \fus_oper_i_alu_branch0__imm_data__ok + connect \oper_i_alu_branch0__insn \fus_oper_i_alu_branch0__insn + connect \oper_i_alu_branch0__insn_type \fus_oper_i_alu_branch0__insn_type + connect \oper_i_alu_branch0__is_32bit \fus_oper_i_alu_branch0__is_32bit + connect \oper_i_alu_branch0__lk \fus_oper_i_alu_branch0__lk + connect \oper_i_alu_cr0__fn_unit \fus_oper_i_alu_cr0__fn_unit + connect \oper_i_alu_cr0__insn \fus_oper_i_alu_cr0__insn + connect \oper_i_alu_cr0__insn_type \fus_oper_i_alu_cr0__insn_type + connect \oper_i_alu_div0__data_len \fus_oper_i_alu_div0__data_len + connect \oper_i_alu_div0__fn_unit \fus_oper_i_alu_div0__fn_unit + connect \oper_i_alu_div0__imm_data__data \fus_oper_i_alu_div0__imm_data__data + connect \oper_i_alu_div0__imm_data__ok \fus_oper_i_alu_div0__imm_data__ok + connect \oper_i_alu_div0__input_carry \fus_oper_i_alu_div0__input_carry + connect \oper_i_alu_div0__insn \fus_oper_i_alu_div0__insn + connect \oper_i_alu_div0__insn_type \fus_oper_i_alu_div0__insn_type + connect \oper_i_alu_div0__invert_in \fus_oper_i_alu_div0__invert_in + connect \oper_i_alu_div0__invert_out \fus_oper_i_alu_div0__invert_out + connect \oper_i_alu_div0__is_32bit \fus_oper_i_alu_div0__is_32bit + connect \oper_i_alu_div0__is_signed \fus_oper_i_alu_div0__is_signed + connect \oper_i_alu_div0__oe__oe \fus_oper_i_alu_div0__oe__oe + connect \oper_i_alu_div0__oe__ok \fus_oper_i_alu_div0__oe__ok + connect \oper_i_alu_div0__output_carry \fus_oper_i_alu_div0__output_carry + connect \oper_i_alu_div0__rc__ok \fus_oper_i_alu_div0__rc__ok + connect \oper_i_alu_div0__rc__rc \fus_oper_i_alu_div0__rc__rc + connect \oper_i_alu_div0__write_cr0 \fus_oper_i_alu_div0__write_cr0 + connect \oper_i_alu_div0__zero_a \fus_oper_i_alu_div0__zero_a + connect \oper_i_alu_logical0__data_len \fus_oper_i_alu_logical0__data_len + connect \oper_i_alu_logical0__fn_unit \fus_oper_i_alu_logical0__fn_unit + connect \oper_i_alu_logical0__imm_data__data \fus_oper_i_alu_logical0__imm_data__data + connect \oper_i_alu_logical0__imm_data__ok \fus_oper_i_alu_logical0__imm_data__ok + connect \oper_i_alu_logical0__input_carry \fus_oper_i_alu_logical0__input_carry + connect \oper_i_alu_logical0__insn \fus_oper_i_alu_logical0__insn + connect \oper_i_alu_logical0__insn_type \fus_oper_i_alu_logical0__insn_type + connect \oper_i_alu_logical0__invert_in \fus_oper_i_alu_logical0__invert_in + connect \oper_i_alu_logical0__invert_out \fus_oper_i_alu_logical0__invert_out + connect \oper_i_alu_logical0__is_32bit \fus_oper_i_alu_logical0__is_32bit + connect \oper_i_alu_logical0__is_signed \fus_oper_i_alu_logical0__is_signed + connect \oper_i_alu_logical0__oe__oe \fus_oper_i_alu_logical0__oe__oe + connect \oper_i_alu_logical0__oe__ok \fus_oper_i_alu_logical0__oe__ok + connect \oper_i_alu_logical0__output_carry \fus_oper_i_alu_logical0__output_carry + connect \oper_i_alu_logical0__rc__ok \fus_oper_i_alu_logical0__rc__ok + connect \oper_i_alu_logical0__rc__rc \fus_oper_i_alu_logical0__rc__rc + connect \oper_i_alu_logical0__write_cr0 \fus_oper_i_alu_logical0__write_cr0 + connect \oper_i_alu_logical0__zero_a \fus_oper_i_alu_logical0__zero_a + connect \oper_i_alu_mul0__fn_unit \fus_oper_i_alu_mul0__fn_unit + connect \oper_i_alu_mul0__imm_data__data \fus_oper_i_alu_mul0__imm_data__data + connect \oper_i_alu_mul0__imm_data__ok \fus_oper_i_alu_mul0__imm_data__ok + connect \oper_i_alu_mul0__insn \fus_oper_i_alu_mul0__insn + connect \oper_i_alu_mul0__insn_type \fus_oper_i_alu_mul0__insn_type + connect \oper_i_alu_mul0__is_32bit \fus_oper_i_alu_mul0__is_32bit + connect \oper_i_alu_mul0__is_signed \fus_oper_i_alu_mul0__is_signed + connect \oper_i_alu_mul0__oe__oe \fus_oper_i_alu_mul0__oe__oe + connect \oper_i_alu_mul0__oe__ok \fus_oper_i_alu_mul0__oe__ok + connect \oper_i_alu_mul0__rc__ok \fus_oper_i_alu_mul0__rc__ok + connect \oper_i_alu_mul0__rc__rc \fus_oper_i_alu_mul0__rc__rc + connect \oper_i_alu_mul0__write_cr0 \fus_oper_i_alu_mul0__write_cr0 + connect \oper_i_alu_shift_rot0__fn_unit \fus_oper_i_alu_shift_rot0__fn_unit + connect \oper_i_alu_shift_rot0__imm_data__data \fus_oper_i_alu_shift_rot0__imm_data__data + connect \oper_i_alu_shift_rot0__imm_data__ok \fus_oper_i_alu_shift_rot0__imm_data__ok + connect \oper_i_alu_shift_rot0__input_carry \fus_oper_i_alu_shift_rot0__input_carry + connect \oper_i_alu_shift_rot0__input_cr \fus_oper_i_alu_shift_rot0__input_cr + connect \oper_i_alu_shift_rot0__insn \fus_oper_i_alu_shift_rot0__insn + connect \oper_i_alu_shift_rot0__insn_type \fus_oper_i_alu_shift_rot0__insn_type + connect \oper_i_alu_shift_rot0__invert_in \fus_oper_i_alu_shift_rot0__invert_in + connect \oper_i_alu_shift_rot0__is_32bit \fus_oper_i_alu_shift_rot0__is_32bit + connect \oper_i_alu_shift_rot0__is_signed \fus_oper_i_alu_shift_rot0__is_signed + connect \oper_i_alu_shift_rot0__oe__oe \fus_oper_i_alu_shift_rot0__oe__oe + connect \oper_i_alu_shift_rot0__oe__ok \fus_oper_i_alu_shift_rot0__oe__ok + connect \oper_i_alu_shift_rot0__output_carry \fus_oper_i_alu_shift_rot0__output_carry + connect \oper_i_alu_shift_rot0__output_cr \fus_oper_i_alu_shift_rot0__output_cr + connect \oper_i_alu_shift_rot0__rc__ok \fus_oper_i_alu_shift_rot0__rc__ok + connect \oper_i_alu_shift_rot0__rc__rc \fus_oper_i_alu_shift_rot0__rc__rc + connect \oper_i_alu_shift_rot0__write_cr0 \fus_oper_i_alu_shift_rot0__write_cr0 + connect \oper_i_alu_spr0__fn_unit \fus_oper_i_alu_spr0__fn_unit + connect \oper_i_alu_spr0__insn \fus_oper_i_alu_spr0__insn + connect \oper_i_alu_spr0__insn_type \fus_oper_i_alu_spr0__insn_type + connect \oper_i_alu_spr0__is_32bit \fus_oper_i_alu_spr0__is_32bit + connect \oper_i_alu_trap0__cia \fus_oper_i_alu_trap0__cia + connect \oper_i_alu_trap0__fn_unit \fus_oper_i_alu_trap0__fn_unit + connect \oper_i_alu_trap0__insn \fus_oper_i_alu_trap0__insn + connect \oper_i_alu_trap0__insn_type \fus_oper_i_alu_trap0__insn_type + connect \oper_i_alu_trap0__is_32bit \fus_oper_i_alu_trap0__is_32bit + connect \oper_i_alu_trap0__ldst_exc \fus_oper_i_alu_trap0__ldst_exc + connect \oper_i_alu_trap0__msr \fus_oper_i_alu_trap0__msr + connect \oper_i_alu_trap0__trapaddr \fus_oper_i_alu_trap0__trapaddr + connect \oper_i_alu_trap0__traptype \fus_oper_i_alu_trap0__traptype + connect \oper_i_ldst_ldst0__byte_reverse \fus_oper_i_ldst_ldst0__byte_reverse + connect \oper_i_ldst_ldst0__data_len \fus_oper_i_ldst_ldst0__data_len + connect \oper_i_ldst_ldst0__fn_unit \fus_oper_i_ldst_ldst0__fn_unit + connect \oper_i_ldst_ldst0__imm_data__data \fus_oper_i_ldst_ldst0__imm_data__data + connect \oper_i_ldst_ldst0__imm_data__ok \fus_oper_i_ldst_ldst0__imm_data__ok + connect \oper_i_ldst_ldst0__insn \fus_oper_i_ldst_ldst0__insn + connect \oper_i_ldst_ldst0__insn_type \fus_oper_i_ldst_ldst0__insn_type + connect \oper_i_ldst_ldst0__is_32bit \fus_oper_i_ldst_ldst0__is_32bit + connect \oper_i_ldst_ldst0__is_signed \fus_oper_i_ldst_ldst0__is_signed + connect \oper_i_ldst_ldst0__ldst_mode \fus_oper_i_ldst_ldst0__ldst_mode + connect \oper_i_ldst_ldst0__oe__oe \fus_oper_i_ldst_ldst0__oe__oe + connect \oper_i_ldst_ldst0__oe__ok \fus_oper_i_ldst_ldst0__oe__ok + connect \oper_i_ldst_ldst0__rc__ok \fus_oper_i_ldst_ldst0__rc__ok + connect \oper_i_ldst_ldst0__rc__rc \fus_oper_i_ldst_ldst0__rc__rc + connect \oper_i_ldst_ldst0__sign_extend \fus_oper_i_ldst_ldst0__sign_extend + connect \oper_i_ldst_ldst0__zero_a \fus_oper_i_ldst_ldst0__zero_a + connect \spr1_ok \fus_spr1_ok + connect \src1_i \fus_src1_i + connect \src1_i$30 \fus_src1_i$42 + connect \src1_i$33 \fus_src1_i$45 + connect \src1_i$36 \fus_src1_i$48 + connect \src1_i$39 \fus_src1_i$51 + connect \src1_i$42 \fus_src1_i$54 + connect \src1_i$45 \fus_src1_i$57 + connect \src1_i$48 \fus_src1_i$60 + connect \src1_i$51 \fus_src1_i$63 + connect \src1_i$74 \fus_src1_i$86 + connect \src2_i \fus_src2_i + connect \src2_i$52 \fus_src2_i$64 + connect \src2_i$53 \fus_src2_i$65 + connect \src2_i$54 \fus_src2_i$66 + connect \src2_i$55 \fus_src2_i$67 + connect \src2_i$56 \fus_src2_i$68 + connect \src2_i$57 \fus_src2_i$69 + connect \src2_i$58 \fus_src2_i$70 + connect \src2_i$77 \fus_src2_i$89 + connect \src2_i$79 \fus_src2_i$91 + connect \src3_i \fus_src3_i + connect \src3_i$59 \fus_src3_i$71 + connect \src3_i$60 \fus_src3_i$72 + connect \src3_i$61 \fus_src3_i$73 + connect \src3_i$62 \fus_src3_i$74 + connect \src3_i$63 \fus_src3_i$75 + connect \src3_i$67 \fus_src3_i$79 + connect \src3_i$71 \fus_src3_i$83 + connect \src3_i$75 \fus_src3_i$87 + connect \src3_i$76 \fus_src3_i$88 + connect \src4_i \fus_src4_i + connect \src4_i$64 \fus_src4_i$76 + connect \src4_i$65 \fus_src4_i$77 + connect \src4_i$68 \fus_src4_i$80 + connect \src4_i$78 \fus_src4_i$90 + connect \src5_i \fus_src5_i + connect \src5_i$66 \fus_src5_i$78 + connect \src5_i$72 \fus_src5_i$84 + connect \src6_i \fus_src6_i + connect \src6_i$73 \fus_src6_i$85 + connect \xer_ca_ok \fus_xer_ca_ok + connect \xer_ca_ok$120 \fus_xer_ca_ok$132 + connect \xer_ca_ok$121 \fus_xer_ca_ok$133 + connect \xer_ov_ok \fus_xer_ov_ok + connect \xer_ov_ok$124 \fus_xer_ov_ok$136 + connect \xer_ov_ok$125 \fus_xer_ov_ok$137 + connect \xer_ov_ok$126 \fus_xer_ov_ok$138 + connect \xer_so_ok \fus_xer_so_ok + connect \xer_so_ok$129 \fus_xer_so_ok$141 + connect \xer_so_ok$130 \fus_xer_so_ok$142 + connect \xer_so_ok$131 \fus_xer_so_ok$143 + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:43212.9-43230.4" + cell \int \int + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \dest1__addr \int_dest1__addr + connect \dest1__data_i \int_dest1__data_i + connect \dest1__wen \int_dest1__wen + connect \dmi__addr \dmi__addr + connect \dmi__data_o \dmi__data_o + connect \dmi__ren \dmi__ren + connect \src1__addr \int_src1__addr + connect \src1__data_o \int_src1__data_o + connect \src1__ren \int_src1__ren + connect \src2__addr \int_src2__addr + connect \src2__data_o \int_src2__data_o + connect \src2__ren \int_src2__ren + connect \src3__addr \int_src3__addr + connect \src3__data_o \int_src3__data_o + connect \src3__ren \int_src3__ren + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:43231.6-43263.4" + cell \l0 \l0 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \dbus__ack \dbus__ack + connect \dbus__adr \dbus__adr + connect \dbus__cyc \dbus__cyc + connect \dbus__dat_r \dbus__dat_r + connect \dbus__dat_w \dbus__dat_w + connect \dbus__err \dbus__err + connect \dbus__sel \dbus__sel + connect \dbus__stb \dbus__stb + connect \dbus__we \dbus__we + connect \ldst_port0_addr_i \fus_ldst_port0_addr_i + connect \ldst_port0_addr_i_ok \fus_ldst_port0_addr_i_ok + connect \ldst_port0_addr_ok_o \fus_ldst_port0_addr_ok_o + connect \ldst_port0_busy_o \fus_ldst_port0_busy_o + connect \ldst_port0_data_len \fus_ldst_port0_data_len + connect \ldst_port0_exc_$signal \fus_ldst_port0_exc_$signal + connect \ldst_port0_exc_$signal$1 \fus_ldst_port0_exc_$signal$163 + connect \ldst_port0_exc_$signal$2 \fus_ldst_port0_exc_$signal$164 + connect \ldst_port0_exc_$signal$3 \fus_ldst_port0_exc_$signal$165 + connect \ldst_port0_exc_$signal$4 \fus_ldst_port0_exc_$signal$166 + connect \ldst_port0_exc_$signal$5 \fus_ldst_port0_exc_$signal$167 + connect \ldst_port0_exc_$signal$6 \fus_ldst_port0_exc_$signal$168 + connect \ldst_port0_exc_$signal$7 \fus_ldst_port0_exc_$signal$169 + connect \ldst_port0_is_ld_i \fus_ldst_port0_is_ld_i + connect \ldst_port0_is_st_i \fus_ldst_port0_is_st_i + connect \ldst_port0_ld_data_o \fus_ldst_port0_ld_data_o + connect \ldst_port0_ld_data_o_ok \fus_ldst_port0_ld_data_o_ok + connect \ldst_port0_st_data_i \fus_ldst_port0_st_data_i + connect \ldst_port0_st_data_i_ok \fus_ldst_port0_st_data_i_ok + connect \wb_dcache_en \wb_dcache_en + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:43264.18-43268.4" + cell \rdpick_CR_cr_a \rdpick_CR_cr_a + connect \en_o \rdpick_CR_cr_a_en_o + connect \i \rdpick_CR_cr_a_i + connect \o \rdpick_CR_cr_a_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:43269.18-43273.4" + cell \rdpick_CR_cr_b \rdpick_CR_cr_b + connect \en_o \rdpick_CR_cr_b_en_o + connect \i \rdpick_CR_cr_b_i + connect \o \rdpick_CR_cr_b_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:43274.18-43278.4" + cell \rdpick_CR_cr_c \rdpick_CR_cr_c + connect \en_o \rdpick_CR_cr_c_en_o + connect \i \rdpick_CR_cr_c_i + connect \o \rdpick_CR_cr_c_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:43279.21-43283.4" + cell \rdpick_CR_full_cr \rdpick_CR_full_cr + connect \en_o \rdpick_CR_full_cr_en_o + connect \i \rdpick_CR_full_cr_i + connect \o \rdpick_CR_full_cr_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:43284.21-43288.4" + cell \rdpick_FAST_fast1 \rdpick_FAST_fast1 + connect \en_o \rdpick_FAST_fast1_en_o + connect \i \rdpick_FAST_fast1_i + connect \o \rdpick_FAST_fast1_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:43289.21-43293.4" + cell \rdpick_FAST_fast2 \rdpick_FAST_fast2 + connect \en_o \rdpick_FAST_fast2_en_o + connect \i \rdpick_FAST_fast2_i + connect \o \rdpick_FAST_fast2_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:43294.17-43298.4" + cell \rdpick_INT_ra \rdpick_INT_ra + connect \en_o \rdpick_INT_ra_en_o + connect \i \rdpick_INT_ra_i + connect \o \rdpick_INT_ra_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:43299.17-43303.4" + cell \rdpick_INT_rb \rdpick_INT_rb + connect \en_o \rdpick_INT_rb_en_o + connect \i \rdpick_INT_rb_i + connect \o \rdpick_INT_rb_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:43304.17-43308.4" + cell \rdpick_INT_rc \rdpick_INT_rc + connect \en_o \rdpick_INT_rc_en_o + connect \i \rdpick_INT_rc_i + connect \o \rdpick_INT_rc_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:43309.19-43313.4" + cell \rdpick_SPR_spr1 \rdpick_SPR_spr1 + connect \en_o \rdpick_SPR_spr1_en_o + connect \i \rdpick_SPR_spr1_i + connect \o \rdpick_SPR_spr1_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:43314.21-43318.4" + cell \rdpick_XER_xer_ca \rdpick_XER_xer_ca + connect \en_o \rdpick_XER_xer_ca_en_o + connect \i \rdpick_XER_xer_ca_i + connect \o \rdpick_XER_xer_ca_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:43319.21-43323.4" + cell \rdpick_XER_xer_ov \rdpick_XER_xer_ov + connect \en_o \rdpick_XER_xer_ov_en_o + connect \i \rdpick_XER_xer_ov_i + connect \o \rdpick_XER_xer_ov_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:43324.21-43328.4" + cell \rdpick_XER_xer_so \rdpick_XER_xer_so + connect \en_o \rdpick_XER_xer_so_en_o + connect \i \rdpick_XER_xer_so_i + connect \o \rdpick_XER_xer_so_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:43329.7-43338.4" + cell \spr \spr + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \spr1__addr \spr_spr1__addr + connect \spr1__addr$1 \spr_spr1__addr$175 + connect \spr1__data_i \spr_spr1__data_i + connect \spr1__data_o \spr_spr1__data_o + connect \spr1__ren \spr_spr1__ren + connect \spr1__wen \spr_spr1__wen + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:43339.9-43356.4" + cell \state \state + connect \cia__data_o \cia__data_o + connect \cia__ren \cia__ren + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \data_i \data_i + connect \data_i$2 \data_i$11 + connect \data_i$3 \state_data_i + connect \data_i$4 \state_data_i$174 + connect \msr__data_o \msr__data_o + connect \msr__ren \msr__ren + connect \state_nia_wen \state_nia_wen + connect \sv__data_o \sv__data_o + connect \sv__ren \sv__ren + connect \wen \wen + connect \wen$1 \wen$10 + connect \wen$5 \state_wen + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:43357.18-43361.4" + cell \wrpick_CR_cr_a \wrpick_CR_cr_a + connect \en_o \wrpick_CR_cr_a_en_o + connect \i \wrpick_CR_cr_a_i + connect \o \wrpick_CR_cr_a_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:43362.21-43366.4" + cell \wrpick_CR_full_cr \wrpick_CR_full_cr + connect \en_o \wrpick_CR_full_cr_en_o + connect \i \wrpick_CR_full_cr_i + connect \o \wrpick_CR_full_cr_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:43367.21-43371.4" + cell \wrpick_FAST_fast1 \wrpick_FAST_fast1 + connect \en_o \wrpick_FAST_fast1_en_o + connect \i \wrpick_FAST_fast1_i + connect \o \wrpick_FAST_fast1_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:43372.16-43376.4" + cell \wrpick_INT_o \wrpick_INT_o + connect \en_o \wrpick_INT_o_en_o + connect \i \wrpick_INT_o_i + connect \o \wrpick_INT_o_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:43377.19-43381.4" + cell \wrpick_SPR_spr1 \wrpick_SPR_spr1 + connect \en_o \wrpick_SPR_spr1_en_o + connect \i \wrpick_SPR_spr1_i + connect \o \wrpick_SPR_spr1_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:43382.20-43386.4" + cell \wrpick_STATE_msr \wrpick_STATE_msr + connect \en_o \wrpick_STATE_msr_en_o + connect \i \wrpick_STATE_msr_i + connect \o \wrpick_STATE_msr_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:43387.20-43391.4" + cell \wrpick_STATE_nia \wrpick_STATE_nia + connect \en_o \wrpick_STATE_nia_en_o + connect \i \wrpick_STATE_nia_i + connect \o \wrpick_STATE_nia_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:43392.21-43396.4" + cell \wrpick_XER_xer_ca \wrpick_XER_xer_ca + connect \en_o \wrpick_XER_xer_ca_en_o + connect \i \wrpick_XER_xer_ca_i + connect \o \wrpick_XER_xer_ca_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:43397.21-43401.4" + cell \wrpick_XER_xer_ov \wrpick_XER_xer_ov + connect \en_o \wrpick_XER_xer_ov_en_o + connect \i \wrpick_XER_xer_ov_i + connect \o \wrpick_XER_xer_ov_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:43402.21-43406.4" + cell \wrpick_XER_xer_so \wrpick_XER_xer_so + connect \en_o \wrpick_XER_xer_so_en_o + connect \i \wrpick_XER_xer_so_i + connect \o \wrpick_XER_xer_so_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:43407.7-43424.4" + cell \xer \xer + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \data_i \xer_data_i + connect \data_i$1 \xer_data_i$170 + connect \data_i$3 \xer_data_i$172 + connect \full_rd__data_o \full_rd__data_o + connect \full_rd__ren \full_rd__ren + connect \src1__data_o \xer_src1__data_o + connect \src1__ren \xer_src1__ren + connect \src2__data_o \xer_src2__data_o + connect \src2__ren \xer_src2__ren + connect \src3__data_o \xer_src3__data_o + connect \src3__ren \xer_src3__ren + connect \wen \xer_wen + connect \wen$2 \xer_wen$171 + connect \wen$4 \xer_wen$173 + end + attribute \src "libresoc.v:35982.7-35982.20" + process $proc$libresoc.v:35982$2900 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:38027.7-38027.30" + process $proc$libresoc.v:38027$2901 + assign { } { } + assign $1\core_terminate_o[0:0] 1'0 + sync always + sync init + update \core_terminate_o $1\core_terminate_o[0:0] + end + attribute \src "libresoc.v:38040.13-38040.27" + process $proc$libresoc.v:38040$2902 + assign { } { } + assign $1\counter[1:0] 2'00 + sync always + sync init + update \counter $1\counter[1:0] + end + attribute \src "libresoc.v:39181.7-39181.34" + process $proc$libresoc.v:39181$2903 + assign { } { } + assign $1\dp_CR_cr_a_branch0_1[0:0] 1'0 + sync always + sync init + update \dp_CR_cr_a_branch0_1 $1\dp_CR_cr_a_branch0_1[0:0] + end + attribute \src "libresoc.v:39185.7-39185.30" + process $proc$libresoc.v:39185$2904 + assign { } { } + assign $1\dp_CR_cr_a_cr0_0[0:0] 1'0 + sync always + sync init + update \dp_CR_cr_a_cr0_0 $1\dp_CR_cr_a_cr0_0[0:0] + end + attribute \src "libresoc.v:39189.7-39189.30" + process $proc$libresoc.v:39189$2905 + assign { } { } + assign $1\dp_CR_cr_b_cr0_0[0:0] 1'0 + sync always + sync init + update \dp_CR_cr_b_cr0_0 $1\dp_CR_cr_b_cr0_0[0:0] + end + attribute \src "libresoc.v:39193.7-39193.30" + process $proc$libresoc.v:39193$2906 + assign { } { } + assign $1\dp_CR_cr_c_cr0_0[0:0] 1'0 + sync always + sync init + update \dp_CR_cr_c_cr0_0 $1\dp_CR_cr_c_cr0_0[0:0] + end + attribute \src "libresoc.v:39197.7-39197.33" + process $proc$libresoc.v:39197$2907 + assign { } { } + assign $1\dp_CR_full_cr_cr0_0[0:0] 1'0 + sync always + sync init + update \dp_CR_full_cr_cr0_0 $1\dp_CR_full_cr_cr0_0[0:0] + end + attribute \src "libresoc.v:39201.7-39201.37" + process $proc$libresoc.v:39201$2908 + assign { } { } + assign $1\dp_FAST_fast1_branch0_0[0:0] 1'0 + sync always + sync init + update \dp_FAST_fast1_branch0_0 $1\dp_FAST_fast1_branch0_0[0:0] + end + attribute \src "libresoc.v:39205.7-39205.34" + process $proc$libresoc.v:39205$2909 + assign { } { } + assign $1\dp_FAST_fast1_spr0_2[0:0] 1'0 + sync always + sync init + update \dp_FAST_fast1_spr0_2 $1\dp_FAST_fast1_spr0_2[0:0] + end + attribute \src "libresoc.v:39209.7-39209.35" + process $proc$libresoc.v:39209$2910 + assign { } { } + assign $1\dp_FAST_fast1_trap0_1[0:0] 1'0 + sync always + sync init + update \dp_FAST_fast1_trap0_1 $1\dp_FAST_fast1_trap0_1[0:0] + end + attribute \src "libresoc.v:39213.7-39213.37" + process $proc$libresoc.v:39213$2911 + assign { } { } + assign $1\dp_FAST_fast2_branch0_0[0:0] 1'0 + sync always + sync init + update \dp_FAST_fast2_branch0_0 $1\dp_FAST_fast2_branch0_0[0:0] + end + attribute \src "libresoc.v:39217.7-39217.35" + process $proc$libresoc.v:39217$2912 + assign { } { } + assign $1\dp_FAST_fast2_trap0_1[0:0] 1'0 + sync always + sync init + update \dp_FAST_fast2_trap0_1 $1\dp_FAST_fast2_trap0_1[0:0] + end + attribute \src "libresoc.v:39221.7-39221.30" + process $proc$libresoc.v:39221$2913 + assign { } { } + assign $1\dp_INT_ra_alu0_0[0:0] 1'0 + sync always + sync init + update \dp_INT_ra_alu0_0 $1\dp_INT_ra_alu0_0[0:0] + end + attribute \src "libresoc.v:39225.7-39225.29" + process $proc$libresoc.v:39225$2914 + assign { } { } + assign $1\dp_INT_ra_cr0_1[0:0] 1'0 + sync always + sync init + update \dp_INT_ra_cr0_1 $1\dp_INT_ra_cr0_1[0:0] + end + attribute \src "libresoc.v:39229.7-39229.30" + process $proc$libresoc.v:39229$2915 + assign { } { } + assign $1\dp_INT_ra_div0_5[0:0] 1'0 + sync always + sync init + update \dp_INT_ra_div0_5 $1\dp_INT_ra_div0_5[0:0] + end + attribute \src "libresoc.v:39233.7-39233.31" + process $proc$libresoc.v:39233$2916 + assign { } { } + assign $1\dp_INT_ra_ldst0_8[0:0] 1'0 + sync always + sync init + update \dp_INT_ra_ldst0_8 $1\dp_INT_ra_ldst0_8[0:0] + end + attribute \src "libresoc.v:39237.7-39237.34" + process $proc$libresoc.v:39237$2917 + assign { } { } + assign $1\dp_INT_ra_logical0_3[0:0] 1'0 + sync always + sync init + update \dp_INT_ra_logical0_3 $1\dp_INT_ra_logical0_3[0:0] + end + attribute \src "libresoc.v:39241.7-39241.30" + process $proc$libresoc.v:39241$2918 + assign { } { } + assign $1\dp_INT_ra_mul0_6[0:0] 1'0 + sync always + sync init + update \dp_INT_ra_mul0_6 $1\dp_INT_ra_mul0_6[0:0] + end + attribute \src "libresoc.v:39245.7-39245.35" + process $proc$libresoc.v:39245$2919 + assign { } { } + assign $1\dp_INT_ra_shiftrot0_7[0:0] 1'0 + sync always + sync init + update \dp_INT_ra_shiftrot0_7 $1\dp_INT_ra_shiftrot0_7[0:0] + end + attribute \src "libresoc.v:39249.7-39249.30" + process $proc$libresoc.v:39249$2920 + assign { } { } + assign $1\dp_INT_ra_spr0_4[0:0] 1'0 + sync always + sync init + update \dp_INT_ra_spr0_4 $1\dp_INT_ra_spr0_4[0:0] + end + attribute \src "libresoc.v:39253.7-39253.31" + process $proc$libresoc.v:39253$2921 + assign { } { } + assign $1\dp_INT_ra_trap0_2[0:0] 1'0 + sync always + sync init + update \dp_INT_ra_trap0_2 $1\dp_INT_ra_trap0_2[0:0] + end + attribute \src "libresoc.v:39257.7-39257.30" + process $proc$libresoc.v:39257$2922 + assign { } { } + assign $1\dp_INT_rb_alu0_0[0:0] 1'0 + sync always + sync init + update \dp_INT_rb_alu0_0 $1\dp_INT_rb_alu0_0[0:0] + end + attribute \src "libresoc.v:39261.7-39261.29" + process $proc$libresoc.v:39261$2923 + assign { } { } + assign $1\dp_INT_rb_cr0_1[0:0] 1'0 + sync always + sync init + update \dp_INT_rb_cr0_1 $1\dp_INT_rb_cr0_1[0:0] + end + attribute \src "libresoc.v:39265.7-39265.30" + process $proc$libresoc.v:39265$2924 + assign { } { } + assign $1\dp_INT_rb_div0_4[0:0] 1'0 + sync always + sync init + update \dp_INT_rb_div0_4 $1\dp_INT_rb_div0_4[0:0] + end + attribute \src "libresoc.v:39269.7-39269.31" + process $proc$libresoc.v:39269$2925 + assign { } { } + assign $1\dp_INT_rb_ldst0_7[0:0] 1'0 + sync always + sync init + update \dp_INT_rb_ldst0_7 $1\dp_INT_rb_ldst0_7[0:0] + end + attribute \src "libresoc.v:39273.7-39273.34" + process $proc$libresoc.v:39273$2926 + assign { } { } + assign $1\dp_INT_rb_logical0_3[0:0] 1'0 + sync always + sync init + update \dp_INT_rb_logical0_3 $1\dp_INT_rb_logical0_3[0:0] + end + attribute \src "libresoc.v:39277.7-39277.30" + process $proc$libresoc.v:39277$2927 + assign { } { } + assign $1\dp_INT_rb_mul0_5[0:0] 1'0 + sync always + sync init + update \dp_INT_rb_mul0_5 $1\dp_INT_rb_mul0_5[0:0] + end + attribute \src "libresoc.v:39281.7-39281.35" + process $proc$libresoc.v:39281$2928 + assign { } { } + assign $1\dp_INT_rb_shiftrot0_6[0:0] 1'0 + sync always + sync init + update \dp_INT_rb_shiftrot0_6 $1\dp_INT_rb_shiftrot0_6[0:0] + end + attribute \src "libresoc.v:39285.7-39285.31" + process $proc$libresoc.v:39285$2929 + assign { } { } + assign $1\dp_INT_rb_trap0_2[0:0] 1'0 + sync always + sync init + update \dp_INT_rb_trap0_2 $1\dp_INT_rb_trap0_2[0:0] + end + attribute \src "libresoc.v:39289.7-39289.31" + process $proc$libresoc.v:39289$2930 + assign { } { } + assign $1\dp_INT_rc_ldst0_1[0:0] 1'0 + sync always + sync init + update \dp_INT_rc_ldst0_1 $1\dp_INT_rc_ldst0_1[0:0] + end + attribute \src "libresoc.v:39293.7-39293.35" + process $proc$libresoc.v:39293$2931 + assign { } { } + assign $1\dp_INT_rc_shiftrot0_0[0:0] 1'0 + sync always + sync init + update \dp_INT_rc_shiftrot0_0 $1\dp_INT_rc_shiftrot0_0[0:0] + end + attribute \src "libresoc.v:39297.7-39297.32" + process $proc$libresoc.v:39297$2932 + assign { } { } + assign $1\dp_SPR_spr1_spr0_0[0:0] 1'0 + sync always + sync init + update \dp_SPR_spr1_spr0_0 $1\dp_SPR_spr1_spr0_0[0:0] + end + attribute \src "libresoc.v:39301.7-39301.34" + process $proc$libresoc.v:39301$2933 + assign { } { } + assign $1\dp_XER_xer_ca_alu0_0[0:0] 1'0 + sync always + sync init + update \dp_XER_xer_ca_alu0_0 $1\dp_XER_xer_ca_alu0_0[0:0] + end + attribute \src "libresoc.v:39305.7-39305.39" + process $proc$libresoc.v:39305$2934 + assign { } { } + assign $1\dp_XER_xer_ca_shiftrot0_2[0:0] 1'0 + sync always + sync init + update \dp_XER_xer_ca_shiftrot0_2 $1\dp_XER_xer_ca_shiftrot0_2[0:0] + end + attribute \src "libresoc.v:39309.7-39309.34" + process $proc$libresoc.v:39309$2935 + assign { } { } + assign $1\dp_XER_xer_ca_spr0_1[0:0] 1'0 + sync always + sync init + update \dp_XER_xer_ca_spr0_1 $1\dp_XER_xer_ca_spr0_1[0:0] + end + attribute \src "libresoc.v:39313.7-39313.34" + process $proc$libresoc.v:39313$2936 + assign { } { } + assign $1\dp_XER_xer_ov_spr0_0[0:0] 1'0 + sync always + sync init + update \dp_XER_xer_ov_spr0_0 $1\dp_XER_xer_ov_spr0_0[0:0] + end + attribute \src "libresoc.v:39317.7-39317.34" + process $proc$libresoc.v:39317$2937 + assign { } { } + assign $1\dp_XER_xer_so_alu0_0[0:0] 1'0 + sync always + sync init + update \dp_XER_xer_so_alu0_0 $1\dp_XER_xer_so_alu0_0[0:0] + end + attribute \src "libresoc.v:39321.7-39321.34" + process $proc$libresoc.v:39321$2938 + assign { } { } + assign $1\dp_XER_xer_so_div0_3[0:0] 1'0 + sync always + sync init + update \dp_XER_xer_so_div0_3 $1\dp_XER_xer_so_div0_3[0:0] + end + attribute \src "libresoc.v:39325.7-39325.38" + process $proc$libresoc.v:39325$2939 + assign { } { } + assign $1\dp_XER_xer_so_logical0_1[0:0] 1'0 + sync always + sync init + update \dp_XER_xer_so_logical0_1 $1\dp_XER_xer_so_logical0_1[0:0] + end + attribute \src "libresoc.v:39329.7-39329.34" + process $proc$libresoc.v:39329$2940 + assign { } { } + assign $1\dp_XER_xer_so_mul0_4[0:0] 1'0 + sync always + sync init + update \dp_XER_xer_so_mul0_4 $1\dp_XER_xer_so_mul0_4[0:0] + end + attribute \src "libresoc.v:39333.7-39333.39" + process $proc$libresoc.v:39333$2941 + assign { } { } + assign $1\dp_XER_xer_so_shiftrot0_5[0:0] 1'0 + sync always + sync init + update \dp_XER_xer_so_shiftrot0_5 $1\dp_XER_xer_so_shiftrot0_5[0:0] + end + attribute \src "libresoc.v:39337.7-39337.34" + process $proc$libresoc.v:39337$2942 + assign { } { } + assign $1\dp_XER_xer_so_spr0_2[0:0] 1'0 + sync always + sync init + update \dp_XER_xer_so_spr0_2 $1\dp_XER_xer_so_spr0_2[0:0] + end + attribute \src "libresoc.v:41430.7-41430.25" + process $proc$libresoc.v:41430$2943 + assign { } { } + assign $1\wr_pick_dly[0:0] 1'0 + sync always + sync init + update \wr_pick_dly $1\wr_pick_dly[0:0] + end + attribute \src "libresoc.v:41432.7-41432.32" + process $proc$libresoc.v:41432$2944 + assign { } { } + assign $0\wr_pick_dly$1005[0:0]$2945 1'0 + sync always + sync init + update \wr_pick_dly$1005 $0\wr_pick_dly$1005[0:0]$2945 + end + attribute \src "libresoc.v:41436.7-41436.32" + process $proc$libresoc.v:41436$2946 + assign { } { } + assign $0\wr_pick_dly$1026[0:0]$2947 1'0 + sync always + sync init + update \wr_pick_dly$1026 $0\wr_pick_dly$1026[0:0]$2947 + end + attribute \src "libresoc.v:41440.7-41440.32" + process $proc$libresoc.v:41440$2948 + assign { } { } + assign $0\wr_pick_dly$1044[0:0]$2949 1'0 + sync always + sync init + update \wr_pick_dly$1044 $0\wr_pick_dly$1044[0:0]$2949 + end + attribute \src "libresoc.v:41444.7-41444.32" + process $proc$libresoc.v:41444$2950 + assign { } { } + assign $0\wr_pick_dly$1066[0:0]$2951 1'0 + sync always + sync init + update \wr_pick_dly$1066 $0\wr_pick_dly$1066[0:0]$2951 + end + attribute \src "libresoc.v:41448.7-41448.32" + process $proc$libresoc.v:41448$2952 + assign { } { } + assign $0\wr_pick_dly$1086[0:0]$2953 1'0 + sync always + sync init + update \wr_pick_dly$1086 $0\wr_pick_dly$1086[0:0]$2953 + end + attribute \src "libresoc.v:41452.7-41452.32" + process $proc$libresoc.v:41452$2954 + assign { } { } + assign $0\wr_pick_dly$1106[0:0]$2955 1'0 + sync always + sync init + update \wr_pick_dly$1106 $0\wr_pick_dly$1106[0:0]$2955 + end + attribute \src "libresoc.v:41456.7-41456.32" + process $proc$libresoc.v:41456$2956 + assign { } { } + assign $0\wr_pick_dly$1125[0:0]$2957 1'0 + sync always + sync init + update \wr_pick_dly$1125 $0\wr_pick_dly$1125[0:0]$2957 + end + attribute \src "libresoc.v:41460.7-41460.32" + process $proc$libresoc.v:41460$2958 + assign { } { } + assign $0\wr_pick_dly$1143[0:0]$2959 1'0 + sync always + sync init + update \wr_pick_dly$1143 $0\wr_pick_dly$1143[0:0]$2959 + end + attribute \src "libresoc.v:41464.7-41464.32" + process $proc$libresoc.v:41464$2960 + assign { } { } + assign $0\wr_pick_dly$1217[0:0]$2961 1'0 + sync always + sync init + update \wr_pick_dly$1217 $0\wr_pick_dly$1217[0:0]$2961 + end + attribute \src "libresoc.v:41468.7-41468.32" + process $proc$libresoc.v:41468$2962 + assign { } { } + assign $0\wr_pick_dly$1245[0:0]$2963 1'0 + sync always + sync init + update \wr_pick_dly$1245 $0\wr_pick_dly$1245[0:0]$2963 + end + attribute \src "libresoc.v:41472.7-41472.32" + process $proc$libresoc.v:41472$2964 + assign { } { } + assign $0\wr_pick_dly$1265[0:0]$2965 1'0 + sync always + sync init + update \wr_pick_dly$1265 $0\wr_pick_dly$1265[0:0]$2965 + end + attribute \src "libresoc.v:41476.7-41476.32" + process $proc$libresoc.v:41476$2966 + assign { } { } + assign $0\wr_pick_dly$1285[0:0]$2967 1'0 + sync always + sync init + update \wr_pick_dly$1285 $0\wr_pick_dly$1285[0:0]$2967 + end + attribute \src "libresoc.v:41480.7-41480.32" + process $proc$libresoc.v:41480$2968 + assign { } { } + assign $0\wr_pick_dly$1305[0:0]$2969 1'0 + sync always + sync init + update \wr_pick_dly$1305 $0\wr_pick_dly$1305[0:0]$2969 + end + attribute \src "libresoc.v:41484.7-41484.32" + process $proc$libresoc.v:41484$2970 + assign { } { } + assign $0\wr_pick_dly$1325[0:0]$2971 1'0 + sync always + sync init + update \wr_pick_dly$1325 $0\wr_pick_dly$1325[0:0]$2971 + end + attribute \src "libresoc.v:41488.7-41488.32" + process $proc$libresoc.v:41488$2972 + assign { } { } + assign $0\wr_pick_dly$1345[0:0]$2973 1'0 + sync always + sync init + update \wr_pick_dly$1345 $0\wr_pick_dly$1345[0:0]$2973 + end + attribute \src "libresoc.v:41492.7-41492.32" + process $proc$libresoc.v:41492$2974 + assign { } { } + assign $0\wr_pick_dly$1392[0:0]$2975 1'0 + sync always + sync init + update \wr_pick_dly$1392 $0\wr_pick_dly$1392[0:0]$2975 + end + attribute \src "libresoc.v:41496.7-41496.32" + process $proc$libresoc.v:41496$2976 + assign { } { } + assign $0\wr_pick_dly$1408[0:0]$2977 1'0 + sync always + sync init + update \wr_pick_dly$1408 $0\wr_pick_dly$1408[0:0]$2977 + end + attribute \src "libresoc.v:41500.7-41500.32" + process $proc$libresoc.v:41500$2978 + assign { } { } + assign $0\wr_pick_dly$1424[0:0]$2979 1'0 + sync always + sync init + update \wr_pick_dly$1424 $0\wr_pick_dly$1424[0:0]$2979 + end + attribute \src "libresoc.v:41504.7-41504.32" + process $proc$libresoc.v:41504$2980 + assign { } { } + assign $0\wr_pick_dly$1458[0:0]$2981 1'0 + sync always + sync init + update \wr_pick_dly$1458 $0\wr_pick_dly$1458[0:0]$2981 + end + attribute \src "libresoc.v:41508.7-41508.32" + process $proc$libresoc.v:41508$2982 + assign { } { } + assign $0\wr_pick_dly$1474[0:0]$2983 1'0 + sync always + sync init + update \wr_pick_dly$1474 $0\wr_pick_dly$1474[0:0]$2983 + end + attribute \src "libresoc.v:41512.7-41512.32" + process $proc$libresoc.v:41512$2984 + assign { } { } + assign $0\wr_pick_dly$1490[0:0]$2985 1'0 + sync always + sync init + update \wr_pick_dly$1490 $0\wr_pick_dly$1490[0:0]$2985 + end + attribute \src "libresoc.v:41516.7-41516.32" + process $proc$libresoc.v:41516$2986 + assign { } { } + assign $0\wr_pick_dly$1506[0:0]$2987 1'0 + sync always + sync init + update \wr_pick_dly$1506 $0\wr_pick_dly$1506[0:0]$2987 + end + attribute \src "libresoc.v:41520.7-41520.32" + process $proc$libresoc.v:41520$2988 + assign { } { } + assign $0\wr_pick_dly$1542[0:0]$2989 1'0 + sync always + sync init + update \wr_pick_dly$1542 $0\wr_pick_dly$1542[0:0]$2989 + end + attribute \src "libresoc.v:41524.7-41524.32" + process $proc$libresoc.v:41524$2990 + assign { } { } + assign $0\wr_pick_dly$1558[0:0]$2991 1'0 + sync always + sync init + update \wr_pick_dly$1558 $0\wr_pick_dly$1558[0:0]$2991 + end + attribute \src "libresoc.v:41528.7-41528.32" + process $proc$libresoc.v:41528$2992 + assign { } { } + assign $0\wr_pick_dly$1574[0:0]$2993 1'0 + sync always + sync init + update \wr_pick_dly$1574 $0\wr_pick_dly$1574[0:0]$2993 + end + attribute \src "libresoc.v:41532.7-41532.32" + process $proc$libresoc.v:41532$2994 + assign { } { } + assign $0\wr_pick_dly$1590[0:0]$2995 1'0 + sync always + sync init + update \wr_pick_dly$1590 $0\wr_pick_dly$1590[0:0]$2995 + end + attribute \src "libresoc.v:41536.7-41536.32" + process $proc$libresoc.v:41536$2996 + assign { } { } + assign $0\wr_pick_dly$1632[0:0]$2997 1'0 + sync always + sync init + update \wr_pick_dly$1632 $0\wr_pick_dly$1632[0:0]$2997 + end + attribute \src "libresoc.v:41540.7-41540.32" + process $proc$libresoc.v:41540$2998 + assign { } { } + assign $0\wr_pick_dly$1651[0:0]$2999 1'0 + sync always + sync init + update \wr_pick_dly$1651 $0\wr_pick_dly$1651[0:0]$2999 + end + attribute \src "libresoc.v:41544.7-41544.32" + process $proc$libresoc.v:41544$3000 + assign { } { } + assign $0\wr_pick_dly$1667[0:0]$3001 1'0 + sync always + sync init + update \wr_pick_dly$1667 $0\wr_pick_dly$1667[0:0]$3001 + end + attribute \src "libresoc.v:41548.7-41548.32" + process $proc$libresoc.v:41548$3002 + assign { } { } + assign $0\wr_pick_dly$1683[0:0]$3003 1'0 + sync always + sync init + update \wr_pick_dly$1683 $0\wr_pick_dly$1683[0:0]$3003 + end + attribute \src "libresoc.v:41552.7-41552.32" + process $proc$libresoc.v:41552$3004 + assign { } { } + assign $0\wr_pick_dly$1699[0:0]$3005 1'0 + sync always + sync init + update \wr_pick_dly$1699 $0\wr_pick_dly$1699[0:0]$3005 + end + attribute \src "libresoc.v:41556.7-41556.32" + process $proc$libresoc.v:41556$3006 + assign { } { } + assign $0\wr_pick_dly$1743[0:0]$3007 1'0 + sync always + sync init + update \wr_pick_dly$1743 $0\wr_pick_dly$1743[0:0]$3007 + end + attribute \src "libresoc.v:41560.7-41560.32" + process $proc$libresoc.v:41560$3008 + assign { } { } + assign $0\wr_pick_dly$1759[0:0]$3009 1'0 + sync always + sync init + update \wr_pick_dly$1759 $0\wr_pick_dly$1759[0:0]$3009 + end + attribute \src "libresoc.v:41564.7-41564.32" + process $proc$libresoc.v:41564$3010 + assign { } { } + assign $0\wr_pick_dly$1783[0:0]$3011 1'0 + sync always + sync init + update \wr_pick_dly$1783 $0\wr_pick_dly$1783[0:0]$3011 + end + attribute \src "libresoc.v:41568.7-41568.32" + process $proc$libresoc.v:41568$3012 + assign { } { } + assign $0\wr_pick_dly$1803[0:0]$3013 1'0 + sync always + sync init + update \wr_pick_dly$1803 $0\wr_pick_dly$1803[0:0]$3013 + end + attribute \src "libresoc.v:41572.7-41572.31" + process $proc$libresoc.v:41572$3014 + assign { } { } + assign $0\wr_pick_dly$986[0:0]$3015 1'0 + sync always + sync init + update \wr_pick_dly$986 $0\wr_pick_dly$986[0:0]$3015 + end + attribute \src "libresoc.v:42534.3-42535.51" + process $proc$libresoc.v:42534$2238 + assign { } { } + assign $0\wr_pick_dly$1803[0:0]$2239 \wr_pick_dly$1803$next + sync posedge \coresync_clk + update \wr_pick_dly$1803 $0\wr_pick_dly$1803[0:0]$2239 + end + attribute \src "libresoc.v:42536.3-42537.51" + process $proc$libresoc.v:42536$2240 + assign { } { } + assign $0\wr_pick_dly$1783[0:0]$2241 \wr_pick_dly$1783$next + sync posedge \coresync_clk + update \wr_pick_dly$1783 $0\wr_pick_dly$1783[0:0]$2241 + end + attribute \src "libresoc.v:42538.3-42539.51" + process $proc$libresoc.v:42538$2242 + assign { } { } + assign $0\wr_pick_dly$1759[0:0]$2243 \wr_pick_dly$1759$next + sync posedge \coresync_clk + update \wr_pick_dly$1759 $0\wr_pick_dly$1759[0:0]$2243 + end + attribute \src "libresoc.v:42540.3-42541.51" + process $proc$libresoc.v:42540$2244 + assign { } { } + assign $0\wr_pick_dly$1743[0:0]$2245 \wr_pick_dly$1743$next + sync posedge \coresync_clk + update \wr_pick_dly$1743 $0\wr_pick_dly$1743[0:0]$2245 + end + attribute \src "libresoc.v:42542.3-42543.51" + process $proc$libresoc.v:42542$2246 + assign { } { } + assign $0\wr_pick_dly$1699[0:0]$2247 \wr_pick_dly$1699$next + sync posedge \coresync_clk + update \wr_pick_dly$1699 $0\wr_pick_dly$1699[0:0]$2247 + end + attribute \src "libresoc.v:42544.3-42545.51" + process $proc$libresoc.v:42544$2248 + assign { } { } + assign $0\wr_pick_dly$1683[0:0]$2249 \wr_pick_dly$1683$next + sync posedge \coresync_clk + update \wr_pick_dly$1683 $0\wr_pick_dly$1683[0:0]$2249 + end + attribute \src "libresoc.v:42546.3-42547.51" + process $proc$libresoc.v:42546$2250 + assign { } { } + assign $0\wr_pick_dly$1667[0:0]$2251 \wr_pick_dly$1667$next + sync posedge \coresync_clk + update \wr_pick_dly$1667 $0\wr_pick_dly$1667[0:0]$2251 + end + attribute \src "libresoc.v:42548.3-42549.51" + process $proc$libresoc.v:42548$2252 + assign { } { } + assign $0\wr_pick_dly$1651[0:0]$2253 \wr_pick_dly$1651$next + sync posedge \coresync_clk + update \wr_pick_dly$1651 $0\wr_pick_dly$1651[0:0]$2253 + end + attribute \src "libresoc.v:42550.3-42551.51" + process $proc$libresoc.v:42550$2254 + assign { } { } + assign $0\wr_pick_dly$1632[0:0]$2255 \wr_pick_dly$1632$next + sync posedge \coresync_clk + update \wr_pick_dly$1632 $0\wr_pick_dly$1632[0:0]$2255 + end + attribute \src "libresoc.v:42552.3-42553.51" + process $proc$libresoc.v:42552$2256 + assign { } { } + assign $0\wr_pick_dly$1590[0:0]$2257 \wr_pick_dly$1590$next + sync posedge \coresync_clk + update \wr_pick_dly$1590 $0\wr_pick_dly$1590[0:0]$2257 + end + attribute \src "libresoc.v:42554.3-42555.51" + process $proc$libresoc.v:42554$2258 + assign { } { } + assign $0\wr_pick_dly$1574[0:0]$2259 \wr_pick_dly$1574$next + sync posedge \coresync_clk + update \wr_pick_dly$1574 $0\wr_pick_dly$1574[0:0]$2259 + end + attribute \src "libresoc.v:42556.3-42557.51" + process $proc$libresoc.v:42556$2260 + assign { } { } + assign $0\wr_pick_dly$1558[0:0]$2261 \wr_pick_dly$1558$next + sync posedge \coresync_clk + update \wr_pick_dly$1558 $0\wr_pick_dly$1558[0:0]$2261 + end + attribute \src "libresoc.v:42558.3-42559.51" + process $proc$libresoc.v:42558$2262 + assign { } { } + assign $0\wr_pick_dly$1542[0:0]$2263 \wr_pick_dly$1542$next + sync posedge \coresync_clk + update \wr_pick_dly$1542 $0\wr_pick_dly$1542[0:0]$2263 + end + attribute \src "libresoc.v:42560.3-42561.51" + process $proc$libresoc.v:42560$2264 + assign { } { } + assign $0\wr_pick_dly$1506[0:0]$2265 \wr_pick_dly$1506$next + sync posedge \coresync_clk + update \wr_pick_dly$1506 $0\wr_pick_dly$1506[0:0]$2265 + end + attribute \src "libresoc.v:42562.3-42563.51" + process $proc$libresoc.v:42562$2266 + assign { } { } + assign $0\wr_pick_dly$1490[0:0]$2267 \wr_pick_dly$1490$next + sync posedge \coresync_clk + update \wr_pick_dly$1490 $0\wr_pick_dly$1490[0:0]$2267 + end + attribute \src "libresoc.v:42564.3-42565.51" + process $proc$libresoc.v:42564$2268 + assign { } { } + assign $0\wr_pick_dly$1474[0:0]$2269 \wr_pick_dly$1474$next + sync posedge \coresync_clk + update \wr_pick_dly$1474 $0\wr_pick_dly$1474[0:0]$2269 + end + attribute \src "libresoc.v:42566.3-42567.51" + process $proc$libresoc.v:42566$2270 + assign { } { } + assign $0\wr_pick_dly$1458[0:0]$2271 \wr_pick_dly$1458$next + sync posedge \coresync_clk + update \wr_pick_dly$1458 $0\wr_pick_dly$1458[0:0]$2271 + end + attribute \src "libresoc.v:42568.3-42569.51" + process $proc$libresoc.v:42568$2272 + assign { } { } + assign $0\wr_pick_dly$1424[0:0]$2273 \wr_pick_dly$1424$next + sync posedge \coresync_clk + update \wr_pick_dly$1424 $0\wr_pick_dly$1424[0:0]$2273 + end + attribute \src "libresoc.v:42570.3-42571.51" + process $proc$libresoc.v:42570$2274 + assign { } { } + assign $0\wr_pick_dly$1408[0:0]$2275 \wr_pick_dly$1408$next + sync posedge \coresync_clk + update \wr_pick_dly$1408 $0\wr_pick_dly$1408[0:0]$2275 + end + attribute \src "libresoc.v:42572.3-42573.51" + process $proc$libresoc.v:42572$2276 + assign { } { } + assign $0\wr_pick_dly$1392[0:0]$2277 \wr_pick_dly$1392$next + sync posedge \coresync_clk + update \wr_pick_dly$1392 $0\wr_pick_dly$1392[0:0]$2277 + end + attribute \src "libresoc.v:42574.3-42575.51" + process $proc$libresoc.v:42574$2278 + assign { } { } + assign $0\wr_pick_dly$1345[0:0]$2279 \wr_pick_dly$1345$next + sync posedge \coresync_clk + update \wr_pick_dly$1345 $0\wr_pick_dly$1345[0:0]$2279 + end + attribute \src "libresoc.v:42576.3-42577.51" + process $proc$libresoc.v:42576$2280 + assign { } { } + assign $0\wr_pick_dly$1325[0:0]$2281 \wr_pick_dly$1325$next + sync posedge \coresync_clk + update \wr_pick_dly$1325 $0\wr_pick_dly$1325[0:0]$2281 + end + attribute \src "libresoc.v:42578.3-42579.51" + process $proc$libresoc.v:42578$2282 + assign { } { } + assign $0\wr_pick_dly$1305[0:0]$2283 \wr_pick_dly$1305$next + sync posedge \coresync_clk + update \wr_pick_dly$1305 $0\wr_pick_dly$1305[0:0]$2283 + end + attribute \src "libresoc.v:42580.3-42581.51" + process $proc$libresoc.v:42580$2284 + assign { } { } + assign $0\wr_pick_dly$1285[0:0]$2285 \wr_pick_dly$1285$next + sync posedge \coresync_clk + update \wr_pick_dly$1285 $0\wr_pick_dly$1285[0:0]$2285 + end + attribute \src "libresoc.v:42582.3-42583.51" + process $proc$libresoc.v:42582$2286 + assign { } { } + assign $0\wr_pick_dly$1265[0:0]$2287 \wr_pick_dly$1265$next + sync posedge \coresync_clk + update \wr_pick_dly$1265 $0\wr_pick_dly$1265[0:0]$2287 + end + attribute \src "libresoc.v:42584.3-42585.51" + process $proc$libresoc.v:42584$2288 + assign { } { } + assign $0\wr_pick_dly$1245[0:0]$2289 \wr_pick_dly$1245$next + sync posedge \coresync_clk + update \wr_pick_dly$1245 $0\wr_pick_dly$1245[0:0]$2289 + end + attribute \src "libresoc.v:42586.3-42587.51" + process $proc$libresoc.v:42586$2290 + assign { } { } + assign $0\wr_pick_dly$1217[0:0]$2291 \wr_pick_dly$1217$next + sync posedge \coresync_clk + update \wr_pick_dly$1217 $0\wr_pick_dly$1217[0:0]$2291 + end + attribute \src "libresoc.v:42588.3-42589.51" + process $proc$libresoc.v:42588$2292 + assign { } { } + assign $0\wr_pick_dly$1143[0:0]$2293 \wr_pick_dly$1143$next + sync posedge \coresync_clk + update \wr_pick_dly$1143 $0\wr_pick_dly$1143[0:0]$2293 + end + attribute \src "libresoc.v:42590.3-42591.51" + process $proc$libresoc.v:42590$2294 + assign { } { } + assign $0\wr_pick_dly$1125[0:0]$2295 \wr_pick_dly$1125$next + sync posedge \coresync_clk + update \wr_pick_dly$1125 $0\wr_pick_dly$1125[0:0]$2295 + end + attribute \src "libresoc.v:42592.3-42593.51" + process $proc$libresoc.v:42592$2296 + assign { } { } + assign $0\wr_pick_dly$1106[0:0]$2297 \wr_pick_dly$1106$next + sync posedge \coresync_clk + update \wr_pick_dly$1106 $0\wr_pick_dly$1106[0:0]$2297 + end + attribute \src "libresoc.v:42594.3-42595.51" + process $proc$libresoc.v:42594$2298 + assign { } { } + assign $0\wr_pick_dly$1086[0:0]$2299 \wr_pick_dly$1086$next + sync posedge \coresync_clk + update \wr_pick_dly$1086 $0\wr_pick_dly$1086[0:0]$2299 + end + attribute \src "libresoc.v:42596.3-42597.51" + process $proc$libresoc.v:42596$2300 + assign { } { } + assign $0\wr_pick_dly$1066[0:0]$2301 \wr_pick_dly$1066$next + sync posedge \coresync_clk + update \wr_pick_dly$1066 $0\wr_pick_dly$1066[0:0]$2301 + end + attribute \src "libresoc.v:42598.3-42599.51" + process $proc$libresoc.v:42598$2302 + assign { } { } + assign $0\wr_pick_dly$1044[0:0]$2303 \wr_pick_dly$1044$next + sync posedge \coresync_clk + update \wr_pick_dly$1044 $0\wr_pick_dly$1044[0:0]$2303 + end + attribute \src "libresoc.v:42600.3-42601.51" + process $proc$libresoc.v:42600$2304 + assign { } { } + assign $0\wr_pick_dly$1026[0:0]$2305 \wr_pick_dly$1026$next + sync posedge \coresync_clk + update \wr_pick_dly$1026 $0\wr_pick_dly$1026[0:0]$2305 + end + attribute \src "libresoc.v:42602.3-42603.51" + process $proc$libresoc.v:42602$2306 + assign { } { } + assign $0\wr_pick_dly$1005[0:0]$2307 \wr_pick_dly$1005$next + sync posedge \coresync_clk + update \wr_pick_dly$1005 $0\wr_pick_dly$1005[0:0]$2307 + end + attribute \src "libresoc.v:42604.3-42605.49" + process $proc$libresoc.v:42604$2308 + assign { } { } + assign $0\wr_pick_dly$986[0:0]$2309 \wr_pick_dly$986$next + sync posedge \coresync_clk + update \wr_pick_dly$986 $0\wr_pick_dly$986[0:0]$2309 + end + attribute \src "libresoc.v:42606.3-42607.39" + process $proc$libresoc.v:42606$2310 + assign { } { } + assign $0\wr_pick_dly[0:0] \wr_pick_dly$next + sync posedge \coresync_clk + update \wr_pick_dly $0\wr_pick_dly[0:0] + end + attribute \src "libresoc.v:42608.3-42609.53" + process $proc$libresoc.v:42608$2311 + assign { } { } + assign $0\dp_SPR_spr1_spr0_0[0:0] \dp_SPR_spr1_spr0_0$next + sync posedge \coresync_clk + update \dp_SPR_spr1_spr0_0 $0\dp_SPR_spr1_spr0_0[0:0] + end + attribute \src "libresoc.v:42610.3-42611.59" + process $proc$libresoc.v:42610$2312 + assign { } { } + assign $0\dp_FAST_fast2_trap0_1[0:0] \dp_FAST_fast2_trap0_1$next + sync posedge \coresync_clk + update \dp_FAST_fast2_trap0_1 $0\dp_FAST_fast2_trap0_1[0:0] + end + attribute \src "libresoc.v:42612.3-42613.63" + process $proc$libresoc.v:42612$2313 + assign { } { } + assign $0\dp_FAST_fast2_branch0_0[0:0] \dp_FAST_fast2_branch0_0$next + sync posedge \coresync_clk + update \dp_FAST_fast2_branch0_0 $0\dp_FAST_fast2_branch0_0[0:0] + end + attribute \src "libresoc.v:42614.3-42615.57" + process $proc$libresoc.v:42614$2314 + assign { } { } + assign $0\dp_FAST_fast1_spr0_2[0:0] \dp_FAST_fast1_spr0_2$next + sync posedge \coresync_clk + update \dp_FAST_fast1_spr0_2 $0\dp_FAST_fast1_spr0_2[0:0] + end + attribute \src "libresoc.v:42616.3-42617.59" + process $proc$libresoc.v:42616$2315 + assign { } { } + assign $0\dp_FAST_fast1_trap0_1[0:0] \dp_FAST_fast1_trap0_1$next + sync posedge \coresync_clk + update \dp_FAST_fast1_trap0_1 $0\dp_FAST_fast1_trap0_1[0:0] + end + attribute \src "libresoc.v:42618.3-42619.63" + process $proc$libresoc.v:42618$2316 + assign { } { } + assign $0\dp_FAST_fast1_branch0_0[0:0] \dp_FAST_fast1_branch0_0$next + sync posedge \coresync_clk + update \dp_FAST_fast1_branch0_0 $0\dp_FAST_fast1_branch0_0[0:0] + end + attribute \src "libresoc.v:42620.3-42621.49" + process $proc$libresoc.v:42620$2317 + assign { } { } + assign $0\dp_CR_cr_c_cr0_0[0:0] \dp_CR_cr_c_cr0_0$next + sync posedge \coresync_clk + update \dp_CR_cr_c_cr0_0 $0\dp_CR_cr_c_cr0_0[0:0] + end + attribute \src "libresoc.v:42622.3-42623.49" + process $proc$libresoc.v:42622$2318 + assign { } { } + assign $0\dp_CR_cr_b_cr0_0[0:0] \dp_CR_cr_b_cr0_0$next + sync posedge \coresync_clk + update \dp_CR_cr_b_cr0_0 $0\dp_CR_cr_b_cr0_0[0:0] + end + attribute \src "libresoc.v:42624.3-42625.57" + process $proc$libresoc.v:42624$2319 + assign { } { } + assign $0\dp_CR_cr_a_branch0_1[0:0] \dp_CR_cr_a_branch0_1$next + sync posedge \coresync_clk + update \dp_CR_cr_a_branch0_1 $0\dp_CR_cr_a_branch0_1[0:0] + end + attribute \src "libresoc.v:42626.3-42627.49" + process $proc$libresoc.v:42626$2320 + assign { } { } + assign $0\dp_CR_cr_a_cr0_0[0:0] \dp_CR_cr_a_cr0_0$next + sync posedge \coresync_clk + update \dp_CR_cr_a_cr0_0 $0\dp_CR_cr_a_cr0_0[0:0] + end + attribute \src "libresoc.v:42628.3-42629.55" + process $proc$libresoc.v:42628$2321 + assign { } { } + assign $0\dp_CR_full_cr_cr0_0[0:0] \dp_CR_full_cr_cr0_0$next + sync posedge \coresync_clk + update \dp_CR_full_cr_cr0_0 $0\dp_CR_full_cr_cr0_0[0:0] + end + attribute \src "libresoc.v:42630.3-42631.57" + process $proc$libresoc.v:42630$2322 + assign { } { } + assign $0\dp_XER_xer_ov_spr0_0[0:0] \dp_XER_xer_ov_spr0_0$next + sync posedge \coresync_clk + update \dp_XER_xer_ov_spr0_0 $0\dp_XER_xer_ov_spr0_0[0:0] + end + attribute \src "libresoc.v:42632.3-42633.67" + process $proc$libresoc.v:42632$2323 + assign { } { } + assign $0\dp_XER_xer_ca_shiftrot0_2[0:0] \dp_XER_xer_ca_shiftrot0_2$next + sync posedge \coresync_clk + update \dp_XER_xer_ca_shiftrot0_2 $0\dp_XER_xer_ca_shiftrot0_2[0:0] + end + attribute \src "libresoc.v:42634.3-42635.57" + process $proc$libresoc.v:42634$2324 + assign { } { } + assign $0\dp_XER_xer_ca_spr0_1[0:0] \dp_XER_xer_ca_spr0_1$next + sync posedge \coresync_clk + update \dp_XER_xer_ca_spr0_1 $0\dp_XER_xer_ca_spr0_1[0:0] + end + attribute \src "libresoc.v:42636.3-42637.57" + process $proc$libresoc.v:42636$2325 + assign { } { } + assign $0\dp_XER_xer_ca_alu0_0[0:0] \dp_XER_xer_ca_alu0_0$next + sync posedge \coresync_clk + update \dp_XER_xer_ca_alu0_0 $0\dp_XER_xer_ca_alu0_0[0:0] + end + attribute \src "libresoc.v:42638.3-42639.67" + process $proc$libresoc.v:42638$2326 + assign { } { } + assign $0\dp_XER_xer_so_shiftrot0_5[0:0] \dp_XER_xer_so_shiftrot0_5$next + sync posedge \coresync_clk + update \dp_XER_xer_so_shiftrot0_5 $0\dp_XER_xer_so_shiftrot0_5[0:0] + end + attribute \src "libresoc.v:42640.3-42641.57" + process $proc$libresoc.v:42640$2327 + assign { } { } + assign $0\dp_XER_xer_so_mul0_4[0:0] \dp_XER_xer_so_mul0_4$next + sync posedge \coresync_clk + update \dp_XER_xer_so_mul0_4 $0\dp_XER_xer_so_mul0_4[0:0] + end + attribute \src "libresoc.v:42642.3-42643.57" + process $proc$libresoc.v:42642$2328 + assign { } { } + assign $0\dp_XER_xer_so_div0_3[0:0] \dp_XER_xer_so_div0_3$next + sync posedge \coresync_clk + update \dp_XER_xer_so_div0_3 $0\dp_XER_xer_so_div0_3[0:0] + end + attribute \src "libresoc.v:42644.3-42645.57" + process $proc$libresoc.v:42644$2329 + assign { } { } + assign $0\dp_XER_xer_so_spr0_2[0:0] \dp_XER_xer_so_spr0_2$next + sync posedge \coresync_clk + update \dp_XER_xer_so_spr0_2 $0\dp_XER_xer_so_spr0_2[0:0] + end + attribute \src "libresoc.v:42646.3-42647.65" + process $proc$libresoc.v:42646$2330 + assign { } { } + assign $0\dp_XER_xer_so_logical0_1[0:0] \dp_XER_xer_so_logical0_1$next + sync posedge \coresync_clk + update \dp_XER_xer_so_logical0_1 $0\dp_XER_xer_so_logical0_1[0:0] + end + attribute \src "libresoc.v:42648.3-42649.57" + process $proc$libresoc.v:42648$2331 + assign { } { } + assign $0\dp_XER_xer_so_alu0_0[0:0] \dp_XER_xer_so_alu0_0$next + sync posedge \coresync_clk + update \dp_XER_xer_so_alu0_0 $0\dp_XER_xer_so_alu0_0[0:0] + end + attribute \src "libresoc.v:42650.3-42651.51" + process $proc$libresoc.v:42650$2332 + assign { } { } + assign $0\dp_INT_rc_ldst0_1[0:0] \dp_INT_rc_ldst0_1$next + sync posedge \coresync_clk + update \dp_INT_rc_ldst0_1 $0\dp_INT_rc_ldst0_1[0:0] + end + attribute \src "libresoc.v:42652.3-42653.59" + process $proc$libresoc.v:42652$2333 + assign { } { } + assign $0\dp_INT_rc_shiftrot0_0[0:0] \dp_INT_rc_shiftrot0_0$next + sync posedge \coresync_clk + update \dp_INT_rc_shiftrot0_0 $0\dp_INT_rc_shiftrot0_0[0:0] + end + attribute \src "libresoc.v:42654.3-42655.51" + process $proc$libresoc.v:42654$2334 + assign { } { } + assign $0\dp_INT_rb_ldst0_7[0:0] \dp_INT_rb_ldst0_7$next + sync posedge \coresync_clk + update \dp_INT_rb_ldst0_7 $0\dp_INT_rb_ldst0_7[0:0] + end + attribute \src "libresoc.v:42656.3-42657.59" + process $proc$libresoc.v:42656$2335 + assign { } { } + assign $0\dp_INT_rb_shiftrot0_6[0:0] \dp_INT_rb_shiftrot0_6$next + sync posedge \coresync_clk + update \dp_INT_rb_shiftrot0_6 $0\dp_INT_rb_shiftrot0_6[0:0] + end + attribute \src "libresoc.v:42658.3-42659.49" + process $proc$libresoc.v:42658$2336 + assign { } { } + assign $0\dp_INT_rb_mul0_5[0:0] \dp_INT_rb_mul0_5$next + sync posedge \coresync_clk + update \dp_INT_rb_mul0_5 $0\dp_INT_rb_mul0_5[0:0] + end + attribute \src "libresoc.v:42660.3-42661.49" + process $proc$libresoc.v:42660$2337 + assign { } { } + assign $0\dp_INT_rb_div0_4[0:0] \dp_INT_rb_div0_4$next + sync posedge \coresync_clk + update \dp_INT_rb_div0_4 $0\dp_INT_rb_div0_4[0:0] + end + attribute \src "libresoc.v:42662.3-42663.57" + process $proc$libresoc.v:42662$2338 + assign { } { } + assign $0\dp_INT_rb_logical0_3[0:0] \dp_INT_rb_logical0_3$next + sync posedge \coresync_clk + update \dp_INT_rb_logical0_3 $0\dp_INT_rb_logical0_3[0:0] + end + attribute \src "libresoc.v:42664.3-42665.51" + process $proc$libresoc.v:42664$2339 + assign { } { } + assign $0\dp_INT_rb_trap0_2[0:0] \dp_INT_rb_trap0_2$next + sync posedge \coresync_clk + update \dp_INT_rb_trap0_2 $0\dp_INT_rb_trap0_2[0:0] + end + attribute \src "libresoc.v:42666.3-42667.47" + process $proc$libresoc.v:42666$2340 + assign { } { } + assign $0\dp_INT_rb_cr0_1[0:0] \dp_INT_rb_cr0_1$next + sync posedge \coresync_clk + update \dp_INT_rb_cr0_1 $0\dp_INT_rb_cr0_1[0:0] + end + attribute \src "libresoc.v:42668.3-42669.49" + process $proc$libresoc.v:42668$2341 + assign { } { } + assign $0\dp_INT_rb_alu0_0[0:0] \dp_INT_rb_alu0_0$next + sync posedge \coresync_clk + update \dp_INT_rb_alu0_0 $0\dp_INT_rb_alu0_0[0:0] + end + attribute \src "libresoc.v:42670.3-42671.51" + process $proc$libresoc.v:42670$2342 + assign { } { } + assign $0\dp_INT_ra_ldst0_8[0:0] \dp_INT_ra_ldst0_8$next + sync posedge \coresync_clk + update \dp_INT_ra_ldst0_8 $0\dp_INT_ra_ldst0_8[0:0] + end + attribute \src "libresoc.v:42672.3-42673.59" + process $proc$libresoc.v:42672$2343 + assign { } { } + assign $0\dp_INT_ra_shiftrot0_7[0:0] \dp_INT_ra_shiftrot0_7$next + sync posedge \coresync_clk + update \dp_INT_ra_shiftrot0_7 $0\dp_INT_ra_shiftrot0_7[0:0] + end + attribute \src "libresoc.v:42674.3-42675.49" + process $proc$libresoc.v:42674$2344 + assign { } { } + assign $0\dp_INT_ra_mul0_6[0:0] \dp_INT_ra_mul0_6$next + sync posedge \coresync_clk + update \dp_INT_ra_mul0_6 $0\dp_INT_ra_mul0_6[0:0] + end + attribute \src "libresoc.v:42676.3-42677.49" + process $proc$libresoc.v:42676$2345 + assign { } { } + assign $0\dp_INT_ra_div0_5[0:0] \dp_INT_ra_div0_5$next + sync posedge \coresync_clk + update \dp_INT_ra_div0_5 $0\dp_INT_ra_div0_5[0:0] + end + attribute \src "libresoc.v:42678.3-42679.49" + process $proc$libresoc.v:42678$2346 + assign { } { } + assign $0\dp_INT_ra_spr0_4[0:0] \dp_INT_ra_spr0_4$next + sync posedge \coresync_clk + update \dp_INT_ra_spr0_4 $0\dp_INT_ra_spr0_4[0:0] + end + attribute \src "libresoc.v:42680.3-42681.57" + process $proc$libresoc.v:42680$2347 + assign { } { } + assign $0\dp_INT_ra_logical0_3[0:0] \dp_INT_ra_logical0_3$next + sync posedge \coresync_clk + update \dp_INT_ra_logical0_3 $0\dp_INT_ra_logical0_3[0:0] + end + attribute \src "libresoc.v:42682.3-42683.51" + process $proc$libresoc.v:42682$2348 + assign { } { } + assign $0\dp_INT_ra_trap0_2[0:0] \dp_INT_ra_trap0_2$next + sync posedge \coresync_clk + update \dp_INT_ra_trap0_2 $0\dp_INT_ra_trap0_2[0:0] + end + attribute \src "libresoc.v:42684.3-42685.47" + process $proc$libresoc.v:42684$2349 + assign { } { } + assign $0\dp_INT_ra_cr0_1[0:0] \dp_INT_ra_cr0_1$next + sync posedge \coresync_clk + update \dp_INT_ra_cr0_1 $0\dp_INT_ra_cr0_1[0:0] + end + attribute \src "libresoc.v:42686.3-42687.49" + process $proc$libresoc.v:42686$2350 + assign { } { } + assign $0\dp_INT_ra_alu0_0[0:0] \dp_INT_ra_alu0_0$next + sync posedge \coresync_clk + update \dp_INT_ra_alu0_0 $0\dp_INT_ra_alu0_0[0:0] + end + attribute \src "libresoc.v:42688.3-42689.49" + process $proc$libresoc.v:42688$2351 + assign { } { } + assign $0\core_terminate_o[0:0] \core_terminate_o$next + sync posedge \coresync_clk + update \core_terminate_o $0\core_terminate_o[0:0] + end + attribute \src "libresoc.v:42690.3-42691.31" + process $proc$libresoc.v:42690$2352 + assign { } { } + assign $0\counter[1:0] \counter$next + sync posedge \coresync_clk + update \counter $0\counter[1:0] + end + attribute \src "libresoc.v:43425.3-43453.6" + process $proc$libresoc.v:43425$2353 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_spr0__insn[31:0] $1\fus_oper_i_alu_spr0__insn[31:0] + attribute \src "libresoc.v:43426.5-43426.29" + switch \initial + attribute \src "libresoc.v:43426.9-43426.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_spr0__insn[31:0] $2\fus_oper_i_alu_spr0__insn[31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_spr0__insn[31:0] 0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_spr0__insn[31:0] 0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_spr0__insn[31:0] $3\fus_oper_i_alu_spr0__insn[31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + switch \fu_enable [5] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_spr0__insn[31:0] \dec_SPR_SPR__insn + case + assign $3\fus_oper_i_alu_spr0__insn[31:0] 0 + end + end + case + assign $1\fus_oper_i_alu_spr0__insn[31:0] 0 + end + sync always + update \fus_oper_i_alu_spr0__insn $0\fus_oper_i_alu_spr0__insn[31:0] + end + attribute \src "libresoc.v:43454.3-43482.6" + process $proc$libresoc.v:43454$2354 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_spr0__is_32bit[0:0] $1\fus_oper_i_alu_spr0__is_32bit[0:0] + attribute \src "libresoc.v:43455.5-43455.29" + switch \initial + attribute \src "libresoc.v:43455.9-43455.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_spr0__is_32bit[0:0] $2\fus_oper_i_alu_spr0__is_32bit[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_spr0__is_32bit[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_spr0__is_32bit[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_spr0__is_32bit[0:0] $3\fus_oper_i_alu_spr0__is_32bit[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + switch \fu_enable [5] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_spr0__is_32bit[0:0] \dec_SPR_SPR__is_32bit + case + assign $3\fus_oper_i_alu_spr0__is_32bit[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_spr0__is_32bit[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_spr0__is_32bit $0\fus_oper_i_alu_spr0__is_32bit[0:0] + end + attribute \src "libresoc.v:43483.3-43511.6" + process $proc$libresoc.v:43483$2355 + assign { } { } + assign { } { } + assign $0\fus_cu_issue_i$25[0:0]$2356 $1\fus_cu_issue_i$25[0:0]$2357 + attribute \src "libresoc.v:43484.5-43484.29" + switch \initial + attribute \src "libresoc.v:43484.9-43484.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_cu_issue_i$25[0:0]$2357 $2\fus_cu_issue_i$25[0:0]$2358 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_cu_issue_i$25[0:0]$2358 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_cu_issue_i$25[0:0]$2358 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_cu_issue_i$25[0:0]$2358 $3\fus_cu_issue_i$25[0:0]$2359 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + switch \fu_enable [5] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_cu_issue_i$25[0:0]$2359 \issue_i + case + assign $3\fus_cu_issue_i$25[0:0]$2359 1'0 + end + end + case + assign $1\fus_cu_issue_i$25[0:0]$2357 1'0 + end + sync always + update \fus_cu_issue_i$25 $0\fus_cu_issue_i$25[0:0]$2356 + end + attribute \src "libresoc.v:43512.3-43540.6" + process $proc$libresoc.v:43512$2360 + assign { } { } + assign { } { } + assign $0\fus_cu_rdmaskn_i$27[5:0]$2361 $1\fus_cu_rdmaskn_i$27[5:0]$2362 + attribute \src "libresoc.v:43513.5-43513.29" + switch \initial + attribute \src "libresoc.v:43513.9-43513.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_cu_rdmaskn_i$27[5:0]$2362 $2\fus_cu_rdmaskn_i$27[5:0]$2363 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_cu_rdmaskn_i$27[5:0]$2363 6'000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_cu_rdmaskn_i$27[5:0]$2363 6'000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_cu_rdmaskn_i$27[5:0]$2363 $3\fus_cu_rdmaskn_i$27[5:0]$2364 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + switch \fu_enable [5] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_cu_rdmaskn_i$27[5:0]$2364 \$265 + case + assign $3\fus_cu_rdmaskn_i$27[5:0]$2364 6'000000 + end + end + case + assign $1\fus_cu_rdmaskn_i$27[5:0]$2362 6'000000 + end + sync always + update \fus_cu_rdmaskn_i$27 $0\fus_cu_rdmaskn_i$27[5:0]$2361 + end + attribute \src "libresoc.v:43541.3-43569.6" + process $proc$libresoc.v:43541$2365 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_div0__insn_type[6:0] $1\fus_oper_i_alu_div0__insn_type[6:0] + attribute \src "libresoc.v:43542.5-43542.29" + switch \initial + attribute \src "libresoc.v:43542.9-43542.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_div0__insn_type[6:0] $2\fus_oper_i_alu_div0__insn_type[6:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_div0__insn_type[6:0] 7'0000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_div0__insn_type[6:0] 7'0000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_div0__insn_type[6:0] $3\fus_oper_i_alu_div0__insn_type[6:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + switch \fu_enable [6] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_div0__insn_type[6:0] \dec_DIV_DIV__insn_type + case + assign $3\fus_oper_i_alu_div0__insn_type[6:0] 7'0000000 + end + end + case + assign $1\fus_oper_i_alu_div0__insn_type[6:0] 7'0000000 + end + sync always + update \fus_oper_i_alu_div0__insn_type $0\fus_oper_i_alu_div0__insn_type[6:0] + end + attribute \src "libresoc.v:43570.3-43598.6" + process $proc$libresoc.v:43570$2366 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_div0__fn_unit[12:0] $1\fus_oper_i_alu_div0__fn_unit[12:0] + attribute \src "libresoc.v:43571.5-43571.29" + switch \initial + attribute \src "libresoc.v:43571.9-43571.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_div0__fn_unit[12:0] $2\fus_oper_i_alu_div0__fn_unit[12:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_div0__fn_unit[12:0] 13'0000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_div0__fn_unit[12:0] 13'0000000000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_div0__fn_unit[12:0] $3\fus_oper_i_alu_div0__fn_unit[12:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + switch \fu_enable [6] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_div0__fn_unit[12:0] \dec_DIV_DIV__fn_unit + case + assign $3\fus_oper_i_alu_div0__fn_unit[12:0] 13'0000000000000 + end + end + case + assign $1\fus_oper_i_alu_div0__fn_unit[12:0] 13'0000000000000 + end + sync always + update \fus_oper_i_alu_div0__fn_unit $0\fus_oper_i_alu_div0__fn_unit[12:0] + end + attribute \src "libresoc.v:43599.3-43628.6" + process $proc$libresoc.v:43599$2367 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_div0__imm_data__data[63:0] $1\fus_oper_i_alu_div0__imm_data__data[63:0] + assign $0\fus_oper_i_alu_div0__imm_data__ok[0:0] $1\fus_oper_i_alu_div0__imm_data__ok[0:0] + attribute \src "libresoc.v:43600.5-43600.29" + switch \initial + attribute \src "libresoc.v:43600.9-43600.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $1\fus_oper_i_alu_div0__imm_data__data[63:0] $2\fus_oper_i_alu_div0__imm_data__data[63:0] + assign $1\fus_oper_i_alu_div0__imm_data__ok[0:0] $2\fus_oper_i_alu_div0__imm_data__ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_div0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\fus_oper_i_alu_div0__imm_data__ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_div0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\fus_oper_i_alu_div0__imm_data__ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign $2\fus_oper_i_alu_div0__imm_data__data[63:0] $3\fus_oper_i_alu_div0__imm_data__data[63:0] + assign $2\fus_oper_i_alu_div0__imm_data__ok[0:0] $3\fus_oper_i_alu_div0__imm_data__ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + switch \fu_enable [6] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $3\fus_oper_i_alu_div0__imm_data__ok[0:0] $3\fus_oper_i_alu_div0__imm_data__data[63:0] } { \dec_DIV_DIV__imm_data__ok \dec_DIV_DIV__imm_data__data } + case + assign $3\fus_oper_i_alu_div0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\fus_oper_i_alu_div0__imm_data__ok[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_div0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fus_oper_i_alu_div0__imm_data__ok[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_div0__imm_data__data $0\fus_oper_i_alu_div0__imm_data__data[63:0] + update \fus_oper_i_alu_div0__imm_data__ok $0\fus_oper_i_alu_div0__imm_data__ok[0:0] + end + attribute \src "libresoc.v:43629.3-43658.6" + process $proc$libresoc.v:43629$2368 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_div0__rc__ok[0:0] $1\fus_oper_i_alu_div0__rc__ok[0:0] + assign $0\fus_oper_i_alu_div0__rc__rc[0:0] $1\fus_oper_i_alu_div0__rc__rc[0:0] + attribute \src "libresoc.v:43630.5-43630.29" + switch \initial + attribute \src "libresoc.v:43630.9-43630.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $1\fus_oper_i_alu_div0__rc__ok[0:0] $2\fus_oper_i_alu_div0__rc__ok[0:0] + assign $1\fus_oper_i_alu_div0__rc__rc[0:0] $2\fus_oper_i_alu_div0__rc__rc[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_div0__rc__ok[0:0] 1'0 + assign $2\fus_oper_i_alu_div0__rc__rc[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_div0__rc__ok[0:0] 1'0 + assign $2\fus_oper_i_alu_div0__rc__rc[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign $2\fus_oper_i_alu_div0__rc__ok[0:0] $3\fus_oper_i_alu_div0__rc__ok[0:0] + assign $2\fus_oper_i_alu_div0__rc__rc[0:0] $3\fus_oper_i_alu_div0__rc__rc[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + switch \fu_enable [6] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $3\fus_oper_i_alu_div0__rc__ok[0:0] $3\fus_oper_i_alu_div0__rc__rc[0:0] } { \dec_DIV_DIV__rc__ok \dec_DIV_DIV__rc__rc } + case + assign $3\fus_oper_i_alu_div0__rc__ok[0:0] 1'0 + assign $3\fus_oper_i_alu_div0__rc__rc[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_div0__rc__ok[0:0] 1'0 + assign $1\fus_oper_i_alu_div0__rc__rc[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_div0__rc__ok $0\fus_oper_i_alu_div0__rc__ok[0:0] + update \fus_oper_i_alu_div0__rc__rc $0\fus_oper_i_alu_div0__rc__rc[0:0] + end + attribute \src "libresoc.v:43659.3-43688.6" + process $proc$libresoc.v:43659$2369 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_div0__oe__oe[0:0] $1\fus_oper_i_alu_div0__oe__oe[0:0] + assign $0\fus_oper_i_alu_div0__oe__ok[0:0] $1\fus_oper_i_alu_div0__oe__ok[0:0] + attribute \src "libresoc.v:43660.5-43660.29" + switch \initial + attribute \src "libresoc.v:43660.9-43660.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $1\fus_oper_i_alu_div0__oe__oe[0:0] $2\fus_oper_i_alu_div0__oe__oe[0:0] + assign $1\fus_oper_i_alu_div0__oe__ok[0:0] $2\fus_oper_i_alu_div0__oe__ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_div0__oe__oe[0:0] 1'0 + assign $2\fus_oper_i_alu_div0__oe__ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_div0__oe__oe[0:0] 1'0 + assign $2\fus_oper_i_alu_div0__oe__ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign $2\fus_oper_i_alu_div0__oe__oe[0:0] $3\fus_oper_i_alu_div0__oe__oe[0:0] + assign $2\fus_oper_i_alu_div0__oe__ok[0:0] $3\fus_oper_i_alu_div0__oe__ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + switch \fu_enable [6] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $3\fus_oper_i_alu_div0__oe__ok[0:0] $3\fus_oper_i_alu_div0__oe__oe[0:0] } { \dec_DIV_DIV__oe__ok \dec_DIV_DIV__oe__oe } + case + assign $3\fus_oper_i_alu_div0__oe__oe[0:0] 1'0 + assign $3\fus_oper_i_alu_div0__oe__ok[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_div0__oe__oe[0:0] 1'0 + assign $1\fus_oper_i_alu_div0__oe__ok[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_div0__oe__oe $0\fus_oper_i_alu_div0__oe__oe[0:0] + update \fus_oper_i_alu_div0__oe__ok $0\fus_oper_i_alu_div0__oe__ok[0:0] + end + attribute \src "libresoc.v:43689.3-43717.6" + process $proc$libresoc.v:43689$2370 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_div0__invert_in[0:0] $1\fus_oper_i_alu_div0__invert_in[0:0] + attribute \src "libresoc.v:43690.5-43690.29" + switch \initial + attribute \src "libresoc.v:43690.9-43690.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_div0__invert_in[0:0] $2\fus_oper_i_alu_div0__invert_in[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_div0__invert_in[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_div0__invert_in[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_div0__invert_in[0:0] $3\fus_oper_i_alu_div0__invert_in[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + switch \fu_enable [6] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_div0__invert_in[0:0] \dec_DIV_DIV__invert_in + case + assign $3\fus_oper_i_alu_div0__invert_in[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_div0__invert_in[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_div0__invert_in $0\fus_oper_i_alu_div0__invert_in[0:0] + end + attribute \src "libresoc.v:43718.3-43746.6" + process $proc$libresoc.v:43718$2371 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_div0__zero_a[0:0] $1\fus_oper_i_alu_div0__zero_a[0:0] + attribute \src "libresoc.v:43719.5-43719.29" + switch \initial + attribute \src "libresoc.v:43719.9-43719.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_div0__zero_a[0:0] $2\fus_oper_i_alu_div0__zero_a[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_div0__zero_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_div0__zero_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_div0__zero_a[0:0] $3\fus_oper_i_alu_div0__zero_a[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + switch \fu_enable [6] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_div0__zero_a[0:0] \dec_DIV_DIV__zero_a + case + assign $3\fus_oper_i_alu_div0__zero_a[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_div0__zero_a[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_div0__zero_a $0\fus_oper_i_alu_div0__zero_a[0:0] + end + attribute \src "libresoc.v:43747.3-43775.6" + process $proc$libresoc.v:43747$2372 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_div0__input_carry[1:0] $1\fus_oper_i_alu_div0__input_carry[1:0] + attribute \src "libresoc.v:43748.5-43748.29" + switch \initial + attribute \src "libresoc.v:43748.9-43748.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_div0__input_carry[1:0] $2\fus_oper_i_alu_div0__input_carry[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_div0__input_carry[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_div0__input_carry[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_div0__input_carry[1:0] $3\fus_oper_i_alu_div0__input_carry[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + switch \fu_enable [6] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_div0__input_carry[1:0] \dec_DIV_DIV__input_carry + case + assign $3\fus_oper_i_alu_div0__input_carry[1:0] 2'00 + end + end + case + assign $1\fus_oper_i_alu_div0__input_carry[1:0] 2'00 + end + sync always + update \fus_oper_i_alu_div0__input_carry $0\fus_oper_i_alu_div0__input_carry[1:0] + end + attribute \src "libresoc.v:43776.3-43804.6" + process $proc$libresoc.v:43776$2373 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_div0__invert_out[0:0] $1\fus_oper_i_alu_div0__invert_out[0:0] + attribute \src "libresoc.v:43777.5-43777.29" + switch \initial + attribute \src "libresoc.v:43777.9-43777.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_div0__invert_out[0:0] $2\fus_oper_i_alu_div0__invert_out[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_div0__invert_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_div0__invert_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_div0__invert_out[0:0] $3\fus_oper_i_alu_div0__invert_out[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + switch \fu_enable [6] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_div0__invert_out[0:0] \dec_DIV_DIV__invert_out + case + assign $3\fus_oper_i_alu_div0__invert_out[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_div0__invert_out[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_div0__invert_out $0\fus_oper_i_alu_div0__invert_out[0:0] + end + attribute \src "libresoc.v:43805.3-43833.6" + process $proc$libresoc.v:43805$2374 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_div0__write_cr0[0:0] $1\fus_oper_i_alu_div0__write_cr0[0:0] + attribute \src "libresoc.v:43806.5-43806.29" + switch \initial + attribute \src "libresoc.v:43806.9-43806.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_div0__write_cr0[0:0] $2\fus_oper_i_alu_div0__write_cr0[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_div0__write_cr0[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_div0__write_cr0[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_div0__write_cr0[0:0] $3\fus_oper_i_alu_div0__write_cr0[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + switch \fu_enable [6] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_div0__write_cr0[0:0] \dec_DIV_DIV__write_cr0 + case + assign $3\fus_oper_i_alu_div0__write_cr0[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_div0__write_cr0[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_div0__write_cr0 $0\fus_oper_i_alu_div0__write_cr0[0:0] + end + attribute \src "libresoc.v:43834.3-43862.6" + process $proc$libresoc.v:43834$2375 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_div0__output_carry[0:0] $1\fus_oper_i_alu_div0__output_carry[0:0] + attribute \src "libresoc.v:43835.5-43835.29" + switch \initial + attribute \src "libresoc.v:43835.9-43835.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_div0__output_carry[0:0] $2\fus_oper_i_alu_div0__output_carry[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_div0__output_carry[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_div0__output_carry[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_div0__output_carry[0:0] $3\fus_oper_i_alu_div0__output_carry[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + switch \fu_enable [6] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_div0__output_carry[0:0] \dec_DIV_DIV__output_carry + case + assign $3\fus_oper_i_alu_div0__output_carry[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_div0__output_carry[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_div0__output_carry $0\fus_oper_i_alu_div0__output_carry[0:0] + end + attribute \src "libresoc.v:43863.3-43891.6" + process $proc$libresoc.v:43863$2376 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_div0__is_32bit[0:0] $1\fus_oper_i_alu_div0__is_32bit[0:0] + attribute \src "libresoc.v:43864.5-43864.29" + switch \initial + attribute \src "libresoc.v:43864.9-43864.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_div0__is_32bit[0:0] $2\fus_oper_i_alu_div0__is_32bit[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_div0__is_32bit[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_div0__is_32bit[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_div0__is_32bit[0:0] $3\fus_oper_i_alu_div0__is_32bit[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + switch \fu_enable [6] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_div0__is_32bit[0:0] \dec_DIV_DIV__is_32bit + case + assign $3\fus_oper_i_alu_div0__is_32bit[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_div0__is_32bit[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_div0__is_32bit $0\fus_oper_i_alu_div0__is_32bit[0:0] + end + attribute \src "libresoc.v:43892.3-43920.6" + process $proc$libresoc.v:43892$2377 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_div0__is_signed[0:0] $1\fus_oper_i_alu_div0__is_signed[0:0] + attribute \src "libresoc.v:43893.5-43893.29" + switch \initial + attribute \src "libresoc.v:43893.9-43893.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_div0__is_signed[0:0] $2\fus_oper_i_alu_div0__is_signed[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_div0__is_signed[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_div0__is_signed[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_div0__is_signed[0:0] $3\fus_oper_i_alu_div0__is_signed[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + switch \fu_enable [6] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_div0__is_signed[0:0] \dec_DIV_DIV__is_signed + case + assign $3\fus_oper_i_alu_div0__is_signed[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_div0__is_signed[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_div0__is_signed $0\fus_oper_i_alu_div0__is_signed[0:0] + end + attribute \src "libresoc.v:43921.3-43949.6" + process $proc$libresoc.v:43921$2378 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_div0__data_len[3:0] $1\fus_oper_i_alu_div0__data_len[3:0] + attribute \src "libresoc.v:43922.5-43922.29" + switch \initial + attribute \src "libresoc.v:43922.9-43922.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_div0__data_len[3:0] $2\fus_oper_i_alu_div0__data_len[3:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_div0__data_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_div0__data_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_div0__data_len[3:0] $3\fus_oper_i_alu_div0__data_len[3:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + switch \fu_enable [6] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_div0__data_len[3:0] \dec_DIV_DIV__data_len + case + assign $3\fus_oper_i_alu_div0__data_len[3:0] 4'0000 + end + end + case + assign $1\fus_oper_i_alu_div0__data_len[3:0] 4'0000 + end + sync always + update \fus_oper_i_alu_div0__data_len $0\fus_oper_i_alu_div0__data_len[3:0] + end + attribute \src "libresoc.v:43950.3-43978.6" + process $proc$libresoc.v:43950$2379 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_div0__insn[31:0] $1\fus_oper_i_alu_div0__insn[31:0] + attribute \src "libresoc.v:43951.5-43951.29" + switch \initial + attribute \src "libresoc.v:43951.9-43951.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_div0__insn[31:0] $2\fus_oper_i_alu_div0__insn[31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_div0__insn[31:0] 0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_div0__insn[31:0] 0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_div0__insn[31:0] $3\fus_oper_i_alu_div0__insn[31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + switch \fu_enable [6] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_div0__insn[31:0] \dec_DIV_DIV__insn + case + assign $3\fus_oper_i_alu_div0__insn[31:0] 0 + end + end + case + assign $1\fus_oper_i_alu_div0__insn[31:0] 0 + end + sync always + update \fus_oper_i_alu_div0__insn $0\fus_oper_i_alu_div0__insn[31:0] + end + attribute \src "libresoc.v:43979.3-44007.6" + process $proc$libresoc.v:43979$2380 + assign { } { } + assign { } { } + assign $0\fus_cu_issue_i$28[0:0]$2381 $1\fus_cu_issue_i$28[0:0]$2382 + attribute \src "libresoc.v:43980.5-43980.29" + switch \initial + attribute \src "libresoc.v:43980.9-43980.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_cu_issue_i$28[0:0]$2382 $2\fus_cu_issue_i$28[0:0]$2383 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_cu_issue_i$28[0:0]$2383 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_cu_issue_i$28[0:0]$2383 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_cu_issue_i$28[0:0]$2383 $3\fus_cu_issue_i$28[0:0]$2384 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + switch \fu_enable [6] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_cu_issue_i$28[0:0]$2384 \issue_i + case + assign $3\fus_cu_issue_i$28[0:0]$2384 1'0 + end + end + case + assign $1\fus_cu_issue_i$28[0:0]$2382 1'0 + end + sync always + update \fus_cu_issue_i$28 $0\fus_cu_issue_i$28[0:0]$2381 + end + attribute \src "libresoc.v:44008.3-44036.6" + process $proc$libresoc.v:44008$2385 + assign { } { } + assign { } { } + assign $0\fus_cu_rdmaskn_i$30[2:0]$2386 $1\fus_cu_rdmaskn_i$30[2:0]$2387 + attribute \src "libresoc.v:44009.5-44009.29" + switch \initial + attribute \src "libresoc.v:44009.9-44009.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_cu_rdmaskn_i$30[2:0]$2387 $2\fus_cu_rdmaskn_i$30[2:0]$2388 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_cu_rdmaskn_i$30[2:0]$2388 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_cu_rdmaskn_i$30[2:0]$2388 3'000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_cu_rdmaskn_i$30[2:0]$2388 $3\fus_cu_rdmaskn_i$30[2:0]$2389 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + switch \fu_enable [6] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_cu_rdmaskn_i$30[2:0]$2389 \$295 + case + assign $3\fus_cu_rdmaskn_i$30[2:0]$2389 3'000 + end + end + case + assign $1\fus_cu_rdmaskn_i$30[2:0]$2387 3'000 + end + sync always + update \fus_cu_rdmaskn_i$30 $0\fus_cu_rdmaskn_i$30[2:0]$2386 + end + attribute \src "libresoc.v:44037.3-44065.6" + process $proc$libresoc.v:44037$2390 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_mul0__insn_type[6:0] $1\fus_oper_i_alu_mul0__insn_type[6:0] + attribute \src "libresoc.v:44038.5-44038.29" + switch \initial + attribute \src "libresoc.v:44038.9-44038.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_mul0__insn_type[6:0] $2\fus_oper_i_alu_mul0__insn_type[6:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_mul0__insn_type[6:0] 7'0000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_mul0__insn_type[6:0] 7'0000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_mul0__insn_type[6:0] $3\fus_oper_i_alu_mul0__insn_type[6:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + switch \fu_enable [7] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_mul0__insn_type[6:0] \dec_MUL_MUL__insn_type + case + assign $3\fus_oper_i_alu_mul0__insn_type[6:0] 7'0000000 + end + end + case + assign $1\fus_oper_i_alu_mul0__insn_type[6:0] 7'0000000 + end + sync always + update \fus_oper_i_alu_mul0__insn_type $0\fus_oper_i_alu_mul0__insn_type[6:0] + end + attribute \src "libresoc.v:44066.3-44094.6" + process $proc$libresoc.v:44066$2391 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_mul0__fn_unit[12:0] $1\fus_oper_i_alu_mul0__fn_unit[12:0] + attribute \src "libresoc.v:44067.5-44067.29" + switch \initial + attribute \src "libresoc.v:44067.9-44067.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_mul0__fn_unit[12:0] $2\fus_oper_i_alu_mul0__fn_unit[12:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_mul0__fn_unit[12:0] 13'0000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_mul0__fn_unit[12:0] 13'0000000000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_mul0__fn_unit[12:0] $3\fus_oper_i_alu_mul0__fn_unit[12:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + switch \fu_enable [7] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_mul0__fn_unit[12:0] \dec_MUL_MUL__fn_unit + case + assign $3\fus_oper_i_alu_mul0__fn_unit[12:0] 13'0000000000000 + end + end + case + assign $1\fus_oper_i_alu_mul0__fn_unit[12:0] 13'0000000000000 + end + sync always + update \fus_oper_i_alu_mul0__fn_unit $0\fus_oper_i_alu_mul0__fn_unit[12:0] + end + attribute \src "libresoc.v:44095.3-44124.6" + process $proc$libresoc.v:44095$2392 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_mul0__imm_data__data[63:0] $1\fus_oper_i_alu_mul0__imm_data__data[63:0] + assign $0\fus_oper_i_alu_mul0__imm_data__ok[0:0] $1\fus_oper_i_alu_mul0__imm_data__ok[0:0] + attribute \src "libresoc.v:44096.5-44096.29" + switch \initial + attribute \src "libresoc.v:44096.9-44096.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $1\fus_oper_i_alu_mul0__imm_data__data[63:0] $2\fus_oper_i_alu_mul0__imm_data__data[63:0] + assign $1\fus_oper_i_alu_mul0__imm_data__ok[0:0] $2\fus_oper_i_alu_mul0__imm_data__ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_mul0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\fus_oper_i_alu_mul0__imm_data__ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_mul0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\fus_oper_i_alu_mul0__imm_data__ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign $2\fus_oper_i_alu_mul0__imm_data__data[63:0] $3\fus_oper_i_alu_mul0__imm_data__data[63:0] + assign $2\fus_oper_i_alu_mul0__imm_data__ok[0:0] $3\fus_oper_i_alu_mul0__imm_data__ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + switch \fu_enable [7] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $3\fus_oper_i_alu_mul0__imm_data__ok[0:0] $3\fus_oper_i_alu_mul0__imm_data__data[63:0] } { \dec_MUL_MUL__imm_data__ok \dec_MUL_MUL__imm_data__data } + case + assign $3\fus_oper_i_alu_mul0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\fus_oper_i_alu_mul0__imm_data__ok[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_mul0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fus_oper_i_alu_mul0__imm_data__ok[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_mul0__imm_data__data $0\fus_oper_i_alu_mul0__imm_data__data[63:0] + update \fus_oper_i_alu_mul0__imm_data__ok $0\fus_oper_i_alu_mul0__imm_data__ok[0:0] + end + attribute \src "libresoc.v:44125.3-44154.6" + process $proc$libresoc.v:44125$2393 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_mul0__rc__ok[0:0] $1\fus_oper_i_alu_mul0__rc__ok[0:0] + assign $0\fus_oper_i_alu_mul0__rc__rc[0:0] $1\fus_oper_i_alu_mul0__rc__rc[0:0] + attribute \src "libresoc.v:44126.5-44126.29" + switch \initial + attribute \src "libresoc.v:44126.9-44126.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $1\fus_oper_i_alu_mul0__rc__ok[0:0] $2\fus_oper_i_alu_mul0__rc__ok[0:0] + assign $1\fus_oper_i_alu_mul0__rc__rc[0:0] $2\fus_oper_i_alu_mul0__rc__rc[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_mul0__rc__ok[0:0] 1'0 + assign $2\fus_oper_i_alu_mul0__rc__rc[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_mul0__rc__ok[0:0] 1'0 + assign $2\fus_oper_i_alu_mul0__rc__rc[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign $2\fus_oper_i_alu_mul0__rc__ok[0:0] $3\fus_oper_i_alu_mul0__rc__ok[0:0] + assign $2\fus_oper_i_alu_mul0__rc__rc[0:0] $3\fus_oper_i_alu_mul0__rc__rc[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + switch \fu_enable [7] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $3\fus_oper_i_alu_mul0__rc__ok[0:0] $3\fus_oper_i_alu_mul0__rc__rc[0:0] } { \dec_MUL_MUL__rc__ok \dec_MUL_MUL__rc__rc } + case + assign $3\fus_oper_i_alu_mul0__rc__ok[0:0] 1'0 + assign $3\fus_oper_i_alu_mul0__rc__rc[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_mul0__rc__ok[0:0] 1'0 + assign $1\fus_oper_i_alu_mul0__rc__rc[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_mul0__rc__ok $0\fus_oper_i_alu_mul0__rc__ok[0:0] + update \fus_oper_i_alu_mul0__rc__rc $0\fus_oper_i_alu_mul0__rc__rc[0:0] + end + attribute \src "libresoc.v:44155.3-44184.6" + process $proc$libresoc.v:44155$2394 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_mul0__oe__oe[0:0] $1\fus_oper_i_alu_mul0__oe__oe[0:0] + assign $0\fus_oper_i_alu_mul0__oe__ok[0:0] $1\fus_oper_i_alu_mul0__oe__ok[0:0] + attribute \src "libresoc.v:44156.5-44156.29" + switch \initial + attribute \src "libresoc.v:44156.9-44156.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $1\fus_oper_i_alu_mul0__oe__oe[0:0] $2\fus_oper_i_alu_mul0__oe__oe[0:0] + assign $1\fus_oper_i_alu_mul0__oe__ok[0:0] $2\fus_oper_i_alu_mul0__oe__ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_mul0__oe__oe[0:0] 1'0 + assign $2\fus_oper_i_alu_mul0__oe__ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_mul0__oe__oe[0:0] 1'0 + assign $2\fus_oper_i_alu_mul0__oe__ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign $2\fus_oper_i_alu_mul0__oe__oe[0:0] $3\fus_oper_i_alu_mul0__oe__oe[0:0] + assign $2\fus_oper_i_alu_mul0__oe__ok[0:0] $3\fus_oper_i_alu_mul0__oe__ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + switch \fu_enable [7] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $3\fus_oper_i_alu_mul0__oe__ok[0:0] $3\fus_oper_i_alu_mul0__oe__oe[0:0] } { \dec_MUL_MUL__oe__ok \dec_MUL_MUL__oe__oe } + case + assign $3\fus_oper_i_alu_mul0__oe__oe[0:0] 1'0 + assign $3\fus_oper_i_alu_mul0__oe__ok[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_mul0__oe__oe[0:0] 1'0 + assign $1\fus_oper_i_alu_mul0__oe__ok[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_mul0__oe__oe $0\fus_oper_i_alu_mul0__oe__oe[0:0] + update \fus_oper_i_alu_mul0__oe__ok $0\fus_oper_i_alu_mul0__oe__ok[0:0] + end + attribute \src "libresoc.v:44185.3-44213.6" + process $proc$libresoc.v:44185$2395 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_mul0__write_cr0[0:0] $1\fus_oper_i_alu_mul0__write_cr0[0:0] + attribute \src "libresoc.v:44186.5-44186.29" + switch \initial + attribute \src "libresoc.v:44186.9-44186.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_mul0__write_cr0[0:0] $2\fus_oper_i_alu_mul0__write_cr0[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_mul0__write_cr0[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_mul0__write_cr0[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_mul0__write_cr0[0:0] $3\fus_oper_i_alu_mul0__write_cr0[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + switch \fu_enable [7] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_mul0__write_cr0[0:0] \dec_MUL_MUL__write_cr0 + case + assign $3\fus_oper_i_alu_mul0__write_cr0[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_mul0__write_cr0[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_mul0__write_cr0 $0\fus_oper_i_alu_mul0__write_cr0[0:0] + end + attribute \src "libresoc.v:44214.3-44242.6" + process $proc$libresoc.v:44214$2396 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_mul0__is_32bit[0:0] $1\fus_oper_i_alu_mul0__is_32bit[0:0] + attribute \src "libresoc.v:44215.5-44215.29" + switch \initial + attribute \src "libresoc.v:44215.9-44215.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_mul0__is_32bit[0:0] $2\fus_oper_i_alu_mul0__is_32bit[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_mul0__is_32bit[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_mul0__is_32bit[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_mul0__is_32bit[0:0] $3\fus_oper_i_alu_mul0__is_32bit[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + switch \fu_enable [7] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_mul0__is_32bit[0:0] \dec_MUL_MUL__is_32bit + case + assign $3\fus_oper_i_alu_mul0__is_32bit[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_mul0__is_32bit[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_mul0__is_32bit $0\fus_oper_i_alu_mul0__is_32bit[0:0] + end + attribute \src "libresoc.v:44243.3-44271.6" + process $proc$libresoc.v:44243$2397 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_mul0__is_signed[0:0] $1\fus_oper_i_alu_mul0__is_signed[0:0] + attribute \src "libresoc.v:44244.5-44244.29" + switch \initial + attribute \src "libresoc.v:44244.9-44244.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_mul0__is_signed[0:0] $2\fus_oper_i_alu_mul0__is_signed[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_mul0__is_signed[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_mul0__is_signed[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_mul0__is_signed[0:0] $3\fus_oper_i_alu_mul0__is_signed[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + switch \fu_enable [7] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_mul0__is_signed[0:0] \dec_MUL_MUL__is_signed + case + assign $3\fus_oper_i_alu_mul0__is_signed[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_mul0__is_signed[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_mul0__is_signed $0\fus_oper_i_alu_mul0__is_signed[0:0] + end + attribute \src "libresoc.v:44272.3-44300.6" + process $proc$libresoc.v:44272$2398 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_mul0__insn[31:0] $1\fus_oper_i_alu_mul0__insn[31:0] + attribute \src "libresoc.v:44273.5-44273.29" + switch \initial + attribute \src "libresoc.v:44273.9-44273.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_mul0__insn[31:0] $2\fus_oper_i_alu_mul0__insn[31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_mul0__insn[31:0] 0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_mul0__insn[31:0] 0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_mul0__insn[31:0] $3\fus_oper_i_alu_mul0__insn[31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + switch \fu_enable [7] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_mul0__insn[31:0] \dec_MUL_MUL__insn + case + assign $3\fus_oper_i_alu_mul0__insn[31:0] 0 + end + end + case + assign $1\fus_oper_i_alu_mul0__insn[31:0] 0 + end + sync always + update \fus_oper_i_alu_mul0__insn $0\fus_oper_i_alu_mul0__insn[31:0] + end + attribute \src "libresoc.v:44301.3-44329.6" + process $proc$libresoc.v:44301$2399 + assign { } { } + assign { } { } + assign $0\fus_cu_issue_i$31[0:0]$2400 $1\fus_cu_issue_i$31[0:0]$2401 + attribute \src "libresoc.v:44302.5-44302.29" + switch \initial + attribute \src "libresoc.v:44302.9-44302.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_cu_issue_i$31[0:0]$2401 $2\fus_cu_issue_i$31[0:0]$2402 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_cu_issue_i$31[0:0]$2402 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_cu_issue_i$31[0:0]$2402 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_cu_issue_i$31[0:0]$2402 $3\fus_cu_issue_i$31[0:0]$2403 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + switch \fu_enable [7] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_cu_issue_i$31[0:0]$2403 \issue_i + case + assign $3\fus_cu_issue_i$31[0:0]$2403 1'0 + end + end + case + assign $1\fus_cu_issue_i$31[0:0]$2401 1'0 + end + sync always + update \fus_cu_issue_i$31 $0\fus_cu_issue_i$31[0:0]$2400 + end + attribute \src "libresoc.v:44330.3-44358.6" + process $proc$libresoc.v:44330$2404 + assign { } { } + assign { } { } + assign $0\fus_cu_rdmaskn_i$33[2:0]$2405 $1\fus_cu_rdmaskn_i$33[2:0]$2406 + attribute \src "libresoc.v:44331.5-44331.29" + switch \initial + attribute \src "libresoc.v:44331.9-44331.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_cu_rdmaskn_i$33[2:0]$2406 $2\fus_cu_rdmaskn_i$33[2:0]$2407 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_cu_rdmaskn_i$33[2:0]$2407 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_cu_rdmaskn_i$33[2:0]$2407 3'000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_cu_rdmaskn_i$33[2:0]$2407 $3\fus_cu_rdmaskn_i$33[2:0]$2408 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + switch \fu_enable [7] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_cu_rdmaskn_i$33[2:0]$2408 \$309 + case + assign $3\fus_cu_rdmaskn_i$33[2:0]$2408 3'000 + end + end + case + assign $1\fus_cu_rdmaskn_i$33[2:0]$2406 3'000 + end + sync always + update \fus_cu_rdmaskn_i$33 $0\fus_cu_rdmaskn_i$33[2:0]$2405 + end + attribute \src "libresoc.v:44359.3-44387.6" + process $proc$libresoc.v:44359$2409 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_shift_rot0__insn_type[6:0] $1\fus_oper_i_alu_shift_rot0__insn_type[6:0] + attribute \src "libresoc.v:44360.5-44360.29" + switch \initial + attribute \src "libresoc.v:44360.9-44360.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_shift_rot0__insn_type[6:0] $2\fus_oper_i_alu_shift_rot0__insn_type[6:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_shift_rot0__insn_type[6:0] 7'0000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_shift_rot0__insn_type[6:0] 7'0000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_shift_rot0__insn_type[6:0] $3\fus_oper_i_alu_shift_rot0__insn_type[6:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + switch \fu_enable [8] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_shift_rot0__insn_type[6:0] \dec_SHIFT_ROT_SHIFT_ROT__insn_type + case + assign $3\fus_oper_i_alu_shift_rot0__insn_type[6:0] 7'0000000 + end + end + case + assign $1\fus_oper_i_alu_shift_rot0__insn_type[6:0] 7'0000000 + end + sync always + update \fus_oper_i_alu_shift_rot0__insn_type $0\fus_oper_i_alu_shift_rot0__insn_type[6:0] + end + attribute \src "libresoc.v:44388.3-44416.6" + process $proc$libresoc.v:44388$2410 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_shift_rot0__fn_unit[12:0] $1\fus_oper_i_alu_shift_rot0__fn_unit[12:0] + attribute \src "libresoc.v:44389.5-44389.29" + switch \initial + attribute \src "libresoc.v:44389.9-44389.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_shift_rot0__fn_unit[12:0] $2\fus_oper_i_alu_shift_rot0__fn_unit[12:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_shift_rot0__fn_unit[12:0] 13'0000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_shift_rot0__fn_unit[12:0] 13'0000000000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_shift_rot0__fn_unit[12:0] $3\fus_oper_i_alu_shift_rot0__fn_unit[12:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + switch \fu_enable [8] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_shift_rot0__fn_unit[12:0] \dec_SHIFT_ROT_SHIFT_ROT__fn_unit + case + assign $3\fus_oper_i_alu_shift_rot0__fn_unit[12:0] 13'0000000000000 + end + end + case + assign $1\fus_oper_i_alu_shift_rot0__fn_unit[12:0] 13'0000000000000 + end + sync always + update \fus_oper_i_alu_shift_rot0__fn_unit $0\fus_oper_i_alu_shift_rot0__fn_unit[12:0] + end + attribute \src "libresoc.v:44417.3-44446.6" + process $proc$libresoc.v:44417$2411 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] $1\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] + assign $0\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] $1\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] + attribute \src "libresoc.v:44418.5-44418.29" + switch \initial + attribute \src "libresoc.v:44418.9-44418.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $1\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] $2\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] + assign $1\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] $2\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign $2\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] $3\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] + assign $2\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] $3\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + switch \fu_enable [8] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $3\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] $3\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] } { \dec_SHIFT_ROT_SHIFT_ROT__imm_data__ok \dec_SHIFT_ROT_SHIFT_ROT__imm_data__data } + case + assign $3\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_shift_rot0__imm_data__data $0\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] + update \fus_oper_i_alu_shift_rot0__imm_data__ok $0\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] + end + attribute \src "libresoc.v:44447.3-44476.6" + process $proc$libresoc.v:44447$2412 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_shift_rot0__rc__ok[0:0] $1\fus_oper_i_alu_shift_rot0__rc__ok[0:0] + assign $0\fus_oper_i_alu_shift_rot0__rc__rc[0:0] $1\fus_oper_i_alu_shift_rot0__rc__rc[0:0] + attribute \src "libresoc.v:44448.5-44448.29" + switch \initial + attribute \src "libresoc.v:44448.9-44448.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $1\fus_oper_i_alu_shift_rot0__rc__ok[0:0] $2\fus_oper_i_alu_shift_rot0__rc__ok[0:0] + assign $1\fus_oper_i_alu_shift_rot0__rc__rc[0:0] $2\fus_oper_i_alu_shift_rot0__rc__rc[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_shift_rot0__rc__ok[0:0] 1'0 + assign $2\fus_oper_i_alu_shift_rot0__rc__rc[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_shift_rot0__rc__ok[0:0] 1'0 + assign $2\fus_oper_i_alu_shift_rot0__rc__rc[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign $2\fus_oper_i_alu_shift_rot0__rc__ok[0:0] $3\fus_oper_i_alu_shift_rot0__rc__ok[0:0] + assign $2\fus_oper_i_alu_shift_rot0__rc__rc[0:0] $3\fus_oper_i_alu_shift_rot0__rc__rc[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + switch \fu_enable [8] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $3\fus_oper_i_alu_shift_rot0__rc__ok[0:0] $3\fus_oper_i_alu_shift_rot0__rc__rc[0:0] } { \dec_SHIFT_ROT_SHIFT_ROT__rc__ok \dec_SHIFT_ROT_SHIFT_ROT__rc__rc } + case + assign $3\fus_oper_i_alu_shift_rot0__rc__ok[0:0] 1'0 + assign $3\fus_oper_i_alu_shift_rot0__rc__rc[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_shift_rot0__rc__ok[0:0] 1'0 + assign $1\fus_oper_i_alu_shift_rot0__rc__rc[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_shift_rot0__rc__ok $0\fus_oper_i_alu_shift_rot0__rc__ok[0:0] + update \fus_oper_i_alu_shift_rot0__rc__rc $0\fus_oper_i_alu_shift_rot0__rc__rc[0:0] + end + attribute \src "libresoc.v:44477.3-44506.6" + process $proc$libresoc.v:44477$2413 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_shift_rot0__oe__oe[0:0] $1\fus_oper_i_alu_shift_rot0__oe__oe[0:0] + assign $0\fus_oper_i_alu_shift_rot0__oe__ok[0:0] $1\fus_oper_i_alu_shift_rot0__oe__ok[0:0] + attribute \src "libresoc.v:44478.5-44478.29" + switch \initial + attribute \src "libresoc.v:44478.9-44478.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $1\fus_oper_i_alu_shift_rot0__oe__oe[0:0] $2\fus_oper_i_alu_shift_rot0__oe__oe[0:0] + assign $1\fus_oper_i_alu_shift_rot0__oe__ok[0:0] $2\fus_oper_i_alu_shift_rot0__oe__ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_shift_rot0__oe__oe[0:0] 1'0 + assign $2\fus_oper_i_alu_shift_rot0__oe__ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_shift_rot0__oe__oe[0:0] 1'0 + assign $2\fus_oper_i_alu_shift_rot0__oe__ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign $2\fus_oper_i_alu_shift_rot0__oe__oe[0:0] $3\fus_oper_i_alu_shift_rot0__oe__oe[0:0] + assign $2\fus_oper_i_alu_shift_rot0__oe__ok[0:0] $3\fus_oper_i_alu_shift_rot0__oe__ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + switch \fu_enable [8] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $3\fus_oper_i_alu_shift_rot0__oe__ok[0:0] $3\fus_oper_i_alu_shift_rot0__oe__oe[0:0] } { \dec_SHIFT_ROT_SHIFT_ROT__oe__ok \dec_SHIFT_ROT_SHIFT_ROT__oe__oe } + case + assign $3\fus_oper_i_alu_shift_rot0__oe__oe[0:0] 1'0 + assign $3\fus_oper_i_alu_shift_rot0__oe__ok[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_shift_rot0__oe__oe[0:0] 1'0 + assign $1\fus_oper_i_alu_shift_rot0__oe__ok[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_shift_rot0__oe__oe $0\fus_oper_i_alu_shift_rot0__oe__oe[0:0] + update \fus_oper_i_alu_shift_rot0__oe__ok $0\fus_oper_i_alu_shift_rot0__oe__ok[0:0] + end + attribute \src "libresoc.v:44507.3-44535.6" + process $proc$libresoc.v:44507$2414 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_shift_rot0__write_cr0[0:0] $1\fus_oper_i_alu_shift_rot0__write_cr0[0:0] + attribute \src "libresoc.v:44508.5-44508.29" + switch \initial + attribute \src "libresoc.v:44508.9-44508.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_shift_rot0__write_cr0[0:0] $2\fus_oper_i_alu_shift_rot0__write_cr0[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_shift_rot0__write_cr0[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_shift_rot0__write_cr0[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_shift_rot0__write_cr0[0:0] $3\fus_oper_i_alu_shift_rot0__write_cr0[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + switch \fu_enable [8] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_shift_rot0__write_cr0[0:0] \dec_SHIFT_ROT_SHIFT_ROT__write_cr0 + case + assign $3\fus_oper_i_alu_shift_rot0__write_cr0[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_shift_rot0__write_cr0[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_shift_rot0__write_cr0 $0\fus_oper_i_alu_shift_rot0__write_cr0[0:0] + end + attribute \src "libresoc.v:44536.3-44564.6" + process $proc$libresoc.v:44536$2415 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_shift_rot0__invert_in[0:0] $1\fus_oper_i_alu_shift_rot0__invert_in[0:0] + attribute \src "libresoc.v:44537.5-44537.29" + switch \initial + attribute \src "libresoc.v:44537.9-44537.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_shift_rot0__invert_in[0:0] $2\fus_oper_i_alu_shift_rot0__invert_in[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_shift_rot0__invert_in[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_shift_rot0__invert_in[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_shift_rot0__invert_in[0:0] $3\fus_oper_i_alu_shift_rot0__invert_in[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + switch \fu_enable [8] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_shift_rot0__invert_in[0:0] \dec_SHIFT_ROT_SHIFT_ROT__invert_in + case + assign $3\fus_oper_i_alu_shift_rot0__invert_in[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_shift_rot0__invert_in[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_shift_rot0__invert_in $0\fus_oper_i_alu_shift_rot0__invert_in[0:0] + end + attribute \src "libresoc.v:44565.3-44593.6" + process $proc$libresoc.v:44565$2416 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_shift_rot0__input_carry[1:0] $1\fus_oper_i_alu_shift_rot0__input_carry[1:0] + attribute \src "libresoc.v:44566.5-44566.29" + switch \initial + attribute \src "libresoc.v:44566.9-44566.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_shift_rot0__input_carry[1:0] $2\fus_oper_i_alu_shift_rot0__input_carry[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_shift_rot0__input_carry[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_shift_rot0__input_carry[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_shift_rot0__input_carry[1:0] $3\fus_oper_i_alu_shift_rot0__input_carry[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + switch \fu_enable [8] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_shift_rot0__input_carry[1:0] \dec_SHIFT_ROT_SHIFT_ROT__input_carry + case + assign $3\fus_oper_i_alu_shift_rot0__input_carry[1:0] 2'00 + end + end + case + assign $1\fus_oper_i_alu_shift_rot0__input_carry[1:0] 2'00 + end + sync always + update \fus_oper_i_alu_shift_rot0__input_carry $0\fus_oper_i_alu_shift_rot0__input_carry[1:0] + end + attribute \src "libresoc.v:44594.3-44622.6" + process $proc$libresoc.v:44594$2417 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_shift_rot0__output_carry[0:0] $1\fus_oper_i_alu_shift_rot0__output_carry[0:0] + attribute \src "libresoc.v:44595.5-44595.29" + switch \initial + attribute \src "libresoc.v:44595.9-44595.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_shift_rot0__output_carry[0:0] $2\fus_oper_i_alu_shift_rot0__output_carry[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_shift_rot0__output_carry[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_shift_rot0__output_carry[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_shift_rot0__output_carry[0:0] $3\fus_oper_i_alu_shift_rot0__output_carry[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + switch \fu_enable [8] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_shift_rot0__output_carry[0:0] \dec_SHIFT_ROT_SHIFT_ROT__output_carry + case + assign $3\fus_oper_i_alu_shift_rot0__output_carry[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_shift_rot0__output_carry[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_shift_rot0__output_carry $0\fus_oper_i_alu_shift_rot0__output_carry[0:0] + end + attribute \src "libresoc.v:44623.3-44651.6" + process $proc$libresoc.v:44623$2418 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_shift_rot0__input_cr[0:0] $1\fus_oper_i_alu_shift_rot0__input_cr[0:0] + attribute \src "libresoc.v:44624.5-44624.29" + switch \initial + attribute \src "libresoc.v:44624.9-44624.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_shift_rot0__input_cr[0:0] $2\fus_oper_i_alu_shift_rot0__input_cr[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_shift_rot0__input_cr[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_shift_rot0__input_cr[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_shift_rot0__input_cr[0:0] $3\fus_oper_i_alu_shift_rot0__input_cr[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + switch \fu_enable [8] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_shift_rot0__input_cr[0:0] \dec_SHIFT_ROT_SHIFT_ROT__input_cr + case + assign $3\fus_oper_i_alu_shift_rot0__input_cr[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_shift_rot0__input_cr[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_shift_rot0__input_cr $0\fus_oper_i_alu_shift_rot0__input_cr[0:0] + end + attribute \src "libresoc.v:44652.3-44680.6" + process $proc$libresoc.v:44652$2419 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_shift_rot0__output_cr[0:0] $1\fus_oper_i_alu_shift_rot0__output_cr[0:0] + attribute \src "libresoc.v:44653.5-44653.29" + switch \initial + attribute \src "libresoc.v:44653.9-44653.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_shift_rot0__output_cr[0:0] $2\fus_oper_i_alu_shift_rot0__output_cr[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_shift_rot0__output_cr[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_shift_rot0__output_cr[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_shift_rot0__output_cr[0:0] $3\fus_oper_i_alu_shift_rot0__output_cr[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + switch \fu_enable [8] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_shift_rot0__output_cr[0:0] \dec_SHIFT_ROT_SHIFT_ROT__output_cr + case + assign $3\fus_oper_i_alu_shift_rot0__output_cr[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_shift_rot0__output_cr[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_shift_rot0__output_cr $0\fus_oper_i_alu_shift_rot0__output_cr[0:0] + end + attribute \src "libresoc.v:44681.3-44709.6" + process $proc$libresoc.v:44681$2420 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_shift_rot0__is_32bit[0:0] $1\fus_oper_i_alu_shift_rot0__is_32bit[0:0] + attribute \src "libresoc.v:44682.5-44682.29" + switch \initial + attribute \src "libresoc.v:44682.9-44682.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_shift_rot0__is_32bit[0:0] $2\fus_oper_i_alu_shift_rot0__is_32bit[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_shift_rot0__is_32bit[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_shift_rot0__is_32bit[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_shift_rot0__is_32bit[0:0] $3\fus_oper_i_alu_shift_rot0__is_32bit[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + switch \fu_enable [8] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_shift_rot0__is_32bit[0:0] \dec_SHIFT_ROT_SHIFT_ROT__is_32bit + case + assign $3\fus_oper_i_alu_shift_rot0__is_32bit[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_shift_rot0__is_32bit[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_shift_rot0__is_32bit $0\fus_oper_i_alu_shift_rot0__is_32bit[0:0] + end + attribute \src "libresoc.v:44710.3-44738.6" + process $proc$libresoc.v:44710$2421 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_shift_rot0__is_signed[0:0] $1\fus_oper_i_alu_shift_rot0__is_signed[0:0] + attribute \src "libresoc.v:44711.5-44711.29" + switch \initial + attribute \src "libresoc.v:44711.9-44711.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_shift_rot0__is_signed[0:0] $2\fus_oper_i_alu_shift_rot0__is_signed[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_shift_rot0__is_signed[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_shift_rot0__is_signed[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_shift_rot0__is_signed[0:0] $3\fus_oper_i_alu_shift_rot0__is_signed[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + switch \fu_enable [8] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_shift_rot0__is_signed[0:0] \dec_SHIFT_ROT_SHIFT_ROT__is_signed + case + assign $3\fus_oper_i_alu_shift_rot0__is_signed[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_shift_rot0__is_signed[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_shift_rot0__is_signed $0\fus_oper_i_alu_shift_rot0__is_signed[0:0] + end + attribute \src "libresoc.v:44739.3-44767.6" + process $proc$libresoc.v:44739$2422 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_shift_rot0__insn[31:0] $1\fus_oper_i_alu_shift_rot0__insn[31:0] + attribute \src "libresoc.v:44740.5-44740.29" + switch \initial + attribute \src "libresoc.v:44740.9-44740.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_shift_rot0__insn[31:0] $2\fus_oper_i_alu_shift_rot0__insn[31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_shift_rot0__insn[31:0] 0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_shift_rot0__insn[31:0] 0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_shift_rot0__insn[31:0] $3\fus_oper_i_alu_shift_rot0__insn[31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + switch \fu_enable [8] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_shift_rot0__insn[31:0] \dec_SHIFT_ROT_SHIFT_ROT__insn + case + assign $3\fus_oper_i_alu_shift_rot0__insn[31:0] 0 + end + end + case + assign $1\fus_oper_i_alu_shift_rot0__insn[31:0] 0 + end + sync always + update \fus_oper_i_alu_shift_rot0__insn $0\fus_oper_i_alu_shift_rot0__insn[31:0] + end + attribute \src "libresoc.v:44768.3-44796.6" + process $proc$libresoc.v:44768$2423 + assign { } { } + assign { } { } + assign $0\fus_cu_issue_i$34[0:0]$2424 $1\fus_cu_issue_i$34[0:0]$2425 + attribute \src "libresoc.v:44769.5-44769.29" + switch \initial + attribute \src "libresoc.v:44769.9-44769.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_cu_issue_i$34[0:0]$2425 $2\fus_cu_issue_i$34[0:0]$2426 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_cu_issue_i$34[0:0]$2426 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_cu_issue_i$34[0:0]$2426 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_cu_issue_i$34[0:0]$2426 $3\fus_cu_issue_i$34[0:0]$2427 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + switch \fu_enable [8] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_cu_issue_i$34[0:0]$2427 \issue_i + case + assign $3\fus_cu_issue_i$34[0:0]$2427 1'0 + end + end + case + assign $1\fus_cu_issue_i$34[0:0]$2425 1'0 + end + sync always + update \fus_cu_issue_i$34 $0\fus_cu_issue_i$34[0:0]$2424 + end + attribute \src "libresoc.v:44797.3-44825.6" + process $proc$libresoc.v:44797$2428 + assign { } { } + assign { } { } + assign $0\fus_cu_rdmaskn_i$36[4:0]$2429 $1\fus_cu_rdmaskn_i$36[4:0]$2430 + attribute \src "libresoc.v:44798.5-44798.29" + switch \initial + attribute \src "libresoc.v:44798.9-44798.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_cu_rdmaskn_i$36[4:0]$2430 $2\fus_cu_rdmaskn_i$36[4:0]$2431 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_cu_rdmaskn_i$36[4:0]$2431 5'00000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_cu_rdmaskn_i$36[4:0]$2431 5'00000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_cu_rdmaskn_i$36[4:0]$2431 $3\fus_cu_rdmaskn_i$36[4:0]$2432 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + switch \fu_enable [8] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_cu_rdmaskn_i$36[4:0]$2432 \$323 + case + assign $3\fus_cu_rdmaskn_i$36[4:0]$2432 5'00000 + end + end + case + assign $1\fus_cu_rdmaskn_i$36[4:0]$2430 5'00000 + end + sync always + update \fus_cu_rdmaskn_i$36 $0\fus_cu_rdmaskn_i$36[4:0]$2429 + end + attribute \src "libresoc.v:44826.3-44854.6" + process $proc$libresoc.v:44826$2433 + assign { } { } + assign { } { } + assign $0\fus_oper_i_ldst_ldst0__insn_type[6:0] $1\fus_oper_i_ldst_ldst0__insn_type[6:0] + attribute \src "libresoc.v:44827.5-44827.29" + switch \initial + attribute \src "libresoc.v:44827.9-44827.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_ldst_ldst0__insn_type[6:0] $2\fus_oper_i_ldst_ldst0__insn_type[6:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_ldst_ldst0__insn_type[6:0] 7'0000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_ldst_ldst0__insn_type[6:0] 7'0000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_ldst_ldst0__insn_type[6:0] $3\fus_oper_i_ldst_ldst0__insn_type[6:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + switch \fu_enable [9] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_ldst_ldst0__insn_type[6:0] \dec_LDST_LDST__insn_type + case + assign $3\fus_oper_i_ldst_ldst0__insn_type[6:0] 7'0000000 + end + end + case + assign $1\fus_oper_i_ldst_ldst0__insn_type[6:0] 7'0000000 + end + sync always + update \fus_oper_i_ldst_ldst0__insn_type $0\fus_oper_i_ldst_ldst0__insn_type[6:0] + end + attribute \src "libresoc.v:44855.3-44883.6" + process $proc$libresoc.v:44855$2434 + assign { } { } + assign { } { } + assign $0\fus_oper_i_ldst_ldst0__fn_unit[12:0] $1\fus_oper_i_ldst_ldst0__fn_unit[12:0] + attribute \src "libresoc.v:44856.5-44856.29" + switch \initial + attribute \src "libresoc.v:44856.9-44856.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_ldst_ldst0__fn_unit[12:0] $2\fus_oper_i_ldst_ldst0__fn_unit[12:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_ldst_ldst0__fn_unit[12:0] 13'0000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_ldst_ldst0__fn_unit[12:0] 13'0000000000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_ldst_ldst0__fn_unit[12:0] $3\fus_oper_i_ldst_ldst0__fn_unit[12:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + switch \fu_enable [9] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_ldst_ldst0__fn_unit[12:0] \dec_LDST_LDST__fn_unit + case + assign $3\fus_oper_i_ldst_ldst0__fn_unit[12:0] 13'0000000000000 + end + end + case + assign $1\fus_oper_i_ldst_ldst0__fn_unit[12:0] 13'0000000000000 + end + sync always + update \fus_oper_i_ldst_ldst0__fn_unit $0\fus_oper_i_ldst_ldst0__fn_unit[12:0] + end + attribute \src "libresoc.v:44884.3-44913.6" + process $proc$libresoc.v:44884$2435 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\fus_oper_i_ldst_ldst0__imm_data__data[63:0] $1\fus_oper_i_ldst_ldst0__imm_data__data[63:0] + assign $0\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] $1\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] + attribute \src "libresoc.v:44885.5-44885.29" + switch \initial + attribute \src "libresoc.v:44885.9-44885.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $1\fus_oper_i_ldst_ldst0__imm_data__data[63:0] $2\fus_oper_i_ldst_ldst0__imm_data__data[63:0] + assign $1\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] $2\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_ldst_ldst0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_ldst_ldst0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign $2\fus_oper_i_ldst_ldst0__imm_data__data[63:0] $3\fus_oper_i_ldst_ldst0__imm_data__data[63:0] + assign $2\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] $3\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + switch \fu_enable [9] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $3\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] $3\fus_oper_i_ldst_ldst0__imm_data__data[63:0] } { \dec_LDST_LDST__imm_data__ok \dec_LDST_LDST__imm_data__data } + case + assign $3\fus_oper_i_ldst_ldst0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_ldst_ldst0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] 1'0 + end + sync always + update \fus_oper_i_ldst_ldst0__imm_data__data $0\fus_oper_i_ldst_ldst0__imm_data__data[63:0] + update \fus_oper_i_ldst_ldst0__imm_data__ok $0\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] + end + attribute \src "libresoc.v:44914.3-44942.6" + process $proc$libresoc.v:44914$2436 + assign { } { } + assign { } { } + assign $0\fus_oper_i_ldst_ldst0__zero_a[0:0] $1\fus_oper_i_ldst_ldst0__zero_a[0:0] + attribute \src "libresoc.v:44915.5-44915.29" + switch \initial + attribute \src "libresoc.v:44915.9-44915.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_ldst_ldst0__zero_a[0:0] $2\fus_oper_i_ldst_ldst0__zero_a[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_ldst_ldst0__zero_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_ldst_ldst0__zero_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_ldst_ldst0__zero_a[0:0] $3\fus_oper_i_ldst_ldst0__zero_a[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + switch \fu_enable [9] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_ldst_ldst0__zero_a[0:0] \dec_LDST_LDST__zero_a + case + assign $3\fus_oper_i_ldst_ldst0__zero_a[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_ldst_ldst0__zero_a[0:0] 1'0 + end + sync always + update \fus_oper_i_ldst_ldst0__zero_a $0\fus_oper_i_ldst_ldst0__zero_a[0:0] + end + attribute \src "libresoc.v:44943.3-44972.6" + process $proc$libresoc.v:44943$2437 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\fus_oper_i_ldst_ldst0__rc__ok[0:0] $1\fus_oper_i_ldst_ldst0__rc__ok[0:0] + assign $0\fus_oper_i_ldst_ldst0__rc__rc[0:0] $1\fus_oper_i_ldst_ldst0__rc__rc[0:0] + attribute \src "libresoc.v:44944.5-44944.29" + switch \initial + attribute \src "libresoc.v:44944.9-44944.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $1\fus_oper_i_ldst_ldst0__rc__ok[0:0] $2\fus_oper_i_ldst_ldst0__rc__ok[0:0] + assign $1\fus_oper_i_ldst_ldst0__rc__rc[0:0] $2\fus_oper_i_ldst_ldst0__rc__rc[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_ldst_ldst0__rc__ok[0:0] 1'0 + assign $2\fus_oper_i_ldst_ldst0__rc__rc[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_ldst_ldst0__rc__ok[0:0] 1'0 + assign $2\fus_oper_i_ldst_ldst0__rc__rc[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign $2\fus_oper_i_ldst_ldst0__rc__ok[0:0] $3\fus_oper_i_ldst_ldst0__rc__ok[0:0] + assign $2\fus_oper_i_ldst_ldst0__rc__rc[0:0] $3\fus_oper_i_ldst_ldst0__rc__rc[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + switch \fu_enable [9] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $3\fus_oper_i_ldst_ldst0__rc__ok[0:0] $3\fus_oper_i_ldst_ldst0__rc__rc[0:0] } { \dec_LDST_LDST__rc__ok \dec_LDST_LDST__rc__rc } + case + assign $3\fus_oper_i_ldst_ldst0__rc__ok[0:0] 1'0 + assign $3\fus_oper_i_ldst_ldst0__rc__rc[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_ldst_ldst0__rc__ok[0:0] 1'0 + assign $1\fus_oper_i_ldst_ldst0__rc__rc[0:0] 1'0 + end + sync always + update \fus_oper_i_ldst_ldst0__rc__ok $0\fus_oper_i_ldst_ldst0__rc__ok[0:0] + update \fus_oper_i_ldst_ldst0__rc__rc $0\fus_oper_i_ldst_ldst0__rc__rc[0:0] + end + attribute \src "libresoc.v:44973.3-45002.6" + process $proc$libresoc.v:44973$2438 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\fus_oper_i_ldst_ldst0__oe__oe[0:0] $1\fus_oper_i_ldst_ldst0__oe__oe[0:0] + assign $0\fus_oper_i_ldst_ldst0__oe__ok[0:0] $1\fus_oper_i_ldst_ldst0__oe__ok[0:0] + attribute \src "libresoc.v:44974.5-44974.29" + switch \initial + attribute \src "libresoc.v:44974.9-44974.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $1\fus_oper_i_ldst_ldst0__oe__oe[0:0] $2\fus_oper_i_ldst_ldst0__oe__oe[0:0] + assign $1\fus_oper_i_ldst_ldst0__oe__ok[0:0] $2\fus_oper_i_ldst_ldst0__oe__ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_ldst_ldst0__oe__oe[0:0] 1'0 + assign $2\fus_oper_i_ldst_ldst0__oe__ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_ldst_ldst0__oe__oe[0:0] 1'0 + assign $2\fus_oper_i_ldst_ldst0__oe__ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign $2\fus_oper_i_ldst_ldst0__oe__oe[0:0] $3\fus_oper_i_ldst_ldst0__oe__oe[0:0] + assign $2\fus_oper_i_ldst_ldst0__oe__ok[0:0] $3\fus_oper_i_ldst_ldst0__oe__ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + switch \fu_enable [9] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $3\fus_oper_i_ldst_ldst0__oe__ok[0:0] $3\fus_oper_i_ldst_ldst0__oe__oe[0:0] } { \dec_LDST_LDST__oe__ok \dec_LDST_LDST__oe__oe } + case + assign $3\fus_oper_i_ldst_ldst0__oe__oe[0:0] 1'0 + assign $3\fus_oper_i_ldst_ldst0__oe__ok[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_ldst_ldst0__oe__oe[0:0] 1'0 + assign $1\fus_oper_i_ldst_ldst0__oe__ok[0:0] 1'0 + end + sync always + update \fus_oper_i_ldst_ldst0__oe__oe $0\fus_oper_i_ldst_ldst0__oe__oe[0:0] + update \fus_oper_i_ldst_ldst0__oe__ok $0\fus_oper_i_ldst_ldst0__oe__ok[0:0] + end + attribute \src "libresoc.v:45003.3-45031.6" + process $proc$libresoc.v:45003$2439 + assign { } { } + assign { } { } + assign $0\fus_oper_i_ldst_ldst0__is_32bit[0:0] $1\fus_oper_i_ldst_ldst0__is_32bit[0:0] + attribute \src "libresoc.v:45004.5-45004.29" + switch \initial + attribute \src "libresoc.v:45004.9-45004.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_ldst_ldst0__is_32bit[0:0] $2\fus_oper_i_ldst_ldst0__is_32bit[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_ldst_ldst0__is_32bit[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_ldst_ldst0__is_32bit[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_ldst_ldst0__is_32bit[0:0] $3\fus_oper_i_ldst_ldst0__is_32bit[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + switch \fu_enable [9] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_ldst_ldst0__is_32bit[0:0] \dec_LDST_LDST__is_32bit + case + assign $3\fus_oper_i_ldst_ldst0__is_32bit[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_ldst_ldst0__is_32bit[0:0] 1'0 + end + sync always + update \fus_oper_i_ldst_ldst0__is_32bit $0\fus_oper_i_ldst_ldst0__is_32bit[0:0] + end + attribute \src "libresoc.v:45032.3-45060.6" + process $proc$libresoc.v:45032$2440 + assign { } { } + assign { } { } + assign $0\fus_oper_i_ldst_ldst0__is_signed[0:0] $1\fus_oper_i_ldst_ldst0__is_signed[0:0] + attribute \src "libresoc.v:45033.5-45033.29" + switch \initial + attribute \src "libresoc.v:45033.9-45033.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_ldst_ldst0__is_signed[0:0] $2\fus_oper_i_ldst_ldst0__is_signed[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_ldst_ldst0__is_signed[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_ldst_ldst0__is_signed[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_ldst_ldst0__is_signed[0:0] $3\fus_oper_i_ldst_ldst0__is_signed[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + switch \fu_enable [9] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_ldst_ldst0__is_signed[0:0] \dec_LDST_LDST__is_signed + case + assign $3\fus_oper_i_ldst_ldst0__is_signed[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_ldst_ldst0__is_signed[0:0] 1'0 + end + sync always + update \fus_oper_i_ldst_ldst0__is_signed $0\fus_oper_i_ldst_ldst0__is_signed[0:0] + end + attribute \src "libresoc.v:45061.3-45089.6" + process $proc$libresoc.v:45061$2441 + assign { } { } + assign { } { } + assign $0\fus_oper_i_ldst_ldst0__data_len[3:0] $1\fus_oper_i_ldst_ldst0__data_len[3:0] + attribute \src "libresoc.v:45062.5-45062.29" + switch \initial + attribute \src "libresoc.v:45062.9-45062.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_ldst_ldst0__data_len[3:0] $2\fus_oper_i_ldst_ldst0__data_len[3:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_ldst_ldst0__data_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_ldst_ldst0__data_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_ldst_ldst0__data_len[3:0] $3\fus_oper_i_ldst_ldst0__data_len[3:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + switch \fu_enable [9] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_ldst_ldst0__data_len[3:0] \dec_LDST_LDST__data_len + case + assign $3\fus_oper_i_ldst_ldst0__data_len[3:0] 4'0000 + end + end + case + assign $1\fus_oper_i_ldst_ldst0__data_len[3:0] 4'0000 + end + sync always + update \fus_oper_i_ldst_ldst0__data_len $0\fus_oper_i_ldst_ldst0__data_len[3:0] + end + attribute \src "libresoc.v:45090.3-45118.6" + process $proc$libresoc.v:45090$2442 + assign { } { } + assign { } { } + assign $0\fus_oper_i_ldst_ldst0__byte_reverse[0:0] $1\fus_oper_i_ldst_ldst0__byte_reverse[0:0] + attribute \src "libresoc.v:45091.5-45091.29" + switch \initial + attribute \src "libresoc.v:45091.9-45091.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_ldst_ldst0__byte_reverse[0:0] $2\fus_oper_i_ldst_ldst0__byte_reverse[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_ldst_ldst0__byte_reverse[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_ldst_ldst0__byte_reverse[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_ldst_ldst0__byte_reverse[0:0] $3\fus_oper_i_ldst_ldst0__byte_reverse[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + switch \fu_enable [9] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_ldst_ldst0__byte_reverse[0:0] \dec_LDST_LDST__byte_reverse + case + assign $3\fus_oper_i_ldst_ldst0__byte_reverse[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_ldst_ldst0__byte_reverse[0:0] 1'0 + end + sync always + update \fus_oper_i_ldst_ldst0__byte_reverse $0\fus_oper_i_ldst_ldst0__byte_reverse[0:0] + end + attribute \src "libresoc.v:45119.3-45147.6" + process $proc$libresoc.v:45119$2443 + assign { } { } + assign { } { } + assign $0\fus_oper_i_ldst_ldst0__sign_extend[0:0] $1\fus_oper_i_ldst_ldst0__sign_extend[0:0] + attribute \src "libresoc.v:45120.5-45120.29" + switch \initial + attribute \src "libresoc.v:45120.9-45120.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_ldst_ldst0__sign_extend[0:0] $2\fus_oper_i_ldst_ldst0__sign_extend[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_ldst_ldst0__sign_extend[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_ldst_ldst0__sign_extend[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_ldst_ldst0__sign_extend[0:0] $3\fus_oper_i_ldst_ldst0__sign_extend[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + switch \fu_enable [9] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_ldst_ldst0__sign_extend[0:0] \dec_LDST_LDST__sign_extend + case + assign $3\fus_oper_i_ldst_ldst0__sign_extend[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_ldst_ldst0__sign_extend[0:0] 1'0 + end + sync always + update \fus_oper_i_ldst_ldst0__sign_extend $0\fus_oper_i_ldst_ldst0__sign_extend[0:0] + end + attribute \src "libresoc.v:45148.3-45176.6" + process $proc$libresoc.v:45148$2444 + assign { } { } + assign { } { } + assign $0\fus_oper_i_ldst_ldst0__ldst_mode[1:0] $1\fus_oper_i_ldst_ldst0__ldst_mode[1:0] + attribute \src "libresoc.v:45149.5-45149.29" + switch \initial + attribute \src "libresoc.v:45149.9-45149.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_ldst_ldst0__ldst_mode[1:0] $2\fus_oper_i_ldst_ldst0__ldst_mode[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_ldst_ldst0__ldst_mode[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_ldst_ldst0__ldst_mode[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_ldst_ldst0__ldst_mode[1:0] $3\fus_oper_i_ldst_ldst0__ldst_mode[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + switch \fu_enable [9] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_ldst_ldst0__ldst_mode[1:0] \dec_LDST_LDST__ldst_mode + case + assign $3\fus_oper_i_ldst_ldst0__ldst_mode[1:0] 2'00 + end + end + case + assign $1\fus_oper_i_ldst_ldst0__ldst_mode[1:0] 2'00 + end + sync always + update \fus_oper_i_ldst_ldst0__ldst_mode $0\fus_oper_i_ldst_ldst0__ldst_mode[1:0] + end + attribute \src "libresoc.v:45177.3-45205.6" + process $proc$libresoc.v:45177$2445 + assign { } { } + assign { } { } + assign $0\fus_oper_i_ldst_ldst0__insn[31:0] $1\fus_oper_i_ldst_ldst0__insn[31:0] + attribute \src "libresoc.v:45178.5-45178.29" + switch \initial + attribute \src "libresoc.v:45178.9-45178.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_ldst_ldst0__insn[31:0] $2\fus_oper_i_ldst_ldst0__insn[31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_ldst_ldst0__insn[31:0] 0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_ldst_ldst0__insn[31:0] 0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_ldst_ldst0__insn[31:0] $3\fus_oper_i_ldst_ldst0__insn[31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + switch \fu_enable [9] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_ldst_ldst0__insn[31:0] \dec_LDST_LDST__insn + case + assign $3\fus_oper_i_ldst_ldst0__insn[31:0] 0 + end + end + case + assign $1\fus_oper_i_ldst_ldst0__insn[31:0] 0 + end + sync always + update \fus_oper_i_ldst_ldst0__insn $0\fus_oper_i_ldst_ldst0__insn[31:0] + end + attribute \src "libresoc.v:45206.3-45234.6" + process $proc$libresoc.v:45206$2446 + assign { } { } + assign { } { } + assign $0\fus_cu_issue_i$37[0:0]$2447 $1\fus_cu_issue_i$37[0:0]$2448 + attribute \src "libresoc.v:45207.5-45207.29" + switch \initial + attribute \src "libresoc.v:45207.9-45207.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_cu_issue_i$37[0:0]$2448 $2\fus_cu_issue_i$37[0:0]$2449 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_cu_issue_i$37[0:0]$2449 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_cu_issue_i$37[0:0]$2449 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_cu_issue_i$37[0:0]$2449 $3\fus_cu_issue_i$37[0:0]$2450 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + switch \fu_enable [9] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_cu_issue_i$37[0:0]$2450 \issue_i + case + assign $3\fus_cu_issue_i$37[0:0]$2450 1'0 + end + end + case + assign $1\fus_cu_issue_i$37[0:0]$2448 1'0 + end + sync always + update \fus_cu_issue_i$37 $0\fus_cu_issue_i$37[0:0]$2447 + end + attribute \src "libresoc.v:45235.3-45263.6" + process $proc$libresoc.v:45235$2451 + assign { } { } + assign { } { } + assign $0\fus_cu_rdmaskn_i$39[2:0]$2452 $1\fus_cu_rdmaskn_i$39[2:0]$2453 + attribute \src "libresoc.v:45236.5-45236.29" + switch \initial + attribute \src "libresoc.v:45236.9-45236.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_cu_rdmaskn_i$39[2:0]$2453 $2\fus_cu_rdmaskn_i$39[2:0]$2454 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_cu_rdmaskn_i$39[2:0]$2454 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_cu_rdmaskn_i$39[2:0]$2454 3'000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_cu_rdmaskn_i$39[2:0]$2454 $3\fus_cu_rdmaskn_i$39[2:0]$2455 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + switch \fu_enable [9] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_cu_rdmaskn_i$39[2:0]$2455 \$345 + case + assign $3\fus_cu_rdmaskn_i$39[2:0]$2455 3'000 + end + end + case + assign $1\fus_cu_rdmaskn_i$39[2:0]$2453 3'000 + end + sync always + update \fus_cu_rdmaskn_i$39 $0\fus_cu_rdmaskn_i$39[2:0]$2452 + end + attribute \src "libresoc.v:45264.3-45272.6" + process $proc$libresoc.v:45264$2456 + assign { } { } + assign { } { } + assign $0\dp_INT_ra_alu0_0$next[0:0]$2457 $1\dp_INT_ra_alu0_0$next[0:0]$2458 + attribute \src "libresoc.v:45265.5-45265.29" + switch \initial + attribute \src "libresoc.v:45265.9-45265.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_INT_ra_alu0_0$next[0:0]$2458 1'0 + case + assign $1\dp_INT_ra_alu0_0$next[0:0]$2458 \rp_INT_ra_alu0_0 + end + sync always + update \dp_INT_ra_alu0_0$next $0\dp_INT_ra_alu0_0$next[0:0]$2457 + end + attribute \src "libresoc.v:45273.3-45282.6" + process $proc$libresoc.v:45273$2459 + assign { } { } + assign { } { } + assign $0\fus_src1_i[63:0] $1\fus_src1_i[63:0] + attribute \src "libresoc.v:45274.5-45274.29" + switch \initial + attribute \src "libresoc.v:45274.9-45274.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:294" + switch \dp_INT_ra_alu0_0 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src1_i[63:0] \int_src1__data_o + case + assign $1\fus_src1_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fus_src1_i $0\fus_src1_i[63:0] + end + attribute \src "libresoc.v:45283.3-45291.6" + process $proc$libresoc.v:45283$2460 + assign { } { } + assign { } { } + assign $0\dp_INT_ra_cr0_1$next[0:0]$2461 $1\dp_INT_ra_cr0_1$next[0:0]$2462 + attribute \src "libresoc.v:45284.5-45284.29" + switch \initial + attribute \src "libresoc.v:45284.9-45284.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_INT_ra_cr0_1$next[0:0]$2462 1'0 + case + assign $1\dp_INT_ra_cr0_1$next[0:0]$2462 \rp_INT_ra_cr0_1 + end + sync always + update \dp_INT_ra_cr0_1$next $0\dp_INT_ra_cr0_1$next[0:0]$2461 + end + attribute \src "libresoc.v:45292.3-45301.6" + process $proc$libresoc.v:45292$2463 + assign { } { } + assign { } { } + assign $0\fus_src1_i$42[63:0]$2464 $1\fus_src1_i$42[63:0]$2465 + attribute \src "libresoc.v:45293.5-45293.29" + switch \initial + attribute \src "libresoc.v:45293.9-45293.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:294" + switch \dp_INT_ra_cr0_1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src1_i$42[63:0]$2465 \int_src1__data_o + case + assign $1\fus_src1_i$42[63:0]$2465 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fus_src1_i$42 $0\fus_src1_i$42[63:0]$2464 + end + attribute \src "libresoc.v:45302.3-45310.6" + process $proc$libresoc.v:45302$2466 + assign { } { } + assign { } { } + assign $0\dp_INT_ra_trap0_2$next[0:0]$2467 $1\dp_INT_ra_trap0_2$next[0:0]$2468 + attribute \src "libresoc.v:45303.5-45303.29" + switch \initial + attribute \src "libresoc.v:45303.9-45303.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_INT_ra_trap0_2$next[0:0]$2468 1'0 + case + assign $1\dp_INT_ra_trap0_2$next[0:0]$2468 \rp_INT_ra_trap0_2 + end + sync always + update \dp_INT_ra_trap0_2$next $0\dp_INT_ra_trap0_2$next[0:0]$2467 + end + attribute \src "libresoc.v:45311.3-45320.6" + process $proc$libresoc.v:45311$2469 + assign { } { } + assign { } { } + assign $0\fus_src1_i$45[63:0]$2470 $1\fus_src1_i$45[63:0]$2471 + attribute \src "libresoc.v:45312.5-45312.29" + switch \initial + attribute \src "libresoc.v:45312.9-45312.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:294" + switch \dp_INT_ra_trap0_2 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src1_i$45[63:0]$2471 \int_src1__data_o + case + assign $1\fus_src1_i$45[63:0]$2471 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fus_src1_i$45 $0\fus_src1_i$45[63:0]$2470 + end + attribute \src "libresoc.v:45321.3-45329.6" + process $proc$libresoc.v:45321$2472 + assign { } { } + assign { } { } + assign $0\dp_INT_ra_logical0_3$next[0:0]$2473 $1\dp_INT_ra_logical0_3$next[0:0]$2474 + attribute \src "libresoc.v:45322.5-45322.29" + switch \initial + attribute \src "libresoc.v:45322.9-45322.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_INT_ra_logical0_3$next[0:0]$2474 1'0 + case + assign $1\dp_INT_ra_logical0_3$next[0:0]$2474 \rp_INT_ra_logical0_3 + end + sync always + update \dp_INT_ra_logical0_3$next $0\dp_INT_ra_logical0_3$next[0:0]$2473 + end + attribute \src "libresoc.v:45330.3-45339.6" + process $proc$libresoc.v:45330$2475 + assign { } { } + assign { } { } + assign $0\fus_src1_i$48[63:0]$2476 $1\fus_src1_i$48[63:0]$2477 + attribute \src "libresoc.v:45331.5-45331.29" + switch \initial + attribute \src "libresoc.v:45331.9-45331.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:294" + switch \dp_INT_ra_logical0_3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src1_i$48[63:0]$2477 \int_src1__data_o + case + assign $1\fus_src1_i$48[63:0]$2477 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fus_src1_i$48 $0\fus_src1_i$48[63:0]$2476 + end + attribute \src "libresoc.v:45340.3-45348.6" + process $proc$libresoc.v:45340$2478 + assign { } { } + assign { } { } + assign $0\dp_INT_ra_spr0_4$next[0:0]$2479 $1\dp_INT_ra_spr0_4$next[0:0]$2480 + attribute \src "libresoc.v:45341.5-45341.29" + switch \initial + attribute \src "libresoc.v:45341.9-45341.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_INT_ra_spr0_4$next[0:0]$2480 1'0 + case + assign $1\dp_INT_ra_spr0_4$next[0:0]$2480 \rp_INT_ra_spr0_4 + end + sync always + update \dp_INT_ra_spr0_4$next $0\dp_INT_ra_spr0_4$next[0:0]$2479 + end + attribute \src "libresoc.v:45349.3-45358.6" + process $proc$libresoc.v:45349$2481 + assign { } { } + assign { } { } + assign $0\fus_src1_i$51[63:0]$2482 $1\fus_src1_i$51[63:0]$2483 + attribute \src "libresoc.v:45350.5-45350.29" + switch \initial + attribute \src "libresoc.v:45350.9-45350.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:294" + switch \dp_INT_ra_spr0_4 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src1_i$51[63:0]$2483 \int_src1__data_o + case + assign $1\fus_src1_i$51[63:0]$2483 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fus_src1_i$51 $0\fus_src1_i$51[63:0]$2482 + end + attribute \src "libresoc.v:45359.3-45367.6" + process $proc$libresoc.v:45359$2484 + assign { } { } + assign { } { } + assign $0\dp_INT_ra_div0_5$next[0:0]$2485 $1\dp_INT_ra_div0_5$next[0:0]$2486 + attribute \src "libresoc.v:45360.5-45360.29" + switch \initial + attribute \src "libresoc.v:45360.9-45360.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_INT_ra_div0_5$next[0:0]$2486 1'0 + case + assign $1\dp_INT_ra_div0_5$next[0:0]$2486 \rp_INT_ra_div0_5 + end + sync always + update \dp_INT_ra_div0_5$next $0\dp_INT_ra_div0_5$next[0:0]$2485 + end + attribute \src "libresoc.v:45368.3-45377.6" + process $proc$libresoc.v:45368$2487 + assign { } { } + assign { } { } + assign $0\fus_src1_i$54[63:0]$2488 $1\fus_src1_i$54[63:0]$2489 + attribute \src "libresoc.v:45369.5-45369.29" + switch \initial + attribute \src "libresoc.v:45369.9-45369.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:294" + switch \dp_INT_ra_div0_5 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src1_i$54[63:0]$2489 \int_src1__data_o + case + assign $1\fus_src1_i$54[63:0]$2489 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fus_src1_i$54 $0\fus_src1_i$54[63:0]$2488 + end + attribute \src "libresoc.v:45378.3-45386.6" + process $proc$libresoc.v:45378$2490 + assign { } { } + assign { } { } + assign $0\dp_INT_ra_mul0_6$next[0:0]$2491 $1\dp_INT_ra_mul0_6$next[0:0]$2492 + attribute \src "libresoc.v:45379.5-45379.29" + switch \initial + attribute \src "libresoc.v:45379.9-45379.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_INT_ra_mul0_6$next[0:0]$2492 1'0 + case + assign $1\dp_INT_ra_mul0_6$next[0:0]$2492 \rp_INT_ra_mul0_6 + end + sync always + update \dp_INT_ra_mul0_6$next $0\dp_INT_ra_mul0_6$next[0:0]$2491 + end + attribute \src "libresoc.v:45387.3-45396.6" + process $proc$libresoc.v:45387$2493 + assign { } { } + assign { } { } + assign $0\fus_src1_i$57[63:0]$2494 $1\fus_src1_i$57[63:0]$2495 + attribute \src "libresoc.v:45388.5-45388.29" + switch \initial + attribute \src "libresoc.v:45388.9-45388.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:294" + switch \dp_INT_ra_mul0_6 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src1_i$57[63:0]$2495 \int_src1__data_o + case + assign $1\fus_src1_i$57[63:0]$2495 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fus_src1_i$57 $0\fus_src1_i$57[63:0]$2494 + end + attribute \src "libresoc.v:45397.3-45405.6" + process $proc$libresoc.v:45397$2496 + assign { } { } + assign { } { } + assign $0\dp_INT_ra_shiftrot0_7$next[0:0]$2497 $1\dp_INT_ra_shiftrot0_7$next[0:0]$2498 + attribute \src "libresoc.v:45398.5-45398.29" + switch \initial + attribute \src "libresoc.v:45398.9-45398.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_INT_ra_shiftrot0_7$next[0:0]$2498 1'0 + case + assign $1\dp_INT_ra_shiftrot0_7$next[0:0]$2498 \rp_INT_ra_shiftrot0_7 + end + sync always + update \dp_INT_ra_shiftrot0_7$next $0\dp_INT_ra_shiftrot0_7$next[0:0]$2497 + end + attribute \src "libresoc.v:45406.3-45415.6" + process $proc$libresoc.v:45406$2499 + assign { } { } + assign { } { } + assign $0\fus_src1_i$60[63:0]$2500 $1\fus_src1_i$60[63:0]$2501 + attribute \src "libresoc.v:45407.5-45407.29" + switch \initial + attribute \src "libresoc.v:45407.9-45407.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:294" + switch \dp_INT_ra_shiftrot0_7 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src1_i$60[63:0]$2501 \int_src1__data_o + case + assign $1\fus_src1_i$60[63:0]$2501 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fus_src1_i$60 $0\fus_src1_i$60[63:0]$2500 + end + attribute \src "libresoc.v:45416.3-45424.6" + process $proc$libresoc.v:45416$2502 + assign { } { } + assign { } { } + assign $0\dp_INT_ra_ldst0_8$next[0:0]$2503 $1\dp_INT_ra_ldst0_8$next[0:0]$2504 + attribute \src "libresoc.v:45417.5-45417.29" + switch \initial + attribute \src "libresoc.v:45417.9-45417.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_INT_ra_ldst0_8$next[0:0]$2504 1'0 + case + assign $1\dp_INT_ra_ldst0_8$next[0:0]$2504 \rp_INT_ra_ldst0_8 + end + sync always + update \dp_INT_ra_ldst0_8$next $0\dp_INT_ra_ldst0_8$next[0:0]$2503 + end + attribute \src "libresoc.v:45425.3-45434.6" + process $proc$libresoc.v:45425$2505 + assign { } { } + assign { } { } + assign $0\fus_src1_i$63[63:0]$2506 $1\fus_src1_i$63[63:0]$2507 + attribute \src "libresoc.v:45426.5-45426.29" + switch \initial + attribute \src "libresoc.v:45426.9-45426.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:294" + switch \dp_INT_ra_ldst0_8 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src1_i$63[63:0]$2507 \int_src1__data_o + case + assign $1\fus_src1_i$63[63:0]$2507 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fus_src1_i$63 $0\fus_src1_i$63[63:0]$2506 + end + attribute \src "libresoc.v:45435.3-45443.6" + process $proc$libresoc.v:45435$2508 + assign { } { } + assign { } { } + assign $0\dp_INT_rb_alu0_0$next[0:0]$2509 $1\dp_INT_rb_alu0_0$next[0:0]$2510 + attribute \src "libresoc.v:45436.5-45436.29" + switch \initial + attribute \src "libresoc.v:45436.9-45436.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_INT_rb_alu0_0$next[0:0]$2510 1'0 + case + assign $1\dp_INT_rb_alu0_0$next[0:0]$2510 \rp_INT_rb_alu0_0 + end + sync always + update \dp_INT_rb_alu0_0$next $0\dp_INT_rb_alu0_0$next[0:0]$2509 + end + attribute \src "libresoc.v:45444.3-45453.6" + process $proc$libresoc.v:45444$2511 + assign { } { } + assign { } { } + assign $0\fus_src2_i[63:0] $1\fus_src2_i[63:0] + attribute \src "libresoc.v:45445.5-45445.29" + switch \initial + attribute \src "libresoc.v:45445.9-45445.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:294" + switch \dp_INT_rb_alu0_0 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src2_i[63:0] \int_src2__data_o + case + assign $1\fus_src2_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fus_src2_i $0\fus_src2_i[63:0] + end + attribute \src "libresoc.v:45454.3-45462.6" + process $proc$libresoc.v:45454$2512 + assign { } { } + assign { } { } + assign $0\dp_INT_rb_cr0_1$next[0:0]$2513 $1\dp_INT_rb_cr0_1$next[0:0]$2514 + attribute \src "libresoc.v:45455.5-45455.29" + switch \initial + attribute \src "libresoc.v:45455.9-45455.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_INT_rb_cr0_1$next[0:0]$2514 1'0 + case + assign $1\dp_INT_rb_cr0_1$next[0:0]$2514 \rp_INT_rb_cr0_1 + end + sync always + update \dp_INT_rb_cr0_1$next $0\dp_INT_rb_cr0_1$next[0:0]$2513 + end + attribute \src "libresoc.v:45463.3-45472.6" + process $proc$libresoc.v:45463$2515 + assign { } { } + assign { } { } + assign $0\fus_src2_i$64[63:0]$2516 $1\fus_src2_i$64[63:0]$2517 + attribute \src "libresoc.v:45464.5-45464.29" + switch \initial + attribute \src "libresoc.v:45464.9-45464.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:294" + switch \dp_INT_rb_cr0_1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src2_i$64[63:0]$2517 \int_src2__data_o + case + assign $1\fus_src2_i$64[63:0]$2517 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fus_src2_i$64 $0\fus_src2_i$64[63:0]$2516 + end + attribute \src "libresoc.v:45473.3-45481.6" + process $proc$libresoc.v:45473$2518 + assign { } { } + assign { } { } + assign $0\dp_INT_rb_trap0_2$next[0:0]$2519 $1\dp_INT_rb_trap0_2$next[0:0]$2520 + attribute \src "libresoc.v:45474.5-45474.29" + switch \initial + attribute \src "libresoc.v:45474.9-45474.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_INT_rb_trap0_2$next[0:0]$2520 1'0 + case + assign $1\dp_INT_rb_trap0_2$next[0:0]$2520 \rp_INT_rb_trap0_2 + end + sync always + update \dp_INT_rb_trap0_2$next $0\dp_INT_rb_trap0_2$next[0:0]$2519 + end + attribute \src "libresoc.v:45482.3-45491.6" + process $proc$libresoc.v:45482$2521 + assign { } { } + assign { } { } + assign $0\fus_src2_i$65[63:0]$2522 $1\fus_src2_i$65[63:0]$2523 + attribute \src "libresoc.v:45483.5-45483.29" + switch \initial + attribute \src "libresoc.v:45483.9-45483.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:294" + switch \dp_INT_rb_trap0_2 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src2_i$65[63:0]$2523 \int_src2__data_o + case + assign $1\fus_src2_i$65[63:0]$2523 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fus_src2_i$65 $0\fus_src2_i$65[63:0]$2522 + end + attribute \src "libresoc.v:45492.3-45500.6" + process $proc$libresoc.v:45492$2524 + assign { } { } + assign { } { } + assign $0\dp_INT_rb_logical0_3$next[0:0]$2525 $1\dp_INT_rb_logical0_3$next[0:0]$2526 + attribute \src "libresoc.v:45493.5-45493.29" + switch \initial + attribute \src "libresoc.v:45493.9-45493.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_INT_rb_logical0_3$next[0:0]$2526 1'0 + case + assign $1\dp_INT_rb_logical0_3$next[0:0]$2526 \rp_INT_rb_logical0_3 + end + sync always + update \dp_INT_rb_logical0_3$next $0\dp_INT_rb_logical0_3$next[0:0]$2525 + end + attribute \src "libresoc.v:45501.3-45510.6" + process $proc$libresoc.v:45501$2527 + assign { } { } + assign { } { } + assign $0\fus_src2_i$66[63:0]$2528 $1\fus_src2_i$66[63:0]$2529 + attribute \src "libresoc.v:45502.5-45502.29" + switch \initial + attribute \src "libresoc.v:45502.9-45502.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:294" + switch \dp_INT_rb_logical0_3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src2_i$66[63:0]$2529 \int_src2__data_o + case + assign $1\fus_src2_i$66[63:0]$2529 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fus_src2_i$66 $0\fus_src2_i$66[63:0]$2528 + end + attribute \src "libresoc.v:45511.3-45519.6" + process $proc$libresoc.v:45511$2530 + assign { } { } + assign { } { } + assign $0\dp_INT_rb_div0_4$next[0:0]$2531 $1\dp_INT_rb_div0_4$next[0:0]$2532 + attribute \src "libresoc.v:45512.5-45512.29" + switch \initial + attribute \src "libresoc.v:45512.9-45512.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_INT_rb_div0_4$next[0:0]$2532 1'0 + case + assign $1\dp_INT_rb_div0_4$next[0:0]$2532 \rp_INT_rb_div0_4 + end + sync always + update \dp_INT_rb_div0_4$next $0\dp_INT_rb_div0_4$next[0:0]$2531 + end + attribute \src "libresoc.v:45520.3-45529.6" + process $proc$libresoc.v:45520$2533 + assign { } { } + assign { } { } + assign $0\fus_src2_i$67[63:0]$2534 $1\fus_src2_i$67[63:0]$2535 + attribute \src "libresoc.v:45521.5-45521.29" + switch \initial + attribute \src "libresoc.v:45521.9-45521.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:294" + switch \dp_INT_rb_div0_4 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src2_i$67[63:0]$2535 \int_src2__data_o + case + assign $1\fus_src2_i$67[63:0]$2535 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fus_src2_i$67 $0\fus_src2_i$67[63:0]$2534 + end + attribute \src "libresoc.v:45530.3-45538.6" + process $proc$libresoc.v:45530$2536 + assign { } { } + assign { } { } + assign $0\dp_INT_rb_mul0_5$next[0:0]$2537 $1\dp_INT_rb_mul0_5$next[0:0]$2538 + attribute \src "libresoc.v:45531.5-45531.29" + switch \initial + attribute \src "libresoc.v:45531.9-45531.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_INT_rb_mul0_5$next[0:0]$2538 1'0 + case + assign $1\dp_INT_rb_mul0_5$next[0:0]$2538 \rp_INT_rb_mul0_5 + end + sync always + update \dp_INT_rb_mul0_5$next $0\dp_INT_rb_mul0_5$next[0:0]$2537 + end + attribute \src "libresoc.v:45539.3-45548.6" + process $proc$libresoc.v:45539$2539 + assign { } { } + assign { } { } + assign $0\fus_src2_i$68[63:0]$2540 $1\fus_src2_i$68[63:0]$2541 + attribute \src "libresoc.v:45540.5-45540.29" + switch \initial + attribute \src "libresoc.v:45540.9-45540.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:294" + switch \dp_INT_rb_mul0_5 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src2_i$68[63:0]$2541 \int_src2__data_o + case + assign $1\fus_src2_i$68[63:0]$2541 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fus_src2_i$68 $0\fus_src2_i$68[63:0]$2540 + end + attribute \src "libresoc.v:45549.3-45557.6" + process $proc$libresoc.v:45549$2542 + assign { } { } + assign { } { } + assign $0\dp_INT_rb_shiftrot0_6$next[0:0]$2543 $1\dp_INT_rb_shiftrot0_6$next[0:0]$2544 + attribute \src "libresoc.v:45550.5-45550.29" + switch \initial + attribute \src "libresoc.v:45550.9-45550.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_INT_rb_shiftrot0_6$next[0:0]$2544 1'0 + case + assign $1\dp_INT_rb_shiftrot0_6$next[0:0]$2544 \rp_INT_rb_shiftrot0_6 + end + sync always + update \dp_INT_rb_shiftrot0_6$next $0\dp_INT_rb_shiftrot0_6$next[0:0]$2543 + end + attribute \src "libresoc.v:45558.3-45567.6" + process $proc$libresoc.v:45558$2545 + assign { } { } + assign { } { } + assign $0\fus_src2_i$69[63:0]$2546 $1\fus_src2_i$69[63:0]$2547 + attribute \src "libresoc.v:45559.5-45559.29" + switch \initial + attribute \src "libresoc.v:45559.9-45559.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:294" + switch \dp_INT_rb_shiftrot0_6 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src2_i$69[63:0]$2547 \int_src2__data_o + case + assign $1\fus_src2_i$69[63:0]$2547 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fus_src2_i$69 $0\fus_src2_i$69[63:0]$2546 + end + attribute \src "libresoc.v:45568.3-45576.6" + process $proc$libresoc.v:45568$2548 + assign { } { } + assign { } { } + assign $0\dp_INT_rb_ldst0_7$next[0:0]$2549 $1\dp_INT_rb_ldst0_7$next[0:0]$2550 + attribute \src "libresoc.v:45569.5-45569.29" + switch \initial + attribute \src "libresoc.v:45569.9-45569.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_INT_rb_ldst0_7$next[0:0]$2550 1'0 + case + assign $1\dp_INT_rb_ldst0_7$next[0:0]$2550 \rp_INT_rb_ldst0_7 + end + sync always + update \dp_INT_rb_ldst0_7$next $0\dp_INT_rb_ldst0_7$next[0:0]$2549 + end + attribute \src "libresoc.v:45577.3-45586.6" + process $proc$libresoc.v:45577$2551 + assign { } { } + assign { } { } + assign $0\fus_src2_i$70[63:0]$2552 $1\fus_src2_i$70[63:0]$2553 + attribute \src "libresoc.v:45578.5-45578.29" + switch \initial + attribute \src "libresoc.v:45578.9-45578.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:294" + switch \dp_INT_rb_ldst0_7 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src2_i$70[63:0]$2553 \int_src2__data_o + case + assign $1\fus_src2_i$70[63:0]$2553 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fus_src2_i$70 $0\fus_src2_i$70[63:0]$2552 + end + attribute \src "libresoc.v:45587.3-45595.6" + process $proc$libresoc.v:45587$2554 + assign { } { } + assign { } { } + assign $0\dp_INT_rc_shiftrot0_0$next[0:0]$2555 $1\dp_INT_rc_shiftrot0_0$next[0:0]$2556 + attribute \src "libresoc.v:45588.5-45588.29" + switch \initial + attribute \src "libresoc.v:45588.9-45588.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_INT_rc_shiftrot0_0$next[0:0]$2556 1'0 + case + assign $1\dp_INT_rc_shiftrot0_0$next[0:0]$2556 \rp_INT_rc_shiftrot0_0 + end + sync always + update \dp_INT_rc_shiftrot0_0$next $0\dp_INT_rc_shiftrot0_0$next[0:0]$2555 + end + attribute \src "libresoc.v:45596.3-45605.6" + process $proc$libresoc.v:45596$2557 + assign { } { } + assign { } { } + assign $0\fus_src3_i[63:0] $1\fus_src3_i[63:0] + attribute \src "libresoc.v:45597.5-45597.29" + switch \initial + attribute \src "libresoc.v:45597.9-45597.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:294" + switch \dp_INT_rc_shiftrot0_0 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src3_i[63:0] \int_src3__data_o + case + assign $1\fus_src3_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fus_src3_i $0\fus_src3_i[63:0] + end + attribute \src "libresoc.v:45606.3-45614.6" + process $proc$libresoc.v:45606$2558 + assign { } { } + assign { } { } + assign $0\dp_INT_rc_ldst0_1$next[0:0]$2559 $1\dp_INT_rc_ldst0_1$next[0:0]$2560 + attribute \src "libresoc.v:45607.5-45607.29" + switch \initial + attribute \src "libresoc.v:45607.9-45607.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_INT_rc_ldst0_1$next[0:0]$2560 1'0 + case + assign $1\dp_INT_rc_ldst0_1$next[0:0]$2560 \rp_INT_rc_ldst0_1 + end + sync always + update \dp_INT_rc_ldst0_1$next $0\dp_INT_rc_ldst0_1$next[0:0]$2559 + end + attribute \src "libresoc.v:45615.3-45624.6" + process $proc$libresoc.v:45615$2561 + assign { } { } + assign { } { } + assign $0\fus_src3_i$71[63:0]$2562 $1\fus_src3_i$71[63:0]$2563 + attribute \src "libresoc.v:45616.5-45616.29" + switch \initial + attribute \src "libresoc.v:45616.9-45616.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:294" + switch \dp_INT_rc_ldst0_1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src3_i$71[63:0]$2563 \int_src3__data_o + case + assign $1\fus_src3_i$71[63:0]$2563 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fus_src3_i$71 $0\fus_src3_i$71[63:0]$2562 + end + attribute \src "libresoc.v:45625.3-45651.6" + process $proc$libresoc.v:45625$2564 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\counter$next[1:0]$2565 $4\counter$next[1:0]$2569 + attribute \src "libresoc.v:45626.5-45626.29" + switch \initial + attribute \src "libresoc.v:45626.9-45626.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:183" + switch \$216 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\counter$next[1:0]$2566 \$218 [1:0] + case + assign $1\counter$next[1:0]$2566 \counter + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\counter$next[1:0]$2567 $3\counter$next[1:0]$2568 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign { } { } + assign $3\counter$next[1:0]$2568 2'10 + case + assign $3\counter$next[1:0]$2568 $1\counter$next[1:0]$2566 + end + case + assign $2\counter$next[1:0]$2567 $1\counter$next[1:0]$2566 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\counter$next[1:0]$2569 2'00 + case + assign $4\counter$next[1:0]$2569 $2\counter$next[1:0]$2567 + end + sync always + update \counter$next $0\counter$next[1:0]$2565 + end + attribute \src "libresoc.v:45652.3-45660.6" + process $proc$libresoc.v:45652$2570 + assign { } { } + assign { } { } + assign $0\dp_XER_xer_so_alu0_0$next[0:0]$2571 $1\dp_XER_xer_so_alu0_0$next[0:0]$2572 + attribute \src "libresoc.v:45653.5-45653.29" + switch \initial + attribute \src "libresoc.v:45653.9-45653.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_XER_xer_so_alu0_0$next[0:0]$2572 1'0 + case + assign $1\dp_XER_xer_so_alu0_0$next[0:0]$2572 \rp_XER_xer_so_alu0_0 + end + sync always + update \dp_XER_xer_so_alu0_0$next $0\dp_XER_xer_so_alu0_0$next[0:0]$2571 + end + attribute \src "libresoc.v:45661.3-45670.6" + process $proc$libresoc.v:45661$2573 + assign { } { } + assign { } { } + assign $0\fus_src3_i$72[0:0]$2574 $1\fus_src3_i$72[0:0]$2575 + attribute \src "libresoc.v:45662.5-45662.29" + switch \initial + attribute \src "libresoc.v:45662.9-45662.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:294" + switch \dp_XER_xer_so_alu0_0 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src3_i$72[0:0]$2575 \xer_src1__data_o [0] + case + assign $1\fus_src3_i$72[0:0]$2575 1'0 + end + sync always + update \fus_src3_i$72 $0\fus_src3_i$72[0:0]$2574 + end + attribute \src "libresoc.v:45671.3-45761.6" + process $proc$libresoc.v:45671$2576 + assign { } { } + assign { } { } + assign { } { } + assign $0\corebusy_o[0:0] $2\corebusy_o[0:0] + attribute \src "libresoc.v:45672.5-45672.29" + switch \initial + attribute \src "libresoc.v:45672.9-45672.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:183" + switch \$221 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\corebusy_o[0:0] 1'1 + case + assign $1\corebusy_o[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\corebusy_o[0:0] $3\corebusy_o[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $3\corebusy_o[0:0] $1\corebusy_o[0:0] + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign { } { } + assign $3\corebusy_o[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $3\corebusy_o[0:0] $13\corebusy_o[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + switch \fu_enable [0] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\corebusy_o[0:0] \fus_cu_busy_o + case + assign $4\corebusy_o[0:0] $1\corebusy_o[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + switch \fu_enable [1] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\corebusy_o[0:0] \fus_cu_busy_o$14 + case + assign $5\corebusy_o[0:0] $4\corebusy_o[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + switch \fu_enable [2] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\corebusy_o[0:0] \fus_cu_busy_o$17 + case + assign $6\corebusy_o[0:0] $5\corebusy_o[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + switch \fu_enable [3] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\corebusy_o[0:0] \fus_cu_busy_o$20 + case + assign $7\corebusy_o[0:0] $6\corebusy_o[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + switch \fu_enable [4] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $8\corebusy_o[0:0] \fus_cu_busy_o$23 + case + assign $8\corebusy_o[0:0] $7\corebusy_o[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + switch \fu_enable [5] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $9\corebusy_o[0:0] \fus_cu_busy_o$26 + case + assign $9\corebusy_o[0:0] $8\corebusy_o[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + switch \fu_enable [6] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $10\corebusy_o[0:0] \fus_cu_busy_o$29 + case + assign $10\corebusy_o[0:0] $9\corebusy_o[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + switch \fu_enable [7] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $11\corebusy_o[0:0] \fus_cu_busy_o$32 + case + assign $11\corebusy_o[0:0] $10\corebusy_o[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + switch \fu_enable [8] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $12\corebusy_o[0:0] \fus_cu_busy_o$35 + case + assign $12\corebusy_o[0:0] $11\corebusy_o[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + switch \fu_enable [9] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $13\corebusy_o[0:0] \fus_cu_busy_o$38 + case + assign $13\corebusy_o[0:0] $12\corebusy_o[0:0] + end + end + case + assign $2\corebusy_o[0:0] $1\corebusy_o[0:0] + end + sync always + update \corebusy_o $0\corebusy_o[0:0] + end + attribute \src "libresoc.v:45762.3-45770.6" + process $proc$libresoc.v:45762$2577 + assign { } { } + assign { } { } + assign $0\dp_XER_xer_so_logical0_1$next[0:0]$2578 $1\dp_XER_xer_so_logical0_1$next[0:0]$2579 + attribute \src "libresoc.v:45763.5-45763.29" + switch \initial + attribute \src "libresoc.v:45763.9-45763.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_XER_xer_so_logical0_1$next[0:0]$2579 1'0 + case + assign $1\dp_XER_xer_so_logical0_1$next[0:0]$2579 \rp_XER_xer_so_logical0_1 + end + sync always + update \dp_XER_xer_so_logical0_1$next $0\dp_XER_xer_so_logical0_1$next[0:0]$2578 + end + attribute \src "libresoc.v:45771.3-45780.6" + process $proc$libresoc.v:45771$2580 + assign { } { } + assign { } { } + assign $0\fus_src3_i$73[0:0]$2581 $1\fus_src3_i$73[0:0]$2582 + attribute \src "libresoc.v:45772.5-45772.29" + switch \initial + attribute \src "libresoc.v:45772.9-45772.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:294" + switch \dp_XER_xer_so_logical0_1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src3_i$73[0:0]$2582 \xer_src1__data_o [0] + case + assign $1\fus_src3_i$73[0:0]$2582 1'0 + end + sync always + update \fus_src3_i$73 $0\fus_src3_i$73[0:0]$2581 + end + attribute \src "libresoc.v:45781.3-45789.6" + process $proc$libresoc.v:45781$2583 + assign { } { } + assign { } { } + assign $0\dp_XER_xer_so_spr0_2$next[0:0]$2584 $1\dp_XER_xer_so_spr0_2$next[0:0]$2585 + attribute \src "libresoc.v:45782.5-45782.29" + switch \initial + attribute \src "libresoc.v:45782.9-45782.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_XER_xer_so_spr0_2$next[0:0]$2585 1'0 + case + assign $1\dp_XER_xer_so_spr0_2$next[0:0]$2585 \rp_XER_xer_so_spr0_2 + end + sync always + update \dp_XER_xer_so_spr0_2$next $0\dp_XER_xer_so_spr0_2$next[0:0]$2584 + end + attribute \src "libresoc.v:45790.3-45799.6" + process $proc$libresoc.v:45790$2586 + assign { } { } + assign { } { } + assign $0\fus_src4_i[0:0] $1\fus_src4_i[0:0] + attribute \src "libresoc.v:45791.5-45791.29" + switch \initial + attribute \src "libresoc.v:45791.9-45791.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:294" + switch \dp_XER_xer_so_spr0_2 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src4_i[0:0] \xer_src1__data_o [0] + case + assign $1\fus_src4_i[0:0] 1'0 + end + sync always + update \fus_src4_i $0\fus_src4_i[0:0] + end + attribute \src "libresoc.v:45800.3-45820.6" + process $proc$libresoc.v:45800$2587 + assign { } { } + assign { } { } + assign { } { } + assign $0\core_terminate_o$next[0:0]$2588 $3\core_terminate_o$next[0:0]$2591 + attribute \src "libresoc.v:45801.5-45801.29" + switch \initial + attribute \src "libresoc.v:45801.9-45801.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\core_terminate_o$next[0:0]$2589 $2\core_terminate_o$next[0:0]$2590 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign { } { } + assign $2\core_terminate_o$next[0:0]$2590 1'1 + case + assign $2\core_terminate_o$next[0:0]$2590 \core_terminate_o + end + case + assign $1\core_terminate_o$next[0:0]$2589 \core_terminate_o + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\core_terminate_o$next[0:0]$2591 1'0 + case + assign $3\core_terminate_o$next[0:0]$2591 $1\core_terminate_o$next[0:0]$2589 + end + sync always + update \core_terminate_o$next $0\core_terminate_o$next[0:0]$2588 + end + attribute \src "libresoc.v:45821.3-45829.6" + process $proc$libresoc.v:45821$2592 + assign { } { } + assign { } { } + assign $0\dp_XER_xer_so_div0_3$next[0:0]$2593 $1\dp_XER_xer_so_div0_3$next[0:0]$2594 + attribute \src "libresoc.v:45822.5-45822.29" + switch \initial + attribute \src "libresoc.v:45822.9-45822.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_XER_xer_so_div0_3$next[0:0]$2594 1'0 + case + assign $1\dp_XER_xer_so_div0_3$next[0:0]$2594 \rp_XER_xer_so_div0_3 + end + sync always + update \dp_XER_xer_so_div0_3$next $0\dp_XER_xer_so_div0_3$next[0:0]$2593 + end + attribute \src "libresoc.v:45830.3-45839.6" + process $proc$libresoc.v:45830$2595 + assign { } { } + assign { } { } + assign $0\fus_src3_i$74[0:0]$2596 $1\fus_src3_i$74[0:0]$2597 + attribute \src "libresoc.v:45831.5-45831.29" + switch \initial + attribute \src "libresoc.v:45831.9-45831.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:294" + switch \dp_XER_xer_so_div0_3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src3_i$74[0:0]$2597 \xer_src1__data_o [0] + case + assign $1\fus_src3_i$74[0:0]$2597 1'0 + end + sync always + update \fus_src3_i$74 $0\fus_src3_i$74[0:0]$2596 + end + attribute \src "libresoc.v:45840.3-45848.6" + process $proc$libresoc.v:45840$2598 + assign { } { } + assign { } { } + assign $0\dp_XER_xer_so_mul0_4$next[0:0]$2599 $1\dp_XER_xer_so_mul0_4$next[0:0]$2600 + attribute \src "libresoc.v:45841.5-45841.29" + switch \initial + attribute \src "libresoc.v:45841.9-45841.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_XER_xer_so_mul0_4$next[0:0]$2600 1'0 + case + assign $1\dp_XER_xer_so_mul0_4$next[0:0]$2600 \rp_XER_xer_so_mul0_4 + end + sync always + update \dp_XER_xer_so_mul0_4$next $0\dp_XER_xer_so_mul0_4$next[0:0]$2599 + end + attribute \src "libresoc.v:45849.3-45858.6" + process $proc$libresoc.v:45849$2601 + assign { } { } + assign { } { } + assign $0\fus_src3_i$75[0:0]$2602 $1\fus_src3_i$75[0:0]$2603 + attribute \src "libresoc.v:45850.5-45850.29" + switch \initial + attribute \src "libresoc.v:45850.9-45850.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:294" + switch \dp_XER_xer_so_mul0_4 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src3_i$75[0:0]$2603 \xer_src1__data_o [0] + case + assign $1\fus_src3_i$75[0:0]$2603 1'0 + end + sync always + update \fus_src3_i$75 $0\fus_src3_i$75[0:0]$2602 + end + attribute \src "libresoc.v:45859.3-45887.6" + process $proc$libresoc.v:45859$2604 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_alu0__insn_type[6:0] $1\fus_oper_i_alu_alu0__insn_type[6:0] + attribute \src "libresoc.v:45860.5-45860.29" + switch \initial + attribute \src "libresoc.v:45860.9-45860.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_alu0__insn_type[6:0] $2\fus_oper_i_alu_alu0__insn_type[6:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_alu0__insn_type[6:0] 7'0000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_alu0__insn_type[6:0] 7'0000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_alu0__insn_type[6:0] $3\fus_oper_i_alu_alu0__insn_type[6:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + switch \fu_enable [0] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_alu0__insn_type[6:0] \dec_ALU_ALU__insn_type + case + assign $3\fus_oper_i_alu_alu0__insn_type[6:0] 7'0000000 + end + end + case + assign $1\fus_oper_i_alu_alu0__insn_type[6:0] 7'0000000 + end + sync always + update \fus_oper_i_alu_alu0__insn_type $0\fus_oper_i_alu_alu0__insn_type[6:0] + end + attribute \src "libresoc.v:45888.3-45896.6" + process $proc$libresoc.v:45888$2605 + assign { } { } + assign { } { } + assign $0\dp_XER_xer_so_shiftrot0_5$next[0:0]$2606 $1\dp_XER_xer_so_shiftrot0_5$next[0:0]$2607 + attribute \src "libresoc.v:45889.5-45889.29" + switch \initial + attribute \src "libresoc.v:45889.9-45889.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_XER_xer_so_shiftrot0_5$next[0:0]$2607 1'0 + case + assign $1\dp_XER_xer_so_shiftrot0_5$next[0:0]$2607 \rp_XER_xer_so_shiftrot0_5 + end + sync always + update \dp_XER_xer_so_shiftrot0_5$next $0\dp_XER_xer_so_shiftrot0_5$next[0:0]$2606 + end + attribute \src "libresoc.v:45897.3-45906.6" + process $proc$libresoc.v:45897$2608 + assign { } { } + assign { } { } + assign $0\fus_src4_i$76[0:0]$2609 $1\fus_src4_i$76[0:0]$2610 + attribute \src "libresoc.v:45898.5-45898.29" + switch \initial + attribute \src "libresoc.v:45898.9-45898.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:294" + switch \dp_XER_xer_so_shiftrot0_5 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src4_i$76[0:0]$2610 \xer_src1__data_o [0] + case + assign $1\fus_src4_i$76[0:0]$2610 1'0 + end + sync always + update \fus_src4_i$76 $0\fus_src4_i$76[0:0]$2609 + end + attribute \src "libresoc.v:45907.3-45915.6" + process $proc$libresoc.v:45907$2611 + assign { } { } + assign { } { } + assign $0\dp_XER_xer_ca_alu0_0$next[0:0]$2612 $1\dp_XER_xer_ca_alu0_0$next[0:0]$2613 + attribute \src "libresoc.v:45908.5-45908.29" + switch \initial + attribute \src "libresoc.v:45908.9-45908.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_XER_xer_ca_alu0_0$next[0:0]$2613 1'0 + case + assign $1\dp_XER_xer_ca_alu0_0$next[0:0]$2613 \rp_XER_xer_ca_alu0_0 + end + sync always + update \dp_XER_xer_ca_alu0_0$next $0\dp_XER_xer_ca_alu0_0$next[0:0]$2612 + end + attribute \src "libresoc.v:45916.3-45944.6" + process $proc$libresoc.v:45916$2614 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_alu0__fn_unit[12:0] $1\fus_oper_i_alu_alu0__fn_unit[12:0] + attribute \src "libresoc.v:45917.5-45917.29" + switch \initial + attribute \src "libresoc.v:45917.9-45917.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_alu0__fn_unit[12:0] $2\fus_oper_i_alu_alu0__fn_unit[12:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_alu0__fn_unit[12:0] 13'0000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_alu0__fn_unit[12:0] 13'0000000000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_alu0__fn_unit[12:0] $3\fus_oper_i_alu_alu0__fn_unit[12:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + switch \fu_enable [0] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_alu0__fn_unit[12:0] \dec_ALU_ALU__fn_unit + case + assign $3\fus_oper_i_alu_alu0__fn_unit[12:0] 13'0000000000000 + end + end + case + assign $1\fus_oper_i_alu_alu0__fn_unit[12:0] 13'0000000000000 + end + sync always + update \fus_oper_i_alu_alu0__fn_unit $0\fus_oper_i_alu_alu0__fn_unit[12:0] + end + attribute \src "libresoc.v:45945.3-45954.6" + process $proc$libresoc.v:45945$2615 + assign { } { } + assign { } { } + assign $0\fus_src4_i$77[1:0]$2616 $1\fus_src4_i$77[1:0]$2617 + attribute \src "libresoc.v:45946.5-45946.29" + switch \initial + attribute \src "libresoc.v:45946.9-45946.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:294" + switch \dp_XER_xer_ca_alu0_0 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src4_i$77[1:0]$2617 \xer_src2__data_o + case + assign $1\fus_src4_i$77[1:0]$2617 2'00 + end + sync always + update \fus_src4_i$77 $0\fus_src4_i$77[1:0]$2616 + end + attribute \src "libresoc.v:45955.3-45963.6" + process $proc$libresoc.v:45955$2618 + assign { } { } + assign { } { } + assign $0\dp_XER_xer_ca_spr0_1$next[0:0]$2619 $1\dp_XER_xer_ca_spr0_1$next[0:0]$2620 + attribute \src "libresoc.v:45956.5-45956.29" + switch \initial + attribute \src "libresoc.v:45956.9-45956.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_XER_xer_ca_spr0_1$next[0:0]$2620 1'0 + case + assign $1\dp_XER_xer_ca_spr0_1$next[0:0]$2620 \rp_XER_xer_ca_spr0_1 + end + sync always + update \dp_XER_xer_ca_spr0_1$next $0\dp_XER_xer_ca_spr0_1$next[0:0]$2619 + end + attribute \src "libresoc.v:45964.3-45973.6" + process $proc$libresoc.v:45964$2621 + assign { } { } + assign { } { } + assign $0\fus_src6_i[1:0] $1\fus_src6_i[1:0] + attribute \src "libresoc.v:45965.5-45965.29" + switch \initial + attribute \src "libresoc.v:45965.9-45965.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:294" + switch \dp_XER_xer_ca_spr0_1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src6_i[1:0] \xer_src2__data_o + case + assign $1\fus_src6_i[1:0] 2'00 + end + sync always + update \fus_src6_i $0\fus_src6_i[1:0] + end + attribute \src "libresoc.v:45974.3-45982.6" + process $proc$libresoc.v:45974$2622 + assign { } { } + assign { } { } + assign $0\dp_XER_xer_ca_shiftrot0_2$next[0:0]$2623 $1\dp_XER_xer_ca_shiftrot0_2$next[0:0]$2624 + attribute \src "libresoc.v:45975.5-45975.29" + switch \initial + attribute \src "libresoc.v:45975.9-45975.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_XER_xer_ca_shiftrot0_2$next[0:0]$2624 1'0 + case + assign $1\dp_XER_xer_ca_shiftrot0_2$next[0:0]$2624 \rp_XER_xer_ca_shiftrot0_2 + end + sync always + update \dp_XER_xer_ca_shiftrot0_2$next $0\dp_XER_xer_ca_shiftrot0_2$next[0:0]$2623 + end + attribute \src "libresoc.v:45983.3-46012.6" + process $proc$libresoc.v:45983$2625 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_alu0__imm_data__data[63:0] $1\fus_oper_i_alu_alu0__imm_data__data[63:0] + assign $0\fus_oper_i_alu_alu0__imm_data__ok[0:0] $1\fus_oper_i_alu_alu0__imm_data__ok[0:0] + attribute \src "libresoc.v:45984.5-45984.29" + switch \initial + attribute \src "libresoc.v:45984.9-45984.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $1\fus_oper_i_alu_alu0__imm_data__data[63:0] $2\fus_oper_i_alu_alu0__imm_data__data[63:0] + assign $1\fus_oper_i_alu_alu0__imm_data__ok[0:0] $2\fus_oper_i_alu_alu0__imm_data__ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_alu0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\fus_oper_i_alu_alu0__imm_data__ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_alu0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\fus_oper_i_alu_alu0__imm_data__ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign $2\fus_oper_i_alu_alu0__imm_data__data[63:0] $3\fus_oper_i_alu_alu0__imm_data__data[63:0] + assign $2\fus_oper_i_alu_alu0__imm_data__ok[0:0] $3\fus_oper_i_alu_alu0__imm_data__ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + switch \fu_enable [0] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $3\fus_oper_i_alu_alu0__imm_data__ok[0:0] $3\fus_oper_i_alu_alu0__imm_data__data[63:0] } { \dec_ALU_ALU__imm_data__ok \dec_ALU_ALU__imm_data__data } + case + assign $3\fus_oper_i_alu_alu0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\fus_oper_i_alu_alu0__imm_data__ok[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_alu0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fus_oper_i_alu_alu0__imm_data__ok[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_alu0__imm_data__data $0\fus_oper_i_alu_alu0__imm_data__data[63:0] + update \fus_oper_i_alu_alu0__imm_data__ok $0\fus_oper_i_alu_alu0__imm_data__ok[0:0] + end + attribute \src "libresoc.v:46013.3-46022.6" + process $proc$libresoc.v:46013$2626 + assign { } { } + assign { } { } + assign $0\fus_src5_i[1:0] $1\fus_src5_i[1:0] + attribute \src "libresoc.v:46014.5-46014.29" + switch \initial + attribute \src "libresoc.v:46014.9-46014.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:294" + switch \dp_XER_xer_ca_shiftrot0_2 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src5_i[1:0] \xer_src2__data_o + case + assign $1\fus_src5_i[1:0] 2'00 + end + sync always + update \fus_src5_i $0\fus_src5_i[1:0] + end + attribute \src "libresoc.v:46023.3-46031.6" + process $proc$libresoc.v:46023$2627 + assign { } { } + assign { } { } + assign $0\dp_XER_xer_ov_spr0_0$next[0:0]$2628 $1\dp_XER_xer_ov_spr0_0$next[0:0]$2629 + attribute \src "libresoc.v:46024.5-46024.29" + switch \initial + attribute \src "libresoc.v:46024.9-46024.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_XER_xer_ov_spr0_0$next[0:0]$2629 1'0 + case + assign $1\dp_XER_xer_ov_spr0_0$next[0:0]$2629 \rp_XER_xer_ov_spr0_0 + end + sync always + update \dp_XER_xer_ov_spr0_0$next $0\dp_XER_xer_ov_spr0_0$next[0:0]$2628 + end + attribute \src "libresoc.v:46032.3-46041.6" + process $proc$libresoc.v:46032$2630 + assign { } { } + assign { } { } + assign $0\fus_src5_i$78[1:0]$2631 $1\fus_src5_i$78[1:0]$2632 + attribute \src "libresoc.v:46033.5-46033.29" + switch \initial + attribute \src "libresoc.v:46033.9-46033.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:294" + switch \dp_XER_xer_ov_spr0_0 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src5_i$78[1:0]$2632 \xer_src3__data_o + case + assign $1\fus_src5_i$78[1:0]$2632 2'00 + end + sync always + update \fus_src5_i$78 $0\fus_src5_i$78[1:0]$2631 + end + attribute \src "libresoc.v:46042.3-46050.6" + process $proc$libresoc.v:46042$2633 + assign { } { } + assign { } { } + assign $0\dp_CR_full_cr_cr0_0$next[0:0]$2634 $1\dp_CR_full_cr_cr0_0$next[0:0]$2635 + attribute \src "libresoc.v:46043.5-46043.29" + switch \initial + attribute \src "libresoc.v:46043.9-46043.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_CR_full_cr_cr0_0$next[0:0]$2635 1'0 + case + assign $1\dp_CR_full_cr_cr0_0$next[0:0]$2635 \rp_CR_full_cr_cr0_0 + end + sync always + update \dp_CR_full_cr_cr0_0$next $0\dp_CR_full_cr_cr0_0$next[0:0]$2634 + end + attribute \src "libresoc.v:46051.3-46060.6" + process $proc$libresoc.v:46051$2636 + assign { } { } + assign { } { } + assign $0\fus_src3_i$79[31:0]$2637 $1\fus_src3_i$79[31:0]$2638 + attribute \src "libresoc.v:46052.5-46052.29" + switch \initial + attribute \src "libresoc.v:46052.9-46052.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:294" + switch \dp_CR_full_cr_cr0_0 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src3_i$79[31:0]$2638 \cr_full_rd__data_o + case + assign $1\fus_src3_i$79[31:0]$2638 0 + end + sync always + update \fus_src3_i$79 $0\fus_src3_i$79[31:0]$2637 + end + attribute \src "libresoc.v:46061.3-46090.6" + process $proc$libresoc.v:46061$2639 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_alu0__rc__ok[0:0] $1\fus_oper_i_alu_alu0__rc__ok[0:0] + assign $0\fus_oper_i_alu_alu0__rc__rc[0:0] $1\fus_oper_i_alu_alu0__rc__rc[0:0] + attribute \src "libresoc.v:46062.5-46062.29" + switch \initial + attribute \src "libresoc.v:46062.9-46062.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $1\fus_oper_i_alu_alu0__rc__ok[0:0] $2\fus_oper_i_alu_alu0__rc__ok[0:0] + assign $1\fus_oper_i_alu_alu0__rc__rc[0:0] $2\fus_oper_i_alu_alu0__rc__rc[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_alu0__rc__ok[0:0] 1'0 + assign $2\fus_oper_i_alu_alu0__rc__rc[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_alu0__rc__ok[0:0] 1'0 + assign $2\fus_oper_i_alu_alu0__rc__rc[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign $2\fus_oper_i_alu_alu0__rc__ok[0:0] $3\fus_oper_i_alu_alu0__rc__ok[0:0] + assign $2\fus_oper_i_alu_alu0__rc__rc[0:0] $3\fus_oper_i_alu_alu0__rc__rc[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + switch \fu_enable [0] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $3\fus_oper_i_alu_alu0__rc__ok[0:0] $3\fus_oper_i_alu_alu0__rc__rc[0:0] } { \dec_ALU_ALU__rc__ok \dec_ALU_ALU__rc__rc } + case + assign $3\fus_oper_i_alu_alu0__rc__ok[0:0] 1'0 + assign $3\fus_oper_i_alu_alu0__rc__rc[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_alu0__rc__ok[0:0] 1'0 + assign $1\fus_oper_i_alu_alu0__rc__rc[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_alu0__rc__ok $0\fus_oper_i_alu_alu0__rc__ok[0:0] + update \fus_oper_i_alu_alu0__rc__rc $0\fus_oper_i_alu_alu0__rc__rc[0:0] + end + attribute \src "libresoc.v:46091.3-46099.6" + process $proc$libresoc.v:46091$2640 + assign { } { } + assign { } { } + assign $0\dp_CR_cr_a_cr0_0$next[0:0]$2641 $1\dp_CR_cr_a_cr0_0$next[0:0]$2642 + attribute \src "libresoc.v:46092.5-46092.29" + switch \initial + attribute \src "libresoc.v:46092.9-46092.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_CR_cr_a_cr0_0$next[0:0]$2642 1'0 + case + assign $1\dp_CR_cr_a_cr0_0$next[0:0]$2642 \rp_CR_cr_a_cr0_0 + end + sync always + update \dp_CR_cr_a_cr0_0$next $0\dp_CR_cr_a_cr0_0$next[0:0]$2641 + end + attribute \src "libresoc.v:46100.3-46109.6" + process $proc$libresoc.v:46100$2643 + assign { } { } + assign { } { } + assign $0\fus_src4_i$80[3:0]$2644 $1\fus_src4_i$80[3:0]$2645 + attribute \src "libresoc.v:46101.5-46101.29" + switch \initial + attribute \src "libresoc.v:46101.9-46101.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:294" + switch \dp_CR_cr_a_cr0_0 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src4_i$80[3:0]$2645 \cr_src1__data_o + case + assign $1\fus_src4_i$80[3:0]$2645 4'0000 + end + sync always + update \fus_src4_i$80 $0\fus_src4_i$80[3:0]$2644 + end + attribute \src "libresoc.v:46110.3-46118.6" + process $proc$libresoc.v:46110$2646 + assign { } { } + assign { } { } + assign $0\dp_CR_cr_a_branch0_1$next[0:0]$2647 $1\dp_CR_cr_a_branch0_1$next[0:0]$2648 + attribute \src "libresoc.v:46111.5-46111.29" + switch \initial + attribute \src "libresoc.v:46111.9-46111.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_CR_cr_a_branch0_1$next[0:0]$2648 1'0 + case + assign $1\dp_CR_cr_a_branch0_1$next[0:0]$2648 \rp_CR_cr_a_branch0_1 + end + sync always + update \dp_CR_cr_a_branch0_1$next $0\dp_CR_cr_a_branch0_1$next[0:0]$2647 + end + attribute \src "libresoc.v:46119.3-46128.6" + process $proc$libresoc.v:46119$2649 + assign { } { } + assign { } { } + assign $0\fus_src3_i$83[3:0]$2650 $1\fus_src3_i$83[3:0]$2651 + attribute \src "libresoc.v:46120.5-46120.29" + switch \initial + attribute \src "libresoc.v:46120.9-46120.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:294" + switch \dp_CR_cr_a_branch0_1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src3_i$83[3:0]$2651 \cr_src1__data_o + case + assign $1\fus_src3_i$83[3:0]$2651 4'0000 + end + sync always + update \fus_src3_i$83 $0\fus_src3_i$83[3:0]$2650 + end + attribute \src "libresoc.v:46129.3-46137.6" + process $proc$libresoc.v:46129$2652 + assign { } { } + assign { } { } + assign $0\dp_CR_cr_b_cr0_0$next[0:0]$2653 $1\dp_CR_cr_b_cr0_0$next[0:0]$2654 + attribute \src "libresoc.v:46130.5-46130.29" + switch \initial + attribute \src "libresoc.v:46130.9-46130.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_CR_cr_b_cr0_0$next[0:0]$2654 1'0 + case + assign $1\dp_CR_cr_b_cr0_0$next[0:0]$2654 \rp_CR_cr_b_cr0_0 + end + sync always + update \dp_CR_cr_b_cr0_0$next $0\dp_CR_cr_b_cr0_0$next[0:0]$2653 + end + attribute \src "libresoc.v:46138.3-46147.6" + process $proc$libresoc.v:46138$2655 + assign { } { } + assign { } { } + assign $0\fus_src5_i$84[3:0]$2656 $1\fus_src5_i$84[3:0]$2657 + attribute \src "libresoc.v:46139.5-46139.29" + switch \initial + attribute \src "libresoc.v:46139.9-46139.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:294" + switch \dp_CR_cr_b_cr0_0 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src5_i$84[3:0]$2657 \cr_src2__data_o + case + assign $1\fus_src5_i$84[3:0]$2657 4'0000 + end + sync always + update \fus_src5_i$84 $0\fus_src5_i$84[3:0]$2656 + end + attribute \src "libresoc.v:46148.3-46177.6" + process $proc$libresoc.v:46148$2658 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_alu0__oe__oe[0:0] $1\fus_oper_i_alu_alu0__oe__oe[0:0] + assign $0\fus_oper_i_alu_alu0__oe__ok[0:0] $1\fus_oper_i_alu_alu0__oe__ok[0:0] + attribute \src "libresoc.v:46149.5-46149.29" + switch \initial + attribute \src "libresoc.v:46149.9-46149.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $1\fus_oper_i_alu_alu0__oe__oe[0:0] $2\fus_oper_i_alu_alu0__oe__oe[0:0] + assign $1\fus_oper_i_alu_alu0__oe__ok[0:0] $2\fus_oper_i_alu_alu0__oe__ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_alu0__oe__oe[0:0] 1'0 + assign $2\fus_oper_i_alu_alu0__oe__ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_alu0__oe__oe[0:0] 1'0 + assign $2\fus_oper_i_alu_alu0__oe__ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign $2\fus_oper_i_alu_alu0__oe__oe[0:0] $3\fus_oper_i_alu_alu0__oe__oe[0:0] + assign $2\fus_oper_i_alu_alu0__oe__ok[0:0] $3\fus_oper_i_alu_alu0__oe__ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + switch \fu_enable [0] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $3\fus_oper_i_alu_alu0__oe__ok[0:0] $3\fus_oper_i_alu_alu0__oe__oe[0:0] } { \dec_ALU_ALU__oe__ok \dec_ALU_ALU__oe__oe } + case + assign $3\fus_oper_i_alu_alu0__oe__oe[0:0] 1'0 + assign $3\fus_oper_i_alu_alu0__oe__ok[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_alu0__oe__oe[0:0] 1'0 + assign $1\fus_oper_i_alu_alu0__oe__ok[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_alu0__oe__oe $0\fus_oper_i_alu_alu0__oe__oe[0:0] + update \fus_oper_i_alu_alu0__oe__ok $0\fus_oper_i_alu_alu0__oe__ok[0:0] + end + attribute \src "libresoc.v:46178.3-46186.6" + process $proc$libresoc.v:46178$2659 + assign { } { } + assign { } { } + assign $0\dp_CR_cr_c_cr0_0$next[0:0]$2660 $1\dp_CR_cr_c_cr0_0$next[0:0]$2661 + attribute \src "libresoc.v:46179.5-46179.29" + switch \initial + attribute \src "libresoc.v:46179.9-46179.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_CR_cr_c_cr0_0$next[0:0]$2661 1'0 + case + assign $1\dp_CR_cr_c_cr0_0$next[0:0]$2661 \rp_CR_cr_c_cr0_0 + end + sync always + update \dp_CR_cr_c_cr0_0$next $0\dp_CR_cr_c_cr0_0$next[0:0]$2660 + end + attribute \src "libresoc.v:46187.3-46196.6" + process $proc$libresoc.v:46187$2662 + assign { } { } + assign { } { } + assign $0\fus_src6_i$85[3:0]$2663 $1\fus_src6_i$85[3:0]$2664 + attribute \src "libresoc.v:46188.5-46188.29" + switch \initial + attribute \src "libresoc.v:46188.9-46188.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:294" + switch \dp_CR_cr_c_cr0_0 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src6_i$85[3:0]$2664 \cr_src3__data_o + case + assign $1\fus_src6_i$85[3:0]$2664 4'0000 + end + sync always + update \fus_src6_i$85 $0\fus_src6_i$85[3:0]$2663 + end + attribute \src "libresoc.v:46197.3-46205.6" + process $proc$libresoc.v:46197$2665 + assign { } { } + assign { } { } + assign $0\dp_FAST_fast1_branch0_0$next[0:0]$2666 $1\dp_FAST_fast1_branch0_0$next[0:0]$2667 + attribute \src "libresoc.v:46198.5-46198.29" + switch \initial + attribute \src "libresoc.v:46198.9-46198.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_FAST_fast1_branch0_0$next[0:0]$2667 1'0 + case + assign $1\dp_FAST_fast1_branch0_0$next[0:0]$2667 \rp_FAST_fast1_branch0_0 + end + sync always + update \dp_FAST_fast1_branch0_0$next $0\dp_FAST_fast1_branch0_0$next[0:0]$2666 + end + attribute \src "libresoc.v:46206.3-46215.6" + process $proc$libresoc.v:46206$2668 + assign { } { } + assign { } { } + assign $0\fus_src1_i$86[63:0]$2669 $1\fus_src1_i$86[63:0]$2670 + attribute \src "libresoc.v:46207.5-46207.29" + switch \initial + attribute \src "libresoc.v:46207.9-46207.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:294" + switch \dp_FAST_fast1_branch0_0 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src1_i$86[63:0]$2670 \fast_src1__data_o + case + assign $1\fus_src1_i$86[63:0]$2670 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fus_src1_i$86 $0\fus_src1_i$86[63:0]$2669 + end + attribute \src "libresoc.v:46216.3-46224.6" + process $proc$libresoc.v:46216$2671 + assign { } { } + assign { } { } + assign $0\dp_FAST_fast1_trap0_1$next[0:0]$2672 $1\dp_FAST_fast1_trap0_1$next[0:0]$2673 + attribute \src "libresoc.v:46217.5-46217.29" + switch \initial + attribute \src "libresoc.v:46217.9-46217.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_FAST_fast1_trap0_1$next[0:0]$2673 1'0 + case + assign $1\dp_FAST_fast1_trap0_1$next[0:0]$2673 \rp_FAST_fast1_trap0_1 + end + sync always + update \dp_FAST_fast1_trap0_1$next $0\dp_FAST_fast1_trap0_1$next[0:0]$2672 + end + attribute \src "libresoc.v:46225.3-46234.6" + process $proc$libresoc.v:46225$2674 + assign { } { } + assign { } { } + assign $0\fus_src3_i$87[63:0]$2675 $1\fus_src3_i$87[63:0]$2676 + attribute \src "libresoc.v:46226.5-46226.29" + switch \initial + attribute \src "libresoc.v:46226.9-46226.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:294" + switch \dp_FAST_fast1_trap0_1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src3_i$87[63:0]$2676 \fast_src1__data_o + case + assign $1\fus_src3_i$87[63:0]$2676 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fus_src3_i$87 $0\fus_src3_i$87[63:0]$2675 + end + attribute \src "libresoc.v:46235.3-46263.6" + process $proc$libresoc.v:46235$2677 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_alu0__invert_in[0:0] $1\fus_oper_i_alu_alu0__invert_in[0:0] + attribute \src "libresoc.v:46236.5-46236.29" + switch \initial + attribute \src "libresoc.v:46236.9-46236.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_alu0__invert_in[0:0] $2\fus_oper_i_alu_alu0__invert_in[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_alu0__invert_in[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_alu0__invert_in[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_alu0__invert_in[0:0] $3\fus_oper_i_alu_alu0__invert_in[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + switch \fu_enable [0] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_alu0__invert_in[0:0] \dec_ALU_ALU__invert_in + case + assign $3\fus_oper_i_alu_alu0__invert_in[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_alu0__invert_in[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_alu0__invert_in $0\fus_oper_i_alu_alu0__invert_in[0:0] + end + attribute \src "libresoc.v:46264.3-46272.6" + process $proc$libresoc.v:46264$2678 + assign { } { } + assign { } { } + assign $0\dp_FAST_fast1_spr0_2$next[0:0]$2679 $1\dp_FAST_fast1_spr0_2$next[0:0]$2680 + attribute \src "libresoc.v:46265.5-46265.29" + switch \initial + attribute \src "libresoc.v:46265.9-46265.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_FAST_fast1_spr0_2$next[0:0]$2680 1'0 + case + assign $1\dp_FAST_fast1_spr0_2$next[0:0]$2680 \rp_FAST_fast1_spr0_2 + end + sync always + update \dp_FAST_fast1_spr0_2$next $0\dp_FAST_fast1_spr0_2$next[0:0]$2679 + end + attribute \src "libresoc.v:46273.3-46282.6" + process $proc$libresoc.v:46273$2681 + assign { } { } + assign { } { } + assign $0\fus_src3_i$88[63:0]$2682 $1\fus_src3_i$88[63:0]$2683 + attribute \src "libresoc.v:46274.5-46274.29" + switch \initial + attribute \src "libresoc.v:46274.9-46274.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:294" + switch \dp_FAST_fast1_spr0_2 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src3_i$88[63:0]$2683 \fast_src1__data_o + case + assign $1\fus_src3_i$88[63:0]$2683 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fus_src3_i$88 $0\fus_src3_i$88[63:0]$2682 + end + attribute \src "libresoc.v:46283.3-46311.6" + process $proc$libresoc.v:46283$2684 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_alu0__zero_a[0:0] $1\fus_oper_i_alu_alu0__zero_a[0:0] + attribute \src "libresoc.v:46284.5-46284.29" + switch \initial + attribute \src "libresoc.v:46284.9-46284.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_alu0__zero_a[0:0] $2\fus_oper_i_alu_alu0__zero_a[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_alu0__zero_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_alu0__zero_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_alu0__zero_a[0:0] $3\fus_oper_i_alu_alu0__zero_a[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + switch \fu_enable [0] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_alu0__zero_a[0:0] \dec_ALU_ALU__zero_a + case + assign $3\fus_oper_i_alu_alu0__zero_a[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_alu0__zero_a[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_alu0__zero_a $0\fus_oper_i_alu_alu0__zero_a[0:0] + end + attribute \src "libresoc.v:46312.3-46320.6" + process $proc$libresoc.v:46312$2685 + assign { } { } + assign { } { } + assign $0\dp_FAST_fast2_branch0_0$next[0:0]$2686 $1\dp_FAST_fast2_branch0_0$next[0:0]$2687 + attribute \src "libresoc.v:46313.5-46313.29" + switch \initial + attribute \src "libresoc.v:46313.9-46313.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_FAST_fast2_branch0_0$next[0:0]$2687 1'0 + case + assign $1\dp_FAST_fast2_branch0_0$next[0:0]$2687 \rp_FAST_fast2_branch0_0 + end + sync always + update \dp_FAST_fast2_branch0_0$next $0\dp_FAST_fast2_branch0_0$next[0:0]$2686 + end + attribute \src "libresoc.v:46321.3-46330.6" + process $proc$libresoc.v:46321$2688 + assign { } { } + assign { } { } + assign $0\fus_src2_i$89[63:0]$2689 $1\fus_src2_i$89[63:0]$2690 + attribute \src "libresoc.v:46322.5-46322.29" + switch \initial + attribute \src "libresoc.v:46322.9-46322.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:294" + switch \dp_FAST_fast2_branch0_0 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src2_i$89[63:0]$2690 \fast_src2__data_o + case + assign $1\fus_src2_i$89[63:0]$2690 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fus_src2_i$89 $0\fus_src2_i$89[63:0]$2689 + end + attribute \src "libresoc.v:46331.3-46339.6" + process $proc$libresoc.v:46331$2691 + assign { } { } + assign { } { } + assign $0\dp_FAST_fast2_trap0_1$next[0:0]$2692 $1\dp_FAST_fast2_trap0_1$next[0:0]$2693 + attribute \src "libresoc.v:46332.5-46332.29" + switch \initial + attribute \src "libresoc.v:46332.9-46332.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_FAST_fast2_trap0_1$next[0:0]$2693 1'0 + case + assign $1\dp_FAST_fast2_trap0_1$next[0:0]$2693 \rp_FAST_fast2_trap0_1 + end + sync always + update \dp_FAST_fast2_trap0_1$next $0\dp_FAST_fast2_trap0_1$next[0:0]$2692 + end + attribute \src "libresoc.v:46340.3-46349.6" + process $proc$libresoc.v:46340$2694 + assign { } { } + assign { } { } + assign $0\fus_src4_i$90[63:0]$2695 $1\fus_src4_i$90[63:0]$2696 + attribute \src "libresoc.v:46341.5-46341.29" + switch \initial + attribute \src "libresoc.v:46341.9-46341.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:294" + switch \dp_FAST_fast2_trap0_1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src4_i$90[63:0]$2696 \fast_src2__data_o + case + assign $1\fus_src4_i$90[63:0]$2696 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fus_src4_i$90 $0\fus_src4_i$90[63:0]$2695 + end + attribute \src "libresoc.v:46350.3-46378.6" + process $proc$libresoc.v:46350$2697 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_alu0__invert_out[0:0] $1\fus_oper_i_alu_alu0__invert_out[0:0] + attribute \src "libresoc.v:46351.5-46351.29" + switch \initial + attribute \src "libresoc.v:46351.9-46351.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_alu0__invert_out[0:0] $2\fus_oper_i_alu_alu0__invert_out[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_alu0__invert_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_alu0__invert_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_alu0__invert_out[0:0] $3\fus_oper_i_alu_alu0__invert_out[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + switch \fu_enable [0] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_alu0__invert_out[0:0] \dec_ALU_ALU__invert_out + case + assign $3\fus_oper_i_alu_alu0__invert_out[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_alu0__invert_out[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_alu0__invert_out $0\fus_oper_i_alu_alu0__invert_out[0:0] + end + attribute \src "libresoc.v:46379.3-46387.6" + process $proc$libresoc.v:46379$2698 + assign { } { } + assign { } { } + assign $0\dp_SPR_spr1_spr0_0$next[0:0]$2699 $1\dp_SPR_spr1_spr0_0$next[0:0]$2700 + attribute \src "libresoc.v:46380.5-46380.29" + switch \initial + attribute \src "libresoc.v:46380.9-46380.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_SPR_spr1_spr0_0$next[0:0]$2700 1'0 + case + assign $1\dp_SPR_spr1_spr0_0$next[0:0]$2700 \rp_SPR_spr1_spr0_0 + end + sync always + update \dp_SPR_spr1_spr0_0$next $0\dp_SPR_spr1_spr0_0$next[0:0]$2699 + end + attribute \src "libresoc.v:46388.3-46397.6" + process $proc$libresoc.v:46388$2701 + assign { } { } + assign { } { } + assign $0\fus_src2_i$91[63:0]$2702 $1\fus_src2_i$91[63:0]$2703 + attribute \src "libresoc.v:46389.5-46389.29" + switch \initial + attribute \src "libresoc.v:46389.9-46389.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:294" + switch \dp_SPR_spr1_spr0_0 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src2_i$91[63:0]$2703 \spr_spr1__data_o + case + assign $1\fus_src2_i$91[63:0]$2703 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fus_src2_i$91 $0\fus_src2_i$91[63:0]$2702 + end + attribute \src "libresoc.v:46398.3-46426.6" + process $proc$libresoc.v:46398$2704 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_alu0__write_cr0[0:0] $1\fus_oper_i_alu_alu0__write_cr0[0:0] + attribute \src "libresoc.v:46399.5-46399.29" + switch \initial + attribute \src "libresoc.v:46399.9-46399.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_alu0__write_cr0[0:0] $2\fus_oper_i_alu_alu0__write_cr0[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_alu0__write_cr0[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_alu0__write_cr0[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_alu0__write_cr0[0:0] $3\fus_oper_i_alu_alu0__write_cr0[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + switch \fu_enable [0] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_alu0__write_cr0[0:0] \dec_ALU_ALU__write_cr0 + case + assign $3\fus_oper_i_alu_alu0__write_cr0[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_alu0__write_cr0[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_alu0__write_cr0 $0\fus_oper_i_alu_alu0__write_cr0[0:0] + end + attribute \src "libresoc.v:46427.3-46435.6" + process $proc$libresoc.v:46427$2705 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$next[0:0]$2706 $1\wr_pick_dly$next[0:0]$2707 + attribute \src "libresoc.v:46428.5-46428.29" + switch \initial + attribute \src "libresoc.v:46428.9-46428.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$next[0:0]$2707 1'0 + case + assign $1\wr_pick_dly$next[0:0]$2707 \wr_pick + end + sync always + update \wr_pick_dly$next $0\wr_pick_dly$next[0:0]$2706 + end + attribute \src "libresoc.v:46436.3-46464.6" + process $proc$libresoc.v:46436$2708 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_alu0__input_carry[1:0] $1\fus_oper_i_alu_alu0__input_carry[1:0] + attribute \src "libresoc.v:46437.5-46437.29" + switch \initial + attribute \src "libresoc.v:46437.9-46437.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_alu0__input_carry[1:0] $2\fus_oper_i_alu_alu0__input_carry[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_alu0__input_carry[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_alu0__input_carry[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_alu0__input_carry[1:0] $3\fus_oper_i_alu_alu0__input_carry[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + switch \fu_enable [0] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_alu0__input_carry[1:0] \dec_ALU_ALU__input_carry + case + assign $3\fus_oper_i_alu_alu0__input_carry[1:0] 2'00 + end + end + case + assign $1\fus_oper_i_alu_alu0__input_carry[1:0] 2'00 + end + sync always + update \fus_oper_i_alu_alu0__input_carry $0\fus_oper_i_alu_alu0__input_carry[1:0] + end + attribute \src "libresoc.v:46465.3-46473.6" + process $proc$libresoc.v:46465$2709 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$986$next[0:0]$2710 $1\wr_pick_dly$986$next[0:0]$2711 + attribute \src "libresoc.v:46466.5-46466.29" + switch \initial + attribute \src "libresoc.v:46466.9-46466.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$986$next[0:0]$2711 1'0 + case + assign $1\wr_pick_dly$986$next[0:0]$2711 \wr_pick$983 + end + sync always + update \wr_pick_dly$986$next $0\wr_pick_dly$986$next[0:0]$2710 + end + attribute \src "libresoc.v:46474.3-46482.6" + process $proc$libresoc.v:46474$2712 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1005$next[0:0]$2713 $1\wr_pick_dly$1005$next[0:0]$2714 + attribute \src "libresoc.v:46475.5-46475.29" + switch \initial + attribute \src "libresoc.v:46475.9-46475.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1005$next[0:0]$2714 1'0 + case + assign $1\wr_pick_dly$1005$next[0:0]$2714 \wr_pick$1002 + end + sync always + update \wr_pick_dly$1005$next $0\wr_pick_dly$1005$next[0:0]$2713 + end + attribute \src "libresoc.v:46483.3-46511.6" + process $proc$libresoc.v:46483$2715 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_alu0__output_carry[0:0] $1\fus_oper_i_alu_alu0__output_carry[0:0] + attribute \src "libresoc.v:46484.5-46484.29" + switch \initial + attribute \src "libresoc.v:46484.9-46484.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_alu0__output_carry[0:0] $2\fus_oper_i_alu_alu0__output_carry[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_alu0__output_carry[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_alu0__output_carry[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_alu0__output_carry[0:0] $3\fus_oper_i_alu_alu0__output_carry[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + switch \fu_enable [0] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_alu0__output_carry[0:0] \dec_ALU_ALU__output_carry + case + assign $3\fus_oper_i_alu_alu0__output_carry[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_alu0__output_carry[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_alu0__output_carry $0\fus_oper_i_alu_alu0__output_carry[0:0] + end + attribute \src "libresoc.v:46512.3-46520.6" + process $proc$libresoc.v:46512$2716 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1026$next[0:0]$2717 $1\wr_pick_dly$1026$next[0:0]$2718 + attribute \src "libresoc.v:46513.5-46513.29" + switch \initial + attribute \src "libresoc.v:46513.9-46513.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1026$next[0:0]$2718 1'0 + case + assign $1\wr_pick_dly$1026$next[0:0]$2718 \wr_pick$1023 + end + sync always + update \wr_pick_dly$1026$next $0\wr_pick_dly$1026$next[0:0]$2717 + end + attribute \src "libresoc.v:46521.3-46549.6" + process $proc$libresoc.v:46521$2719 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_alu0__is_32bit[0:0] $1\fus_oper_i_alu_alu0__is_32bit[0:0] + attribute \src "libresoc.v:46522.5-46522.29" + switch \initial + attribute \src "libresoc.v:46522.9-46522.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_alu0__is_32bit[0:0] $2\fus_oper_i_alu_alu0__is_32bit[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_alu0__is_32bit[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_alu0__is_32bit[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_alu0__is_32bit[0:0] $3\fus_oper_i_alu_alu0__is_32bit[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + switch \fu_enable [0] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_alu0__is_32bit[0:0] \dec_ALU_ALU__is_32bit + case + assign $3\fus_oper_i_alu_alu0__is_32bit[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_alu0__is_32bit[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_alu0__is_32bit $0\fus_oper_i_alu_alu0__is_32bit[0:0] + end + attribute \src "libresoc.v:46550.3-46558.6" + process $proc$libresoc.v:46550$2720 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1044$next[0:0]$2721 $1\wr_pick_dly$1044$next[0:0]$2722 + attribute \src "libresoc.v:46551.5-46551.29" + switch \initial + attribute \src "libresoc.v:46551.9-46551.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1044$next[0:0]$2722 1'0 + case + assign $1\wr_pick_dly$1044$next[0:0]$2722 \wr_pick$1041 + end + sync always + update \wr_pick_dly$1044$next $0\wr_pick_dly$1044$next[0:0]$2721 + end + attribute \src "libresoc.v:46559.3-46567.6" + process $proc$libresoc.v:46559$2723 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1066$next[0:0]$2724 $1\wr_pick_dly$1066$next[0:0]$2725 + attribute \src "libresoc.v:46560.5-46560.29" + switch \initial + attribute \src "libresoc.v:46560.9-46560.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1066$next[0:0]$2725 1'0 + case + assign $1\wr_pick_dly$1066$next[0:0]$2725 \wr_pick$1063 + end + sync always + update \wr_pick_dly$1066$next $0\wr_pick_dly$1066$next[0:0]$2724 + end + attribute \src "libresoc.v:46568.3-46596.6" + process $proc$libresoc.v:46568$2726 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_alu0__is_signed[0:0] $1\fus_oper_i_alu_alu0__is_signed[0:0] + attribute \src "libresoc.v:46569.5-46569.29" + switch \initial + attribute \src "libresoc.v:46569.9-46569.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_alu0__is_signed[0:0] $2\fus_oper_i_alu_alu0__is_signed[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_alu0__is_signed[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_alu0__is_signed[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_alu0__is_signed[0:0] $3\fus_oper_i_alu_alu0__is_signed[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + switch \fu_enable [0] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_alu0__is_signed[0:0] \dec_ALU_ALU__is_signed + case + assign $3\fus_oper_i_alu_alu0__is_signed[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_alu0__is_signed[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_alu0__is_signed $0\fus_oper_i_alu_alu0__is_signed[0:0] + end + attribute \src "libresoc.v:46597.3-46605.6" + process $proc$libresoc.v:46597$2727 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1086$next[0:0]$2728 $1\wr_pick_dly$1086$next[0:0]$2729 + attribute \src "libresoc.v:46598.5-46598.29" + switch \initial + attribute \src "libresoc.v:46598.9-46598.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1086$next[0:0]$2729 1'0 + case + assign $1\wr_pick_dly$1086$next[0:0]$2729 \wr_pick$1083 + end + sync always + update \wr_pick_dly$1086$next $0\wr_pick_dly$1086$next[0:0]$2728 + end + attribute \src "libresoc.v:46606.3-46634.6" + process $proc$libresoc.v:46606$2730 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_alu0__data_len[3:0] $1\fus_oper_i_alu_alu0__data_len[3:0] + attribute \src "libresoc.v:46607.5-46607.29" + switch \initial + attribute \src "libresoc.v:46607.9-46607.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_alu0__data_len[3:0] $2\fus_oper_i_alu_alu0__data_len[3:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_alu0__data_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_alu0__data_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_alu0__data_len[3:0] $3\fus_oper_i_alu_alu0__data_len[3:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + switch \fu_enable [0] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_alu0__data_len[3:0] \dec_ALU_ALU__data_len + case + assign $3\fus_oper_i_alu_alu0__data_len[3:0] 4'0000 + end + end + case + assign $1\fus_oper_i_alu_alu0__data_len[3:0] 4'0000 + end + sync always + update \fus_oper_i_alu_alu0__data_len $0\fus_oper_i_alu_alu0__data_len[3:0] + end + attribute \src "libresoc.v:46635.3-46643.6" + process $proc$libresoc.v:46635$2731 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1106$next[0:0]$2732 $1\wr_pick_dly$1106$next[0:0]$2733 + attribute \src "libresoc.v:46636.5-46636.29" + switch \initial + attribute \src "libresoc.v:46636.9-46636.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1106$next[0:0]$2733 1'0 + case + assign $1\wr_pick_dly$1106$next[0:0]$2733 \wr_pick$1103 + end + sync always + update \wr_pick_dly$1106$next $0\wr_pick_dly$1106$next[0:0]$2732 + end + attribute \src "libresoc.v:46644.3-46652.6" + process $proc$libresoc.v:46644$2734 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1125$next[0:0]$2735 $1\wr_pick_dly$1125$next[0:0]$2736 + attribute \src "libresoc.v:46645.5-46645.29" + switch \initial + attribute \src "libresoc.v:46645.9-46645.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1125$next[0:0]$2736 1'0 + case + assign $1\wr_pick_dly$1125$next[0:0]$2736 \wr_pick$1122 + end + sync always + update \wr_pick_dly$1125$next $0\wr_pick_dly$1125$next[0:0]$2735 + end + attribute \src "libresoc.v:46653.3-46681.6" + process $proc$libresoc.v:46653$2737 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_alu0__insn[31:0] $1\fus_oper_i_alu_alu0__insn[31:0] + attribute \src "libresoc.v:46654.5-46654.29" + switch \initial + attribute \src "libresoc.v:46654.9-46654.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_alu0__insn[31:0] $2\fus_oper_i_alu_alu0__insn[31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_alu0__insn[31:0] 0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_alu0__insn[31:0] 0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_alu0__insn[31:0] $3\fus_oper_i_alu_alu0__insn[31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + switch \fu_enable [0] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_alu0__insn[31:0] \dec_ALU_ALU__insn + case + assign $3\fus_oper_i_alu_alu0__insn[31:0] 0 + end + end + case + assign $1\fus_oper_i_alu_alu0__insn[31:0] 0 + end + sync always + update \fus_oper_i_alu_alu0__insn $0\fus_oper_i_alu_alu0__insn[31:0] + end + attribute \src "libresoc.v:46682.3-46690.6" + process $proc$libresoc.v:46682$2738 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1143$next[0:0]$2739 $1\wr_pick_dly$1143$next[0:0]$2740 + attribute \src "libresoc.v:46683.5-46683.29" + switch \initial + attribute \src "libresoc.v:46683.9-46683.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1143$next[0:0]$2740 1'0 + case + assign $1\wr_pick_dly$1143$next[0:0]$2740 \wr_pick$1140 + end + sync always + update \wr_pick_dly$1143$next $0\wr_pick_dly$1143$next[0:0]$2739 + end + attribute \src "libresoc.v:46691.3-46719.6" + process $proc$libresoc.v:46691$2741 + assign { } { } + assign { } { } + assign $0\fus_cu_issue_i[0:0] $1\fus_cu_issue_i[0:0] + attribute \src "libresoc.v:46692.5-46692.29" + switch \initial + attribute \src "libresoc.v:46692.9-46692.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_cu_issue_i[0:0] $2\fus_cu_issue_i[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_cu_issue_i[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_cu_issue_i[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_cu_issue_i[0:0] $3\fus_cu_issue_i[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + switch \fu_enable [0] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_cu_issue_i[0:0] \issue_i + case + assign $3\fus_cu_issue_i[0:0] 1'0 + end + end + case + assign $1\fus_cu_issue_i[0:0] 1'0 + end + sync always + update \fus_cu_issue_i $0\fus_cu_issue_i[0:0] + end + attribute \src "libresoc.v:46720.3-46728.6" + process $proc$libresoc.v:46720$2742 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1217$next[0:0]$2743 $1\wr_pick_dly$1217$next[0:0]$2744 + attribute \src "libresoc.v:46721.5-46721.29" + switch \initial + attribute \src "libresoc.v:46721.9-46721.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1217$next[0:0]$2744 1'0 + case + assign $1\wr_pick_dly$1217$next[0:0]$2744 \wr_pick$1214 + end + sync always + update \wr_pick_dly$1217$next $0\wr_pick_dly$1217$next[0:0]$2743 + end + attribute \src "libresoc.v:46729.3-46757.6" + process $proc$libresoc.v:46729$2745 + assign { } { } + assign { } { } + assign $0\fus_cu_rdmaskn_i[3:0] $1\fus_cu_rdmaskn_i[3:0] + attribute \src "libresoc.v:46730.5-46730.29" + switch \initial + attribute \src "libresoc.v:46730.9-46730.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_cu_rdmaskn_i[3:0] $2\fus_cu_rdmaskn_i[3:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_cu_rdmaskn_i[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_cu_rdmaskn_i[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_cu_rdmaskn_i[3:0] $3\fus_cu_rdmaskn_i[3:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + switch \fu_enable [0] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_cu_rdmaskn_i[3:0] \$223 + case + assign $3\fus_cu_rdmaskn_i[3:0] 4'0000 + end + end + case + assign $1\fus_cu_rdmaskn_i[3:0] 4'0000 + end + sync always + update \fus_cu_rdmaskn_i $0\fus_cu_rdmaskn_i[3:0] + end + attribute \src "libresoc.v:46758.3-46766.6" + process $proc$libresoc.v:46758$2746 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1245$next[0:0]$2747 $1\wr_pick_dly$1245$next[0:0]$2748 + attribute \src "libresoc.v:46759.5-46759.29" + switch \initial + attribute \src "libresoc.v:46759.9-46759.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1245$next[0:0]$2748 1'0 + case + assign $1\wr_pick_dly$1245$next[0:0]$2748 \wr_pick$1242 + end + sync always + update \wr_pick_dly$1245$next $0\wr_pick_dly$1245$next[0:0]$2747 + end + attribute \src "libresoc.v:46767.3-46795.6" + process $proc$libresoc.v:46767$2749 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_cr0__insn_type[6:0] $1\fus_oper_i_alu_cr0__insn_type[6:0] + attribute \src "libresoc.v:46768.5-46768.29" + switch \initial + attribute \src "libresoc.v:46768.9-46768.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_cr0__insn_type[6:0] $2\fus_oper_i_alu_cr0__insn_type[6:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_cr0__insn_type[6:0] 7'0000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_cr0__insn_type[6:0] 7'0000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_cr0__insn_type[6:0] $3\fus_oper_i_alu_cr0__insn_type[6:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + switch \fu_enable [1] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_cr0__insn_type[6:0] \dec_CR_CR__insn_type + case + assign $3\fus_oper_i_alu_cr0__insn_type[6:0] 7'0000000 + end + end + case + assign $1\fus_oper_i_alu_cr0__insn_type[6:0] 7'0000000 + end + sync always + update \fus_oper_i_alu_cr0__insn_type $0\fus_oper_i_alu_cr0__insn_type[6:0] + end + attribute \src "libresoc.v:46796.3-46804.6" + process $proc$libresoc.v:46796$2750 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1265$next[0:0]$2751 $1\wr_pick_dly$1265$next[0:0]$2752 + attribute \src "libresoc.v:46797.5-46797.29" + switch \initial + attribute \src "libresoc.v:46797.9-46797.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1265$next[0:0]$2752 1'0 + case + assign $1\wr_pick_dly$1265$next[0:0]$2752 \wr_pick$1262 + end + sync always + update \wr_pick_dly$1265$next $0\wr_pick_dly$1265$next[0:0]$2751 + end + attribute \src "libresoc.v:46805.3-46813.6" + process $proc$libresoc.v:46805$2753 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1285$next[0:0]$2754 $1\wr_pick_dly$1285$next[0:0]$2755 + attribute \src "libresoc.v:46806.5-46806.29" + switch \initial + attribute \src "libresoc.v:46806.9-46806.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1285$next[0:0]$2755 1'0 + case + assign $1\wr_pick_dly$1285$next[0:0]$2755 \wr_pick$1282 + end + sync always + update \wr_pick_dly$1285$next $0\wr_pick_dly$1285$next[0:0]$2754 + end + attribute \src "libresoc.v:46814.3-46842.6" + process $proc$libresoc.v:46814$2756 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_cr0__fn_unit[12:0] $1\fus_oper_i_alu_cr0__fn_unit[12:0] + attribute \src "libresoc.v:46815.5-46815.29" + switch \initial + attribute \src "libresoc.v:46815.9-46815.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_cr0__fn_unit[12:0] $2\fus_oper_i_alu_cr0__fn_unit[12:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_cr0__fn_unit[12:0] 13'0000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_cr0__fn_unit[12:0] 13'0000000000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_cr0__fn_unit[12:0] $3\fus_oper_i_alu_cr0__fn_unit[12:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + switch \fu_enable [1] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_cr0__fn_unit[12:0] \dec_CR_CR__fn_unit + case + assign $3\fus_oper_i_alu_cr0__fn_unit[12:0] 13'0000000000000 + end + end + case + assign $1\fus_oper_i_alu_cr0__fn_unit[12:0] 13'0000000000000 + end + sync always + update \fus_oper_i_alu_cr0__fn_unit $0\fus_oper_i_alu_cr0__fn_unit[12:0] + end + attribute \src "libresoc.v:46843.3-46851.6" + process $proc$libresoc.v:46843$2757 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1305$next[0:0]$2758 $1\wr_pick_dly$1305$next[0:0]$2759 + attribute \src "libresoc.v:46844.5-46844.29" + switch \initial + attribute \src "libresoc.v:46844.9-46844.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1305$next[0:0]$2759 1'0 + case + assign $1\wr_pick_dly$1305$next[0:0]$2759 \wr_pick$1302 + end + sync always + update \wr_pick_dly$1305$next $0\wr_pick_dly$1305$next[0:0]$2758 + end + attribute \src "libresoc.v:46852.3-46860.6" + process $proc$libresoc.v:46852$2760 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1325$next[0:0]$2761 $1\wr_pick_dly$1325$next[0:0]$2762 + attribute \src "libresoc.v:46853.5-46853.29" + switch \initial + attribute \src "libresoc.v:46853.9-46853.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1325$next[0:0]$2762 1'0 + case + assign $1\wr_pick_dly$1325$next[0:0]$2762 \wr_pick$1322 + end + sync always + update \wr_pick_dly$1325$next $0\wr_pick_dly$1325$next[0:0]$2761 + end + attribute \src "libresoc.v:46861.3-46889.6" + process $proc$libresoc.v:46861$2763 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_cr0__insn[31:0] $1\fus_oper_i_alu_cr0__insn[31:0] + attribute \src "libresoc.v:46862.5-46862.29" + switch \initial + attribute \src "libresoc.v:46862.9-46862.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_cr0__insn[31:0] $2\fus_oper_i_alu_cr0__insn[31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_cr0__insn[31:0] 0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_cr0__insn[31:0] 0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_cr0__insn[31:0] $3\fus_oper_i_alu_cr0__insn[31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + switch \fu_enable [1] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_cr0__insn[31:0] \dec_CR_CR__insn + case + assign $3\fus_oper_i_alu_cr0__insn[31:0] 0 + end + end + case + assign $1\fus_oper_i_alu_cr0__insn[31:0] 0 + end + sync always + update \fus_oper_i_alu_cr0__insn $0\fus_oper_i_alu_cr0__insn[31:0] + end + attribute \src "libresoc.v:46890.3-46898.6" + process $proc$libresoc.v:46890$2764 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1345$next[0:0]$2765 $1\wr_pick_dly$1345$next[0:0]$2766 + attribute \src "libresoc.v:46891.5-46891.29" + switch \initial + attribute \src "libresoc.v:46891.9-46891.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1345$next[0:0]$2766 1'0 + case + assign $1\wr_pick_dly$1345$next[0:0]$2766 \wr_pick$1342 + end + sync always + update \wr_pick_dly$1345$next $0\wr_pick_dly$1345$next[0:0]$2765 + end + attribute \src "libresoc.v:46899.3-46927.6" + process $proc$libresoc.v:46899$2767 + assign { } { } + assign { } { } + assign $0\fus_cu_issue_i$13[0:0]$2768 $1\fus_cu_issue_i$13[0:0]$2769 + attribute \src "libresoc.v:46900.5-46900.29" + switch \initial + attribute \src "libresoc.v:46900.9-46900.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_cu_issue_i$13[0:0]$2769 $2\fus_cu_issue_i$13[0:0]$2770 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_cu_issue_i$13[0:0]$2770 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_cu_issue_i$13[0:0]$2770 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_cu_issue_i$13[0:0]$2770 $3\fus_cu_issue_i$13[0:0]$2771 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + switch \fu_enable [1] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_cu_issue_i$13[0:0]$2771 \issue_i + case + assign $3\fus_cu_issue_i$13[0:0]$2771 1'0 + end + end + case + assign $1\fus_cu_issue_i$13[0:0]$2769 1'0 + end + sync always + update \fus_cu_issue_i$13 $0\fus_cu_issue_i$13[0:0]$2768 + end + attribute \src "libresoc.v:46928.3-46936.6" + process $proc$libresoc.v:46928$2772 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1392$next[0:0]$2773 $1\wr_pick_dly$1392$next[0:0]$2774 + attribute \src "libresoc.v:46929.5-46929.29" + switch \initial + attribute \src "libresoc.v:46929.9-46929.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1392$next[0:0]$2774 1'0 + case + assign $1\wr_pick_dly$1392$next[0:0]$2774 \wr_pick$1389 + end + sync always + update \wr_pick_dly$1392$next $0\wr_pick_dly$1392$next[0:0]$2773 + end + attribute \src "libresoc.v:46937.3-46965.6" + process $proc$libresoc.v:46937$2775 + assign { } { } + assign { } { } + assign $0\fus_cu_rdmaskn_i$15[5:0]$2776 $1\fus_cu_rdmaskn_i$15[5:0]$2777 + attribute \src "libresoc.v:46938.5-46938.29" + switch \initial + attribute \src "libresoc.v:46938.9-46938.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_cu_rdmaskn_i$15[5:0]$2777 $2\fus_cu_rdmaskn_i$15[5:0]$2778 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_cu_rdmaskn_i$15[5:0]$2778 6'000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_cu_rdmaskn_i$15[5:0]$2778 6'000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_cu_rdmaskn_i$15[5:0]$2778 $3\fus_cu_rdmaskn_i$15[5:0]$2779 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + switch \fu_enable [1] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_cu_rdmaskn_i$15[5:0]$2779 \$245 + case + assign $3\fus_cu_rdmaskn_i$15[5:0]$2779 6'000000 + end + end + case + assign $1\fus_cu_rdmaskn_i$15[5:0]$2777 6'000000 + end + sync always + update \fus_cu_rdmaskn_i$15 $0\fus_cu_rdmaskn_i$15[5:0]$2776 + end + attribute \src "libresoc.v:46966.3-46974.6" + process $proc$libresoc.v:46966$2780 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1408$next[0:0]$2781 $1\wr_pick_dly$1408$next[0:0]$2782 + attribute \src "libresoc.v:46967.5-46967.29" + switch \initial + attribute \src "libresoc.v:46967.9-46967.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1408$next[0:0]$2782 1'0 + case + assign $1\wr_pick_dly$1408$next[0:0]$2782 \wr_pick$1405 + end + sync always + update \wr_pick_dly$1408$next $0\wr_pick_dly$1408$next[0:0]$2781 + end + attribute \src "libresoc.v:46975.3-46983.6" + process $proc$libresoc.v:46975$2783 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1424$next[0:0]$2784 $1\wr_pick_dly$1424$next[0:0]$2785 + attribute \src "libresoc.v:46976.5-46976.29" + switch \initial + attribute \src "libresoc.v:46976.9-46976.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1424$next[0:0]$2785 1'0 + case + assign $1\wr_pick_dly$1424$next[0:0]$2785 \wr_pick$1421 + end + sync always + update \wr_pick_dly$1424$next $0\wr_pick_dly$1424$next[0:0]$2784 + end + attribute \src "libresoc.v:46984.3-47012.6" + process $proc$libresoc.v:46984$2786 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_branch0__cia[63:0] $1\fus_oper_i_alu_branch0__cia[63:0] + attribute \src "libresoc.v:46985.5-46985.29" + switch \initial + attribute \src "libresoc.v:46985.9-46985.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_branch0__cia[63:0] $2\fus_oper_i_alu_branch0__cia[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_branch0__cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_branch0__cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_branch0__cia[63:0] $3\fus_oper_i_alu_branch0__cia[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + switch \fu_enable [2] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_branch0__cia[63:0] \dec_BRANCH_BRANCH__cia + case + assign $3\fus_oper_i_alu_branch0__cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + end + case + assign $1\fus_oper_i_alu_branch0__cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fus_oper_i_alu_branch0__cia $0\fus_oper_i_alu_branch0__cia[63:0] + end + attribute \src "libresoc.v:47013.3-47021.6" + process $proc$libresoc.v:47013$2787 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1458$next[0:0]$2788 $1\wr_pick_dly$1458$next[0:0]$2789 + attribute \src "libresoc.v:47014.5-47014.29" + switch \initial + attribute \src "libresoc.v:47014.9-47014.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1458$next[0:0]$2789 1'0 + case + assign $1\wr_pick_dly$1458$next[0:0]$2789 \wr_pick$1455 + end + sync always + update \wr_pick_dly$1458$next $0\wr_pick_dly$1458$next[0:0]$2788 + end + attribute \src "libresoc.v:47022.3-47050.6" + process $proc$libresoc.v:47022$2790 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_branch0__insn_type[6:0] $1\fus_oper_i_alu_branch0__insn_type[6:0] + attribute \src "libresoc.v:47023.5-47023.29" + switch \initial + attribute \src "libresoc.v:47023.9-47023.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_branch0__insn_type[6:0] $2\fus_oper_i_alu_branch0__insn_type[6:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_branch0__insn_type[6:0] 7'0000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_branch0__insn_type[6:0] 7'0000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_branch0__insn_type[6:0] $3\fus_oper_i_alu_branch0__insn_type[6:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + switch \fu_enable [2] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_branch0__insn_type[6:0] \dec_BRANCH_BRANCH__insn_type + case + assign $3\fus_oper_i_alu_branch0__insn_type[6:0] 7'0000000 + end + end + case + assign $1\fus_oper_i_alu_branch0__insn_type[6:0] 7'0000000 + end + sync always + update \fus_oper_i_alu_branch0__insn_type $0\fus_oper_i_alu_branch0__insn_type[6:0] + end + attribute \src "libresoc.v:47051.3-47059.6" + process $proc$libresoc.v:47051$2791 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1474$next[0:0]$2792 $1\wr_pick_dly$1474$next[0:0]$2793 + attribute \src "libresoc.v:47052.5-47052.29" + switch \initial + attribute \src "libresoc.v:47052.9-47052.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1474$next[0:0]$2793 1'0 + case + assign $1\wr_pick_dly$1474$next[0:0]$2793 \wr_pick$1471 + end + sync always + update \wr_pick_dly$1474$next $0\wr_pick_dly$1474$next[0:0]$2792 + end + attribute \src "libresoc.v:47060.3-47068.6" + process $proc$libresoc.v:47060$2794 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1490$next[0:0]$2795 $1\wr_pick_dly$1490$next[0:0]$2796 + attribute \src "libresoc.v:47061.5-47061.29" + switch \initial + attribute \src "libresoc.v:47061.9-47061.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1490$next[0:0]$2796 1'0 + case + assign $1\wr_pick_dly$1490$next[0:0]$2796 \wr_pick$1487 + end + sync always + update \wr_pick_dly$1490$next $0\wr_pick_dly$1490$next[0:0]$2795 + end + attribute \src "libresoc.v:47069.3-47097.6" + process $proc$libresoc.v:47069$2797 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_branch0__fn_unit[12:0] $1\fus_oper_i_alu_branch0__fn_unit[12:0] + attribute \src "libresoc.v:47070.5-47070.29" + switch \initial + attribute \src "libresoc.v:47070.9-47070.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_branch0__fn_unit[12:0] $2\fus_oper_i_alu_branch0__fn_unit[12:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_branch0__fn_unit[12:0] 13'0000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_branch0__fn_unit[12:0] 13'0000000000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_branch0__fn_unit[12:0] $3\fus_oper_i_alu_branch0__fn_unit[12:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + switch \fu_enable [2] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_branch0__fn_unit[12:0] \dec_BRANCH_BRANCH__fn_unit + case + assign $3\fus_oper_i_alu_branch0__fn_unit[12:0] 13'0000000000000 + end + end + case + assign $1\fus_oper_i_alu_branch0__fn_unit[12:0] 13'0000000000000 + end + sync always + update \fus_oper_i_alu_branch0__fn_unit $0\fus_oper_i_alu_branch0__fn_unit[12:0] + end + attribute \src "libresoc.v:47098.3-47106.6" + process $proc$libresoc.v:47098$2798 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1506$next[0:0]$2799 $1\wr_pick_dly$1506$next[0:0]$2800 + attribute \src "libresoc.v:47099.5-47099.29" + switch \initial + attribute \src "libresoc.v:47099.9-47099.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1506$next[0:0]$2800 1'0 + case + assign $1\wr_pick_dly$1506$next[0:0]$2800 \wr_pick$1503 + end + sync always + update \wr_pick_dly$1506$next $0\wr_pick_dly$1506$next[0:0]$2799 + end + attribute \src "libresoc.v:47107.3-47135.6" + process $proc$libresoc.v:47107$2801 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_branch0__insn[31:0] $1\fus_oper_i_alu_branch0__insn[31:0] + attribute \src "libresoc.v:47108.5-47108.29" + switch \initial + attribute \src "libresoc.v:47108.9-47108.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_branch0__insn[31:0] $2\fus_oper_i_alu_branch0__insn[31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_branch0__insn[31:0] 0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_branch0__insn[31:0] 0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_branch0__insn[31:0] $3\fus_oper_i_alu_branch0__insn[31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + switch \fu_enable [2] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_branch0__insn[31:0] \dec_BRANCH_BRANCH__insn + case + assign $3\fus_oper_i_alu_branch0__insn[31:0] 0 + end + end + case + assign $1\fus_oper_i_alu_branch0__insn[31:0] 0 + end + sync always + update \fus_oper_i_alu_branch0__insn $0\fus_oper_i_alu_branch0__insn[31:0] + end + attribute \src "libresoc.v:47136.3-47144.6" + process $proc$libresoc.v:47136$2802 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1542$next[0:0]$2803 $1\wr_pick_dly$1542$next[0:0]$2804 + attribute \src "libresoc.v:47137.5-47137.29" + switch \initial + attribute \src "libresoc.v:47137.9-47137.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1542$next[0:0]$2804 1'0 + case + assign $1\wr_pick_dly$1542$next[0:0]$2804 \wr_pick$1539 + end + sync always + update \wr_pick_dly$1542$next $0\wr_pick_dly$1542$next[0:0]$2803 + end + attribute \src "libresoc.v:47145.3-47153.6" + process $proc$libresoc.v:47145$2805 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1558$next[0:0]$2806 $1\wr_pick_dly$1558$next[0:0]$2807 + attribute \src "libresoc.v:47146.5-47146.29" + switch \initial + attribute \src "libresoc.v:47146.9-47146.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1558$next[0:0]$2807 1'0 + case + assign $1\wr_pick_dly$1558$next[0:0]$2807 \wr_pick$1555 + end + sync always + update \wr_pick_dly$1558$next $0\wr_pick_dly$1558$next[0:0]$2806 + end + attribute \src "libresoc.v:47154.3-47183.6" + process $proc$libresoc.v:47154$2808 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_branch0__imm_data__data[63:0] $1\fus_oper_i_alu_branch0__imm_data__data[63:0] + assign $0\fus_oper_i_alu_branch0__imm_data__ok[0:0] $1\fus_oper_i_alu_branch0__imm_data__ok[0:0] + attribute \src "libresoc.v:47155.5-47155.29" + switch \initial + attribute \src "libresoc.v:47155.9-47155.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $1\fus_oper_i_alu_branch0__imm_data__data[63:0] $2\fus_oper_i_alu_branch0__imm_data__data[63:0] + assign $1\fus_oper_i_alu_branch0__imm_data__ok[0:0] $2\fus_oper_i_alu_branch0__imm_data__ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_branch0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\fus_oper_i_alu_branch0__imm_data__ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_branch0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\fus_oper_i_alu_branch0__imm_data__ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign $2\fus_oper_i_alu_branch0__imm_data__data[63:0] $3\fus_oper_i_alu_branch0__imm_data__data[63:0] + assign $2\fus_oper_i_alu_branch0__imm_data__ok[0:0] $3\fus_oper_i_alu_branch0__imm_data__ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + switch \fu_enable [2] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $3\fus_oper_i_alu_branch0__imm_data__ok[0:0] $3\fus_oper_i_alu_branch0__imm_data__data[63:0] } { \dec_BRANCH_BRANCH__imm_data__ok \dec_BRANCH_BRANCH__imm_data__data } + case + assign $3\fus_oper_i_alu_branch0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\fus_oper_i_alu_branch0__imm_data__ok[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_branch0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fus_oper_i_alu_branch0__imm_data__ok[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_branch0__imm_data__data $0\fus_oper_i_alu_branch0__imm_data__data[63:0] + update \fus_oper_i_alu_branch0__imm_data__ok $0\fus_oper_i_alu_branch0__imm_data__ok[0:0] + end + attribute \src "libresoc.v:47184.3-47192.6" + process $proc$libresoc.v:47184$2809 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1574$next[0:0]$2810 $1\wr_pick_dly$1574$next[0:0]$2811 + attribute \src "libresoc.v:47185.5-47185.29" + switch \initial + attribute \src "libresoc.v:47185.9-47185.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1574$next[0:0]$2811 1'0 + case + assign $1\wr_pick_dly$1574$next[0:0]$2811 \wr_pick$1571 + end + sync always + update \wr_pick_dly$1574$next $0\wr_pick_dly$1574$next[0:0]$2810 + end + attribute \src "libresoc.v:47193.3-47201.6" + process $proc$libresoc.v:47193$2812 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1590$next[0:0]$2813 $1\wr_pick_dly$1590$next[0:0]$2814 + attribute \src "libresoc.v:47194.5-47194.29" + switch \initial + attribute \src "libresoc.v:47194.9-47194.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1590$next[0:0]$2814 1'0 + case + assign $1\wr_pick_dly$1590$next[0:0]$2814 \wr_pick$1587 + end + sync always + update \wr_pick_dly$1590$next $0\wr_pick_dly$1590$next[0:0]$2813 + end + attribute \src "libresoc.v:47202.3-47210.6" + process $proc$libresoc.v:47202$2815 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1632$next[0:0]$2816 $1\wr_pick_dly$1632$next[0:0]$2817 + attribute \src "libresoc.v:47203.5-47203.29" + switch \initial + attribute \src "libresoc.v:47203.9-47203.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1632$next[0:0]$2817 1'0 + case + assign $1\wr_pick_dly$1632$next[0:0]$2817 \wr_pick$1629 + end + sync always + update \wr_pick_dly$1632$next $0\wr_pick_dly$1632$next[0:0]$2816 + end + attribute \src "libresoc.v:47211.3-47239.6" + process $proc$libresoc.v:47211$2818 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_branch0__lk[0:0] $1\fus_oper_i_alu_branch0__lk[0:0] + attribute \src "libresoc.v:47212.5-47212.29" + switch \initial + attribute \src "libresoc.v:47212.9-47212.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_branch0__lk[0:0] $2\fus_oper_i_alu_branch0__lk[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_branch0__lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_branch0__lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_branch0__lk[0:0] $3\fus_oper_i_alu_branch0__lk[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + switch \fu_enable [2] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_branch0__lk[0:0] \dec_BRANCH_BRANCH__lk + case + assign $3\fus_oper_i_alu_branch0__lk[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_branch0__lk[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_branch0__lk $0\fus_oper_i_alu_branch0__lk[0:0] + end + attribute \src "libresoc.v:47240.3-47248.6" + process $proc$libresoc.v:47240$2819 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1651$next[0:0]$2820 $1\wr_pick_dly$1651$next[0:0]$2821 + attribute \src "libresoc.v:47241.5-47241.29" + switch \initial + attribute \src "libresoc.v:47241.9-47241.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1651$next[0:0]$2821 1'0 + case + assign $1\wr_pick_dly$1651$next[0:0]$2821 \wr_pick$1648 + end + sync always + update \wr_pick_dly$1651$next $0\wr_pick_dly$1651$next[0:0]$2820 + end + attribute \src "libresoc.v:47249.3-47277.6" + process $proc$libresoc.v:47249$2822 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_branch0__is_32bit[0:0] $1\fus_oper_i_alu_branch0__is_32bit[0:0] + attribute \src "libresoc.v:47250.5-47250.29" + switch \initial + attribute \src "libresoc.v:47250.9-47250.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_branch0__is_32bit[0:0] $2\fus_oper_i_alu_branch0__is_32bit[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_branch0__is_32bit[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_branch0__is_32bit[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_branch0__is_32bit[0:0] $3\fus_oper_i_alu_branch0__is_32bit[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + switch \fu_enable [2] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_branch0__is_32bit[0:0] \dec_BRANCH_BRANCH__is_32bit + case + assign $3\fus_oper_i_alu_branch0__is_32bit[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_branch0__is_32bit[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_branch0__is_32bit $0\fus_oper_i_alu_branch0__is_32bit[0:0] + end + attribute \src "libresoc.v:47278.3-47286.6" + process $proc$libresoc.v:47278$2823 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1667$next[0:0]$2824 $1\wr_pick_dly$1667$next[0:0]$2825 + attribute \src "libresoc.v:47279.5-47279.29" + switch \initial + attribute \src "libresoc.v:47279.9-47279.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1667$next[0:0]$2825 1'0 + case + assign $1\wr_pick_dly$1667$next[0:0]$2825 \wr_pick$1664 + end + sync always + update \wr_pick_dly$1667$next $0\wr_pick_dly$1667$next[0:0]$2824 + end + attribute \src "libresoc.v:47287.3-47295.6" + process $proc$libresoc.v:47287$2826 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1683$next[0:0]$2827 $1\wr_pick_dly$1683$next[0:0]$2828 + attribute \src "libresoc.v:47288.5-47288.29" + switch \initial + attribute \src "libresoc.v:47288.9-47288.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1683$next[0:0]$2828 1'0 + case + assign $1\wr_pick_dly$1683$next[0:0]$2828 \wr_pick$1680 + end + sync always + update \wr_pick_dly$1683$next $0\wr_pick_dly$1683$next[0:0]$2827 + end + attribute \src "libresoc.v:47296.3-47324.6" + process $proc$libresoc.v:47296$2829 + assign { } { } + assign { } { } + assign $0\fus_cu_issue_i$16[0:0]$2830 $1\fus_cu_issue_i$16[0:0]$2831 + attribute \src "libresoc.v:47297.5-47297.29" + switch \initial + attribute \src "libresoc.v:47297.9-47297.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_cu_issue_i$16[0:0]$2831 $2\fus_cu_issue_i$16[0:0]$2832 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_cu_issue_i$16[0:0]$2832 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_cu_issue_i$16[0:0]$2832 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_cu_issue_i$16[0:0]$2832 $3\fus_cu_issue_i$16[0:0]$2833 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + switch \fu_enable [2] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_cu_issue_i$16[0:0]$2833 \issue_i + case + assign $3\fus_cu_issue_i$16[0:0]$2833 1'0 + end + end + case + assign $1\fus_cu_issue_i$16[0:0]$2831 1'0 + end + sync always + update \fus_cu_issue_i$16 $0\fus_cu_issue_i$16[0:0]$2830 + end + attribute \src "libresoc.v:47325.3-47333.6" + process $proc$libresoc.v:47325$2834 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1699$next[0:0]$2835 $1\wr_pick_dly$1699$next[0:0]$2836 + attribute \src "libresoc.v:47326.5-47326.29" + switch \initial + attribute \src "libresoc.v:47326.9-47326.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1699$next[0:0]$2836 1'0 + case + assign $1\wr_pick_dly$1699$next[0:0]$2836 \wr_pick$1696 + end + sync always + update \wr_pick_dly$1699$next $0\wr_pick_dly$1699$next[0:0]$2835 + end + attribute \src "libresoc.v:47334.3-47362.6" + process $proc$libresoc.v:47334$2837 + assign { } { } + assign { } { } + assign $0\fus_cu_rdmaskn_i$18[2:0]$2838 $1\fus_cu_rdmaskn_i$18[2:0]$2839 + attribute \src "libresoc.v:47335.5-47335.29" + switch \initial + attribute \src "libresoc.v:47335.9-47335.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_cu_rdmaskn_i$18[2:0]$2839 $2\fus_cu_rdmaskn_i$18[2:0]$2840 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_cu_rdmaskn_i$18[2:0]$2840 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_cu_rdmaskn_i$18[2:0]$2840 3'000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_cu_rdmaskn_i$18[2:0]$2840 $3\fus_cu_rdmaskn_i$18[2:0]$2841 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + switch \fu_enable [2] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_cu_rdmaskn_i$18[2:0]$2841 \$247 + case + assign $3\fus_cu_rdmaskn_i$18[2:0]$2841 3'000 + end + end + case + assign $1\fus_cu_rdmaskn_i$18[2:0]$2839 3'000 + end + sync always + update \fus_cu_rdmaskn_i$18 $0\fus_cu_rdmaskn_i$18[2:0]$2838 + end + attribute \src "libresoc.v:47363.3-47371.6" + process $proc$libresoc.v:47363$2842 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1743$next[0:0]$2843 $1\wr_pick_dly$1743$next[0:0]$2844 + attribute \src "libresoc.v:47364.5-47364.29" + switch \initial + attribute \src "libresoc.v:47364.9-47364.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1743$next[0:0]$2844 1'0 + case + assign $1\wr_pick_dly$1743$next[0:0]$2844 \wr_pick$1740 + end + sync always + update \wr_pick_dly$1743$next $0\wr_pick_dly$1743$next[0:0]$2843 + end + attribute \src "libresoc.v:47372.3-47400.6" + process $proc$libresoc.v:47372$2845 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_trap0__insn_type[6:0] $1\fus_oper_i_alu_trap0__insn_type[6:0] + attribute \src "libresoc.v:47373.5-47373.29" + switch \initial + attribute \src "libresoc.v:47373.9-47373.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_trap0__insn_type[6:0] $2\fus_oper_i_alu_trap0__insn_type[6:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_trap0__insn_type[6:0] 7'0000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_trap0__insn_type[6:0] 7'0000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_trap0__insn_type[6:0] $3\fus_oper_i_alu_trap0__insn_type[6:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + switch \fu_enable [3] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_trap0__insn_type[6:0] \core_core_insn_type + case + assign $3\fus_oper_i_alu_trap0__insn_type[6:0] 7'0000000 + end + end + case + assign $1\fus_oper_i_alu_trap0__insn_type[6:0] 7'0000000 + end + sync always + update \fus_oper_i_alu_trap0__insn_type $0\fus_oper_i_alu_trap0__insn_type[6:0] + end + attribute \src "libresoc.v:47401.3-47409.6" + process $proc$libresoc.v:47401$2846 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1759$next[0:0]$2847 $1\wr_pick_dly$1759$next[0:0]$2848 + attribute \src "libresoc.v:47402.5-47402.29" + switch \initial + attribute \src "libresoc.v:47402.9-47402.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1759$next[0:0]$2848 1'0 + case + assign $1\wr_pick_dly$1759$next[0:0]$2848 \wr_pick$1756 + end + sync always + update \wr_pick_dly$1759$next $0\wr_pick_dly$1759$next[0:0]$2847 + end + attribute \src "libresoc.v:47410.3-47418.6" + process $proc$libresoc.v:47410$2849 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1783$next[0:0]$2850 $1\wr_pick_dly$1783$next[0:0]$2851 + attribute \src "libresoc.v:47411.5-47411.29" + switch \initial + attribute \src "libresoc.v:47411.9-47411.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1783$next[0:0]$2851 1'0 + case + assign $1\wr_pick_dly$1783$next[0:0]$2851 \wr_pick$1780 + end + sync always + update \wr_pick_dly$1783$next $0\wr_pick_dly$1783$next[0:0]$2850 + end + attribute \src "libresoc.v:47419.3-47447.6" + process $proc$libresoc.v:47419$2852 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_trap0__fn_unit[12:0] $1\fus_oper_i_alu_trap0__fn_unit[12:0] + attribute \src "libresoc.v:47420.5-47420.29" + switch \initial + attribute \src "libresoc.v:47420.9-47420.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_trap0__fn_unit[12:0] $2\fus_oper_i_alu_trap0__fn_unit[12:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_trap0__fn_unit[12:0] 13'0000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_trap0__fn_unit[12:0] 13'0000000000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_trap0__fn_unit[12:0] $3\fus_oper_i_alu_trap0__fn_unit[12:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + switch \fu_enable [3] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_trap0__fn_unit[12:0] \core_core_fn_unit + case + assign $3\fus_oper_i_alu_trap0__fn_unit[12:0] 13'0000000000000 + end + end + case + assign $1\fus_oper_i_alu_trap0__fn_unit[12:0] 13'0000000000000 + end + sync always + update \fus_oper_i_alu_trap0__fn_unit $0\fus_oper_i_alu_trap0__fn_unit[12:0] + end + attribute \src "libresoc.v:47448.3-47456.6" + process $proc$libresoc.v:47448$2853 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1803$next[0:0]$2854 $1\wr_pick_dly$1803$next[0:0]$2855 + attribute \src "libresoc.v:47449.5-47449.29" + switch \initial + attribute \src "libresoc.v:47449.9-47449.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1803$next[0:0]$2855 1'0 + case + assign $1\wr_pick_dly$1803$next[0:0]$2855 \wr_pick$1800 + end + sync always + update \wr_pick_dly$1803$next $0\wr_pick_dly$1803$next[0:0]$2854 + end + attribute \src "libresoc.v:47457.3-47485.6" + process $proc$libresoc.v:47457$2856 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_trap0__insn[31:0] $1\fus_oper_i_alu_trap0__insn[31:0] + attribute \src "libresoc.v:47458.5-47458.29" + switch \initial + attribute \src "libresoc.v:47458.9-47458.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_trap0__insn[31:0] $2\fus_oper_i_alu_trap0__insn[31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_trap0__insn[31:0] 0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_trap0__insn[31:0] 0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_trap0__insn[31:0] $3\fus_oper_i_alu_trap0__insn[31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + switch \fu_enable [3] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_trap0__insn[31:0] \core_core_insn + case + assign $3\fus_oper_i_alu_trap0__insn[31:0] 0 + end + end + case + assign $1\fus_oper_i_alu_trap0__insn[31:0] 0 + end + sync always + update \fus_oper_i_alu_trap0__insn $0\fus_oper_i_alu_trap0__insn[31:0] + end + attribute \src "libresoc.v:47486.3-47514.6" + process $proc$libresoc.v:47486$2857 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_trap0__msr[63:0] $1\fus_oper_i_alu_trap0__msr[63:0] + attribute \src "libresoc.v:47487.5-47487.29" + switch \initial + attribute \src "libresoc.v:47487.9-47487.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_trap0__msr[63:0] $2\fus_oper_i_alu_trap0__msr[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_trap0__msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_trap0__msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_trap0__msr[63:0] $3\fus_oper_i_alu_trap0__msr[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + switch \fu_enable [3] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_trap0__msr[63:0] \core_core_msr + case + assign $3\fus_oper_i_alu_trap0__msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + end + case + assign $1\fus_oper_i_alu_trap0__msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fus_oper_i_alu_trap0__msr $0\fus_oper_i_alu_trap0__msr[63:0] + end + attribute \src "libresoc.v:47515.3-47543.6" + process $proc$libresoc.v:47515$2858 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_trap0__cia[63:0] $1\fus_oper_i_alu_trap0__cia[63:0] + attribute \src "libresoc.v:47516.5-47516.29" + switch \initial + attribute \src "libresoc.v:47516.9-47516.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_trap0__cia[63:0] $2\fus_oper_i_alu_trap0__cia[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_trap0__cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_trap0__cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_trap0__cia[63:0] $3\fus_oper_i_alu_trap0__cia[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + switch \fu_enable [3] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_trap0__cia[63:0] \core_core_cia + case + assign $3\fus_oper_i_alu_trap0__cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + end + case + assign $1\fus_oper_i_alu_trap0__cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fus_oper_i_alu_trap0__cia $0\fus_oper_i_alu_trap0__cia[63:0] + end + attribute \src "libresoc.v:47544.3-47572.6" + process $proc$libresoc.v:47544$2859 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_trap0__is_32bit[0:0] $1\fus_oper_i_alu_trap0__is_32bit[0:0] + attribute \src "libresoc.v:47545.5-47545.29" + switch \initial + attribute \src "libresoc.v:47545.9-47545.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_trap0__is_32bit[0:0] $2\fus_oper_i_alu_trap0__is_32bit[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_trap0__is_32bit[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_trap0__is_32bit[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_trap0__is_32bit[0:0] $3\fus_oper_i_alu_trap0__is_32bit[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + switch \fu_enable [3] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_trap0__is_32bit[0:0] \core_core_is_32bit + case + assign $3\fus_oper_i_alu_trap0__is_32bit[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_trap0__is_32bit[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_trap0__is_32bit $0\fus_oper_i_alu_trap0__is_32bit[0:0] + end + attribute \src "libresoc.v:47573.3-47601.6" + process $proc$libresoc.v:47573$2860 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_trap0__traptype[7:0] $1\fus_oper_i_alu_trap0__traptype[7:0] + attribute \src "libresoc.v:47574.5-47574.29" + switch \initial + attribute \src "libresoc.v:47574.9-47574.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_trap0__traptype[7:0] $2\fus_oper_i_alu_trap0__traptype[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_trap0__traptype[7:0] 8'00000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_trap0__traptype[7:0] 8'00000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_trap0__traptype[7:0] $3\fus_oper_i_alu_trap0__traptype[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + switch \fu_enable [3] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_trap0__traptype[7:0] \core_core_traptype + case + assign $3\fus_oper_i_alu_trap0__traptype[7:0] 8'00000000 + end + end + case + assign $1\fus_oper_i_alu_trap0__traptype[7:0] 8'00000000 + end + sync always + update \fus_oper_i_alu_trap0__traptype $0\fus_oper_i_alu_trap0__traptype[7:0] + end + attribute \src "libresoc.v:47602.3-47630.6" + process $proc$libresoc.v:47602$2861 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_trap0__trapaddr[12:0] $1\fus_oper_i_alu_trap0__trapaddr[12:0] + attribute \src "libresoc.v:47603.5-47603.29" + switch \initial + attribute \src "libresoc.v:47603.9-47603.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_trap0__trapaddr[12:0] $2\fus_oper_i_alu_trap0__trapaddr[12:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_trap0__trapaddr[12:0] 13'0000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_trap0__trapaddr[12:0] 13'0000000000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_trap0__trapaddr[12:0] $3\fus_oper_i_alu_trap0__trapaddr[12:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + switch \fu_enable [3] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_trap0__trapaddr[12:0] \core_core_trapaddr + case + assign $3\fus_oper_i_alu_trap0__trapaddr[12:0] 13'0000000000000 + end + end + case + assign $1\fus_oper_i_alu_trap0__trapaddr[12:0] 13'0000000000000 + end + sync always + update \fus_oper_i_alu_trap0__trapaddr $0\fus_oper_i_alu_trap0__trapaddr[12:0] + end + attribute \src "libresoc.v:47631.3-47659.6" + process $proc$libresoc.v:47631$2862 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_trap0__ldst_exc[7:0] $1\fus_oper_i_alu_trap0__ldst_exc[7:0] + attribute \src "libresoc.v:47632.5-47632.29" + switch \initial + attribute \src "libresoc.v:47632.9-47632.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_trap0__ldst_exc[7:0] $2\fus_oper_i_alu_trap0__ldst_exc[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_trap0__ldst_exc[7:0] 8'00000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_trap0__ldst_exc[7:0] 8'00000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_trap0__ldst_exc[7:0] $3\fus_oper_i_alu_trap0__ldst_exc[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + switch \fu_enable [3] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_trap0__ldst_exc[7:0] { \core_core_exc_$signal$9 \core_core_exc_$signal$8 \core_core_exc_$signal$7 \core_core_exc_$signal$6 \core_core_exc_$signal$5 \core_core_exc_$signal$4 \core_core_exc_$signal$3 \core_core_exc_$signal } + case + assign $3\fus_oper_i_alu_trap0__ldst_exc[7:0] 8'00000000 + end + end + case + assign $1\fus_oper_i_alu_trap0__ldst_exc[7:0] 8'00000000 + end + sync always + update \fus_oper_i_alu_trap0__ldst_exc $0\fus_oper_i_alu_trap0__ldst_exc[7:0] + end + attribute \src "libresoc.v:47660.3-47688.6" + process $proc$libresoc.v:47660$2863 + assign { } { } + assign { } { } + assign $0\fus_cu_issue_i$19[0:0]$2864 $1\fus_cu_issue_i$19[0:0]$2865 + attribute \src "libresoc.v:47661.5-47661.29" + switch \initial + attribute \src "libresoc.v:47661.9-47661.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_cu_issue_i$19[0:0]$2865 $2\fus_cu_issue_i$19[0:0]$2866 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_cu_issue_i$19[0:0]$2866 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_cu_issue_i$19[0:0]$2866 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_cu_issue_i$19[0:0]$2866 $3\fus_cu_issue_i$19[0:0]$2867 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + switch \fu_enable [3] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_cu_issue_i$19[0:0]$2867 \issue_i + case + assign $3\fus_cu_issue_i$19[0:0]$2867 1'0 + end + end + case + assign $1\fus_cu_issue_i$19[0:0]$2865 1'0 + end + sync always + update \fus_cu_issue_i$19 $0\fus_cu_issue_i$19[0:0]$2864 + end + attribute \src "libresoc.v:47689.3-47717.6" + process $proc$libresoc.v:47689$2868 + assign { } { } + assign { } { } + assign $0\fus_cu_rdmaskn_i$21[3:0]$2869 $1\fus_cu_rdmaskn_i$21[3:0]$2870 + attribute \src "libresoc.v:47690.5-47690.29" + switch \initial + attribute \src "libresoc.v:47690.9-47690.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_cu_rdmaskn_i$21[3:0]$2870 $2\fus_cu_rdmaskn_i$21[3:0]$2871 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_cu_rdmaskn_i$21[3:0]$2871 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_cu_rdmaskn_i$21[3:0]$2871 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_cu_rdmaskn_i$21[3:0]$2871 $3\fus_cu_rdmaskn_i$21[3:0]$2872 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + switch \fu_enable [3] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_cu_rdmaskn_i$21[3:0]$2872 \$249 + case + assign $3\fus_cu_rdmaskn_i$21[3:0]$2872 4'0000 + end + end + case + assign $1\fus_cu_rdmaskn_i$21[3:0]$2870 4'0000 + end + sync always + update \fus_cu_rdmaskn_i$21 $0\fus_cu_rdmaskn_i$21[3:0]$2869 + end + attribute \src "libresoc.v:47718.3-47746.6" + process $proc$libresoc.v:47718$2873 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_logical0__insn_type[6:0] $1\fus_oper_i_alu_logical0__insn_type[6:0] + attribute \src "libresoc.v:47719.5-47719.29" + switch \initial + attribute \src "libresoc.v:47719.9-47719.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_logical0__insn_type[6:0] $2\fus_oper_i_alu_logical0__insn_type[6:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_logical0__insn_type[6:0] 7'0000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_logical0__insn_type[6:0] 7'0000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_logical0__insn_type[6:0] $3\fus_oper_i_alu_logical0__insn_type[6:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + switch \fu_enable [4] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_logical0__insn_type[6:0] \dec_LOGICAL_LOGICAL__insn_type + case + assign $3\fus_oper_i_alu_logical0__insn_type[6:0] 7'0000000 + end + end + case + assign $1\fus_oper_i_alu_logical0__insn_type[6:0] 7'0000000 + end + sync always + update \fus_oper_i_alu_logical0__insn_type $0\fus_oper_i_alu_logical0__insn_type[6:0] + end + attribute \src "libresoc.v:47747.3-47775.6" + process $proc$libresoc.v:47747$2874 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_logical0__fn_unit[12:0] $1\fus_oper_i_alu_logical0__fn_unit[12:0] + attribute \src "libresoc.v:47748.5-47748.29" + switch \initial + attribute \src "libresoc.v:47748.9-47748.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_logical0__fn_unit[12:0] $2\fus_oper_i_alu_logical0__fn_unit[12:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_logical0__fn_unit[12:0] 13'0000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_logical0__fn_unit[12:0] 13'0000000000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_logical0__fn_unit[12:0] $3\fus_oper_i_alu_logical0__fn_unit[12:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + switch \fu_enable [4] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_logical0__fn_unit[12:0] \dec_LOGICAL_LOGICAL__fn_unit + case + assign $3\fus_oper_i_alu_logical0__fn_unit[12:0] 13'0000000000000 + end + end + case + assign $1\fus_oper_i_alu_logical0__fn_unit[12:0] 13'0000000000000 + end + sync always + update \fus_oper_i_alu_logical0__fn_unit $0\fus_oper_i_alu_logical0__fn_unit[12:0] + end + attribute \src "libresoc.v:47776.3-47805.6" + process $proc$libresoc.v:47776$2875 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_logical0__imm_data__data[63:0] $1\fus_oper_i_alu_logical0__imm_data__data[63:0] + assign $0\fus_oper_i_alu_logical0__imm_data__ok[0:0] $1\fus_oper_i_alu_logical0__imm_data__ok[0:0] + attribute \src "libresoc.v:47777.5-47777.29" + switch \initial + attribute \src "libresoc.v:47777.9-47777.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $1\fus_oper_i_alu_logical0__imm_data__data[63:0] $2\fus_oper_i_alu_logical0__imm_data__data[63:0] + assign $1\fus_oper_i_alu_logical0__imm_data__ok[0:0] $2\fus_oper_i_alu_logical0__imm_data__ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_logical0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\fus_oper_i_alu_logical0__imm_data__ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_logical0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\fus_oper_i_alu_logical0__imm_data__ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign $2\fus_oper_i_alu_logical0__imm_data__data[63:0] $3\fus_oper_i_alu_logical0__imm_data__data[63:0] + assign $2\fus_oper_i_alu_logical0__imm_data__ok[0:0] $3\fus_oper_i_alu_logical0__imm_data__ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + switch \fu_enable [4] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $3\fus_oper_i_alu_logical0__imm_data__ok[0:0] $3\fus_oper_i_alu_logical0__imm_data__data[63:0] } { \dec_LOGICAL_LOGICAL__imm_data__ok \dec_LOGICAL_LOGICAL__imm_data__data } + case + assign $3\fus_oper_i_alu_logical0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\fus_oper_i_alu_logical0__imm_data__ok[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_logical0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fus_oper_i_alu_logical0__imm_data__ok[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_logical0__imm_data__data $0\fus_oper_i_alu_logical0__imm_data__data[63:0] + update \fus_oper_i_alu_logical0__imm_data__ok $0\fus_oper_i_alu_logical0__imm_data__ok[0:0] + end + attribute \src "libresoc.v:47806.3-47835.6" + process $proc$libresoc.v:47806$2876 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_logical0__rc__ok[0:0] $1\fus_oper_i_alu_logical0__rc__ok[0:0] + assign $0\fus_oper_i_alu_logical0__rc__rc[0:0] $1\fus_oper_i_alu_logical0__rc__rc[0:0] + attribute \src "libresoc.v:47807.5-47807.29" + switch \initial + attribute \src "libresoc.v:47807.9-47807.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $1\fus_oper_i_alu_logical0__rc__ok[0:0] $2\fus_oper_i_alu_logical0__rc__ok[0:0] + assign $1\fus_oper_i_alu_logical0__rc__rc[0:0] $2\fus_oper_i_alu_logical0__rc__rc[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_logical0__rc__ok[0:0] 1'0 + assign $2\fus_oper_i_alu_logical0__rc__rc[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_logical0__rc__ok[0:0] 1'0 + assign $2\fus_oper_i_alu_logical0__rc__rc[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign $2\fus_oper_i_alu_logical0__rc__ok[0:0] $3\fus_oper_i_alu_logical0__rc__ok[0:0] + assign $2\fus_oper_i_alu_logical0__rc__rc[0:0] $3\fus_oper_i_alu_logical0__rc__rc[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + switch \fu_enable [4] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $3\fus_oper_i_alu_logical0__rc__ok[0:0] $3\fus_oper_i_alu_logical0__rc__rc[0:0] } { \dec_LOGICAL_LOGICAL__rc__ok \dec_LOGICAL_LOGICAL__rc__rc } + case + assign $3\fus_oper_i_alu_logical0__rc__ok[0:0] 1'0 + assign $3\fus_oper_i_alu_logical0__rc__rc[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_logical0__rc__ok[0:0] 1'0 + assign $1\fus_oper_i_alu_logical0__rc__rc[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_logical0__rc__ok $0\fus_oper_i_alu_logical0__rc__ok[0:0] + update \fus_oper_i_alu_logical0__rc__rc $0\fus_oper_i_alu_logical0__rc__rc[0:0] + end + attribute \src "libresoc.v:47836.3-47865.6" + process $proc$libresoc.v:47836$2877 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_logical0__oe__oe[0:0] $1\fus_oper_i_alu_logical0__oe__oe[0:0] + assign $0\fus_oper_i_alu_logical0__oe__ok[0:0] $1\fus_oper_i_alu_logical0__oe__ok[0:0] + attribute \src "libresoc.v:47837.5-47837.29" + switch \initial + attribute \src "libresoc.v:47837.9-47837.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $1\fus_oper_i_alu_logical0__oe__oe[0:0] $2\fus_oper_i_alu_logical0__oe__oe[0:0] + assign $1\fus_oper_i_alu_logical0__oe__ok[0:0] $2\fus_oper_i_alu_logical0__oe__ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_logical0__oe__oe[0:0] 1'0 + assign $2\fus_oper_i_alu_logical0__oe__ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_logical0__oe__oe[0:0] 1'0 + assign $2\fus_oper_i_alu_logical0__oe__ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign $2\fus_oper_i_alu_logical0__oe__oe[0:0] $3\fus_oper_i_alu_logical0__oe__oe[0:0] + assign $2\fus_oper_i_alu_logical0__oe__ok[0:0] $3\fus_oper_i_alu_logical0__oe__ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + switch \fu_enable [4] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $3\fus_oper_i_alu_logical0__oe__ok[0:0] $3\fus_oper_i_alu_logical0__oe__oe[0:0] } { \dec_LOGICAL_LOGICAL__oe__ok \dec_LOGICAL_LOGICAL__oe__oe } + case + assign $3\fus_oper_i_alu_logical0__oe__oe[0:0] 1'0 + assign $3\fus_oper_i_alu_logical0__oe__ok[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_logical0__oe__oe[0:0] 1'0 + assign $1\fus_oper_i_alu_logical0__oe__ok[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_logical0__oe__oe $0\fus_oper_i_alu_logical0__oe__oe[0:0] + update \fus_oper_i_alu_logical0__oe__ok $0\fus_oper_i_alu_logical0__oe__ok[0:0] + end + attribute \src "libresoc.v:47866.3-47894.6" + process $proc$libresoc.v:47866$2878 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_logical0__invert_in[0:0] $1\fus_oper_i_alu_logical0__invert_in[0:0] + attribute \src "libresoc.v:47867.5-47867.29" + switch \initial + attribute \src "libresoc.v:47867.9-47867.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_logical0__invert_in[0:0] $2\fus_oper_i_alu_logical0__invert_in[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_logical0__invert_in[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_logical0__invert_in[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_logical0__invert_in[0:0] $3\fus_oper_i_alu_logical0__invert_in[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + switch \fu_enable [4] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_logical0__invert_in[0:0] \dec_LOGICAL_LOGICAL__invert_in + case + assign $3\fus_oper_i_alu_logical0__invert_in[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_logical0__invert_in[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_logical0__invert_in $0\fus_oper_i_alu_logical0__invert_in[0:0] + end + attribute \src "libresoc.v:47895.3-47923.6" + process $proc$libresoc.v:47895$2879 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_logical0__zero_a[0:0] $1\fus_oper_i_alu_logical0__zero_a[0:0] + attribute \src "libresoc.v:47896.5-47896.29" + switch \initial + attribute \src "libresoc.v:47896.9-47896.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_logical0__zero_a[0:0] $2\fus_oper_i_alu_logical0__zero_a[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_logical0__zero_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_logical0__zero_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_logical0__zero_a[0:0] $3\fus_oper_i_alu_logical0__zero_a[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + switch \fu_enable [4] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_logical0__zero_a[0:0] \dec_LOGICAL_LOGICAL__zero_a + case + assign $3\fus_oper_i_alu_logical0__zero_a[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_logical0__zero_a[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_logical0__zero_a $0\fus_oper_i_alu_logical0__zero_a[0:0] + end + attribute \src "libresoc.v:47924.3-47952.6" + process $proc$libresoc.v:47924$2880 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_logical0__input_carry[1:0] $1\fus_oper_i_alu_logical0__input_carry[1:0] + attribute \src "libresoc.v:47925.5-47925.29" + switch \initial + attribute \src "libresoc.v:47925.9-47925.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_logical0__input_carry[1:0] $2\fus_oper_i_alu_logical0__input_carry[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_logical0__input_carry[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_logical0__input_carry[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_logical0__input_carry[1:0] $3\fus_oper_i_alu_logical0__input_carry[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + switch \fu_enable [4] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_logical0__input_carry[1:0] \dec_LOGICAL_LOGICAL__input_carry + case + assign $3\fus_oper_i_alu_logical0__input_carry[1:0] 2'00 + end + end + case + assign $1\fus_oper_i_alu_logical0__input_carry[1:0] 2'00 + end + sync always + update \fus_oper_i_alu_logical0__input_carry $0\fus_oper_i_alu_logical0__input_carry[1:0] + end + attribute \src "libresoc.v:47953.3-47981.6" + process $proc$libresoc.v:47953$2881 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_logical0__invert_out[0:0] $1\fus_oper_i_alu_logical0__invert_out[0:0] + attribute \src "libresoc.v:47954.5-47954.29" + switch \initial + attribute \src "libresoc.v:47954.9-47954.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_logical0__invert_out[0:0] $2\fus_oper_i_alu_logical0__invert_out[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_logical0__invert_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_logical0__invert_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_logical0__invert_out[0:0] $3\fus_oper_i_alu_logical0__invert_out[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + switch \fu_enable [4] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_logical0__invert_out[0:0] \dec_LOGICAL_LOGICAL__invert_out + case + assign $3\fus_oper_i_alu_logical0__invert_out[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_logical0__invert_out[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_logical0__invert_out $0\fus_oper_i_alu_logical0__invert_out[0:0] + end + attribute \src "libresoc.v:47982.3-48010.6" + process $proc$libresoc.v:47982$2882 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_logical0__write_cr0[0:0] $1\fus_oper_i_alu_logical0__write_cr0[0:0] + attribute \src "libresoc.v:47983.5-47983.29" + switch \initial + attribute \src "libresoc.v:47983.9-47983.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_logical0__write_cr0[0:0] $2\fus_oper_i_alu_logical0__write_cr0[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_logical0__write_cr0[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_logical0__write_cr0[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_logical0__write_cr0[0:0] $3\fus_oper_i_alu_logical0__write_cr0[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + switch \fu_enable [4] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_logical0__write_cr0[0:0] \dec_LOGICAL_LOGICAL__write_cr0 + case + assign $3\fus_oper_i_alu_logical0__write_cr0[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_logical0__write_cr0[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_logical0__write_cr0 $0\fus_oper_i_alu_logical0__write_cr0[0:0] + end + attribute \src "libresoc.v:48011.3-48039.6" + process $proc$libresoc.v:48011$2883 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_logical0__output_carry[0:0] $1\fus_oper_i_alu_logical0__output_carry[0:0] + attribute \src "libresoc.v:48012.5-48012.29" + switch \initial + attribute \src "libresoc.v:48012.9-48012.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_logical0__output_carry[0:0] $2\fus_oper_i_alu_logical0__output_carry[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_logical0__output_carry[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_logical0__output_carry[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_logical0__output_carry[0:0] $3\fus_oper_i_alu_logical0__output_carry[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + switch \fu_enable [4] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_logical0__output_carry[0:0] \dec_LOGICAL_LOGICAL__output_carry + case + assign $3\fus_oper_i_alu_logical0__output_carry[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_logical0__output_carry[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_logical0__output_carry $0\fus_oper_i_alu_logical0__output_carry[0:0] + end + attribute \src "libresoc.v:48040.3-48068.6" + process $proc$libresoc.v:48040$2884 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_logical0__is_32bit[0:0] $1\fus_oper_i_alu_logical0__is_32bit[0:0] + attribute \src "libresoc.v:48041.5-48041.29" + switch \initial + attribute \src "libresoc.v:48041.9-48041.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_logical0__is_32bit[0:0] $2\fus_oper_i_alu_logical0__is_32bit[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_logical0__is_32bit[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_logical0__is_32bit[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_logical0__is_32bit[0:0] $3\fus_oper_i_alu_logical0__is_32bit[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + switch \fu_enable [4] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_logical0__is_32bit[0:0] \dec_LOGICAL_LOGICAL__is_32bit + case + assign $3\fus_oper_i_alu_logical0__is_32bit[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_logical0__is_32bit[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_logical0__is_32bit $0\fus_oper_i_alu_logical0__is_32bit[0:0] + end + attribute \src "libresoc.v:48069.3-48097.6" + process $proc$libresoc.v:48069$2885 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_logical0__is_signed[0:0] $1\fus_oper_i_alu_logical0__is_signed[0:0] + attribute \src "libresoc.v:48070.5-48070.29" + switch \initial + attribute \src "libresoc.v:48070.9-48070.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_logical0__is_signed[0:0] $2\fus_oper_i_alu_logical0__is_signed[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_logical0__is_signed[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_logical0__is_signed[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_logical0__is_signed[0:0] $3\fus_oper_i_alu_logical0__is_signed[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + switch \fu_enable [4] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_logical0__is_signed[0:0] \dec_LOGICAL_LOGICAL__is_signed + case + assign $3\fus_oper_i_alu_logical0__is_signed[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_logical0__is_signed[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_logical0__is_signed $0\fus_oper_i_alu_logical0__is_signed[0:0] + end + attribute \src "libresoc.v:48098.3-48126.6" + process $proc$libresoc.v:48098$2886 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_logical0__data_len[3:0] $1\fus_oper_i_alu_logical0__data_len[3:0] + attribute \src "libresoc.v:48099.5-48099.29" + switch \initial + attribute \src "libresoc.v:48099.9-48099.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_logical0__data_len[3:0] $2\fus_oper_i_alu_logical0__data_len[3:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_logical0__data_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_logical0__data_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_logical0__data_len[3:0] $3\fus_oper_i_alu_logical0__data_len[3:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + switch \fu_enable [4] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_logical0__data_len[3:0] \dec_LOGICAL_LOGICAL__data_len + case + assign $3\fus_oper_i_alu_logical0__data_len[3:0] 4'0000 + end + end + case + assign $1\fus_oper_i_alu_logical0__data_len[3:0] 4'0000 + end + sync always + update \fus_oper_i_alu_logical0__data_len $0\fus_oper_i_alu_logical0__data_len[3:0] + end + attribute \src "libresoc.v:48127.3-48155.6" + process $proc$libresoc.v:48127$2887 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_logical0__insn[31:0] $1\fus_oper_i_alu_logical0__insn[31:0] + attribute \src "libresoc.v:48128.5-48128.29" + switch \initial + attribute \src "libresoc.v:48128.9-48128.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_logical0__insn[31:0] $2\fus_oper_i_alu_logical0__insn[31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_logical0__insn[31:0] 0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_logical0__insn[31:0] 0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_logical0__insn[31:0] $3\fus_oper_i_alu_logical0__insn[31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + switch \fu_enable [4] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_logical0__insn[31:0] \dec_LOGICAL_LOGICAL__insn + case + assign $3\fus_oper_i_alu_logical0__insn[31:0] 0 + end + end + case + assign $1\fus_oper_i_alu_logical0__insn[31:0] 0 + end + sync always + update \fus_oper_i_alu_logical0__insn $0\fus_oper_i_alu_logical0__insn[31:0] + end + attribute \src "libresoc.v:48156.3-48184.6" + process $proc$libresoc.v:48156$2888 + assign { } { } + assign { } { } + assign $0\fus_cu_issue_i$22[0:0]$2889 $1\fus_cu_issue_i$22[0:0]$2890 + attribute \src "libresoc.v:48157.5-48157.29" + switch \initial + attribute \src "libresoc.v:48157.9-48157.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_cu_issue_i$22[0:0]$2890 $2\fus_cu_issue_i$22[0:0]$2891 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_cu_issue_i$22[0:0]$2891 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_cu_issue_i$22[0:0]$2891 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_cu_issue_i$22[0:0]$2891 $3\fus_cu_issue_i$22[0:0]$2892 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + switch \fu_enable [4] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_cu_issue_i$22[0:0]$2892 \issue_i + case + assign $3\fus_cu_issue_i$22[0:0]$2892 1'0 + end + end + case + assign $1\fus_cu_issue_i$22[0:0]$2890 1'0 + end + sync always + update \fus_cu_issue_i$22 $0\fus_cu_issue_i$22[0:0]$2889 + end + attribute \src "libresoc.v:48185.3-48213.6" + process $proc$libresoc.v:48185$2893 + assign { } { } + assign { } { } + assign $0\fus_cu_rdmaskn_i$24[2:0]$2894 $1\fus_cu_rdmaskn_i$24[2:0]$2895 + attribute \src "libresoc.v:48186.5-48186.29" + switch \initial + attribute \src "libresoc.v:48186.9-48186.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_cu_rdmaskn_i$24[2:0]$2895 $2\fus_cu_rdmaskn_i$24[2:0]$2896 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_cu_rdmaskn_i$24[2:0]$2896 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_cu_rdmaskn_i$24[2:0]$2896 3'000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_cu_rdmaskn_i$24[2:0]$2896 $3\fus_cu_rdmaskn_i$24[2:0]$2897 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + switch \fu_enable [4] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_cu_rdmaskn_i$24[2:0]$2897 \$251 + case + assign $3\fus_cu_rdmaskn_i$24[2:0]$2897 3'000 + end + end + case + assign $1\fus_cu_rdmaskn_i$24[2:0]$2895 3'000 + end + sync always + update \fus_cu_rdmaskn_i$24 $0\fus_cu_rdmaskn_i$24[2:0]$2894 + end + attribute \src "libresoc.v:48214.3-48242.6" + process $proc$libresoc.v:48214$2898 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_spr0__insn_type[6:0] $1\fus_oper_i_alu_spr0__insn_type[6:0] + attribute \src "libresoc.v:48215.5-48215.29" + switch \initial + attribute \src "libresoc.v:48215.9-48215.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_spr0__insn_type[6:0] $2\fus_oper_i_alu_spr0__insn_type[6:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_spr0__insn_type[6:0] 7'0000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_spr0__insn_type[6:0] 7'0000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_spr0__insn_type[6:0] $3\fus_oper_i_alu_spr0__insn_type[6:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + switch \fu_enable [5] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_spr0__insn_type[6:0] \dec_SPR_SPR__insn_type + case + assign $3\fus_oper_i_alu_spr0__insn_type[6:0] 7'0000000 + end + end + case + assign $1\fus_oper_i_alu_spr0__insn_type[6:0] 7'0000000 + end + sync always + update \fus_oper_i_alu_spr0__insn_type $0\fus_oper_i_alu_spr0__insn_type[6:0] + end + attribute \src "libresoc.v:48243.3-48271.6" + process $proc$libresoc.v:48243$2899 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_spr0__fn_unit[12:0] $1\fus_oper_i_alu_spr0__fn_unit[12:0] + attribute \src "libresoc.v:48244.5-48244.29" + switch \initial + attribute \src "libresoc.v:48244.9-48244.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" + switch \ivalid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_spr0__fn_unit[12:0] $2\fus_oper_i_alu_spr0__fn_unit[12:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" + switch \core_core_insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_spr0__fn_unit[12:0] 13'0000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_spr0__fn_unit[12:0] 13'0000000000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_spr0__fn_unit[12:0] $3\fus_oper_i_alu_spr0__fn_unit[12:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:205" + switch \fu_enable [5] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_spr0__fn_unit[12:0] \dec_SPR_SPR__fn_unit + case + assign $3\fus_oper_i_alu_spr0__fn_unit[12:0] 13'0000000000000 + end + end + case + assign $1\fus_oper_i_alu_spr0__fn_unit[12:0] 13'0000000000000 + end + sync always + update \fus_oper_i_alu_spr0__fn_unit $0\fus_oper_i_alu_spr0__fn_unit[12:0] + end + connect \$1000 $and$libresoc.v:41809$1506_Y + connect \$1003 $and$libresoc.v:41810$1507_Y + connect \$1007 $not$libresoc.v:41811$1508_Y + connect \$1009 $and$libresoc.v:41812$1509_Y + connect \$1016 $and$libresoc.v:41813$1510_Y + connect \$1019 $ternary$libresoc.v:41814$1511_Y + connect \$1021 $and$libresoc.v:41815$1512_Y + connect \$1024 $and$libresoc.v:41816$1513_Y + connect \$1028 $not$libresoc.v:41817$1514_Y + connect \$1030 $and$libresoc.v:41818$1515_Y + connect \$1034 $and$libresoc.v:41819$1516_Y + connect \$1037 $ternary$libresoc.v:41820$1517_Y + connect \$1039 $and$libresoc.v:41821$1518_Y + connect \$1042 $and$libresoc.v:41822$1519_Y + connect \$1046 $not$libresoc.v:41823$1520_Y + connect \$1048 $and$libresoc.v:41824$1521_Y + connect \$1056 $and$libresoc.v:41825$1522_Y + connect \$1059 $ternary$libresoc.v:41826$1523_Y + connect \$1061 $and$libresoc.v:41827$1524_Y + connect \$1064 $and$libresoc.v:41828$1525_Y + connect \$1068 $not$libresoc.v:41829$1526_Y + connect \$1070 $and$libresoc.v:41830$1527_Y + connect \$1076 $and$libresoc.v:41831$1528_Y + connect \$1079 $ternary$libresoc.v:41832$1529_Y + connect \$1081 $and$libresoc.v:41833$1530_Y + connect \$1084 $and$libresoc.v:41834$1531_Y + connect \$1088 $not$libresoc.v:41835$1532_Y + connect \$1090 $and$libresoc.v:41836$1533_Y + connect \$1096 $and$libresoc.v:41837$1534_Y + connect \$1099 $ternary$libresoc.v:41838$1535_Y + connect \$1101 $and$libresoc.v:41839$1536_Y + connect \$1104 $and$libresoc.v:41840$1537_Y + connect \$1108 $not$libresoc.v:41841$1538_Y + connect \$1110 $and$libresoc.v:41842$1539_Y + connect \$1115 $and$libresoc.v:41843$1540_Y + connect \$1118 $ternary$libresoc.v:41844$1541_Y + connect \$1120 $and$libresoc.v:41845$1542_Y + connect \$1123 $and$libresoc.v:41846$1543_Y + connect \$1127 $not$libresoc.v:41847$1544_Y + connect \$1129 $and$libresoc.v:41848$1545_Y + connect \$1133 $and$libresoc.v:41849$1546_Y + connect \$1136 $ternary$libresoc.v:41850$1547_Y + connect \$1138 $and$libresoc.v:41851$1548_Y + connect \$1141 $and$libresoc.v:41852$1549_Y + connect \$1144 $not$libresoc.v:41853$1550_Y + connect \$1146 $and$libresoc.v:41854$1551_Y + connect \$1149 $and$libresoc.v:41855$1552_Y + connect \$1152 $ternary$libresoc.v:41856$1553_Y + connect \$1155 $or$libresoc.v:41857$1554_Y + connect \$1157 $or$libresoc.v:41858$1555_Y + connect \$1159 $or$libresoc.v:41859$1556_Y + connect \$1161 $or$libresoc.v:41860$1557_Y + connect \$1163 $or$libresoc.v:41861$1558_Y + connect \$1165 $or$libresoc.v:41862$1559_Y + connect \$1167 $or$libresoc.v:41863$1560_Y + connect \$1169 $or$libresoc.v:41864$1561_Y + connect \$1171 $or$libresoc.v:41865$1562_Y + connect \$1174 $or$libresoc.v:41866$1563_Y + connect \$1176 $or$libresoc.v:41867$1564_Y + connect \$1178 $or$libresoc.v:41868$1565_Y + connect \$1180 $or$libresoc.v:41869$1566_Y + connect \$1182 $or$libresoc.v:41870$1567_Y + connect \$1184 $or$libresoc.v:41871$1568_Y + connect \$1186 $or$libresoc.v:41872$1569_Y + connect \$1188 $or$libresoc.v:41873$1570_Y + connect \$1190 $or$libresoc.v:41874$1571_Y + connect \$1192 $or$libresoc.v:41875$1572_Y + connect \$1194 $or$libresoc.v:41876$1573_Y + connect \$1196 $or$libresoc.v:41877$1574_Y + connect \$1198 $or$libresoc.v:41878$1575_Y + connect \$1200 $or$libresoc.v:41879$1576_Y + connect \$1202 $or$libresoc.v:41880$1577_Y + connect \$1204 $or$libresoc.v:41881$1578_Y + connect \$1206 $or$libresoc.v:41882$1579_Y + connect \$1208 $or$libresoc.v:41883$1580_Y + connect \$1210 $and$libresoc.v:41884$1581_Y + connect \$1212 $and$libresoc.v:41885$1582_Y + connect \$1215 $and$libresoc.v:41886$1583_Y + connect \$1218 $not$libresoc.v:41887$1584_Y + connect \$1220 $and$libresoc.v:41888$1585_Y + connect \$1223 $and$libresoc.v:41889$1586_Y + connect \$1226 $ternary$libresoc.v:41890$1587_Y + connect \$1228 $and$libresoc.v:41891$1588_Y + connect \$1230 $and$libresoc.v:41892$1589_Y + connect \$1232 $and$libresoc.v:41893$1590_Y + connect \$1234 $and$libresoc.v:41894$1591_Y + connect \$1236 $and$libresoc.v:41895$1592_Y + connect \$1238 $and$libresoc.v:41896$1593_Y + connect \$1240 $and$libresoc.v:41897$1594_Y + connect \$1243 $and$libresoc.v:41898$1595_Y + connect \$1246 $not$libresoc.v:41899$1596_Y + connect \$1248 $and$libresoc.v:41900$1597_Y + connect \$1251 $and$libresoc.v:41901$1598_Y + connect \$1254 $sub$libresoc.v:41902$1599_Y + connect \$1256 $sshl$libresoc.v:41903$1600_Y + connect \$1258 $ternary$libresoc.v:41904$1601_Y + connect \$1260 $and$libresoc.v:41905$1602_Y + connect \$1263 $and$libresoc.v:41906$1603_Y + connect \$1266 $not$libresoc.v:41907$1604_Y + connect \$1268 $and$libresoc.v:41908$1605_Y + connect \$1271 $and$libresoc.v:41909$1606_Y + connect \$1274 $sub$libresoc.v:41910$1607_Y + connect \$1276 $sshl$libresoc.v:41911$1608_Y + connect \$1278 $ternary$libresoc.v:41912$1609_Y + connect \$1280 $and$libresoc.v:41913$1610_Y + connect \$1283 $and$libresoc.v:41914$1611_Y + connect \$1286 $not$libresoc.v:41915$1612_Y + connect \$1288 $and$libresoc.v:41916$1613_Y + connect \$1291 $and$libresoc.v:41917$1614_Y + connect \$1294 $sub$libresoc.v:41918$1615_Y + connect \$1296 $sshl$libresoc.v:41919$1616_Y + connect \$1298 $ternary$libresoc.v:41920$1617_Y + connect \$1300 $and$libresoc.v:41921$1618_Y + connect \$1303 $and$libresoc.v:41922$1619_Y + connect \$1306 $not$libresoc.v:41923$1620_Y + connect \$1308 $and$libresoc.v:41924$1621_Y + connect \$1311 $and$libresoc.v:41925$1622_Y + connect \$1314 $sub$libresoc.v:41926$1623_Y + connect \$1316 $sshl$libresoc.v:41927$1624_Y + connect \$1318 $ternary$libresoc.v:41928$1625_Y + connect \$1320 $and$libresoc.v:41929$1626_Y + connect \$1323 $and$libresoc.v:41930$1627_Y + connect \$1326 $not$libresoc.v:41931$1628_Y + connect \$1328 $and$libresoc.v:41932$1629_Y + connect \$1331 $and$libresoc.v:41933$1630_Y + connect \$1334 $sub$libresoc.v:41934$1631_Y + connect \$1336 $sshl$libresoc.v:41935$1632_Y + connect \$1338 $ternary$libresoc.v:41936$1633_Y + connect \$1340 $and$libresoc.v:41937$1634_Y + connect \$1343 $and$libresoc.v:41938$1635_Y + connect \$1346 $not$libresoc.v:41939$1636_Y + connect \$1348 $and$libresoc.v:41940$1637_Y + connect \$1351 $and$libresoc.v:41941$1638_Y + connect \$1354 $sub$libresoc.v:41942$1639_Y + connect \$1356 $sshl$libresoc.v:41943$1640_Y + connect \$1358 $ternary$libresoc.v:41944$1641_Y + connect \$1360 $or$libresoc.v:41945$1642_Y + connect \$1362 $or$libresoc.v:41946$1643_Y + connect \$1364 $or$libresoc.v:41947$1644_Y + connect \$1366 $or$libresoc.v:41948$1645_Y + connect \$1368 $or$libresoc.v:41949$1646_Y + connect \$1371 $or$libresoc.v:41950$1647_Y + connect \$1373 $or$libresoc.v:41951$1648_Y + connect \$1375 $or$libresoc.v:41952$1649_Y + connect \$1377 $or$libresoc.v:41953$1650_Y + connect \$1379 $or$libresoc.v:41954$1651_Y + connect \$1381 $and$libresoc.v:41955$1652_Y + connect \$1383 $and$libresoc.v:41956$1653_Y + connect \$1385 $and$libresoc.v:41957$1654_Y + connect \$1387 $and$libresoc.v:41958$1655_Y + connect \$1390 $and$libresoc.v:41959$1656_Y + connect \$1393 $not$libresoc.v:41960$1657_Y + connect \$1395 $and$libresoc.v:41961$1658_Y + connect \$1398 $and$libresoc.v:41962$1659_Y + connect \$1401 $ternary$libresoc.v:41963$1660_Y + connect \$1403 $and$libresoc.v:41964$1661_Y + connect \$1406 $and$libresoc.v:41965$1662_Y + connect \$1409 $not$libresoc.v:41966$1663_Y + connect \$1411 $and$libresoc.v:41967$1664_Y + connect \$1414 $and$libresoc.v:41968$1665_Y + connect \$1417 $ternary$libresoc.v:41969$1666_Y + connect \$1419 $and$libresoc.v:41970$1667_Y + connect \$1422 $and$libresoc.v:41971$1668_Y + connect \$1425 $not$libresoc.v:41972$1669_Y + connect \$1427 $and$libresoc.v:41973$1670_Y + connect \$1430 $and$libresoc.v:41974$1671_Y + connect \$1433 $ternary$libresoc.v:41975$1672_Y + connect \$1435 $or$libresoc.v:41976$1673_Y + connect \$1437 $or$libresoc.v:41977$1674_Y + connect \$1440 $or$libresoc.v:41978$1675_Y + connect \$1442 $or$libresoc.v:41979$1676_Y + connect \$1439 $pos$libresoc.v:41980$1678_Y + connect \$1445 $and$libresoc.v:41981$1679_Y + connect \$1447 $and$libresoc.v:41982$1680_Y + connect \$1449 $and$libresoc.v:41983$1681_Y + connect \$1451 $and$libresoc.v:41984$1682_Y + connect \$1453 $and$libresoc.v:41985$1683_Y + connect \$1456 $and$libresoc.v:41986$1684_Y + connect \$1459 $not$libresoc.v:41987$1685_Y + connect \$1461 $and$libresoc.v:41988$1686_Y + connect \$1464 $and$libresoc.v:41989$1687_Y + connect \$1467 $ternary$libresoc.v:41990$1688_Y + connect \$1469 $and$libresoc.v:41991$1689_Y + connect \$1472 $and$libresoc.v:41992$1690_Y + connect \$1475 $not$libresoc.v:41993$1691_Y + connect \$1477 $and$libresoc.v:41994$1692_Y + connect \$1480 $and$libresoc.v:41995$1693_Y + connect \$1483 $ternary$libresoc.v:41996$1694_Y + connect \$1485 $and$libresoc.v:41997$1695_Y + connect \$1488 $and$libresoc.v:41998$1696_Y + connect \$1491 $not$libresoc.v:41999$1697_Y + connect \$1493 $and$libresoc.v:42000$1698_Y + connect \$1496 $and$libresoc.v:42001$1699_Y + connect \$1499 $ternary$libresoc.v:42002$1700_Y + connect \$1501 $and$libresoc.v:42003$1701_Y + connect \$1504 $and$libresoc.v:42004$1702_Y + connect \$1507 $not$libresoc.v:42005$1703_Y + connect \$1509 $and$libresoc.v:42006$1704_Y + connect \$1512 $and$libresoc.v:42007$1705_Y + connect \$1515 $ternary$libresoc.v:42008$1706_Y + connect \$1517 $or$libresoc.v:42009$1707_Y + connect \$1519 $or$libresoc.v:42010$1708_Y + connect \$1521 $or$libresoc.v:42011$1709_Y + connect \$1523 $or$libresoc.v:42012$1710_Y + connect \$1525 $or$libresoc.v:42013$1711_Y + connect \$1527 $or$libresoc.v:42014$1712_Y + connect \$1529 $and$libresoc.v:42015$1713_Y + connect \$1531 $and$libresoc.v:42016$1714_Y + connect \$1533 $and$libresoc.v:42017$1715_Y + connect \$1535 $and$libresoc.v:42018$1716_Y + connect \$1537 $and$libresoc.v:42019$1717_Y + connect \$1540 $and$libresoc.v:42020$1718_Y + connect \$1543 $not$libresoc.v:42021$1719_Y + connect \$1545 $and$libresoc.v:42022$1720_Y + connect \$1548 $and$libresoc.v:42023$1721_Y + connect \$1551 $ternary$libresoc.v:42024$1722_Y + connect \$1553 $and$libresoc.v:42025$1723_Y + connect \$1556 $and$libresoc.v:42026$1724_Y + connect \$1559 $not$libresoc.v:42027$1725_Y + connect \$1561 $and$libresoc.v:42028$1726_Y + connect \$1564 $and$libresoc.v:42029$1727_Y + connect \$1567 $ternary$libresoc.v:42030$1728_Y + connect \$1569 $and$libresoc.v:42031$1729_Y + connect \$1572 $and$libresoc.v:42032$1730_Y + connect \$1575 $not$libresoc.v:42033$1731_Y + connect \$1577 $and$libresoc.v:42034$1732_Y + connect \$1580 $and$libresoc.v:42035$1733_Y + connect \$1583 $ternary$libresoc.v:42036$1734_Y + connect \$1585 $and$libresoc.v:42037$1735_Y + connect \$1588 $and$libresoc.v:42038$1736_Y + connect \$1591 $not$libresoc.v:42039$1737_Y + connect \$1593 $and$libresoc.v:42040$1738_Y + connect \$1596 $and$libresoc.v:42041$1739_Y + connect \$1599 $ternary$libresoc.v:42042$1740_Y + connect \$1602 $or$libresoc.v:42043$1741_Y + connect \$1604 $or$libresoc.v:42044$1742_Y + connect \$1606 $or$libresoc.v:42045$1743_Y + connect \$1601 $pos$libresoc.v:42046$1745_Y + connect \$1610 $or$libresoc.v:42047$1746_Y + connect \$1612 $or$libresoc.v:42048$1747_Y + connect \$1614 $or$libresoc.v:42049$1748_Y + connect \$1609 $pos$libresoc.v:42050$1750_Y + connect \$1617 $and$libresoc.v:42051$1751_Y + connect \$1619 $and$libresoc.v:42052$1752_Y + connect \$1621 $and$libresoc.v:42053$1753_Y + connect \$1623 $and$libresoc.v:42054$1754_Y + connect \$1625 $and$libresoc.v:42055$1755_Y + connect \$1627 $and$libresoc.v:42056$1756_Y + connect \$1630 $and$libresoc.v:42057$1757_Y + connect \$1634 $not$libresoc.v:42058$1758_Y + connect \$1636 $and$libresoc.v:42059$1759_Y + connect \$1641 $and$libresoc.v:42060$1760_Y + connect \$1644 $ternary$libresoc.v:42061$1761_Y + connect \$1646 $and$libresoc.v:42062$1762_Y + connect \$1649 $and$libresoc.v:42063$1763_Y + connect \$1652 $not$libresoc.v:42064$1764_Y + connect \$1654 $and$libresoc.v:42065$1765_Y + connect \$1657 $and$libresoc.v:42066$1766_Y + connect \$1660 $ternary$libresoc.v:42067$1767_Y + connect \$1662 $and$libresoc.v:42068$1768_Y + connect \$1665 $and$libresoc.v:42069$1769_Y + connect \$1668 $not$libresoc.v:42070$1770_Y + connect \$1670 $and$libresoc.v:42071$1771_Y + connect \$1673 $and$libresoc.v:42072$1772_Y + connect \$1676 $ternary$libresoc.v:42073$1773_Y + connect \$1678 $and$libresoc.v:42074$1774_Y + connect \$1681 $and$libresoc.v:42075$1775_Y + connect \$1684 $not$libresoc.v:42076$1776_Y + connect \$1686 $and$libresoc.v:42077$1777_Y + connect \$1689 $and$libresoc.v:42078$1778_Y + connect \$1692 $ternary$libresoc.v:42079$1779_Y + connect \$1694 $and$libresoc.v:42080$1780_Y + connect \$1697 $and$libresoc.v:42081$1781_Y + connect \$1700 $not$libresoc.v:42082$1782_Y + connect \$1702 $and$libresoc.v:42083$1783_Y + connect \$1705 $and$libresoc.v:42084$1784_Y + connect \$1708 $ternary$libresoc.v:42085$1785_Y + connect \$1710 $or$libresoc.v:42086$1786_Y + connect \$1712 $or$libresoc.v:42087$1787_Y + connect \$1714 $or$libresoc.v:42088$1788_Y + connect \$1716 $or$libresoc.v:42089$1789_Y + connect \$1718 $or$libresoc.v:42090$1790_Y + connect \$1720 $or$libresoc.v:42091$1791_Y + connect \$1722 $or$libresoc.v:42092$1792_Y + connect \$1724 $or$libresoc.v:42093$1793_Y + connect \$1726 $or$libresoc.v:42094$1794_Y + connect \$1728 $or$libresoc.v:42095$1795_Y + connect \$1730 $or$libresoc.v:42096$1796_Y + connect \$1732 $or$libresoc.v:42097$1797_Y + connect \$1734 $and$libresoc.v:42098$1798_Y + connect \$1736 $and$libresoc.v:42099$1799_Y + connect \$1738 $and$libresoc.v:42100$1800_Y + connect \$1741 $and$libresoc.v:42101$1801_Y + connect \$1744 $not$libresoc.v:42102$1802_Y + connect \$1746 $and$libresoc.v:42103$1803_Y + connect \$1749 $and$libresoc.v:42104$1804_Y + connect \$1752 $ternary$libresoc.v:42105$1805_Y + connect \$1754 $and$libresoc.v:42106$1806_Y + connect \$1757 $and$libresoc.v:42107$1807_Y + connect \$1760 $not$libresoc.v:42108$1808_Y + connect \$1762 $and$libresoc.v:42109$1809_Y + connect \$1765 $and$libresoc.v:42110$1810_Y + connect \$1768 $ternary$libresoc.v:42111$1811_Y + connect \$1770 $or$libresoc.v:42112$1812_Y + connect \$1773 $or$libresoc.v:42113$1813_Y + connect \$1772 $pos$libresoc.v:42114$1815_Y + connect \$1776 $and$libresoc.v:42115$1816_Y + connect \$1778 $and$libresoc.v:42116$1817_Y + connect \$177 $and$libresoc.v:42117$1818_Y + connect \$1781 $and$libresoc.v:42118$1819_Y + connect \$1784 $not$libresoc.v:42119$1820_Y + connect \$1786 $and$libresoc.v:42120$1821_Y + connect \$176 $reduce_or$libresoc.v:42121$1822_Y + connect \$1789 $and$libresoc.v:42122$1823_Y + connect \$1792 $ternary$libresoc.v:42123$1824_Y + connect \$1794 $pos$libresoc.v:42124$1826_Y + connect \$1796 $and$libresoc.v:42125$1827_Y + connect \$1798 $and$libresoc.v:42126$1828_Y + connect \$1801 $and$libresoc.v:42127$1829_Y + connect \$1804 $not$libresoc.v:42128$1830_Y + connect \$1806 $and$libresoc.v:42129$1831_Y + connect \$1809 $and$libresoc.v:42130$1832_Y + connect \$1812 $ternary$libresoc.v:42131$1833_Y + connect \$181 $and$libresoc.v:42132$1834_Y + connect \$180 $reduce_or$libresoc.v:42133$1835_Y + connect \$185 $and$libresoc.v:42134$1836_Y + connect \$184 $reduce_or$libresoc.v:42135$1837_Y + connect \$189 $and$libresoc.v:42136$1838_Y + connect \$188 $reduce_or$libresoc.v:42137$1839_Y + connect \$193 $and$libresoc.v:42138$1840_Y + connect \$192 $reduce_or$libresoc.v:42139$1841_Y + connect \$197 $and$libresoc.v:42140$1842_Y + connect \$196 $reduce_or$libresoc.v:42141$1843_Y + connect \$201 $and$libresoc.v:42142$1844_Y + connect \$200 $reduce_or$libresoc.v:42143$1845_Y + connect \$205 $and$libresoc.v:42144$1846_Y + connect \$204 $reduce_or$libresoc.v:42145$1847_Y + connect \$209 $and$libresoc.v:42146$1848_Y + connect \$208 $reduce_or$libresoc.v:42147$1849_Y + connect \$213 $and$libresoc.v:42148$1850_Y + connect \$212 $reduce_or$libresoc.v:42149$1851_Y + connect \$216 $ne$libresoc.v:42150$1852_Y + connect \$219 $sub$libresoc.v:42151$1853_Y + connect \$221 $ne$libresoc.v:42152$1854_Y + connect \$224 $and$libresoc.v:42153$1855_Y + connect \$226 $and$libresoc.v:42154$1856_Y + connect \$228 $eq$libresoc.v:42155$1857_Y + connect \$230 $or$libresoc.v:42156$1858_Y + connect \$232 $and$libresoc.v:42157$1859_Y + connect \$234 $or$libresoc.v:42158$1860_Y + connect \$236 $eq$libresoc.v:42159$1861_Y + connect \$238 $and$libresoc.v:42160$1862_Y + connect \$240 $eq$libresoc.v:42161$1863_Y + connect \$242 $or$libresoc.v:42162$1864_Y + connect \$223 $not$libresoc.v:42163$1865_Y + connect \$245 $not$libresoc.v:42164$1866_Y + connect \$247 $not$libresoc.v:42165$1867_Y + connect \$249 $not$libresoc.v:42166$1868_Y + connect \$252 $and$libresoc.v:42167$1869_Y + connect \$254 $and$libresoc.v:42168$1870_Y + connect \$256 $eq$libresoc.v:42169$1871_Y + connect \$258 $or$libresoc.v:42170$1872_Y + connect \$260 $and$libresoc.v:42171$1873_Y + connect \$262 $or$libresoc.v:42172$1874_Y + connect \$251 $not$libresoc.v:42173$1875_Y + connect \$266 $and$libresoc.v:42174$1876_Y + connect \$268 $and$libresoc.v:42175$1877_Y + connect \$270 $eq$libresoc.v:42176$1878_Y + connect \$272 $or$libresoc.v:42177$1879_Y + connect \$274 $and$libresoc.v:42178$1880_Y + connect \$276 $or$libresoc.v:42179$1881_Y + connect \$278 $and$libresoc.v:42180$1882_Y + connect \$280 $and$libresoc.v:42181$1883_Y + connect \$282 $eq$libresoc.v:42182$1884_Y + connect \$284 $or$libresoc.v:42183$1885_Y + connect \$286 $eq$libresoc.v:42184$1886_Y + connect \$288 $and$libresoc.v:42185$1887_Y + connect \$290 $eq$libresoc.v:42186$1888_Y + connect \$292 $or$libresoc.v:42187$1889_Y + connect \$265 $not$libresoc.v:42188$1890_Y + connect \$296 $and$libresoc.v:42189$1891_Y + connect \$298 $and$libresoc.v:42190$1892_Y + connect \$300 $eq$libresoc.v:42191$1893_Y + connect \$302 $or$libresoc.v:42192$1894_Y + connect \$304 $and$libresoc.v:42193$1895_Y + connect \$306 $or$libresoc.v:42194$1896_Y + connect \$295 $not$libresoc.v:42195$1897_Y + connect \$310 $and$libresoc.v:42196$1898_Y + connect \$312 $and$libresoc.v:42197$1899_Y + connect \$314 $eq$libresoc.v:42198$1900_Y + connect \$316 $or$libresoc.v:42199$1901_Y + connect \$318 $and$libresoc.v:42200$1902_Y + connect \$320 $or$libresoc.v:42201$1903_Y + connect \$309 $not$libresoc.v:42202$1904_Y + connect \$324 $and$libresoc.v:42203$1905_Y + connect \$326 $and$libresoc.v:42204$1906_Y + connect \$328 $eq$libresoc.v:42205$1907_Y + connect \$330 $or$libresoc.v:42206$1908_Y + connect \$332 $and$libresoc.v:42207$1909_Y + connect \$334 $or$libresoc.v:42208$1910_Y + connect \$336 $eq$libresoc.v:42209$1911_Y + connect \$338 $and$libresoc.v:42210$1912_Y + connect \$340 $eq$libresoc.v:42211$1913_Y + connect \$342 $or$libresoc.v:42212$1914_Y + connect \$323 $not$libresoc.v:42213$1915_Y + connect \$345 $not$libresoc.v:42214$1916_Y + connect \$347 $and$libresoc.v:42215$1917_Y + connect \$349 $and$libresoc.v:42216$1918_Y + connect \$351 $not$libresoc.v:42217$1919_Y + connect \$353 $and$libresoc.v:42218$1920_Y + connect \$355 $and$libresoc.v:42219$1921_Y + connect \$357 $ternary$libresoc.v:42220$1922_Y + connect \$359 $and$libresoc.v:42221$1923_Y + connect \$361 $and$libresoc.v:42222$1924_Y + connect \$363 $not$libresoc.v:42223$1925_Y + connect \$365 $and$libresoc.v:42224$1926_Y + connect \$367 $and$libresoc.v:42225$1927_Y + connect \$369 $ternary$libresoc.v:42226$1928_Y + connect \$371 $and$libresoc.v:42227$1929_Y + connect \$373 $and$libresoc.v:42228$1930_Y + connect \$375 $not$libresoc.v:42229$1931_Y + connect \$377 $and$libresoc.v:42230$1932_Y + connect \$379 $and$libresoc.v:42231$1933_Y + connect \$381 $ternary$libresoc.v:42232$1934_Y + connect \$383 $and$libresoc.v:42233$1935_Y + connect \$385 $and$libresoc.v:42234$1936_Y + connect \$387 $not$libresoc.v:42235$1937_Y + connect \$389 $and$libresoc.v:42236$1938_Y + connect \$391 $and$libresoc.v:42237$1939_Y + connect \$393 $ternary$libresoc.v:42238$1940_Y + connect \$395 $and$libresoc.v:42239$1941_Y + connect \$397 $and$libresoc.v:42240$1942_Y + connect \$399 $not$libresoc.v:42241$1943_Y + connect \$401 $and$libresoc.v:42242$1944_Y + connect \$403 $and$libresoc.v:42243$1945_Y + connect \$405 $ternary$libresoc.v:42244$1946_Y + connect \$407 $and$libresoc.v:42245$1947_Y + connect \$409 $and$libresoc.v:42246$1948_Y + connect \$411 $not$libresoc.v:42247$1949_Y + connect \$413 $and$libresoc.v:42248$1950_Y + connect \$415 $and$libresoc.v:42249$1951_Y + connect \$417 $ternary$libresoc.v:42250$1952_Y + connect \$419 $and$libresoc.v:42251$1953_Y + connect \$421 $and$libresoc.v:42252$1954_Y + connect \$423 $not$libresoc.v:42253$1955_Y + connect \$425 $and$libresoc.v:42254$1956_Y + connect \$427 $and$libresoc.v:42255$1957_Y + connect \$429 $ternary$libresoc.v:42256$1958_Y + connect \$431 $and$libresoc.v:42257$1959_Y + connect \$433 $and$libresoc.v:42258$1960_Y + connect \$435 $not$libresoc.v:42259$1961_Y + connect \$437 $and$libresoc.v:42260$1962_Y + connect \$439 $and$libresoc.v:42261$1963_Y + connect \$441 $ternary$libresoc.v:42262$1964_Y + connect \$443 $and$libresoc.v:42263$1965_Y + connect \$445 $and$libresoc.v:42264$1966_Y + connect \$447 $not$libresoc.v:42265$1967_Y + connect \$449 $and$libresoc.v:42266$1968_Y + connect \$451 $and$libresoc.v:42267$1969_Y + connect \$453 $ternary$libresoc.v:42268$1970_Y + connect \$456 $or$libresoc.v:42269$1971_Y + connect \$458 $or$libresoc.v:42270$1972_Y + connect \$460 $or$libresoc.v:42271$1973_Y + connect \$462 $or$libresoc.v:42272$1974_Y + connect \$464 $or$libresoc.v:42273$1975_Y + connect \$466 $or$libresoc.v:42274$1976_Y + connect \$468 $or$libresoc.v:42275$1977_Y + connect \$470 $or$libresoc.v:42276$1978_Y + connect \$472 $reduce_or$libresoc.v:42277$1979_Y + connect \$474 $and$libresoc.v:42278$1980_Y + connect \$476 $and$libresoc.v:42279$1981_Y + connect \$478 $not$libresoc.v:42280$1982_Y + connect \$480 $and$libresoc.v:42281$1983_Y + connect \$482 $and$libresoc.v:42282$1984_Y + connect \$484 $ternary$libresoc.v:42283$1985_Y + connect \$486 $and$libresoc.v:42284$1986_Y + connect \$488 $and$libresoc.v:42285$1987_Y + connect \$490 $not$libresoc.v:42286$1988_Y + connect \$492 $and$libresoc.v:42287$1989_Y + connect \$494 $and$libresoc.v:42288$1990_Y + connect \$496 $ternary$libresoc.v:42289$1991_Y + connect \$498 $and$libresoc.v:42290$1992_Y + connect \$500 $and$libresoc.v:42291$1993_Y + connect \$502 $not$libresoc.v:42292$1994_Y + connect \$504 $and$libresoc.v:42293$1995_Y + connect \$506 $and$libresoc.v:42294$1996_Y + connect \$508 $ternary$libresoc.v:42295$1997_Y + connect \$510 $and$libresoc.v:42296$1998_Y + connect \$512 $and$libresoc.v:42297$1999_Y + connect \$514 $not$libresoc.v:42298$2000_Y + connect \$516 $and$libresoc.v:42299$2001_Y + connect \$518 $and$libresoc.v:42300$2002_Y + connect \$520 $ternary$libresoc.v:42301$2003_Y + connect \$522 $and$libresoc.v:42302$2004_Y + connect \$524 $and$libresoc.v:42303$2005_Y + connect \$526 $not$libresoc.v:42304$2006_Y + connect \$528 $and$libresoc.v:42305$2007_Y + connect \$530 $and$libresoc.v:42306$2008_Y + connect \$532 $ternary$libresoc.v:42307$2009_Y + connect \$534 $and$libresoc.v:42308$2010_Y + connect \$536 $and$libresoc.v:42309$2011_Y + connect \$538 $not$libresoc.v:42310$2012_Y + connect \$540 $and$libresoc.v:42311$2013_Y + connect \$542 $and$libresoc.v:42312$2014_Y + connect \$544 $ternary$libresoc.v:42313$2015_Y + connect \$546 $and$libresoc.v:42314$2016_Y + connect \$548 $and$libresoc.v:42315$2017_Y + connect \$550 $not$libresoc.v:42316$2018_Y + connect \$552 $and$libresoc.v:42317$2019_Y + connect \$554 $and$libresoc.v:42318$2020_Y + connect \$556 $ternary$libresoc.v:42319$2021_Y + connect \$558 $and$libresoc.v:42320$2022_Y + connect \$560 $and$libresoc.v:42321$2023_Y + connect \$562 $not$libresoc.v:42322$2024_Y + connect \$564 $and$libresoc.v:42323$2025_Y + connect \$566 $and$libresoc.v:42324$2026_Y + connect \$568 $ternary$libresoc.v:42325$2027_Y + connect \$571 $or$libresoc.v:42326$2028_Y + connect \$573 $or$libresoc.v:42327$2029_Y + connect \$575 $or$libresoc.v:42328$2030_Y + connect \$577 $or$libresoc.v:42329$2031_Y + connect \$579 $or$libresoc.v:42330$2032_Y + connect \$581 $or$libresoc.v:42331$2033_Y + connect \$583 $or$libresoc.v:42332$2034_Y + connect \$585 $reduce_or$libresoc.v:42333$2035_Y + connect \$587 $and$libresoc.v:42334$2036_Y + connect \$589 $and$libresoc.v:42335$2037_Y + connect \$591 $not$libresoc.v:42336$2038_Y + connect \$593 $and$libresoc.v:42337$2039_Y + connect \$595 $and$libresoc.v:42338$2040_Y + connect \$597 $ternary$libresoc.v:42339$2041_Y + connect \$599 $and$libresoc.v:42340$2042_Y + connect \$601 $and$libresoc.v:42341$2043_Y + connect \$603 $not$libresoc.v:42342$2044_Y + connect \$605 $and$libresoc.v:42343$2045_Y + connect \$607 $and$libresoc.v:42344$2046_Y + connect \$609 $ternary$libresoc.v:42345$2047_Y + connect \$612 $or$libresoc.v:42346$2048_Y + connect \$614 $reduce_or$libresoc.v:42347$2049_Y + connect \$616 $and$libresoc.v:42348$2050_Y + connect \$618 $and$libresoc.v:42349$2051_Y + connect \$620 $eq$libresoc.v:42350$2052_Y + connect \$622 $or$libresoc.v:42351$2053_Y + connect \$624 $and$libresoc.v:42352$2054_Y + connect \$626 $or$libresoc.v:42353$2055_Y + connect \$628 $and$libresoc.v:42354$2056_Y + connect \$630 $and$libresoc.v:42355$2057_Y + connect \$632 $not$libresoc.v:42356$2058_Y + connect \$634 $and$libresoc.v:42357$2059_Y + connect \$636 $and$libresoc.v:42358$2060_Y + connect \$638 $ternary$libresoc.v:42359$2061_Y + connect \$640 $and$libresoc.v:42360$2062_Y + connect \$642 $and$libresoc.v:42361$2063_Y + connect \$644 $not$libresoc.v:42362$2064_Y + connect \$646 $and$libresoc.v:42363$2065_Y + connect \$648 $and$libresoc.v:42364$2066_Y + connect \$650 $ternary$libresoc.v:42365$2067_Y + connect \$652 $and$libresoc.v:42366$2068_Y + connect \$654 $and$libresoc.v:42367$2069_Y + connect \$656 $not$libresoc.v:42368$2070_Y + connect \$658 $and$libresoc.v:42369$2071_Y + connect \$660 $and$libresoc.v:42370$2072_Y + connect \$662 $ternary$libresoc.v:42371$2073_Y + connect \$664 $and$libresoc.v:42372$2074_Y + connect \$666 $and$libresoc.v:42373$2075_Y + connect \$668 $not$libresoc.v:42374$2076_Y + connect \$670 $and$libresoc.v:42375$2077_Y + connect \$672 $and$libresoc.v:42376$2078_Y + connect \$674 $ternary$libresoc.v:42377$2079_Y + connect \$676 $and$libresoc.v:42378$2080_Y + connect \$678 $and$libresoc.v:42379$2081_Y + connect \$680 $not$libresoc.v:42380$2082_Y + connect \$682 $and$libresoc.v:42381$2083_Y + connect \$684 $and$libresoc.v:42382$2084_Y + connect \$686 $ternary$libresoc.v:42383$2085_Y + connect \$688 $and$libresoc.v:42384$2086_Y + connect \$690 $and$libresoc.v:42385$2087_Y + connect \$692 $not$libresoc.v:42386$2088_Y + connect \$694 $and$libresoc.v:42387$2089_Y + connect \$696 $and$libresoc.v:42388$2090_Y + connect \$698 $ternary$libresoc.v:42389$2091_Y + connect \$701 $or$libresoc.v:42390$2092_Y + connect \$703 $or$libresoc.v:42391$2093_Y + connect \$705 $or$libresoc.v:42392$2094_Y + connect \$707 $or$libresoc.v:42393$2095_Y + connect \$709 $or$libresoc.v:42394$2096_Y + connect \$700 $pos$libresoc.v:42395$2098_Y + connect \$712 $eq$libresoc.v:42396$2099_Y + connect \$714 $and$libresoc.v:42397$2100_Y + connect \$716 $eq$libresoc.v:42398$2101_Y + connect \$718 $or$libresoc.v:42399$2102_Y + connect \$720 $and$libresoc.v:42400$2103_Y + connect \$722 $and$libresoc.v:42401$2104_Y + connect \$724 $not$libresoc.v:42402$2105_Y + connect \$726 $and$libresoc.v:42403$2106_Y + connect \$728 $and$libresoc.v:42404$2107_Y + connect \$730 $ternary$libresoc.v:42405$2108_Y + connect \$732 $and$libresoc.v:42406$2109_Y + connect \$734 $and$libresoc.v:42407$2110_Y + connect \$736 $not$libresoc.v:42408$2111_Y + connect \$738 $and$libresoc.v:42409$2112_Y + connect \$740 $and$libresoc.v:42410$2113_Y + connect \$742 $ternary$libresoc.v:42411$2114_Y + connect \$744 $and$libresoc.v:42412$2115_Y + connect \$746 $and$libresoc.v:42413$2116_Y + connect \$748 $not$libresoc.v:42414$2117_Y + connect \$750 $and$libresoc.v:42415$2118_Y + connect \$752 $and$libresoc.v:42416$2119_Y + connect \$754 $ternary$libresoc.v:42417$2120_Y + connect \$757 $or$libresoc.v:42418$2121_Y + connect \$759 $or$libresoc.v:42419$2122_Y + connect \$756 $pos$libresoc.v:42420$2124_Y + connect \$762 $and$libresoc.v:42421$2125_Y + connect \$764 $and$libresoc.v:42422$2126_Y + connect \$766 $eq$libresoc.v:42423$2127_Y + connect \$768 $or$libresoc.v:42424$2128_Y + connect \$770 $and$libresoc.v:42425$2129_Y + connect \$772 $and$libresoc.v:42426$2130_Y + connect \$774 $not$libresoc.v:42427$2131_Y + connect \$776 $and$libresoc.v:42428$2132_Y + connect \$778 $and$libresoc.v:42429$2133_Y + connect \$780 $ternary$libresoc.v:42430$2134_Y + connect \$782 $and$libresoc.v:42431$2135_Y + connect \$784 $and$libresoc.v:42432$2136_Y + connect \$786 $not$libresoc.v:42433$2137_Y + connect \$788 $and$libresoc.v:42434$2138_Y + connect \$790 $and$libresoc.v:42435$2139_Y + connect \$792 $ternary$libresoc.v:42436$2140_Y + connect \$794 $and$libresoc.v:42437$2141_Y + connect \$796 $and$libresoc.v:42438$2142_Y + connect \$798 $not$libresoc.v:42439$2143_Y + connect \$800 $and$libresoc.v:42440$2144_Y + connect \$802 $and$libresoc.v:42441$2145_Y + connect \$804 $sub$libresoc.v:42442$2146_Y + connect \$806 $sshl$libresoc.v:42443$2147_Y + connect \$808 $ternary$libresoc.v:42444$2148_Y + connect \$810 $and$libresoc.v:42445$2149_Y + connect \$812 $and$libresoc.v:42446$2150_Y + connect \$814 $not$libresoc.v:42447$2151_Y + connect \$816 $and$libresoc.v:42448$2152_Y + connect \$818 $and$libresoc.v:42449$2153_Y + connect \$820 $sub$libresoc.v:42450$2154_Y + connect \$822 $sshl$libresoc.v:42451$2155_Y + connect \$824 $ternary$libresoc.v:42452$2156_Y + connect \$827 $or$libresoc.v:42453$2157_Y + connect \$829 $and$libresoc.v:42454$2158_Y + connect \$831 $and$libresoc.v:42455$2159_Y + connect \$833 $not$libresoc.v:42456$2160_Y + connect \$835 $and$libresoc.v:42457$2161_Y + connect \$837 $and$libresoc.v:42458$2162_Y + connect \$839 $sub$libresoc.v:42459$2163_Y + connect \$841 $sshl$libresoc.v:42460$2164_Y + connect \$843 $ternary$libresoc.v:42461$2165_Y + connect \$845 $and$libresoc.v:42462$2166_Y + connect \$847 $and$libresoc.v:42463$2167_Y + connect \$849 $not$libresoc.v:42464$2168_Y + connect \$851 $and$libresoc.v:42465$2169_Y + connect \$853 $and$libresoc.v:42466$2170_Y + connect \$855 $sub$libresoc.v:42467$2171_Y + connect \$857 $sshl$libresoc.v:42468$2172_Y + connect \$859 $ternary$libresoc.v:42469$2173_Y + connect \$861 $and$libresoc.v:42470$2174_Y + connect \$863 $and$libresoc.v:42471$2175_Y + connect \$865 $not$libresoc.v:42472$2176_Y + connect \$867 $and$libresoc.v:42473$2177_Y + connect \$869 $and$libresoc.v:42474$2178_Y + connect \$871 $ternary$libresoc.v:42475$2179_Y + connect \$873 $and$libresoc.v:42476$2180_Y + connect \$875 $and$libresoc.v:42477$2181_Y + connect \$877 $not$libresoc.v:42478$2182_Y + connect \$879 $and$libresoc.v:42479$2183_Y + connect \$881 $and$libresoc.v:42480$2184_Y + connect \$883 $ternary$libresoc.v:42481$2185_Y + connect \$885 $and$libresoc.v:42482$2186_Y + connect \$887 $and$libresoc.v:42483$2187_Y + connect \$889 $not$libresoc.v:42484$2188_Y + connect \$891 $and$libresoc.v:42485$2189_Y + connect \$893 $and$libresoc.v:42486$2190_Y + connect \$895 $ternary$libresoc.v:42487$2191_Y + connect \$897 $or$libresoc.v:42488$2192_Y + connect \$899 $or$libresoc.v:42489$2193_Y + connect \$901 $reduce_or$libresoc.v:42490$2194_Y + connect \$903 $and$libresoc.v:42491$2195_Y + connect \$905 $and$libresoc.v:42492$2196_Y + connect \$907 $not$libresoc.v:42493$2197_Y + connect \$909 $and$libresoc.v:42494$2198_Y + connect \$911 $and$libresoc.v:42495$2199_Y + connect \$913 $ternary$libresoc.v:42496$2200_Y + connect \$915 $and$libresoc.v:42497$2201_Y + connect \$917 $and$libresoc.v:42498$2202_Y + connect \$919 $not$libresoc.v:42499$2203_Y + connect \$921 $and$libresoc.v:42500$2204_Y + connect \$923 $and$libresoc.v:42501$2205_Y + connect \$925 $ternary$libresoc.v:42502$2206_Y + connect \$927 $or$libresoc.v:42503$2207_Y + connect \$929 $reduce_or$libresoc.v:42504$2208_Y + connect \$931 $and$libresoc.v:42505$2209_Y + connect \$933 $and$libresoc.v:42506$2210_Y + connect \$935 $not$libresoc.v:42507$2211_Y + connect \$937 $and$libresoc.v:42508$2212_Y + connect \$939 $and$libresoc.v:42509$2213_Y + connect \$941 $ternary$libresoc.v:42510$2214_Y + connect \$943 $reduce_or$libresoc.v:42511$2215_Y + connect \$945 $and$libresoc.v:42512$2216_Y + connect \$947 $and$libresoc.v:42513$2217_Y + connect \$949 $and$libresoc.v:42514$2218_Y + connect \$951 $and$libresoc.v:42515$2219_Y + connect \$953 $and$libresoc.v:42516$2220_Y + connect \$955 $and$libresoc.v:42517$2221_Y + connect \$957 $and$libresoc.v:42518$2222_Y + connect \$959 $and$libresoc.v:42519$2223_Y + connect \$961 $and$libresoc.v:42520$2224_Y + connect \$963 $and$libresoc.v:42521$2225_Y + connect \$965 $and$libresoc.v:42522$2226_Y + connect \$967 $and$libresoc.v:42523$2227_Y + connect \$969 $not$libresoc.v:42524$2228_Y + connect \$971 $and$libresoc.v:42525$2229_Y + connect \$977 $and$libresoc.v:42526$2230_Y + connect \$979 $ternary$libresoc.v:42527$2231_Y + connect \$981 $and$libresoc.v:42528$2232_Y + connect \$984 $and$libresoc.v:42529$2233_Y + connect \$988 $not$libresoc.v:42530$2234_Y + connect \$990 $and$libresoc.v:42531$2235_Y + connect \$995 $and$libresoc.v:42532$2236_Y + connect \$998 $ternary$libresoc.v:42533$2237_Y + connect \$218 \$219 + connect \$455 \$470 + connect \$570 \$583 + connect \$611 \$612 + connect \$826 \$827 + connect \$1154 \$1171 + connect \$1173 \$1190 + connect \$1370 \$1379 + connect \o_ok 1'0 + connect \ea_ok 1'0 + connect \spr_spr1__wen \wp$1808 + connect \spr_spr1__addr$175 \addr_en$1811 [6:0] + connect \spr_spr1__data_i \fus_dest2_o$162 + connect \addr_en$1811 \$1812 + connect \wp$1808 \$1809 + connect \wr_pick_rise$1054 \$1806 + connect \wr_pick$1800 \$1801 + connect \wrpick_SPR_spr1_i \$1798 + connect \wrflag_spr0_spr1_1 \$1796 + connect \state_wen \$1794 + connect \state_data_i$174 \fus_dest5_o$161 + connect \addr_en$1791 \$1792 + connect \wp$1788 \$1789 + connect \wr_pick_rise$1014 \$1786 + connect \wr_pick$1780 \$1781 + connect \wrpick_STATE_msr_i \$1778 + connect \wrflag_trap0_msr_4 \$1776 + connect \state_nia_wen \$1772 + connect \state_data_i \$1770 + connect \addr_en$1767 \$1768 + connect \wp$1764 \$1765 + connect \wr_pick_rise$1013 \$1762 + connect \wr_pick$1756 \$1757 + connect \wrflag_trap0_nia_3 \$1754 + connect \addr_en$1751 \$1752 + connect \wp$1748 \$1749 + connect \wr_pick_rise$1639 \$1746 + connect \wr_pick$1740 \$1741 + connect \wrpick_STATE_nia_i [1] \$1738 + connect \wrpick_STATE_nia_i [0] \$1736 + connect \wrflag_branch0_nia_2 \$1734 + connect \fast_dest1__wen \$1732 + connect \fast_dest1__addr \$1724 + connect \fast_dest1__data_i \$1716 + connect \addr_en$1707 \$1708 + connect \wp$1704 \$1705 + connect \wr_pick_rise$1012 \$1702 + connect \wr_pick$1696 \$1697 + connect \wrflag_trap0_fast1_2 \$1694 + connect \addr_en$1691 \$1692 + connect \wp$1688 \$1689 + connect \wr_pick_rise$1638 \$1686 + connect \wr_pick$1680 \$1681 + connect \wrflag_branch0_fast1_1 \$1678 + connect \addr_en$1675 \$1676 + connect \wp$1672 \$1673 + connect \wr_pick_rise$1053 \$1670 + connect \wr_pick$1664 \$1665 + connect \wrflag_spr0_fast1_2 \$1662 + connect \addr_en$1659 \$1660 + connect \wp$1656 \$1657 + connect \wr_pick_rise$1011 \$1654 + connect \wr_pick$1648 \$1649 + connect \wrflag_trap0_fast1_1 \$1646 + connect \addr_en$1643 \$1644 + connect \wp$1640 \$1641 + connect \fus_cu_wr__go_i$149 [2] \wr_pick_rise$1639 + connect \fus_cu_wr__go_i$149 [1] \wr_pick_rise$1638 + connect \fus_cu_wr__go_i$149 [0] \wr_pick_rise$1633 + connect \wr_pick_rise$1633 \$1636 + connect \wr_pick$1629 \$1630 + connect \wrpick_FAST_fast1_i [4] \$1627 + connect \wrpick_FAST_fast1_i [3] \$1625 + connect \wrpick_FAST_fast1_i [2] \$1623 + connect \wrpick_FAST_fast1_i [1] \$1621 + connect \wrpick_FAST_fast1_i [0] \$1619 + connect \wrflag_branch0_fast1_0 \$1617 + connect \xer_wen$173 \$1609 + connect \xer_data_i$172 \$1601 + connect \addr_en$1598 \$1599 + connect \wp$1595 \$1596 + connect \wr_pick_rise$1094 \$1593 + connect \wr_pick$1587 \$1588 + connect \wrflag_mul0_xer_so_3 \$1585 + connect \addr_en$1582 \$1583 + connect \wp$1579 \$1580 + connect \wr_pick_rise$1074 \$1577 + connect \wr_pick$1571 \$1572 + connect \wrflag_div0_xer_so_3 \$1569 + connect \addr_en$1566 \$1567 + connect \wp$1563 \$1564 + connect \wr_pick_rise$1052 \$1561 + connect \wr_pick$1555 \$1556 + connect \wrflag_spr0_xer_so_3 \$1553 + connect \addr_en$1550 \$1551 + connect \wp$1547 \$1548 + connect \wr_pick_rise$976 \$1545 + connect \wr_pick$1539 \$1540 + connect \wrpick_XER_xer_so_i [3] \$1537 + connect \wrpick_XER_xer_so_i [2] \$1535 + connect \wrpick_XER_xer_so_i [1] \$1533 + connect \wrpick_XER_xer_so_i [0] \$1531 + connect \wrflag_alu0_xer_so_4 \$1529 + connect \xer_wen$171 \$1527 + connect \xer_data_i$170 \$1521 + connect \addr_en$1514 \$1515 + connect \wp$1511 \$1512 + connect \wr_pick_rise$1093 \$1509 + connect \wr_pick$1503 \$1504 + connect \wrflag_mul0_xer_ov_2 \$1501 + connect \addr_en$1498 \$1499 + connect \wp$1495 \$1496 + connect \wr_pick_rise$1073 \$1493 + connect \wr_pick$1487 \$1488 + connect \wrflag_div0_xer_ov_2 \$1485 + connect \addr_en$1482 \$1483 + connect \wp$1479 \$1480 + connect \wr_pick_rise$1051 \$1477 + connect \wr_pick$1471 \$1472 + connect \wrflag_spr0_xer_ov_4 \$1469 + connect \addr_en$1466 \$1467 + connect \wp$1463 \$1464 + connect \wr_pick_rise$975 \$1461 + connect \wr_pick$1455 \$1456 + connect \wrpick_XER_xer_ov_i [3] \$1453 + connect \wrpick_XER_xer_ov_i [2] \$1451 + connect \wrpick_XER_xer_ov_i [1] \$1449 + connect \wrpick_XER_xer_ov_i [0] \$1447 + connect \wrflag_alu0_xer_ov_3 \$1445 + connect \xer_wen \$1439 + connect \xer_data_i \$1437 + connect \addr_en$1432 \$1433 + connect \wp$1429 \$1430 + connect \wr_pick_rise$1113 \$1427 + connect \wr_pick$1421 \$1422 + connect \wrflag_shiftrot0_xer_ca_2 \$1419 + connect \addr_en$1416 \$1417 + connect \wp$1413 \$1414 + connect \wr_pick_rise$1050 \$1411 + connect \wr_pick$1405 \$1406 + connect \wrflag_spr0_xer_ca_5 \$1403 + connect \addr_en$1400 \$1401 + connect \wp$1397 \$1398 + connect \wr_pick_rise$974 \$1395 + connect \wr_pick$1389 \$1390 + connect \wrpick_XER_xer_ca_i [2] \$1387 + connect \wrpick_XER_xer_ca_i [1] \$1385 + connect \wrpick_XER_xer_ca_i [0] \$1383 + connect \wrflag_alu0_xer_ca_2 \$1381 + connect \cr_wen \$1379 [7:0] + connect \cr_data_i \$1368 + connect \addr_en$1353 \$1358 + connect \wp$1350 \$1351 + connect \wr_pick_rise$1112 \$1348 + connect \wr_pick$1342 \$1343 + connect \wrflag_shiftrot0_cr_a_1 \$1340 + connect \addr_en$1333 \$1338 + connect \wp$1330 \$1331 + connect \wr_pick_rise$1092 \$1328 + connect \wr_pick$1322 \$1323 + connect \wrflag_mul0_cr_a_1 \$1320 + connect \addr_en$1313 \$1318 + connect \wp$1310 \$1311 + connect \wr_pick_rise$1072 \$1308 + connect \wr_pick$1302 \$1303 + connect \wrflag_div0_cr_a_1 \$1300 + connect \addr_en$1293 \$1298 + connect \wp$1290 \$1291 + connect \wr_pick_rise$1032 \$1288 + connect \wr_pick$1282 \$1283 + connect \wrflag_logical0_cr_a_1 \$1280 + connect \addr_en$1273 \$1278 + connect \wp$1270 \$1271 + connect \wr_pick_rise$993 \$1268 + connect \wr_pick$1262 \$1263 + connect \wrflag_cr0_cr_a_2 \$1260 + connect \addr_en$1253 \$1258 + connect \wp$1250 \$1251 + connect \wr_pick_rise$973 \$1248 + connect \wr_pick$1242 \$1243 + connect \wrpick_CR_cr_a_i [5] \$1240 + connect \wrpick_CR_cr_a_i [4] \$1238 + connect \wrpick_CR_cr_a_i [3] \$1236 + connect \wrpick_CR_cr_a_i [2] \$1234 + connect \wrpick_CR_cr_a_i [1] \$1232 + connect \wrpick_CR_cr_a_i [0] \$1230 + connect \wrflag_alu0_cr_a_1 \$1228 + connect \cr_full_wr__wen \addr_en$1225 + connect \cr_full_wr__data_i \fus_dest2_o + connect \addr_en$1225 \$1226 + connect \wp$1222 \$1223 + connect \wr_pick_rise$992 \$1220 + connect \wr_pick$1214 \$1215 + connect \wrpick_CR_full_cr_i \$1212 + connect \wrflag_cr0_full_cr_1 \$1210 + connect \int_dest1__wen \$1208 + connect \int_dest1__addr \$1190 [4:0] + connect \int_dest1__data_i \$1171 [63:0] + connect \addr_en$1151 \$1152 + connect \wp$1148 \$1149 + connect \wr_pick_rise$1131 \$1146 + connect \wr_pick$1140 \$1141 + connect \wrflag_ldst0_o_1 \$1138 + connect \addr_en$1135 \$1136 + connect \wp$1132 \$1133 + connect \fus_cu_wr__go_i$114 [1] \wr_pick_rise$1131 + connect \fus_cu_wr__go_i$114 [0] \wr_pick_rise$1126 + connect \wr_pick_rise$1126 \$1129 + connect \wr_pick$1122 \$1123 + connect \wrflag_ldst0_o_0 \$1120 + connect \addr_en$1117 \$1118 + connect \wp$1114 \$1115 + connect \fus_cu_wr__go_i$112 [2] \wr_pick_rise$1113 + connect \fus_cu_wr__go_i$112 [1] \wr_pick_rise$1112 + connect \fus_cu_wr__go_i$112 [0] \wr_pick_rise$1107 + connect \wr_pick_rise$1107 \$1110 + connect \wr_pick$1103 \$1104 + connect \wrflag_shiftrot0_o_0 \$1101 + connect \addr_en$1098 \$1099 + connect \wp$1095 \$1096 + connect \fus_cu_wr__go_i$109 [3] \wr_pick_rise$1094 + connect \fus_cu_wr__go_i$109 [2] \wr_pick_rise$1093 + connect \fus_cu_wr__go_i$109 [1] \wr_pick_rise$1092 + connect \fus_cu_wr__go_i$109 [0] \wr_pick_rise$1087 + connect \wr_pick_rise$1087 \$1090 + connect \wr_pick$1083 \$1084 + connect \wrflag_mul0_o_0 \$1081 + connect \addr_en$1078 \$1079 + connect \wp$1075 \$1076 + connect \fus_cu_wr__go_i$106 [3] \wr_pick_rise$1074 + connect \fus_cu_wr__go_i$106 [2] \wr_pick_rise$1073 + connect \fus_cu_wr__go_i$106 [1] \wr_pick_rise$1072 + connect \fus_cu_wr__go_i$106 [0] \wr_pick_rise$1067 + connect \wr_pick_rise$1067 \$1070 + connect \wr_pick$1063 \$1064 + connect \wrflag_div0_o_0 \$1061 + connect \addr_en$1058 \$1059 + connect \wp$1055 \$1056 + connect \fus_cu_wr__go_i$103 [1] \wr_pick_rise$1054 + connect \fus_cu_wr__go_i$103 [2] \wr_pick_rise$1053 + connect \fus_cu_wr__go_i$103 [3] \wr_pick_rise$1052 + connect \fus_cu_wr__go_i$103 [4] \wr_pick_rise$1051 + connect \fus_cu_wr__go_i$103 [5] \wr_pick_rise$1050 + connect \fus_cu_wr__go_i$103 [0] \wr_pick_rise$1045 + connect \wr_pick_rise$1045 \$1048 + connect \wr_pick$1041 \$1042 + connect \wrflag_spr0_o_0 \$1039 + connect \addr_en$1036 \$1037 + connect \wp$1033 \$1034 + connect \fus_cu_wr__go_i$100 [1] \wr_pick_rise$1032 + connect \fus_cu_wr__go_i$100 [0] \wr_pick_rise$1027 + connect \wr_pick_rise$1027 \$1030 + connect \wr_pick$1023 \$1024 + connect \wrflag_logical0_o_0 \$1021 + connect \addr_en$1018 \$1019 + connect \wp$1015 \$1016 + connect \fus_cu_wr__go_i$97 [4] \wr_pick_rise$1014 + connect \fus_cu_wr__go_i$97 [3] \wr_pick_rise$1013 + connect \fus_cu_wr__go_i$97 [2] \wr_pick_rise$1012 + connect \fus_cu_wr__go_i$97 [1] \wr_pick_rise$1011 + connect \fus_cu_wr__go_i$97 [0] \wr_pick_rise$1006 + connect \wr_pick_rise$1006 \$1009 + connect \wr_pick$1002 \$1003 + connect \wrflag_trap0_o_0 \$1000 + connect \addr_en$997 \$998 + connect \wp$994 \$995 + connect \fus_cu_wr__go_i$94 [2] \wr_pick_rise$993 + connect \fus_cu_wr__go_i$94 [1] \wr_pick_rise$992 + connect \fus_cu_wr__go_i$94 [0] \wr_pick_rise$987 + connect \wr_pick_rise$987 \$990 + connect \wr_pick$983 \$984 + connect \wrflag_cr0_o_0 \$981 + connect \addr_en \$979 + connect \wp \$977 + connect \fus_cu_wr__go_i [4] \wr_pick_rise$976 + connect \fus_cu_wr__go_i [3] \wr_pick_rise$975 + connect \fus_cu_wr__go_i [2] \wr_pick_rise$974 + connect \fus_cu_wr__go_i [1] \wr_pick_rise$973 + connect \fus_cu_wr__go_i [0] \wr_pick_rise + connect \wr_pick_rise \$971 + connect \wr_pick \$967 + connect \wrpick_INT_o_i [9] \$965 + connect \wrpick_INT_o_i [8] \$963 + connect \wrpick_INT_o_i [7] \$961 + connect \wrpick_INT_o_i [6] \$959 + connect \wrpick_INT_o_i [5] \$957 + connect \wrpick_INT_o_i [4] \$955 + connect \wrpick_INT_o_i [3] \$953 + connect \wrpick_INT_o_i [2] \$951 + connect \wrpick_INT_o_i [1] \$949 + connect \wrpick_INT_o_i [0] \$947 + connect \wrflag_alu0_o_0 \$945 + connect \spr_spr1__ren \$943 + connect \spr_spr1__addr \addr_en_SPR_spr1_spr0_0 [6:0] + connect \addr_en_SPR_spr1_spr0_0 \$941 + connect \rp_SPR_spr1_spr0_0 \$939 + connect \rdpick_SPR_spr1_i \pick_SPR_spr1_spr0_0 + connect \pick_SPR_spr1_spr0_0 \$937 + connect \rdflag_SPR_spr1_0 \core_spr1_ok + connect \fast_src2__ren \$929 + connect \fast_src2__addr \$927 + connect \addr_en_FAST_fast2_trap0_1 \$925 + connect \rp_FAST_fast2_trap0_1 \$923 + connect \pick_FAST_fast2_trap0_1 \$921 + connect \addr_en_FAST_fast2_branch0_0 \$913 + connect \rp_FAST_fast2_branch0_0 \$911 + connect \rdpick_FAST_fast2_i [1] \pick_FAST_fast2_trap0_1 + connect \rdpick_FAST_fast2_i [0] \pick_FAST_fast2_branch0_0 + connect \pick_FAST_fast2_branch0_0 \$909 + connect \rdflag_FAST_fast2_0 \core_fast2_ok + connect \fast_src1__ren \$901 + connect \fast_src1__addr \$899 + connect \addr_en_FAST_fast1_spr0_2 \$895 + connect \rp_FAST_fast1_spr0_2 \$893 + connect \pick_FAST_fast1_spr0_2 \$891 + connect \addr_en_FAST_fast1_trap0_1 \$883 + connect \rp_FAST_fast1_trap0_1 \$881 + connect \pick_FAST_fast1_trap0_1 \$879 + connect \addr_en_FAST_fast1_branch0_0 \$871 + connect \rp_FAST_fast1_branch0_0 \$869 + connect \rdpick_FAST_fast1_i [2] \pick_FAST_fast1_spr0_2 + connect \rdpick_FAST_fast1_i [1] \pick_FAST_fast1_trap0_1 + connect \rdpick_FAST_fast1_i [0] \pick_FAST_fast1_branch0_0 + connect \pick_FAST_fast1_branch0_0 \$867 + connect \rdflag_FAST_fast1_0 \core_fast1_ok + connect \cr_src3__ren \addr_en_CR_cr_c_cr0_0 [7:0] + connect \addr_en_CR_cr_c_cr0_0 \$859 + connect \rp_CR_cr_c_cr0_0 \$853 + connect \rdpick_CR_cr_c_i \pick_CR_cr_c_cr0_0 + connect \pick_CR_cr_c_cr0_0 \$851 + connect \rdflag_CR_cr_c_0 \core_cr_in2_ok$2 + connect \cr_src2__ren \addr_en_CR_cr_b_cr0_0 [7:0] + connect \addr_en_CR_cr_b_cr0_0 \$843 + connect \rp_CR_cr_b_cr0_0 \$837 + connect \rdpick_CR_cr_b_i \pick_CR_cr_b_cr0_0 + connect \pick_CR_cr_b_cr0_0 \$835 + connect \rdflag_CR_cr_b_0 \core_cr_in2_ok + connect \cr_src1__ren \$827 [7:0] + connect \addr_en_CR_cr_a_branch0_1 \$824 + connect \rp_CR_cr_a_branch0_1 \$818 + connect \fus_cu_rd__go_i$82 [1] \dp_FAST_fast2_branch0_0 + connect \fus_cu_rd__go_i$82 [0] \dp_FAST_fast1_branch0_0 + connect \fus_cu_rd__go_i$82 [2] \dp_CR_cr_a_branch0_1 + connect \pick_CR_cr_a_branch0_1 \$816 + connect \addr_en_CR_cr_a_cr0_0 \$808 + connect \rp_CR_cr_a_cr0_0 \$802 + connect \rdpick_CR_cr_a_i [1] \pick_CR_cr_a_branch0_1 + connect \rdpick_CR_cr_a_i [0] \pick_CR_cr_a_cr0_0 + connect \pick_CR_cr_a_cr0_0 \$800 + connect \rdflag_CR_cr_a_0 \core_cr_in1_ok + connect \cr_full_rd__ren \addr_en_CR_full_cr_cr0_0 + connect \addr_en_CR_full_cr_cr0_0 \$792 + connect \rp_CR_full_cr_cr0_0 \$790 + connect \rdpick_CR_full_cr_i \pick_CR_full_cr_cr0_0 + connect \pick_CR_full_cr_cr0_0 \$788 + connect \rdflag_CR_full_cr_0 \core_core_cr_rd_ok + connect \xer_src3__ren \addr_en_XER_xer_ov_spr0_0 + connect \addr_en_XER_xer_ov_spr0_0 \$780 + connect \rp_XER_xer_ov_spr0_0 \$778 + connect \rdpick_XER_xer_ov_i \pick_XER_xer_ov_spr0_0 + connect \pick_XER_xer_ov_spr0_0 \$776 + connect \rdflag_XER_xer_ov_0 \$768 + connect \xer_src2__ren \$756 + connect \addr_en_XER_xer_ca_shiftrot0_2 \$754 + connect \rp_XER_xer_ca_shiftrot0_2 \$752 + connect \pick_XER_xer_ca_shiftrot0_2 \$750 + connect \addr_en_XER_xer_ca_spr0_1 \$742 + connect \rp_XER_xer_ca_spr0_1 \$740 + connect \pick_XER_xer_ca_spr0_1 \$738 + connect \addr_en_XER_xer_ca_alu0_0 \$730 + connect \rp_XER_xer_ca_alu0_0 \$728 + connect \rdpick_XER_xer_ca_i [2] \pick_XER_xer_ca_shiftrot0_2 + connect \rdpick_XER_xer_ca_i [1] \pick_XER_xer_ca_spr0_1 + connect \rdpick_XER_xer_ca_i [0] \pick_XER_xer_ca_alu0_0 + connect \pick_XER_xer_ca_alu0_0 \$726 + connect \rdflag_XER_xer_ca_0 \$718 + connect \xer_src1__ren \$700 + connect \addr_en_XER_xer_so_shiftrot0_5 \$698 + connect \rp_XER_xer_so_shiftrot0_5 \$696 + connect \pick_XER_xer_so_shiftrot0_5 \$694 + connect \addr_en_XER_xer_so_mul0_4 \$686 + connect \rp_XER_xer_so_mul0_4 \$684 + connect \pick_XER_xer_so_mul0_4 \$682 + connect \addr_en_XER_xer_so_div0_3 \$674 + connect \rp_XER_xer_so_div0_3 \$672 + connect \pick_XER_xer_so_div0_3 \$670 + connect \addr_en_XER_xer_so_spr0_2 \$662 + connect \rp_XER_xer_so_spr0_2 \$660 + connect \pick_XER_xer_so_spr0_2 \$658 + connect \addr_en_XER_xer_so_logical0_1 \$650 + connect \rp_XER_xer_so_logical0_1 \$648 + connect \pick_XER_xer_so_logical0_1 \$646 + connect \addr_en_XER_xer_so_alu0_0 \$638 + connect \rp_XER_xer_so_alu0_0 \$636 + connect \rdpick_XER_xer_so_i [5] \pick_XER_xer_so_shiftrot0_5 + connect \rdpick_XER_xer_so_i [4] \pick_XER_xer_so_mul0_4 + connect \rdpick_XER_xer_so_i [3] \pick_XER_xer_so_div0_3 + connect \rdpick_XER_xer_so_i [2] \pick_XER_xer_so_spr0_2 + connect \rdpick_XER_xer_so_i [1] \pick_XER_xer_so_logical0_1 + connect \rdpick_XER_xer_so_i [0] \pick_XER_xer_so_alu0_0 + connect \pick_XER_xer_so_alu0_0 \$634 + connect \rdflag_XER_xer_so_0 \$626 + connect \int_src3__ren \$614 + connect \int_src3__addr \$612 [4:0] + connect \addr_en_INT_rc_ldst0_1 \$609 + connect \rp_INT_rc_ldst0_1 \$607 + connect \pick_INT_rc_ldst0_1 \$605 + connect \addr_en_INT_rc_shiftrot0_0 \$597 + connect \rp_INT_rc_shiftrot0_0 \$595 + connect \rdpick_INT_rc_i [1] \pick_INT_rc_ldst0_1 + connect \rdpick_INT_rc_i [0] \pick_INT_rc_shiftrot0_0 + connect \pick_INT_rc_shiftrot0_0 \$593 + connect \rdflag_INT_rc_0 \core_reg3_ok + connect \int_src2__ren \$585 + connect \int_src2__addr \$583 [4:0] + connect \addr_en_INT_rb_ldst0_7 \$568 + connect \rp_INT_rb_ldst0_7 \$566 + connect \pick_INT_rb_ldst0_7 \$564 + connect \addr_en_INT_rb_shiftrot0_6 \$556 + connect \rp_INT_rb_shiftrot0_6 \$554 + connect \pick_INT_rb_shiftrot0_6 \$552 + connect \addr_en_INT_rb_mul0_5 \$544 + connect \rp_INT_rb_mul0_5 \$542 + connect \pick_INT_rb_mul0_5 \$540 + connect \addr_en_INT_rb_div0_4 \$532 + connect \rp_INT_rb_div0_4 \$530 + connect \pick_INT_rb_div0_4 \$528 + connect \addr_en_INT_rb_logical0_3 \$520 + connect \rp_INT_rb_logical0_3 \$518 + connect \pick_INT_rb_logical0_3 \$516 + connect \addr_en_INT_rb_trap0_2 \$508 + connect \rp_INT_rb_trap0_2 \$506 + connect \pick_INT_rb_trap0_2 \$504 + connect \addr_en_INT_rb_cr0_1 \$496 + connect \rp_INT_rb_cr0_1 \$494 + connect \pick_INT_rb_cr0_1 \$492 + connect \addr_en_INT_rb_alu0_0 \$484 + connect \rp_INT_rb_alu0_0 \$482 + connect \rdpick_INT_rb_i [7] \pick_INT_rb_ldst0_7 + connect \rdpick_INT_rb_i [6] \pick_INT_rb_shiftrot0_6 + connect \rdpick_INT_rb_i [5] \pick_INT_rb_mul0_5 + connect \rdpick_INT_rb_i [4] \pick_INT_rb_div0_4 + connect \rdpick_INT_rb_i [3] \pick_INT_rb_logical0_3 + connect \rdpick_INT_rb_i [2] \pick_INT_rb_trap0_2 + connect \rdpick_INT_rb_i [1] \pick_INT_rb_cr0_1 + connect \rdpick_INT_rb_i [0] \pick_INT_rb_alu0_0 + connect \pick_INT_rb_alu0_0 \$480 + connect \rdflag_INT_rb_0 \core_reg2_ok + connect \int_src1__ren \$472 + connect \int_src1__addr \$470 [4:0] + connect \addr_en_INT_ra_ldst0_8 \$453 + connect \rp_INT_ra_ldst0_8 \$451 + connect \fus_cu_rd__go_i$62 [2] \dp_INT_rc_ldst0_1 + connect \fus_cu_rd__go_i$62 [1] \dp_INT_rb_ldst0_7 + connect \fus_cu_rd__go_i$62 [0] \dp_INT_ra_ldst0_8 + connect \pick_INT_ra_ldst0_8 \$449 + connect \addr_en_INT_ra_shiftrot0_7 \$441 + connect \rp_INT_ra_shiftrot0_7 \$439 + connect \fus_cu_rd__go_i$59 [4] \dp_XER_xer_ca_shiftrot0_2 + connect \fus_cu_rd__go_i$59 [3] \dp_XER_xer_so_shiftrot0_5 + connect \fus_cu_rd__go_i$59 [2] \dp_INT_rc_shiftrot0_0 + connect \fus_cu_rd__go_i$59 [1] \dp_INT_rb_shiftrot0_6 + connect \fus_cu_rd__go_i$59 [0] \dp_INT_ra_shiftrot0_7 + connect \pick_INT_ra_shiftrot0_7 \$437 + connect \addr_en_INT_ra_mul0_6 \$429 + connect \rp_INT_ra_mul0_6 \$427 + connect \fus_cu_rd__go_i$56 [2] \dp_XER_xer_so_mul0_4 + connect \fus_cu_rd__go_i$56 [1] \dp_INT_rb_mul0_5 + connect \fus_cu_rd__go_i$56 [0] \dp_INT_ra_mul0_6 + connect \pick_INT_ra_mul0_6 \$425 + connect \addr_en_INT_ra_div0_5 \$417 + connect \rp_INT_ra_div0_5 \$415 + connect \fus_cu_rd__go_i$53 [2] \dp_XER_xer_so_div0_3 + connect \fus_cu_rd__go_i$53 [1] \dp_INT_rb_div0_4 + connect \fus_cu_rd__go_i$53 [0] \dp_INT_ra_div0_5 + connect \pick_INT_ra_div0_5 \$413 + connect \addr_en_INT_ra_spr0_4 \$405 + connect \rp_INT_ra_spr0_4 \$403 + connect \fus_cu_rd__go_i$50 [1] \dp_SPR_spr1_spr0_0 + connect \fus_cu_rd__go_i$50 [2] \dp_FAST_fast1_spr0_2 + connect \fus_cu_rd__go_i$50 [4] \dp_XER_xer_ov_spr0_0 + connect \fus_cu_rd__go_i$50 [5] \dp_XER_xer_ca_spr0_1 + connect \fus_cu_rd__go_i$50 [3] \dp_XER_xer_so_spr0_2 + connect \fus_cu_rd__go_i$50 [0] \dp_INT_ra_spr0_4 + connect \pick_INT_ra_spr0_4 \$401 + connect \addr_en_INT_ra_logical0_3 \$393 + connect \rp_INT_ra_logical0_3 \$391 + connect \fus_cu_rd__go_i$47 [2] \dp_XER_xer_so_logical0_1 + connect \fus_cu_rd__go_i$47 [1] \dp_INT_rb_logical0_3 + connect \fus_cu_rd__go_i$47 [0] \dp_INT_ra_logical0_3 + connect \pick_INT_ra_logical0_3 \$389 + connect \addr_en_INT_ra_trap0_2 \$381 + connect \rp_INT_ra_trap0_2 \$379 + connect \fus_cu_rd__go_i$44 [3] \dp_FAST_fast2_trap0_1 + connect \fus_cu_rd__go_i$44 [2] \dp_FAST_fast1_trap0_1 + connect \fus_cu_rd__go_i$44 [1] \dp_INT_rb_trap0_2 + connect \fus_cu_rd__go_i$44 [0] \dp_INT_ra_trap0_2 + connect \pick_INT_ra_trap0_2 \$377 + connect \addr_en_INT_ra_cr0_1 \$369 + connect \rp_INT_ra_cr0_1 \$367 + connect \fus_cu_rd__go_i$41 [5] \dp_CR_cr_c_cr0_0 + connect \fus_cu_rd__go_i$41 [4] \dp_CR_cr_b_cr0_0 + connect \fus_cu_rd__go_i$41 [3] \dp_CR_cr_a_cr0_0 + connect \fus_cu_rd__go_i$41 [2] \dp_CR_full_cr_cr0_0 + connect \fus_cu_rd__go_i$41 [1] \dp_INT_rb_cr0_1 + connect \fus_cu_rd__go_i$41 [0] \dp_INT_ra_cr0_1 + connect \pick_INT_ra_cr0_1 \$365 + connect \addr_en_INT_ra_alu0_0 \$357 + connect \rp_INT_ra_alu0_0 \$355 + connect \fus_cu_rd__go_i [3] \dp_XER_xer_ca_alu0_0 + connect \fus_cu_rd__go_i [2] \dp_XER_xer_so_alu0_0 + connect \fus_cu_rd__go_i [1] \dp_INT_rb_alu0_0 + connect \fus_cu_rd__go_i [0] \dp_INT_ra_alu0_0 + connect \rdpick_INT_ra_i [8] \pick_INT_ra_ldst0_8 + connect \rdpick_INT_ra_i [7] \pick_INT_ra_shiftrot0_7 + connect \rdpick_INT_ra_i [6] \pick_INT_ra_mul0_6 + connect \rdpick_INT_ra_i [5] \pick_INT_ra_div0_5 + connect \rdpick_INT_ra_i [4] \pick_INT_ra_spr0_4 + connect \rdpick_INT_ra_i [3] \pick_INT_ra_logical0_3 + connect \rdpick_INT_ra_i [2] \pick_INT_ra_trap0_2 + connect \rdpick_INT_ra_i [1] \pick_INT_ra_cr0_1 + connect \rdpick_INT_ra_i [0] \pick_INT_ra_alu0_0 + connect \pick_INT_ra_alu0_0 \$353 + connect \rdflag_INT_ra_0 \core_reg1_ok + connect \en_ldst0 \$212 + connect \en_shiftrot0 \$208 + connect \en_mul0 \$204 + connect \en_div0 \$200 + connect \en_spr0 \$196 + connect \en_logical0 \$192 + connect \en_trap0 \$188 + connect \en_branch0 \$184 + connect \en_cr0 \$180 + connect \fu_enable [9] \en_ldst0 + connect \fu_enable [8] \en_shiftrot0 + connect \fu_enable [7] \en_mul0 + connect \fu_enable [6] \en_div0 + connect \fu_enable [5] \en_spr0 + connect \fu_enable [4] \en_logical0 + connect \fu_enable [3] \en_trap0 + connect \fu_enable [2] \en_branch0 + connect \fu_enable [1] \en_cr0 + connect \fu_enable [0] \en_alu0 + connect \en_alu0 \$176 + connect \dec_LDST_bigendian \bigendian_i + connect \dec_LDST_raw_opcode_in \raw_insn_i + connect \dec_SHIFT_ROT_bigendian \bigendian_i + connect \dec_SHIFT_ROT_raw_opcode_in \raw_insn_i + connect \dec_MUL_bigendian \bigendian_i + connect \dec_MUL_raw_opcode_in \raw_insn_i + connect \dec_DIV_bigendian \bigendian_i + connect \dec_DIV_raw_opcode_in \raw_insn_i + connect \dec_SPR_bigendian \bigendian_i + connect \dec_SPR_raw_opcode_in \raw_insn_i + connect \dec_LOGICAL_bigendian \bigendian_i + connect \dec_LOGICAL_raw_opcode_in \raw_insn_i + connect \dec_BRANCH_bigendian \bigendian_i + connect \dec_BRANCH_raw_opcode_in \raw_insn_i + connect \dec_CR_bigendian \bigendian_i + connect \dec_CR_raw_opcode_in \raw_insn_i + connect \dec_ALU_bigendian \bigendian_i + connect \dec_ALU_raw_opcode_in \raw_insn_i +end +attribute \src "libresoc.v:48838.1-49471.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.cr" +attribute \generator "nMigen" +module \cr + attribute \src "libresoc.v:48839.7-48839.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:49385.3-49393.6" + wire width 8 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"/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 \reg_5_dest15__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire \reg_5_dest15__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 \reg_5_dest25__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire \reg_5_dest25__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 \reg_5_r25__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire \reg_5_r25__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 \reg_5_r5__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire \reg_5_r5__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 \reg_5_src15__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire \reg_5_src15__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 \reg_5_src25__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire \reg_5_src25__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 \reg_5_src35__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire \reg_5_src35__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 \reg_5_w5__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire \reg_5_w5__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 \reg_6_dest16__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire \reg_6_dest16__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 \reg_6_dest26__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire \reg_6_dest26__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 \reg_6_r26__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire \reg_6_r26__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 \reg_6_r6__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire \reg_6_r6__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 \reg_6_src16__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire \reg_6_src16__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 \reg_6_src26__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire \reg_6_src26__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 \reg_6_src36__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire \reg_6_src36__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 \reg_6_w6__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire \reg_6_w6__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 \reg_7_dest17__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire \reg_7_dest17__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 \reg_7_dest27__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire \reg_7_dest27__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 \reg_7_r27__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire \reg_7_r27__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 \reg_7_r7__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire \reg_7_r7__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 \reg_7_src17__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire \reg_7_src17__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 \reg_7_src27__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire \reg_7_src27__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 \reg_7_src37__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire \reg_7_src37__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 \reg_7_w7__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire \reg_7_w7__wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" + wire width 8 \ren_delay + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" + wire width 8 \ren_delay$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" + wire width 8 \ren_delay$17$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" + wire width 8 \ren_delay$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" + wire width 8 \ren_delay$34$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" + wire width 8 \ren_delay$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 output 6 \src1__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 8 input 7 \src1__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 output 8 \src2__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 8 input 9 \src2__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 output 10 \src3__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 8 input 11 \src3__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 8 input 15 \wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 8 \wen$51 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" + cell $or $or$libresoc.v:49195$3016 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \reg_4_src14__data_o + connect \B \reg_5_src15__data_o + connect \Y $or$libresoc.v:49195$3016_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" + cell $or $or$libresoc.v:49196$3017 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \reg_6_src16__data_o + connect \B \reg_7_src17__data_o + connect \Y $or$libresoc.v:49196$3017_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" + cell $or $or$libresoc.v:49197$3018 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \$9 + connect \B \$11 + connect \Y $or$libresoc.v:49197$3018_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" + cell $or $or$libresoc.v:49198$3019 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \$7 + connect \B \$13 + connect \Y $or$libresoc.v:49198$3019_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" + cell $or $or$libresoc.v:49201$3022 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \reg_0_src20__data_o + connect \B \reg_1_src21__data_o + connect \Y $or$libresoc.v:49201$3022_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" + cell $or $or$libresoc.v:49202$3023 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \reg_2_src22__data_o + connect \B \reg_3_src23__data_o + connect \Y $or$libresoc.v:49202$3023_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" + cell $or $or$libresoc.v:49203$3024 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \$20 + connect \B \$22 + connect \Y $or$libresoc.v:49203$3024_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" + cell $or $or$libresoc.v:49204$3025 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \reg_4_src24__data_o + connect \B \reg_5_src25__data_o + connect \Y $or$libresoc.v:49204$3025_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" + cell $or $or$libresoc.v:49205$3026 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \reg_6_src26__data_o + connect \B \reg_7_src27__data_o + connect \Y $or$libresoc.v:49205$3026_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" + cell $or $or$libresoc.v:49206$3027 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \$26 + connect \B \$28 + connect \Y $or$libresoc.v:49206$3027_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" + cell $or $or$libresoc.v:49207$3028 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \$24 + connect \B \$30 + connect \Y $or$libresoc.v:49207$3028_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" + cell $or $or$libresoc.v:49209$3030 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \reg_0_src30__data_o + connect \B \reg_1_src31__data_o + connect \Y $or$libresoc.v:49209$3030_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" + cell $or $or$libresoc.v:49210$3031 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \reg_0_src10__data_o + connect \B \reg_1_src11__data_o + connect \Y $or$libresoc.v:49210$3031_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" + cell $or $or$libresoc.v:49211$3032 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \reg_2_src32__data_o + connect \B \reg_3_src33__data_o + connect \Y $or$libresoc.v:49211$3032_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" + cell $or $or$libresoc.v:49212$3033 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \$37 + connect \B \$39 + connect \Y $or$libresoc.v:49212$3033_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" + cell $or $or$libresoc.v:49213$3034 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \reg_4_src34__data_o + connect \B \reg_5_src35__data_o + connect \Y $or$libresoc.v:49213$3034_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" + cell $or $or$libresoc.v:49214$3035 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \reg_6_src36__data_o + connect \B \reg_7_src37__data_o + connect \Y $or$libresoc.v:49214$3035_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" + cell $or $or$libresoc.v:49215$3036 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \$43 + connect \B \$45 + connect \Y $or$libresoc.v:49215$3036_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" + cell $or $or$libresoc.v:49216$3037 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \$41 + connect \B \$47 + connect \Y $or$libresoc.v:49216$3037_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" + cell $or $or$libresoc.v:49217$3038 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \reg_2_src12__data_o + connect \B \reg_3_src13__data_o + connect \Y $or$libresoc.v:49217$3038_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" + cell $or $or$libresoc.v:49218$3039 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \$3 + connect \B \$5 + connect \Y $or$libresoc.v:49218$3039_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + cell $reduce_or $reduce_or$libresoc.v:49199$3020 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ren_delay$17 + connect \Y $reduce_or$libresoc.v:49199$3020_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + cell $reduce_or $reduce_or$libresoc.v:49200$3021 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ren_delay + connect \Y $reduce_or$libresoc.v:49200$3021_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + cell $reduce_or $reduce_or$libresoc.v:49208$3029 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ren_delay$34 + connect \Y $reduce_or$libresoc.v:49208$3029_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:49225.9-49244.4" + cell \reg_0 \reg_0 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \dest10__data_i \reg_0_dest10__data_i + connect \dest10__wen \reg_0_dest10__wen + connect \dest20__data_i \reg_0_dest20__data_i + connect \dest20__wen \reg_0_dest20__wen + connect \r0__data_o \reg_0_r0__data_o + connect \r0__ren \reg_0_r0__ren + connect \r20__data_o \reg_0_r20__data_o + connect \r20__ren \reg_0_r20__ren + connect \src10__data_o \reg_0_src10__data_o + connect \src10__ren \reg_0_src10__ren + connect \src20__data_o \reg_0_src20__data_o + connect \src20__ren \reg_0_src20__ren + connect \src30__data_o \reg_0_src30__data_o + connect \src30__ren \reg_0_src30__ren + connect \w0__data_i \reg_0_w0__data_i + connect \w0__wen \reg_0_w0__wen + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:49245.9-49264.4" + cell \reg_1 \reg_1 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \dest11__data_i \reg_1_dest11__data_i + connect \dest11__wen \reg_1_dest11__wen + connect \dest21__data_i \reg_1_dest21__data_i + connect \dest21__wen \reg_1_dest21__wen + connect \r1__data_o \reg_1_r1__data_o + connect \r1__ren \reg_1_r1__ren + connect \r21__data_o \reg_1_r21__data_o + connect \r21__ren \reg_1_r21__ren + connect \src11__data_o \reg_1_src11__data_o + connect \src11__ren \reg_1_src11__ren + connect \src21__data_o \reg_1_src21__data_o + connect \src21__ren \reg_1_src21__ren + connect \src31__data_o \reg_1_src31__data_o + connect \src31__ren \reg_1_src31__ren + connect \w1__data_i \reg_1_w1__data_i + connect \w1__wen \reg_1_w1__wen + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:49265.9-49284.4" + cell \reg_2 \reg_2 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \dest12__data_i \reg_2_dest12__data_i + connect \dest12__wen \reg_2_dest12__wen + connect \dest22__data_i \reg_2_dest22__data_i + connect \dest22__wen \reg_2_dest22__wen + connect \r22__data_o \reg_2_r22__data_o + connect \r22__ren \reg_2_r22__ren + connect \r2__data_o \reg_2_r2__data_o + connect \r2__ren \reg_2_r2__ren + connect \src12__data_o \reg_2_src12__data_o + connect \src12__ren \reg_2_src12__ren + connect \src22__data_o \reg_2_src22__data_o + connect \src22__ren \reg_2_src22__ren + connect \src32__data_o \reg_2_src32__data_o + connect \src32__ren \reg_2_src32__ren + connect \w2__data_i \reg_2_w2__data_i + connect \w2__wen \reg_2_w2__wen + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:49285.9-49304.4" + cell \reg_3 \reg_3 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \dest13__data_i \reg_3_dest13__data_i + connect \dest13__wen \reg_3_dest13__wen + connect \dest23__data_i \reg_3_dest23__data_i + connect \dest23__wen \reg_3_dest23__wen + connect \r23__data_o \reg_3_r23__data_o + connect \r23__ren \reg_3_r23__ren + connect \r3__data_o \reg_3_r3__data_o + connect \r3__ren \reg_3_r3__ren + connect \src13__data_o \reg_3_src13__data_o + connect \src13__ren \reg_3_src13__ren + connect \src23__data_o \reg_3_src23__data_o + connect \src23__ren \reg_3_src23__ren + connect \src33__data_o \reg_3_src33__data_o + connect \src33__ren \reg_3_src33__ren + connect \w3__data_i \reg_3_w3__data_i + connect \w3__wen \reg_3_w3__wen + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:49305.9-49324.4" + cell \reg_4 \reg_4 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \dest14__data_i \reg_4_dest14__data_i + connect \dest14__wen \reg_4_dest14__wen + connect \dest24__data_i \reg_4_dest24__data_i + connect \dest24__wen \reg_4_dest24__wen + connect \r24__data_o \reg_4_r24__data_o + connect \r24__ren \reg_4_r24__ren + connect \r4__data_o \reg_4_r4__data_o + connect \r4__ren \reg_4_r4__ren + connect \src14__data_o \reg_4_src14__data_o + connect \src14__ren \reg_4_src14__ren + connect \src24__data_o \reg_4_src24__data_o + connect \src24__ren \reg_4_src24__ren + connect \src34__data_o \reg_4_src34__data_o + connect \src34__ren \reg_4_src34__ren + connect \w4__data_i \reg_4_w4__data_i + connect \w4__wen \reg_4_w4__wen + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:49325.9-49344.4" + cell \reg_5 \reg_5 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \dest15__data_i \reg_5_dest15__data_i + connect \dest15__wen \reg_5_dest15__wen + connect \dest25__data_i \reg_5_dest25__data_i + connect \dest25__wen \reg_5_dest25__wen + connect \r25__data_o \reg_5_r25__data_o + connect \r25__ren \reg_5_r25__ren + connect \r5__data_o \reg_5_r5__data_o + connect \r5__ren \reg_5_r5__ren + connect \src15__data_o \reg_5_src15__data_o + connect \src15__ren \reg_5_src15__ren + connect \src25__data_o \reg_5_src25__data_o + connect \src25__ren \reg_5_src25__ren + connect \src35__data_o \reg_5_src35__data_o + connect \src35__ren \reg_5_src35__ren + connect \w5__data_i \reg_5_w5__data_i + connect \w5__wen \reg_5_w5__wen + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:49345.9-49364.4" + cell \reg_6 \reg_6 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \dest16__data_i \reg_6_dest16__data_i + connect \dest16__wen \reg_6_dest16__wen + connect \dest26__data_i \reg_6_dest26__data_i + connect \dest26__wen \reg_6_dest26__wen + connect \r26__data_o \reg_6_r26__data_o + connect \r26__ren \reg_6_r26__ren + connect \r6__data_o \reg_6_r6__data_o + connect \r6__ren \reg_6_r6__ren + connect \src16__data_o \reg_6_src16__data_o + connect \src16__ren \reg_6_src16__ren + connect \src26__data_o \reg_6_src26__data_o + connect \src26__ren \reg_6_src26__ren + connect \src36__data_o \reg_6_src36__data_o + connect \src36__ren \reg_6_src36__ren + connect \w6__data_i \reg_6_w6__data_i + connect \w6__wen \reg_6_w6__wen + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:49365.9-49384.4" + cell \reg_7 \reg_7 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \dest17__data_i \reg_7_dest17__data_i + connect \dest17__wen \reg_7_dest17__wen + connect \dest27__data_i \reg_7_dest27__data_i + connect \dest27__wen \reg_7_dest27__wen + connect \r27__data_o \reg_7_r27__data_o + connect \r27__ren \reg_7_r27__ren + connect \r7__data_o \reg_7_r7__data_o + connect \r7__ren \reg_7_r7__ren + connect \src17__data_o \reg_7_src17__data_o + connect \src17__ren \reg_7_src17__ren + connect \src27__data_o \reg_7_src27__data_o + connect \src27__ren \reg_7_src27__ren + connect \src37__data_o \reg_7_src37__data_o + connect \src37__ren \reg_7_src37__ren + connect \w7__data_i \reg_7_w7__data_i + connect \w7__wen \reg_7_w7__wen + end + attribute \src "libresoc.v:48839.7-48839.20" + process $proc$libresoc.v:48839$3057 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:49165.13-49165.30" + process $proc$libresoc.v:49165$3058 + assign { } { } + assign $1\ren_delay[7:0] 8'00000000 + sync always + sync init + update \ren_delay $1\ren_delay[7:0] + end + attribute \src "libresoc.v:49167.13-49167.35" + process $proc$libresoc.v:49167$3059 + assign { } { } + assign $0\ren_delay$17[7:0]$3060 8'00000000 + sync always + sync init + update \ren_delay$17 $0\ren_delay$17[7:0]$3060 + end + attribute \src "libresoc.v:49171.13-49171.35" + process $proc$libresoc.v:49171$3061 + assign { } { } + assign $0\ren_delay$34[7:0]$3062 8'00000000 + sync always + sync init + update \ren_delay$34 $0\ren_delay$34[7:0]$3062 + end + attribute \src "libresoc.v:49219.3-49220.43" + process $proc$libresoc.v:49219$3040 + assign { } { } + assign $0\ren_delay$34[7:0]$3041 \ren_delay$34$next + sync posedge \coresync_clk + update \ren_delay$34 $0\ren_delay$34[7:0]$3041 + end + attribute \src "libresoc.v:49221.3-49222.43" + process $proc$libresoc.v:49221$3042 + assign { } { } + assign $0\ren_delay$17[7:0]$3043 \ren_delay$17$next + sync posedge \coresync_clk + update \ren_delay$17 $0\ren_delay$17[7:0]$3043 + end + attribute \src "libresoc.v:49223.3-49224.35" + process $proc$libresoc.v:49223$3044 + assign { } { } + assign $0\ren_delay[7:0] \ren_delay$next + sync posedge \coresync_clk + update \ren_delay $0\ren_delay[7:0] + end + attribute \src "libresoc.v:49385.3-49393.6" + process $proc$libresoc.v:49385$3045 + assign { } { } + assign { } { } + assign $0\ren_delay$17$next[7:0]$3046 $1\ren_delay$17$next[7:0]$3047 + attribute \src "libresoc.v:49386.5-49386.29" + switch \initial + attribute \src "libresoc.v:49386.9-49386.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ren_delay$17$next[7:0]$3047 8'00000000 + case + assign $1\ren_delay$17$next[7:0]$3047 \src2__ren + end + sync always + update \ren_delay$17$next $0\ren_delay$17$next[7:0]$3046 + end + attribute \src "libresoc.v:49394.3-49403.6" + process $proc$libresoc.v:49394$3048 + assign { } { } + assign { } { } + assign $0\src2__data_o[3:0] $1\src2__data_o[3:0] + attribute \src "libresoc.v:49395.5-49395.29" + switch \initial + attribute \src "libresoc.v:49395.9-49395.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" + switch \$18 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src2__data_o[3:0] \$32 + case + assign $1\src2__data_o[3:0] 4'0000 + end + sync always + update \src2__data_o $0\src2__data_o[3:0] + end + attribute \src "libresoc.v:49404.3-49412.6" + process $proc$libresoc.v:49404$3049 + assign { } { } + assign { } { } + assign $0\ren_delay$34$next[7:0]$3050 $1\ren_delay$34$next[7:0]$3051 + attribute \src "libresoc.v:49405.5-49405.29" + switch \initial + attribute \src "libresoc.v:49405.9-49405.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ren_delay$34$next[7:0]$3051 8'00000000 + case + assign $1\ren_delay$34$next[7:0]$3051 \src3__ren + end + sync always + update \ren_delay$34$next $0\ren_delay$34$next[7:0]$3050 + end + attribute \src "libresoc.v:49413.3-49422.6" + process $proc$libresoc.v:49413$3052 + assign { } { } + assign { } { } + assign $0\src3__data_o[3:0] $1\src3__data_o[3:0] + attribute \src "libresoc.v:49414.5-49414.29" + switch \initial + attribute \src "libresoc.v:49414.9-49414.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" + switch \$35 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src3__data_o[3:0] \$49 + case + assign $1\src3__data_o[3:0] 4'0000 + end + sync always + update \src3__data_o $0\src3__data_o[3:0] + end + attribute \src "libresoc.v:49423.3-49431.6" + process $proc$libresoc.v:49423$3053 + assign { } { } + assign { } { } + assign $0\ren_delay$next[7:0]$3054 $1\ren_delay$next[7:0]$3055 + attribute \src "libresoc.v:49424.5-49424.29" + switch \initial + attribute \src "libresoc.v:49424.9-49424.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ren_delay$next[7:0]$3055 8'00000000 + case + assign $1\ren_delay$next[7:0]$3055 \src1__ren + end + sync always + update \ren_delay$next $0\ren_delay$next[7:0]$3054 + end + attribute \src "libresoc.v:49432.3-49441.6" + process $proc$libresoc.v:49432$3056 + assign { } { } + assign { } { } + assign $0\src1__data_o[3:0] $1\src1__data_o[3:0] + attribute \src "libresoc.v:49433.5-49433.29" + switch \initial + attribute \src "libresoc.v:49433.9-49433.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" + switch \$1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src1__data_o[3:0] \$15 + case + assign $1\src1__data_o[3:0] 4'0000 + end + sync always + update \src1__data_o $0\src1__data_o[3:0] + end + connect \$9 $or$libresoc.v:49195$3016_Y + connect \$11 $or$libresoc.v:49196$3017_Y + connect \$13 $or$libresoc.v:49197$3018_Y + connect \$15 $or$libresoc.v:49198$3019_Y + connect \$18 $reduce_or$libresoc.v:49199$3020_Y + connect \$1 $reduce_or$libresoc.v:49200$3021_Y + connect \$20 $or$libresoc.v:49201$3022_Y + connect \$22 $or$libresoc.v:49202$3023_Y + connect \$24 $or$libresoc.v:49203$3024_Y + connect \$26 $or$libresoc.v:49204$3025_Y + connect \$28 $or$libresoc.v:49205$3026_Y + connect \$30 $or$libresoc.v:49206$3027_Y + connect \$32 $or$libresoc.v:49207$3028_Y + connect \$35 $reduce_or$libresoc.v:49208$3029_Y + connect \$37 $or$libresoc.v:49209$3030_Y + connect \$3 $or$libresoc.v:49210$3031_Y + connect \$39 $or$libresoc.v:49211$3032_Y + connect \$41 $or$libresoc.v:49212$3033_Y + connect \$43 $or$libresoc.v:49213$3034_Y + connect \$45 $or$libresoc.v:49214$3035_Y + connect \$47 $or$libresoc.v:49215$3036_Y + connect \$49 $or$libresoc.v:49216$3037_Y + connect \$5 $or$libresoc.v:49217$3038_Y + connect \$7 $or$libresoc.v:49218$3039_Y + connect \wen$51 8'00000000 + connect \data_i$52 4'0000 + connect { \reg_7_w7__wen \reg_6_w6__wen \reg_5_w5__wen \reg_4_w4__wen \reg_3_w3__wen \reg_2_w2__wen \reg_1_w1__wen \reg_0_w0__wen } \full_wr__wen + connect { \reg_7_w7__data_i \reg_6_w6__data_i \reg_5_w5__data_i \reg_4_w4__data_i \reg_3_w3__data_i \reg_2_w2__data_i \reg_1_w1__data_i \reg_0_w0__data_i } \full_wr__data_i + connect { \reg_7_r27__ren \reg_6_r26__ren \reg_5_r25__ren \reg_4_r24__ren \reg_3_r23__ren \reg_2_r22__ren \reg_1_r21__ren \reg_0_r20__ren } \full_rd2__ren + connect \full_rd2__data_o { \reg_7_r27__data_o \reg_6_r26__data_o \reg_5_r25__data_o \reg_4_r24__data_o \reg_3_r23__data_o \reg_2_r22__data_o \reg_1_r21__data_o \reg_0_r20__data_o } + connect { \reg_7_r7__ren \reg_6_r6__ren \reg_5_r5__ren \reg_4_r4__ren \reg_3_r3__ren \reg_2_r2__ren \reg_1_r1__ren \reg_0_r0__ren } \full_rd__ren + connect \full_rd__data_o { \reg_7_r7__data_o \reg_6_r6__data_o \reg_5_r5__data_o \reg_4_r4__data_o \reg_3_r3__data_o \reg_2_r2__data_o \reg_1_r1__data_o \reg_0_r0__data_o } + connect \reg_7_dest27__data_i 4'0000 + connect \reg_6_dest26__data_i 4'0000 + connect \reg_5_dest25__data_i 4'0000 + connect \reg_4_dest24__data_i 4'0000 + connect \reg_3_dest23__data_i 4'0000 + connect \reg_2_dest22__data_i 4'0000 + connect \reg_1_dest21__data_i 4'0000 + connect \reg_0_dest20__data_i 4'0000 + connect { \reg_7_dest27__wen \reg_6_dest26__wen \reg_5_dest25__wen \reg_4_dest24__wen \reg_3_dest23__wen \reg_2_dest22__wen \reg_1_dest21__wen \reg_0_dest20__wen } 8'00000000 + connect \reg_7_dest17__data_i \data_i + connect \reg_6_dest16__data_i \data_i + connect \reg_5_dest15__data_i \data_i + connect \reg_4_dest14__data_i \data_i + connect \reg_3_dest13__data_i \data_i + connect \reg_2_dest12__data_i \data_i + connect \reg_1_dest11__data_i \data_i + connect \reg_0_dest10__data_i \data_i + connect { \reg_7_dest17__wen \reg_6_dest16__wen \reg_5_dest15__wen \reg_4_dest14__wen \reg_3_dest13__wen \reg_2_dest12__wen \reg_1_dest11__wen \reg_0_dest10__wen } \wen + connect { \reg_7_src37__ren \reg_6_src36__ren \reg_5_src35__ren \reg_4_src34__ren \reg_3_src33__ren \reg_2_src32__ren \reg_1_src31__ren \reg_0_src30__ren } \src3__ren + connect { \reg_7_src27__ren \reg_6_src26__ren \reg_5_src25__ren \reg_4_src24__ren \reg_3_src23__ren \reg_2_src22__ren \reg_1_src21__ren \reg_0_src20__ren } \src2__ren + connect { \reg_7_src17__ren \reg_6_src16__ren \reg_5_src15__ren \reg_4_src14__ren \reg_3_src13__ren \reg_2_src12__ren \reg_1_src11__ren \reg_0_src10__ren } \src1__ren +end +attribute \src "libresoc.v:49475.1-50528.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0" +attribute \generator "nMigen" +module \cr0 + attribute \src "libresoc.v:50129.3-50130.25" + wire $0\all_rd_dly[0:0] + attribute \src "libresoc.v:50302.3-50313.6" + wire width 13 $0\alu_cr0_cr_op__fn_unit$next[12:0]$3182 + attribute \src "libresoc.v:50101.3-50102.61" + wire width 13 $0\alu_cr0_cr_op__fn_unit[12:0] + attribute \src "libresoc.v:50302.3-50313.6" + wire width 32 $0\alu_cr0_cr_op__insn$next[31:0]$3183 + attribute \src "libresoc.v:50103.3-50104.55" + wire width 32 $0\alu_cr0_cr_op__insn[31:0] + attribute \src "libresoc.v:50302.3-50313.6" + wire width 7 $0\alu_cr0_cr_op__insn_type$next[6:0]$3184 + attribute \src "libresoc.v:50099.3-50100.65" + wire width 7 $0\alu_cr0_cr_op__insn_type[6:0] + attribute \src "libresoc.v:50127.3-50128.39" + wire $0\alu_done_dly[0:0] + attribute \src "libresoc.v:50449.3-50457.6" + wire $0\alu_l_r_alu$next[0:0]$3234 + attribute \src "libresoc.v:50071.3-50072.39" + wire $0\alu_l_r_alu[0:0] + attribute \src "libresoc.v:50440.3-50448.6" + wire $0\alui_l_r_alui$next[0:0]$3231 + attribute \src "libresoc.v:50073.3-50074.43" + wire $0\alui_l_r_alui[0:0] + attribute \src "libresoc.v:50314.3-50335.6" + wire width 64 $0\data_r0__o$next[63:0]$3189 + attribute \src "libresoc.v:50095.3-50096.37" + wire width 64 $0\data_r0__o[63:0] + attribute \src "libresoc.v:50314.3-50335.6" + wire $0\data_r0__o_ok$next[0:0]$3190 + attribute \src "libresoc.v:50097.3-50098.43" + wire $0\data_r0__o_ok[0:0] + attribute \src "libresoc.v:50336.3-50357.6" + wire width 32 $0\data_r1__full_cr$next[31:0]$3197 + attribute \src "libresoc.v:50091.3-50092.49" + wire width 32 $0\data_r1__full_cr[31:0] + attribute \src "libresoc.v:50336.3-50357.6" + wire $0\data_r1__full_cr_ok$next[0:0]$3198 + attribute \src "libresoc.v:50093.3-50094.55" + wire $0\data_r1__full_cr_ok[0:0] + attribute \src "libresoc.v:50358.3-50379.6" + wire width 4 $0\data_r2__cr_a$next[3:0]$3205 + attribute \src "libresoc.v:50087.3-50088.43" + wire width 4 $0\data_r2__cr_a[3:0] + attribute \src "libresoc.v:50358.3-50379.6" + wire $0\data_r2__cr_a_ok$next[0:0]$3206 + attribute \src "libresoc.v:50089.3-50090.49" + wire $0\data_r2__cr_a_ok[0:0] + attribute \src "libresoc.v:50458.3-50467.6" + wire width 64 $0\dest1_o[63:0] + attribute \src "libresoc.v:50468.3-50477.6" + wire width 32 $0\dest2_o[31:0] + attribute \src "libresoc.v:50478.3-50487.6" + wire width 4 $0\dest3_o[3:0] + attribute \src "libresoc.v:49476.7-49476.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:50257.3-50265.6" + wire $0\opc_l_r_opc$next[0:0]$3167 + attribute \src "libresoc.v:50113.3-50114.39" + wire $0\opc_l_r_opc[0:0] + attribute \src "libresoc.v:50248.3-50256.6" + wire $0\opc_l_s_opc$next[0:0]$3164 + attribute \src "libresoc.v:50115.3-50116.39" + wire $0\opc_l_s_opc[0:0] + attribute \src "libresoc.v:50488.3-50496.6" + wire width 3 $0\prev_wr_go$next[2:0]$3240 + attribute \src "libresoc.v:50125.3-50126.37" + wire width 3 $0\prev_wr_go[2:0] + attribute \src "libresoc.v:50202.3-50211.6" + wire $0\req_done[0:0] + attribute \src "libresoc.v:50293.3-50301.6" + wire width 3 $0\req_l_r_req$next[2:0]$3179 + attribute \src "libresoc.v:50105.3-50106.39" + wire width 3 $0\req_l_r_req[2:0] + attribute \src "libresoc.v:50284.3-50292.6" + wire width 3 $0\req_l_s_req$next[2:0]$3176 + attribute \src "libresoc.v:50107.3-50108.39" + wire width 3 $0\req_l_s_req[2:0] + attribute \src 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0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \src_l_q_src + connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } + connect \Y $and$libresoc.v:50068$3117_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + cell $and $and$libresoc.v:50069$3118 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \$93 + connect \B 6'111111 + connect \Y $and$libresoc.v:50069$3118_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + cell $eq $eq$libresoc.v:50042$3091 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$43 + connect \B 1'0 + connect \Y $eq$libresoc.v:50042$3091_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + cell $eq $eq$libresoc.v:50044$3093 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_wrmask_o + connect \B 1'0 + connect \Y $eq$libresoc.v:50044$3093_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $not $not$libresoc.v:50025$3074 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \all_rd_dly + connect \Y $not$libresoc.v:50025$3074_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $not $not$libresoc.v:50027$3076 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_done_dly + connect \Y $not$libresoc.v:50027$3076_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $not $not$libresoc.v:50030$3079 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \cu_wrmask_o + connect \Y $not$libresoc.v:50030$3079_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $not $not$libresoc.v:50033$3082 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$24 + connect \Y $not$libresoc.v:50033$3082_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + cell $not $not$libresoc.v:50039$3088 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_cr0_n_ready_i + connect \Y $not$libresoc.v:50039$3088_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $not $not$libresoc.v:50054$3103 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \cu_rd__rel_o + connect \Y $not$libresoc.v:50054$3103_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + cell $not $not$libresoc.v:50070$3119 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \cu_rdmaskn_i + connect \Y $not$libresoc.v:50070$3119_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $or $or$libresoc.v:50037$3086 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$33 + connect \B \$35 + connect \Y $or$libresoc.v:50037$3086_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" + cell $or $or$libresoc.v:50048$3097 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \req_done + connect \B \cu_go_die_i + connect \Y $or$libresoc.v:50048$3097_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" + cell $or $or$libresoc.v:50049$3098 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_issue_i + connect \B \cu_go_die_i + connect \Y $or$libresoc.v:50049$3098_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" + cell $or $or$libresoc.v:50050$3099 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \cu_wr__go_i + connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } + connect \Y $or$libresoc.v:50050$3099_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" + cell $or $or$libresoc.v:50051$3100 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \cu_rd__go_i + connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } + connect \Y $or$libresoc.v:50051$3100_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" + cell $or $or$libresoc.v:50055$3104 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \reset_w + connect \B \prev_wr_go + connect \Y $or$libresoc.v:50055$3104_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $or $or$libresoc.v:50065$3114 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \$6 + connect \B \cu_rd__go_i + connect \Y $or$libresoc.v:50065$3114_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $reduce_and $reduce_and$libresoc.v:50014$3063 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $reduce_and$libresoc.v:50014$3063_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $reduce_or $reduce_or$libresoc.v:50032$3081 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \$27 + connect \Y $reduce_or$libresoc.v:50032$3081_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $reduce_or $reduce_or$libresoc.v:50035$3084 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \cu_wr__go_i + connect \Y $reduce_or$libresoc.v:50035$3084_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $reduce_or $reduce_or$libresoc.v:50036$3085 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \prev_wr_go + connect \Y $reduce_or$libresoc.v:50036$3085_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" + cell $mux $ternary$libresoc.v:50059$3108 + parameter \WIDTH 64 + connect \A \src_r0 + connect \B \src1_i + connect \S \src_l_q_src [0] + connect \Y $ternary$libresoc.v:50059$3108_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" + cell $mux $ternary$libresoc.v:50060$3109 + parameter \WIDTH 64 + connect \A \src_r1 + connect \B \src2_i + connect \S \src_l_q_src [1] + connect \Y $ternary$libresoc.v:50060$3109_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" + cell $mux $ternary$libresoc.v:50061$3110 + parameter \WIDTH 32 + connect \A \src_r2 + connect \B \src3_i + connect \S \src_l_q_src [2] + connect \Y $ternary$libresoc.v:50061$3110_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" + cell $mux $ternary$libresoc.v:50062$3111 + parameter \WIDTH 4 + connect \A \src_r3 + connect \B \src4_i + connect \S \src_l_q_src [3] + connect \Y $ternary$libresoc.v:50062$3111_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" + cell $mux $ternary$libresoc.v:50063$3112 + parameter \WIDTH 4 + connect \A \src_r4 + connect \B \src5_i + connect \S \src_l_q_src [4] + connect \Y $ternary$libresoc.v:50063$3112_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" + cell $mux $ternary$libresoc.v:50064$3113 + parameter \WIDTH 4 + connect \A \src_r5 + connect \B \src6_i + connect \S \src_l_q_src [5] + connect \Y $ternary$libresoc.v:50064$3113_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:50131.11-50153.4" + cell \alu_cr0 \alu_cr0 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cr_a \alu_cr0_cr_a + connect \cr_a$2 \alu_cr0_cr_a$2 + connect \cr_a_ok \cr_a_ok + connect \cr_b \alu_cr0_cr_b + connect \cr_c \alu_cr0_cr_c + connect \cr_op__fn_unit \alu_cr0_cr_op__fn_unit + connect \cr_op__insn \alu_cr0_cr_op__insn + connect \cr_op__insn_type \alu_cr0_cr_op__insn_type + connect \full_cr \alu_cr0_full_cr + connect \full_cr$1 \alu_cr0_full_cr$1 + connect \full_cr_ok \full_cr_ok + connect \n_ready_i \alu_cr0_n_ready_i + connect \n_valid_o \alu_cr0_n_valid_o + connect \o \alu_cr0_o + connect \o_ok \o_ok + connect \p_ready_o \alu_cr0_p_ready_o + connect \p_valid_i \alu_cr0_p_valid_i + connect \ra \alu_cr0_ra + connect \rb \alu_cr0_rb + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:50154.14-50160.4" + cell \alu_l$16 \alu_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_alu \alu_l_q_alu + connect \r_alu \alu_l_r_alu + connect \s_alu \alu_l_s_alu + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:50161.15-50167.4" + cell \alui_l$15 \alui_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_alui \alui_l_q_alui + connect \r_alui \alui_l_r_alui + connect \s_alui \alui_l_s_alui + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:50168.14-50174.4" + cell \opc_l$11 \opc_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_opc \opc_l_q_opc + connect \r_opc \opc_l_r_opc + connect \s_opc \opc_l_s_opc + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:50175.14-50181.4" + cell \req_l$12 \req_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_req \req_l_q_req + connect \r_req \req_l_r_req + connect \s_req \req_l_s_req + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:50182.14-50188.4" + cell \rok_l$14 \rok_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_rdok \rok_l_q_rdok + connect \r_rdok \rok_l_r_rdok + connect \s_rdok \rok_l_s_rdok + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:50189.14-50194.4" + cell \rst_l$13 \rst_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \r_rst \rst_l_r_rst + connect \s_rst \rst_l_s_rst + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:50195.14-50201.4" + cell \src_l$10 \src_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_src \src_l_q_src + connect \r_src \src_l_r_src + connect \s_src \src_l_s_src + end + attribute \src "libresoc.v:49476.7-49476.20" + process $proc$libresoc.v:49476$3242 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:49594.7-49594.24" + process $proc$libresoc.v:49594$3243 + assign { } { } + assign $1\all_rd_dly[0:0] 1'0 + sync always + sync init + update \all_rd_dly $1\all_rd_dly[0:0] + end + attribute \src "libresoc.v:49624.14-49624.47" + process $proc$libresoc.v:49624$3244 + assign { } { } + assign $1\alu_cr0_cr_op__fn_unit[12:0] 13'0000000000000 + sync always + sync init + update \alu_cr0_cr_op__fn_unit $1\alu_cr0_cr_op__fn_unit[12:0] + end + attribute \src "libresoc.v:49628.14-49628.41" + process $proc$libresoc.v:49628$3245 + assign { } { } + assign $1\alu_cr0_cr_op__insn[31:0] 0 + sync always + sync init + update \alu_cr0_cr_op__insn $1\alu_cr0_cr_op__insn[31:0] + end + attribute \src "libresoc.v:49706.13-49706.45" + process $proc$libresoc.v:49706$3246 + assign { } { } + assign $1\alu_cr0_cr_op__insn_type[6:0] 7'0000000 + sync always + sync init + update \alu_cr0_cr_op__insn_type $1\alu_cr0_cr_op__insn_type[6:0] + end + attribute \src "libresoc.v:49730.7-49730.26" + process $proc$libresoc.v:49730$3247 + assign { } { } + assign $1\alu_done_dly[0:0] 1'0 + sync always + sync init + update \alu_done_dly $1\alu_done_dly[0:0] + end + attribute \src "libresoc.v:49738.7-49738.25" + process $proc$libresoc.v:49738$3248 + assign { } { } + assign $1\alu_l_r_alu[0:0] 1'1 + sync always + sync init + update \alu_l_r_alu $1\alu_l_r_alu[0:0] + end + attribute \src "libresoc.v:49750.7-49750.27" + process $proc$libresoc.v:49750$3249 + assign { } { } + assign $1\alui_l_r_alui[0:0] 1'1 + sync always + sync init + update \alui_l_r_alui $1\alui_l_r_alui[0:0] + end + attribute \src "libresoc.v:49784.14-49784.47" + process $proc$libresoc.v:49784$3250 + assign { } { } + assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \data_r0__o $1\data_r0__o[63:0] + end + attribute \src "libresoc.v:49788.7-49788.27" + process $proc$libresoc.v:49788$3251 + assign { } { } + assign $1\data_r0__o_ok[0:0] 1'0 + sync always + sync init + update \data_r0__o_ok $1\data_r0__o_ok[0:0] + end + attribute \src "libresoc.v:49792.14-49792.38" + process $proc$libresoc.v:49792$3252 + assign { } { } + assign $1\data_r1__full_cr[31:0] 0 + sync always + sync init + update \data_r1__full_cr $1\data_r1__full_cr[31:0] + end + attribute \src "libresoc.v:49796.7-49796.33" + process $proc$libresoc.v:49796$3253 + assign { } { } + assign $1\data_r1__full_cr_ok[0:0] 1'0 + sync always + sync init + update \data_r1__full_cr_ok $1\data_r1__full_cr_ok[0:0] + end + attribute \src "libresoc.v:49800.13-49800.33" + process $proc$libresoc.v:49800$3254 + assign { } { } + assign $1\data_r2__cr_a[3:0] 4'0000 + sync always + sync init + update \data_r2__cr_a $1\data_r2__cr_a[3:0] + end + attribute \src "libresoc.v:49804.7-49804.30" + process $proc$libresoc.v:49804$3255 + assign { } { } + assign $1\data_r2__cr_a_ok[0:0] 1'0 + sync always + sync init + update \data_r2__cr_a_ok $1\data_r2__cr_a_ok[0:0] + end + attribute \src "libresoc.v:49823.7-49823.25" + process $proc$libresoc.v:49823$3256 + assign { } { } + assign $1\opc_l_r_opc[0:0] 1'1 + sync always + sync init + update \opc_l_r_opc $1\opc_l_r_opc[0:0] + end + attribute \src "libresoc.v:49827.7-49827.25" + process $proc$libresoc.v:49827$3257 + assign { } { } + assign $1\opc_l_s_opc[0:0] 1'0 + sync always + sync init + update \opc_l_s_opc $1\opc_l_s_opc[0:0] + end + attribute \src "libresoc.v:49925.13-49925.30" + process $proc$libresoc.v:49925$3258 + assign { } { } + assign $1\prev_wr_go[2:0] 3'000 + sync always + sync init + update \prev_wr_go $1\prev_wr_go[2:0] + end + attribute \src "libresoc.v:49933.13-49933.31" + process $proc$libresoc.v:49933$3259 + assign { } { } + assign $1\req_l_r_req[2:0] 3'111 + sync always + sync init + update \req_l_r_req $1\req_l_r_req[2:0] + end + attribute \src "libresoc.v:49937.13-49937.31" + process $proc$libresoc.v:49937$3260 + assign { } { } + assign $1\req_l_s_req[2:0] 3'000 + sync always + sync init + update \req_l_s_req $1\req_l_s_req[2:0] + end + attribute \src "libresoc.v:49949.7-49949.26" + process $proc$libresoc.v:49949$3261 + assign { } { } + assign $1\rok_l_r_rdok[0:0] 1'1 + sync always + sync init + update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] + end + attribute \src "libresoc.v:49953.7-49953.26" + process $proc$libresoc.v:49953$3262 + assign { } { } + assign $1\rok_l_s_rdok[0:0] 1'0 + sync always + sync init + update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] + end + attribute \src "libresoc.v:49957.7-49957.25" + process $proc$libresoc.v:49957$3263 + assign { } { } + assign $1\rst_l_r_rst[0:0] 1'1 + sync always + sync init + update \rst_l_r_rst $1\rst_l_r_rst[0:0] + end + attribute \src "libresoc.v:49961.7-49961.25" + process $proc$libresoc.v:49961$3264 + assign { } { } + assign $1\rst_l_s_rst[0:0] 1'0 + sync always + sync init + update \rst_l_s_rst $1\rst_l_s_rst[0:0] + end + attribute \src "libresoc.v:49981.13-49981.32" + process $proc$libresoc.v:49981$3265 + assign { } { } + assign $1\src_l_r_src[5:0] 6'111111 + sync always + sync init + update \src_l_r_src $1\src_l_r_src[5:0] + end + attribute \src "libresoc.v:49985.13-49985.32" + process $proc$libresoc.v:49985$3266 + assign { } { } + assign $1\src_l_s_src[5:0] 6'000000 + sync always + sync init + update \src_l_s_src $1\src_l_s_src[5:0] + end + attribute \src "libresoc.v:49989.14-49989.43" + process $proc$libresoc.v:49989$3267 + assign { } { } + assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \src_r0 $1\src_r0[63:0] + end + attribute \src "libresoc.v:49993.14-49993.43" + process $proc$libresoc.v:49993$3268 + assign { } { } + assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \src_r1 $1\src_r1[63:0] + end + attribute \src "libresoc.v:49997.14-49997.28" + process $proc$libresoc.v:49997$3269 + assign { } { } + assign $1\src_r2[31:0] 0 + sync always + sync init + update \src_r2 $1\src_r2[31:0] + end + attribute \src "libresoc.v:50001.13-50001.26" + process $proc$libresoc.v:50001$3270 + assign { } { } + assign $1\src_r3[3:0] 4'0000 + sync always + sync init + update \src_r3 $1\src_r3[3:0] + end + attribute \src "libresoc.v:50005.13-50005.26" + process $proc$libresoc.v:50005$3271 + assign { } { } + assign $1\src_r4[3:0] 4'0000 + sync always + sync init + update \src_r4 $1\src_r4[3:0] + end + attribute \src "libresoc.v:50009.13-50009.26" + process $proc$libresoc.v:50009$3272 + assign { } { } + assign $1\src_r5[3:0] 4'0000 + sync always + sync init + update \src_r5 $1\src_r5[3:0] + end + attribute \src "libresoc.v:50071.3-50072.39" + process $proc$libresoc.v:50071$3120 + assign { } { } + assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next + sync posedge \coresync_clk + update \alu_l_r_alu $0\alu_l_r_alu[0:0] + end + attribute \src "libresoc.v:50073.3-50074.43" + process $proc$libresoc.v:50073$3121 + assign { } { } + assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next + sync posedge \coresync_clk + update \alui_l_r_alui $0\alui_l_r_alui[0:0] + end + attribute \src "libresoc.v:50075.3-50076.29" + process $proc$libresoc.v:50075$3122 + assign { } { } + assign $0\src_r5[3:0] \src_r5$next + sync posedge \coresync_clk + update \src_r5 $0\src_r5[3:0] + end + attribute \src "libresoc.v:50077.3-50078.29" + process $proc$libresoc.v:50077$3123 + assign { } { } + assign $0\src_r4[3:0] \src_r4$next + sync posedge \coresync_clk + update \src_r4 $0\src_r4[3:0] + end + attribute \src "libresoc.v:50079.3-50080.29" + process $proc$libresoc.v:50079$3124 + assign { } { } + assign $0\src_r3[3:0] \src_r3$next + sync posedge \coresync_clk + update \src_r3 $0\src_r3[3:0] + end + attribute \src "libresoc.v:50081.3-50082.29" + process $proc$libresoc.v:50081$3125 + assign { } { } + assign $0\src_r2[31:0] \src_r2$next + sync posedge \coresync_clk + update \src_r2 $0\src_r2[31:0] + end + attribute \src "libresoc.v:50083.3-50084.29" + process $proc$libresoc.v:50083$3126 + assign { } { } + assign $0\src_r1[63:0] \src_r1$next + sync posedge \coresync_clk + update \src_r1 $0\src_r1[63:0] + end + attribute \src "libresoc.v:50085.3-50086.29" + process $proc$libresoc.v:50085$3127 + assign { } { } + assign $0\src_r0[63:0] \src_r0$next + sync posedge \coresync_clk + update \src_r0 $0\src_r0[63:0] + end + attribute \src "libresoc.v:50087.3-50088.43" + process $proc$libresoc.v:50087$3128 + assign { } { } + assign $0\data_r2__cr_a[3:0] \data_r2__cr_a$next + sync posedge \coresync_clk + update \data_r2__cr_a $0\data_r2__cr_a[3:0] + end + attribute \src "libresoc.v:50089.3-50090.49" + process $proc$libresoc.v:50089$3129 + assign { } { } + assign $0\data_r2__cr_a_ok[0:0] \data_r2__cr_a_ok$next + sync posedge \coresync_clk + update \data_r2__cr_a_ok $0\data_r2__cr_a_ok[0:0] + end + attribute \src "libresoc.v:50091.3-50092.49" + process $proc$libresoc.v:50091$3130 + assign { } { } + assign $0\data_r1__full_cr[31:0] \data_r1__full_cr$next + sync posedge \coresync_clk + update \data_r1__full_cr $0\data_r1__full_cr[31:0] + end + attribute \src "libresoc.v:50093.3-50094.55" + process $proc$libresoc.v:50093$3131 + assign { } { } + assign $0\data_r1__full_cr_ok[0:0] \data_r1__full_cr_ok$next + sync posedge \coresync_clk + update \data_r1__full_cr_ok $0\data_r1__full_cr_ok[0:0] + end + attribute \src "libresoc.v:50095.3-50096.37" + process $proc$libresoc.v:50095$3132 + assign { } { } + assign $0\data_r0__o[63:0] \data_r0__o$next + sync posedge \coresync_clk + update \data_r0__o $0\data_r0__o[63:0] + end + attribute \src "libresoc.v:50097.3-50098.43" + process $proc$libresoc.v:50097$3133 + assign { } { } + assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next + sync posedge \coresync_clk + update \data_r0__o_ok $0\data_r0__o_ok[0:0] + end + attribute \src "libresoc.v:50099.3-50100.65" + process $proc$libresoc.v:50099$3134 + assign { } { } + assign $0\alu_cr0_cr_op__insn_type[6:0] \alu_cr0_cr_op__insn_type$next + sync posedge \coresync_clk + update \alu_cr0_cr_op__insn_type $0\alu_cr0_cr_op__insn_type[6:0] + end + attribute \src "libresoc.v:50101.3-50102.61" + process $proc$libresoc.v:50101$3135 + assign { } { } + assign $0\alu_cr0_cr_op__fn_unit[12:0] \alu_cr0_cr_op__fn_unit$next + sync posedge \coresync_clk + update \alu_cr0_cr_op__fn_unit $0\alu_cr0_cr_op__fn_unit[12:0] + end + attribute \src "libresoc.v:50103.3-50104.55" + process $proc$libresoc.v:50103$3136 + assign { } { } + assign $0\alu_cr0_cr_op__insn[31:0] \alu_cr0_cr_op__insn$next + sync posedge \coresync_clk + update \alu_cr0_cr_op__insn $0\alu_cr0_cr_op__insn[31:0] + end + attribute \src "libresoc.v:50105.3-50106.39" + process $proc$libresoc.v:50105$3137 + assign { } { } + assign $0\req_l_r_req[2:0] \req_l_r_req$next + sync posedge \coresync_clk + update \req_l_r_req $0\req_l_r_req[2:0] + end + attribute \src "libresoc.v:50107.3-50108.39" + process $proc$libresoc.v:50107$3138 + assign { } { } + assign $0\req_l_s_req[2:0] \req_l_s_req$next + sync posedge \coresync_clk + update \req_l_s_req $0\req_l_s_req[2:0] + end + attribute \src "libresoc.v:50109.3-50110.39" + process $proc$libresoc.v:50109$3139 + assign { } { } + assign $0\src_l_r_src[5:0] \src_l_r_src$next + sync posedge \coresync_clk + update \src_l_r_src $0\src_l_r_src[5:0] + end + attribute \src "libresoc.v:50111.3-50112.39" + process $proc$libresoc.v:50111$3140 + assign { } { } + assign $0\src_l_s_src[5:0] \src_l_s_src$next + sync posedge \coresync_clk + update \src_l_s_src $0\src_l_s_src[5:0] + end + attribute \src "libresoc.v:50113.3-50114.39" + process $proc$libresoc.v:50113$3141 + assign { } { } + assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next + sync posedge \coresync_clk + update \opc_l_r_opc $0\opc_l_r_opc[0:0] + end + attribute \src "libresoc.v:50115.3-50116.39" + process $proc$libresoc.v:50115$3142 + assign { } { } + assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next + sync posedge \coresync_clk + update \opc_l_s_opc $0\opc_l_s_opc[0:0] + end + attribute \src "libresoc.v:50117.3-50118.39" + process $proc$libresoc.v:50117$3143 + assign { } { } + assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next + sync posedge \coresync_clk + update \rst_l_r_rst $0\rst_l_r_rst[0:0] + end + attribute \src "libresoc.v:50119.3-50120.39" + process $proc$libresoc.v:50119$3144 + assign { } { } + assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next + sync posedge \coresync_clk + update \rst_l_s_rst $0\rst_l_s_rst[0:0] + end + attribute \src "libresoc.v:50121.3-50122.41" + process $proc$libresoc.v:50121$3145 + assign { } { } + assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next + sync posedge \coresync_clk + update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] + end + attribute \src "libresoc.v:50123.3-50124.41" + process $proc$libresoc.v:50123$3146 + assign { } { } + assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next + sync posedge \coresync_clk + update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] + end + attribute \src "libresoc.v:50125.3-50126.37" + process $proc$libresoc.v:50125$3147 + assign { } { } + assign $0\prev_wr_go[2:0] \prev_wr_go$next + sync posedge \coresync_clk + update \prev_wr_go $0\prev_wr_go[2:0] + end + attribute \src "libresoc.v:50127.3-50128.39" + process $proc$libresoc.v:50127$3148 + assign { } { } + assign $0\alu_done_dly[0:0] \alu_cr0_n_valid_o + sync posedge \coresync_clk + update \alu_done_dly $0\alu_done_dly[0:0] + end + attribute \src "libresoc.v:50129.3-50130.25" + process $proc$libresoc.v:50129$3149 + assign { } { } + assign $0\all_rd_dly[0:0] \$11 + sync posedge \coresync_clk + update \all_rd_dly $0\all_rd_dly[0:0] + end + attribute \src "libresoc.v:50202.3-50211.6" + process $proc$libresoc.v:50202$3150 + assign { } { } + assign { } { } + assign $0\req_done[0:0] $1\req_done[0:0] + attribute \src "libresoc.v:50203.5-50203.29" + switch \initial + attribute \src "libresoc.v:50203.9-50203.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + switch \$55 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\req_done[0:0] 1'1 + case + assign $1\req_done[0:0] \$47 + end + sync always + update \req_done $0\req_done[0:0] + end + attribute \src "libresoc.v:50212.3-50220.6" + process $proc$libresoc.v:50212$3151 + assign { } { } + assign { } { } + assign $0\rok_l_s_rdok$next[0:0]$3152 $1\rok_l_s_rdok$next[0:0]$3153 + attribute \src "libresoc.v:50213.5-50213.29" + switch \initial + attribute \src "libresoc.v:50213.9-50213.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rok_l_s_rdok$next[0:0]$3153 1'0 + case + assign $1\rok_l_s_rdok$next[0:0]$3153 \cu_issue_i + end + sync always + update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$3152 + end + attribute \src "libresoc.v:50221.3-50229.6" + process $proc$libresoc.v:50221$3154 + assign { } { } + assign { } { } + assign $0\rok_l_r_rdok$next[0:0]$3155 $1\rok_l_r_rdok$next[0:0]$3156 + attribute \src "libresoc.v:50222.5-50222.29" + switch \initial + attribute \src "libresoc.v:50222.9-50222.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rok_l_r_rdok$next[0:0]$3156 1'1 + case + assign $1\rok_l_r_rdok$next[0:0]$3156 \$65 + end + sync always + update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$3155 + end + attribute \src "libresoc.v:50230.3-50238.6" + process $proc$libresoc.v:50230$3157 + assign { } { } + assign { } { } + assign $0\rst_l_s_rst$next[0:0]$3158 $1\rst_l_s_rst$next[0:0]$3159 + attribute \src "libresoc.v:50231.5-50231.29" + switch \initial + attribute \src "libresoc.v:50231.9-50231.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rst_l_s_rst$next[0:0]$3159 1'0 + case + assign $1\rst_l_s_rst$next[0:0]$3159 \all_rd + end + sync always + update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$3158 + end + attribute \src "libresoc.v:50239.3-50247.6" + process $proc$libresoc.v:50239$3160 + assign { } { } + assign { } { } + assign $0\rst_l_r_rst$next[0:0]$3161 $1\rst_l_r_rst$next[0:0]$3162 + attribute \src "libresoc.v:50240.5-50240.29" + switch \initial + attribute \src "libresoc.v:50240.9-50240.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rst_l_r_rst$next[0:0]$3162 1'1 + case + assign $1\rst_l_r_rst$next[0:0]$3162 \rst_r + end + sync always + update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$3161 + end + attribute \src "libresoc.v:50248.3-50256.6" + process $proc$libresoc.v:50248$3163 + assign { } { } + assign { } { } + assign $0\opc_l_s_opc$next[0:0]$3164 $1\opc_l_s_opc$next[0:0]$3165 + attribute \src "libresoc.v:50249.5-50249.29" + switch \initial + attribute \src "libresoc.v:50249.9-50249.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\opc_l_s_opc$next[0:0]$3165 1'0 + case + assign $1\opc_l_s_opc$next[0:0]$3165 \cu_issue_i + end + sync always + update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$3164 + end + attribute \src "libresoc.v:50257.3-50265.6" + process $proc$libresoc.v:50257$3166 + assign { } { } + assign { } { } + assign $0\opc_l_r_opc$next[0:0]$3167 $1\opc_l_r_opc$next[0:0]$3168 + attribute \src "libresoc.v:50258.5-50258.29" + switch \initial + attribute \src "libresoc.v:50258.9-50258.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\opc_l_r_opc$next[0:0]$3168 1'1 + case + assign $1\opc_l_r_opc$next[0:0]$3168 \req_done + end + sync always + update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$3167 + end + attribute \src "libresoc.v:50266.3-50274.6" + process $proc$libresoc.v:50266$3169 + assign { } { } + assign { } { } + assign $0\src_l_s_src$next[5:0]$3170 $1\src_l_s_src$next[5:0]$3171 + attribute \src "libresoc.v:50267.5-50267.29" + switch \initial + attribute \src "libresoc.v:50267.9-50267.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_l_s_src$next[5:0]$3171 6'000000 + case + assign $1\src_l_s_src$next[5:0]$3171 { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i } + end + sync always + update \src_l_s_src$next $0\src_l_s_src$next[5:0]$3170 + end + attribute \src "libresoc.v:50275.3-50283.6" + process $proc$libresoc.v:50275$3172 + assign { } { } + assign { } { } + assign $0\src_l_r_src$next[5:0]$3173 $1\src_l_r_src$next[5:0]$3174 + attribute \src "libresoc.v:50276.5-50276.29" + switch \initial + attribute \src "libresoc.v:50276.9-50276.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_l_r_src$next[5:0]$3174 6'111111 + case + assign $1\src_l_r_src$next[5:0]$3174 \reset_r + end + sync always + update \src_l_r_src$next $0\src_l_r_src$next[5:0]$3173 + end + attribute \src "libresoc.v:50284.3-50292.6" + process $proc$libresoc.v:50284$3175 + assign { } { } + assign { } { } + assign $0\req_l_s_req$next[2:0]$3176 $1\req_l_s_req$next[2:0]$3177 + attribute \src "libresoc.v:50285.5-50285.29" + switch \initial + attribute \src "libresoc.v:50285.9-50285.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\req_l_s_req$next[2:0]$3177 3'000 + case + assign $1\req_l_s_req$next[2:0]$3177 \$67 + end + sync always + update \req_l_s_req$next $0\req_l_s_req$next[2:0]$3176 + end + attribute \src "libresoc.v:50293.3-50301.6" + process $proc$libresoc.v:50293$3178 + assign { } { } + assign { } { } + assign $0\req_l_r_req$next[2:0]$3179 $1\req_l_r_req$next[2:0]$3180 + attribute \src "libresoc.v:50294.5-50294.29" + switch \initial + attribute \src "libresoc.v:50294.9-50294.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\req_l_r_req$next[2:0]$3180 3'111 + case + assign $1\req_l_r_req$next[2:0]$3180 \$69 + end + sync always + update \req_l_r_req$next $0\req_l_r_req$next[2:0]$3179 + end + attribute \src "libresoc.v:50302.3-50313.6" + process $proc$libresoc.v:50302$3181 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\alu_cr0_cr_op__fn_unit$next[12:0]$3182 $1\alu_cr0_cr_op__fn_unit$next[12:0]$3185 + assign $0\alu_cr0_cr_op__insn$next[31:0]$3183 $1\alu_cr0_cr_op__insn$next[31:0]$3186 + assign $0\alu_cr0_cr_op__insn_type$next[6:0]$3184 $1\alu_cr0_cr_op__insn_type$next[6:0]$3187 + attribute \src "libresoc.v:50303.5-50303.29" + switch \initial + attribute \src "libresoc.v:50303.9-50303.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { $1\alu_cr0_cr_op__insn$next[31:0]$3186 $1\alu_cr0_cr_op__fn_unit$next[12:0]$3185 $1\alu_cr0_cr_op__insn_type$next[6:0]$3187 } { \oper_i_alu_cr0__insn \oper_i_alu_cr0__fn_unit \oper_i_alu_cr0__insn_type } + case + assign $1\alu_cr0_cr_op__fn_unit$next[12:0]$3185 \alu_cr0_cr_op__fn_unit + assign $1\alu_cr0_cr_op__insn$next[31:0]$3186 \alu_cr0_cr_op__insn + assign $1\alu_cr0_cr_op__insn_type$next[6:0]$3187 \alu_cr0_cr_op__insn_type + end + sync always + update \alu_cr0_cr_op__fn_unit$next $0\alu_cr0_cr_op__fn_unit$next[12:0]$3182 + update \alu_cr0_cr_op__insn$next $0\alu_cr0_cr_op__insn$next[31:0]$3183 + update \alu_cr0_cr_op__insn_type$next $0\alu_cr0_cr_op__insn_type$next[6:0]$3184 + end + attribute \src "libresoc.v:50314.3-50335.6" + process $proc$libresoc.v:50314$3188 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r0__o$next[63:0]$3189 $2\data_r0__o$next[63:0]$3193 + assign { } { } + assign $0\data_r0__o_ok$next[0:0]$3190 $3\data_r0__o_ok$next[0:0]$3195 + attribute \src "libresoc.v:50315.5-50315.29" + switch \initial + attribute \src "libresoc.v:50315.9-50315.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r0__o_ok$next[0:0]$3192 $1\data_r0__o$next[63:0]$3191 } { \o_ok \alu_cr0_o } + case + assign $1\data_r0__o$next[63:0]$3191 \data_r0__o + assign $1\data_r0__o_ok$next[0:0]$3192 \data_r0__o_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r0__o_ok$next[0:0]$3194 $2\data_r0__o$next[63:0]$3193 } 65'00000000000000000000000000000000000000000000000000000000000000000 + case + assign $2\data_r0__o$next[63:0]$3193 $1\data_r0__o$next[63:0]$3191 + assign $2\data_r0__o_ok$next[0:0]$3194 $1\data_r0__o_ok$next[0:0]$3192 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r0__o_ok$next[0:0]$3195 1'0 + case + assign $3\data_r0__o_ok$next[0:0]$3195 $2\data_r0__o_ok$next[0:0]$3194 + end + sync always + update \data_r0__o$next $0\data_r0__o$next[63:0]$3189 + update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$3190 + end + attribute \src "libresoc.v:50336.3-50357.6" + process $proc$libresoc.v:50336$3196 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r1__full_cr$next[31:0]$3197 $2\data_r1__full_cr$next[31:0]$3201 + assign { } { } + assign $0\data_r1__full_cr_ok$next[0:0]$3198 $3\data_r1__full_cr_ok$next[0:0]$3203 + attribute \src "libresoc.v:50337.5-50337.29" + switch \initial + attribute \src "libresoc.v:50337.9-50337.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r1__full_cr_ok$next[0:0]$3200 $1\data_r1__full_cr$next[31:0]$3199 } { \full_cr_ok \alu_cr0_full_cr } + case + assign $1\data_r1__full_cr$next[31:0]$3199 \data_r1__full_cr + assign $1\data_r1__full_cr_ok$next[0:0]$3200 \data_r1__full_cr_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r1__full_cr_ok$next[0:0]$3202 $2\data_r1__full_cr$next[31:0]$3201 } 33'000000000000000000000000000000000 + case + assign $2\data_r1__full_cr$next[31:0]$3201 $1\data_r1__full_cr$next[31:0]$3199 + assign $2\data_r1__full_cr_ok$next[0:0]$3202 $1\data_r1__full_cr_ok$next[0:0]$3200 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r1__full_cr_ok$next[0:0]$3203 1'0 + case + assign $3\data_r1__full_cr_ok$next[0:0]$3203 $2\data_r1__full_cr_ok$next[0:0]$3202 + end + sync always + update \data_r1__full_cr$next $0\data_r1__full_cr$next[31:0]$3197 + update \data_r1__full_cr_ok$next $0\data_r1__full_cr_ok$next[0:0]$3198 + end + attribute \src "libresoc.v:50358.3-50379.6" + process $proc$libresoc.v:50358$3204 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r2__cr_a$next[3:0]$3205 $2\data_r2__cr_a$next[3:0]$3209 + assign { } { } + assign $0\data_r2__cr_a_ok$next[0:0]$3206 $3\data_r2__cr_a_ok$next[0:0]$3211 + attribute \src "libresoc.v:50359.5-50359.29" + switch \initial + attribute \src "libresoc.v:50359.9-50359.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r2__cr_a_ok$next[0:0]$3208 $1\data_r2__cr_a$next[3:0]$3207 } { \cr_a_ok \alu_cr0_cr_a } + case + assign $1\data_r2__cr_a$next[3:0]$3207 \data_r2__cr_a + assign $1\data_r2__cr_a_ok$next[0:0]$3208 \data_r2__cr_a_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r2__cr_a_ok$next[0:0]$3210 $2\data_r2__cr_a$next[3:0]$3209 } 5'00000 + case + assign $2\data_r2__cr_a$next[3:0]$3209 $1\data_r2__cr_a$next[3:0]$3207 + assign $2\data_r2__cr_a_ok$next[0:0]$3210 $1\data_r2__cr_a_ok$next[0:0]$3208 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r2__cr_a_ok$next[0:0]$3211 1'0 + case + assign $3\data_r2__cr_a_ok$next[0:0]$3211 $2\data_r2__cr_a_ok$next[0:0]$3210 + end + sync always + update \data_r2__cr_a$next $0\data_r2__cr_a$next[3:0]$3205 + update \data_r2__cr_a_ok$next $0\data_r2__cr_a_ok$next[0:0]$3206 + end + attribute \src "libresoc.v:50380.3-50389.6" + process $proc$libresoc.v:50380$3212 + assign { } { } + assign { } { } + assign $0\src_r0$next[63:0]$3213 $1\src_r0$next[63:0]$3214 + attribute \src "libresoc.v:50381.5-50381.29" + switch \initial + attribute \src "libresoc.v:50381.9-50381.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" + switch \src_l_q_src [0] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r0$next[63:0]$3214 \src1_i + case + assign $1\src_r0$next[63:0]$3214 \src_r0 + end + sync always + update \src_r0$next $0\src_r0$next[63:0]$3213 + end + attribute \src "libresoc.v:50390.3-50399.6" + process $proc$libresoc.v:50390$3215 + assign { } { } + assign { } { } + assign $0\src_r1$next[63:0]$3216 $1\src_r1$next[63:0]$3217 + attribute \src "libresoc.v:50391.5-50391.29" + switch \initial + attribute \src "libresoc.v:50391.9-50391.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" + switch \src_l_q_src [1] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r1$next[63:0]$3217 \src2_i + case + assign $1\src_r1$next[63:0]$3217 \src_r1 + end + sync always + update \src_r1$next $0\src_r1$next[63:0]$3216 + end + attribute \src "libresoc.v:50400.3-50409.6" + process $proc$libresoc.v:50400$3218 + assign { } { } + assign { } { } + assign $0\src_r2$next[31:0]$3219 $1\src_r2$next[31:0]$3220 + attribute \src "libresoc.v:50401.5-50401.29" + switch \initial + attribute \src "libresoc.v:50401.9-50401.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" + switch \src_l_q_src [2] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r2$next[31:0]$3220 \src3_i + case + assign $1\src_r2$next[31:0]$3220 \src_r2 + end + sync always + update \src_r2$next $0\src_r2$next[31:0]$3219 + end + attribute \src "libresoc.v:50410.3-50419.6" + process $proc$libresoc.v:50410$3221 + assign { } { } + assign { } { } + assign $0\src_r3$next[3:0]$3222 $1\src_r3$next[3:0]$3223 + attribute \src "libresoc.v:50411.5-50411.29" + switch \initial + attribute \src "libresoc.v:50411.9-50411.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" + switch \src_l_q_src [3] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r3$next[3:0]$3223 \src4_i + case + assign $1\src_r3$next[3:0]$3223 \src_r3 + end + sync always + update \src_r3$next $0\src_r3$next[3:0]$3222 + end + attribute \src "libresoc.v:50420.3-50429.6" + process $proc$libresoc.v:50420$3224 + assign { } { } + assign { } { } + assign $0\src_r4$next[3:0]$3225 $1\src_r4$next[3:0]$3226 + attribute \src "libresoc.v:50421.5-50421.29" + switch \initial + attribute \src "libresoc.v:50421.9-50421.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" + switch \src_l_q_src [4] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r4$next[3:0]$3226 \src5_i + case + assign $1\src_r4$next[3:0]$3226 \src_r4 + end + sync always + update \src_r4$next $0\src_r4$next[3:0]$3225 + end + attribute \src "libresoc.v:50430.3-50439.6" + process $proc$libresoc.v:50430$3227 + assign { } { } + assign { } { } + assign $0\src_r5$next[3:0]$3228 $1\src_r5$next[3:0]$3229 + attribute \src "libresoc.v:50431.5-50431.29" + switch \initial + attribute \src "libresoc.v:50431.9-50431.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" + switch \src_l_q_src [5] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r5$next[3:0]$3229 \src6_i + case + assign $1\src_r5$next[3:0]$3229 \src_r5 + end + sync always + update \src_r5$next $0\src_r5$next[3:0]$3228 + end + attribute \src "libresoc.v:50440.3-50448.6" + process $proc$libresoc.v:50440$3230 + assign { } { } + assign { } { } + assign $0\alui_l_r_alui$next[0:0]$3231 $1\alui_l_r_alui$next[0:0]$3232 + attribute \src "libresoc.v:50441.5-50441.29" + switch \initial + attribute \src "libresoc.v:50441.9-50441.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\alui_l_r_alui$next[0:0]$3232 1'1 + case + assign $1\alui_l_r_alui$next[0:0]$3232 \$89 + end + sync always + update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$3231 + end + attribute \src "libresoc.v:50449.3-50457.6" + process $proc$libresoc.v:50449$3233 + assign { } { } + assign { } { } + assign $0\alu_l_r_alu$next[0:0]$3234 $1\alu_l_r_alu$next[0:0]$3235 + attribute \src "libresoc.v:50450.5-50450.29" + switch \initial + attribute \src "libresoc.v:50450.9-50450.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\alu_l_r_alu$next[0:0]$3235 1'1 + case + assign $1\alu_l_r_alu$next[0:0]$3235 \$91 + end + sync always + update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$3234 + end + attribute \src "libresoc.v:50458.3-50467.6" + process $proc$libresoc.v:50458$3236 + assign { } { } + assign { } { } + assign $0\dest1_o[63:0] $1\dest1_o[63:0] + attribute \src "libresoc.v:50459.5-50459.29" + switch \initial + attribute \src "libresoc.v:50459.9-50459.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$111 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest1_o[63:0] \data_r0__o + case + assign $1\dest1_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \dest1_o $0\dest1_o[63:0] + end + attribute \src "libresoc.v:50468.3-50477.6" + process $proc$libresoc.v:50468$3237 + assign { } { } + assign { } { } + assign $0\dest2_o[31:0] $1\dest2_o[31:0] + attribute \src "libresoc.v:50469.5-50469.29" + switch \initial + attribute \src "libresoc.v:50469.9-50469.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$113 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest2_o[31:0] \data_r1__full_cr + case + assign $1\dest2_o[31:0] 0 + end + sync always + update \dest2_o $0\dest2_o[31:0] + end + attribute \src "libresoc.v:50478.3-50487.6" + process $proc$libresoc.v:50478$3238 + assign { } { } + assign { } { } + assign $0\dest3_o[3:0] $1\dest3_o[3:0] + attribute \src "libresoc.v:50479.5-50479.29" + switch \initial + attribute \src "libresoc.v:50479.9-50479.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$115 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest3_o[3:0] \data_r2__cr_a + case + assign $1\dest3_o[3:0] 4'0000 + end + sync always + update \dest3_o $0\dest3_o[3:0] + end + attribute \src "libresoc.v:50488.3-50496.6" + process $proc$libresoc.v:50488$3239 + assign { } { } + assign { } { } + assign $0\prev_wr_go$next[2:0]$3240 $1\prev_wr_go$next[2:0]$3241 + attribute \src "libresoc.v:50489.5-50489.29" + switch \initial + attribute \src "libresoc.v:50489.9-50489.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\prev_wr_go$next[2:0]$3241 3'000 + case + assign $1\prev_wr_go$next[2:0]$3241 \$21 + end + sync always + update \prev_wr_go$next $0\prev_wr_go$next[2:0]$3240 + end + connect \$5 $reduce_and$libresoc.v:50014$3063_Y + connect \$99 $and$libresoc.v:50015$3064_Y + connect \$101 $and$libresoc.v:50016$3065_Y + connect \$103 $and$libresoc.v:50017$3066_Y + connect \$105 $and$libresoc.v:50018$3067_Y + connect \$107 $and$libresoc.v:50019$3068_Y + connect \$109 $and$libresoc.v:50020$3069_Y + connect \$111 $and$libresoc.v:50021$3070_Y + connect \$113 $and$libresoc.v:50022$3071_Y + connect \$115 $and$libresoc.v:50023$3072_Y + connect \$11 $and$libresoc.v:50024$3073_Y + connect \$13 $not$libresoc.v:50025$3074_Y + connect \$15 $and$libresoc.v:50026$3075_Y + connect \$17 $not$libresoc.v:50027$3076_Y + connect \$19 $and$libresoc.v:50028$3077_Y + connect \$21 $and$libresoc.v:50029$3078_Y + connect \$25 $not$libresoc.v:50030$3079_Y + connect \$27 $and$libresoc.v:50031$3080_Y + connect \$24 $reduce_or$libresoc.v:50032$3081_Y + connect \$23 $not$libresoc.v:50033$3082_Y + connect \$31 $and$libresoc.v:50034$3083_Y + connect \$33 $reduce_or$libresoc.v:50035$3084_Y + connect \$35 $reduce_or$libresoc.v:50036$3085_Y + connect \$37 $or$libresoc.v:50037$3086_Y + connect \$3 $and$libresoc.v:50038$3087_Y + connect \$39 $not$libresoc.v:50039$3088_Y + connect \$41 $and$libresoc.v:50040$3089_Y + connect \$43 $and$libresoc.v:50041$3090_Y + connect \$45 $eq$libresoc.v:50042$3091_Y + connect \$47 $and$libresoc.v:50043$3092_Y + connect \$49 $eq$libresoc.v:50044$3093_Y + connect \$51 $and$libresoc.v:50045$3094_Y + connect \$53 $and$libresoc.v:50046$3095_Y + connect \$55 $and$libresoc.v:50047$3096_Y + connect \$57 $or$libresoc.v:50048$3097_Y + connect \$59 $or$libresoc.v:50049$3098_Y + connect \$61 $or$libresoc.v:50050$3099_Y + connect \$63 $or$libresoc.v:50051$3100_Y + connect \$65 $and$libresoc.v:50052$3101_Y + connect \$67 $and$libresoc.v:50053$3102_Y + connect \$6 $not$libresoc.v:50054$3103_Y + connect \$69 $or$libresoc.v:50055$3104_Y + connect \$71 $and$libresoc.v:50056$3105_Y + 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\$85 + connect \alu_cr0_cr_a$2 \$83 + connect \alu_cr0_full_cr$1 \$81 + connect \alu_cr0_rb \$79 + connect \alu_cr0_ra \$77 + connect \cu_wrmask_o { \$75 \$73 \$71 } + connect \reset_r \$63 + connect \reset_w \$61 + connect \rst_r \$59 + connect \reset \$57 + connect \wr_any \$37 + connect \cu_done_o \$31 + connect \alu_pulsem { \alu_pulse \alu_pulse \alu_pulse } + connect \alu_pulse \alu_done_rise + connect \alu_done_rise \$19 + connect \alu_done_dly$next \alu_done + connect \alu_done \alu_cr0_n_valid_o + connect \all_rd_pulse \all_rd_rise + connect \all_rd_rise \$15 + connect \all_rd_dly$next \all_rd + connect \all_rd \$11 +end +attribute \src "libresoc.v:50532.1-50635.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.crin_svdec" +attribute \generator "nMigen" +module \crin_svdec + attribute \src "libresoc.v:50622.3-50633.6" + wire width 7 $0\cr_out[6:0] + attribute \src "libresoc.v:50533.7-50533.20" + wire $0\initial[0:0] + attribute \src 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:90" + wire width 2 input 3 \etype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:89" + wire width 9 input 2 \extra + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:91" + wire width 3 input 1 \idx + attribute \src "libresoc.v:50533.7-50533.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:193" + wire output 6 \isvec + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" + wire width 3 \spec + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:215" + cell $pos $pos$libresoc.v:50562$3273 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 7 + connect \A { 2'00 \spec [1:0] \cr_in } + connect \Y $pos$libresoc.v:50562$3273_Y + end + attribute \src "libresoc.v:50533.7-50533.20" + process $proc$libresoc.v:50533$3276 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:50563.3-50621.6" + process $proc$libresoc.v:50563$3274 + assign { } { } + assign { } { } + assign $0\spec[2:0] $1\spec[2:0] + attribute \src "libresoc.v:50564.5-50564.29" + switch \initial + attribute \src "libresoc.v:50564.9-50564.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:104" + switch \etype + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign $1\spec[2:0] [0] 1'0 + assign $1\spec[2:0] [2:1] $2\spec[2:1] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:107" + switch \idx + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $2\spec[2:1] [1] \extra [8] + assign $2\spec[2:1] [0] \extra [7] + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $2\spec[2:1] [1] \extra [6] + assign $2\spec[2:1] [0] \extra [5] + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $2\spec[2:1] [1] \extra [4] + assign $2\spec[2:1] [0] \extra [3] + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $2\spec[2:1] [1] \extra [2] + assign $2\spec[2:1] [0] \extra [1] + case + assign $2\spec[2:1] 2'00 + end + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\spec[2:0] $3\spec[2:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:122" + switch \idx + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $3\spec[2:0] \extra [8:6] + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $3\spec[2:0] \extra [5:3] + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $3\spec[2:0] \extra [2:0] + case + assign $3\spec[2:0] 3'000 + end + case + assign $1\spec[2:0] 3'000 + end + sync always + update \spec $0\spec[2:0] + end + attribute \src "libresoc.v:50622.3-50633.6" + process $proc$libresoc.v:50622$3275 + assign { } { } + assign $0\cr_out[6:0] $1\cr_out[6:0] + attribute \src "libresoc.v:50623.5-50623.29" + switch \initial + attribute \src "libresoc.v:50623.9-50623.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:210" + switch \isvec + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cr_out[6:0] { \cr_in \spec [1:0] 2'00 } + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cr_out[6:0] \$1 + end + sync always + update \cr_out $0\cr_out[6:0] + end + connect \$1 $pos$libresoc.v:50562$3273_Y + connect \isvec \spec [2] +end +attribute \src "libresoc.v:50639.1-50742.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.crin_svdec_b" +attribute \generator "nMigen" +module \crin_svdec_b + attribute \src "libresoc.v:50729.3-50740.6" + wire width 7 $0\cr_out[6:0] + attribute \src "libresoc.v:50640.7-50640.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:50670.3-50728.6" + wire width 3 $0\spec[2:0] + attribute \src "libresoc.v:50729.3-50740.6" + wire width 7 $1\cr_out[6:0] + attribute \src "libresoc.v:50670.3-50728.6" + wire width 3 $1\spec[2:0] + attribute \src "libresoc.v:50670.3-50728.6" + wire width 2 $2\spec[2:1] + attribute \src "libresoc.v:50670.3-50728.6" + wire width 3 $3\spec[2:0] + attribute \src "libresoc.v:50669.17-50669.119" + wire width 7 $pos$libresoc.v:50669$3277_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:215" + wire width 7 \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" + wire width 3 input 4 \cr_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" + wire width 7 output 5 \cr_out + attribute \enum_base_type "SVEtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "EXTRA2" + attribute \enum_value_10 "EXTRA3" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:90" + wire width 2 input 3 \etype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:89" + wire width 9 input 2 \extra + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:91" + wire width 3 input 1 \idx + attribute \src "libresoc.v:50640.7-50640.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:193" + wire output 6 \isvec + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" + wire width 3 \spec + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:215" + cell $pos $pos$libresoc.v:50669$3277 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 7 + connect \A { 2'00 \spec [1:0] \cr_in } + connect \Y $pos$libresoc.v:50669$3277_Y + end + attribute \src "libresoc.v:50640.7-50640.20" + process $proc$libresoc.v:50640$3280 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:50670.3-50728.6" + process $proc$libresoc.v:50670$3278 + assign { } { } + assign { } { } + assign $0\spec[2:0] $1\spec[2:0] + attribute \src "libresoc.v:50671.5-50671.29" + switch \initial + attribute \src "libresoc.v:50671.9-50671.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:104" + switch \etype + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign $1\spec[2:0] [0] 1'0 + assign $1\spec[2:0] [2:1] $2\spec[2:1] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:107" + switch \idx + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $2\spec[2:1] [1] \extra [8] + assign $2\spec[2:1] [0] \extra [7] + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $2\spec[2:1] [1] \extra [6] + assign $2\spec[2:1] [0] \extra [5] + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $2\spec[2:1] [1] \extra [4] + assign $2\spec[2:1] [0] \extra [3] + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $2\spec[2:1] [1] \extra [2] + assign $2\spec[2:1] [0] \extra [1] + case + assign $2\spec[2:1] 2'00 + end + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\spec[2:0] $3\spec[2:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:122" + switch \idx + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $3\spec[2:0] \extra [8:6] + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $3\spec[2:0] \extra [5:3] + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $3\spec[2:0] \extra [2:0] + case + assign $3\spec[2:0] 3'000 + end + case + assign $1\spec[2:0] 3'000 + end + sync always + update \spec $0\spec[2:0] + end + attribute \src "libresoc.v:50729.3-50740.6" + process $proc$libresoc.v:50729$3279 + assign { } { } + assign $0\cr_out[6:0] $1\cr_out[6:0] + attribute \src "libresoc.v:50730.5-50730.29" + switch \initial + attribute \src "libresoc.v:50730.9-50730.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:210" + switch \isvec + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cr_out[6:0] { \cr_in \spec [1:0] 2'00 } + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cr_out[6:0] \$1 + end + sync always + update \cr_out $0\cr_out[6:0] + end + connect \$1 $pos$libresoc.v:50669$3277_Y + connect \isvec \spec [2] +end +attribute \src "libresoc.v:50746.1-50849.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.crin_svdec_o" +attribute \generator "nMigen" +module \crin_svdec_o + attribute \src "libresoc.v:50836.3-50847.6" + wire width 7 $0\cr_out[6:0] + attribute \src "libresoc.v:50747.7-50747.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:50777.3-50835.6" + wire width 3 $0\spec[2:0] + attribute \src "libresoc.v:50836.3-50847.6" + wire width 7 $1\cr_out[6:0] + attribute \src "libresoc.v:50777.3-50835.6" + wire width 3 $1\spec[2:0] + attribute \src "libresoc.v:50777.3-50835.6" + wire width 2 $2\spec[2:1] + attribute \src "libresoc.v:50777.3-50835.6" + wire width 3 $3\spec[2:0] + attribute \src "libresoc.v:50776.17-50776.119" + wire width 7 $pos$libresoc.v:50776$3281_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:215" + wire width 7 \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" + wire width 3 input 4 \cr_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" + wire width 7 output 5 \cr_out + attribute \enum_base_type "SVEtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "EXTRA2" + attribute \enum_value_10 "EXTRA3" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:90" + wire width 2 input 3 \etype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:89" + wire width 9 input 2 \extra + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:91" + wire width 3 input 1 \idx + attribute \src "libresoc.v:50747.7-50747.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:193" + wire output 6 \isvec + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" + wire width 3 \spec + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:215" + cell $pos $pos$libresoc.v:50776$3281 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 7 + connect \A { 2'00 \spec [1:0] \cr_in } + connect \Y $pos$libresoc.v:50776$3281_Y + end + attribute \src "libresoc.v:50747.7-50747.20" + process $proc$libresoc.v:50747$3284 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:50777.3-50835.6" + process $proc$libresoc.v:50777$3282 + assign { } { } + assign { } { } + assign $0\spec[2:0] $1\spec[2:0] + attribute \src "libresoc.v:50778.5-50778.29" + switch \initial + attribute \src "libresoc.v:50778.9-50778.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:104" + switch \etype + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign $1\spec[2:0] [0] 1'0 + assign $1\spec[2:0] [2:1] $2\spec[2:1] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:107" + switch \idx + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $2\spec[2:1] [1] \extra [8] + assign $2\spec[2:1] [0] \extra [7] + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $2\spec[2:1] [1] \extra [6] + assign $2\spec[2:1] [0] \extra [5] + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $2\spec[2:1] [1] \extra [4] + assign $2\spec[2:1] [0] \extra [3] + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $2\spec[2:1] [1] \extra [2] + assign $2\spec[2:1] [0] \extra [1] + case + assign $2\spec[2:1] 2'00 + end + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\spec[2:0] $3\spec[2:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:122" + switch \idx + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $3\spec[2:0] \extra [8:6] + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $3\spec[2:0] \extra [5:3] + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $3\spec[2:0] \extra [2:0] + case + assign $3\spec[2:0] 3'000 + end + case + assign $1\spec[2:0] 3'000 + end + sync always + update \spec $0\spec[2:0] + end + attribute \src "libresoc.v:50836.3-50847.6" + process $proc$libresoc.v:50836$3283 + assign { } { } + assign $0\cr_out[6:0] $1\cr_out[6:0] + attribute \src "libresoc.v:50837.5-50837.29" + switch \initial + attribute \src "libresoc.v:50837.9-50837.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:210" + switch \isvec + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cr_out[6:0] { \cr_in \spec [1:0] 2'00 } + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cr_out[6:0] \$1 + end + sync always + update \cr_out $0\cr_out[6:0] + end + connect \$1 $pos$libresoc.v:50776$3281_Y + connect \isvec \spec [2] +end +attribute \src "libresoc.v:50853.1-50956.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.crout_svdec" +attribute \generator "nMigen" +module \crout_svdec + attribute \src "libresoc.v:50943.3-50954.6" + wire width 7 $0\cr_out[6:0] + attribute \src "libresoc.v:50854.7-50854.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:50884.3-50942.6" + wire width 3 $0\spec[2:0] + attribute \src "libresoc.v:50943.3-50954.6" + wire width 7 $1\cr_out[6:0] + attribute \src "libresoc.v:50884.3-50942.6" + wire width 3 $1\spec[2:0] + attribute \src "libresoc.v:50884.3-50942.6" + wire width 2 $2\spec[2:1] + attribute \src "libresoc.v:50884.3-50942.6" + wire width 3 $3\spec[2:0] + attribute \src "libresoc.v:50883.17-50883.119" + wire width 7 $pos$libresoc.v:50883$3285_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:215" + wire width 7 \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" + wire width 3 input 4 \cr_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" + wire width 7 output 5 \cr_out + attribute \enum_base_type "SVEtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "EXTRA2" + attribute \enum_value_10 "EXTRA3" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:90" + wire width 2 input 3 \etype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:89" + wire width 9 input 2 \extra + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:91" + wire width 3 input 6 \idx + attribute \src "libresoc.v:50854.7-50854.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:193" + wire output 1 \isvec + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" + wire width 3 \spec + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:215" + cell $pos $pos$libresoc.v:50883$3285 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 7 + connect \A { 2'00 \spec [1:0] \cr_in } + connect \Y $pos$libresoc.v:50883$3285_Y + end + attribute \src "libresoc.v:50854.7-50854.20" + process $proc$libresoc.v:50854$3288 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:50884.3-50942.6" + process $proc$libresoc.v:50884$3286 + assign { } { } + assign { } { } + assign $0\spec[2:0] $1\spec[2:0] + attribute \src "libresoc.v:50885.5-50885.29" + switch \initial + attribute \src "libresoc.v:50885.9-50885.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:104" + switch \etype + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign $1\spec[2:0] [0] 1'0 + assign $1\spec[2:0] [2:1] $2\spec[2:1] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:107" + switch \idx + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $2\spec[2:1] [1] \extra [8] + assign $2\spec[2:1] [0] \extra [7] + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $2\spec[2:1] [1] \extra [6] + assign $2\spec[2:1] [0] \extra [5] + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $2\spec[2:1] [1] \extra [4] + assign $2\spec[2:1] [0] \extra [3] + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $2\spec[2:1] [1] \extra [2] + assign $2\spec[2:1] [0] \extra [1] + case + assign $2\spec[2:1] 2'00 + end + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\spec[2:0] $3\spec[2:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:122" + switch \idx + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $3\spec[2:0] \extra [8:6] + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $3\spec[2:0] \extra [5:3] + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $3\spec[2:0] \extra [2:0] + case + assign $3\spec[2:0] 3'000 + end + case + assign $1\spec[2:0] 3'000 + end + sync always + update \spec $0\spec[2:0] + end + attribute \src "libresoc.v:50943.3-50954.6" + process $proc$libresoc.v:50943$3287 + assign { } { } + assign $0\cr_out[6:0] $1\cr_out[6:0] + attribute \src "libresoc.v:50944.5-50944.29" + switch \initial + attribute \src "libresoc.v:50944.9-50944.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:210" + switch \isvec + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cr_out[6:0] { \cr_in \spec [1:0] 2'00 } + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cr_out[6:0] \$1 + end + sync always + update \cr_out $0\cr_out[6:0] + end + connect \$1 $pos$libresoc.v:50883$3285_Y + connect \isvec \spec [2] +end +attribute \src "libresoc.v:50960.1-51009.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem.cyc_l" +attribute \generator "nMigen" +module \cyc_l + attribute \src "libresoc.v:50961.7-50961.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:50997.3-51005.6" + wire $0\q_int$next[0:0]$3296 + attribute \src "libresoc.v:50995.3-50996.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:50997.3-51005.6" + wire $1\q_int$next[0:0]$3297 + attribute \src "libresoc.v:50979.7-50979.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:50992.17-50992.96" + wire $and$libresoc.v:50992$3291_Y + attribute \src "libresoc.v:50991.17-50991.92" + wire $not$libresoc.v:50991$3290_Y + attribute \src "libresoc.v:50994.17-50994.92" + wire $not$libresoc.v:50994$3293_Y + attribute \src "libresoc.v:50990.17-50990.98" + wire $or$libresoc.v:50990$3289_Y + attribute \src "libresoc.v:50993.17-50993.97" + wire $or$libresoc.v:50993$3292_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 1 \coresync_rst + attribute \src "libresoc.v:50961.7-50961.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire output 4 \q_cyc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" + wire \qlq_cyc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \qn_cyc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire input 3 \r_cyc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire input 2 \s_cyc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:50992$3291 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:50992$3291_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:50991$3290 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_cyc + connect \Y $not$libresoc.v:50991$3290_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:50994$3293 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_cyc + connect \Y $not$libresoc.v:50994$3293_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:50990$3289 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_cyc + connect \B \q_int + connect \Y $or$libresoc.v:50990$3289_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:50993$3292 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_cyc + connect \Y $or$libresoc.v:50993$3292_Y + end + attribute \src "libresoc.v:50961.7-50961.20" + process $proc$libresoc.v:50961$3298 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:50979.7-50979.19" + process $proc$libresoc.v:50979$3299 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:50995.3-50996.27" + process $proc$libresoc.v:50995$3294 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:50997.3-51005.6" + process $proc$libresoc.v:50997$3295 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$3296 $1\q_int$next[0:0]$3297 + attribute \src "libresoc.v:50998.5-50998.29" + switch \initial + attribute \src "libresoc.v:50998.9-50998.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$3297 1'0 + case + assign $1\q_int$next[0:0]$3297 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$3296 + end + connect \$9 $or$libresoc.v:50990$3289_Y + connect \$1 $not$libresoc.v:50991$3290_Y + connect \$3 $and$libresoc.v:50992$3291_Y + connect \$5 $or$libresoc.v:50993$3292_Y + connect \$7 $not$libresoc.v:50994$3293_Y + connect \qlq_cyc \$9 + connect \qn_cyc \$7 + connect \q_cyc \q_int +end +attribute \src "libresoc.v:51013.1-51727.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dbg" +attribute \generator "nMigen" +module \dbg + attribute \src "libresoc.v:51543.3-51552.6" + wire $0\d_cr_req[0:0] + attribute \src "libresoc.v:51350.3-51359.6" + wire $0\d_gpr_req[0:0] + attribute \src "libresoc.v:51553.3-51562.6" + wire $0\d_xer_req[0:0] + attribute \src "libresoc.v:51332.3-51349.6" + wire $0\dmi_ack_o[0:0] + attribute \src "libresoc.v:51563.3-51593.6" + wire width 64 $0\dmi_dout[63:0] + attribute \src "libresoc.v:51534.3-51542.6" + wire $0\dmi_read_log_data$next[0:0]$3413 + attribute \src "libresoc.v:51310.3-51311.51" + wire $0\dmi_read_log_data[0:0] + attribute \src "libresoc.v:51525.3-51533.6" + wire $0\dmi_read_log_data_1$next[0:0]$3410 + attribute \src "libresoc.v:51312.3-51313.55" + wire $0\dmi_read_log_data_1[0:0] + attribute \src "libresoc.v:51360.3-51368.6" + wire $0\dmi_req_i_1$next[0:0]$3376 + attribute \src "libresoc.v:51322.3-51323.39" + wire $0\dmi_req_i_1[0:0] + attribute \src "libresoc.v:51684.3-51717.6" + wire $0\do_dmi_log_rd$next[0:0]$3440 + attribute \src "libresoc.v:51324.3-51325.43" + wire $0\do_dmi_log_rd[0:0] + attribute \src "libresoc.v:51654.3-51683.6" + wire $0\do_icreset$next[0:0]$3433 + attribute \src "libresoc.v:51326.3-51327.37" + wire $0\do_icreset[0:0] + attribute \src "libresoc.v:51624.3-51653.6" + wire $0\do_reset$next[0:0]$3426 + attribute \src "libresoc.v:51328.3-51329.33" + wire $0\do_reset[0:0] + attribute \src "libresoc.v:51594.3-51623.6" + wire $0\do_step$next[0:0]$3419 + attribute \src "libresoc.v:51330.3-51331.31" + wire $0\do_step[0:0] + attribute \src "libresoc.v:51463.3-51490.6" + wire width 7 $0\gspr_index$next[6:0]$3398 + attribute \src "libresoc.v:51316.3-51317.37" + wire width 7 $0\gspr_index[6:0] + attribute \src "libresoc.v:51014.7-51014.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:51491.3-51524.6" + wire width 32 $0\log_dmi_addr$next[31:0]$3404 + attribute \src "libresoc.v:51314.3-51315.41" + wire width 32 $0\log_dmi_addr[31:0] + attribute \src "libresoc.v:51419.3-51462.6" + wire $0\stopping$next[0:0]$3389 + attribute \src "libresoc.v:51318.3-51319.33" + wire $0\stopping[0:0] + attribute \src "libresoc.v:51369.3-51418.6" + wire $0\terminated$next[0:0]$3379 + attribute \src "libresoc.v:51320.3-51321.37" + wire $0\terminated[0:0] + attribute \src "libresoc.v:51543.3-51552.6" + wire $1\d_cr_req[0:0] + attribute \src "libresoc.v:51350.3-51359.6" + wire $1\d_gpr_req[0:0] + attribute \src "libresoc.v:51553.3-51562.6" + wire $1\d_xer_req[0:0] + attribute \src "libresoc.v:51332.3-51349.6" + wire $1\dmi_ack_o[0:0] + attribute \src "libresoc.v:51563.3-51593.6" + wire width 64 $1\dmi_dout[63:0] + attribute \src "libresoc.v:51534.3-51542.6" + wire $1\dmi_read_log_data$next[0:0]$3414 + attribute \src "libresoc.v:51187.7-51187.31" + wire $1\dmi_read_log_data[0:0] + attribute \src "libresoc.v:51525.3-51533.6" + wire $1\dmi_read_log_data_1$next[0:0]$3411 + attribute \src "libresoc.v:51191.7-51191.33" + wire $1\dmi_read_log_data_1[0:0] + attribute \src "libresoc.v:51360.3-51368.6" + wire $1\dmi_req_i_1$next[0:0]$3377 + attribute \src "libresoc.v:51197.7-51197.25" + wire $1\dmi_req_i_1[0:0] + attribute \src "libresoc.v:51684.3-51717.6" + wire $1\do_dmi_log_rd$next[0:0]$3441 + attribute \src "libresoc.v:51203.7-51203.27" + wire $1\do_dmi_log_rd[0:0] + attribute \src "libresoc.v:51654.3-51683.6" + wire $1\do_icreset$next[0:0]$3434 + attribute \src "libresoc.v:51207.7-51207.24" + wire $1\do_icreset[0:0] + attribute \src "libresoc.v:51624.3-51653.6" + wire $1\do_reset$next[0:0]$3427 + attribute \src "libresoc.v:51211.7-51211.22" + wire $1\do_reset[0:0] + attribute \src "libresoc.v:51594.3-51623.6" + wire $1\do_step$next[0:0]$3420 + attribute \src "libresoc.v:51215.7-51215.21" + wire $1\do_step[0:0] + attribute \src "libresoc.v:51463.3-51490.6" + wire width 7 $1\gspr_index$next[6:0]$3399 + attribute \src "libresoc.v:51219.13-51219.31" + wire width 7 $1\gspr_index[6:0] + attribute \src "libresoc.v:51491.3-51524.6" + wire width 32 $1\log_dmi_addr$next[31:0]$3405 + attribute \src "libresoc.v:51225.14-51225.34" + wire width 32 $1\log_dmi_addr[31:0] + attribute \src "libresoc.v:51419.3-51462.6" + wire $1\stopping$next[0:0]$3390 + attribute \src "libresoc.v:51237.7-51237.22" + wire $1\stopping[0:0] + attribute \src "libresoc.v:51369.3-51418.6" + wire $1\terminated$next[0:0]$3380 + attribute \src "libresoc.v:51243.7-51243.24" + wire $1\terminated[0:0] + attribute \src "libresoc.v:51684.3-51717.6" + wire $2\do_dmi_log_rd$next[0:0]$3442 + attribute \src "libresoc.v:51654.3-51683.6" + wire $2\do_icreset$next[0:0]$3435 + attribute \src "libresoc.v:51624.3-51653.6" + wire $2\do_reset$next[0:0]$3428 + attribute \src "libresoc.v:51594.3-51623.6" + wire $2\do_step$next[0:0]$3421 + attribute \src "libresoc.v:51463.3-51490.6" + wire width 7 $2\gspr_index$next[6:0]$3400 + attribute \src "libresoc.v:51491.3-51524.6" + wire width 32 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\dmi_addr_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:58" + wire width 64 input 5 \dmi_din + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:59" + wire width 64 output 7 \dmi_dout + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:148" + wire \dmi_read_log_data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:148" + wire \dmi_read_log_data$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:149" + wire \dmi_read_log_data_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:149" + wire \dmi_read_log_data_1$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:60" + wire input 3 \dmi_req_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:131" + wire \dmi_req_i_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:131" + wire \dmi_req_i_1$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:61" + wire input 4 \dmi_we_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:147" + wire \do_dmi_log_rd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:147" + wire \do_dmi_log_rd$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:140" + wire \do_icreset + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:140" + wire \do_icreset$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:139" + wire \do_reset + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:139" + wire \do_reset$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:138" + wire \do_step + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:138" + wire \do_step$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:143" + wire width 7 \gspr_index + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:143" + wire width 7 \gspr_index$next + attribute \src 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"/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:227" + cell $eq $eq$libresoc.v:51303$3355 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 3'110 + connect \Y $eq$libresoc.v:51303$3355_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" + cell $eq $eq$libresoc.v:51308$3360 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 1'0 + connect \Y $eq$libresoc.v:51308$3360_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:223" + cell $eq $eq$libresoc.v:51309$3361 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 3'100 + connect \Y $eq$libresoc.v:51309$3361_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + cell $not $not$libresoc.v:51250$3302 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_req_i_1 + connect \Y $not$libresoc.v:51250$3302_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" + cell $not $not$libresoc.v:51252$3304 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_read_log_data + connect \Y $not$libresoc.v:51252$3304_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:254" + cell $not $not$libresoc.v:51261$3313 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \do_step + connect \Y $not$libresoc.v:51261$3313_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + cell $not $not$libresoc.v:51265$3317 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_req_i_1 + connect \Y $not$libresoc.v:51265$3317_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" + cell $not $not$libresoc.v:51268$3320 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_read_log_data + connect \Y $not$libresoc.v:51268$3320_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + cell $not $not$libresoc.v:51273$3325 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_req_i_1 + connect \Y $not$libresoc.v:51273$3325_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" + cell $not $not$libresoc.v:51275$3327 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_read_log_data + connect \Y $not$libresoc.v:51275$3327_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + cell $not $not$libresoc.v:51277$3329 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_req_i_1 + connect \Y $not$libresoc.v:51277$3329_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + cell $not $not$libresoc.v:51281$3333 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_req_i_1 + connect \Y $not$libresoc.v:51281$3333_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" + cell $not $not$libresoc.v:51283$3335 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_read_log_data + connect \Y $not$libresoc.v:51283$3335_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + cell $not $not$libresoc.v:51289$3341 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_req_i_1 + connect \Y $not$libresoc.v:51289$3341_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" + cell $not $not$libresoc.v:51291$3343 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_read_log_data + connect \Y $not$libresoc.v:51291$3343_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + cell $not $not$libresoc.v:51296$3348 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_req_i_1 + connect \Y $not$libresoc.v:51296$3348_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" + cell $not $not$libresoc.v:51298$3350 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_read_log_data + connect \Y $not$libresoc.v:51298$3350_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" + cell $not $not$libresoc.v:51299$3351 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_read_log_data + connect \Y $not$libresoc.v:51299$3351_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + cell $not $not$libresoc.v:51304$3356 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_req_i_1 + connect \Y $not$libresoc.v:51304$3356_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" + cell $not $not$libresoc.v:51306$3358 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_read_log_data + connect \Y $not$libresoc.v:51306$3358_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:170" + cell $pos $pos$libresoc.v:51266$3318 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A { 61'0000000000000000000000000000000000000000000000000000000000000 \terminated \core_stopped_i \stopping } + connect \Y $pos$libresoc.v:51266$3318_Y + end + attribute \src "libresoc.v:51014.7-51014.20" + process $proc$libresoc.v:51014$3445 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:51187.7-51187.31" + process $proc$libresoc.v:51187$3446 + assign { } { } + assign $1\dmi_read_log_data[0:0] 1'0 + sync always + sync init + update \dmi_read_log_data $1\dmi_read_log_data[0:0] + end + attribute \src "libresoc.v:51191.7-51191.33" + process $proc$libresoc.v:51191$3447 + assign { } { } + assign $1\dmi_read_log_data_1[0:0] 1'0 + sync always + sync init + update \dmi_read_log_data_1 $1\dmi_read_log_data_1[0:0] + end + attribute \src "libresoc.v:51197.7-51197.25" + process $proc$libresoc.v:51197$3448 + assign { } { } + assign $1\dmi_req_i_1[0:0] 1'0 + sync always + sync init + update \dmi_req_i_1 $1\dmi_req_i_1[0:0] + end + attribute \src "libresoc.v:51203.7-51203.27" + process $proc$libresoc.v:51203$3449 + assign { } { } + assign $1\do_dmi_log_rd[0:0] 1'0 + sync always + sync init + update \do_dmi_log_rd $1\do_dmi_log_rd[0:0] + end + attribute \src "libresoc.v:51207.7-51207.24" + process $proc$libresoc.v:51207$3450 + assign { } { } + assign $1\do_icreset[0:0] 1'0 + sync always + sync init + update \do_icreset $1\do_icreset[0:0] + end + attribute \src "libresoc.v:51211.7-51211.22" + process $proc$libresoc.v:51211$3451 + assign { } { } + assign $1\do_reset[0:0] 1'0 + sync always + sync init + update \do_reset $1\do_reset[0:0] + end + attribute \src "libresoc.v:51215.7-51215.21" + process $proc$libresoc.v:51215$3452 + assign { } { } + assign $1\do_step[0:0] 1'0 + sync always + sync init + update \do_step $1\do_step[0:0] + end + attribute \src "libresoc.v:51219.13-51219.31" + process $proc$libresoc.v:51219$3453 + assign { } { } + assign $1\gspr_index[6:0] 7'0000000 + sync always + sync init + update \gspr_index $1\gspr_index[6:0] + end + attribute \src "libresoc.v:51225.14-51225.34" + process $proc$libresoc.v:51225$3454 + assign { } { } + assign $1\log_dmi_addr[31:0] 0 + sync always + sync init + update \log_dmi_addr $1\log_dmi_addr[31:0] + end + attribute \src "libresoc.v:51237.7-51237.22" + process $proc$libresoc.v:51237$3455 + assign { } { } + assign $1\stopping[0:0] 1'0 + sync always + sync init + update \stopping $1\stopping[0:0] + end + attribute \src "libresoc.v:51243.7-51243.24" + process $proc$libresoc.v:51243$3456 + assign { } { } + assign $1\terminated[0:0] 1'0 + sync always + sync init + update \terminated $1\terminated[0:0] + end + attribute \src "libresoc.v:51310.3-51311.51" + process $proc$libresoc.v:51310$3362 + assign { } { } + assign $0\dmi_read_log_data[0:0] \dmi_read_log_data$next + sync posedge \clk + update \dmi_read_log_data $0\dmi_read_log_data[0:0] + end + attribute \src "libresoc.v:51312.3-51313.55" + process $proc$libresoc.v:51312$3363 + assign { } { } + assign $0\dmi_read_log_data_1[0:0] \dmi_read_log_data_1$next + sync posedge \clk + update \dmi_read_log_data_1 $0\dmi_read_log_data_1[0:0] + end + attribute \src "libresoc.v:51314.3-51315.41" + process $proc$libresoc.v:51314$3364 + assign { } { } + assign $0\log_dmi_addr[31:0] \log_dmi_addr$next + sync posedge \clk + update \log_dmi_addr $0\log_dmi_addr[31:0] + end + attribute \src "libresoc.v:51316.3-51317.37" + process $proc$libresoc.v:51316$3365 + assign { } { } + assign $0\gspr_index[6:0] \gspr_index$next + sync posedge \clk + update \gspr_index $0\gspr_index[6:0] + end + attribute \src "libresoc.v:51318.3-51319.33" + process $proc$libresoc.v:51318$3366 + assign { } { } + assign $0\stopping[0:0] \stopping$next + sync posedge \clk + update \stopping $0\stopping[0:0] + end + attribute \src "libresoc.v:51320.3-51321.37" + process $proc$libresoc.v:51320$3367 + assign { } { } + assign $0\terminated[0:0] \terminated$next + sync posedge \clk + update \terminated $0\terminated[0:0] + end + attribute \src "libresoc.v:51322.3-51323.39" + process $proc$libresoc.v:51322$3368 + assign { } { } + assign $0\dmi_req_i_1[0:0] \dmi_req_i_1$next + sync posedge \clk + update \dmi_req_i_1 $0\dmi_req_i_1[0:0] + end + attribute \src "libresoc.v:51324.3-51325.43" + process $proc$libresoc.v:51324$3369 + assign { } { } + assign $0\do_dmi_log_rd[0:0] \do_dmi_log_rd$next + sync posedge \clk + update \do_dmi_log_rd $0\do_dmi_log_rd[0:0] + end + attribute \src "libresoc.v:51326.3-51327.37" + process $proc$libresoc.v:51326$3370 + assign { } { } + assign $0\do_icreset[0:0] \do_icreset$next + sync posedge \clk + update \do_icreset $0\do_icreset[0:0] + end + attribute \src "libresoc.v:51328.3-51329.33" + process $proc$libresoc.v:51328$3371 + assign { } { } + assign $0\do_reset[0:0] \do_reset$next + sync posedge \clk + update \do_reset $0\do_reset[0:0] + end + attribute \src "libresoc.v:51330.3-51331.31" + process $proc$libresoc.v:51330$3372 + assign { } { } + assign $0\do_step[0:0] \do_step$next + sync posedge \clk + update \do_step $0\do_step[0:0] + end + attribute \src "libresoc.v:51332.3-51349.6" + process $proc$libresoc.v:51332$3373 + assign { } { } + assign $0\dmi_ack_o[0:0] $1\dmi_ack_o[0:0] + attribute \src "libresoc.v:51333.5-51333.29" + switch \initial + attribute \src "libresoc.v:51333.9-51333.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:154" + switch \dmi_addr_i + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dmi_ack_o[0:0] \d_gpr_ack + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dmi_ack_o[0:0] \d_cr_ack + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dmi_ack_o[0:0] \d_xer_ack + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\dmi_ack_o[0:0] \dmi_req_i + end + sync always + update \dmi_ack_o $0\dmi_ack_o[0:0] + end + attribute \src "libresoc.v:51350.3-51359.6" + process $proc$libresoc.v:51350$3374 + assign { } { } + assign { } { } + assign $0\d_gpr_req[0:0] $1\d_gpr_req[0:0] + attribute \src "libresoc.v:51351.5-51351.29" + switch \initial + attribute \src "libresoc.v:51351.9-51351.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:154" + switch \dmi_addr_i + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\d_gpr_req[0:0] \dmi_req_i + case + assign $1\d_gpr_req[0:0] 1'0 + end + sync always + update \d_gpr_req $0\d_gpr_req[0:0] + end + attribute \src "libresoc.v:51360.3-51368.6" + process $proc$libresoc.v:51360$3375 + assign { } { } + assign { } { } + assign $0\dmi_req_i_1$next[0:0]$3376 $1\dmi_req_i_1$next[0:0]$3377 + attribute \src "libresoc.v:51361.5-51361.29" + switch \initial + attribute \src "libresoc.v:51361.9-51361.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dmi_req_i_1$next[0:0]$3377 1'0 + case + assign $1\dmi_req_i_1$next[0:0]$3377 \dmi_req_i + end + sync always + update \dmi_req_i_1$next $0\dmi_req_i_1$next[0:0]$3376 + end + attribute \src "libresoc.v:51369.3-51418.6" + process $proc$libresoc.v:51369$3378 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\terminated$next[0:0]$3379 $8\terminated$next[0:0]$3387 + attribute \src "libresoc.v:51370.5-51370.29" + switch \initial + attribute \src "libresoc.v:51370.9-51370.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + switch { \$65 \$61 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\terminated$next[0:0]$3380 $2\terminated$next[0:0]$3381 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:201" + switch \dmi_we_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\terminated$next[0:0]$3381 $3\terminated$next[0:0]$3382 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" + switch { \$71 \$69 \$67 } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign { } { } + assign { } { } + assign { } { } + assign $3\terminated$next[0:0]$3382 $6\terminated$next[0:0]$3385 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:208" + switch \dmi_din [1] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\terminated$next[0:0]$3383 1'0 + case + assign $4\terminated$next[0:0]$3383 \terminated + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:213" + switch \dmi_din [3] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\terminated$next[0:0]$3384 1'0 + case + assign $5\terminated$next[0:0]$3384 $4\terminated$next[0:0]$3383 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:218" + switch \dmi_din [4] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\terminated$next[0:0]$3385 1'0 + case + assign $6\terminated$next[0:0]$3385 $5\terminated$next[0:0]$3384 + end + case + assign $3\terminated$next[0:0]$3382 \terminated + end + case + assign $2\terminated$next[0:0]$3381 \terminated + end + case + assign $1\terminated$next[0:0]$3380 \terminated + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:247" + switch \terminate_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\terminated$next[0:0]$3386 1'1 + case + assign $7\terminated$next[0:0]$3386 $1\terminated$next[0:0]$3380 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $8\terminated$next[0:0]$3387 1'0 + case + assign $8\terminated$next[0:0]$3387 $7\terminated$next[0:0]$3386 + end + sync always + update \terminated$next $0\terminated$next[0:0]$3379 + end + attribute \src "libresoc.v:51419.3-51462.6" + process $proc$libresoc.v:51419$3388 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\stopping$next[0:0]$3389 $7\stopping$next[0:0]$3396 + attribute \src "libresoc.v:51420.5-51420.29" + switch \initial + attribute \src "libresoc.v:51420.9-51420.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + switch { \$79 \$75 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\stopping$next[0:0]$3390 $2\stopping$next[0:0]$3391 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:201" + switch \dmi_we_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\stopping$next[0:0]$3391 $3\stopping$next[0:0]$3392 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" + switch { \$85 \$83 \$81 } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign { } { } + assign { } { } + assign $3\stopping$next[0:0]$3392 $5\stopping$next[0:0]$3394 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:211" + switch \dmi_din [0] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\stopping$next[0:0]$3393 1'1 + case + assign $4\stopping$next[0:0]$3393 \stopping + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:218" + switch \dmi_din [4] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\stopping$next[0:0]$3394 1'0 + case + assign $5\stopping$next[0:0]$3394 $4\stopping$next[0:0]$3393 + end + case + assign $3\stopping$next[0:0]$3392 \stopping + end + case + assign $2\stopping$next[0:0]$3391 \stopping + end + case + assign $1\stopping$next[0:0]$3390 \stopping + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:247" + switch \terminate_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\stopping$next[0:0]$3395 1'1 + case + assign $6\stopping$next[0:0]$3395 $1\stopping$next[0:0]$3390 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\stopping$next[0:0]$3396 1'0 + case + assign $7\stopping$next[0:0]$3396 $6\stopping$next[0:0]$3395 + end + sync always + update \stopping$next $0\stopping$next[0:0]$3389 + end + attribute \src "libresoc.v:51463.3-51490.6" + process $proc$libresoc.v:51463$3397 + assign { } { } + assign { } { } + assign { } { } + assign $0\gspr_index$next[6:0]$3398 $4\gspr_index$next[6:0]$3402 + attribute \src "libresoc.v:51464.5-51464.29" + switch \initial + attribute \src "libresoc.v:51464.9-51464.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + switch { \$93 \$89 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\gspr_index$next[6:0]$3399 $2\gspr_index$next[6:0]$3400 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:201" + switch \dmi_we_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\gspr_index$next[6:0]$3400 $3\gspr_index$next[6:0]$3401 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" + switch { \$99 \$97 \$95 } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign $3\gspr_index$next[6:0]$3401 \gspr_index + attribute \src "libresoc.v:0.0-0.0" + case 3'-1- + assign { } { } + assign $3\gspr_index$next[6:0]$3401 \dmi_din [6:0] + case + assign $3\gspr_index$next[6:0]$3401 \gspr_index + end + case + assign $2\gspr_index$next[6:0]$3400 \gspr_index + end + case + assign $1\gspr_index$next[6:0]$3399 \gspr_index + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\gspr_index$next[6:0]$3402 7'0000000 + case + assign $4\gspr_index$next[6:0]$3402 $1\gspr_index$next[6:0]$3399 + end + sync always + update \gspr_index$next $0\gspr_index$next[6:0]$3398 + end + attribute \src "libresoc.v:51491.3-51524.6" + process $proc$libresoc.v:51491$3403 + assign { } { } + assign { } { } + assign { } { } + assign $0\log_dmi_addr$next[31:0]$3404 $4\log_dmi_addr$next[31:0]$3408 + attribute \src "libresoc.v:51492.5-51492.29" + switch \initial + attribute \src "libresoc.v:51492.9-51492.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + switch { \$107 \$103 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\log_dmi_addr$next[31:0]$3405 $2\log_dmi_addr$next[31:0]$3406 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:201" + switch \dmi_we_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\log_dmi_addr$next[31:0]$3406 $3\log_dmi_addr$next[31:0]$3407 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" + switch { \$113 \$111 \$109 } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign $3\log_dmi_addr$next[31:0]$3407 \log_dmi_addr + attribute \src "libresoc.v:0.0-0.0" + case 3'-1- + assign $3\log_dmi_addr$next[31:0]$3407 \log_dmi_addr + attribute \src "libresoc.v:0.0-0.0" + case 3'1-- + assign { } { } + assign $3\log_dmi_addr$next[31:0]$3407 \dmi_din [31:0] + case + assign $3\log_dmi_addr$next[31:0]$3407 \log_dmi_addr + end + case + assign $2\log_dmi_addr$next[31:0]$3406 \log_dmi_addr + end + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign $1\log_dmi_addr$next[31:0]$3405 [31:2] \log_dmi_addr [31:2] + assign $1\log_dmi_addr$next[31:0]$3405 [1:0] \$115 [1:0] + case + assign $1\log_dmi_addr$next[31:0]$3405 \log_dmi_addr + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\log_dmi_addr$next[31:0]$3408 0 + case + assign $4\log_dmi_addr$next[31:0]$3408 $1\log_dmi_addr$next[31:0]$3405 + end + sync always + update \log_dmi_addr$next $0\log_dmi_addr$next[31:0]$3404 + end + attribute \src "libresoc.v:51525.3-51533.6" + process $proc$libresoc.v:51525$3409 + assign { } { } + assign { } { } + assign $0\dmi_read_log_data_1$next[0:0]$3410 $1\dmi_read_log_data_1$next[0:0]$3411 + attribute \src "libresoc.v:51526.5-51526.29" + switch \initial + attribute \src "libresoc.v:51526.9-51526.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dmi_read_log_data_1$next[0:0]$3411 1'0 + case + assign $1\dmi_read_log_data_1$next[0:0]$3411 \dmi_read_log_data + end + sync always + update \dmi_read_log_data_1$next $0\dmi_read_log_data_1$next[0:0]$3410 + end + attribute \src "libresoc.v:51534.3-51542.6" + process $proc$libresoc.v:51534$3412 + assign { } { } + assign { } { } + assign $0\dmi_read_log_data$next[0:0]$3413 $1\dmi_read_log_data$next[0:0]$3414 + attribute \src "libresoc.v:51535.5-51535.29" + switch \initial + attribute \src "libresoc.v:51535.9-51535.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dmi_read_log_data$next[0:0]$3414 1'0 + case + assign $1\dmi_read_log_data$next[0:0]$3414 \$120 + end + sync always + update \dmi_read_log_data$next $0\dmi_read_log_data$next[0:0]$3413 + end + attribute \src "libresoc.v:51543.3-51552.6" + process $proc$libresoc.v:51543$3415 + assign { } { } + assign { } { } + assign $0\d_cr_req[0:0] $1\d_cr_req[0:0] + attribute \src "libresoc.v:51544.5-51544.29" + switch \initial + attribute \src "libresoc.v:51544.9-51544.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:154" + switch \dmi_addr_i + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\d_cr_req[0:0] \dmi_req_i + case + assign $1\d_cr_req[0:0] 1'0 + end + sync always + update \d_cr_req $0\d_cr_req[0:0] + end + attribute \src "libresoc.v:51553.3-51562.6" + process $proc$libresoc.v:51553$3416 + assign { } { } + assign { } { } + assign $0\d_xer_req[0:0] $1\d_xer_req[0:0] + attribute \src "libresoc.v:51554.5-51554.29" + switch \initial + attribute \src "libresoc.v:51554.9-51554.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:154" + switch \dmi_addr_i + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\d_xer_req[0:0] \dmi_req_i + case + assign $1\d_xer_req[0:0] 1'0 + end + sync always + update \d_xer_req $0\d_xer_req[0:0] + end + attribute \src "libresoc.v:51563.3-51593.6" + process $proc$libresoc.v:51563$3417 + assign { } { } + assign { } { } + assign $0\dmi_dout[63:0] $1\dmi_dout[63:0] + attribute \src "libresoc.v:51564.5-51564.29" + switch \initial + attribute \src "libresoc.v:51564.9-51564.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:173" + switch \dmi_addr_i + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dmi_dout[63:0] \stat_reg + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dmi_dout[63:0] \core_dbg_pc + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dmi_dout[63:0] \core_dbg_msr + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dmi_dout[63:0] \d_gpr_data + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dmi_dout[63:0] { \log_write_addr_o \log_dmi_addr } + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dmi_dout[63:0] \log_dmi_data + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dmi_dout[63:0] \d_cr_data + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dmi_dout[63:0] \d_xer_data + case + assign $1\dmi_dout[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \dmi_dout $0\dmi_dout[63:0] + end + attribute \src "libresoc.v:51594.3-51623.6" + process $proc$libresoc.v:51594$3418 + assign { } { } + assign { } { } + assign { } { } + assign $0\do_step$next[0:0]$3419 $5\do_step$next[0:0]$3424 + attribute \src "libresoc.v:51595.5-51595.29" + switch \initial + attribute \src "libresoc.v:51595.9-51595.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + switch { \$9 \$5 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\do_step$next[0:0]$3420 $2\do_step$next[0:0]$3421 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:201" + switch \dmi_we_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\do_step$next[0:0]$3421 $3\do_step$next[0:0]$3422 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" + switch { \$15 \$13 \$11 } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign { } { } + assign $3\do_step$next[0:0]$3422 $4\do_step$next[0:0]$3423 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:213" + switch \dmi_din [3] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\do_step$next[0:0]$3423 1'1 + case + assign $4\do_step$next[0:0]$3423 1'0 + end + case + assign $3\do_step$next[0:0]$3422 1'0 + end + case + assign $2\do_step$next[0:0]$3421 1'0 + end + case + assign $1\do_step$next[0:0]$3420 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\do_step$next[0:0]$3424 1'0 + case + assign $5\do_step$next[0:0]$3424 $1\do_step$next[0:0]$3420 + end + sync always + update \do_step$next $0\do_step$next[0:0]$3419 + end + attribute \src "libresoc.v:51624.3-51653.6" + process $proc$libresoc.v:51624$3425 + assign { } { } + assign { } { } + assign { } { } + assign $0\do_reset$next[0:0]$3426 $5\do_reset$next[0:0]$3431 + attribute \src "libresoc.v:51625.5-51625.29" + switch \initial + attribute \src "libresoc.v:51625.9-51625.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + switch { \$23 \$19 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\do_reset$next[0:0]$3427 $2\do_reset$next[0:0]$3428 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:201" + switch \dmi_we_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\do_reset$next[0:0]$3428 $3\do_reset$next[0:0]$3429 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" + switch { \$29 \$27 \$25 } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign { } { } + assign $3\do_reset$next[0:0]$3429 $4\do_reset$next[0:0]$3430 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:208" + switch \dmi_din [1] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\do_reset$next[0:0]$3430 1'1 + case + assign $4\do_reset$next[0:0]$3430 1'0 + end + case + assign $3\do_reset$next[0:0]$3429 1'0 + end + case + assign $2\do_reset$next[0:0]$3428 1'0 + end + case + assign $1\do_reset$next[0:0]$3427 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\do_reset$next[0:0]$3431 1'0 + case + assign $5\do_reset$next[0:0]$3431 $1\do_reset$next[0:0]$3427 + end + sync always + update \do_reset$next $0\do_reset$next[0:0]$3426 + end + attribute \src "libresoc.v:51654.3-51683.6" + process $proc$libresoc.v:51654$3432 + assign { } { } + assign { } { } + assign { } { } + assign $0\do_icreset$next[0:0]$3433 $5\do_icreset$next[0:0]$3438 + attribute \src "libresoc.v:51655.5-51655.29" + switch \initial + attribute \src "libresoc.v:51655.9-51655.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + switch { \$37 \$33 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\do_icreset$next[0:0]$3434 $2\do_icreset$next[0:0]$3435 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:201" + switch \dmi_we_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\do_icreset$next[0:0]$3435 $3\do_icreset$next[0:0]$3436 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" + switch { \$43 \$41 \$39 } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign { } { } + assign $3\do_icreset$next[0:0]$3436 $4\do_icreset$next[0:0]$3437 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:216" + switch \dmi_din [2] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\do_icreset$next[0:0]$3437 1'1 + case + assign $4\do_icreset$next[0:0]$3437 1'0 + end + case + assign $3\do_icreset$next[0:0]$3436 1'0 + end + case + assign $2\do_icreset$next[0:0]$3435 1'0 + end + case + assign $1\do_icreset$next[0:0]$3434 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\do_icreset$next[0:0]$3438 1'0 + case + assign $5\do_icreset$next[0:0]$3438 $1\do_icreset$next[0:0]$3434 + end + sync always + update \do_icreset$next $0\do_icreset$next[0:0]$3433 + end + attribute \src "libresoc.v:51684.3-51717.6" + process $proc$libresoc.v:51684$3439 + assign { } { } + assign { } { } + assign { } { } + assign $0\do_dmi_log_rd$next[0:0]$3440 $4\do_dmi_log_rd$next[0:0]$3444 + attribute \src "libresoc.v:51685.5-51685.29" + switch \initial + attribute \src "libresoc.v:51685.9-51685.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + switch { \$51 \$47 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\do_dmi_log_rd$next[0:0]$3441 $2\do_dmi_log_rd$next[0:0]$3442 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:201" + switch \dmi_we_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\do_dmi_log_rd$next[0:0]$3442 $3\do_dmi_log_rd$next[0:0]$3443 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:207" + switch { \$57 \$55 \$53 } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign $3\do_dmi_log_rd$next[0:0]$3443 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 3'-1- + assign $3\do_dmi_log_rd$next[0:0]$3443 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 3'1-- + assign { } { } + assign $3\do_dmi_log_rd$next[0:0]$3443 1'1 + case + assign $3\do_dmi_log_rd$next[0:0]$3443 1'0 + end + case + assign $2\do_dmi_log_rd$next[0:0]$3442 1'0 + end + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\do_dmi_log_rd$next[0:0]$3441 1'1 + case + assign $1\do_dmi_log_rd$next[0:0]$3441 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\do_dmi_log_rd$next[0:0]$3444 1'0 + case + assign $4\do_dmi_log_rd$next[0:0]$3444 $1\do_dmi_log_rd$next[0:0]$3441 + end + sync always + update \do_dmi_log_rd$next $0\do_dmi_log_rd$next[0:0]$3440 + end + connect \$9 $and$libresoc.v:51248$3300_Y + connect \$99 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\enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 \ALU_dec31_ALU_dec31_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 \ALU_dec31_ALU_dec31_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \ALU_dec31_ALU_dec31_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \ALU_dec31_ALU_dec31_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \ALU_dec31_ALU_dec31_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 \ALU_dec31_ALU_dec31_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \ALU_dec31_ALU_dec31_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \ALU_dec31_ALU_dec31_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + wire width 32 \ALU_dec31_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 13 output 8 \ALU_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 9 \ALU_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 10 \ALU_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 output 6 \ALU_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 12 \ALU_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 13 \ALU_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 16 \ALU_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 11 \ALU_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 3 \ALU_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 17 \ALU_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 6 output 22 \ALU_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \A_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \A_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \A_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \A_FRC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \A_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \A_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \A_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \A_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \A_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \A_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \B_AA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 14 \B_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \B_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \B_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \B_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DQE_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DQE_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 2 \DQE_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 12 \DQ_DQ + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 4 \DQ_PT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DQ_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DQ_RTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DQ_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \DQ_SX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \DQ_SX_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DQ_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \DQ_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \DQ_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 3 \DQ_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 14 \DS_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DS_FRSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DS_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DS_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DS_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DS_RSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DS_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DS_VRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DS_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 2 \DS_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DX_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 10 \DX_d0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 16 \DX_d0_d1_d2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DX_d1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \DX_d2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 3 \D_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 16 \D_D + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \D_FRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \D_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \D_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \D_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \D_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \D_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 16 \D_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \D_TO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 16 \D_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 3 \EVS_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \I_AA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 24 \I_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \I_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \MDS_IB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \MDS_IS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \MDS_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \MDS_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \MDS_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \MDS_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 4 \MDS_XBI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 4 \MDS_XBI_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 4 \MDS_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \MDS_mb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \MDS_me + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \MD_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \MD_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \MD_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 3 \MD_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \MD_mb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \MD_me + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \MD_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \M_MB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \M_ME + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \M_RA + attribute \src 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 10 \VX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 11 \VX_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 8 \XFL_FLM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \XFL_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \XFL_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \XFL_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \XFL_W + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 10 \XFL_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 10 \XFX_BHRBE + attribute \src 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \XL_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 10 \XL_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \XO_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \XO_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \XO_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \XO_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \XO_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 9 \XO_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \XS_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \XS_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \XS_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 9 \XS_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \XS_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \XX2_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 3 \XX2_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \XX2_BX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \XX2_BX_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 7 \XX2_DCMX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \XX2_EO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \XX2_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \XX2_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \XX2_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \XX2_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 4 \XX2_UIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 2 \XX2_UIM_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 7 \XX2_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 9 \XX2_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \XX2_dc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 7 \XX2_dc_dm_dx + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \XX2_dm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \XX2_dx + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \XX3_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \XX3_AX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \XX3_AX_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \XX3_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 3 \XX3_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \XX3_BX + attribute \src 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_TH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_TO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \X_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \X_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 4 \X_U + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_UIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_VRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \X_W + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 2 \X_WC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 10 \X_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 8 \X_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 3 \Z22_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \Z22_DCM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \Z22_DGM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \Z22_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \Z22_FRAp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \Z22_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \Z22_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \Z22_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \Z22_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 9 \Z22_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \Z23_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \Z23_FRAp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \Z23_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \Z23_FRBp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \Z23_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \Z23_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \Z23_R + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 2 \Z23_RMC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \Z23_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \Z23_TE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 8 \Z23_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \all_OPCD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \all_PO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" + wire input 1 \bigendian + attribute \src "libresoc.v:51732.7-51732.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + wire width 32 output 2 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + wire width 6 \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 32 input 37 \raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:504" + cell $mux $ternary$libresoc.v:52928$3457 + parameter \WIDTH 32 + connect \A \raw_opcode_in + connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } + connect \S \bigendian + connect \Y $ternary$libresoc.v:52928$3457_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:52929.13-52945.4" + cell \ALU_dec19 \ALU_dec19 + connect \ALU_dec19_cr_in \ALU_dec19_ALU_dec19_cr_in + connect \ALU_dec19_cr_out \ALU_dec19_ALU_dec19_cr_out + connect \ALU_dec19_cry_in \ALU_dec19_ALU_dec19_cry_in + connect \ALU_dec19_cry_out \ALU_dec19_ALU_dec19_cry_out + connect \ALU_dec19_function_unit \ALU_dec19_ALU_dec19_function_unit + connect \ALU_dec19_in1_sel \ALU_dec19_ALU_dec19_in1_sel + connect \ALU_dec19_in2_sel \ALU_dec19_ALU_dec19_in2_sel + connect \ALU_dec19_internal_op \ALU_dec19_ALU_dec19_internal_op + connect \ALU_dec19_inv_a \ALU_dec19_ALU_dec19_inv_a + connect \ALU_dec19_inv_out \ALU_dec19_ALU_dec19_inv_out + connect \ALU_dec19_is_32b \ALU_dec19_ALU_dec19_is_32b + connect \ALU_dec19_ldst_len \ALU_dec19_ALU_dec19_ldst_len + connect \ALU_dec19_rc_sel \ALU_dec19_ALU_dec19_rc_sel + connect \ALU_dec19_sgn \ALU_dec19_ALU_dec19_sgn + connect \opcode_in \ALU_dec19_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:52946.13-52962.4" + cell \ALU_dec31 \ALU_dec31 + connect \ALU_dec31_cr_in \ALU_dec31_ALU_dec31_cr_in + connect \ALU_dec31_cr_out \ALU_dec31_ALU_dec31_cr_out + connect \ALU_dec31_cry_in \ALU_dec31_ALU_dec31_cry_in + connect \ALU_dec31_cry_out \ALU_dec31_ALU_dec31_cry_out + connect \ALU_dec31_function_unit \ALU_dec31_ALU_dec31_function_unit + connect \ALU_dec31_in1_sel \ALU_dec31_ALU_dec31_in1_sel + connect \ALU_dec31_in2_sel \ALU_dec31_ALU_dec31_in2_sel + connect \ALU_dec31_internal_op \ALU_dec31_ALU_dec31_internal_op + connect \ALU_dec31_inv_a \ALU_dec31_ALU_dec31_inv_a + connect \ALU_dec31_inv_out \ALU_dec31_ALU_dec31_inv_out + connect \ALU_dec31_is_32b \ALU_dec31_ALU_dec31_is_32b + connect \ALU_dec31_ldst_len \ALU_dec31_ALU_dec31_ldst_len + connect \ALU_dec31_rc_sel \ALU_dec31_ALU_dec31_rc_sel + connect \ALU_dec31_sgn \ALU_dec31_ALU_dec31_sgn + connect \opcode_in \ALU_dec31_opcode_in + end + attribute \src "libresoc.v:51732.7-51732.20" + process $proc$libresoc.v:51732$3472 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:52963.3-52996.6" + process $proc$libresoc.v:52963$3458 + assign { } { } + assign { } { } + assign $0\ALU_rc_sel[1:0] $1\ALU_rc_sel[1:0] + attribute \src "libresoc.v:52964.5-52964.29" + switch \initial + attribute \src "libresoc.v:52964.9-52964.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\ALU_rc_sel[1:0] \ALU_dec19_ALU_dec19_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\ALU_rc_sel[1:0] \ALU_dec31_ALU_dec31_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\ALU_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\ALU_rc_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\ALU_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\ALU_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\ALU_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\ALU_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\ALU_rc_sel[1:0] 2'00 + case + assign $1\ALU_rc_sel[1:0] 2'00 + end + sync always + update \ALU_rc_sel $0\ALU_rc_sel[1:0] + end + attribute \src "libresoc.v:52997.3-53030.6" + process $proc$libresoc.v:52997$3459 + assign { } { } + assign { } { } + assign $0\ALU_cry_in[1:0] $1\ALU_cry_in[1:0] + attribute \src "libresoc.v:52998.5-52998.29" + switch \initial + attribute \src "libresoc.v:52998.9-52998.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\ALU_cry_in[1:0] \ALU_dec19_ALU_dec19_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\ALU_cry_in[1:0] \ALU_dec31_ALU_dec31_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\ALU_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\ALU_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\ALU_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\ALU_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\ALU_cry_in[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\ALU_cry_in[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\ALU_cry_in[1:0] 2'01 + case + assign $1\ALU_cry_in[1:0] 2'00 + end + sync always + update \ALU_cry_in $0\ALU_cry_in[1:0] + end + attribute \src "libresoc.v:53031.3-53064.6" + process $proc$libresoc.v:53031$3460 + assign { } { } + assign { } { } + assign $0\ALU_inv_a[0:0] $1\ALU_inv_a[0:0] + attribute \src "libresoc.v:53032.5-53032.29" + switch \initial + attribute \src "libresoc.v:53032.9-53032.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\ALU_inv_a[0:0] \ALU_dec19_ALU_dec19_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\ALU_inv_a[0:0] \ALU_dec31_ALU_dec31_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\ALU_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\ALU_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\ALU_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\ALU_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\ALU_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\ALU_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\ALU_inv_a[0:0] 1'1 + case + assign $1\ALU_inv_a[0:0] 1'0 + end + sync always + update \ALU_inv_a $0\ALU_inv_a[0:0] + end + attribute \src "libresoc.v:53065.3-53098.6" + process $proc$libresoc.v:53065$3461 + assign { } { } + assign { } { } + assign $0\ALU_inv_out[0:0] $1\ALU_inv_out[0:0] + attribute \src "libresoc.v:53066.5-53066.29" + switch \initial + attribute \src "libresoc.v:53066.9-53066.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\ALU_inv_out[0:0] \ALU_dec19_ALU_dec19_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\ALU_inv_out[0:0] \ALU_dec31_ALU_dec31_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\ALU_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\ALU_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\ALU_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\ALU_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\ALU_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\ALU_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\ALU_inv_out[0:0] 1'0 + case + assign $1\ALU_inv_out[0:0] 1'0 + end + sync always + update \ALU_inv_out $0\ALU_inv_out[0:0] + end + attribute \src "libresoc.v:53099.3-53132.6" + process $proc$libresoc.v:53099$3462 + assign { } { } + assign { } { } + assign $0\ALU_cry_out[0:0] $1\ALU_cry_out[0:0] + attribute \src "libresoc.v:53100.5-53100.29" + switch \initial + attribute \src "libresoc.v:53100.9-53100.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\ALU_cry_out[0:0] \ALU_dec19_ALU_dec19_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\ALU_cry_out[0:0] \ALU_dec31_ALU_dec31_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\ALU_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\ALU_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\ALU_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\ALU_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\ALU_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\ALU_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\ALU_cry_out[0:0] 1'1 + case + assign $1\ALU_cry_out[0:0] 1'0 + end + sync always + update \ALU_cry_out $0\ALU_cry_out[0:0] + end + attribute \src "libresoc.v:53133.3-53166.6" + process $proc$libresoc.v:53133$3463 + assign { } { } + assign { } { } + assign $0\ALU_is_32b[0:0] $1\ALU_is_32b[0:0] + attribute \src "libresoc.v:53134.5-53134.29" + switch \initial + attribute \src "libresoc.v:53134.9-53134.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\ALU_is_32b[0:0] \ALU_dec19_ALU_dec19_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\ALU_is_32b[0:0] \ALU_dec31_ALU_dec31_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\ALU_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\ALU_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\ALU_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\ALU_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\ALU_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\ALU_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\ALU_is_32b[0:0] 1'0 + case + assign $1\ALU_is_32b[0:0] 1'0 + end + sync always + update \ALU_is_32b $0\ALU_is_32b[0:0] + end + attribute \src "libresoc.v:53167.3-53200.6" + process $proc$libresoc.v:53167$3464 + assign { } { } + assign { } { } + assign $0\ALU_sgn[0:0] $1\ALU_sgn[0:0] + attribute \src "libresoc.v:53168.5-53168.29" + switch \initial + attribute \src "libresoc.v:53168.9-53168.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\ALU_sgn[0:0] \ALU_dec19_ALU_dec19_sgn + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\ALU_sgn[0:0] \ALU_dec31_ALU_dec31_sgn + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\ALU_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\ALU_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\ALU_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\ALU_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\ALU_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\ALU_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\ALU_sgn[0:0] 1'0 + case + assign $1\ALU_sgn[0:0] 1'0 + end + sync always + update \ALU_sgn $0\ALU_sgn[0:0] + end + attribute \src "libresoc.v:53201.3-53234.6" + process $proc$libresoc.v:53201$3465 + assign { } { } + assign { } { } + assign $0\ALU_function_unit[12:0] $1\ALU_function_unit[12:0] + attribute \src "libresoc.v:53202.5-53202.29" + switch \initial + attribute \src "libresoc.v:53202.9-53202.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\ALU_function_unit[12:0] \ALU_dec19_ALU_dec19_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\ALU_function_unit[12:0] \ALU_dec31_ALU_dec31_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\ALU_function_unit[12:0] 13'0000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\ALU_function_unit[12:0] 13'0000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\ALU_function_unit[12:0] 13'0000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\ALU_function_unit[12:0] 13'0000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\ALU_function_unit[12:0] 13'0000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\ALU_function_unit[12:0] 13'0000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\ALU_function_unit[12:0] 13'0000000000010 + case + assign $1\ALU_function_unit[12:0] 13'0000000000000 + end + sync always + update \ALU_function_unit $0\ALU_function_unit[12:0] + end + attribute \src "libresoc.v:53235.3-53268.6" + process $proc$libresoc.v:53235$3466 + assign { } { } + assign { } { } + assign $0\ALU_internal_op[6:0] $1\ALU_internal_op[6:0] + attribute \src "libresoc.v:53236.5-53236.29" + switch \initial + attribute \src "libresoc.v:53236.9-53236.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\ALU_internal_op[6:0] \ALU_dec19_ALU_dec19_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\ALU_internal_op[6:0] \ALU_dec31_ALU_dec31_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\ALU_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\ALU_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\ALU_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\ALU_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\ALU_internal_op[6:0] 7'0001010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\ALU_internal_op[6:0] 7'0001010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\ALU_internal_op[6:0] 7'0000010 + case + assign $1\ALU_internal_op[6:0] 7'0000000 + end + sync always + update \ALU_internal_op $0\ALU_internal_op[6:0] + end + attribute \src "libresoc.v:53269.3-53302.6" + process $proc$libresoc.v:53269$3467 + assign { } { } + assign { } { } + assign $0\ALU_in1_sel[2:0] $1\ALU_in1_sel[2:0] + attribute \src "libresoc.v:53270.5-53270.29" + switch \initial + attribute \src "libresoc.v:53270.9-53270.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\ALU_in1_sel[2:0] \ALU_dec19_ALU_dec19_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\ALU_in1_sel[2:0] \ALU_dec31_ALU_dec31_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\ALU_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\ALU_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\ALU_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\ALU_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\ALU_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\ALU_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\ALU_in1_sel[2:0] 3'001 + case + assign $1\ALU_in1_sel[2:0] 3'000 + end + sync always + update \ALU_in1_sel $0\ALU_in1_sel[2:0] + end + attribute \src "libresoc.v:53303.3-53336.6" + process $proc$libresoc.v:53303$3468 + assign { } { } + assign { } { } + assign $0\ALU_in2_sel[3:0] $1\ALU_in2_sel[3:0] + attribute \src "libresoc.v:53304.5-53304.29" + switch \initial + attribute \src "libresoc.v:53304.9-53304.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\ALU_in2_sel[3:0] \ALU_dec19_ALU_dec19_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\ALU_in2_sel[3:0] \ALU_dec31_ALU_dec31_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\ALU_in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\ALU_in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\ALU_in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\ALU_in2_sel[3:0] 4'0101 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\ALU_in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\ALU_in2_sel[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\ALU_in2_sel[3:0] 4'0011 + case + assign $1\ALU_in2_sel[3:0] 4'0000 + end + sync always + update \ALU_in2_sel $0\ALU_in2_sel[3:0] + end + attribute \src "libresoc.v:53337.3-53370.6" + process $proc$libresoc.v:53337$3469 + assign { } { } + assign { } { } + assign $0\ALU_cr_in[2:0] $1\ALU_cr_in[2:0] + attribute \src "libresoc.v:53338.5-53338.29" + switch \initial + attribute \src "libresoc.v:53338.9-53338.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\ALU_cr_in[2:0] \ALU_dec19_ALU_dec19_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\ALU_cr_in[2:0] \ALU_dec31_ALU_dec31_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\ALU_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\ALU_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\ALU_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\ALU_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\ALU_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\ALU_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\ALU_cr_in[2:0] 3'000 + case + assign $1\ALU_cr_in[2:0] 3'000 + end + sync always + update \ALU_cr_in $0\ALU_cr_in[2:0] + end + attribute \src "libresoc.v:53371.3-53404.6" + process $proc$libresoc.v:53371$3470 + assign { } { } + assign { } { } + assign $0\ALU_cr_out[2:0] $1\ALU_cr_out[2:0] + attribute \src "libresoc.v:53372.5-53372.29" + switch \initial + attribute \src "libresoc.v:53372.9-53372.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\ALU_cr_out[2:0] \ALU_dec19_ALU_dec19_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\ALU_cr_out[2:0] \ALU_dec31_ALU_dec31_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\ALU_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\ALU_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\ALU_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\ALU_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\ALU_cr_out[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\ALU_cr_out[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\ALU_cr_out[2:0] 3'000 + case + assign $1\ALU_cr_out[2:0] 3'000 + end + sync always + update \ALU_cr_out $0\ALU_cr_out[2:0] + end + attribute \src "libresoc.v:53405.3-53438.6" + process $proc$libresoc.v:53405$3471 + assign { } { } + assign { } { } + assign $0\ALU_ldst_len[3:0] $1\ALU_ldst_len[3:0] + attribute \src "libresoc.v:53406.5-53406.29" + switch \initial + attribute \src "libresoc.v:53406.9-53406.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\ALU_ldst_len[3:0] \ALU_dec19_ALU_dec19_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\ALU_ldst_len[3:0] \ALU_dec31_ALU_dec31_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\ALU_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\ALU_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\ALU_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\ALU_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\ALU_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\ALU_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\ALU_ldst_len[3:0] 4'0000 + case + assign $1\ALU_ldst_len[3:0] 4'0000 + end + sync always + update \ALU_ldst_len $0\ALU_ldst_len[3:0] + end + connect \$1 $ternary$libresoc.v:52928$3457_Y + connect \VC_XO \opcode_in [9:0] + connect \VC_VRT \opcode_in [25:21] + connect \VC_VRB \opcode_in [15:11] + connect \VC_VRA \opcode_in [20:16] + connect \VC_Rc \opcode_in [10] + connect \XS_XO \opcode_in [10:2] + connect \XS_sh { \opcode_in [1] \opcode_in [15:11] } + connect \XS_RS \opcode_in [25:21] + connect \XS_Rc \opcode_in [0] + connect \XS_RA \opcode_in [20:16] + connect \VA_XO \opcode_in [5:0] + connect \VA_VRT \opcode_in [25:21] + connect \VA_VRC \opcode_in [10:6] + connect \VA_VRB \opcode_in [15:11] + connect \VA_VRA \opcode_in [20:16] + connect \VA_SHB \opcode_in [9:6] + connect \VA_RT \opcode_in [25:21] + connect \VA_RC \opcode_in [10:6] + connect \VA_RB \opcode_in [15:11] + connect \VA_RA \opcode_in [20:16] + connect \TX_XO \opcode_in [6:1] + connect \TX_XBI \opcode_in [10:7] + connect \TX_UI \opcode_in [15:11] + connect \TX_RA \opcode_in [20:16] + connect \DQE_XO \opcode_in [1:0] + connect \DQE_RT \opcode_in [25:21] + connect \DQE_RA \opcode_in [20:16] + connect \XO_XO \opcode_in [9:1] + connect \XO_RT \opcode_in [25:21] + connect \XO_Rc \opcode_in [0] + connect \XO_RB \opcode_in [15:11] + connect \XO_RA \opcode_in [20:16] + connect \XO_OE \opcode_in [10] + connect \all_PO \opcode_in [31:26] + connect \all_OPCD \opcode_in [31:26] + connect \SVL_XO \opcode_in [5:1] + connect \SVL_vs \opcode_in [7] + connect \SVL_SVi \opcode_in [15:10] + connect \SVL_RT \opcode_in [25:21] + connect \SVL_Rc \opcode_in [0] + connect \SVL_RA \opcode_in [20:16] + connect \SVL_ms \opcode_in [6] + connect \MD_XO \opcode_in [4:2] + connect \MD_sh { \opcode_in [1] \opcode_in [15:11] } + connect \MD_RS \opcode_in [25:21] + connect \MD_Rc \opcode_in [0] + connect \MD_RA \opcode_in [20:16] + connect \MD_me \opcode_in [10:5] + connect \MD_mb \opcode_in [10:5] + connect \M_SH \opcode_in [15:11] + connect \M_RS \opcode_in [25:21] + connect \M_Rc \opcode_in [0] + connect \M_RB \opcode_in [15:11] + connect \M_RA \opcode_in [20:16] + connect \M_ME \opcode_in [5:1] + connect \M_MB \opcode_in [10:6] + connect \SC_XO_1 \opcode_in [1:0] + connect \SC_XO \opcode_in [1] + connect \SC_LEV \opcode_in [11:5] + connect \MDS_XO \opcode_in [4:1] + connect \MDS_XBI_1 \opcode_in [10:7] + connect \MDS_XBI \opcode_in [10:7] + connect \MDS_RS \opcode_in [25:21] + connect \MDS_Rc \opcode_in [0] + connect \MDS_RB \opcode_in [15:11] + connect \MDS_RA \opcode_in [20:16] + connect \MDS_me \opcode_in [10:5] + connect \MDS_mb \opcode_in [10:5] + connect \MDS_IS \opcode_in [25:21] + connect \MDS_IB \opcode_in [15:11] + connect \Z23_XO \opcode_in [8:1] + connect \Z23_TE \opcode_in [20:16] + connect \Z23_RMC \opcode_in [10:9] + connect \Z23_Rc \opcode_in [0] + connect \Z23_R \opcode_in [16] + connect \Z23_FRTp \opcode_in [25:21] + connect \Z23_FRT \opcode_in [25:21] + connect \Z23_FRBp \opcode_in [15:11] + connect \Z23_FRB \opcode_in [15:11] + connect \Z23_FRAp \opcode_in [20:16] + connect \Z23_FRA \opcode_in [20:16] + connect \XFL_XO \opcode_in [10:1] + connect \XFL_W \opcode_in [16] + connect \XFL_Rc \opcode_in [0] + connect \XFL_L \opcode_in [25] + connect \XFL_FRB \opcode_in [15:11] + connect \XFL_FLM \opcode_in [24:17] + connect \VX_XO_1 \opcode_in [10:0] + connect \VX_XO { \opcode_in [10] \opcode_in [8:0] } + connect \VX_VRT \opcode_in [25:21] + connect \VX_VRB \opcode_in [15:11] + connect \VX_VRA \opcode_in [20:16] + connect \VX_UIM_3 \opcode_in [17:16] + connect \VX_UIM_2 \opcode_in [18:16] + connect \VX_UIM_1 \opcode_in [19:16] + connect \VX_UIM \opcode_in [20:16] + connect \VX_SIM \opcode_in [20:16] + connect \VX_RT \opcode_in [25:21] + connect \VX_RA \opcode_in [20:16] + connect \VX_PS \opcode_in [9] + connect \VX_EO \opcode_in [20:16] + connect \DS_XO \opcode_in [1:0] + connect \DS_VRT \opcode_in [25:21] + connect \DS_VRS \opcode_in [25:21] + connect \DS_RT \opcode_in [25:21] + connect \DS_RSp \opcode_in [25:21] + connect \DS_RS \opcode_in [25:21] + connect \DS_RA \opcode_in [20:16] + connect \DS_FRTp \opcode_in [25:21] + connect \DS_FRSp \opcode_in [25:21] + connect \DS_DS \opcode_in [15:2] + connect \DQ_XO \opcode_in [2:0] + connect \DQ_TX_T { \opcode_in [3] \opcode_in [25:21] } + connect \DQ_T \opcode_in [25:21] + connect \DQ_TX \opcode_in [3] + connect \DQ_SX_S { \opcode_in [3] \opcode_in [25:21] } + connect \DQ_S \opcode_in [25:21] + connect \DQ_SX \opcode_in [3] + connect \DQ_RTp \opcode_in [25:21] + connect \DQ_RA \opcode_in [20:16] + connect \DQ_PT \opcode_in [3:0] + connect \DQ_DQ \opcode_in [15:4] + connect \DX_XO \opcode_in [5:1] + connect \DX_RT \opcode_in [25:21] + connect \DX_d0_d1_d2 { \opcode_in [15:6] \opcode_in [20:16] \opcode_in [0] } + connect \DX_d2 \opcode_in [0] + connect \DX_d1 \opcode_in [20:16] + connect \DX_d0 \opcode_in [15:6] + connect \XFX_XO \opcode_in [10:1] + connect \XFX_SPR \opcode_in [20:11] + connect \XFX_RT \opcode_in [25:21] + connect \XFX_RS \opcode_in [25:21] + connect \XFX_FXM \opcode_in [19:12] + connect \XFX_DUIS \opcode_in [20:11] + connect \XFX_DUI \opcode_in [25:21] + connect \XFX_BHRBE \opcode_in [20:11] + connect \EVS_BFA \opcode_in [2:0] + connect \Z22_XO \opcode_in [9:1] + connect \Z22_SH \opcode_in [15:10] + connect \Z22_Rc \opcode_in [0] + connect \Z22_FRTp \opcode_in [25:21] + connect \Z22_FRT \opcode_in [25:21] + connect \Z22_FRAp \opcode_in [20:16] + connect \Z22_FRA \opcode_in [20:16] + connect \Z22_DGM \opcode_in [15:10] + connect \Z22_DCM \opcode_in [15:10] + connect \Z22_BF \opcode_in [25:23] + connect \XX2_XO_1 \opcode_in [10:2] + connect \XX2_XO { \opcode_in [10:7] \opcode_in [5:3] } + connect \XX2_UIM_1 \opcode_in [17:16] + connect \XX2_UIM \opcode_in [19:16] + connect \XX2_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX2_T \opcode_in [25:21] + connect \XX2_TX \opcode_in [0] + connect \XX2_RT \opcode_in [25:21] + connect \XX2_EO \opcode_in [20:16] + connect \XX2_DCMX \opcode_in [22:16] + connect \XX2_dc_dm_dx { \opcode_in [6] \opcode_in [2] \opcode_in [20:16] } + connect \XX2_dx \opcode_in [20:16] + connect \XX2_dm \opcode_in [2] + connect \XX2_dc \opcode_in [6] + connect \XX2_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX2_B \opcode_in [15:11] + connect \XX2_BX \opcode_in [1] + connect \XX2_BF \opcode_in [25:23] + connect \D_UI \opcode_in [15:0] + connect \D_TO \opcode_in [25:21] + connect \D_SI \opcode_in [15:0] + connect \D_RT \opcode_in [25:21] + connect \D_RS \opcode_in [25:21] + connect \D_RA \opcode_in [20:16] + connect \D_L \opcode_in [21] + connect \D_FRT \opcode_in [25:21] + connect \D_FRS \opcode_in [25:21] + connect \D_D \opcode_in [15:0] + connect \D_BF \opcode_in [25:23] + connect \A_XO \opcode_in [5:1] + connect \A_RT \opcode_in [25:21] + connect \A_Rc \opcode_in [0] + connect \A_RB \opcode_in [15:11] + connect \A_RA \opcode_in [20:16] + connect \A_FRT \opcode_in [25:21] + connect \A_FRC \opcode_in [10:6] + connect \A_FRB \opcode_in [15:11] + connect \A_FRA \opcode_in [20:16] + connect \A_BC \opcode_in [10:6] + connect \XL_XO \opcode_in [10:1] + connect \XL_S \opcode_in [11] + connect \XL_OC \opcode_in [25:11] + connect \XL_LK \opcode_in [0] + connect \XL_BT \opcode_in [25:21] + connect \XL_BO_1 \opcode_in [25:21] + connect \XL_BO \opcode_in [25:21] + connect \XL_BI \opcode_in [20:16] + connect \XL_BH \opcode_in [12:11] + connect \XL_BFA \opcode_in [20:18] + connect \XL_BF \opcode_in [25:23] + connect \XL_BB \opcode_in [15:11] + connect \XL_BA \opcode_in [20:16] + connect \XX4_XO \opcode_in [5:4] + connect \XX4_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX4_T \opcode_in [25:21] + connect \XX4_TX \opcode_in [0] + connect \XX4_CX_C { \opcode_in [3] \opcode_in [10:6] } + connect \XX4_C \opcode_in [10:6] + connect \XX4_CX \opcode_in [3] + connect \XX4_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX4_B \opcode_in [15:11] + connect \XX4_BX \opcode_in [1] + connect \XX4_AX_A { \opcode_in [2] \opcode_in [20:16] } + connect \XX4_A \opcode_in [20:16] + connect \XX4_AX \opcode_in [2] + connect \XX3_XO_2 \opcode_in [9:1] + connect \XX3_XO_1 \opcode_in [10:3] + connect \XX3_XO \opcode_in [10:7] + connect \XX3_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX3_T \opcode_in [25:21] + connect \XX3_TX \opcode_in [0] + connect \XX3_SHW \opcode_in [9:8] + connect \XX3_Rc \opcode_in [10] + connect \XX3_DM \opcode_in [9:8] + connect \XX3_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX3_B \opcode_in [15:11] + connect \XX3_BX \opcode_in [1] + connect \XX3_BF \opcode_in [25:23] + connect \XX3_AX_A { \opcode_in [2] \opcode_in [20:16] } + connect \XX3_A \opcode_in [20:16] + connect \XX3_AX \opcode_in [2] + connect \I_LK \opcode_in [0] + connect \I_LI \opcode_in [25:2] + connect \I_AA \opcode_in [1] + connect \B_LK \opcode_in [0] + connect \B_BO \opcode_in [25:21] + connect \B_BI \opcode_in [20:16] + connect \B_BD \opcode_in [15:2] + connect \B_AA \opcode_in [1] + connect \X_XO_1 \opcode_in [8:1] + connect \X_XO \opcode_in [10:1] + connect \X_WC \opcode_in [22:21] + connect \X_W \opcode_in [16] + connect \X_VRT \opcode_in [25:21] + connect \X_VRS \opcode_in [25:21] + connect \X_UIM \opcode_in [20:16] + connect \X_U \opcode_in [15:12] + connect \X_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \X_TX \opcode_in [0] + connect \X_TO \opcode_in [25:21] + connect \X_TH \opcode_in [25:21] + connect \X_TBR \opcode_in [20:11] + connect \X_T \opcode_in [25:21] + connect \X_SX_S { \opcode_in [0] \opcode_in [25:21] } + connect \X_SX \opcode_in [0] + connect \X_SR \opcode_in [19:16] + connect \X_SP \opcode_in [20:19] + connect \X_SI \opcode_in [15:11] + connect \X_SH \opcode_in [15:11] + connect \X_S \opcode_in [25:21] + connect \X_RTp \opcode_in [25:21] + connect \X_RT \opcode_in [25:21] + connect \X_RSp \opcode_in [25:21] + connect \X_RS \opcode_in [25:21] + connect \X_RO \opcode_in [0] + connect \X_RM \opcode_in [12:11] + connect \X_RIC \opcode_in [19:18] + connect \X_Rc \opcode_in [0] + connect \X_RB \opcode_in [15:11] + connect \X_RA \opcode_in [20:16] + connect \X_R_1 \opcode_in [16] + connect \X_R \opcode_in [21] + connect \X_PRS \opcode_in [17] + connect \X_NB \opcode_in [15:11] + connect \X_MO \opcode_in [25:21] + connect \X_L3 \opcode_in [17:16] + connect \X_L1 \opcode_in [16] + connect \X_L \opcode_in [21] + connect \X_L2 \opcode_in [22:21] + connect \X_IMM8 \opcode_in [18:11] + connect \X_IH \opcode_in [23:21] + connect \X_FRTp \opcode_in [25:21] + connect \X_FRT \opcode_in [25:21] + connect \X_FRSp \opcode_in [25:21] + connect \X_FRS \opcode_in [25:21] + connect \X_FRBp \opcode_in [15:11] + connect \X_FRB \opcode_in [15:11] + connect \X_FRAp \opcode_in [20:16] + connect \X_FRA \opcode_in [20:16] + connect \X_FC \opcode_in [15:11] + connect \X_EX \opcode_in [0] + connect \X_EO_1 \opcode_in [20:16] + connect \X_EO \opcode_in [20:19] + connect \X_E_1 \opcode_in [19:16] + connect \X_E \opcode_in [15] + connect \X_DRM \opcode_in [13:11] + connect \X_DCMX \opcode_in [22:16] + connect \X_CT \opcode_in [24:21] + connect \X_BO \opcode_in [25:21] + connect \X_BFA \opcode_in [20:18] + connect \X_BF \opcode_in [25:23] + connect \X_A \opcode_in [25] + connect \ALU_SPR \opcode_in [20:11] + connect \ALU_MB \opcode_in [10:6] + connect \ALU_ME \opcode_in [5:1] + connect \ALU_SH \opcode_in [15:11] + connect \ALU_BC \opcode_in [10:6] + connect \ALU_TO \opcode_in [25:21] + connect \ALU_DS \opcode_in [15:2] + connect \ALU_D \opcode_in [15:0] + connect \ALU_BH \opcode_in [12:11] + connect \ALU_BI \opcode_in [20:16] + connect \ALU_BO \opcode_in [25:21] + connect \ALU_FXM \opcode_in [19:12] + connect \ALU_BT \opcode_in [25:21] + connect \ALU_BA \opcode_in [20:16] + connect \ALU_BB \opcode_in [15:11] + connect \ALU_CR \opcode_in [10:1] + connect \ALU_BF \opcode_in [25:23] + connect \ALU_BD \opcode_in [15:2] + connect \ALU_OE \opcode_in [10] + connect \ALU_Rc \opcode_in [0] + connect \ALU_AA \opcode_in [1] + connect \ALU_LK \opcode_in [0] + connect \ALU_LI \opcode_in [25:2] + connect \ALU_ME32 \opcode_in [5:1] + connect \ALU_MB32 \opcode_in [10:6] + connect \ALU_sh { \opcode_in [1] \opcode_in [15:11] } + connect \ALU_SH32 \opcode_in [15:11] + connect \ALU_L \opcode_in [21] + connect \ALU_UI \opcode_in [15:0] + connect \ALU_SI \opcode_in [15:0] + connect \ALU_RB \opcode_in [15:11] + connect \ALU_RA \opcode_in [20:16] + connect \ALU_RT \opcode_in [25:21] + connect \ALU_RS \opcode_in [25:21] + connect \opcode_in \$1 + connect \ALU_dec31_opcode_in \opcode_in + connect \ALU_dec19_opcode_in \opcode_in + connect \opcode_switch \opcode_in [31:26] +end +attribute \src "libresoc.v:53780.1-55240.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_CR.dec" +attribute \generator "nMigen" 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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:504" + wire width 32 \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \A_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \A_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \A_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \A_FRC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \A_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \A_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \A_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \A_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \A_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \A_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \B_AA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 14 \B_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \B_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \B_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \B_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire \CR_AA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 output 12 \CR_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 output 11 \CR_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 output 16 \CR_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 14 \CR_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 3 \CR_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 2 \CR_BH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 output 15 \CR_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \CR_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 output 13 \CR_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 10 \CR_CR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 16 \CR_D + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 14 \CR_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 8 output 14 \CR_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire \CR_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 24 \CR_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire \CR_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \CR_MB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \CR_MB32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \CR_ME + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \CR_ME32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire output 10 \CR_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \CR_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \CR_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \CR_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \CR_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire output 9 \CR_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \CR_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \CR_SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 16 \CR_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 10 output 7 \CR_SPR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \CR_TO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 16 \CR_UI + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 4 \CR_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 5 \CR_cr_out + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \CR_dec19_CR_dec19_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \CR_dec19_CR_dec19_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 13 \CR_dec19_CR_dec19_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 \CR_dec19_CR_dec19_internal_op + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \CR_dec19_CR_dec19_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + wire width 32 \CR_dec19_opcode_in + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \CR_dec31_CR_dec31_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \CR_dec31_CR_dec31_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 13 \CR_dec31_CR_dec31_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 \CR_dec31_CR_dec31_internal_op + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \CR_dec31_CR_dec31_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + wire width 32 \CR_dec31_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 13 output 8 \CR_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 output 6 \CR_internal_op + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 3 \CR_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 6 \CR_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DQE_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DQE_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 2 \DQE_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 12 \DQ_DQ + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 4 \DQ_PT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DQ_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DQ_RTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DQ_S + attribute \src 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_EO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \X_EX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 4 \X_E_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_FC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_FRAp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_FRBp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_FRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_FRSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 3 \X_IH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 8 \X_IMM8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \X_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \X_L1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 2 \X_L2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 2 \X_L3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_MO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_NB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \X_PRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \X_R + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 2 \X_RIC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 2 \X_RM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \X_RO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_RSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_RTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \X_R_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \X_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 2 \X_SP + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 4 \X_SR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \X_SX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \X_SX_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 10 \X_TBR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_TH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_TO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \X_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \X_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 4 \X_U + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_UIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_VRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \X_W + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 2 \X_WC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 10 \X_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 8 \X_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 3 \Z22_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \Z22_DCM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \Z22_DGM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \Z22_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \Z22_FRAp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \Z22_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \Z22_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \Z22_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \Z22_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 9 \Z22_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \Z23_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \Z23_FRAp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \Z23_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \Z23_FRBp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \Z23_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \Z23_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \Z23_R + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 2 \Z23_RMC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \Z23_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \Z23_TE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 8 \Z23_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \all_OPCD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \all_PO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" + wire input 1 \bigendian + attribute \src "libresoc.v:53781.7-53781.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + wire width 32 output 2 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + wire width 6 \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 32 input 20 \raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:504" + cell $mux $ternary$libresoc.v:54821$3473 + parameter \WIDTH 32 + connect \A \raw_opcode_in + connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } + connect \S \bigendian + connect \Y $ternary$libresoc.v:54821$3473_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:54822.12-54829.4" + cell \CR_dec19 \CR_dec19 + connect \CR_dec19_cr_in \CR_dec19_CR_dec19_cr_in + connect \CR_dec19_cr_out \CR_dec19_CR_dec19_cr_out + connect \CR_dec19_function_unit \CR_dec19_CR_dec19_function_unit + connect \CR_dec19_internal_op \CR_dec19_CR_dec19_internal_op + connect \CR_dec19_rc_sel \CR_dec19_CR_dec19_rc_sel + connect \opcode_in \CR_dec19_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:54830.12-54837.4" + cell \CR_dec31 \CR_dec31 + connect \CR_dec31_cr_in \CR_dec31_CR_dec31_cr_in + connect \CR_dec31_cr_out \CR_dec31_CR_dec31_cr_out + connect \CR_dec31_function_unit \CR_dec31_CR_dec31_function_unit + connect \CR_dec31_internal_op \CR_dec31_CR_dec31_internal_op + connect \CR_dec31_rc_sel \CR_dec31_CR_dec31_rc_sel + connect \opcode_in \CR_dec31_opcode_in + end + attribute \src "libresoc.v:53781.7-53781.20" + process $proc$libresoc.v:53781$3479 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:54838.3-54850.6" + process $proc$libresoc.v:54838$3474 + assign { } { } + assign { } { } + assign $0\CR_function_unit[12:0] $1\CR_function_unit[12:0] + attribute \src "libresoc.v:54839.5-54839.29" + switch \initial + attribute \src "libresoc.v:54839.9-54839.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\CR_function_unit[12:0] \CR_dec19_CR_dec19_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\CR_function_unit[12:0] \CR_dec31_CR_dec31_function_unit + case + assign $1\CR_function_unit[12:0] 13'0000000000000 + end + sync always + update \CR_function_unit $0\CR_function_unit[12:0] + end + attribute \src "libresoc.v:54851.3-54863.6" + process $proc$libresoc.v:54851$3475 + assign { } { } + assign { } { } + assign $0\CR_internal_op[6:0] $1\CR_internal_op[6:0] + attribute \src "libresoc.v:54852.5-54852.29" + switch \initial + attribute \src "libresoc.v:54852.9-54852.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\CR_internal_op[6:0] \CR_dec19_CR_dec19_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\CR_internal_op[6:0] \CR_dec31_CR_dec31_internal_op + case + assign $1\CR_internal_op[6:0] 7'0000000 + end + sync always + update \CR_internal_op $0\CR_internal_op[6:0] + end + attribute \src "libresoc.v:54864.3-54876.6" + process $proc$libresoc.v:54864$3476 + assign { } { } + assign { } { } + assign $0\CR_cr_in[2:0] $1\CR_cr_in[2:0] + attribute \src "libresoc.v:54865.5-54865.29" + switch \initial + attribute \src "libresoc.v:54865.9-54865.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\CR_cr_in[2:0] \CR_dec19_CR_dec19_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\CR_cr_in[2:0] \CR_dec31_CR_dec31_cr_in + case + assign $1\CR_cr_in[2:0] 3'000 + end + sync always + update \CR_cr_in $0\CR_cr_in[2:0] + end + attribute \src "libresoc.v:54877.3-54889.6" + process $proc$libresoc.v:54877$3477 + assign { } { } + assign { } { } + assign $0\CR_cr_out[2:0] $1\CR_cr_out[2:0] + attribute \src "libresoc.v:54878.5-54878.29" + switch \initial + attribute \src "libresoc.v:54878.9-54878.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\CR_cr_out[2:0] \CR_dec19_CR_dec19_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\CR_cr_out[2:0] \CR_dec31_CR_dec31_cr_out + case + assign $1\CR_cr_out[2:0] 3'000 + end + sync always + update \CR_cr_out $0\CR_cr_out[2:0] + end + attribute \src "libresoc.v:54890.3-54902.6" + process $proc$libresoc.v:54890$3478 + assign { } { } + assign { } { } + assign $0\CR_rc_sel[1:0] $1\CR_rc_sel[1:0] + attribute \src "libresoc.v:54891.5-54891.29" + switch \initial + attribute \src "libresoc.v:54891.9-54891.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\CR_rc_sel[1:0] \CR_dec19_CR_dec19_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\CR_rc_sel[1:0] \CR_dec31_CR_dec31_rc_sel + case + assign $1\CR_rc_sel[1:0] 2'00 + end + sync always + update \CR_rc_sel $0\CR_rc_sel[1:0] + end + connect \$1 $ternary$libresoc.v:54821$3473_Y + connect \VC_XO \opcode_in [9:0] + connect \VC_VRT \opcode_in [25:21] + connect \VC_VRB \opcode_in [15:11] + connect \VC_VRA \opcode_in [20:16] + connect \VC_Rc \opcode_in [10] + connect \XS_XO \opcode_in [10:2] + connect \XS_sh { \opcode_in [1] \opcode_in [15:11] } + connect \XS_RS \opcode_in [25:21] + connect \XS_Rc \opcode_in [0] + connect \XS_RA \opcode_in [20:16] + connect \VA_XO \opcode_in [5:0] + connect \VA_VRT \opcode_in [25:21] + connect \VA_VRC \opcode_in [10:6] + connect \VA_VRB \opcode_in [15:11] + connect \VA_VRA \opcode_in [20:16] + connect \VA_SHB \opcode_in [9:6] + connect \VA_RT \opcode_in [25:21] + connect \VA_RC \opcode_in [10:6] + connect \VA_RB \opcode_in [15:11] + connect \VA_RA \opcode_in [20:16] + connect \TX_XO \opcode_in [6:1] + connect \TX_XBI \opcode_in [10:7] + connect \TX_UI \opcode_in [15:11] + connect \TX_RA \opcode_in [20:16] + connect \DQE_XO \opcode_in [1:0] + connect \DQE_RT \opcode_in [25:21] + connect \DQE_RA \opcode_in [20:16] + connect \XO_XO \opcode_in [9:1] + connect \XO_RT \opcode_in [25:21] + connect \XO_Rc \opcode_in [0] + connect \XO_RB \opcode_in [15:11] + connect \XO_RA \opcode_in [20:16] + connect \XO_OE \opcode_in [10] + connect \all_PO \opcode_in [31:26] + connect \all_OPCD \opcode_in [31:26] + connect \SVL_XO \opcode_in [5:1] + connect \SVL_vs \opcode_in [7] + connect \SVL_SVi \opcode_in [15:10] + connect \SVL_RT \opcode_in [25:21] + connect \SVL_Rc \opcode_in [0] + connect \SVL_RA \opcode_in [20:16] + connect \SVL_ms \opcode_in [6] + connect \MD_XO \opcode_in [4:2] + connect \MD_sh { \opcode_in [1] \opcode_in [15:11] } + connect \MD_RS \opcode_in [25:21] + connect \MD_Rc \opcode_in [0] + connect \MD_RA \opcode_in [20:16] + connect \MD_me \opcode_in [10:5] + connect \MD_mb \opcode_in [10:5] + connect \M_SH \opcode_in [15:11] + connect \M_RS \opcode_in [25:21] + connect \M_Rc \opcode_in [0] + connect \M_RB \opcode_in [15:11] + connect \M_RA \opcode_in [20:16] + connect \M_ME \opcode_in [5:1] + connect \M_MB \opcode_in [10:6] + connect \SC_XO_1 \opcode_in [1:0] + connect \SC_XO \opcode_in [1] + connect \SC_LEV \opcode_in [11:5] + connect \MDS_XO \opcode_in [4:1] + connect \MDS_XBI_1 \opcode_in [10:7] + connect \MDS_XBI \opcode_in [10:7] + connect \MDS_RS \opcode_in [25:21] + connect \MDS_Rc \opcode_in [0] + connect \MDS_RB \opcode_in [15:11] + connect \MDS_RA \opcode_in [20:16] + connect \MDS_me \opcode_in [10:5] + connect \MDS_mb \opcode_in [10:5] + connect \MDS_IS \opcode_in [25:21] + connect \MDS_IB \opcode_in [15:11] + connect \Z23_XO \opcode_in [8:1] + connect \Z23_TE \opcode_in [20:16] + connect \Z23_RMC \opcode_in [10:9] + connect \Z23_Rc \opcode_in [0] + connect \Z23_R \opcode_in [16] + connect \Z23_FRTp \opcode_in [25:21] + connect \Z23_FRT \opcode_in [25:21] + connect \Z23_FRBp \opcode_in [15:11] + connect \Z23_FRB \opcode_in [15:11] + connect \Z23_FRAp \opcode_in [20:16] + connect \Z23_FRA \opcode_in [20:16] + connect \XFL_XO \opcode_in [10:1] + connect \XFL_W \opcode_in [16] + connect \XFL_Rc \opcode_in [0] + connect \XFL_L \opcode_in [25] + connect \XFL_FRB \opcode_in [15:11] + connect \XFL_FLM \opcode_in [24:17] + connect \VX_XO_1 \opcode_in [10:0] + connect \VX_XO { \opcode_in [10] \opcode_in [8:0] } + connect \VX_VRT \opcode_in [25:21] + connect \VX_VRB \opcode_in [15:11] + connect \VX_VRA \opcode_in [20:16] + connect \VX_UIM_3 \opcode_in [17:16] + connect \VX_UIM_2 \opcode_in [18:16] + connect \VX_UIM_1 \opcode_in [19:16] + connect \VX_UIM \opcode_in [20:16] + connect \VX_SIM \opcode_in [20:16] + connect \VX_RT \opcode_in [25:21] + connect \VX_RA \opcode_in [20:16] + connect \VX_PS \opcode_in [9] + connect \VX_EO \opcode_in [20:16] + connect \DS_XO \opcode_in [1:0] + connect \DS_VRT \opcode_in [25:21] + connect \DS_VRS \opcode_in [25:21] + connect \DS_RT \opcode_in [25:21] + connect \DS_RSp \opcode_in [25:21] + connect \DS_RS \opcode_in [25:21] + connect \DS_RA \opcode_in [20:16] + connect \DS_FRTp \opcode_in [25:21] + connect \DS_FRSp \opcode_in [25:21] + connect \DS_DS \opcode_in [15:2] + connect \DQ_XO \opcode_in [2:0] + connect \DQ_TX_T { \opcode_in [3] \opcode_in [25:21] } + connect \DQ_T \opcode_in [25:21] + connect \DQ_TX \opcode_in [3] + connect \DQ_SX_S { \opcode_in [3] \opcode_in [25:21] } + connect \DQ_S \opcode_in [25:21] + connect \DQ_SX \opcode_in [3] + connect \DQ_RTp \opcode_in [25:21] + connect \DQ_RA \opcode_in [20:16] + connect \DQ_PT \opcode_in [3:0] + connect \DQ_DQ \opcode_in [15:4] + connect \DX_XO \opcode_in [5:1] + connect \DX_RT \opcode_in [25:21] + connect \DX_d0_d1_d2 { \opcode_in [15:6] \opcode_in [20:16] \opcode_in [0] } + connect \DX_d2 \opcode_in [0] + connect \DX_d1 \opcode_in [20:16] + connect \DX_d0 \opcode_in [15:6] + connect \XFX_XO \opcode_in [10:1] + connect \XFX_SPR \opcode_in [20:11] + connect \XFX_RT \opcode_in [25:21] + connect \XFX_RS \opcode_in [25:21] + connect \XFX_FXM \opcode_in [19:12] + connect \XFX_DUIS \opcode_in [20:11] + connect \XFX_DUI \opcode_in [25:21] + connect \XFX_BHRBE \opcode_in [20:11] + connect \EVS_BFA \opcode_in [2:0] + connect \Z22_XO \opcode_in [9:1] + connect \Z22_SH \opcode_in [15:10] + connect \Z22_Rc \opcode_in [0] + connect \Z22_FRTp \opcode_in [25:21] + connect \Z22_FRT \opcode_in [25:21] + connect \Z22_FRAp \opcode_in [20:16] + connect \Z22_FRA \opcode_in [20:16] + connect \Z22_DGM \opcode_in [15:10] + connect \Z22_DCM \opcode_in [15:10] + connect \Z22_BF \opcode_in [25:23] + connect \XX2_XO_1 \opcode_in [10:2] + connect \XX2_XO { \opcode_in [10:7] \opcode_in [5:3] } + connect \XX2_UIM_1 \opcode_in [17:16] + connect \XX2_UIM \opcode_in [19:16] + connect \XX2_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX2_T \opcode_in [25:21] + connect \XX2_TX \opcode_in [0] + connect \XX2_RT \opcode_in [25:21] + connect \XX2_EO \opcode_in [20:16] + connect \XX2_DCMX \opcode_in [22:16] + connect \XX2_dc_dm_dx { \opcode_in [6] \opcode_in [2] \opcode_in [20:16] } + connect \XX2_dx \opcode_in [20:16] + connect \XX2_dm \opcode_in [2] + connect \XX2_dc \opcode_in [6] + connect \XX2_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX2_B \opcode_in [15:11] + connect \XX2_BX \opcode_in [1] + connect \XX2_BF \opcode_in [25:23] + connect \D_UI \opcode_in [15:0] + connect \D_TO \opcode_in [25:21] + connect \D_SI \opcode_in [15:0] + connect \D_RT \opcode_in [25:21] + connect \D_RS \opcode_in [25:21] + connect \D_RA \opcode_in [20:16] + connect \D_L \opcode_in [21] + connect \D_FRT \opcode_in [25:21] + connect \D_FRS \opcode_in [25:21] + connect \D_D \opcode_in [15:0] + connect \D_BF \opcode_in [25:23] + connect \A_XO \opcode_in [5:1] + connect \A_RT \opcode_in [25:21] + connect \A_Rc \opcode_in [0] + connect \A_RB \opcode_in [15:11] + connect \A_RA \opcode_in [20:16] + connect \A_FRT \opcode_in [25:21] + connect \A_FRC \opcode_in [10:6] + connect \A_FRB \opcode_in [15:11] + connect \A_FRA \opcode_in [20:16] + connect \A_BC \opcode_in [10:6] + connect \XL_XO \opcode_in [10:1] + connect \XL_S \opcode_in [11] + connect \XL_OC \opcode_in [25:11] + connect \XL_LK \opcode_in [0] + connect \XL_BT \opcode_in [25:21] + connect \XL_BO_1 \opcode_in [25:21] + connect \XL_BO \opcode_in [25:21] + connect \XL_BI \opcode_in [20:16] + connect \XL_BH \opcode_in [12:11] + connect \XL_BFA \opcode_in [20:18] + connect \XL_BF \opcode_in [25:23] + connect \XL_BB \opcode_in [15:11] + connect \XL_BA \opcode_in [20:16] + connect \XX4_XO \opcode_in [5:4] + connect \XX4_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX4_T \opcode_in [25:21] + connect \XX4_TX \opcode_in [0] + connect \XX4_CX_C { \opcode_in [3] \opcode_in [10:6] } + connect \XX4_C \opcode_in [10:6] + connect \XX4_CX \opcode_in [3] + connect \XX4_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX4_B \opcode_in [15:11] + connect \XX4_BX \opcode_in [1] + connect \XX4_AX_A { \opcode_in [2] \opcode_in [20:16] } + connect \XX4_A \opcode_in [20:16] + connect \XX4_AX \opcode_in [2] + connect \XX3_XO_2 \opcode_in [9:1] + connect \XX3_XO_1 \opcode_in [10:3] + connect \XX3_XO \opcode_in [10:7] + connect \XX3_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX3_T \opcode_in [25:21] + connect \XX3_TX \opcode_in [0] + connect \XX3_SHW \opcode_in [9:8] + connect \XX3_Rc \opcode_in [10] + connect \XX3_DM \opcode_in [9:8] + connect \XX3_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX3_B \opcode_in [15:11] + connect \XX3_BX \opcode_in [1] + connect \XX3_BF \opcode_in [25:23] + connect \XX3_AX_A { \opcode_in [2] \opcode_in [20:16] } + connect \XX3_A \opcode_in [20:16] + connect \XX3_AX \opcode_in [2] + connect \I_LK \opcode_in [0] + connect \I_LI \opcode_in [25:2] + connect \I_AA \opcode_in [1] + connect \B_LK \opcode_in [0] + connect \B_BO \opcode_in [25:21] + connect \B_BI \opcode_in [20:16] + connect \B_BD \opcode_in [15:2] + connect \B_AA \opcode_in [1] + connect \X_XO_1 \opcode_in [8:1] + connect \X_XO \opcode_in [10:1] + connect \X_WC \opcode_in [22:21] + connect \X_W \opcode_in [16] + connect \X_VRT \opcode_in [25:21] + connect \X_VRS \opcode_in [25:21] + connect \X_UIM \opcode_in [20:16] + connect \X_U \opcode_in [15:12] + connect \X_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \X_TX \opcode_in [0] + connect \X_TO \opcode_in [25:21] + connect \X_TH \opcode_in [25:21] + connect \X_TBR \opcode_in [20:11] + connect \X_T \opcode_in [25:21] + connect \X_SX_S { \opcode_in [0] \opcode_in [25:21] } + connect \X_SX \opcode_in [0] + connect \X_SR \opcode_in [19:16] + connect \X_SP \opcode_in [20:19] + connect \X_SI \opcode_in [15:11] + connect \X_SH \opcode_in [15:11] + connect \X_S \opcode_in [25:21] + connect \X_RTp \opcode_in [25:21] + connect \X_RT \opcode_in [25:21] + connect \X_RSp \opcode_in [25:21] + connect \X_RS \opcode_in [25:21] + connect \X_RO \opcode_in [0] + connect \X_RM \opcode_in [12:11] + connect \X_RIC \opcode_in [19:18] + connect \X_Rc \opcode_in [0] + connect \X_RB \opcode_in [15:11] + connect \X_RA \opcode_in [20:16] + connect \X_R_1 \opcode_in [16] + connect \X_R \opcode_in [21] + connect \X_PRS \opcode_in [17] + connect \X_NB \opcode_in [15:11] + connect \X_MO \opcode_in [25:21] + connect \X_L3 \opcode_in [17:16] + connect \X_L1 \opcode_in [16] + connect \X_L \opcode_in [21] + connect \X_L2 \opcode_in [22:21] + connect \X_IMM8 \opcode_in [18:11] + connect \X_IH \opcode_in [23:21] + connect \X_FRTp \opcode_in [25:21] + connect \X_FRT \opcode_in [25:21] + connect \X_FRSp \opcode_in [25:21] + connect \X_FRS \opcode_in [25:21] + connect \X_FRBp \opcode_in [15:11] + connect \X_FRB \opcode_in [15:11] + connect \X_FRAp \opcode_in [20:16] + connect \X_FRA \opcode_in [20:16] + connect \X_FC \opcode_in [15:11] + connect \X_EX \opcode_in [0] + connect \X_EO_1 \opcode_in [20:16] + connect \X_EO \opcode_in [20:19] + connect \X_E_1 \opcode_in [19:16] + connect \X_E \opcode_in [15] + connect \X_DRM \opcode_in [13:11] + connect \X_DCMX \opcode_in [22:16] + connect \X_CT \opcode_in [24:21] + connect \X_BO \opcode_in [25:21] + connect \X_BFA \opcode_in [20:18] + connect \X_BF \opcode_in [25:23] + connect \X_A \opcode_in [25] + connect \CR_SPR \opcode_in [20:11] + connect \CR_MB \opcode_in [10:6] + connect \CR_ME \opcode_in [5:1] + connect \CR_SH \opcode_in [15:11] + connect \CR_BC \opcode_in [10:6] + connect \CR_TO \opcode_in [25:21] + connect \CR_DS \opcode_in [15:2] + connect \CR_D \opcode_in [15:0] + connect \CR_BH \opcode_in [12:11] + connect \CR_BI \opcode_in [20:16] + connect \CR_BO \opcode_in [25:21] + connect \CR_FXM \opcode_in [19:12] + connect \CR_BT \opcode_in [25:21] + connect \CR_BA \opcode_in [20:16] + connect \CR_BB \opcode_in [15:11] + connect \CR_CR \opcode_in [10:1] + connect \CR_BF \opcode_in [25:23] + connect \CR_BD \opcode_in [15:2] + connect \CR_OE \opcode_in [10] + connect \CR_Rc \opcode_in [0] + connect \CR_AA \opcode_in [1] + connect \CR_LK \opcode_in [0] + connect \CR_LI \opcode_in [25:2] + connect \CR_ME32 \opcode_in [5:1] + connect \CR_MB32 \opcode_in [10:6] + connect \CR_sh { \opcode_in [1] \opcode_in [15:11] } + connect \CR_SH32 \opcode_in [15:11] + connect \CR_L \opcode_in [21] + connect \CR_UI \opcode_in [15:0] + connect \CR_SI \opcode_in [15:0] + connect \CR_RB \opcode_in [15:11] + connect \CR_RA \opcode_in [20:16] + connect \CR_RT \opcode_in [25:21] + connect \CR_RS \opcode_in [25:21] + connect \opcode_in \$1 + connect \CR_dec31_opcode_in \opcode_in + connect \CR_dec19_opcode_in \opcode_in + connect \opcode_switch \opcode_in [31:26] +end +attribute \src "libresoc.v:55244.1-56686.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_BRANCH.dec" +attribute \generator "nMigen" +module \dec$146 + attribute \src "libresoc.v:56270.3-56285.6" + wire width 3 $0\BRANCH_cr_in[2:0] + attribute \src "libresoc.v:56286.3-56301.6" + wire width 3 $0\BRANCH_cr_out[2:0] + attribute \src "libresoc.v:56222.3-56237.6" + wire width 13 $0\BRANCH_function_unit[12:0] + attribute \src "libresoc.v:56254.3-56269.6" + wire width 4 $0\BRANCH_in2_sel[3:0] + attribute \src "libresoc.v:56238.3-56253.6" + wire width 7 $0\BRANCH_internal_op[6:0] + attribute \src "libresoc.v:56318.3-56333.6" + wire $0\BRANCH_is_32b[0:0] + attribute \src "libresoc.v:56334.3-56349.6" + wire $0\BRANCH_lk[0:0] + attribute \src "libresoc.v:56302.3-56317.6" + wire width 2 $0\BRANCH_rc_sel[1:0] + attribute \src "libresoc.v:55245.7-55245.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:56270.3-56285.6" + wire width 3 $1\BRANCH_cr_in[2:0] + attribute \src "libresoc.v:56286.3-56301.6" + wire width 3 $1\BRANCH_cr_out[2:0] + attribute \src "libresoc.v:56222.3-56237.6" + wire width 13 $1\BRANCH_function_unit[12:0] + attribute \src "libresoc.v:56254.3-56269.6" + wire width 4 $1\BRANCH_in2_sel[3:0] + attribute \src "libresoc.v:56238.3-56253.6" + wire width 7 $1\BRANCH_internal_op[6:0] + attribute \src "libresoc.v:56318.3-56333.6" + wire $1\BRANCH_is_32b[0:0] + attribute \src "libresoc.v:56334.3-56349.6" + wire $1\BRANCH_lk[0:0] + attribute \src "libresoc.v:56302.3-56317.6" + wire width 2 $1\BRANCH_rc_sel[1:0] + attribute \src "libresoc.v:56210.17-56210.211" + wire width 32 $ternary$libresoc.v:56210$3480_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:504" + wire width 32 \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \A_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \A_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \A_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \A_FRC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \A_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \A_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \A_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \A_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \A_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \A_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire \BRANCH_AA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 output 22 \BRANCH_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 output 21 \BRANCH_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 output 27 \BRANCH_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 14 output 20 \BRANCH_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 3 \BRANCH_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 2 \BRANCH_BH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 output 25 \BRANCH_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \BRANCH_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 output 23 \BRANCH_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 10 \BRANCH_CR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 16 \BRANCH_D + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 14 output 26 \BRANCH_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 8 output 24 \BRANCH_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire \BRANCH_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 24 output 17 \BRANCH_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire output 12 \BRANCH_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \BRANCH_MB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \BRANCH_MB32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \BRANCH_ME + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \BRANCH_ME32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire output 19 \BRANCH_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \BRANCH_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \BRANCH_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \BRANCH_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \BRANCH_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire output 18 \BRANCH_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \BRANCH_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 output 15 \BRANCH_SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 16 output 13 \BRANCH_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 10 output 7 \BRANCH_SPR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \BRANCH_TO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 16 output 14 \BRANCH_UI + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 4 \BRANCH_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 5 \BRANCH_cr_out + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \BRANCH_dec19_BRANCH_dec19_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \BRANCH_dec19_BRANCH_dec19_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 13 \BRANCH_dec19_BRANCH_dec19_function_unit + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 \BRANCH_dec19_BRANCH_dec19_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 \BRANCH_dec19_BRANCH_dec19_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \BRANCH_dec19_BRANCH_dec19_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \BRANCH_dec19_BRANCH_dec19_lk + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \BRANCH_dec19_BRANCH_dec19_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + wire width 32 \BRANCH_dec19_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 13 output 8 \BRANCH_function_unit + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 9 \BRANCH_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 output 6 \BRANCH_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 10 \BRANCH_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 11 \BRANCH_lk + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 3 \BRANCH_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 6 output 16 \BRANCH_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \B_AA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 14 \B_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \B_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \B_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \B_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DQE_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DQE_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 2 \DQE_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 12 \DQ_DQ + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 4 \DQ_PT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DQ_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DQ_RTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DQ_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \DQ_SX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \DQ_SX_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DQ_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \DQ_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \DQ_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 3 \DQ_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 14 \DS_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DS_FRSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DS_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DS_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DS_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DS_RSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DS_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DS_VRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DS_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 2 \DS_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DX_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 10 \DX_d0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 16 \DX_d0_d1_d2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DX_d1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \DX_d2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 3 \D_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 16 \D_D + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \D_FRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \D_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \D_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \D_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \D_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \D_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 16 \D_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \D_TO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 16 \D_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 3 \EVS_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \I_AA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 24 \I_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \I_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \MDS_IB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \MDS_IS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \MDS_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \MDS_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \MDS_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \MDS_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 4 \MDS_XBI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 4 \MDS_XBI_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 4 \MDS_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \MDS_mb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \MDS_me + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \MD_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \MD_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \MD_Rc + attribute \src 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_TO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \X_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \X_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 4 \X_U + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_UIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_VRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \X_W + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 2 \X_WC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 10 \X_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 8 \X_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 3 \Z22_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \Z22_DCM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \Z22_DGM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \Z22_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \Z22_FRAp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \Z22_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \Z22_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \Z22_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \Z22_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 9 \Z22_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \Z23_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \Z23_FRAp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \Z23_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \Z23_FRBp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \Z23_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \Z23_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \Z23_R + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 2 \Z23_RMC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \Z23_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \Z23_TE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 8 \Z23_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \all_OPCD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \all_PO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" + wire input 1 \bigendian + attribute \src "libresoc.v:55245.7-55245.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + wire width 32 output 2 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + wire width 6 \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 32 input 31 \raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:504" + cell $mux $ternary$libresoc.v:56210$3480 + parameter \WIDTH 32 + connect \A \raw_opcode_in + connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } + connect \S \bigendian + connect \Y $ternary$libresoc.v:56210$3480_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:56211.16-56221.4" + cell \BRANCH_dec19 \BRANCH_dec19 + connect \BRANCH_dec19_cr_in \BRANCH_dec19_BRANCH_dec19_cr_in + connect \BRANCH_dec19_cr_out \BRANCH_dec19_BRANCH_dec19_cr_out + connect \BRANCH_dec19_function_unit \BRANCH_dec19_BRANCH_dec19_function_unit + connect \BRANCH_dec19_in2_sel \BRANCH_dec19_BRANCH_dec19_in2_sel + connect \BRANCH_dec19_internal_op \BRANCH_dec19_BRANCH_dec19_internal_op + connect \BRANCH_dec19_is_32b \BRANCH_dec19_BRANCH_dec19_is_32b + connect \BRANCH_dec19_lk \BRANCH_dec19_BRANCH_dec19_lk + connect \BRANCH_dec19_rc_sel \BRANCH_dec19_BRANCH_dec19_rc_sel + connect \opcode_in \BRANCH_dec19_opcode_in + end + attribute \src "libresoc.v:55245.7-55245.20" + process $proc$libresoc.v:55245$3489 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:56222.3-56237.6" + process $proc$libresoc.v:56222$3481 + assign { } { } + assign { } { } + assign $0\BRANCH_function_unit[12:0] $1\BRANCH_function_unit[12:0] + attribute \src "libresoc.v:56223.5-56223.29" + switch \initial + attribute \src "libresoc.v:56223.9-56223.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\BRANCH_function_unit[12:0] \BRANCH_dec19_BRANCH_dec19_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\BRANCH_function_unit[12:0] 13'0000000100000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\BRANCH_function_unit[12:0] 13'0000000100000 + case + assign $1\BRANCH_function_unit[12:0] 13'0000000000000 + end + sync always + update \BRANCH_function_unit $0\BRANCH_function_unit[12:0] + end + attribute \src "libresoc.v:56238.3-56253.6" + process $proc$libresoc.v:56238$3482 + assign { } { } + assign { } { } + assign $0\BRANCH_internal_op[6:0] $1\BRANCH_internal_op[6:0] + attribute \src "libresoc.v:56239.5-56239.29" + switch \initial + attribute \src "libresoc.v:56239.9-56239.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\BRANCH_internal_op[6:0] \BRANCH_dec19_BRANCH_dec19_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\BRANCH_internal_op[6:0] 7'0000110 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\BRANCH_internal_op[6:0] 7'0000111 + case + assign $1\BRANCH_internal_op[6:0] 7'0000000 + end + sync always + update \BRANCH_internal_op $0\BRANCH_internal_op[6:0] + end + attribute \src "libresoc.v:56254.3-56269.6" + process $proc$libresoc.v:56254$3483 + assign { } { } + assign { } { } + assign $0\BRANCH_in2_sel[3:0] $1\BRANCH_in2_sel[3:0] + attribute \src "libresoc.v:56255.5-56255.29" + switch \initial + attribute \src "libresoc.v:56255.9-56255.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\BRANCH_in2_sel[3:0] \BRANCH_dec19_BRANCH_dec19_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\BRANCH_in2_sel[3:0] 4'0110 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\BRANCH_in2_sel[3:0] 4'0111 + case + assign $1\BRANCH_in2_sel[3:0] 4'0000 + end + sync always + update \BRANCH_in2_sel $0\BRANCH_in2_sel[3:0] + end + attribute \src "libresoc.v:56270.3-56285.6" + process $proc$libresoc.v:56270$3484 + assign { } { } + assign { } { } + assign $0\BRANCH_cr_in[2:0] $1\BRANCH_cr_in[2:0] + attribute \src "libresoc.v:56271.5-56271.29" + switch \initial + attribute \src "libresoc.v:56271.9-56271.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\BRANCH_cr_in[2:0] \BRANCH_dec19_BRANCH_dec19_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\BRANCH_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\BRANCH_cr_in[2:0] 3'010 + case + assign $1\BRANCH_cr_in[2:0] 3'000 + end + sync always + update \BRANCH_cr_in $0\BRANCH_cr_in[2:0] + end + attribute \src "libresoc.v:56286.3-56301.6" + process $proc$libresoc.v:56286$3485 + assign { } { } + assign { } { } + assign $0\BRANCH_cr_out[2:0] $1\BRANCH_cr_out[2:0] + attribute \src "libresoc.v:56287.5-56287.29" + switch \initial + attribute \src "libresoc.v:56287.9-56287.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\BRANCH_cr_out[2:0] \BRANCH_dec19_BRANCH_dec19_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\BRANCH_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\BRANCH_cr_out[2:0] 3'000 + case + assign $1\BRANCH_cr_out[2:0] 3'000 + end + sync always + update \BRANCH_cr_out $0\BRANCH_cr_out[2:0] + end + attribute \src "libresoc.v:56302.3-56317.6" + process $proc$libresoc.v:56302$3486 + assign { } { } + assign { } { } + assign $0\BRANCH_rc_sel[1:0] $1\BRANCH_rc_sel[1:0] + attribute \src "libresoc.v:56303.5-56303.29" + switch \initial + attribute \src "libresoc.v:56303.9-56303.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\BRANCH_rc_sel[1:0] \BRANCH_dec19_BRANCH_dec19_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\BRANCH_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\BRANCH_rc_sel[1:0] 2'00 + case + assign $1\BRANCH_rc_sel[1:0] 2'00 + end + sync always + update \BRANCH_rc_sel $0\BRANCH_rc_sel[1:0] + end + attribute \src "libresoc.v:56318.3-56333.6" + process $proc$libresoc.v:56318$3487 + assign { } { } + assign { } { } + assign $0\BRANCH_is_32b[0:0] $1\BRANCH_is_32b[0:0] + attribute \src "libresoc.v:56319.5-56319.29" + switch \initial + attribute \src "libresoc.v:56319.9-56319.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\BRANCH_is_32b[0:0] \BRANCH_dec19_BRANCH_dec19_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\BRANCH_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\BRANCH_is_32b[0:0] 1'0 + case + assign $1\BRANCH_is_32b[0:0] 1'0 + end + sync always + update \BRANCH_is_32b $0\BRANCH_is_32b[0:0] + end + attribute \src "libresoc.v:56334.3-56349.6" + process $proc$libresoc.v:56334$3488 + assign { } { } + assign { } { } + assign $0\BRANCH_lk[0:0] $1\BRANCH_lk[0:0] + attribute \src "libresoc.v:56335.5-56335.29" + switch \initial + attribute \src "libresoc.v:56335.9-56335.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\BRANCH_lk[0:0] \BRANCH_dec19_BRANCH_dec19_lk + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\BRANCH_lk[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\BRANCH_lk[0:0] 1'1 + case + assign $1\BRANCH_lk[0:0] 1'0 + end + sync always + update \BRANCH_lk $0\BRANCH_lk[0:0] + end + connect \$1 $ternary$libresoc.v:56210$3480_Y + connect \VC_XO \opcode_in [9:0] + connect \VC_VRT \opcode_in [25:21] + connect \VC_VRB \opcode_in [15:11] + connect \VC_VRA \opcode_in [20:16] + connect \VC_Rc \opcode_in [10] + connect \XS_XO \opcode_in [10:2] + connect \XS_sh { \opcode_in [1] \opcode_in [15:11] } + connect \XS_RS \opcode_in [25:21] + connect \XS_Rc \opcode_in [0] + connect \XS_RA \opcode_in [20:16] + connect \VA_XO \opcode_in [5:0] + connect \VA_VRT \opcode_in [25:21] + connect \VA_VRC \opcode_in [10:6] + connect \VA_VRB \opcode_in [15:11] + connect \VA_VRA \opcode_in [20:16] + connect \VA_SHB \opcode_in [9:6] + connect \VA_RT \opcode_in [25:21] + connect \VA_RC \opcode_in [10:6] + connect \VA_RB \opcode_in [15:11] + connect \VA_RA \opcode_in [20:16] + connect \TX_XO \opcode_in [6:1] + connect \TX_XBI \opcode_in [10:7] + connect \TX_UI \opcode_in [15:11] + connect \TX_RA \opcode_in [20:16] + connect \DQE_XO \opcode_in [1:0] + connect \DQE_RT \opcode_in [25:21] + connect \DQE_RA \opcode_in [20:16] + connect \XO_XO \opcode_in [9:1] + connect \XO_RT \opcode_in [25:21] + connect \XO_Rc \opcode_in [0] + connect \XO_RB \opcode_in [15:11] + connect \XO_RA \opcode_in [20:16] + connect \XO_OE \opcode_in [10] + connect \all_PO \opcode_in [31:26] + connect \all_OPCD \opcode_in [31:26] + connect \SVL_XO \opcode_in [5:1] + connect \SVL_vs \opcode_in [7] + connect \SVL_SVi \opcode_in [15:10] + connect \SVL_RT \opcode_in [25:21] + connect \SVL_Rc \opcode_in [0] + connect \SVL_RA \opcode_in [20:16] + connect \SVL_ms \opcode_in [6] + connect \MD_XO \opcode_in [4:2] + connect \MD_sh { \opcode_in [1] \opcode_in [15:11] } + connect \MD_RS \opcode_in [25:21] + connect \MD_Rc \opcode_in [0] + connect \MD_RA \opcode_in [20:16] + connect \MD_me \opcode_in [10:5] + connect \MD_mb \opcode_in [10:5] + connect \M_SH \opcode_in [15:11] + connect \M_RS \opcode_in [25:21] + connect \M_Rc \opcode_in [0] + connect \M_RB \opcode_in [15:11] + connect \M_RA \opcode_in [20:16] + connect \M_ME \opcode_in [5:1] + connect \M_MB \opcode_in [10:6] + connect \SC_XO_1 \opcode_in [1:0] + connect \SC_XO \opcode_in [1] + connect \SC_LEV \opcode_in [11:5] + connect \MDS_XO \opcode_in [4:1] + connect \MDS_XBI_1 \opcode_in [10:7] + connect \MDS_XBI \opcode_in [10:7] + connect \MDS_RS \opcode_in [25:21] + connect \MDS_Rc \opcode_in [0] + connect \MDS_RB \opcode_in [15:11] + connect \MDS_RA \opcode_in [20:16] + connect \MDS_me \opcode_in [10:5] + connect \MDS_mb \opcode_in [10:5] + connect \MDS_IS \opcode_in [25:21] + connect \MDS_IB \opcode_in [15:11] + connect \Z23_XO \opcode_in [8:1] + connect \Z23_TE \opcode_in [20:16] + connect \Z23_RMC \opcode_in [10:9] + connect \Z23_Rc \opcode_in [0] + connect \Z23_R \opcode_in [16] + connect \Z23_FRTp \opcode_in [25:21] + connect \Z23_FRT \opcode_in [25:21] + connect \Z23_FRBp \opcode_in [15:11] + connect \Z23_FRB \opcode_in [15:11] + connect \Z23_FRAp \opcode_in [20:16] + connect \Z23_FRA \opcode_in [20:16] + connect \XFL_XO \opcode_in [10:1] + connect \XFL_W \opcode_in [16] + connect \XFL_Rc \opcode_in [0] + connect \XFL_L \opcode_in [25] + connect \XFL_FRB \opcode_in [15:11] + connect \XFL_FLM \opcode_in [24:17] + connect \VX_XO_1 \opcode_in [10:0] + connect \VX_XO { \opcode_in [10] \opcode_in [8:0] } + connect \VX_VRT \opcode_in [25:21] + connect \VX_VRB \opcode_in [15:11] + connect \VX_VRA \opcode_in [20:16] + connect \VX_UIM_3 \opcode_in [17:16] + connect \VX_UIM_2 \opcode_in [18:16] + connect \VX_UIM_1 \opcode_in [19:16] + connect \VX_UIM \opcode_in [20:16] + connect \VX_SIM \opcode_in [20:16] + connect \VX_RT \opcode_in [25:21] + connect \VX_RA \opcode_in [20:16] + connect \VX_PS \opcode_in [9] + connect \VX_EO \opcode_in [20:16] + connect \DS_XO \opcode_in [1:0] + connect \DS_VRT \opcode_in [25:21] + connect \DS_VRS \opcode_in [25:21] + connect \DS_RT \opcode_in [25:21] + connect \DS_RSp \opcode_in [25:21] + connect \DS_RS \opcode_in [25:21] + connect \DS_RA \opcode_in [20:16] + connect \DS_FRTp \opcode_in [25:21] + connect \DS_FRSp \opcode_in [25:21] + connect \DS_DS \opcode_in [15:2] + connect \DQ_XO \opcode_in [2:0] + connect \DQ_TX_T { \opcode_in [3] \opcode_in [25:21] } + connect \DQ_T \opcode_in [25:21] + connect \DQ_TX \opcode_in [3] + connect \DQ_SX_S { \opcode_in [3] \opcode_in [25:21] } + connect \DQ_S \opcode_in [25:21] + connect \DQ_SX \opcode_in [3] + connect \DQ_RTp \opcode_in [25:21] + connect \DQ_RA \opcode_in [20:16] + connect \DQ_PT \opcode_in [3:0] + connect \DQ_DQ \opcode_in [15:4] + connect \DX_XO \opcode_in [5:1] + connect \DX_RT \opcode_in [25:21] + connect \DX_d0_d1_d2 { \opcode_in [15:6] \opcode_in [20:16] \opcode_in [0] } + connect \DX_d2 \opcode_in [0] + connect \DX_d1 \opcode_in [20:16] + connect \DX_d0 \opcode_in [15:6] + connect \XFX_XO \opcode_in [10:1] + connect \XFX_SPR \opcode_in [20:11] + connect \XFX_RT \opcode_in [25:21] + connect \XFX_RS \opcode_in [25:21] + connect \XFX_FXM \opcode_in [19:12] + connect \XFX_DUIS \opcode_in [20:11] + connect \XFX_DUI \opcode_in [25:21] + connect \XFX_BHRBE \opcode_in [20:11] + connect \EVS_BFA \opcode_in [2:0] + connect \Z22_XO \opcode_in [9:1] + connect \Z22_SH \opcode_in [15:10] + connect \Z22_Rc \opcode_in [0] + connect \Z22_FRTp \opcode_in [25:21] + connect \Z22_FRT \opcode_in [25:21] + connect \Z22_FRAp \opcode_in [20:16] + connect \Z22_FRA \opcode_in [20:16] + connect \Z22_DGM \opcode_in [15:10] + connect \Z22_DCM \opcode_in [15:10] + connect \Z22_BF \opcode_in [25:23] + connect \XX2_XO_1 \opcode_in [10:2] + connect \XX2_XO { \opcode_in [10:7] \opcode_in [5:3] } + connect \XX2_UIM_1 \opcode_in [17:16] + connect \XX2_UIM \opcode_in [19:16] + connect \XX2_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX2_T \opcode_in [25:21] + connect \XX2_TX \opcode_in [0] + connect \XX2_RT \opcode_in [25:21] + connect \XX2_EO \opcode_in [20:16] + connect \XX2_DCMX \opcode_in [22:16] + connect \XX2_dc_dm_dx { \opcode_in [6] \opcode_in [2] \opcode_in [20:16] } + connect \XX2_dx \opcode_in [20:16] + connect \XX2_dm \opcode_in [2] + connect \XX2_dc \opcode_in [6] + connect \XX2_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX2_B \opcode_in [15:11] + connect \XX2_BX \opcode_in [1] + connect \XX2_BF \opcode_in [25:23] + connect \D_UI \opcode_in [15:0] + connect \D_TO \opcode_in [25:21] + connect \D_SI \opcode_in [15:0] + connect \D_RT \opcode_in [25:21] + connect \D_RS \opcode_in [25:21] + connect \D_RA \opcode_in [20:16] + connect \D_L \opcode_in [21] + connect \D_FRT \opcode_in [25:21] + connect \D_FRS \opcode_in [25:21] + connect \D_D \opcode_in [15:0] + connect \D_BF \opcode_in [25:23] + connect \A_XO \opcode_in [5:1] + connect \A_RT \opcode_in [25:21] + connect \A_Rc \opcode_in [0] + connect \A_RB \opcode_in [15:11] + connect \A_RA \opcode_in [20:16] + connect \A_FRT \opcode_in [25:21] + connect \A_FRC \opcode_in [10:6] + connect \A_FRB \opcode_in [15:11] + connect \A_FRA \opcode_in [20:16] + connect \A_BC \opcode_in [10:6] + connect \XL_XO \opcode_in [10:1] + connect \XL_S \opcode_in [11] + connect \XL_OC \opcode_in [25:11] + connect \XL_LK \opcode_in [0] + connect \XL_BT \opcode_in [25:21] + connect \XL_BO_1 \opcode_in [25:21] + connect \XL_BO \opcode_in [25:21] + connect \XL_BI \opcode_in [20:16] + connect \XL_BH \opcode_in [12:11] + connect \XL_BFA \opcode_in [20:18] + connect \XL_BF \opcode_in [25:23] + connect \XL_BB \opcode_in [15:11] + connect \XL_BA \opcode_in [20:16] + connect \XX4_XO \opcode_in [5:4] + connect \XX4_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX4_T \opcode_in [25:21] + connect \XX4_TX \opcode_in [0] + connect \XX4_CX_C { \opcode_in [3] \opcode_in [10:6] } + connect \XX4_C \opcode_in [10:6] + connect \XX4_CX \opcode_in [3] + connect \XX4_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX4_B \opcode_in [15:11] + connect \XX4_BX \opcode_in [1] + connect \XX4_AX_A { \opcode_in [2] \opcode_in [20:16] } + connect \XX4_A \opcode_in [20:16] + connect \XX4_AX \opcode_in [2] + connect \XX3_XO_2 \opcode_in [9:1] + connect \XX3_XO_1 \opcode_in [10:3] + connect \XX3_XO \opcode_in [10:7] + connect \XX3_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX3_T \opcode_in [25:21] + connect \XX3_TX \opcode_in [0] + connect \XX3_SHW \opcode_in [9:8] + connect \XX3_Rc \opcode_in [10] + connect \XX3_DM \opcode_in [9:8] + connect \XX3_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX3_B \opcode_in [15:11] + connect \XX3_BX \opcode_in [1] + connect \XX3_BF \opcode_in [25:23] + connect \XX3_AX_A { \opcode_in [2] \opcode_in [20:16] } + connect \XX3_A \opcode_in [20:16] + connect \XX3_AX \opcode_in [2] + connect \I_LK \opcode_in [0] + connect \I_LI \opcode_in [25:2] + connect \I_AA \opcode_in [1] + connect \B_LK \opcode_in [0] + connect \B_BO \opcode_in [25:21] + connect \B_BI \opcode_in [20:16] + connect \B_BD \opcode_in [15:2] + connect \B_AA \opcode_in [1] + connect \X_XO_1 \opcode_in [8:1] + connect \X_XO \opcode_in [10:1] + connect \X_WC \opcode_in [22:21] + connect \X_W \opcode_in [16] + connect \X_VRT \opcode_in [25:21] + connect \X_VRS \opcode_in [25:21] + connect \X_UIM \opcode_in [20:16] + connect \X_U \opcode_in [15:12] + connect \X_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \X_TX \opcode_in [0] + connect \X_TO \opcode_in [25:21] + connect \X_TH \opcode_in [25:21] + connect \X_TBR \opcode_in [20:11] + connect \X_T \opcode_in [25:21] + connect \X_SX_S { \opcode_in [0] \opcode_in [25:21] } + connect \X_SX \opcode_in [0] + connect \X_SR \opcode_in [19:16] + connect \X_SP \opcode_in [20:19] + connect \X_SI \opcode_in [15:11] + connect \X_SH \opcode_in [15:11] + connect \X_S \opcode_in [25:21] + connect \X_RTp \opcode_in [25:21] + connect \X_RT \opcode_in [25:21] + connect \X_RSp \opcode_in [25:21] + connect \X_RS \opcode_in [25:21] + connect \X_RO \opcode_in [0] + connect \X_RM \opcode_in [12:11] + connect \X_RIC \opcode_in [19:18] + connect \X_Rc \opcode_in [0] + connect \X_RB \opcode_in [15:11] + connect \X_RA \opcode_in [20:16] + connect \X_R_1 \opcode_in [16] + connect \X_R \opcode_in [21] + connect \X_PRS \opcode_in [17] + connect \X_NB \opcode_in [15:11] + connect \X_MO \opcode_in [25:21] + connect \X_L3 \opcode_in [17:16] + connect \X_L1 \opcode_in [16] + connect \X_L \opcode_in [21] + connect \X_L2 \opcode_in [22:21] + connect \X_IMM8 \opcode_in [18:11] + connect \X_IH \opcode_in [23:21] + connect \X_FRTp \opcode_in [25:21] + connect \X_FRT \opcode_in [25:21] + connect \X_FRSp \opcode_in [25:21] + connect \X_FRS \opcode_in [25:21] + connect \X_FRBp \opcode_in [15:11] + connect \X_FRB \opcode_in [15:11] + connect \X_FRAp \opcode_in [20:16] + connect \X_FRA \opcode_in [20:16] + connect \X_FC \opcode_in [15:11] + connect \X_EX \opcode_in [0] + connect \X_EO_1 \opcode_in [20:16] + connect \X_EO \opcode_in [20:19] + connect \X_E_1 \opcode_in [19:16] + connect \X_E \opcode_in [15] + connect \X_DRM \opcode_in [13:11] + connect \X_DCMX \opcode_in [22:16] + connect \X_CT \opcode_in [24:21] + connect \X_BO \opcode_in [25:21] + connect \X_BFA \opcode_in [20:18] + connect \X_BF \opcode_in [25:23] + connect \X_A \opcode_in [25] + connect \BRANCH_SPR \opcode_in [20:11] + connect \BRANCH_MB \opcode_in [10:6] + connect \BRANCH_ME \opcode_in [5:1] + connect \BRANCH_SH \opcode_in [15:11] + connect \BRANCH_BC \opcode_in [10:6] + connect \BRANCH_TO \opcode_in [25:21] + connect \BRANCH_DS \opcode_in [15:2] + connect \BRANCH_D \opcode_in [15:0] + connect \BRANCH_BH \opcode_in [12:11] + connect \BRANCH_BI \opcode_in [20:16] + connect \BRANCH_BO \opcode_in [25:21] + connect \BRANCH_FXM \opcode_in [19:12] + connect \BRANCH_BT \opcode_in [25:21] + connect \BRANCH_BA \opcode_in [20:16] + connect \BRANCH_BB \opcode_in [15:11] + connect \BRANCH_CR \opcode_in [10:1] + connect \BRANCH_BF \opcode_in [25:23] + connect \BRANCH_BD \opcode_in [15:2] + connect \BRANCH_OE \opcode_in [10] + connect \BRANCH_Rc \opcode_in [0] + connect \BRANCH_AA \opcode_in [1] + connect \BRANCH_LK \opcode_in [0] + connect \BRANCH_LI \opcode_in [25:2] + connect \BRANCH_ME32 \opcode_in [5:1] + connect \BRANCH_MB32 \opcode_in [10:6] + connect \BRANCH_sh { \opcode_in [1] \opcode_in [15:11] } + connect \BRANCH_SH32 \opcode_in [15:11] + connect \BRANCH_L \opcode_in [21] + connect \BRANCH_UI \opcode_in [15:0] + connect \BRANCH_SI \opcode_in [15:0] + connect \BRANCH_RB \opcode_in [15:11] + connect \BRANCH_RA \opcode_in [20:16] + connect \BRANCH_RT \opcode_in [25:21] + connect \BRANCH_RS \opcode_in [25:21] + connect \opcode_in \$1 + connect \BRANCH_dec19_opcode_in \opcode_in + connect \opcode_switch \opcode_in [31:26] +end +attribute \src "libresoc.v:56690.1-58464.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LOGICAL.dec" +attribute \generator "nMigen" +module \dec$154 + attribute \src "libresoc.v:58016.3-58043.6" + wire width 3 $0\LOGICAL_cr_in[2:0] + attribute \src "libresoc.v:58044.3-58071.6" + wire width 3 $0\LOGICAL_cr_out[2:0] + attribute \src "libresoc.v:57736.3-57763.6" + wire width 2 $0\LOGICAL_cry_in[1:0] + attribute \src "libresoc.v:57820.3-57847.6" + wire $0\LOGICAL_cry_out[0:0] + attribute \src "libresoc.v:57904.3-57931.6" + wire width 13 $0\LOGICAL_function_unit[12:0] + attribute \src "libresoc.v:57960.3-57987.6" + wire width 3 $0\LOGICAL_in1_sel[2:0] + attribute \src "libresoc.v:57988.3-58015.6" + wire width 4 $0\LOGICAL_in2_sel[3:0] + attribute \src "libresoc.v:57932.3-57959.6" + wire width 7 $0\LOGICAL_internal_op[6:0] + attribute \src "libresoc.v:57764.3-57791.6" + wire $0\LOGICAL_inv_a[0:0] + attribute \src "libresoc.v:57792.3-57819.6" + wire $0\LOGICAL_inv_out[0:0] + attribute \src "libresoc.v:57848.3-57875.6" + wire $0\LOGICAL_is_32b[0:0] + attribute \src "libresoc.v:58072.3-58099.6" + wire width 4 $0\LOGICAL_ldst_len[3:0] + attribute \src "libresoc.v:58100.3-58127.6" + wire width 2 $0\LOGICAL_rc_sel[1:0] + attribute \src "libresoc.v:57876.3-57903.6" + wire $0\LOGICAL_sgn[0:0] + attribute \src "libresoc.v:56691.7-56691.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:58016.3-58043.6" + wire width 3 $1\LOGICAL_cr_in[2:0] + attribute \src "libresoc.v:58044.3-58071.6" + wire width 3 $1\LOGICAL_cr_out[2:0] + attribute \src "libresoc.v:57736.3-57763.6" + wire width 2 $1\LOGICAL_cry_in[1:0] + attribute \src "libresoc.v:57820.3-57847.6" + wire $1\LOGICAL_cry_out[0:0] + attribute \src "libresoc.v:57904.3-57931.6" + wire width 13 $1\LOGICAL_function_unit[12:0] + attribute \src "libresoc.v:57960.3-57987.6" + wire width 3 $1\LOGICAL_in1_sel[2:0] + attribute \src "libresoc.v:57988.3-58015.6" + wire width 4 $1\LOGICAL_in2_sel[3:0] + attribute \src "libresoc.v:57932.3-57959.6" + wire width 7 $1\LOGICAL_internal_op[6:0] + attribute \src "libresoc.v:57764.3-57791.6" + wire $1\LOGICAL_inv_a[0:0] + attribute \src "libresoc.v:57792.3-57819.6" + wire $1\LOGICAL_inv_out[0:0] + attribute \src "libresoc.v:57848.3-57875.6" + wire $1\LOGICAL_is_32b[0:0] + attribute \src "libresoc.v:58072.3-58099.6" + wire width 4 $1\LOGICAL_ldst_len[3:0] + attribute \src "libresoc.v:58100.3-58127.6" + wire width 2 $1\LOGICAL_rc_sel[1:0] + attribute \src "libresoc.v:57876.3-57903.6" + wire $1\LOGICAL_sgn[0:0] + attribute \src "libresoc.v:57718.17-57718.211" + wire width 32 $ternary$libresoc.v:57718$3490_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:504" + wire width 32 \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \A_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \A_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \A_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \A_FRC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \A_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \A_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \A_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \A_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \A_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \A_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \B_AA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 14 \B_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \B_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \B_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \B_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DQE_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DQE_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 2 \DQE_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 12 \DQ_DQ + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 4 \DQ_PT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DQ_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DQ_RTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DQ_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \DQ_SX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \DQ_SX_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DQ_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \DQ_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \DQ_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 3 \DQ_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 14 \DS_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DS_FRSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DS_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DS_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DS_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DS_RSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DS_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DS_VRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DS_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 2 \DS_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DX_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 10 \DX_d0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 16 \DX_d0_d1_d2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DX_d1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \DX_d2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 3 \D_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 16 \D_D + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \D_FRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \D_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \D_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \D_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \D_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \D_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 16 \D_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \D_TO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 16 \D_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 3 \EVS_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \I_AA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 24 \I_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \I_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire \LOGICAL_AA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 output 28 \LOGICAL_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 output 27 \LOGICAL_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 output 33 \LOGICAL_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 14 output 26 \LOGICAL_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 3 \LOGICAL_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 2 \LOGICAL_BH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 output 31 \LOGICAL_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \LOGICAL_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 output 29 \LOGICAL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 10 \LOGICAL_CR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 16 \LOGICAL_D + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 14 output 32 \LOGICAL_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 8 output 30 \LOGICAL_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire \LOGICAL_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 24 output 23 \LOGICAL_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire \LOGICAL_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \LOGICAL_MB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \LOGICAL_MB32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \LOGICAL_ME + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \LOGICAL_ME32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire output 25 \LOGICAL_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 output 18 \LOGICAL_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \LOGICAL_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \LOGICAL_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \LOGICAL_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire output 24 \LOGICAL_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \LOGICAL_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 output 21 \LOGICAL_SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 16 output 19 \LOGICAL_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 10 output 7 \LOGICAL_SPR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \LOGICAL_TO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 16 output 20 \LOGICAL_UI + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 4 \LOGICAL_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 5 \LOGICAL_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 14 \LOGICAL_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 15 \LOGICAL_cry_out + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \LOGICAL_dec31_LOGICAL_dec31_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \LOGICAL_dec31_LOGICAL_dec31_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \LOGICAL_dec31_LOGICAL_dec31_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \LOGICAL_dec31_LOGICAL_dec31_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 13 \LOGICAL_dec31_LOGICAL_dec31_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \LOGICAL_dec31_LOGICAL_dec31_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 \LOGICAL_dec31_LOGICAL_dec31_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 \LOGICAL_dec31_LOGICAL_dec31_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \LOGICAL_dec31_LOGICAL_dec31_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \LOGICAL_dec31_LOGICAL_dec31_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \LOGICAL_dec31_LOGICAL_dec31_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 \LOGICAL_dec31_LOGICAL_dec31_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \LOGICAL_dec31_LOGICAL_dec31_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \LOGICAL_dec31_LOGICAL_dec31_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + wire width 32 \LOGICAL_dec31_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 13 output 8 \LOGICAL_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 9 \LOGICAL_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 10 \LOGICAL_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 output 6 \LOGICAL_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 12 \LOGICAL_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 13 \LOGICAL_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 16 \LOGICAL_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 11 \LOGICAL_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 3 \LOGICAL_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 17 \LOGICAL_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 6 output 22 \LOGICAL_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \MDS_IB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \MDS_IS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \MDS_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \MDS_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \MDS_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \MDS_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 4 \MDS_XBI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 4 \MDS_XBI_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 4 \MDS_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \MDS_mb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \MDS_me + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \MD_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \MD_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \MD_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 3 \MD_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \MD_mb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \MD_me + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \MD_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \M_MB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \M_ME + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \M_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \M_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \M_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \M_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \M_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 7 \SC_LEV + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \SC_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 2 \SC_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \SVL_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \SVL_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \SVL_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \SVL_SVi + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \SVL_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \SVL_ms + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \SVL_vs + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \TX_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \TX_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 4 \TX_XBI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \TX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \VA_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \VA_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \VA_RC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \VA_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 4 \VA_SHB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \VA_VRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \VA_VRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \VA_VRC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \VA_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \VA_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \VC_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \VC_VRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \VC_VRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \VC_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 10 \VC_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \VX_EO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \VX_PS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \VX_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \VX_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \VX_SIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \VX_UIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 4 \VX_UIM_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 3 \VX_UIM_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 2 \VX_UIM_3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \VX_VRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \VX_VRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \VX_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 10 \VX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 11 \VX_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 8 \XFL_FLM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \XFL_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \XFL_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \XFL_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \XFL_W + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 10 \XFL_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 10 \XFX_BHRBE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \XFX_DUI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 10 \XFX_DUIS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 8 \XFX_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \XFX_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \XFX_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 10 \XFX_SPR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 10 \XFX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \XL_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \XL_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 3 \XL_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 3 \XL_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 2 \XL_BH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \XL_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \XL_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \XL_BO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 output 36 \XL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \XL_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 15 \XL_OC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \XL_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 10 \XL_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \XO_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \XO_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \XO_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \XO_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \XO_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 9 \XO_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \XS_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \XS_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \XS_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 9 \XS_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \XS_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \XX2_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 3 \XX2_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \XX2_BX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \XX2_BX_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 7 \XX2_DCMX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \XX2_EO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \XX2_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \XX2_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \XX2_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \XX2_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 4 \XX2_UIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 2 \XX2_UIM_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 7 \XX2_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 9 \XX2_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \XX2_dc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 7 \XX2_dc_dm_dx + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \XX2_dm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \XX2_dx + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \XX3_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \XX3_AX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \XX3_AX_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \XX3_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 3 \XX3_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \XX3_BX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \XX3_BX_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 2 \XX3_DM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \XX3_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 2 \XX3_SHW + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \XX3_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \XX3_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \XX3_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 4 \XX3_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 8 \XX3_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 9 \XX3_XO_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \XX4_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \XX4_AX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \XX4_AX_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \XX4_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \XX4_BX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \XX4_BX_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \XX4_C + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \XX4_CX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \XX4_CX_C + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \XX4_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \XX4_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \XX4_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 2 \XX4_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \X_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 3 output 34 \X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 3 output 35 \X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 4 \X_CT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 7 \X_DCMX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 3 \X_DRM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \X_E + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 2 \X_EO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_EO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \X_EX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 4 \X_E_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_FC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_FRAp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_FRBp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_FRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_FRSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 3 \X_IH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 8 \X_IMM8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \X_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \X_L1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 2 \X_L2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 2 \X_L3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_MO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_NB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \X_PRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \X_R + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 2 \X_RIC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 2 \X_RM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \X_RO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_RSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_RTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \X_R_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \X_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 2 \X_SP + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 4 \X_SR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \X_SX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \X_SX_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 10 \X_TBR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_TH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_TO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \X_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \X_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 4 \X_U + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_UIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_VRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \X_W + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 2 \X_WC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 10 \X_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 8 \X_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 3 \Z22_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \Z22_DCM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \Z22_DGM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \Z22_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \Z22_FRAp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \Z22_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \Z22_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \Z22_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \Z22_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 9 \Z22_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \Z23_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \Z23_FRAp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \Z23_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \Z23_FRBp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \Z23_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \Z23_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \Z23_R + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 2 \Z23_RMC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \Z23_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \Z23_TE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 8 \Z23_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \all_OPCD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \all_PO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" + wire input 1 \bigendian + attribute \src "libresoc.v:56691.7-56691.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + wire width 32 output 2 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + wire width 6 \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 32 input 37 \raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:504" + cell $mux $ternary$libresoc.v:57718$3490 + parameter \WIDTH 32 + connect \A \raw_opcode_in + connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } + connect \S \bigendian + connect \Y $ternary$libresoc.v:57718$3490_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:57719.17-57735.4" + cell \LOGICAL_dec31 \LOGICAL_dec31 + connect \LOGICAL_dec31_cr_in \LOGICAL_dec31_LOGICAL_dec31_cr_in + connect \LOGICAL_dec31_cr_out \LOGICAL_dec31_LOGICAL_dec31_cr_out + connect \LOGICAL_dec31_cry_in \LOGICAL_dec31_LOGICAL_dec31_cry_in + connect \LOGICAL_dec31_cry_out \LOGICAL_dec31_LOGICAL_dec31_cry_out + connect \LOGICAL_dec31_function_unit \LOGICAL_dec31_LOGICAL_dec31_function_unit + connect \LOGICAL_dec31_in1_sel \LOGICAL_dec31_LOGICAL_dec31_in1_sel + connect \LOGICAL_dec31_in2_sel \LOGICAL_dec31_LOGICAL_dec31_in2_sel + connect \LOGICAL_dec31_internal_op \LOGICAL_dec31_LOGICAL_dec31_internal_op + connect \LOGICAL_dec31_inv_a \LOGICAL_dec31_LOGICAL_dec31_inv_a + connect \LOGICAL_dec31_inv_out \LOGICAL_dec31_LOGICAL_dec31_inv_out + connect \LOGICAL_dec31_is_32b \LOGICAL_dec31_LOGICAL_dec31_is_32b + connect \LOGICAL_dec31_ldst_len \LOGICAL_dec31_LOGICAL_dec31_ldst_len + connect \LOGICAL_dec31_rc_sel \LOGICAL_dec31_LOGICAL_dec31_rc_sel + connect \LOGICAL_dec31_sgn \LOGICAL_dec31_LOGICAL_dec31_sgn + connect \opcode_in \LOGICAL_dec31_opcode_in + end + attribute \src "libresoc.v:56691.7-56691.20" + process $proc$libresoc.v:56691$3505 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:57736.3-57763.6" + process $proc$libresoc.v:57736$3491 + assign { } { } + assign { } { } + assign $0\LOGICAL_cry_in[1:0] $1\LOGICAL_cry_in[1:0] + attribute \src "libresoc.v:57737.5-57737.29" + switch \initial + attribute \src "libresoc.v:57737.9-57737.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\LOGICAL_cry_in[1:0] \LOGICAL_dec31_LOGICAL_dec31_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\LOGICAL_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\LOGICAL_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\LOGICAL_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\LOGICAL_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\LOGICAL_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\LOGICAL_cry_in[1:0] 2'00 + case + assign $1\LOGICAL_cry_in[1:0] 2'00 + end + sync always + update \LOGICAL_cry_in $0\LOGICAL_cry_in[1:0] + end + attribute \src "libresoc.v:57764.3-57791.6" + process $proc$libresoc.v:57764$3492 + assign { } { } + assign { } { } + assign $0\LOGICAL_inv_a[0:0] $1\LOGICAL_inv_a[0:0] + attribute \src "libresoc.v:57765.5-57765.29" + switch \initial + attribute \src "libresoc.v:57765.9-57765.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\LOGICAL_inv_a[0:0] \LOGICAL_dec31_LOGICAL_dec31_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\LOGICAL_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\LOGICAL_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\LOGICAL_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\LOGICAL_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\LOGICAL_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\LOGICAL_inv_a[0:0] 1'0 + case + assign $1\LOGICAL_inv_a[0:0] 1'0 + end + sync always + update \LOGICAL_inv_a $0\LOGICAL_inv_a[0:0] + end + attribute \src "libresoc.v:57792.3-57819.6" + process $proc$libresoc.v:57792$3493 + assign { } { } + assign { } { } + assign $0\LOGICAL_inv_out[0:0] $1\LOGICAL_inv_out[0:0] + attribute \src "libresoc.v:57793.5-57793.29" + switch \initial + attribute \src "libresoc.v:57793.9-57793.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\LOGICAL_inv_out[0:0] \LOGICAL_dec31_LOGICAL_dec31_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\LOGICAL_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\LOGICAL_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\LOGICAL_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\LOGICAL_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\LOGICAL_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\LOGICAL_inv_out[0:0] 1'0 + case + assign $1\LOGICAL_inv_out[0:0] 1'0 + end + sync always + update \LOGICAL_inv_out $0\LOGICAL_inv_out[0:0] + end + attribute \src "libresoc.v:57820.3-57847.6" + process $proc$libresoc.v:57820$3494 + assign { } { } + assign { } { } + assign $0\LOGICAL_cry_out[0:0] $1\LOGICAL_cry_out[0:0] + attribute \src "libresoc.v:57821.5-57821.29" + switch \initial + attribute \src "libresoc.v:57821.9-57821.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\LOGICAL_cry_out[0:0] \LOGICAL_dec31_LOGICAL_dec31_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\LOGICAL_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\LOGICAL_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\LOGICAL_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\LOGICAL_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\LOGICAL_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\LOGICAL_cry_out[0:0] 1'0 + case + assign $1\LOGICAL_cry_out[0:0] 1'0 + end + sync always + update \LOGICAL_cry_out $0\LOGICAL_cry_out[0:0] + end + attribute \src "libresoc.v:57848.3-57875.6" + process $proc$libresoc.v:57848$3495 + assign { } { } + assign { } { } + assign $0\LOGICAL_is_32b[0:0] $1\LOGICAL_is_32b[0:0] + attribute \src "libresoc.v:57849.5-57849.29" + switch \initial + attribute \src "libresoc.v:57849.9-57849.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\LOGICAL_is_32b[0:0] \LOGICAL_dec31_LOGICAL_dec31_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\LOGICAL_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\LOGICAL_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\LOGICAL_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\LOGICAL_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\LOGICAL_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\LOGICAL_is_32b[0:0] 1'0 + case + assign $1\LOGICAL_is_32b[0:0] 1'0 + end + sync always + update \LOGICAL_is_32b $0\LOGICAL_is_32b[0:0] + end + attribute \src "libresoc.v:57876.3-57903.6" + process $proc$libresoc.v:57876$3496 + assign { } { } + assign { } { } + assign $0\LOGICAL_sgn[0:0] $1\LOGICAL_sgn[0:0] + attribute \src "libresoc.v:57877.5-57877.29" + switch \initial + attribute \src "libresoc.v:57877.9-57877.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\LOGICAL_sgn[0:0] \LOGICAL_dec31_LOGICAL_dec31_sgn + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\LOGICAL_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\LOGICAL_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\LOGICAL_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\LOGICAL_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\LOGICAL_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\LOGICAL_sgn[0:0] 1'0 + case + assign $1\LOGICAL_sgn[0:0] 1'0 + end + sync always + update \LOGICAL_sgn $0\LOGICAL_sgn[0:0] + end + attribute \src "libresoc.v:57904.3-57931.6" + process $proc$libresoc.v:57904$3497 + assign { } { } + assign { } { } + assign $0\LOGICAL_function_unit[12:0] $1\LOGICAL_function_unit[12:0] + attribute \src "libresoc.v:57905.5-57905.29" + switch \initial + attribute \src "libresoc.v:57905.9-57905.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\LOGICAL_function_unit[12:0] \LOGICAL_dec31_LOGICAL_dec31_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\LOGICAL_function_unit[12:0] 13'0000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\LOGICAL_function_unit[12:0] 13'0000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\LOGICAL_function_unit[12:0] 13'0000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\LOGICAL_function_unit[12:0] 13'0000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\LOGICAL_function_unit[12:0] 13'0000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\LOGICAL_function_unit[12:0] 13'0000000010000 + case + assign $1\LOGICAL_function_unit[12:0] 13'0000000000000 + end + sync always + update \LOGICAL_function_unit $0\LOGICAL_function_unit[12:0] + end + attribute \src "libresoc.v:57932.3-57959.6" + process $proc$libresoc.v:57932$3498 + assign { } { } + assign { } { } + assign $0\LOGICAL_internal_op[6:0] $1\LOGICAL_internal_op[6:0] + attribute \src "libresoc.v:57933.5-57933.29" + switch \initial + attribute \src "libresoc.v:57933.9-57933.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\LOGICAL_internal_op[6:0] \LOGICAL_dec31_LOGICAL_dec31_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\LOGICAL_internal_op[6:0] 7'0000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\LOGICAL_internal_op[6:0] 7'0000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\LOGICAL_internal_op[6:0] 7'0110101 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\LOGICAL_internal_op[6:0] 7'0110101 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\LOGICAL_internal_op[6:0] 7'1000011 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\LOGICAL_internal_op[6:0] 7'1000011 + case + assign $1\LOGICAL_internal_op[6:0] 7'0000000 + end + sync always + update \LOGICAL_internal_op $0\LOGICAL_internal_op[6:0] + end + attribute \src "libresoc.v:57960.3-57987.6" + process $proc$libresoc.v:57960$3499 + assign { } { } + assign { } { } + assign $0\LOGICAL_in1_sel[2:0] $1\LOGICAL_in1_sel[2:0] + attribute \src "libresoc.v:57961.5-57961.29" + switch \initial + attribute \src "libresoc.v:57961.9-57961.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\LOGICAL_in1_sel[2:0] \LOGICAL_dec31_LOGICAL_dec31_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\LOGICAL_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\LOGICAL_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\LOGICAL_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\LOGICAL_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\LOGICAL_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\LOGICAL_in1_sel[2:0] 3'100 + case + assign $1\LOGICAL_in1_sel[2:0] 3'000 + end + sync always + update \LOGICAL_in1_sel $0\LOGICAL_in1_sel[2:0] + end + attribute \src "libresoc.v:57988.3-58015.6" + process $proc$libresoc.v:57988$3500 + assign { } { } + assign { } { } + assign $0\LOGICAL_in2_sel[3:0] $1\LOGICAL_in2_sel[3:0] + attribute \src "libresoc.v:57989.5-57989.29" + switch \initial + attribute \src "libresoc.v:57989.9-57989.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\LOGICAL_in2_sel[3:0] \LOGICAL_dec31_LOGICAL_dec31_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\LOGICAL_in2_sel[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\LOGICAL_in2_sel[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\LOGICAL_in2_sel[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\LOGICAL_in2_sel[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\LOGICAL_in2_sel[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\LOGICAL_in2_sel[3:0] 4'0100 + case + assign $1\LOGICAL_in2_sel[3:0] 4'0000 + end + sync always + update \LOGICAL_in2_sel $0\LOGICAL_in2_sel[3:0] + end + attribute \src "libresoc.v:58016.3-58043.6" + process $proc$libresoc.v:58016$3501 + assign { } { } + assign { } { } + assign $0\LOGICAL_cr_in[2:0] $1\LOGICAL_cr_in[2:0] + attribute \src "libresoc.v:58017.5-58017.29" + switch \initial + attribute \src "libresoc.v:58017.9-58017.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\LOGICAL_cr_in[2:0] \LOGICAL_dec31_LOGICAL_dec31_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\LOGICAL_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\LOGICAL_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\LOGICAL_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\LOGICAL_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\LOGICAL_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\LOGICAL_cr_in[2:0] 3'000 + case + assign $1\LOGICAL_cr_in[2:0] 3'000 + end + sync always + update \LOGICAL_cr_in $0\LOGICAL_cr_in[2:0] + end + attribute \src "libresoc.v:58044.3-58071.6" + process $proc$libresoc.v:58044$3502 + assign { } { } + assign { } { } + assign $0\LOGICAL_cr_out[2:0] $1\LOGICAL_cr_out[2:0] + attribute \src "libresoc.v:58045.5-58045.29" + switch \initial + attribute \src "libresoc.v:58045.9-58045.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\LOGICAL_cr_out[2:0] \LOGICAL_dec31_LOGICAL_dec31_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\LOGICAL_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\LOGICAL_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\LOGICAL_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\LOGICAL_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\LOGICAL_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\LOGICAL_cr_out[2:0] 3'000 + case + assign $1\LOGICAL_cr_out[2:0] 3'000 + end + sync always + update \LOGICAL_cr_out $0\LOGICAL_cr_out[2:0] + end + attribute \src "libresoc.v:58072.3-58099.6" + process $proc$libresoc.v:58072$3503 + assign { } { } + assign { } { } + assign $0\LOGICAL_ldst_len[3:0] $1\LOGICAL_ldst_len[3:0] + attribute \src "libresoc.v:58073.5-58073.29" + switch \initial + attribute \src "libresoc.v:58073.9-58073.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\LOGICAL_ldst_len[3:0] \LOGICAL_dec31_LOGICAL_dec31_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\LOGICAL_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\LOGICAL_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\LOGICAL_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\LOGICAL_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\LOGICAL_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\LOGICAL_ldst_len[3:0] 4'0000 + case + assign $1\LOGICAL_ldst_len[3:0] 4'0000 + end + sync always + update \LOGICAL_ldst_len $0\LOGICAL_ldst_len[3:0] + end + attribute \src "libresoc.v:58100.3-58127.6" + process $proc$libresoc.v:58100$3504 + assign { } { } + assign { } { } + assign $0\LOGICAL_rc_sel[1:0] $1\LOGICAL_rc_sel[1:0] + attribute \src "libresoc.v:58101.5-58101.29" + switch \initial + attribute \src "libresoc.v:58101.9-58101.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\LOGICAL_rc_sel[1:0] \LOGICAL_dec31_LOGICAL_dec31_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\LOGICAL_rc_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\LOGICAL_rc_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\LOGICAL_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\LOGICAL_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\LOGICAL_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\LOGICAL_rc_sel[1:0] 2'00 + case + assign $1\LOGICAL_rc_sel[1:0] 2'00 + end + sync always + update \LOGICAL_rc_sel $0\LOGICAL_rc_sel[1:0] + end + connect \$1 $ternary$libresoc.v:57718$3490_Y + connect \VC_XO \opcode_in [9:0] + connect \VC_VRT \opcode_in [25:21] + connect \VC_VRB \opcode_in [15:11] + connect \VC_VRA \opcode_in [20:16] + connect \VC_Rc \opcode_in [10] + connect \XS_XO \opcode_in [10:2] + connect \XS_sh { \opcode_in [1] \opcode_in [15:11] } + connect \XS_RS \opcode_in [25:21] + connect \XS_Rc \opcode_in [0] + connect \XS_RA \opcode_in [20:16] + connect \VA_XO \opcode_in [5:0] + connect \VA_VRT \opcode_in [25:21] + connect \VA_VRC \opcode_in [10:6] + connect \VA_VRB \opcode_in [15:11] + connect \VA_VRA \opcode_in [20:16] + connect \VA_SHB \opcode_in [9:6] + connect \VA_RT \opcode_in [25:21] + connect \VA_RC \opcode_in [10:6] + connect \VA_RB \opcode_in [15:11] + connect \VA_RA \opcode_in [20:16] + connect \TX_XO \opcode_in [6:1] + connect \TX_XBI \opcode_in [10:7] + connect \TX_UI \opcode_in [15:11] + connect \TX_RA \opcode_in [20:16] + connect \DQE_XO \opcode_in [1:0] + connect \DQE_RT \opcode_in [25:21] + connect \DQE_RA \opcode_in [20:16] + connect \XO_XO \opcode_in [9:1] + connect \XO_RT \opcode_in [25:21] + connect \XO_Rc \opcode_in [0] + connect \XO_RB \opcode_in [15:11] + connect \XO_RA \opcode_in [20:16] + connect \XO_OE \opcode_in [10] + connect \all_PO \opcode_in [31:26] + connect \all_OPCD \opcode_in [31:26] + connect \SVL_XO \opcode_in [5:1] + connect \SVL_vs \opcode_in [7] + connect \SVL_SVi \opcode_in [15:10] + connect \SVL_RT \opcode_in [25:21] + connect \SVL_Rc \opcode_in [0] + connect \SVL_RA \opcode_in [20:16] + connect \SVL_ms \opcode_in [6] + connect \MD_XO \opcode_in [4:2] + connect \MD_sh { \opcode_in [1] \opcode_in [15:11] } + connect \MD_RS \opcode_in [25:21] + connect \MD_Rc \opcode_in [0] + connect \MD_RA \opcode_in [20:16] + connect \MD_me \opcode_in [10:5] + connect \MD_mb \opcode_in [10:5] + connect \M_SH \opcode_in [15:11] + connect \M_RS \opcode_in [25:21] + connect \M_Rc \opcode_in [0] + connect \M_RB \opcode_in [15:11] + connect \M_RA \opcode_in [20:16] + connect \M_ME \opcode_in [5:1] + connect \M_MB \opcode_in [10:6] + connect \SC_XO_1 \opcode_in [1:0] + connect \SC_XO \opcode_in [1] + connect \SC_LEV \opcode_in [11:5] + connect \MDS_XO \opcode_in [4:1] + connect \MDS_XBI_1 \opcode_in [10:7] + connect \MDS_XBI \opcode_in [10:7] + connect \MDS_RS \opcode_in [25:21] + connect \MDS_Rc \opcode_in [0] + connect \MDS_RB \opcode_in [15:11] + connect \MDS_RA \opcode_in [20:16] + connect \MDS_me \opcode_in [10:5] + connect \MDS_mb \opcode_in [10:5] + connect \MDS_IS \opcode_in [25:21] + connect \MDS_IB \opcode_in [15:11] + connect \Z23_XO \opcode_in [8:1] + connect \Z23_TE \opcode_in [20:16] + connect \Z23_RMC \opcode_in [10:9] + connect \Z23_Rc \opcode_in [0] + connect \Z23_R \opcode_in [16] + connect \Z23_FRTp \opcode_in [25:21] + connect \Z23_FRT \opcode_in [25:21] + connect \Z23_FRBp \opcode_in [15:11] + connect \Z23_FRB \opcode_in [15:11] + connect \Z23_FRAp \opcode_in [20:16] + connect \Z23_FRA \opcode_in [20:16] + connect \XFL_XO \opcode_in [10:1] + connect \XFL_W \opcode_in [16] + connect \XFL_Rc \opcode_in [0] + connect \XFL_L \opcode_in [25] + connect \XFL_FRB \opcode_in [15:11] + connect \XFL_FLM \opcode_in [24:17] + connect \VX_XO_1 \opcode_in [10:0] + connect \VX_XO { \opcode_in [10] \opcode_in [8:0] } + connect \VX_VRT \opcode_in [25:21] + connect \VX_VRB \opcode_in [15:11] + connect \VX_VRA \opcode_in [20:16] + connect \VX_UIM_3 \opcode_in [17:16] + connect \VX_UIM_2 \opcode_in [18:16] + connect \VX_UIM_1 \opcode_in [19:16] + connect \VX_UIM \opcode_in [20:16] + connect \VX_SIM \opcode_in [20:16] + connect \VX_RT \opcode_in [25:21] + connect \VX_RA \opcode_in [20:16] + connect \VX_PS \opcode_in [9] + connect \VX_EO \opcode_in [20:16] + connect \DS_XO \opcode_in [1:0] + connect \DS_VRT \opcode_in [25:21] + connect \DS_VRS \opcode_in [25:21] + connect \DS_RT \opcode_in [25:21] + connect \DS_RSp \opcode_in [25:21] + connect \DS_RS \opcode_in [25:21] + connect \DS_RA \opcode_in [20:16] + connect \DS_FRTp \opcode_in [25:21] + connect \DS_FRSp \opcode_in [25:21] + connect \DS_DS \opcode_in [15:2] + connect \DQ_XO \opcode_in [2:0] + connect \DQ_TX_T { \opcode_in [3] \opcode_in [25:21] } + connect \DQ_T \opcode_in [25:21] + connect \DQ_TX \opcode_in [3] + connect \DQ_SX_S { \opcode_in [3] \opcode_in [25:21] } + connect \DQ_S \opcode_in [25:21] + connect \DQ_SX \opcode_in [3] + connect \DQ_RTp \opcode_in [25:21] + connect \DQ_RA \opcode_in [20:16] + connect \DQ_PT \opcode_in [3:0] + connect \DQ_DQ \opcode_in [15:4] + connect \DX_XO \opcode_in [5:1] + connect \DX_RT \opcode_in [25:21] + connect \DX_d0_d1_d2 { \opcode_in [15:6] \opcode_in [20:16] \opcode_in [0] } + connect \DX_d2 \opcode_in [0] + connect \DX_d1 \opcode_in [20:16] + connect \DX_d0 \opcode_in [15:6] + connect \XFX_XO \opcode_in [10:1] + connect \XFX_SPR \opcode_in [20:11] + connect \XFX_RT \opcode_in [25:21] + connect \XFX_RS \opcode_in [25:21] + connect \XFX_FXM \opcode_in [19:12] + connect \XFX_DUIS \opcode_in [20:11] + connect \XFX_DUI \opcode_in [25:21] + connect \XFX_BHRBE \opcode_in [20:11] + connect \EVS_BFA \opcode_in [2:0] + connect \Z22_XO \opcode_in [9:1] + connect \Z22_SH \opcode_in [15:10] + connect \Z22_Rc \opcode_in [0] + connect \Z22_FRTp \opcode_in [25:21] + connect \Z22_FRT \opcode_in [25:21] + connect \Z22_FRAp \opcode_in [20:16] + connect \Z22_FRA \opcode_in [20:16] + connect \Z22_DGM \opcode_in [15:10] + connect \Z22_DCM \opcode_in [15:10] + connect \Z22_BF \opcode_in [25:23] + connect \XX2_XO_1 \opcode_in [10:2] + connect \XX2_XO { \opcode_in [10:7] \opcode_in [5:3] } + connect \XX2_UIM_1 \opcode_in [17:16] + connect \XX2_UIM \opcode_in [19:16] + connect \XX2_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX2_T \opcode_in [25:21] + connect \XX2_TX \opcode_in [0] + connect \XX2_RT \opcode_in [25:21] + connect \XX2_EO \opcode_in [20:16] + connect \XX2_DCMX \opcode_in [22:16] + connect \XX2_dc_dm_dx { \opcode_in [6] \opcode_in [2] \opcode_in [20:16] } + connect \XX2_dx \opcode_in [20:16] + connect \XX2_dm \opcode_in [2] + connect \XX2_dc \opcode_in [6] + connect \XX2_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX2_B \opcode_in [15:11] + connect \XX2_BX \opcode_in [1] + connect \XX2_BF \opcode_in [25:23] + connect \D_UI \opcode_in [15:0] + connect \D_TO \opcode_in [25:21] + connect \D_SI \opcode_in [15:0] + connect \D_RT \opcode_in [25:21] + connect \D_RS \opcode_in [25:21] + connect \D_RA \opcode_in [20:16] + connect \D_L \opcode_in [21] + connect \D_FRT \opcode_in [25:21] + connect \D_FRS \opcode_in [25:21] + connect \D_D \opcode_in [15:0] + connect \D_BF \opcode_in [25:23] + connect \A_XO \opcode_in [5:1] + connect \A_RT \opcode_in [25:21] + connect \A_Rc \opcode_in [0] + connect \A_RB \opcode_in [15:11] + connect \A_RA \opcode_in [20:16] + connect \A_FRT \opcode_in [25:21] + connect \A_FRC \opcode_in [10:6] + connect \A_FRB \opcode_in [15:11] + connect \A_FRA \opcode_in [20:16] + connect \A_BC \opcode_in [10:6] + connect \XL_XO \opcode_in [10:1] + connect \XL_S \opcode_in [11] + connect \XL_OC \opcode_in [25:11] + connect \XL_LK \opcode_in [0] + connect \XL_BT \opcode_in [25:21] + connect \XL_BO_1 \opcode_in [25:21] + connect \XL_BO \opcode_in [25:21] + connect \XL_BI \opcode_in [20:16] + connect \XL_BH \opcode_in [12:11] + connect \XL_BFA \opcode_in [20:18] + connect \XL_BF \opcode_in [25:23] + connect \XL_BB \opcode_in [15:11] + connect \XL_BA \opcode_in [20:16] + connect \XX4_XO \opcode_in [5:4] + connect \XX4_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX4_T \opcode_in [25:21] + connect \XX4_TX \opcode_in [0] + connect \XX4_CX_C { \opcode_in [3] \opcode_in [10:6] } + connect \XX4_C \opcode_in [10:6] + connect \XX4_CX \opcode_in [3] + connect \XX4_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX4_B \opcode_in [15:11] + connect \XX4_BX \opcode_in [1] + connect \XX4_AX_A { \opcode_in [2] \opcode_in [20:16] } + connect \XX4_A \opcode_in [20:16] + connect \XX4_AX \opcode_in [2] + connect \XX3_XO_2 \opcode_in [9:1] + connect \XX3_XO_1 \opcode_in [10:3] + connect \XX3_XO \opcode_in [10:7] + connect \XX3_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX3_T \opcode_in [25:21] + connect \XX3_TX \opcode_in [0] + connect \XX3_SHW \opcode_in [9:8] + connect \XX3_Rc \opcode_in [10] + connect \XX3_DM \opcode_in [9:8] + connect \XX3_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX3_B \opcode_in [15:11] + connect \XX3_BX \opcode_in [1] + connect \XX3_BF \opcode_in [25:23] + connect \XX3_AX_A { \opcode_in [2] \opcode_in [20:16] } + connect \XX3_A \opcode_in [20:16] + connect \XX3_AX \opcode_in [2] + connect \I_LK \opcode_in [0] + connect \I_LI \opcode_in [25:2] + connect \I_AA \opcode_in [1] + connect \B_LK \opcode_in [0] + connect \B_BO \opcode_in [25:21] + connect \B_BI \opcode_in [20:16] + connect \B_BD \opcode_in [15:2] + connect \B_AA \opcode_in [1] + connect \X_XO_1 \opcode_in [8:1] + connect \X_XO \opcode_in [10:1] + connect \X_WC \opcode_in [22:21] + connect \X_W \opcode_in [16] + connect \X_VRT \opcode_in [25:21] + connect \X_VRS \opcode_in [25:21] + connect \X_UIM \opcode_in [20:16] + connect \X_U \opcode_in [15:12] + connect \X_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \X_TX \opcode_in [0] + connect \X_TO \opcode_in [25:21] + connect \X_TH \opcode_in [25:21] + connect \X_TBR \opcode_in [20:11] + connect \X_T \opcode_in [25:21] + connect \X_SX_S { \opcode_in [0] \opcode_in [25:21] } + connect \X_SX \opcode_in [0] + connect \X_SR \opcode_in [19:16] + connect \X_SP \opcode_in [20:19] + connect \X_SI \opcode_in [15:11] + connect \X_SH \opcode_in [15:11] + connect \X_S \opcode_in [25:21] + connect \X_RTp \opcode_in [25:21] + connect \X_RT \opcode_in [25:21] + connect \X_RSp \opcode_in [25:21] + connect \X_RS \opcode_in [25:21] + connect \X_RO \opcode_in [0] + connect \X_RM \opcode_in [12:11] + connect \X_RIC \opcode_in [19:18] + connect \X_Rc \opcode_in [0] + connect \X_RB \opcode_in [15:11] + connect \X_RA \opcode_in [20:16] + connect \X_R_1 \opcode_in [16] + connect \X_R \opcode_in [21] + connect \X_PRS \opcode_in [17] + connect \X_NB \opcode_in [15:11] + connect \X_MO \opcode_in [25:21] + connect \X_L3 \opcode_in [17:16] + connect \X_L1 \opcode_in [16] + connect \X_L \opcode_in [21] + connect \X_L2 \opcode_in [22:21] + connect \X_IMM8 \opcode_in [18:11] + connect \X_IH \opcode_in [23:21] + connect \X_FRTp \opcode_in [25:21] + connect \X_FRT \opcode_in [25:21] + connect \X_FRSp \opcode_in [25:21] + connect \X_FRS \opcode_in [25:21] + connect \X_FRBp \opcode_in [15:11] + connect \X_FRB \opcode_in [15:11] + connect \X_FRAp \opcode_in [20:16] + connect \X_FRA \opcode_in [20:16] + connect \X_FC \opcode_in [15:11] + connect \X_EX \opcode_in [0] + connect \X_EO_1 \opcode_in [20:16] + connect \X_EO \opcode_in [20:19] + connect \X_E_1 \opcode_in [19:16] + connect \X_E \opcode_in [15] + connect \X_DRM \opcode_in [13:11] + connect \X_DCMX \opcode_in [22:16] + connect \X_CT \opcode_in [24:21] + connect \X_BO \opcode_in [25:21] + connect \X_BFA \opcode_in [20:18] + connect \X_BF \opcode_in [25:23] + connect \X_A \opcode_in [25] + connect \LOGICAL_SPR \opcode_in [20:11] + connect \LOGICAL_MB \opcode_in [10:6] + connect \LOGICAL_ME \opcode_in [5:1] + connect \LOGICAL_SH \opcode_in [15:11] + connect \LOGICAL_BC \opcode_in [10:6] + connect \LOGICAL_TO \opcode_in [25:21] + connect \LOGICAL_DS \opcode_in [15:2] + connect \LOGICAL_D \opcode_in [15:0] + connect \LOGICAL_BH \opcode_in [12:11] + connect \LOGICAL_BI \opcode_in [20:16] + connect \LOGICAL_BO \opcode_in [25:21] + connect \LOGICAL_FXM \opcode_in [19:12] + connect \LOGICAL_BT \opcode_in [25:21] + connect \LOGICAL_BA \opcode_in [20:16] + connect \LOGICAL_BB \opcode_in [15:11] + connect \LOGICAL_CR \opcode_in [10:1] + connect \LOGICAL_BF \opcode_in [25:23] + connect \LOGICAL_BD \opcode_in [15:2] + connect \LOGICAL_OE \opcode_in [10] + connect \LOGICAL_Rc \opcode_in [0] + connect \LOGICAL_AA \opcode_in [1] + connect \LOGICAL_LK \opcode_in [0] + connect \LOGICAL_LI \opcode_in [25:2] + connect \LOGICAL_ME32 \opcode_in [5:1] + connect \LOGICAL_MB32 \opcode_in [10:6] + connect \LOGICAL_sh { \opcode_in [1] \opcode_in [15:11] } + connect \LOGICAL_SH32 \opcode_in [15:11] + connect \LOGICAL_L \opcode_in [21] + connect \LOGICAL_UI \opcode_in [15:0] + connect \LOGICAL_SI \opcode_in [15:0] + connect \LOGICAL_RB \opcode_in [15:11] + connect \LOGICAL_RA \opcode_in [20:16] + connect \LOGICAL_RT \opcode_in [25:21] + connect \LOGICAL_RS \opcode_in [25:21] + connect \opcode_in \$1 + connect \LOGICAL_dec31_opcode_in \opcode_in + connect \opcode_switch \opcode_in [31:26] +end +attribute \src "libresoc.v:58468.1-59800.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SPR.dec" +attribute \generator "nMigen" +module \dec$163 + attribute \src "libresoc.v:59424.3-59433.6" + wire width 3 $0\SPR_cr_in[2:0] + attribute \src "libresoc.v:59434.3-59443.6" + wire width 3 $0\SPR_cr_out[2:0] + attribute \src "libresoc.v:59404.3-59413.6" + wire width 13 $0\SPR_function_unit[12:0] + attribute \src "libresoc.v:59414.3-59423.6" + wire width 7 $0\SPR_internal_op[6:0] + attribute \src "libresoc.v:59454.3-59463.6" + wire $0\SPR_is_32b[0:0] + attribute \src "libresoc.v:59444.3-59453.6" + wire width 2 $0\SPR_rc_sel[1:0] + attribute \src "libresoc.v:58469.7-58469.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:59424.3-59433.6" + wire width 3 $1\SPR_cr_in[2:0] + attribute \src "libresoc.v:59434.3-59443.6" + wire width 3 $1\SPR_cr_out[2:0] + attribute \src "libresoc.v:59404.3-59413.6" + wire width 13 $1\SPR_function_unit[12:0] + attribute \src "libresoc.v:59414.3-59423.6" + wire width 7 $1\SPR_internal_op[6:0] + attribute \src "libresoc.v:59454.3-59463.6" + wire $1\SPR_is_32b[0:0] + attribute \src "libresoc.v:59444.3-59453.6" + wire width 2 $1\SPR_rc_sel[1:0] + attribute \src "libresoc.v:59394.17-59394.211" + wire width 32 $ternary$libresoc.v:59394$3506_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:504" + wire width 32 \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \A_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \A_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \A_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \A_FRC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \A_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \A_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \A_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \A_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \A_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \A_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \B_AA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 14 \B_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \B_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \B_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \B_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DQE_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DQE_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 2 \DQE_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 12 \DQ_DQ + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 4 \DQ_PT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DQ_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DQ_RTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DQ_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \DQ_SX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \DQ_SX_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DQ_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \DQ_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \DQ_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 3 \DQ_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 14 \DS_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DS_FRSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DS_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DS_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DS_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DS_RSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DS_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DS_VRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DS_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 2 \DS_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DX_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 10 \DX_d0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 16 \DX_d0_d1_d2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DX_d1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \DX_d2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 3 \D_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 16 \D_D + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \D_FRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \D_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \D_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \D_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \D_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \D_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 16 \D_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \D_TO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 16 \D_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 3 \EVS_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \I_AA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 24 \I_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \I_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \MDS_IB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \MDS_IS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \MDS_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \MDS_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \MDS_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \MDS_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 4 \MDS_XBI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 4 \MDS_XBI_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 4 \MDS_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \MDS_mb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \MDS_me + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \MD_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \MD_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \MD_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 3 \MD_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \MD_mb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \MD_me + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \MD_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \M_MB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \M_ME + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \M_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \M_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \M_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \M_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \M_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 7 \SC_LEV + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \SC_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 2 \SC_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire \SPR_AA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 output 13 \SPR_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 output 12 \SPR_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 output 17 \SPR_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 14 \SPR_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 3 \SPR_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 2 \SPR_BH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 output 16 \SPR_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \SPR_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 output 14 \SPR_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 10 \SPR_CR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 16 \SPR_D + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 14 \SPR_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 8 output 15 \SPR_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire \SPR_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 24 \SPR_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire \SPR_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \SPR_MB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \SPR_MB32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \SPR_ME + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \SPR_ME32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire output 11 \SPR_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \SPR_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \SPR_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \SPR_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \SPR_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire output 10 \SPR_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \SPR_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \SPR_SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 16 \SPR_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 10 output 7 \SPR_SPR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \SPR_TO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 16 \SPR_UI + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 4 \SPR_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 5 \SPR_cr_out + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \SPR_dec31_SPR_dec31_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \SPR_dec31_SPR_dec31_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 13 \SPR_dec31_SPR_dec31_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 \SPR_dec31_SPR_dec31_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \SPR_dec31_SPR_dec31_is_32b + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \SPR_dec31_SPR_dec31_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + wire width 32 \SPR_dec31_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 13 output 8 \SPR_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 output 6 \SPR_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 9 \SPR_is_32b + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + 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wire width 6 \X_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 4 \X_U + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_UIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_VRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \X_W + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 2 \X_WC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 10 \X_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 8 \X_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 3 \Z22_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \Z22_DCM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \Z22_DGM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \Z22_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \Z22_FRAp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \Z22_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \Z22_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \Z22_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \Z22_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 9 \Z22_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \Z23_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \Z23_FRAp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \Z23_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \Z23_FRBp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \Z23_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \Z23_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \Z23_R + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 2 \Z23_RMC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \Z23_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \Z23_TE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 8 \Z23_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \all_OPCD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \all_PO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" + wire input 1 \bigendian + attribute \src "libresoc.v:58469.7-58469.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + wire width 32 output 2 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + wire width 6 \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 32 input 21 \raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:504" + cell $mux $ternary$libresoc.v:59394$3506 + parameter \WIDTH 32 + connect \A \raw_opcode_in + connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } + connect \S \bigendian + connect \Y $ternary$libresoc.v:59394$3506_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:59395.13-59403.4" + cell \SPR_dec31 \SPR_dec31 + connect \SPR_dec31_cr_in \SPR_dec31_SPR_dec31_cr_in + connect \SPR_dec31_cr_out \SPR_dec31_SPR_dec31_cr_out + connect \SPR_dec31_function_unit \SPR_dec31_SPR_dec31_function_unit + connect \SPR_dec31_internal_op \SPR_dec31_SPR_dec31_internal_op + connect \SPR_dec31_is_32b \SPR_dec31_SPR_dec31_is_32b + connect \SPR_dec31_rc_sel \SPR_dec31_SPR_dec31_rc_sel + connect \opcode_in \SPR_dec31_opcode_in + end + attribute \src "libresoc.v:58469.7-58469.20" + process $proc$libresoc.v:58469$3513 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:59404.3-59413.6" + process $proc$libresoc.v:59404$3507 + assign { } { } + assign { } { } + assign $0\SPR_function_unit[12:0] $1\SPR_function_unit[12:0] + attribute \src "libresoc.v:59405.5-59405.29" + switch \initial + attribute \src "libresoc.v:59405.9-59405.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\SPR_function_unit[12:0] \SPR_dec31_SPR_dec31_function_unit + case + assign $1\SPR_function_unit[12:0] 13'0000000000000 + end + sync always + update \SPR_function_unit $0\SPR_function_unit[12:0] + end + attribute \src "libresoc.v:59414.3-59423.6" + process $proc$libresoc.v:59414$3508 + assign { } { } + assign { } { } + assign $0\SPR_internal_op[6:0] $1\SPR_internal_op[6:0] + attribute \src "libresoc.v:59415.5-59415.29" + switch \initial + attribute \src "libresoc.v:59415.9-59415.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\SPR_internal_op[6:0] \SPR_dec31_SPR_dec31_internal_op + case + assign $1\SPR_internal_op[6:0] 7'0000000 + end + sync always + update \SPR_internal_op $0\SPR_internal_op[6:0] + end + attribute \src "libresoc.v:59424.3-59433.6" + process $proc$libresoc.v:59424$3509 + assign { } { } + assign { } { } + assign $0\SPR_cr_in[2:0] $1\SPR_cr_in[2:0] + attribute \src "libresoc.v:59425.5-59425.29" + switch \initial + attribute \src "libresoc.v:59425.9-59425.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\SPR_cr_in[2:0] \SPR_dec31_SPR_dec31_cr_in + case + assign $1\SPR_cr_in[2:0] 3'000 + end + sync always + update \SPR_cr_in $0\SPR_cr_in[2:0] + end + attribute \src "libresoc.v:59434.3-59443.6" + process $proc$libresoc.v:59434$3510 + assign { } { } + assign { } { } + assign $0\SPR_cr_out[2:0] $1\SPR_cr_out[2:0] + attribute \src "libresoc.v:59435.5-59435.29" + switch \initial + attribute \src "libresoc.v:59435.9-59435.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\SPR_cr_out[2:0] \SPR_dec31_SPR_dec31_cr_out + case + assign $1\SPR_cr_out[2:0] 3'000 + end + sync always + update \SPR_cr_out $0\SPR_cr_out[2:0] + end + attribute \src "libresoc.v:59444.3-59453.6" + process $proc$libresoc.v:59444$3511 + assign { } { } + assign { } { } + assign $0\SPR_rc_sel[1:0] $1\SPR_rc_sel[1:0] + attribute \src "libresoc.v:59445.5-59445.29" + switch \initial + attribute \src "libresoc.v:59445.9-59445.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\SPR_rc_sel[1:0] \SPR_dec31_SPR_dec31_rc_sel + case + assign $1\SPR_rc_sel[1:0] 2'00 + end + sync always + update \SPR_rc_sel $0\SPR_rc_sel[1:0] + end + attribute \src "libresoc.v:59454.3-59463.6" + process $proc$libresoc.v:59454$3512 + assign { } { } + assign { } { } + assign $0\SPR_is_32b[0:0] $1\SPR_is_32b[0:0] + attribute \src "libresoc.v:59455.5-59455.29" + switch \initial + attribute \src "libresoc.v:59455.9-59455.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\SPR_is_32b[0:0] \SPR_dec31_SPR_dec31_is_32b + case + assign $1\SPR_is_32b[0:0] 1'0 + end + sync always + update \SPR_is_32b $0\SPR_is_32b[0:0] + end + connect \$1 $ternary$libresoc.v:59394$3506_Y + connect \VC_XO \opcode_in [9:0] + connect \VC_VRT \opcode_in [25:21] + connect \VC_VRB \opcode_in [15:11] + connect \VC_VRA \opcode_in [20:16] + connect \VC_Rc \opcode_in [10] + connect \XS_XO \opcode_in [10:2] + connect \XS_sh { \opcode_in [1] \opcode_in [15:11] } + connect \XS_RS \opcode_in [25:21] + connect \XS_Rc \opcode_in [0] + connect \XS_RA \opcode_in [20:16] + connect \VA_XO \opcode_in [5:0] + connect \VA_VRT \opcode_in [25:21] + connect \VA_VRC \opcode_in [10:6] + connect \VA_VRB \opcode_in [15:11] + connect \VA_VRA \opcode_in [20:16] + connect \VA_SHB \opcode_in [9:6] + connect \VA_RT \opcode_in [25:21] + connect \VA_RC \opcode_in [10:6] + connect \VA_RB \opcode_in [15:11] + connect \VA_RA \opcode_in [20:16] + connect \TX_XO \opcode_in [6:1] + connect \TX_XBI \opcode_in [10:7] + connect \TX_UI \opcode_in [15:11] + connect \TX_RA \opcode_in [20:16] + connect \DQE_XO \opcode_in [1:0] + connect \DQE_RT \opcode_in [25:21] + connect \DQE_RA \opcode_in [20:16] + connect \XO_XO \opcode_in [9:1] + connect \XO_RT \opcode_in [25:21] + connect \XO_Rc \opcode_in [0] + connect \XO_RB \opcode_in [15:11] + connect \XO_RA \opcode_in [20:16] + connect \XO_OE \opcode_in [10] + connect \all_PO \opcode_in [31:26] + connect \all_OPCD \opcode_in [31:26] + connect \SVL_XO \opcode_in [5:1] + connect \SVL_vs \opcode_in [7] + connect \SVL_SVi \opcode_in [15:10] + connect \SVL_RT \opcode_in [25:21] + connect \SVL_Rc \opcode_in [0] + connect \SVL_RA \opcode_in [20:16] + connect \SVL_ms \opcode_in [6] + connect \MD_XO \opcode_in [4:2] + connect \MD_sh { \opcode_in [1] \opcode_in [15:11] } + connect \MD_RS \opcode_in [25:21] + connect \MD_Rc \opcode_in [0] + connect \MD_RA \opcode_in [20:16] + connect \MD_me \opcode_in [10:5] + connect \MD_mb \opcode_in [10:5] + connect \M_SH \opcode_in [15:11] + connect \M_RS \opcode_in [25:21] + connect \M_Rc \opcode_in [0] + connect \M_RB \opcode_in [15:11] + connect \M_RA \opcode_in [20:16] + connect \M_ME \opcode_in [5:1] + connect \M_MB \opcode_in [10:6] + connect \SC_XO_1 \opcode_in [1:0] + connect \SC_XO \opcode_in [1] + connect \SC_LEV \opcode_in [11:5] + connect \MDS_XO \opcode_in [4:1] + connect \MDS_XBI_1 \opcode_in [10:7] + connect \MDS_XBI \opcode_in [10:7] + connect \MDS_RS \opcode_in [25:21] + connect \MDS_Rc \opcode_in [0] + connect \MDS_RB \opcode_in [15:11] + connect \MDS_RA \opcode_in [20:16] + connect \MDS_me \opcode_in [10:5] + connect \MDS_mb \opcode_in [10:5] + connect \MDS_IS \opcode_in [25:21] + connect \MDS_IB \opcode_in [15:11] + connect \Z23_XO \opcode_in [8:1] + connect \Z23_TE \opcode_in [20:16] + connect \Z23_RMC \opcode_in [10:9] + connect \Z23_Rc \opcode_in [0] + connect \Z23_R \opcode_in [16] + connect \Z23_FRTp \opcode_in [25:21] + connect \Z23_FRT \opcode_in [25:21] + connect \Z23_FRBp \opcode_in [15:11] + connect \Z23_FRB \opcode_in [15:11] + connect \Z23_FRAp \opcode_in [20:16] + connect \Z23_FRA \opcode_in [20:16] + connect \XFL_XO \opcode_in [10:1] + connect \XFL_W \opcode_in [16] + connect \XFL_Rc \opcode_in [0] + connect \XFL_L \opcode_in [25] + connect \XFL_FRB \opcode_in [15:11] + connect \XFL_FLM \opcode_in [24:17] + connect \VX_XO_1 \opcode_in [10:0] + connect \VX_XO { \opcode_in [10] \opcode_in [8:0] } + connect \VX_VRT \opcode_in [25:21] + connect \VX_VRB \opcode_in [15:11] + connect \VX_VRA \opcode_in [20:16] + connect \VX_UIM_3 \opcode_in [17:16] + connect \VX_UIM_2 \opcode_in [18:16] + connect \VX_UIM_1 \opcode_in [19:16] + connect \VX_UIM \opcode_in [20:16] + connect \VX_SIM \opcode_in [20:16] + connect \VX_RT \opcode_in [25:21] + connect \VX_RA \opcode_in [20:16] + connect \VX_PS \opcode_in [9] + connect \VX_EO \opcode_in [20:16] + connect \DS_XO \opcode_in [1:0] + connect \DS_VRT \opcode_in [25:21] + connect \DS_VRS \opcode_in [25:21] + connect \DS_RT \opcode_in [25:21] + connect \DS_RSp \opcode_in [25:21] + connect \DS_RS \opcode_in [25:21] + connect \DS_RA \opcode_in [20:16] + connect \DS_FRTp \opcode_in [25:21] + connect \DS_FRSp \opcode_in [25:21] + connect \DS_DS \opcode_in [15:2] + connect \DQ_XO \opcode_in [2:0] + connect \DQ_TX_T { \opcode_in [3] \opcode_in [25:21] } + connect \DQ_T \opcode_in [25:21] + connect \DQ_TX \opcode_in [3] + connect \DQ_SX_S { \opcode_in [3] \opcode_in [25:21] } + connect \DQ_S \opcode_in [25:21] + connect \DQ_SX \opcode_in [3] + connect \DQ_RTp \opcode_in [25:21] + connect \DQ_RA \opcode_in [20:16] + connect \DQ_PT \opcode_in [3:0] + connect \DQ_DQ \opcode_in [15:4] + connect \DX_XO \opcode_in [5:1] + connect \DX_RT \opcode_in [25:21] + connect \DX_d0_d1_d2 { \opcode_in [15:6] \opcode_in [20:16] \opcode_in [0] } + connect \DX_d2 \opcode_in [0] + connect \DX_d1 \opcode_in [20:16] + connect \DX_d0 \opcode_in [15:6] + connect \XFX_XO \opcode_in [10:1] + connect \XFX_SPR \opcode_in [20:11] + connect \XFX_RT \opcode_in [25:21] + connect \XFX_RS \opcode_in [25:21] + connect \XFX_FXM \opcode_in [19:12] + connect \XFX_DUIS \opcode_in [20:11] + connect \XFX_DUI \opcode_in [25:21] + connect \XFX_BHRBE \opcode_in [20:11] + connect \EVS_BFA \opcode_in [2:0] + connect \Z22_XO \opcode_in [9:1] + connect \Z22_SH \opcode_in [15:10] + connect \Z22_Rc \opcode_in [0] + connect \Z22_FRTp \opcode_in [25:21] + connect \Z22_FRT \opcode_in [25:21] + connect \Z22_FRAp \opcode_in [20:16] + connect \Z22_FRA \opcode_in [20:16] + connect \Z22_DGM \opcode_in [15:10] + connect \Z22_DCM \opcode_in [15:10] + connect \Z22_BF \opcode_in [25:23] + connect \XX2_XO_1 \opcode_in [10:2] + connect \XX2_XO { \opcode_in [10:7] \opcode_in [5:3] } + connect \XX2_UIM_1 \opcode_in [17:16] + connect \XX2_UIM \opcode_in [19:16] + connect \XX2_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX2_T \opcode_in [25:21] + connect \XX2_TX \opcode_in [0] + connect \XX2_RT \opcode_in [25:21] + connect \XX2_EO \opcode_in [20:16] + connect \XX2_DCMX \opcode_in [22:16] + connect \XX2_dc_dm_dx { \opcode_in [6] \opcode_in [2] \opcode_in [20:16] } + connect \XX2_dx \opcode_in [20:16] + connect \XX2_dm \opcode_in [2] + connect \XX2_dc \opcode_in [6] + connect \XX2_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX2_B \opcode_in [15:11] + connect \XX2_BX \opcode_in [1] + connect \XX2_BF \opcode_in [25:23] + connect \D_UI \opcode_in [15:0] + connect \D_TO \opcode_in [25:21] + connect \D_SI \opcode_in [15:0] + connect \D_RT \opcode_in [25:21] + connect \D_RS \opcode_in [25:21] + connect \D_RA \opcode_in [20:16] + connect \D_L \opcode_in [21] + connect \D_FRT \opcode_in [25:21] + connect \D_FRS \opcode_in [25:21] + connect \D_D \opcode_in [15:0] + connect \D_BF \opcode_in [25:23] + connect \A_XO \opcode_in [5:1] + connect \A_RT \opcode_in [25:21] + connect \A_Rc \opcode_in [0] + connect \A_RB \opcode_in [15:11] + connect \A_RA \opcode_in [20:16] + connect \A_FRT \opcode_in [25:21] + connect \A_FRC \opcode_in [10:6] + connect \A_FRB \opcode_in [15:11] + connect \A_FRA \opcode_in [20:16] + connect \A_BC \opcode_in [10:6] + connect \XL_XO \opcode_in [10:1] + connect \XL_S \opcode_in [11] + connect \XL_OC \opcode_in [25:11] + connect \XL_LK \opcode_in [0] + connect \XL_BT \opcode_in [25:21] + connect \XL_BO_1 \opcode_in [25:21] + connect \XL_BO \opcode_in [25:21] + connect \XL_BI \opcode_in [20:16] + connect \XL_BH \opcode_in [12:11] + connect \XL_BFA \opcode_in [20:18] + connect \XL_BF \opcode_in [25:23] + connect \XL_BB \opcode_in [15:11] + connect \XL_BA \opcode_in [20:16] + connect \XX4_XO \opcode_in [5:4] + connect \XX4_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX4_T \opcode_in [25:21] + connect \XX4_TX \opcode_in [0] + connect \XX4_CX_C { \opcode_in [3] \opcode_in [10:6] } + connect \XX4_C \opcode_in [10:6] + connect \XX4_CX \opcode_in [3] + connect \XX4_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX4_B \opcode_in [15:11] + connect \XX4_BX \opcode_in [1] + connect \XX4_AX_A { \opcode_in [2] \opcode_in [20:16] } + connect \XX4_A \opcode_in [20:16] + connect \XX4_AX \opcode_in [2] + connect \XX3_XO_2 \opcode_in [9:1] + connect \XX3_XO_1 \opcode_in [10:3] + connect \XX3_XO \opcode_in [10:7] + connect \XX3_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX3_T \opcode_in [25:21] + connect \XX3_TX \opcode_in [0] + connect \XX3_SHW \opcode_in [9:8] + connect \XX3_Rc \opcode_in [10] + connect \XX3_DM \opcode_in [9:8] + connect \XX3_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX3_B \opcode_in [15:11] + connect \XX3_BX \opcode_in [1] + connect \XX3_BF \opcode_in [25:23] + connect \XX3_AX_A { \opcode_in [2] \opcode_in [20:16] } + connect \XX3_A \opcode_in [20:16] + connect \XX3_AX \opcode_in [2] + connect \I_LK \opcode_in [0] + connect \I_LI \opcode_in [25:2] + connect \I_AA \opcode_in [1] + connect \B_LK \opcode_in [0] + connect \B_BO \opcode_in [25:21] + connect \B_BI \opcode_in [20:16] + connect \B_BD \opcode_in [15:2] + connect \B_AA \opcode_in [1] + connect \X_XO_1 \opcode_in [8:1] + connect \X_XO \opcode_in [10:1] + connect \X_WC \opcode_in [22:21] + connect \X_W \opcode_in [16] + connect \X_VRT \opcode_in [25:21] + connect \X_VRS \opcode_in [25:21] + connect \X_UIM \opcode_in [20:16] + connect \X_U \opcode_in [15:12] + connect \X_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \X_TX \opcode_in [0] + connect \X_TO \opcode_in [25:21] + connect \X_TH \opcode_in [25:21] + connect \X_TBR \opcode_in [20:11] + connect \X_T \opcode_in [25:21] + connect \X_SX_S { \opcode_in [0] \opcode_in [25:21] } + connect \X_SX \opcode_in [0] + connect \X_SR \opcode_in [19:16] + connect \X_SP \opcode_in [20:19] + connect \X_SI \opcode_in [15:11] + connect \X_SH \opcode_in [15:11] + connect \X_S \opcode_in [25:21] + connect \X_RTp \opcode_in [25:21] + connect \X_RT \opcode_in [25:21] + connect \X_RSp \opcode_in [25:21] + connect \X_RS \opcode_in [25:21] + connect \X_RO \opcode_in [0] + connect \X_RM \opcode_in [12:11] + connect \X_RIC \opcode_in [19:18] + connect \X_Rc \opcode_in [0] + connect \X_RB \opcode_in [15:11] + connect \X_RA \opcode_in [20:16] + connect \X_R_1 \opcode_in [16] + connect \X_R \opcode_in [21] + connect \X_PRS \opcode_in [17] + connect \X_NB \opcode_in [15:11] + connect \X_MO \opcode_in [25:21] + connect \X_L3 \opcode_in [17:16] + connect \X_L1 \opcode_in [16] + connect \X_L \opcode_in [21] + connect \X_L2 \opcode_in [22:21] + connect \X_IMM8 \opcode_in [18:11] + connect \X_IH \opcode_in [23:21] + connect \X_FRTp \opcode_in [25:21] + connect \X_FRT \opcode_in [25:21] + connect \X_FRSp \opcode_in [25:21] + connect \X_FRS \opcode_in [25:21] + connect \X_FRBp \opcode_in [15:11] + connect \X_FRB \opcode_in [15:11] + connect \X_FRAp \opcode_in [20:16] + connect \X_FRA \opcode_in [20:16] + connect \X_FC \opcode_in [15:11] + connect \X_EX \opcode_in [0] + connect \X_EO_1 \opcode_in [20:16] + connect \X_EO \opcode_in [20:19] + connect \X_E_1 \opcode_in [19:16] + connect \X_E \opcode_in [15] + connect \X_DRM \opcode_in [13:11] + connect \X_DCMX \opcode_in [22:16] + connect \X_CT \opcode_in [24:21] + connect \X_BO \opcode_in [25:21] + connect \X_BFA \opcode_in [20:18] + connect \X_BF \opcode_in [25:23] + connect \X_A \opcode_in [25] + connect \SPR_SPR \opcode_in [20:11] + connect \SPR_MB \opcode_in [10:6] + connect \SPR_ME \opcode_in [5:1] + connect \SPR_SH \opcode_in [15:11] + connect \SPR_BC \opcode_in [10:6] + connect \SPR_TO \opcode_in [25:21] + connect \SPR_DS \opcode_in [15:2] + connect \SPR_D \opcode_in [15:0] + connect \SPR_BH \opcode_in [12:11] + connect \SPR_BI \opcode_in [20:16] + connect \SPR_BO \opcode_in [25:21] + connect \SPR_FXM \opcode_in [19:12] + connect \SPR_BT \opcode_in [25:21] + connect \SPR_BA \opcode_in [20:16] + connect \SPR_BB \opcode_in [15:11] + connect \SPR_CR \opcode_in [10:1] + connect \SPR_BF \opcode_in [25:23] + connect \SPR_BD \opcode_in [15:2] + connect \SPR_OE \opcode_in [10] + connect \SPR_Rc \opcode_in [0] + connect \SPR_AA \opcode_in [1] + connect \SPR_LK \opcode_in [0] + connect \SPR_LI \opcode_in [25:2] + connect \SPR_ME32 \opcode_in [5:1] + connect \SPR_MB32 \opcode_in [10:6] + connect \SPR_sh { \opcode_in [1] \opcode_in [15:11] } + connect \SPR_SH32 \opcode_in [15:11] + connect \SPR_L \opcode_in [21] + connect \SPR_UI \opcode_in [15:0] + connect \SPR_SI \opcode_in [15:0] + connect \SPR_RB \opcode_in [15:11] + connect \SPR_RA \opcode_in [20:16] + connect \SPR_RT \opcode_in [25:21] + connect \SPR_RS \opcode_in [25:21] + connect \opcode_in \$1 + connect \SPR_dec31_opcode_in \opcode_in + connect \opcode_switch \opcode_in [31:26] +end +attribute \src "libresoc.v:59804.1-61326.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_DIV.dec" +attribute \generator "nMigen" +module \dec$170 + attribute \src "libresoc.v:60950.3-60959.6" + wire width 3 $0\DIV_cr_in[2:0] + attribute \src "libresoc.v:60960.3-60969.6" + wire width 3 $0\DIV_cr_out[2:0] + attribute \src "libresoc.v:60850.3-60859.6" + wire width 2 $0\DIV_cry_in[1:0] + attribute \src "libresoc.v:60880.3-60889.6" + wire $0\DIV_cry_out[0:0] + attribute \src "libresoc.v:60910.3-60919.6" + wire width 13 $0\DIV_function_unit[12:0] + attribute \src "libresoc.v:60930.3-60939.6" + wire width 3 $0\DIV_in1_sel[2:0] + attribute \src "libresoc.v:60940.3-60949.6" + wire width 4 $0\DIV_in2_sel[3:0] + attribute \src "libresoc.v:60920.3-60929.6" + wire width 7 $0\DIV_internal_op[6:0] + attribute \src "libresoc.v:60860.3-60869.6" + wire $0\DIV_inv_a[0:0] + attribute \src "libresoc.v:60870.3-60879.6" + wire $0\DIV_inv_out[0:0] + attribute \src "libresoc.v:60890.3-60899.6" + wire $0\DIV_is_32b[0:0] + attribute \src "libresoc.v:60970.3-60979.6" + wire width 4 $0\DIV_ldst_len[3:0] + attribute \src "libresoc.v:60980.3-60989.6" + wire width 2 $0\DIV_rc_sel[1:0] + attribute \src "libresoc.v:60900.3-60909.6" + wire $0\DIV_sgn[0:0] + attribute \src "libresoc.v:59805.7-59805.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:60950.3-60959.6" + wire width 3 $1\DIV_cr_in[2:0] + attribute \src "libresoc.v:60960.3-60969.6" + wire width 3 $1\DIV_cr_out[2:0] + attribute \src "libresoc.v:60850.3-60859.6" + wire width 2 $1\DIV_cry_in[1:0] + attribute \src "libresoc.v:60880.3-60889.6" + wire $1\DIV_cry_out[0:0] + attribute \src "libresoc.v:60910.3-60919.6" + wire width 13 $1\DIV_function_unit[12:0] + attribute \src "libresoc.v:60930.3-60939.6" + wire width 3 $1\DIV_in1_sel[2:0] + attribute \src "libresoc.v:60940.3-60949.6" + wire width 4 $1\DIV_in2_sel[3:0] + attribute \src "libresoc.v:60920.3-60929.6" + wire width 7 $1\DIV_internal_op[6:0] + attribute \src "libresoc.v:60860.3-60869.6" + wire $1\DIV_inv_a[0:0] + attribute \src "libresoc.v:60870.3-60879.6" + wire $1\DIV_inv_out[0:0] + attribute \src "libresoc.v:60890.3-60899.6" + wire $1\DIV_is_32b[0:0] + attribute \src "libresoc.v:60970.3-60979.6" + wire width 4 $1\DIV_ldst_len[3:0] + attribute \src "libresoc.v:60980.3-60989.6" + wire width 2 $1\DIV_rc_sel[1:0] + attribute \src "libresoc.v:60900.3-60909.6" + wire $1\DIV_sgn[0:0] + attribute \src "libresoc.v:60832.17-60832.211" + wire width 32 $ternary$libresoc.v:60832$3514_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:504" + wire width 32 \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \A_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \A_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \A_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \A_FRC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \A_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \A_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \A_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \A_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \A_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \A_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \B_AA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 14 \B_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \B_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \B_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \B_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire \DIV_AA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 output 28 \DIV_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 output 27 \DIV_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 output 33 \DIV_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 14 output 26 \DIV_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 3 \DIV_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 2 \DIV_BH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 output 31 \DIV_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \DIV_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 output 29 \DIV_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 10 \DIV_CR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 16 \DIV_D + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 14 output 32 \DIV_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 8 output 30 \DIV_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire \DIV_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 24 output 23 \DIV_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire \DIV_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \DIV_MB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \DIV_MB32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \DIV_ME + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \DIV_ME32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire output 25 \DIV_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 output 18 \DIV_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \DIV_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \DIV_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \DIV_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire output 24 \DIV_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \DIV_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 output 21 \DIV_SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 16 output 19 \DIV_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 10 output 7 \DIV_SPR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \DIV_TO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 16 output 20 \DIV_UI + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 4 \DIV_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 5 \DIV_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 14 \DIV_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 15 \DIV_cry_out + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \DIV_dec31_DIV_dec31_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \DIV_dec31_DIV_dec31_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \DIV_dec31_DIV_dec31_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \DIV_dec31_DIV_dec31_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 13 \DIV_dec31_DIV_dec31_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \DIV_dec31_DIV_dec31_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 \DIV_dec31_DIV_dec31_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 \DIV_dec31_DIV_dec31_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \DIV_dec31_DIV_dec31_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \DIV_dec31_DIV_dec31_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \DIV_dec31_DIV_dec31_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 \DIV_dec31_DIV_dec31_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \DIV_dec31_DIV_dec31_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \DIV_dec31_DIV_dec31_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + wire width 32 \DIV_dec31_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 13 output 8 \DIV_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 9 \DIV_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 10 \DIV_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 output 6 \DIV_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 12 \DIV_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 13 \DIV_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 16 \DIV_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 11 \DIV_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 3 \DIV_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 17 \DIV_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 6 output 22 \DIV_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DQE_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DQE_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 2 \DQE_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 12 \DQ_DQ + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 4 \DQ_PT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DQ_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DQ_RTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DQ_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \DQ_SX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \DQ_SX_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DQ_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \DQ_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \DQ_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 3 \DQ_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 14 \DS_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DS_FRSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DS_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DS_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DS_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DS_RSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DS_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DS_VRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DS_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 2 \DS_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DX_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 10 \DX_d0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 16 \DX_d0_d1_d2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DX_d1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \DX_d2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 3 \D_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 16 \D_D + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \D_FRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \D_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \D_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \D_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \D_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \D_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 16 \D_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \D_TO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 16 \D_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 3 \EVS_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \I_AA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 24 \I_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \I_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \MDS_IB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \MDS_IS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \MDS_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \MDS_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \MDS_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \MDS_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 4 \MDS_XBI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 4 \MDS_XBI_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 4 \MDS_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \MDS_mb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \MDS_me + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \MD_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \MD_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \MD_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 3 \MD_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \MD_mb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \MD_me + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \MD_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \M_MB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \M_ME + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \M_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \M_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \M_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \M_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \M_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 7 \SC_LEV + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \SC_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 2 \SC_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \SVL_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \SVL_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \SVL_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \SVL_SVi + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \SVL_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \SVL_ms + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \SVL_vs + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \TX_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \TX_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 4 \TX_XBI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \TX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \VA_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \VA_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \VA_RC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \VA_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 4 \VA_SHB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \VA_VRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \VA_VRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \VA_VRC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \VA_VRT + attribute \src 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wire width 5 \XS_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \XS_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 9 \XS_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \XS_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \XX2_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 3 \XX2_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \XX2_BX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \XX2_BX_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 7 \XX2_DCMX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \XX2_EO + attribute \src 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_TH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_TO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \X_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \X_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 4 \X_U + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_UIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_VRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \X_W + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 2 \X_WC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 10 \X_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 8 \X_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 3 \Z22_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \Z22_DCM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \Z22_DGM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \Z22_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \Z22_FRAp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \Z22_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \Z22_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \Z22_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \Z22_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 9 \Z22_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \Z23_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \Z23_FRAp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \Z23_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \Z23_FRBp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \Z23_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \Z23_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \Z23_R + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 2 \Z23_RMC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \Z23_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \Z23_TE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 8 \Z23_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \all_OPCD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \all_PO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" + wire input 1 \bigendian + attribute \src "libresoc.v:59805.7-59805.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + wire width 32 output 2 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + wire width 6 \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 32 input 37 \raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:504" + cell $mux $ternary$libresoc.v:60832$3514 + parameter \WIDTH 32 + connect \A \raw_opcode_in + connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } + connect \S \bigendian + connect \Y $ternary$libresoc.v:60832$3514_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:60833.13-60849.4" + cell \DIV_dec31 \DIV_dec31 + connect \DIV_dec31_cr_in \DIV_dec31_DIV_dec31_cr_in + connect \DIV_dec31_cr_out \DIV_dec31_DIV_dec31_cr_out + connect \DIV_dec31_cry_in \DIV_dec31_DIV_dec31_cry_in + connect \DIV_dec31_cry_out \DIV_dec31_DIV_dec31_cry_out + connect \DIV_dec31_function_unit \DIV_dec31_DIV_dec31_function_unit + connect \DIV_dec31_in1_sel \DIV_dec31_DIV_dec31_in1_sel + connect \DIV_dec31_in2_sel \DIV_dec31_DIV_dec31_in2_sel + connect \DIV_dec31_internal_op \DIV_dec31_DIV_dec31_internal_op + connect \DIV_dec31_inv_a \DIV_dec31_DIV_dec31_inv_a + connect \DIV_dec31_inv_out \DIV_dec31_DIV_dec31_inv_out + connect \DIV_dec31_is_32b \DIV_dec31_DIV_dec31_is_32b + connect \DIV_dec31_ldst_len \DIV_dec31_DIV_dec31_ldst_len + connect \DIV_dec31_rc_sel \DIV_dec31_DIV_dec31_rc_sel + connect \DIV_dec31_sgn \DIV_dec31_DIV_dec31_sgn + connect \opcode_in \DIV_dec31_opcode_in + end + attribute \src "libresoc.v:59805.7-59805.20" + process $proc$libresoc.v:59805$3529 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:60850.3-60859.6" + process $proc$libresoc.v:60850$3515 + assign { } { } + assign { } { } + assign $0\DIV_cry_in[1:0] $1\DIV_cry_in[1:0] + attribute \src "libresoc.v:60851.5-60851.29" + switch \initial + attribute \src "libresoc.v:60851.9-60851.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\DIV_cry_in[1:0] \DIV_dec31_DIV_dec31_cry_in + case + assign $1\DIV_cry_in[1:0] 2'00 + end + sync always + update \DIV_cry_in $0\DIV_cry_in[1:0] + end + attribute \src "libresoc.v:60860.3-60869.6" + process $proc$libresoc.v:60860$3516 + assign { } { } + assign { } { } + assign $0\DIV_inv_a[0:0] $1\DIV_inv_a[0:0] + attribute \src "libresoc.v:60861.5-60861.29" + switch \initial + attribute \src "libresoc.v:60861.9-60861.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\DIV_inv_a[0:0] \DIV_dec31_DIV_dec31_inv_a + case + assign $1\DIV_inv_a[0:0] 1'0 + end + sync always + update \DIV_inv_a $0\DIV_inv_a[0:0] + end + attribute \src "libresoc.v:60870.3-60879.6" + process $proc$libresoc.v:60870$3517 + assign { } { } + assign { } { } + assign $0\DIV_inv_out[0:0] $1\DIV_inv_out[0:0] + attribute \src "libresoc.v:60871.5-60871.29" + switch \initial + attribute \src "libresoc.v:60871.9-60871.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\DIV_inv_out[0:0] \DIV_dec31_DIV_dec31_inv_out + case + assign $1\DIV_inv_out[0:0] 1'0 + end + sync always + update \DIV_inv_out $0\DIV_inv_out[0:0] + end + attribute \src "libresoc.v:60880.3-60889.6" + process $proc$libresoc.v:60880$3518 + assign { } { } + assign { } { } + assign $0\DIV_cry_out[0:0] $1\DIV_cry_out[0:0] + attribute \src "libresoc.v:60881.5-60881.29" + switch \initial + attribute \src "libresoc.v:60881.9-60881.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\DIV_cry_out[0:0] \DIV_dec31_DIV_dec31_cry_out + case + assign $1\DIV_cry_out[0:0] 1'0 + end + sync always + update \DIV_cry_out $0\DIV_cry_out[0:0] + end + attribute \src "libresoc.v:60890.3-60899.6" + process $proc$libresoc.v:60890$3519 + assign { } { } + assign { } { } + assign $0\DIV_is_32b[0:0] $1\DIV_is_32b[0:0] + attribute \src "libresoc.v:60891.5-60891.29" + switch \initial + attribute \src "libresoc.v:60891.9-60891.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\DIV_is_32b[0:0] \DIV_dec31_DIV_dec31_is_32b + case + assign $1\DIV_is_32b[0:0] 1'0 + end + sync always + update \DIV_is_32b $0\DIV_is_32b[0:0] + end + attribute \src "libresoc.v:60900.3-60909.6" + process $proc$libresoc.v:60900$3520 + assign { } { } + assign { } { } + assign $0\DIV_sgn[0:0] $1\DIV_sgn[0:0] + attribute \src "libresoc.v:60901.5-60901.29" + switch \initial + attribute \src "libresoc.v:60901.9-60901.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\DIV_sgn[0:0] \DIV_dec31_DIV_dec31_sgn + case + assign $1\DIV_sgn[0:0] 1'0 + end + sync always + update \DIV_sgn $0\DIV_sgn[0:0] + end + attribute \src "libresoc.v:60910.3-60919.6" + process $proc$libresoc.v:60910$3521 + assign { } { } + assign { } { } + assign $0\DIV_function_unit[12:0] $1\DIV_function_unit[12:0] + attribute \src "libresoc.v:60911.5-60911.29" + switch \initial + attribute \src "libresoc.v:60911.9-60911.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\DIV_function_unit[12:0] \DIV_dec31_DIV_dec31_function_unit + case + assign $1\DIV_function_unit[12:0] 13'0000000000000 + end + sync always + update \DIV_function_unit $0\DIV_function_unit[12:0] + end + attribute \src "libresoc.v:60920.3-60929.6" + process $proc$libresoc.v:60920$3522 + assign { } { } + assign { } { } + assign $0\DIV_internal_op[6:0] $1\DIV_internal_op[6:0] + attribute \src "libresoc.v:60921.5-60921.29" + switch \initial + attribute \src "libresoc.v:60921.9-60921.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\DIV_internal_op[6:0] \DIV_dec31_DIV_dec31_internal_op + case + assign $1\DIV_internal_op[6:0] 7'0000000 + end + sync always + update \DIV_internal_op $0\DIV_internal_op[6:0] + end + attribute \src "libresoc.v:60930.3-60939.6" + process $proc$libresoc.v:60930$3523 + assign { } { } + assign { } { } + assign $0\DIV_in1_sel[2:0] $1\DIV_in1_sel[2:0] + attribute \src "libresoc.v:60931.5-60931.29" + switch \initial + attribute \src "libresoc.v:60931.9-60931.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\DIV_in1_sel[2:0] \DIV_dec31_DIV_dec31_in1_sel + case + assign $1\DIV_in1_sel[2:0] 3'000 + end + sync always + update \DIV_in1_sel $0\DIV_in1_sel[2:0] + end + attribute \src "libresoc.v:60940.3-60949.6" + process $proc$libresoc.v:60940$3524 + assign { } { } + assign { } { } + assign $0\DIV_in2_sel[3:0] $1\DIV_in2_sel[3:0] + attribute \src "libresoc.v:60941.5-60941.29" + switch \initial + attribute \src "libresoc.v:60941.9-60941.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\DIV_in2_sel[3:0] \DIV_dec31_DIV_dec31_in2_sel + case + assign $1\DIV_in2_sel[3:0] 4'0000 + end + sync always + update \DIV_in2_sel $0\DIV_in2_sel[3:0] + end + attribute \src "libresoc.v:60950.3-60959.6" + process $proc$libresoc.v:60950$3525 + assign { } { } + assign { } { } + assign $0\DIV_cr_in[2:0] $1\DIV_cr_in[2:0] + attribute \src "libresoc.v:60951.5-60951.29" + switch \initial + attribute \src "libresoc.v:60951.9-60951.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\DIV_cr_in[2:0] \DIV_dec31_DIV_dec31_cr_in + case + assign $1\DIV_cr_in[2:0] 3'000 + end + sync always + update \DIV_cr_in $0\DIV_cr_in[2:0] + end + attribute \src "libresoc.v:60960.3-60969.6" + process $proc$libresoc.v:60960$3526 + assign { } { } + assign { } { } + assign $0\DIV_cr_out[2:0] $1\DIV_cr_out[2:0] + attribute \src "libresoc.v:60961.5-60961.29" + switch \initial + attribute \src "libresoc.v:60961.9-60961.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\DIV_cr_out[2:0] \DIV_dec31_DIV_dec31_cr_out + case + assign $1\DIV_cr_out[2:0] 3'000 + end + sync always + update \DIV_cr_out $0\DIV_cr_out[2:0] + end + attribute \src "libresoc.v:60970.3-60979.6" + process $proc$libresoc.v:60970$3527 + assign { } { } + assign { } { } + assign $0\DIV_ldst_len[3:0] $1\DIV_ldst_len[3:0] + attribute \src "libresoc.v:60971.5-60971.29" + switch \initial + attribute \src "libresoc.v:60971.9-60971.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\DIV_ldst_len[3:0] \DIV_dec31_DIV_dec31_ldst_len + case + assign $1\DIV_ldst_len[3:0] 4'0000 + end + sync always + update \DIV_ldst_len $0\DIV_ldst_len[3:0] + end + attribute \src "libresoc.v:60980.3-60989.6" + process $proc$libresoc.v:60980$3528 + assign { } { } + assign { } { } + assign $0\DIV_rc_sel[1:0] $1\DIV_rc_sel[1:0] + attribute \src "libresoc.v:60981.5-60981.29" + switch \initial + attribute \src "libresoc.v:60981.9-60981.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\DIV_rc_sel[1:0] \DIV_dec31_DIV_dec31_rc_sel + case + assign $1\DIV_rc_sel[1:0] 2'00 + end + sync always + update \DIV_rc_sel $0\DIV_rc_sel[1:0] + end + connect \$1 $ternary$libresoc.v:60832$3514_Y + connect \VC_XO \opcode_in [9:0] + connect \VC_VRT \opcode_in [25:21] + connect \VC_VRB \opcode_in [15:11] + connect \VC_VRA \opcode_in [20:16] + connect \VC_Rc \opcode_in [10] + connect \XS_XO \opcode_in [10:2] + connect \XS_sh { \opcode_in [1] \opcode_in [15:11] } + connect \XS_RS \opcode_in [25:21] + connect \XS_Rc \opcode_in [0] + connect \XS_RA \opcode_in [20:16] + connect \VA_XO \opcode_in [5:0] + connect \VA_VRT \opcode_in [25:21] + connect \VA_VRC \opcode_in [10:6] + connect \VA_VRB \opcode_in [15:11] + connect \VA_VRA \opcode_in [20:16] + connect \VA_SHB \opcode_in [9:6] + connect \VA_RT \opcode_in [25:21] + connect \VA_RC \opcode_in [10:6] + connect \VA_RB \opcode_in [15:11] + connect \VA_RA \opcode_in [20:16] + connect \TX_XO \opcode_in [6:1] + connect \TX_XBI \opcode_in [10:7] + connect \TX_UI \opcode_in [15:11] + connect \TX_RA \opcode_in [20:16] + connect \DQE_XO \opcode_in [1:0] + connect \DQE_RT \opcode_in [25:21] + connect \DQE_RA \opcode_in [20:16] + connect \XO_XO \opcode_in [9:1] + connect \XO_RT \opcode_in [25:21] + connect \XO_Rc \opcode_in [0] + connect \XO_RB \opcode_in [15:11] + connect \XO_RA \opcode_in [20:16] + connect \XO_OE \opcode_in [10] + connect \all_PO \opcode_in [31:26] + connect \all_OPCD \opcode_in [31:26] + connect \SVL_XO \opcode_in [5:1] + connect \SVL_vs \opcode_in [7] + connect \SVL_SVi \opcode_in [15:10] + connect \SVL_RT \opcode_in [25:21] + connect \SVL_Rc \opcode_in [0] + connect \SVL_RA \opcode_in [20:16] + connect \SVL_ms \opcode_in [6] + connect \MD_XO \opcode_in [4:2] + connect \MD_sh { \opcode_in [1] \opcode_in [15:11] } + connect \MD_RS \opcode_in [25:21] + connect \MD_Rc \opcode_in [0] + connect \MD_RA \opcode_in [20:16] + connect \MD_me \opcode_in [10:5] + connect \MD_mb \opcode_in [10:5] + connect \M_SH \opcode_in [15:11] + connect \M_RS \opcode_in [25:21] + connect \M_Rc \opcode_in [0] + connect \M_RB \opcode_in [15:11] + connect \M_RA \opcode_in [20:16] + connect \M_ME \opcode_in [5:1] + connect \M_MB \opcode_in [10:6] + connect \SC_XO_1 \opcode_in [1:0] + connect \SC_XO \opcode_in [1] + connect \SC_LEV \opcode_in [11:5] + connect \MDS_XO \opcode_in [4:1] + connect \MDS_XBI_1 \opcode_in [10:7] + connect \MDS_XBI \opcode_in [10:7] + connect \MDS_RS \opcode_in [25:21] + connect \MDS_Rc \opcode_in [0] + connect \MDS_RB \opcode_in [15:11] + connect \MDS_RA \opcode_in [20:16] + connect \MDS_me \opcode_in [10:5] + connect \MDS_mb \opcode_in [10:5] + connect \MDS_IS \opcode_in [25:21] + connect \MDS_IB \opcode_in [15:11] + connect \Z23_XO \opcode_in [8:1] + connect \Z23_TE \opcode_in [20:16] + connect \Z23_RMC \opcode_in [10:9] + connect \Z23_Rc \opcode_in [0] + connect \Z23_R \opcode_in [16] + connect \Z23_FRTp \opcode_in [25:21] + connect \Z23_FRT \opcode_in [25:21] + connect \Z23_FRBp \opcode_in [15:11] + connect \Z23_FRB \opcode_in [15:11] + connect \Z23_FRAp \opcode_in [20:16] + connect \Z23_FRA \opcode_in [20:16] + connect \XFL_XO \opcode_in [10:1] + connect \XFL_W \opcode_in [16] + connect \XFL_Rc \opcode_in [0] + connect \XFL_L \opcode_in [25] + connect \XFL_FRB \opcode_in [15:11] + connect \XFL_FLM \opcode_in [24:17] + connect \VX_XO_1 \opcode_in [10:0] + connect \VX_XO { \opcode_in [10] \opcode_in [8:0] } + connect \VX_VRT \opcode_in [25:21] + connect \VX_VRB \opcode_in [15:11] + connect \VX_VRA \opcode_in [20:16] + connect \VX_UIM_3 \opcode_in [17:16] + connect \VX_UIM_2 \opcode_in [18:16] + connect \VX_UIM_1 \opcode_in [19:16] + connect \VX_UIM \opcode_in [20:16] + connect \VX_SIM \opcode_in [20:16] + connect \VX_RT \opcode_in [25:21] + connect \VX_RA \opcode_in [20:16] + connect \VX_PS \opcode_in [9] + connect \VX_EO \opcode_in [20:16] + connect \DS_XO \opcode_in [1:0] + connect \DS_VRT \opcode_in [25:21] + connect \DS_VRS \opcode_in [25:21] + connect \DS_RT \opcode_in [25:21] + connect \DS_RSp \opcode_in [25:21] + connect \DS_RS \opcode_in [25:21] + connect \DS_RA \opcode_in [20:16] + connect \DS_FRTp \opcode_in [25:21] + connect \DS_FRSp \opcode_in [25:21] + connect \DS_DS \opcode_in [15:2] + connect \DQ_XO \opcode_in [2:0] + connect \DQ_TX_T { \opcode_in [3] \opcode_in [25:21] } + connect \DQ_T \opcode_in [25:21] + connect \DQ_TX \opcode_in [3] + connect \DQ_SX_S { \opcode_in [3] \opcode_in [25:21] } + connect \DQ_S \opcode_in [25:21] + connect \DQ_SX \opcode_in [3] + connect \DQ_RTp \opcode_in [25:21] + connect \DQ_RA \opcode_in [20:16] + connect \DQ_PT \opcode_in [3:0] + connect \DQ_DQ \opcode_in [15:4] + connect \DX_XO \opcode_in [5:1] + connect \DX_RT \opcode_in [25:21] + connect \DX_d0_d1_d2 { \opcode_in [15:6] \opcode_in [20:16] \opcode_in [0] } + connect \DX_d2 \opcode_in [0] + connect \DX_d1 \opcode_in [20:16] + connect \DX_d0 \opcode_in [15:6] + connect \XFX_XO \opcode_in [10:1] + connect \XFX_SPR \opcode_in [20:11] + connect \XFX_RT \opcode_in [25:21] + connect \XFX_RS \opcode_in [25:21] + connect \XFX_FXM \opcode_in [19:12] + connect \XFX_DUIS \opcode_in [20:11] + connect \XFX_DUI \opcode_in [25:21] + connect \XFX_BHRBE \opcode_in [20:11] + connect \EVS_BFA \opcode_in [2:0] + connect \Z22_XO \opcode_in [9:1] + connect \Z22_SH \opcode_in [15:10] + connect \Z22_Rc \opcode_in [0] + connect \Z22_FRTp \opcode_in [25:21] + connect \Z22_FRT \opcode_in [25:21] + connect \Z22_FRAp \opcode_in [20:16] + connect \Z22_FRA \opcode_in [20:16] + connect \Z22_DGM \opcode_in [15:10] + connect \Z22_DCM \opcode_in [15:10] + connect \Z22_BF \opcode_in [25:23] + connect \XX2_XO_1 \opcode_in [10:2] + connect \XX2_XO { \opcode_in [10:7] \opcode_in [5:3] } + connect \XX2_UIM_1 \opcode_in [17:16] + connect \XX2_UIM \opcode_in [19:16] + connect \XX2_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX2_T \opcode_in [25:21] + connect \XX2_TX \opcode_in [0] + connect \XX2_RT \opcode_in [25:21] + connect \XX2_EO \opcode_in [20:16] + connect \XX2_DCMX \opcode_in [22:16] + connect \XX2_dc_dm_dx { \opcode_in [6] \opcode_in [2] \opcode_in [20:16] } + connect \XX2_dx \opcode_in [20:16] + connect \XX2_dm \opcode_in [2] + connect \XX2_dc \opcode_in [6] + connect \XX2_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX2_B \opcode_in [15:11] + connect \XX2_BX \opcode_in [1] + connect \XX2_BF \opcode_in [25:23] + connect \D_UI \opcode_in [15:0] + connect \D_TO \opcode_in [25:21] + connect \D_SI \opcode_in [15:0] + connect \D_RT \opcode_in [25:21] + connect \D_RS \opcode_in [25:21] + connect \D_RA \opcode_in [20:16] + connect \D_L \opcode_in [21] + connect \D_FRT \opcode_in [25:21] + connect \D_FRS \opcode_in [25:21] + connect \D_D \opcode_in [15:0] + connect \D_BF \opcode_in [25:23] + connect \A_XO \opcode_in [5:1] + connect \A_RT \opcode_in [25:21] + connect \A_Rc \opcode_in [0] + connect \A_RB \opcode_in [15:11] + connect \A_RA \opcode_in [20:16] + connect \A_FRT \opcode_in [25:21] + connect \A_FRC \opcode_in [10:6] + connect \A_FRB \opcode_in [15:11] + connect \A_FRA \opcode_in [20:16] + connect \A_BC \opcode_in [10:6] + connect \XL_XO \opcode_in [10:1] + connect \XL_S \opcode_in [11] + connect \XL_OC \opcode_in [25:11] + connect \XL_LK \opcode_in [0] + connect \XL_BT \opcode_in [25:21] + connect \XL_BO_1 \opcode_in [25:21] + connect \XL_BO \opcode_in [25:21] + connect \XL_BI \opcode_in [20:16] + connect \XL_BH \opcode_in [12:11] + connect \XL_BFA \opcode_in [20:18] + connect \XL_BF \opcode_in [25:23] + connect \XL_BB \opcode_in [15:11] + connect \XL_BA \opcode_in [20:16] + connect \XX4_XO \opcode_in [5:4] + connect \XX4_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX4_T \opcode_in [25:21] + connect \XX4_TX \opcode_in [0] + connect \XX4_CX_C { \opcode_in [3] \opcode_in [10:6] } + connect \XX4_C \opcode_in [10:6] + connect \XX4_CX \opcode_in [3] + connect \XX4_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX4_B \opcode_in [15:11] + connect \XX4_BX \opcode_in [1] + connect \XX4_AX_A { \opcode_in [2] \opcode_in [20:16] } + connect \XX4_A \opcode_in [20:16] + connect \XX4_AX \opcode_in [2] + connect \XX3_XO_2 \opcode_in [9:1] + connect \XX3_XO_1 \opcode_in [10:3] + connect \XX3_XO \opcode_in [10:7] + connect \XX3_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX3_T \opcode_in [25:21] + connect \XX3_TX \opcode_in [0] + connect \XX3_SHW \opcode_in [9:8] + connect \XX3_Rc \opcode_in [10] + connect \XX3_DM \opcode_in [9:8] + connect \XX3_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX3_B \opcode_in [15:11] + connect \XX3_BX \opcode_in [1] + connect \XX3_BF \opcode_in [25:23] + connect \XX3_AX_A { \opcode_in [2] \opcode_in [20:16] } + connect \XX3_A \opcode_in [20:16] + connect \XX3_AX \opcode_in [2] + connect \I_LK \opcode_in [0] + connect \I_LI \opcode_in [25:2] + connect \I_AA \opcode_in [1] + connect \B_LK \opcode_in [0] + connect \B_BO \opcode_in [25:21] + connect \B_BI \opcode_in [20:16] + connect \B_BD \opcode_in [15:2] + connect \B_AA \opcode_in [1] + connect \X_XO_1 \opcode_in [8:1] + connect \X_XO \opcode_in [10:1] + connect \X_WC \opcode_in [22:21] + connect \X_W \opcode_in [16] + connect \X_VRT \opcode_in [25:21] + connect \X_VRS \opcode_in [25:21] + connect \X_UIM \opcode_in [20:16] + connect \X_U \opcode_in [15:12] + connect \X_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \X_TX \opcode_in [0] + connect \X_TO \opcode_in [25:21] + connect \X_TH \opcode_in [25:21] + connect \X_TBR \opcode_in [20:11] + connect \X_T \opcode_in [25:21] + connect \X_SX_S { \opcode_in [0] \opcode_in [25:21] } + connect \X_SX \opcode_in [0] + connect \X_SR \opcode_in [19:16] + connect \X_SP \opcode_in [20:19] + connect \X_SI \opcode_in [15:11] + connect \X_SH \opcode_in [15:11] + connect \X_S \opcode_in [25:21] + connect \X_RTp \opcode_in [25:21] + connect \X_RT \opcode_in [25:21] + connect \X_RSp \opcode_in [25:21] + connect \X_RS \opcode_in [25:21] + connect \X_RO \opcode_in [0] + connect \X_RM \opcode_in [12:11] + connect \X_RIC \opcode_in [19:18] + connect \X_Rc \opcode_in [0] + connect \X_RB \opcode_in [15:11] + connect \X_RA \opcode_in [20:16] + connect \X_R_1 \opcode_in [16] + connect \X_R \opcode_in [21] + connect \X_PRS \opcode_in [17] + connect \X_NB \opcode_in [15:11] + connect \X_MO \opcode_in [25:21] + connect \X_L3 \opcode_in [17:16] + connect \X_L1 \opcode_in [16] + connect \X_L \opcode_in [21] + connect \X_L2 \opcode_in [22:21] + connect \X_IMM8 \opcode_in [18:11] + connect \X_IH \opcode_in [23:21] + connect \X_FRTp \opcode_in [25:21] + connect \X_FRT \opcode_in [25:21] + connect \X_FRSp \opcode_in [25:21] + connect \X_FRS \opcode_in [25:21] + connect \X_FRBp \opcode_in [15:11] + connect \X_FRB \opcode_in [15:11] + connect \X_FRAp \opcode_in [20:16] + connect \X_FRA \opcode_in [20:16] + connect \X_FC \opcode_in [15:11] + connect \X_EX \opcode_in [0] + connect \X_EO_1 \opcode_in [20:16] + connect \X_EO \opcode_in [20:19] + connect \X_E_1 \opcode_in [19:16] + connect \X_E \opcode_in [15] + connect \X_DRM \opcode_in [13:11] + connect \X_DCMX \opcode_in [22:16] + connect \X_CT \opcode_in [24:21] + connect \X_BO \opcode_in [25:21] + connect \X_BFA \opcode_in [20:18] + connect \X_BF \opcode_in [25:23] + connect \X_A \opcode_in [25] + connect \DIV_SPR \opcode_in [20:11] + connect \DIV_MB \opcode_in [10:6] + connect \DIV_ME \opcode_in [5:1] + connect \DIV_SH \opcode_in [15:11] + connect \DIV_BC \opcode_in [10:6] + connect \DIV_TO \opcode_in [25:21] + connect \DIV_DS \opcode_in [15:2] + connect \DIV_D \opcode_in [15:0] + connect \DIV_BH \opcode_in [12:11] + connect \DIV_BI \opcode_in [20:16] + connect \DIV_BO \opcode_in [25:21] + connect \DIV_FXM \opcode_in [19:12] + connect \DIV_BT \opcode_in [25:21] + connect \DIV_BA \opcode_in [20:16] + connect \DIV_BB \opcode_in [15:11] + connect \DIV_CR \opcode_in [10:1] + connect \DIV_BF \opcode_in [25:23] + connect \DIV_BD \opcode_in [15:2] + connect \DIV_OE \opcode_in [10] + connect \DIV_Rc \opcode_in [0] + connect \DIV_AA \opcode_in [1] + connect \DIV_LK \opcode_in [0] + connect \DIV_LI \opcode_in [25:2] + connect \DIV_ME32 \opcode_in [5:1] + connect \DIV_MB32 \opcode_in [10:6] + connect \DIV_sh { \opcode_in [1] \opcode_in [15:11] } + connect \DIV_SH32 \opcode_in [15:11] + connect \DIV_L \opcode_in [21] + connect \DIV_UI \opcode_in [15:0] + connect \DIV_SI \opcode_in [15:0] + connect \DIV_RB \opcode_in [15:11] + connect \DIV_RA \opcode_in [20:16] + connect \DIV_RT \opcode_in [25:21] + connect \DIV_RS \opcode_in [25:21] + connect \opcode_in \$1 + connect \DIV_dec31_opcode_in \opcode_in + connect \opcode_switch \opcode_in [31:26] +end +attribute \src "libresoc.v:61330.1-62748.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_MUL.dec" +attribute \generator "nMigen" +module \dec$179 + attribute \src "libresoc.v:62347.3-62359.6" + wire width 3 $0\MUL_cr_in[2:0] + attribute \src "libresoc.v:62360.3-62372.6" + wire width 3 $0\MUL_cr_out[2:0] + attribute \src "libresoc.v:62308.3-62320.6" + wire width 13 $0\MUL_function_unit[12:0] + attribute \src "libresoc.v:62334.3-62346.6" + wire width 4 $0\MUL_in2_sel[3:0] + attribute \src "libresoc.v:62321.3-62333.6" + wire width 7 $0\MUL_internal_op[6:0] + attribute \src "libresoc.v:62386.3-62398.6" + wire $0\MUL_is_32b[0:0] + attribute \src "libresoc.v:62373.3-62385.6" + wire width 2 $0\MUL_rc_sel[1:0] + attribute \src "libresoc.v:62399.3-62411.6" + wire $0\MUL_sgn[0:0] + attribute \src "libresoc.v:61331.7-61331.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:62347.3-62359.6" + wire width 3 $1\MUL_cr_in[2:0] + attribute \src "libresoc.v:62360.3-62372.6" + wire width 3 $1\MUL_cr_out[2:0] + attribute \src "libresoc.v:62308.3-62320.6" + wire width 13 $1\MUL_function_unit[12:0] + attribute \src "libresoc.v:62334.3-62346.6" + wire width 4 $1\MUL_in2_sel[3:0] + attribute \src "libresoc.v:62321.3-62333.6" + wire width 7 $1\MUL_internal_op[6:0] + attribute \src "libresoc.v:62386.3-62398.6" + wire $1\MUL_is_32b[0:0] + attribute \src "libresoc.v:62373.3-62385.6" + wire width 2 $1\MUL_rc_sel[1:0] + attribute \src "libresoc.v:62399.3-62411.6" + wire $1\MUL_sgn[0:0] + attribute \src "libresoc.v:62296.17-62296.211" + wire width 32 $ternary$libresoc.v:62296$3530_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:504" + wire width 32 \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \A_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \A_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \A_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \A_FRC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \A_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \A_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \A_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \A_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \A_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \A_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \B_AA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 14 \B_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \B_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \B_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \B_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DQE_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DQE_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 2 \DQE_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 12 \DQ_DQ + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 4 \DQ_PT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DQ_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DQ_RTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DQ_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \DQ_SX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \DQ_SX_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DQ_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \DQ_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \DQ_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 3 \DQ_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 14 \DS_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DS_FRSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DS_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DS_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DS_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DS_RSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DS_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DS_VRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DS_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 2 \DS_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DX_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 10 \DX_d0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 16 \DX_d0_d1_d2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DX_d1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \DX_d2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 3 \D_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 16 \D_D + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \D_FRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \D_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \D_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \D_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \D_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \D_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 16 \D_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \D_TO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 16 \D_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 3 \EVS_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \I_AA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 24 \I_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \I_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \MDS_IB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \MDS_IS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \MDS_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \MDS_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \MDS_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \MDS_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 4 \MDS_XBI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 4 \MDS_XBI_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 4 \MDS_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \MDS_mb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \MDS_me + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \MD_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \MD_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \MD_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 3 \MD_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \MD_mb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \MD_me + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \MD_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire \MUL_AA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 output 21 \MUL_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 output 20 \MUL_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 output 26 \MUL_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 14 output 19 \MUL_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 3 \MUL_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 2 \MUL_BH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 output 24 \MUL_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \MUL_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 output 22 \MUL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 10 \MUL_CR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 16 \MUL_D + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 14 output 25 \MUL_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 8 output 23 \MUL_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire \MUL_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 24 output 16 \MUL_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire \MUL_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \MUL_MB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \MUL_MB32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \MUL_ME + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \MUL_ME32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire output 18 \MUL_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \MUL_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \MUL_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \MUL_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \MUL_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire output 17 \MUL_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \MUL_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 output 14 \MUL_SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 16 output 12 \MUL_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 10 output 7 \MUL_SPR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \MUL_TO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 16 output 13 \MUL_UI + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 4 \MUL_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 5 \MUL_cr_out + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \MUL_dec31_MUL_dec31_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \MUL_dec31_MUL_dec31_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 13 \MUL_dec31_MUL_dec31_function_unit + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 \MUL_dec31_MUL_dec31_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 \MUL_dec31_MUL_dec31_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \MUL_dec31_MUL_dec31_is_32b + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \MUL_dec31_MUL_dec31_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \MUL_dec31_MUL_dec31_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + wire width 32 \MUL_dec31_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 13 output 8 \MUL_function_unit + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 9 \MUL_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 output 6 \MUL_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 10 \MUL_is_32b + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 3 \MUL_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 11 \MUL_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 6 output 15 \MUL_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \M_MB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \M_ME + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \M_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \M_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \M_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \M_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \M_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 7 \SC_LEV + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \SC_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 2 \SC_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \SVL_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \SVL_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \SVL_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \SVL_SVi + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \SVL_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \SVL_ms + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \SVL_vs + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \TX_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \TX_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 4 \TX_XBI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \TX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \VA_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \VA_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \VA_RC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \VA_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 4 \VA_SHB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \VA_VRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \VA_VRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \VA_VRC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \VA_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \VA_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \VC_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \VC_VRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \VC_VRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \VC_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 10 \VC_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \VX_EO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \VX_PS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \VX_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \VX_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \VX_SIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \VX_UIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 4 \VX_UIM_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 3 \VX_UIM_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 2 \VX_UIM_3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \VX_VRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \VX_VRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \VX_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 10 \VX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 11 \VX_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 8 \XFL_FLM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \XFL_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \XFL_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \XFL_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \XFL_W + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 10 \XFL_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 10 \XFX_BHRBE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \XFX_DUI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 10 \XFX_DUIS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 8 \XFX_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \XFX_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \XFX_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 10 \XFX_SPR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 10 \XFX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \XL_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \XL_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 3 \XL_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 3 \XL_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 2 \XL_BH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \XL_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \XL_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \XL_BO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 output 29 \XL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \XL_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 15 \XL_OC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \XL_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 10 \XL_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \XO_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \XO_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \XO_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \XO_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \XO_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 9 \XO_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \XS_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \XS_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \XS_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 9 \XS_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \XS_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \XX2_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 3 \XX2_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \XX2_BX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \XX2_BX_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 7 \XX2_DCMX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \XX2_EO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \XX2_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \XX2_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \XX2_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \XX2_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 4 \XX2_UIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 2 \XX2_UIM_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 7 \XX2_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 9 \XX2_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \XX2_dc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 7 \XX2_dc_dm_dx + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \XX2_dm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \XX2_dx + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \XX3_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \XX3_AX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \XX3_AX_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \XX3_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 3 \XX3_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \XX3_BX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \XX3_BX_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 2 \XX3_DM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \XX3_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 2 \XX3_SHW + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \XX3_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \XX3_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \XX3_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 4 \XX3_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 8 \XX3_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 9 \XX3_XO_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \XX4_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \XX4_AX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \XX4_AX_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \XX4_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \XX4_BX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \XX4_BX_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \XX4_C + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \XX4_CX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \XX4_CX_C + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \XX4_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \XX4_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \XX4_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 2 \XX4_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \X_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 3 output 27 \X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 3 output 28 \X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 4 \X_CT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 7 \X_DCMX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 3 \X_DRM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \X_E + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 2 \X_EO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_EO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \X_EX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 4 \X_E_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_FC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_FRAp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_FRBp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_FRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_FRSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 3 \X_IH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 8 \X_IMM8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \X_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \X_L1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 2 \X_L2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 2 \X_L3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_MO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_NB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \X_PRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \X_R + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 2 \X_RIC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 2 \X_RM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \X_RO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_RSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_RTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \X_R_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \X_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 2 \X_SP + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 4 \X_SR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \X_SX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \X_SX_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 10 \X_TBR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_TH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_TO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \X_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \X_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 4 \X_U + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_UIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_VRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \X_W + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 2 \X_WC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 10 \X_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 8 \X_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 3 \Z22_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \Z22_DCM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \Z22_DGM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \Z22_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \Z22_FRAp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \Z22_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \Z22_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \Z22_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \Z22_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 9 \Z22_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \Z23_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \Z23_FRAp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \Z23_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \Z23_FRBp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \Z23_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \Z23_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \Z23_R + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 2 \Z23_RMC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \Z23_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \Z23_TE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 8 \Z23_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \all_OPCD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \all_PO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" + wire input 1 \bigendian + attribute \src "libresoc.v:61331.7-61331.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + wire width 32 output 2 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + wire width 6 \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 32 input 30 \raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:504" + cell $mux $ternary$libresoc.v:62296$3530 + parameter \WIDTH 32 + connect \A \raw_opcode_in + connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } + connect \S \bigendian + connect \Y $ternary$libresoc.v:62296$3530_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:62297.13-62307.4" + cell \MUL_dec31 \MUL_dec31 + connect \MUL_dec31_cr_in \MUL_dec31_MUL_dec31_cr_in + connect \MUL_dec31_cr_out \MUL_dec31_MUL_dec31_cr_out + connect \MUL_dec31_function_unit \MUL_dec31_MUL_dec31_function_unit + connect \MUL_dec31_in2_sel \MUL_dec31_MUL_dec31_in2_sel + connect \MUL_dec31_internal_op \MUL_dec31_MUL_dec31_internal_op + connect \MUL_dec31_is_32b \MUL_dec31_MUL_dec31_is_32b + connect \MUL_dec31_rc_sel \MUL_dec31_MUL_dec31_rc_sel + connect \MUL_dec31_sgn \MUL_dec31_MUL_dec31_sgn + connect \opcode_in \MUL_dec31_opcode_in + end + attribute \src "libresoc.v:61331.7-61331.20" + process $proc$libresoc.v:61331$3539 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:62308.3-62320.6" + process $proc$libresoc.v:62308$3531 + assign { } { } + assign { } { } + assign $0\MUL_function_unit[12:0] $1\MUL_function_unit[12:0] + attribute \src "libresoc.v:62309.5-62309.29" + switch \initial + attribute \src "libresoc.v:62309.9-62309.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\MUL_function_unit[12:0] \MUL_dec31_MUL_dec31_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\MUL_function_unit[12:0] 13'0000100000000 + case + assign $1\MUL_function_unit[12:0] 13'0000000000000 + end + sync always + update \MUL_function_unit $0\MUL_function_unit[12:0] + end + attribute \src "libresoc.v:62321.3-62333.6" + process $proc$libresoc.v:62321$3532 + assign { } { } + assign { } { } + assign $0\MUL_internal_op[6:0] $1\MUL_internal_op[6:0] + attribute \src "libresoc.v:62322.5-62322.29" + switch \initial + attribute \src "libresoc.v:62322.9-62322.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\MUL_internal_op[6:0] \MUL_dec31_MUL_dec31_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\MUL_internal_op[6:0] 7'0110010 + case + assign $1\MUL_internal_op[6:0] 7'0000000 + end + sync always + update \MUL_internal_op $0\MUL_internal_op[6:0] + end + attribute \src "libresoc.v:62334.3-62346.6" + process $proc$libresoc.v:62334$3533 + assign { } { } + assign { } { } + assign $0\MUL_in2_sel[3:0] $1\MUL_in2_sel[3:0] + attribute \src "libresoc.v:62335.5-62335.29" + switch \initial + attribute \src "libresoc.v:62335.9-62335.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\MUL_in2_sel[3:0] \MUL_dec31_MUL_dec31_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\MUL_in2_sel[3:0] 4'0011 + case + assign $1\MUL_in2_sel[3:0] 4'0000 + end + sync always + update \MUL_in2_sel $0\MUL_in2_sel[3:0] + end + attribute \src "libresoc.v:62347.3-62359.6" + process $proc$libresoc.v:62347$3534 + assign { } { } + assign { } { } + assign $0\MUL_cr_in[2:0] $1\MUL_cr_in[2:0] + attribute \src "libresoc.v:62348.5-62348.29" + switch \initial + attribute \src "libresoc.v:62348.9-62348.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\MUL_cr_in[2:0] \MUL_dec31_MUL_dec31_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\MUL_cr_in[2:0] 3'000 + case + assign $1\MUL_cr_in[2:0] 3'000 + end + sync always + update \MUL_cr_in $0\MUL_cr_in[2:0] + end + attribute \src "libresoc.v:62360.3-62372.6" + process $proc$libresoc.v:62360$3535 + assign { } { } + assign { } { } + assign $0\MUL_cr_out[2:0] $1\MUL_cr_out[2:0] + attribute \src "libresoc.v:62361.5-62361.29" + switch \initial + attribute \src "libresoc.v:62361.9-62361.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\MUL_cr_out[2:0] \MUL_dec31_MUL_dec31_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\MUL_cr_out[2:0] 3'001 + case + assign $1\MUL_cr_out[2:0] 3'000 + end + sync always + update \MUL_cr_out $0\MUL_cr_out[2:0] + end + attribute \src "libresoc.v:62373.3-62385.6" + process $proc$libresoc.v:62373$3536 + assign { } { } + assign { } { } + assign $0\MUL_rc_sel[1:0] $1\MUL_rc_sel[1:0] + attribute \src "libresoc.v:62374.5-62374.29" + switch \initial + attribute \src "libresoc.v:62374.9-62374.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\MUL_rc_sel[1:0] \MUL_dec31_MUL_dec31_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\MUL_rc_sel[1:0] 2'00 + case + assign $1\MUL_rc_sel[1:0] 2'00 + end + sync always + update \MUL_rc_sel $0\MUL_rc_sel[1:0] + end + attribute \src "libresoc.v:62386.3-62398.6" + process $proc$libresoc.v:62386$3537 + assign { } { } + assign { } { } + assign $0\MUL_is_32b[0:0] $1\MUL_is_32b[0:0] + attribute \src "libresoc.v:62387.5-62387.29" + switch \initial + attribute \src "libresoc.v:62387.9-62387.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\MUL_is_32b[0:0] \MUL_dec31_MUL_dec31_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\MUL_is_32b[0:0] 1'0 + case + assign $1\MUL_is_32b[0:0] 1'0 + end + sync always + update \MUL_is_32b $0\MUL_is_32b[0:0] + end + attribute \src "libresoc.v:62399.3-62411.6" + process $proc$libresoc.v:62399$3538 + assign { } { } + assign { } { } + assign $0\MUL_sgn[0:0] $1\MUL_sgn[0:0] + attribute \src "libresoc.v:62400.5-62400.29" + switch \initial + attribute \src "libresoc.v:62400.9-62400.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\MUL_sgn[0:0] \MUL_dec31_MUL_dec31_sgn + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\MUL_sgn[0:0] 1'1 + case + assign $1\MUL_sgn[0:0] 1'0 + end + sync always + update \MUL_sgn $0\MUL_sgn[0:0] + end + connect \$1 $ternary$libresoc.v:62296$3530_Y + connect \VC_XO \opcode_in [9:0] + connect \VC_VRT \opcode_in [25:21] + connect \VC_VRB \opcode_in [15:11] + connect \VC_VRA \opcode_in [20:16] + connect \VC_Rc \opcode_in [10] + connect \XS_XO \opcode_in [10:2] + connect \XS_sh { \opcode_in [1] \opcode_in [15:11] } + connect \XS_RS \opcode_in [25:21] + connect \XS_Rc \opcode_in [0] + connect \XS_RA \opcode_in [20:16] + connect \VA_XO \opcode_in [5:0] + connect \VA_VRT \opcode_in [25:21] + connect \VA_VRC \opcode_in [10:6] + connect \VA_VRB \opcode_in [15:11] + connect \VA_VRA \opcode_in [20:16] + connect \VA_SHB \opcode_in [9:6] + connect \VA_RT \opcode_in [25:21] + connect \VA_RC \opcode_in [10:6] + connect \VA_RB \opcode_in [15:11] + connect \VA_RA \opcode_in [20:16] + connect \TX_XO \opcode_in [6:1] + connect \TX_XBI \opcode_in [10:7] + connect \TX_UI \opcode_in [15:11] + connect \TX_RA \opcode_in [20:16] + connect \DQE_XO \opcode_in [1:0] + connect \DQE_RT \opcode_in [25:21] + connect \DQE_RA \opcode_in [20:16] + connect \XO_XO \opcode_in [9:1] + connect \XO_RT \opcode_in [25:21] + connect \XO_Rc \opcode_in [0] + connect \XO_RB \opcode_in [15:11] + connect \XO_RA \opcode_in [20:16] + connect \XO_OE \opcode_in [10] + connect \all_PO \opcode_in [31:26] + connect \all_OPCD \opcode_in [31:26] + connect \SVL_XO \opcode_in [5:1] + connect \SVL_vs \opcode_in [7] + connect \SVL_SVi \opcode_in [15:10] + connect \SVL_RT \opcode_in [25:21] + connect \SVL_Rc \opcode_in [0] + connect \SVL_RA \opcode_in [20:16] + connect \SVL_ms \opcode_in [6] + connect \MD_XO \opcode_in [4:2] + connect \MD_sh { \opcode_in [1] \opcode_in [15:11] } + connect \MD_RS \opcode_in [25:21] + connect \MD_Rc \opcode_in [0] + connect \MD_RA \opcode_in [20:16] + connect \MD_me \opcode_in [10:5] + connect \MD_mb \opcode_in [10:5] + connect \M_SH \opcode_in [15:11] + connect \M_RS \opcode_in [25:21] + connect \M_Rc \opcode_in [0] + connect \M_RB \opcode_in [15:11] + connect \M_RA \opcode_in [20:16] + connect \M_ME \opcode_in [5:1] + connect \M_MB \opcode_in [10:6] + connect \SC_XO_1 \opcode_in [1:0] + connect \SC_XO \opcode_in [1] + connect \SC_LEV \opcode_in [11:5] + connect \MDS_XO \opcode_in [4:1] + connect \MDS_XBI_1 \opcode_in [10:7] + connect \MDS_XBI \opcode_in [10:7] + connect \MDS_RS \opcode_in [25:21] + connect \MDS_Rc \opcode_in [0] + connect \MDS_RB \opcode_in [15:11] + connect \MDS_RA \opcode_in [20:16] + connect \MDS_me \opcode_in [10:5] + connect \MDS_mb \opcode_in [10:5] + connect \MDS_IS \opcode_in [25:21] + connect \MDS_IB \opcode_in [15:11] + connect \Z23_XO \opcode_in [8:1] + connect \Z23_TE \opcode_in [20:16] + connect \Z23_RMC \opcode_in [10:9] + connect \Z23_Rc \opcode_in [0] + connect \Z23_R \opcode_in [16] + connect \Z23_FRTp \opcode_in [25:21] + connect \Z23_FRT \opcode_in [25:21] + connect \Z23_FRBp \opcode_in [15:11] + connect \Z23_FRB \opcode_in [15:11] + connect \Z23_FRAp \opcode_in [20:16] + connect \Z23_FRA \opcode_in [20:16] + connect \XFL_XO \opcode_in [10:1] + connect \XFL_W \opcode_in [16] + connect \XFL_Rc \opcode_in [0] + connect \XFL_L \opcode_in [25] + connect \XFL_FRB \opcode_in [15:11] + connect \XFL_FLM \opcode_in [24:17] + connect \VX_XO_1 \opcode_in [10:0] + connect \VX_XO { \opcode_in [10] \opcode_in [8:0] } + connect \VX_VRT \opcode_in [25:21] + connect \VX_VRB \opcode_in [15:11] + connect \VX_VRA \opcode_in [20:16] + connect \VX_UIM_3 \opcode_in [17:16] + connect \VX_UIM_2 \opcode_in [18:16] + connect \VX_UIM_1 \opcode_in [19:16] + connect \VX_UIM \opcode_in [20:16] + connect \VX_SIM \opcode_in [20:16] + connect \VX_RT \opcode_in [25:21] + connect \VX_RA \opcode_in [20:16] + connect \VX_PS \opcode_in [9] + connect \VX_EO \opcode_in [20:16] + connect \DS_XO \opcode_in [1:0] + connect \DS_VRT \opcode_in [25:21] + connect \DS_VRS \opcode_in [25:21] + connect \DS_RT \opcode_in [25:21] + connect \DS_RSp \opcode_in [25:21] + connect \DS_RS \opcode_in [25:21] + connect \DS_RA \opcode_in [20:16] + connect \DS_FRTp \opcode_in [25:21] + connect \DS_FRSp \opcode_in [25:21] + connect \DS_DS \opcode_in [15:2] + connect \DQ_XO \opcode_in [2:0] + connect \DQ_TX_T { \opcode_in [3] \opcode_in [25:21] } + connect \DQ_T \opcode_in [25:21] + connect \DQ_TX \opcode_in [3] + connect \DQ_SX_S { \opcode_in [3] \opcode_in [25:21] } + connect \DQ_S \opcode_in [25:21] + connect \DQ_SX \opcode_in [3] + connect \DQ_RTp \opcode_in [25:21] + connect \DQ_RA \opcode_in [20:16] + connect \DQ_PT \opcode_in [3:0] + connect \DQ_DQ \opcode_in [15:4] + connect \DX_XO \opcode_in [5:1] + connect \DX_RT \opcode_in [25:21] + connect \DX_d0_d1_d2 { \opcode_in [15:6] \opcode_in [20:16] \opcode_in [0] } + connect \DX_d2 \opcode_in [0] + connect \DX_d1 \opcode_in [20:16] + connect \DX_d0 \opcode_in [15:6] + connect \XFX_XO \opcode_in [10:1] + connect \XFX_SPR \opcode_in [20:11] + connect \XFX_RT \opcode_in [25:21] + connect \XFX_RS \opcode_in [25:21] + connect \XFX_FXM \opcode_in [19:12] + connect \XFX_DUIS \opcode_in [20:11] + connect \XFX_DUI \opcode_in [25:21] + connect \XFX_BHRBE \opcode_in [20:11] + connect \EVS_BFA \opcode_in [2:0] + connect \Z22_XO \opcode_in [9:1] + connect \Z22_SH \opcode_in [15:10] + connect \Z22_Rc \opcode_in [0] + connect \Z22_FRTp \opcode_in [25:21] + connect \Z22_FRT \opcode_in [25:21] + connect \Z22_FRAp \opcode_in [20:16] + connect \Z22_FRA \opcode_in [20:16] + connect \Z22_DGM \opcode_in [15:10] + connect \Z22_DCM \opcode_in [15:10] + connect \Z22_BF \opcode_in [25:23] + connect \XX2_XO_1 \opcode_in [10:2] + connect \XX2_XO { \opcode_in [10:7] \opcode_in [5:3] } + connect \XX2_UIM_1 \opcode_in [17:16] + connect \XX2_UIM \opcode_in [19:16] + connect \XX2_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX2_T \opcode_in [25:21] + connect \XX2_TX \opcode_in [0] + connect \XX2_RT \opcode_in [25:21] + connect \XX2_EO \opcode_in [20:16] + connect \XX2_DCMX \opcode_in [22:16] + connect \XX2_dc_dm_dx { \opcode_in [6] \opcode_in [2] \opcode_in [20:16] } + connect \XX2_dx \opcode_in [20:16] + connect \XX2_dm \opcode_in [2] + connect \XX2_dc \opcode_in [6] + connect \XX2_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX2_B \opcode_in [15:11] + connect \XX2_BX \opcode_in [1] + connect \XX2_BF \opcode_in [25:23] + connect \D_UI \opcode_in [15:0] + connect \D_TO \opcode_in [25:21] + connect \D_SI \opcode_in [15:0] + connect \D_RT \opcode_in [25:21] + connect \D_RS \opcode_in [25:21] + connect \D_RA \opcode_in [20:16] + connect \D_L \opcode_in [21] + connect \D_FRT \opcode_in [25:21] + connect \D_FRS \opcode_in [25:21] + connect \D_D \opcode_in [15:0] + connect \D_BF \opcode_in [25:23] + connect \A_XO \opcode_in [5:1] + connect \A_RT \opcode_in [25:21] + connect \A_Rc \opcode_in [0] + connect \A_RB \opcode_in [15:11] + connect \A_RA \opcode_in [20:16] + connect \A_FRT \opcode_in [25:21] + connect \A_FRC \opcode_in [10:6] + connect \A_FRB \opcode_in [15:11] + connect \A_FRA \opcode_in [20:16] + connect \A_BC \opcode_in [10:6] + connect \XL_XO \opcode_in [10:1] + connect \XL_S \opcode_in [11] + connect \XL_OC \opcode_in [25:11] + connect \XL_LK \opcode_in [0] + connect \XL_BT \opcode_in [25:21] + connect \XL_BO_1 \opcode_in [25:21] + connect \XL_BO \opcode_in [25:21] + connect \XL_BI \opcode_in [20:16] + connect \XL_BH \opcode_in [12:11] + connect \XL_BFA \opcode_in [20:18] + connect \XL_BF \opcode_in [25:23] + connect \XL_BB \opcode_in [15:11] + connect \XL_BA \opcode_in [20:16] + connect \XX4_XO \opcode_in [5:4] + connect \XX4_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX4_T \opcode_in [25:21] + connect \XX4_TX \opcode_in [0] + connect \XX4_CX_C { \opcode_in [3] \opcode_in [10:6] } + connect \XX4_C \opcode_in [10:6] + connect \XX4_CX \opcode_in [3] + connect \XX4_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX4_B \opcode_in [15:11] + connect \XX4_BX \opcode_in [1] + connect \XX4_AX_A { \opcode_in [2] \opcode_in [20:16] } + connect \XX4_A \opcode_in [20:16] + connect \XX4_AX \opcode_in [2] + connect \XX3_XO_2 \opcode_in [9:1] + connect \XX3_XO_1 \opcode_in [10:3] + connect \XX3_XO \opcode_in [10:7] + connect \XX3_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX3_T \opcode_in [25:21] + connect \XX3_TX \opcode_in [0] + connect \XX3_SHW \opcode_in [9:8] + connect \XX3_Rc \opcode_in [10] + connect \XX3_DM \opcode_in [9:8] + connect \XX3_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX3_B \opcode_in [15:11] + connect \XX3_BX \opcode_in [1] + connect \XX3_BF \opcode_in [25:23] + connect \XX3_AX_A { \opcode_in [2] \opcode_in [20:16] } + connect \XX3_A \opcode_in [20:16] + connect \XX3_AX \opcode_in [2] + connect \I_LK \opcode_in [0] + connect \I_LI \opcode_in [25:2] + connect \I_AA \opcode_in [1] + connect \B_LK \opcode_in [0] + connect \B_BO \opcode_in [25:21] + connect \B_BI \opcode_in [20:16] + connect \B_BD \opcode_in [15:2] + connect \B_AA \opcode_in [1] + connect \X_XO_1 \opcode_in [8:1] + connect \X_XO \opcode_in [10:1] + connect \X_WC \opcode_in [22:21] + connect \X_W \opcode_in [16] + connect \X_VRT \opcode_in [25:21] + connect \X_VRS \opcode_in [25:21] + connect \X_UIM \opcode_in [20:16] + connect \X_U \opcode_in [15:12] + connect \X_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \X_TX \opcode_in [0] + connect \X_TO \opcode_in [25:21] + connect \X_TH \opcode_in [25:21] + connect \X_TBR \opcode_in [20:11] + connect \X_T \opcode_in [25:21] + connect \X_SX_S { \opcode_in [0] \opcode_in [25:21] } + connect \X_SX \opcode_in [0] + connect \X_SR \opcode_in [19:16] + connect \X_SP \opcode_in [20:19] + connect \X_SI \opcode_in [15:11] + connect \X_SH \opcode_in [15:11] + connect \X_S \opcode_in [25:21] + connect \X_RTp \opcode_in [25:21] + connect \X_RT \opcode_in [25:21] + connect \X_RSp \opcode_in [25:21] + connect \X_RS \opcode_in [25:21] + connect \X_RO \opcode_in [0] + connect \X_RM \opcode_in [12:11] + connect \X_RIC \opcode_in [19:18] + connect \X_Rc \opcode_in [0] + connect \X_RB \opcode_in [15:11] + connect \X_RA \opcode_in [20:16] + connect \X_R_1 \opcode_in [16] + connect \X_R \opcode_in [21] + connect \X_PRS \opcode_in [17] + connect \X_NB \opcode_in [15:11] + connect \X_MO \opcode_in [25:21] + connect \X_L3 \opcode_in [17:16] + connect \X_L1 \opcode_in [16] + connect \X_L \opcode_in [21] + connect \X_L2 \opcode_in [22:21] + connect \X_IMM8 \opcode_in [18:11] + connect \X_IH \opcode_in [23:21] + connect \X_FRTp \opcode_in [25:21] + connect \X_FRT \opcode_in [25:21] + connect \X_FRSp \opcode_in [25:21] + connect \X_FRS \opcode_in [25:21] + connect \X_FRBp \opcode_in [15:11] + connect \X_FRB \opcode_in [15:11] + connect \X_FRAp \opcode_in [20:16] + connect \X_FRA \opcode_in [20:16] + connect \X_FC \opcode_in [15:11] + connect \X_EX \opcode_in [0] + connect \X_EO_1 \opcode_in [20:16] + connect \X_EO \opcode_in [20:19] + connect \X_E_1 \opcode_in [19:16] + connect \X_E \opcode_in [15] + connect \X_DRM \opcode_in [13:11] + connect \X_DCMX \opcode_in [22:16] + connect \X_CT \opcode_in [24:21] + connect \X_BO \opcode_in [25:21] + connect \X_BFA \opcode_in [20:18] + connect \X_BF \opcode_in [25:23] + connect \X_A \opcode_in [25] + connect \MUL_SPR \opcode_in [20:11] + connect \MUL_MB \opcode_in [10:6] + connect \MUL_ME \opcode_in [5:1] + connect \MUL_SH \opcode_in [15:11] + connect \MUL_BC \opcode_in [10:6] + connect \MUL_TO \opcode_in [25:21] + connect \MUL_DS \opcode_in [15:2] + connect \MUL_D \opcode_in [15:0] + connect \MUL_BH \opcode_in [12:11] + connect \MUL_BI \opcode_in [20:16] + connect \MUL_BO \opcode_in [25:21] + connect \MUL_FXM \opcode_in [19:12] + connect \MUL_BT \opcode_in [25:21] + connect \MUL_BA \opcode_in [20:16] + connect \MUL_BB \opcode_in [15:11] + connect \MUL_CR \opcode_in [10:1] + connect \MUL_BF \opcode_in [25:23] + connect \MUL_BD \opcode_in [15:2] + connect \MUL_OE \opcode_in [10] + connect \MUL_Rc \opcode_in [0] + connect \MUL_AA \opcode_in [1] + connect \MUL_LK \opcode_in [0] + connect \MUL_LI \opcode_in [25:2] + connect \MUL_ME32 \opcode_in [5:1] + connect \MUL_MB32 \opcode_in [10:6] + connect \MUL_sh { \opcode_in [1] \opcode_in [15:11] } + connect \MUL_SH32 \opcode_in [15:11] + connect \MUL_L \opcode_in [21] + connect \MUL_UI \opcode_in [15:0] + connect \MUL_SI \opcode_in [15:0] + connect \MUL_RB \opcode_in [15:11] + connect \MUL_RA \opcode_in [20:16] + connect \MUL_RT \opcode_in [25:21] + connect \MUL_RS \opcode_in [25:21] + connect \opcode_in \$1 + connect \MUL_dec31_opcode_in \opcode_in + connect \opcode_switch \opcode_in [31:26] +end +attribute \src "libresoc.v:62752.1-64500.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SHIFT_ROT.dec" +attribute \generator "nMigen" +module \dec$187 + attribute \src "libresoc.v:64075.3-64096.6" + wire width 3 $0\SHIFT_ROT_cr_in[2:0] + attribute \src "libresoc.v:64097.3-64118.6" + wire width 3 $0\SHIFT_ROT_cr_out[2:0] + attribute \src "libresoc.v:64141.3-64162.6" + wire width 2 $0\SHIFT_ROT_cry_in[1:0] + attribute \src "libresoc.v:63943.3-63964.6" + wire $0\SHIFT_ROT_cry_out[0:0] + attribute \src "libresoc.v:64009.3-64030.6" + wire width 13 $0\SHIFT_ROT_function_unit[12:0] + attribute \src "libresoc.v:64053.3-64074.6" + wire width 4 $0\SHIFT_ROT_in2_sel[3:0] + attribute \src "libresoc.v:64031.3-64052.6" + wire width 7 $0\SHIFT_ROT_internal_op[6:0] + attribute \src "libresoc.v:63921.3-63942.6" + wire $0\SHIFT_ROT_inv_a[0:0] + attribute \src "libresoc.v:63965.3-63986.6" + wire $0\SHIFT_ROT_is_32b[0:0] + attribute \src "libresoc.v:64119.3-64140.6" + wire width 2 $0\SHIFT_ROT_rc_sel[1:0] + attribute \src "libresoc.v:63987.3-64008.6" + wire $0\SHIFT_ROT_sgn[0:0] + attribute \src "libresoc.v:62753.7-62753.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:64075.3-64096.6" + wire width 3 $1\SHIFT_ROT_cr_in[2:0] + attribute \src "libresoc.v:64097.3-64118.6" + wire width 3 $1\SHIFT_ROT_cr_out[2:0] + attribute \src "libresoc.v:64141.3-64162.6" + wire width 2 $1\SHIFT_ROT_cry_in[1:0] + attribute \src "libresoc.v:63943.3-63964.6" + wire $1\SHIFT_ROT_cry_out[0:0] + attribute \src "libresoc.v:64009.3-64030.6" + wire width 13 $1\SHIFT_ROT_function_unit[12:0] + attribute \src "libresoc.v:64053.3-64074.6" + wire width 4 $1\SHIFT_ROT_in2_sel[3:0] + attribute \src "libresoc.v:64031.3-64052.6" + wire width 7 $1\SHIFT_ROT_internal_op[6:0] + attribute \src "libresoc.v:63921.3-63942.6" + wire $1\SHIFT_ROT_inv_a[0:0] + attribute \src "libresoc.v:63965.3-63986.6" + wire $1\SHIFT_ROT_is_32b[0:0] + attribute \src "libresoc.v:64119.3-64140.6" + wire width 2 $1\SHIFT_ROT_rc_sel[1:0] + attribute \src "libresoc.v:63987.3-64008.6" + wire $1\SHIFT_ROT_sgn[0:0] + attribute \src "libresoc.v:63892.17-63892.211" + wire width 32 $ternary$libresoc.v:63892$3540_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:504" + wire width 32 \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \A_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \A_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \A_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \A_FRC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \A_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \A_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \A_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \A_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \A_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \A_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \B_AA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 14 \B_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \B_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \B_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \B_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DQE_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DQE_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 2 \DQE_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 12 \DQ_DQ + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 4 \DQ_PT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DQ_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DQ_RTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DQ_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \DQ_SX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \DQ_SX_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DQ_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \DQ_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \DQ_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 3 \DQ_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 14 \DS_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DS_FRSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DS_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DS_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DS_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DS_RSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DS_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DS_VRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DS_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 2 \DS_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DX_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 10 \DX_d0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 16 \DX_d0_d1_d2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DX_d1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \DX_d2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 3 \D_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 16 \D_D + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \D_FRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \D_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \D_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \D_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \D_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \D_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 16 \D_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \D_TO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 16 \D_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 3 \EVS_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \I_AA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 24 \I_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \I_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \MDS_IB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \MDS_IS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \MDS_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \MDS_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \MDS_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \MDS_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 4 \MDS_XBI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 4 \MDS_XBI_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 4 \MDS_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \MDS_mb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \MDS_me + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \MD_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \MD_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \MD_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 3 \MD_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \MD_mb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \MD_me + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \MD_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \M_MB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \M_ME + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \M_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \M_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \M_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \M_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \M_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 7 \SC_LEV + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \SC_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 2 \SC_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire \SHIFT_ROT_AA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 output 24 \SHIFT_ROT_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 output 23 \SHIFT_ROT_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 output 29 \SHIFT_ROT_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 14 output 22 \SHIFT_ROT_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 3 \SHIFT_ROT_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 2 \SHIFT_ROT_BH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 output 27 \SHIFT_ROT_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \SHIFT_ROT_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 output 25 \SHIFT_ROT_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 10 \SHIFT_ROT_CR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 16 \SHIFT_ROT_D + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 14 output 28 \SHIFT_ROT_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 8 output 26 \SHIFT_ROT_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire \SHIFT_ROT_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 24 output 19 \SHIFT_ROT_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire \SHIFT_ROT_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \SHIFT_ROT_MB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \SHIFT_ROT_MB32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \SHIFT_ROT_ME + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \SHIFT_ROT_ME32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire output 21 \SHIFT_ROT_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \SHIFT_ROT_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \SHIFT_ROT_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \SHIFT_ROT_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \SHIFT_ROT_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire output 20 \SHIFT_ROT_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \SHIFT_ROT_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 output 17 \SHIFT_ROT_SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 16 output 15 \SHIFT_ROT_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 10 output 7 \SHIFT_ROT_SPR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \SHIFT_ROT_TO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 16 output 16 \SHIFT_ROT_UI + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 4 \SHIFT_ROT_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 5 \SHIFT_ROT_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 11 \SHIFT_ROT_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 12 \SHIFT_ROT_cry_out + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \SHIFT_ROT_dec30_SHIFT_ROT_dec30_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \SHIFT_ROT_dec30_SHIFT_ROT_dec30_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \SHIFT_ROT_dec30_SHIFT_ROT_dec30_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \SHIFT_ROT_dec30_SHIFT_ROT_dec30_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 13 \SHIFT_ROT_dec30_SHIFT_ROT_dec30_function_unit + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 \SHIFT_ROT_dec30_SHIFT_ROT_dec30_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 \SHIFT_ROT_dec30_SHIFT_ROT_dec30_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \SHIFT_ROT_dec30_SHIFT_ROT_dec30_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \SHIFT_ROT_dec30_SHIFT_ROT_dec30_is_32b + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \SHIFT_ROT_dec30_SHIFT_ROT_dec30_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \SHIFT_ROT_dec30_SHIFT_ROT_dec30_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + wire width 32 \SHIFT_ROT_dec30_opcode_in + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \SHIFT_ROT_dec31_SHIFT_ROT_dec31_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \SHIFT_ROT_dec31_SHIFT_ROT_dec31_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \SHIFT_ROT_dec31_SHIFT_ROT_dec31_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \SHIFT_ROT_dec31_SHIFT_ROT_dec31_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 13 \SHIFT_ROT_dec31_SHIFT_ROT_dec31_function_unit + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 \SHIFT_ROT_dec31_SHIFT_ROT_dec31_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 \SHIFT_ROT_dec31_SHIFT_ROT_dec31_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \SHIFT_ROT_dec31_SHIFT_ROT_dec31_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \SHIFT_ROT_dec31_SHIFT_ROT_dec31_is_32b + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \SHIFT_ROT_dec31_SHIFT_ROT_dec31_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \SHIFT_ROT_dec31_SHIFT_ROT_dec31_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + wire width 32 \SHIFT_ROT_dec31_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 13 output 8 \SHIFT_ROT_function_unit + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 9 \SHIFT_ROT_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 output 6 \SHIFT_ROT_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 10 \SHIFT_ROT_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 13 \SHIFT_ROT_is_32b + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 3 \SHIFT_ROT_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 14 \SHIFT_ROT_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 6 output 18 \SHIFT_ROT_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \SVL_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \SVL_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \SVL_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \SVL_SVi + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \SVL_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \SVL_ms + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \SVL_vs + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \TX_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \TX_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 4 \TX_XBI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \TX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \VA_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \VA_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \VA_RC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \VA_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 4 \VA_SHB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \VA_VRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \VA_VRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \VA_VRC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \VA_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \VA_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \VC_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \VC_VRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \VC_VRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \VC_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 10 \VC_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \VX_EO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \VX_PS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \VX_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \VX_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \VX_SIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \VX_UIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 4 \VX_UIM_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 3 \VX_UIM_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 2 \VX_UIM_3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \VX_VRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \VX_VRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \VX_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 10 \VX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 11 \VX_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 8 \XFL_FLM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \XFL_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \XFL_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \XFL_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \XFL_W + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 10 \XFL_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 10 \XFX_BHRBE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \XFX_DUI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 10 \XFX_DUIS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 8 \XFX_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \XFX_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \XFX_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 10 \XFX_SPR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 10 \XFX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \XL_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \XL_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 3 \XL_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 3 \XL_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 2 \XL_BH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \XL_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \XL_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \XL_BO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 output 32 \XL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \XL_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 15 \XL_OC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \XL_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 10 \XL_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \XO_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \XO_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \XO_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \XO_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \XO_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 9 \XO_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \XS_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \XS_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \XS_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 9 \XS_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \XS_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \XX2_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 3 \XX2_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \XX2_BX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \XX2_BX_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 7 \XX2_DCMX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \XX2_EO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \XX2_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \XX2_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \XX2_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \XX2_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 4 \XX2_UIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 2 \XX2_UIM_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 7 \XX2_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 9 \XX2_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \XX2_dc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 7 \XX2_dc_dm_dx + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \XX2_dm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \XX2_dx + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \XX3_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \XX3_AX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \XX3_AX_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \XX3_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 3 \XX3_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \XX3_BX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \XX3_BX_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 2 \XX3_DM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \XX3_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 2 \XX3_SHW + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \XX3_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \XX3_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \XX3_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 4 \XX3_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 8 \XX3_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 9 \XX3_XO_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \XX4_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \XX4_AX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \XX4_AX_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \XX4_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \XX4_BX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \XX4_BX_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \XX4_C + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \XX4_CX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \XX4_CX_C + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \XX4_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \XX4_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \XX4_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 2 \XX4_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \X_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 3 output 30 \X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 3 output 31 \X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 4 \X_CT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 7 \X_DCMX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 3 \X_DRM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \X_E + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 2 \X_EO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_EO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \X_EX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 4 \X_E_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_FC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_FRAp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_FRBp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_FRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_FRSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 3 \X_IH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 8 \X_IMM8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \X_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \X_L1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 2 \X_L2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 2 \X_L3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_MO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_NB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \X_PRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \X_R + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 2 \X_RIC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 2 \X_RM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \X_RO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_RSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_RTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \X_R_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \X_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 2 \X_SP + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 4 \X_SR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \X_SX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \X_SX_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 10 \X_TBR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_TH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_TO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \X_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \X_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 4 \X_U + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_UIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_VRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \X_W + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 2 \X_WC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 10 \X_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 8 \X_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 3 \Z22_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \Z22_DCM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \Z22_DGM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \Z22_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \Z22_FRAp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \Z22_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \Z22_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \Z22_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \Z22_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 9 \Z22_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \Z23_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \Z23_FRAp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \Z23_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \Z23_FRBp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \Z23_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \Z23_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \Z23_R + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 2 \Z23_RMC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \Z23_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \Z23_TE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 8 \Z23_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \all_OPCD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \all_PO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" + wire input 1 \bigendian + attribute \src "libresoc.v:62753.7-62753.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + wire width 32 output 2 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + wire width 6 \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 32 input 33 \raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:504" + cell $mux $ternary$libresoc.v:63892$3540 + parameter \WIDTH 32 + connect \A \raw_opcode_in + connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } + connect \S \bigendian + connect \Y $ternary$libresoc.v:63892$3540_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:63893.19-63906.4" + cell \SHIFT_ROT_dec30 \SHIFT_ROT_dec30 + connect \SHIFT_ROT_dec30_cr_in \SHIFT_ROT_dec30_SHIFT_ROT_dec30_cr_in + connect \SHIFT_ROT_dec30_cr_out \SHIFT_ROT_dec30_SHIFT_ROT_dec30_cr_out + connect \SHIFT_ROT_dec30_cry_in \SHIFT_ROT_dec30_SHIFT_ROT_dec30_cry_in + connect \SHIFT_ROT_dec30_cry_out \SHIFT_ROT_dec30_SHIFT_ROT_dec30_cry_out + connect \SHIFT_ROT_dec30_function_unit \SHIFT_ROT_dec30_SHIFT_ROT_dec30_function_unit + connect \SHIFT_ROT_dec30_in2_sel \SHIFT_ROT_dec30_SHIFT_ROT_dec30_in2_sel + connect \SHIFT_ROT_dec30_internal_op \SHIFT_ROT_dec30_SHIFT_ROT_dec30_internal_op + connect \SHIFT_ROT_dec30_inv_a \SHIFT_ROT_dec30_SHIFT_ROT_dec30_inv_a + connect \SHIFT_ROT_dec30_is_32b \SHIFT_ROT_dec30_SHIFT_ROT_dec30_is_32b + connect \SHIFT_ROT_dec30_rc_sel \SHIFT_ROT_dec30_SHIFT_ROT_dec30_rc_sel + connect \SHIFT_ROT_dec30_sgn \SHIFT_ROT_dec30_SHIFT_ROT_dec30_sgn + connect \opcode_in \SHIFT_ROT_dec30_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:63907.19-63920.4" + cell \SHIFT_ROT_dec31 \SHIFT_ROT_dec31 + connect \SHIFT_ROT_dec31_cr_in \SHIFT_ROT_dec31_SHIFT_ROT_dec31_cr_in + connect \SHIFT_ROT_dec31_cr_out \SHIFT_ROT_dec31_SHIFT_ROT_dec31_cr_out + connect \SHIFT_ROT_dec31_cry_in \SHIFT_ROT_dec31_SHIFT_ROT_dec31_cry_in + connect \SHIFT_ROT_dec31_cry_out \SHIFT_ROT_dec31_SHIFT_ROT_dec31_cry_out + connect \SHIFT_ROT_dec31_function_unit \SHIFT_ROT_dec31_SHIFT_ROT_dec31_function_unit + connect \SHIFT_ROT_dec31_in2_sel \SHIFT_ROT_dec31_SHIFT_ROT_dec31_in2_sel + connect \SHIFT_ROT_dec31_internal_op \SHIFT_ROT_dec31_SHIFT_ROT_dec31_internal_op + connect \SHIFT_ROT_dec31_inv_a \SHIFT_ROT_dec31_SHIFT_ROT_dec31_inv_a + connect \SHIFT_ROT_dec31_is_32b \SHIFT_ROT_dec31_SHIFT_ROT_dec31_is_32b + connect \SHIFT_ROT_dec31_rc_sel \SHIFT_ROT_dec31_SHIFT_ROT_dec31_rc_sel + connect \SHIFT_ROT_dec31_sgn \SHIFT_ROT_dec31_SHIFT_ROT_dec31_sgn + connect \opcode_in \SHIFT_ROT_dec31_opcode_in + end + attribute \src "libresoc.v:62753.7-62753.20" + process $proc$libresoc.v:62753$3552 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:63921.3-63942.6" + process $proc$libresoc.v:63921$3541 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_inv_a[0:0] $1\SHIFT_ROT_inv_a[0:0] + attribute \src "libresoc.v:63922.5-63922.29" + switch \initial + attribute \src "libresoc.v:63922.9-63922.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\SHIFT_ROT_inv_a[0:0] \SHIFT_ROT_dec30_SHIFT_ROT_dec30_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\SHIFT_ROT_inv_a[0:0] \SHIFT_ROT_dec31_SHIFT_ROT_dec31_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\SHIFT_ROT_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\SHIFT_ROT_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\SHIFT_ROT_inv_a[0:0] 1'0 + case + assign $1\SHIFT_ROT_inv_a[0:0] 1'0 + end + sync always + update \SHIFT_ROT_inv_a $0\SHIFT_ROT_inv_a[0:0] + end + attribute \src "libresoc.v:63943.3-63964.6" + process $proc$libresoc.v:63943$3542 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_cry_out[0:0] $1\SHIFT_ROT_cry_out[0:0] + attribute \src "libresoc.v:63944.5-63944.29" + switch \initial + attribute \src "libresoc.v:63944.9-63944.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\SHIFT_ROT_cry_out[0:0] \SHIFT_ROT_dec30_SHIFT_ROT_dec30_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\SHIFT_ROT_cry_out[0:0] \SHIFT_ROT_dec31_SHIFT_ROT_dec31_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\SHIFT_ROT_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\SHIFT_ROT_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\SHIFT_ROT_cry_out[0:0] 1'0 + case + assign $1\SHIFT_ROT_cry_out[0:0] 1'0 + end + sync always + update \SHIFT_ROT_cry_out $0\SHIFT_ROT_cry_out[0:0] + end + attribute \src "libresoc.v:63965.3-63986.6" + process $proc$libresoc.v:63965$3543 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_is_32b[0:0] $1\SHIFT_ROT_is_32b[0:0] + attribute \src "libresoc.v:63966.5-63966.29" + switch \initial + attribute \src "libresoc.v:63966.9-63966.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\SHIFT_ROT_is_32b[0:0] \SHIFT_ROT_dec30_SHIFT_ROT_dec30_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\SHIFT_ROT_is_32b[0:0] \SHIFT_ROT_dec31_SHIFT_ROT_dec31_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\SHIFT_ROT_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\SHIFT_ROT_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\SHIFT_ROT_is_32b[0:0] 1'1 + case + assign $1\SHIFT_ROT_is_32b[0:0] 1'0 + end + sync always + update \SHIFT_ROT_is_32b $0\SHIFT_ROT_is_32b[0:0] + end + attribute \src "libresoc.v:63987.3-64008.6" + process $proc$libresoc.v:63987$3544 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_sgn[0:0] $1\SHIFT_ROT_sgn[0:0] + attribute \src "libresoc.v:63988.5-63988.29" + switch \initial + attribute \src "libresoc.v:63988.9-63988.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\SHIFT_ROT_sgn[0:0] \SHIFT_ROT_dec30_SHIFT_ROT_dec30_sgn + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\SHIFT_ROT_sgn[0:0] \SHIFT_ROT_dec31_SHIFT_ROT_dec31_sgn + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\SHIFT_ROT_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\SHIFT_ROT_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\SHIFT_ROT_sgn[0:0] 1'0 + case + assign $1\SHIFT_ROT_sgn[0:0] 1'0 + end + sync always + update \SHIFT_ROT_sgn $0\SHIFT_ROT_sgn[0:0] + end + attribute \src "libresoc.v:64009.3-64030.6" + process $proc$libresoc.v:64009$3545 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_function_unit[12:0] $1\SHIFT_ROT_function_unit[12:0] + attribute \src "libresoc.v:64010.5-64010.29" + switch \initial + attribute \src "libresoc.v:64010.9-64010.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\SHIFT_ROT_function_unit[12:0] \SHIFT_ROT_dec30_SHIFT_ROT_dec30_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\SHIFT_ROT_function_unit[12:0] \SHIFT_ROT_dec31_SHIFT_ROT_dec31_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\SHIFT_ROT_function_unit[12:0] 13'0000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\SHIFT_ROT_function_unit[12:0] 13'0000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\SHIFT_ROT_function_unit[12:0] 13'0000000001000 + case + assign $1\SHIFT_ROT_function_unit[12:0] 13'0000000000000 + end + sync always + update \SHIFT_ROT_function_unit $0\SHIFT_ROT_function_unit[12:0] + end + attribute \src "libresoc.v:64031.3-64052.6" + process $proc$libresoc.v:64031$3546 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_internal_op[6:0] $1\SHIFT_ROT_internal_op[6:0] + attribute \src "libresoc.v:64032.5-64032.29" + switch \initial + attribute \src "libresoc.v:64032.9-64032.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\SHIFT_ROT_internal_op[6:0] \SHIFT_ROT_dec30_SHIFT_ROT_dec30_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\SHIFT_ROT_internal_op[6:0] \SHIFT_ROT_dec31_SHIFT_ROT_dec31_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\SHIFT_ROT_internal_op[6:0] 7'0111000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\SHIFT_ROT_internal_op[6:0] 7'0111000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\SHIFT_ROT_internal_op[6:0] 7'0111000 + case + assign $1\SHIFT_ROT_internal_op[6:0] 7'0000000 + end + sync always + update \SHIFT_ROT_internal_op $0\SHIFT_ROT_internal_op[6:0] + end + attribute \src "libresoc.v:64053.3-64074.6" + process $proc$libresoc.v:64053$3547 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_in2_sel[3:0] $1\SHIFT_ROT_in2_sel[3:0] + attribute \src "libresoc.v:64054.5-64054.29" + switch \initial + attribute \src "libresoc.v:64054.9-64054.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\SHIFT_ROT_in2_sel[3:0] \SHIFT_ROT_dec30_SHIFT_ROT_dec30_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\SHIFT_ROT_in2_sel[3:0] \SHIFT_ROT_dec31_SHIFT_ROT_dec31_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\SHIFT_ROT_in2_sel[3:0] 4'1011 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\SHIFT_ROT_in2_sel[3:0] 4'1011 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\SHIFT_ROT_in2_sel[3:0] 4'0001 + case + assign $1\SHIFT_ROT_in2_sel[3:0] 4'0000 + end + sync always + update \SHIFT_ROT_in2_sel $0\SHIFT_ROT_in2_sel[3:0] + end + attribute \src "libresoc.v:64075.3-64096.6" + process $proc$libresoc.v:64075$3548 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_cr_in[2:0] $1\SHIFT_ROT_cr_in[2:0] + attribute \src "libresoc.v:64076.5-64076.29" + switch \initial + attribute \src "libresoc.v:64076.9-64076.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\SHIFT_ROT_cr_in[2:0] \SHIFT_ROT_dec30_SHIFT_ROT_dec30_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\SHIFT_ROT_cr_in[2:0] \SHIFT_ROT_dec31_SHIFT_ROT_dec31_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\SHIFT_ROT_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\SHIFT_ROT_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\SHIFT_ROT_cr_in[2:0] 3'000 + case + assign $1\SHIFT_ROT_cr_in[2:0] 3'000 + end + sync always + update \SHIFT_ROT_cr_in $0\SHIFT_ROT_cr_in[2:0] + end + attribute \src "libresoc.v:64097.3-64118.6" + process $proc$libresoc.v:64097$3549 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_cr_out[2:0] $1\SHIFT_ROT_cr_out[2:0] + attribute \src "libresoc.v:64098.5-64098.29" + switch \initial + attribute \src "libresoc.v:64098.9-64098.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\SHIFT_ROT_cr_out[2:0] \SHIFT_ROT_dec30_SHIFT_ROT_dec30_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\SHIFT_ROT_cr_out[2:0] \SHIFT_ROT_dec31_SHIFT_ROT_dec31_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\SHIFT_ROT_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\SHIFT_ROT_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\SHIFT_ROT_cr_out[2:0] 3'001 + case + assign $1\SHIFT_ROT_cr_out[2:0] 3'000 + end + sync always + update \SHIFT_ROT_cr_out $0\SHIFT_ROT_cr_out[2:0] + end + attribute \src "libresoc.v:64119.3-64140.6" + process $proc$libresoc.v:64119$3550 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_rc_sel[1:0] $1\SHIFT_ROT_rc_sel[1:0] + attribute \src "libresoc.v:64120.5-64120.29" + switch \initial + attribute \src "libresoc.v:64120.9-64120.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\SHIFT_ROT_rc_sel[1:0] \SHIFT_ROT_dec30_SHIFT_ROT_dec30_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\SHIFT_ROT_rc_sel[1:0] \SHIFT_ROT_dec31_SHIFT_ROT_dec31_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\SHIFT_ROT_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\SHIFT_ROT_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\SHIFT_ROT_rc_sel[1:0] 2'10 + case + assign $1\SHIFT_ROT_rc_sel[1:0] 2'00 + end + sync always + update \SHIFT_ROT_rc_sel $0\SHIFT_ROT_rc_sel[1:0] + end + attribute \src "libresoc.v:64141.3-64162.6" + process $proc$libresoc.v:64141$3551 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_cry_in[1:0] $1\SHIFT_ROT_cry_in[1:0] + attribute \src "libresoc.v:64142.5-64142.29" + switch \initial + attribute \src "libresoc.v:64142.9-64142.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\SHIFT_ROT_cry_in[1:0] \SHIFT_ROT_dec30_SHIFT_ROT_dec30_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\SHIFT_ROT_cry_in[1:0] \SHIFT_ROT_dec31_SHIFT_ROT_dec31_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\SHIFT_ROT_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\SHIFT_ROT_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\SHIFT_ROT_cry_in[1:0] 2'00 + case + assign $1\SHIFT_ROT_cry_in[1:0] 2'00 + end + sync always + update \SHIFT_ROT_cry_in $0\SHIFT_ROT_cry_in[1:0] + end + connect \$1 $ternary$libresoc.v:63892$3540_Y + connect \VC_XO \opcode_in [9:0] + connect \VC_VRT \opcode_in [25:21] + connect \VC_VRB \opcode_in [15:11] + connect \VC_VRA \opcode_in [20:16] + connect \VC_Rc \opcode_in [10] + connect \XS_XO \opcode_in [10:2] + connect \XS_sh { \opcode_in [1] \opcode_in [15:11] } + connect \XS_RS \opcode_in [25:21] + connect \XS_Rc \opcode_in [0] + connect \XS_RA \opcode_in [20:16] + connect \VA_XO \opcode_in [5:0] + connect \VA_VRT \opcode_in [25:21] + connect \VA_VRC \opcode_in [10:6] + connect \VA_VRB \opcode_in [15:11] + connect \VA_VRA \opcode_in [20:16] + connect \VA_SHB \opcode_in [9:6] + connect \VA_RT \opcode_in [25:21] + connect \VA_RC \opcode_in [10:6] + connect \VA_RB \opcode_in [15:11] + connect \VA_RA \opcode_in [20:16] + connect \TX_XO \opcode_in [6:1] + connect \TX_XBI \opcode_in [10:7] + connect \TX_UI \opcode_in [15:11] + connect \TX_RA \opcode_in [20:16] + connect \DQE_XO \opcode_in [1:0] + connect \DQE_RT \opcode_in [25:21] + connect \DQE_RA \opcode_in [20:16] + connect \XO_XO \opcode_in [9:1] + connect \XO_RT \opcode_in [25:21] + connect \XO_Rc \opcode_in [0] + connect \XO_RB \opcode_in [15:11] + connect \XO_RA \opcode_in [20:16] + connect \XO_OE \opcode_in [10] + connect \all_PO \opcode_in [31:26] + connect \all_OPCD \opcode_in [31:26] + connect \SVL_XO \opcode_in [5:1] + connect \SVL_vs \opcode_in [7] + connect \SVL_SVi \opcode_in [15:10] + connect \SVL_RT \opcode_in [25:21] + connect \SVL_Rc \opcode_in [0] + connect \SVL_RA \opcode_in [20:16] + connect \SVL_ms \opcode_in [6] + connect \MD_XO \opcode_in [4:2] + connect \MD_sh { \opcode_in [1] \opcode_in [15:11] } + connect \MD_RS \opcode_in [25:21] + connect \MD_Rc \opcode_in [0] + connect \MD_RA \opcode_in [20:16] + connect \MD_me \opcode_in [10:5] + connect \MD_mb \opcode_in [10:5] + connect \M_SH \opcode_in [15:11] + connect \M_RS \opcode_in [25:21] + connect \M_Rc \opcode_in [0] + connect \M_RB \opcode_in [15:11] + connect \M_RA \opcode_in [20:16] + connect \M_ME \opcode_in [5:1] + connect \M_MB \opcode_in [10:6] + connect \SC_XO_1 \opcode_in [1:0] + connect \SC_XO \opcode_in [1] + connect \SC_LEV \opcode_in [11:5] + connect \MDS_XO \opcode_in [4:1] + connect \MDS_XBI_1 \opcode_in [10:7] + connect \MDS_XBI \opcode_in [10:7] + connect \MDS_RS \opcode_in [25:21] + connect \MDS_Rc \opcode_in [0] + connect \MDS_RB \opcode_in [15:11] + connect \MDS_RA \opcode_in [20:16] + connect \MDS_me \opcode_in [10:5] + connect \MDS_mb \opcode_in [10:5] + connect \MDS_IS \opcode_in [25:21] + connect \MDS_IB \opcode_in [15:11] + connect \Z23_XO \opcode_in [8:1] + connect \Z23_TE \opcode_in [20:16] + connect \Z23_RMC \opcode_in [10:9] + connect \Z23_Rc \opcode_in [0] + connect \Z23_R \opcode_in [16] + connect \Z23_FRTp \opcode_in [25:21] + connect \Z23_FRT \opcode_in [25:21] + connect \Z23_FRBp \opcode_in [15:11] + connect \Z23_FRB \opcode_in [15:11] + connect \Z23_FRAp \opcode_in [20:16] + connect \Z23_FRA \opcode_in [20:16] + connect \XFL_XO \opcode_in [10:1] + connect \XFL_W \opcode_in [16] + connect \XFL_Rc \opcode_in [0] + connect \XFL_L \opcode_in [25] + connect \XFL_FRB \opcode_in [15:11] + connect \XFL_FLM \opcode_in [24:17] + connect \VX_XO_1 \opcode_in [10:0] + connect \VX_XO { \opcode_in [10] \opcode_in [8:0] } + connect \VX_VRT \opcode_in [25:21] + connect \VX_VRB \opcode_in [15:11] + connect \VX_VRA \opcode_in [20:16] + connect \VX_UIM_3 \opcode_in [17:16] + connect \VX_UIM_2 \opcode_in [18:16] + connect \VX_UIM_1 \opcode_in [19:16] + connect \VX_UIM \opcode_in [20:16] + connect \VX_SIM \opcode_in [20:16] + connect \VX_RT \opcode_in [25:21] + connect \VX_RA \opcode_in [20:16] + connect \VX_PS \opcode_in [9] + connect \VX_EO \opcode_in [20:16] + connect \DS_XO \opcode_in [1:0] + connect \DS_VRT \opcode_in [25:21] + connect \DS_VRS \opcode_in [25:21] + connect \DS_RT \opcode_in [25:21] + connect \DS_RSp \opcode_in [25:21] + connect \DS_RS \opcode_in [25:21] + connect \DS_RA \opcode_in [20:16] + connect \DS_FRTp \opcode_in [25:21] + connect \DS_FRSp \opcode_in [25:21] + connect \DS_DS \opcode_in [15:2] + connect \DQ_XO \opcode_in [2:0] + connect \DQ_TX_T { \opcode_in [3] \opcode_in [25:21] } + connect \DQ_T \opcode_in [25:21] + connect \DQ_TX \opcode_in [3] + connect \DQ_SX_S { \opcode_in [3] \opcode_in [25:21] } + connect \DQ_S \opcode_in [25:21] + connect \DQ_SX \opcode_in [3] + connect \DQ_RTp \opcode_in [25:21] + connect \DQ_RA \opcode_in [20:16] + connect \DQ_PT \opcode_in [3:0] + connect \DQ_DQ \opcode_in [15:4] + connect \DX_XO \opcode_in [5:1] + connect \DX_RT \opcode_in [25:21] + connect \DX_d0_d1_d2 { \opcode_in [15:6] \opcode_in [20:16] \opcode_in [0] } + connect \DX_d2 \opcode_in [0] + connect \DX_d1 \opcode_in [20:16] + connect \DX_d0 \opcode_in [15:6] + connect \XFX_XO \opcode_in [10:1] + connect \XFX_SPR \opcode_in [20:11] + connect \XFX_RT \opcode_in [25:21] + connect \XFX_RS \opcode_in [25:21] + connect \XFX_FXM \opcode_in [19:12] + connect \XFX_DUIS \opcode_in [20:11] + connect \XFX_DUI \opcode_in [25:21] + connect \XFX_BHRBE \opcode_in [20:11] + connect \EVS_BFA \opcode_in [2:0] + connect \Z22_XO \opcode_in [9:1] + connect \Z22_SH \opcode_in [15:10] + connect \Z22_Rc \opcode_in [0] + connect \Z22_FRTp \opcode_in [25:21] + connect \Z22_FRT \opcode_in [25:21] + connect \Z22_FRAp \opcode_in [20:16] + connect \Z22_FRA \opcode_in [20:16] + connect \Z22_DGM \opcode_in [15:10] + connect \Z22_DCM \opcode_in [15:10] + connect \Z22_BF \opcode_in [25:23] + connect \XX2_XO_1 \opcode_in [10:2] + connect \XX2_XO { \opcode_in [10:7] \opcode_in [5:3] } + connect \XX2_UIM_1 \opcode_in [17:16] + connect \XX2_UIM \opcode_in [19:16] + connect \XX2_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX2_T \opcode_in [25:21] + connect \XX2_TX \opcode_in [0] + connect \XX2_RT \opcode_in [25:21] + connect \XX2_EO \opcode_in [20:16] + connect \XX2_DCMX \opcode_in [22:16] + connect \XX2_dc_dm_dx { \opcode_in [6] \opcode_in [2] \opcode_in [20:16] } + connect \XX2_dx \opcode_in [20:16] + connect \XX2_dm \opcode_in [2] + connect \XX2_dc \opcode_in [6] + connect \XX2_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX2_B \opcode_in [15:11] + connect \XX2_BX \opcode_in [1] + connect \XX2_BF \opcode_in [25:23] + connect \D_UI \opcode_in [15:0] + connect \D_TO \opcode_in [25:21] + connect \D_SI \opcode_in [15:0] + connect \D_RT \opcode_in [25:21] + connect \D_RS \opcode_in [25:21] + connect \D_RA \opcode_in [20:16] + connect \D_L \opcode_in [21] + connect \D_FRT \opcode_in [25:21] + connect \D_FRS \opcode_in [25:21] + connect \D_D \opcode_in [15:0] + connect \D_BF \opcode_in [25:23] + connect \A_XO \opcode_in [5:1] + connect \A_RT \opcode_in [25:21] + connect \A_Rc \opcode_in [0] + connect \A_RB \opcode_in [15:11] + connect \A_RA \opcode_in [20:16] + connect \A_FRT \opcode_in [25:21] + connect \A_FRC \opcode_in [10:6] + connect \A_FRB \opcode_in [15:11] + connect \A_FRA \opcode_in [20:16] + connect \A_BC \opcode_in [10:6] + connect \XL_XO \opcode_in [10:1] + connect \XL_S \opcode_in [11] + connect \XL_OC \opcode_in [25:11] + connect \XL_LK \opcode_in [0] + connect \XL_BT \opcode_in [25:21] + connect \XL_BO_1 \opcode_in [25:21] + connect \XL_BO \opcode_in [25:21] + connect \XL_BI \opcode_in [20:16] + connect \XL_BH \opcode_in [12:11] + connect \XL_BFA \opcode_in [20:18] + connect \XL_BF \opcode_in [25:23] + connect \XL_BB \opcode_in [15:11] + connect \XL_BA \opcode_in [20:16] + connect \XX4_XO \opcode_in [5:4] + connect \XX4_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX4_T \opcode_in [25:21] + connect \XX4_TX \opcode_in [0] + connect \XX4_CX_C { \opcode_in [3] \opcode_in [10:6] } + connect \XX4_C \opcode_in [10:6] + connect \XX4_CX \opcode_in [3] + connect \XX4_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX4_B \opcode_in [15:11] + connect \XX4_BX \opcode_in [1] + connect \XX4_AX_A { \opcode_in [2] \opcode_in [20:16] } + connect \XX4_A \opcode_in [20:16] + connect \XX4_AX \opcode_in [2] + connect \XX3_XO_2 \opcode_in [9:1] + connect \XX3_XO_1 \opcode_in [10:3] + connect \XX3_XO \opcode_in [10:7] + connect \XX3_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX3_T \opcode_in [25:21] + connect \XX3_TX \opcode_in [0] + connect \XX3_SHW \opcode_in [9:8] + connect \XX3_Rc \opcode_in [10] + connect \XX3_DM \opcode_in [9:8] + connect \XX3_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX3_B \opcode_in [15:11] + connect \XX3_BX \opcode_in [1] + connect \XX3_BF \opcode_in [25:23] + connect \XX3_AX_A { \opcode_in [2] \opcode_in [20:16] } + connect \XX3_A \opcode_in [20:16] + connect \XX3_AX \opcode_in [2] + connect \I_LK \opcode_in [0] + connect \I_LI \opcode_in [25:2] + connect \I_AA \opcode_in [1] + connect \B_LK \opcode_in [0] + connect \B_BO \opcode_in [25:21] + connect \B_BI \opcode_in [20:16] + connect \B_BD \opcode_in [15:2] + connect \B_AA \opcode_in [1] + connect \X_XO_1 \opcode_in [8:1] + connect \X_XO \opcode_in [10:1] + connect \X_WC \opcode_in [22:21] + connect \X_W \opcode_in [16] + connect \X_VRT \opcode_in [25:21] + connect \X_VRS \opcode_in [25:21] + connect \X_UIM \opcode_in [20:16] + connect \X_U \opcode_in [15:12] + connect \X_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \X_TX \opcode_in [0] + connect \X_TO \opcode_in [25:21] + connect \X_TH \opcode_in [25:21] + connect \X_TBR \opcode_in [20:11] + connect \X_T \opcode_in [25:21] + connect \X_SX_S { \opcode_in [0] \opcode_in [25:21] } + connect \X_SX \opcode_in [0] + connect \X_SR \opcode_in [19:16] + connect \X_SP \opcode_in [20:19] + connect \X_SI \opcode_in [15:11] + connect \X_SH \opcode_in [15:11] + connect \X_S \opcode_in [25:21] + connect \X_RTp \opcode_in [25:21] + connect \X_RT \opcode_in [25:21] + connect \X_RSp \opcode_in [25:21] + connect \X_RS \opcode_in [25:21] + connect \X_RO \opcode_in [0] + connect \X_RM \opcode_in [12:11] + connect \X_RIC \opcode_in [19:18] + connect \X_Rc \opcode_in [0] + connect \X_RB \opcode_in [15:11] + connect \X_RA \opcode_in [20:16] + connect \X_R_1 \opcode_in [16] + connect \X_R \opcode_in [21] + connect \X_PRS \opcode_in [17] + connect \X_NB \opcode_in [15:11] + connect \X_MO \opcode_in [25:21] + connect \X_L3 \opcode_in [17:16] + connect \X_L1 \opcode_in [16] + connect \X_L \opcode_in [21] + connect \X_L2 \opcode_in [22:21] + connect \X_IMM8 \opcode_in [18:11] + connect \X_IH \opcode_in [23:21] + connect \X_FRTp \opcode_in [25:21] + connect \X_FRT \opcode_in [25:21] + connect \X_FRSp \opcode_in [25:21] + connect \X_FRS \opcode_in [25:21] + connect \X_FRBp \opcode_in [15:11] + connect \X_FRB \opcode_in [15:11] + connect \X_FRAp \opcode_in [20:16] + connect \X_FRA \opcode_in [20:16] + connect \X_FC \opcode_in [15:11] + connect \X_EX \opcode_in [0] + connect \X_EO_1 \opcode_in [20:16] + connect \X_EO \opcode_in [20:19] + connect \X_E_1 \opcode_in [19:16] + connect \X_E \opcode_in [15] + connect \X_DRM \opcode_in [13:11] + connect \X_DCMX \opcode_in [22:16] + connect \X_CT \opcode_in [24:21] + connect \X_BO \opcode_in [25:21] + connect \X_BFA \opcode_in [20:18] + connect \X_BF \opcode_in [25:23] + connect \X_A \opcode_in [25] + connect \SHIFT_ROT_SPR \opcode_in [20:11] + connect \SHIFT_ROT_MB \opcode_in [10:6] + connect \SHIFT_ROT_ME \opcode_in [5:1] + connect \SHIFT_ROT_SH \opcode_in [15:11] + connect \SHIFT_ROT_BC \opcode_in [10:6] + connect \SHIFT_ROT_TO \opcode_in [25:21] + connect \SHIFT_ROT_DS \opcode_in [15:2] + connect \SHIFT_ROT_D \opcode_in [15:0] + connect \SHIFT_ROT_BH \opcode_in [12:11] + connect \SHIFT_ROT_BI \opcode_in [20:16] + connect \SHIFT_ROT_BO \opcode_in [25:21] + connect \SHIFT_ROT_FXM \opcode_in [19:12] + connect \SHIFT_ROT_BT \opcode_in [25:21] + connect \SHIFT_ROT_BA \opcode_in [20:16] + connect \SHIFT_ROT_BB \opcode_in [15:11] + connect \SHIFT_ROT_CR \opcode_in [10:1] + connect \SHIFT_ROT_BF \opcode_in [25:23] + connect \SHIFT_ROT_BD \opcode_in [15:2] + connect \SHIFT_ROT_OE \opcode_in [10] + connect \SHIFT_ROT_Rc \opcode_in [0] + connect \SHIFT_ROT_AA \opcode_in [1] + connect \SHIFT_ROT_LK \opcode_in [0] + connect \SHIFT_ROT_LI \opcode_in [25:2] + connect \SHIFT_ROT_ME32 \opcode_in [5:1] + connect \SHIFT_ROT_MB32 \opcode_in [10:6] + connect \SHIFT_ROT_sh { \opcode_in [1] \opcode_in [15:11] } + connect \SHIFT_ROT_SH32 \opcode_in [15:11] + connect \SHIFT_ROT_L \opcode_in [21] + connect \SHIFT_ROT_UI \opcode_in [15:0] + connect \SHIFT_ROT_SI \opcode_in [15:0] + connect \SHIFT_ROT_RB \opcode_in [15:11] + connect \SHIFT_ROT_RA \opcode_in [20:16] + connect \SHIFT_ROT_RT \opcode_in [25:21] + connect \SHIFT_ROT_RS \opcode_in [25:21] + connect \opcode_in \$1 + connect \SHIFT_ROT_dec31_opcode_in \opcode_in + connect \SHIFT_ROT_dec30_opcode_in \opcode_in + connect \opcode_switch \opcode_in [31:26] +end +attribute \src "libresoc.v:64504.1-67006.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec" +attribute \generator "nMigen" +module \dec$195 + attribute \src "libresoc.v:66088.3-66145.6" + wire $0\LDST_br[0:0] + attribute \src "libresoc.v:66552.3-66609.6" + wire width 3 $0\LDST_cr_in[2:0] + attribute \src "libresoc.v:66610.3-66667.6" + wire width 3 $0\LDST_cr_out[2:0] + attribute \src "libresoc.v:66320.3-66377.6" + wire width 13 $0\LDST_function_unit[12:0] + attribute \src "libresoc.v:66436.3-66493.6" + wire width 3 $0\LDST_in1_sel[2:0] + attribute \src "libresoc.v:66494.3-66551.6" + wire width 4 $0\LDST_in2_sel[3:0] + attribute \src "libresoc.v:66378.3-66435.6" + wire width 7 $0\LDST_internal_op[6:0] + attribute \src "libresoc.v:66204.3-66261.6" + wire $0\LDST_is_32b[0:0] + attribute \src "libresoc.v:65914.3-65971.6" + wire width 4 $0\LDST_ldst_len[3:0] + attribute \src "libresoc.v:66030.3-66087.6" + wire width 2 $0\LDST_rc_sel[1:0] + attribute \src "libresoc.v:66262.3-66319.6" + wire $0\LDST_sgn[0:0] + attribute \src "libresoc.v:66146.3-66203.6" + wire $0\LDST_sgn_ext[0:0] + attribute \src "libresoc.v:65972.3-66029.6" + wire width 2 $0\LDST_upd[1:0] + attribute \src "libresoc.v:64505.7-64505.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:66088.3-66145.6" + wire $1\LDST_br[0:0] + attribute \src "libresoc.v:66552.3-66609.6" + wire width 3 $1\LDST_cr_in[2:0] + attribute \src "libresoc.v:66610.3-66667.6" + wire width 3 $1\LDST_cr_out[2:0] + attribute \src "libresoc.v:66320.3-66377.6" + wire width 13 $1\LDST_function_unit[12:0] + attribute \src "libresoc.v:66436.3-66493.6" + wire width 3 $1\LDST_in1_sel[2:0] + attribute \src "libresoc.v:66494.3-66551.6" + wire width 4 $1\LDST_in2_sel[3:0] + attribute \src "libresoc.v:66378.3-66435.6" + wire width 7 $1\LDST_internal_op[6:0] + attribute \src "libresoc.v:66204.3-66261.6" + wire $1\LDST_is_32b[0:0] + attribute \src "libresoc.v:65914.3-65971.6" + wire width 4 $1\LDST_ldst_len[3:0] + attribute \src "libresoc.v:66030.3-66087.6" + wire width 2 $1\LDST_rc_sel[1:0] + attribute \src "libresoc.v:66262.3-66319.6" + wire $1\LDST_sgn[0:0] + attribute \src "libresoc.v:66146.3-66203.6" + wire $1\LDST_sgn_ext[0:0] + attribute \src "libresoc.v:65972.3-66029.6" + wire width 2 $1\LDST_upd[1:0] + attribute \src "libresoc.v:65865.17-65865.211" + wire width 32 $ternary$libresoc.v:65865$3553_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:504" + wire width 32 \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \A_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \A_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \A_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \A_FRC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \A_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \A_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \A_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \A_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \A_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \A_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \B_AA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 14 \B_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \B_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \B_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \B_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DQE_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DQE_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 2 \DQE_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 12 \DQ_DQ + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 4 \DQ_PT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DQ_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DQ_RTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DQ_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \DQ_SX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \DQ_SX_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DQ_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \DQ_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \DQ_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 3 \DQ_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 14 \DS_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DS_FRSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DS_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DS_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DS_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DS_RSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DS_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DS_VRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DS_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 2 \DS_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DX_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 10 \DX_d0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 16 \DX_d0_d1_d2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DX_d1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \DX_d2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 3 \D_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 16 \D_D + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \D_FRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \D_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \D_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \D_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \D_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \D_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 16 \D_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \D_TO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 16 \D_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 3 \EVS_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \I_AA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 24 \I_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \I_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire \LDST_AA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 output 27 \LDST_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 output 26 \LDST_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 output 32 \LDST_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 14 output 25 \LDST_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 3 \LDST_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 2 \LDST_BH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 output 30 \LDST_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \LDST_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 output 28 \LDST_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 10 \LDST_CR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 16 \LDST_D + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 14 output 31 \LDST_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 8 output 29 \LDST_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire \LDST_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 24 output 22 \LDST_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire \LDST_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \LDST_MB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \LDST_MB32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \LDST_ME + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \LDST_ME32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire output 24 \LDST_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 output 17 \LDST_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \LDST_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \LDST_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \LDST_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire output 23 \LDST_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \LDST_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 output 20 \LDST_SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 16 output 18 \LDST_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 10 output 7 \LDST_SPR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \LDST_TO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 16 output 19 \LDST_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 14 \LDST_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 4 \LDST_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 5 \LDST_cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \LDST_dec31_LDST_dec31_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \LDST_dec31_LDST_dec31_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \LDST_dec31_LDST_dec31_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 13 \LDST_dec31_LDST_dec31_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \LDST_dec31_LDST_dec31_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 \LDST_dec31_LDST_dec31_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 \LDST_dec31_LDST_dec31_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \LDST_dec31_LDST_dec31_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 \LDST_dec31_LDST_dec31_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \LDST_dec31_LDST_dec31_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \LDST_dec31_LDST_dec31_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \LDST_dec31_LDST_dec31_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \LDST_dec31_LDST_dec31_upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + wire width 32 \LDST_dec31_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \LDST_dec58_LDST_dec58_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \LDST_dec58_LDST_dec58_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \LDST_dec58_LDST_dec58_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 13 \LDST_dec58_LDST_dec58_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \LDST_dec58_LDST_dec58_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 \LDST_dec58_LDST_dec58_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute 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\enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 \LDST_dec58_LDST_dec58_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \LDST_dec58_LDST_dec58_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 \LDST_dec58_LDST_dec58_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \LDST_dec58_LDST_dec58_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \LDST_dec58_LDST_dec58_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \LDST_dec58_LDST_dec58_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \LDST_dec58_LDST_dec58_upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + wire width 32 \LDST_dec58_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \LDST_dec62_LDST_dec62_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \LDST_dec62_LDST_dec62_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \LDST_dec62_LDST_dec62_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 13 \LDST_dec62_LDST_dec62_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \LDST_dec62_LDST_dec62_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 \LDST_dec62_LDST_dec62_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 \LDST_dec62_LDST_dec62_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \LDST_dec62_LDST_dec62_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 \LDST_dec62_LDST_dec62_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \LDST_dec62_LDST_dec62_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \LDST_dec62_LDST_dec62_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \LDST_dec62_LDST_dec62_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \LDST_dec62_LDST_dec62_upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + wire width 32 \LDST_dec62_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 13 output 8 \LDST_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 9 \LDST_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 10 \LDST_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 output 6 \LDST_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 12 \LDST_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 11 \LDST_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 3 \LDST_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 13 \LDST_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 15 \LDST_sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 6 output 21 \LDST_sh + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 16 \LDST_upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \MDS_IB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \MDS_IS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \MDS_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \MDS_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \MDS_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \MDS_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 4 \MDS_XBI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 4 \MDS_XBI_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 4 \MDS_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \MDS_mb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \MDS_me + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \MD_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \MD_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \MD_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 3 \MD_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \MD_mb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \MD_me + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \MD_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \M_MB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \M_ME + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \M_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \M_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \M_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \M_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \M_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 7 \SC_LEV + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \SC_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 2 \SC_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \SVL_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \SVL_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \SVL_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \SVL_SVi + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \SVL_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \SVL_ms + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \SVL_vs + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \TX_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \TX_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 4 \TX_XBI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \TX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \VA_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \VA_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \VA_RC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \VA_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 4 \VA_SHB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \VA_VRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \VA_VRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \VA_VRC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \VA_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \VA_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \VC_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \VC_VRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \VC_VRB + attribute \src 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \X_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \X_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 4 \X_U + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_UIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_VRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \X_W + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 2 \X_WC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 10 \X_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 8 \X_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 3 \Z22_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \Z22_DCM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \Z22_DGM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \Z22_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \Z22_FRAp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \Z22_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \Z22_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \Z22_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \Z22_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 9 \Z22_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \Z23_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \Z23_FRAp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \Z23_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \Z23_FRBp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \Z23_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \Z23_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \Z23_R + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 2 \Z23_RMC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \Z23_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \Z23_TE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 8 \Z23_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \all_OPCD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \all_PO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" + wire input 1 \bigendian + attribute \src "libresoc.v:64505.7-64505.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + wire width 32 output 2 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + wire width 6 \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 32 input 36 \raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:504" + cell $mux $ternary$libresoc.v:65865$3553 + parameter \WIDTH 32 + connect \A \raw_opcode_in + connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } + connect \S \bigendian + connect \Y $ternary$libresoc.v:65865$3553_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:65866.14-65881.4" + cell \LDST_dec31 \LDST_dec31 + connect \LDST_dec31_br \LDST_dec31_LDST_dec31_br + connect \LDST_dec31_cr_in \LDST_dec31_LDST_dec31_cr_in + connect \LDST_dec31_cr_out \LDST_dec31_LDST_dec31_cr_out + connect \LDST_dec31_function_unit \LDST_dec31_LDST_dec31_function_unit + connect \LDST_dec31_in1_sel \LDST_dec31_LDST_dec31_in1_sel + connect \LDST_dec31_in2_sel \LDST_dec31_LDST_dec31_in2_sel + connect \LDST_dec31_internal_op \LDST_dec31_LDST_dec31_internal_op + connect \LDST_dec31_is_32b \LDST_dec31_LDST_dec31_is_32b + connect \LDST_dec31_ldst_len \LDST_dec31_LDST_dec31_ldst_len + connect \LDST_dec31_rc_sel \LDST_dec31_LDST_dec31_rc_sel + connect \LDST_dec31_sgn \LDST_dec31_LDST_dec31_sgn + connect \LDST_dec31_sgn_ext \LDST_dec31_LDST_dec31_sgn_ext + connect \LDST_dec31_upd \LDST_dec31_LDST_dec31_upd + connect \opcode_in \LDST_dec31_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:65882.14-65897.4" + cell \LDST_dec58 \LDST_dec58 + connect \LDST_dec58_br \LDST_dec58_LDST_dec58_br + connect \LDST_dec58_cr_in \LDST_dec58_LDST_dec58_cr_in + connect \LDST_dec58_cr_out \LDST_dec58_LDST_dec58_cr_out + connect \LDST_dec58_function_unit \LDST_dec58_LDST_dec58_function_unit + connect \LDST_dec58_in1_sel \LDST_dec58_LDST_dec58_in1_sel + connect \LDST_dec58_in2_sel \LDST_dec58_LDST_dec58_in2_sel + connect \LDST_dec58_internal_op \LDST_dec58_LDST_dec58_internal_op + connect \LDST_dec58_is_32b \LDST_dec58_LDST_dec58_is_32b + connect \LDST_dec58_ldst_len \LDST_dec58_LDST_dec58_ldst_len + connect \LDST_dec58_rc_sel \LDST_dec58_LDST_dec58_rc_sel + connect \LDST_dec58_sgn \LDST_dec58_LDST_dec58_sgn + connect \LDST_dec58_sgn_ext \LDST_dec58_LDST_dec58_sgn_ext + connect \LDST_dec58_upd \LDST_dec58_LDST_dec58_upd + connect \opcode_in \LDST_dec58_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:65898.14-65913.4" + cell \LDST_dec62 \LDST_dec62 + connect \LDST_dec62_br \LDST_dec62_LDST_dec62_br + connect \LDST_dec62_cr_in \LDST_dec62_LDST_dec62_cr_in + connect \LDST_dec62_cr_out \LDST_dec62_LDST_dec62_cr_out + connect \LDST_dec62_function_unit \LDST_dec62_LDST_dec62_function_unit + connect \LDST_dec62_in1_sel \LDST_dec62_LDST_dec62_in1_sel + connect \LDST_dec62_in2_sel \LDST_dec62_LDST_dec62_in2_sel + connect \LDST_dec62_internal_op \LDST_dec62_LDST_dec62_internal_op + connect \LDST_dec62_is_32b \LDST_dec62_LDST_dec62_is_32b + connect \LDST_dec62_ldst_len \LDST_dec62_LDST_dec62_ldst_len + connect \LDST_dec62_rc_sel \LDST_dec62_LDST_dec62_rc_sel + connect \LDST_dec62_sgn \LDST_dec62_LDST_dec62_sgn + connect \LDST_dec62_sgn_ext \LDST_dec62_LDST_dec62_sgn_ext + connect \LDST_dec62_upd \LDST_dec62_LDST_dec62_upd + connect \opcode_in \LDST_dec62_opcode_in + end + attribute \src "libresoc.v:64505.7-64505.20" + process $proc$libresoc.v:64505$3567 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:65914.3-65971.6" + process $proc$libresoc.v:65914$3554 + assign { } { } + assign { } { } + assign $0\LDST_ldst_len[3:0] $1\LDST_ldst_len[3:0] + attribute \src "libresoc.v:65915.5-65915.29" + switch \initial + attribute \src "libresoc.v:65915.9-65915.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\LDST_ldst_len[3:0] \LDST_dec31_LDST_dec31_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\LDST_ldst_len[3:0] \LDST_dec58_LDST_dec58_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\LDST_ldst_len[3:0] \LDST_dec62_LDST_dec62_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\LDST_ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\LDST_ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\LDST_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\LDST_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\LDST_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\LDST_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\LDST_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\LDST_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\LDST_ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\LDST_ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\LDST_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\LDST_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\LDST_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\LDST_ldst_len[3:0] 4'0100 + case + assign $1\LDST_ldst_len[3:0] 4'0000 + end + sync always + update \LDST_ldst_len $0\LDST_ldst_len[3:0] + end + attribute \src "libresoc.v:65972.3-66029.6" + process $proc$libresoc.v:65972$3555 + assign { } { } + assign { } { } + assign $0\LDST_upd[1:0] $1\LDST_upd[1:0] + attribute \src "libresoc.v:65973.5-65973.29" + switch \initial + attribute \src "libresoc.v:65973.9-65973.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\LDST_upd[1:0] \LDST_dec31_LDST_dec31_upd + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\LDST_upd[1:0] \LDST_dec58_LDST_dec58_upd + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\LDST_upd[1:0] \LDST_dec62_LDST_dec62_upd + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\LDST_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\LDST_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\LDST_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\LDST_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\LDST_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\LDST_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\LDST_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\LDST_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\LDST_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\LDST_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\LDST_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\LDST_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\LDST_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\LDST_upd[1:0] 2'01 + case + assign $1\LDST_upd[1:0] 2'00 + end + sync always + update \LDST_upd $0\LDST_upd[1:0] + end + attribute \src "libresoc.v:66030.3-66087.6" + process $proc$libresoc.v:66030$3556 + assign { } { } + assign { } { } + assign $0\LDST_rc_sel[1:0] $1\LDST_rc_sel[1:0] + attribute \src "libresoc.v:66031.5-66031.29" + switch \initial + attribute \src "libresoc.v:66031.9-66031.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\LDST_rc_sel[1:0] \LDST_dec31_LDST_dec31_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\LDST_rc_sel[1:0] \LDST_dec58_LDST_dec58_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\LDST_rc_sel[1:0] \LDST_dec62_LDST_dec62_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\LDST_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\LDST_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\LDST_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\LDST_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\LDST_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\LDST_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\LDST_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\LDST_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\LDST_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\LDST_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\LDST_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\LDST_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\LDST_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\LDST_rc_sel[1:0] 2'00 + case + assign $1\LDST_rc_sel[1:0] 2'00 + end + sync always + update \LDST_rc_sel $0\LDST_rc_sel[1:0] + end + attribute \src "libresoc.v:66088.3-66145.6" + process $proc$libresoc.v:66088$3557 + assign { } { } + assign { } { } + assign $0\LDST_br[0:0] $1\LDST_br[0:0] + attribute \src "libresoc.v:66089.5-66089.29" + switch \initial + attribute \src "libresoc.v:66089.9-66089.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\LDST_br[0:0] \LDST_dec31_LDST_dec31_br + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\LDST_br[0:0] \LDST_dec58_LDST_dec58_br + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\LDST_br[0:0] \LDST_dec62_LDST_dec62_br + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\LDST_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\LDST_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\LDST_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\LDST_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\LDST_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\LDST_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\LDST_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\LDST_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\LDST_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\LDST_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\LDST_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\LDST_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\LDST_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\LDST_br[0:0] 1'0 + case + assign $1\LDST_br[0:0] 1'0 + end + sync always + update \LDST_br $0\LDST_br[0:0] + end + attribute \src "libresoc.v:66146.3-66203.6" + process $proc$libresoc.v:66146$3558 + assign { } { } + assign { } { } + assign $0\LDST_sgn_ext[0:0] $1\LDST_sgn_ext[0:0] + attribute \src "libresoc.v:66147.5-66147.29" + switch \initial + attribute \src "libresoc.v:66147.9-66147.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\LDST_sgn_ext[0:0] \LDST_dec31_LDST_dec31_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\LDST_sgn_ext[0:0] \LDST_dec58_LDST_dec58_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\LDST_sgn_ext[0:0] \LDST_dec62_LDST_dec62_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\LDST_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\LDST_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\LDST_sgn_ext[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\LDST_sgn_ext[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\LDST_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\LDST_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\LDST_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\LDST_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\LDST_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\LDST_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\LDST_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\LDST_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\LDST_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\LDST_sgn_ext[0:0] 1'0 + case + assign $1\LDST_sgn_ext[0:0] 1'0 + end + sync always + update \LDST_sgn_ext $0\LDST_sgn_ext[0:0] + end + attribute \src "libresoc.v:66204.3-66261.6" + process $proc$libresoc.v:66204$3559 + assign { } { } + assign { } { } + assign $0\LDST_is_32b[0:0] $1\LDST_is_32b[0:0] + attribute \src "libresoc.v:66205.5-66205.29" + switch \initial + attribute \src "libresoc.v:66205.9-66205.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\LDST_is_32b[0:0] \LDST_dec31_LDST_dec31_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\LDST_is_32b[0:0] \LDST_dec58_LDST_dec58_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\LDST_is_32b[0:0] \LDST_dec62_LDST_dec62_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\LDST_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\LDST_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\LDST_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\LDST_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\LDST_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\LDST_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\LDST_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\LDST_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\LDST_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\LDST_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\LDST_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\LDST_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\LDST_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\LDST_is_32b[0:0] 1'0 + case + assign $1\LDST_is_32b[0:0] 1'0 + end + sync always + update \LDST_is_32b $0\LDST_is_32b[0:0] + end + attribute \src "libresoc.v:66262.3-66319.6" + process $proc$libresoc.v:66262$3560 + assign { } { } + assign { } { } + assign $0\LDST_sgn[0:0] $1\LDST_sgn[0:0] + attribute \src "libresoc.v:66263.5-66263.29" + switch \initial + attribute \src "libresoc.v:66263.9-66263.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\LDST_sgn[0:0] \LDST_dec31_LDST_dec31_sgn + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\LDST_sgn[0:0] \LDST_dec58_LDST_dec58_sgn + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\LDST_sgn[0:0] \LDST_dec62_LDST_dec62_sgn + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\LDST_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\LDST_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\LDST_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\LDST_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\LDST_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\LDST_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\LDST_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\LDST_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\LDST_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\LDST_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\LDST_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\LDST_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\LDST_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\LDST_sgn[0:0] 1'0 + case + assign $1\LDST_sgn[0:0] 1'0 + end + sync always + update \LDST_sgn $0\LDST_sgn[0:0] + end + attribute \src "libresoc.v:66320.3-66377.6" + process $proc$libresoc.v:66320$3561 + assign { } { } + assign { } { } + assign $0\LDST_function_unit[12:0] $1\LDST_function_unit[12:0] + attribute \src "libresoc.v:66321.5-66321.29" + switch \initial + attribute \src "libresoc.v:66321.9-66321.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\LDST_function_unit[12:0] \LDST_dec31_LDST_dec31_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\LDST_function_unit[12:0] \LDST_dec58_LDST_dec58_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\LDST_function_unit[12:0] \LDST_dec62_LDST_dec62_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\LDST_function_unit[12:0] 13'0000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\LDST_function_unit[12:0] 13'0000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\LDST_function_unit[12:0] 13'0000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\LDST_function_unit[12:0] 13'0000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\LDST_function_unit[12:0] 13'0000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\LDST_function_unit[12:0] 13'0000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\LDST_function_unit[12:0] 13'0000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\LDST_function_unit[12:0] 13'0000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\LDST_function_unit[12:0] 13'0000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\LDST_function_unit[12:0] 13'0000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\LDST_function_unit[12:0] 13'0000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\LDST_function_unit[12:0] 13'0000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\LDST_function_unit[12:0] 13'0000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\LDST_function_unit[12:0] 13'0000000000100 + case + assign $1\LDST_function_unit[12:0] 13'0000000000000 + end + sync always + update \LDST_function_unit $0\LDST_function_unit[12:0] + end + attribute \src "libresoc.v:66378.3-66435.6" + process $proc$libresoc.v:66378$3562 + assign { } { } + assign { } { } + assign $0\LDST_internal_op[6:0] $1\LDST_internal_op[6:0] + attribute \src "libresoc.v:66379.5-66379.29" + switch \initial + attribute \src "libresoc.v:66379.9-66379.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\LDST_internal_op[6:0] \LDST_dec31_LDST_dec31_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\LDST_internal_op[6:0] \LDST_dec58_LDST_dec58_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\LDST_internal_op[6:0] \LDST_dec62_LDST_dec62_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\LDST_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\LDST_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\LDST_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\LDST_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\LDST_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\LDST_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\LDST_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\LDST_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\LDST_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\LDST_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\LDST_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\LDST_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\LDST_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\LDST_internal_op[6:0] 7'0100110 + case + assign $1\LDST_internal_op[6:0] 7'0000000 + end + sync always + update \LDST_internal_op $0\LDST_internal_op[6:0] + end + attribute \src "libresoc.v:66436.3-66493.6" + process $proc$libresoc.v:66436$3563 + assign { } { } + assign { } { } + assign $0\LDST_in1_sel[2:0] $1\LDST_in1_sel[2:0] + attribute \src "libresoc.v:66437.5-66437.29" + switch \initial + attribute \src "libresoc.v:66437.9-66437.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\LDST_in1_sel[2:0] \LDST_dec31_LDST_dec31_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\LDST_in1_sel[2:0] \LDST_dec58_LDST_dec58_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\LDST_in1_sel[2:0] \LDST_dec62_LDST_dec62_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\LDST_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\LDST_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\LDST_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\LDST_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\LDST_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\LDST_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\LDST_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\LDST_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\LDST_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\LDST_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\LDST_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\LDST_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\LDST_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\LDST_in1_sel[2:0] 3'010 + case + assign $1\LDST_in1_sel[2:0] 3'000 + end + sync always + update \LDST_in1_sel $0\LDST_in1_sel[2:0] + end + attribute \src "libresoc.v:66494.3-66551.6" + process $proc$libresoc.v:66494$3564 + assign { } { } + assign { } { } + assign $0\LDST_in2_sel[3:0] $1\LDST_in2_sel[3:0] + attribute \src "libresoc.v:66495.5-66495.29" + switch \initial + attribute \src "libresoc.v:66495.9-66495.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\LDST_in2_sel[3:0] \LDST_dec31_LDST_dec31_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\LDST_in2_sel[3:0] \LDST_dec58_LDST_dec58_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\LDST_in2_sel[3:0] \LDST_dec62_LDST_dec62_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\LDST_in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\LDST_in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\LDST_in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\LDST_in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\LDST_in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\LDST_in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\LDST_in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\LDST_in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\LDST_in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\LDST_in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\LDST_in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\LDST_in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\LDST_in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\LDST_in2_sel[3:0] 4'0011 + case + assign $1\LDST_in2_sel[3:0] 4'0000 + end + sync always + update \LDST_in2_sel $0\LDST_in2_sel[3:0] + end + attribute \src "libresoc.v:66552.3-66609.6" + process $proc$libresoc.v:66552$3565 + assign { } { } + assign { } { } + assign $0\LDST_cr_in[2:0] $1\LDST_cr_in[2:0] + attribute \src "libresoc.v:66553.5-66553.29" + switch \initial + attribute \src "libresoc.v:66553.9-66553.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\LDST_cr_in[2:0] \LDST_dec31_LDST_dec31_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\LDST_cr_in[2:0] \LDST_dec58_LDST_dec58_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\LDST_cr_in[2:0] \LDST_dec62_LDST_dec62_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\LDST_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\LDST_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\LDST_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\LDST_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\LDST_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\LDST_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\LDST_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\LDST_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\LDST_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\LDST_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\LDST_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\LDST_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\LDST_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\LDST_cr_in[2:0] 3'000 + case + assign $1\LDST_cr_in[2:0] 3'000 + end + sync always + update \LDST_cr_in $0\LDST_cr_in[2:0] + end + attribute \src "libresoc.v:66610.3-66667.6" + process $proc$libresoc.v:66610$3566 + assign { } { } + assign { } { } + assign $0\LDST_cr_out[2:0] $1\LDST_cr_out[2:0] + attribute \src "libresoc.v:66611.5-66611.29" + switch \initial + attribute \src "libresoc.v:66611.9-66611.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\LDST_cr_out[2:0] \LDST_dec31_LDST_dec31_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\LDST_cr_out[2:0] \LDST_dec58_LDST_dec58_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\LDST_cr_out[2:0] \LDST_dec62_LDST_dec62_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\LDST_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\LDST_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\LDST_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\LDST_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\LDST_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\LDST_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\LDST_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\LDST_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\LDST_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\LDST_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\LDST_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\LDST_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\LDST_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\LDST_cr_out[2:0] 3'000 + case + assign $1\LDST_cr_out[2:0] 3'000 + end + sync always + update \LDST_cr_out $0\LDST_cr_out[2:0] + end + connect \$1 $ternary$libresoc.v:65865$3553_Y + connect \VC_XO \opcode_in [9:0] + connect \VC_VRT \opcode_in [25:21] + connect \VC_VRB \opcode_in [15:11] + connect \VC_VRA \opcode_in [20:16] + connect \VC_Rc \opcode_in [10] + connect \XS_XO \opcode_in [10:2] + connect \XS_sh { \opcode_in [1] \opcode_in [15:11] } + connect \XS_RS \opcode_in [25:21] + connect \XS_Rc \opcode_in [0] + connect \XS_RA \opcode_in [20:16] + connect \VA_XO \opcode_in [5:0] + connect \VA_VRT \opcode_in [25:21] + connect \VA_VRC \opcode_in [10:6] + connect \VA_VRB \opcode_in [15:11] + connect \VA_VRA \opcode_in [20:16] + connect \VA_SHB \opcode_in [9:6] + connect \VA_RT \opcode_in [25:21] + connect \VA_RC \opcode_in [10:6] + connect \VA_RB \opcode_in [15:11] + connect \VA_RA \opcode_in [20:16] + connect \TX_XO \opcode_in [6:1] + connect \TX_XBI \opcode_in [10:7] + connect \TX_UI \opcode_in [15:11] + connect \TX_RA \opcode_in [20:16] + connect \DQE_XO \opcode_in [1:0] + connect \DQE_RT \opcode_in [25:21] + connect \DQE_RA \opcode_in [20:16] + connect \XO_XO \opcode_in [9:1] + connect \XO_RT \opcode_in [25:21] + connect \XO_Rc \opcode_in [0] + connect \XO_RB \opcode_in [15:11] + connect \XO_RA \opcode_in [20:16] + connect \XO_OE \opcode_in [10] + connect \all_PO \opcode_in [31:26] + connect \all_OPCD \opcode_in [31:26] + connect \SVL_XO \opcode_in [5:1] + connect \SVL_vs \opcode_in [7] + connect \SVL_SVi \opcode_in [15:10] + connect \SVL_RT \opcode_in [25:21] + connect \SVL_Rc \opcode_in [0] + connect \SVL_RA \opcode_in [20:16] + connect \SVL_ms \opcode_in [6] + connect \MD_XO \opcode_in [4:2] + connect \MD_sh { \opcode_in [1] \opcode_in [15:11] } + connect \MD_RS \opcode_in [25:21] + connect \MD_Rc \opcode_in [0] + connect \MD_RA \opcode_in [20:16] + connect \MD_me \opcode_in [10:5] + connect \MD_mb \opcode_in [10:5] + connect \M_SH \opcode_in [15:11] + connect \M_RS \opcode_in [25:21] + connect \M_Rc \opcode_in [0] + connect \M_RB \opcode_in [15:11] + connect \M_RA \opcode_in [20:16] + connect \M_ME \opcode_in [5:1] + connect \M_MB \opcode_in [10:6] + connect \SC_XO_1 \opcode_in [1:0] + connect \SC_XO \opcode_in [1] + connect \SC_LEV \opcode_in [11:5] + connect \MDS_XO \opcode_in [4:1] + connect \MDS_XBI_1 \opcode_in [10:7] + connect \MDS_XBI \opcode_in [10:7] + connect \MDS_RS \opcode_in [25:21] + connect \MDS_Rc \opcode_in [0] + connect \MDS_RB \opcode_in [15:11] + connect \MDS_RA \opcode_in [20:16] + connect \MDS_me \opcode_in [10:5] + connect \MDS_mb \opcode_in [10:5] + connect \MDS_IS \opcode_in [25:21] + connect \MDS_IB \opcode_in [15:11] + connect \Z23_XO \opcode_in [8:1] + connect \Z23_TE \opcode_in [20:16] + connect \Z23_RMC \opcode_in [10:9] + connect \Z23_Rc \opcode_in [0] + connect \Z23_R \opcode_in [16] + connect \Z23_FRTp \opcode_in [25:21] + connect \Z23_FRT \opcode_in [25:21] + connect \Z23_FRBp \opcode_in [15:11] + connect \Z23_FRB \opcode_in [15:11] + connect \Z23_FRAp \opcode_in [20:16] + connect \Z23_FRA \opcode_in [20:16] + connect \XFL_XO \opcode_in [10:1] + connect \XFL_W \opcode_in [16] + connect \XFL_Rc \opcode_in [0] + connect \XFL_L \opcode_in [25] + connect \XFL_FRB \opcode_in [15:11] + connect \XFL_FLM \opcode_in [24:17] + connect \VX_XO_1 \opcode_in [10:0] + connect \VX_XO { \opcode_in [10] \opcode_in [8:0] } + connect \VX_VRT \opcode_in [25:21] + connect \VX_VRB \opcode_in [15:11] + connect \VX_VRA \opcode_in [20:16] + connect \VX_UIM_3 \opcode_in [17:16] + connect \VX_UIM_2 \opcode_in [18:16] + connect \VX_UIM_1 \opcode_in [19:16] + connect \VX_UIM \opcode_in [20:16] + connect \VX_SIM \opcode_in [20:16] + connect \VX_RT \opcode_in [25:21] + connect \VX_RA \opcode_in [20:16] + connect \VX_PS \opcode_in [9] + connect \VX_EO \opcode_in [20:16] + connect \DS_XO \opcode_in [1:0] + connect \DS_VRT \opcode_in [25:21] + connect \DS_VRS \opcode_in [25:21] + connect \DS_RT \opcode_in [25:21] + connect \DS_RSp \opcode_in [25:21] + connect \DS_RS \opcode_in [25:21] + connect \DS_RA \opcode_in [20:16] + connect \DS_FRTp \opcode_in [25:21] + connect \DS_FRSp \opcode_in [25:21] + connect \DS_DS \opcode_in [15:2] + connect \DQ_XO \opcode_in [2:0] + connect \DQ_TX_T { \opcode_in [3] \opcode_in [25:21] } + connect \DQ_T \opcode_in [25:21] + connect \DQ_TX \opcode_in [3] + connect \DQ_SX_S { \opcode_in [3] \opcode_in [25:21] } + connect \DQ_S \opcode_in [25:21] + connect \DQ_SX \opcode_in [3] + connect \DQ_RTp \opcode_in [25:21] + connect \DQ_RA \opcode_in [20:16] + connect \DQ_PT \opcode_in [3:0] + connect \DQ_DQ \opcode_in [15:4] + connect \DX_XO \opcode_in [5:1] + connect \DX_RT \opcode_in [25:21] + connect \DX_d0_d1_d2 { \opcode_in [15:6] \opcode_in [20:16] \opcode_in [0] } + connect \DX_d2 \opcode_in [0] + connect \DX_d1 \opcode_in [20:16] + connect \DX_d0 \opcode_in [15:6] + connect \XFX_XO \opcode_in [10:1] + connect \XFX_SPR \opcode_in [20:11] + connect \XFX_RT \opcode_in [25:21] + connect \XFX_RS \opcode_in [25:21] + connect \XFX_FXM \opcode_in [19:12] + connect \XFX_DUIS \opcode_in [20:11] + connect \XFX_DUI \opcode_in [25:21] + connect \XFX_BHRBE \opcode_in [20:11] + connect \EVS_BFA \opcode_in [2:0] + connect \Z22_XO \opcode_in [9:1] + connect \Z22_SH \opcode_in [15:10] + connect \Z22_Rc \opcode_in [0] + connect \Z22_FRTp \opcode_in [25:21] + connect \Z22_FRT \opcode_in [25:21] + connect \Z22_FRAp \opcode_in [20:16] + connect \Z22_FRA \opcode_in [20:16] + connect \Z22_DGM \opcode_in [15:10] + connect \Z22_DCM \opcode_in [15:10] + connect \Z22_BF \opcode_in [25:23] + connect \XX2_XO_1 \opcode_in [10:2] + connect \XX2_XO { \opcode_in [10:7] \opcode_in [5:3] } + connect \XX2_UIM_1 \opcode_in [17:16] + connect \XX2_UIM \opcode_in [19:16] + connect \XX2_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX2_T \opcode_in [25:21] + connect \XX2_TX \opcode_in [0] + connect \XX2_RT \opcode_in [25:21] + connect \XX2_EO \opcode_in [20:16] + connect \XX2_DCMX \opcode_in [22:16] + connect \XX2_dc_dm_dx { \opcode_in [6] \opcode_in [2] \opcode_in [20:16] } + connect \XX2_dx \opcode_in [20:16] + connect \XX2_dm \opcode_in [2] + connect \XX2_dc \opcode_in [6] + connect \XX2_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX2_B \opcode_in [15:11] + connect \XX2_BX \opcode_in [1] + connect \XX2_BF \opcode_in [25:23] + connect \D_UI \opcode_in [15:0] + connect \D_TO \opcode_in [25:21] + connect \D_SI \opcode_in [15:0] + connect \D_RT \opcode_in [25:21] + connect \D_RS \opcode_in [25:21] + connect \D_RA \opcode_in [20:16] + connect \D_L \opcode_in [21] + connect \D_FRT \opcode_in [25:21] + connect \D_FRS \opcode_in [25:21] + connect \D_D \opcode_in [15:0] + connect \D_BF \opcode_in [25:23] + connect \A_XO \opcode_in [5:1] + connect \A_RT \opcode_in [25:21] + connect \A_Rc \opcode_in [0] + connect \A_RB \opcode_in [15:11] + connect \A_RA \opcode_in [20:16] + connect \A_FRT \opcode_in [25:21] + connect \A_FRC \opcode_in [10:6] + connect \A_FRB \opcode_in [15:11] + connect \A_FRA \opcode_in [20:16] + connect \A_BC \opcode_in [10:6] + connect \XL_XO \opcode_in [10:1] + connect \XL_S \opcode_in [11] + connect \XL_OC \opcode_in [25:11] + connect \XL_LK \opcode_in [0] + connect \XL_BT \opcode_in [25:21] + connect \XL_BO_1 \opcode_in [25:21] + connect \XL_BO \opcode_in [25:21] + connect \XL_BI \opcode_in [20:16] + connect \XL_BH \opcode_in [12:11] + connect \XL_BFA \opcode_in [20:18] + connect \XL_BF \opcode_in [25:23] + connect \XL_BB \opcode_in [15:11] + connect \XL_BA \opcode_in [20:16] + connect \XX4_XO \opcode_in [5:4] + connect \XX4_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX4_T \opcode_in [25:21] + connect \XX4_TX \opcode_in [0] + connect \XX4_CX_C { \opcode_in [3] \opcode_in [10:6] } + connect \XX4_C \opcode_in [10:6] + connect \XX4_CX \opcode_in [3] + connect \XX4_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX4_B \opcode_in [15:11] + connect \XX4_BX \opcode_in [1] + connect \XX4_AX_A { \opcode_in [2] \opcode_in [20:16] } + connect \XX4_A \opcode_in [20:16] + connect \XX4_AX \opcode_in [2] + connect \XX3_XO_2 \opcode_in [9:1] + connect \XX3_XO_1 \opcode_in [10:3] + connect \XX3_XO \opcode_in [10:7] + connect \XX3_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX3_T \opcode_in [25:21] + connect \XX3_TX \opcode_in [0] + connect \XX3_SHW \opcode_in [9:8] + connect \XX3_Rc \opcode_in [10] + connect \XX3_DM \opcode_in [9:8] + connect \XX3_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX3_B \opcode_in [15:11] + connect \XX3_BX \opcode_in [1] + connect \XX3_BF \opcode_in [25:23] + connect \XX3_AX_A { \opcode_in [2] \opcode_in [20:16] } + connect \XX3_A \opcode_in [20:16] + connect \XX3_AX \opcode_in [2] + connect \I_LK \opcode_in [0] + connect \I_LI \opcode_in [25:2] + connect \I_AA \opcode_in [1] + connect \B_LK \opcode_in [0] + connect \B_BO \opcode_in [25:21] + connect \B_BI \opcode_in [20:16] + connect \B_BD \opcode_in [15:2] + connect \B_AA \opcode_in [1] + connect \X_XO_1 \opcode_in [8:1] + connect \X_XO \opcode_in [10:1] + connect \X_WC \opcode_in [22:21] + connect \X_W \opcode_in [16] + connect \X_VRT \opcode_in [25:21] + connect \X_VRS \opcode_in [25:21] + connect \X_UIM \opcode_in [20:16] + connect \X_U \opcode_in [15:12] + connect \X_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \X_TX \opcode_in [0] + connect \X_TO \opcode_in [25:21] + connect \X_TH \opcode_in [25:21] + connect \X_TBR \opcode_in [20:11] + connect \X_T \opcode_in [25:21] + connect \X_SX_S { \opcode_in [0] \opcode_in [25:21] } + connect \X_SX \opcode_in [0] + connect \X_SR \opcode_in [19:16] + connect \X_SP \opcode_in [20:19] + connect \X_SI \opcode_in [15:11] + connect \X_SH \opcode_in [15:11] + connect \X_S \opcode_in [25:21] + connect \X_RTp \opcode_in [25:21] + connect \X_RT \opcode_in [25:21] + connect \X_RSp \opcode_in [25:21] + connect \X_RS \opcode_in [25:21] + connect \X_RO \opcode_in [0] + connect \X_RM \opcode_in [12:11] + connect \X_RIC \opcode_in [19:18] + connect \X_Rc \opcode_in [0] + connect \X_RB \opcode_in [15:11] + connect \X_RA \opcode_in [20:16] + connect \X_R_1 \opcode_in [16] + connect \X_R \opcode_in [21] + connect \X_PRS \opcode_in [17] + connect \X_NB \opcode_in [15:11] + connect \X_MO \opcode_in [25:21] + connect \X_L3 \opcode_in [17:16] + connect \X_L1 \opcode_in [16] + connect \X_L \opcode_in [21] + connect \X_L2 \opcode_in [22:21] + connect \X_IMM8 \opcode_in [18:11] + connect \X_IH \opcode_in [23:21] + connect \X_FRTp \opcode_in [25:21] + connect \X_FRT \opcode_in [25:21] + connect \X_FRSp \opcode_in [25:21] + connect \X_FRS \opcode_in [25:21] + connect \X_FRBp \opcode_in [15:11] + connect \X_FRB \opcode_in [15:11] + connect \X_FRAp \opcode_in [20:16] + connect \X_FRA \opcode_in [20:16] + connect \X_FC \opcode_in [15:11] + connect \X_EX \opcode_in [0] + connect \X_EO_1 \opcode_in [20:16] + connect \X_EO \opcode_in [20:19] + connect \X_E_1 \opcode_in [19:16] + connect \X_E \opcode_in [15] + connect \X_DRM \opcode_in [13:11] + connect \X_DCMX \opcode_in [22:16] + connect \X_CT \opcode_in [24:21] + connect \X_BO \opcode_in [25:21] + connect \X_BFA \opcode_in [20:18] + connect \X_BF \opcode_in [25:23] + connect \X_A \opcode_in [25] + connect \LDST_SPR \opcode_in [20:11] + connect \LDST_MB \opcode_in [10:6] + connect \LDST_ME \opcode_in [5:1] + connect \LDST_SH \opcode_in [15:11] + connect \LDST_BC \opcode_in [10:6] + connect \LDST_TO \opcode_in [25:21] + connect \LDST_DS \opcode_in [15:2] + connect \LDST_D \opcode_in [15:0] + connect \LDST_BH \opcode_in [12:11] + connect \LDST_BI \opcode_in [20:16] + connect \LDST_BO \opcode_in [25:21] + connect \LDST_FXM \opcode_in [19:12] + connect \LDST_BT \opcode_in [25:21] + connect \LDST_BA \opcode_in [20:16] + connect \LDST_BB \opcode_in [15:11] + connect \LDST_CR \opcode_in [10:1] + connect \LDST_BF \opcode_in [25:23] + connect \LDST_BD \opcode_in [15:2] + connect \LDST_OE \opcode_in [10] + connect \LDST_Rc \opcode_in [0] + connect \LDST_AA \opcode_in [1] + connect \LDST_LK \opcode_in [0] + connect \LDST_LI \opcode_in [25:2] + connect \LDST_ME32 \opcode_in [5:1] + connect \LDST_MB32 \opcode_in [10:6] + connect \LDST_sh { \opcode_in [1] \opcode_in [15:11] } + connect \LDST_SH32 \opcode_in [15:11] + connect \LDST_L \opcode_in [21] + connect \LDST_UI \opcode_in [15:0] + connect \LDST_SI \opcode_in [15:0] + connect \LDST_RB \opcode_in [15:11] + connect \LDST_RA \opcode_in [20:16] + connect \LDST_RT \opcode_in [25:21] + connect \LDST_RS \opcode_in [25:21] + connect \opcode_in \$1 + connect \LDST_dec62_opcode_in \opcode_in + connect \LDST_dec58_opcode_in \opcode_in + connect \LDST_dec31_opcode_in \opcode_in + connect \opcode_switch \opcode_in [31:26] +end +attribute \src "libresoc.v:67010.1-74561.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec" +attribute \generator "nMigen" +module \dec$204 + attribute \src "libresoc.v:69818.3-69959.6" + wire width 2 $0\SV_Etype[1:0] + attribute \src "libresoc.v:69960.3-70101.6" + wire width 2 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"libresoc.v:70670.3-70811.6" + wire width 3 $2\cr_in[2:0] + attribute \src "libresoc.v:70812.3-70953.6" + wire width 3 $2\cr_out[2:0] + attribute \src "libresoc.v:72232.3-72373.6" + wire width 2 $2\cry_in[1:0] + attribute \src "libresoc.v:72658.3-72799.6" + wire $2\cry_out[0:0] + attribute \src "libresoc.v:74078.3-74219.6" + wire width 5 $2\form[4:0] + attribute \src "libresoc.v:73794.3-73935.6" + wire width 13 $2\function_unit[12:0] + attribute \src "libresoc.v:70102.3-70243.6" + wire width 3 $2\in1_sel[2:0] + attribute \src "libresoc.v:70244.3-70385.6" + wire width 4 $2\in2_sel[3:0] + attribute \src "libresoc.v:70386.3-70527.6" + wire width 2 $2\in3_sel[1:0] + attribute \src "libresoc.v:73936.3-74077.6" + wire width 7 $2\internal_op[6:0] + attribute \src "libresoc.v:72374.3-72515.6" + wire $2\inv_a[0:0] + attribute \src "libresoc.v:72516.3-72657.6" + wire $2\inv_out[0:0] + attribute \src "libresoc.v:73226.3-73367.6" + wire $2\is_32b[0:0] + attribute \src "libresoc.v:71806.3-71947.6" + wire width 4 $2\ldst_len[3:0] + attribute \src "libresoc.v:73510.3-73651.6" + wire $2\lk[0:0] + attribute \src "libresoc.v:70528.3-70669.6" + wire width 2 $2\out_sel[1:0] + attribute \src "libresoc.v:72090.3-72231.6" + wire width 2 $2\rc_sel[1:0] + attribute \src "libresoc.v:73084.3-73225.6" + wire $2\rsrv[0:0] + attribute \src "libresoc.v:73652.3-73793.6" + wire $2\sgl_pipe[0:0] + attribute \src "libresoc.v:73368.3-73509.6" + wire $2\sgn[0:0] + attribute \src "libresoc.v:72942.3-73083.6" + wire $2\sgn_ext[0:0] + attribute \src "libresoc.v:71522.3-71663.6" + wire width 3 $2\sv_cr_in[2:0] + attribute \src "libresoc.v:71664.3-71805.6" + wire width 3 $2\sv_cr_out[2:0] + attribute \src "libresoc.v:70954.3-71095.6" + wire width 3 $2\sv_in1[2:0] + attribute \src "libresoc.v:71096.3-71237.6" + wire width 3 $2\sv_in2[2:0] + attribute \src "libresoc.v:71238.3-71379.6" + wire width 3 $2\sv_in3[2:0] + attribute \src "libresoc.v:71380.3-71521.6" + wire width 3 $2\sv_out[2:0] + attribute \src "libresoc.v:71948.3-72089.6" + wire width 2 $2\upd[1:0] + attribute \src "libresoc.v:69503.17-69503.211" + wire width 32 $ternary$libresoc.v:69503$3568_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:504" + wire width 32 \$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire \AA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \A_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \A_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \A_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \A_FRC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \A_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \A_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \A_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \A_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \A_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \A_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 output 33 \BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 output 32 \BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 output 38 \BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 14 \BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 3 \BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 2 \BH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 output 37 \BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 output 36 \BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 output 34 \BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \B_AA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 14 \B_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \B_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \B_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \B_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 10 \CR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 16 \D + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DQE_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DQE_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 2 \DQE_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 12 \DQ_DQ + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 4 \DQ_PT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DQ_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DQ_RTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DQ_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \DQ_SX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \DQ_SX_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DQ_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \DQ_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \DQ_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 3 \DQ_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 14 \DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 14 \DS_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DS_FRSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DS_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DS_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DS_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DS_RSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DS_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DS_VRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DS_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 2 \DS_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DX_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 10 \DX_d0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 16 \DX_d0_d1_d2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \DX_d1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \DX_d2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 3 \D_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 16 \D_D + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \D_FRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \D_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \D_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \D_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \D_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \D_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 16 \D_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \D_TO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 16 \D_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 3 \EVS_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 8 output 35 \FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \I_AA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 24 \I_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \I_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire \L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 24 \LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire output 12 \LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \MB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \MB32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \MDS_IB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \MDS_IS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \MDS_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \MDS_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \MDS_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \MDS_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 4 \MDS_XBI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 4 \MDS_XBI_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 4 \MDS_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \MDS_mb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \MDS_me + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \MD_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \MD_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \MD_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 3 \MD_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \MD_mb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \MD_me + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \MD_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \ME + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \ME32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \M_MB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \M_ME + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \M_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \M_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \M_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \M_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \M_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire output 31 \OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 output 28 \RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 output 29 \RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 output 26 \RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 output 27 \RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire output 30 \Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 7 \SC_LEV + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \SC_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 2 \SC_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 16 \SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 10 output 7 \SPR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \SVL_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \SVL_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \SVL_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \SVL_SVi + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \SVL_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \SVL_ms + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \SVL_vs + attribute \enum_base_type "SVEtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "EXTRA2" + attribute \enum_value_10 "EXTRA3" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 19 \SV_Etype + attribute \enum_base_type "SVPtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "P1" + attribute \enum_value_10 "P2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \SV_Ptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \TO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \TX_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \TX_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 4 \TX_XBI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \TX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 16 \UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \VA_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \VA_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \VA_RC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \VA_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 4 \VA_SHB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \VA_VRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \VA_VRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \VA_VRC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \VA_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \VA_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \VC_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \VC_VRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \VC_VRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \VC_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 10 \VC_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \VX_EO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \VX_PS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \VX_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \VX_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \VX_SIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \VX_UIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 4 \VX_UIM_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 3 \VX_UIM_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 2 \VX_UIM_3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \VX_VRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \VX_VRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \VX_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 10 \VX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 11 \VX_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 8 \XFL_FLM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \XFL_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \XFL_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \XFL_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \XFL_W + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 10 \XFL_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 10 \XFX_BHRBE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \XFX_DUI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 10 \XFX_DUIS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 8 \XFX_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \XFX_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \XFX_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 10 \XFX_SPR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 10 \XFX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \XL_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \XL_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 3 \XL_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 3 \XL_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 2 \XL_BH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \XL_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \XL_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \XL_BO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 output 41 \XL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \XL_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 15 \XL_OC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \XL_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 10 output 42 \XL_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \XO_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \XO_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \XO_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \XO_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \XO_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 9 \XO_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \XS_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \XS_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \XS_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 9 \XS_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \XS_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \XX2_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 3 \XX2_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \XX2_BX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \XX2_BX_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 7 \XX2_DCMX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \XX2_EO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \XX2_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \XX2_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \XX2_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \XX2_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 4 \XX2_UIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 2 \XX2_UIM_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 7 \XX2_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 9 \XX2_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \XX2_dc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 7 \XX2_dc_dm_dx + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \XX2_dm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \XX2_dx + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \XX3_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \XX3_AX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \XX3_AX_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \XX3_B + attribute \src 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \XX4_C + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \XX4_CX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \XX4_CX_C + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \XX4_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \XX4_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \XX4_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 2 \XX4_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \X_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 3 output 39 \X_BF + attribute \src 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 4 \X_E_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_FC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_FRAp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_FRBp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_FRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_FRSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 3 \X_IH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 8 \X_IMM8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \X_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \X_L1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 2 \X_L2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 2 \X_L3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_MO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_NB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \X_PRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \X_R + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 2 \X_RIC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 2 \X_RM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \X_RO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_RSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_RTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \X_R_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \X_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 2 \X_SP + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 4 \X_SR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \X_SX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \X_SX_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 10 \X_TBR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_TH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_TO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \X_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \X_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 4 \X_U + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_UIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_VRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \X_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \X_W + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 2 \X_WC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 10 \X_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 8 \X_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 3 \Z22_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \Z22_DCM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \Z22_DGM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \Z22_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \Z22_FRAp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \Z22_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \Z22_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \Z22_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \Z22_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 9 \Z22_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \Z23_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \Z23_FRAp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \Z23_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \Z23_FRBp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \Z23_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \Z23_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \Z23_R + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 2 \Z23_RMC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire \Z23_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \Z23_TE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 8 \Z23_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \all_OPCD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 6 \all_PO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 8 output 24 \asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" + wire input 43 \bigendian + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 4 \cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 5 \cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 9 \cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \cry_out + attribute \enum_base_type "SVEtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "EXTRA2" + attribute \enum_value_10 "EXTRA3" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \dec19_dec19_SV_Etype + attribute \enum_base_type "SVPtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "P1" + attribute \enum_value_10 "P2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \dec19_dec19_SV_Ptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 8 \dec19_dec19_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \dec19_dec19_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec19_dec19_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec19_dec19_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \dec19_dec19_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \dec19_dec19_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 5 \dec19_dec19_form + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 13 \dec19_dec19_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec19_dec19_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + 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"SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 13 output 8 \function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 15 \in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 16 \in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 17 \in3_sel + attribute \src "libresoc.v:67011.7-67011.15" + wire \initial + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 output 6 \internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 10 \is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 \ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 11 \lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + wire width 32 output 2 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + wire width 6 \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + wire width 32 \opcode_switch$1 + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 18 \out_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 32 input 1 \raw_opcode_in + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 3 \rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 6 \sh + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 14 \sv_cr_in + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 13 \sv_cr_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 20 \sv_in1 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 21 \sv_in2 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 22 \sv_in3 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 23 \sv_out + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 25 \upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:504" + cell $mux $ternary$libresoc.v:69503$3568 + parameter \WIDTH 32 + connect \A \raw_opcode_in + connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } + connect \S \bigendian + connect \Y $ternary$libresoc.v:69503$3568_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:69504.9-69538.4" + cell \dec19 \dec19 + connect \dec19_SV_Etype \dec19_dec19_SV_Etype + connect \dec19_SV_Ptype \dec19_dec19_SV_Ptype + connect \dec19_asmcode \dec19_dec19_asmcode + connect \dec19_br \dec19_dec19_br + connect \dec19_cr_in \dec19_dec19_cr_in + connect \dec19_cr_out \dec19_dec19_cr_out + connect \dec19_cry_in \dec19_dec19_cry_in + connect \dec19_cry_out \dec19_dec19_cry_out + connect \dec19_form \dec19_dec19_form + connect \dec19_function_unit \dec19_dec19_function_unit + connect \dec19_in1_sel \dec19_dec19_in1_sel + connect \dec19_in2_sel \dec19_dec19_in2_sel + connect \dec19_in3_sel \dec19_dec19_in3_sel + connect \dec19_internal_op \dec19_dec19_internal_op + connect \dec19_inv_a \dec19_dec19_inv_a + connect \dec19_inv_out \dec19_dec19_inv_out + connect \dec19_is_32b \dec19_dec19_is_32b + connect \dec19_ldst_len \dec19_dec19_ldst_len + connect \dec19_lk \dec19_dec19_lk + connect \dec19_out_sel \dec19_dec19_out_sel + connect \dec19_rc_sel \dec19_dec19_rc_sel + connect \dec19_rsrv \dec19_dec19_rsrv + connect \dec19_sgl_pipe \dec19_dec19_sgl_pipe + connect \dec19_sgn \dec19_dec19_sgn + connect \dec19_sgn_ext \dec19_dec19_sgn_ext + connect \dec19_sv_cr_in \dec19_dec19_sv_cr_in + connect \dec19_sv_cr_out \dec19_dec19_sv_cr_out + connect \dec19_sv_in1 \dec19_dec19_sv_in1 + connect \dec19_sv_in2 \dec19_dec19_sv_in2 + connect \dec19_sv_in3 \dec19_dec19_sv_in3 + connect \dec19_sv_out \dec19_dec19_sv_out + connect \dec19_upd \dec19_dec19_upd + connect \opcode_in \dec19_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:69539.9-69573.4" + cell \dec30 \dec30 + connect \dec30_SV_Etype \dec30_dec30_SV_Etype + connect \dec30_SV_Ptype \dec30_dec30_SV_Ptype + connect \dec30_asmcode \dec30_dec30_asmcode + connect \dec30_br \dec30_dec30_br + connect \dec30_cr_in \dec30_dec30_cr_in + connect \dec30_cr_out \dec30_dec30_cr_out + connect \dec30_cry_in \dec30_dec30_cry_in + connect \dec30_cry_out \dec30_dec30_cry_out + connect \dec30_form \dec30_dec30_form + connect \dec30_function_unit \dec30_dec30_function_unit + connect \dec30_in1_sel \dec30_dec30_in1_sel + connect \dec30_in2_sel \dec30_dec30_in2_sel + connect \dec30_in3_sel \dec30_dec30_in3_sel + connect \dec30_internal_op \dec30_dec30_internal_op + connect \dec30_inv_a \dec30_dec30_inv_a + connect \dec30_inv_out \dec30_dec30_inv_out + connect \dec30_is_32b \dec30_dec30_is_32b + connect \dec30_ldst_len \dec30_dec30_ldst_len + connect \dec30_lk \dec30_dec30_lk + connect \dec30_out_sel \dec30_dec30_out_sel + connect \dec30_rc_sel \dec30_dec30_rc_sel + connect \dec30_rsrv \dec30_dec30_rsrv + connect \dec30_sgl_pipe \dec30_dec30_sgl_pipe + connect \dec30_sgn \dec30_dec30_sgn + connect \dec30_sgn_ext \dec30_dec30_sgn_ext + connect \dec30_sv_cr_in \dec30_dec30_sv_cr_in + connect \dec30_sv_cr_out \dec30_dec30_sv_cr_out + connect \dec30_sv_in1 \dec30_dec30_sv_in1 + connect \dec30_sv_in2 \dec30_dec30_sv_in2 + connect \dec30_sv_in3 \dec30_dec30_sv_in3 + connect \dec30_sv_out \dec30_dec30_sv_out + connect \dec30_upd \dec30_dec30_upd + connect \opcode_in \dec30_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:69574.9-69608.4" + cell \dec31 \dec31 + connect \dec31_SV_Etype \dec31_dec31_SV_Etype + connect \dec31_SV_Ptype \dec31_dec31_SV_Ptype + connect \dec31_asmcode \dec31_dec31_asmcode + connect \dec31_br \dec31_dec31_br + connect \dec31_cr_in \dec31_dec31_cr_in + connect \dec31_cr_out \dec31_dec31_cr_out + connect \dec31_cry_in \dec31_dec31_cry_in + connect \dec31_cry_out \dec31_dec31_cry_out + connect \dec31_form \dec31_dec31_form + connect \dec31_function_unit \dec31_dec31_function_unit + connect \dec31_in1_sel \dec31_dec31_in1_sel + connect \dec31_in2_sel \dec31_dec31_in2_sel + connect \dec31_in3_sel \dec31_dec31_in3_sel + connect \dec31_internal_op \dec31_dec31_internal_op + connect \dec31_inv_a \dec31_dec31_inv_a + connect \dec31_inv_out \dec31_dec31_inv_out + connect \dec31_is_32b \dec31_dec31_is_32b + connect \dec31_ldst_len \dec31_dec31_ldst_len + connect \dec31_lk \dec31_dec31_lk + connect \dec31_out_sel \dec31_dec31_out_sel + connect \dec31_rc_sel \dec31_dec31_rc_sel + connect \dec31_rsrv \dec31_dec31_rsrv + connect \dec31_sgl_pipe \dec31_dec31_sgl_pipe + connect \dec31_sgn \dec31_dec31_sgn + connect \dec31_sgn_ext \dec31_dec31_sgn_ext + connect \dec31_sv_cr_in \dec31_dec31_sv_cr_in + connect \dec31_sv_cr_out \dec31_dec31_sv_cr_out + connect \dec31_sv_in1 \dec31_dec31_sv_in1 + connect \dec31_sv_in2 \dec31_dec31_sv_in2 + connect \dec31_sv_in3 \dec31_dec31_sv_in3 + connect \dec31_sv_out \dec31_dec31_sv_out + connect \dec31_upd \dec31_dec31_upd + connect \opcode_in \dec31_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:69609.9-69643.4" + cell \dec58 \dec58 + connect \dec58_SV_Etype \dec58_dec58_SV_Etype + connect \dec58_SV_Ptype \dec58_dec58_SV_Ptype + connect \dec58_asmcode \dec58_dec58_asmcode + connect \dec58_br \dec58_dec58_br + connect \dec58_cr_in \dec58_dec58_cr_in + connect \dec58_cr_out \dec58_dec58_cr_out + connect \dec58_cry_in \dec58_dec58_cry_in + connect \dec58_cry_out \dec58_dec58_cry_out + connect \dec58_form \dec58_dec58_form + connect \dec58_function_unit \dec58_dec58_function_unit + connect \dec58_in1_sel \dec58_dec58_in1_sel + connect \dec58_in2_sel \dec58_dec58_in2_sel + connect \dec58_in3_sel \dec58_dec58_in3_sel + connect \dec58_internal_op \dec58_dec58_internal_op + connect \dec58_inv_a \dec58_dec58_inv_a + connect \dec58_inv_out \dec58_dec58_inv_out + connect \dec58_is_32b \dec58_dec58_is_32b + connect \dec58_ldst_len \dec58_dec58_ldst_len + connect \dec58_lk \dec58_dec58_lk + connect \dec58_out_sel \dec58_dec58_out_sel + connect \dec58_rc_sel \dec58_dec58_rc_sel + connect \dec58_rsrv \dec58_dec58_rsrv + connect \dec58_sgl_pipe \dec58_dec58_sgl_pipe + connect \dec58_sgn \dec58_dec58_sgn + connect \dec58_sgn_ext \dec58_dec58_sgn_ext + connect \dec58_sv_cr_in \dec58_dec58_sv_cr_in + connect \dec58_sv_cr_out \dec58_dec58_sv_cr_out + connect \dec58_sv_in1 \dec58_dec58_sv_in1 + connect \dec58_sv_in2 \dec58_dec58_sv_in2 + connect \dec58_sv_in3 \dec58_dec58_sv_in3 + connect \dec58_sv_out \dec58_dec58_sv_out + connect \dec58_upd \dec58_dec58_upd + connect \opcode_in \dec58_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:69644.9-69678.4" + cell \dec62 \dec62 + connect \dec62_SV_Etype \dec62_dec62_SV_Etype + connect \dec62_SV_Ptype \dec62_dec62_SV_Ptype + connect \dec62_asmcode \dec62_dec62_asmcode + connect \dec62_br \dec62_dec62_br + connect \dec62_cr_in \dec62_dec62_cr_in + connect \dec62_cr_out \dec62_dec62_cr_out + connect \dec62_cry_in \dec62_dec62_cry_in + connect \dec62_cry_out \dec62_dec62_cry_out + connect \dec62_form \dec62_dec62_form + connect \dec62_function_unit \dec62_dec62_function_unit + connect \dec62_in1_sel \dec62_dec62_in1_sel + connect \dec62_in2_sel \dec62_dec62_in2_sel + connect \dec62_in3_sel \dec62_dec62_in3_sel + connect \dec62_internal_op \dec62_dec62_internal_op + connect \dec62_inv_a \dec62_dec62_inv_a + connect \dec62_inv_out \dec62_dec62_inv_out + connect \dec62_is_32b \dec62_dec62_is_32b + connect \dec62_ldst_len \dec62_dec62_ldst_len + connect \dec62_lk \dec62_dec62_lk + connect \dec62_out_sel \dec62_dec62_out_sel + connect \dec62_rc_sel \dec62_dec62_rc_sel + connect \dec62_rsrv \dec62_dec62_rsrv + connect \dec62_sgl_pipe \dec62_dec62_sgl_pipe + connect \dec62_sgn \dec62_dec62_sgn + connect \dec62_sgn_ext \dec62_dec62_sgn_ext + connect \dec62_sv_cr_in \dec62_dec62_sv_cr_in + connect \dec62_sv_cr_out \dec62_dec62_sv_cr_out + connect \dec62_sv_in1 \dec62_dec62_sv_in1 + connect \dec62_sv_in2 \dec62_dec62_sv_in2 + connect \dec62_sv_in3 \dec62_dec62_sv_in3 + connect \dec62_sv_out \dec62_dec62_sv_out + connect \dec62_upd \dec62_dec62_upd + connect \opcode_in \dec62_opcode_in + end + attribute \src "libresoc.v:67011.7-67011.20" + process $proc$libresoc.v:67011$3601 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:69679.3-69817.6" + process $proc$libresoc.v:69679$3569 + assign { } { } + assign { } { } + assign { } { } + assign $0\asmcode[7:0] $2\asmcode[7:0] + attribute \src "libresoc.v:69680.5-69680.29" + switch \initial + attribute \src "libresoc.v:69680.9-69680.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\asmcode[7:0] \dec19_dec19_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\asmcode[7:0] \dec30_dec30_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\asmcode[7:0] \dec31_dec31_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\asmcode[7:0] \dec58_dec58_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\asmcode[7:0] \dec62_dec62_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\asmcode[7:0] 8'00000111 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\asmcode[7:0] 8'00001000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\asmcode[7:0] 8'00000110 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\asmcode[7:0] 8'00001001 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\asmcode[7:0] 8'00010001 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\asmcode[7:0] 8'00010010 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\asmcode[7:0] 8'00010100 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\asmcode[7:0] 8'00010101 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\asmcode[7:0] 8'00011101 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\asmcode[7:0] 8'00011111 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\asmcode[7:0] 8'01001110 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\asmcode[7:0] 8'01001111 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\asmcode[7:0] 8'01011000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\asmcode[7:0] 8'01011010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\asmcode[7:0] 8'01011110 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\asmcode[7:0] 8'01011111 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\asmcode[7:0] 8'01100111 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\asmcode[7:0] 8'01101001 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\asmcode[7:0] 8'10000000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\asmcode[7:0] 8'10001010 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\asmcode[7:0] 8'10001011 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\asmcode[7:0] 8'10011000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\asmcode[7:0] 8'10011001 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\asmcode[7:0] 8'10011010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\asmcode[7:0] 8'10100111 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\asmcode[7:0] 8'10101010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\asmcode[7:0] 8'10110011 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\asmcode[7:0] 8'10110110 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\asmcode[7:0] 8'10111001 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\asmcode[7:0] 8'10111100 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\asmcode[7:0] 8'11000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\asmcode[7:0] 8'11001100 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\asmcode[7:0] 8'11010000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\asmcode[7:0] 8'11010010 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\asmcode[7:0] 8'11010011 + case + assign $1\asmcode[7:0] 8'00000000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\asmcode[7:0] 8'00010011 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\asmcode[7:0] 8'10000110 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\asmcode[7:0] 8'10011101 + case + assign $2\asmcode[7:0] $1\asmcode[7:0] + end + sync always + update \asmcode $0\asmcode[7:0] + end + attribute \src "libresoc.v:69818.3-69959.6" + process $proc$libresoc.v:69818$3570 + assign { } { } + assign { } { } + assign { } { } + assign $0\SV_Etype[1:0] $2\SV_Etype[1:0] + attribute \src "libresoc.v:69819.5-69819.29" + switch \initial + attribute \src "libresoc.v:69819.9-69819.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\SV_Etype[1:0] \dec19_dec19_SV_Etype + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\SV_Etype[1:0] \dec30_dec30_SV_Etype + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\SV_Etype[1:0] \dec31_dec31_SV_Etype + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\SV_Etype[1:0] \dec58_dec58_SV_Etype + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\SV_Etype[1:0] \dec62_dec62_SV_Etype + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\SV_Etype[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\SV_Etype[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\SV_Etype[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\SV_Etype[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\SV_Etype[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\SV_Etype[1:0] 2'10 + case + assign $1\SV_Etype[1:0] 2'00 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\SV_Etype[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\SV_Etype[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\SV_Etype[1:0] 2'00 + case + assign $2\SV_Etype[1:0] $1\SV_Etype[1:0] + end + sync always + update \SV_Etype $0\SV_Etype[1:0] + end + attribute \src "libresoc.v:69960.3-70101.6" + process $proc$libresoc.v:69960$3571 + assign { } { } + assign { } { } + assign { } { } + assign $0\SV_Ptype[1:0] $2\SV_Ptype[1:0] + attribute \src "libresoc.v:69961.5-69961.29" + switch \initial + attribute \src "libresoc.v:69961.9-69961.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\SV_Ptype[1:0] \dec19_dec19_SV_Ptype + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\SV_Ptype[1:0] \dec30_dec30_SV_Ptype + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\SV_Ptype[1:0] \dec31_dec31_SV_Ptype + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\SV_Ptype[1:0] \dec58_dec58_SV_Ptype + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\SV_Ptype[1:0] \dec62_dec62_SV_Ptype + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\SV_Ptype[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\SV_Ptype[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\SV_Ptype[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\SV_Ptype[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\SV_Ptype[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\SV_Ptype[1:0] 2'10 + case + assign $1\SV_Ptype[1:0] 2'00 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\SV_Ptype[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\SV_Ptype[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\SV_Ptype[1:0] 2'00 + case + assign $2\SV_Ptype[1:0] $1\SV_Ptype[1:0] + end + sync always + update \SV_Ptype $0\SV_Ptype[1:0] + end + attribute \src "libresoc.v:70102.3-70243.6" + process $proc$libresoc.v:70102$3572 + assign { } { } + assign { } { } + assign { } { } + assign $0\in1_sel[2:0] $2\in1_sel[2:0] + attribute \src "libresoc.v:70103.5-70103.29" + switch \initial + attribute \src "libresoc.v:70103.9-70103.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\in1_sel[2:0] \dec19_dec19_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\in1_sel[2:0] \dec30_dec30_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\in1_sel[2:0] \dec31_dec31_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\in1_sel[2:0] \dec58_dec58_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\in1_sel[2:0] \dec62_dec62_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\in1_sel[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\in1_sel[2:0] 3'100 + case + assign $1\in1_sel[2:0] 3'000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\in1_sel[2:0] 3'000 + case + assign $2\in1_sel[2:0] $1\in1_sel[2:0] + end + sync always + update \in1_sel $0\in1_sel[2:0] + end + attribute \src "libresoc.v:70244.3-70385.6" + process $proc$libresoc.v:70244$3573 + assign { } { } + assign { } { } + assign { } { } + assign $0\in2_sel[3:0] $2\in2_sel[3:0] + attribute \src "libresoc.v:70245.5-70245.29" + switch \initial + attribute \src "libresoc.v:70245.9-70245.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\in2_sel[3:0] \dec19_dec19_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\in2_sel[3:0] \dec30_dec30_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\in2_sel[3:0] \dec31_dec31_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\in2_sel[3:0] \dec58_dec58_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\in2_sel[3:0] \dec62_dec62_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\in2_sel[3:0] 4'0101 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\in2_sel[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\in2_sel[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\in2_sel[3:0] 4'0110 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\in2_sel[3:0] 4'0111 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\in2_sel[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\in2_sel[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\in2_sel[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\in2_sel[3:0] 4'1011 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\in2_sel[3:0] 4'1011 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\in2_sel[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\in2_sel[3:0] 4'0100 + case + assign $1\in2_sel[3:0] 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\in2_sel[3:0] 4'0000 + case + assign $2\in2_sel[3:0] $1\in2_sel[3:0] + end + sync always + update \in2_sel $0\in2_sel[3:0] + end + attribute \src "libresoc.v:70386.3-70527.6" + process $proc$libresoc.v:70386$3574 + assign { } { } + assign { } { } + assign { } { } + assign $0\in3_sel[1:0] $2\in3_sel[1:0] + attribute \src "libresoc.v:70387.5-70387.29" + switch \initial + attribute \src "libresoc.v:70387.9-70387.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\in3_sel[1:0] \dec19_dec19_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\in3_sel[1:0] \dec30_dec30_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\in3_sel[1:0] \dec31_dec31_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\in3_sel[1:0] \dec58_dec58_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\in3_sel[1:0] \dec62_dec62_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + case + assign $1\in3_sel[1:0] 2'00 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\in3_sel[1:0] 2'00 + case + assign $2\in3_sel[1:0] $1\in3_sel[1:0] + end + sync always + update \in3_sel $0\in3_sel[1:0] + end + attribute \src "libresoc.v:70528.3-70669.6" + process $proc$libresoc.v:70528$3575 + assign { } { } + assign { } { } + assign { } { } + assign $0\out_sel[1:0] $2\out_sel[1:0] + attribute \src "libresoc.v:70529.5-70529.29" + switch \initial + attribute \src "libresoc.v:70529.9-70529.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\out_sel[1:0] \dec19_dec19_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\out_sel[1:0] \dec30_dec30_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\out_sel[1:0] \dec31_dec31_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\out_sel[1:0] \dec58_dec58_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\out_sel[1:0] \dec62_dec62_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\out_sel[1:0] 2'11 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\out_sel[1:0] 2'10 + case + assign $1\out_sel[1:0] 2'00 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\out_sel[1:0] 2'01 + case + assign $2\out_sel[1:0] $1\out_sel[1:0] + end + sync always + update \out_sel $0\out_sel[1:0] + end + attribute \src "libresoc.v:70670.3-70811.6" + process $proc$libresoc.v:70670$3576 + assign { } { } + assign { } { } + assign { } { } + assign $0\cr_in[2:0] $2\cr_in[2:0] + attribute \src "libresoc.v:70671.5-70671.29" + switch \initial + attribute \src "libresoc.v:70671.9-70671.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\cr_in[2:0] \dec19_dec19_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\cr_in[2:0] \dec30_dec30_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\cr_in[2:0] \dec31_dec31_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\cr_in[2:0] \dec58_dec58_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\cr_in[2:0] \dec62_dec62_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\cr_in[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\cr_in[2:0] 3'000 + case + assign $1\cr_in[2:0] 3'000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\cr_in[2:0] 3'000 + case + assign $2\cr_in[2:0] $1\cr_in[2:0] + end + sync always + update \cr_in $0\cr_in[2:0] + end + attribute \src "libresoc.v:70812.3-70953.6" + process $proc$libresoc.v:70812$3577 + assign { } { } + assign { } { } + assign { } { } + assign $0\cr_out[2:0] $2\cr_out[2:0] + attribute \src "libresoc.v:70813.5-70813.29" + switch \initial + attribute \src "libresoc.v:70813.9-70813.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\cr_out[2:0] \dec19_dec19_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\cr_out[2:0] \dec30_dec30_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\cr_out[2:0] \dec31_dec31_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\cr_out[2:0] \dec58_dec58_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\cr_out[2:0] \dec62_dec62_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\cr_out[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\cr_out[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\cr_out[2:0] 3'000 + case + assign $1\cr_out[2:0] 3'000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\cr_out[2:0] 3'000 + case + assign $2\cr_out[2:0] $1\cr_out[2:0] + end + sync always + update \cr_out $0\cr_out[2:0] + end + attribute \src "libresoc.v:70954.3-71095.6" + process $proc$libresoc.v:70954$3578 + assign { } { } + assign { } { } + assign { } { } + assign $0\sv_in1[2:0] $2\sv_in1[2:0] + attribute \src "libresoc.v:70955.5-70955.29" + switch \initial + attribute \src "libresoc.v:70955.9-70955.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\sv_in1[2:0] \dec19_dec19_sv_in1 + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\sv_in1[2:0] \dec30_dec30_sv_in1 + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\sv_in1[2:0] \dec31_dec31_sv_in1 + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\sv_in1[2:0] \dec58_dec58_sv_in1 + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\sv_in1[2:0] \dec62_dec62_sv_in1 + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\sv_in1[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\sv_in1[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\sv_in1[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\sv_in1[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\sv_in1[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\sv_in1[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\sv_in1[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\sv_in1[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\sv_in1[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\sv_in1[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\sv_in1[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\sv_in1[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\sv_in1[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\sv_in1[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\sv_in1[2:0] 3'010 + case + assign $1\sv_in1[2:0] 3'000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\sv_in1[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\sv_in1[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\sv_in1[2:0] 3'000 + case + assign $2\sv_in1[2:0] $1\sv_in1[2:0] + end + sync always + update \sv_in1 $0\sv_in1[2:0] + end + attribute \src "libresoc.v:71096.3-71237.6" + process $proc$libresoc.v:71096$3579 + assign { } { } + assign { } { } + assign { } { } + assign $0\sv_in2[2:0] $2\sv_in2[2:0] + attribute \src "libresoc.v:71097.5-71097.29" + switch \initial + attribute \src "libresoc.v:71097.9-71097.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\sv_in2[2:0] \dec19_dec19_sv_in2 + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\sv_in2[2:0] \dec30_dec30_sv_in2 + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\sv_in2[2:0] \dec31_dec31_sv_in2 + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\sv_in2[2:0] \dec58_dec58_sv_in2 + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\sv_in2[2:0] \dec62_dec62_sv_in2 + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\sv_in2[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\sv_in2[2:0] 3'000 + case + assign $1\sv_in2[2:0] 3'000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\sv_in2[2:0] 3'000 + case + assign $2\sv_in2[2:0] $1\sv_in2[2:0] + end + sync always + update \sv_in2 $0\sv_in2[2:0] + end + attribute \src "libresoc.v:71238.3-71379.6" + process $proc$libresoc.v:71238$3580 + assign { } { } + assign { } { } + assign { } { } + assign $0\sv_in3[2:0] $2\sv_in3[2:0] + attribute \src "libresoc.v:71239.5-71239.29" + switch \initial + attribute \src "libresoc.v:71239.9-71239.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\sv_in3[2:0] \dec19_dec19_sv_in3 + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\sv_in3[2:0] \dec30_dec30_sv_in3 + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\sv_in3[2:0] \dec31_dec31_sv_in3 + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\sv_in3[2:0] \dec58_dec58_sv_in3 + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\sv_in3[2:0] \dec62_dec62_sv_in3 + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\sv_in3[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\sv_in3[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\sv_in3[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\sv_in3[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\sv_in3[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\sv_in3[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\sv_in3[2:0] 3'000 + case + assign $1\sv_in3[2:0] 3'000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\sv_in3[2:0] 3'000 + case + assign $2\sv_in3[2:0] $1\sv_in3[2:0] + end + sync always + update \sv_in3 $0\sv_in3[2:0] + end + attribute \src "libresoc.v:71380.3-71521.6" + process $proc$libresoc.v:71380$3581 + assign { } { } + assign { } { } + assign { } { } + assign $0\sv_out[2:0] $2\sv_out[2:0] + attribute \src "libresoc.v:71381.5-71381.29" + switch \initial + attribute \src "libresoc.v:71381.9-71381.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\sv_out[2:0] \dec19_dec19_sv_out + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\sv_out[2:0] \dec30_dec30_sv_out + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\sv_out[2:0] \dec31_dec31_sv_out + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\sv_out[2:0] \dec58_dec58_sv_out + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\sv_out[2:0] \dec62_dec62_sv_out + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\sv_out[2:0] 3'001 + case + assign $1\sv_out[2:0] 3'000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\sv_out[2:0] 3'000 + case + assign $2\sv_out[2:0] $1\sv_out[2:0] + end + sync always + update \sv_out $0\sv_out[2:0] + end + attribute \src "libresoc.v:71522.3-71663.6" + process $proc$libresoc.v:71522$3582 + assign { } { } + assign { } { } + assign { } { } + assign $0\sv_cr_in[2:0] $2\sv_cr_in[2:0] + attribute \src "libresoc.v:71523.5-71523.29" + switch \initial + attribute \src "libresoc.v:71523.9-71523.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\sv_cr_in[2:0] \dec19_dec19_sv_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\sv_cr_in[2:0] \dec30_dec30_sv_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\sv_cr_in[2:0] \dec31_dec31_sv_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\sv_cr_in[2:0] \dec58_dec58_sv_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\sv_cr_in[2:0] \dec62_dec62_sv_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\sv_cr_in[2:0] 3'000 + case + assign $1\sv_cr_in[2:0] 3'000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\sv_cr_in[2:0] 3'000 + case + assign $2\sv_cr_in[2:0] $1\sv_cr_in[2:0] + end + sync always + update \sv_cr_in $0\sv_cr_in[2:0] + end + attribute \src "libresoc.v:71664.3-71805.6" + process $proc$libresoc.v:71664$3583 + assign { } { } + assign { } { } + assign { } { } + assign $0\sv_cr_out[2:0] $2\sv_cr_out[2:0] + attribute \src "libresoc.v:71665.5-71665.29" + switch \initial + attribute \src "libresoc.v:71665.9-71665.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\sv_cr_out[2:0] \dec19_dec19_sv_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\sv_cr_out[2:0] \dec30_dec30_sv_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\sv_cr_out[2:0] \dec31_dec31_sv_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\sv_cr_out[2:0] \dec58_dec58_sv_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\sv_cr_out[2:0] \dec62_dec62_sv_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\sv_cr_out[2:0] 3'000 + case + assign $1\sv_cr_out[2:0] 3'000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\sv_cr_out[2:0] 3'000 + case + assign $2\sv_cr_out[2:0] $1\sv_cr_out[2:0] + end + sync always + update \sv_cr_out $0\sv_cr_out[2:0] + end + attribute \src "libresoc.v:71806.3-71947.6" + process $proc$libresoc.v:71806$3584 + assign { } { } + assign { } { } + assign { } { } + assign $0\ldst_len[3:0] $2\ldst_len[3:0] + attribute \src "libresoc.v:71807.5-71807.29" + switch \initial + attribute \src "libresoc.v:71807.9-71807.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\ldst_len[3:0] \dec19_dec19_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\ldst_len[3:0] \dec30_dec30_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\ldst_len[3:0] \dec31_dec31_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\ldst_len[3:0] \dec58_dec58_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\ldst_len[3:0] \dec62_dec62_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + case + assign $1\ldst_len[3:0] 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\ldst_len[3:0] 4'0000 + case + assign $2\ldst_len[3:0] $1\ldst_len[3:0] + end + sync always + update \ldst_len $0\ldst_len[3:0] + end + attribute \src "libresoc.v:71948.3-72089.6" + process $proc$libresoc.v:71948$3585 + assign { } { } + assign { } { } + assign { } { } + assign $0\upd[1:0] $2\upd[1:0] + attribute \src "libresoc.v:71949.5-71949.29" + switch \initial + attribute \src "libresoc.v:71949.9-71949.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\upd[1:0] \dec19_dec19_upd + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\upd[1:0] \dec30_dec30_upd + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\upd[1:0] \dec31_dec31_upd + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\upd[1:0] \dec58_dec58_upd + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\upd[1:0] \dec62_dec62_upd + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\upd[1:0] 2'00 + case + assign $1\upd[1:0] 2'00 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\upd[1:0] 2'00 + case + assign $2\upd[1:0] $1\upd[1:0] + end + sync always + update \upd $0\upd[1:0] + end + attribute \src "libresoc.v:72090.3-72231.6" + process $proc$libresoc.v:72090$3586 + assign { } { } + assign { } { } + assign { } { } + assign $0\rc_sel[1:0] $2\rc_sel[1:0] + attribute \src "libresoc.v:72091.5-72091.29" + switch \initial + attribute \src "libresoc.v:72091.9-72091.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\rc_sel[1:0] \dec19_dec19_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\rc_sel[1:0] \dec30_dec30_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\rc_sel[1:0] \dec31_dec31_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\rc_sel[1:0] \dec58_dec58_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\rc_sel[1:0] \dec62_dec62_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\rc_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\rc_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\rc_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + case + assign $1\rc_sel[1:0] 2'00 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\rc_sel[1:0] 2'00 + case + assign $2\rc_sel[1:0] $1\rc_sel[1:0] + end + sync always + update \rc_sel $0\rc_sel[1:0] + end + attribute \src "libresoc.v:72232.3-72373.6" + process $proc$libresoc.v:72232$3587 + assign { } { } + assign { } { } + assign { } { } + assign $0\cry_in[1:0] $2\cry_in[1:0] + attribute \src "libresoc.v:72233.5-72233.29" + switch \initial + attribute \src "libresoc.v:72233.9-72233.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\cry_in[1:0] \dec19_dec19_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\cry_in[1:0] \dec30_dec30_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\cry_in[1:0] \dec31_dec31_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\cry_in[1:0] \dec58_dec58_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\cry_in[1:0] \dec62_dec62_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\cry_in[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\cry_in[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\cry_in[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\cry_in[1:0] 2'00 + case + assign $1\cry_in[1:0] 2'00 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\cry_in[1:0] 2'00 + case + assign $2\cry_in[1:0] $1\cry_in[1:0] + end + sync always + update \cry_in $0\cry_in[1:0] + end + attribute \src "libresoc.v:72374.3-72515.6" + process $proc$libresoc.v:72374$3588 + assign { } { } + assign { } { } + assign { } { } + assign $0\inv_a[0:0] $2\inv_a[0:0] + attribute \src "libresoc.v:72375.5-72375.29" + switch \initial + attribute \src "libresoc.v:72375.9-72375.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\inv_a[0:0] \dec19_dec19_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\inv_a[0:0] \dec30_dec30_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\inv_a[0:0] \dec31_dec31_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\inv_a[0:0] \dec58_dec58_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\inv_a[0:0] \dec62_dec62_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\inv_a[0:0] 1'0 + case + assign $1\inv_a[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\inv_a[0:0] 1'0 + case + assign $2\inv_a[0:0] $1\inv_a[0:0] + end + sync always + update \inv_a $0\inv_a[0:0] + end + attribute \src "libresoc.v:72516.3-72657.6" + process $proc$libresoc.v:72516$3589 + assign { } { } + assign { } { } + assign { } { } + assign $0\inv_out[0:0] $2\inv_out[0:0] + attribute \src "libresoc.v:72517.5-72517.29" + switch \initial + attribute \src "libresoc.v:72517.9-72517.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\inv_out[0:0] \dec19_dec19_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\inv_out[0:0] \dec30_dec30_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\inv_out[0:0] \dec31_dec31_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\inv_out[0:0] \dec58_dec58_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\inv_out[0:0] \dec62_dec62_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\inv_out[0:0] 1'0 + case + assign $1\inv_out[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\inv_out[0:0] 1'0 + case + assign $2\inv_out[0:0] $1\inv_out[0:0] + end + sync always + update \inv_out $0\inv_out[0:0] + end + attribute \src "libresoc.v:72658.3-72799.6" + process $proc$libresoc.v:72658$3590 + assign { } { } + assign { } { } + assign { } { } + assign $0\cry_out[0:0] $2\cry_out[0:0] + attribute \src "libresoc.v:72659.5-72659.29" + switch \initial + attribute \src "libresoc.v:72659.9-72659.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\cry_out[0:0] \dec19_dec19_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\cry_out[0:0] \dec30_dec30_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\cry_out[0:0] \dec31_dec31_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\cry_out[0:0] \dec58_dec58_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\cry_out[0:0] \dec62_dec62_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\cry_out[0:0] 1'0 + case + assign $1\cry_out[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\cry_out[0:0] 1'0 + case + assign $2\cry_out[0:0] $1\cry_out[0:0] + end + sync always + update \cry_out $0\cry_out[0:0] + end + attribute \src "libresoc.v:72800.3-72941.6" + process $proc$libresoc.v:72800$3591 + assign { } { } + assign { } { } + assign { } { } + assign $0\br[0:0] $2\br[0:0] + attribute \src "libresoc.v:72801.5-72801.29" + switch \initial + attribute \src "libresoc.v:72801.9-72801.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\br[0:0] \dec19_dec19_br + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\br[0:0] \dec30_dec30_br + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\br[0:0] \dec31_dec31_br + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\br[0:0] \dec58_dec58_br + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\br[0:0] \dec62_dec62_br + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\br[0:0] 1'0 + case + assign $1\br[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\br[0:0] 1'0 + case + assign $2\br[0:0] $1\br[0:0] + end + sync always + update \br $0\br[0:0] + end + attribute \src "libresoc.v:72942.3-73083.6" + process $proc$libresoc.v:72942$3592 + assign { } { } + assign { } { } + assign { } { } + assign $0\sgn_ext[0:0] $2\sgn_ext[0:0] + attribute \src "libresoc.v:72943.5-72943.29" + switch \initial + attribute \src "libresoc.v:72943.9-72943.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\sgn_ext[0:0] \dec19_dec19_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\sgn_ext[0:0] \dec30_dec30_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\sgn_ext[0:0] \dec31_dec31_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\sgn_ext[0:0] \dec58_dec58_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\sgn_ext[0:0] \dec62_dec62_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\sgn_ext[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\sgn_ext[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + case + assign $1\sgn_ext[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\sgn_ext[0:0] 1'0 + case + assign $2\sgn_ext[0:0] $1\sgn_ext[0:0] + end + sync always + update \sgn_ext $0\sgn_ext[0:0] + end + attribute \src "libresoc.v:73084.3-73225.6" + process $proc$libresoc.v:73084$3593 + assign { } { } + assign { } { } + assign { } { } + assign $0\rsrv[0:0] $2\rsrv[0:0] + attribute \src "libresoc.v:73085.5-73085.29" + switch \initial + attribute \src "libresoc.v:73085.9-73085.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\rsrv[0:0] \dec19_dec19_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\rsrv[0:0] \dec30_dec30_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\rsrv[0:0] \dec31_dec31_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\rsrv[0:0] \dec58_dec58_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\rsrv[0:0] \dec62_dec62_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\rsrv[0:0] 1'0 + case + assign $1\rsrv[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\rsrv[0:0] 1'0 + case + assign $2\rsrv[0:0] $1\rsrv[0:0] + end + sync always + update \rsrv $0\rsrv[0:0] + end + attribute \src "libresoc.v:73226.3-73367.6" + process $proc$libresoc.v:73226$3594 + assign { } { } + assign { } { } + assign { } { } + assign $0\is_32b[0:0] $2\is_32b[0:0] + attribute \src "libresoc.v:73227.5-73227.29" + switch \initial + attribute \src "libresoc.v:73227.9-73227.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\is_32b[0:0] \dec19_dec19_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\is_32b[0:0] \dec30_dec30_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\is_32b[0:0] \dec31_dec31_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\is_32b[0:0] \dec58_dec58_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\is_32b[0:0] \dec62_dec62_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\is_32b[0:0] 1'0 + case + assign $1\is_32b[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\is_32b[0:0] 1'0 + case + assign $2\is_32b[0:0] $1\is_32b[0:0] + end + sync always + update \is_32b $0\is_32b[0:0] + end + attribute \src "libresoc.v:73368.3-73509.6" + process $proc$libresoc.v:73368$3595 + assign { } { } + assign { } { } + assign { } { } + assign $0\sgn[0:0] $2\sgn[0:0] + attribute \src "libresoc.v:73369.5-73369.29" + switch \initial + attribute \src "libresoc.v:73369.9-73369.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\sgn[0:0] \dec19_dec19_sgn + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\sgn[0:0] \dec30_dec30_sgn + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\sgn[0:0] \dec31_dec31_sgn + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\sgn[0:0] \dec58_dec58_sgn + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\sgn[0:0] \dec62_dec62_sgn + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\sgn[0:0] 1'0 + case + assign $1\sgn[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\sgn[0:0] 1'0 + case + assign $2\sgn[0:0] $1\sgn[0:0] + end + sync always + update \sgn $0\sgn[0:0] + end + attribute \src "libresoc.v:73510.3-73651.6" + process $proc$libresoc.v:73510$3596 + assign { } { } + assign { } { } + assign { } { } + assign $0\lk[0:0] $2\lk[0:0] + attribute \src "libresoc.v:73511.5-73511.29" + switch \initial + attribute \src "libresoc.v:73511.9-73511.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\lk[0:0] \dec19_dec19_lk + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\lk[0:0] \dec30_dec30_lk + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\lk[0:0] \dec31_dec31_lk + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\lk[0:0] \dec58_dec58_lk + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\lk[0:0] \dec62_dec62_lk + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\lk[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\lk[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\lk[0:0] 1'0 + case + assign $1\lk[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\lk[0:0] 1'0 + case + assign $2\lk[0:0] $1\lk[0:0] + end + sync always + update \lk $0\lk[0:0] + end + attribute \src "libresoc.v:73652.3-73793.6" + process $proc$libresoc.v:73652$3597 + assign { } { } + assign { } { } + assign { } { } + assign $0\sgl_pipe[0:0] $2\sgl_pipe[0:0] + attribute \src "libresoc.v:73653.5-73653.29" + switch \initial + attribute \src "libresoc.v:73653.9-73653.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\sgl_pipe[0:0] \dec19_dec19_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\sgl_pipe[0:0] \dec30_dec30_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\sgl_pipe[0:0] \dec31_dec31_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\sgl_pipe[0:0] \dec58_dec58_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\sgl_pipe[0:0] \dec62_dec62_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + case + assign $1\sgl_pipe[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\sgl_pipe[0:0] 1'1 + case + assign $2\sgl_pipe[0:0] $1\sgl_pipe[0:0] + end + sync always + update \sgl_pipe $0\sgl_pipe[0:0] + end + attribute \src "libresoc.v:73794.3-73935.6" + process $proc$libresoc.v:73794$3598 + assign { } { } + assign { } { } + assign { } { } + assign $0\function_unit[12:0] $2\function_unit[12:0] + attribute \src "libresoc.v:73795.5-73795.29" + switch \initial + attribute \src "libresoc.v:73795.9-73795.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\function_unit[12:0] \dec19_dec19_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\function_unit[12:0] \dec30_dec30_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\function_unit[12:0] \dec31_dec31_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\function_unit[12:0] \dec58_dec58_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\function_unit[12:0] \dec62_dec62_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\function_unit[12:0] 13'0000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\function_unit[12:0] 13'0000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\function_unit[12:0] 13'0000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\function_unit[12:0] 13'0000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\function_unit[12:0] 13'0000010000000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\function_unit[12:0] 13'0000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\function_unit[12:0] 13'0000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\function_unit[12:0] 13'0000000100000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\function_unit[12:0] 13'0000000100000 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\function_unit[12:0] 13'0000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\function_unit[12:0] 13'0000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\function_unit[12:0] 13'0000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\function_unit[12:0] 13'0000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\function_unit[12:0] 13'0000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\function_unit[12:0] 13'0000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\function_unit[12:0] 13'0000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\function_unit[12:0] 13'0000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\function_unit[12:0] 13'0000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\function_unit[12:0] 13'0000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\function_unit[12:0] 13'0000100000000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\function_unit[12:0] 13'0000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\function_unit[12:0] 13'0000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\function_unit[12:0] 13'0000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\function_unit[12:0] 13'0000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\function_unit[12:0] 13'0000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\function_unit[12:0] 13'0000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\function_unit[12:0] 13'0000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\function_unit[12:0] 13'0000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\function_unit[12:0] 13'0000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\function_unit[12:0] 13'0000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\function_unit[12:0] 13'0000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\function_unit[12:0] 13'0000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\function_unit[12:0] 13'0000010000000 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\function_unit[12:0] 13'0000010000000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\function_unit[12:0] 13'0000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\function_unit[12:0] 13'0000000010000 + case + assign $1\function_unit[12:0] 13'0000000000000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\function_unit[12:0] 13'0000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\function_unit[12:0] 13'0000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\function_unit[12:0] 13'0000000000000 + case + assign $2\function_unit[12:0] $1\function_unit[12:0] + end + sync always + update \function_unit $0\function_unit[12:0] + end + attribute \src "libresoc.v:73936.3-74077.6" + process $proc$libresoc.v:73936$3599 + assign { } { } + assign { } { } + assign { } { } + assign $0\internal_op[6:0] $2\internal_op[6:0] + attribute \src "libresoc.v:73937.5-73937.29" + switch \initial + attribute \src "libresoc.v:73937.9-73937.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\internal_op[6:0] \dec19_dec19_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\internal_op[6:0] \dec30_dec30_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\internal_op[6:0] \dec31_dec31_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\internal_op[6:0] \dec58_dec58_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\internal_op[6:0] \dec62_dec62_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\internal_op[6:0] 7'1001001 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\internal_op[6:0] 7'0000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\internal_op[6:0] 7'0000100 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\internal_op[6:0] 7'0000110 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\internal_op[6:0] 7'0000111 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\internal_op[6:0] 7'0001010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\internal_op[6:0] 7'0001010 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\internal_op[6:0] 7'0110010 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\internal_op[6:0] 7'0110101 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\internal_op[6:0] 7'0110101 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\internal_op[6:0] 7'0111000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\internal_op[6:0] 7'0111000 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\internal_op[6:0] 7'0111000 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\internal_op[6:0] 7'0111111 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\internal_op[6:0] 7'0111111 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\internal_op[6:0] 7'1000011 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\internal_op[6:0] 7'1000011 + case + assign $1\internal_op[6:0] 7'0000000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\internal_op[6:0] 7'0000101 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\internal_op[6:0] 7'0000001 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\internal_op[6:0] 7'1000100 + case + assign $2\internal_op[6:0] $1\internal_op[6:0] + end + sync always + update \internal_op $0\internal_op[6:0] + end + attribute \src "libresoc.v:74078.3-74219.6" + process $proc$libresoc.v:74078$3600 + assign { } { } + assign { } { } + assign { } { } + assign $0\form[4:0] $2\form[4:0] + attribute \src "libresoc.v:74079.5-74079.29" + switch \initial + attribute \src "libresoc.v:74079.9-74079.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\form[4:0] \dec19_dec19_form + attribute \src "libresoc.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\form[4:0] \dec30_dec30_form + attribute \src "libresoc.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\form[4:0] \dec31_dec31_form + attribute \src "libresoc.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\form[4:0] \dec58_dec58_form + attribute \src "libresoc.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\form[4:0] \dec62_dec62_form + attribute \src "libresoc.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\form[4:0] 5'00011 + attribute \src "libresoc.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\form[4:0] 5'00010 + attribute \src "libresoc.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\form[4:0] 5'00010 + attribute \src "libresoc.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\form[4:0] 5'00001 + attribute \src "libresoc.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\form[4:0] 5'00010 + attribute \src "libresoc.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\form[4:0] 5'10011 + attribute \src "libresoc.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\form[4:0] 5'10011 + attribute \src "libresoc.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\form[4:0] 5'10011 + attribute \src "libresoc.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\form[4:0] 5'00100 + case + assign $1\form[4:0] 5'00000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch$1 + attribute \src "libresoc.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\form[4:0] 5'00000 + attribute \src "libresoc.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\form[4:0] 5'00100 + attribute \src "libresoc.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\form[4:0] 5'00000 + case + assign $2\form[4:0] $1\form[4:0] + end + sync always + update \form $0\form[4:0] + end + connect \$2 $ternary$libresoc.v:69503$3568_Y + connect \VC_XO \opcode_in [9:0] + connect \VC_VRT \opcode_in [25:21] + connect \VC_VRB \opcode_in [15:11] + connect \VC_VRA \opcode_in [20:16] + connect \VC_Rc \opcode_in [10] + connect \XS_XO \opcode_in [10:2] + connect \XS_sh { \opcode_in [1] \opcode_in [15:11] } + connect \XS_RS \opcode_in [25:21] + connect \XS_Rc \opcode_in [0] + connect \XS_RA \opcode_in [20:16] + connect \VA_XO \opcode_in [5:0] + connect \VA_VRT \opcode_in [25:21] + connect \VA_VRC \opcode_in [10:6] + connect \VA_VRB \opcode_in [15:11] + connect \VA_VRA \opcode_in [20:16] + connect \VA_SHB \opcode_in [9:6] + connect \VA_RT \opcode_in [25:21] + connect \VA_RC \opcode_in [10:6] + connect \VA_RB \opcode_in [15:11] + connect \VA_RA \opcode_in [20:16] + connect \TX_XO \opcode_in [6:1] + connect \TX_XBI \opcode_in [10:7] + connect \TX_UI \opcode_in [15:11] + connect \TX_RA \opcode_in [20:16] + connect \DQE_XO \opcode_in [1:0] + connect \DQE_RT \opcode_in [25:21] + connect \DQE_RA \opcode_in [20:16] + connect \XO_XO \opcode_in [9:1] + connect \XO_RT \opcode_in [25:21] + connect \XO_Rc \opcode_in [0] + connect \XO_RB \opcode_in [15:11] + connect \XO_RA \opcode_in [20:16] + connect \XO_OE \opcode_in [10] + connect \all_PO \opcode_in [31:26] + connect \all_OPCD \opcode_in [31:26] + connect \SVL_XO \opcode_in [5:1] + connect \SVL_vs \opcode_in [7] + connect \SVL_SVi \opcode_in [15:10] + connect \SVL_RT \opcode_in [25:21] + connect \SVL_Rc \opcode_in [0] + connect \SVL_RA \opcode_in [20:16] + connect \SVL_ms \opcode_in [6] + connect \MD_XO \opcode_in [4:2] + connect \MD_sh { \opcode_in [1] \opcode_in [15:11] } + connect \MD_RS \opcode_in [25:21] + connect \MD_Rc \opcode_in [0] + connect \MD_RA \opcode_in [20:16] + connect \MD_me \opcode_in [10:5] + connect \MD_mb \opcode_in [10:5] + connect \M_SH \opcode_in [15:11] + connect \M_RS \opcode_in [25:21] + connect \M_Rc \opcode_in [0] + connect \M_RB \opcode_in [15:11] + connect \M_RA \opcode_in [20:16] + connect \M_ME \opcode_in [5:1] + connect \M_MB \opcode_in [10:6] + connect \SC_XO_1 \opcode_in [1:0] + connect \SC_XO \opcode_in [1] + connect \SC_LEV \opcode_in [11:5] + connect \MDS_XO \opcode_in [4:1] + connect \MDS_XBI_1 \opcode_in [10:7] + connect \MDS_XBI \opcode_in [10:7] + connect \MDS_RS \opcode_in [25:21] + connect \MDS_Rc \opcode_in [0] + connect \MDS_RB \opcode_in [15:11] + connect \MDS_RA \opcode_in [20:16] + connect \MDS_me \opcode_in [10:5] + connect \MDS_mb \opcode_in [10:5] + connect \MDS_IS \opcode_in [25:21] + connect \MDS_IB \opcode_in [15:11] + connect \Z23_XO \opcode_in [8:1] + connect \Z23_TE \opcode_in [20:16] + connect \Z23_RMC \opcode_in [10:9] + connect \Z23_Rc \opcode_in [0] + connect \Z23_R \opcode_in [16] + connect \Z23_FRTp \opcode_in [25:21] + connect \Z23_FRT \opcode_in [25:21] + connect \Z23_FRBp \opcode_in [15:11] + connect \Z23_FRB \opcode_in [15:11] + connect \Z23_FRAp \opcode_in [20:16] + connect \Z23_FRA \opcode_in [20:16] + connect \XFL_XO \opcode_in [10:1] + connect \XFL_W \opcode_in [16] + connect \XFL_Rc \opcode_in [0] + connect \XFL_L \opcode_in [25] + connect \XFL_FRB \opcode_in [15:11] + connect \XFL_FLM \opcode_in [24:17] + connect \VX_XO_1 \opcode_in [10:0] + connect \VX_XO { \opcode_in [10] \opcode_in [8:0] } + connect \VX_VRT \opcode_in [25:21] + connect \VX_VRB \opcode_in [15:11] + connect \VX_VRA \opcode_in [20:16] + connect \VX_UIM_3 \opcode_in [17:16] + connect \VX_UIM_2 \opcode_in [18:16] + connect \VX_UIM_1 \opcode_in [19:16] + connect \VX_UIM \opcode_in [20:16] + connect \VX_SIM \opcode_in [20:16] + connect \VX_RT \opcode_in [25:21] + connect \VX_RA \opcode_in [20:16] + connect \VX_PS \opcode_in [9] + connect \VX_EO \opcode_in [20:16] + connect \DS_XO \opcode_in [1:0] + connect \DS_VRT \opcode_in [25:21] + connect \DS_VRS \opcode_in [25:21] + connect \DS_RT \opcode_in [25:21] + connect \DS_RSp \opcode_in [25:21] + connect \DS_RS \opcode_in [25:21] + connect \DS_RA \opcode_in [20:16] + connect \DS_FRTp \opcode_in [25:21] + connect \DS_FRSp \opcode_in [25:21] + connect \DS_DS \opcode_in [15:2] + connect \DQ_XO \opcode_in [2:0] + connect \DQ_TX_T { \opcode_in [3] \opcode_in [25:21] } + connect \DQ_T \opcode_in [25:21] + connect \DQ_TX \opcode_in [3] + connect \DQ_SX_S { \opcode_in [3] \opcode_in [25:21] } + connect \DQ_S \opcode_in [25:21] + connect \DQ_SX \opcode_in [3] + connect \DQ_RTp \opcode_in [25:21] + connect \DQ_RA \opcode_in [20:16] + connect \DQ_PT \opcode_in [3:0] + connect \DQ_DQ \opcode_in [15:4] + connect \DX_XO \opcode_in [5:1] + connect \DX_RT \opcode_in [25:21] + connect \DX_d0_d1_d2 { \opcode_in [15:6] \opcode_in [20:16] \opcode_in [0] } + connect \DX_d2 \opcode_in [0] + connect \DX_d1 \opcode_in [20:16] + connect \DX_d0 \opcode_in [15:6] + connect \XFX_XO \opcode_in [10:1] + connect \XFX_SPR \opcode_in [20:11] + connect \XFX_RT \opcode_in [25:21] + connect \XFX_RS \opcode_in [25:21] + connect \XFX_FXM \opcode_in [19:12] + connect \XFX_DUIS \opcode_in [20:11] + connect \XFX_DUI \opcode_in [25:21] + connect \XFX_BHRBE \opcode_in [20:11] + connect \EVS_BFA \opcode_in [2:0] + connect \Z22_XO \opcode_in [9:1] + connect \Z22_SH \opcode_in [15:10] + connect \Z22_Rc \opcode_in [0] + connect \Z22_FRTp \opcode_in [25:21] + connect \Z22_FRT \opcode_in [25:21] + connect \Z22_FRAp \opcode_in [20:16] + connect \Z22_FRA \opcode_in [20:16] + connect \Z22_DGM \opcode_in [15:10] + connect \Z22_DCM \opcode_in [15:10] + connect \Z22_BF \opcode_in [25:23] + connect \XX2_XO_1 \opcode_in [10:2] + connect \XX2_XO { \opcode_in [10:7] \opcode_in [5:3] } + connect \XX2_UIM_1 \opcode_in [17:16] + connect \XX2_UIM \opcode_in [19:16] + connect \XX2_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX2_T \opcode_in [25:21] + connect \XX2_TX \opcode_in [0] + connect \XX2_RT \opcode_in [25:21] + connect \XX2_EO \opcode_in [20:16] + connect \XX2_DCMX \opcode_in [22:16] + connect \XX2_dc_dm_dx { \opcode_in [6] \opcode_in [2] \opcode_in [20:16] } + connect \XX2_dx \opcode_in [20:16] + connect \XX2_dm \opcode_in [2] + connect \XX2_dc \opcode_in [6] + connect \XX2_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX2_B \opcode_in [15:11] + connect \XX2_BX \opcode_in [1] + connect \XX2_BF \opcode_in [25:23] + connect \D_UI \opcode_in [15:0] + connect \D_TO \opcode_in [25:21] + connect \D_SI \opcode_in [15:0] + connect \D_RT \opcode_in [25:21] + connect \D_RS \opcode_in [25:21] + connect \D_RA \opcode_in [20:16] + connect \D_L \opcode_in [21] + connect \D_FRT \opcode_in [25:21] + connect \D_FRS \opcode_in [25:21] + connect \D_D \opcode_in [15:0] + connect \D_BF \opcode_in [25:23] + connect \A_XO \opcode_in [5:1] + connect \A_RT \opcode_in [25:21] + connect \A_Rc \opcode_in [0] + connect \A_RB \opcode_in [15:11] + connect \A_RA \opcode_in [20:16] + connect \A_FRT \opcode_in [25:21] + connect \A_FRC \opcode_in [10:6] + connect \A_FRB \opcode_in [15:11] + connect \A_FRA \opcode_in [20:16] + connect \A_BC \opcode_in [10:6] + connect \XL_XO \opcode_in [10:1] + connect \XL_S \opcode_in [11] + connect \XL_OC \opcode_in [25:11] + connect \XL_LK \opcode_in [0] + connect \XL_BT \opcode_in [25:21] + connect \XL_BO_1 \opcode_in [25:21] + connect \XL_BO \opcode_in [25:21] + connect \XL_BI \opcode_in [20:16] + connect \XL_BH \opcode_in [12:11] + connect \XL_BFA \opcode_in [20:18] + connect \XL_BF \opcode_in [25:23] + connect \XL_BB \opcode_in [15:11] + connect \XL_BA \opcode_in [20:16] + connect \XX4_XO \opcode_in [5:4] + connect \XX4_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX4_T \opcode_in [25:21] + connect \XX4_TX \opcode_in [0] + connect \XX4_CX_C { \opcode_in [3] \opcode_in [10:6] } + connect \XX4_C \opcode_in [10:6] + connect \XX4_CX \opcode_in [3] + connect \XX4_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX4_B \opcode_in [15:11] + connect \XX4_BX \opcode_in [1] + connect \XX4_AX_A { \opcode_in [2] \opcode_in [20:16] } + connect \XX4_A \opcode_in [20:16] + connect \XX4_AX \opcode_in [2] + connect \XX3_XO_2 \opcode_in [9:1] + connect \XX3_XO_1 \opcode_in [10:3] + connect \XX3_XO \opcode_in [10:7] + connect \XX3_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX3_T \opcode_in [25:21] + connect \XX3_TX \opcode_in [0] + connect \XX3_SHW \opcode_in [9:8] + connect \XX3_Rc \opcode_in [10] + connect \XX3_DM \opcode_in [9:8] + connect \XX3_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX3_B \opcode_in [15:11] + connect \XX3_BX \opcode_in [1] + connect \XX3_BF \opcode_in [25:23] + connect \XX3_AX_A { \opcode_in [2] \opcode_in [20:16] } + connect \XX3_A \opcode_in [20:16] + connect \XX3_AX \opcode_in [2] + connect \I_LK \opcode_in [0] + connect \I_LI \opcode_in [25:2] + connect \I_AA \opcode_in [1] + connect \B_LK \opcode_in [0] + connect \B_BO \opcode_in [25:21] + connect \B_BI \opcode_in [20:16] + connect \B_BD \opcode_in [15:2] + connect \B_AA \opcode_in [1] + connect \X_XO_1 \opcode_in [8:1] + connect \X_XO \opcode_in [10:1] + connect \X_WC \opcode_in [22:21] + connect \X_W \opcode_in [16] + connect \X_VRT \opcode_in [25:21] + connect \X_VRS \opcode_in [25:21] + connect \X_UIM \opcode_in [20:16] + connect \X_U \opcode_in [15:12] + connect \X_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \X_TX \opcode_in [0] + connect \X_TO \opcode_in [25:21] + connect \X_TH \opcode_in [25:21] + connect \X_TBR \opcode_in [20:11] + connect \X_T \opcode_in [25:21] + connect \X_SX_S { \opcode_in [0] \opcode_in [25:21] } + connect \X_SX \opcode_in [0] + connect \X_SR \opcode_in [19:16] + connect \X_SP \opcode_in [20:19] + connect \X_SI \opcode_in [15:11] + connect \X_SH \opcode_in [15:11] + connect \X_S \opcode_in [25:21] + connect \X_RTp \opcode_in [25:21] + connect \X_RT \opcode_in [25:21] + connect \X_RSp \opcode_in [25:21] + connect \X_RS \opcode_in [25:21] + connect \X_RO \opcode_in [0] + connect \X_RM \opcode_in [12:11] + connect \X_RIC \opcode_in [19:18] + connect \X_Rc \opcode_in [0] + connect \X_RB \opcode_in [15:11] + connect \X_RA \opcode_in [20:16] + connect \X_R_1 \opcode_in [16] + connect \X_R \opcode_in [21] + connect \X_PRS \opcode_in [17] + connect \X_NB \opcode_in [15:11] + connect \X_MO \opcode_in [25:21] + connect \X_L3 \opcode_in [17:16] + connect \X_L1 \opcode_in [16] + connect \X_L \opcode_in [21] + connect \X_L2 \opcode_in [22:21] + connect \X_IMM8 \opcode_in [18:11] + connect \X_IH \opcode_in [23:21] + connect \X_FRTp \opcode_in [25:21] + connect \X_FRT \opcode_in [25:21] + connect \X_FRSp \opcode_in [25:21] + connect \X_FRS \opcode_in [25:21] + connect \X_FRBp \opcode_in [15:11] + connect \X_FRB \opcode_in [15:11] + connect \X_FRAp \opcode_in [20:16] + connect \X_FRA \opcode_in [20:16] + connect \X_FC \opcode_in [15:11] + connect \X_EX \opcode_in [0] + connect \X_EO_1 \opcode_in [20:16] + connect \X_EO \opcode_in [20:19] + connect \X_E_1 \opcode_in [19:16] + connect \X_E \opcode_in [15] + connect \X_DRM \opcode_in [13:11] + connect \X_DCMX \opcode_in [22:16] + connect \X_CT \opcode_in [24:21] + connect \X_BO \opcode_in [25:21] + connect \X_BFA \opcode_in [20:18] + connect \X_BF \opcode_in [25:23] + connect \X_A \opcode_in [25] + connect \SPR \opcode_in [20:11] + connect \MB \opcode_in [10:6] + connect \ME \opcode_in [5:1] + connect \SH \opcode_in [15:11] + connect \BC \opcode_in [10:6] + connect \TO \opcode_in [25:21] + connect \DS \opcode_in [15:2] + connect \D \opcode_in [15:0] + connect \BH \opcode_in [12:11] + connect \BI \opcode_in [20:16] + connect \BO \opcode_in [25:21] + connect \FXM \opcode_in [19:12] + connect \BT \opcode_in [25:21] + connect \BA \opcode_in [20:16] + connect \BB \opcode_in [15:11] + connect \CR \opcode_in [10:1] + connect \BF \opcode_in [25:23] + connect \BD \opcode_in [15:2] + connect \OE \opcode_in [10] + connect \Rc \opcode_in [0] + connect \AA \opcode_in [1] + connect \LK \opcode_in [0] + connect \LI \opcode_in [25:2] + connect \ME32 \opcode_in [5:1] + connect \MB32 \opcode_in [10:6] + connect \sh { \opcode_in [1] \opcode_in [15:11] } + connect \SH32 \opcode_in [15:11] + connect \L \opcode_in [21] + connect \UI \opcode_in [15:0] + connect \SI \opcode_in [15:0] + connect \RB \opcode_in [15:11] + connect \RA \opcode_in [20:16] + connect \RT \opcode_in [25:21] + connect \RS \opcode_in [25:21] + connect \opcode_in \$2 + connect \opcode_switch$1 \opcode_in + connect \dec62_opcode_in \opcode_in + connect \dec58_opcode_in \opcode_in + connect \dec31_opcode_in \opcode_in + connect \dec30_opcode_in \opcode_in + connect \dec19_opcode_in \opcode_in + connect \opcode_switch \opcode_in [31:26] +end +attribute \src "libresoc.v:74565.1-76565.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec19" +attribute \generator "nMigen" +module \dec19 + attribute \src "libresoc.v:76252.3-76303.6" + wire width 2 $0\dec19_SV_Etype[1:0] + attribute \src "libresoc.v:76304.3-76355.6" + wire width 2 $0\dec19_SV_Ptype[1:0] + attribute \src "libresoc.v:75628.3-75679.6" + wire width 8 $0\dec19_asmcode[7:0] + attribute \src "libresoc.v:75836.3-75887.6" + wire $0\dec19_br[0:0] + attribute \src "libresoc.v:74952.3-75003.6" + wire width 3 $0\dec19_cr_in[2:0] + attribute \src "libresoc.v:75004.3-75055.6" + wire width 3 $0\dec19_cr_out[2:0] + attribute \src "libresoc.v:75576.3-75627.6" + wire width 2 $0\dec19_cry_in[1:0] + attribute \src "libresoc.v:75784.3-75835.6" + wire $0\dec19_cry_out[0:0] + attribute \src "libresoc.v:76044.3-76095.6" + wire width 5 $0\dec19_form[4:0] + attribute \src "libresoc.v:74900.3-74951.6" + wire width 13 $0\dec19_function_unit[12:0] + attribute \src "libresoc.v:76356.3-76407.6" + wire width 3 $0\dec19_in1_sel[2:0] + attribute \src "libresoc.v:76408.3-76459.6" + wire width 4 $0\dec19_in2_sel[3:0] + attribute \src "libresoc.v:76460.3-76511.6" + wire width 2 $0\dec19_in3_sel[1:0] + attribute \src "libresoc.v:75472.3-75523.6" + wire width 7 $0\dec19_internal_op[6:0] + attribute \src "libresoc.v:75680.3-75731.6" + wire $0\dec19_inv_a[0:0] + attribute \src "libresoc.v:75732.3-75783.6" + wire $0\dec19_inv_out[0:0] + attribute \src "libresoc.v:75992.3-76043.6" + wire $0\dec19_is_32b[0:0] + attribute \src "libresoc.v:75368.3-75419.6" + wire width 4 $0\dec19_ldst_len[3:0] + attribute \src "libresoc.v:76148.3-76199.6" + wire $0\dec19_lk[0:0] + attribute \src "libresoc.v:76512.3-76563.6" + wire width 2 $0\dec19_out_sel[1:0] + attribute \src "libresoc.v:75524.3-75575.6" + wire width 2 $0\dec19_rc_sel[1:0] + attribute \src "libresoc.v:75940.3-75991.6" + wire $0\dec19_rsrv[0:0] + attribute \src "libresoc.v:76200.3-76251.6" + wire $0\dec19_sgl_pipe[0:0] + attribute \src "libresoc.v:76096.3-76147.6" + wire $0\dec19_sgn[0:0] + attribute \src "libresoc.v:75888.3-75939.6" + wire $0\dec19_sgn_ext[0:0] + attribute \src "libresoc.v:75264.3-75315.6" + wire width 3 $0\dec19_sv_cr_in[2:0] + attribute \src "libresoc.v:75316.3-75367.6" + wire width 3 $0\dec19_sv_cr_out[2:0] + attribute \src "libresoc.v:75056.3-75107.6" + wire width 3 $0\dec19_sv_in1[2:0] + attribute \src "libresoc.v:75108.3-75159.6" + wire width 3 $0\dec19_sv_in2[2:0] + attribute \src "libresoc.v:75160.3-75211.6" + wire width 3 $0\dec19_sv_in3[2:0] + attribute \src "libresoc.v:75212.3-75263.6" + wire width 3 $0\dec19_sv_out[2:0] + attribute \src "libresoc.v:75420.3-75471.6" + wire width 2 $0\dec19_upd[1:0] + attribute \src "libresoc.v:74566.7-74566.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:76252.3-76303.6" + wire width 2 $1\dec19_SV_Etype[1:0] + attribute \src "libresoc.v:76304.3-76355.6" + wire width 2 $1\dec19_SV_Ptype[1:0] + attribute \src "libresoc.v:75628.3-75679.6" + wire width 8 $1\dec19_asmcode[7:0] + attribute \src "libresoc.v:75836.3-75887.6" + wire $1\dec19_br[0:0] + attribute \src "libresoc.v:74952.3-75003.6" + wire width 3 $1\dec19_cr_in[2:0] + attribute \src "libresoc.v:75004.3-75055.6" + wire width 3 $1\dec19_cr_out[2:0] + attribute \src "libresoc.v:75576.3-75627.6" + wire width 2 $1\dec19_cry_in[1:0] + attribute \src "libresoc.v:75784.3-75835.6" + wire $1\dec19_cry_out[0:0] + attribute \src "libresoc.v:76044.3-76095.6" + wire width 5 $1\dec19_form[4:0] + attribute \src "libresoc.v:74900.3-74951.6" + wire width 13 $1\dec19_function_unit[12:0] + attribute \src "libresoc.v:76356.3-76407.6" + wire width 3 $1\dec19_in1_sel[2:0] + attribute \src "libresoc.v:76408.3-76459.6" + wire width 4 $1\dec19_in2_sel[3:0] + attribute \src "libresoc.v:76460.3-76511.6" + wire width 2 $1\dec19_in3_sel[1:0] + attribute \src "libresoc.v:75472.3-75523.6" + wire width 7 $1\dec19_internal_op[6:0] + attribute \src "libresoc.v:75680.3-75731.6" + wire $1\dec19_inv_a[0:0] + attribute \src "libresoc.v:75732.3-75783.6" + wire $1\dec19_inv_out[0:0] + attribute \src "libresoc.v:75992.3-76043.6" + wire $1\dec19_is_32b[0:0] + attribute \src "libresoc.v:75368.3-75419.6" + wire width 4 $1\dec19_ldst_len[3:0] + attribute \src "libresoc.v:76148.3-76199.6" + wire $1\dec19_lk[0:0] + attribute \src "libresoc.v:76512.3-76563.6" + wire width 2 $1\dec19_out_sel[1:0] + attribute \src "libresoc.v:75524.3-75575.6" + wire width 2 $1\dec19_rc_sel[1:0] + attribute \src "libresoc.v:75940.3-75991.6" + wire $1\dec19_rsrv[0:0] + attribute \src "libresoc.v:76200.3-76251.6" + wire $1\dec19_sgl_pipe[0:0] + attribute \src "libresoc.v:76096.3-76147.6" + wire $1\dec19_sgn[0:0] + attribute \src "libresoc.v:75888.3-75939.6" + wire $1\dec19_sgn_ext[0:0] + attribute \src "libresoc.v:75264.3-75315.6" + wire width 3 $1\dec19_sv_cr_in[2:0] + attribute \src "libresoc.v:75316.3-75367.6" + wire width 3 $1\dec19_sv_cr_out[2:0] + attribute \src "libresoc.v:75056.3-75107.6" + wire width 3 $1\dec19_sv_in1[2:0] + attribute \src "libresoc.v:75108.3-75159.6" + wire width 3 $1\dec19_sv_in2[2:0] + attribute \src "libresoc.v:75160.3-75211.6" + wire width 3 $1\dec19_sv_in3[2:0] + attribute \src "libresoc.v:75212.3-75263.6" + wire width 3 $1\dec19_sv_out[2:0] + attribute \src "libresoc.v:75420.3-75471.6" + wire width 2 $1\dec19_upd[1:0] + attribute \enum_base_type "SVEtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "EXTRA2" + attribute \enum_value_10 "EXTRA3" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 5 \dec19_SV_Etype + attribute \enum_base_type "SVPtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "P1" + attribute \enum_value_10 "P2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 6 \dec19_SV_Ptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 8 output 4 \dec19_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 26 \dec19_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 11 \dec19_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 12 \dec19_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 22 \dec19_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 25 \dec19_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 5 output 3 \dec19_form + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 13 output 1 \dec19_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 7 \dec19_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 8 \dec19_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 9 \dec19_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 output 2 \dec19_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 23 \dec19_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 24 \dec19_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 29 \dec19_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 19 \dec19_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 31 \dec19_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 10 \dec19_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 21 \dec19_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 28 \dec19_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 32 \dec19_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 30 \dec19_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 27 \dec19_sgn_ext + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 17 \dec19_sv_cr_in + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 18 \dec19_sv_cr_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 13 \dec19_sv_in1 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 14 \dec19_sv_in2 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 15 \dec19_sv_in3 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 16 \dec19_sv_out + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 20 \dec19_upd + attribute \src "libresoc.v:74566.7-74566.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + wire width 32 input 33 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + wire width 10 \opcode_switch + attribute \src "libresoc.v:74566.7-74566.20" + process $proc$libresoc.v:74566$3634 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:74900.3-74951.6" + process $proc$libresoc.v:74900$3602 + assign { } { } + assign { } { } + assign $0\dec19_function_unit[12:0] $1\dec19_function_unit[12:0] + attribute \src "libresoc.v:74901.5-74901.29" + switch \initial + attribute \src "libresoc.v:74901.9-74901.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_function_unit[12:0] 13'0000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_function_unit[12:0] 13'0000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_function_unit[12:0] 13'0000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_function_unit[12:0] 13'0000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_function_unit[12:0] 13'0000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_function_unit[12:0] 13'0000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_function_unit[12:0] 13'0000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_function_unit[12:0] 13'0000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_function_unit[12:0] 13'0000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_function_unit[12:0] 13'0000000100000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_function_unit[12:0] 13'0000000100000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_function_unit[12:0] 13'0000000100000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_function_unit[12:0] 13'0000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_function_unit[12:0] 13'0000010000000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_function_unit[12:0] 13'0000010000000 + case + assign $1\dec19_function_unit[12:0] 13'0000000000000 + end + sync always + update \dec19_function_unit $0\dec19_function_unit[12:0] + end + attribute \src "libresoc.v:74952.3-75003.6" + process $proc$libresoc.v:74952$3603 + assign { } { } + assign { } { } + assign $0\dec19_cr_in[2:0] $1\dec19_cr_in[2:0] + attribute \src "libresoc.v:74953.5-74953.29" + switch \initial + attribute \src "libresoc.v:74953.9-74953.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_cr_in[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_cr_in[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_cr_in[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_cr_in[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_cr_in[2:0] 3'000 + case + assign $1\dec19_cr_in[2:0] 3'000 + end + sync always + update \dec19_cr_in $0\dec19_cr_in[2:0] + end + attribute \src "libresoc.v:75004.3-75055.6" + process $proc$libresoc.v:75004$3604 + assign { } { } + assign { } { } + assign $0\dec19_cr_out[2:0] $1\dec19_cr_out[2:0] + attribute \src "libresoc.v:75005.5-75005.29" + switch \initial + attribute \src "libresoc.v:75005.9-75005.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_cr_out[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_cr_out[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_cr_out[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_cr_out[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_cr_out[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_cr_out[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_cr_out[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_cr_out[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_cr_out[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_cr_out[2:0] 3'000 + case + assign $1\dec19_cr_out[2:0] 3'000 + end + sync always + update \dec19_cr_out $0\dec19_cr_out[2:0] + end + attribute \src "libresoc.v:75056.3-75107.6" + process $proc$libresoc.v:75056$3605 + assign { } { } + assign { } { } + assign $0\dec19_sv_in1[2:0] $1\dec19_sv_in1[2:0] + attribute \src "libresoc.v:75057.5-75057.29" + switch \initial + attribute \src "libresoc.v:75057.9-75057.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_sv_in1[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_sv_in1[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_sv_in1[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_sv_in1[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_sv_in1[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_sv_in1[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_sv_in1[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_sv_in1[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_sv_in1[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_sv_in1[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_sv_in1[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_sv_in1[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_sv_in1[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_sv_in1[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_sv_in1[2:0] 3'000 + case + assign $1\dec19_sv_in1[2:0] 3'000 + end + sync always + update \dec19_sv_in1 $0\dec19_sv_in1[2:0] + end + attribute \src "libresoc.v:75108.3-75159.6" + process $proc$libresoc.v:75108$3606 + assign { } { } + assign { } { } + assign $0\dec19_sv_in2[2:0] $1\dec19_sv_in2[2:0] + attribute \src "libresoc.v:75109.5-75109.29" + switch \initial + attribute \src "libresoc.v:75109.9-75109.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_sv_in2[2:0] 3'000 + case + assign $1\dec19_sv_in2[2:0] 3'000 + end + sync always + update \dec19_sv_in2 $0\dec19_sv_in2[2:0] + end + attribute \src "libresoc.v:75160.3-75211.6" + process $proc$libresoc.v:75160$3607 + assign { } { } + assign { } { } + assign $0\dec19_sv_in3[2:0] $1\dec19_sv_in3[2:0] + attribute \src "libresoc.v:75161.5-75161.29" + switch \initial + attribute \src "libresoc.v:75161.9-75161.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_sv_in3[2:0] 3'000 + case + assign $1\dec19_sv_in3[2:0] 3'000 + end + sync always + update \dec19_sv_in3 $0\dec19_sv_in3[2:0] + end + attribute \src "libresoc.v:75212.3-75263.6" + process $proc$libresoc.v:75212$3608 + assign { } { } + assign { } { } + assign $0\dec19_sv_out[2:0] $1\dec19_sv_out[2:0] + attribute \src "libresoc.v:75213.5-75213.29" + switch \initial + attribute \src "libresoc.v:75213.9-75213.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_sv_out[2:0] 3'000 + case + assign $1\dec19_sv_out[2:0] 3'000 + end + sync always + update \dec19_sv_out $0\dec19_sv_out[2:0] + end + attribute \src "libresoc.v:75264.3-75315.6" + process $proc$libresoc.v:75264$3609 + assign { } { } + assign { } { } + assign $0\dec19_sv_cr_in[2:0] $1\dec19_sv_cr_in[2:0] + attribute \src "libresoc.v:75265.5-75265.29" + switch \initial + attribute \src "libresoc.v:75265.9-75265.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_sv_cr_in[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_sv_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_sv_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_sv_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_sv_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_sv_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_sv_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_sv_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_sv_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_sv_cr_in[2:0] 3'000 + case + assign $1\dec19_sv_cr_in[2:0] 3'000 + end + sync always + update \dec19_sv_cr_in $0\dec19_sv_cr_in[2:0] + end + attribute \src "libresoc.v:75316.3-75367.6" + process $proc$libresoc.v:75316$3610 + assign { } { } + assign { } { } + assign $0\dec19_sv_cr_out[2:0] $1\dec19_sv_cr_out[2:0] + attribute \src "libresoc.v:75317.5-75317.29" + switch \initial + attribute \src "libresoc.v:75317.9-75317.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_sv_cr_out[2:0] 3'000 + case + assign $1\dec19_sv_cr_out[2:0] 3'000 + end + sync always + update \dec19_sv_cr_out $0\dec19_sv_cr_out[2:0] + end + attribute \src "libresoc.v:75368.3-75419.6" + process $proc$libresoc.v:75368$3611 + assign { } { } + assign { } { } + assign $0\dec19_ldst_len[3:0] $1\dec19_ldst_len[3:0] + attribute \src "libresoc.v:75369.5-75369.29" + switch \initial + attribute \src "libresoc.v:75369.9-75369.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_ldst_len[3:0] 4'0000 + case + assign $1\dec19_ldst_len[3:0] 4'0000 + end + sync always + update \dec19_ldst_len $0\dec19_ldst_len[3:0] + end + attribute \src "libresoc.v:75420.3-75471.6" + process $proc$libresoc.v:75420$3612 + assign { } { } + assign { } { } + assign $0\dec19_upd[1:0] $1\dec19_upd[1:0] + attribute \src "libresoc.v:75421.5-75421.29" + switch \initial + attribute \src "libresoc.v:75421.9-75421.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_upd[1:0] 2'00 + case + assign $1\dec19_upd[1:0] 2'00 + end + sync always + update \dec19_upd $0\dec19_upd[1:0] + end + attribute \src "libresoc.v:75472.3-75523.6" + process $proc$libresoc.v:75472$3613 + assign { } { } + assign { } { } + assign $0\dec19_internal_op[6:0] $1\dec19_internal_op[6:0] + attribute \src "libresoc.v:75473.5-75473.29" + switch \initial + attribute \src "libresoc.v:75473.9-75473.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_internal_op[6:0] 7'0101010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_internal_op[6:0] 7'1000101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_internal_op[6:0] 7'1000101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_internal_op[6:0] 7'1000101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_internal_op[6:0] 7'1000101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_internal_op[6:0] 7'1000101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_internal_op[6:0] 7'1000101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_internal_op[6:0] 7'1000101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_internal_op[6:0] 7'1000101 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_internal_op[6:0] 7'0001000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_internal_op[6:0] 7'0001000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_internal_op[6:0] 7'0001000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_internal_op[6:0] 7'0100100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_internal_op[6:0] 7'1000110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_internal_op[6:0] 7'1000110 + case + assign $1\dec19_internal_op[6:0] 7'0000000 + end + sync always + update \dec19_internal_op $0\dec19_internal_op[6:0] + end + attribute \src "libresoc.v:75524.3-75575.6" + process $proc$libresoc.v:75524$3614 + assign { } { } + assign { } { } + assign $0\dec19_rc_sel[1:0] $1\dec19_rc_sel[1:0] + attribute \src "libresoc.v:75525.5-75525.29" + switch \initial + attribute \src "libresoc.v:75525.9-75525.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_rc_sel[1:0] 2'00 + case + assign $1\dec19_rc_sel[1:0] 2'00 + end + sync always + update \dec19_rc_sel $0\dec19_rc_sel[1:0] + end + attribute \src "libresoc.v:75576.3-75627.6" + process $proc$libresoc.v:75576$3615 + assign { } { } + assign { } { } + assign $0\dec19_cry_in[1:0] $1\dec19_cry_in[1:0] + attribute \src "libresoc.v:75577.5-75577.29" + switch \initial + attribute \src "libresoc.v:75577.9-75577.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_cry_in[1:0] 2'00 + case + assign $1\dec19_cry_in[1:0] 2'00 + end + sync always + update \dec19_cry_in $0\dec19_cry_in[1:0] + end + attribute \src "libresoc.v:75628.3-75679.6" + process $proc$libresoc.v:75628$3616 + assign { } { } + assign { } { } + assign $0\dec19_asmcode[7:0] $1\dec19_asmcode[7:0] + attribute \src "libresoc.v:75629.5-75629.29" + switch \initial + attribute \src "libresoc.v:75629.9-75629.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_asmcode[7:0] 8'01101100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_asmcode[7:0] 8'00100101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_asmcode[7:0] 8'00100110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_asmcode[7:0] 8'00100111 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_asmcode[7:0] 8'00101000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_asmcode[7:0] 8'00101001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_asmcode[7:0] 8'00101010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_asmcode[7:0] 8'00101011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_asmcode[7:0] 8'00101100 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_asmcode[7:0] 8'00010110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_asmcode[7:0] 8'00010111 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_asmcode[7:0] 8'00011000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_asmcode[7:0] 8'01001100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_asmcode[7:0] 8'10010001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_asmcode[7:0] 8'01001000 + case + assign $1\dec19_asmcode[7:0] 8'00000000 + end + sync always + update \dec19_asmcode $0\dec19_asmcode[7:0] + end + attribute \src "libresoc.v:75680.3-75731.6" + process $proc$libresoc.v:75680$3617 + assign { } { } + assign { } { } + assign $0\dec19_inv_a[0:0] $1\dec19_inv_a[0:0] + attribute \src "libresoc.v:75681.5-75681.29" + switch \initial + attribute \src "libresoc.v:75681.9-75681.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_inv_a[0:0] 1'0 + case + assign $1\dec19_inv_a[0:0] 1'0 + end + sync always + update \dec19_inv_a $0\dec19_inv_a[0:0] + end + attribute \src "libresoc.v:75732.3-75783.6" + process $proc$libresoc.v:75732$3618 + assign { } { } + assign { } { } + assign $0\dec19_inv_out[0:0] $1\dec19_inv_out[0:0] + attribute \src "libresoc.v:75733.5-75733.29" + switch \initial + attribute \src "libresoc.v:75733.9-75733.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_inv_out[0:0] 1'0 + case + assign $1\dec19_inv_out[0:0] 1'0 + end + sync always + update \dec19_inv_out $0\dec19_inv_out[0:0] + end + attribute \src "libresoc.v:75784.3-75835.6" + process $proc$libresoc.v:75784$3619 + assign { } { } + assign { } { } + assign $0\dec19_cry_out[0:0] $1\dec19_cry_out[0:0] + attribute \src "libresoc.v:75785.5-75785.29" + switch \initial + attribute \src "libresoc.v:75785.9-75785.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_cry_out[0:0] 1'0 + case + assign $1\dec19_cry_out[0:0] 1'0 + end + sync always + update \dec19_cry_out $0\dec19_cry_out[0:0] + end + attribute \src "libresoc.v:75836.3-75887.6" + process $proc$libresoc.v:75836$3620 + assign { } { } + assign { } { } + assign $0\dec19_br[0:0] $1\dec19_br[0:0] + attribute \src "libresoc.v:75837.5-75837.29" + switch \initial + attribute \src "libresoc.v:75837.9-75837.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_br[0:0] 1'0 + case + assign $1\dec19_br[0:0] 1'0 + end + sync always + update \dec19_br $0\dec19_br[0:0] + end + attribute \src "libresoc.v:75888.3-75939.6" + process $proc$libresoc.v:75888$3621 + assign { } { } + assign { } { } + assign $0\dec19_sgn_ext[0:0] $1\dec19_sgn_ext[0:0] + attribute \src "libresoc.v:75889.5-75889.29" + switch \initial + attribute \src "libresoc.v:75889.9-75889.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_sgn_ext[0:0] 1'0 + case + assign $1\dec19_sgn_ext[0:0] 1'0 + end + sync always + update \dec19_sgn_ext $0\dec19_sgn_ext[0:0] + end + attribute \src "libresoc.v:75940.3-75991.6" + process $proc$libresoc.v:75940$3622 + assign { } { } + assign { } { } + assign $0\dec19_rsrv[0:0] $1\dec19_rsrv[0:0] + attribute \src "libresoc.v:75941.5-75941.29" + switch \initial + attribute \src "libresoc.v:75941.9-75941.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_rsrv[0:0] 1'0 + case + assign $1\dec19_rsrv[0:0] 1'0 + end + sync always + update \dec19_rsrv $0\dec19_rsrv[0:0] + end + attribute \src "libresoc.v:75992.3-76043.6" + process $proc$libresoc.v:75992$3623 + assign { } { } + assign { } { } + assign $0\dec19_is_32b[0:0] $1\dec19_is_32b[0:0] + attribute \src "libresoc.v:75993.5-75993.29" + switch \initial + attribute \src "libresoc.v:75993.9-75993.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_is_32b[0:0] 1'0 + case + assign $1\dec19_is_32b[0:0] 1'0 + end + sync always + update \dec19_is_32b $0\dec19_is_32b[0:0] + end + attribute \src "libresoc.v:76044.3-76095.6" + process $proc$libresoc.v:76044$3624 + assign { } { } + assign { } { } + assign $0\dec19_form[4:0] $1\dec19_form[4:0] + attribute \src "libresoc.v:76045.5-76045.29" + switch \initial + attribute \src "libresoc.v:76045.9-76045.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_form[4:0] 5'01001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_form[4:0] 5'01001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_form[4:0] 5'01001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_form[4:0] 5'01001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_form[4:0] 5'01001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_form[4:0] 5'01001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_form[4:0] 5'01001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_form[4:0] 5'01001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_form[4:0] 5'01001 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_form[4:0] 5'01001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_form[4:0] 5'01001 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_form[4:0] 5'01001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_form[4:0] 5'01001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_form[4:0] 5'01001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_form[4:0] 5'01001 + case + assign $1\dec19_form[4:0] 5'00000 + end + sync always + update \dec19_form $0\dec19_form[4:0] + end + attribute \src "libresoc.v:76096.3-76147.6" + process $proc$libresoc.v:76096$3625 + assign { } { } + assign { } { } + assign $0\dec19_sgn[0:0] $1\dec19_sgn[0:0] + attribute \src "libresoc.v:76097.5-76097.29" + switch \initial + attribute \src "libresoc.v:76097.9-76097.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_sgn[0:0] 1'0 + case + assign $1\dec19_sgn[0:0] 1'0 + end + sync always + update \dec19_sgn $0\dec19_sgn[0:0] + end + attribute \src "libresoc.v:76148.3-76199.6" + process $proc$libresoc.v:76148$3626 + assign { } { } + assign { } { } + assign $0\dec19_lk[0:0] $1\dec19_lk[0:0] + attribute \src "libresoc.v:76149.5-76149.29" + switch \initial + attribute \src "libresoc.v:76149.9-76149.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_lk[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_lk[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_lk[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_lk[0:0] 1'0 + case + assign $1\dec19_lk[0:0] 1'0 + end + sync always + update \dec19_lk $0\dec19_lk[0:0] + end + attribute \src "libresoc.v:76200.3-76251.6" + process $proc$libresoc.v:76200$3627 + assign { } { } + assign { } { } + assign $0\dec19_sgl_pipe[0:0] $1\dec19_sgl_pipe[0:0] + attribute \src "libresoc.v:76201.5-76201.29" + switch \initial + attribute \src "libresoc.v:76201.9-76201.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_sgl_pipe[0:0] 1'0 + case + assign $1\dec19_sgl_pipe[0:0] 1'0 + end + sync always + update \dec19_sgl_pipe $0\dec19_sgl_pipe[0:0] + end + attribute \src "libresoc.v:76252.3-76303.6" + process $proc$libresoc.v:76252$3628 + assign { } { } + assign { } { } + assign $0\dec19_SV_Etype[1:0] $1\dec19_SV_Etype[1:0] + attribute \src "libresoc.v:76253.5-76253.29" + switch \initial + attribute \src "libresoc.v:76253.9-76253.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_SV_Etype[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_SV_Etype[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_SV_Etype[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_SV_Etype[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_SV_Etype[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_SV_Etype[1:0] 2'00 + case + assign $1\dec19_SV_Etype[1:0] 2'00 + end + sync always + update \dec19_SV_Etype $0\dec19_SV_Etype[1:0] + end + attribute \src "libresoc.v:76304.3-76355.6" + process $proc$libresoc.v:76304$3629 + assign { } { } + assign { } { } + assign $0\dec19_SV_Ptype[1:0] $1\dec19_SV_Ptype[1:0] + attribute \src "libresoc.v:76305.5-76305.29" + switch \initial + attribute \src "libresoc.v:76305.9-76305.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_SV_Ptype[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_SV_Ptype[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_SV_Ptype[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_SV_Ptype[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_SV_Ptype[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_SV_Ptype[1:0] 2'00 + case + assign $1\dec19_SV_Ptype[1:0] 2'00 + end + sync always + update \dec19_SV_Ptype $0\dec19_SV_Ptype[1:0] + end + attribute \src "libresoc.v:76356.3-76407.6" + process $proc$libresoc.v:76356$3630 + assign { } { } + assign { } { } + assign $0\dec19_in1_sel[2:0] $1\dec19_in1_sel[2:0] + attribute \src "libresoc.v:76357.5-76357.29" + switch \initial + attribute \src "libresoc.v:76357.9-76357.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_in1_sel[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_in1_sel[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_in1_sel[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_in1_sel[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_in1_sel[2:0] 3'011 + case + assign $1\dec19_in1_sel[2:0] 3'000 + end + sync always + update \dec19_in1_sel $0\dec19_in1_sel[2:0] + end + attribute \src "libresoc.v:76408.3-76459.6" + process $proc$libresoc.v:76408$3631 + assign { } { } + assign { } { } + assign $0\dec19_in2_sel[3:0] $1\dec19_in2_sel[3:0] + attribute \src "libresoc.v:76409.5-76409.29" + switch \initial + attribute \src "libresoc.v:76409.9-76409.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_in2_sel[3:0] 4'1100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_in2_sel[3:0] 4'1100 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_in2_sel[3:0] 4'1100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_in2_sel[3:0] 4'1100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_in2_sel[3:0] 4'1100 + case + assign $1\dec19_in2_sel[3:0] 4'0000 + end + sync always + update \dec19_in2_sel $0\dec19_in2_sel[3:0] + end + attribute \src "libresoc.v:76460.3-76511.6" + process $proc$libresoc.v:76460$3632 + assign { } { } + assign { } { } + assign $0\dec19_in3_sel[1:0] $1\dec19_in3_sel[1:0] + attribute \src "libresoc.v:76461.5-76461.29" + switch \initial + attribute \src "libresoc.v:76461.9-76461.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_in3_sel[1:0] 2'00 + case + assign $1\dec19_in3_sel[1:0] 2'00 + end + sync always + update \dec19_in3_sel $0\dec19_in3_sel[1:0] + end + attribute \src "libresoc.v:76512.3-76563.6" + process $proc$libresoc.v:76512$3633 + assign { } { } + assign { } { } + assign $0\dec19_out_sel[1:0] $1\dec19_out_sel[1:0] + attribute \src "libresoc.v:76513.5-76513.29" + switch \initial + attribute \src "libresoc.v:76513.9-76513.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_out_sel[1:0] 2'11 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_out_sel[1:0] 2'11 + attribute \src "libresoc.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_out_sel[1:0] 2'11 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_out_sel[1:0] 2'00 + case + assign $1\dec19_out_sel[1:0] 2'00 + end + sync always + update \dec19_out_sel $0\dec19_out_sel[1:0] + end + connect \opcode_switch \opcode_in [10:1] +end +attribute \src "libresoc.v:76569.1-79231.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2" +attribute \generator "nMigen" +module \dec2 + attribute \src "libresoc.v:78848.3-79005.6" + wire width 8 $0\asmcode[7:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire width 64 $0\cia[63:0] + attribute \src "libresoc.v:79028.3-79037.6" + wire width 3 $0\cr_a_idx[2:0] + attribute \src "libresoc.v:79038.3-79047.6" + wire width 3 $0\cr_b_idx[2:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire width 7 $0\cr_in1[6:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire $0\cr_in1_ok[0:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire width 7 $0\cr_in2$1[6:0]$3673 + attribute \src "libresoc.v:78848.3-79005.6" + wire width 7 $0\cr_in2[6:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire $0\cr_in2_ok$2[0:0]$3674 + attribute \src "libresoc.v:78848.3-79005.6" + wire $0\cr_in2_ok[0:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire width 7 $0\cr_out[6:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire $0\cr_out_ok[0:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire width 8 $0\cr_rd[7:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire $0\cr_rd_ok[0:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire width 8 $0\cr_wr[7:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire $0\cr_wr_ok[0:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire width 7 $0\ea[6:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire $0\ea_ok[0:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire $0\exc_$signal$3[0:0]$3676 + attribute \src "libresoc.v:78848.3-79005.6" + wire $0\exc_$signal$4[0:0]$3677 + attribute \src "libresoc.v:78848.3-79005.6" + wire $0\exc_$signal$5[0:0]$3678 + attribute \src "libresoc.v:78848.3-79005.6" + wire $0\exc_$signal$6[0:0]$3679 + attribute \src "libresoc.v:78848.3-79005.6" + wire $0\exc_$signal$7[0:0]$3680 + attribute \src "libresoc.v:78848.3-79005.6" + wire $0\exc_$signal$8[0:0]$3681 + attribute \src "libresoc.v:78848.3-79005.6" + wire $0\exc_$signal$9[0:0]$3682 + attribute \src "libresoc.v:78848.3-79005.6" + wire $0\exc_$signal[0:0]$3675 + attribute \src "libresoc.v:78848.3-79005.6" + wire width 3 $0\fast1[2:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire $0\fast1_ok[0:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire width 3 $0\fast2[2:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire $0\fast2_ok[0:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire width 3 $0\fasto1[2:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire $0\fasto1_ok[0:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire width 3 $0\fasto2[2:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire $0\fasto2_ok[0:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire width 13 $0\fn_unit[12:0] + attribute \src "libresoc.v:76570.7-76570.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire width 2 $0\input_carry[1:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire width 32 $0\insn[31:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire width 7 $0\insn_type[6:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire $0\is_32bit[0:0] + attribute \src "libresoc.v:78824.3-78847.6" + wire $0\is_priv_insn[0:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire $0\lk[0:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire width 64 $0\msr[63:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire $0\oe[0:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire $0\oe_ok[0:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire $0\rc[0:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire $0\rc_ok[0:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire width 7 $0\reg1[6:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire $0\reg1_ok[0:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire width 7 $0\reg2[6:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire $0\reg2_ok[0:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire width 7 $0\reg3[6:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire $0\reg3_ok[0:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire width 7 $0\rego[6:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire $0\rego_ok[0:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire width 10 $0\spr1[9:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire $0\spr1_ok[0:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire width 10 $0\spro[9:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire $0\spro_ok[0:0] + attribute \src "libresoc.v:79096.3-79107.6" + wire width 7 $0\tmp_ea[6:0] + attribute \src "libresoc.v:79048.3-79059.6" + wire width 7 $0\tmp_reg1[6:0] + attribute \src "libresoc.v:79060.3-79071.6" + wire width 7 $0\tmp_reg2[6:0] + attribute \src "libresoc.v:79072.3-79083.6" + wire width 7 $0\tmp_reg3[6:0] + attribute \src "libresoc.v:79084.3-79095.6" + wire width 7 $0\tmp_rego[6:0] + attribute \src "libresoc.v:79006.3-79017.6" + wire width 13 $0\tmp_tmp_fn_unit[12:0] + attribute \src "libresoc.v:79018.3-79027.6" + wire $0\tmp_tmp_lk[0:0] + attribute \src "libresoc.v:78814.3-78823.6" + wire width 13 $0\tmp_tmp_trapaddr[12:0] + attribute \src "libresoc.v:78788.3-78803.6" + wire width 3 $0\tmp_xer_in[2:0] + attribute \src "libresoc.v:78804.3-78813.6" + wire $0\tmp_xer_out[0:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire width 13 $0\trapaddr[12:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire width 8 $0\traptype[7:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire width 3 $0\xer_in[2:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire $0\xer_out[0:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire width 8 $1\asmcode[7:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire width 64 $1\cia[63:0] + attribute \src "libresoc.v:79028.3-79037.6" + wire width 3 $1\cr_a_idx[2:0] + attribute \src "libresoc.v:79038.3-79047.6" + wire width 3 $1\cr_b_idx[2:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire width 7 $1\cr_in1[6:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire $1\cr_in1_ok[0:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire width 7 $1\cr_in2$1[6:0]$3683 + attribute \src "libresoc.v:78848.3-79005.6" + wire width 7 $1\cr_in2[6:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire $1\cr_in2_ok$2[0:0]$3684 + attribute \src "libresoc.v:78848.3-79005.6" + wire $1\cr_in2_ok[0:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire width 7 $1\cr_out[6:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire $1\cr_out_ok[0:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire width 8 $1\cr_rd[7:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire $1\cr_rd_ok[0:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire width 8 $1\cr_wr[7:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire $1\cr_wr_ok[0:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire width 7 $1\ea[6:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire $1\ea_ok[0:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire $1\exc_$signal$3[0:0]$3686 + attribute \src "libresoc.v:78848.3-79005.6" + wire $1\exc_$signal$4[0:0]$3687 + attribute \src "libresoc.v:78848.3-79005.6" + wire $1\exc_$signal$5[0:0]$3688 + attribute \src "libresoc.v:78848.3-79005.6" + wire $1\exc_$signal$6[0:0]$3689 + attribute \src "libresoc.v:78848.3-79005.6" + wire $1\exc_$signal$7[0:0]$3690 + attribute \src "libresoc.v:78848.3-79005.6" + wire $1\exc_$signal$8[0:0]$3691 + attribute \src "libresoc.v:78848.3-79005.6" + wire $1\exc_$signal$9[0:0]$3692 + attribute \src "libresoc.v:78848.3-79005.6" + wire $1\exc_$signal[0:0]$3685 + attribute \src "libresoc.v:78848.3-79005.6" + wire width 3 $1\fast1[2:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire $1\fast1_ok[0:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire width 3 $1\fast2[2:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire $1\fast2_ok[0:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire width 3 $1\fasto1[2:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire $1\fasto1_ok[0:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire width 3 $1\fasto2[2:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire $1\fasto2_ok[0:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire width 13 $1\fn_unit[12:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire width 2 $1\input_carry[1:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire width 32 $1\insn[31:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire width 7 $1\insn_type[6:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire $1\is_32bit[0:0] + attribute \src "libresoc.v:78824.3-78847.6" + wire $1\is_priv_insn[0:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire $1\lk[0:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire width 64 $1\msr[63:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire $1\oe[0:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire $1\oe_ok[0:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire $1\rc[0:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire $1\rc_ok[0:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire width 7 $1\reg1[6:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire $1\reg1_ok[0:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire width 7 $1\reg2[6:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire $1\reg2_ok[0:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire width 7 $1\reg3[6:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire $1\reg3_ok[0:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire width 7 $1\rego[6:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire $1\rego_ok[0:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire width 10 $1\spr1[9:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire $1\spr1_ok[0:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire width 10 $1\spro[9:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire $1\spro_ok[0:0] + attribute \src "libresoc.v:79096.3-79107.6" + wire width 7 $1\tmp_ea[6:0] + attribute \src "libresoc.v:79048.3-79059.6" + wire width 7 $1\tmp_reg1[6:0] + attribute \src "libresoc.v:79060.3-79071.6" + wire width 7 $1\tmp_reg2[6:0] + attribute \src "libresoc.v:79072.3-79083.6" + wire width 7 $1\tmp_reg3[6:0] + attribute \src "libresoc.v:79084.3-79095.6" + wire width 7 $1\tmp_rego[6:0] + attribute \src "libresoc.v:79006.3-79017.6" + wire width 13 $1\tmp_tmp_fn_unit[12:0] + attribute \src "libresoc.v:79018.3-79027.6" + wire $1\tmp_tmp_lk[0:0] + attribute \src "libresoc.v:78814.3-78823.6" + wire width 13 $1\tmp_tmp_trapaddr[12:0] + attribute \src "libresoc.v:78788.3-78803.6" + wire width 3 $1\tmp_xer_in[2:0] + attribute \src "libresoc.v:78804.3-78813.6" + wire $1\tmp_xer_out[0:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire width 13 $1\trapaddr[12:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire width 8 $1\traptype[7:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire width 3 $1\xer_in[2:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire $1\xer_out[0:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire width 8 $2\asmcode[7:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire width 64 $2\cia[63:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire width 7 $2\cr_in1[6:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire $2\cr_in1_ok[0:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire width 7 $2\cr_in2$1[6:0]$3693 + attribute \src "libresoc.v:78848.3-79005.6" + wire width 7 $2\cr_in2[6:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire $2\cr_in2_ok$2[0:0]$3694 + attribute \src "libresoc.v:78848.3-79005.6" + wire $2\cr_in2_ok[0:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire width 7 $2\cr_out[6:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire $2\cr_out_ok[0:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire width 8 $2\cr_rd[7:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire $2\cr_rd_ok[0:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire width 8 $2\cr_wr[7:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire $2\cr_wr_ok[0:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire width 7 $2\ea[6:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire $2\ea_ok[0:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire $2\exc_$signal$3[0:0]$3696 + attribute \src "libresoc.v:78848.3-79005.6" + wire $2\exc_$signal$4[0:0]$3697 + attribute \src "libresoc.v:78848.3-79005.6" + wire $2\exc_$signal$5[0:0]$3698 + attribute \src "libresoc.v:78848.3-79005.6" + wire $2\exc_$signal$6[0:0]$3699 + attribute \src "libresoc.v:78848.3-79005.6" + wire $2\exc_$signal$7[0:0]$3700 + attribute \src "libresoc.v:78848.3-79005.6" + wire $2\exc_$signal$8[0:0]$3701 + attribute \src "libresoc.v:78848.3-79005.6" + wire $2\exc_$signal$9[0:0]$3702 + attribute \src "libresoc.v:78848.3-79005.6" + wire $2\exc_$signal[0:0]$3695 + attribute \src "libresoc.v:78848.3-79005.6" + wire width 3 $2\fast1[2:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire $2\fast1_ok[0:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire width 3 $2\fast2[2:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire $2\fast2_ok[0:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire width 3 $2\fasto1[2:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire $2\fasto1_ok[0:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire width 3 $2\fasto2[2:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire $2\fasto2_ok[0:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire width 13 $2\fn_unit[12:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire width 2 $2\input_carry[1:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire width 32 $2\insn[31:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire width 7 $2\insn_type[6:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire $2\is_32bit[0:0] + attribute \src "libresoc.v:78824.3-78847.6" + wire $2\is_priv_insn[0:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire $2\lk[0:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire width 64 $2\msr[63:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire $2\oe[0:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire $2\oe_ok[0:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire $2\rc[0:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire $2\rc_ok[0:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire width 7 $2\reg1[6:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire $2\reg1_ok[0:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire width 7 $2\reg2[6:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire $2\reg2_ok[0:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire width 7 $2\reg3[6:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire $2\reg3_ok[0:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire width 7 $2\rego[6:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire $2\rego_ok[0:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire width 10 $2\spr1[9:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire $2\spr1_ok[0:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire width 10 $2\spro[9:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire $2\spro_ok[0:0] + attribute \src "libresoc.v:78788.3-78803.6" + wire width 3 $2\tmp_xer_in[2:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire width 13 $2\trapaddr[12:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire width 8 $2\traptype[7:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire width 3 $2\xer_in[2:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire $2\xer_out[0:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire width 8 $3\asmcode[7:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire width 64 $3\cia[63:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire width 7 $3\cr_in1[6:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire $3\cr_in1_ok[0:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire width 7 $3\cr_in2$1[6:0]$3703 + attribute \src "libresoc.v:78848.3-79005.6" + wire width 7 $3\cr_in2[6:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire $3\cr_in2_ok$2[0:0]$3704 + attribute \src "libresoc.v:78848.3-79005.6" + wire $3\cr_in2_ok[0:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire width 7 $3\cr_out[6:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire $3\cr_out_ok[0:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire width 8 $3\cr_rd[7:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire $3\cr_rd_ok[0:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire width 8 $3\cr_wr[7:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire $3\cr_wr_ok[0:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire width 7 $3\ea[6:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire $3\ea_ok[0:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire $3\exc_$signal$3[0:0]$3706 + attribute \src "libresoc.v:78848.3-79005.6" + wire $3\exc_$signal$4[0:0]$3707 + attribute \src "libresoc.v:78848.3-79005.6" + wire $3\exc_$signal$5[0:0]$3708 + attribute \src "libresoc.v:78848.3-79005.6" + wire $3\exc_$signal$6[0:0]$3709 + attribute \src "libresoc.v:78848.3-79005.6" + wire $3\exc_$signal$7[0:0]$3710 + attribute \src "libresoc.v:78848.3-79005.6" + wire $3\exc_$signal$8[0:0]$3711 + attribute \src "libresoc.v:78848.3-79005.6" + wire $3\exc_$signal$9[0:0]$3712 + attribute \src "libresoc.v:78848.3-79005.6" + wire $3\exc_$signal[0:0]$3705 + attribute \src "libresoc.v:78848.3-79005.6" + wire width 3 $3\fast1[2:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire $3\fast1_ok[0:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire width 3 $3\fast2[2:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire $3\fast2_ok[0:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire width 3 $3\fasto1[2:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire $3\fasto1_ok[0:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire width 3 $3\fasto2[2:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire $3\fasto2_ok[0:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire width 13 $3\fn_unit[12:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire width 2 $3\input_carry[1:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire width 32 $3\insn[31:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire width 7 $3\insn_type[6:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire $3\is_32bit[0:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire $3\lk[0:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire width 64 $3\msr[63:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire $3\oe[0:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire $3\oe_ok[0:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire $3\rc[0:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire $3\rc_ok[0:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire width 7 $3\reg1[6:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire $3\reg1_ok[0:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire width 7 $3\reg2[6:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire $3\reg2_ok[0:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire width 7 $3\reg3[6:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire $3\reg3_ok[0:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire width 7 $3\rego[6:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire $3\rego_ok[0:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire width 10 $3\spr1[9:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire $3\spr1_ok[0:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire width 10 $3\spro[9:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire $3\spro_ok[0:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire width 13 $3\trapaddr[12:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire width 8 $3\traptype[7:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire width 3 $3\xer_in[2:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire $3\xer_out[0:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire width 8 $4\asmcode[7:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire width 64 $4\cia[63:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire width 7 $4\cr_in1[6:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire $4\cr_in1_ok[0:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire width 7 $4\cr_in2$1[6:0]$3713 + attribute \src "libresoc.v:78848.3-79005.6" + wire width 7 $4\cr_in2[6:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire $4\cr_in2_ok$2[0:0]$3714 + attribute \src "libresoc.v:78848.3-79005.6" + wire $4\cr_in2_ok[0:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire width 7 $4\cr_out[6:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire $4\cr_out_ok[0:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire width 8 $4\cr_rd[7:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire $4\cr_rd_ok[0:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire width 8 $4\cr_wr[7:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire $4\cr_wr_ok[0:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire width 7 $4\ea[6:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire $4\ea_ok[0:0] + attribute \src "libresoc.v:78848.3-79005.6" + wire $4\exc_$signal$3[0:0]$3716 + attribute \src "libresoc.v:78848.3-79005.6" + wire $4\exc_$signal$4[0:0]$3717 + attribute \src "libresoc.v:78848.3-79005.6" + wire $4\exc_$signal$5[0:0]$3718 + attribute \src "libresoc.v:78848.3-79005.6" + wire $4\exc_$signal$6[0:0]$3719 + attribute \src "libresoc.v:78848.3-79005.6" + wire $4\exc_$signal$7[0:0]$3720 + attribute \src "libresoc.v:78848.3-79005.6" + wire $4\exc_$signal$8[0:0]$3721 + attribute \src "libresoc.v:78848.3-79005.6" + wire $4\exc_$signal$9[0:0]$3722 + attribute \src "libresoc.v:78848.3-79005.6" + wire $4\exc_$signal[0:0]$3715 + attribute \src "libresoc.v:78848.3-79005.6" + wire width 3 $4\fast1[2:0] + attribute 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\enum_value_0010000001 "TFIAR" + attribute \enum_value_0010000010 "TEXASR" + attribute \enum_value_0010000011 "TEXASRU" + attribute \enum_value_0010001000 "CTRL" + attribute \enum_value_0010010000 "TIDR" + attribute \enum_value_0010011000 "CTRL_priv" + attribute \enum_value_0010011001 "FSCR" + attribute \enum_value_0010011101 "UAMOR" + attribute \enum_value_0010011110 "GSR" + attribute \enum_value_0010011111 "PSPB" + attribute \enum_value_0010110000 "DPDES" + attribute \enum_value_0010110100 "DAWR0" + attribute \enum_value_0010111010 "RPR" + attribute \enum_value_0010111011 "CIABR" + attribute \enum_value_0010111100 "DAWRX0" + attribute \enum_value_0010111110 "HFSCR" + attribute \enum_value_0100000000 "VRSAVE" + attribute \enum_value_0100000011 "SPRG3" + attribute \enum_value_0100001100 "TB" + attribute \enum_value_0100001101 "TBU" + attribute \enum_value_0100010000 "SPRG0_priv" + attribute \enum_value_0100010001 "SPRG1_priv" + attribute \enum_value_0100010010 "SPRG2_priv" + attribute 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\enum_value_0110111110 "TIR" + attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1011000000 "SVSTATE" + attribute \enum_value_1011010000 "SVSRR0" + attribute \enum_value_1100000000 "SIER" + attribute \enum_value_1100000001 "MMCR2" + attribute \enum_value_1100000010 "MMCRA" + attribute \enum_value_1100000011 "PMC1" + attribute \enum_value_1100000100 "PMC2" + attribute \enum_value_1100000101 "PMC3" + attribute \enum_value_1100000110 "PMC4" + attribute \enum_value_1100000111 "PMC5" + attribute \enum_value_1100001000 "PMC6" + attribute \enum_value_1100001011 "MMCR0" + attribute \enum_value_1100001100 "SIAR" + attribute \enum_value_1100001101 "SDAR" + attribute \enum_value_1100001110 "MMCR1" + attribute \enum_value_1100010000 "SIER_priv" + attribute \enum_value_1100010001 "MMCR2_priv" + attribute \enum_value_1100010010 "MMCRA_priv" + attribute \enum_value_1100010011 "PMC1_priv" + attribute \enum_value_1100010100 "PMC2_priv" + attribute \enum_value_1100010101 "PMC3_priv" + attribute \enum_value_1100010110 "PMC4_priv" + attribute \enum_value_1100010111 "PMC5_priv" + attribute \enum_value_1100011000 "PMC6_priv" + attribute \enum_value_1100011011 "MMCR0_priv" + attribute \enum_value_1100011100 "SIAR_priv" + attribute \enum_value_1100011101 "SDAR_priv" + attribute \enum_value_1100011110 "MMCR1_priv" + attribute \enum_value_1100100000 "BESCRS" + attribute \enum_value_1100100001 "BESCRSU" + attribute \enum_value_1100100010 "BESCRR" + attribute \enum_value_1100100011 "BESCRRU" + attribute \enum_value_1100100100 "EBBHR" + attribute \enum_value_1100100101 "EBBRR" + attribute \enum_value_1100100110 "BESCR" + attribute \enum_value_1100101000 "reserved808" + attribute \enum_value_1100101001 "reserved809" + attribute \enum_value_1100101010 "reserved810" + attribute \enum_value_1100101011 "reserved811" + attribute \enum_value_1100101111 "TAR" + attribute \enum_value_1100110000 "ASDR" + attribute \enum_value_1100110111 "PSSCR" + attribute \enum_value_1101010000 "IC" + attribute \enum_value_1101010001 "VTB" + attribute \enum_value_1101010111 "PSSCR_hypv" + attribute \enum_value_1110000000 "PPR" + attribute \enum_value_1110000010 "PPR32" + attribute \enum_value_1111111111 "PIR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 10 \dec_o_spr_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_o_spr_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_oe_oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_oe_oe_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:607" + wire width 2 \dec_oe_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + wire width 32 \dec_opcode_in + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \dec_out_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_rc_rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_rc_rc_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \dec_rc_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:570" + wire width 2 \dec_rc_sel_in + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec_sv_cr_in + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec_sv_cr_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec_sv_in1 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec_sv_in2 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec_sv_in3 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec_sv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svp64.py:31" + wire width 9 input 5 \dec_svp64__extra + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \dec_upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 7 output 10 \ea + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 11 \ea_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire output 52 \exc_$signal + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire output 53 \exc_$signal$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire output 54 \exc_$signal$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire output 55 \exc_$signal$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire output 56 \exc_$signal$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire output 57 \exc_$signal$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire output 58 \exc_$signal$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire output 59 \exc_$signal$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1202" + wire \ext_irq_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 output 24 \fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 25 \fast1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 output 26 \fast2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 27 \fast2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 output 28 \fasto1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 29 \fasto1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 output 30 \fasto2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 31 \fasto2_ok + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48" + wire width 13 output 44 \fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1205" + wire \illeg_ok + attribute \enum_base_type "SVEtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "EXTRA2" + attribute \enum_value_10 "EXTRA3" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:90" + wire width 2 \in1_svdec_etype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:89" + wire width 9 \in1_svdec_extra + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:91" + wire width 3 \in1_svdec_idx + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:149" + wire \in1_svdec_isvec + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:147" + wire width 5 \in1_svdec_reg_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:148" + wire width 7 \in1_svdec_reg_out + attribute \enum_base_type "SVEtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "EXTRA2" + attribute \enum_value_10 "EXTRA3" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:90" + wire width 2 \in2_svdec_etype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:89" + wire width 9 \in2_svdec_extra + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:91" + wire width 3 \in2_svdec_idx + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:149" + wire \in2_svdec_isvec + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:147" + wire width 5 \in2_svdec_reg_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:148" + wire width 7 \in2_svdec_reg_out + attribute \enum_base_type "SVEtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "EXTRA2" + attribute \enum_value_10 "EXTRA3" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:90" + wire width 2 \in3_svdec_etype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:89" + wire width 9 \in3_svdec_extra + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:91" + wire width 3 \in3_svdec_idx + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:149" + wire \in3_svdec_isvec + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:147" + wire width 5 \in3_svdec_reg_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:148" + wire width 7 \in3_svdec_reg_out + attribute \src "libresoc.v:76570.7-76570.15" + wire \initial + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:52" + wire width 2 output 50 \input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:46" + wire width 32 output 42 \insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:571" + wire width 32 \insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:608" + wire width 32 \insn_in$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:229" + wire width 32 \insn_in$59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:323" + wire width 32 \insn_in$60 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:429" + wire width 32 \insn_in$61 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:460" + wire width 32 \insn_in$62 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:525" + wire width 32 \insn_in$63 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47" + wire width 7 output 43 \insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:58" + wire output 65 \is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:46" + wire \is_priv_insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:49" + wire output 45 \lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:42" + wire width 64 output 40 \msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1011" + wire \no_out_vec + attribute \enum_base_type "SVEtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "EXTRA2" + attribute \enum_value_10 "EXTRA3" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:90" + wire width 2 \o2_svdec_etype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:89" + wire width 9 \o2_svdec_extra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:149" + wire \o2_svdec_isvec + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:147" + wire width 5 \o2_svdec_reg_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:148" + wire width 7 \o2_svdec_reg_out + attribute \enum_base_type "SVEtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "EXTRA2" + attribute \enum_value_10 "EXTRA3" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:90" + wire width 2 \o_svdec_etype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:89" + wire width 9 \o_svdec_extra + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:91" + wire width 3 \o_svdec_idx + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:149" + wire \o_svdec_isvec + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:147" + wire width 5 \o_svdec_reg_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:148" + wire width 7 \o_svdec_reg_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 48 \oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 49 \oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1204" + wire \priv_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 32 input 6 \raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 46 \rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 47 \rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 7 output 12 \reg1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 13 \reg1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 7 output 14 \reg2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 15 \reg2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 7 output 16 \reg3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 17 \reg3_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1006" + wire \reg_a_isvec + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1007" + wire \reg_b_isvec + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1008" + wire \reg_c_isvec + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1010" + wire \reg_o2_isvec + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1009" + wire \reg_o_isvec + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 7 output 8 \rego + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 9 \rego_ok + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:523" + wire width 2 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:910" + wire width 10 \spr + attribute \enum_base_type "SPR" + attribute \enum_value_0000000001 "XER" + attribute \enum_value_0000000011 "DSCR" + attribute \enum_value_0000001000 "LR" + attribute \enum_value_0000001001 "CTR" + attribute \enum_value_0000001101 "AMR" + attribute \enum_value_0000010001 "DSCR_priv" + attribute \enum_value_0000010010 "DSISR" + attribute \enum_value_0000010011 "DAR" + attribute \enum_value_0000010110 "DEC" + attribute \enum_value_0000011010 "SRR0" + attribute \enum_value_0000011011 "SRR1" + attribute \enum_value_0000011100 "CFAR" + attribute \enum_value_0000011101 "AMR_priv" + attribute \enum_value_0000110000 "PIDR" + attribute \enum_value_0000111101 "IAMR" + attribute \enum_value_0010000000 "TFHAR" + attribute \enum_value_0010000001 "TFIAR" + attribute \enum_value_0010000010 "TEXASR" + attribute \enum_value_0010000011 "TEXASRU" + attribute \enum_value_0010001000 "CTRL" + attribute \enum_value_0010010000 "TIDR" + attribute \enum_value_0010011000 "CTRL_priv" + attribute \enum_value_0010011001 "FSCR" + attribute \enum_value_0010011101 "UAMOR" + attribute \enum_value_0010011110 "GSR" + attribute \enum_value_0010011111 "PSPB" + attribute \enum_value_0010110000 "DPDES" + attribute \enum_value_0010110100 "DAWR0" + attribute \enum_value_0010111010 "RPR" + attribute \enum_value_0010111011 "CIABR" + attribute \enum_value_0010111100 "DAWRX0" + attribute \enum_value_0010111110 "HFSCR" + attribute \enum_value_0100000000 "VRSAVE" + attribute \enum_value_0100000011 "SPRG3" + attribute \enum_value_0100001100 "TB" + attribute \enum_value_0100001101 "TBU" + attribute \enum_value_0100010000 "SPRG0_priv" + attribute \enum_value_0100010001 "SPRG1_priv" + attribute \enum_value_0100010010 "SPRG2_priv" + attribute \enum_value_0100010011 "SPRG3_priv" + attribute \enum_value_0100011011 "CIR" + attribute \enum_value_0100011100 "TBL" + attribute \enum_value_0100011101 "TBU_hypv" + attribute \enum_value_0100011110 "TBU40" + attribute \enum_value_0100011111 "PVR" + attribute \enum_value_0100110000 "HSPRG0" + attribute \enum_value_0100110001 "HSPRG1" + attribute \enum_value_0100110010 "HDSISR" + attribute \enum_value_0100110011 "HDAR" + attribute \enum_value_0100110100 "SPURR" + attribute \enum_value_0100110101 "PURR" + attribute \enum_value_0100110110 "HDEC" + attribute \enum_value_0100111001 "HRMOR" + attribute \enum_value_0100111010 "HSRR0" + attribute \enum_value_0100111011 "HSRR1" + attribute \enum_value_0100111110 "LPCR" + attribute \enum_value_0100111111 "LPIDR" + attribute \enum_value_0101010000 "HMER" + attribute \enum_value_0101010001 "HMEER" + attribute \enum_value_0101010010 "PCR" + attribute \enum_value_0101010011 "HEIR" + attribute \enum_value_0101011101 "AMOR" + attribute \enum_value_0110111110 "TIR" + attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1011000000 "SVSTATE" + attribute \enum_value_1011010000 "SVSRR0" + attribute \enum_value_1100000000 "SIER" + attribute \enum_value_1100000001 "MMCR2" + attribute \enum_value_1100000010 "MMCRA" + attribute \enum_value_1100000011 "PMC1" + attribute \enum_value_1100000100 "PMC2" + attribute \enum_value_1100000101 "PMC3" + attribute \enum_value_1100000110 "PMC4" + attribute \enum_value_1100000111 "PMC5" + attribute \enum_value_1100001000 "PMC6" + attribute \enum_value_1100001011 "MMCR0" + attribute \enum_value_1100001100 "SIAR" + attribute \enum_value_1100001101 "SDAR" + attribute \enum_value_1100001110 "MMCR1" + attribute \enum_value_1100010000 "SIER_priv" + attribute \enum_value_1100010001 "MMCR2_priv" + attribute \enum_value_1100010010 "MMCRA_priv" + attribute \enum_value_1100010011 "PMC1_priv" + attribute \enum_value_1100010100 "PMC2_priv" + attribute \enum_value_1100010101 "PMC3_priv" + attribute \enum_value_1100010110 "PMC4_priv" + attribute \enum_value_1100010111 "PMC5_priv" + attribute \enum_value_1100011000 "PMC6_priv" + attribute \enum_value_1100011011 "MMCR0_priv" + attribute \enum_value_1100011100 "SIAR_priv" + attribute \enum_value_1100011101 "SDAR_priv" + attribute \enum_value_1100011110 "MMCR1_priv" + attribute \enum_value_1100100000 "BESCRS" + attribute \enum_value_1100100001 "BESCRSU" + attribute \enum_value_1100100010 "BESCRR" + attribute \enum_value_1100100011 "BESCRRU" + attribute \enum_value_1100100100 "EBBHR" + attribute \enum_value_1100100101 "EBBRR" + attribute \enum_value_1100100110 "BESCR" + attribute \enum_value_1100101000 "reserved808" + attribute \enum_value_1100101001 "reserved809" + attribute \enum_value_1100101010 "reserved810" + attribute \enum_value_1100101011 "reserved811" + attribute \enum_value_1100101111 "TAR" + attribute \enum_value_1100110000 "ASDR" + attribute \enum_value_1100110111 "PSSCR" + attribute \enum_value_1101010000 "IC" + attribute \enum_value_1101010001 "VTB" + attribute \enum_value_1101010111 "PSSCR_hypv" + attribute \enum_value_1110000000 "PPR" + attribute \enum_value_1110000010 "PPR32" + attribute \enum_value_1111111111 "PIR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 10 output 20 \spr1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 21 \spr1_ok + attribute \enum_base_type "SPR" + attribute \enum_value_0000000001 "XER" + attribute \enum_value_0000000011 "DSCR" + attribute \enum_value_0000001000 "LR" + attribute \enum_value_0000001001 "CTR" + attribute \enum_value_0000001101 "AMR" + attribute \enum_value_0000010001 "DSCR_priv" + attribute \enum_value_0000010010 "DSISR" + attribute \enum_value_0000010011 "DAR" + attribute \enum_value_0000010110 "DEC" + attribute \enum_value_0000011010 "SRR0" + attribute \enum_value_0000011011 "SRR1" + attribute \enum_value_0000011100 "CFAR" + attribute \enum_value_0000011101 "AMR_priv" + attribute \enum_value_0000110000 "PIDR" + attribute \enum_value_0000111101 "IAMR" + attribute \enum_value_0010000000 "TFHAR" + attribute \enum_value_0010000001 "TFIAR" + attribute \enum_value_0010000010 "TEXASR" + attribute \enum_value_0010000011 "TEXASRU" + attribute \enum_value_0010001000 "CTRL" + attribute \enum_value_0010010000 "TIDR" + attribute \enum_value_0010011000 "CTRL_priv" + attribute \enum_value_0010011001 "FSCR" + attribute \enum_value_0010011101 "UAMOR" + attribute \enum_value_0010011110 "GSR" + attribute \enum_value_0010011111 "PSPB" + attribute \enum_value_0010110000 "DPDES" + attribute \enum_value_0010110100 "DAWR0" + attribute \enum_value_0010111010 "RPR" + attribute \enum_value_0010111011 "CIABR" + attribute \enum_value_0010111100 "DAWRX0" + attribute \enum_value_0010111110 "HFSCR" + attribute \enum_value_0100000000 "VRSAVE" + attribute \enum_value_0100000011 "SPRG3" + attribute \enum_value_0100001100 "TB" + attribute \enum_value_0100001101 "TBU" + attribute \enum_value_0100010000 "SPRG0_priv" + attribute \enum_value_0100010001 "SPRG1_priv" + attribute \enum_value_0100010010 "SPRG2_priv" + attribute \enum_value_0100010011 "SPRG3_priv" + attribute \enum_value_0100011011 "CIR" + attribute \enum_value_0100011100 "TBL" + attribute \enum_value_0100011101 "TBU_hypv" + attribute \enum_value_0100011110 "TBU40" + attribute \enum_value_0100011111 "PVR" + attribute \enum_value_0100110000 "HSPRG0" + attribute \enum_value_0100110001 "HSPRG1" + attribute \enum_value_0100110010 "HDSISR" + attribute \enum_value_0100110011 "HDAR" + attribute \enum_value_0100110100 "SPURR" + attribute \enum_value_0100110101 "PURR" + attribute \enum_value_0100110110 "HDEC" + attribute \enum_value_0100111001 "HRMOR" + attribute \enum_value_0100111010 "HSRR0" + attribute \enum_value_0100111011 "HSRR1" + attribute \enum_value_0100111110 "LPCR" + attribute \enum_value_0100111111 "LPIDR" + attribute \enum_value_0101010000 "HMER" + attribute \enum_value_0101010001 "HMEER" + attribute \enum_value_0101010010 "PCR" + attribute \enum_value_0101010011 "HEIR" + attribute \enum_value_0101011101 "AMOR" + attribute \enum_value_0110111110 "TIR" + attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1011000000 "SVSTATE" + attribute \enum_value_1011010000 "SVSRR0" + attribute \enum_value_1100000000 "SIER" + attribute \enum_value_1100000001 "MMCR2" + attribute \enum_value_1100000010 "MMCRA" + attribute \enum_value_1100000011 "PMC1" + attribute \enum_value_1100000100 "PMC2" + attribute \enum_value_1100000101 "PMC3" + attribute \enum_value_1100000110 "PMC4" + attribute \enum_value_1100000111 "PMC5" + attribute \enum_value_1100001000 "PMC6" + attribute \enum_value_1100001011 "MMCR0" + attribute \enum_value_1100001100 "SIAR" + attribute \enum_value_1100001101 "SDAR" + attribute \enum_value_1100001110 "MMCR1" + attribute \enum_value_1100010000 "SIER_priv" + attribute \enum_value_1100010001 "MMCR2_priv" + attribute \enum_value_1100010010 "MMCRA_priv" + attribute \enum_value_1100010011 "PMC1_priv" + attribute \enum_value_1100010100 "PMC2_priv" + attribute \enum_value_1100010101 "PMC3_priv" + attribute \enum_value_1100010110 "PMC4_priv" + attribute \enum_value_1100010111 "PMC5_priv" + attribute \enum_value_1100011000 "PMC6_priv" + attribute \enum_value_1100011011 "MMCR0_priv" + attribute \enum_value_1100011100 "SIAR_priv" + attribute \enum_value_1100011101 "SDAR_priv" + attribute \enum_value_1100011110 "MMCR1_priv" + attribute \enum_value_1100100000 "BESCRS" + attribute \enum_value_1100100001 "BESCRSU" + attribute \enum_value_1100100010 "BESCRR" + attribute \enum_value_1100100011 "BESCRRU" + attribute \enum_value_1100100100 "EBBHR" + attribute \enum_value_1100100101 "EBBRR" + attribute \enum_value_1100100110 "BESCR" + attribute \enum_value_1100101000 "reserved808" + attribute \enum_value_1100101001 "reserved809" + attribute \enum_value_1100101010 "reserved810" + attribute \enum_value_1100101011 "reserved811" + attribute \enum_value_1100101111 "TAR" + attribute \enum_value_1100110000 "ASDR" + attribute \enum_value_1100110111 "PSSCR" + attribute \enum_value_1101010000 "IC" + attribute \enum_value_1101010001 "VTB" + attribute \enum_value_1101010111 "PSSCR_hypv" + attribute \enum_value_1110000000 "PPR" + attribute \enum_value_1110000010 "PPR32" + attribute \enum_value_1111111111 "PIR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 10 output 18 \spro + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 19 \spro_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1113" + wire width 7 \srcstep + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:94" + wire width 8 \tmp_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 7 \tmp_cr_in1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \tmp_cr_in1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 7 \tmp_cr_in2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 7 \tmp_cr_in2$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \tmp_cr_in2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \tmp_cr_in2_ok$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 7 \tmp_cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \tmp_cr_out_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 7 \tmp_ea + attribute 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 7 \tmp_reg1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \tmp_reg1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 7 \tmp_reg2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \tmp_reg2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 7 \tmp_reg3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \tmp_reg3_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 7 \tmp_rego + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \tmp_rego_ok + attribute \enum_base_type "SPR" + attribute \enum_value_0000000001 "XER" + attribute \enum_value_0000000011 "DSCR" + attribute \enum_value_0000001000 "LR" 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\B_WIDTH 7 + parameter \Y_WIDTH 8 + connect \A \srcstep + connect \B \in1_svdec_reg_out + connect \Y $add$libresoc.v:78556$3655_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1130" + cell $add $add$libresoc.v:78557$3656 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 8 + connect \A \srcstep + connect \B \in2_svdec_reg_out + connect \Y $add$libresoc.v:78557$3656_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1130" + cell $add $add$libresoc.v:78558$3657 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 8 + connect \A \srcstep + connect \B \in3_svdec_reg_out + connect \Y $add$libresoc.v:78558$3657_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1130" + cell $add $add$libresoc.v:78559$3658 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 8 + connect \A \srcstep + connect \B \o_svdec_reg_out + connect \Y $add$libresoc.v:78559$3658_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1130" + cell $add $add$libresoc.v:78560$3659 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 8 + connect \A \srcstep + connect \B \o2_svdec_reg_out + connect \Y $add$libresoc.v:78560$3659_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1209" + cell $and $and$libresoc.v:78536$3635 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cur_dec [63] + connect \B \cur_msr [15] + connect \Y $and$libresoc.v:78536$3635_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1210" + cell $and $and$libresoc.v:78537$3636 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_priv_insn + connect \B \cur_msr [14] + connect \Y $and$libresoc.v:78537$3636_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + cell $and $and$libresoc.v:78553$3652 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$41 + connect \B \$55 + connect \Y $and$libresoc.v:78553$3652_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1150" + cell $and $and$libresoc.v:78563$3662 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$83 + connect \B \$85 + connect \Y $and$libresoc.v:78563$3662_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1208" + cell $and $and$libresoc.v:78568$3667 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cur_eint + connect \B \cur_msr [15] + connect \Y $and$libresoc.v:78568$3667_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1211" + cell $eq $eq$libresoc.v:78538$3637 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \dec_internal_op + connect \B 7'0000000 + connect \Y $eq$libresoc.v:78538$3637_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1259" + cell $eq $eq$libresoc.v:78539$3638 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \insn_type + connect \B 7'0111111 + connect \Y $eq$libresoc.v:78539$3638_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1260" + cell $eq $eq$libresoc.v:78540$3639 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \insn_type + connect \B 7'1001001 + connect \Y $eq$libresoc.v:78540$3639_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1269" + cell $eq $eq$libresoc.v:78542$3641 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \insn_type + connect \B 7'1000110 + connect \Y $eq$libresoc.v:78542$3641_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:917" + cell $eq $eq$libresoc.v:78543$3642 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \dec_internal_op + connect \B 7'0110001 + connect \Y $eq$libresoc.v:78543$3642_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:918" + cell $eq $eq$libresoc.v:78544$3643 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \dec_internal_op + connect \B 7'0101110 + connect \Y $eq$libresoc.v:78544$3643_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + cell $eq $eq$libresoc.v:78546$3645 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 10 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 10'0000010010 + connect \Y $eq$libresoc.v:78546$3645_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + cell $eq $eq$libresoc.v:78547$3646 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 10 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 10'0000010011 + connect \Y $eq$libresoc.v:78547$3646_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + cell $eq $eq$libresoc.v:78549$3648 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 10 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 10'1011010000 + connect \Y $eq$libresoc.v:78549$3648_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + cell $eq $eq$libresoc.v:78551$3650 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 6'110000 + connect \Y $eq$libresoc.v:78551$3650_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1090" + cell $eq $eq$libresoc.v:78554$3653 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \dec_sv_cr_in + connect \B 3'101 + connect \Y $eq$libresoc.v:78554$3653_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1090" + cell $eq $eq$libresoc.v:78555$3654 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \dec_sv_cr_in + connect \B 3'101 + connect \Y $eq$libresoc.v:78555$3654_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1177" + cell $eq $eq$libresoc.v:78564$3663 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \dec_internal_op + connect \B 7'0101110 + connect \Y $eq$libresoc.v:78564$3663_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1179" + cell $eq $eq$libresoc.v:78565$3664 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \dec_internal_op + connect \B 7'0001010 + connect \Y $eq$libresoc.v:78565$3664_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1181" + cell $eq $eq$libresoc.v:78566$3665 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \dec_internal_op + connect \B 7'0110001 + connect \Y $eq$libresoc.v:78566$3665_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1185" + cell $eq $eq$libresoc.v:78567$3666 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \dec_internal_op + connect \B 7'0111111 + connect \Y $eq$libresoc.v:78567$3666_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1150" + cell $not $not$libresoc.v:78561$3660 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \o2_svdec_isvec + connect \Y $not$libresoc.v:78561$3660_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1150" + cell $not $not$libresoc.v:78562$3661 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \o_svdec_isvec + connect \Y $not$libresoc.v:78562$3661_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1260" + cell $or $or$libresoc.v:78541$3640 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$28 + connect \B \$30 + connect \Y $or$libresoc.v:78541$3640_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:918" + cell $or $or$libresoc.v:78545$3644 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$37 + connect \B \$39 + connect \Y $or$libresoc.v:78545$3644_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + cell $or $or$libresoc.v:78548$3647 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$43 + connect \B \$45 + connect \Y $or$libresoc.v:78548$3647_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + cell $or $or$libresoc.v:78550$3649 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$47 + connect \B \$49 + connect \Y $or$libresoc.v:78550$3649_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + cell $or $or$libresoc.v:78552$3651 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$51 + connect \B \$53 + connect \Y $or$libresoc.v:78552$3651_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:78569.14-78576.4" + cell \crin_svdec \crin_svdec + connect \cr_in \crin_svdec_cr_in + connect \cr_out \crin_svdec_cr_out + connect \etype \crin_svdec_etype + connect \extra \crin_svdec_extra + connect \idx \crin_svdec_idx + connect \isvec \crin_svdec_isvec + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:78577.16-78584.4" + cell \crin_svdec_b \crin_svdec_b + connect \cr_in \crin_svdec_b_cr_in + connect \cr_out \crin_svdec_b_cr_out + connect \etype \crin_svdec_b_etype + connect \extra \crin_svdec_b_extra + connect \idx \crin_svdec_b_idx + connect \isvec \crin_svdec_b_isvec + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:78585.16-78592.4" + cell \crin_svdec_o \crin_svdec_o + connect \cr_in \crin_svdec_o_cr_in + connect \cr_out \crin_svdec_o_cr_out + connect \etype \crin_svdec_o_etype + connect \extra \crin_svdec_o_extra + connect \idx \crin_svdec_o_idx + connect \isvec \crin_svdec_o_isvec + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:78593.15-78600.4" + cell \crout_svdec \crout_svdec + connect \cr_in \crout_svdec_cr_in + connect \cr_out \crout_svdec_cr_out + connect \etype \crout_svdec_etype + connect \extra \crout_svdec_extra + connect \idx \crout_svdec_idx + connect \isvec \crout_svdec_isvec + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:78601.13-78645.4" + cell \dec$204 \dec + connect \BA \dec_BA + connect \BB \dec_BB + connect \BC \dec_BC + connect \BI \dec_BI + connect \BO \dec_BO + connect \BT \dec_BT + connect \FXM \dec_FXM + connect \LK \dec_LK + connect \OE \dec_OE + connect \RA \dec_RA + connect \RB \dec_RB + connect \RS \dec_RS + connect \RT \dec_RT + connect \Rc \dec_Rc + connect \SPR \dec_SPR + connect \SV_Etype \dec_SV_Etype + connect \XL_BT \dec_XL_BT + connect \XL_XO \dec_XL_XO + connect \X_BF \dec_X_BF + connect \X_BFA \dec_X_BFA + connect \asmcode \dec_asmcode + connect \bigendian \bigendian + connect \cr_in \dec_cr_in + connect \cr_out \dec_cr_out + connect \cry_in \dec_cry_in + connect \function_unit \dec_function_unit + connect \in1_sel \dec_in1_sel + connect \in2_sel \dec_in2_sel + connect \in3_sel \dec_in3_sel + connect \internal_op \dec_internal_op + connect \is_32b \dec_is_32b + connect \lk \dec_lk + connect \opcode_in \dec_opcode_in + connect \out_sel \dec_out_sel + connect \raw_opcode_in \raw_opcode_in + connect \rc_sel \dec_rc_sel + connect \sv_cr_in \dec_sv_cr_in + connect \sv_cr_out \dec_sv_cr_out + connect \sv_in1 \dec_sv_in1 + connect \sv_in2 \dec_sv_in2 + connect \sv_in3 \dec_sv_in3 + connect \sv_out \dec_sv_out + connect \upd \dec_upd + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:78646.9-78660.4" + cell \dec_a \dec_a + connect \BO \dec_BO + connect \RA \dec_RA + connect \RS \dec_RS + connect \SPR \dec_SPR + connect \XL_XO \dec_XL_XO + connect \fast_a \dec_a_fast_a + connect \fast_a_ok \dec_a_fast_a_ok + connect \internal_op \dec_internal_op + connect \reg_a \dec_a_reg_a + connect \reg_a_ok \dec_a_reg_a_ok + connect \sel_in \dec_a_sel_in + connect \spr_a \dec_a_spr_a + connect \spr_a_ok \dec_a_spr_a_ok + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:78661.9-78671.4" + cell \dec_b \dec_b + connect \RB \dec_RB + connect \RS \dec_RS + connect \XL_XO \dec_XL_XO + connect \fast_b \dec_b_fast_b + connect \fast_b_ok \dec_b_fast_b_ok + connect \internal_op \dec_internal_op + connect \reg_b \dec_b_reg_b + connect \reg_b_ok \dec_b_reg_b_ok + connect \sel_in \dec_b_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:78672.9-78678.4" + cell \dec_c \dec_c + connect \RB \dec_RB + connect \RS \dec_RS + connect \reg_c \dec_c_reg_c + connect \reg_c_ok \dec_c_reg_c_ok + connect \sel_in \dec_c_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:78679.19-78698.4" + cell \dec_cr_in$207 \dec_cr_in$10 + connect \BA \dec_BA + connect \BB \dec_BB + connect \BC \dec_BC + connect \BI \dec_BI + connect \BT \dec_BT + connect \FXM \dec_FXM + connect \X_BFA \dec_X_BFA + connect \cr_bitfield \dec_cr_in_cr_bitfield + connect \cr_bitfield_b \dec_cr_in_cr_bitfield_b + connect \cr_bitfield_b_ok \dec_cr_in_cr_bitfield_b_ok + connect \cr_bitfield_o \dec_cr_in_cr_bitfield_o + connect \cr_bitfield_o_ok \dec_cr_in_cr_bitfield_o_ok + connect \cr_bitfield_ok \dec_cr_in_cr_bitfield_ok + connect \cr_fxm \dec_cr_in_cr_fxm + connect \cr_fxm_ok \dec_cr_in_cr_fxm_ok + connect \insn_in \dec_cr_in_insn_in + connect \internal_op \dec_internal_op + connect \sel_in \dec_cr_in_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:78699.20-78711.4" + cell \dec_cr_out$209 \dec_cr_out$11 + connect \FXM \dec_FXM + connect \XL_BT \dec_XL_BT + connect \X_BF \dec_X_BF + connect \cr_bitfield \dec_cr_out_cr_bitfield + connect \cr_bitfield_ok \dec_cr_out_cr_bitfield_ok + connect \cr_fxm \dec_cr_out_cr_fxm + connect \cr_fxm_ok \dec_cr_out_cr_fxm_ok + connect \insn_in \dec_cr_out_insn_in + connect \internal_op \dec_internal_op + connect \rc_in \dec_cr_out_rc_in + connect \sel_in \dec_cr_out_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:78712.9-78725.4" + cell \dec_o \dec_o + connect \BO \dec_BO + connect \RA \dec_RA + connect \RT \dec_RT + connect \SPR \dec_SPR + connect \fast_o \dec_o_fast_o + connect \fast_o_ok \dec_o_fast_o_ok + connect \internal_op \dec_internal_op + connect \reg_o \dec_o_reg_o + connect \reg_o_ok \dec_o_reg_o_ok + connect \sel_in \dec_o_sel_in + connect \spr_o \dec_o_spr_o + connect \spr_o_ok \dec_o_spr_o_ok + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:78726.10-78735.4" + cell \dec_o2 \dec_o2 + connect \RA \dec_RA + connect \fast_o2 \dec_o2_fast_o2 + connect \fast_o2_ok \dec_o2_fast_o2_ok + connect \internal_op \dec_internal_op + connect \lk \dec_o2_lk + connect \reg_o2 \dec_o2_reg_o2 + connect \reg_o2_ok \dec_o2_reg_o2_ok + connect \upd \dec_upd + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:78736.16-78742.4" + cell \dec_oe$206 \dec_oe + connect \OE \dec_OE + connect \internal_op \dec_internal_op + connect \oe \dec_oe_oe + connect \oe_ok \dec_oe_oe_ok + connect \sel_in \dec_oe_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:78743.16-78748.4" + cell \dec_rc$205 \dec_rc + connect \Rc \dec_Rc + connect \rc \dec_rc_rc + connect \rc_ok \dec_rc_rc_ok + connect \sel_in \dec_rc_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:78749.13-78756.4" + cell \in1_svdec \in1_svdec + connect \etype \in1_svdec_etype + connect \extra \in1_svdec_extra + connect \idx \in1_svdec_idx + connect \isvec \in1_svdec_isvec + connect \reg_in \in1_svdec_reg_in + connect \reg_out \in1_svdec_reg_out + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:78757.13-78764.4" + cell \in2_svdec \in2_svdec + connect \etype \in2_svdec_etype + connect \extra \in2_svdec_extra + connect \idx \in2_svdec_idx + connect \isvec \in2_svdec_isvec + connect \reg_in \in2_svdec_reg_in + connect \reg_out \in2_svdec_reg_out + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:78765.13-78772.4" + cell \in3_svdec \in3_svdec + connect \etype \in3_svdec_etype + connect \extra \in3_svdec_extra + connect \idx \in3_svdec_idx + connect \isvec \in3_svdec_isvec + connect \reg_in \in3_svdec_reg_in + connect \reg_out \in3_svdec_reg_out + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:78773.12-78779.4" + cell \o2_svdec \o2_svdec + connect \etype \o2_svdec_etype + connect \extra \o2_svdec_extra + connect \isvec \o2_svdec_isvec + connect \reg_in \o2_svdec_reg_in + connect \reg_out \o2_svdec_reg_out + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:78780.11-78787.4" + cell \o_svdec \o_svdec + connect \etype \o_svdec_etype + connect \extra \o_svdec_extra + connect \idx \o_svdec_idx + connect \isvec \o_svdec_isvec + connect \reg_in \o_svdec_reg_in + connect \reg_out \o_svdec_reg_out + end + attribute \src "libresoc.v:76570.7-76570.20" + process $proc$libresoc.v:76570$3732 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:78788.3-78803.6" + process $proc$libresoc.v:78788$3668 + assign { } { } + assign { } { } + assign { } { } + assign $0\tmp_xer_in[2:0] $2\tmp_xer_in[2:0] + attribute \src "libresoc.v:78789.5-78789.29" + switch \initial + attribute \src "libresoc.v:78789.9-78789.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1177" + switch \$89 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\tmp_xer_in[2:0] 3'111 + case + assign $1\tmp_xer_in[2:0] 3'000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1179" + switch \$91 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\tmp_xer_in[2:0] 3'001 + case + assign $2\tmp_xer_in[2:0] $1\tmp_xer_in[2:0] + end + sync always + update \tmp_xer_in $0\tmp_xer_in[2:0] + end + attribute \src "libresoc.v:78804.3-78813.6" + process $proc$libresoc.v:78804$3669 + assign { } { } + assign { } { } + assign $0\tmp_xer_out[0:0] $1\tmp_xer_out[0:0] + attribute \src "libresoc.v:78805.5-78805.29" + switch \initial + attribute \src "libresoc.v:78805.9-78805.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1181" + switch \$93 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\tmp_xer_out[0:0] 1'1 + case + assign $1\tmp_xer_out[0:0] 1'0 + end + sync always + update \tmp_xer_out $0\tmp_xer_out[0:0] + end + attribute \src "libresoc.v:78814.3-78823.6" + process $proc$libresoc.v:78814$3670 + assign { } { } + assign { } { } + assign $0\tmp_tmp_trapaddr[12:0] $1\tmp_tmp_trapaddr[12:0] + attribute \src "libresoc.v:78815.5-78815.29" + switch \initial + attribute \src "libresoc.v:78815.9-78815.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1185" + switch \$95 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\tmp_tmp_trapaddr[12:0] 13'0000001110000 + case + assign $1\tmp_tmp_trapaddr[12:0] 13'0000000000000 + end + sync always + update \tmp_tmp_trapaddr $0\tmp_tmp_trapaddr[12:0] + end + attribute \src "libresoc.v:78824.3-78847.6" + process $proc$libresoc.v:78824$3671 + assign { } { } + assign { } { } + assign $0\is_priv_insn[0:0] $1\is_priv_insn[0:0] + attribute \src "libresoc.v:78825.5-78825.29" + switch \initial + attribute \src "libresoc.v:78825.9-78825.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:47" + switch \dec_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 , 7'1000111 , 7'1001000 , 7'1001010 , 7'1000110 + assign { } { } + assign $1\is_priv_insn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 7'1001011 + assign { } { } + assign $1\is_priv_insn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 7'0101110 , 7'0110001 + assign { } { } + assign $1\is_priv_insn[0:0] $2\is_priv_insn[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:53" + switch \tmp_tmp_insn [20] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\is_priv_insn[0:0] 1'1 + case + assign $2\is_priv_insn[0:0] 1'0 + end + case + assign $1\is_priv_insn[0:0] 1'0 + end + sync always + update \is_priv_insn $0\is_priv_insn[0:0] + end + attribute \src "libresoc.v:78848.3-79005.6" + process $proc$libresoc.v:78848$3672 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\rc[0:0] $1\rc[0:0] + assign $0\spr1[9:0] $1\spr1[9:0] + assign $0\spr1_ok[0:0] $1\spr1_ok[0:0] + assign $0\msr[63:0] $1\msr[63:0] + assign $0\ea_ok[0:0] $1\ea_ok[0:0] + assign $0\ea[6:0] $1\ea[6:0] + assign $0\cr_out[6:0] $1\cr_out[6:0] + assign { } { } + assign $0\lk[0:0] $1\lk[0:0] + assign $0\cia[63:0] $1\cia[63:0] + assign $0\cr_in1[6:0] $1\cr_in1[6:0] + assign $0\cr_in1_ok[0:0] $1\cr_in1_ok[0:0] + assign $0\cr_in2[6:0] $1\cr_in2[6:0] + assign $0\cr_in2$1[6:0]$3673 $1\cr_in2$1[6:0]$3683 + assign $0\cr_in2_ok[0:0] $1\cr_in2_ok[0:0] + assign $0\cr_in2_ok$2[0:0]$3674 $1\cr_in2_ok$2[0:0]$3684 + assign $0\cr_out_ok[0:0] $1\cr_out_ok[0:0] + assign $0\cr_rd[7:0] $1\cr_rd[7:0] + assign $0\cr_rd_ok[0:0] $1\cr_rd_ok[0:0] + assign $0\cr_wr[7:0] $1\cr_wr[7:0] + assign $0\cr_wr_ok[0:0] $1\cr_wr_ok[0:0] + assign $0\exc_$signal[0:0]$3675 $1\exc_$signal[0:0]$3685 + assign $0\exc_$signal$3[0:0]$3676 $1\exc_$signal$3[0:0]$3686 + assign $0\exc_$signal$4[0:0]$3677 $1\exc_$signal$4[0:0]$3687 + assign $0\exc_$signal$5[0:0]$3678 $1\exc_$signal$5[0:0]$3688 + assign $0\exc_$signal$6[0:0]$3679 $1\exc_$signal$6[0:0]$3689 + assign $0\exc_$signal$7[0:0]$3680 $1\exc_$signal$7[0:0]$3690 + assign $0\exc_$signal$8[0:0]$3681 $1\exc_$signal$8[0:0]$3691 + assign $0\exc_$signal$9[0:0]$3682 $1\exc_$signal$9[0:0]$3692 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\fn_unit[12:0] $1\fn_unit[12:0] + assign $0\input_carry[1:0] $1\input_carry[1:0] + assign $0\insn[31:0] $1\insn[31:0] + assign $0\insn_type[6:0] $1\insn_type[6:0] + assign $0\is_32bit[0:0] $1\is_32bit[0:0] + assign $0\oe[0:0] $1\oe[0:0] + assign $0\oe_ok[0:0] $1\oe_ok[0:0] + assign $0\rc_ok[0:0] $1\rc_ok[0:0] + assign $0\reg1[6:0] $1\reg1[6:0] + assign $0\reg1_ok[0:0] $1\reg1_ok[0:0] + assign $0\reg2[6:0] $1\reg2[6:0] + assign $0\reg2_ok[0:0] $1\reg2_ok[0:0] + assign $0\reg3[6:0] $1\reg3[6:0] + assign $0\reg3_ok[0:0] $1\reg3_ok[0:0] + assign $0\rego[6:0] $1\rego[6:0] + assign $0\rego_ok[0:0] $1\rego_ok[0:0] + assign $0\spro[9:0] $1\spro[9:0] + assign $0\spro_ok[0:0] $1\spro_ok[0:0] + assign $0\trapaddr[12:0] $1\trapaddr[12:0] + assign $0\traptype[7:0] $1\traptype[7:0] + assign $0\xer_in[2:0] $1\xer_in[2:0] + assign $0\xer_out[0:0] $1\xer_out[0:0] + assign $0\fasto1[2:0] $5\fasto1[2:0] + assign $0\fasto1_ok[0:0] $5\fasto1_ok[0:0] + assign $0\fasto2[2:0] $5\fasto2[2:0] + assign $0\fasto2_ok[0:0] $5\fasto2_ok[0:0] + assign $0\fast1[2:0] $5\fast1[2:0] + assign $0\fast1_ok[0:0] $5\fast1_ok[0:0] + assign $0\fast2[2:0] $5\fast2[2:0] + assign $0\fast2_ok[0:0] $5\fast2_ok[0:0] + assign $0\asmcode[7:0] \dec_asmcode + attribute \src "libresoc.v:78849.5-78849.29" + switch \initial + attribute \src "libresoc.v:78849.9-78849.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1215" + switch { \illeg_ok \priv_ok \ext_irq_ok \dec_irq_ok \dec2_exc_$signal } + attribute \src "libresoc.v:0.0-0.0" + case 5'----1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\fast1[2:0] $2\fast1[2:0] + assign $1\fast1_ok[0:0] $2\fast1_ok[0:0] + assign $1\fast2[2:0] $2\fast2[2:0] + assign $1\fast2_ok[0:0] $2\fast2_ok[0:0] + assign $1\rc[0:0] $2\rc[0:0] + assign $1\spr1[9:0] $2\spr1[9:0] + assign $1\spr1_ok[0:0] $2\spr1_ok[0:0] + assign $1\msr[63:0] $2\msr[63:0] + assign $1\ea_ok[0:0] $2\ea_ok[0:0] + assign $1\ea[6:0] $2\ea[6:0] + assign $1\cr_out[6:0] $2\cr_out[6:0] + assign $1\asmcode[7:0] $2\asmcode[7:0] + assign $1\lk[0:0] $2\lk[0:0] + assign $1\cia[63:0] $2\cia[63:0] + assign $1\cr_in1[6:0] $2\cr_in1[6:0] + assign $1\cr_in1_ok[0:0] $2\cr_in1_ok[0:0] + assign $1\cr_in2[6:0] $2\cr_in2[6:0] + assign $1\cr_in2$1[6:0]$3683 $2\cr_in2$1[6:0]$3693 + assign $1\cr_in2_ok[0:0] $2\cr_in2_ok[0:0] + assign $1\cr_in2_ok$2[0:0]$3684 $2\cr_in2_ok$2[0:0]$3694 + assign $1\cr_out_ok[0:0] $2\cr_out_ok[0:0] + assign $1\cr_rd[7:0] $2\cr_rd[7:0] + assign $1\cr_rd_ok[0:0] $2\cr_rd_ok[0:0] + assign $1\cr_wr[7:0] $2\cr_wr[7:0] + assign $1\cr_wr_ok[0:0] $2\cr_wr_ok[0:0] + assign $1\exc_$signal[0:0]$3685 $2\exc_$signal[0:0]$3695 + assign $1\exc_$signal$3[0:0]$3686 $2\exc_$signal$3[0:0]$3696 + assign $1\exc_$signal$4[0:0]$3687 $2\exc_$signal$4[0:0]$3697 + assign $1\exc_$signal$5[0:0]$3688 $2\exc_$signal$5[0:0]$3698 + assign $1\exc_$signal$6[0:0]$3689 $2\exc_$signal$6[0:0]$3699 + assign $1\exc_$signal$7[0:0]$3690 $2\exc_$signal$7[0:0]$3700 + assign $1\exc_$signal$8[0:0]$3691 $2\exc_$signal$8[0:0]$3701 + assign $1\exc_$signal$9[0:0]$3692 $2\exc_$signal$9[0:0]$3702 + assign $1\fasto1[2:0] $2\fasto1[2:0] + assign $1\fasto1_ok[0:0] $2\fasto1_ok[0:0] + assign $1\fasto2[2:0] $2\fasto2[2:0] + assign $1\fasto2_ok[0:0] $2\fasto2_ok[0:0] + assign $1\fn_unit[12:0] $2\fn_unit[12:0] + assign $1\input_carry[1:0] $2\input_carry[1:0] + assign $1\insn[31:0] $2\insn[31:0] + assign $1\insn_type[6:0] $2\insn_type[6:0] + assign $1\is_32bit[0:0] $2\is_32bit[0:0] + assign $1\oe[0:0] $2\oe[0:0] + assign $1\oe_ok[0:0] $2\oe_ok[0:0] + assign $1\rc_ok[0:0] $2\rc_ok[0:0] + assign $1\reg1[6:0] $2\reg1[6:0] + assign $1\reg1_ok[0:0] $2\reg1_ok[0:0] + assign $1\reg2[6:0] $2\reg2[6:0] + assign $1\reg2_ok[0:0] $2\reg2_ok[0:0] + assign $1\reg3[6:0] $2\reg3[6:0] + assign $1\reg3_ok[0:0] $2\reg3_ok[0:0] + assign $1\rego[6:0] $2\rego[6:0] + assign $1\rego_ok[0:0] $2\rego_ok[0:0] + assign $1\spro[9:0] $2\spro[9:0] + assign $1\spro_ok[0:0] $2\spro_ok[0:0] + assign $1\trapaddr[12:0] $2\trapaddr[12:0] + assign $1\traptype[7:0] $2\traptype[7:0] + assign $1\xer_in[2:0] $2\xer_in[2:0] + assign $1\xer_out[0:0] $2\xer_out[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1216" + switch { \dec2_exc_$signal$13 \dec2_exc_$signal$12 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $2\is_32bit[0:0] $2\cr_wr_ok[0:0] $2\cr_wr[7:0] $2\cr_rd_ok[0:0] $2\cr_rd[7:0] $2\exc_$signal$9[0:0]$3702 $2\exc_$signal$8[0:0]$3701 $2\exc_$signal$7[0:0]$3700 $2\exc_$signal$6[0:0]$3699 $2\exc_$signal$5[0:0]$3698 $2\exc_$signal$4[0:0]$3697 $2\exc_$signal$3[0:0]$3696 $2\exc_$signal[0:0]$3695 $2\input_carry[1:0] $2\oe_ok[0:0] $2\oe[0:0] $2\rc_ok[0:0] $2\rc[0:0] $2\lk[0:0] $2\cr_out_ok[0:0] $2\cr_out[6:0] $2\cr_in2_ok$2[0:0]$3694 $2\cr_in2$1[6:0]$3693 $2\cr_in2_ok[0:0] $2\cr_in2[6:0] $2\cr_in1_ok[0:0] $2\cr_in1[6:0] $2\fasto2_ok[0:0] $2\fasto2[2:0] $2\fasto1_ok[0:0] $2\fasto1[2:0] $2\fast2_ok[0:0] $2\fast2[2:0] $2\fast1_ok[0:0] $2\fast1[2:0] $2\xer_out[0:0] $2\xer_in[2:0] $2\spr1_ok[0:0] $2\spr1[9:0] $2\spro_ok[0:0] $2\spro[9:0] $2\reg3_ok[0:0] $2\reg3[6:0] $2\reg2_ok[0:0] $2\reg2[6:0] $2\reg1_ok[0:0] $2\reg1[6:0] $2\ea_ok[0:0] $2\ea[6:0] $2\rego_ok[0:0] $2\rego[6:0] $2\asmcode[7:0] } 156'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign $2\insn[31:0] \dec_opcode_in + assign $2\insn_type[6:0] 7'0111111 + assign $2\fn_unit[12:0] 13'0000010000000 + assign $2\trapaddr[12:0] 13'0000001100000 + assign $2\traptype[7:0] 8'00000010 + assign $2\msr[63:0] \cur_msr + assign $2\cia[63:0] \cur_pc + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $2\fast1[2:0] $3\fast1[2:0] + assign $2\fast1_ok[0:0] $3\fast1_ok[0:0] + assign $2\fast2[2:0] $3\fast2[2:0] + assign $2\fast2_ok[0:0] $3\fast2_ok[0:0] + assign $2\rc[0:0] $3\rc[0:0] + assign $2\spr1[9:0] $3\spr1[9:0] + assign $2\spr1_ok[0:0] $3\spr1_ok[0:0] + assign $2\msr[63:0] $3\msr[63:0] + assign $2\ea_ok[0:0] $3\ea_ok[0:0] + assign $2\ea[6:0] $3\ea[6:0] + assign $2\cr_out[6:0] $3\cr_out[6:0] + assign $2\asmcode[7:0] $3\asmcode[7:0] + assign $2\lk[0:0] $3\lk[0:0] + assign $2\cia[63:0] $3\cia[63:0] + assign $2\cr_in1[6:0] $3\cr_in1[6:0] + assign $2\cr_in1_ok[0:0] $3\cr_in1_ok[0:0] + assign $2\cr_in2[6:0] $3\cr_in2[6:0] + assign $2\cr_in2$1[6:0]$3693 $3\cr_in2$1[6:0]$3703 + assign $2\cr_in2_ok[0:0] $3\cr_in2_ok[0:0] + assign $2\cr_in2_ok$2[0:0]$3694 $3\cr_in2_ok$2[0:0]$3704 + assign $2\cr_out_ok[0:0] $3\cr_out_ok[0:0] + assign $2\cr_rd[7:0] $3\cr_rd[7:0] + assign $2\cr_rd_ok[0:0] $3\cr_rd_ok[0:0] + assign $2\cr_wr[7:0] $3\cr_wr[7:0] + assign $2\cr_wr_ok[0:0] $3\cr_wr_ok[0:0] + assign $2\exc_$signal[0:0]$3695 $3\exc_$signal[0:0]$3705 + assign $2\exc_$signal$3[0:0]$3696 $3\exc_$signal$3[0:0]$3706 + assign $2\exc_$signal$4[0:0]$3697 $3\exc_$signal$4[0:0]$3707 + assign $2\exc_$signal$5[0:0]$3698 $3\exc_$signal$5[0:0]$3708 + assign $2\exc_$signal$6[0:0]$3699 $3\exc_$signal$6[0:0]$3709 + assign $2\exc_$signal$7[0:0]$3700 $3\exc_$signal$7[0:0]$3710 + assign $2\exc_$signal$8[0:0]$3701 $3\exc_$signal$8[0:0]$3711 + assign $2\exc_$signal$9[0:0]$3702 $3\exc_$signal$9[0:0]$3712 + assign $2\fasto1[2:0] $3\fasto1[2:0] + assign $2\fasto1_ok[0:0] $3\fasto1_ok[0:0] + assign $2\fasto2[2:0] $3\fasto2[2:0] + assign $2\fasto2_ok[0:0] $3\fasto2_ok[0:0] + assign $2\fn_unit[12:0] $3\fn_unit[12:0] + assign $2\input_carry[1:0] $3\input_carry[1:0] + assign $2\insn[31:0] $3\insn[31:0] + assign $2\insn_type[6:0] $3\insn_type[6:0] + assign $2\is_32bit[0:0] $3\is_32bit[0:0] + assign $2\oe[0:0] $3\oe[0:0] + assign $2\oe_ok[0:0] $3\oe_ok[0:0] + assign $2\rc_ok[0:0] $3\rc_ok[0:0] + assign $2\reg1[6:0] $3\reg1[6:0] + assign $2\reg1_ok[0:0] $3\reg1_ok[0:0] + assign $2\reg2[6:0] $3\reg2[6:0] + assign $2\reg2_ok[0:0] $3\reg2_ok[0:0] + assign $2\reg3[6:0] $3\reg3[6:0] + assign $2\reg3_ok[0:0] $3\reg3_ok[0:0] + assign $2\rego[6:0] $3\rego[6:0] + assign $2\rego_ok[0:0] $3\rego_ok[0:0] + assign $2\spro[9:0] $3\spro[9:0] + assign $2\spro_ok[0:0] $3\spro_ok[0:0] + assign $2\trapaddr[12:0] $3\trapaddr[12:0] + assign $2\traptype[7:0] $3\traptype[7:0] + assign $2\xer_in[2:0] $3\xer_in[2:0] + assign $2\xer_out[0:0] $3\xer_out[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1219" + switch \dec2_exc_$signal$14 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $3\is_32bit[0:0] $3\cr_wr_ok[0:0] $3\cr_wr[7:0] $3\cr_rd_ok[0:0] $3\cr_rd[7:0] $3\exc_$signal$9[0:0]$3712 $3\exc_$signal$8[0:0]$3711 $3\exc_$signal$7[0:0]$3710 $3\exc_$signal$6[0:0]$3709 $3\exc_$signal$5[0:0]$3708 $3\exc_$signal$4[0:0]$3707 $3\exc_$signal$3[0:0]$3706 $3\exc_$signal[0:0]$3705 $3\input_carry[1:0] $3\oe_ok[0:0] $3\oe[0:0] $3\rc_ok[0:0] $3\rc[0:0] $3\lk[0:0] $3\cr_out_ok[0:0] $3\cr_out[6:0] $3\cr_in2_ok$2[0:0]$3704 $3\cr_in2$1[6:0]$3703 $3\cr_in2_ok[0:0] $3\cr_in2[6:0] $3\cr_in1_ok[0:0] $3\cr_in1[6:0] $3\fasto2_ok[0:0] $3\fasto2[2:0] $3\fasto1_ok[0:0] $3\fasto1[2:0] $3\fast2_ok[0:0] $3\fast2[2:0] $3\fast1_ok[0:0] $3\fast1[2:0] $3\xer_out[0:0] $3\xer_in[2:0] $3\spr1_ok[0:0] $3\spr1[9:0] $3\spro_ok[0:0] $3\spro[9:0] $3\reg3_ok[0:0] $3\reg3[6:0] $3\reg2_ok[0:0] $3\reg2[6:0] $3\reg1_ok[0:0] $3\reg1[6:0] $3\ea_ok[0:0] $3\ea[6:0] $3\rego_ok[0:0] $3\rego[6:0] $3\asmcode[7:0] } 156'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign $3\insn[31:0] \dec_opcode_in + assign $3\insn_type[6:0] 7'0111111 + assign $3\fn_unit[12:0] 13'0000010000000 + assign $3\trapaddr[12:0] 13'0000001001000 + assign $3\traptype[7:0] 8'00000010 + assign $3\msr[63:0] \cur_msr + assign $3\cia[63:0] \cur_pc + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $3\is_32bit[0:0] $3\cr_wr_ok[0:0] $3\cr_wr[7:0] $3\cr_rd_ok[0:0] $3\cr_rd[7:0] $3\input_carry[1:0] $3\oe_ok[0:0] $3\oe[0:0] $3\rc_ok[0:0] $3\rc[0:0] $3\lk[0:0] $3\cr_out_ok[0:0] $3\cr_out[6:0] $3\cr_in2_ok$2[0:0]$3704 $3\cr_in2$1[6:0]$3703 $3\cr_in2_ok[0:0] $3\cr_in2[6:0] $3\cr_in1_ok[0:0] $3\cr_in1[6:0] $3\fasto2_ok[0:0] $3\fasto2[2:0] $3\fasto1_ok[0:0] $3\fasto1[2:0] $3\fast2_ok[0:0] $3\fast2[2:0] $3\fast1_ok[0:0] $3\fast1[2:0] $3\xer_out[0:0] $3\xer_in[2:0] $3\spr1_ok[0:0] $3\spr1[9:0] $3\spro_ok[0:0] $3\spro[9:0] $3\reg3_ok[0:0] $3\reg3[6:0] $3\reg2_ok[0:0] $3\reg2[6:0] $3\reg1_ok[0:0] $3\reg1[6:0] $3\ea_ok[0:0] $3\ea[6:0] $3\rego_ok[0:0] $3\rego[6:0] $3\asmcode[7:0] } 148'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign $3\insn[31:0] \dec_opcode_in + assign $3\insn_type[6:0] 7'0111111 + assign $3\fn_unit[12:0] 13'0000010000000 + assign $3\trapaddr[12:0] 13'0000001000000 + assign $3\traptype[7:0] 8'01000000 + assign { $3\exc_$signal$9[0:0]$3712 $3\exc_$signal$8[0:0]$3711 $3\exc_$signal$7[0:0]$3710 $3\exc_$signal$6[0:0]$3709 $3\exc_$signal$5[0:0]$3708 $3\exc_$signal$4[0:0]$3707 $3\exc_$signal$3[0:0]$3706 $3\exc_$signal[0:0]$3705 } { \dec2_exc_$signal$14 \dec2_exc_$signal$18 \dec2_exc_$signal$17 \dec2_exc_$signal$16 \dec2_exc_$signal$15 \dec2_exc_$signal$13 \dec2_exc_$signal$12 \dec2_exc_$signal } + assign $3\msr[63:0] \cur_msr + assign $3\cia[63:0] \cur_pc + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $2\fast1[2:0] $4\fast1[2:0] + assign $2\fast1_ok[0:0] $4\fast1_ok[0:0] + assign $2\fast2[2:0] $4\fast2[2:0] + assign $2\fast2_ok[0:0] $4\fast2_ok[0:0] + assign $2\rc[0:0] $4\rc[0:0] + assign $2\spr1[9:0] $4\spr1[9:0] + assign $2\spr1_ok[0:0] $4\spr1_ok[0:0] + assign $2\msr[63:0] $4\msr[63:0] + assign $2\ea_ok[0:0] $4\ea_ok[0:0] + assign $2\ea[6:0] $4\ea[6:0] + assign $2\cr_out[6:0] $4\cr_out[6:0] + assign $2\asmcode[7:0] $4\asmcode[7:0] + assign $2\lk[0:0] $4\lk[0:0] + assign $2\cia[63:0] $4\cia[63:0] + assign $2\cr_in1[6:0] $4\cr_in1[6:0] + assign $2\cr_in1_ok[0:0] $4\cr_in1_ok[0:0] + assign $2\cr_in2[6:0] $4\cr_in2[6:0] + assign $2\cr_in2$1[6:0]$3693 $4\cr_in2$1[6:0]$3713 + assign $2\cr_in2_ok[0:0] $4\cr_in2_ok[0:0] + assign $2\cr_in2_ok$2[0:0]$3694 $4\cr_in2_ok$2[0:0]$3714 + assign $2\cr_out_ok[0:0] $4\cr_out_ok[0:0] + assign $2\cr_rd[7:0] $4\cr_rd[7:0] + assign $2\cr_rd_ok[0:0] $4\cr_rd_ok[0:0] + assign $2\cr_wr[7:0] $4\cr_wr[7:0] + assign $2\cr_wr_ok[0:0] $4\cr_wr_ok[0:0] + assign $2\exc_$signal[0:0]$3695 $4\exc_$signal[0:0]$3715 + assign $2\exc_$signal$3[0:0]$3696 $4\exc_$signal$3[0:0]$3716 + assign $2\exc_$signal$4[0:0]$3697 $4\exc_$signal$4[0:0]$3717 + assign $2\exc_$signal$5[0:0]$3698 $4\exc_$signal$5[0:0]$3718 + assign $2\exc_$signal$6[0:0]$3699 $4\exc_$signal$6[0:0]$3719 + assign $2\exc_$signal$7[0:0]$3700 $4\exc_$signal$7[0:0]$3720 + assign $2\exc_$signal$8[0:0]$3701 $4\exc_$signal$8[0:0]$3721 + assign $2\exc_$signal$9[0:0]$3702 $4\exc_$signal$9[0:0]$3722 + assign $2\fasto1[2:0] $4\fasto1[2:0] + assign $2\fasto1_ok[0:0] $4\fasto1_ok[0:0] + assign $2\fasto2[2:0] $4\fasto2[2:0] + assign $2\fasto2_ok[0:0] $4\fasto2_ok[0:0] + assign $2\fn_unit[12:0] $4\fn_unit[12:0] + assign $2\input_carry[1:0] $4\input_carry[1:0] + assign $2\insn[31:0] $4\insn[31:0] + assign $2\insn_type[6:0] $4\insn_type[6:0] + assign $2\is_32bit[0:0] $4\is_32bit[0:0] + assign $2\oe[0:0] $4\oe[0:0] + assign $2\oe_ok[0:0] $4\oe_ok[0:0] + assign $2\rc_ok[0:0] $4\rc_ok[0:0] + assign $2\reg1[6:0] $4\reg1[6:0] + assign $2\reg1_ok[0:0] $4\reg1_ok[0:0] + assign $2\reg2[6:0] $4\reg2[6:0] + assign $2\reg2_ok[0:0] $4\reg2_ok[0:0] + assign $2\reg3[6:0] $4\reg3[6:0] + assign $2\reg3_ok[0:0] $4\reg3_ok[0:0] + assign $2\rego[6:0] $4\rego[6:0] + assign $2\rego_ok[0:0] $4\rego_ok[0:0] + assign $2\spro[9:0] $4\spro[9:0] + assign $2\spro_ok[0:0] $4\spro_ok[0:0] + assign $2\trapaddr[12:0] $4\trapaddr[12:0] + assign $2\traptype[7:0] $4\traptype[7:0] + assign $2\xer_in[2:0] $4\xer_in[2:0] + assign $2\xer_out[0:0] $4\xer_out[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1225" + switch \dec2_exc_$signal$14 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $4\is_32bit[0:0] $4\cr_wr_ok[0:0] $4\cr_wr[7:0] $4\cr_rd_ok[0:0] $4\cr_rd[7:0] $4\exc_$signal$9[0:0]$3722 $4\exc_$signal$8[0:0]$3721 $4\exc_$signal$7[0:0]$3720 $4\exc_$signal$6[0:0]$3719 $4\exc_$signal$5[0:0]$3718 $4\exc_$signal$4[0:0]$3717 $4\exc_$signal$3[0:0]$3716 $4\exc_$signal[0:0]$3715 $4\input_carry[1:0] $4\oe_ok[0:0] $4\oe[0:0] $4\rc_ok[0:0] $4\rc[0:0] $4\lk[0:0] $4\cr_out_ok[0:0] $4\cr_out[6:0] $4\cr_in2_ok$2[0:0]$3714 $4\cr_in2$1[6:0]$3713 $4\cr_in2_ok[0:0] $4\cr_in2[6:0] $4\cr_in1_ok[0:0] $4\cr_in1[6:0] $4\fasto2_ok[0:0] $4\fasto2[2:0] $4\fasto1_ok[0:0] $4\fasto1[2:0] $4\fast2_ok[0:0] $4\fast2[2:0] $4\fast1_ok[0:0] $4\fast1[2:0] $4\xer_out[0:0] $4\xer_in[2:0] $4\spr1_ok[0:0] $4\spr1[9:0] $4\spro_ok[0:0] $4\spro[9:0] $4\reg3_ok[0:0] $4\reg3[6:0] $4\reg2_ok[0:0] $4\reg2[6:0] $4\reg1_ok[0:0] $4\reg1[6:0] $4\ea_ok[0:0] $4\ea[6:0] $4\rego_ok[0:0] $4\rego[6:0] $4\asmcode[7:0] } 156'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign $4\insn[31:0] \dec_opcode_in + assign $4\insn_type[6:0] 7'0111111 + assign $4\fn_unit[12:0] 13'0000010000000 + assign $4\trapaddr[12:0] 13'0000000111000 + assign $4\traptype[7:0] 8'00000010 + assign $4\msr[63:0] \cur_msr + assign $4\cia[63:0] \cur_pc + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $4\is_32bit[0:0] $4\cr_wr_ok[0:0] $4\cr_wr[7:0] $4\cr_rd_ok[0:0] $4\cr_rd[7:0] $4\exc_$signal$9[0:0]$3722 $4\exc_$signal$8[0:0]$3721 $4\exc_$signal$7[0:0]$3720 $4\exc_$signal$6[0:0]$3719 $4\exc_$signal$5[0:0]$3718 $4\exc_$signal$4[0:0]$3717 $4\exc_$signal$3[0:0]$3716 $4\exc_$signal[0:0]$3715 $4\input_carry[1:0] $4\oe_ok[0:0] $4\oe[0:0] $4\rc_ok[0:0] $4\rc[0:0] $4\lk[0:0] $4\cr_out_ok[0:0] $4\cr_out[6:0] $4\cr_in2_ok$2[0:0]$3714 $4\cr_in2$1[6:0]$3713 $4\cr_in2_ok[0:0] $4\cr_in2[6:0] $4\cr_in1_ok[0:0] $4\cr_in1[6:0] $4\fasto2_ok[0:0] $4\fasto2[2:0] $4\fasto1_ok[0:0] $4\fasto1[2:0] $4\fast2_ok[0:0] $4\fast2[2:0] $4\fast1_ok[0:0] $4\fast1[2:0] $4\xer_out[0:0] $4\xer_in[2:0] $4\spr1_ok[0:0] $4\spr1[9:0] $4\spro_ok[0:0] $4\spro[9:0] $4\reg3_ok[0:0] $4\reg3[6:0] $4\reg2_ok[0:0] $4\reg2[6:0] $4\reg1_ok[0:0] $4\reg1[6:0] $4\ea_ok[0:0] $4\ea[6:0] $4\rego_ok[0:0] $4\rego[6:0] $4\asmcode[7:0] } 156'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign $4\insn[31:0] \dec_opcode_in + assign $4\insn_type[6:0] 7'0111111 + assign $4\fn_unit[12:0] 13'0000010000000 + assign $4\trapaddr[12:0] 13'0000000110000 + assign $4\traptype[7:0] 8'00000010 + assign $4\msr[63:0] \cur_msr + assign $4\cia[63:0] \cur_pc + end + end + attribute \src "libresoc.v:0.0-0.0" + case 5'---1- + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\exc_$signal$9[0:0]$3692 $1\exc_$signal$8[0:0]$3691 $1\exc_$signal$7[0:0]$3690 $1\exc_$signal$6[0:0]$3689 $1\exc_$signal$5[0:0]$3688 $1\exc_$signal$4[0:0]$3687 $1\exc_$signal$3[0:0]$3686 $1\exc_$signal[0:0]$3685 $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\cr_out_ok[0:0] $1\cr_out[6:0] $1\cr_in2_ok$2[0:0]$3684 $1\cr_in2$1[6:0]$3683 $1\cr_in2_ok[0:0] $1\cr_in2[6:0] $1\cr_in1_ok[0:0] $1\cr_in1[6:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[6:0] $1\reg2_ok[0:0] $1\reg2[6:0] $1\reg1_ok[0:0] $1\reg1[6:0] $1\ea_ok[0:0] $1\ea[6:0] $1\rego_ok[0:0] $1\rego[6:0] $1\asmcode[7:0] } 156'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign $1\insn[31:0] \dec_opcode_in + assign $1\insn_type[6:0] 7'0111111 + assign $1\fn_unit[12:0] 13'0000010000000 + assign $1\trapaddr[12:0] 13'0000010010000 + assign $1\traptype[7:0] 8'00100000 + assign $1\msr[63:0] \cur_msr + assign $1\cia[63:0] \cur_pc + attribute \src "libresoc.v:0.0-0.0" + case 5'--1-- + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\exc_$signal$9[0:0]$3692 $1\exc_$signal$8[0:0]$3691 $1\exc_$signal$7[0:0]$3690 $1\exc_$signal$6[0:0]$3689 $1\exc_$signal$5[0:0]$3688 $1\exc_$signal$4[0:0]$3687 $1\exc_$signal$3[0:0]$3686 $1\exc_$signal[0:0]$3685 $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\cr_out_ok[0:0] $1\cr_out[6:0] $1\cr_in2_ok$2[0:0]$3684 $1\cr_in2$1[6:0]$3683 $1\cr_in2_ok[0:0] $1\cr_in2[6:0] $1\cr_in1_ok[0:0] $1\cr_in1[6:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[6:0] $1\reg2_ok[0:0] $1\reg2[6:0] $1\reg1_ok[0:0] $1\reg1[6:0] $1\ea_ok[0:0] $1\ea[6:0] $1\rego_ok[0:0] $1\rego[6:0] $1\asmcode[7:0] } 156'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign $1\insn[31:0] \dec_opcode_in + assign $1\insn_type[6:0] 7'0111111 + assign $1\fn_unit[12:0] 13'0000010000000 + assign $1\trapaddr[12:0] 13'0000001010000 + assign $1\traptype[7:0] 8'00010000 + assign $1\msr[63:0] \cur_msr + assign $1\cia[63:0] \cur_pc + attribute \src "libresoc.v:0.0-0.0" + case 5'-1--- + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\exc_$signal$9[0:0]$3692 $1\exc_$signal$8[0:0]$3691 $1\exc_$signal$7[0:0]$3690 $1\exc_$signal$6[0:0]$3689 $1\exc_$signal$5[0:0]$3688 $1\exc_$signal$4[0:0]$3687 $1\exc_$signal$3[0:0]$3686 $1\exc_$signal[0:0]$3685 $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\cr_out_ok[0:0] $1\cr_out[6:0] $1\cr_in2_ok$2[0:0]$3684 $1\cr_in2$1[6:0]$3683 $1\cr_in2_ok[0:0] $1\cr_in2[6:0] $1\cr_in1_ok[0:0] $1\cr_in1[6:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[6:0] $1\reg2_ok[0:0] $1\reg2[6:0] $1\reg1_ok[0:0] $1\reg1[6:0] $1\ea_ok[0:0] $1\ea[6:0] $1\rego_ok[0:0] $1\rego[6:0] $1\asmcode[7:0] } 156'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign $1\insn[31:0] \dec_opcode_in + assign $1\insn_type[6:0] 7'0111111 + assign $1\fn_unit[12:0] 13'0000010000000 + assign $1\trapaddr[12:0] 13'0000001110000 + assign $1\traptype[7:0] 8'00000010 + assign $1\msr[63:0] \cur_msr + assign $1\cia[63:0] \cur_pc + attribute \src "libresoc.v:0.0-0.0" + case 5'1---- + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\exc_$signal$9[0:0]$3692 $1\exc_$signal$8[0:0]$3691 $1\exc_$signal$7[0:0]$3690 $1\exc_$signal$6[0:0]$3689 $1\exc_$signal$5[0:0]$3688 $1\exc_$signal$4[0:0]$3687 $1\exc_$signal$3[0:0]$3686 $1\exc_$signal[0:0]$3685 $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\cr_out_ok[0:0] $1\cr_out[6:0] $1\cr_in2_ok$2[0:0]$3684 $1\cr_in2$1[6:0]$3683 $1\cr_in2_ok[0:0] $1\cr_in2[6:0] $1\cr_in1_ok[0:0] $1\cr_in1[6:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[6:0] $1\reg2_ok[0:0] $1\reg2[6:0] $1\reg1_ok[0:0] $1\reg1[6:0] $1\ea_ok[0:0] $1\ea[6:0] $1\rego_ok[0:0] $1\rego[6:0] $1\asmcode[7:0] } 156'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign $1\insn[31:0] \dec_opcode_in + assign $1\insn_type[6:0] 7'0111111 + assign $1\fn_unit[12:0] 13'0000010000000 + assign $1\trapaddr[12:0] 13'0000001110000 + assign $1\traptype[7:0] 8'10000000 + assign $1\msr[63:0] \cur_msr + assign $1\cia[63:0] \cur_pc + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\trapaddr[12:0] $1\exc_$signal$9[0:0]$3692 $1\exc_$signal$8[0:0]$3691 $1\exc_$signal$7[0:0]$3690 $1\exc_$signal$6[0:0]$3689 $1\exc_$signal$5[0:0]$3688 $1\exc_$signal$4[0:0]$3687 $1\exc_$signal$3[0:0]$3686 $1\exc_$signal[0:0]$3685 $1\traptype[7:0] $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\fn_unit[12:0] $1\insn_type[6:0] $1\insn[31:0] $1\cia[63:0] $1\msr[63:0] $1\cr_out_ok[0:0] $1\cr_out[6:0] $1\cr_in2_ok$2[0:0]$3684 $1\cr_in2$1[6:0]$3683 $1\cr_in2_ok[0:0] $1\cr_in2[6:0] $1\cr_in1_ok[0:0] $1\cr_in1[6:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[6:0] $1\reg2_ok[0:0] $1\reg2[6:0] $1\reg1_ok[0:0] $1\reg1[6:0] $1\ea_ok[0:0] $1\ea[6:0] $1\rego_ok[0:0] $1\rego[6:0] $1\asmcode[7:0] } { \tmp_tmp_is_32bit \tmp_tmp_cr_wr_ok \tmp_tmp_cr_wr \tmp_tmp_cr_rd_ok \tmp_tmp_cr_rd \tmp_tmp_trapaddr \tmp_tmp_exc_$signal$27 \tmp_tmp_exc_$signal$26 \tmp_tmp_exc_$signal$25 \tmp_tmp_exc_$signal$24 \tmp_tmp_exc_$signal$23 \tmp_tmp_exc_$signal$22 \tmp_tmp_exc_$signal$21 \tmp_tmp_exc_$signal \tmp_tmp_traptype \tmp_tmp_input_carry \tmp_tmp_oe_ok \tmp_tmp_oe \tmp_tmp_rc_ok \tmp_tmp_rc \tmp_tmp_lk \tmp_tmp_fn_unit \tmp_tmp_insn_type \tmp_tmp_insn \tmp_tmp_cia \tmp_tmp_msr \tmp_cr_out_ok \tmp_cr_out \tmp_cr_in2_ok$20 \tmp_cr_in2$19 \tmp_cr_in2_ok \tmp_cr_in2 \tmp_cr_in1_ok \tmp_cr_in1 \tmp_fasto2_ok \tmp_fasto2 \tmp_fasto1_ok \tmp_fasto1 \tmp_fast2_ok \tmp_fast2 \tmp_fast1_ok \tmp_fast1 \tmp_xer_out \tmp_xer_in \tmp_spr1_ok \tmp_spr1 \tmp_spro_ok \tmp_spro \tmp_reg3_ok \tmp_reg3 \tmp_reg2_ok \tmp_reg2 \tmp_reg1_ok \tmp_reg1 \tmp_ea_ok \tmp_ea \tmp_rego_ok \tmp_rego \tmp_asmcode } + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1260" + switch \$32 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $5\fasto1[2:0] 3'011 + assign $5\fasto1_ok[0:0] 1'1 + assign $5\fasto2[2:0] 3'100 + assign $5\fasto2_ok[0:0] 1'1 + case + assign $5\fasto1[2:0] $1\fasto1[2:0] + assign $5\fasto1_ok[0:0] $1\fasto1_ok[0:0] + assign $5\fasto2[2:0] $1\fasto2[2:0] + assign $5\fasto2_ok[0:0] $1\fasto2_ok[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1269" + switch \$34 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $5\fast1[2:0] 3'011 + assign $5\fast1_ok[0:0] 1'1 + assign $5\fast2[2:0] 3'100 + assign $5\fast2_ok[0:0] 1'1 + case + assign $5\fast1[2:0] $1\fast1[2:0] + assign $5\fast1_ok[0:0] $1\fast1_ok[0:0] + assign $5\fast2[2:0] $1\fast2[2:0] + assign $5\fast2_ok[0:0] $1\fast2_ok[0:0] + end + sync always + update \fast1 $0\fast1[2:0] + update \fast1_ok $0\fast1_ok[0:0] + update \fast2 $0\fast2[2:0] + update \fast2_ok $0\fast2_ok[0:0] + update \rc $0\rc[0:0] + update \spr1 $0\spr1[9:0] + update \spr1_ok $0\spr1_ok[0:0] + update \msr $0\msr[63:0] + update \ea_ok $0\ea_ok[0:0] + update \ea $0\ea[6:0] + update \cr_out $0\cr_out[6:0] + update \asmcode $0\asmcode[7:0] + update \lk $0\lk[0:0] + update \cia $0\cia[63:0] + update \cr_in1 $0\cr_in1[6:0] + update \cr_in1_ok $0\cr_in1_ok[0:0] + update \cr_in2 $0\cr_in2[6:0] + update \cr_in2$1 $0\cr_in2$1[6:0]$3673 + update \cr_in2_ok $0\cr_in2_ok[0:0] + update \cr_in2_ok$2 $0\cr_in2_ok$2[0:0]$3674 + update \cr_out_ok $0\cr_out_ok[0:0] + update \cr_rd $0\cr_rd[7:0] + update \cr_rd_ok $0\cr_rd_ok[0:0] + update \cr_wr $0\cr_wr[7:0] + update \cr_wr_ok $0\cr_wr_ok[0:0] + update \exc_$signal $0\exc_$signal[0:0]$3675 + update \exc_$signal$3 $0\exc_$signal$3[0:0]$3676 + update \exc_$signal$4 $0\exc_$signal$4[0:0]$3677 + update \exc_$signal$5 $0\exc_$signal$5[0:0]$3678 + update \exc_$signal$6 $0\exc_$signal$6[0:0]$3679 + update \exc_$signal$7 $0\exc_$signal$7[0:0]$3680 + update \exc_$signal$8 $0\exc_$signal$8[0:0]$3681 + update \exc_$signal$9 $0\exc_$signal$9[0:0]$3682 + update \fasto1 $0\fasto1[2:0] + update \fasto1_ok $0\fasto1_ok[0:0] + update \fasto2 $0\fasto2[2:0] + update \fasto2_ok $0\fasto2_ok[0:0] + update \fn_unit $0\fn_unit[12:0] + update \input_carry $0\input_carry[1:0] + update \insn $0\insn[31:0] + update \insn_type $0\insn_type[6:0] + update \is_32bit $0\is_32bit[0:0] + update \oe $0\oe[0:0] + update \oe_ok $0\oe_ok[0:0] + update \rc_ok $0\rc_ok[0:0] + update \reg1 $0\reg1[6:0] + update \reg1_ok $0\reg1_ok[0:0] + update \reg2 $0\reg2[6:0] + update \reg2_ok $0\reg2_ok[0:0] + update \reg3 $0\reg3[6:0] + update \reg3_ok $0\reg3_ok[0:0] + update \rego $0\rego[6:0] + update \rego_ok $0\rego_ok[0:0] + update \spro $0\spro[9:0] + update \spro_ok $0\spro_ok[0:0] + update \trapaddr $0\trapaddr[12:0] + update \traptype $0\traptype[7:0] + update \xer_in $0\xer_in[2:0] + update \xer_out $0\xer_out[0:0] + end + attribute \src "libresoc.v:79006.3-79017.6" + process $proc$libresoc.v:79006$3723 + assign { } { } + assign $0\tmp_tmp_fn_unit[12:0] $1\tmp_tmp_fn_unit[12:0] + attribute \src "libresoc.v:79007.5-79007.29" + switch \initial + attribute \src "libresoc.v:79007.9-79007.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + switch \$57 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\tmp_tmp_fn_unit[12:0] 13'0100000000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\tmp_tmp_fn_unit[12:0] \dec_function_unit + end + sync always + update \tmp_tmp_fn_unit $0\tmp_tmp_fn_unit[12:0] + end + attribute \src "libresoc.v:79018.3-79027.6" + process $proc$libresoc.v:79018$3724 + assign { } { } + assign { } { } + assign $0\tmp_tmp_lk[0:0] $1\tmp_tmp_lk[0:0] + attribute \src "libresoc.v:79019.5-79019.29" + switch \initial + attribute \src "libresoc.v:79019.9-79019.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:957" + switch \dec_lk + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\tmp_tmp_lk[0:0] \dec_LK + case + assign $1\tmp_tmp_lk[0:0] 1'0 + end + sync always + update \tmp_tmp_lk $0\tmp_tmp_lk[0:0] + end + attribute \src "libresoc.v:79028.3-79037.6" + process $proc$libresoc.v:79028$3725 + assign { } { } + assign { } { } + assign $0\cr_a_idx[2:0] $1\cr_a_idx[2:0] + attribute \src "libresoc.v:79029.5-79029.29" + switch \initial + attribute \src "libresoc.v:79029.9-79029.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1090" + switch \$64 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cr_a_idx[2:0] 3'010 + case + assign $1\cr_a_idx[2:0] \dec_sv_cr_in + end + sync always + update \cr_a_idx $0\cr_a_idx[2:0] + end + attribute \src "libresoc.v:79038.3-79047.6" + process $proc$libresoc.v:79038$3726 + assign { } { } + assign { } { } + assign $0\cr_b_idx[2:0] $1\cr_b_idx[2:0] + attribute \src "libresoc.v:79039.5-79039.29" + switch \initial + attribute \src "libresoc.v:79039.9-79039.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1090" + switch \$66 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cr_b_idx[2:0] 3'011 + case + assign $1\cr_b_idx[2:0] 3'000 + end + sync always + update \cr_b_idx $0\cr_b_idx[2:0] + end + attribute \src "libresoc.v:79048.3-79059.6" + process $proc$libresoc.v:79048$3727 + assign { } { } + assign $0\tmp_reg1[6:0] $1\tmp_reg1[6:0] + attribute \src "libresoc.v:79049.5-79049.29" + switch \initial + attribute \src "libresoc.v:79049.9-79049.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1129" + switch \in1_svdec_isvec + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\tmp_reg1[6:0] \$68 [6:0] + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\tmp_reg1[6:0] \in1_svdec_reg_out + end + sync always + update \tmp_reg1 $0\tmp_reg1[6:0] + end + attribute \src "libresoc.v:79060.3-79071.6" + process $proc$libresoc.v:79060$3728 + assign { } { } + assign $0\tmp_reg2[6:0] $1\tmp_reg2[6:0] + attribute \src "libresoc.v:79061.5-79061.29" + switch \initial + attribute \src "libresoc.v:79061.9-79061.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1129" + switch \in2_svdec_isvec + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\tmp_reg2[6:0] \$71 [6:0] + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\tmp_reg2[6:0] \in2_svdec_reg_out + end + sync always + update \tmp_reg2 $0\tmp_reg2[6:0] + end + attribute \src "libresoc.v:79072.3-79083.6" + process $proc$libresoc.v:79072$3729 + assign { } { } + assign $0\tmp_reg3[6:0] $1\tmp_reg3[6:0] + attribute \src "libresoc.v:79073.5-79073.29" + switch \initial + attribute \src "libresoc.v:79073.9-79073.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1129" + switch \in3_svdec_isvec + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\tmp_reg3[6:0] \$74 [6:0] + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\tmp_reg3[6:0] \in3_svdec_reg_out + end + sync always + update \tmp_reg3 $0\tmp_reg3[6:0] + end + attribute \src "libresoc.v:79084.3-79095.6" + process $proc$libresoc.v:79084$3730 + assign { } { } + assign $0\tmp_rego[6:0] $1\tmp_rego[6:0] + attribute \src "libresoc.v:79085.5-79085.29" + switch \initial + attribute \src "libresoc.v:79085.9-79085.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1129" + switch \o_svdec_isvec + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\tmp_rego[6:0] \$77 [6:0] + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\tmp_rego[6:0] \o_svdec_reg_out + end + sync always + update \tmp_rego $0\tmp_rego[6:0] + end + attribute \src "libresoc.v:79096.3-79107.6" + process $proc$libresoc.v:79096$3731 + assign { } { } + assign $0\tmp_ea[6:0] $1\tmp_ea[6:0] + attribute \src "libresoc.v:79097.5-79097.29" + switch \initial + attribute \src "libresoc.v:79097.9-79097.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1129" + switch \o2_svdec_isvec + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\tmp_ea[6:0] \$80 [6:0] + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\tmp_ea[6:0] \o2_svdec_reg_out + end + sync always + update \tmp_ea $0\tmp_ea[6:0] + end + connect \$99 $and$libresoc.v:78536$3635_Y + connect \$101 $and$libresoc.v:78537$3636_Y + connect \$103 $eq$libresoc.v:78538$3637_Y + connect \$28 $eq$libresoc.v:78539$3638_Y + connect \$30 $eq$libresoc.v:78540$3639_Y + connect \$32 $or$libresoc.v:78541$3640_Y + connect \$34 $eq$libresoc.v:78542$3641_Y + connect \$37 $eq$libresoc.v:78543$3642_Y + connect \$39 $eq$libresoc.v:78544$3643_Y + connect \$41 $or$libresoc.v:78545$3644_Y + connect \$43 $eq$libresoc.v:78546$3645_Y + connect \$45 $eq$libresoc.v:78547$3646_Y + connect \$47 $or$libresoc.v:78548$3647_Y + connect \$49 $eq$libresoc.v:78549$3648_Y + connect \$51 $or$libresoc.v:78550$3649_Y + connect \$53 $eq$libresoc.v:78551$3650_Y + connect \$55 $or$libresoc.v:78552$3651_Y + connect \$57 $and$libresoc.v:78553$3652_Y + connect \$64 $eq$libresoc.v:78554$3653_Y + connect \$66 $eq$libresoc.v:78555$3654_Y + connect \$69 $add$libresoc.v:78556$3655_Y + connect \$72 $add$libresoc.v:78557$3656_Y + connect \$75 $add$libresoc.v:78558$3657_Y + connect \$78 $add$libresoc.v:78559$3658_Y + connect \$81 $add$libresoc.v:78560$3659_Y + connect \$83 $not$libresoc.v:78561$3660_Y + connect \$85 $not$libresoc.v:78562$3661_Y + connect \$87 $and$libresoc.v:78563$3662_Y + connect \$89 $eq$libresoc.v:78564$3663_Y + connect \$91 $eq$libresoc.v:78565$3664_Y + connect \$93 $eq$libresoc.v:78566$3665_Y + connect \$95 $eq$libresoc.v:78567$3666_Y + connect \$97 $and$libresoc.v:78568$3667_Y + connect \$68 \$69 + connect \$71 \$72 + connect \$74 \$75 + connect \$77 \$78 + connect \$80 \$81 + connect \dec2_exc_$signal 1'0 + connect \dec2_exc_$signal$12 1'0 + connect \dec2_exc_$signal$13 1'0 + connect \dec2_exc_$signal$14 1'0 + connect \dec2_exc_$signal$15 1'0 + connect \dec2_exc_$signal$16 1'0 + connect \dec2_exc_$signal$17 1'0 + connect \dec2_exc_$signal$18 1'0 + connect \tmp_asmcode 8'00000000 + connect \tmp_tmp_traptype 8'00000000 + connect \tmp_tmp_exc_$signal 1'0 + connect \tmp_tmp_exc_$signal$21 1'0 + connect \tmp_tmp_exc_$signal$22 1'0 + connect \tmp_tmp_exc_$signal$23 1'0 + connect \tmp_tmp_exc_$signal$24 1'0 + connect \tmp_tmp_exc_$signal$25 1'0 + connect \tmp_tmp_exc_$signal$26 1'0 + connect \tmp_tmp_exc_$signal$27 1'0 + connect \illeg_ok \$103 + connect \priv_ok \$101 + connect \dec_irq_ok \$99 + connect \ext_irq_ok \$97 + connect \tmp_cr_out_ok \dec_cr_out_cr_bitfield_ok + connect \tmp_cr_out \crout_svdec_cr_out + connect \crout_svdec_cr_in \dec_cr_out_cr_bitfield + connect \crout_svdec_etype \dec_SV_Etype + connect \crout_svdec_extra \dec_svp64__extra + connect \tmp_cr_in2_ok$20 \dec_cr_in_cr_bitfield_o_ok + connect \tmp_cr_in2$19 \crin_svdec_o_cr_out + connect \crin_svdec_o_cr_in \dec_cr_in_cr_bitfield_o + connect \crin_svdec_o_etype \dec_SV_Etype + connect \crin_svdec_o_extra \dec_svp64__extra + connect \tmp_cr_in2_ok \dec_cr_in_cr_bitfield_b_ok + connect \tmp_cr_in2 \crin_svdec_b_cr_out + connect \crin_svdec_b_cr_in \dec_cr_in_cr_bitfield_b + connect \crin_svdec_b_etype \dec_SV_Etype + connect \crin_svdec_b_extra \dec_svp64__extra + connect \tmp_cr_in1_ok \dec_cr_in_cr_bitfield_ok + connect \tmp_cr_in1 \crin_svdec_cr_out + connect \crin_svdec_cr_in \dec_cr_in_cr_bitfield + connect \crin_svdec_etype \dec_SV_Etype + connect \crin_svdec_extra \dec_svp64__extra + connect { \tmp_fasto2_ok \tmp_fasto2 } { \dec_o2_fast_o2_ok \dec_o2_fast_o2 } + connect { \tmp_fasto1_ok \tmp_fasto1 } { \dec_o_fast_o_ok \dec_o_fast_o } + connect { \tmp_fast2_ok \tmp_fast2 } { \dec_b_fast_b_ok \dec_b_fast_b } + connect { \tmp_fast1_ok \tmp_fast1 } { \dec_a_fast_a_ok \dec_a_fast_a } + connect { \tmp_spro_ok \tmp_spro } { \dec_o_spr_o_ok \dec_o_spr_o } + connect { \tmp_spr1_ok \tmp_spr1 } { \dec_a_spr_a_ok \dec_a_spr_a } + connect \no_out_vec \$87 + connect \reg_o2_isvec \o2_svdec_isvec + connect \reg_o_isvec \o_svdec_isvec + connect \reg_c_isvec \in3_svdec_isvec + connect \reg_b_isvec \in2_svdec_isvec + connect \reg_a_isvec \in1_svdec_isvec + connect \o_svdec_idx \dec_sv_out + connect \in3_svdec_idx \dec_sv_in3 + connect \in2_svdec_idx \dec_sv_in2 + connect \in1_svdec_idx \dec_sv_in1 + connect \tmp_ea_ok \dec_o2_reg_o2_ok + connect \o2_svdec_reg_in \dec_o2_reg_o2 + connect \o2_svdec_etype \dec_SV_Etype + connect \o2_svdec_extra \dec_svp64__extra + connect \tmp_rego_ok \dec_o_reg_o_ok + connect \o_svdec_reg_in \dec_o_reg_o + connect \o_svdec_etype \dec_SV_Etype + connect \o_svdec_extra \dec_svp64__extra + connect \tmp_reg3_ok \dec_c_reg_c_ok + connect \in3_svdec_reg_in \dec_c_reg_c + connect \in3_svdec_etype \dec_SV_Etype + connect \in3_svdec_extra \dec_svp64__extra + connect \tmp_reg2_ok \dec_b_reg_b_ok + connect \in2_svdec_reg_in \dec_b_reg_b [4:0] + connect \in2_svdec_etype \dec_SV_Etype + connect \in2_svdec_extra \dec_svp64__extra + connect \tmp_reg1_ok \dec_a_reg_a_ok + connect \in1_svdec_reg_in \dec_a_reg_a + connect \in1_svdec_etype \dec_SV_Etype + connect \in1_svdec_extra \dec_svp64__extra + connect \srcstep \cur_cur_srcstep + connect \dec_o2_lk \tmp_tmp_lk + connect \sel_in \dec_out_sel + connect \dec_o_sel_in \dec_out_sel + connect \dec_c_sel_in \dec_in3_sel + connect \dec_b_sel_in \dec_in2_sel + connect \dec_a_sel_in \dec_in1_sel + connect \crin_svdec_o_idx \dec_sv_cr_out + connect \crin_svdec_b_idx \cr_b_idx + connect \crin_svdec_idx \cr_a_idx + connect \cr_in_o_isvec \crin_svdec_o_isvec + connect \cr_in_b_isvec \crin_svdec_b_isvec + connect \cr_in_isvec \crin_svdec_isvec + connect \cr_out_isvec \crout_svdec_isvec + connect \crout_svdec_idx \dec_sv_cr_out + connect \insn_in$63 \dec_opcode_in + connect \insn_in$62 \dec_opcode_in + connect \insn_in$61 \dec_opcode_in + connect \insn_in$60 \dec_opcode_in + connect \insn_in$59 \dec_opcode_in + connect \tmp_tmp_insn \dec_opcode_in + connect \tmp_tmp_is_32bit \dec_is_32b + connect \tmp_tmp_input_carry \dec_cry_in + connect { \tmp_tmp_cr_wr_ok \tmp_tmp_cr_wr } { \dec_cr_out_cr_fxm_ok \dec_cr_out_cr_fxm } + connect { \tmp_tmp_cr_rd_ok \tmp_tmp_cr_rd } { \dec_cr_in_cr_fxm_ok \dec_cr_in_cr_fxm } + connect { \tmp_tmp_oe_ok \tmp_tmp_oe } { \dec_oe_oe_ok \dec_oe_oe } + connect { \tmp_tmp_rc_ok \tmp_tmp_rc } { \dec_rc_rc_ok \dec_rc_rc } + connect \spr { \dec_SPR [4:0] \dec_SPR [9:5] } + connect \tmp_tmp_insn_type \dec_internal_op + connect \tmp_tmp_cia \cur_pc + connect \tmp_tmp_msr \cur_msr + connect \dec_cr_out_rc_in \dec_rc_rc + connect \dec_cr_out_sel_in \dec_cr_out + connect \dec_cr_in_sel_in \dec_cr_in + connect \dec_oe_sel_in \dec_rc_sel + connect \dec_rc_sel_in \dec_rc_sel + connect \dec_cr_out_insn_in \dec_opcode_in + connect \dec_cr_in_insn_in \dec_opcode_in + connect \insn_in$36 \dec_opcode_in + connect \insn_in \dec_opcode_in +end +attribute \src "libresoc.v:79235.1-80755.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec30" +attribute \generator "nMigen" +module \dec30 + attribute \src "libresoc.v:80532.3-80568.6" + wire width 2 $0\dec30_SV_Etype[1:0] + attribute \src "libresoc.v:80569.3-80605.6" + wire width 2 $0\dec30_SV_Ptype[1:0] + attribute \src "libresoc.v:80088.3-80124.6" + wire width 8 $0\dec30_asmcode[7:0] + attribute \src "libresoc.v:80236.3-80272.6" + wire $0\dec30_br[0:0] + attribute \src "libresoc.v:79607.3-79643.6" + wire width 3 $0\dec30_cr_in[2:0] + attribute \src "libresoc.v:79644.3-79680.6" + wire width 3 $0\dec30_cr_out[2:0] + attribute \src "libresoc.v:80051.3-80087.6" + wire width 2 $0\dec30_cry_in[1:0] + attribute \src "libresoc.v:80199.3-80235.6" + wire $0\dec30_cry_out[0:0] + attribute \src "libresoc.v:80384.3-80420.6" + wire width 5 $0\dec30_form[4:0] + attribute \src "libresoc.v:79570.3-79606.6" + wire width 13 $0\dec30_function_unit[12:0] + attribute \src "libresoc.v:80606.3-80642.6" + wire width 3 $0\dec30_in1_sel[2:0] + attribute \src "libresoc.v:80643.3-80679.6" + wire width 4 $0\dec30_in2_sel[3:0] + attribute \src "libresoc.v:80680.3-80716.6" + wire width 2 $0\dec30_in3_sel[1:0] + attribute \src "libresoc.v:79977.3-80013.6" + wire width 7 $0\dec30_internal_op[6:0] + attribute \src "libresoc.v:80125.3-80161.6" + wire $0\dec30_inv_a[0:0] + attribute \src "libresoc.v:80162.3-80198.6" + wire $0\dec30_inv_out[0:0] + attribute \src "libresoc.v:80347.3-80383.6" + wire $0\dec30_is_32b[0:0] + attribute \src "libresoc.v:79903.3-79939.6" + wire width 4 $0\dec30_ldst_len[3:0] + attribute \src "libresoc.v:80458.3-80494.6" + wire $0\dec30_lk[0:0] + attribute \src "libresoc.v:80717.3-80753.6" + wire width 2 $0\dec30_out_sel[1:0] + attribute \src "libresoc.v:80014.3-80050.6" + wire width 2 $0\dec30_rc_sel[1:0] + attribute \src "libresoc.v:80310.3-80346.6" + wire $0\dec30_rsrv[0:0] + attribute \src "libresoc.v:80495.3-80531.6" + wire $0\dec30_sgl_pipe[0:0] + attribute \src "libresoc.v:80421.3-80457.6" + wire $0\dec30_sgn[0:0] + attribute \src "libresoc.v:80273.3-80309.6" + wire $0\dec30_sgn_ext[0:0] + attribute \src "libresoc.v:79829.3-79865.6" + wire width 3 $0\dec30_sv_cr_in[2:0] + attribute \src "libresoc.v:79866.3-79902.6" + wire width 3 $0\dec30_sv_cr_out[2:0] + attribute \src "libresoc.v:79681.3-79717.6" + wire width 3 $0\dec30_sv_in1[2:0] + attribute \src "libresoc.v:79718.3-79754.6" + wire width 3 $0\dec30_sv_in2[2:0] + attribute \src "libresoc.v:79755.3-79791.6" + wire width 3 $0\dec30_sv_in3[2:0] + attribute \src "libresoc.v:79792.3-79828.6" + wire width 3 $0\dec30_sv_out[2:0] + attribute \src "libresoc.v:79940.3-79976.6" + wire width 2 $0\dec30_upd[1:0] + attribute \src "libresoc.v:79236.7-79236.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:80532.3-80568.6" + wire width 2 $1\dec30_SV_Etype[1:0] + attribute \src "libresoc.v:80569.3-80605.6" + wire width 2 $1\dec30_SV_Ptype[1:0] + attribute \src "libresoc.v:80088.3-80124.6" + wire width 8 $1\dec30_asmcode[7:0] + attribute \src "libresoc.v:80236.3-80272.6" + wire $1\dec30_br[0:0] + attribute \src "libresoc.v:79607.3-79643.6" + wire width 3 $1\dec30_cr_in[2:0] + attribute \src "libresoc.v:79644.3-79680.6" + wire width 3 $1\dec30_cr_out[2:0] + attribute \src "libresoc.v:80051.3-80087.6" + wire width 2 $1\dec30_cry_in[1:0] + attribute \src "libresoc.v:80199.3-80235.6" + wire $1\dec30_cry_out[0:0] + attribute \src "libresoc.v:80384.3-80420.6" + wire width 5 $1\dec30_form[4:0] + attribute \src "libresoc.v:79570.3-79606.6" + wire width 13 $1\dec30_function_unit[12:0] + attribute \src "libresoc.v:80606.3-80642.6" + wire width 3 $1\dec30_in1_sel[2:0] + attribute \src "libresoc.v:80643.3-80679.6" + wire width 4 $1\dec30_in2_sel[3:0] + attribute \src "libresoc.v:80680.3-80716.6" + wire width 2 $1\dec30_in3_sel[1:0] + attribute \src "libresoc.v:79977.3-80013.6" + wire width 7 $1\dec30_internal_op[6:0] + attribute \src "libresoc.v:80125.3-80161.6" + wire $1\dec30_inv_a[0:0] + attribute \src "libresoc.v:80162.3-80198.6" + wire $1\dec30_inv_out[0:0] + attribute \src "libresoc.v:80347.3-80383.6" + wire $1\dec30_is_32b[0:0] + attribute \src "libresoc.v:79903.3-79939.6" + wire width 4 $1\dec30_ldst_len[3:0] + attribute \src "libresoc.v:80458.3-80494.6" + wire $1\dec30_lk[0:0] + attribute \src "libresoc.v:80717.3-80753.6" + wire width 2 $1\dec30_out_sel[1:0] + attribute \src "libresoc.v:80014.3-80050.6" + wire width 2 $1\dec30_rc_sel[1:0] + attribute \src "libresoc.v:80310.3-80346.6" + wire $1\dec30_rsrv[0:0] + attribute \src "libresoc.v:80495.3-80531.6" + wire $1\dec30_sgl_pipe[0:0] + attribute \src "libresoc.v:80421.3-80457.6" + wire $1\dec30_sgn[0:0] + attribute \src "libresoc.v:80273.3-80309.6" + wire $1\dec30_sgn_ext[0:0] + attribute \src "libresoc.v:79829.3-79865.6" + wire width 3 $1\dec30_sv_cr_in[2:0] + attribute \src "libresoc.v:79866.3-79902.6" + wire width 3 $1\dec30_sv_cr_out[2:0] + attribute \src "libresoc.v:79681.3-79717.6" + wire width 3 $1\dec30_sv_in1[2:0] + attribute \src "libresoc.v:79718.3-79754.6" + wire width 3 $1\dec30_sv_in2[2:0] + attribute \src "libresoc.v:79755.3-79791.6" + wire width 3 $1\dec30_sv_in3[2:0] + attribute \src "libresoc.v:79792.3-79828.6" + wire width 3 $1\dec30_sv_out[2:0] + attribute \src "libresoc.v:79940.3-79976.6" + wire width 2 $1\dec30_upd[1:0] + attribute \enum_base_type "SVEtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "EXTRA2" + attribute \enum_value_10 "EXTRA3" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 5 \dec30_SV_Etype + attribute \enum_base_type "SVPtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "P1" + attribute \enum_value_10 "P2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 6 \dec30_SV_Ptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 8 output 4 \dec30_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 26 \dec30_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 11 \dec30_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 12 \dec30_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 22 \dec30_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 25 \dec30_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 5 output 3 \dec30_form + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 13 output 1 \dec30_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 7 \dec30_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 8 \dec30_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 9 \dec30_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 output 2 \dec30_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 23 \dec30_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 24 \dec30_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 29 \dec30_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 19 \dec30_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 31 \dec30_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 10 \dec30_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 21 \dec30_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 28 \dec30_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 32 \dec30_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 30 \dec30_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 27 \dec30_sgn_ext + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 17 \dec30_sv_cr_in + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 18 \dec30_sv_cr_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 13 \dec30_sv_in1 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 14 \dec30_sv_in2 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 15 \dec30_sv_in3 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 16 \dec30_sv_out + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 20 \dec30_upd + attribute \src "libresoc.v:79236.7-79236.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + wire width 32 input 33 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + wire width 4 \opcode_switch + attribute \src "libresoc.v:79236.7-79236.20" + process $proc$libresoc.v:79236$3765 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:79570.3-79606.6" + process $proc$libresoc.v:79570$3733 + assign { } { } + assign { } { } + assign $0\dec30_function_unit[12:0] $1\dec30_function_unit[12:0] + attribute \src "libresoc.v:79571.5-79571.29" + switch \initial + attribute \src "libresoc.v:79571.9-79571.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_function_unit[12:0] 13'0000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_function_unit[12:0] 13'0000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_function_unit[12:0] 13'0000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_function_unit[12:0] 13'0000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_function_unit[12:0] 13'0000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_function_unit[12:0] 13'0000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_function_unit[12:0] 13'0000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_function_unit[12:0] 13'0000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_function_unit[12:0] 13'0000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_function_unit[12:0] 13'0000000001000 + case + assign $1\dec30_function_unit[12:0] 13'0000000000000 + end + sync always + update \dec30_function_unit $0\dec30_function_unit[12:0] + end + attribute \src "libresoc.v:79607.3-79643.6" + process $proc$libresoc.v:79607$3734 + assign { } { } + assign { } { } + assign $0\dec30_cr_in[2:0] $1\dec30_cr_in[2:0] + attribute \src "libresoc.v:79608.5-79608.29" + switch \initial + attribute \src "libresoc.v:79608.9-79608.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_cr_in[2:0] 3'000 + case + assign $1\dec30_cr_in[2:0] 3'000 + end + sync always + update \dec30_cr_in $0\dec30_cr_in[2:0] + end + attribute \src "libresoc.v:79644.3-79680.6" + process $proc$libresoc.v:79644$3735 + assign { } { } + assign { } { } + assign $0\dec30_cr_out[2:0] $1\dec30_cr_out[2:0] + attribute \src "libresoc.v:79645.5-79645.29" + switch \initial + attribute \src "libresoc.v:79645.9-79645.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_cr_out[2:0] 3'001 + case + assign $1\dec30_cr_out[2:0] 3'000 + end + sync always + update \dec30_cr_out $0\dec30_cr_out[2:0] + end + attribute \src "libresoc.v:79681.3-79717.6" + process $proc$libresoc.v:79681$3736 + assign { } { } + assign { } { } + assign $0\dec30_sv_in1[2:0] $1\dec30_sv_in1[2:0] + attribute \src "libresoc.v:79682.5-79682.29" + switch \initial + attribute \src "libresoc.v:79682.9-79682.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_sv_in1[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_sv_in1[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_sv_in1[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_sv_in1[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_sv_in1[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_sv_in1[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_sv_in1[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_sv_in1[2:0] 3'000 + case + assign $1\dec30_sv_in1[2:0] 3'000 + end + sync always + update \dec30_sv_in1 $0\dec30_sv_in1[2:0] + end + attribute \src "libresoc.v:79718.3-79754.6" + process $proc$libresoc.v:79718$3737 + assign { } { } + assign { } { } + assign $0\dec30_sv_in2[2:0] $1\dec30_sv_in2[2:0] + attribute \src "libresoc.v:79719.5-79719.29" + switch \initial + attribute \src "libresoc.v:79719.9-79719.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_sv_in2[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_sv_in2[2:0] 3'010 + case + assign $1\dec30_sv_in2[2:0] 3'000 + end + sync always + update \dec30_sv_in2 $0\dec30_sv_in2[2:0] + end + attribute \src "libresoc.v:79755.3-79791.6" + process $proc$libresoc.v:79755$3738 + assign { } { } + assign { } { } + assign $0\dec30_sv_in3[2:0] $1\dec30_sv_in3[2:0] + attribute \src "libresoc.v:79756.5-79756.29" + switch \initial + attribute \src "libresoc.v:79756.9-79756.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_sv_in3[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_sv_in3[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_sv_in3[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_sv_in3[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_sv_in3[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_sv_in3[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_sv_in3[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_sv_in3[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_sv_in3[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_sv_in3[2:0] 3'011 + case + assign $1\dec30_sv_in3[2:0] 3'000 + end + sync always + update \dec30_sv_in3 $0\dec30_sv_in3[2:0] + end + attribute \src "libresoc.v:79792.3-79828.6" + process $proc$libresoc.v:79792$3739 + assign { } { } + assign { } { } + assign $0\dec30_sv_out[2:0] $1\dec30_sv_out[2:0] + attribute \src "libresoc.v:79793.5-79793.29" + switch \initial + attribute \src "libresoc.v:79793.9-79793.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_sv_out[2:0] 3'001 + case + assign $1\dec30_sv_out[2:0] 3'000 + end + sync always + update \dec30_sv_out $0\dec30_sv_out[2:0] + end + attribute \src "libresoc.v:79829.3-79865.6" + process $proc$libresoc.v:79829$3740 + assign { } { } + assign { } { } + assign $0\dec30_sv_cr_in[2:0] $1\dec30_sv_cr_in[2:0] + attribute \src "libresoc.v:79830.5-79830.29" + switch \initial + attribute \src "libresoc.v:79830.9-79830.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_sv_cr_in[2:0] 3'000 + case + assign $1\dec30_sv_cr_in[2:0] 3'000 + end + sync always + update \dec30_sv_cr_in $0\dec30_sv_cr_in[2:0] + end + attribute \src "libresoc.v:79866.3-79902.6" + process $proc$libresoc.v:79866$3741 + assign { } { } + assign { } { } + assign $0\dec30_sv_cr_out[2:0] $1\dec30_sv_cr_out[2:0] + attribute \src "libresoc.v:79867.5-79867.29" + switch \initial + attribute \src "libresoc.v:79867.9-79867.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_sv_cr_out[2:0] 3'001 + case + assign $1\dec30_sv_cr_out[2:0] 3'000 + end + sync always + update \dec30_sv_cr_out $0\dec30_sv_cr_out[2:0] + end + attribute \src "libresoc.v:79903.3-79939.6" + process $proc$libresoc.v:79903$3742 + assign { } { } + assign { } { } + assign $0\dec30_ldst_len[3:0] $1\dec30_ldst_len[3:0] + attribute \src "libresoc.v:79904.5-79904.29" + switch \initial + attribute \src "libresoc.v:79904.9-79904.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_ldst_len[3:0] 4'0000 + case + assign $1\dec30_ldst_len[3:0] 4'0000 + end + sync always + update \dec30_ldst_len $0\dec30_ldst_len[3:0] + end + attribute \src "libresoc.v:79940.3-79976.6" + process $proc$libresoc.v:79940$3743 + assign { } { } + assign { } { } + assign $0\dec30_upd[1:0] $1\dec30_upd[1:0] + attribute \src "libresoc.v:79941.5-79941.29" + switch \initial + attribute \src "libresoc.v:79941.9-79941.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_upd[1:0] 2'00 + case + assign $1\dec30_upd[1:0] 2'00 + end + sync always + update \dec30_upd $0\dec30_upd[1:0] + end + attribute \src "libresoc.v:79977.3-80013.6" + process $proc$libresoc.v:79977$3744 + assign { } { } + assign { } { } + assign $0\dec30_internal_op[6:0] $1\dec30_internal_op[6:0] + attribute \src "libresoc.v:79978.5-79978.29" + switch \initial + attribute \src "libresoc.v:79978.9-79978.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_internal_op[6:0] 7'0111000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_internal_op[6:0] 7'0111000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_internal_op[6:0] 7'0111001 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_internal_op[6:0] 7'0111001 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_internal_op[6:0] 7'0111010 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_internal_op[6:0] 7'0111010 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_internal_op[6:0] 7'0111000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_internal_op[6:0] 7'0111000 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_internal_op[6:0] 7'0111001 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_internal_op[6:0] 7'0111010 + case + assign $1\dec30_internal_op[6:0] 7'0000000 + end + sync always + update \dec30_internal_op $0\dec30_internal_op[6:0] + end + attribute \src "libresoc.v:80014.3-80050.6" + process $proc$libresoc.v:80014$3745 + assign { } { } + assign { } { } + assign $0\dec30_rc_sel[1:0] $1\dec30_rc_sel[1:0] + attribute \src "libresoc.v:80015.5-80015.29" + switch \initial + attribute \src "libresoc.v:80015.9-80015.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_rc_sel[1:0] 2'10 + case + assign $1\dec30_rc_sel[1:0] 2'00 + end + sync always + update \dec30_rc_sel $0\dec30_rc_sel[1:0] + end + attribute \src "libresoc.v:80051.3-80087.6" + process $proc$libresoc.v:80051$3746 + assign { } { } + assign { } { } + assign $0\dec30_cry_in[1:0] $1\dec30_cry_in[1:0] + attribute \src "libresoc.v:80052.5-80052.29" + switch \initial + attribute \src "libresoc.v:80052.9-80052.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_cry_in[1:0] 2'00 + case + assign $1\dec30_cry_in[1:0] 2'00 + end + sync always + update \dec30_cry_in $0\dec30_cry_in[1:0] + end + attribute \src "libresoc.v:80088.3-80124.6" + process $proc$libresoc.v:80088$3747 + assign { } { } + assign { } { } + assign $0\dec30_asmcode[7:0] $1\dec30_asmcode[7:0] + attribute \src "libresoc.v:80089.5-80089.29" + switch \initial + attribute \src "libresoc.v:80089.9-80089.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_asmcode[7:0] 8'10010100 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_asmcode[7:0] 8'10010100 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_asmcode[7:0] 8'10010101 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_asmcode[7:0] 8'10010101 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_asmcode[7:0] 8'10010110 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_asmcode[7:0] 8'10010110 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_asmcode[7:0] 8'10010111 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_asmcode[7:0] 8'10010111 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_asmcode[7:0] 8'10010010 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_asmcode[7:0] 8'10010011 + case + assign $1\dec30_asmcode[7:0] 8'00000000 + end + sync always + update \dec30_asmcode $0\dec30_asmcode[7:0] + end + attribute \src "libresoc.v:80125.3-80161.6" + process $proc$libresoc.v:80125$3748 + assign { } { } + assign { } { } + assign $0\dec30_inv_a[0:0] $1\dec30_inv_a[0:0] + attribute \src "libresoc.v:80126.5-80126.29" + switch \initial + attribute \src "libresoc.v:80126.9-80126.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_inv_a[0:0] 1'0 + case + assign $1\dec30_inv_a[0:0] 1'0 + end + sync always + update \dec30_inv_a $0\dec30_inv_a[0:0] + end + attribute \src "libresoc.v:80162.3-80198.6" + process $proc$libresoc.v:80162$3749 + assign { } { } + assign { } { } + assign $0\dec30_inv_out[0:0] $1\dec30_inv_out[0:0] + attribute \src "libresoc.v:80163.5-80163.29" + switch \initial + attribute \src "libresoc.v:80163.9-80163.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_inv_out[0:0] 1'0 + case + assign $1\dec30_inv_out[0:0] 1'0 + end + sync always + update \dec30_inv_out $0\dec30_inv_out[0:0] + end + attribute \src "libresoc.v:80199.3-80235.6" + process $proc$libresoc.v:80199$3750 + assign { } { } + assign { } { } + assign $0\dec30_cry_out[0:0] $1\dec30_cry_out[0:0] + attribute \src "libresoc.v:80200.5-80200.29" + switch \initial + attribute \src "libresoc.v:80200.9-80200.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_cry_out[0:0] 1'0 + case + assign $1\dec30_cry_out[0:0] 1'0 + end + sync always + update \dec30_cry_out $0\dec30_cry_out[0:0] + end + attribute \src "libresoc.v:80236.3-80272.6" + process $proc$libresoc.v:80236$3751 + assign { } { } + assign { } { } + assign $0\dec30_br[0:0] $1\dec30_br[0:0] + attribute \src "libresoc.v:80237.5-80237.29" + switch \initial + attribute \src "libresoc.v:80237.9-80237.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_br[0:0] 1'0 + case + assign $1\dec30_br[0:0] 1'0 + end + sync always + update \dec30_br $0\dec30_br[0:0] + end + attribute \src "libresoc.v:80273.3-80309.6" + process $proc$libresoc.v:80273$3752 + assign { } { } + assign { } { } + assign $0\dec30_sgn_ext[0:0] $1\dec30_sgn_ext[0:0] + attribute \src "libresoc.v:80274.5-80274.29" + switch \initial + attribute \src "libresoc.v:80274.9-80274.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_sgn_ext[0:0] 1'0 + case + assign $1\dec30_sgn_ext[0:0] 1'0 + end + sync always + update \dec30_sgn_ext $0\dec30_sgn_ext[0:0] + end + attribute \src "libresoc.v:80310.3-80346.6" + process $proc$libresoc.v:80310$3753 + assign { } { } + assign { } { } + assign $0\dec30_rsrv[0:0] $1\dec30_rsrv[0:0] + attribute \src "libresoc.v:80311.5-80311.29" + switch \initial + attribute \src "libresoc.v:80311.9-80311.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_rsrv[0:0] 1'0 + case + assign $1\dec30_rsrv[0:0] 1'0 + end + sync always + update \dec30_rsrv $0\dec30_rsrv[0:0] + end + attribute \src "libresoc.v:80347.3-80383.6" + process $proc$libresoc.v:80347$3754 + assign { } { } + assign { } { } + assign $0\dec30_is_32b[0:0] $1\dec30_is_32b[0:0] + attribute \src "libresoc.v:80348.5-80348.29" + switch \initial + attribute \src "libresoc.v:80348.9-80348.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_is_32b[0:0] 1'0 + case + assign $1\dec30_is_32b[0:0] 1'0 + end + sync always + update \dec30_is_32b $0\dec30_is_32b[0:0] + end + attribute \src "libresoc.v:80384.3-80420.6" + process $proc$libresoc.v:80384$3755 + assign { } { } + assign { } { } + assign $0\dec30_form[4:0] $1\dec30_form[4:0] + attribute \src "libresoc.v:80385.5-80385.29" + switch \initial + attribute \src "libresoc.v:80385.9-80385.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_form[4:0] 5'10100 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_form[4:0] 5'10100 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_form[4:0] 5'10101 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_form[4:0] 5'10101 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_form[4:0] 5'10100 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_form[4:0] 5'10100 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_form[4:0] 5'10100 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_form[4:0] 5'10100 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_form[4:0] 5'10100 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_form[4:0] 5'10100 + case + assign $1\dec30_form[4:0] 5'00000 + end + sync always + update \dec30_form $0\dec30_form[4:0] + end + attribute \src "libresoc.v:80421.3-80457.6" + process $proc$libresoc.v:80421$3756 + assign { } { } + assign { } { } + assign $0\dec30_sgn[0:0] $1\dec30_sgn[0:0] + attribute \src "libresoc.v:80422.5-80422.29" + switch \initial + attribute \src "libresoc.v:80422.9-80422.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_sgn[0:0] 1'0 + case + assign $1\dec30_sgn[0:0] 1'0 + end + sync always + update \dec30_sgn $0\dec30_sgn[0:0] + end + attribute \src "libresoc.v:80458.3-80494.6" + process $proc$libresoc.v:80458$3757 + assign { } { } + assign { } { } + assign $0\dec30_lk[0:0] $1\dec30_lk[0:0] + attribute \src "libresoc.v:80459.5-80459.29" + switch \initial + attribute \src "libresoc.v:80459.9-80459.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_lk[0:0] 1'0 + case + assign $1\dec30_lk[0:0] 1'0 + end + sync always + update \dec30_lk $0\dec30_lk[0:0] + end + attribute \src "libresoc.v:80495.3-80531.6" + process $proc$libresoc.v:80495$3758 + assign { } { } + assign { } { } + assign $0\dec30_sgl_pipe[0:0] $1\dec30_sgl_pipe[0:0] + attribute \src "libresoc.v:80496.5-80496.29" + switch \initial + attribute \src "libresoc.v:80496.9-80496.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_sgl_pipe[0:0] 1'0 + case + assign $1\dec30_sgl_pipe[0:0] 1'0 + end + sync always + update \dec30_sgl_pipe $0\dec30_sgl_pipe[0:0] + end + attribute \src "libresoc.v:80532.3-80568.6" + process $proc$libresoc.v:80532$3759 + assign { } { } + assign { } { } + assign $0\dec30_SV_Etype[1:0] $1\dec30_SV_Etype[1:0] + attribute \src "libresoc.v:80533.5-80533.29" + switch \initial + attribute \src "libresoc.v:80533.9-80533.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_SV_Etype[1:0] 2'10 + case + assign $1\dec30_SV_Etype[1:0] 2'00 + end + sync always + update \dec30_SV_Etype $0\dec30_SV_Etype[1:0] + end + attribute \src "libresoc.v:80569.3-80605.6" + process $proc$libresoc.v:80569$3760 + assign { } { } + assign { } { } + assign $0\dec30_SV_Ptype[1:0] $1\dec30_SV_Ptype[1:0] + attribute \src "libresoc.v:80570.5-80570.29" + switch \initial + attribute \src "libresoc.v:80570.9-80570.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_SV_Ptype[1:0] 2'01 + case + assign $1\dec30_SV_Ptype[1:0] 2'00 + end + sync always + update \dec30_SV_Ptype $0\dec30_SV_Ptype[1:0] + end + attribute \src "libresoc.v:80606.3-80642.6" + process $proc$libresoc.v:80606$3761 + assign { } { } + assign { } { } + assign $0\dec30_in1_sel[2:0] $1\dec30_in1_sel[2:0] + attribute \src "libresoc.v:80607.5-80607.29" + switch \initial + attribute \src "libresoc.v:80607.9-80607.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_in1_sel[2:0] 3'000 + case + assign $1\dec30_in1_sel[2:0] 3'000 + end + sync always + update \dec30_in1_sel $0\dec30_in1_sel[2:0] + end + attribute \src "libresoc.v:80643.3-80679.6" + process $proc$libresoc.v:80643$3762 + assign { } { } + assign { } { } + assign $0\dec30_in2_sel[3:0] $1\dec30_in2_sel[3:0] + attribute \src "libresoc.v:80644.5-80644.29" + switch \initial + attribute \src "libresoc.v:80644.9-80644.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_in2_sel[3:0] 4'1010 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_in2_sel[3:0] 4'1010 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_in2_sel[3:0] 4'1010 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_in2_sel[3:0] 4'1010 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_in2_sel[3:0] 4'1010 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_in2_sel[3:0] 4'1010 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_in2_sel[3:0] 4'1010 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_in2_sel[3:0] 4'1010 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_in2_sel[3:0] 4'0001 + case + assign $1\dec30_in2_sel[3:0] 4'0000 + end + sync always + update \dec30_in2_sel $0\dec30_in2_sel[3:0] + end + attribute \src "libresoc.v:80680.3-80716.6" + process $proc$libresoc.v:80680$3763 + assign { } { } + assign { } { } + assign $0\dec30_in3_sel[1:0] $1\dec30_in3_sel[1:0] + attribute \src "libresoc.v:80681.5-80681.29" + switch \initial + attribute \src "libresoc.v:80681.9-80681.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_in3_sel[1:0] 2'01 + case + assign $1\dec30_in3_sel[1:0] 2'00 + end + sync always + update \dec30_in3_sel $0\dec30_in3_sel[1:0] + end + attribute \src "libresoc.v:80717.3-80753.6" + process $proc$libresoc.v:80717$3764 + assign { } { } + assign { } { } + assign $0\dec30_out_sel[1:0] $1\dec30_out_sel[1:0] + attribute \src "libresoc.v:80718.5-80718.29" + switch \initial + attribute \src "libresoc.v:80718.9-80718.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_out_sel[1:0] 2'10 + case + assign $1\dec30_out_sel[1:0] 2'00 + end + sync always + update \dec30_out_sel $0\dec30_out_sel[1:0] + end + connect \opcode_switch \opcode_in [4:1] +end +attribute \src "libresoc.v:80759.1-89080.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31" +attribute \generator "nMigen" +module \dec31 + attribute \src "libresoc.v:87352.3-87412.6" + wire width 2 $0\dec31_SV_Etype[1:0] + attribute \src "libresoc.v:87413.3-87473.6" + wire width 2 $0\dec31_SV_Ptype[1:0] + attribute \src "libresoc.v:87291.3-87351.6" + wire width 8 $0\dec31_asmcode[7:0] + attribute \src "libresoc.v:88633.3-88693.6" + wire $0\dec31_br[0:0] + attribute \src "libresoc.v:87718.3-87778.6" + wire width 3 $0\dec31_cr_in[2:0] + attribute \src "libresoc.v:87779.3-87839.6" + wire width 3 $0\dec31_cr_out[2:0] + attribute \src "libresoc.v:88389.3-88449.6" + wire width 2 $0\dec31_cry_in[1:0] + attribute \src "libresoc.v:88572.3-88632.6" + wire $0\dec31_cry_out[0:0] + attribute \src "libresoc.v:87230.3-87290.6" + wire width 5 $0\dec31_form[4:0] + attribute \src "libresoc.v:87108.3-87168.6" + wire width 13 $0\dec31_function_unit[12:0] + attribute \src "libresoc.v:87474.3-87534.6" + wire width 3 $0\dec31_in1_sel[2:0] + attribute \src "libresoc.v:87535.3-87595.6" + wire width 4 $0\dec31_in2_sel[3:0] + attribute \src "libresoc.v:87596.3-87656.6" + wire width 2 $0\dec31_in3_sel[1:0] + attribute \src "libresoc.v:87169.3-87229.6" + wire width 7 $0\dec31_internal_op[6:0] + attribute \src "libresoc.v:88450.3-88510.6" + wire $0\dec31_inv_a[0:0] + attribute \src "libresoc.v:88511.3-88571.6" + wire $0\dec31_inv_out[0:0] + attribute \src "libresoc.v:88816.3-88876.6" + wire $0\dec31_is_32b[0:0] + attribute \src "libresoc.v:88206.3-88266.6" + wire width 4 $0\dec31_ldst_len[3:0] + attribute \src "libresoc.v:88938.3-88998.6" + wire $0\dec31_lk[0:0] + attribute \src "libresoc.v:87657.3-87717.6" + wire width 2 $0\dec31_out_sel[1:0] + attribute \src "libresoc.v:88328.3-88388.6" + wire width 2 $0\dec31_rc_sel[1:0] + attribute \src "libresoc.v:88755.3-88815.6" + wire $0\dec31_rsrv[0:0] + attribute \src "libresoc.v:88999.3-89059.6" + wire $0\dec31_sgl_pipe[0:0] + attribute \src "libresoc.v:88877.3-88937.6" + wire $0\dec31_sgn[0:0] + attribute \src "libresoc.v:88694.3-88754.6" + wire $0\dec31_sgn_ext[0:0] + attribute \src "libresoc.v:88084.3-88144.6" + wire width 3 $0\dec31_sv_cr_in[2:0] + attribute \src "libresoc.v:88145.3-88205.6" + wire width 3 $0\dec31_sv_cr_out[2:0] + attribute \src "libresoc.v:87840.3-87900.6" + wire width 3 $0\dec31_sv_in1[2:0] + attribute \src "libresoc.v:87901.3-87961.6" + wire width 3 $0\dec31_sv_in2[2:0] + attribute \src "libresoc.v:87962.3-88022.6" + wire width 3 $0\dec31_sv_in3[2:0] + attribute \src "libresoc.v:88023.3-88083.6" + wire width 3 $0\dec31_sv_out[2:0] + attribute \src "libresoc.v:88267.3-88327.6" + wire width 2 $0\dec31_upd[1:0] + attribute \src "libresoc.v:80760.7-80760.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:87352.3-87412.6" + wire width 2 $1\dec31_SV_Etype[1:0] + attribute \src "libresoc.v:87413.3-87473.6" + wire width 2 $1\dec31_SV_Ptype[1:0] + attribute \src "libresoc.v:87291.3-87351.6" + wire width 8 $1\dec31_asmcode[7:0] + attribute \src "libresoc.v:88633.3-88693.6" + wire $1\dec31_br[0:0] + attribute \src "libresoc.v:87718.3-87778.6" + wire width 3 $1\dec31_cr_in[2:0] + attribute \src "libresoc.v:87779.3-87839.6" + wire width 3 $1\dec31_cr_out[2:0] + attribute \src "libresoc.v:88389.3-88449.6" + wire width 2 $1\dec31_cry_in[1:0] + attribute \src "libresoc.v:88572.3-88632.6" + wire $1\dec31_cry_out[0:0] + attribute \src "libresoc.v:87230.3-87290.6" + wire width 5 $1\dec31_form[4:0] + attribute \src "libresoc.v:87108.3-87168.6" + wire width 13 $1\dec31_function_unit[12:0] + attribute \src "libresoc.v:87474.3-87534.6" + wire width 3 $1\dec31_in1_sel[2:0] + attribute \src "libresoc.v:87535.3-87595.6" + wire width 4 $1\dec31_in2_sel[3:0] + attribute \src "libresoc.v:87596.3-87656.6" + wire width 2 $1\dec31_in3_sel[1:0] + attribute \src "libresoc.v:87169.3-87229.6" + wire width 7 $1\dec31_internal_op[6:0] + attribute \src "libresoc.v:88450.3-88510.6" + wire $1\dec31_inv_a[0:0] + attribute \src "libresoc.v:88511.3-88571.6" + wire $1\dec31_inv_out[0:0] + attribute \src "libresoc.v:88816.3-88876.6" + wire $1\dec31_is_32b[0:0] + attribute \src "libresoc.v:88206.3-88266.6" + wire width 4 $1\dec31_ldst_len[3:0] + attribute \src "libresoc.v:88938.3-88998.6" + wire $1\dec31_lk[0:0] + attribute \src "libresoc.v:87657.3-87717.6" + wire width 2 $1\dec31_out_sel[1:0] + attribute \src "libresoc.v:88328.3-88388.6" + wire width 2 $1\dec31_rc_sel[1:0] + attribute \src "libresoc.v:88755.3-88815.6" + wire $1\dec31_rsrv[0:0] + attribute \src "libresoc.v:88999.3-89059.6" + wire $1\dec31_sgl_pipe[0:0] + attribute \src "libresoc.v:88877.3-88937.6" + wire $1\dec31_sgn[0:0] + attribute \src "libresoc.v:88694.3-88754.6" + wire $1\dec31_sgn_ext[0:0] + attribute \src "libresoc.v:88084.3-88144.6" + wire width 3 $1\dec31_sv_cr_in[2:0] + attribute \src "libresoc.v:88145.3-88205.6" + wire width 3 $1\dec31_sv_cr_out[2:0] + attribute \src "libresoc.v:87840.3-87900.6" + wire width 3 $1\dec31_sv_in1[2:0] + attribute \src "libresoc.v:87901.3-87961.6" + wire width 3 $1\dec31_sv_in2[2:0] + attribute \src "libresoc.v:87962.3-88022.6" + wire width 3 $1\dec31_sv_in3[2:0] + attribute \src "libresoc.v:88023.3-88083.6" + wire width 3 $1\dec31_sv_out[2:0] + attribute \src "libresoc.v:88267.3-88327.6" + wire width 2 $1\dec31_upd[1:0] + attribute \enum_base_type "SVEtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "EXTRA2" + attribute \enum_value_10 "EXTRA3" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 5 \dec31_SV_Etype + attribute \enum_base_type "SVPtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "P1" + attribute \enum_value_10 "P2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 6 \dec31_SV_Ptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 8 output 4 \dec31_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 26 \dec31_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 11 \dec31_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 12 \dec31_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 22 \dec31_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 25 \dec31_cry_out + attribute \enum_base_type "SVEtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "EXTRA2" + attribute \enum_value_10 "EXTRA3" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \dec31_dec_sub0_dec31_dec_sub0_SV_Etype + attribute \enum_base_type "SVPtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "P1" + attribute \enum_value_10 "P2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \dec31_dec_sub0_dec31_dec_sub0_SV_Ptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 8 \dec31_dec_sub0_dec31_dec_sub0_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \dec31_dec_sub0_dec31_dec_sub0_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec31_dec_sub0_dec31_dec_sub0_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec31_dec_sub0_dec31_dec_sub0_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \dec31_dec_sub0_dec31_dec_sub0_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \dec31_dec_sub0_dec31_dec_sub0_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute 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+ attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec31_dec_sub9_dec31_dec_sub9_sv_cr_in + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec31_dec_sub9_dec31_dec_sub9_sv_cr_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec31_dec_sub9_dec31_dec_sub9_sv_in1 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec31_dec_sub9_dec31_dec_sub9_sv_in2 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec31_dec_sub9_dec31_dec_sub9_sv_in3 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec31_dec_sub9_dec31_dec_sub9_sv_out + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \dec31_dec_sub9_dec31_dec_sub9_upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + wire width 32 \dec31_dec_sub9_opcode_in + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 5 output 3 \dec31_form + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 13 output 1 \dec31_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 7 \dec31_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 8 \dec31_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 9 \dec31_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 output 2 \dec31_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 23 \dec31_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 24 \dec31_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 29 \dec31_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 19 \dec31_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 31 \dec31_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 10 \dec31_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 21 \dec31_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 28 \dec31_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 32 \dec31_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 30 \dec31_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 27 \dec31_sgn_ext + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 17 \dec31_sv_cr_in + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 18 \dec31_sv_cr_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 13 \dec31_sv_in1 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 14 \dec31_sv_in2 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 15 \dec31_sv_in3 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 16 \dec31_sv_out + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 20 \dec31_upd + attribute \src "libresoc.v:80760.7-80760.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:347" + wire width 5 \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + wire width 32 input 33 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + wire width 10 \opcode_switch + attribute \module_not_derived 1 + attribute \src "libresoc.v:86478.18-86512.4" + cell \dec31_dec_sub0 \dec31_dec_sub0 + connect \dec31_dec_sub0_SV_Etype \dec31_dec_sub0_dec31_dec_sub0_SV_Etype + connect \dec31_dec_sub0_SV_Ptype \dec31_dec_sub0_dec31_dec_sub0_SV_Ptype + connect \dec31_dec_sub0_asmcode \dec31_dec_sub0_dec31_dec_sub0_asmcode + connect \dec31_dec_sub0_br \dec31_dec_sub0_dec31_dec_sub0_br + connect \dec31_dec_sub0_cr_in \dec31_dec_sub0_dec31_dec_sub0_cr_in + connect \dec31_dec_sub0_cr_out \dec31_dec_sub0_dec31_dec_sub0_cr_out + connect \dec31_dec_sub0_cry_in \dec31_dec_sub0_dec31_dec_sub0_cry_in + connect \dec31_dec_sub0_cry_out \dec31_dec_sub0_dec31_dec_sub0_cry_out + connect \dec31_dec_sub0_form \dec31_dec_sub0_dec31_dec_sub0_form + connect \dec31_dec_sub0_function_unit \dec31_dec_sub0_dec31_dec_sub0_function_unit + connect \dec31_dec_sub0_in1_sel \dec31_dec_sub0_dec31_dec_sub0_in1_sel + connect \dec31_dec_sub0_in2_sel \dec31_dec_sub0_dec31_dec_sub0_in2_sel + connect \dec31_dec_sub0_in3_sel \dec31_dec_sub0_dec31_dec_sub0_in3_sel + connect \dec31_dec_sub0_internal_op \dec31_dec_sub0_dec31_dec_sub0_internal_op + connect \dec31_dec_sub0_inv_a \dec31_dec_sub0_dec31_dec_sub0_inv_a + connect \dec31_dec_sub0_inv_out \dec31_dec_sub0_dec31_dec_sub0_inv_out + connect \dec31_dec_sub0_is_32b \dec31_dec_sub0_dec31_dec_sub0_is_32b + connect \dec31_dec_sub0_ldst_len \dec31_dec_sub0_dec31_dec_sub0_ldst_len + connect \dec31_dec_sub0_lk \dec31_dec_sub0_dec31_dec_sub0_lk + connect \dec31_dec_sub0_out_sel \dec31_dec_sub0_dec31_dec_sub0_out_sel + connect \dec31_dec_sub0_rc_sel \dec31_dec_sub0_dec31_dec_sub0_rc_sel + connect \dec31_dec_sub0_rsrv \dec31_dec_sub0_dec31_dec_sub0_rsrv + connect \dec31_dec_sub0_sgl_pipe \dec31_dec_sub0_dec31_dec_sub0_sgl_pipe + connect \dec31_dec_sub0_sgn \dec31_dec_sub0_dec31_dec_sub0_sgn + connect \dec31_dec_sub0_sgn_ext \dec31_dec_sub0_dec31_dec_sub0_sgn_ext + connect \dec31_dec_sub0_sv_cr_in \dec31_dec_sub0_dec31_dec_sub0_sv_cr_in + connect \dec31_dec_sub0_sv_cr_out \dec31_dec_sub0_dec31_dec_sub0_sv_cr_out + connect \dec31_dec_sub0_sv_in1 \dec31_dec_sub0_dec31_dec_sub0_sv_in1 + connect \dec31_dec_sub0_sv_in2 \dec31_dec_sub0_dec31_dec_sub0_sv_in2 + connect \dec31_dec_sub0_sv_in3 \dec31_dec_sub0_dec31_dec_sub0_sv_in3 + connect \dec31_dec_sub0_sv_out \dec31_dec_sub0_dec31_dec_sub0_sv_out + connect \dec31_dec_sub0_upd \dec31_dec_sub0_dec31_dec_sub0_upd + connect \opcode_in \dec31_dec_sub0_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:86513.19-86547.4" + cell \dec31_dec_sub10 \dec31_dec_sub10 + connect \dec31_dec_sub10_SV_Etype \dec31_dec_sub10_dec31_dec_sub10_SV_Etype + connect \dec31_dec_sub10_SV_Ptype \dec31_dec_sub10_dec31_dec_sub10_SV_Ptype + connect \dec31_dec_sub10_asmcode \dec31_dec_sub10_dec31_dec_sub10_asmcode + connect \dec31_dec_sub10_br \dec31_dec_sub10_dec31_dec_sub10_br + connect \dec31_dec_sub10_cr_in \dec31_dec_sub10_dec31_dec_sub10_cr_in + connect \dec31_dec_sub10_cr_out \dec31_dec_sub10_dec31_dec_sub10_cr_out + connect \dec31_dec_sub10_cry_in \dec31_dec_sub10_dec31_dec_sub10_cry_in + connect \dec31_dec_sub10_cry_out \dec31_dec_sub10_dec31_dec_sub10_cry_out + connect \dec31_dec_sub10_form \dec31_dec_sub10_dec31_dec_sub10_form + connect \dec31_dec_sub10_function_unit \dec31_dec_sub10_dec31_dec_sub10_function_unit + connect \dec31_dec_sub10_in1_sel \dec31_dec_sub10_dec31_dec_sub10_in1_sel + connect \dec31_dec_sub10_in2_sel \dec31_dec_sub10_dec31_dec_sub10_in2_sel + connect \dec31_dec_sub10_in3_sel \dec31_dec_sub10_dec31_dec_sub10_in3_sel + connect \dec31_dec_sub10_internal_op \dec31_dec_sub10_dec31_dec_sub10_internal_op + connect \dec31_dec_sub10_inv_a \dec31_dec_sub10_dec31_dec_sub10_inv_a + connect \dec31_dec_sub10_inv_out \dec31_dec_sub10_dec31_dec_sub10_inv_out + connect \dec31_dec_sub10_is_32b \dec31_dec_sub10_dec31_dec_sub10_is_32b + connect \dec31_dec_sub10_ldst_len \dec31_dec_sub10_dec31_dec_sub10_ldst_len + connect \dec31_dec_sub10_lk \dec31_dec_sub10_dec31_dec_sub10_lk + connect \dec31_dec_sub10_out_sel \dec31_dec_sub10_dec31_dec_sub10_out_sel + connect \dec31_dec_sub10_rc_sel \dec31_dec_sub10_dec31_dec_sub10_rc_sel + connect \dec31_dec_sub10_rsrv \dec31_dec_sub10_dec31_dec_sub10_rsrv + connect \dec31_dec_sub10_sgl_pipe \dec31_dec_sub10_dec31_dec_sub10_sgl_pipe + connect \dec31_dec_sub10_sgn \dec31_dec_sub10_dec31_dec_sub10_sgn + connect \dec31_dec_sub10_sgn_ext \dec31_dec_sub10_dec31_dec_sub10_sgn_ext + connect \dec31_dec_sub10_sv_cr_in \dec31_dec_sub10_dec31_dec_sub10_sv_cr_in + connect \dec31_dec_sub10_sv_cr_out \dec31_dec_sub10_dec31_dec_sub10_sv_cr_out + connect \dec31_dec_sub10_sv_in1 \dec31_dec_sub10_dec31_dec_sub10_sv_in1 + connect \dec31_dec_sub10_sv_in2 \dec31_dec_sub10_dec31_dec_sub10_sv_in2 + connect \dec31_dec_sub10_sv_in3 \dec31_dec_sub10_dec31_dec_sub10_sv_in3 + connect \dec31_dec_sub10_sv_out \dec31_dec_sub10_dec31_dec_sub10_sv_out + connect \dec31_dec_sub10_upd \dec31_dec_sub10_dec31_dec_sub10_upd + connect \opcode_in \dec31_dec_sub10_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:86548.19-86582.4" + cell \dec31_dec_sub11 \dec31_dec_sub11 + connect \dec31_dec_sub11_SV_Etype \dec31_dec_sub11_dec31_dec_sub11_SV_Etype + connect \dec31_dec_sub11_SV_Ptype \dec31_dec_sub11_dec31_dec_sub11_SV_Ptype + connect \dec31_dec_sub11_asmcode \dec31_dec_sub11_dec31_dec_sub11_asmcode + connect \dec31_dec_sub11_br \dec31_dec_sub11_dec31_dec_sub11_br + connect \dec31_dec_sub11_cr_in \dec31_dec_sub11_dec31_dec_sub11_cr_in + connect \dec31_dec_sub11_cr_out \dec31_dec_sub11_dec31_dec_sub11_cr_out + connect \dec31_dec_sub11_cry_in \dec31_dec_sub11_dec31_dec_sub11_cry_in + connect \dec31_dec_sub11_cry_out \dec31_dec_sub11_dec31_dec_sub11_cry_out + connect \dec31_dec_sub11_form \dec31_dec_sub11_dec31_dec_sub11_form + connect \dec31_dec_sub11_function_unit \dec31_dec_sub11_dec31_dec_sub11_function_unit + connect \dec31_dec_sub11_in1_sel \dec31_dec_sub11_dec31_dec_sub11_in1_sel + connect \dec31_dec_sub11_in2_sel \dec31_dec_sub11_dec31_dec_sub11_in2_sel + connect \dec31_dec_sub11_in3_sel \dec31_dec_sub11_dec31_dec_sub11_in3_sel + connect \dec31_dec_sub11_internal_op \dec31_dec_sub11_dec31_dec_sub11_internal_op + connect \dec31_dec_sub11_inv_a \dec31_dec_sub11_dec31_dec_sub11_inv_a + connect \dec31_dec_sub11_inv_out \dec31_dec_sub11_dec31_dec_sub11_inv_out + connect \dec31_dec_sub11_is_32b \dec31_dec_sub11_dec31_dec_sub11_is_32b + connect \dec31_dec_sub11_ldst_len \dec31_dec_sub11_dec31_dec_sub11_ldst_len + connect \dec31_dec_sub11_lk \dec31_dec_sub11_dec31_dec_sub11_lk + connect \dec31_dec_sub11_out_sel \dec31_dec_sub11_dec31_dec_sub11_out_sel + connect \dec31_dec_sub11_rc_sel \dec31_dec_sub11_dec31_dec_sub11_rc_sel + connect \dec31_dec_sub11_rsrv \dec31_dec_sub11_dec31_dec_sub11_rsrv + connect \dec31_dec_sub11_sgl_pipe \dec31_dec_sub11_dec31_dec_sub11_sgl_pipe + connect \dec31_dec_sub11_sgn \dec31_dec_sub11_dec31_dec_sub11_sgn + connect \dec31_dec_sub11_sgn_ext \dec31_dec_sub11_dec31_dec_sub11_sgn_ext + connect \dec31_dec_sub11_sv_cr_in \dec31_dec_sub11_dec31_dec_sub11_sv_cr_in + connect \dec31_dec_sub11_sv_cr_out \dec31_dec_sub11_dec31_dec_sub11_sv_cr_out + connect \dec31_dec_sub11_sv_in1 \dec31_dec_sub11_dec31_dec_sub11_sv_in1 + connect \dec31_dec_sub11_sv_in2 \dec31_dec_sub11_dec31_dec_sub11_sv_in2 + connect \dec31_dec_sub11_sv_in3 \dec31_dec_sub11_dec31_dec_sub11_sv_in3 + connect \dec31_dec_sub11_sv_out \dec31_dec_sub11_dec31_dec_sub11_sv_out + connect \dec31_dec_sub11_upd \dec31_dec_sub11_dec31_dec_sub11_upd + connect \opcode_in \dec31_dec_sub11_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:86583.19-86617.4" + cell \dec31_dec_sub15 \dec31_dec_sub15 + connect \dec31_dec_sub15_SV_Etype \dec31_dec_sub15_dec31_dec_sub15_SV_Etype + connect \dec31_dec_sub15_SV_Ptype \dec31_dec_sub15_dec31_dec_sub15_SV_Ptype + connect \dec31_dec_sub15_asmcode \dec31_dec_sub15_dec31_dec_sub15_asmcode + connect \dec31_dec_sub15_br \dec31_dec_sub15_dec31_dec_sub15_br + connect \dec31_dec_sub15_cr_in \dec31_dec_sub15_dec31_dec_sub15_cr_in + connect \dec31_dec_sub15_cr_out \dec31_dec_sub15_dec31_dec_sub15_cr_out + connect \dec31_dec_sub15_cry_in \dec31_dec_sub15_dec31_dec_sub15_cry_in + connect \dec31_dec_sub15_cry_out \dec31_dec_sub15_dec31_dec_sub15_cry_out + connect \dec31_dec_sub15_form \dec31_dec_sub15_dec31_dec_sub15_form + connect \dec31_dec_sub15_function_unit \dec31_dec_sub15_dec31_dec_sub15_function_unit + connect \dec31_dec_sub15_in1_sel \dec31_dec_sub15_dec31_dec_sub15_in1_sel + connect \dec31_dec_sub15_in2_sel \dec31_dec_sub15_dec31_dec_sub15_in2_sel + connect \dec31_dec_sub15_in3_sel \dec31_dec_sub15_dec31_dec_sub15_in3_sel + connect \dec31_dec_sub15_internal_op \dec31_dec_sub15_dec31_dec_sub15_internal_op + connect \dec31_dec_sub15_inv_a \dec31_dec_sub15_dec31_dec_sub15_inv_a + connect \dec31_dec_sub15_inv_out \dec31_dec_sub15_dec31_dec_sub15_inv_out + connect \dec31_dec_sub15_is_32b \dec31_dec_sub15_dec31_dec_sub15_is_32b + connect \dec31_dec_sub15_ldst_len \dec31_dec_sub15_dec31_dec_sub15_ldst_len + connect \dec31_dec_sub15_lk \dec31_dec_sub15_dec31_dec_sub15_lk + connect \dec31_dec_sub15_out_sel \dec31_dec_sub15_dec31_dec_sub15_out_sel + connect \dec31_dec_sub15_rc_sel \dec31_dec_sub15_dec31_dec_sub15_rc_sel + connect \dec31_dec_sub15_rsrv \dec31_dec_sub15_dec31_dec_sub15_rsrv + connect \dec31_dec_sub15_sgl_pipe \dec31_dec_sub15_dec31_dec_sub15_sgl_pipe + connect \dec31_dec_sub15_sgn \dec31_dec_sub15_dec31_dec_sub15_sgn + connect \dec31_dec_sub15_sgn_ext \dec31_dec_sub15_dec31_dec_sub15_sgn_ext + connect \dec31_dec_sub15_sv_cr_in \dec31_dec_sub15_dec31_dec_sub15_sv_cr_in + connect \dec31_dec_sub15_sv_cr_out \dec31_dec_sub15_dec31_dec_sub15_sv_cr_out + connect \dec31_dec_sub15_sv_in1 \dec31_dec_sub15_dec31_dec_sub15_sv_in1 + connect \dec31_dec_sub15_sv_in2 \dec31_dec_sub15_dec31_dec_sub15_sv_in2 + connect \dec31_dec_sub15_sv_in3 \dec31_dec_sub15_dec31_dec_sub15_sv_in3 + connect \dec31_dec_sub15_sv_out \dec31_dec_sub15_dec31_dec_sub15_sv_out + connect \dec31_dec_sub15_upd \dec31_dec_sub15_dec31_dec_sub15_upd + connect \opcode_in \dec31_dec_sub15_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:86618.19-86652.4" + cell \dec31_dec_sub16 \dec31_dec_sub16 + connect \dec31_dec_sub16_SV_Etype \dec31_dec_sub16_dec31_dec_sub16_SV_Etype + connect \dec31_dec_sub16_SV_Ptype \dec31_dec_sub16_dec31_dec_sub16_SV_Ptype + connect \dec31_dec_sub16_asmcode \dec31_dec_sub16_dec31_dec_sub16_asmcode + connect \dec31_dec_sub16_br \dec31_dec_sub16_dec31_dec_sub16_br + connect \dec31_dec_sub16_cr_in \dec31_dec_sub16_dec31_dec_sub16_cr_in + connect \dec31_dec_sub16_cr_out \dec31_dec_sub16_dec31_dec_sub16_cr_out + connect \dec31_dec_sub16_cry_in \dec31_dec_sub16_dec31_dec_sub16_cry_in + connect \dec31_dec_sub16_cry_out \dec31_dec_sub16_dec31_dec_sub16_cry_out + connect \dec31_dec_sub16_form \dec31_dec_sub16_dec31_dec_sub16_form + connect \dec31_dec_sub16_function_unit \dec31_dec_sub16_dec31_dec_sub16_function_unit + connect \dec31_dec_sub16_in1_sel \dec31_dec_sub16_dec31_dec_sub16_in1_sel + connect \dec31_dec_sub16_in2_sel \dec31_dec_sub16_dec31_dec_sub16_in2_sel + connect \dec31_dec_sub16_in3_sel \dec31_dec_sub16_dec31_dec_sub16_in3_sel + connect \dec31_dec_sub16_internal_op \dec31_dec_sub16_dec31_dec_sub16_internal_op + connect \dec31_dec_sub16_inv_a \dec31_dec_sub16_dec31_dec_sub16_inv_a + connect \dec31_dec_sub16_inv_out \dec31_dec_sub16_dec31_dec_sub16_inv_out + connect \dec31_dec_sub16_is_32b \dec31_dec_sub16_dec31_dec_sub16_is_32b + connect \dec31_dec_sub16_ldst_len \dec31_dec_sub16_dec31_dec_sub16_ldst_len + connect \dec31_dec_sub16_lk \dec31_dec_sub16_dec31_dec_sub16_lk + connect \dec31_dec_sub16_out_sel \dec31_dec_sub16_dec31_dec_sub16_out_sel + connect \dec31_dec_sub16_rc_sel \dec31_dec_sub16_dec31_dec_sub16_rc_sel + connect \dec31_dec_sub16_rsrv \dec31_dec_sub16_dec31_dec_sub16_rsrv + connect \dec31_dec_sub16_sgl_pipe \dec31_dec_sub16_dec31_dec_sub16_sgl_pipe + connect \dec31_dec_sub16_sgn \dec31_dec_sub16_dec31_dec_sub16_sgn + connect \dec31_dec_sub16_sgn_ext \dec31_dec_sub16_dec31_dec_sub16_sgn_ext + connect \dec31_dec_sub16_sv_cr_in \dec31_dec_sub16_dec31_dec_sub16_sv_cr_in + connect \dec31_dec_sub16_sv_cr_out \dec31_dec_sub16_dec31_dec_sub16_sv_cr_out + connect \dec31_dec_sub16_sv_in1 \dec31_dec_sub16_dec31_dec_sub16_sv_in1 + connect \dec31_dec_sub16_sv_in2 \dec31_dec_sub16_dec31_dec_sub16_sv_in2 + connect \dec31_dec_sub16_sv_in3 \dec31_dec_sub16_dec31_dec_sub16_sv_in3 + connect \dec31_dec_sub16_sv_out \dec31_dec_sub16_dec31_dec_sub16_sv_out + connect \dec31_dec_sub16_upd \dec31_dec_sub16_dec31_dec_sub16_upd + connect \opcode_in \dec31_dec_sub16_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:86653.19-86687.4" + cell \dec31_dec_sub18 \dec31_dec_sub18 + connect \dec31_dec_sub18_SV_Etype \dec31_dec_sub18_dec31_dec_sub18_SV_Etype + connect \dec31_dec_sub18_SV_Ptype \dec31_dec_sub18_dec31_dec_sub18_SV_Ptype + connect \dec31_dec_sub18_asmcode \dec31_dec_sub18_dec31_dec_sub18_asmcode + connect \dec31_dec_sub18_br \dec31_dec_sub18_dec31_dec_sub18_br + connect \dec31_dec_sub18_cr_in \dec31_dec_sub18_dec31_dec_sub18_cr_in + connect \dec31_dec_sub18_cr_out \dec31_dec_sub18_dec31_dec_sub18_cr_out + connect \dec31_dec_sub18_cry_in \dec31_dec_sub18_dec31_dec_sub18_cry_in + connect \dec31_dec_sub18_cry_out \dec31_dec_sub18_dec31_dec_sub18_cry_out + connect \dec31_dec_sub18_form \dec31_dec_sub18_dec31_dec_sub18_form + connect \dec31_dec_sub18_function_unit \dec31_dec_sub18_dec31_dec_sub18_function_unit + connect \dec31_dec_sub18_in1_sel \dec31_dec_sub18_dec31_dec_sub18_in1_sel + connect \dec31_dec_sub18_in2_sel \dec31_dec_sub18_dec31_dec_sub18_in2_sel + connect \dec31_dec_sub18_in3_sel \dec31_dec_sub18_dec31_dec_sub18_in3_sel + connect \dec31_dec_sub18_internal_op \dec31_dec_sub18_dec31_dec_sub18_internal_op + connect \dec31_dec_sub18_inv_a \dec31_dec_sub18_dec31_dec_sub18_inv_a + connect \dec31_dec_sub18_inv_out \dec31_dec_sub18_dec31_dec_sub18_inv_out + connect \dec31_dec_sub18_is_32b \dec31_dec_sub18_dec31_dec_sub18_is_32b + connect \dec31_dec_sub18_ldst_len \dec31_dec_sub18_dec31_dec_sub18_ldst_len + connect \dec31_dec_sub18_lk \dec31_dec_sub18_dec31_dec_sub18_lk + connect \dec31_dec_sub18_out_sel \dec31_dec_sub18_dec31_dec_sub18_out_sel + connect \dec31_dec_sub18_rc_sel \dec31_dec_sub18_dec31_dec_sub18_rc_sel + connect \dec31_dec_sub18_rsrv \dec31_dec_sub18_dec31_dec_sub18_rsrv + connect \dec31_dec_sub18_sgl_pipe \dec31_dec_sub18_dec31_dec_sub18_sgl_pipe + connect \dec31_dec_sub18_sgn \dec31_dec_sub18_dec31_dec_sub18_sgn + connect \dec31_dec_sub18_sgn_ext \dec31_dec_sub18_dec31_dec_sub18_sgn_ext + connect \dec31_dec_sub18_sv_cr_in \dec31_dec_sub18_dec31_dec_sub18_sv_cr_in + connect \dec31_dec_sub18_sv_cr_out \dec31_dec_sub18_dec31_dec_sub18_sv_cr_out + connect \dec31_dec_sub18_sv_in1 \dec31_dec_sub18_dec31_dec_sub18_sv_in1 + connect \dec31_dec_sub18_sv_in2 \dec31_dec_sub18_dec31_dec_sub18_sv_in2 + connect \dec31_dec_sub18_sv_in3 \dec31_dec_sub18_dec31_dec_sub18_sv_in3 + connect \dec31_dec_sub18_sv_out \dec31_dec_sub18_dec31_dec_sub18_sv_out + connect \dec31_dec_sub18_upd \dec31_dec_sub18_dec31_dec_sub18_upd + connect \opcode_in \dec31_dec_sub18_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:86688.19-86722.4" + cell \dec31_dec_sub19 \dec31_dec_sub19 + connect \dec31_dec_sub19_SV_Etype \dec31_dec_sub19_dec31_dec_sub19_SV_Etype + connect \dec31_dec_sub19_SV_Ptype \dec31_dec_sub19_dec31_dec_sub19_SV_Ptype + connect \dec31_dec_sub19_asmcode \dec31_dec_sub19_dec31_dec_sub19_asmcode + connect \dec31_dec_sub19_br \dec31_dec_sub19_dec31_dec_sub19_br + connect \dec31_dec_sub19_cr_in \dec31_dec_sub19_dec31_dec_sub19_cr_in + connect \dec31_dec_sub19_cr_out \dec31_dec_sub19_dec31_dec_sub19_cr_out + connect \dec31_dec_sub19_cry_in \dec31_dec_sub19_dec31_dec_sub19_cry_in + connect \dec31_dec_sub19_cry_out \dec31_dec_sub19_dec31_dec_sub19_cry_out + connect \dec31_dec_sub19_form \dec31_dec_sub19_dec31_dec_sub19_form + connect \dec31_dec_sub19_function_unit \dec31_dec_sub19_dec31_dec_sub19_function_unit + connect \dec31_dec_sub19_in1_sel \dec31_dec_sub19_dec31_dec_sub19_in1_sel + connect \dec31_dec_sub19_in2_sel \dec31_dec_sub19_dec31_dec_sub19_in2_sel + connect \dec31_dec_sub19_in3_sel \dec31_dec_sub19_dec31_dec_sub19_in3_sel + connect \dec31_dec_sub19_internal_op \dec31_dec_sub19_dec31_dec_sub19_internal_op + connect \dec31_dec_sub19_inv_a \dec31_dec_sub19_dec31_dec_sub19_inv_a + connect \dec31_dec_sub19_inv_out \dec31_dec_sub19_dec31_dec_sub19_inv_out + connect \dec31_dec_sub19_is_32b \dec31_dec_sub19_dec31_dec_sub19_is_32b + connect \dec31_dec_sub19_ldst_len \dec31_dec_sub19_dec31_dec_sub19_ldst_len + connect \dec31_dec_sub19_lk \dec31_dec_sub19_dec31_dec_sub19_lk + connect \dec31_dec_sub19_out_sel \dec31_dec_sub19_dec31_dec_sub19_out_sel + connect \dec31_dec_sub19_rc_sel \dec31_dec_sub19_dec31_dec_sub19_rc_sel + connect \dec31_dec_sub19_rsrv \dec31_dec_sub19_dec31_dec_sub19_rsrv + connect \dec31_dec_sub19_sgl_pipe \dec31_dec_sub19_dec31_dec_sub19_sgl_pipe + connect \dec31_dec_sub19_sgn \dec31_dec_sub19_dec31_dec_sub19_sgn + connect \dec31_dec_sub19_sgn_ext \dec31_dec_sub19_dec31_dec_sub19_sgn_ext + connect \dec31_dec_sub19_sv_cr_in \dec31_dec_sub19_dec31_dec_sub19_sv_cr_in + connect \dec31_dec_sub19_sv_cr_out \dec31_dec_sub19_dec31_dec_sub19_sv_cr_out + connect \dec31_dec_sub19_sv_in1 \dec31_dec_sub19_dec31_dec_sub19_sv_in1 + connect \dec31_dec_sub19_sv_in2 \dec31_dec_sub19_dec31_dec_sub19_sv_in2 + connect \dec31_dec_sub19_sv_in3 \dec31_dec_sub19_dec31_dec_sub19_sv_in3 + connect \dec31_dec_sub19_sv_out \dec31_dec_sub19_dec31_dec_sub19_sv_out + connect \dec31_dec_sub19_upd \dec31_dec_sub19_dec31_dec_sub19_upd + connect \opcode_in \dec31_dec_sub19_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:86723.19-86757.4" + cell \dec31_dec_sub20 \dec31_dec_sub20 + connect \dec31_dec_sub20_SV_Etype \dec31_dec_sub20_dec31_dec_sub20_SV_Etype + connect \dec31_dec_sub20_SV_Ptype \dec31_dec_sub20_dec31_dec_sub20_SV_Ptype + connect \dec31_dec_sub20_asmcode \dec31_dec_sub20_dec31_dec_sub20_asmcode + connect \dec31_dec_sub20_br \dec31_dec_sub20_dec31_dec_sub20_br + connect \dec31_dec_sub20_cr_in \dec31_dec_sub20_dec31_dec_sub20_cr_in + connect \dec31_dec_sub20_cr_out \dec31_dec_sub20_dec31_dec_sub20_cr_out + connect \dec31_dec_sub20_cry_in \dec31_dec_sub20_dec31_dec_sub20_cry_in + connect \dec31_dec_sub20_cry_out \dec31_dec_sub20_dec31_dec_sub20_cry_out + connect \dec31_dec_sub20_form \dec31_dec_sub20_dec31_dec_sub20_form + connect \dec31_dec_sub20_function_unit \dec31_dec_sub20_dec31_dec_sub20_function_unit + connect \dec31_dec_sub20_in1_sel \dec31_dec_sub20_dec31_dec_sub20_in1_sel + connect \dec31_dec_sub20_in2_sel \dec31_dec_sub20_dec31_dec_sub20_in2_sel + connect \dec31_dec_sub20_in3_sel \dec31_dec_sub20_dec31_dec_sub20_in3_sel + connect \dec31_dec_sub20_internal_op \dec31_dec_sub20_dec31_dec_sub20_internal_op + connect \dec31_dec_sub20_inv_a \dec31_dec_sub20_dec31_dec_sub20_inv_a + connect \dec31_dec_sub20_inv_out \dec31_dec_sub20_dec31_dec_sub20_inv_out + connect \dec31_dec_sub20_is_32b \dec31_dec_sub20_dec31_dec_sub20_is_32b + connect \dec31_dec_sub20_ldst_len \dec31_dec_sub20_dec31_dec_sub20_ldst_len + connect \dec31_dec_sub20_lk \dec31_dec_sub20_dec31_dec_sub20_lk + connect \dec31_dec_sub20_out_sel \dec31_dec_sub20_dec31_dec_sub20_out_sel + connect \dec31_dec_sub20_rc_sel \dec31_dec_sub20_dec31_dec_sub20_rc_sel + connect \dec31_dec_sub20_rsrv \dec31_dec_sub20_dec31_dec_sub20_rsrv + connect \dec31_dec_sub20_sgl_pipe \dec31_dec_sub20_dec31_dec_sub20_sgl_pipe + connect \dec31_dec_sub20_sgn \dec31_dec_sub20_dec31_dec_sub20_sgn + connect \dec31_dec_sub20_sgn_ext \dec31_dec_sub20_dec31_dec_sub20_sgn_ext + connect \dec31_dec_sub20_sv_cr_in \dec31_dec_sub20_dec31_dec_sub20_sv_cr_in + connect \dec31_dec_sub20_sv_cr_out \dec31_dec_sub20_dec31_dec_sub20_sv_cr_out + connect \dec31_dec_sub20_sv_in1 \dec31_dec_sub20_dec31_dec_sub20_sv_in1 + connect \dec31_dec_sub20_sv_in2 \dec31_dec_sub20_dec31_dec_sub20_sv_in2 + connect \dec31_dec_sub20_sv_in3 \dec31_dec_sub20_dec31_dec_sub20_sv_in3 + connect \dec31_dec_sub20_sv_out \dec31_dec_sub20_dec31_dec_sub20_sv_out + connect \dec31_dec_sub20_upd \dec31_dec_sub20_dec31_dec_sub20_upd + connect \opcode_in \dec31_dec_sub20_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:86758.19-86792.4" + cell \dec31_dec_sub21 \dec31_dec_sub21 + connect \dec31_dec_sub21_SV_Etype \dec31_dec_sub21_dec31_dec_sub21_SV_Etype + connect \dec31_dec_sub21_SV_Ptype \dec31_dec_sub21_dec31_dec_sub21_SV_Ptype + connect \dec31_dec_sub21_asmcode \dec31_dec_sub21_dec31_dec_sub21_asmcode + connect \dec31_dec_sub21_br \dec31_dec_sub21_dec31_dec_sub21_br + connect \dec31_dec_sub21_cr_in \dec31_dec_sub21_dec31_dec_sub21_cr_in + connect \dec31_dec_sub21_cr_out \dec31_dec_sub21_dec31_dec_sub21_cr_out + connect \dec31_dec_sub21_cry_in \dec31_dec_sub21_dec31_dec_sub21_cry_in + connect \dec31_dec_sub21_cry_out \dec31_dec_sub21_dec31_dec_sub21_cry_out + connect \dec31_dec_sub21_form \dec31_dec_sub21_dec31_dec_sub21_form + connect \dec31_dec_sub21_function_unit \dec31_dec_sub21_dec31_dec_sub21_function_unit + connect \dec31_dec_sub21_in1_sel \dec31_dec_sub21_dec31_dec_sub21_in1_sel + connect \dec31_dec_sub21_in2_sel \dec31_dec_sub21_dec31_dec_sub21_in2_sel + connect \dec31_dec_sub21_in3_sel \dec31_dec_sub21_dec31_dec_sub21_in3_sel + connect \dec31_dec_sub21_internal_op \dec31_dec_sub21_dec31_dec_sub21_internal_op + connect \dec31_dec_sub21_inv_a \dec31_dec_sub21_dec31_dec_sub21_inv_a + connect \dec31_dec_sub21_inv_out \dec31_dec_sub21_dec31_dec_sub21_inv_out + connect \dec31_dec_sub21_is_32b \dec31_dec_sub21_dec31_dec_sub21_is_32b + connect \dec31_dec_sub21_ldst_len \dec31_dec_sub21_dec31_dec_sub21_ldst_len + connect \dec31_dec_sub21_lk \dec31_dec_sub21_dec31_dec_sub21_lk + connect \dec31_dec_sub21_out_sel \dec31_dec_sub21_dec31_dec_sub21_out_sel + connect \dec31_dec_sub21_rc_sel \dec31_dec_sub21_dec31_dec_sub21_rc_sel + connect \dec31_dec_sub21_rsrv \dec31_dec_sub21_dec31_dec_sub21_rsrv + connect \dec31_dec_sub21_sgl_pipe \dec31_dec_sub21_dec31_dec_sub21_sgl_pipe + connect \dec31_dec_sub21_sgn \dec31_dec_sub21_dec31_dec_sub21_sgn + connect \dec31_dec_sub21_sgn_ext \dec31_dec_sub21_dec31_dec_sub21_sgn_ext + connect \dec31_dec_sub21_sv_cr_in \dec31_dec_sub21_dec31_dec_sub21_sv_cr_in + connect \dec31_dec_sub21_sv_cr_out \dec31_dec_sub21_dec31_dec_sub21_sv_cr_out + connect \dec31_dec_sub21_sv_in1 \dec31_dec_sub21_dec31_dec_sub21_sv_in1 + connect \dec31_dec_sub21_sv_in2 \dec31_dec_sub21_dec31_dec_sub21_sv_in2 + connect \dec31_dec_sub21_sv_in3 \dec31_dec_sub21_dec31_dec_sub21_sv_in3 + connect \dec31_dec_sub21_sv_out \dec31_dec_sub21_dec31_dec_sub21_sv_out + connect \dec31_dec_sub21_upd \dec31_dec_sub21_dec31_dec_sub21_upd + connect \opcode_in \dec31_dec_sub21_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:86793.19-86827.4" + cell \dec31_dec_sub22 \dec31_dec_sub22 + connect \dec31_dec_sub22_SV_Etype \dec31_dec_sub22_dec31_dec_sub22_SV_Etype + connect \dec31_dec_sub22_SV_Ptype \dec31_dec_sub22_dec31_dec_sub22_SV_Ptype + connect \dec31_dec_sub22_asmcode \dec31_dec_sub22_dec31_dec_sub22_asmcode + connect \dec31_dec_sub22_br \dec31_dec_sub22_dec31_dec_sub22_br + connect \dec31_dec_sub22_cr_in \dec31_dec_sub22_dec31_dec_sub22_cr_in + connect \dec31_dec_sub22_cr_out \dec31_dec_sub22_dec31_dec_sub22_cr_out + connect \dec31_dec_sub22_cry_in \dec31_dec_sub22_dec31_dec_sub22_cry_in + connect \dec31_dec_sub22_cry_out \dec31_dec_sub22_dec31_dec_sub22_cry_out + connect \dec31_dec_sub22_form \dec31_dec_sub22_dec31_dec_sub22_form + connect \dec31_dec_sub22_function_unit \dec31_dec_sub22_dec31_dec_sub22_function_unit + connect \dec31_dec_sub22_in1_sel \dec31_dec_sub22_dec31_dec_sub22_in1_sel + connect \dec31_dec_sub22_in2_sel \dec31_dec_sub22_dec31_dec_sub22_in2_sel + connect \dec31_dec_sub22_in3_sel \dec31_dec_sub22_dec31_dec_sub22_in3_sel + connect \dec31_dec_sub22_internal_op \dec31_dec_sub22_dec31_dec_sub22_internal_op + connect \dec31_dec_sub22_inv_a \dec31_dec_sub22_dec31_dec_sub22_inv_a + connect \dec31_dec_sub22_inv_out \dec31_dec_sub22_dec31_dec_sub22_inv_out + connect \dec31_dec_sub22_is_32b \dec31_dec_sub22_dec31_dec_sub22_is_32b + connect \dec31_dec_sub22_ldst_len \dec31_dec_sub22_dec31_dec_sub22_ldst_len + connect \dec31_dec_sub22_lk \dec31_dec_sub22_dec31_dec_sub22_lk + connect \dec31_dec_sub22_out_sel \dec31_dec_sub22_dec31_dec_sub22_out_sel + connect \dec31_dec_sub22_rc_sel \dec31_dec_sub22_dec31_dec_sub22_rc_sel + connect \dec31_dec_sub22_rsrv \dec31_dec_sub22_dec31_dec_sub22_rsrv + connect \dec31_dec_sub22_sgl_pipe \dec31_dec_sub22_dec31_dec_sub22_sgl_pipe + connect \dec31_dec_sub22_sgn \dec31_dec_sub22_dec31_dec_sub22_sgn + connect \dec31_dec_sub22_sgn_ext \dec31_dec_sub22_dec31_dec_sub22_sgn_ext + connect \dec31_dec_sub22_sv_cr_in \dec31_dec_sub22_dec31_dec_sub22_sv_cr_in + connect \dec31_dec_sub22_sv_cr_out \dec31_dec_sub22_dec31_dec_sub22_sv_cr_out + connect \dec31_dec_sub22_sv_in1 \dec31_dec_sub22_dec31_dec_sub22_sv_in1 + connect \dec31_dec_sub22_sv_in2 \dec31_dec_sub22_dec31_dec_sub22_sv_in2 + connect \dec31_dec_sub22_sv_in3 \dec31_dec_sub22_dec31_dec_sub22_sv_in3 + connect \dec31_dec_sub22_sv_out \dec31_dec_sub22_dec31_dec_sub22_sv_out + connect \dec31_dec_sub22_upd \dec31_dec_sub22_dec31_dec_sub22_upd + connect \opcode_in \dec31_dec_sub22_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:86828.19-86862.4" + cell \dec31_dec_sub23 \dec31_dec_sub23 + connect \dec31_dec_sub23_SV_Etype \dec31_dec_sub23_dec31_dec_sub23_SV_Etype + connect \dec31_dec_sub23_SV_Ptype \dec31_dec_sub23_dec31_dec_sub23_SV_Ptype + connect \dec31_dec_sub23_asmcode \dec31_dec_sub23_dec31_dec_sub23_asmcode + connect \dec31_dec_sub23_br \dec31_dec_sub23_dec31_dec_sub23_br + connect \dec31_dec_sub23_cr_in \dec31_dec_sub23_dec31_dec_sub23_cr_in + connect \dec31_dec_sub23_cr_out \dec31_dec_sub23_dec31_dec_sub23_cr_out + connect \dec31_dec_sub23_cry_in \dec31_dec_sub23_dec31_dec_sub23_cry_in + connect \dec31_dec_sub23_cry_out \dec31_dec_sub23_dec31_dec_sub23_cry_out + connect \dec31_dec_sub23_form \dec31_dec_sub23_dec31_dec_sub23_form + connect \dec31_dec_sub23_function_unit \dec31_dec_sub23_dec31_dec_sub23_function_unit + connect \dec31_dec_sub23_in1_sel \dec31_dec_sub23_dec31_dec_sub23_in1_sel + connect \dec31_dec_sub23_in2_sel \dec31_dec_sub23_dec31_dec_sub23_in2_sel + connect \dec31_dec_sub23_in3_sel \dec31_dec_sub23_dec31_dec_sub23_in3_sel + connect \dec31_dec_sub23_internal_op \dec31_dec_sub23_dec31_dec_sub23_internal_op + connect \dec31_dec_sub23_inv_a \dec31_dec_sub23_dec31_dec_sub23_inv_a + connect \dec31_dec_sub23_inv_out \dec31_dec_sub23_dec31_dec_sub23_inv_out + connect \dec31_dec_sub23_is_32b \dec31_dec_sub23_dec31_dec_sub23_is_32b + connect \dec31_dec_sub23_ldst_len \dec31_dec_sub23_dec31_dec_sub23_ldst_len + connect \dec31_dec_sub23_lk \dec31_dec_sub23_dec31_dec_sub23_lk + connect \dec31_dec_sub23_out_sel \dec31_dec_sub23_dec31_dec_sub23_out_sel + connect \dec31_dec_sub23_rc_sel \dec31_dec_sub23_dec31_dec_sub23_rc_sel + connect \dec31_dec_sub23_rsrv \dec31_dec_sub23_dec31_dec_sub23_rsrv + connect \dec31_dec_sub23_sgl_pipe \dec31_dec_sub23_dec31_dec_sub23_sgl_pipe + connect \dec31_dec_sub23_sgn \dec31_dec_sub23_dec31_dec_sub23_sgn + connect \dec31_dec_sub23_sgn_ext \dec31_dec_sub23_dec31_dec_sub23_sgn_ext + connect \dec31_dec_sub23_sv_cr_in \dec31_dec_sub23_dec31_dec_sub23_sv_cr_in + connect \dec31_dec_sub23_sv_cr_out \dec31_dec_sub23_dec31_dec_sub23_sv_cr_out + connect \dec31_dec_sub23_sv_in1 \dec31_dec_sub23_dec31_dec_sub23_sv_in1 + connect \dec31_dec_sub23_sv_in2 \dec31_dec_sub23_dec31_dec_sub23_sv_in2 + connect \dec31_dec_sub23_sv_in3 \dec31_dec_sub23_dec31_dec_sub23_sv_in3 + connect \dec31_dec_sub23_sv_out \dec31_dec_sub23_dec31_dec_sub23_sv_out + connect \dec31_dec_sub23_upd \dec31_dec_sub23_dec31_dec_sub23_upd + connect \opcode_in \dec31_dec_sub23_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:86863.19-86897.4" + cell \dec31_dec_sub24 \dec31_dec_sub24 + connect \dec31_dec_sub24_SV_Etype \dec31_dec_sub24_dec31_dec_sub24_SV_Etype + connect \dec31_dec_sub24_SV_Ptype \dec31_dec_sub24_dec31_dec_sub24_SV_Ptype + connect \dec31_dec_sub24_asmcode \dec31_dec_sub24_dec31_dec_sub24_asmcode + connect \dec31_dec_sub24_br \dec31_dec_sub24_dec31_dec_sub24_br + connect \dec31_dec_sub24_cr_in \dec31_dec_sub24_dec31_dec_sub24_cr_in + connect \dec31_dec_sub24_cr_out \dec31_dec_sub24_dec31_dec_sub24_cr_out + connect \dec31_dec_sub24_cry_in \dec31_dec_sub24_dec31_dec_sub24_cry_in + connect \dec31_dec_sub24_cry_out \dec31_dec_sub24_dec31_dec_sub24_cry_out + connect \dec31_dec_sub24_form \dec31_dec_sub24_dec31_dec_sub24_form + connect \dec31_dec_sub24_function_unit \dec31_dec_sub24_dec31_dec_sub24_function_unit + connect \dec31_dec_sub24_in1_sel \dec31_dec_sub24_dec31_dec_sub24_in1_sel + connect \dec31_dec_sub24_in2_sel \dec31_dec_sub24_dec31_dec_sub24_in2_sel + connect \dec31_dec_sub24_in3_sel \dec31_dec_sub24_dec31_dec_sub24_in3_sel + connect \dec31_dec_sub24_internal_op \dec31_dec_sub24_dec31_dec_sub24_internal_op + connect \dec31_dec_sub24_inv_a \dec31_dec_sub24_dec31_dec_sub24_inv_a + connect \dec31_dec_sub24_inv_out \dec31_dec_sub24_dec31_dec_sub24_inv_out + connect \dec31_dec_sub24_is_32b \dec31_dec_sub24_dec31_dec_sub24_is_32b + connect \dec31_dec_sub24_ldst_len \dec31_dec_sub24_dec31_dec_sub24_ldst_len + connect \dec31_dec_sub24_lk \dec31_dec_sub24_dec31_dec_sub24_lk + connect \dec31_dec_sub24_out_sel \dec31_dec_sub24_dec31_dec_sub24_out_sel + connect \dec31_dec_sub24_rc_sel \dec31_dec_sub24_dec31_dec_sub24_rc_sel + connect \dec31_dec_sub24_rsrv \dec31_dec_sub24_dec31_dec_sub24_rsrv + connect \dec31_dec_sub24_sgl_pipe \dec31_dec_sub24_dec31_dec_sub24_sgl_pipe + connect \dec31_dec_sub24_sgn \dec31_dec_sub24_dec31_dec_sub24_sgn + connect \dec31_dec_sub24_sgn_ext \dec31_dec_sub24_dec31_dec_sub24_sgn_ext + connect \dec31_dec_sub24_sv_cr_in \dec31_dec_sub24_dec31_dec_sub24_sv_cr_in + connect \dec31_dec_sub24_sv_cr_out \dec31_dec_sub24_dec31_dec_sub24_sv_cr_out + connect \dec31_dec_sub24_sv_in1 \dec31_dec_sub24_dec31_dec_sub24_sv_in1 + connect \dec31_dec_sub24_sv_in2 \dec31_dec_sub24_dec31_dec_sub24_sv_in2 + connect \dec31_dec_sub24_sv_in3 \dec31_dec_sub24_dec31_dec_sub24_sv_in3 + connect \dec31_dec_sub24_sv_out \dec31_dec_sub24_dec31_dec_sub24_sv_out + connect \dec31_dec_sub24_upd \dec31_dec_sub24_dec31_dec_sub24_upd + connect \opcode_in \dec31_dec_sub24_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:86898.19-86932.4" + cell \dec31_dec_sub26 \dec31_dec_sub26 + connect \dec31_dec_sub26_SV_Etype \dec31_dec_sub26_dec31_dec_sub26_SV_Etype + connect \dec31_dec_sub26_SV_Ptype \dec31_dec_sub26_dec31_dec_sub26_SV_Ptype + connect \dec31_dec_sub26_asmcode \dec31_dec_sub26_dec31_dec_sub26_asmcode + connect \dec31_dec_sub26_br \dec31_dec_sub26_dec31_dec_sub26_br + connect \dec31_dec_sub26_cr_in \dec31_dec_sub26_dec31_dec_sub26_cr_in + connect \dec31_dec_sub26_cr_out \dec31_dec_sub26_dec31_dec_sub26_cr_out + connect \dec31_dec_sub26_cry_in \dec31_dec_sub26_dec31_dec_sub26_cry_in + connect \dec31_dec_sub26_cry_out \dec31_dec_sub26_dec31_dec_sub26_cry_out + connect \dec31_dec_sub26_form \dec31_dec_sub26_dec31_dec_sub26_form + connect \dec31_dec_sub26_function_unit \dec31_dec_sub26_dec31_dec_sub26_function_unit + connect \dec31_dec_sub26_in1_sel \dec31_dec_sub26_dec31_dec_sub26_in1_sel + connect \dec31_dec_sub26_in2_sel \dec31_dec_sub26_dec31_dec_sub26_in2_sel + connect \dec31_dec_sub26_in3_sel \dec31_dec_sub26_dec31_dec_sub26_in3_sel + connect \dec31_dec_sub26_internal_op \dec31_dec_sub26_dec31_dec_sub26_internal_op + connect \dec31_dec_sub26_inv_a \dec31_dec_sub26_dec31_dec_sub26_inv_a + connect \dec31_dec_sub26_inv_out \dec31_dec_sub26_dec31_dec_sub26_inv_out + connect \dec31_dec_sub26_is_32b \dec31_dec_sub26_dec31_dec_sub26_is_32b + connect \dec31_dec_sub26_ldst_len \dec31_dec_sub26_dec31_dec_sub26_ldst_len + connect \dec31_dec_sub26_lk \dec31_dec_sub26_dec31_dec_sub26_lk + connect \dec31_dec_sub26_out_sel \dec31_dec_sub26_dec31_dec_sub26_out_sel + connect \dec31_dec_sub26_rc_sel \dec31_dec_sub26_dec31_dec_sub26_rc_sel + connect \dec31_dec_sub26_rsrv \dec31_dec_sub26_dec31_dec_sub26_rsrv + connect \dec31_dec_sub26_sgl_pipe \dec31_dec_sub26_dec31_dec_sub26_sgl_pipe + connect \dec31_dec_sub26_sgn \dec31_dec_sub26_dec31_dec_sub26_sgn + connect \dec31_dec_sub26_sgn_ext \dec31_dec_sub26_dec31_dec_sub26_sgn_ext + connect \dec31_dec_sub26_sv_cr_in \dec31_dec_sub26_dec31_dec_sub26_sv_cr_in + connect \dec31_dec_sub26_sv_cr_out \dec31_dec_sub26_dec31_dec_sub26_sv_cr_out + connect \dec31_dec_sub26_sv_in1 \dec31_dec_sub26_dec31_dec_sub26_sv_in1 + connect \dec31_dec_sub26_sv_in2 \dec31_dec_sub26_dec31_dec_sub26_sv_in2 + connect \dec31_dec_sub26_sv_in3 \dec31_dec_sub26_dec31_dec_sub26_sv_in3 + connect \dec31_dec_sub26_sv_out \dec31_dec_sub26_dec31_dec_sub26_sv_out + connect \dec31_dec_sub26_upd \dec31_dec_sub26_dec31_dec_sub26_upd + connect \opcode_in \dec31_dec_sub26_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:86933.19-86967.4" + cell \dec31_dec_sub27 \dec31_dec_sub27 + connect \dec31_dec_sub27_SV_Etype \dec31_dec_sub27_dec31_dec_sub27_SV_Etype + connect \dec31_dec_sub27_SV_Ptype \dec31_dec_sub27_dec31_dec_sub27_SV_Ptype + connect \dec31_dec_sub27_asmcode \dec31_dec_sub27_dec31_dec_sub27_asmcode + connect \dec31_dec_sub27_br \dec31_dec_sub27_dec31_dec_sub27_br + connect \dec31_dec_sub27_cr_in \dec31_dec_sub27_dec31_dec_sub27_cr_in + connect \dec31_dec_sub27_cr_out \dec31_dec_sub27_dec31_dec_sub27_cr_out + connect \dec31_dec_sub27_cry_in \dec31_dec_sub27_dec31_dec_sub27_cry_in + connect \dec31_dec_sub27_cry_out \dec31_dec_sub27_dec31_dec_sub27_cry_out + connect \dec31_dec_sub27_form \dec31_dec_sub27_dec31_dec_sub27_form + connect \dec31_dec_sub27_function_unit \dec31_dec_sub27_dec31_dec_sub27_function_unit + connect \dec31_dec_sub27_in1_sel \dec31_dec_sub27_dec31_dec_sub27_in1_sel + connect \dec31_dec_sub27_in2_sel \dec31_dec_sub27_dec31_dec_sub27_in2_sel + connect \dec31_dec_sub27_in3_sel \dec31_dec_sub27_dec31_dec_sub27_in3_sel + connect \dec31_dec_sub27_internal_op \dec31_dec_sub27_dec31_dec_sub27_internal_op + connect \dec31_dec_sub27_inv_a \dec31_dec_sub27_dec31_dec_sub27_inv_a + connect \dec31_dec_sub27_inv_out \dec31_dec_sub27_dec31_dec_sub27_inv_out + connect \dec31_dec_sub27_is_32b \dec31_dec_sub27_dec31_dec_sub27_is_32b + connect \dec31_dec_sub27_ldst_len \dec31_dec_sub27_dec31_dec_sub27_ldst_len + connect \dec31_dec_sub27_lk \dec31_dec_sub27_dec31_dec_sub27_lk + connect \dec31_dec_sub27_out_sel \dec31_dec_sub27_dec31_dec_sub27_out_sel + connect \dec31_dec_sub27_rc_sel \dec31_dec_sub27_dec31_dec_sub27_rc_sel + connect \dec31_dec_sub27_rsrv \dec31_dec_sub27_dec31_dec_sub27_rsrv + connect \dec31_dec_sub27_sgl_pipe \dec31_dec_sub27_dec31_dec_sub27_sgl_pipe + connect \dec31_dec_sub27_sgn \dec31_dec_sub27_dec31_dec_sub27_sgn + connect \dec31_dec_sub27_sgn_ext \dec31_dec_sub27_dec31_dec_sub27_sgn_ext + connect \dec31_dec_sub27_sv_cr_in \dec31_dec_sub27_dec31_dec_sub27_sv_cr_in + connect \dec31_dec_sub27_sv_cr_out \dec31_dec_sub27_dec31_dec_sub27_sv_cr_out + connect \dec31_dec_sub27_sv_in1 \dec31_dec_sub27_dec31_dec_sub27_sv_in1 + connect \dec31_dec_sub27_sv_in2 \dec31_dec_sub27_dec31_dec_sub27_sv_in2 + connect \dec31_dec_sub27_sv_in3 \dec31_dec_sub27_dec31_dec_sub27_sv_in3 + connect \dec31_dec_sub27_sv_out \dec31_dec_sub27_dec31_dec_sub27_sv_out + connect \dec31_dec_sub27_upd \dec31_dec_sub27_dec31_dec_sub27_upd + connect \opcode_in \dec31_dec_sub27_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:86968.19-87002.4" + cell \dec31_dec_sub28 \dec31_dec_sub28 + connect \dec31_dec_sub28_SV_Etype \dec31_dec_sub28_dec31_dec_sub28_SV_Etype + connect \dec31_dec_sub28_SV_Ptype \dec31_dec_sub28_dec31_dec_sub28_SV_Ptype + connect \dec31_dec_sub28_asmcode \dec31_dec_sub28_dec31_dec_sub28_asmcode + connect \dec31_dec_sub28_br \dec31_dec_sub28_dec31_dec_sub28_br + connect \dec31_dec_sub28_cr_in \dec31_dec_sub28_dec31_dec_sub28_cr_in + connect \dec31_dec_sub28_cr_out \dec31_dec_sub28_dec31_dec_sub28_cr_out + connect \dec31_dec_sub28_cry_in \dec31_dec_sub28_dec31_dec_sub28_cry_in + connect \dec31_dec_sub28_cry_out \dec31_dec_sub28_dec31_dec_sub28_cry_out + connect \dec31_dec_sub28_form \dec31_dec_sub28_dec31_dec_sub28_form + connect \dec31_dec_sub28_function_unit \dec31_dec_sub28_dec31_dec_sub28_function_unit + connect \dec31_dec_sub28_in1_sel \dec31_dec_sub28_dec31_dec_sub28_in1_sel + connect \dec31_dec_sub28_in2_sel \dec31_dec_sub28_dec31_dec_sub28_in2_sel + connect \dec31_dec_sub28_in3_sel \dec31_dec_sub28_dec31_dec_sub28_in3_sel + connect \dec31_dec_sub28_internal_op \dec31_dec_sub28_dec31_dec_sub28_internal_op + connect \dec31_dec_sub28_inv_a \dec31_dec_sub28_dec31_dec_sub28_inv_a + connect \dec31_dec_sub28_inv_out \dec31_dec_sub28_dec31_dec_sub28_inv_out + connect \dec31_dec_sub28_is_32b \dec31_dec_sub28_dec31_dec_sub28_is_32b + connect \dec31_dec_sub28_ldst_len \dec31_dec_sub28_dec31_dec_sub28_ldst_len + connect \dec31_dec_sub28_lk \dec31_dec_sub28_dec31_dec_sub28_lk + connect \dec31_dec_sub28_out_sel \dec31_dec_sub28_dec31_dec_sub28_out_sel + connect \dec31_dec_sub28_rc_sel \dec31_dec_sub28_dec31_dec_sub28_rc_sel + connect \dec31_dec_sub28_rsrv \dec31_dec_sub28_dec31_dec_sub28_rsrv + connect \dec31_dec_sub28_sgl_pipe \dec31_dec_sub28_dec31_dec_sub28_sgl_pipe + connect \dec31_dec_sub28_sgn \dec31_dec_sub28_dec31_dec_sub28_sgn + connect \dec31_dec_sub28_sgn_ext \dec31_dec_sub28_dec31_dec_sub28_sgn_ext + connect \dec31_dec_sub28_sv_cr_in \dec31_dec_sub28_dec31_dec_sub28_sv_cr_in + connect \dec31_dec_sub28_sv_cr_out \dec31_dec_sub28_dec31_dec_sub28_sv_cr_out + connect \dec31_dec_sub28_sv_in1 \dec31_dec_sub28_dec31_dec_sub28_sv_in1 + connect \dec31_dec_sub28_sv_in2 \dec31_dec_sub28_dec31_dec_sub28_sv_in2 + connect \dec31_dec_sub28_sv_in3 \dec31_dec_sub28_dec31_dec_sub28_sv_in3 + connect \dec31_dec_sub28_sv_out \dec31_dec_sub28_dec31_dec_sub28_sv_out + connect \dec31_dec_sub28_upd \dec31_dec_sub28_dec31_dec_sub28_upd + connect \opcode_in \dec31_dec_sub28_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:87003.18-87037.4" + cell \dec31_dec_sub4 \dec31_dec_sub4 + connect \dec31_dec_sub4_SV_Etype \dec31_dec_sub4_dec31_dec_sub4_SV_Etype + connect \dec31_dec_sub4_SV_Ptype \dec31_dec_sub4_dec31_dec_sub4_SV_Ptype + connect \dec31_dec_sub4_asmcode \dec31_dec_sub4_dec31_dec_sub4_asmcode + connect \dec31_dec_sub4_br \dec31_dec_sub4_dec31_dec_sub4_br + connect \dec31_dec_sub4_cr_in \dec31_dec_sub4_dec31_dec_sub4_cr_in + connect \dec31_dec_sub4_cr_out \dec31_dec_sub4_dec31_dec_sub4_cr_out + connect \dec31_dec_sub4_cry_in \dec31_dec_sub4_dec31_dec_sub4_cry_in + connect \dec31_dec_sub4_cry_out \dec31_dec_sub4_dec31_dec_sub4_cry_out + connect \dec31_dec_sub4_form \dec31_dec_sub4_dec31_dec_sub4_form + connect \dec31_dec_sub4_function_unit \dec31_dec_sub4_dec31_dec_sub4_function_unit + connect \dec31_dec_sub4_in1_sel \dec31_dec_sub4_dec31_dec_sub4_in1_sel + connect \dec31_dec_sub4_in2_sel \dec31_dec_sub4_dec31_dec_sub4_in2_sel + connect \dec31_dec_sub4_in3_sel \dec31_dec_sub4_dec31_dec_sub4_in3_sel + connect \dec31_dec_sub4_internal_op \dec31_dec_sub4_dec31_dec_sub4_internal_op + connect \dec31_dec_sub4_inv_a \dec31_dec_sub4_dec31_dec_sub4_inv_a + connect \dec31_dec_sub4_inv_out \dec31_dec_sub4_dec31_dec_sub4_inv_out + connect \dec31_dec_sub4_is_32b \dec31_dec_sub4_dec31_dec_sub4_is_32b + connect \dec31_dec_sub4_ldst_len \dec31_dec_sub4_dec31_dec_sub4_ldst_len + connect \dec31_dec_sub4_lk \dec31_dec_sub4_dec31_dec_sub4_lk + connect \dec31_dec_sub4_out_sel \dec31_dec_sub4_dec31_dec_sub4_out_sel + connect \dec31_dec_sub4_rc_sel \dec31_dec_sub4_dec31_dec_sub4_rc_sel + connect \dec31_dec_sub4_rsrv \dec31_dec_sub4_dec31_dec_sub4_rsrv + connect \dec31_dec_sub4_sgl_pipe \dec31_dec_sub4_dec31_dec_sub4_sgl_pipe + connect \dec31_dec_sub4_sgn \dec31_dec_sub4_dec31_dec_sub4_sgn + connect \dec31_dec_sub4_sgn_ext \dec31_dec_sub4_dec31_dec_sub4_sgn_ext + connect \dec31_dec_sub4_sv_cr_in \dec31_dec_sub4_dec31_dec_sub4_sv_cr_in + connect \dec31_dec_sub4_sv_cr_out \dec31_dec_sub4_dec31_dec_sub4_sv_cr_out + connect \dec31_dec_sub4_sv_in1 \dec31_dec_sub4_dec31_dec_sub4_sv_in1 + connect \dec31_dec_sub4_sv_in2 \dec31_dec_sub4_dec31_dec_sub4_sv_in2 + connect \dec31_dec_sub4_sv_in3 \dec31_dec_sub4_dec31_dec_sub4_sv_in3 + connect \dec31_dec_sub4_sv_out \dec31_dec_sub4_dec31_dec_sub4_sv_out + connect \dec31_dec_sub4_upd \dec31_dec_sub4_dec31_dec_sub4_upd + connect \opcode_in \dec31_dec_sub4_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:87038.18-87072.4" + cell \dec31_dec_sub8 \dec31_dec_sub8 + connect \dec31_dec_sub8_SV_Etype \dec31_dec_sub8_dec31_dec_sub8_SV_Etype + connect \dec31_dec_sub8_SV_Ptype \dec31_dec_sub8_dec31_dec_sub8_SV_Ptype + connect \dec31_dec_sub8_asmcode \dec31_dec_sub8_dec31_dec_sub8_asmcode + connect \dec31_dec_sub8_br \dec31_dec_sub8_dec31_dec_sub8_br + connect \dec31_dec_sub8_cr_in \dec31_dec_sub8_dec31_dec_sub8_cr_in + connect \dec31_dec_sub8_cr_out \dec31_dec_sub8_dec31_dec_sub8_cr_out + connect \dec31_dec_sub8_cry_in \dec31_dec_sub8_dec31_dec_sub8_cry_in + connect \dec31_dec_sub8_cry_out \dec31_dec_sub8_dec31_dec_sub8_cry_out + connect \dec31_dec_sub8_form \dec31_dec_sub8_dec31_dec_sub8_form + connect \dec31_dec_sub8_function_unit \dec31_dec_sub8_dec31_dec_sub8_function_unit + connect \dec31_dec_sub8_in1_sel \dec31_dec_sub8_dec31_dec_sub8_in1_sel + connect \dec31_dec_sub8_in2_sel \dec31_dec_sub8_dec31_dec_sub8_in2_sel + connect \dec31_dec_sub8_in3_sel \dec31_dec_sub8_dec31_dec_sub8_in3_sel + connect \dec31_dec_sub8_internal_op \dec31_dec_sub8_dec31_dec_sub8_internal_op + connect \dec31_dec_sub8_inv_a \dec31_dec_sub8_dec31_dec_sub8_inv_a + connect \dec31_dec_sub8_inv_out \dec31_dec_sub8_dec31_dec_sub8_inv_out + connect \dec31_dec_sub8_is_32b \dec31_dec_sub8_dec31_dec_sub8_is_32b + connect \dec31_dec_sub8_ldst_len \dec31_dec_sub8_dec31_dec_sub8_ldst_len + connect \dec31_dec_sub8_lk \dec31_dec_sub8_dec31_dec_sub8_lk + connect \dec31_dec_sub8_out_sel \dec31_dec_sub8_dec31_dec_sub8_out_sel + connect \dec31_dec_sub8_rc_sel \dec31_dec_sub8_dec31_dec_sub8_rc_sel + connect \dec31_dec_sub8_rsrv \dec31_dec_sub8_dec31_dec_sub8_rsrv + connect \dec31_dec_sub8_sgl_pipe \dec31_dec_sub8_dec31_dec_sub8_sgl_pipe + connect \dec31_dec_sub8_sgn \dec31_dec_sub8_dec31_dec_sub8_sgn + connect \dec31_dec_sub8_sgn_ext \dec31_dec_sub8_dec31_dec_sub8_sgn_ext + connect \dec31_dec_sub8_sv_cr_in \dec31_dec_sub8_dec31_dec_sub8_sv_cr_in + connect \dec31_dec_sub8_sv_cr_out \dec31_dec_sub8_dec31_dec_sub8_sv_cr_out + connect \dec31_dec_sub8_sv_in1 \dec31_dec_sub8_dec31_dec_sub8_sv_in1 + connect \dec31_dec_sub8_sv_in2 \dec31_dec_sub8_dec31_dec_sub8_sv_in2 + connect \dec31_dec_sub8_sv_in3 \dec31_dec_sub8_dec31_dec_sub8_sv_in3 + connect \dec31_dec_sub8_sv_out \dec31_dec_sub8_dec31_dec_sub8_sv_out + connect \dec31_dec_sub8_upd \dec31_dec_sub8_dec31_dec_sub8_upd + connect \opcode_in \dec31_dec_sub8_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:87073.18-87107.4" + cell \dec31_dec_sub9 \dec31_dec_sub9 + connect \dec31_dec_sub9_SV_Etype \dec31_dec_sub9_dec31_dec_sub9_SV_Etype + connect \dec31_dec_sub9_SV_Ptype \dec31_dec_sub9_dec31_dec_sub9_SV_Ptype + connect \dec31_dec_sub9_asmcode \dec31_dec_sub9_dec31_dec_sub9_asmcode + connect \dec31_dec_sub9_br \dec31_dec_sub9_dec31_dec_sub9_br + connect \dec31_dec_sub9_cr_in \dec31_dec_sub9_dec31_dec_sub9_cr_in + connect \dec31_dec_sub9_cr_out \dec31_dec_sub9_dec31_dec_sub9_cr_out + connect \dec31_dec_sub9_cry_in \dec31_dec_sub9_dec31_dec_sub9_cry_in + connect \dec31_dec_sub9_cry_out \dec31_dec_sub9_dec31_dec_sub9_cry_out + connect \dec31_dec_sub9_form \dec31_dec_sub9_dec31_dec_sub9_form + connect \dec31_dec_sub9_function_unit \dec31_dec_sub9_dec31_dec_sub9_function_unit + connect \dec31_dec_sub9_in1_sel \dec31_dec_sub9_dec31_dec_sub9_in1_sel + connect \dec31_dec_sub9_in2_sel \dec31_dec_sub9_dec31_dec_sub9_in2_sel + connect \dec31_dec_sub9_in3_sel \dec31_dec_sub9_dec31_dec_sub9_in3_sel + connect \dec31_dec_sub9_internal_op \dec31_dec_sub9_dec31_dec_sub9_internal_op + connect \dec31_dec_sub9_inv_a \dec31_dec_sub9_dec31_dec_sub9_inv_a + connect \dec31_dec_sub9_inv_out \dec31_dec_sub9_dec31_dec_sub9_inv_out + connect \dec31_dec_sub9_is_32b \dec31_dec_sub9_dec31_dec_sub9_is_32b + connect \dec31_dec_sub9_ldst_len \dec31_dec_sub9_dec31_dec_sub9_ldst_len + connect \dec31_dec_sub9_lk \dec31_dec_sub9_dec31_dec_sub9_lk + connect \dec31_dec_sub9_out_sel \dec31_dec_sub9_dec31_dec_sub9_out_sel + connect \dec31_dec_sub9_rc_sel \dec31_dec_sub9_dec31_dec_sub9_rc_sel + connect \dec31_dec_sub9_rsrv \dec31_dec_sub9_dec31_dec_sub9_rsrv + connect \dec31_dec_sub9_sgl_pipe \dec31_dec_sub9_dec31_dec_sub9_sgl_pipe + connect \dec31_dec_sub9_sgn \dec31_dec_sub9_dec31_dec_sub9_sgn + connect \dec31_dec_sub9_sgn_ext \dec31_dec_sub9_dec31_dec_sub9_sgn_ext + connect \dec31_dec_sub9_sv_cr_in \dec31_dec_sub9_dec31_dec_sub9_sv_cr_in + connect \dec31_dec_sub9_sv_cr_out \dec31_dec_sub9_dec31_dec_sub9_sv_cr_out + connect \dec31_dec_sub9_sv_in1 \dec31_dec_sub9_dec31_dec_sub9_sv_in1 + connect \dec31_dec_sub9_sv_in2 \dec31_dec_sub9_dec31_dec_sub9_sv_in2 + connect \dec31_dec_sub9_sv_in3 \dec31_dec_sub9_dec31_dec_sub9_sv_in3 + connect \dec31_dec_sub9_sv_out \dec31_dec_sub9_dec31_dec_sub9_sv_out + connect \dec31_dec_sub9_upd \dec31_dec_sub9_dec31_dec_sub9_upd + connect \opcode_in \dec31_dec_sub9_opcode_in + end + attribute \src "libresoc.v:80760.7-80760.20" + process $proc$libresoc.v:80760$3798 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:87108.3-87168.6" + process $proc$libresoc.v:87108$3766 + assign { } { } + assign { } { } + assign $0\dec31_function_unit[12:0] $1\dec31_function_unit[12:0] + attribute \src "libresoc.v:87109.5-87109.29" + switch \initial + attribute \src "libresoc.v:87109.9-87109.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_function_unit[12:0] \dec31_dec_sub10_dec31_dec_sub10_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_function_unit[12:0] \dec31_dec_sub28_dec31_dec_sub28_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_function_unit[12:0] \dec31_dec_sub0_dec31_dec_sub0_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_function_unit[12:0] \dec31_dec_sub26_dec31_dec_sub26_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_function_unit[12:0] \dec31_dec_sub19_dec31_dec_sub19_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_function_unit[12:0] \dec31_dec_sub22_dec31_dec_sub22_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_function_unit[12:0] \dec31_dec_sub9_dec31_dec_sub9_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_function_unit[12:0] \dec31_dec_sub11_dec31_dec_sub11_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_function_unit[12:0] \dec31_dec_sub27_dec31_dec_sub27_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_function_unit[12:0] \dec31_dec_sub15_dec31_dec_sub15_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_function_unit[12:0] \dec31_dec_sub20_dec31_dec_sub20_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_function_unit[12:0] \dec31_dec_sub21_dec31_dec_sub21_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_function_unit[12:0] \dec31_dec_sub23_dec31_dec_sub23_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_function_unit[12:0] \dec31_dec_sub16_dec31_dec_sub16_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_function_unit[12:0] \dec31_dec_sub18_dec31_dec_sub18_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_function_unit[12:0] \dec31_dec_sub8_dec31_dec_sub8_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_function_unit[12:0] \dec31_dec_sub24_dec31_dec_sub24_function_unit + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_function_unit[12:0] \dec31_dec_sub4_dec31_dec_sub4_function_unit + case + assign $1\dec31_function_unit[12:0] 13'0000000000000 + end + sync always + update \dec31_function_unit $0\dec31_function_unit[12:0] + end + attribute \src "libresoc.v:87169.3-87229.6" + process $proc$libresoc.v:87169$3767 + assign { } { } + assign { } { } + assign $0\dec31_internal_op[6:0] $1\dec31_internal_op[6:0] + attribute \src "libresoc.v:87170.5-87170.29" + switch \initial + attribute \src "libresoc.v:87170.9-87170.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub10_dec31_dec_sub10_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub28_dec31_dec_sub28_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub0_dec31_dec_sub0_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub26_dec31_dec_sub26_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub19_dec31_dec_sub19_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub22_dec31_dec_sub22_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub9_dec31_dec_sub9_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub11_dec31_dec_sub11_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub27_dec31_dec_sub27_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub15_dec31_dec_sub15_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub20_dec31_dec_sub20_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub21_dec31_dec_sub21_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub23_dec31_dec_sub23_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub16_dec31_dec_sub16_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub18_dec31_dec_sub18_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub8_dec31_dec_sub8_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub24_dec31_dec_sub24_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub4_dec31_dec_sub4_internal_op + case + assign $1\dec31_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_internal_op $0\dec31_internal_op[6:0] + end + attribute \src "libresoc.v:87230.3-87290.6" + process $proc$libresoc.v:87230$3768 + assign { } { } + assign { } { } + assign $0\dec31_form[4:0] $1\dec31_form[4:0] + attribute \src "libresoc.v:87231.5-87231.29" + switch \initial + attribute \src "libresoc.v:87231.9-87231.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub10_dec31_dec_sub10_form + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub28_dec31_dec_sub28_form + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub0_dec31_dec_sub0_form + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub26_dec31_dec_sub26_form + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub19_dec31_dec_sub19_form + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub22_dec31_dec_sub22_form + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub9_dec31_dec_sub9_form + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub11_dec31_dec_sub11_form + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub27_dec31_dec_sub27_form + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub15_dec31_dec_sub15_form + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub20_dec31_dec_sub20_form + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub21_dec31_dec_sub21_form + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub23_dec31_dec_sub23_form + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub16_dec31_dec_sub16_form + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub18_dec31_dec_sub18_form + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub8_dec31_dec_sub8_form + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub24_dec31_dec_sub24_form + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub4_dec31_dec_sub4_form + case + assign $1\dec31_form[4:0] 5'00000 + end + sync always + update \dec31_form $0\dec31_form[4:0] + end + attribute \src "libresoc.v:87291.3-87351.6" + process $proc$libresoc.v:87291$3769 + assign { } { } + assign { } { } + assign $0\dec31_asmcode[7:0] $1\dec31_asmcode[7:0] + attribute \src "libresoc.v:87292.5-87292.29" + switch \initial + attribute \src "libresoc.v:87292.9-87292.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub10_dec31_dec_sub10_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub28_dec31_dec_sub28_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub0_dec31_dec_sub0_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub26_dec31_dec_sub26_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub19_dec31_dec_sub19_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub22_dec31_dec_sub22_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub9_dec31_dec_sub9_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub11_dec31_dec_sub11_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub27_dec31_dec_sub27_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub15_dec31_dec_sub15_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub20_dec31_dec_sub20_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub21_dec31_dec_sub21_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub23_dec31_dec_sub23_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub16_dec31_dec_sub16_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub18_dec31_dec_sub18_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub8_dec31_dec_sub8_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub24_dec31_dec_sub24_asmcode + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub4_dec31_dec_sub4_asmcode + case + assign $1\dec31_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_asmcode $0\dec31_asmcode[7:0] + end + attribute \src "libresoc.v:87352.3-87412.6" + process $proc$libresoc.v:87352$3770 + assign { } { } + assign { } { } + assign $0\dec31_SV_Etype[1:0] $1\dec31_SV_Etype[1:0] + attribute \src "libresoc.v:87353.5-87353.29" + switch \initial + attribute \src "libresoc.v:87353.9-87353.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_SV_Etype[1:0] \dec31_dec_sub10_dec31_dec_sub10_SV_Etype + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_SV_Etype[1:0] \dec31_dec_sub28_dec31_dec_sub28_SV_Etype + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_SV_Etype[1:0] \dec31_dec_sub0_dec31_dec_sub0_SV_Etype + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_SV_Etype[1:0] \dec31_dec_sub26_dec31_dec_sub26_SV_Etype + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_SV_Etype[1:0] \dec31_dec_sub19_dec31_dec_sub19_SV_Etype + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_SV_Etype[1:0] \dec31_dec_sub22_dec31_dec_sub22_SV_Etype + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_SV_Etype[1:0] \dec31_dec_sub9_dec31_dec_sub9_SV_Etype + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_SV_Etype[1:0] \dec31_dec_sub11_dec31_dec_sub11_SV_Etype + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_SV_Etype[1:0] \dec31_dec_sub27_dec31_dec_sub27_SV_Etype + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_SV_Etype[1:0] \dec31_dec_sub15_dec31_dec_sub15_SV_Etype + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_SV_Etype[1:0] \dec31_dec_sub20_dec31_dec_sub20_SV_Etype + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_SV_Etype[1:0] \dec31_dec_sub21_dec31_dec_sub21_SV_Etype + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_SV_Etype[1:0] \dec31_dec_sub23_dec31_dec_sub23_SV_Etype + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_SV_Etype[1:0] \dec31_dec_sub16_dec31_dec_sub16_SV_Etype + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_SV_Etype[1:0] \dec31_dec_sub18_dec31_dec_sub18_SV_Etype + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_SV_Etype[1:0] \dec31_dec_sub8_dec31_dec_sub8_SV_Etype + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_SV_Etype[1:0] \dec31_dec_sub24_dec31_dec_sub24_SV_Etype + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_SV_Etype[1:0] \dec31_dec_sub4_dec31_dec_sub4_SV_Etype + case + assign $1\dec31_SV_Etype[1:0] 2'00 + end + sync always + update \dec31_SV_Etype $0\dec31_SV_Etype[1:0] + end + attribute \src "libresoc.v:87413.3-87473.6" + process $proc$libresoc.v:87413$3771 + assign { } { } + assign { } { } + assign $0\dec31_SV_Ptype[1:0] $1\dec31_SV_Ptype[1:0] + attribute \src "libresoc.v:87414.5-87414.29" + switch \initial + attribute \src "libresoc.v:87414.9-87414.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_SV_Ptype[1:0] \dec31_dec_sub10_dec31_dec_sub10_SV_Ptype + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_SV_Ptype[1:0] \dec31_dec_sub28_dec31_dec_sub28_SV_Ptype + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_SV_Ptype[1:0] \dec31_dec_sub0_dec31_dec_sub0_SV_Ptype + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_SV_Ptype[1:0] \dec31_dec_sub26_dec31_dec_sub26_SV_Ptype + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_SV_Ptype[1:0] \dec31_dec_sub19_dec31_dec_sub19_SV_Ptype + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_SV_Ptype[1:0] \dec31_dec_sub22_dec31_dec_sub22_SV_Ptype + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_SV_Ptype[1:0] \dec31_dec_sub9_dec31_dec_sub9_SV_Ptype + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_SV_Ptype[1:0] \dec31_dec_sub11_dec31_dec_sub11_SV_Ptype + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_SV_Ptype[1:0] \dec31_dec_sub27_dec31_dec_sub27_SV_Ptype + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_SV_Ptype[1:0] \dec31_dec_sub15_dec31_dec_sub15_SV_Ptype + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_SV_Ptype[1:0] \dec31_dec_sub20_dec31_dec_sub20_SV_Ptype + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_SV_Ptype[1:0] \dec31_dec_sub21_dec31_dec_sub21_SV_Ptype + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_SV_Ptype[1:0] \dec31_dec_sub23_dec31_dec_sub23_SV_Ptype + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_SV_Ptype[1:0] \dec31_dec_sub16_dec31_dec_sub16_SV_Ptype + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_SV_Ptype[1:0] \dec31_dec_sub18_dec31_dec_sub18_SV_Ptype + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_SV_Ptype[1:0] \dec31_dec_sub8_dec31_dec_sub8_SV_Ptype + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_SV_Ptype[1:0] \dec31_dec_sub24_dec31_dec_sub24_SV_Ptype + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_SV_Ptype[1:0] \dec31_dec_sub4_dec31_dec_sub4_SV_Ptype + case + assign $1\dec31_SV_Ptype[1:0] 2'00 + end + sync always + update \dec31_SV_Ptype $0\dec31_SV_Ptype[1:0] + end + attribute \src "libresoc.v:87474.3-87534.6" + process $proc$libresoc.v:87474$3772 + assign { } { } + assign { } { } + assign $0\dec31_in1_sel[2:0] $1\dec31_in1_sel[2:0] + attribute \src "libresoc.v:87475.5-87475.29" + switch \initial + attribute \src "libresoc.v:87475.9-87475.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub10_dec31_dec_sub10_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub28_dec31_dec_sub28_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub0_dec31_dec_sub0_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub26_dec31_dec_sub26_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub19_dec31_dec_sub19_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub22_dec31_dec_sub22_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub9_dec31_dec_sub9_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub11_dec31_dec_sub11_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub27_dec31_dec_sub27_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub15_dec31_dec_sub15_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub20_dec31_dec_sub20_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub21_dec31_dec_sub21_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub23_dec31_dec_sub23_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub16_dec31_dec_sub16_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub18_dec31_dec_sub18_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub8_dec31_dec_sub8_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub24_dec31_dec_sub24_in1_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub4_dec31_dec_sub4_in1_sel + case + assign $1\dec31_in1_sel[2:0] 3'000 + end + sync always + update \dec31_in1_sel $0\dec31_in1_sel[2:0] + end + attribute \src "libresoc.v:87535.3-87595.6" + process $proc$libresoc.v:87535$3773 + assign { } { } + assign { } { } + assign $0\dec31_in2_sel[3:0] $1\dec31_in2_sel[3:0] + attribute \src "libresoc.v:87536.5-87536.29" + switch \initial + attribute \src "libresoc.v:87536.9-87536.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub10_dec31_dec_sub10_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub28_dec31_dec_sub28_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub0_dec31_dec_sub0_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub26_dec31_dec_sub26_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub19_dec31_dec_sub19_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub22_dec31_dec_sub22_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub9_dec31_dec_sub9_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub11_dec31_dec_sub11_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub27_dec31_dec_sub27_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub15_dec31_dec_sub15_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub20_dec31_dec_sub20_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub21_dec31_dec_sub21_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub23_dec31_dec_sub23_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub16_dec31_dec_sub16_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub18_dec31_dec_sub18_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub8_dec31_dec_sub8_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub24_dec31_dec_sub24_in2_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub4_dec31_dec_sub4_in2_sel + case + assign $1\dec31_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_in2_sel $0\dec31_in2_sel[3:0] + end + attribute \src "libresoc.v:87596.3-87656.6" + process $proc$libresoc.v:87596$3774 + assign { } { } + assign { } { } + assign $0\dec31_in3_sel[1:0] $1\dec31_in3_sel[1:0] + attribute \src "libresoc.v:87597.5-87597.29" + switch \initial + attribute \src "libresoc.v:87597.9-87597.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub10_dec31_dec_sub10_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub28_dec31_dec_sub28_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub0_dec31_dec_sub0_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub26_dec31_dec_sub26_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub19_dec31_dec_sub19_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub22_dec31_dec_sub22_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub9_dec31_dec_sub9_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub11_dec31_dec_sub11_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub27_dec31_dec_sub27_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub15_dec31_dec_sub15_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub20_dec31_dec_sub20_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub21_dec31_dec_sub21_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub23_dec31_dec_sub23_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub16_dec31_dec_sub16_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub18_dec31_dec_sub18_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub8_dec31_dec_sub8_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub24_dec31_dec_sub24_in3_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub4_dec31_dec_sub4_in3_sel + case + assign $1\dec31_in3_sel[1:0] 2'00 + end + sync always + update \dec31_in3_sel $0\dec31_in3_sel[1:0] + end + attribute \src "libresoc.v:87657.3-87717.6" + process $proc$libresoc.v:87657$3775 + assign { } { } + assign { } { } + assign $0\dec31_out_sel[1:0] $1\dec31_out_sel[1:0] + attribute \src "libresoc.v:87658.5-87658.29" + switch \initial + attribute \src "libresoc.v:87658.9-87658.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_out_sel[1:0] \dec31_dec_sub10_dec31_dec_sub10_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_out_sel[1:0] \dec31_dec_sub28_dec31_dec_sub28_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_out_sel[1:0] \dec31_dec_sub0_dec31_dec_sub0_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_out_sel[1:0] \dec31_dec_sub26_dec31_dec_sub26_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_out_sel[1:0] \dec31_dec_sub19_dec31_dec_sub19_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_out_sel[1:0] \dec31_dec_sub22_dec31_dec_sub22_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_out_sel[1:0] \dec31_dec_sub9_dec31_dec_sub9_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_out_sel[1:0] \dec31_dec_sub11_dec31_dec_sub11_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_out_sel[1:0] \dec31_dec_sub27_dec31_dec_sub27_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_out_sel[1:0] \dec31_dec_sub15_dec31_dec_sub15_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_out_sel[1:0] \dec31_dec_sub20_dec31_dec_sub20_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_out_sel[1:0] \dec31_dec_sub21_dec31_dec_sub21_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_out_sel[1:0] \dec31_dec_sub23_dec31_dec_sub23_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_out_sel[1:0] \dec31_dec_sub16_dec31_dec_sub16_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_out_sel[1:0] \dec31_dec_sub18_dec31_dec_sub18_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_out_sel[1:0] \dec31_dec_sub8_dec31_dec_sub8_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_out_sel[1:0] \dec31_dec_sub24_dec31_dec_sub24_out_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_out_sel[1:0] \dec31_dec_sub4_dec31_dec_sub4_out_sel + case + assign $1\dec31_out_sel[1:0] 2'00 + end + sync always + update \dec31_out_sel $0\dec31_out_sel[1:0] + end + attribute \src "libresoc.v:87718.3-87778.6" + process $proc$libresoc.v:87718$3776 + assign { } { } + assign { } { } + assign $0\dec31_cr_in[2:0] $1\dec31_cr_in[2:0] + attribute \src "libresoc.v:87719.5-87719.29" + switch \initial + attribute \src "libresoc.v:87719.9-87719.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub10_dec31_dec_sub10_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub28_dec31_dec_sub28_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub0_dec31_dec_sub0_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub26_dec31_dec_sub26_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub19_dec31_dec_sub19_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub22_dec31_dec_sub22_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub9_dec31_dec_sub9_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub11_dec31_dec_sub11_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub27_dec31_dec_sub27_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub15_dec31_dec_sub15_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub20_dec31_dec_sub20_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub21_dec31_dec_sub21_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub23_dec31_dec_sub23_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub16_dec31_dec_sub16_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub18_dec31_dec_sub18_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub8_dec31_dec_sub8_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub24_dec31_dec_sub24_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub4_dec31_dec_sub4_cr_in + case + assign $1\dec31_cr_in[2:0] 3'000 + end + sync always + update \dec31_cr_in $0\dec31_cr_in[2:0] + end + attribute \src "libresoc.v:87779.3-87839.6" + process $proc$libresoc.v:87779$3777 + assign { } { } + assign { } { } + assign $0\dec31_cr_out[2:0] $1\dec31_cr_out[2:0] + attribute \src "libresoc.v:87780.5-87780.29" + switch \initial + attribute \src "libresoc.v:87780.9-87780.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub10_dec31_dec_sub10_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub28_dec31_dec_sub28_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub0_dec31_dec_sub0_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub26_dec31_dec_sub26_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub19_dec31_dec_sub19_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub22_dec31_dec_sub22_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub9_dec31_dec_sub9_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub11_dec31_dec_sub11_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub27_dec31_dec_sub27_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub15_dec31_dec_sub15_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub20_dec31_dec_sub20_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub21_dec31_dec_sub21_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub23_dec31_dec_sub23_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub16_dec31_dec_sub16_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub18_dec31_dec_sub18_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub8_dec31_dec_sub8_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub24_dec31_dec_sub24_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub4_dec31_dec_sub4_cr_out + case + assign $1\dec31_cr_out[2:0] 3'000 + end + sync always + update \dec31_cr_out $0\dec31_cr_out[2:0] + end + attribute \src "libresoc.v:87840.3-87900.6" + process $proc$libresoc.v:87840$3778 + assign { } { } + assign { } { } + assign $0\dec31_sv_in1[2:0] $1\dec31_sv_in1[2:0] + attribute \src "libresoc.v:87841.5-87841.29" + switch \initial + attribute \src "libresoc.v:87841.9-87841.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_sv_in1[2:0] \dec31_dec_sub10_dec31_dec_sub10_sv_in1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_sv_in1[2:0] \dec31_dec_sub28_dec31_dec_sub28_sv_in1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_sv_in1[2:0] \dec31_dec_sub0_dec31_dec_sub0_sv_in1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_sv_in1[2:0] \dec31_dec_sub26_dec31_dec_sub26_sv_in1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_sv_in1[2:0] \dec31_dec_sub19_dec31_dec_sub19_sv_in1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_sv_in1[2:0] \dec31_dec_sub22_dec31_dec_sub22_sv_in1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_sv_in1[2:0] \dec31_dec_sub9_dec31_dec_sub9_sv_in1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_sv_in1[2:0] \dec31_dec_sub11_dec31_dec_sub11_sv_in1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_sv_in1[2:0] \dec31_dec_sub27_dec31_dec_sub27_sv_in1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_sv_in1[2:0] \dec31_dec_sub15_dec31_dec_sub15_sv_in1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_sv_in1[2:0] \dec31_dec_sub20_dec31_dec_sub20_sv_in1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_sv_in1[2:0] \dec31_dec_sub21_dec31_dec_sub21_sv_in1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_sv_in1[2:0] \dec31_dec_sub23_dec31_dec_sub23_sv_in1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_sv_in1[2:0] \dec31_dec_sub16_dec31_dec_sub16_sv_in1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_sv_in1[2:0] \dec31_dec_sub18_dec31_dec_sub18_sv_in1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_sv_in1[2:0] \dec31_dec_sub8_dec31_dec_sub8_sv_in1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_sv_in1[2:0] \dec31_dec_sub24_dec31_dec_sub24_sv_in1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_sv_in1[2:0] \dec31_dec_sub4_dec31_dec_sub4_sv_in1 + case + assign $1\dec31_sv_in1[2:0] 3'000 + end + sync always + update \dec31_sv_in1 $0\dec31_sv_in1[2:0] + end + attribute \src "libresoc.v:87901.3-87961.6" + process $proc$libresoc.v:87901$3779 + assign { } { } + assign { } { } + assign $0\dec31_sv_in2[2:0] $1\dec31_sv_in2[2:0] + attribute \src "libresoc.v:87902.5-87902.29" + switch \initial + attribute \src "libresoc.v:87902.9-87902.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_sv_in2[2:0] \dec31_dec_sub10_dec31_dec_sub10_sv_in2 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_sv_in2[2:0] \dec31_dec_sub28_dec31_dec_sub28_sv_in2 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_sv_in2[2:0] \dec31_dec_sub0_dec31_dec_sub0_sv_in2 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_sv_in2[2:0] \dec31_dec_sub26_dec31_dec_sub26_sv_in2 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_sv_in2[2:0] \dec31_dec_sub19_dec31_dec_sub19_sv_in2 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_sv_in2[2:0] \dec31_dec_sub22_dec31_dec_sub22_sv_in2 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_sv_in2[2:0] \dec31_dec_sub9_dec31_dec_sub9_sv_in2 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_sv_in2[2:0] \dec31_dec_sub11_dec31_dec_sub11_sv_in2 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_sv_in2[2:0] \dec31_dec_sub27_dec31_dec_sub27_sv_in2 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_sv_in2[2:0] \dec31_dec_sub15_dec31_dec_sub15_sv_in2 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_sv_in2[2:0] \dec31_dec_sub20_dec31_dec_sub20_sv_in2 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_sv_in2[2:0] \dec31_dec_sub21_dec31_dec_sub21_sv_in2 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_sv_in2[2:0] \dec31_dec_sub23_dec31_dec_sub23_sv_in2 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_sv_in2[2:0] \dec31_dec_sub16_dec31_dec_sub16_sv_in2 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_sv_in2[2:0] \dec31_dec_sub18_dec31_dec_sub18_sv_in2 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_sv_in2[2:0] \dec31_dec_sub8_dec31_dec_sub8_sv_in2 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_sv_in2[2:0] \dec31_dec_sub24_dec31_dec_sub24_sv_in2 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_sv_in2[2:0] \dec31_dec_sub4_dec31_dec_sub4_sv_in2 + case + assign $1\dec31_sv_in2[2:0] 3'000 + end + sync always + update \dec31_sv_in2 $0\dec31_sv_in2[2:0] + end + attribute \src "libresoc.v:87962.3-88022.6" + process $proc$libresoc.v:87962$3780 + assign { } { } + assign { } { } + assign $0\dec31_sv_in3[2:0] $1\dec31_sv_in3[2:0] + attribute \src "libresoc.v:87963.5-87963.29" + switch \initial + attribute \src "libresoc.v:87963.9-87963.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_sv_in3[2:0] \dec31_dec_sub10_dec31_dec_sub10_sv_in3 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_sv_in3[2:0] \dec31_dec_sub28_dec31_dec_sub28_sv_in3 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_sv_in3[2:0] \dec31_dec_sub0_dec31_dec_sub0_sv_in3 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_sv_in3[2:0] \dec31_dec_sub26_dec31_dec_sub26_sv_in3 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_sv_in3[2:0] \dec31_dec_sub19_dec31_dec_sub19_sv_in3 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_sv_in3[2:0] \dec31_dec_sub22_dec31_dec_sub22_sv_in3 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_sv_in3[2:0] \dec31_dec_sub9_dec31_dec_sub9_sv_in3 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_sv_in3[2:0] \dec31_dec_sub11_dec31_dec_sub11_sv_in3 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_sv_in3[2:0] \dec31_dec_sub27_dec31_dec_sub27_sv_in3 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_sv_in3[2:0] \dec31_dec_sub15_dec31_dec_sub15_sv_in3 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_sv_in3[2:0] \dec31_dec_sub20_dec31_dec_sub20_sv_in3 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_sv_in3[2:0] \dec31_dec_sub21_dec31_dec_sub21_sv_in3 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_sv_in3[2:0] \dec31_dec_sub23_dec31_dec_sub23_sv_in3 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_sv_in3[2:0] \dec31_dec_sub16_dec31_dec_sub16_sv_in3 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_sv_in3[2:0] \dec31_dec_sub18_dec31_dec_sub18_sv_in3 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_sv_in3[2:0] \dec31_dec_sub8_dec31_dec_sub8_sv_in3 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_sv_in3[2:0] \dec31_dec_sub24_dec31_dec_sub24_sv_in3 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_sv_in3[2:0] \dec31_dec_sub4_dec31_dec_sub4_sv_in3 + case + assign $1\dec31_sv_in3[2:0] 3'000 + end + sync always + update \dec31_sv_in3 $0\dec31_sv_in3[2:0] + end + attribute \src "libresoc.v:88023.3-88083.6" + process $proc$libresoc.v:88023$3781 + assign { } { } + assign { } { } + assign $0\dec31_sv_out[2:0] $1\dec31_sv_out[2:0] + attribute \src "libresoc.v:88024.5-88024.29" + switch \initial + attribute \src "libresoc.v:88024.9-88024.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_sv_out[2:0] \dec31_dec_sub10_dec31_dec_sub10_sv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_sv_out[2:0] \dec31_dec_sub28_dec31_dec_sub28_sv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_sv_out[2:0] \dec31_dec_sub0_dec31_dec_sub0_sv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_sv_out[2:0] \dec31_dec_sub26_dec31_dec_sub26_sv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_sv_out[2:0] \dec31_dec_sub19_dec31_dec_sub19_sv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_sv_out[2:0] \dec31_dec_sub22_dec31_dec_sub22_sv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_sv_out[2:0] \dec31_dec_sub9_dec31_dec_sub9_sv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_sv_out[2:0] \dec31_dec_sub11_dec31_dec_sub11_sv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_sv_out[2:0] \dec31_dec_sub27_dec31_dec_sub27_sv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_sv_out[2:0] \dec31_dec_sub15_dec31_dec_sub15_sv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_sv_out[2:0] \dec31_dec_sub20_dec31_dec_sub20_sv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_sv_out[2:0] \dec31_dec_sub21_dec31_dec_sub21_sv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_sv_out[2:0] \dec31_dec_sub23_dec31_dec_sub23_sv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_sv_out[2:0] \dec31_dec_sub16_dec31_dec_sub16_sv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_sv_out[2:0] \dec31_dec_sub18_dec31_dec_sub18_sv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_sv_out[2:0] \dec31_dec_sub8_dec31_dec_sub8_sv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_sv_out[2:0] \dec31_dec_sub24_dec31_dec_sub24_sv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_sv_out[2:0] \dec31_dec_sub4_dec31_dec_sub4_sv_out + case + assign $1\dec31_sv_out[2:0] 3'000 + end + sync always + update \dec31_sv_out $0\dec31_sv_out[2:0] + end + attribute \src "libresoc.v:88084.3-88144.6" + process $proc$libresoc.v:88084$3782 + assign { } { } + assign { } { } + assign $0\dec31_sv_cr_in[2:0] $1\dec31_sv_cr_in[2:0] + attribute \src "libresoc.v:88085.5-88085.29" + switch \initial + attribute \src "libresoc.v:88085.9-88085.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_sv_cr_in[2:0] \dec31_dec_sub10_dec31_dec_sub10_sv_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_sv_cr_in[2:0] \dec31_dec_sub28_dec31_dec_sub28_sv_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_sv_cr_in[2:0] \dec31_dec_sub0_dec31_dec_sub0_sv_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_sv_cr_in[2:0] \dec31_dec_sub26_dec31_dec_sub26_sv_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_sv_cr_in[2:0] \dec31_dec_sub19_dec31_dec_sub19_sv_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_sv_cr_in[2:0] \dec31_dec_sub22_dec31_dec_sub22_sv_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_sv_cr_in[2:0] \dec31_dec_sub9_dec31_dec_sub9_sv_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_sv_cr_in[2:0] \dec31_dec_sub11_dec31_dec_sub11_sv_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_sv_cr_in[2:0] \dec31_dec_sub27_dec31_dec_sub27_sv_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_sv_cr_in[2:0] \dec31_dec_sub15_dec31_dec_sub15_sv_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_sv_cr_in[2:0] \dec31_dec_sub20_dec31_dec_sub20_sv_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_sv_cr_in[2:0] \dec31_dec_sub21_dec31_dec_sub21_sv_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_sv_cr_in[2:0] \dec31_dec_sub23_dec31_dec_sub23_sv_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_sv_cr_in[2:0] \dec31_dec_sub16_dec31_dec_sub16_sv_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_sv_cr_in[2:0] \dec31_dec_sub18_dec31_dec_sub18_sv_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_sv_cr_in[2:0] \dec31_dec_sub8_dec31_dec_sub8_sv_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_sv_cr_in[2:0] \dec31_dec_sub24_dec31_dec_sub24_sv_cr_in + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_sv_cr_in[2:0] \dec31_dec_sub4_dec31_dec_sub4_sv_cr_in + case + assign $1\dec31_sv_cr_in[2:0] 3'000 + end + sync always + update \dec31_sv_cr_in $0\dec31_sv_cr_in[2:0] + end + attribute \src "libresoc.v:88145.3-88205.6" + process $proc$libresoc.v:88145$3783 + assign { } { } + assign { } { } + assign $0\dec31_sv_cr_out[2:0] $1\dec31_sv_cr_out[2:0] + attribute \src "libresoc.v:88146.5-88146.29" + switch \initial + attribute \src "libresoc.v:88146.9-88146.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_sv_cr_out[2:0] \dec31_dec_sub10_dec31_dec_sub10_sv_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_sv_cr_out[2:0] \dec31_dec_sub28_dec31_dec_sub28_sv_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_sv_cr_out[2:0] \dec31_dec_sub0_dec31_dec_sub0_sv_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_sv_cr_out[2:0] \dec31_dec_sub26_dec31_dec_sub26_sv_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_sv_cr_out[2:0] \dec31_dec_sub19_dec31_dec_sub19_sv_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_sv_cr_out[2:0] \dec31_dec_sub22_dec31_dec_sub22_sv_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_sv_cr_out[2:0] \dec31_dec_sub9_dec31_dec_sub9_sv_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_sv_cr_out[2:0] \dec31_dec_sub11_dec31_dec_sub11_sv_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_sv_cr_out[2:0] \dec31_dec_sub27_dec31_dec_sub27_sv_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_sv_cr_out[2:0] \dec31_dec_sub15_dec31_dec_sub15_sv_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_sv_cr_out[2:0] \dec31_dec_sub20_dec31_dec_sub20_sv_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_sv_cr_out[2:0] \dec31_dec_sub21_dec31_dec_sub21_sv_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_sv_cr_out[2:0] \dec31_dec_sub23_dec31_dec_sub23_sv_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_sv_cr_out[2:0] \dec31_dec_sub16_dec31_dec_sub16_sv_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_sv_cr_out[2:0] \dec31_dec_sub18_dec31_dec_sub18_sv_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_sv_cr_out[2:0] \dec31_dec_sub8_dec31_dec_sub8_sv_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_sv_cr_out[2:0] \dec31_dec_sub24_dec31_dec_sub24_sv_cr_out + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_sv_cr_out[2:0] \dec31_dec_sub4_dec31_dec_sub4_sv_cr_out + case + assign $1\dec31_sv_cr_out[2:0] 3'000 + end + sync always + update \dec31_sv_cr_out $0\dec31_sv_cr_out[2:0] + end + attribute \src "libresoc.v:88206.3-88266.6" + process $proc$libresoc.v:88206$3784 + assign { } { } + assign { } { } + assign $0\dec31_ldst_len[3:0] $1\dec31_ldst_len[3:0] + attribute \src "libresoc.v:88207.5-88207.29" + switch \initial + attribute \src "libresoc.v:88207.9-88207.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub10_dec31_dec_sub10_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub28_dec31_dec_sub28_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub0_dec31_dec_sub0_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub26_dec31_dec_sub26_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub19_dec31_dec_sub19_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub22_dec31_dec_sub22_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub9_dec31_dec_sub9_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub11_dec31_dec_sub11_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub27_dec31_dec_sub27_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub15_dec31_dec_sub15_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub20_dec31_dec_sub20_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub21_dec31_dec_sub21_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub23_dec31_dec_sub23_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub16_dec31_dec_sub16_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub18_dec31_dec_sub18_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub8_dec31_dec_sub8_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub24_dec31_dec_sub24_ldst_len + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub4_dec31_dec_sub4_ldst_len + case + assign $1\dec31_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_ldst_len $0\dec31_ldst_len[3:0] + end + attribute \src "libresoc.v:88267.3-88327.6" + process $proc$libresoc.v:88267$3785 + assign { } { } + assign { } { } + assign $0\dec31_upd[1:0] $1\dec31_upd[1:0] + attribute \src "libresoc.v:88268.5-88268.29" + switch \initial + attribute \src "libresoc.v:88268.9-88268.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub10_dec31_dec_sub10_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub28_dec31_dec_sub28_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub0_dec31_dec_sub0_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub26_dec31_dec_sub26_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub19_dec31_dec_sub19_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub22_dec31_dec_sub22_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub9_dec31_dec_sub9_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub11_dec31_dec_sub11_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub27_dec31_dec_sub27_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub15_dec31_dec_sub15_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub20_dec31_dec_sub20_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub21_dec31_dec_sub21_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub23_dec31_dec_sub23_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub16_dec31_dec_sub16_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub18_dec31_dec_sub18_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub8_dec31_dec_sub8_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub24_dec31_dec_sub24_upd + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub4_dec31_dec_sub4_upd + case + assign $1\dec31_upd[1:0] 2'00 + end + sync always + update \dec31_upd $0\dec31_upd[1:0] + end + attribute \src "libresoc.v:88328.3-88388.6" + process $proc$libresoc.v:88328$3786 + assign { } { } + assign { } { } + assign $0\dec31_rc_sel[1:0] $1\dec31_rc_sel[1:0] + attribute \src "libresoc.v:88329.5-88329.29" + switch \initial + attribute \src "libresoc.v:88329.9-88329.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub10_dec31_dec_sub10_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub28_dec31_dec_sub28_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub0_dec31_dec_sub0_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub26_dec31_dec_sub26_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub19_dec31_dec_sub19_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub22_dec31_dec_sub22_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub9_dec31_dec_sub9_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub11_dec31_dec_sub11_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub27_dec31_dec_sub27_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub15_dec31_dec_sub15_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub20_dec31_dec_sub20_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub21_dec31_dec_sub21_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub23_dec31_dec_sub23_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub16_dec31_dec_sub16_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub18_dec31_dec_sub18_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub8_dec31_dec_sub8_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub24_dec31_dec_sub24_rc_sel + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub4_dec31_dec_sub4_rc_sel + case + assign $1\dec31_rc_sel[1:0] 2'00 + end + sync always + update \dec31_rc_sel $0\dec31_rc_sel[1:0] + end + attribute \src "libresoc.v:88389.3-88449.6" + process $proc$libresoc.v:88389$3787 + assign { } { } + assign { } { } + assign $0\dec31_cry_in[1:0] $1\dec31_cry_in[1:0] + attribute \src "libresoc.v:88390.5-88390.29" + switch \initial + attribute \src "libresoc.v:88390.9-88390.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub10_dec31_dec_sub10_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub28_dec31_dec_sub28_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub0_dec31_dec_sub0_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub26_dec31_dec_sub26_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub19_dec31_dec_sub19_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub22_dec31_dec_sub22_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub9_dec31_dec_sub9_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub11_dec31_dec_sub11_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub27_dec31_dec_sub27_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub15_dec31_dec_sub15_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub20_dec31_dec_sub20_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub21_dec31_dec_sub21_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub23_dec31_dec_sub23_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub16_dec31_dec_sub16_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub18_dec31_dec_sub18_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub8_dec31_dec_sub8_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub24_dec31_dec_sub24_cry_in + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub4_dec31_dec_sub4_cry_in + case + assign $1\dec31_cry_in[1:0] 2'00 + end + sync always + update \dec31_cry_in $0\dec31_cry_in[1:0] + end + attribute \src "libresoc.v:88450.3-88510.6" + process $proc$libresoc.v:88450$3788 + assign { } { } + assign { } { } + assign $0\dec31_inv_a[0:0] $1\dec31_inv_a[0:0] + attribute \src "libresoc.v:88451.5-88451.29" + switch \initial + attribute \src "libresoc.v:88451.9-88451.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub10_dec31_dec_sub10_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub28_dec31_dec_sub28_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub0_dec31_dec_sub0_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub26_dec31_dec_sub26_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub19_dec31_dec_sub19_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub22_dec31_dec_sub22_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub9_dec31_dec_sub9_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub11_dec31_dec_sub11_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub27_dec31_dec_sub27_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub15_dec31_dec_sub15_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub20_dec31_dec_sub20_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub21_dec31_dec_sub21_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub23_dec31_dec_sub23_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub16_dec31_dec_sub16_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub18_dec31_dec_sub18_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub8_dec31_dec_sub8_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub24_dec31_dec_sub24_inv_a + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub4_dec31_dec_sub4_inv_a + case + assign $1\dec31_inv_a[0:0] 1'0 + end + sync always + update \dec31_inv_a $0\dec31_inv_a[0:0] + end + attribute \src "libresoc.v:88511.3-88571.6" + process $proc$libresoc.v:88511$3789 + assign { } { } + assign { } { } + assign $0\dec31_inv_out[0:0] $1\dec31_inv_out[0:0] + attribute \src "libresoc.v:88512.5-88512.29" + switch \initial + attribute \src "libresoc.v:88512.9-88512.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub10_dec31_dec_sub10_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub28_dec31_dec_sub28_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub0_dec31_dec_sub0_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub26_dec31_dec_sub26_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub19_dec31_dec_sub19_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub22_dec31_dec_sub22_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub9_dec31_dec_sub9_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub11_dec31_dec_sub11_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub27_dec31_dec_sub27_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub15_dec31_dec_sub15_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub20_dec31_dec_sub20_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub21_dec31_dec_sub21_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub23_dec31_dec_sub23_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub16_dec31_dec_sub16_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub18_dec31_dec_sub18_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub8_dec31_dec_sub8_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub24_dec31_dec_sub24_inv_out + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub4_dec31_dec_sub4_inv_out + case + assign $1\dec31_inv_out[0:0] 1'0 + end + sync always + update \dec31_inv_out $0\dec31_inv_out[0:0] + end + attribute \src "libresoc.v:88572.3-88632.6" + process $proc$libresoc.v:88572$3790 + assign { } { } + assign { } { } + assign $0\dec31_cry_out[0:0] $1\dec31_cry_out[0:0] + attribute \src "libresoc.v:88573.5-88573.29" + switch \initial + attribute \src "libresoc.v:88573.9-88573.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub10_dec31_dec_sub10_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub28_dec31_dec_sub28_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub0_dec31_dec_sub0_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub26_dec31_dec_sub26_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub19_dec31_dec_sub19_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub22_dec31_dec_sub22_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub9_dec31_dec_sub9_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub11_dec31_dec_sub11_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub27_dec31_dec_sub27_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub15_dec31_dec_sub15_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub20_dec31_dec_sub20_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub21_dec31_dec_sub21_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub23_dec31_dec_sub23_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub16_dec31_dec_sub16_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub18_dec31_dec_sub18_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub8_dec31_dec_sub8_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub24_dec31_dec_sub24_cry_out + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub4_dec31_dec_sub4_cry_out + case + assign $1\dec31_cry_out[0:0] 1'0 + end + sync always + update \dec31_cry_out $0\dec31_cry_out[0:0] + end + attribute \src "libresoc.v:88633.3-88693.6" + process $proc$libresoc.v:88633$3791 + assign { } { } + assign { } { } + assign $0\dec31_br[0:0] $1\dec31_br[0:0] + attribute \src "libresoc.v:88634.5-88634.29" + switch \initial + attribute \src "libresoc.v:88634.9-88634.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub10_dec31_dec_sub10_br + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub28_dec31_dec_sub28_br + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub0_dec31_dec_sub0_br + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub26_dec31_dec_sub26_br + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub19_dec31_dec_sub19_br + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub22_dec31_dec_sub22_br + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub9_dec31_dec_sub9_br + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub11_dec31_dec_sub11_br + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub27_dec31_dec_sub27_br + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub15_dec31_dec_sub15_br + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub20_dec31_dec_sub20_br + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub21_dec31_dec_sub21_br + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub23_dec31_dec_sub23_br + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub16_dec31_dec_sub16_br + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub18_dec31_dec_sub18_br + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub8_dec31_dec_sub8_br + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub24_dec31_dec_sub24_br + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub4_dec31_dec_sub4_br + case + assign $1\dec31_br[0:0] 1'0 + end + sync always + update \dec31_br $0\dec31_br[0:0] + end + attribute \src "libresoc.v:88694.3-88754.6" + process $proc$libresoc.v:88694$3792 + assign { } { } + assign { } { } + assign $0\dec31_sgn_ext[0:0] $1\dec31_sgn_ext[0:0] + attribute \src "libresoc.v:88695.5-88695.29" + switch \initial + attribute \src "libresoc.v:88695.9-88695.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub10_dec31_dec_sub10_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub28_dec31_dec_sub28_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub0_dec31_dec_sub0_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub26_dec31_dec_sub26_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub19_dec31_dec_sub19_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub22_dec31_dec_sub22_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub9_dec31_dec_sub9_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub11_dec31_dec_sub11_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub27_dec31_dec_sub27_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub15_dec31_dec_sub15_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub20_dec31_dec_sub20_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub21_dec31_dec_sub21_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub23_dec31_dec_sub23_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub16_dec31_dec_sub16_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub18_dec31_dec_sub18_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub8_dec31_dec_sub8_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub24_dec31_dec_sub24_sgn_ext + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub4_dec31_dec_sub4_sgn_ext + case + assign $1\dec31_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_sgn_ext $0\dec31_sgn_ext[0:0] + end + attribute \src "libresoc.v:88755.3-88815.6" + process $proc$libresoc.v:88755$3793 + assign { } { } + assign { } { } + assign $0\dec31_rsrv[0:0] $1\dec31_rsrv[0:0] + attribute \src "libresoc.v:88756.5-88756.29" + switch \initial + attribute \src "libresoc.v:88756.9-88756.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub10_dec31_dec_sub10_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub28_dec31_dec_sub28_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub0_dec31_dec_sub0_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub26_dec31_dec_sub26_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub19_dec31_dec_sub19_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub22_dec31_dec_sub22_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub9_dec31_dec_sub9_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub11_dec31_dec_sub11_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub27_dec31_dec_sub27_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub15_dec31_dec_sub15_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub20_dec31_dec_sub20_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub21_dec31_dec_sub21_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub23_dec31_dec_sub23_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub16_dec31_dec_sub16_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub18_dec31_dec_sub18_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub8_dec31_dec_sub8_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub24_dec31_dec_sub24_rsrv + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub4_dec31_dec_sub4_rsrv + case + assign $1\dec31_rsrv[0:0] 1'0 + end + sync always + update \dec31_rsrv $0\dec31_rsrv[0:0] + end + attribute \src "libresoc.v:88816.3-88876.6" + process $proc$libresoc.v:88816$3794 + assign { } { } + assign { } { } + assign $0\dec31_is_32b[0:0] $1\dec31_is_32b[0:0] + attribute \src "libresoc.v:88817.5-88817.29" + switch \initial + attribute \src "libresoc.v:88817.9-88817.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub10_dec31_dec_sub10_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub28_dec31_dec_sub28_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub0_dec31_dec_sub0_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub26_dec31_dec_sub26_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub19_dec31_dec_sub19_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub22_dec31_dec_sub22_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub9_dec31_dec_sub9_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub11_dec31_dec_sub11_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub27_dec31_dec_sub27_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub15_dec31_dec_sub15_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub20_dec31_dec_sub20_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub21_dec31_dec_sub21_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub23_dec31_dec_sub23_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub16_dec31_dec_sub16_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub18_dec31_dec_sub18_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub8_dec31_dec_sub8_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub24_dec31_dec_sub24_is_32b + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub4_dec31_dec_sub4_is_32b + case + assign $1\dec31_is_32b[0:0] 1'0 + end + sync always + update \dec31_is_32b $0\dec31_is_32b[0:0] + end + attribute \src "libresoc.v:88877.3-88937.6" + process $proc$libresoc.v:88877$3795 + assign { } { } + assign { } { } + assign $0\dec31_sgn[0:0] $1\dec31_sgn[0:0] + attribute \src "libresoc.v:88878.5-88878.29" + switch \initial + attribute \src "libresoc.v:88878.9-88878.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub10_dec31_dec_sub10_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub28_dec31_dec_sub28_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub0_dec31_dec_sub0_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub26_dec31_dec_sub26_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub19_dec31_dec_sub19_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub22_dec31_dec_sub22_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub9_dec31_dec_sub9_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub11_dec31_dec_sub11_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub27_dec31_dec_sub27_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub15_dec31_dec_sub15_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub20_dec31_dec_sub20_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub21_dec31_dec_sub21_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub23_dec31_dec_sub23_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub16_dec31_dec_sub16_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub18_dec31_dec_sub18_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub8_dec31_dec_sub8_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub24_dec31_dec_sub24_sgn + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub4_dec31_dec_sub4_sgn + case + assign $1\dec31_sgn[0:0] 1'0 + end + sync always + update \dec31_sgn $0\dec31_sgn[0:0] + end + attribute \src "libresoc.v:88938.3-88998.6" + process $proc$libresoc.v:88938$3796 + assign { } { } + assign { } { } + assign $0\dec31_lk[0:0] $1\dec31_lk[0:0] + attribute \src "libresoc.v:88939.5-88939.29" + switch \initial + attribute \src "libresoc.v:88939.9-88939.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub10_dec31_dec_sub10_lk + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub28_dec31_dec_sub28_lk + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub0_dec31_dec_sub0_lk + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub26_dec31_dec_sub26_lk + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub19_dec31_dec_sub19_lk + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub22_dec31_dec_sub22_lk + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub9_dec31_dec_sub9_lk + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub11_dec31_dec_sub11_lk + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub27_dec31_dec_sub27_lk + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub15_dec31_dec_sub15_lk + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub20_dec31_dec_sub20_lk + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub21_dec31_dec_sub21_lk + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub23_dec31_dec_sub23_lk + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub16_dec31_dec_sub16_lk + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub18_dec31_dec_sub18_lk + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub8_dec31_dec_sub8_lk + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub24_dec31_dec_sub24_lk + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub4_dec31_dec_sub4_lk + case + assign $1\dec31_lk[0:0] 1'0 + end + sync always + update \dec31_lk $0\dec31_lk[0:0] + end + attribute \src "libresoc.v:88999.3-89059.6" + process $proc$libresoc.v:88999$3797 + assign { } { } + assign { } { } + assign $0\dec31_sgl_pipe[0:0] $1\dec31_sgl_pipe[0:0] + attribute \src "libresoc.v:89000.5-89000.29" + switch \initial + attribute \src "libresoc.v:89000.9-89000.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opc_in + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub10_dec31_dec_sub10_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub28_dec31_dec_sub28_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub0_dec31_dec_sub0_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub26_dec31_dec_sub26_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub19_dec31_dec_sub19_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub22_dec31_dec_sub22_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub9_dec31_dec_sub9_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub11_dec31_dec_sub11_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub27_dec31_dec_sub27_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub15_dec31_dec_sub15_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub20_dec31_dec_sub20_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub21_dec31_dec_sub21_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub23_dec31_dec_sub23_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub16_dec31_dec_sub16_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub18_dec31_dec_sub18_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub8_dec31_dec_sub8_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub24_dec31_dec_sub24_sgl_pipe + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub4_dec31_dec_sub4_sgl_pipe + case + assign $1\dec31_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_sgl_pipe $0\dec31_sgl_pipe[0:0] + end + connect \dec31_dec_sub4_opcode_in \opcode_in + connect \dec31_dec_sub24_opcode_in \opcode_in + connect \dec31_dec_sub8_opcode_in \opcode_in + connect \dec31_dec_sub18_opcode_in \opcode_in + connect \dec31_dec_sub16_opcode_in \opcode_in + connect \dec31_dec_sub23_opcode_in \opcode_in + connect \dec31_dec_sub21_opcode_in \opcode_in + connect \dec31_dec_sub20_opcode_in \opcode_in + connect \dec31_dec_sub15_opcode_in \opcode_in + connect \dec31_dec_sub27_opcode_in \opcode_in + connect \dec31_dec_sub11_opcode_in \opcode_in + connect \dec31_dec_sub9_opcode_in \opcode_in + connect \dec31_dec_sub22_opcode_in \opcode_in + connect \dec31_dec_sub19_opcode_in \opcode_in + connect \dec31_dec_sub26_opcode_in \opcode_in + connect \dec31_dec_sub0_opcode_in \opcode_in + connect \dec31_dec_sub28_opcode_in \opcode_in + connect \dec31_dec_sub10_opcode_in \opcode_in + connect \opc_in \opcode_switch [4:0] + connect \opcode_switch \opcode_in [10:1] +end +attribute \src "libresoc.v:89084.1-90028.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub0" +attribute \generator "nMigen" +module \dec31_dec_sub0 + attribute \src "libresoc.v:89913.3-89931.6" + wire width 2 $0\dec31_dec_sub0_SV_Etype[1:0] + attribute \src "libresoc.v:89932.3-89950.6" + wire width 2 $0\dec31_dec_sub0_SV_Ptype[1:0] + attribute \src "libresoc.v:89685.3-89703.6" + wire width 8 $0\dec31_dec_sub0_asmcode[7:0] + attribute \src "libresoc.v:89761.3-89779.6" + wire $0\dec31_dec_sub0_br[0:0] + attribute \src "libresoc.v:89438.3-89456.6" + wire width 3 $0\dec31_dec_sub0_cr_in[2:0] + attribute \src "libresoc.v:89457.3-89475.6" + wire width 3 $0\dec31_dec_sub0_cr_out[2:0] + attribute \src "libresoc.v:89666.3-89684.6" + wire width 2 $0\dec31_dec_sub0_cry_in[1:0] + attribute \src "libresoc.v:89742.3-89760.6" + wire $0\dec31_dec_sub0_cry_out[0:0] + attribute \src "libresoc.v:89837.3-89855.6" + wire width 5 $0\dec31_dec_sub0_form[4:0] + attribute \src "libresoc.v:89419.3-89437.6" + wire width 13 $0\dec31_dec_sub0_function_unit[12:0] + attribute \src "libresoc.v:89951.3-89969.6" + wire width 3 $0\dec31_dec_sub0_in1_sel[2:0] + attribute \src "libresoc.v:89970.3-89988.6" + wire width 4 $0\dec31_dec_sub0_in2_sel[3:0] + attribute \src "libresoc.v:89989.3-90007.6" + wire width 2 $0\dec31_dec_sub0_in3_sel[1:0] + attribute \src "libresoc.v:89628.3-89646.6" + wire width 7 $0\dec31_dec_sub0_internal_op[6:0] + attribute \src "libresoc.v:89704.3-89722.6" + wire $0\dec31_dec_sub0_inv_a[0:0] + attribute \src "libresoc.v:89723.3-89741.6" + wire $0\dec31_dec_sub0_inv_out[0:0] + attribute \src "libresoc.v:89818.3-89836.6" + wire $0\dec31_dec_sub0_is_32b[0:0] + attribute \src "libresoc.v:89590.3-89608.6" + wire width 4 $0\dec31_dec_sub0_ldst_len[3:0] + attribute \src "libresoc.v:89875.3-89893.6" + wire $0\dec31_dec_sub0_lk[0:0] + attribute \src "libresoc.v:90008.3-90026.6" + wire width 2 $0\dec31_dec_sub0_out_sel[1:0] + attribute \src "libresoc.v:89647.3-89665.6" + wire width 2 $0\dec31_dec_sub0_rc_sel[1:0] + attribute \src "libresoc.v:89799.3-89817.6" + wire $0\dec31_dec_sub0_rsrv[0:0] + attribute \src "libresoc.v:89894.3-89912.6" + wire $0\dec31_dec_sub0_sgl_pipe[0:0] + attribute \src "libresoc.v:89856.3-89874.6" + wire $0\dec31_dec_sub0_sgn[0:0] + attribute \src "libresoc.v:89780.3-89798.6" + wire $0\dec31_dec_sub0_sgn_ext[0:0] + attribute \src "libresoc.v:89552.3-89570.6" + wire width 3 $0\dec31_dec_sub0_sv_cr_in[2:0] + attribute \src "libresoc.v:89571.3-89589.6" + wire width 3 $0\dec31_dec_sub0_sv_cr_out[2:0] + attribute \src "libresoc.v:89476.3-89494.6" + wire width 3 $0\dec31_dec_sub0_sv_in1[2:0] + attribute \src "libresoc.v:89495.3-89513.6" + wire width 3 $0\dec31_dec_sub0_sv_in2[2:0] + attribute \src "libresoc.v:89514.3-89532.6" + wire width 3 $0\dec31_dec_sub0_sv_in3[2:0] + attribute \src "libresoc.v:89533.3-89551.6" + wire width 3 $0\dec31_dec_sub0_sv_out[2:0] + attribute \src "libresoc.v:89609.3-89627.6" + wire width 2 $0\dec31_dec_sub0_upd[1:0] + attribute \src "libresoc.v:89085.7-89085.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:89913.3-89931.6" + wire width 2 $1\dec31_dec_sub0_SV_Etype[1:0] + attribute \src "libresoc.v:89932.3-89950.6" + wire width 2 $1\dec31_dec_sub0_SV_Ptype[1:0] + attribute \src "libresoc.v:89685.3-89703.6" + wire width 8 $1\dec31_dec_sub0_asmcode[7:0] + attribute \src "libresoc.v:89761.3-89779.6" + wire $1\dec31_dec_sub0_br[0:0] + attribute \src "libresoc.v:89438.3-89456.6" + wire width 3 $1\dec31_dec_sub0_cr_in[2:0] + attribute \src "libresoc.v:89457.3-89475.6" + wire width 3 $1\dec31_dec_sub0_cr_out[2:0] + attribute \src "libresoc.v:89666.3-89684.6" + wire width 2 $1\dec31_dec_sub0_cry_in[1:0] + attribute \src "libresoc.v:89742.3-89760.6" + wire $1\dec31_dec_sub0_cry_out[0:0] + attribute \src "libresoc.v:89837.3-89855.6" + wire width 5 $1\dec31_dec_sub0_form[4:0] + attribute \src "libresoc.v:89419.3-89437.6" + wire width 13 $1\dec31_dec_sub0_function_unit[12:0] + attribute \src "libresoc.v:89951.3-89969.6" + wire width 3 $1\dec31_dec_sub0_in1_sel[2:0] + attribute \src "libresoc.v:89970.3-89988.6" + wire width 4 $1\dec31_dec_sub0_in2_sel[3:0] + attribute \src "libresoc.v:89989.3-90007.6" + wire width 2 $1\dec31_dec_sub0_in3_sel[1:0] + attribute \src "libresoc.v:89628.3-89646.6" + wire width 7 $1\dec31_dec_sub0_internal_op[6:0] + attribute \src "libresoc.v:89704.3-89722.6" + wire $1\dec31_dec_sub0_inv_a[0:0] + attribute \src "libresoc.v:89723.3-89741.6" + wire $1\dec31_dec_sub0_inv_out[0:0] + attribute \src "libresoc.v:89818.3-89836.6" + wire $1\dec31_dec_sub0_is_32b[0:0] + attribute \src "libresoc.v:89590.3-89608.6" + wire width 4 $1\dec31_dec_sub0_ldst_len[3:0] + attribute \src "libresoc.v:89875.3-89893.6" + wire $1\dec31_dec_sub0_lk[0:0] + attribute \src "libresoc.v:90008.3-90026.6" + wire width 2 $1\dec31_dec_sub0_out_sel[1:0] + attribute \src "libresoc.v:89647.3-89665.6" + wire width 2 $1\dec31_dec_sub0_rc_sel[1:0] + attribute \src "libresoc.v:89799.3-89817.6" + wire $1\dec31_dec_sub0_rsrv[0:0] + attribute \src "libresoc.v:89894.3-89912.6" + wire $1\dec31_dec_sub0_sgl_pipe[0:0] + attribute \src "libresoc.v:89856.3-89874.6" + wire $1\dec31_dec_sub0_sgn[0:0] + attribute \src "libresoc.v:89780.3-89798.6" + wire $1\dec31_dec_sub0_sgn_ext[0:0] + attribute \src "libresoc.v:89552.3-89570.6" + wire width 3 $1\dec31_dec_sub0_sv_cr_in[2:0] + attribute \src "libresoc.v:89571.3-89589.6" + wire width 3 $1\dec31_dec_sub0_sv_cr_out[2:0] + attribute \src "libresoc.v:89476.3-89494.6" + wire width 3 $1\dec31_dec_sub0_sv_in1[2:0] + attribute \src "libresoc.v:89495.3-89513.6" + wire width 3 $1\dec31_dec_sub0_sv_in2[2:0] + attribute \src "libresoc.v:89514.3-89532.6" + wire width 3 $1\dec31_dec_sub0_sv_in3[2:0] + attribute \src "libresoc.v:89533.3-89551.6" + wire width 3 $1\dec31_dec_sub0_sv_out[2:0] + attribute \src "libresoc.v:89609.3-89627.6" + wire width 2 $1\dec31_dec_sub0_upd[1:0] + attribute \enum_base_type "SVEtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "EXTRA2" + attribute \enum_value_10 "EXTRA3" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 5 \dec31_dec_sub0_SV_Etype + attribute \enum_base_type "SVPtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "P1" + attribute \enum_value_10 "P2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 6 \dec31_dec_sub0_SV_Ptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 8 output 4 \dec31_dec_sub0_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 26 \dec31_dec_sub0_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 11 \dec31_dec_sub0_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 12 \dec31_dec_sub0_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 22 \dec31_dec_sub0_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 25 \dec31_dec_sub0_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 5 output 3 \dec31_dec_sub0_form + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 13 output 1 \dec31_dec_sub0_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 7 \dec31_dec_sub0_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 8 \dec31_dec_sub0_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 9 \dec31_dec_sub0_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 output 2 \dec31_dec_sub0_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 23 \dec31_dec_sub0_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 24 \dec31_dec_sub0_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 29 \dec31_dec_sub0_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 19 \dec31_dec_sub0_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 31 \dec31_dec_sub0_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 10 \dec31_dec_sub0_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 21 \dec31_dec_sub0_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 28 \dec31_dec_sub0_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 32 \dec31_dec_sub0_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 30 \dec31_dec_sub0_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 27 \dec31_dec_sub0_sgn_ext + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 17 \dec31_dec_sub0_sv_cr_in + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 18 \dec31_dec_sub0_sv_cr_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 13 \dec31_dec_sub0_sv_in1 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 14 \dec31_dec_sub0_sv_in2 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 15 \dec31_dec_sub0_sv_in3 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 16 \dec31_dec_sub0_sv_out + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 20 \dec31_dec_sub0_upd + attribute \src "libresoc.v:89085.7-89085.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + wire width 32 input 33 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + wire width 5 \opcode_switch + attribute \src "libresoc.v:89085.7-89085.20" + process $proc$libresoc.v:89085$3831 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:89419.3-89437.6" + process $proc$libresoc.v:89419$3799 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_function_unit[12:0] $1\dec31_dec_sub0_function_unit[12:0] + attribute \src "libresoc.v:89420.5-89420.29" + switch \initial + attribute \src "libresoc.v:89420.9-89420.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_function_unit[12:0] 13'0000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_function_unit[12:0] 13'0000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_function_unit[12:0] 13'0000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_function_unit[12:0] 13'0000001000000 + case + assign $1\dec31_dec_sub0_function_unit[12:0] 13'0000000000000 + end + sync always + update \dec31_dec_sub0_function_unit $0\dec31_dec_sub0_function_unit[12:0] + end + attribute \src "libresoc.v:89438.3-89456.6" + process $proc$libresoc.v:89438$3800 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_cr_in[2:0] $1\dec31_dec_sub0_cr_in[2:0] + attribute \src "libresoc.v:89439.5-89439.29" + switch \initial + attribute \src "libresoc.v:89439.9-89439.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_cr_in[2:0] 3'011 + case + assign $1\dec31_dec_sub0_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub0_cr_in $0\dec31_dec_sub0_cr_in[2:0] + end + attribute \src "libresoc.v:89457.3-89475.6" + process $proc$libresoc.v:89457$3801 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_cr_out[2:0] $1\dec31_dec_sub0_cr_out[2:0] + attribute \src "libresoc.v:89458.5-89458.29" + switch \initial + attribute \src "libresoc.v:89458.9-89458.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_cr_out[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_cr_out[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_cr_out[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_cr_out[2:0] 3'000 + case + assign $1\dec31_dec_sub0_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub0_cr_out $0\dec31_dec_sub0_cr_out[2:0] + end + attribute \src "libresoc.v:89476.3-89494.6" + process $proc$libresoc.v:89476$3802 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_sv_in1[2:0] $1\dec31_dec_sub0_sv_in1[2:0] + attribute \src "libresoc.v:89477.5-89477.29" + switch \initial + attribute \src "libresoc.v:89477.9-89477.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_sv_in1[2:0] 3'000 + case + assign $1\dec31_dec_sub0_sv_in1[2:0] 3'000 + end + sync always + update \dec31_dec_sub0_sv_in1 $0\dec31_dec_sub0_sv_in1[2:0] + end + attribute \src "libresoc.v:89495.3-89513.6" + process $proc$libresoc.v:89495$3803 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_sv_in2[2:0] $1\dec31_dec_sub0_sv_in2[2:0] + attribute \src "libresoc.v:89496.5-89496.29" + switch \initial + attribute \src "libresoc.v:89496.9-89496.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_sv_in2[2:0] 3'000 + case + assign $1\dec31_dec_sub0_sv_in2[2:0] 3'000 + end + sync always + update \dec31_dec_sub0_sv_in2 $0\dec31_dec_sub0_sv_in2[2:0] + end + attribute \src "libresoc.v:89514.3-89532.6" + process $proc$libresoc.v:89514$3804 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_sv_in3[2:0] $1\dec31_dec_sub0_sv_in3[2:0] + attribute \src "libresoc.v:89515.5-89515.29" + switch \initial + attribute \src "libresoc.v:89515.9-89515.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_sv_in3[2:0] 3'000 + case + assign $1\dec31_dec_sub0_sv_in3[2:0] 3'000 + end + sync always + update \dec31_dec_sub0_sv_in3 $0\dec31_dec_sub0_sv_in3[2:0] + end + attribute \src "libresoc.v:89533.3-89551.6" + process $proc$libresoc.v:89533$3805 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_sv_out[2:0] $1\dec31_dec_sub0_sv_out[2:0] + attribute \src "libresoc.v:89534.5-89534.29" + switch \initial + attribute \src "libresoc.v:89534.9-89534.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_sv_out[2:0] 3'001 + case + assign $1\dec31_dec_sub0_sv_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub0_sv_out $0\dec31_dec_sub0_sv_out[2:0] + end + attribute \src "libresoc.v:89552.3-89570.6" + process $proc$libresoc.v:89552$3806 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_sv_cr_in[2:0] $1\dec31_dec_sub0_sv_cr_in[2:0] + attribute \src "libresoc.v:89553.5-89553.29" + switch \initial + attribute \src "libresoc.v:89553.9-89553.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_sv_cr_in[2:0] 3'010 + case + assign $1\dec31_dec_sub0_sv_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub0_sv_cr_in $0\dec31_dec_sub0_sv_cr_in[2:0] + end + attribute \src "libresoc.v:89571.3-89589.6" + process $proc$libresoc.v:89571$3807 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_sv_cr_out[2:0] $1\dec31_dec_sub0_sv_cr_out[2:0] + attribute \src "libresoc.v:89572.5-89572.29" + switch \initial + attribute \src "libresoc.v:89572.9-89572.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_sv_cr_out[2:0] 3'000 + case + assign $1\dec31_dec_sub0_sv_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub0_sv_cr_out $0\dec31_dec_sub0_sv_cr_out[2:0] + end + attribute \src "libresoc.v:89590.3-89608.6" + process $proc$libresoc.v:89590$3808 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_ldst_len[3:0] $1\dec31_dec_sub0_ldst_len[3:0] + attribute \src "libresoc.v:89591.5-89591.29" + switch \initial + attribute \src "libresoc.v:89591.9-89591.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_ldst_len[3:0] 4'0000 + case + assign $1\dec31_dec_sub0_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub0_ldst_len $0\dec31_dec_sub0_ldst_len[3:0] + end + attribute \src "libresoc.v:89609.3-89627.6" + process $proc$libresoc.v:89609$3809 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_upd[1:0] $1\dec31_dec_sub0_upd[1:0] + attribute \src "libresoc.v:89610.5-89610.29" + switch \initial + attribute \src "libresoc.v:89610.9-89610.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_upd[1:0] 2'00 + case + assign $1\dec31_dec_sub0_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub0_upd $0\dec31_dec_sub0_upd[1:0] + end + attribute \src "libresoc.v:89628.3-89646.6" + process $proc$libresoc.v:89628$3810 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_internal_op[6:0] $1\dec31_dec_sub0_internal_op[6:0] + attribute \src "libresoc.v:89629.5-89629.29" + switch \initial + attribute \src "libresoc.v:89629.9-89629.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_internal_op[6:0] 7'0001010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_internal_op[6:0] 7'0001100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_internal_op[6:0] 7'0001010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_internal_op[6:0] 7'0111011 + case + assign $1\dec31_dec_sub0_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub0_internal_op $0\dec31_dec_sub0_internal_op[6:0] + end + attribute \src "libresoc.v:89647.3-89665.6" + process $proc$libresoc.v:89647$3811 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_rc_sel[1:0] $1\dec31_dec_sub0_rc_sel[1:0] + attribute \src "libresoc.v:89648.5-89648.29" + switch \initial + attribute \src "libresoc.v:89648.9-89648.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_rc_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub0_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub0_rc_sel $0\dec31_dec_sub0_rc_sel[1:0] + end + attribute \src "libresoc.v:89666.3-89684.6" + process $proc$libresoc.v:89666$3812 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_cry_in[1:0] $1\dec31_dec_sub0_cry_in[1:0] + attribute \src "libresoc.v:89667.5-89667.29" + switch \initial + attribute \src "libresoc.v:89667.9-89667.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_cry_in[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_cry_in[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_cry_in[1:0] 2'00 + case + assign $1\dec31_dec_sub0_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub0_cry_in $0\dec31_dec_sub0_cry_in[1:0] + end + attribute \src "libresoc.v:89685.3-89703.6" + process $proc$libresoc.v:89685$3813 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_asmcode[7:0] $1\dec31_dec_sub0_asmcode[7:0] + attribute \src "libresoc.v:89686.5-89686.29" + switch \initial + attribute \src "libresoc.v:89686.9-89686.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_asmcode[7:0] 8'00011010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_asmcode[7:0] 8'00011100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_asmcode[7:0] 8'00011110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_asmcode[7:0] 8'10011011 + case + assign $1\dec31_dec_sub0_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub0_asmcode $0\dec31_dec_sub0_asmcode[7:0] + end + attribute \src "libresoc.v:89704.3-89722.6" + process $proc$libresoc.v:89704$3814 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_inv_a[0:0] $1\dec31_dec_sub0_inv_a[0:0] + attribute \src "libresoc.v:89705.5-89705.29" + switch \initial + attribute \src "libresoc.v:89705.9-89705.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_inv_a[0:0] 1'0 + case + assign $1\dec31_dec_sub0_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub0_inv_a $0\dec31_dec_sub0_inv_a[0:0] + end + attribute \src "libresoc.v:89723.3-89741.6" + process $proc$libresoc.v:89723$3815 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_inv_out[0:0] $1\dec31_dec_sub0_inv_out[0:0] + attribute \src "libresoc.v:89724.5-89724.29" + switch \initial + attribute \src "libresoc.v:89724.9-89724.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub0_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub0_inv_out $0\dec31_dec_sub0_inv_out[0:0] + end + attribute \src "libresoc.v:89742.3-89760.6" + process $proc$libresoc.v:89742$3816 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_cry_out[0:0] $1\dec31_dec_sub0_cry_out[0:0] + attribute \src "libresoc.v:89743.5-89743.29" + switch \initial + attribute \src "libresoc.v:89743.9-89743.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_cry_out[0:0] 1'0 + case + assign $1\dec31_dec_sub0_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub0_cry_out $0\dec31_dec_sub0_cry_out[0:0] + end + attribute \src "libresoc.v:89761.3-89779.6" + process $proc$libresoc.v:89761$3817 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_br[0:0] $1\dec31_dec_sub0_br[0:0] + attribute \src "libresoc.v:89762.5-89762.29" + switch \initial + attribute \src "libresoc.v:89762.9-89762.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_br[0:0] 1'0 + case + assign $1\dec31_dec_sub0_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub0_br $0\dec31_dec_sub0_br[0:0] + end + attribute \src "libresoc.v:89780.3-89798.6" + process $proc$libresoc.v:89780$3818 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_sgn_ext[0:0] $1\dec31_dec_sub0_sgn_ext[0:0] + attribute \src "libresoc.v:89781.5-89781.29" + switch \initial + attribute \src "libresoc.v:89781.9-89781.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub0_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub0_sgn_ext $0\dec31_dec_sub0_sgn_ext[0:0] + end + attribute \src "libresoc.v:89799.3-89817.6" + process $proc$libresoc.v:89799$3819 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_rsrv[0:0] $1\dec31_dec_sub0_rsrv[0:0] + attribute \src "libresoc.v:89800.5-89800.29" + switch \initial + attribute \src "libresoc.v:89800.9-89800.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub0_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub0_rsrv $0\dec31_dec_sub0_rsrv[0:0] + end + attribute \src "libresoc.v:89818.3-89836.6" + process $proc$libresoc.v:89818$3820 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_is_32b[0:0] $1\dec31_dec_sub0_is_32b[0:0] + attribute \src "libresoc.v:89819.5-89819.29" + switch \initial + attribute \src "libresoc.v:89819.9-89819.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_is_32b[0:0] 1'0 + case + assign $1\dec31_dec_sub0_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub0_is_32b $0\dec31_dec_sub0_is_32b[0:0] + end + attribute \src "libresoc.v:89837.3-89855.6" + process $proc$libresoc.v:89837$3821 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_form[4:0] $1\dec31_dec_sub0_form[4:0] + attribute \src "libresoc.v:89838.5-89838.29" + switch \initial + attribute \src "libresoc.v:89838.9-89838.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_form[4:0] 5'11000 + case + assign $1\dec31_dec_sub0_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub0_form $0\dec31_dec_sub0_form[4:0] + end + attribute \src "libresoc.v:89856.3-89874.6" + process $proc$libresoc.v:89856$3822 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_sgn[0:0] $1\dec31_dec_sub0_sgn[0:0] + attribute \src "libresoc.v:89857.5-89857.29" + switch \initial + attribute \src "libresoc.v:89857.9-89857.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_sgn[0:0] 1'0 + case + assign $1\dec31_dec_sub0_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub0_sgn $0\dec31_dec_sub0_sgn[0:0] + end + attribute \src "libresoc.v:89875.3-89893.6" + process $proc$libresoc.v:89875$3823 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_lk[0:0] $1\dec31_dec_sub0_lk[0:0] + attribute \src "libresoc.v:89876.5-89876.29" + switch \initial + attribute \src "libresoc.v:89876.9-89876.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub0_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub0_lk $0\dec31_dec_sub0_lk[0:0] + end + attribute \src "libresoc.v:89894.3-89912.6" + process $proc$libresoc.v:89894$3824 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_sgl_pipe[0:0] $1\dec31_dec_sub0_sgl_pipe[0:0] + attribute \src "libresoc.v:89895.5-89895.29" + switch \initial + attribute \src "libresoc.v:89895.9-89895.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_sgl_pipe[0:0] 1'0 + case + assign $1\dec31_dec_sub0_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub0_sgl_pipe $0\dec31_dec_sub0_sgl_pipe[0:0] + end + attribute \src "libresoc.v:89913.3-89931.6" + process $proc$libresoc.v:89913$3825 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_SV_Etype[1:0] $1\dec31_dec_sub0_SV_Etype[1:0] + attribute \src "libresoc.v:89914.5-89914.29" + switch \initial + attribute \src "libresoc.v:89914.9-89914.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_SV_Etype[1:0] 2'10 + case + assign $1\dec31_dec_sub0_SV_Etype[1:0] 2'00 + end + sync always + update \dec31_dec_sub0_SV_Etype $0\dec31_dec_sub0_SV_Etype[1:0] + end + attribute \src "libresoc.v:89932.3-89950.6" + process $proc$libresoc.v:89932$3826 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_SV_Ptype[1:0] $1\dec31_dec_sub0_SV_Ptype[1:0] + attribute \src "libresoc.v:89933.5-89933.29" + switch \initial + attribute \src "libresoc.v:89933.9-89933.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_SV_Ptype[1:0] 2'10 + case + assign $1\dec31_dec_sub0_SV_Ptype[1:0] 2'00 + end + sync always + update \dec31_dec_sub0_SV_Ptype $0\dec31_dec_sub0_SV_Ptype[1:0] + end + attribute \src "libresoc.v:89951.3-89969.6" + process $proc$libresoc.v:89951$3827 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_in1_sel[2:0] $1\dec31_dec_sub0_in1_sel[2:0] + attribute \src "libresoc.v:89952.5-89952.29" + switch \initial + attribute \src "libresoc.v:89952.9-89952.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_in1_sel[2:0] 3'000 + case + assign $1\dec31_dec_sub0_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub0_in1_sel $0\dec31_dec_sub0_in1_sel[2:0] + end + attribute \src "libresoc.v:89970.3-89988.6" + process $proc$libresoc.v:89970$3828 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_in2_sel[3:0] $1\dec31_dec_sub0_in2_sel[3:0] + attribute \src "libresoc.v:89971.5-89971.29" + switch \initial + attribute \src "libresoc.v:89971.9-89971.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_in2_sel[3:0] 4'0000 + case + assign $1\dec31_dec_sub0_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub0_in2_sel $0\dec31_dec_sub0_in2_sel[3:0] + end + attribute \src "libresoc.v:89989.3-90007.6" + process $proc$libresoc.v:89989$3829 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_in3_sel[1:0] $1\dec31_dec_sub0_in3_sel[1:0] + attribute \src "libresoc.v:89990.5-89990.29" + switch \initial + attribute \src "libresoc.v:89990.9-89990.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_in3_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub0_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub0_in3_sel $0\dec31_dec_sub0_in3_sel[1:0] + end + attribute \src "libresoc.v:90008.3-90026.6" + process $proc$libresoc.v:90008$3830 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_out_sel[1:0] $1\dec31_dec_sub0_out_sel[1:0] + attribute \src "libresoc.v:90009.5-90009.29" + switch \initial + attribute \src "libresoc.v:90009.9-90009.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_out_sel[1:0] 2'01 + case + assign $1\dec31_dec_sub0_out_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub0_out_sel $0\dec31_dec_sub0_out_sel[1:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:90032.1-91552.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub10" +attribute \generator "nMigen" +module \dec31_dec_sub10 + attribute \src "libresoc.v:91329.3-91365.6" + wire width 2 $0\dec31_dec_sub10_SV_Etype[1:0] + attribute \src "libresoc.v:91366.3-91402.6" + wire width 2 $0\dec31_dec_sub10_SV_Ptype[1:0] + attribute \src "libresoc.v:90885.3-90921.6" + wire width 8 $0\dec31_dec_sub10_asmcode[7:0] + attribute \src "libresoc.v:91033.3-91069.6" + wire $0\dec31_dec_sub10_br[0:0] + attribute \src "libresoc.v:90404.3-90440.6" + wire width 3 $0\dec31_dec_sub10_cr_in[2:0] + attribute \src "libresoc.v:90441.3-90477.6" + wire width 3 $0\dec31_dec_sub10_cr_out[2:0] + attribute \src "libresoc.v:90848.3-90884.6" + wire width 2 $0\dec31_dec_sub10_cry_in[1:0] + attribute \src "libresoc.v:90996.3-91032.6" + wire $0\dec31_dec_sub10_cry_out[0:0] + attribute \src "libresoc.v:91181.3-91217.6" + wire width 5 $0\dec31_dec_sub10_form[4:0] + attribute \src "libresoc.v:90367.3-90403.6" + wire width 13 $0\dec31_dec_sub10_function_unit[12:0] + attribute \src "libresoc.v:91403.3-91439.6" + wire width 3 $0\dec31_dec_sub10_in1_sel[2:0] + attribute \src "libresoc.v:91440.3-91476.6" + wire width 4 $0\dec31_dec_sub10_in2_sel[3:0] + attribute \src "libresoc.v:91477.3-91513.6" + wire width 2 $0\dec31_dec_sub10_in3_sel[1:0] + attribute \src "libresoc.v:90774.3-90810.6" + wire width 7 $0\dec31_dec_sub10_internal_op[6:0] + attribute \src "libresoc.v:90922.3-90958.6" + wire $0\dec31_dec_sub10_inv_a[0:0] + attribute \src "libresoc.v:90959.3-90995.6" + wire $0\dec31_dec_sub10_inv_out[0:0] + attribute \src "libresoc.v:91144.3-91180.6" + wire $0\dec31_dec_sub10_is_32b[0:0] + attribute \src "libresoc.v:90700.3-90736.6" + wire width 4 $0\dec31_dec_sub10_ldst_len[3:0] + attribute \src "libresoc.v:91255.3-91291.6" + wire $0\dec31_dec_sub10_lk[0:0] + attribute \src "libresoc.v:91514.3-91550.6" + wire width 2 $0\dec31_dec_sub10_out_sel[1:0] + attribute \src "libresoc.v:90811.3-90847.6" + wire width 2 $0\dec31_dec_sub10_rc_sel[1:0] + attribute \src "libresoc.v:91107.3-91143.6" + wire $0\dec31_dec_sub10_rsrv[0:0] + attribute \src "libresoc.v:91292.3-91328.6" + wire $0\dec31_dec_sub10_sgl_pipe[0:0] + attribute \src "libresoc.v:91218.3-91254.6" + wire $0\dec31_dec_sub10_sgn[0:0] + attribute \src "libresoc.v:91070.3-91106.6" + wire $0\dec31_dec_sub10_sgn_ext[0:0] + attribute \src "libresoc.v:90626.3-90662.6" + wire width 3 $0\dec31_dec_sub10_sv_cr_in[2:0] + attribute \src "libresoc.v:90663.3-90699.6" + wire width 3 $0\dec31_dec_sub10_sv_cr_out[2:0] + attribute \src "libresoc.v:90478.3-90514.6" + wire width 3 $0\dec31_dec_sub10_sv_in1[2:0] + attribute \src "libresoc.v:90515.3-90551.6" + wire width 3 $0\dec31_dec_sub10_sv_in2[2:0] + attribute \src "libresoc.v:90552.3-90588.6" + wire width 3 $0\dec31_dec_sub10_sv_in3[2:0] + attribute \src "libresoc.v:90589.3-90625.6" + wire width 3 $0\dec31_dec_sub10_sv_out[2:0] + attribute \src "libresoc.v:90737.3-90773.6" + wire width 2 $0\dec31_dec_sub10_upd[1:0] + attribute \src "libresoc.v:90033.7-90033.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:91329.3-91365.6" + wire width 2 $1\dec31_dec_sub10_SV_Etype[1:0] + attribute \src "libresoc.v:91366.3-91402.6" + wire width 2 $1\dec31_dec_sub10_SV_Ptype[1:0] + attribute \src "libresoc.v:90885.3-90921.6" + wire width 8 $1\dec31_dec_sub10_asmcode[7:0] + attribute \src "libresoc.v:91033.3-91069.6" + wire $1\dec31_dec_sub10_br[0:0] + attribute \src "libresoc.v:90404.3-90440.6" + wire width 3 $1\dec31_dec_sub10_cr_in[2:0] + attribute \src "libresoc.v:90441.3-90477.6" + wire width 3 $1\dec31_dec_sub10_cr_out[2:0] + attribute \src "libresoc.v:90848.3-90884.6" + wire width 2 $1\dec31_dec_sub10_cry_in[1:0] + attribute \src "libresoc.v:90996.3-91032.6" + wire $1\dec31_dec_sub10_cry_out[0:0] + attribute \src "libresoc.v:91181.3-91217.6" + wire width 5 $1\dec31_dec_sub10_form[4:0] + attribute \src "libresoc.v:90367.3-90403.6" + wire width 13 $1\dec31_dec_sub10_function_unit[12:0] + attribute \src "libresoc.v:91403.3-91439.6" + wire width 3 $1\dec31_dec_sub10_in1_sel[2:0] + attribute \src "libresoc.v:91440.3-91476.6" + wire width 4 $1\dec31_dec_sub10_in2_sel[3:0] + attribute \src "libresoc.v:91477.3-91513.6" + wire width 2 $1\dec31_dec_sub10_in3_sel[1:0] + attribute \src "libresoc.v:90774.3-90810.6" + wire width 7 $1\dec31_dec_sub10_internal_op[6:0] + attribute \src "libresoc.v:90922.3-90958.6" + wire $1\dec31_dec_sub10_inv_a[0:0] + attribute \src "libresoc.v:90959.3-90995.6" + wire $1\dec31_dec_sub10_inv_out[0:0] + attribute \src "libresoc.v:91144.3-91180.6" + wire $1\dec31_dec_sub10_is_32b[0:0] + attribute \src "libresoc.v:90700.3-90736.6" + wire width 4 $1\dec31_dec_sub10_ldst_len[3:0] + attribute \src "libresoc.v:91255.3-91291.6" + wire $1\dec31_dec_sub10_lk[0:0] + attribute \src "libresoc.v:91514.3-91550.6" + wire width 2 $1\dec31_dec_sub10_out_sel[1:0] + attribute \src "libresoc.v:90811.3-90847.6" + wire width 2 $1\dec31_dec_sub10_rc_sel[1:0] + attribute \src "libresoc.v:91107.3-91143.6" + wire $1\dec31_dec_sub10_rsrv[0:0] + attribute \src "libresoc.v:91292.3-91328.6" + wire $1\dec31_dec_sub10_sgl_pipe[0:0] + attribute \src "libresoc.v:91218.3-91254.6" + wire $1\dec31_dec_sub10_sgn[0:0] + attribute \src "libresoc.v:91070.3-91106.6" + wire $1\dec31_dec_sub10_sgn_ext[0:0] + attribute \src "libresoc.v:90626.3-90662.6" + wire width 3 $1\dec31_dec_sub10_sv_cr_in[2:0] + attribute \src "libresoc.v:90663.3-90699.6" + wire width 3 $1\dec31_dec_sub10_sv_cr_out[2:0] + attribute \src "libresoc.v:90478.3-90514.6" + wire width 3 $1\dec31_dec_sub10_sv_in1[2:0] + attribute \src "libresoc.v:90515.3-90551.6" + wire width 3 $1\dec31_dec_sub10_sv_in2[2:0] + attribute \src "libresoc.v:90552.3-90588.6" + wire width 3 $1\dec31_dec_sub10_sv_in3[2:0] + attribute \src "libresoc.v:90589.3-90625.6" + wire width 3 $1\dec31_dec_sub10_sv_out[2:0] + attribute \src "libresoc.v:90737.3-90773.6" + wire width 2 $1\dec31_dec_sub10_upd[1:0] + attribute \enum_base_type "SVEtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "EXTRA2" + attribute \enum_value_10 "EXTRA3" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 5 \dec31_dec_sub10_SV_Etype + attribute \enum_base_type "SVPtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "P1" + attribute \enum_value_10 "P2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 6 \dec31_dec_sub10_SV_Ptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 8 output 4 \dec31_dec_sub10_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 26 \dec31_dec_sub10_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 11 \dec31_dec_sub10_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 12 \dec31_dec_sub10_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 22 \dec31_dec_sub10_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 25 \dec31_dec_sub10_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 5 output 3 \dec31_dec_sub10_form + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 13 output 1 \dec31_dec_sub10_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 7 \dec31_dec_sub10_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 8 \dec31_dec_sub10_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 9 \dec31_dec_sub10_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 output 2 \dec31_dec_sub10_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 23 \dec31_dec_sub10_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 24 \dec31_dec_sub10_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 29 \dec31_dec_sub10_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 19 \dec31_dec_sub10_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 31 \dec31_dec_sub10_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 10 \dec31_dec_sub10_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 21 \dec31_dec_sub10_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 28 \dec31_dec_sub10_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 32 \dec31_dec_sub10_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 30 \dec31_dec_sub10_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 27 \dec31_dec_sub10_sgn_ext + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 17 \dec31_dec_sub10_sv_cr_in + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 18 \dec31_dec_sub10_sv_cr_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 13 \dec31_dec_sub10_sv_in1 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 14 \dec31_dec_sub10_sv_in2 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 15 \dec31_dec_sub10_sv_in3 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 16 \dec31_dec_sub10_sv_out + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 20 \dec31_dec_sub10_upd + attribute \src "libresoc.v:90033.7-90033.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + wire width 32 input 33 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + wire width 5 \opcode_switch + attribute \src "libresoc.v:90033.7-90033.20" + process $proc$libresoc.v:90033$3864 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:90367.3-90403.6" + process $proc$libresoc.v:90367$3832 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_function_unit[12:0] $1\dec31_dec_sub10_function_unit[12:0] + attribute \src "libresoc.v:90368.5-90368.29" + switch \initial + attribute \src "libresoc.v:90368.9-90368.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_function_unit[12:0] 13'0000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_function_unit[12:0] 13'0000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_function_unit[12:0] 13'0000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_function_unit[12:0] 13'0000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_function_unit[12:0] 13'0000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_function_unit[12:0] 13'0000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_function_unit[12:0] 13'0000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_function_unit[12:0] 13'0000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_function_unit[12:0] 13'0000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_function_unit[12:0] 13'0000000000010 + case + assign $1\dec31_dec_sub10_function_unit[12:0] 13'0000000000000 + end + sync always + update \dec31_dec_sub10_function_unit $0\dec31_dec_sub10_function_unit[12:0] + end + attribute \src "libresoc.v:90404.3-90440.6" + process $proc$libresoc.v:90404$3833 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_cr_in[2:0] $1\dec31_dec_sub10_cr_in[2:0] + attribute \src "libresoc.v:90405.5-90405.29" + switch \initial + attribute \src "libresoc.v:90405.9-90405.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub10_cr_in $0\dec31_dec_sub10_cr_in[2:0] + end + attribute \src "libresoc.v:90441.3-90477.6" + process $proc$libresoc.v:90441$3834 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_cr_out[2:0] $1\dec31_dec_sub10_cr_out[2:0] + attribute \src "libresoc.v:90442.5-90442.29" + switch \initial + attribute \src "libresoc.v:90442.9-90442.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 + case + assign $1\dec31_dec_sub10_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub10_cr_out $0\dec31_dec_sub10_cr_out[2:0] + end + attribute \src "libresoc.v:90478.3-90514.6" + process $proc$libresoc.v:90478$3835 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_sv_in1[2:0] $1\dec31_dec_sub10_sv_in1[2:0] + attribute \src "libresoc.v:90479.5-90479.29" + switch \initial + attribute \src "libresoc.v:90479.9-90479.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_sv_in1[2:0] 3'010 + case + assign $1\dec31_dec_sub10_sv_in1[2:0] 3'000 + end + sync always + update \dec31_dec_sub10_sv_in1 $0\dec31_dec_sub10_sv_in1[2:0] + end + attribute \src "libresoc.v:90515.3-90551.6" + process $proc$libresoc.v:90515$3836 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_sv_in2[2:0] $1\dec31_dec_sub10_sv_in2[2:0] + attribute \src "libresoc.v:90516.5-90516.29" + switch \initial + attribute \src "libresoc.v:90516.9-90516.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_sv_in2[2:0] 3'000 + case + assign $1\dec31_dec_sub10_sv_in2[2:0] 3'000 + end + sync always + update \dec31_dec_sub10_sv_in2 $0\dec31_dec_sub10_sv_in2[2:0] + end + attribute \src "libresoc.v:90552.3-90588.6" + process $proc$libresoc.v:90552$3837 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_sv_in3[2:0] $1\dec31_dec_sub10_sv_in3[2:0] + attribute \src "libresoc.v:90553.5-90553.29" + switch \initial + attribute \src "libresoc.v:90553.9-90553.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_sv_in3[2:0] 3'000 + case + assign $1\dec31_dec_sub10_sv_in3[2:0] 3'000 + end + sync always + update \dec31_dec_sub10_sv_in3 $0\dec31_dec_sub10_sv_in3[2:0] + end + attribute \src "libresoc.v:90589.3-90625.6" + process $proc$libresoc.v:90589$3838 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_sv_out[2:0] $1\dec31_dec_sub10_sv_out[2:0] + attribute \src "libresoc.v:90590.5-90590.29" + switch \initial + attribute \src "libresoc.v:90590.9-90590.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_sv_out[2:0] 3'001 + case + assign $1\dec31_dec_sub10_sv_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub10_sv_out $0\dec31_dec_sub10_sv_out[2:0] + end + attribute \src "libresoc.v:90626.3-90662.6" + process $proc$libresoc.v:90626$3839 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_sv_cr_in[2:0] $1\dec31_dec_sub10_sv_cr_in[2:0] + attribute \src "libresoc.v:90627.5-90627.29" + switch \initial + attribute \src "libresoc.v:90627.9-90627.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_sv_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub10_sv_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub10_sv_cr_in $0\dec31_dec_sub10_sv_cr_in[2:0] + end + attribute \src "libresoc.v:90663.3-90699.6" + process $proc$libresoc.v:90663$3840 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_sv_cr_out[2:0] $1\dec31_dec_sub10_sv_cr_out[2:0] + attribute \src "libresoc.v:90664.5-90664.29" + switch \initial + attribute \src "libresoc.v:90664.9-90664.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_sv_cr_out[2:0] 3'001 + case + assign $1\dec31_dec_sub10_sv_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub10_sv_cr_out $0\dec31_dec_sub10_sv_cr_out[2:0] + end + attribute \src "libresoc.v:90700.3-90736.6" + process $proc$libresoc.v:90700$3841 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_ldst_len[3:0] $1\dec31_dec_sub10_ldst_len[3:0] + attribute \src "libresoc.v:90701.5-90701.29" + switch \initial + attribute \src "libresoc.v:90701.9-90701.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 + case + assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub10_ldst_len $0\dec31_dec_sub10_ldst_len[3:0] + end + attribute \src "libresoc.v:90737.3-90773.6" + process $proc$libresoc.v:90737$3842 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_upd[1:0] $1\dec31_dec_sub10_upd[1:0] + attribute \src "libresoc.v:90738.5-90738.29" + switch \initial + attribute \src "libresoc.v:90738.9-90738.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_upd[1:0] 2'00 + case + assign $1\dec31_dec_sub10_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub10_upd $0\dec31_dec_sub10_upd[1:0] + end + attribute \src "libresoc.v:90774.3-90810.6" + process $proc$libresoc.v:90774$3843 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_internal_op[6:0] $1\dec31_dec_sub10_internal_op[6:0] + attribute \src "libresoc.v:90775.5-90775.29" + switch \initial + attribute \src "libresoc.v:90775.9-90775.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 + case + assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub10_internal_op $0\dec31_dec_sub10_internal_op[6:0] + end + attribute \src "libresoc.v:90811.3-90847.6" + process $proc$libresoc.v:90811$3844 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_rc_sel[1:0] $1\dec31_dec_sub10_rc_sel[1:0] + attribute \src "libresoc.v:90812.5-90812.29" + switch \initial + attribute \src "libresoc.v:90812.9-90812.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 + case + assign $1\dec31_dec_sub10_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub10_rc_sel $0\dec31_dec_sub10_rc_sel[1:0] + end + attribute \src "libresoc.v:90848.3-90884.6" + process $proc$libresoc.v:90848$3845 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_cry_in[1:0] $1\dec31_dec_sub10_cry_in[1:0] + attribute \src "libresoc.v:90849.5-90849.29" + switch \initial + attribute \src "libresoc.v:90849.9-90849.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_cry_in[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_cry_in[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_cry_in[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_cry_in[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_cry_in[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_cry_in[1:0] 2'10 + case + assign $1\dec31_dec_sub10_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub10_cry_in $0\dec31_dec_sub10_cry_in[1:0] + end + attribute \src "libresoc.v:90885.3-90921.6" + process $proc$libresoc.v:90885$3846 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_asmcode[7:0] $1\dec31_dec_sub10_asmcode[7:0] + attribute \src "libresoc.v:90886.5-90886.29" + switch \initial + attribute \src "libresoc.v:90886.9-90886.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_asmcode[7:0] 8'00000001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_asmcode[7:0] 8'00001100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_asmcode[7:0] 8'00000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_asmcode[7:0] 8'00000011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_asmcode[7:0] 8'00000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_asmcode[7:0] 8'00000101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_asmcode[7:0] 8'00001010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_asmcode[7:0] 8'00001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_asmcode[7:0] 8'00001101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_asmcode[7:0] 8'00001110 + case + assign $1\dec31_dec_sub10_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub10_asmcode $0\dec31_dec_sub10_asmcode[7:0] + end + attribute \src "libresoc.v:90922.3-90958.6" + process $proc$libresoc.v:90922$3847 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_inv_a[0:0] $1\dec31_dec_sub10_inv_a[0:0] + attribute \src "libresoc.v:90923.5-90923.29" + switch \initial + attribute \src "libresoc.v:90923.9-90923.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 + case + assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub10_inv_a $0\dec31_dec_sub10_inv_a[0:0] + end + attribute \src "libresoc.v:90959.3-90995.6" + process $proc$libresoc.v:90959$3848 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_inv_out[0:0] $1\dec31_dec_sub10_inv_out[0:0] + attribute \src "libresoc.v:90960.5-90960.29" + switch \initial + attribute \src "libresoc.v:90960.9-90960.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub10_inv_out $0\dec31_dec_sub10_inv_out[0:0] + end + attribute \src "libresoc.v:90996.3-91032.6" + process $proc$libresoc.v:90996$3849 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_cry_out[0:0] $1\dec31_dec_sub10_cry_out[0:0] + attribute \src "libresoc.v:90997.5-90997.29" + switch \initial + attribute \src "libresoc.v:90997.9-90997.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_cry_out[0:0] 1'1 + case + assign $1\dec31_dec_sub10_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub10_cry_out $0\dec31_dec_sub10_cry_out[0:0] + end + attribute \src "libresoc.v:91033.3-91069.6" + process $proc$libresoc.v:91033$3850 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_br[0:0] $1\dec31_dec_sub10_br[0:0] + attribute \src "libresoc.v:91034.5-91034.29" + switch \initial + attribute \src "libresoc.v:91034.9-91034.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_br[0:0] 1'0 + case + assign $1\dec31_dec_sub10_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub10_br $0\dec31_dec_sub10_br[0:0] + end + attribute \src "libresoc.v:91070.3-91106.6" + process $proc$libresoc.v:91070$3851 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_sgn_ext[0:0] $1\dec31_dec_sub10_sgn_ext[0:0] + attribute \src "libresoc.v:91071.5-91071.29" + switch \initial + attribute \src "libresoc.v:91071.9-91071.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub10_sgn_ext $0\dec31_dec_sub10_sgn_ext[0:0] + end + attribute \src "libresoc.v:91107.3-91143.6" + process $proc$libresoc.v:91107$3852 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_rsrv[0:0] $1\dec31_dec_sub10_rsrv[0:0] + attribute \src "libresoc.v:91108.5-91108.29" + switch \initial + attribute \src "libresoc.v:91108.9-91108.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub10_rsrv $0\dec31_dec_sub10_rsrv[0:0] + end + attribute \src "libresoc.v:91144.3-91180.6" + process $proc$libresoc.v:91144$3853 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_is_32b[0:0] $1\dec31_dec_sub10_is_32b[0:0] + attribute \src "libresoc.v:91145.5-91145.29" + switch \initial + attribute \src "libresoc.v:91145.9-91145.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 + case + assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub10_is_32b $0\dec31_dec_sub10_is_32b[0:0] + end + attribute \src "libresoc.v:91181.3-91217.6" + process $proc$libresoc.v:91181$3854 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_form[4:0] $1\dec31_dec_sub10_form[4:0] + attribute \src "libresoc.v:91182.5-91182.29" + switch \initial + attribute \src "libresoc.v:91182.9-91182.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_form[4:0] 5'10001 + case + assign $1\dec31_dec_sub10_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub10_form $0\dec31_dec_sub10_form[4:0] + end + attribute \src "libresoc.v:91218.3-91254.6" + process $proc$libresoc.v:91218$3855 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_sgn[0:0] $1\dec31_dec_sub10_sgn[0:0] + attribute \src "libresoc.v:91219.5-91219.29" + switch \initial + attribute \src "libresoc.v:91219.9-91219.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_sgn[0:0] 1'0 + case + assign $1\dec31_dec_sub10_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub10_sgn $0\dec31_dec_sub10_sgn[0:0] + end + attribute \src "libresoc.v:91255.3-91291.6" + process $proc$libresoc.v:91255$3856 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_lk[0:0] $1\dec31_dec_sub10_lk[0:0] + attribute \src "libresoc.v:91256.5-91256.29" + switch \initial + attribute \src "libresoc.v:91256.9-91256.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub10_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub10_lk $0\dec31_dec_sub10_lk[0:0] + end + attribute \src "libresoc.v:91292.3-91328.6" + process $proc$libresoc.v:91292$3857 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_sgl_pipe[0:0] $1\dec31_dec_sub10_sgl_pipe[0:0] + attribute \src "libresoc.v:91293.5-91293.29" + switch \initial + attribute \src "libresoc.v:91293.9-91293.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 + case + assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub10_sgl_pipe $0\dec31_dec_sub10_sgl_pipe[0:0] + end + attribute \src "libresoc.v:91329.3-91365.6" + process $proc$libresoc.v:91329$3858 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_SV_Etype[1:0] $1\dec31_dec_sub10_SV_Etype[1:0] + attribute \src "libresoc.v:91330.5-91330.29" + switch \initial + attribute \src "libresoc.v:91330.9-91330.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_SV_Etype[1:0] 2'10 + case + assign $1\dec31_dec_sub10_SV_Etype[1:0] 2'00 + end + sync always + update \dec31_dec_sub10_SV_Etype $0\dec31_dec_sub10_SV_Etype[1:0] + end + attribute \src "libresoc.v:91366.3-91402.6" + process $proc$libresoc.v:91366$3859 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_SV_Ptype[1:0] $1\dec31_dec_sub10_SV_Ptype[1:0] + attribute \src "libresoc.v:91367.5-91367.29" + switch \initial + attribute \src "libresoc.v:91367.9-91367.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_SV_Ptype[1:0] 2'10 + case + assign $1\dec31_dec_sub10_SV_Ptype[1:0] 2'00 + end + sync always + update \dec31_dec_sub10_SV_Ptype $0\dec31_dec_sub10_SV_Ptype[1:0] + end + attribute \src "libresoc.v:91403.3-91439.6" + process $proc$libresoc.v:91403$3860 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_in1_sel[2:0] $1\dec31_dec_sub10_in1_sel[2:0] + attribute \src "libresoc.v:91404.5-91404.29" + switch \initial + attribute \src "libresoc.v:91404.9-91404.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 + case + assign $1\dec31_dec_sub10_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub10_in1_sel $0\dec31_dec_sub10_in1_sel[2:0] + end + attribute \src "libresoc.v:91440.3-91476.6" + process $proc$libresoc.v:91440$3861 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_in2_sel[3:0] $1\dec31_dec_sub10_in2_sel[3:0] + attribute \src "libresoc.v:91441.5-91441.29" + switch \initial + attribute \src "libresoc.v:91441.9-91441.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_in2_sel[3:0] 4'1001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_in2_sel[3:0] 4'1001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0000 + case + assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub10_in2_sel $0\dec31_dec_sub10_in2_sel[3:0] + end + attribute \src "libresoc.v:91477.3-91513.6" + process $proc$libresoc.v:91477$3862 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_in3_sel[1:0] $1\dec31_dec_sub10_in3_sel[1:0] + attribute \src "libresoc.v:91478.5-91478.29" + switch \initial + attribute \src "libresoc.v:91478.9-91478.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub10_in3_sel $0\dec31_dec_sub10_in3_sel[1:0] + end + attribute \src "libresoc.v:91514.3-91550.6" + process $proc$libresoc.v:91514$3863 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_out_sel[1:0] $1\dec31_dec_sub10_out_sel[1:0] + attribute \src "libresoc.v:91515.5-91515.29" + switch \initial + attribute \src "libresoc.v:91515.9-91515.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_out_sel[1:0] 2'01 + case + assign $1\dec31_dec_sub10_out_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub10_out_sel $0\dec31_dec_sub10_out_sel[1:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:91556.1-93652.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub11" +attribute \generator "nMigen" +module \dec31_dec_sub11 + attribute \src "libresoc.v:93321.3-93375.6" + wire width 2 $0\dec31_dec_sub11_SV_Etype[1:0] + attribute \src "libresoc.v:93376.3-93430.6" + wire width 2 $0\dec31_dec_sub11_SV_Ptype[1:0] + attribute \src "libresoc.v:92661.3-92715.6" + wire width 8 $0\dec31_dec_sub11_asmcode[7:0] + attribute \src "libresoc.v:92881.3-92935.6" + wire $0\dec31_dec_sub11_br[0:0] + attribute \src "libresoc.v:91946.3-92000.6" + wire width 3 $0\dec31_dec_sub11_cr_in[2:0] + attribute \src "libresoc.v:92001.3-92055.6" + wire width 3 $0\dec31_dec_sub11_cr_out[2:0] + attribute \src "libresoc.v:92606.3-92660.6" + wire width 2 $0\dec31_dec_sub11_cry_in[1:0] + attribute \src "libresoc.v:92826.3-92880.6" + wire $0\dec31_dec_sub11_cry_out[0:0] + attribute \src "libresoc.v:93101.3-93155.6" + wire width 5 $0\dec31_dec_sub11_form[4:0] + attribute \src "libresoc.v:91891.3-91945.6" + wire width 13 $0\dec31_dec_sub11_function_unit[12:0] + attribute \src "libresoc.v:93431.3-93485.6" + wire width 3 $0\dec31_dec_sub11_in1_sel[2:0] + attribute \src "libresoc.v:93486.3-93540.6" + wire width 4 $0\dec31_dec_sub11_in2_sel[3:0] + attribute \src "libresoc.v:93541.3-93595.6" + wire width 2 $0\dec31_dec_sub11_in3_sel[1:0] + attribute \src "libresoc.v:92496.3-92550.6" + wire width 7 $0\dec31_dec_sub11_internal_op[6:0] + attribute \src "libresoc.v:92716.3-92770.6" + wire $0\dec31_dec_sub11_inv_a[0:0] + attribute \src "libresoc.v:92771.3-92825.6" + wire $0\dec31_dec_sub11_inv_out[0:0] + attribute \src "libresoc.v:93046.3-93100.6" + wire $0\dec31_dec_sub11_is_32b[0:0] + attribute \src "libresoc.v:92386.3-92440.6" + wire width 4 $0\dec31_dec_sub11_ldst_len[3:0] + attribute \src "libresoc.v:93211.3-93265.6" + wire $0\dec31_dec_sub11_lk[0:0] + attribute \src "libresoc.v:93596.3-93650.6" + wire width 2 $0\dec31_dec_sub11_out_sel[1:0] + attribute \src "libresoc.v:92551.3-92605.6" + wire width 2 $0\dec31_dec_sub11_rc_sel[1:0] + attribute \src "libresoc.v:92991.3-93045.6" + wire $0\dec31_dec_sub11_rsrv[0:0] + attribute \src "libresoc.v:93266.3-93320.6" + wire $0\dec31_dec_sub11_sgl_pipe[0:0] + attribute \src "libresoc.v:93156.3-93210.6" + wire $0\dec31_dec_sub11_sgn[0:0] + attribute \src "libresoc.v:92936.3-92990.6" + wire $0\dec31_dec_sub11_sgn_ext[0:0] + attribute \src "libresoc.v:92276.3-92330.6" + wire width 3 $0\dec31_dec_sub11_sv_cr_in[2:0] + attribute \src "libresoc.v:92331.3-92385.6" + wire width 3 $0\dec31_dec_sub11_sv_cr_out[2:0] + attribute \src "libresoc.v:92056.3-92110.6" + wire width 3 $0\dec31_dec_sub11_sv_in1[2:0] + attribute \src "libresoc.v:92111.3-92165.6" + wire width 3 $0\dec31_dec_sub11_sv_in2[2:0] + attribute \src "libresoc.v:92166.3-92220.6" + wire width 3 $0\dec31_dec_sub11_sv_in3[2:0] + attribute \src "libresoc.v:92221.3-92275.6" + wire width 3 $0\dec31_dec_sub11_sv_out[2:0] + attribute \src "libresoc.v:92441.3-92495.6" + wire width 2 $0\dec31_dec_sub11_upd[1:0] + attribute \src "libresoc.v:91557.7-91557.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:93321.3-93375.6" + wire width 2 $1\dec31_dec_sub11_SV_Etype[1:0] + attribute \src "libresoc.v:93376.3-93430.6" + wire width 2 $1\dec31_dec_sub11_SV_Ptype[1:0] + attribute \src "libresoc.v:92661.3-92715.6" + wire width 8 $1\dec31_dec_sub11_asmcode[7:0] + attribute \src "libresoc.v:92881.3-92935.6" + wire $1\dec31_dec_sub11_br[0:0] + attribute \src "libresoc.v:91946.3-92000.6" + wire width 3 $1\dec31_dec_sub11_cr_in[2:0] + attribute \src "libresoc.v:92001.3-92055.6" + wire width 3 $1\dec31_dec_sub11_cr_out[2:0] + attribute \src "libresoc.v:92606.3-92660.6" + wire width 2 $1\dec31_dec_sub11_cry_in[1:0] + attribute \src "libresoc.v:92826.3-92880.6" + wire $1\dec31_dec_sub11_cry_out[0:0] + attribute \src "libresoc.v:93101.3-93155.6" + wire width 5 $1\dec31_dec_sub11_form[4:0] + attribute \src "libresoc.v:91891.3-91945.6" + wire width 13 $1\dec31_dec_sub11_function_unit[12:0] + attribute \src "libresoc.v:93431.3-93485.6" + wire width 3 $1\dec31_dec_sub11_in1_sel[2:0] + attribute \src "libresoc.v:93486.3-93540.6" + wire width 4 $1\dec31_dec_sub11_in2_sel[3:0] + attribute \src "libresoc.v:93541.3-93595.6" + wire width 2 $1\dec31_dec_sub11_in3_sel[1:0] + attribute \src "libresoc.v:92496.3-92550.6" + wire width 7 $1\dec31_dec_sub11_internal_op[6:0] + attribute \src "libresoc.v:92716.3-92770.6" + wire $1\dec31_dec_sub11_inv_a[0:0] + attribute \src "libresoc.v:92771.3-92825.6" + wire $1\dec31_dec_sub11_inv_out[0:0] + attribute \src "libresoc.v:93046.3-93100.6" + wire $1\dec31_dec_sub11_is_32b[0:0] + attribute \src "libresoc.v:92386.3-92440.6" + wire width 4 $1\dec31_dec_sub11_ldst_len[3:0] + attribute \src "libresoc.v:93211.3-93265.6" + wire $1\dec31_dec_sub11_lk[0:0] + attribute \src "libresoc.v:93596.3-93650.6" + wire width 2 $1\dec31_dec_sub11_out_sel[1:0] + attribute \src "libresoc.v:92551.3-92605.6" + wire width 2 $1\dec31_dec_sub11_rc_sel[1:0] + attribute \src "libresoc.v:92991.3-93045.6" + wire $1\dec31_dec_sub11_rsrv[0:0] + attribute \src "libresoc.v:93266.3-93320.6" + wire $1\dec31_dec_sub11_sgl_pipe[0:0] + attribute \src "libresoc.v:93156.3-93210.6" + wire $1\dec31_dec_sub11_sgn[0:0] + attribute \src "libresoc.v:92936.3-92990.6" + wire $1\dec31_dec_sub11_sgn_ext[0:0] + attribute \src "libresoc.v:92276.3-92330.6" + wire width 3 $1\dec31_dec_sub11_sv_cr_in[2:0] + attribute \src "libresoc.v:92331.3-92385.6" + wire width 3 $1\dec31_dec_sub11_sv_cr_out[2:0] + attribute \src "libresoc.v:92056.3-92110.6" + wire width 3 $1\dec31_dec_sub11_sv_in1[2:0] + attribute \src "libresoc.v:92111.3-92165.6" + wire width 3 $1\dec31_dec_sub11_sv_in2[2:0] + attribute \src "libresoc.v:92166.3-92220.6" + wire width 3 $1\dec31_dec_sub11_sv_in3[2:0] + attribute \src "libresoc.v:92221.3-92275.6" + wire width 3 $1\dec31_dec_sub11_sv_out[2:0] + attribute \src "libresoc.v:92441.3-92495.6" + wire width 2 $1\dec31_dec_sub11_upd[1:0] + attribute \enum_base_type "SVEtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "EXTRA2" + attribute \enum_value_10 "EXTRA3" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 5 \dec31_dec_sub11_SV_Etype + attribute \enum_base_type "SVPtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "P1" + attribute \enum_value_10 "P2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 6 \dec31_dec_sub11_SV_Ptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 8 output 4 \dec31_dec_sub11_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 26 \dec31_dec_sub11_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 11 \dec31_dec_sub11_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 12 \dec31_dec_sub11_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 22 \dec31_dec_sub11_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 25 \dec31_dec_sub11_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 5 output 3 \dec31_dec_sub11_form + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 13 output 1 \dec31_dec_sub11_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 7 \dec31_dec_sub11_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 8 \dec31_dec_sub11_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 9 \dec31_dec_sub11_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 output 2 \dec31_dec_sub11_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 23 \dec31_dec_sub11_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 24 \dec31_dec_sub11_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 29 \dec31_dec_sub11_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 19 \dec31_dec_sub11_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 31 \dec31_dec_sub11_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 10 \dec31_dec_sub11_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 21 \dec31_dec_sub11_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 28 \dec31_dec_sub11_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 32 \dec31_dec_sub11_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 30 \dec31_dec_sub11_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 27 \dec31_dec_sub11_sgn_ext + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 17 \dec31_dec_sub11_sv_cr_in + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 18 \dec31_dec_sub11_sv_cr_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 13 \dec31_dec_sub11_sv_in1 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 14 \dec31_dec_sub11_sv_in2 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 15 \dec31_dec_sub11_sv_in3 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 16 \dec31_dec_sub11_sv_out + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 20 \dec31_dec_sub11_upd + attribute \src "libresoc.v:91557.7-91557.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + wire width 32 input 33 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + wire width 5 \opcode_switch + attribute \src "libresoc.v:91557.7-91557.20" + process $proc$libresoc.v:91557$3897 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:91891.3-91945.6" + process $proc$libresoc.v:91891$3865 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_function_unit[12:0] $1\dec31_dec_sub11_function_unit[12:0] + attribute \src "libresoc.v:91892.5-91892.29" + switch \initial + attribute \src "libresoc.v:91892.9-91892.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_function_unit[12:0] 13'0001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_function_unit[12:0] 13'0001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_function_unit[12:0] 13'0001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_function_unit[12:0] 13'0001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_function_unit[12:0] 13'0001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_function_unit[12:0] 13'0001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_function_unit[12:0] 13'0001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_function_unit[12:0] 13'0001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_function_unit[12:0] 13'0001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_function_unit[12:0] 13'0001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_function_unit[12:0] 13'0000100000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_function_unit[12:0] 13'0000100000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_function_unit[12:0] 13'0000100000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_function_unit[12:0] 13'0000100000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_function_unit[12:0] 13'0000100000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_function_unit[12:0] 13'0000100000000 + case + assign $1\dec31_dec_sub11_function_unit[12:0] 13'0000000000000 + end + sync always + update \dec31_dec_sub11_function_unit $0\dec31_dec_sub11_function_unit[12:0] + end + attribute \src "libresoc.v:91946.3-92000.6" + process $proc$libresoc.v:91946$3866 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_cr_in[2:0] $1\dec31_dec_sub11_cr_in[2:0] + attribute \src "libresoc.v:91947.5-91947.29" + switch \initial + attribute \src "libresoc.v:91947.9-91947.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub11_cr_in $0\dec31_dec_sub11_cr_in[2:0] + end + attribute \src "libresoc.v:92001.3-92055.6" + process $proc$libresoc.v:92001$3867 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_cr_out[2:0] $1\dec31_dec_sub11_cr_out[2:0] + attribute \src "libresoc.v:92002.5-92002.29" + switch \initial + attribute \src "libresoc.v:92002.9-92002.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + case + assign $1\dec31_dec_sub11_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub11_cr_out $0\dec31_dec_sub11_cr_out[2:0] + end + attribute \src "libresoc.v:92056.3-92110.6" + process $proc$libresoc.v:92056$3868 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_sv_in1[2:0] $1\dec31_dec_sub11_sv_in1[2:0] + attribute \src "libresoc.v:92057.5-92057.29" + switch \initial + attribute \src "libresoc.v:92057.9-92057.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_sv_in1[2:0] 3'010 + case + assign $1\dec31_dec_sub11_sv_in1[2:0] 3'000 + end + sync always + update \dec31_dec_sub11_sv_in1 $0\dec31_dec_sub11_sv_in1[2:0] + end + attribute \src "libresoc.v:92111.3-92165.6" + process $proc$libresoc.v:92111$3869 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_sv_in2[2:0] $1\dec31_dec_sub11_sv_in2[2:0] + attribute \src "libresoc.v:92112.5-92112.29" + switch \initial + attribute \src "libresoc.v:92112.9-92112.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_sv_in2[2:0] 3'011 + case + assign $1\dec31_dec_sub11_sv_in2[2:0] 3'000 + end + sync always + update \dec31_dec_sub11_sv_in2 $0\dec31_dec_sub11_sv_in2[2:0] + end + attribute \src "libresoc.v:92166.3-92220.6" + process $proc$libresoc.v:92166$3870 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_sv_in3[2:0] $1\dec31_dec_sub11_sv_in3[2:0] + attribute \src "libresoc.v:92167.5-92167.29" + switch \initial + attribute \src "libresoc.v:92167.9-92167.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_sv_in3[2:0] 3'000 + case + assign $1\dec31_dec_sub11_sv_in3[2:0] 3'000 + end + sync always + update \dec31_dec_sub11_sv_in3 $0\dec31_dec_sub11_sv_in3[2:0] + end + attribute \src "libresoc.v:92221.3-92275.6" + process $proc$libresoc.v:92221$3871 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_sv_out[2:0] $1\dec31_dec_sub11_sv_out[2:0] + attribute \src "libresoc.v:92222.5-92222.29" + switch \initial + attribute \src "libresoc.v:92222.9-92222.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_sv_out[2:0] 3'001 + case + assign $1\dec31_dec_sub11_sv_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub11_sv_out $0\dec31_dec_sub11_sv_out[2:0] + end + attribute \src "libresoc.v:92276.3-92330.6" + process $proc$libresoc.v:92276$3872 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_sv_cr_in[2:0] $1\dec31_dec_sub11_sv_cr_in[2:0] + attribute \src "libresoc.v:92277.5-92277.29" + switch \initial + attribute \src "libresoc.v:92277.9-92277.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_sv_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub11_sv_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub11_sv_cr_in $0\dec31_dec_sub11_sv_cr_in[2:0] + end + attribute \src "libresoc.v:92331.3-92385.6" + process $proc$libresoc.v:92331$3873 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_sv_cr_out[2:0] $1\dec31_dec_sub11_sv_cr_out[2:0] + attribute \src "libresoc.v:92332.5-92332.29" + switch \initial + attribute \src "libresoc.v:92332.9-92332.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_sv_cr_out[2:0] 3'001 + case + assign $1\dec31_dec_sub11_sv_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub11_sv_cr_out $0\dec31_dec_sub11_sv_cr_out[2:0] + end + attribute \src "libresoc.v:92386.3-92440.6" + process $proc$libresoc.v:92386$3874 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_ldst_len[3:0] $1\dec31_dec_sub11_ldst_len[3:0] + attribute \src "libresoc.v:92387.5-92387.29" + switch \initial + attribute \src "libresoc.v:92387.9-92387.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + case + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub11_ldst_len $0\dec31_dec_sub11_ldst_len[3:0] + end + attribute \src "libresoc.v:92441.3-92495.6" + process $proc$libresoc.v:92441$3875 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_upd[1:0] $1\dec31_dec_sub11_upd[1:0] + attribute \src "libresoc.v:92442.5-92442.29" + switch \initial + attribute \src "libresoc.v:92442.9-92442.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + case + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub11_upd $0\dec31_dec_sub11_upd[1:0] + end + attribute \src "libresoc.v:92496.3-92550.6" + process $proc$libresoc.v:92496$3876 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_internal_op[6:0] $1\dec31_dec_sub11_internal_op[6:0] + attribute \src "libresoc.v:92497.5-92497.29" + switch \initial + attribute \src "libresoc.v:92497.9-92497.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011110 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011110 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011110 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011110 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0101111 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0101111 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0110100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0110100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0110100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0110100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0110010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0110010 + case + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub11_internal_op $0\dec31_dec_sub11_internal_op[6:0] + end + attribute \src "libresoc.v:92551.3-92605.6" + process $proc$libresoc.v:92551$3877 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_rc_sel[1:0] $1\dec31_dec_sub11_rc_sel[1:0] + attribute \src "libresoc.v:92552.5-92552.29" + switch \initial + attribute \src "libresoc.v:92552.9-92552.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + case + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub11_rc_sel $0\dec31_dec_sub11_rc_sel[1:0] + end + attribute \src "libresoc.v:92606.3-92660.6" + process $proc$libresoc.v:92606$3878 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_cry_in[1:0] $1\dec31_dec_sub11_cry_in[1:0] + attribute \src "libresoc.v:92607.5-92607.29" + switch \initial + attribute \src "libresoc.v:92607.9-92607.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + case + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub11_cry_in $0\dec31_dec_sub11_cry_in[1:0] + end + attribute \src "libresoc.v:92661.3-92715.6" + process $proc$libresoc.v:92661$3879 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_asmcode[7:0] $1\dec31_dec_sub11_asmcode[7:0] + attribute \src "libresoc.v:92662.5-92662.29" + switch \initial + attribute \src "libresoc.v:92662.9-92662.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_asmcode[7:0] 8'00111110 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_asmcode[7:0] 8'00111111 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_asmcode[7:0] 8'00111100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_asmcode[7:0] 8'00111101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_asmcode[7:0] 8'01000001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_asmcode[7:0] 8'01000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_asmcode[7:0] 8'00111011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_asmcode[7:0] 8'01000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_asmcode[7:0] 8'01110101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_asmcode[7:0] 8'01110011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_asmcode[7:0] 8'01111100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_asmcode[7:0] 8'01111101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_asmcode[7:0] 8'01111100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_asmcode[7:0] 8'01111101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_asmcode[7:0] 8'10000001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_asmcode[7:0] 8'10000010 + case + assign $1\dec31_dec_sub11_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub11_asmcode $0\dec31_dec_sub11_asmcode[7:0] + end + attribute \src "libresoc.v:92716.3-92770.6" + process $proc$libresoc.v:92716$3880 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_inv_a[0:0] $1\dec31_dec_sub11_inv_a[0:0] + attribute \src "libresoc.v:92717.5-92717.29" + switch \initial + attribute \src "libresoc.v:92717.9-92717.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + case + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub11_inv_a $0\dec31_dec_sub11_inv_a[0:0] + end + attribute \src "libresoc.v:92771.3-92825.6" + process $proc$libresoc.v:92771$3881 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_inv_out[0:0] $1\dec31_dec_sub11_inv_out[0:0] + attribute \src "libresoc.v:92772.5-92772.29" + switch \initial + attribute \src "libresoc.v:92772.9-92772.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub11_inv_out $0\dec31_dec_sub11_inv_out[0:0] + end + attribute \src "libresoc.v:92826.3-92880.6" + process $proc$libresoc.v:92826$3882 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_cry_out[0:0] $1\dec31_dec_sub11_cry_out[0:0] + attribute \src "libresoc.v:92827.5-92827.29" + switch \initial + attribute \src "libresoc.v:92827.9-92827.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + case + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub11_cry_out $0\dec31_dec_sub11_cry_out[0:0] + end + attribute \src "libresoc.v:92881.3-92935.6" + process $proc$libresoc.v:92881$3883 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_br[0:0] $1\dec31_dec_sub11_br[0:0] + attribute \src "libresoc.v:92882.5-92882.29" + switch \initial + attribute \src "libresoc.v:92882.9-92882.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + case + assign $1\dec31_dec_sub11_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub11_br $0\dec31_dec_sub11_br[0:0] + end + attribute \src "libresoc.v:92936.3-92990.6" + process $proc$libresoc.v:92936$3884 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_sgn_ext[0:0] $1\dec31_dec_sub11_sgn_ext[0:0] + attribute \src "libresoc.v:92937.5-92937.29" + switch \initial + attribute \src "libresoc.v:92937.9-92937.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub11_sgn_ext $0\dec31_dec_sub11_sgn_ext[0:0] + end + attribute \src "libresoc.v:92991.3-93045.6" + process $proc$libresoc.v:92991$3885 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_rsrv[0:0] $1\dec31_dec_sub11_rsrv[0:0] + attribute \src "libresoc.v:92992.5-92992.29" + switch \initial + attribute \src "libresoc.v:92992.9-92992.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub11_rsrv $0\dec31_dec_sub11_rsrv[0:0] + end + attribute \src "libresoc.v:93046.3-93100.6" + process $proc$libresoc.v:93046$3886 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_is_32b[0:0] $1\dec31_dec_sub11_is_32b[0:0] + attribute \src "libresoc.v:93047.5-93047.29" + switch \initial + attribute \src "libresoc.v:93047.9-93047.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + case + assign $1\dec31_dec_sub11_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub11_is_32b $0\dec31_dec_sub11_is_32b[0:0] + end + attribute \src "libresoc.v:93101.3-93155.6" + process $proc$libresoc.v:93101$3887 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_form[4:0] $1\dec31_dec_sub11_form[4:0] + attribute \src "libresoc.v:93102.5-93102.29" + switch \initial + attribute \src "libresoc.v:93102.9-93102.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_form[4:0] 5'10001 + case + assign $1\dec31_dec_sub11_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub11_form $0\dec31_dec_sub11_form[4:0] + end + attribute \src "libresoc.v:93156.3-93210.6" + process $proc$libresoc.v:93156$3888 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_sgn[0:0] $1\dec31_dec_sub11_sgn[0:0] + attribute \src "libresoc.v:93157.5-93157.29" + switch \initial + attribute \src "libresoc.v:93157.9-93157.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_sgn[0:0] 1'1 + case + assign $1\dec31_dec_sub11_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub11_sgn $0\dec31_dec_sub11_sgn[0:0] + end + attribute \src "libresoc.v:93211.3-93265.6" + process $proc$libresoc.v:93211$3889 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_lk[0:0] $1\dec31_dec_sub11_lk[0:0] + attribute \src "libresoc.v:93212.5-93212.29" + switch \initial + attribute \src "libresoc.v:93212.9-93212.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub11_lk $0\dec31_dec_sub11_lk[0:0] + end + attribute \src "libresoc.v:93266.3-93320.6" + process $proc$libresoc.v:93266$3890 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_sgl_pipe[0:0] $1\dec31_dec_sub11_sgl_pipe[0:0] + attribute \src "libresoc.v:93267.5-93267.29" + switch \initial + attribute \src "libresoc.v:93267.9-93267.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + case + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub11_sgl_pipe $0\dec31_dec_sub11_sgl_pipe[0:0] + end + attribute \src "libresoc.v:93321.3-93375.6" + process $proc$libresoc.v:93321$3891 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_SV_Etype[1:0] $1\dec31_dec_sub11_SV_Etype[1:0] + attribute \src "libresoc.v:93322.5-93322.29" + switch \initial + attribute \src "libresoc.v:93322.9-93322.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_SV_Etype[1:0] 2'10 + case + assign $1\dec31_dec_sub11_SV_Etype[1:0] 2'00 + end + sync always + update \dec31_dec_sub11_SV_Etype $0\dec31_dec_sub11_SV_Etype[1:0] + end + attribute \src "libresoc.v:93376.3-93430.6" + process $proc$libresoc.v:93376$3892 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_SV_Ptype[1:0] $1\dec31_dec_sub11_SV_Ptype[1:0] + attribute \src "libresoc.v:93377.5-93377.29" + switch \initial + attribute \src "libresoc.v:93377.9-93377.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_SV_Ptype[1:0] 2'01 + case + assign $1\dec31_dec_sub11_SV_Ptype[1:0] 2'00 + end + sync always + update \dec31_dec_sub11_SV_Ptype $0\dec31_dec_sub11_SV_Ptype[1:0] + end + attribute \src "libresoc.v:93431.3-93485.6" + process $proc$libresoc.v:93431$3893 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_in1_sel[2:0] $1\dec31_dec_sub11_in1_sel[2:0] + attribute \src "libresoc.v:93432.5-93432.29" + switch \initial + attribute \src "libresoc.v:93432.9-93432.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + case + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub11_in1_sel $0\dec31_dec_sub11_in1_sel[2:0] + end + attribute \src "libresoc.v:93486.3-93540.6" + process $proc$libresoc.v:93486$3894 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_in2_sel[3:0] $1\dec31_dec_sub11_in2_sel[3:0] + attribute \src "libresoc.v:93487.5-93487.29" + switch \initial + attribute \src "libresoc.v:93487.9-93487.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + case + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub11_in2_sel $0\dec31_dec_sub11_in2_sel[3:0] + end + attribute \src "libresoc.v:93541.3-93595.6" + process $proc$libresoc.v:93541$3895 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_in3_sel[1:0] $1\dec31_dec_sub11_in3_sel[1:0] + attribute \src "libresoc.v:93542.5-93542.29" + switch \initial + attribute \src "libresoc.v:93542.9-93542.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub11_in3_sel $0\dec31_dec_sub11_in3_sel[1:0] + end + attribute \src "libresoc.v:93596.3-93650.6" + process $proc$libresoc.v:93596$3896 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_out_sel[1:0] $1\dec31_dec_sub11_out_sel[1:0] + attribute \src "libresoc.v:93597.5-93597.29" + switch \initial + attribute \src "libresoc.v:93597.9-93597.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + case + assign $1\dec31_dec_sub11_out_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub11_out_sel $0\dec31_dec_sub11_out_sel[1:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:93656.1-97288.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub15" +attribute \generator "nMigen" +module \dec31_dec_sub15 + attribute \src "libresoc.v:96669.3-96771.6" + wire width 2 $0\dec31_dec_sub15_SV_Etype[1:0] + attribute \src "libresoc.v:96772.3-96874.6" + wire width 2 $0\dec31_dec_sub15_SV_Ptype[1:0] + attribute \src "libresoc.v:95433.3-95535.6" + wire width 8 $0\dec31_dec_sub15_asmcode[7:0] + attribute \src "libresoc.v:95845.3-95947.6" + wire $0\dec31_dec_sub15_br[0:0] + attribute \src "libresoc.v:94094.3-94196.6" + wire width 3 $0\dec31_dec_sub15_cr_in[2:0] + attribute \src "libresoc.v:94197.3-94299.6" + wire width 3 $0\dec31_dec_sub15_cr_out[2:0] + attribute \src "libresoc.v:95330.3-95432.6" + wire width 2 $0\dec31_dec_sub15_cry_in[1:0] + attribute \src "libresoc.v:95742.3-95844.6" + wire $0\dec31_dec_sub15_cry_out[0:0] + attribute \src "libresoc.v:96257.3-96359.6" + wire width 5 $0\dec31_dec_sub15_form[4:0] + attribute \src "libresoc.v:93991.3-94093.6" + wire width 13 $0\dec31_dec_sub15_function_unit[12:0] + attribute \src "libresoc.v:96875.3-96977.6" + wire width 3 $0\dec31_dec_sub15_in1_sel[2:0] + attribute \src "libresoc.v:96978.3-97080.6" + wire width 4 $0\dec31_dec_sub15_in2_sel[3:0] + attribute \src "libresoc.v:97081.3-97183.6" + wire width 2 $0\dec31_dec_sub15_in3_sel[1:0] + attribute \src "libresoc.v:95124.3-95226.6" + wire width 7 $0\dec31_dec_sub15_internal_op[6:0] + attribute \src "libresoc.v:95536.3-95638.6" + wire $0\dec31_dec_sub15_inv_a[0:0] + attribute \src "libresoc.v:95639.3-95741.6" + wire $0\dec31_dec_sub15_inv_out[0:0] + attribute \src "libresoc.v:96154.3-96256.6" + wire $0\dec31_dec_sub15_is_32b[0:0] + attribute \src "libresoc.v:94918.3-95020.6" + wire width 4 $0\dec31_dec_sub15_ldst_len[3:0] + attribute \src "libresoc.v:96463.3-96565.6" + wire $0\dec31_dec_sub15_lk[0:0] + attribute \src "libresoc.v:97184.3-97286.6" + wire width 2 $0\dec31_dec_sub15_out_sel[1:0] + attribute \src "libresoc.v:95227.3-95329.6" + wire width 2 $0\dec31_dec_sub15_rc_sel[1:0] + attribute \src "libresoc.v:96051.3-96153.6" + wire $0\dec31_dec_sub15_rsrv[0:0] + attribute \src "libresoc.v:96566.3-96668.6" + wire $0\dec31_dec_sub15_sgl_pipe[0:0] + attribute \src "libresoc.v:96360.3-96462.6" + wire $0\dec31_dec_sub15_sgn[0:0] + attribute \src "libresoc.v:95948.3-96050.6" + wire $0\dec31_dec_sub15_sgn_ext[0:0] + attribute \src "libresoc.v:94712.3-94814.6" + wire width 3 $0\dec31_dec_sub15_sv_cr_in[2:0] + attribute \src "libresoc.v:94815.3-94917.6" + wire width 3 $0\dec31_dec_sub15_sv_cr_out[2:0] + attribute \src "libresoc.v:94300.3-94402.6" + wire width 3 $0\dec31_dec_sub15_sv_in1[2:0] + attribute \src "libresoc.v:94403.3-94505.6" + wire width 3 $0\dec31_dec_sub15_sv_in2[2:0] + attribute \src "libresoc.v:94506.3-94608.6" + wire width 3 $0\dec31_dec_sub15_sv_in3[2:0] + attribute \src "libresoc.v:94609.3-94711.6" + wire width 3 $0\dec31_dec_sub15_sv_out[2:0] + attribute \src "libresoc.v:95021.3-95123.6" + wire width 2 $0\dec31_dec_sub15_upd[1:0] + attribute \src "libresoc.v:93657.7-93657.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:96669.3-96771.6" + wire width 2 $1\dec31_dec_sub15_SV_Etype[1:0] + attribute \src "libresoc.v:96772.3-96874.6" + wire width 2 $1\dec31_dec_sub15_SV_Ptype[1:0] + attribute \src "libresoc.v:95433.3-95535.6" + wire width 8 $1\dec31_dec_sub15_asmcode[7:0] + attribute \src "libresoc.v:95845.3-95947.6" + wire $1\dec31_dec_sub15_br[0:0] + attribute \src "libresoc.v:94094.3-94196.6" + wire width 3 $1\dec31_dec_sub15_cr_in[2:0] + attribute \src "libresoc.v:94197.3-94299.6" + wire width 3 $1\dec31_dec_sub15_cr_out[2:0] + attribute \src "libresoc.v:95330.3-95432.6" + wire width 2 $1\dec31_dec_sub15_cry_in[1:0] + attribute \src "libresoc.v:95742.3-95844.6" + wire $1\dec31_dec_sub15_cry_out[0:0] + attribute \src "libresoc.v:96257.3-96359.6" + wire width 5 $1\dec31_dec_sub15_form[4:0] + attribute \src "libresoc.v:93991.3-94093.6" + wire width 13 $1\dec31_dec_sub15_function_unit[12:0] + attribute \src "libresoc.v:96875.3-96977.6" + wire width 3 $1\dec31_dec_sub15_in1_sel[2:0] + attribute \src "libresoc.v:96978.3-97080.6" + wire width 4 $1\dec31_dec_sub15_in2_sel[3:0] + attribute \src "libresoc.v:97081.3-97183.6" + wire width 2 $1\dec31_dec_sub15_in3_sel[1:0] + attribute \src "libresoc.v:95124.3-95226.6" + wire width 7 $1\dec31_dec_sub15_internal_op[6:0] + attribute \src "libresoc.v:95536.3-95638.6" + wire $1\dec31_dec_sub15_inv_a[0:0] + attribute \src "libresoc.v:95639.3-95741.6" + wire $1\dec31_dec_sub15_inv_out[0:0] + attribute \src "libresoc.v:96154.3-96256.6" + wire $1\dec31_dec_sub15_is_32b[0:0] + attribute \src "libresoc.v:94918.3-95020.6" + wire width 4 $1\dec31_dec_sub15_ldst_len[3:0] + attribute \src "libresoc.v:96463.3-96565.6" + wire $1\dec31_dec_sub15_lk[0:0] + attribute \src "libresoc.v:97184.3-97286.6" + wire width 2 $1\dec31_dec_sub15_out_sel[1:0] + attribute \src "libresoc.v:95227.3-95329.6" + wire width 2 $1\dec31_dec_sub15_rc_sel[1:0] + attribute \src "libresoc.v:96051.3-96153.6" + wire $1\dec31_dec_sub15_rsrv[0:0] + attribute \src "libresoc.v:96566.3-96668.6" + wire $1\dec31_dec_sub15_sgl_pipe[0:0] + attribute \src "libresoc.v:96360.3-96462.6" + wire $1\dec31_dec_sub15_sgn[0:0] + attribute \src "libresoc.v:95948.3-96050.6" + wire $1\dec31_dec_sub15_sgn_ext[0:0] + attribute \src "libresoc.v:94712.3-94814.6" + wire width 3 $1\dec31_dec_sub15_sv_cr_in[2:0] + attribute \src "libresoc.v:94815.3-94917.6" + wire width 3 $1\dec31_dec_sub15_sv_cr_out[2:0] + attribute \src "libresoc.v:94300.3-94402.6" + wire width 3 $1\dec31_dec_sub15_sv_in1[2:0] + attribute \src "libresoc.v:94403.3-94505.6" + wire width 3 $1\dec31_dec_sub15_sv_in2[2:0] + attribute \src "libresoc.v:94506.3-94608.6" + wire width 3 $1\dec31_dec_sub15_sv_in3[2:0] + attribute \src "libresoc.v:94609.3-94711.6" + wire width 3 $1\dec31_dec_sub15_sv_out[2:0] + attribute \src "libresoc.v:95021.3-95123.6" + wire width 2 $1\dec31_dec_sub15_upd[1:0] + attribute \enum_base_type "SVEtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "EXTRA2" + attribute \enum_value_10 "EXTRA3" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 5 \dec31_dec_sub15_SV_Etype + attribute \enum_base_type "SVPtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "P1" + attribute \enum_value_10 "P2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 6 \dec31_dec_sub15_SV_Ptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 8 output 4 \dec31_dec_sub15_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 26 \dec31_dec_sub15_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 11 \dec31_dec_sub15_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 12 \dec31_dec_sub15_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 22 \dec31_dec_sub15_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 25 \dec31_dec_sub15_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 5 output 3 \dec31_dec_sub15_form + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 13 output 1 \dec31_dec_sub15_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 7 \dec31_dec_sub15_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 8 \dec31_dec_sub15_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 9 \dec31_dec_sub15_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 output 2 \dec31_dec_sub15_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 23 \dec31_dec_sub15_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 24 \dec31_dec_sub15_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 29 \dec31_dec_sub15_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 19 \dec31_dec_sub15_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 31 \dec31_dec_sub15_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 10 \dec31_dec_sub15_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 21 \dec31_dec_sub15_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 28 \dec31_dec_sub15_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 32 \dec31_dec_sub15_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 30 \dec31_dec_sub15_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 27 \dec31_dec_sub15_sgn_ext + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 17 \dec31_dec_sub15_sv_cr_in + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 18 \dec31_dec_sub15_sv_cr_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 13 \dec31_dec_sub15_sv_in1 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 14 \dec31_dec_sub15_sv_in2 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 15 \dec31_dec_sub15_sv_in3 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 16 \dec31_dec_sub15_sv_out + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 20 \dec31_dec_sub15_upd + attribute \src "libresoc.v:93657.7-93657.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + wire width 32 input 33 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + wire width 5 \opcode_switch + attribute \src "libresoc.v:93657.7-93657.20" + process $proc$libresoc.v:93657$3930 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:93991.3-94093.6" + process $proc$libresoc.v:93991$3898 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_function_unit[12:0] $1\dec31_dec_sub15_function_unit[12:0] + attribute \src "libresoc.v:93992.5-93992.29" + switch \initial + attribute \src "libresoc.v:93992.9-93992.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[12:0] 13'0000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[12:0] 13'0000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[12:0] 13'0000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[12:0] 13'0000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[12:0] 13'0000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[12:0] 13'0000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[12:0] 13'0000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[12:0] 13'0000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[12:0] 13'0000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[12:0] 13'0000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[12:0] 13'0000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[12:0] 13'0000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[12:0] 13'0000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[12:0] 13'0000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[12:0] 13'0000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[12:0] 13'0000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[12:0] 13'0000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[12:0] 13'0000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[12:0] 13'0000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[12:0] 13'0000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[12:0] 13'0000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[12:0] 13'0000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[12:0] 13'0000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[12:0] 13'0000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[12:0] 13'0000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[12:0] 13'0000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[12:0] 13'0000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[12:0] 13'0000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[12:0] 13'0000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[12:0] 13'0000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[12:0] 13'0000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[12:0] 13'0000001000000 + case + assign $1\dec31_dec_sub15_function_unit[12:0] 13'0000000000000 + end + sync always + update \dec31_dec_sub15_function_unit $0\dec31_dec_sub15_function_unit[12:0] + end + attribute \src "libresoc.v:94094.3-94196.6" + process $proc$libresoc.v:94094$3899 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_cr_in[2:0] $1\dec31_dec_sub15_cr_in[2:0] + attribute \src "libresoc.v:94095.5-94095.29" + switch \initial + attribute \src "libresoc.v:94095.9-94095.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + case + assign $1\dec31_dec_sub15_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub15_cr_in $0\dec31_dec_sub15_cr_in[2:0] + end + attribute \src "libresoc.v:94197.3-94299.6" + process $proc$libresoc.v:94197$3900 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_cr_out[2:0] $1\dec31_dec_sub15_cr_out[2:0] + attribute \src "libresoc.v:94198.5-94198.29" + switch \initial + attribute \src "libresoc.v:94198.9-94198.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + case + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub15_cr_out $0\dec31_dec_sub15_cr_out[2:0] + end + attribute \src "libresoc.v:94300.3-94402.6" + process $proc$libresoc.v:94300$3901 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_sv_in1[2:0] $1\dec31_dec_sub15_sv_in1[2:0] + attribute \src "libresoc.v:94301.5-94301.29" + switch \initial + attribute \src "libresoc.v:94301.9-94301.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_sv_in1[2:0] 3'010 + case + assign $1\dec31_dec_sub15_sv_in1[2:0] 3'000 + end + sync always + update \dec31_dec_sub15_sv_in1 $0\dec31_dec_sub15_sv_in1[2:0] + end + attribute \src "libresoc.v:94403.3-94505.6" + process $proc$libresoc.v:94403$3902 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_sv_in2[2:0] $1\dec31_dec_sub15_sv_in2[2:0] + attribute \src "libresoc.v:94404.5-94404.29" + switch \initial + attribute \src "libresoc.v:94404.9-94404.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_sv_in2[2:0] 3'011 + case + assign $1\dec31_dec_sub15_sv_in2[2:0] 3'000 + end + sync always + update \dec31_dec_sub15_sv_in2 $0\dec31_dec_sub15_sv_in2[2:0] + end + attribute \src "libresoc.v:94506.3-94608.6" + process $proc$libresoc.v:94506$3903 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_sv_in3[2:0] $1\dec31_dec_sub15_sv_in3[2:0] + attribute \src "libresoc.v:94507.5-94507.29" + switch \initial + attribute \src "libresoc.v:94507.9-94507.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_sv_in3[2:0] 3'000 + case + assign $1\dec31_dec_sub15_sv_in3[2:0] 3'000 + end + sync always + update \dec31_dec_sub15_sv_in3 $0\dec31_dec_sub15_sv_in3[2:0] + end + attribute \src "libresoc.v:94609.3-94711.6" + process $proc$libresoc.v:94609$3904 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_sv_out[2:0] $1\dec31_dec_sub15_sv_out[2:0] + attribute \src "libresoc.v:94610.5-94610.29" + switch \initial + attribute \src "libresoc.v:94610.9-94610.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_sv_out[2:0] 3'001 + case + assign $1\dec31_dec_sub15_sv_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub15_sv_out $0\dec31_dec_sub15_sv_out[2:0] + end + attribute \src "libresoc.v:94712.3-94814.6" + process $proc$libresoc.v:94712$3905 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_sv_cr_in[2:0] $1\dec31_dec_sub15_sv_cr_in[2:0] + attribute \src "libresoc.v:94713.5-94713.29" + switch \initial + attribute \src "libresoc.v:94713.9-94713.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_sv_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_sv_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_sv_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_sv_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_sv_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_sv_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_sv_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_sv_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_sv_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_sv_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_sv_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_sv_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_sv_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_sv_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_sv_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_sv_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_sv_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_sv_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_sv_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_sv_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_sv_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_sv_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_sv_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_sv_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_sv_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_sv_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_sv_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_sv_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_sv_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_sv_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_sv_cr_in[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_sv_cr_in[2:0] 3'100 + case + assign $1\dec31_dec_sub15_sv_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub15_sv_cr_in $0\dec31_dec_sub15_sv_cr_in[2:0] + end + attribute \src "libresoc.v:94815.3-94917.6" + process $proc$libresoc.v:94815$3906 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_sv_cr_out[2:0] $1\dec31_dec_sub15_sv_cr_out[2:0] + attribute \src "libresoc.v:94816.5-94816.29" + switch \initial + attribute \src "libresoc.v:94816.9-94816.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_sv_cr_out[2:0] 3'000 + case + assign $1\dec31_dec_sub15_sv_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub15_sv_cr_out $0\dec31_dec_sub15_sv_cr_out[2:0] + end + attribute \src "libresoc.v:94918.3-95020.6" + process $proc$libresoc.v:94918$3907 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_ldst_len[3:0] $1\dec31_dec_sub15_ldst_len[3:0] + attribute \src "libresoc.v:94919.5-94919.29" + switch \initial + attribute \src "libresoc.v:94919.9-94919.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + case + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub15_ldst_len $0\dec31_dec_sub15_ldst_len[3:0] + end + attribute \src "libresoc.v:95021.3-95123.6" + process $proc$libresoc.v:95021$3908 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_upd[1:0] $1\dec31_dec_sub15_upd[1:0] + attribute \src "libresoc.v:95022.5-95022.29" + switch \initial + attribute \src "libresoc.v:95022.9-95022.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + case + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub15_upd $0\dec31_dec_sub15_upd[1:0] + end + attribute \src "libresoc.v:95124.3-95226.6" + process $proc$libresoc.v:95124$3909 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_internal_op[6:0] $1\dec31_dec_sub15_internal_op[6:0] + attribute \src "libresoc.v:95125.5-95125.29" + switch \initial + attribute \src "libresoc.v:95125.9-95125.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + case + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub15_internal_op $0\dec31_dec_sub15_internal_op[6:0] + end + attribute \src "libresoc.v:95227.3-95329.6" + process $proc$libresoc.v:95227$3910 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_rc_sel[1:0] $1\dec31_dec_sub15_rc_sel[1:0] + attribute \src "libresoc.v:95228.5-95228.29" + switch \initial + attribute \src "libresoc.v:95228.9-95228.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub15_rc_sel $0\dec31_dec_sub15_rc_sel[1:0] + end + attribute \src "libresoc.v:95330.3-95432.6" + process $proc$libresoc.v:95330$3911 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_cry_in[1:0] $1\dec31_dec_sub15_cry_in[1:0] + attribute \src "libresoc.v:95331.5-95331.29" + switch \initial + attribute \src "libresoc.v:95331.9-95331.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + case + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub15_cry_in $0\dec31_dec_sub15_cry_in[1:0] + end + attribute \src "libresoc.v:95433.3-95535.6" + process $proc$libresoc.v:95433$3912 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_asmcode[7:0] $1\dec31_dec_sub15_asmcode[7:0] + attribute \src "libresoc.v:95434.5-95434.29" + switch \initial + attribute \src "libresoc.v:95434.9-95434.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + case + assign $1\dec31_dec_sub15_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub15_asmcode $0\dec31_dec_sub15_asmcode[7:0] + end + attribute \src "libresoc.v:95536.3-95638.6" + process $proc$libresoc.v:95536$3913 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_inv_a[0:0] $1\dec31_dec_sub15_inv_a[0:0] + attribute \src "libresoc.v:95537.5-95537.29" + switch \initial + attribute \src "libresoc.v:95537.9-95537.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + case + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub15_inv_a $0\dec31_dec_sub15_inv_a[0:0] + end + attribute \src "libresoc.v:95639.3-95741.6" + process $proc$libresoc.v:95639$3914 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_inv_out[0:0] $1\dec31_dec_sub15_inv_out[0:0] + attribute \src "libresoc.v:95640.5-95640.29" + switch \initial + attribute \src "libresoc.v:95640.9-95640.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub15_inv_out $0\dec31_dec_sub15_inv_out[0:0] + end + attribute \src "libresoc.v:95742.3-95844.6" + process $proc$libresoc.v:95742$3915 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_cry_out[0:0] $1\dec31_dec_sub15_cry_out[0:0] + attribute \src "libresoc.v:95743.5-95743.29" + switch \initial + attribute \src "libresoc.v:95743.9-95743.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + case + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub15_cry_out $0\dec31_dec_sub15_cry_out[0:0] + end + attribute \src "libresoc.v:95845.3-95947.6" + process $proc$libresoc.v:95845$3916 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_br[0:0] $1\dec31_dec_sub15_br[0:0] + attribute \src "libresoc.v:95846.5-95846.29" + switch \initial + attribute \src "libresoc.v:95846.9-95846.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + case + assign $1\dec31_dec_sub15_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub15_br $0\dec31_dec_sub15_br[0:0] + end + attribute \src "libresoc.v:95948.3-96050.6" + process $proc$libresoc.v:95948$3917 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_sgn_ext[0:0] $1\dec31_dec_sub15_sgn_ext[0:0] + attribute \src "libresoc.v:95949.5-95949.29" + switch \initial + attribute \src "libresoc.v:95949.9-95949.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub15_sgn_ext $0\dec31_dec_sub15_sgn_ext[0:0] + end + attribute \src "libresoc.v:96051.3-96153.6" + process $proc$libresoc.v:96051$3918 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_rsrv[0:0] $1\dec31_dec_sub15_rsrv[0:0] + attribute \src "libresoc.v:96052.5-96052.29" + switch \initial + attribute \src "libresoc.v:96052.9-96052.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub15_rsrv $0\dec31_dec_sub15_rsrv[0:0] + end + attribute \src "libresoc.v:96154.3-96256.6" + process $proc$libresoc.v:96154$3919 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_is_32b[0:0] $1\dec31_dec_sub15_is_32b[0:0] + attribute \src "libresoc.v:96155.5-96155.29" + switch \initial + attribute \src "libresoc.v:96155.9-96155.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + case + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub15_is_32b $0\dec31_dec_sub15_is_32b[0:0] + end + attribute \src "libresoc.v:96257.3-96359.6" + process $proc$libresoc.v:96257$3920 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_form[4:0] $1\dec31_dec_sub15_form[4:0] + attribute \src "libresoc.v:96258.5-96258.29" + switch \initial + attribute \src "libresoc.v:96258.9-96258.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + case + assign $1\dec31_dec_sub15_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub15_form $0\dec31_dec_sub15_form[4:0] + end + attribute \src "libresoc.v:96360.3-96462.6" + process $proc$libresoc.v:96360$3921 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_sgn[0:0] $1\dec31_dec_sub15_sgn[0:0] + attribute \src "libresoc.v:96361.5-96361.29" + switch \initial + attribute \src "libresoc.v:96361.9-96361.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + case + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub15_sgn $0\dec31_dec_sub15_sgn[0:0] + end + attribute \src "libresoc.v:96463.3-96565.6" + process $proc$libresoc.v:96463$3922 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_lk[0:0] $1\dec31_dec_sub15_lk[0:0] + attribute \src "libresoc.v:96464.5-96464.29" + switch \initial + attribute \src "libresoc.v:96464.9-96464.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub15_lk $0\dec31_dec_sub15_lk[0:0] + end + attribute \src "libresoc.v:96566.3-96668.6" + process $proc$libresoc.v:96566$3923 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_sgl_pipe[0:0] $1\dec31_dec_sub15_sgl_pipe[0:0] + attribute \src "libresoc.v:96567.5-96567.29" + switch \initial + attribute \src "libresoc.v:96567.9-96567.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + case + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub15_sgl_pipe $0\dec31_dec_sub15_sgl_pipe[0:0] + end + attribute \src "libresoc.v:96669.3-96771.6" + process $proc$libresoc.v:96669$3924 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_SV_Etype[1:0] $1\dec31_dec_sub15_SV_Etype[1:0] + attribute \src "libresoc.v:96670.5-96670.29" + switch \initial + attribute \src "libresoc.v:96670.9-96670.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_SV_Etype[1:0] 2'01 + case + assign $1\dec31_dec_sub15_SV_Etype[1:0] 2'00 + end + sync always + update \dec31_dec_sub15_SV_Etype $0\dec31_dec_sub15_SV_Etype[1:0] + end + attribute \src "libresoc.v:96772.3-96874.6" + process $proc$libresoc.v:96772$3925 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_SV_Ptype[1:0] $1\dec31_dec_sub15_SV_Ptype[1:0] + attribute \src "libresoc.v:96773.5-96773.29" + switch \initial + attribute \src "libresoc.v:96773.9-96773.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_SV_Ptype[1:0] 2'01 + case + assign $1\dec31_dec_sub15_SV_Ptype[1:0] 2'00 + end + sync always + update \dec31_dec_sub15_SV_Ptype $0\dec31_dec_sub15_SV_Ptype[1:0] + end + attribute \src "libresoc.v:96875.3-96977.6" + process $proc$libresoc.v:96875$3926 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_in1_sel[2:0] $1\dec31_dec_sub15_in1_sel[2:0] + attribute \src "libresoc.v:96876.5-96876.29" + switch \initial + attribute \src "libresoc.v:96876.9-96876.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + case + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub15_in1_sel $0\dec31_dec_sub15_in1_sel[2:0] + end + attribute \src "libresoc.v:96978.3-97080.6" + process $proc$libresoc.v:96978$3927 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_in2_sel[3:0] $1\dec31_dec_sub15_in2_sel[3:0] + attribute \src "libresoc.v:96979.5-96979.29" + switch \initial + attribute \src "libresoc.v:96979.9-96979.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + case + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub15_in2_sel $0\dec31_dec_sub15_in2_sel[3:0] + end + attribute \src "libresoc.v:97081.3-97183.6" + process $proc$libresoc.v:97081$3928 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_in3_sel[1:0] $1\dec31_dec_sub15_in3_sel[1:0] + attribute \src "libresoc.v:97082.5-97082.29" + switch \initial + attribute \src "libresoc.v:97082.9-97082.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub15_in3_sel $0\dec31_dec_sub15_in3_sel[1:0] + end + attribute \src "libresoc.v:97184.3-97286.6" + process $proc$libresoc.v:97184$3929 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_out_sel[1:0] $1\dec31_dec_sub15_out_sel[1:0] + attribute \src "libresoc.v:97185.5-97185.29" + switch \initial + attribute \src "libresoc.v:97185.9-97185.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + case + assign $1\dec31_dec_sub15_out_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub15_out_sel $0\dec31_dec_sub15_out_sel[1:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:97292.1-97948.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub16" +attribute \generator "nMigen" +module \dec31_dec_sub16 + attribute \src "libresoc.v:97887.3-97896.6" + wire width 2 $0\dec31_dec_sub16_SV_Etype[1:0] + attribute \src "libresoc.v:97897.3-97906.6" + wire width 2 $0\dec31_dec_sub16_SV_Ptype[1:0] + attribute \src "libresoc.v:97767.3-97776.6" + wire width 8 $0\dec31_dec_sub16_asmcode[7:0] + attribute \src "libresoc.v:97807.3-97816.6" + wire $0\dec31_dec_sub16_br[0:0] + attribute \src "libresoc.v:97637.3-97646.6" + wire width 3 $0\dec31_dec_sub16_cr_in[2:0] + attribute \src "libresoc.v:97647.3-97656.6" + wire width 3 $0\dec31_dec_sub16_cr_out[2:0] + attribute \src "libresoc.v:97757.3-97766.6" + wire width 2 $0\dec31_dec_sub16_cry_in[1:0] + attribute \src "libresoc.v:97797.3-97806.6" + wire $0\dec31_dec_sub16_cry_out[0:0] + attribute \src "libresoc.v:97847.3-97856.6" + wire width 5 $0\dec31_dec_sub16_form[4:0] + attribute \src "libresoc.v:97627.3-97636.6" + wire width 13 $0\dec31_dec_sub16_function_unit[12:0] + attribute \src "libresoc.v:97907.3-97916.6" + wire width 3 $0\dec31_dec_sub16_in1_sel[2:0] + attribute \src "libresoc.v:97917.3-97926.6" + wire width 4 $0\dec31_dec_sub16_in2_sel[3:0] + attribute \src "libresoc.v:97927.3-97936.6" + wire width 2 $0\dec31_dec_sub16_in3_sel[1:0] + attribute \src "libresoc.v:97737.3-97746.6" + wire width 7 $0\dec31_dec_sub16_internal_op[6:0] + attribute \src "libresoc.v:97777.3-97786.6" + wire $0\dec31_dec_sub16_inv_a[0:0] + attribute \src "libresoc.v:97787.3-97796.6" + wire $0\dec31_dec_sub16_inv_out[0:0] + attribute \src "libresoc.v:97837.3-97846.6" + wire $0\dec31_dec_sub16_is_32b[0:0] + attribute \src "libresoc.v:97717.3-97726.6" + wire width 4 $0\dec31_dec_sub16_ldst_len[3:0] + attribute \src "libresoc.v:97867.3-97876.6" + wire $0\dec31_dec_sub16_lk[0:0] + attribute \src "libresoc.v:97937.3-97946.6" + wire width 2 $0\dec31_dec_sub16_out_sel[1:0] + attribute \src "libresoc.v:97747.3-97756.6" + wire width 2 $0\dec31_dec_sub16_rc_sel[1:0] + attribute \src "libresoc.v:97827.3-97836.6" + wire $0\dec31_dec_sub16_rsrv[0:0] + attribute \src "libresoc.v:97877.3-97886.6" + wire $0\dec31_dec_sub16_sgl_pipe[0:0] + attribute \src "libresoc.v:97857.3-97866.6" + wire $0\dec31_dec_sub16_sgn[0:0] + attribute \src "libresoc.v:97817.3-97826.6" + wire $0\dec31_dec_sub16_sgn_ext[0:0] + attribute \src "libresoc.v:97697.3-97706.6" + wire width 3 $0\dec31_dec_sub16_sv_cr_in[2:0] + attribute \src "libresoc.v:97707.3-97716.6" + wire width 3 $0\dec31_dec_sub16_sv_cr_out[2:0] + attribute \src "libresoc.v:97657.3-97666.6" + wire width 3 $0\dec31_dec_sub16_sv_in1[2:0] + attribute \src "libresoc.v:97667.3-97676.6" + wire width 3 $0\dec31_dec_sub16_sv_in2[2:0] + attribute \src "libresoc.v:97677.3-97686.6" + wire width 3 $0\dec31_dec_sub16_sv_in3[2:0] + attribute \src "libresoc.v:97687.3-97696.6" + wire width 3 $0\dec31_dec_sub16_sv_out[2:0] + attribute \src "libresoc.v:97727.3-97736.6" + wire width 2 $0\dec31_dec_sub16_upd[1:0] + attribute \src "libresoc.v:97293.7-97293.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:97887.3-97896.6" + wire width 2 $1\dec31_dec_sub16_SV_Etype[1:0] + attribute \src "libresoc.v:97897.3-97906.6" + wire width 2 $1\dec31_dec_sub16_SV_Ptype[1:0] + attribute \src "libresoc.v:97767.3-97776.6" + wire width 8 $1\dec31_dec_sub16_asmcode[7:0] + attribute \src "libresoc.v:97807.3-97816.6" + wire $1\dec31_dec_sub16_br[0:0] + attribute \src "libresoc.v:97637.3-97646.6" + wire width 3 $1\dec31_dec_sub16_cr_in[2:0] + attribute \src "libresoc.v:97647.3-97656.6" + wire width 3 $1\dec31_dec_sub16_cr_out[2:0] + attribute \src "libresoc.v:97757.3-97766.6" + wire width 2 $1\dec31_dec_sub16_cry_in[1:0] + attribute \src "libresoc.v:97797.3-97806.6" + wire $1\dec31_dec_sub16_cry_out[0:0] + attribute \src "libresoc.v:97847.3-97856.6" + wire width 5 $1\dec31_dec_sub16_form[4:0] + attribute \src "libresoc.v:97627.3-97636.6" + wire width 13 $1\dec31_dec_sub16_function_unit[12:0] + attribute \src "libresoc.v:97907.3-97916.6" + wire width 3 $1\dec31_dec_sub16_in1_sel[2:0] + attribute \src "libresoc.v:97917.3-97926.6" + wire width 4 $1\dec31_dec_sub16_in2_sel[3:0] + attribute \src "libresoc.v:97927.3-97936.6" + wire width 2 $1\dec31_dec_sub16_in3_sel[1:0] + attribute \src "libresoc.v:97737.3-97746.6" + wire width 7 $1\dec31_dec_sub16_internal_op[6:0] + attribute \src "libresoc.v:97777.3-97786.6" + wire $1\dec31_dec_sub16_inv_a[0:0] + attribute \src "libresoc.v:97787.3-97796.6" + wire $1\dec31_dec_sub16_inv_out[0:0] + attribute \src "libresoc.v:97837.3-97846.6" + wire $1\dec31_dec_sub16_is_32b[0:0] + attribute \src "libresoc.v:97717.3-97726.6" + wire width 4 $1\dec31_dec_sub16_ldst_len[3:0] + attribute \src "libresoc.v:97867.3-97876.6" + wire $1\dec31_dec_sub16_lk[0:0] + attribute \src "libresoc.v:97937.3-97946.6" + wire width 2 $1\dec31_dec_sub16_out_sel[1:0] + attribute \src "libresoc.v:97747.3-97756.6" + wire width 2 $1\dec31_dec_sub16_rc_sel[1:0] + attribute \src "libresoc.v:97827.3-97836.6" + wire $1\dec31_dec_sub16_rsrv[0:0] + attribute \src "libresoc.v:97877.3-97886.6" + wire $1\dec31_dec_sub16_sgl_pipe[0:0] + attribute \src "libresoc.v:97857.3-97866.6" + wire $1\dec31_dec_sub16_sgn[0:0] + attribute \src "libresoc.v:97817.3-97826.6" + wire $1\dec31_dec_sub16_sgn_ext[0:0] + attribute \src "libresoc.v:97697.3-97706.6" + wire width 3 $1\dec31_dec_sub16_sv_cr_in[2:0] + attribute \src "libresoc.v:97707.3-97716.6" + wire width 3 $1\dec31_dec_sub16_sv_cr_out[2:0] + attribute \src "libresoc.v:97657.3-97666.6" + wire width 3 $1\dec31_dec_sub16_sv_in1[2:0] + attribute \src "libresoc.v:97667.3-97676.6" + wire width 3 $1\dec31_dec_sub16_sv_in2[2:0] + attribute \src "libresoc.v:97677.3-97686.6" + wire width 3 $1\dec31_dec_sub16_sv_in3[2:0] + attribute \src "libresoc.v:97687.3-97696.6" + wire width 3 $1\dec31_dec_sub16_sv_out[2:0] + attribute \src "libresoc.v:97727.3-97736.6" + wire width 2 $1\dec31_dec_sub16_upd[1:0] + attribute \enum_base_type "SVEtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "EXTRA2" + attribute \enum_value_10 "EXTRA3" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 5 \dec31_dec_sub16_SV_Etype + attribute \enum_base_type "SVPtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "P1" + attribute \enum_value_10 "P2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 6 \dec31_dec_sub16_SV_Ptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 8 output 4 \dec31_dec_sub16_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 26 \dec31_dec_sub16_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 11 \dec31_dec_sub16_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 12 \dec31_dec_sub16_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 22 \dec31_dec_sub16_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 25 \dec31_dec_sub16_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 5 output 3 \dec31_dec_sub16_form + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 13 output 1 \dec31_dec_sub16_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 7 \dec31_dec_sub16_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 8 \dec31_dec_sub16_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 9 \dec31_dec_sub16_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 output 2 \dec31_dec_sub16_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 23 \dec31_dec_sub16_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 24 \dec31_dec_sub16_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 29 \dec31_dec_sub16_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 19 \dec31_dec_sub16_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 31 \dec31_dec_sub16_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 10 \dec31_dec_sub16_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 21 \dec31_dec_sub16_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 28 \dec31_dec_sub16_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 32 \dec31_dec_sub16_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 30 \dec31_dec_sub16_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 27 \dec31_dec_sub16_sgn_ext + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 17 \dec31_dec_sub16_sv_cr_in + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 18 \dec31_dec_sub16_sv_cr_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 13 \dec31_dec_sub16_sv_in1 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 14 \dec31_dec_sub16_sv_in2 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 15 \dec31_dec_sub16_sv_in3 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 16 \dec31_dec_sub16_sv_out + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 20 \dec31_dec_sub16_upd + attribute \src "libresoc.v:97293.7-97293.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + wire width 32 input 33 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + wire width 5 \opcode_switch + attribute \src "libresoc.v:97293.7-97293.20" + process $proc$libresoc.v:97293$3963 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:97627.3-97636.6" + process $proc$libresoc.v:97627$3931 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_function_unit[12:0] $1\dec31_dec_sub16_function_unit[12:0] + attribute \src "libresoc.v:97628.5-97628.29" + switch \initial + attribute \src "libresoc.v:97628.9-97628.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_function_unit[12:0] 13'0000001000000 + case + assign $1\dec31_dec_sub16_function_unit[12:0] 13'0000000000000 + end + sync always + update \dec31_dec_sub16_function_unit $0\dec31_dec_sub16_function_unit[12:0] + end + attribute \src "libresoc.v:97637.3-97646.6" + process $proc$libresoc.v:97637$3932 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_cr_in[2:0] $1\dec31_dec_sub16_cr_in[2:0] + attribute \src "libresoc.v:97638.5-97638.29" + switch \initial + attribute \src "libresoc.v:97638.9-97638.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_cr_in[2:0] 3'110 + case + assign $1\dec31_dec_sub16_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub16_cr_in $0\dec31_dec_sub16_cr_in[2:0] + end + attribute \src "libresoc.v:97647.3-97656.6" + process $proc$libresoc.v:97647$3933 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_cr_out[2:0] $1\dec31_dec_sub16_cr_out[2:0] + attribute \src "libresoc.v:97648.5-97648.29" + switch \initial + attribute \src "libresoc.v:97648.9-97648.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_cr_out[2:0] 3'100 + case + assign $1\dec31_dec_sub16_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub16_cr_out $0\dec31_dec_sub16_cr_out[2:0] + end + attribute \src "libresoc.v:97657.3-97666.6" + process $proc$libresoc.v:97657$3934 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_sv_in1[2:0] $1\dec31_dec_sub16_sv_in1[2:0] + attribute \src "libresoc.v:97658.5-97658.29" + switch \initial + attribute \src "libresoc.v:97658.9-97658.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_sv_in1[2:0] 3'010 + case + assign $1\dec31_dec_sub16_sv_in1[2:0] 3'000 + end + sync always + update \dec31_dec_sub16_sv_in1 $0\dec31_dec_sub16_sv_in1[2:0] + end + attribute \src "libresoc.v:97667.3-97676.6" + process $proc$libresoc.v:97667$3935 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_sv_in2[2:0] $1\dec31_dec_sub16_sv_in2[2:0] + attribute \src "libresoc.v:97668.5-97668.29" + switch \initial + attribute \src "libresoc.v:97668.9-97668.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_sv_in2[2:0] 3'000 + case + assign $1\dec31_dec_sub16_sv_in2[2:0] 3'000 + end + sync always + update \dec31_dec_sub16_sv_in2 $0\dec31_dec_sub16_sv_in2[2:0] + end + attribute \src "libresoc.v:97677.3-97686.6" + process $proc$libresoc.v:97677$3936 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_sv_in3[2:0] $1\dec31_dec_sub16_sv_in3[2:0] + attribute \src "libresoc.v:97678.5-97678.29" + switch \initial + attribute \src "libresoc.v:97678.9-97678.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_sv_in3[2:0] 3'000 + case + assign $1\dec31_dec_sub16_sv_in3[2:0] 3'000 + end + sync always + update \dec31_dec_sub16_sv_in3 $0\dec31_dec_sub16_sv_in3[2:0] + end + attribute \src "libresoc.v:97687.3-97696.6" + process $proc$libresoc.v:97687$3937 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_sv_out[2:0] $1\dec31_dec_sub16_sv_out[2:0] + attribute \src "libresoc.v:97688.5-97688.29" + switch \initial + attribute \src "libresoc.v:97688.9-97688.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_sv_out[2:0] 3'000 + case + assign $1\dec31_dec_sub16_sv_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub16_sv_out $0\dec31_dec_sub16_sv_out[2:0] + end + attribute \src "libresoc.v:97697.3-97706.6" + process $proc$libresoc.v:97697$3938 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_sv_cr_in[2:0] $1\dec31_dec_sub16_sv_cr_in[2:0] + attribute \src "libresoc.v:97698.5-97698.29" + switch \initial + attribute \src "libresoc.v:97698.9-97698.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_sv_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub16_sv_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub16_sv_cr_in $0\dec31_dec_sub16_sv_cr_in[2:0] + end + attribute \src "libresoc.v:97707.3-97716.6" + process $proc$libresoc.v:97707$3939 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_sv_cr_out[2:0] $1\dec31_dec_sub16_sv_cr_out[2:0] + attribute \src "libresoc.v:97708.5-97708.29" + switch \initial + attribute \src "libresoc.v:97708.9-97708.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_sv_cr_out[2:0] 3'000 + case + assign $1\dec31_dec_sub16_sv_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub16_sv_cr_out $0\dec31_dec_sub16_sv_cr_out[2:0] + end + attribute \src "libresoc.v:97717.3-97726.6" + process $proc$libresoc.v:97717$3940 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_ldst_len[3:0] $1\dec31_dec_sub16_ldst_len[3:0] + attribute \src "libresoc.v:97718.5-97718.29" + switch \initial + attribute \src "libresoc.v:97718.9-97718.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_ldst_len[3:0] 4'0000 + case + assign $1\dec31_dec_sub16_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub16_ldst_len $0\dec31_dec_sub16_ldst_len[3:0] + end + attribute \src "libresoc.v:97727.3-97736.6" + process $proc$libresoc.v:97727$3941 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_upd[1:0] $1\dec31_dec_sub16_upd[1:0] + attribute \src "libresoc.v:97728.5-97728.29" + switch \initial + attribute \src "libresoc.v:97728.9-97728.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_upd[1:0] 2'00 + case + assign $1\dec31_dec_sub16_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub16_upd $0\dec31_dec_sub16_upd[1:0] + end + attribute \src "libresoc.v:97737.3-97746.6" + process $proc$libresoc.v:97737$3942 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_internal_op[6:0] $1\dec31_dec_sub16_internal_op[6:0] + attribute \src "libresoc.v:97738.5-97738.29" + switch \initial + attribute \src "libresoc.v:97738.9-97738.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_internal_op[6:0] 7'0110000 + case + assign $1\dec31_dec_sub16_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub16_internal_op $0\dec31_dec_sub16_internal_op[6:0] + end + attribute \src "libresoc.v:97747.3-97756.6" + process $proc$libresoc.v:97747$3943 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_rc_sel[1:0] $1\dec31_dec_sub16_rc_sel[1:0] + attribute \src "libresoc.v:97748.5-97748.29" + switch \initial + attribute \src "libresoc.v:97748.9-97748.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_rc_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub16_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub16_rc_sel $0\dec31_dec_sub16_rc_sel[1:0] + end + attribute \src "libresoc.v:97757.3-97766.6" + process $proc$libresoc.v:97757$3944 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_cry_in[1:0] $1\dec31_dec_sub16_cry_in[1:0] + attribute \src "libresoc.v:97758.5-97758.29" + switch \initial + attribute \src "libresoc.v:97758.9-97758.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_cry_in[1:0] 2'00 + case + assign $1\dec31_dec_sub16_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub16_cry_in $0\dec31_dec_sub16_cry_in[1:0] + end + attribute \src "libresoc.v:97767.3-97776.6" + process $proc$libresoc.v:97767$3945 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_asmcode[7:0] $1\dec31_dec_sub16_asmcode[7:0] + attribute \src "libresoc.v:97768.5-97768.29" + switch \initial + attribute \src "libresoc.v:97768.9-97768.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_asmcode[7:0] 8'01110110 + case + assign $1\dec31_dec_sub16_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub16_asmcode $0\dec31_dec_sub16_asmcode[7:0] + end + attribute \src "libresoc.v:97777.3-97786.6" + process $proc$libresoc.v:97777$3946 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_inv_a[0:0] $1\dec31_dec_sub16_inv_a[0:0] + attribute \src "libresoc.v:97778.5-97778.29" + switch \initial + attribute \src "libresoc.v:97778.9-97778.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_inv_a[0:0] 1'0 + case + assign $1\dec31_dec_sub16_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub16_inv_a $0\dec31_dec_sub16_inv_a[0:0] + end + attribute \src "libresoc.v:97787.3-97796.6" + process $proc$libresoc.v:97787$3947 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_inv_out[0:0] $1\dec31_dec_sub16_inv_out[0:0] + attribute \src "libresoc.v:97788.5-97788.29" + switch \initial + attribute \src "libresoc.v:97788.9-97788.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub16_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub16_inv_out $0\dec31_dec_sub16_inv_out[0:0] + end + attribute \src "libresoc.v:97797.3-97806.6" + process $proc$libresoc.v:97797$3948 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_cry_out[0:0] $1\dec31_dec_sub16_cry_out[0:0] + attribute \src "libresoc.v:97798.5-97798.29" + switch \initial + attribute \src "libresoc.v:97798.9-97798.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_cry_out[0:0] 1'0 + case + assign $1\dec31_dec_sub16_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub16_cry_out $0\dec31_dec_sub16_cry_out[0:0] + end + attribute \src "libresoc.v:97807.3-97816.6" + process $proc$libresoc.v:97807$3949 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_br[0:0] $1\dec31_dec_sub16_br[0:0] + attribute \src "libresoc.v:97808.5-97808.29" + switch \initial + attribute \src "libresoc.v:97808.9-97808.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_br[0:0] 1'0 + case + assign $1\dec31_dec_sub16_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub16_br $0\dec31_dec_sub16_br[0:0] + end + attribute \src "libresoc.v:97817.3-97826.6" + process $proc$libresoc.v:97817$3950 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_sgn_ext[0:0] $1\dec31_dec_sub16_sgn_ext[0:0] + attribute \src "libresoc.v:97818.5-97818.29" + switch \initial + attribute \src "libresoc.v:97818.9-97818.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub16_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub16_sgn_ext $0\dec31_dec_sub16_sgn_ext[0:0] + end + attribute \src "libresoc.v:97827.3-97836.6" + process $proc$libresoc.v:97827$3951 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_rsrv[0:0] $1\dec31_dec_sub16_rsrv[0:0] + attribute \src "libresoc.v:97828.5-97828.29" + switch \initial + attribute \src "libresoc.v:97828.9-97828.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub16_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub16_rsrv $0\dec31_dec_sub16_rsrv[0:0] + end + attribute \src "libresoc.v:97837.3-97846.6" + process $proc$libresoc.v:97837$3952 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_is_32b[0:0] $1\dec31_dec_sub16_is_32b[0:0] + attribute \src "libresoc.v:97838.5-97838.29" + switch \initial + attribute \src "libresoc.v:97838.9-97838.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_is_32b[0:0] 1'0 + case + assign $1\dec31_dec_sub16_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub16_is_32b $0\dec31_dec_sub16_is_32b[0:0] + end + attribute \src "libresoc.v:97847.3-97856.6" + process $proc$libresoc.v:97847$3953 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_form[4:0] $1\dec31_dec_sub16_form[4:0] + attribute \src "libresoc.v:97848.5-97848.29" + switch \initial + attribute \src "libresoc.v:97848.9-97848.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_form[4:0] 5'01010 + case + assign $1\dec31_dec_sub16_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub16_form $0\dec31_dec_sub16_form[4:0] + end + attribute \src "libresoc.v:97857.3-97866.6" + process $proc$libresoc.v:97857$3954 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_sgn[0:0] $1\dec31_dec_sub16_sgn[0:0] + attribute \src "libresoc.v:97858.5-97858.29" + switch \initial + attribute \src "libresoc.v:97858.9-97858.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_sgn[0:0] 1'0 + case + assign $1\dec31_dec_sub16_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub16_sgn $0\dec31_dec_sub16_sgn[0:0] + end + attribute \src "libresoc.v:97867.3-97876.6" + process $proc$libresoc.v:97867$3955 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_lk[0:0] $1\dec31_dec_sub16_lk[0:0] + attribute \src "libresoc.v:97868.5-97868.29" + switch \initial + attribute \src "libresoc.v:97868.9-97868.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub16_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub16_lk $0\dec31_dec_sub16_lk[0:0] + end + attribute \src "libresoc.v:97877.3-97886.6" + process $proc$libresoc.v:97877$3956 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_sgl_pipe[0:0] $1\dec31_dec_sub16_sgl_pipe[0:0] + attribute \src "libresoc.v:97878.5-97878.29" + switch \initial + attribute \src "libresoc.v:97878.9-97878.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_sgl_pipe[0:0] 1'0 + case + assign $1\dec31_dec_sub16_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub16_sgl_pipe $0\dec31_dec_sub16_sgl_pipe[0:0] + end + attribute \src "libresoc.v:97887.3-97896.6" + process $proc$libresoc.v:97887$3957 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_SV_Etype[1:0] $1\dec31_dec_sub16_SV_Etype[1:0] + attribute \src "libresoc.v:97888.5-97888.29" + switch \initial + attribute \src "libresoc.v:97888.9-97888.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_SV_Etype[1:0] 2'01 + case + assign $1\dec31_dec_sub16_SV_Etype[1:0] 2'00 + end + sync always + update \dec31_dec_sub16_SV_Etype $0\dec31_dec_sub16_SV_Etype[1:0] + end + attribute \src "libresoc.v:97897.3-97906.6" + process $proc$libresoc.v:97897$3958 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_SV_Ptype[1:0] $1\dec31_dec_sub16_SV_Ptype[1:0] + attribute \src "libresoc.v:97898.5-97898.29" + switch \initial + attribute \src "libresoc.v:97898.9-97898.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_SV_Ptype[1:0] 2'10 + case + assign $1\dec31_dec_sub16_SV_Ptype[1:0] 2'00 + end + sync always + update \dec31_dec_sub16_SV_Ptype $0\dec31_dec_sub16_SV_Ptype[1:0] + end + attribute \src "libresoc.v:97907.3-97916.6" + process $proc$libresoc.v:97907$3959 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_in1_sel[2:0] $1\dec31_dec_sub16_in1_sel[2:0] + attribute \src "libresoc.v:97908.5-97908.29" + switch \initial + attribute \src "libresoc.v:97908.9-97908.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_in1_sel[2:0] 3'100 + case + assign $1\dec31_dec_sub16_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub16_in1_sel $0\dec31_dec_sub16_in1_sel[2:0] + end + attribute \src "libresoc.v:97917.3-97926.6" + process $proc$libresoc.v:97917$3960 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_in2_sel[3:0] $1\dec31_dec_sub16_in2_sel[3:0] + attribute \src "libresoc.v:97918.5-97918.29" + switch \initial + attribute \src "libresoc.v:97918.9-97918.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_in2_sel[3:0] 4'0000 + case + assign $1\dec31_dec_sub16_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub16_in2_sel $0\dec31_dec_sub16_in2_sel[3:0] + end + attribute \src "libresoc.v:97927.3-97936.6" + process $proc$libresoc.v:97927$3961 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_in3_sel[1:0] $1\dec31_dec_sub16_in3_sel[1:0] + attribute \src "libresoc.v:97928.5-97928.29" + switch \initial + attribute \src "libresoc.v:97928.9-97928.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_in3_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub16_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub16_in3_sel $0\dec31_dec_sub16_in3_sel[1:0] + end + attribute \src "libresoc.v:97937.3-97946.6" + process $proc$libresoc.v:97937$3962 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_out_sel[1:0] $1\dec31_dec_sub16_out_sel[1:0] + attribute \src "libresoc.v:97938.5-97938.29" + switch \initial + attribute \src "libresoc.v:97938.9-97938.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_out_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub16_out_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub16_out_sel $0\dec31_dec_sub16_out_sel[1:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:97952.1-98992.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub18" +attribute \generator "nMigen" +module \dec31_dec_sub18 + attribute \src "libresoc.v:98859.3-98880.6" + wire width 2 $0\dec31_dec_sub18_SV_Etype[1:0] + attribute \src "libresoc.v:98881.3-98902.6" + wire width 2 $0\dec31_dec_sub18_SV_Ptype[1:0] + attribute \src "libresoc.v:98595.3-98616.6" + wire width 8 $0\dec31_dec_sub18_asmcode[7:0] + attribute \src "libresoc.v:98683.3-98704.6" + wire $0\dec31_dec_sub18_br[0:0] + attribute \src "libresoc.v:98309.3-98330.6" + wire width 3 $0\dec31_dec_sub18_cr_in[2:0] + attribute \src "libresoc.v:98331.3-98352.6" + wire width 3 $0\dec31_dec_sub18_cr_out[2:0] + attribute \src "libresoc.v:98573.3-98594.6" + wire width 2 $0\dec31_dec_sub18_cry_in[1:0] + attribute \src "libresoc.v:98661.3-98682.6" + wire $0\dec31_dec_sub18_cry_out[0:0] + attribute \src "libresoc.v:98771.3-98792.6" + wire width 5 $0\dec31_dec_sub18_form[4:0] + attribute \src "libresoc.v:98287.3-98308.6" + wire width 13 $0\dec31_dec_sub18_function_unit[12:0] + attribute \src "libresoc.v:98903.3-98924.6" + wire width 3 $0\dec31_dec_sub18_in1_sel[2:0] + attribute \src "libresoc.v:98925.3-98946.6" + wire width 4 $0\dec31_dec_sub18_in2_sel[3:0] + attribute \src "libresoc.v:98947.3-98968.6" + wire width 2 $0\dec31_dec_sub18_in3_sel[1:0] + attribute \src "libresoc.v:98529.3-98550.6" + wire width 7 $0\dec31_dec_sub18_internal_op[6:0] + attribute \src "libresoc.v:98617.3-98638.6" + wire $0\dec31_dec_sub18_inv_a[0:0] + attribute \src "libresoc.v:98639.3-98660.6" + wire $0\dec31_dec_sub18_inv_out[0:0] + attribute \src "libresoc.v:98749.3-98770.6" + wire $0\dec31_dec_sub18_is_32b[0:0] + attribute \src "libresoc.v:98485.3-98506.6" + wire width 4 $0\dec31_dec_sub18_ldst_len[3:0] + attribute \src "libresoc.v:98815.3-98836.6" + wire $0\dec31_dec_sub18_lk[0:0] + attribute \src "libresoc.v:98969.3-98990.6" + wire width 2 $0\dec31_dec_sub18_out_sel[1:0] + attribute \src "libresoc.v:98551.3-98572.6" + wire width 2 $0\dec31_dec_sub18_rc_sel[1:0] + attribute \src "libresoc.v:98727.3-98748.6" + wire $0\dec31_dec_sub18_rsrv[0:0] + attribute \src "libresoc.v:98837.3-98858.6" + wire $0\dec31_dec_sub18_sgl_pipe[0:0] + attribute \src "libresoc.v:98793.3-98814.6" + wire $0\dec31_dec_sub18_sgn[0:0] + attribute \src "libresoc.v:98705.3-98726.6" + wire $0\dec31_dec_sub18_sgn_ext[0:0] + attribute \src "libresoc.v:98441.3-98462.6" + wire width 3 $0\dec31_dec_sub18_sv_cr_in[2:0] + attribute \src "libresoc.v:98463.3-98484.6" + wire width 3 $0\dec31_dec_sub18_sv_cr_out[2:0] + attribute \src "libresoc.v:98353.3-98374.6" + wire width 3 $0\dec31_dec_sub18_sv_in1[2:0] + attribute \src "libresoc.v:98375.3-98396.6" + wire width 3 $0\dec31_dec_sub18_sv_in2[2:0] + attribute \src "libresoc.v:98397.3-98418.6" + wire width 3 $0\dec31_dec_sub18_sv_in3[2:0] + attribute \src "libresoc.v:98419.3-98440.6" + wire width 3 $0\dec31_dec_sub18_sv_out[2:0] + attribute \src "libresoc.v:98507.3-98528.6" + wire width 2 $0\dec31_dec_sub18_upd[1:0] + attribute \src "libresoc.v:97953.7-97953.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:98859.3-98880.6" + wire width 2 $1\dec31_dec_sub18_SV_Etype[1:0] + attribute \src "libresoc.v:98881.3-98902.6" + wire width 2 $1\dec31_dec_sub18_SV_Ptype[1:0] + attribute \src "libresoc.v:98595.3-98616.6" + wire width 8 $1\dec31_dec_sub18_asmcode[7:0] + attribute \src "libresoc.v:98683.3-98704.6" + wire $1\dec31_dec_sub18_br[0:0] + attribute \src "libresoc.v:98309.3-98330.6" + wire width 3 $1\dec31_dec_sub18_cr_in[2:0] + attribute \src "libresoc.v:98331.3-98352.6" + wire width 3 $1\dec31_dec_sub18_cr_out[2:0] + attribute \src "libresoc.v:98573.3-98594.6" + wire width 2 $1\dec31_dec_sub18_cry_in[1:0] + attribute \src "libresoc.v:98661.3-98682.6" + wire $1\dec31_dec_sub18_cry_out[0:0] + attribute \src "libresoc.v:98771.3-98792.6" + wire width 5 $1\dec31_dec_sub18_form[4:0] + attribute \src "libresoc.v:98287.3-98308.6" + wire width 13 $1\dec31_dec_sub18_function_unit[12:0] + attribute \src "libresoc.v:98903.3-98924.6" + wire width 3 $1\dec31_dec_sub18_in1_sel[2:0] + attribute \src "libresoc.v:98925.3-98946.6" + wire width 4 $1\dec31_dec_sub18_in2_sel[3:0] + attribute \src "libresoc.v:98947.3-98968.6" + wire width 2 $1\dec31_dec_sub18_in3_sel[1:0] + attribute \src "libresoc.v:98529.3-98550.6" + wire width 7 $1\dec31_dec_sub18_internal_op[6:0] + attribute \src "libresoc.v:98617.3-98638.6" + wire $1\dec31_dec_sub18_inv_a[0:0] + attribute \src "libresoc.v:98639.3-98660.6" + wire $1\dec31_dec_sub18_inv_out[0:0] + attribute \src "libresoc.v:98749.3-98770.6" + wire $1\dec31_dec_sub18_is_32b[0:0] + attribute \src "libresoc.v:98485.3-98506.6" + wire width 4 $1\dec31_dec_sub18_ldst_len[3:0] + attribute \src "libresoc.v:98815.3-98836.6" + wire $1\dec31_dec_sub18_lk[0:0] + attribute \src "libresoc.v:98969.3-98990.6" + wire width 2 $1\dec31_dec_sub18_out_sel[1:0] + attribute \src "libresoc.v:98551.3-98572.6" + wire width 2 $1\dec31_dec_sub18_rc_sel[1:0] + attribute \src "libresoc.v:98727.3-98748.6" + wire $1\dec31_dec_sub18_rsrv[0:0] + attribute \src "libresoc.v:98837.3-98858.6" + wire $1\dec31_dec_sub18_sgl_pipe[0:0] + attribute \src "libresoc.v:98793.3-98814.6" + wire $1\dec31_dec_sub18_sgn[0:0] + attribute \src "libresoc.v:98705.3-98726.6" + wire $1\dec31_dec_sub18_sgn_ext[0:0] + attribute \src "libresoc.v:98441.3-98462.6" + wire width 3 $1\dec31_dec_sub18_sv_cr_in[2:0] + attribute \src "libresoc.v:98463.3-98484.6" + wire width 3 $1\dec31_dec_sub18_sv_cr_out[2:0] + attribute \src "libresoc.v:98353.3-98374.6" + wire width 3 $1\dec31_dec_sub18_sv_in1[2:0] + attribute \src "libresoc.v:98375.3-98396.6" + wire width 3 $1\dec31_dec_sub18_sv_in2[2:0] + attribute \src "libresoc.v:98397.3-98418.6" + wire width 3 $1\dec31_dec_sub18_sv_in3[2:0] + attribute \src "libresoc.v:98419.3-98440.6" + wire width 3 $1\dec31_dec_sub18_sv_out[2:0] + attribute \src "libresoc.v:98507.3-98528.6" + wire width 2 $1\dec31_dec_sub18_upd[1:0] + attribute \enum_base_type "SVEtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "EXTRA2" + attribute \enum_value_10 "EXTRA3" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 5 \dec31_dec_sub18_SV_Etype + attribute \enum_base_type "SVPtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "P1" + attribute \enum_value_10 "P2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 6 \dec31_dec_sub18_SV_Ptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 8 output 4 \dec31_dec_sub18_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 26 \dec31_dec_sub18_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 11 \dec31_dec_sub18_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 12 \dec31_dec_sub18_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 22 \dec31_dec_sub18_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 25 \dec31_dec_sub18_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 5 output 3 \dec31_dec_sub18_form + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 13 output 1 \dec31_dec_sub18_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 7 \dec31_dec_sub18_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 8 \dec31_dec_sub18_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 9 \dec31_dec_sub18_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 output 2 \dec31_dec_sub18_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 23 \dec31_dec_sub18_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 24 \dec31_dec_sub18_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 29 \dec31_dec_sub18_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 19 \dec31_dec_sub18_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 31 \dec31_dec_sub18_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 10 \dec31_dec_sub18_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 21 \dec31_dec_sub18_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 28 \dec31_dec_sub18_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 32 \dec31_dec_sub18_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 30 \dec31_dec_sub18_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 27 \dec31_dec_sub18_sgn_ext + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 17 \dec31_dec_sub18_sv_cr_in + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 18 \dec31_dec_sub18_sv_cr_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 13 \dec31_dec_sub18_sv_in1 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 14 \dec31_dec_sub18_sv_in2 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 15 \dec31_dec_sub18_sv_in3 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 16 \dec31_dec_sub18_sv_out + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 20 \dec31_dec_sub18_upd + attribute \src "libresoc.v:97953.7-97953.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + wire width 32 input 33 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + wire width 5 \opcode_switch + attribute \src "libresoc.v:97953.7-97953.20" + process $proc$libresoc.v:97953$3996 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:98287.3-98308.6" + process $proc$libresoc.v:98287$3964 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_function_unit[12:0] $1\dec31_dec_sub18_function_unit[12:0] + attribute \src "libresoc.v:98288.5-98288.29" + switch \initial + attribute \src "libresoc.v:98288.9-98288.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_function_unit[12:0] 13'0000010000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_function_unit[12:0] 13'0000010000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_function_unit[12:0] 13'0100000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_function_unit[12:0] 13'0100000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_function_unit[12:0] 13'0100000000000 + case + assign $1\dec31_dec_sub18_function_unit[12:0] 13'0000000000000 + end + sync always + update \dec31_dec_sub18_function_unit $0\dec31_dec_sub18_function_unit[12:0] + end + attribute \src "libresoc.v:98309.3-98330.6" + process $proc$libresoc.v:98309$3965 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_cr_in[2:0] $1\dec31_dec_sub18_cr_in[2:0] + attribute \src "libresoc.v:98310.5-98310.29" + switch \initial + attribute \src "libresoc.v:98310.9-98310.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub18_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub18_cr_in $0\dec31_dec_sub18_cr_in[2:0] + end + attribute \src "libresoc.v:98331.3-98352.6" + process $proc$libresoc.v:98331$3966 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_cr_out[2:0] $1\dec31_dec_sub18_cr_out[2:0] + attribute \src "libresoc.v:98332.5-98332.29" + switch \initial + attribute \src "libresoc.v:98332.9-98332.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_cr_out[2:0] 3'000 + case + assign $1\dec31_dec_sub18_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub18_cr_out $0\dec31_dec_sub18_cr_out[2:0] + end + attribute \src "libresoc.v:98353.3-98374.6" + process $proc$libresoc.v:98353$3967 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_sv_in1[2:0] $1\dec31_dec_sub18_sv_in1[2:0] + attribute \src "libresoc.v:98354.5-98354.29" + switch \initial + attribute \src "libresoc.v:98354.9-98354.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_sv_in1[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_sv_in1[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_sv_in1[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_sv_in1[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_sv_in1[2:0] 3'000 + case + assign $1\dec31_dec_sub18_sv_in1[2:0] 3'000 + end + sync always + update \dec31_dec_sub18_sv_in1 $0\dec31_dec_sub18_sv_in1[2:0] + end + attribute \src "libresoc.v:98375.3-98396.6" + process $proc$libresoc.v:98375$3968 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_sv_in2[2:0] $1\dec31_dec_sub18_sv_in2[2:0] + attribute \src "libresoc.v:98376.5-98376.29" + switch \initial + attribute \src "libresoc.v:98376.9-98376.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_sv_in2[2:0] 3'000 + case + assign $1\dec31_dec_sub18_sv_in2[2:0] 3'000 + end + sync always + update \dec31_dec_sub18_sv_in2 $0\dec31_dec_sub18_sv_in2[2:0] + end + attribute \src "libresoc.v:98397.3-98418.6" + process $proc$libresoc.v:98397$3969 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_sv_in3[2:0] $1\dec31_dec_sub18_sv_in3[2:0] + attribute \src "libresoc.v:98398.5-98398.29" + switch \initial + attribute \src "libresoc.v:98398.9-98398.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_sv_in3[2:0] 3'000 + case + assign $1\dec31_dec_sub18_sv_in3[2:0] 3'000 + end + sync always + update \dec31_dec_sub18_sv_in3 $0\dec31_dec_sub18_sv_in3[2:0] + end + attribute \src "libresoc.v:98419.3-98440.6" + process $proc$libresoc.v:98419$3970 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_sv_out[2:0] $1\dec31_dec_sub18_sv_out[2:0] + attribute \src "libresoc.v:98420.5-98420.29" + switch \initial + attribute \src "libresoc.v:98420.9-98420.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_sv_out[2:0] 3'000 + case + assign $1\dec31_dec_sub18_sv_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub18_sv_out $0\dec31_dec_sub18_sv_out[2:0] + end + attribute \src "libresoc.v:98441.3-98462.6" + process $proc$libresoc.v:98441$3971 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_sv_cr_in[2:0] $1\dec31_dec_sub18_sv_cr_in[2:0] + attribute \src "libresoc.v:98442.5-98442.29" + switch \initial + attribute \src "libresoc.v:98442.9-98442.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_sv_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub18_sv_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub18_sv_cr_in $0\dec31_dec_sub18_sv_cr_in[2:0] + end + attribute \src "libresoc.v:98463.3-98484.6" + process $proc$libresoc.v:98463$3972 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_sv_cr_out[2:0] $1\dec31_dec_sub18_sv_cr_out[2:0] + attribute \src "libresoc.v:98464.5-98464.29" + switch \initial + attribute \src "libresoc.v:98464.9-98464.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_sv_cr_out[2:0] 3'000 + case + assign $1\dec31_dec_sub18_sv_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub18_sv_cr_out $0\dec31_dec_sub18_sv_cr_out[2:0] + end + attribute \src "libresoc.v:98485.3-98506.6" + process $proc$libresoc.v:98485$3973 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_ldst_len[3:0] $1\dec31_dec_sub18_ldst_len[3:0] + attribute \src "libresoc.v:98486.5-98486.29" + switch \initial + attribute \src "libresoc.v:98486.9-98486.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_ldst_len[3:0] 4'0000 + case + assign $1\dec31_dec_sub18_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub18_ldst_len $0\dec31_dec_sub18_ldst_len[3:0] + end + attribute \src "libresoc.v:98507.3-98528.6" + process $proc$libresoc.v:98507$3974 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_upd[1:0] $1\dec31_dec_sub18_upd[1:0] + attribute \src "libresoc.v:98508.5-98508.29" + switch \initial + attribute \src "libresoc.v:98508.9-98508.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_upd[1:0] 2'00 + case + assign $1\dec31_dec_sub18_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub18_upd $0\dec31_dec_sub18_upd[1:0] + end + attribute \src "libresoc.v:98529.3-98550.6" + process $proc$libresoc.v:98529$3975 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_internal_op[6:0] $1\dec31_dec_sub18_internal_op[6:0] + attribute \src "libresoc.v:98530.5-98530.29" + switch \initial + attribute \src "libresoc.v:98530.9-98530.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_internal_op[6:0] 7'1001000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_internal_op[6:0] 7'1001010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_internal_op[6:0] 7'1001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_internal_op[6:0] 7'1001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_internal_op[6:0] 7'1001011 + case + assign $1\dec31_dec_sub18_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub18_internal_op $0\dec31_dec_sub18_internal_op[6:0] + end + attribute \src "libresoc.v:98551.3-98572.6" + process $proc$libresoc.v:98551$3976 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_rc_sel[1:0] $1\dec31_dec_sub18_rc_sel[1:0] + attribute \src "libresoc.v:98552.5-98552.29" + switch \initial + attribute \src "libresoc.v:98552.9-98552.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_rc_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub18_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub18_rc_sel $0\dec31_dec_sub18_rc_sel[1:0] + end + attribute \src "libresoc.v:98573.3-98594.6" + process $proc$libresoc.v:98573$3977 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_cry_in[1:0] $1\dec31_dec_sub18_cry_in[1:0] + attribute \src "libresoc.v:98574.5-98574.29" + switch \initial + attribute \src "libresoc.v:98574.9-98574.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_cry_in[1:0] 2'00 + case + assign $1\dec31_dec_sub18_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub18_cry_in $0\dec31_dec_sub18_cry_in[1:0] + end + attribute \src "libresoc.v:98595.3-98616.6" + process $proc$libresoc.v:98595$3978 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_asmcode[7:0] $1\dec31_dec_sub18_asmcode[7:0] + attribute \src "libresoc.v:98596.5-98596.29" + switch \initial + attribute \src "libresoc.v:98596.9-98596.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_asmcode[7:0] 8'01111000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_asmcode[7:0] 8'01110111 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_asmcode[7:0] 8'10011110 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_asmcode[7:0] 8'11001101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_asmcode[7:0] 8'11001110 + case + assign $1\dec31_dec_sub18_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub18_asmcode $0\dec31_dec_sub18_asmcode[7:0] + end + attribute \src "libresoc.v:98617.3-98638.6" + process $proc$libresoc.v:98617$3979 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_inv_a[0:0] $1\dec31_dec_sub18_inv_a[0:0] + attribute \src "libresoc.v:98618.5-98618.29" + switch \initial + attribute \src "libresoc.v:98618.9-98618.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_inv_a[0:0] 1'0 + case + assign $1\dec31_dec_sub18_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub18_inv_a $0\dec31_dec_sub18_inv_a[0:0] + end + attribute \src "libresoc.v:98639.3-98660.6" + process $proc$libresoc.v:98639$3980 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_inv_out[0:0] $1\dec31_dec_sub18_inv_out[0:0] + attribute \src "libresoc.v:98640.5-98640.29" + switch \initial + attribute \src "libresoc.v:98640.9-98640.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub18_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub18_inv_out $0\dec31_dec_sub18_inv_out[0:0] + end + attribute \src "libresoc.v:98661.3-98682.6" + process $proc$libresoc.v:98661$3981 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_cry_out[0:0] $1\dec31_dec_sub18_cry_out[0:0] + attribute \src "libresoc.v:98662.5-98662.29" + switch \initial + attribute \src "libresoc.v:98662.9-98662.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_cry_out[0:0] 1'0 + case + assign $1\dec31_dec_sub18_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub18_cry_out $0\dec31_dec_sub18_cry_out[0:0] + end + attribute \src "libresoc.v:98683.3-98704.6" + process $proc$libresoc.v:98683$3982 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_br[0:0] $1\dec31_dec_sub18_br[0:0] + attribute \src "libresoc.v:98684.5-98684.29" + switch \initial + attribute \src "libresoc.v:98684.9-98684.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_br[0:0] 1'0 + case + assign $1\dec31_dec_sub18_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub18_br $0\dec31_dec_sub18_br[0:0] + end + attribute \src "libresoc.v:98705.3-98726.6" + process $proc$libresoc.v:98705$3983 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_sgn_ext[0:0] $1\dec31_dec_sub18_sgn_ext[0:0] + attribute \src "libresoc.v:98706.5-98706.29" + switch \initial + attribute \src "libresoc.v:98706.9-98706.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub18_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub18_sgn_ext $0\dec31_dec_sub18_sgn_ext[0:0] + end + attribute \src "libresoc.v:98727.3-98748.6" + process $proc$libresoc.v:98727$3984 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_rsrv[0:0] $1\dec31_dec_sub18_rsrv[0:0] + attribute \src "libresoc.v:98728.5-98728.29" + switch \initial + attribute \src "libresoc.v:98728.9-98728.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub18_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub18_rsrv $0\dec31_dec_sub18_rsrv[0:0] + end + attribute \src "libresoc.v:98749.3-98770.6" + process $proc$libresoc.v:98749$3985 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_is_32b[0:0] $1\dec31_dec_sub18_is_32b[0:0] + attribute \src "libresoc.v:98750.5-98750.29" + switch \initial + attribute \src "libresoc.v:98750.9-98750.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_is_32b[0:0] 1'0 + case + assign $1\dec31_dec_sub18_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub18_is_32b $0\dec31_dec_sub18_is_32b[0:0] + end + attribute \src "libresoc.v:98771.3-98792.6" + process $proc$libresoc.v:98771$3986 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_form[4:0] $1\dec31_dec_sub18_form[4:0] + attribute \src "libresoc.v:98772.5-98772.29" + switch \initial + attribute \src "libresoc.v:98772.9-98772.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_form[4:0] 5'01000 + case + assign $1\dec31_dec_sub18_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub18_form $0\dec31_dec_sub18_form[4:0] + end + attribute \src "libresoc.v:98793.3-98814.6" + process $proc$libresoc.v:98793$3987 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_sgn[0:0] $1\dec31_dec_sub18_sgn[0:0] + attribute \src "libresoc.v:98794.5-98794.29" + switch \initial + attribute \src "libresoc.v:98794.9-98794.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_sgn[0:0] 1'0 + case + assign $1\dec31_dec_sub18_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub18_sgn $0\dec31_dec_sub18_sgn[0:0] + end + attribute \src "libresoc.v:98815.3-98836.6" + process $proc$libresoc.v:98815$3988 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_lk[0:0] $1\dec31_dec_sub18_lk[0:0] + attribute \src "libresoc.v:98816.5-98816.29" + switch \initial + attribute \src "libresoc.v:98816.9-98816.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub18_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub18_lk $0\dec31_dec_sub18_lk[0:0] + end + attribute \src "libresoc.v:98837.3-98858.6" + process $proc$libresoc.v:98837$3989 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_sgl_pipe[0:0] $1\dec31_dec_sub18_sgl_pipe[0:0] + attribute \src "libresoc.v:98838.5-98838.29" + switch \initial + attribute \src "libresoc.v:98838.9-98838.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_sgl_pipe[0:0] 1'0 + case + assign $1\dec31_dec_sub18_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub18_sgl_pipe $0\dec31_dec_sub18_sgl_pipe[0:0] + end + attribute \src "libresoc.v:98859.3-98880.6" + process $proc$libresoc.v:98859$3990 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_SV_Etype[1:0] $1\dec31_dec_sub18_SV_Etype[1:0] + attribute \src "libresoc.v:98860.5-98860.29" + switch \initial + attribute \src "libresoc.v:98860.9-98860.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_SV_Etype[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_SV_Etype[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_SV_Etype[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_SV_Etype[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_SV_Etype[1:0] 2'00 + case + assign $1\dec31_dec_sub18_SV_Etype[1:0] 2'00 + end + sync always + update \dec31_dec_sub18_SV_Etype $0\dec31_dec_sub18_SV_Etype[1:0] + end + attribute \src "libresoc.v:98881.3-98902.6" + process $proc$libresoc.v:98881$3991 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_SV_Ptype[1:0] $1\dec31_dec_sub18_SV_Ptype[1:0] + attribute \src "libresoc.v:98882.5-98882.29" + switch \initial + attribute \src "libresoc.v:98882.9-98882.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_SV_Ptype[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_SV_Ptype[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_SV_Ptype[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_SV_Ptype[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_SV_Ptype[1:0] 2'00 + case + assign $1\dec31_dec_sub18_SV_Ptype[1:0] 2'00 + end + sync always + update \dec31_dec_sub18_SV_Ptype $0\dec31_dec_sub18_SV_Ptype[1:0] + end + attribute \src "libresoc.v:98903.3-98924.6" + process $proc$libresoc.v:98903$3992 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_in1_sel[2:0] $1\dec31_dec_sub18_in1_sel[2:0] + attribute \src "libresoc.v:98904.5-98904.29" + switch \initial + attribute \src "libresoc.v:98904.9-98904.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_in1_sel[2:0] 3'000 + case + assign $1\dec31_dec_sub18_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub18_in1_sel $0\dec31_dec_sub18_in1_sel[2:0] + end + attribute \src "libresoc.v:98925.3-98946.6" + process $proc$libresoc.v:98925$3993 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_in2_sel[3:0] $1\dec31_dec_sub18_in2_sel[3:0] + attribute \src "libresoc.v:98926.5-98926.29" + switch \initial + attribute \src "libresoc.v:98926.9-98926.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_in2_sel[3:0] 4'0001 + case + assign $1\dec31_dec_sub18_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub18_in2_sel $0\dec31_dec_sub18_in2_sel[3:0] + end + attribute \src "libresoc.v:98947.3-98968.6" + process $proc$libresoc.v:98947$3994 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_in3_sel[1:0] $1\dec31_dec_sub18_in3_sel[1:0] + attribute \src "libresoc.v:98948.5-98948.29" + switch \initial + attribute \src "libresoc.v:98948.9-98948.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_in3_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub18_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub18_in3_sel $0\dec31_dec_sub18_in3_sel[1:0] + end + attribute \src "libresoc.v:98969.3-98990.6" + process $proc$libresoc.v:98969$3995 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_out_sel[1:0] $1\dec31_dec_sub18_out_sel[1:0] + attribute \src "libresoc.v:98970.5-98970.29" + switch \initial + attribute \src "libresoc.v:98970.9-98970.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_out_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub18_out_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub18_out_sel $0\dec31_dec_sub18_out_sel[1:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:98996.1-99940.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub19" +attribute \generator "nMigen" +module \dec31_dec_sub19 + attribute \src "libresoc.v:99825.3-99843.6" + wire width 2 $0\dec31_dec_sub19_SV_Etype[1:0] + attribute \src "libresoc.v:99844.3-99862.6" + wire width 2 $0\dec31_dec_sub19_SV_Ptype[1:0] + attribute \src "libresoc.v:99597.3-99615.6" + wire width 8 $0\dec31_dec_sub19_asmcode[7:0] + attribute \src "libresoc.v:99673.3-99691.6" + wire $0\dec31_dec_sub19_br[0:0] + attribute \src "libresoc.v:99350.3-99368.6" + wire width 3 $0\dec31_dec_sub19_cr_in[2:0] + attribute \src "libresoc.v:99369.3-99387.6" + wire width 3 $0\dec31_dec_sub19_cr_out[2:0] + attribute \src "libresoc.v:99578.3-99596.6" + wire width 2 $0\dec31_dec_sub19_cry_in[1:0] + attribute \src "libresoc.v:99654.3-99672.6" + wire $0\dec31_dec_sub19_cry_out[0:0] + attribute \src "libresoc.v:99749.3-99767.6" + wire width 5 $0\dec31_dec_sub19_form[4:0] + attribute \src "libresoc.v:99331.3-99349.6" + wire width 13 $0\dec31_dec_sub19_function_unit[12:0] + attribute \src "libresoc.v:99863.3-99881.6" + wire width 3 $0\dec31_dec_sub19_in1_sel[2:0] + attribute \src "libresoc.v:99882.3-99900.6" + wire width 4 $0\dec31_dec_sub19_in2_sel[3:0] + attribute \src "libresoc.v:99901.3-99919.6" + wire width 2 $0\dec31_dec_sub19_in3_sel[1:0] + attribute \src "libresoc.v:99540.3-99558.6" + wire width 7 $0\dec31_dec_sub19_internal_op[6:0] + attribute \src "libresoc.v:99616.3-99634.6" + wire $0\dec31_dec_sub19_inv_a[0:0] + attribute \src "libresoc.v:99635.3-99653.6" + wire $0\dec31_dec_sub19_inv_out[0:0] + attribute \src "libresoc.v:99730.3-99748.6" + wire $0\dec31_dec_sub19_is_32b[0:0] + attribute \src "libresoc.v:99502.3-99520.6" + wire width 4 $0\dec31_dec_sub19_ldst_len[3:0] + attribute \src "libresoc.v:99787.3-99805.6" + wire $0\dec31_dec_sub19_lk[0:0] + attribute \src "libresoc.v:99920.3-99938.6" + wire width 2 $0\dec31_dec_sub19_out_sel[1:0] + attribute \src "libresoc.v:99559.3-99577.6" + wire width 2 $0\dec31_dec_sub19_rc_sel[1:0] + attribute \src "libresoc.v:99711.3-99729.6" + wire $0\dec31_dec_sub19_rsrv[0:0] + attribute \src "libresoc.v:99806.3-99824.6" + wire $0\dec31_dec_sub19_sgl_pipe[0:0] + attribute \src "libresoc.v:99768.3-99786.6" + wire $0\dec31_dec_sub19_sgn[0:0] + attribute \src "libresoc.v:99692.3-99710.6" + wire $0\dec31_dec_sub19_sgn_ext[0:0] + attribute \src "libresoc.v:99464.3-99482.6" + wire width 3 $0\dec31_dec_sub19_sv_cr_in[2:0] + attribute \src "libresoc.v:99483.3-99501.6" + wire width 3 $0\dec31_dec_sub19_sv_cr_out[2:0] + attribute \src "libresoc.v:99388.3-99406.6" + wire width 3 $0\dec31_dec_sub19_sv_in1[2:0] + attribute \src "libresoc.v:99407.3-99425.6" + wire width 3 $0\dec31_dec_sub19_sv_in2[2:0] + attribute \src "libresoc.v:99426.3-99444.6" + wire width 3 $0\dec31_dec_sub19_sv_in3[2:0] + attribute \src "libresoc.v:99445.3-99463.6" + wire width 3 $0\dec31_dec_sub19_sv_out[2:0] + attribute \src "libresoc.v:99521.3-99539.6" + wire width 2 $0\dec31_dec_sub19_upd[1:0] + attribute \src "libresoc.v:98997.7-98997.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:99825.3-99843.6" + wire width 2 $1\dec31_dec_sub19_SV_Etype[1:0] + attribute \src "libresoc.v:99844.3-99862.6" + wire width 2 $1\dec31_dec_sub19_SV_Ptype[1:0] + attribute \src "libresoc.v:99597.3-99615.6" + wire width 8 $1\dec31_dec_sub19_asmcode[7:0] + attribute \src "libresoc.v:99673.3-99691.6" + wire $1\dec31_dec_sub19_br[0:0] + attribute \src "libresoc.v:99350.3-99368.6" + wire width 3 $1\dec31_dec_sub19_cr_in[2:0] + attribute \src "libresoc.v:99369.3-99387.6" + wire width 3 $1\dec31_dec_sub19_cr_out[2:0] + attribute \src "libresoc.v:99578.3-99596.6" + wire width 2 $1\dec31_dec_sub19_cry_in[1:0] + attribute \src "libresoc.v:99654.3-99672.6" + wire $1\dec31_dec_sub19_cry_out[0:0] + attribute \src "libresoc.v:99749.3-99767.6" + wire width 5 $1\dec31_dec_sub19_form[4:0] + attribute \src "libresoc.v:99331.3-99349.6" + wire width 13 $1\dec31_dec_sub19_function_unit[12:0] + attribute \src "libresoc.v:99863.3-99881.6" + wire width 3 $1\dec31_dec_sub19_in1_sel[2:0] + attribute \src "libresoc.v:99882.3-99900.6" + wire width 4 $1\dec31_dec_sub19_in2_sel[3:0] + attribute \src "libresoc.v:99901.3-99919.6" + wire width 2 $1\dec31_dec_sub19_in3_sel[1:0] + attribute \src "libresoc.v:99540.3-99558.6" + wire width 7 $1\dec31_dec_sub19_internal_op[6:0] + attribute \src "libresoc.v:99616.3-99634.6" + wire $1\dec31_dec_sub19_inv_a[0:0] + attribute \src "libresoc.v:99635.3-99653.6" + wire $1\dec31_dec_sub19_inv_out[0:0] + attribute \src "libresoc.v:99730.3-99748.6" + wire $1\dec31_dec_sub19_is_32b[0:0] + attribute \src "libresoc.v:99502.3-99520.6" + wire width 4 $1\dec31_dec_sub19_ldst_len[3:0] + attribute \src "libresoc.v:99787.3-99805.6" + wire $1\dec31_dec_sub19_lk[0:0] + attribute \src "libresoc.v:99920.3-99938.6" + wire width 2 $1\dec31_dec_sub19_out_sel[1:0] + attribute \src "libresoc.v:99559.3-99577.6" + wire width 2 $1\dec31_dec_sub19_rc_sel[1:0] + attribute \src "libresoc.v:99711.3-99729.6" + wire $1\dec31_dec_sub19_rsrv[0:0] + attribute \src "libresoc.v:99806.3-99824.6" + wire $1\dec31_dec_sub19_sgl_pipe[0:0] + attribute \src "libresoc.v:99768.3-99786.6" + wire $1\dec31_dec_sub19_sgn[0:0] + attribute \src "libresoc.v:99692.3-99710.6" + wire $1\dec31_dec_sub19_sgn_ext[0:0] + attribute \src "libresoc.v:99464.3-99482.6" + wire width 3 $1\dec31_dec_sub19_sv_cr_in[2:0] + attribute \src "libresoc.v:99483.3-99501.6" + wire width 3 $1\dec31_dec_sub19_sv_cr_out[2:0] + attribute \src "libresoc.v:99388.3-99406.6" + wire width 3 $1\dec31_dec_sub19_sv_in1[2:0] + attribute \src "libresoc.v:99407.3-99425.6" + wire width 3 $1\dec31_dec_sub19_sv_in2[2:0] + attribute \src "libresoc.v:99426.3-99444.6" + wire width 3 $1\dec31_dec_sub19_sv_in3[2:0] + attribute \src "libresoc.v:99445.3-99463.6" + wire width 3 $1\dec31_dec_sub19_sv_out[2:0] + attribute \src "libresoc.v:99521.3-99539.6" + wire width 2 $1\dec31_dec_sub19_upd[1:0] + attribute \enum_base_type "SVEtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "EXTRA2" + attribute \enum_value_10 "EXTRA3" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 5 \dec31_dec_sub19_SV_Etype + attribute \enum_base_type "SVPtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "P1" + attribute \enum_value_10 "P2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 6 \dec31_dec_sub19_SV_Ptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 8 output 4 \dec31_dec_sub19_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 26 \dec31_dec_sub19_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 11 \dec31_dec_sub19_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 12 \dec31_dec_sub19_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 22 \dec31_dec_sub19_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 25 \dec31_dec_sub19_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 5 output 3 \dec31_dec_sub19_form + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 13 output 1 \dec31_dec_sub19_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 7 \dec31_dec_sub19_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 8 \dec31_dec_sub19_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 9 \dec31_dec_sub19_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 output 2 \dec31_dec_sub19_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 23 \dec31_dec_sub19_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 24 \dec31_dec_sub19_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 29 \dec31_dec_sub19_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 19 \dec31_dec_sub19_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 31 \dec31_dec_sub19_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 10 \dec31_dec_sub19_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 21 \dec31_dec_sub19_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 28 \dec31_dec_sub19_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 32 \dec31_dec_sub19_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 30 \dec31_dec_sub19_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 27 \dec31_dec_sub19_sgn_ext + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 17 \dec31_dec_sub19_sv_cr_in + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 18 \dec31_dec_sub19_sv_cr_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 13 \dec31_dec_sub19_sv_in1 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 14 \dec31_dec_sub19_sv_in2 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 15 \dec31_dec_sub19_sv_in3 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 16 \dec31_dec_sub19_sv_out + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 20 \dec31_dec_sub19_upd + attribute \src "libresoc.v:98997.7-98997.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + wire width 32 input 33 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + wire width 5 \opcode_switch + attribute \src "libresoc.v:98997.7-98997.20" + process $proc$libresoc.v:98997$4029 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:99331.3-99349.6" + process $proc$libresoc.v:99331$3997 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_function_unit[12:0] $1\dec31_dec_sub19_function_unit[12:0] + attribute \src "libresoc.v:99332.5-99332.29" + switch \initial + attribute \src "libresoc.v:99332.9-99332.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_function_unit[12:0] 13'0000001000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_function_unit[12:0] 13'0000010000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_function_unit[12:0] 13'0010000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_function_unit[12:0] 13'0010000000000 + case + assign $1\dec31_dec_sub19_function_unit[12:0] 13'0000000000000 + end + sync always + update \dec31_dec_sub19_function_unit $0\dec31_dec_sub19_function_unit[12:0] + end + attribute \src "libresoc.v:99350.3-99368.6" + process $proc$libresoc.v:99350$3998 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_cr_in[2:0] $1\dec31_dec_sub19_cr_in[2:0] + attribute \src "libresoc.v:99351.5-99351.29" + switch \initial + attribute \src "libresoc.v:99351.9-99351.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_cr_in[2:0] 3'110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub19_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub19_cr_in $0\dec31_dec_sub19_cr_in[2:0] + end + attribute \src "libresoc.v:99369.3-99387.6" + process $proc$libresoc.v:99369$3999 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_cr_out[2:0] $1\dec31_dec_sub19_cr_out[2:0] + attribute \src "libresoc.v:99370.5-99370.29" + switch \initial + attribute \src "libresoc.v:99370.9-99370.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_cr_out[2:0] 3'000 + case + assign $1\dec31_dec_sub19_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub19_cr_out $0\dec31_dec_sub19_cr_out[2:0] + end + attribute \src "libresoc.v:99388.3-99406.6" + process $proc$libresoc.v:99388$4000 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_sv_in1[2:0] $1\dec31_dec_sub19_sv_in1[2:0] + attribute \src "libresoc.v:99389.5-99389.29" + switch \initial + attribute \src "libresoc.v:99389.9-99389.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_sv_in1[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_sv_in1[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_sv_in1[2:0] 3'010 + case + assign $1\dec31_dec_sub19_sv_in1[2:0] 3'000 + end + sync always + update \dec31_dec_sub19_sv_in1 $0\dec31_dec_sub19_sv_in1[2:0] + end + attribute \src "libresoc.v:99407.3-99425.6" + process $proc$libresoc.v:99407$4001 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_sv_in2[2:0] $1\dec31_dec_sub19_sv_in2[2:0] + attribute \src "libresoc.v:99408.5-99408.29" + switch \initial + attribute \src "libresoc.v:99408.9-99408.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_sv_in2[2:0] 3'000 + case + assign $1\dec31_dec_sub19_sv_in2[2:0] 3'000 + end + sync always + update \dec31_dec_sub19_sv_in2 $0\dec31_dec_sub19_sv_in2[2:0] + end + attribute \src "libresoc.v:99426.3-99444.6" + process $proc$libresoc.v:99426$4002 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_sv_in3[2:0] $1\dec31_dec_sub19_sv_in3[2:0] + attribute \src "libresoc.v:99427.5-99427.29" + switch \initial + attribute \src "libresoc.v:99427.9-99427.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_sv_in3[2:0] 3'000 + case + assign $1\dec31_dec_sub19_sv_in3[2:0] 3'000 + end + sync always + update \dec31_dec_sub19_sv_in3 $0\dec31_dec_sub19_sv_in3[2:0] + end + attribute \src "libresoc.v:99445.3-99463.6" + process $proc$libresoc.v:99445$4003 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_sv_out[2:0] $1\dec31_dec_sub19_sv_out[2:0] + attribute \src "libresoc.v:99446.5-99446.29" + switch \initial + attribute \src "libresoc.v:99446.9-99446.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_sv_out[2:0] 3'001 + case + assign $1\dec31_dec_sub19_sv_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub19_sv_out $0\dec31_dec_sub19_sv_out[2:0] + end + attribute \src "libresoc.v:99464.3-99482.6" + process $proc$libresoc.v:99464$4004 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_sv_cr_in[2:0] $1\dec31_dec_sub19_sv_cr_in[2:0] + attribute \src "libresoc.v:99465.5-99465.29" + switch \initial + attribute \src "libresoc.v:99465.9-99465.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_sv_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub19_sv_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub19_sv_cr_in $0\dec31_dec_sub19_sv_cr_in[2:0] + end + attribute \src "libresoc.v:99483.3-99501.6" + process $proc$libresoc.v:99483$4005 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_sv_cr_out[2:0] $1\dec31_dec_sub19_sv_cr_out[2:0] + attribute \src "libresoc.v:99484.5-99484.29" + switch \initial + attribute \src "libresoc.v:99484.9-99484.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_sv_cr_out[2:0] 3'000 + case + assign $1\dec31_dec_sub19_sv_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub19_sv_cr_out $0\dec31_dec_sub19_sv_cr_out[2:0] + end + attribute \src "libresoc.v:99502.3-99520.6" + process $proc$libresoc.v:99502$4006 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_ldst_len[3:0] $1\dec31_dec_sub19_ldst_len[3:0] + attribute \src "libresoc.v:99503.5-99503.29" + switch \initial + attribute \src "libresoc.v:99503.9-99503.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_ldst_len[3:0] 4'0000 + case + assign $1\dec31_dec_sub19_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub19_ldst_len $0\dec31_dec_sub19_ldst_len[3:0] + end + attribute \src "libresoc.v:99521.3-99539.6" + process $proc$libresoc.v:99521$4007 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_upd[1:0] $1\dec31_dec_sub19_upd[1:0] + attribute \src "libresoc.v:99522.5-99522.29" + switch \initial + attribute \src "libresoc.v:99522.9-99522.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_upd[1:0] 2'00 + case + assign $1\dec31_dec_sub19_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub19_upd $0\dec31_dec_sub19_upd[1:0] + end + attribute \src "libresoc.v:99540.3-99558.6" + process $proc$libresoc.v:99540$4008 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_internal_op[6:0] $1\dec31_dec_sub19_internal_op[6:0] + attribute \src "libresoc.v:99541.5-99541.29" + switch \initial + attribute \src "libresoc.v:99541.9-99541.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_internal_op[6:0] 7'0101101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_internal_op[6:0] 7'1000111 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_internal_op[6:0] 7'0101110 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_internal_op[6:0] 7'0110001 + case + assign $1\dec31_dec_sub19_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub19_internal_op $0\dec31_dec_sub19_internal_op[6:0] + end + attribute \src "libresoc.v:99559.3-99577.6" + process $proc$libresoc.v:99559$4009 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_rc_sel[1:0] $1\dec31_dec_sub19_rc_sel[1:0] + attribute \src "libresoc.v:99560.5-99560.29" + switch \initial + attribute \src "libresoc.v:99560.9-99560.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_rc_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub19_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub19_rc_sel $0\dec31_dec_sub19_rc_sel[1:0] + end + attribute \src "libresoc.v:99578.3-99596.6" + process $proc$libresoc.v:99578$4010 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_cry_in[1:0] $1\dec31_dec_sub19_cry_in[1:0] + attribute \src "libresoc.v:99579.5-99579.29" + switch \initial + attribute \src "libresoc.v:99579.9-99579.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_cry_in[1:0] 2'00 + case + assign $1\dec31_dec_sub19_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub19_cry_in $0\dec31_dec_sub19_cry_in[1:0] + end + attribute \src "libresoc.v:99597.3-99615.6" + process $proc$libresoc.v:99597$4011 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_asmcode[7:0] $1\dec31_dec_sub19_asmcode[7:0] + attribute \src "libresoc.v:99598.5-99598.29" + switch \initial + attribute \src "libresoc.v:99598.9-99598.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_asmcode[7:0] 8'01101111 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_asmcode[7:0] 8'01110000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_asmcode[7:0] 8'01110001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_asmcode[7:0] 8'01111001 + case + assign $1\dec31_dec_sub19_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub19_asmcode $0\dec31_dec_sub19_asmcode[7:0] + end + attribute \src "libresoc.v:99616.3-99634.6" + process $proc$libresoc.v:99616$4012 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_inv_a[0:0] $1\dec31_dec_sub19_inv_a[0:0] + attribute \src "libresoc.v:99617.5-99617.29" + switch \initial + attribute \src "libresoc.v:99617.9-99617.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_inv_a[0:0] 1'0 + case + assign $1\dec31_dec_sub19_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub19_inv_a $0\dec31_dec_sub19_inv_a[0:0] + end + attribute \src "libresoc.v:99635.3-99653.6" + process $proc$libresoc.v:99635$4013 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_inv_out[0:0] $1\dec31_dec_sub19_inv_out[0:0] + attribute \src "libresoc.v:99636.5-99636.29" + switch \initial + attribute \src "libresoc.v:99636.9-99636.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub19_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub19_inv_out $0\dec31_dec_sub19_inv_out[0:0] + end + attribute \src "libresoc.v:99654.3-99672.6" + process $proc$libresoc.v:99654$4014 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_cry_out[0:0] $1\dec31_dec_sub19_cry_out[0:0] + attribute \src "libresoc.v:99655.5-99655.29" + switch \initial + attribute \src "libresoc.v:99655.9-99655.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_cry_out[0:0] 1'0 + case + assign $1\dec31_dec_sub19_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub19_cry_out $0\dec31_dec_sub19_cry_out[0:0] + end + attribute \src "libresoc.v:99673.3-99691.6" + process $proc$libresoc.v:99673$4015 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_br[0:0] $1\dec31_dec_sub19_br[0:0] + attribute \src "libresoc.v:99674.5-99674.29" + switch \initial + attribute \src "libresoc.v:99674.9-99674.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_br[0:0] 1'0 + case + assign $1\dec31_dec_sub19_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub19_br $0\dec31_dec_sub19_br[0:0] + end + attribute \src "libresoc.v:99692.3-99710.6" + process $proc$libresoc.v:99692$4016 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_sgn_ext[0:0] $1\dec31_dec_sub19_sgn_ext[0:0] + attribute \src "libresoc.v:99693.5-99693.29" + switch \initial + attribute \src "libresoc.v:99693.9-99693.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub19_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub19_sgn_ext $0\dec31_dec_sub19_sgn_ext[0:0] + end + attribute \src "libresoc.v:99711.3-99729.6" + process $proc$libresoc.v:99711$4017 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_rsrv[0:0] $1\dec31_dec_sub19_rsrv[0:0] + attribute \src "libresoc.v:99712.5-99712.29" + switch \initial + attribute \src "libresoc.v:99712.9-99712.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub19_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub19_rsrv $0\dec31_dec_sub19_rsrv[0:0] + end + attribute \src "libresoc.v:99730.3-99748.6" + process $proc$libresoc.v:99730$4018 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_is_32b[0:0] $1\dec31_dec_sub19_is_32b[0:0] + attribute \src "libresoc.v:99731.5-99731.29" + switch \initial + attribute \src "libresoc.v:99731.9-99731.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_is_32b[0:0] 1'0 + case + assign $1\dec31_dec_sub19_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub19_is_32b $0\dec31_dec_sub19_is_32b[0:0] + end + attribute \src "libresoc.v:99749.3-99767.6" + process $proc$libresoc.v:99749$4019 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_form[4:0] $1\dec31_dec_sub19_form[4:0] + attribute \src "libresoc.v:99750.5-99750.29" + switch \initial + attribute \src "libresoc.v:99750.9-99750.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_form[4:0] 5'01010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_form[4:0] 5'01010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_form[4:0] 5'01010 + case + assign $1\dec31_dec_sub19_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub19_form $0\dec31_dec_sub19_form[4:0] + end + attribute \src "libresoc.v:99768.3-99786.6" + process $proc$libresoc.v:99768$4020 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_sgn[0:0] $1\dec31_dec_sub19_sgn[0:0] + attribute \src "libresoc.v:99769.5-99769.29" + switch \initial + attribute \src "libresoc.v:99769.9-99769.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_sgn[0:0] 1'0 + case + assign $1\dec31_dec_sub19_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub19_sgn $0\dec31_dec_sub19_sgn[0:0] + end + attribute \src "libresoc.v:99787.3-99805.6" + process $proc$libresoc.v:99787$4021 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_lk[0:0] $1\dec31_dec_sub19_lk[0:0] + attribute \src "libresoc.v:99788.5-99788.29" + switch \initial + attribute \src "libresoc.v:99788.9-99788.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub19_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub19_lk $0\dec31_dec_sub19_lk[0:0] + end + attribute \src "libresoc.v:99806.3-99824.6" + process $proc$libresoc.v:99806$4022 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_sgl_pipe[0:0] $1\dec31_dec_sub19_sgl_pipe[0:0] + attribute \src "libresoc.v:99807.5-99807.29" + switch \initial + attribute \src "libresoc.v:99807.9-99807.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_sgl_pipe[0:0] 1'0 + case + assign $1\dec31_dec_sub19_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub19_sgl_pipe $0\dec31_dec_sub19_sgl_pipe[0:0] + end + attribute \src "libresoc.v:99825.3-99843.6" + process $proc$libresoc.v:99825$4023 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_SV_Etype[1:0] $1\dec31_dec_sub19_SV_Etype[1:0] + attribute \src "libresoc.v:99826.5-99826.29" + switch \initial + attribute \src "libresoc.v:99826.9-99826.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_SV_Etype[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_SV_Etype[1:0] 2'10 + case + assign $1\dec31_dec_sub19_SV_Etype[1:0] 2'00 + end + sync always + update \dec31_dec_sub19_SV_Etype $0\dec31_dec_sub19_SV_Etype[1:0] + end + attribute \src "libresoc.v:99844.3-99862.6" + process $proc$libresoc.v:99844$4024 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_SV_Ptype[1:0] $1\dec31_dec_sub19_SV_Ptype[1:0] + attribute \src "libresoc.v:99845.5-99845.29" + switch \initial + attribute \src "libresoc.v:99845.9-99845.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_SV_Ptype[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_SV_Ptype[1:0] 2'10 + case + assign $1\dec31_dec_sub19_SV_Ptype[1:0] 2'00 + end + sync always + update \dec31_dec_sub19_SV_Ptype $0\dec31_dec_sub19_SV_Ptype[1:0] + end + attribute \src "libresoc.v:99863.3-99881.6" + process $proc$libresoc.v:99863$4025 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_in1_sel[2:0] $1\dec31_dec_sub19_in1_sel[2:0] + attribute \src "libresoc.v:99864.5-99864.29" + switch \initial + attribute \src "libresoc.v:99864.9-99864.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_in1_sel[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_in1_sel[2:0] 3'100 + case + assign $1\dec31_dec_sub19_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub19_in1_sel $0\dec31_dec_sub19_in1_sel[2:0] + end + attribute \src "libresoc.v:99882.3-99900.6" + process $proc$libresoc.v:99882$4026 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_in2_sel[3:0] $1\dec31_dec_sub19_in2_sel[3:0] + attribute \src "libresoc.v:99883.5-99883.29" + switch \initial + attribute \src "libresoc.v:99883.9-99883.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_in2_sel[3:0] 4'0000 + case + assign $1\dec31_dec_sub19_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub19_in2_sel $0\dec31_dec_sub19_in2_sel[3:0] + end + attribute \src "libresoc.v:99901.3-99919.6" + process $proc$libresoc.v:99901$4027 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_in3_sel[1:0] $1\dec31_dec_sub19_in3_sel[1:0] + attribute \src "libresoc.v:99902.5-99902.29" + switch \initial + attribute \src "libresoc.v:99902.9-99902.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_in3_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub19_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub19_in3_sel $0\dec31_dec_sub19_in3_sel[1:0] + end + attribute \src "libresoc.v:99920.3-99938.6" + process $proc$libresoc.v:99920$4028 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_out_sel[1:0] $1\dec31_dec_sub19_out_sel[1:0] + attribute \src "libresoc.v:99921.5-99921.29" + switch \initial + attribute \src "libresoc.v:99921.9-99921.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_out_sel[1:0] 2'11 + case + assign $1\dec31_dec_sub19_out_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub19_out_sel $0\dec31_dec_sub19_out_sel[1:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:99944.1-101080.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub20" +attribute \generator "nMigen" +module \dec31_dec_sub20 + attribute \src "libresoc.v:100929.3-100953.6" + wire width 2 $0\dec31_dec_sub20_SV_Etype[1:0] + attribute \src "libresoc.v:100954.3-100978.6" + wire width 2 $0\dec31_dec_sub20_SV_Ptype[1:0] + attribute \src "libresoc.v:100629.3-100653.6" + wire width 8 $0\dec31_dec_sub20_asmcode[7:0] + attribute \src "libresoc.v:100729.3-100753.6" + wire $0\dec31_dec_sub20_br[0:0] + attribute \src "libresoc.v:100304.3-100328.6" + wire width 3 $0\dec31_dec_sub20_cr_in[2:0] + attribute \src "libresoc.v:100329.3-100353.6" + wire width 3 $0\dec31_dec_sub20_cr_out[2:0] + attribute \src "libresoc.v:100604.3-100628.6" + wire width 2 $0\dec31_dec_sub20_cry_in[1:0] + attribute \src "libresoc.v:100704.3-100728.6" + wire $0\dec31_dec_sub20_cry_out[0:0] + attribute \src "libresoc.v:100829.3-100853.6" + wire width 5 $0\dec31_dec_sub20_form[4:0] + attribute \src "libresoc.v:100279.3-100303.6" + wire width 13 $0\dec31_dec_sub20_function_unit[12:0] + attribute \src "libresoc.v:100979.3-101003.6" + wire width 3 $0\dec31_dec_sub20_in1_sel[2:0] + attribute \src "libresoc.v:101004.3-101028.6" + wire width 4 $0\dec31_dec_sub20_in2_sel[3:0] + attribute \src "libresoc.v:101029.3-101053.6" + wire width 2 $0\dec31_dec_sub20_in3_sel[1:0] + attribute \src "libresoc.v:100554.3-100578.6" + wire width 7 $0\dec31_dec_sub20_internal_op[6:0] + attribute \src "libresoc.v:100654.3-100678.6" + wire $0\dec31_dec_sub20_inv_a[0:0] + attribute \src "libresoc.v:100679.3-100703.6" + wire $0\dec31_dec_sub20_inv_out[0:0] + attribute \src "libresoc.v:100804.3-100828.6" + wire $0\dec31_dec_sub20_is_32b[0:0] + attribute \src "libresoc.v:100504.3-100528.6" + wire width 4 $0\dec31_dec_sub20_ldst_len[3:0] + attribute \src "libresoc.v:100879.3-100903.6" + wire $0\dec31_dec_sub20_lk[0:0] + attribute \src "libresoc.v:101054.3-101078.6" + wire width 2 $0\dec31_dec_sub20_out_sel[1:0] + attribute \src "libresoc.v:100579.3-100603.6" + wire width 2 $0\dec31_dec_sub20_rc_sel[1:0] + attribute \src "libresoc.v:100779.3-100803.6" + wire $0\dec31_dec_sub20_rsrv[0:0] + attribute \src "libresoc.v:100904.3-100928.6" + wire $0\dec31_dec_sub20_sgl_pipe[0:0] + attribute \src "libresoc.v:100854.3-100878.6" + wire $0\dec31_dec_sub20_sgn[0:0] + attribute \src "libresoc.v:100754.3-100778.6" + wire $0\dec31_dec_sub20_sgn_ext[0:0] + attribute \src "libresoc.v:100454.3-100478.6" + wire width 3 $0\dec31_dec_sub20_sv_cr_in[2:0] + attribute \src "libresoc.v:100479.3-100503.6" + wire width 3 $0\dec31_dec_sub20_sv_cr_out[2:0] + attribute \src "libresoc.v:100354.3-100378.6" + wire width 3 $0\dec31_dec_sub20_sv_in1[2:0] + attribute \src "libresoc.v:100379.3-100403.6" + wire width 3 $0\dec31_dec_sub20_sv_in2[2:0] + attribute \src "libresoc.v:100404.3-100428.6" + wire width 3 $0\dec31_dec_sub20_sv_in3[2:0] + attribute \src "libresoc.v:100429.3-100453.6" + wire width 3 $0\dec31_dec_sub20_sv_out[2:0] + attribute \src "libresoc.v:100529.3-100553.6" + wire width 2 $0\dec31_dec_sub20_upd[1:0] + attribute \src "libresoc.v:99945.7-99945.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:100929.3-100953.6" + wire width 2 $1\dec31_dec_sub20_SV_Etype[1:0] + attribute \src "libresoc.v:100954.3-100978.6" + wire width 2 $1\dec31_dec_sub20_SV_Ptype[1:0] + attribute \src "libresoc.v:100629.3-100653.6" + wire width 8 $1\dec31_dec_sub20_asmcode[7:0] + attribute \src "libresoc.v:100729.3-100753.6" + wire $1\dec31_dec_sub20_br[0:0] + attribute \src "libresoc.v:100304.3-100328.6" + wire width 3 $1\dec31_dec_sub20_cr_in[2:0] + attribute \src "libresoc.v:100329.3-100353.6" + wire width 3 $1\dec31_dec_sub20_cr_out[2:0] + attribute \src "libresoc.v:100604.3-100628.6" + wire width 2 $1\dec31_dec_sub20_cry_in[1:0] + attribute \src "libresoc.v:100704.3-100728.6" + wire $1\dec31_dec_sub20_cry_out[0:0] + attribute \src "libresoc.v:100829.3-100853.6" + wire width 5 $1\dec31_dec_sub20_form[4:0] + attribute \src "libresoc.v:100279.3-100303.6" + wire width 13 $1\dec31_dec_sub20_function_unit[12:0] + attribute \src "libresoc.v:100979.3-101003.6" + wire width 3 $1\dec31_dec_sub20_in1_sel[2:0] + attribute \src "libresoc.v:101004.3-101028.6" + wire width 4 $1\dec31_dec_sub20_in2_sel[3:0] + attribute \src "libresoc.v:101029.3-101053.6" + wire width 2 $1\dec31_dec_sub20_in3_sel[1:0] + attribute \src "libresoc.v:100554.3-100578.6" + wire width 7 $1\dec31_dec_sub20_internal_op[6:0] + attribute \src "libresoc.v:100654.3-100678.6" + wire $1\dec31_dec_sub20_inv_a[0:0] + attribute \src "libresoc.v:100679.3-100703.6" + wire $1\dec31_dec_sub20_inv_out[0:0] + attribute \src "libresoc.v:100804.3-100828.6" + wire $1\dec31_dec_sub20_is_32b[0:0] + attribute \src "libresoc.v:100504.3-100528.6" + wire width 4 $1\dec31_dec_sub20_ldst_len[3:0] + attribute \src "libresoc.v:100879.3-100903.6" + wire $1\dec31_dec_sub20_lk[0:0] + attribute \src "libresoc.v:101054.3-101078.6" + wire width 2 $1\dec31_dec_sub20_out_sel[1:0] + attribute \src "libresoc.v:100579.3-100603.6" + wire width 2 $1\dec31_dec_sub20_rc_sel[1:0] + attribute \src "libresoc.v:100779.3-100803.6" + wire $1\dec31_dec_sub20_rsrv[0:0] + attribute \src "libresoc.v:100904.3-100928.6" + wire $1\dec31_dec_sub20_sgl_pipe[0:0] + attribute \src "libresoc.v:100854.3-100878.6" + wire $1\dec31_dec_sub20_sgn[0:0] + attribute \src "libresoc.v:100754.3-100778.6" + wire $1\dec31_dec_sub20_sgn_ext[0:0] + attribute \src "libresoc.v:100454.3-100478.6" + wire width 3 $1\dec31_dec_sub20_sv_cr_in[2:0] + attribute \src "libresoc.v:100479.3-100503.6" + wire width 3 $1\dec31_dec_sub20_sv_cr_out[2:0] + attribute \src "libresoc.v:100354.3-100378.6" + wire width 3 $1\dec31_dec_sub20_sv_in1[2:0] + attribute \src "libresoc.v:100379.3-100403.6" + wire width 3 $1\dec31_dec_sub20_sv_in2[2:0] + attribute \src "libresoc.v:100404.3-100428.6" + wire width 3 $1\dec31_dec_sub20_sv_in3[2:0] + attribute \src "libresoc.v:100429.3-100453.6" + wire width 3 $1\dec31_dec_sub20_sv_out[2:0] + attribute \src "libresoc.v:100529.3-100553.6" + wire width 2 $1\dec31_dec_sub20_upd[1:0] + attribute \enum_base_type "SVEtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "EXTRA2" + attribute \enum_value_10 "EXTRA3" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 5 \dec31_dec_sub20_SV_Etype + attribute \enum_base_type "SVPtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "P1" + attribute \enum_value_10 "P2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 6 \dec31_dec_sub20_SV_Ptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 8 output 4 \dec31_dec_sub20_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 26 \dec31_dec_sub20_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 11 \dec31_dec_sub20_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 12 \dec31_dec_sub20_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 22 \dec31_dec_sub20_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 25 \dec31_dec_sub20_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 5 output 3 \dec31_dec_sub20_form + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 13 output 1 \dec31_dec_sub20_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 7 \dec31_dec_sub20_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 8 \dec31_dec_sub20_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 9 \dec31_dec_sub20_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 output 2 \dec31_dec_sub20_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 23 \dec31_dec_sub20_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 24 \dec31_dec_sub20_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 29 \dec31_dec_sub20_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 19 \dec31_dec_sub20_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 31 \dec31_dec_sub20_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 10 \dec31_dec_sub20_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 21 \dec31_dec_sub20_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 28 \dec31_dec_sub20_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 32 \dec31_dec_sub20_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 30 \dec31_dec_sub20_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 27 \dec31_dec_sub20_sgn_ext + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 17 \dec31_dec_sub20_sv_cr_in + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 18 \dec31_dec_sub20_sv_cr_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 13 \dec31_dec_sub20_sv_in1 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 14 \dec31_dec_sub20_sv_in2 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 15 \dec31_dec_sub20_sv_in3 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 16 \dec31_dec_sub20_sv_out + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 20 \dec31_dec_sub20_upd + attribute \src "libresoc.v:99945.7-99945.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + wire width 32 input 33 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + wire width 5 \opcode_switch + attribute \src "libresoc.v:100279.3-100303.6" + process $proc$libresoc.v:100279$4030 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_function_unit[12:0] $1\dec31_dec_sub20_function_unit[12:0] + attribute \src "libresoc.v:100280.5-100280.29" + switch \initial + attribute \src "libresoc.v:100280.9-100280.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_function_unit[12:0] 13'0000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_function_unit[12:0] 13'0000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_function_unit[12:0] 13'0000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_function_unit[12:0] 13'0000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_function_unit[12:0] 13'0000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_function_unit[12:0] 13'0000000000100 + case + assign $1\dec31_dec_sub20_function_unit[12:0] 13'0000000000000 + end + sync always + update \dec31_dec_sub20_function_unit $0\dec31_dec_sub20_function_unit[12:0] + end + attribute \src "libresoc.v:100304.3-100328.6" + process $proc$libresoc.v:100304$4031 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_cr_in[2:0] $1\dec31_dec_sub20_cr_in[2:0] + attribute \src "libresoc.v:100305.5-100305.29" + switch \initial + attribute \src "libresoc.v:100305.9-100305.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub20_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub20_cr_in $0\dec31_dec_sub20_cr_in[2:0] + end + attribute \src "libresoc.v:100329.3-100353.6" + process $proc$libresoc.v:100329$4032 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_cr_out[2:0] $1\dec31_dec_sub20_cr_out[2:0] + attribute \src "libresoc.v:100330.5-100330.29" + switch \initial + attribute \src "libresoc.v:100330.9-100330.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_cr_out[2:0] 3'000 + case + assign $1\dec31_dec_sub20_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub20_cr_out $0\dec31_dec_sub20_cr_out[2:0] + end + attribute \src "libresoc.v:100354.3-100378.6" + process $proc$libresoc.v:100354$4033 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_sv_in1[2:0] $1\dec31_dec_sub20_sv_in1[2:0] + attribute \src "libresoc.v:100355.5-100355.29" + switch \initial + attribute \src "libresoc.v:100355.9-100355.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_sv_in1[2:0] 3'010 + case + assign $1\dec31_dec_sub20_sv_in1[2:0] 3'000 + end + sync always + update \dec31_dec_sub20_sv_in1 $0\dec31_dec_sub20_sv_in1[2:0] + end + attribute \src "libresoc.v:100379.3-100403.6" + process $proc$libresoc.v:100379$4034 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_sv_in2[2:0] $1\dec31_dec_sub20_sv_in2[2:0] + attribute \src "libresoc.v:100380.5-100380.29" + switch \initial + attribute \src "libresoc.v:100380.9-100380.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_sv_in2[2:0] 3'011 + case + assign $1\dec31_dec_sub20_sv_in2[2:0] 3'000 + end + sync always + update \dec31_dec_sub20_sv_in2 $0\dec31_dec_sub20_sv_in2[2:0] + end + attribute \src "libresoc.v:100404.3-100428.6" + process $proc$libresoc.v:100404$4035 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_sv_in3[2:0] $1\dec31_dec_sub20_sv_in3[2:0] + attribute \src "libresoc.v:100405.5-100405.29" + switch \initial + attribute \src "libresoc.v:100405.9-100405.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_sv_in3[2:0] 3'001 + case + assign $1\dec31_dec_sub20_sv_in3[2:0] 3'000 + end + sync always + update \dec31_dec_sub20_sv_in3 $0\dec31_dec_sub20_sv_in3[2:0] + end + attribute \src "libresoc.v:100429.3-100453.6" + process $proc$libresoc.v:100429$4036 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_sv_out[2:0] $1\dec31_dec_sub20_sv_out[2:0] + attribute \src "libresoc.v:100430.5-100430.29" + switch \initial + attribute \src "libresoc.v:100430.9-100430.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_sv_out[2:0] 3'000 + case + assign $1\dec31_dec_sub20_sv_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub20_sv_out $0\dec31_dec_sub20_sv_out[2:0] + end + attribute \src "libresoc.v:100454.3-100478.6" + process $proc$libresoc.v:100454$4037 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_sv_cr_in[2:0] $1\dec31_dec_sub20_sv_cr_in[2:0] + attribute \src "libresoc.v:100455.5-100455.29" + switch \initial + attribute \src "libresoc.v:100455.9-100455.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_sv_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub20_sv_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub20_sv_cr_in $0\dec31_dec_sub20_sv_cr_in[2:0] + end + attribute \src "libresoc.v:100479.3-100503.6" + process $proc$libresoc.v:100479$4038 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_sv_cr_out[2:0] $1\dec31_dec_sub20_sv_cr_out[2:0] + attribute \src "libresoc.v:100480.5-100480.29" + switch \initial + attribute \src "libresoc.v:100480.9-100480.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_sv_cr_out[2:0] 3'000 + case + assign $1\dec31_dec_sub20_sv_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub20_sv_cr_out $0\dec31_dec_sub20_sv_cr_out[2:0] + end + attribute \src "libresoc.v:100504.3-100528.6" + process $proc$libresoc.v:100504$4039 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_ldst_len[3:0] $1\dec31_dec_sub20_ldst_len[3:0] + attribute \src "libresoc.v:100505.5-100505.29" + switch \initial + attribute \src "libresoc.v:100505.9-100505.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_ldst_len[3:0] 4'1000 + case + assign $1\dec31_dec_sub20_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub20_ldst_len $0\dec31_dec_sub20_ldst_len[3:0] + end + attribute \src "libresoc.v:100529.3-100553.6" + process $proc$libresoc.v:100529$4040 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_upd[1:0] $1\dec31_dec_sub20_upd[1:0] + attribute \src "libresoc.v:100530.5-100530.29" + switch \initial + attribute \src "libresoc.v:100530.9-100530.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_upd[1:0] 2'00 + case + assign $1\dec31_dec_sub20_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub20_upd $0\dec31_dec_sub20_upd[1:0] + end + attribute \src "libresoc.v:100554.3-100578.6" + process $proc$libresoc.v:100554$4041 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_internal_op[6:0] $1\dec31_dec_sub20_internal_op[6:0] + attribute \src "libresoc.v:100555.5-100555.29" + switch \initial + attribute \src "libresoc.v:100555.9-100555.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_internal_op[6:0] 7'0100110 + case + assign $1\dec31_dec_sub20_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub20_internal_op $0\dec31_dec_sub20_internal_op[6:0] + end + attribute \src "libresoc.v:100579.3-100603.6" + process $proc$libresoc.v:100579$4042 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_rc_sel[1:0] $1\dec31_dec_sub20_rc_sel[1:0] + attribute \src "libresoc.v:100580.5-100580.29" + switch \initial + attribute \src "libresoc.v:100580.9-100580.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_rc_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub20_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub20_rc_sel $0\dec31_dec_sub20_rc_sel[1:0] + end + attribute \src "libresoc.v:100604.3-100628.6" + process $proc$libresoc.v:100604$4043 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_cry_in[1:0] $1\dec31_dec_sub20_cry_in[1:0] + attribute \src "libresoc.v:100605.5-100605.29" + switch \initial + attribute \src "libresoc.v:100605.9-100605.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_cry_in[1:0] 2'00 + case + assign $1\dec31_dec_sub20_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub20_cry_in $0\dec31_dec_sub20_cry_in[1:0] + end + attribute \src "libresoc.v:100629.3-100653.6" + process $proc$libresoc.v:100629$4044 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_asmcode[7:0] $1\dec31_dec_sub20_asmcode[7:0] + attribute \src "libresoc.v:100630.5-100630.29" + switch \initial + attribute \src "libresoc.v:100630.9-100630.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_asmcode[7:0] 8'01001101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_asmcode[7:0] 8'01010011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_asmcode[7:0] 8'01010100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_asmcode[7:0] 8'01011001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_asmcode[7:0] 8'01100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_asmcode[7:0] 8'10101110 + case + assign $1\dec31_dec_sub20_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub20_asmcode $0\dec31_dec_sub20_asmcode[7:0] + end + attribute \src "libresoc.v:100654.3-100678.6" + process $proc$libresoc.v:100654$4045 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_inv_a[0:0] $1\dec31_dec_sub20_inv_a[0:0] + attribute \src "libresoc.v:100655.5-100655.29" + switch \initial + attribute \src "libresoc.v:100655.9-100655.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_inv_a[0:0] 1'0 + case + assign $1\dec31_dec_sub20_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub20_inv_a $0\dec31_dec_sub20_inv_a[0:0] + end + attribute \src "libresoc.v:100679.3-100703.6" + process $proc$libresoc.v:100679$4046 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_inv_out[0:0] $1\dec31_dec_sub20_inv_out[0:0] + attribute \src "libresoc.v:100680.5-100680.29" + switch \initial + attribute \src "libresoc.v:100680.9-100680.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub20_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub20_inv_out $0\dec31_dec_sub20_inv_out[0:0] + end + attribute \src "libresoc.v:100704.3-100728.6" + process $proc$libresoc.v:100704$4047 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_cry_out[0:0] $1\dec31_dec_sub20_cry_out[0:0] + attribute \src "libresoc.v:100705.5-100705.29" + switch \initial + attribute \src "libresoc.v:100705.9-100705.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_cry_out[0:0] 1'0 + case + assign $1\dec31_dec_sub20_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub20_cry_out $0\dec31_dec_sub20_cry_out[0:0] + end + attribute \src "libresoc.v:100729.3-100753.6" + process $proc$libresoc.v:100729$4048 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_br[0:0] $1\dec31_dec_sub20_br[0:0] + attribute \src "libresoc.v:100730.5-100730.29" + switch \initial + attribute \src "libresoc.v:100730.9-100730.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_br[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_br[0:0] 1'1 + case + assign $1\dec31_dec_sub20_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub20_br $0\dec31_dec_sub20_br[0:0] + end + attribute \src "libresoc.v:100754.3-100778.6" + process $proc$libresoc.v:100754$4049 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_sgn_ext[0:0] $1\dec31_dec_sub20_sgn_ext[0:0] + attribute \src "libresoc.v:100755.5-100755.29" + switch \initial + attribute \src "libresoc.v:100755.9-100755.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub20_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub20_sgn_ext $0\dec31_dec_sub20_sgn_ext[0:0] + end + attribute \src "libresoc.v:100779.3-100803.6" + process $proc$libresoc.v:100779$4050 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_rsrv[0:0] $1\dec31_dec_sub20_rsrv[0:0] + attribute \src "libresoc.v:100780.5-100780.29" + switch \initial + attribute \src "libresoc.v:100780.9-100780.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_rsrv[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_rsrv[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_rsrv[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_rsrv[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub20_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub20_rsrv $0\dec31_dec_sub20_rsrv[0:0] + end + attribute \src "libresoc.v:100804.3-100828.6" + process $proc$libresoc.v:100804$4051 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_is_32b[0:0] $1\dec31_dec_sub20_is_32b[0:0] + attribute \src "libresoc.v:100805.5-100805.29" + switch \initial + attribute \src "libresoc.v:100805.9-100805.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_is_32b[0:0] 1'0 + case + assign $1\dec31_dec_sub20_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub20_is_32b $0\dec31_dec_sub20_is_32b[0:0] + end + attribute \src "libresoc.v:100829.3-100853.6" + process $proc$libresoc.v:100829$4052 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_form[4:0] $1\dec31_dec_sub20_form[4:0] + attribute \src "libresoc.v:100830.5-100830.29" + switch \initial + attribute \src "libresoc.v:100830.9-100830.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_form[4:0] 5'01000 + case + assign $1\dec31_dec_sub20_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub20_form $0\dec31_dec_sub20_form[4:0] + end + attribute \src "libresoc.v:100854.3-100878.6" + process $proc$libresoc.v:100854$4053 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_sgn[0:0] $1\dec31_dec_sub20_sgn[0:0] + attribute \src "libresoc.v:100855.5-100855.29" + switch \initial + attribute \src "libresoc.v:100855.9-100855.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_sgn[0:0] 1'0 + case + assign $1\dec31_dec_sub20_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub20_sgn $0\dec31_dec_sub20_sgn[0:0] + end + attribute \src "libresoc.v:100879.3-100903.6" + process $proc$libresoc.v:100879$4054 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_lk[0:0] $1\dec31_dec_sub20_lk[0:0] + attribute \src "libresoc.v:100880.5-100880.29" + switch \initial + attribute \src "libresoc.v:100880.9-100880.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub20_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub20_lk $0\dec31_dec_sub20_lk[0:0] + end + attribute \src "libresoc.v:100904.3-100928.6" + process $proc$libresoc.v:100904$4055 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_sgl_pipe[0:0] $1\dec31_dec_sub20_sgl_pipe[0:0] + attribute \src "libresoc.v:100905.5-100905.29" + switch \initial + attribute \src "libresoc.v:100905.9-100905.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_sgl_pipe[0:0] 1'1 + case + assign $1\dec31_dec_sub20_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub20_sgl_pipe $0\dec31_dec_sub20_sgl_pipe[0:0] + end + attribute \src "libresoc.v:100929.3-100953.6" + process $proc$libresoc.v:100929$4056 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_SV_Etype[1:0] $1\dec31_dec_sub20_SV_Etype[1:0] + attribute \src "libresoc.v:100930.5-100930.29" + switch \initial + attribute \src "libresoc.v:100930.9-100930.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_SV_Etype[1:0] 2'01 + case + assign $1\dec31_dec_sub20_SV_Etype[1:0] 2'00 + end + sync always + update \dec31_dec_sub20_SV_Etype $0\dec31_dec_sub20_SV_Etype[1:0] + end + attribute \src "libresoc.v:100954.3-100978.6" + process $proc$libresoc.v:100954$4057 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_SV_Ptype[1:0] $1\dec31_dec_sub20_SV_Ptype[1:0] + attribute \src "libresoc.v:100955.5-100955.29" + switch \initial + attribute \src "libresoc.v:100955.9-100955.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_SV_Ptype[1:0] 2'10 + case + assign $1\dec31_dec_sub20_SV_Ptype[1:0] 2'00 + end + sync always + update \dec31_dec_sub20_SV_Ptype $0\dec31_dec_sub20_SV_Ptype[1:0] + end + attribute \src "libresoc.v:100979.3-101003.6" + process $proc$libresoc.v:100979$4058 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_in1_sel[2:0] $1\dec31_dec_sub20_in1_sel[2:0] + attribute \src "libresoc.v:100980.5-100980.29" + switch \initial + attribute \src "libresoc.v:100980.9-100980.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_in1_sel[2:0] 3'010 + case + assign $1\dec31_dec_sub20_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub20_in1_sel $0\dec31_dec_sub20_in1_sel[2:0] + end + attribute \src "libresoc.v:101004.3-101028.6" + process $proc$libresoc.v:101004$4059 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_in2_sel[3:0] $1\dec31_dec_sub20_in2_sel[3:0] + attribute \src "libresoc.v:101005.5-101005.29" + switch \initial + attribute \src "libresoc.v:101005.9-101005.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_in2_sel[3:0] 4'0001 + case + assign $1\dec31_dec_sub20_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub20_in2_sel $0\dec31_dec_sub20_in2_sel[3:0] + end + attribute \src "libresoc.v:101029.3-101053.6" + process $proc$libresoc.v:101029$4060 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_in3_sel[1:0] $1\dec31_dec_sub20_in3_sel[1:0] + attribute \src "libresoc.v:101030.5-101030.29" + switch \initial + attribute \src "libresoc.v:101030.9-101030.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_in3_sel[1:0] 2'01 + case + assign $1\dec31_dec_sub20_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub20_in3_sel $0\dec31_dec_sub20_in3_sel[1:0] + end + attribute \src "libresoc.v:101054.3-101078.6" + process $proc$libresoc.v:101054$4061 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_out_sel[1:0] $1\dec31_dec_sub20_out_sel[1:0] + attribute \src "libresoc.v:101055.5-101055.29" + switch \initial + attribute \src "libresoc.v:101055.9-101055.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_out_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub20_out_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub20_out_sel $0\dec31_dec_sub20_out_sel[1:0] + end + attribute \src "libresoc.v:99945.7-99945.20" + process $proc$libresoc.v:99945$4062 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:101084.1-102970.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub21" +attribute \generator "nMigen" +module \dec31_dec_sub21 + attribute \src "libresoc.v:102675.3-102723.6" + wire width 2 $0\dec31_dec_sub21_SV_Etype[1:0] + attribute \src "libresoc.v:102724.3-102772.6" + wire width 2 $0\dec31_dec_sub21_SV_Ptype[1:0] + attribute \src "libresoc.v:102644.3-102674.6" + wire width 8 $0\dec31_dec_sub21_asmcode[7:0] + attribute \src "libresoc.v:102252.3-102300.6" + wire $0\dec31_dec_sub21_br[0:0] + attribute \src "libresoc.v:101468.3-101516.6" + wire width 3 $0\dec31_dec_sub21_cr_in[2:0] + attribute \src "libresoc.v:101517.3-101565.6" + wire width 3 $0\dec31_dec_sub21_cr_out[2:0] + attribute \src "libresoc.v:102056.3-102104.6" + wire width 2 $0\dec31_dec_sub21_cry_in[1:0] + attribute \src "libresoc.v:102203.3-102251.6" + wire $0\dec31_dec_sub21_cry_out[0:0] + attribute \src "libresoc.v:102497.3-102545.6" + wire width 5 $0\dec31_dec_sub21_form[4:0] + attribute \src "libresoc.v:101419.3-101467.6" + wire width 13 $0\dec31_dec_sub21_function_unit[12:0] + attribute \src "libresoc.v:102773.3-102821.6" + wire width 3 $0\dec31_dec_sub21_in1_sel[2:0] + attribute \src "libresoc.v:102822.3-102870.6" + wire width 4 $0\dec31_dec_sub21_in2_sel[3:0] + attribute \src "libresoc.v:102871.3-102919.6" + wire width 2 $0\dec31_dec_sub21_in3_sel[1:0] + attribute \src "libresoc.v:101958.3-102006.6" + wire width 7 $0\dec31_dec_sub21_internal_op[6:0] + attribute \src "libresoc.v:102105.3-102153.6" + wire $0\dec31_dec_sub21_inv_a[0:0] + attribute \src "libresoc.v:102154.3-102202.6" + wire $0\dec31_dec_sub21_inv_out[0:0] + attribute \src "libresoc.v:102399.3-102447.6" + wire $0\dec31_dec_sub21_is_32b[0:0] + attribute \src "libresoc.v:101860.3-101908.6" + wire width 4 $0\dec31_dec_sub21_ldst_len[3:0] + attribute \src "libresoc.v:102546.3-102594.6" + wire $0\dec31_dec_sub21_lk[0:0] + attribute \src "libresoc.v:102920.3-102968.6" + wire width 2 $0\dec31_dec_sub21_out_sel[1:0] + attribute \src "libresoc.v:102007.3-102055.6" + wire width 2 $0\dec31_dec_sub21_rc_sel[1:0] + attribute \src "libresoc.v:102350.3-102398.6" + wire $0\dec31_dec_sub21_rsrv[0:0] + attribute \src "libresoc.v:102595.3-102643.6" + wire $0\dec31_dec_sub21_sgl_pipe[0:0] + attribute \src "libresoc.v:102448.3-102496.6" + wire $0\dec31_dec_sub21_sgn[0:0] + attribute \src "libresoc.v:102301.3-102349.6" + wire $0\dec31_dec_sub21_sgn_ext[0:0] + attribute \src "libresoc.v:101762.3-101810.6" + wire width 3 $0\dec31_dec_sub21_sv_cr_in[2:0] + attribute \src "libresoc.v:101811.3-101859.6" + wire width 3 $0\dec31_dec_sub21_sv_cr_out[2:0] + attribute \src "libresoc.v:101566.3-101614.6" + wire width 3 $0\dec31_dec_sub21_sv_in1[2:0] + attribute \src "libresoc.v:101615.3-101663.6" + wire width 3 $0\dec31_dec_sub21_sv_in2[2:0] + attribute \src "libresoc.v:101664.3-101712.6" + wire width 3 $0\dec31_dec_sub21_sv_in3[2:0] + attribute \src "libresoc.v:101713.3-101761.6" + wire width 3 $0\dec31_dec_sub21_sv_out[2:0] + attribute \src "libresoc.v:101909.3-101957.6" + wire width 2 $0\dec31_dec_sub21_upd[1:0] + attribute \src "libresoc.v:101085.7-101085.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:102675.3-102723.6" + wire width 2 $1\dec31_dec_sub21_SV_Etype[1:0] + attribute \src "libresoc.v:102724.3-102772.6" + wire width 2 $1\dec31_dec_sub21_SV_Ptype[1:0] + attribute \src "libresoc.v:102644.3-102674.6" + wire width 8 $1\dec31_dec_sub21_asmcode[7:0] + attribute \src "libresoc.v:102252.3-102300.6" + wire $1\dec31_dec_sub21_br[0:0] + attribute \src "libresoc.v:101468.3-101516.6" + wire width 3 $1\dec31_dec_sub21_cr_in[2:0] + attribute \src "libresoc.v:101517.3-101565.6" + wire width 3 $1\dec31_dec_sub21_cr_out[2:0] + attribute \src "libresoc.v:102056.3-102104.6" + wire width 2 $1\dec31_dec_sub21_cry_in[1:0] + attribute \src "libresoc.v:102203.3-102251.6" + wire $1\dec31_dec_sub21_cry_out[0:0] + attribute \src "libresoc.v:102497.3-102545.6" + wire width 5 $1\dec31_dec_sub21_form[4:0] + attribute \src "libresoc.v:101419.3-101467.6" + wire width 13 $1\dec31_dec_sub21_function_unit[12:0] + attribute \src "libresoc.v:102773.3-102821.6" + wire width 3 $1\dec31_dec_sub21_in1_sel[2:0] + attribute \src "libresoc.v:102822.3-102870.6" + wire width 4 $1\dec31_dec_sub21_in2_sel[3:0] + attribute \src "libresoc.v:102871.3-102919.6" + wire width 2 $1\dec31_dec_sub21_in3_sel[1:0] + attribute \src "libresoc.v:101958.3-102006.6" + wire width 7 $1\dec31_dec_sub21_internal_op[6:0] + attribute \src "libresoc.v:102105.3-102153.6" + wire $1\dec31_dec_sub21_inv_a[0:0] + attribute \src "libresoc.v:102154.3-102202.6" + wire $1\dec31_dec_sub21_inv_out[0:0] + attribute \src "libresoc.v:102399.3-102447.6" + wire $1\dec31_dec_sub21_is_32b[0:0] + attribute \src "libresoc.v:101860.3-101908.6" + wire width 4 $1\dec31_dec_sub21_ldst_len[3:0] + attribute \src "libresoc.v:102546.3-102594.6" + wire $1\dec31_dec_sub21_lk[0:0] + attribute \src "libresoc.v:102920.3-102968.6" + wire width 2 $1\dec31_dec_sub21_out_sel[1:0] + attribute \src "libresoc.v:102007.3-102055.6" + wire width 2 $1\dec31_dec_sub21_rc_sel[1:0] + attribute \src "libresoc.v:102350.3-102398.6" + wire $1\dec31_dec_sub21_rsrv[0:0] + attribute \src "libresoc.v:102595.3-102643.6" + wire $1\dec31_dec_sub21_sgl_pipe[0:0] + attribute \src "libresoc.v:102448.3-102496.6" + wire $1\dec31_dec_sub21_sgn[0:0] + attribute \src "libresoc.v:102301.3-102349.6" + wire $1\dec31_dec_sub21_sgn_ext[0:0] + attribute \src "libresoc.v:101762.3-101810.6" + wire width 3 $1\dec31_dec_sub21_sv_cr_in[2:0] + attribute \src "libresoc.v:101811.3-101859.6" + wire width 3 $1\dec31_dec_sub21_sv_cr_out[2:0] + attribute \src "libresoc.v:101566.3-101614.6" + wire width 3 $1\dec31_dec_sub21_sv_in1[2:0] + attribute \src "libresoc.v:101615.3-101663.6" + wire width 3 $1\dec31_dec_sub21_sv_in2[2:0] + attribute \src "libresoc.v:101664.3-101712.6" + wire width 3 $1\dec31_dec_sub21_sv_in3[2:0] + attribute \src "libresoc.v:101713.3-101761.6" + wire width 3 $1\dec31_dec_sub21_sv_out[2:0] + attribute \src "libresoc.v:101909.3-101957.6" + wire width 2 $1\dec31_dec_sub21_upd[1:0] + attribute \enum_base_type "SVEtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "EXTRA2" + attribute \enum_value_10 "EXTRA3" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 5 \dec31_dec_sub21_SV_Etype + attribute \enum_base_type "SVPtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "P1" + attribute \enum_value_10 "P2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 6 \dec31_dec_sub21_SV_Ptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 8 output 4 \dec31_dec_sub21_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 26 \dec31_dec_sub21_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 11 \dec31_dec_sub21_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 12 \dec31_dec_sub21_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 22 \dec31_dec_sub21_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 25 \dec31_dec_sub21_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 5 output 3 \dec31_dec_sub21_form + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 13 output 1 \dec31_dec_sub21_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 7 \dec31_dec_sub21_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 8 \dec31_dec_sub21_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 9 \dec31_dec_sub21_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 output 2 \dec31_dec_sub21_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 23 \dec31_dec_sub21_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 24 \dec31_dec_sub21_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 29 \dec31_dec_sub21_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 19 \dec31_dec_sub21_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 31 \dec31_dec_sub21_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 10 \dec31_dec_sub21_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 21 \dec31_dec_sub21_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 28 \dec31_dec_sub21_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 32 \dec31_dec_sub21_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 30 \dec31_dec_sub21_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 27 \dec31_dec_sub21_sgn_ext + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 17 \dec31_dec_sub21_sv_cr_in + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 18 \dec31_dec_sub21_sv_cr_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 13 \dec31_dec_sub21_sv_in1 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 14 \dec31_dec_sub21_sv_in2 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 15 \dec31_dec_sub21_sv_in3 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 16 \dec31_dec_sub21_sv_out + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 20 \dec31_dec_sub21_upd + attribute \src "libresoc.v:101085.7-101085.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + wire width 32 input 33 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + wire width 5 \opcode_switch + attribute \src "libresoc.v:101085.7-101085.20" + process $proc$libresoc.v:101085$4095 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:101419.3-101467.6" + process $proc$libresoc.v:101419$4063 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_function_unit[12:0] $1\dec31_dec_sub21_function_unit[12:0] + attribute \src "libresoc.v:101420.5-101420.29" + switch \initial + attribute \src "libresoc.v:101420.9-101420.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_function_unit[12:0] 13'0000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_function_unit[12:0] 13'0000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_function_unit[12:0] 13'0000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_function_unit[12:0] 13'0000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_function_unit[12:0] 13'0000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_function_unit[12:0] 13'0000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_function_unit[12:0] 13'0000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_function_unit[12:0] 13'0000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_function_unit[12:0] 13'0000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_function_unit[12:0] 13'0000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_function_unit[12:0] 13'0000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_function_unit[12:0] 13'0000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_function_unit[12:0] 13'0000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_function_unit[12:0] 13'0000000000100 + case + assign $1\dec31_dec_sub21_function_unit[12:0] 13'0000000000000 + end + sync always + update \dec31_dec_sub21_function_unit $0\dec31_dec_sub21_function_unit[12:0] + end + attribute \src "libresoc.v:101468.3-101516.6" + process $proc$libresoc.v:101468$4064 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_cr_in[2:0] $1\dec31_dec_sub21_cr_in[2:0] + attribute \src "libresoc.v:101469.5-101469.29" + switch \initial + attribute \src "libresoc.v:101469.9-101469.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub21_cr_in $0\dec31_dec_sub21_cr_in[2:0] + end + attribute \src "libresoc.v:101517.3-101565.6" + process $proc$libresoc.v:101517$4065 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_cr_out[2:0] $1\dec31_dec_sub21_cr_out[2:0] + attribute \src "libresoc.v:101518.5-101518.29" + switch \initial + attribute \src "libresoc.v:101518.9-101518.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + case + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub21_cr_out $0\dec31_dec_sub21_cr_out[2:0] + end + attribute \src "libresoc.v:101566.3-101614.6" + process $proc$libresoc.v:101566$4066 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_sv_in1[2:0] $1\dec31_dec_sub21_sv_in1[2:0] + attribute \src "libresoc.v:101567.5-101567.29" + switch \initial + attribute \src "libresoc.v:101567.9-101567.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_sv_in1[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_sv_in1[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_sv_in1[2:0] 3'010 + case + assign $1\dec31_dec_sub21_sv_in1[2:0] 3'000 + end + sync always + update \dec31_dec_sub21_sv_in1 $0\dec31_dec_sub21_sv_in1[2:0] + end + attribute \src "libresoc.v:101615.3-101663.6" + process $proc$libresoc.v:101615$4067 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_sv_in2[2:0] $1\dec31_dec_sub21_sv_in2[2:0] + attribute \src "libresoc.v:101616.5-101616.29" + switch \initial + attribute \src "libresoc.v:101616.9-101616.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_sv_in2[2:0] 3'011 + case + assign $1\dec31_dec_sub21_sv_in2[2:0] 3'000 + end + sync always + update \dec31_dec_sub21_sv_in2 $0\dec31_dec_sub21_sv_in2[2:0] + end + attribute \src "libresoc.v:101664.3-101712.6" + process $proc$libresoc.v:101664$4068 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_sv_in3[2:0] $1\dec31_dec_sub21_sv_in3[2:0] + attribute \src "libresoc.v:101665.5-101665.29" + switch \initial + attribute \src "libresoc.v:101665.9-101665.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_sv_in3[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_sv_in3[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_sv_in3[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_sv_in3[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_sv_in3[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_sv_in3[2:0] 3'001 + case + assign $1\dec31_dec_sub21_sv_in3[2:0] 3'000 + end + sync always + update \dec31_dec_sub21_sv_in3 $0\dec31_dec_sub21_sv_in3[2:0] + end + attribute \src "libresoc.v:101713.3-101761.6" + process $proc$libresoc.v:101713$4069 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_sv_out[2:0] $1\dec31_dec_sub21_sv_out[2:0] + attribute \src "libresoc.v:101714.5-101714.29" + switch \initial + attribute \src "libresoc.v:101714.9-101714.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_sv_out[2:0] 3'000 + case + assign $1\dec31_dec_sub21_sv_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub21_sv_out $0\dec31_dec_sub21_sv_out[2:0] + end + attribute \src "libresoc.v:101762.3-101810.6" + process $proc$libresoc.v:101762$4070 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_sv_cr_in[2:0] $1\dec31_dec_sub21_sv_cr_in[2:0] + attribute \src "libresoc.v:101763.5-101763.29" + switch \initial + attribute \src "libresoc.v:101763.9-101763.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_sv_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub21_sv_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub21_sv_cr_in $0\dec31_dec_sub21_sv_cr_in[2:0] + end + attribute \src "libresoc.v:101811.3-101859.6" + process $proc$libresoc.v:101811$4071 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_sv_cr_out[2:0] $1\dec31_dec_sub21_sv_cr_out[2:0] + attribute \src "libresoc.v:101812.5-101812.29" + switch \initial + attribute \src "libresoc.v:101812.9-101812.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_sv_cr_out[2:0] 3'000 + case + assign $1\dec31_dec_sub21_sv_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub21_sv_cr_out $0\dec31_dec_sub21_sv_cr_out[2:0] + end + attribute \src "libresoc.v:101860.3-101908.6" + process $proc$libresoc.v:101860$4072 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_ldst_len[3:0] $1\dec31_dec_sub21_ldst_len[3:0] + attribute \src "libresoc.v:101861.5-101861.29" + switch \initial + attribute \src "libresoc.v:101861.9-101861.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0100 + case + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub21_ldst_len $0\dec31_dec_sub21_ldst_len[3:0] + end + attribute \src "libresoc.v:101909.3-101957.6" + process $proc$libresoc.v:101909$4073 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_upd[1:0] $1\dec31_dec_sub21_upd[1:0] + attribute \src "libresoc.v:101910.5-101910.29" + switch \initial + attribute \src "libresoc.v:101910.9-101910.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_upd[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_upd[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_upd[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_upd[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_upd[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_upd[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_upd[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_upd[1:0] 2'10 + case + assign $1\dec31_dec_sub21_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub21_upd $0\dec31_dec_sub21_upd[1:0] + end + attribute \src "libresoc.v:101958.3-102006.6" + process $proc$libresoc.v:101958$4074 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_internal_op[6:0] $1\dec31_dec_sub21_internal_op[6:0] + attribute \src "libresoc.v:101959.5-101959.29" + switch \initial + attribute \src "libresoc.v:101959.9-101959.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100110 + case + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub21_internal_op $0\dec31_dec_sub21_internal_op[6:0] + end + attribute \src "libresoc.v:102007.3-102055.6" + process $proc$libresoc.v:102007$4075 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_rc_sel[1:0] $1\dec31_dec_sub21_rc_sel[1:0] + attribute \src "libresoc.v:102008.5-102008.29" + switch \initial + attribute \src "libresoc.v:102008.9-102008.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub21_rc_sel $0\dec31_dec_sub21_rc_sel[1:0] + end + attribute \src "libresoc.v:102056.3-102104.6" + process $proc$libresoc.v:102056$4076 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_cry_in[1:0] $1\dec31_dec_sub21_cry_in[1:0] + attribute \src "libresoc.v:102057.5-102057.29" + switch \initial + attribute \src "libresoc.v:102057.9-102057.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + case + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub21_cry_in $0\dec31_dec_sub21_cry_in[1:0] + end + attribute \src "libresoc.v:102105.3-102153.6" + process $proc$libresoc.v:102105$4077 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_inv_a[0:0] $1\dec31_dec_sub21_inv_a[0:0] + attribute \src "libresoc.v:102106.5-102106.29" + switch \initial + attribute \src "libresoc.v:102106.9-102106.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + case + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub21_inv_a $0\dec31_dec_sub21_inv_a[0:0] + end + attribute \src "libresoc.v:102154.3-102202.6" + process $proc$libresoc.v:102154$4078 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_inv_out[0:0] $1\dec31_dec_sub21_inv_out[0:0] + attribute \src "libresoc.v:102155.5-102155.29" + switch \initial + attribute \src "libresoc.v:102155.9-102155.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub21_inv_out $0\dec31_dec_sub21_inv_out[0:0] + end + attribute \src "libresoc.v:102203.3-102251.6" + process $proc$libresoc.v:102203$4079 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_cry_out[0:0] $1\dec31_dec_sub21_cry_out[0:0] + attribute \src "libresoc.v:102204.5-102204.29" + switch \initial + attribute \src "libresoc.v:102204.9-102204.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + case + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub21_cry_out $0\dec31_dec_sub21_cry_out[0:0] + end + attribute \src "libresoc.v:102252.3-102300.6" + process $proc$libresoc.v:102252$4080 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_br[0:0] $1\dec31_dec_sub21_br[0:0] + attribute \src "libresoc.v:102253.5-102253.29" + switch \initial + attribute \src "libresoc.v:102253.9-102253.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_br[0:0] 1'0 + case + assign $1\dec31_dec_sub21_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub21_br $0\dec31_dec_sub21_br[0:0] + end + attribute \src "libresoc.v:102301.3-102349.6" + process $proc$libresoc.v:102301$4081 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_sgn_ext[0:0] $1\dec31_dec_sub21_sgn_ext[0:0] + attribute \src "libresoc.v:102302.5-102302.29" + switch \initial + attribute \src "libresoc.v:102302.9-102302.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub21_sgn_ext $0\dec31_dec_sub21_sgn_ext[0:0] + end + attribute \src "libresoc.v:102350.3-102398.6" + process $proc$libresoc.v:102350$4082 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_rsrv[0:0] $1\dec31_dec_sub21_rsrv[0:0] + attribute \src "libresoc.v:102351.5-102351.29" + switch \initial + attribute \src "libresoc.v:102351.9-102351.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub21_rsrv $0\dec31_dec_sub21_rsrv[0:0] + end + attribute \src "libresoc.v:102399.3-102447.6" + process $proc$libresoc.v:102399$4083 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_is_32b[0:0] $1\dec31_dec_sub21_is_32b[0:0] + attribute \src "libresoc.v:102400.5-102400.29" + switch \initial + attribute \src "libresoc.v:102400.9-102400.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + case + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub21_is_32b $0\dec31_dec_sub21_is_32b[0:0] + end + attribute \src "libresoc.v:102448.3-102496.6" + process $proc$libresoc.v:102448$4084 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_sgn[0:0] $1\dec31_dec_sub21_sgn[0:0] + attribute \src "libresoc.v:102449.5-102449.29" + switch \initial + attribute \src "libresoc.v:102449.9-102449.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + case + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub21_sgn $0\dec31_dec_sub21_sgn[0:0] + end + attribute \src "libresoc.v:102497.3-102545.6" + process $proc$libresoc.v:102497$4085 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_form[4:0] $1\dec31_dec_sub21_form[4:0] + attribute \src "libresoc.v:102498.5-102498.29" + switch \initial + attribute \src "libresoc.v:102498.9-102498.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_form[4:0] 5'01000 + case + assign $1\dec31_dec_sub21_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub21_form $0\dec31_dec_sub21_form[4:0] + end + attribute \src "libresoc.v:102546.3-102594.6" + process $proc$libresoc.v:102546$4086 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_lk[0:0] $1\dec31_dec_sub21_lk[0:0] + attribute \src "libresoc.v:102547.5-102547.29" + switch \initial + attribute \src "libresoc.v:102547.9-102547.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub21_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub21_lk $0\dec31_dec_sub21_lk[0:0] + end + attribute \src "libresoc.v:102595.3-102643.6" + process $proc$libresoc.v:102595$4087 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_sgl_pipe[0:0] $1\dec31_dec_sub21_sgl_pipe[0:0] + attribute \src "libresoc.v:102596.5-102596.29" + switch \initial + attribute \src "libresoc.v:102596.9-102596.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 + case + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub21_sgl_pipe $0\dec31_dec_sub21_sgl_pipe[0:0] + end + attribute \src "libresoc.v:102644.3-102674.6" + process $proc$libresoc.v:102644$4088 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_asmcode[7:0] $1\dec31_dec_sub21_asmcode[7:0] + attribute \src "libresoc.v:102645.5-102645.29" + switch \initial + attribute \src "libresoc.v:102645.9-102645.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_asmcode[7:0] 8'01010110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_asmcode[7:0] 8'01010111 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_asmcode[7:0] 8'01100100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_asmcode[7:0] 8'01100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_asmcode[7:0] 8'01101000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_asmcode[7:0] 8'10101000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_asmcode[7:0] 8'10110001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_asmcode[7:0] 8'10110010 + case + assign $1\dec31_dec_sub21_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub21_asmcode $0\dec31_dec_sub21_asmcode[7:0] + end + attribute \src "libresoc.v:102675.3-102723.6" + process $proc$libresoc.v:102675$4089 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_SV_Etype[1:0] $1\dec31_dec_sub21_SV_Etype[1:0] + attribute \src "libresoc.v:102676.5-102676.29" + switch \initial + attribute \src "libresoc.v:102676.9-102676.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_SV_Etype[1:0] 2'01 + case + assign $1\dec31_dec_sub21_SV_Etype[1:0] 2'00 + end + sync always + update \dec31_dec_sub21_SV_Etype $0\dec31_dec_sub21_SV_Etype[1:0] + end + attribute \src "libresoc.v:102724.3-102772.6" + process $proc$libresoc.v:102724$4090 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_SV_Ptype[1:0] $1\dec31_dec_sub21_SV_Ptype[1:0] + attribute \src "libresoc.v:102725.5-102725.29" + switch \initial + attribute \src "libresoc.v:102725.9-102725.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_SV_Ptype[1:0] 2'10 + case + assign $1\dec31_dec_sub21_SV_Ptype[1:0] 2'00 + end + sync always + update \dec31_dec_sub21_SV_Ptype $0\dec31_dec_sub21_SV_Ptype[1:0] + end + attribute \src "libresoc.v:102773.3-102821.6" + process $proc$libresoc.v:102773$4091 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_in1_sel[2:0] $1\dec31_dec_sub21_in1_sel[2:0] + attribute \src "libresoc.v:102774.5-102774.29" + switch \initial + attribute \src "libresoc.v:102774.9-102774.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + case + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub21_in1_sel $0\dec31_dec_sub21_in1_sel[2:0] + end + attribute \src "libresoc.v:102822.3-102870.6" + process $proc$libresoc.v:102822$4092 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_in2_sel[3:0] $1\dec31_dec_sub21_in2_sel[3:0] + attribute \src "libresoc.v:102823.5-102823.29" + switch \initial + attribute \src "libresoc.v:102823.9-102823.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + case + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub21_in2_sel $0\dec31_dec_sub21_in2_sel[3:0] + end + attribute \src "libresoc.v:102871.3-102919.6" + process $proc$libresoc.v:102871$4093 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_in3_sel[1:0] $1\dec31_dec_sub21_in3_sel[1:0] + attribute \src "libresoc.v:102872.5-102872.29" + switch \initial + attribute \src "libresoc.v:102872.9-102872.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'01 + case + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub21_in3_sel $0\dec31_dec_sub21_in3_sel[1:0] + end + attribute \src "libresoc.v:102920.3-102968.6" + process $proc$libresoc.v:102920$4094 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_out_sel[1:0] $1\dec31_dec_sub21_out_sel[1:0] + attribute \src "libresoc.v:102921.5-102921.29" + switch \initial + attribute \src "libresoc.v:102921.9-102921.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_out_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub21_out_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub21_out_sel $0\dec31_dec_sub21_out_sel[1:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:102974.1-105070.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub22" +attribute \generator "nMigen" +module \dec31_dec_sub22 + attribute \src "libresoc.v:104739.3-104793.6" + wire width 2 $0\dec31_dec_sub22_SV_Etype[1:0] + attribute \src "libresoc.v:104794.3-104848.6" + wire width 2 $0\dec31_dec_sub22_SV_Ptype[1:0] + attribute \src "libresoc.v:104079.3-104133.6" + wire width 8 $0\dec31_dec_sub22_asmcode[7:0] + attribute \src "libresoc.v:104299.3-104353.6" + wire $0\dec31_dec_sub22_br[0:0] + attribute \src "libresoc.v:103364.3-103418.6" + wire width 3 $0\dec31_dec_sub22_cr_in[2:0] + attribute \src "libresoc.v:103419.3-103473.6" + wire width 3 $0\dec31_dec_sub22_cr_out[2:0] + attribute \src "libresoc.v:104024.3-104078.6" + wire width 2 $0\dec31_dec_sub22_cry_in[1:0] + attribute \src "libresoc.v:104244.3-104298.6" + wire $0\dec31_dec_sub22_cry_out[0:0] + attribute \src "libresoc.v:104519.3-104573.6" + wire width 5 $0\dec31_dec_sub22_form[4:0] + attribute \src "libresoc.v:103309.3-103363.6" + wire width 13 $0\dec31_dec_sub22_function_unit[12:0] + attribute \src "libresoc.v:104849.3-104903.6" + wire width 3 $0\dec31_dec_sub22_in1_sel[2:0] + attribute \src "libresoc.v:104904.3-104958.6" + wire width 4 $0\dec31_dec_sub22_in2_sel[3:0] + attribute \src "libresoc.v:104959.3-105013.6" + wire width 2 $0\dec31_dec_sub22_in3_sel[1:0] + attribute \src "libresoc.v:103914.3-103968.6" + wire width 7 $0\dec31_dec_sub22_internal_op[6:0] + attribute \src "libresoc.v:104134.3-104188.6" + wire $0\dec31_dec_sub22_inv_a[0:0] + attribute \src "libresoc.v:104189.3-104243.6" + wire $0\dec31_dec_sub22_inv_out[0:0] + attribute \src "libresoc.v:104464.3-104518.6" + wire $0\dec31_dec_sub22_is_32b[0:0] + attribute \src "libresoc.v:103804.3-103858.6" + wire width 4 $0\dec31_dec_sub22_ldst_len[3:0] + attribute \src "libresoc.v:104629.3-104683.6" + wire $0\dec31_dec_sub22_lk[0:0] + attribute \src "libresoc.v:105014.3-105068.6" + wire width 2 $0\dec31_dec_sub22_out_sel[1:0] + attribute \src "libresoc.v:103969.3-104023.6" + wire width 2 $0\dec31_dec_sub22_rc_sel[1:0] + attribute \src "libresoc.v:104409.3-104463.6" + wire $0\dec31_dec_sub22_rsrv[0:0] + attribute \src "libresoc.v:104684.3-104738.6" + wire $0\dec31_dec_sub22_sgl_pipe[0:0] + attribute \src "libresoc.v:104574.3-104628.6" + wire $0\dec31_dec_sub22_sgn[0:0] + attribute \src "libresoc.v:104354.3-104408.6" + wire $0\dec31_dec_sub22_sgn_ext[0:0] + attribute \src "libresoc.v:103694.3-103748.6" + wire width 3 $0\dec31_dec_sub22_sv_cr_in[2:0] + attribute \src "libresoc.v:103749.3-103803.6" + wire width 3 $0\dec31_dec_sub22_sv_cr_out[2:0] + attribute \src "libresoc.v:103474.3-103528.6" + wire width 3 $0\dec31_dec_sub22_sv_in1[2:0] + attribute \src "libresoc.v:103529.3-103583.6" + wire width 3 $0\dec31_dec_sub22_sv_in2[2:0] + attribute \src "libresoc.v:103584.3-103638.6" + wire width 3 $0\dec31_dec_sub22_sv_in3[2:0] + attribute \src "libresoc.v:103639.3-103693.6" + wire width 3 $0\dec31_dec_sub22_sv_out[2:0] + attribute \src "libresoc.v:103859.3-103913.6" + wire width 2 $0\dec31_dec_sub22_upd[1:0] + attribute \src "libresoc.v:102975.7-102975.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:104739.3-104793.6" + wire width 2 $1\dec31_dec_sub22_SV_Etype[1:0] + attribute \src "libresoc.v:104794.3-104848.6" + wire width 2 $1\dec31_dec_sub22_SV_Ptype[1:0] + attribute \src "libresoc.v:104079.3-104133.6" + wire width 8 $1\dec31_dec_sub22_asmcode[7:0] + attribute \src "libresoc.v:104299.3-104353.6" + wire $1\dec31_dec_sub22_br[0:0] + attribute \src "libresoc.v:103364.3-103418.6" + wire width 3 $1\dec31_dec_sub22_cr_in[2:0] + attribute \src "libresoc.v:103419.3-103473.6" + wire width 3 $1\dec31_dec_sub22_cr_out[2:0] + attribute \src "libresoc.v:104024.3-104078.6" + wire width 2 $1\dec31_dec_sub22_cry_in[1:0] + attribute \src "libresoc.v:104244.3-104298.6" + wire $1\dec31_dec_sub22_cry_out[0:0] + attribute \src "libresoc.v:104519.3-104573.6" + wire width 5 $1\dec31_dec_sub22_form[4:0] + attribute \src "libresoc.v:103309.3-103363.6" + wire width 13 $1\dec31_dec_sub22_function_unit[12:0] + attribute \src "libresoc.v:104849.3-104903.6" + wire width 3 $1\dec31_dec_sub22_in1_sel[2:0] + attribute \src "libresoc.v:104904.3-104958.6" + wire width 4 $1\dec31_dec_sub22_in2_sel[3:0] + attribute \src "libresoc.v:104959.3-105013.6" + wire width 2 $1\dec31_dec_sub22_in3_sel[1:0] + attribute \src "libresoc.v:103914.3-103968.6" + wire width 7 $1\dec31_dec_sub22_internal_op[6:0] + attribute \src "libresoc.v:104134.3-104188.6" + wire $1\dec31_dec_sub22_inv_a[0:0] + attribute \src "libresoc.v:104189.3-104243.6" + wire $1\dec31_dec_sub22_inv_out[0:0] + attribute \src "libresoc.v:104464.3-104518.6" + wire $1\dec31_dec_sub22_is_32b[0:0] + attribute \src "libresoc.v:103804.3-103858.6" + wire width 4 $1\dec31_dec_sub22_ldst_len[3:0] + attribute \src "libresoc.v:104629.3-104683.6" + wire $1\dec31_dec_sub22_lk[0:0] + attribute \src "libresoc.v:105014.3-105068.6" + wire width 2 $1\dec31_dec_sub22_out_sel[1:0] + attribute \src "libresoc.v:103969.3-104023.6" + wire width 2 $1\dec31_dec_sub22_rc_sel[1:0] + attribute \src "libresoc.v:104409.3-104463.6" + wire $1\dec31_dec_sub22_rsrv[0:0] + attribute \src "libresoc.v:104684.3-104738.6" + wire $1\dec31_dec_sub22_sgl_pipe[0:0] + attribute \src "libresoc.v:104574.3-104628.6" + wire $1\dec31_dec_sub22_sgn[0:0] + attribute \src "libresoc.v:104354.3-104408.6" + wire $1\dec31_dec_sub22_sgn_ext[0:0] + attribute \src "libresoc.v:103694.3-103748.6" + wire width 3 $1\dec31_dec_sub22_sv_cr_in[2:0] + attribute \src "libresoc.v:103749.3-103803.6" + wire width 3 $1\dec31_dec_sub22_sv_cr_out[2:0] + attribute \src "libresoc.v:103474.3-103528.6" + wire width 3 $1\dec31_dec_sub22_sv_in1[2:0] + attribute \src "libresoc.v:103529.3-103583.6" + wire width 3 $1\dec31_dec_sub22_sv_in2[2:0] + attribute \src "libresoc.v:103584.3-103638.6" + wire width 3 $1\dec31_dec_sub22_sv_in3[2:0] + attribute \src "libresoc.v:103639.3-103693.6" + wire width 3 $1\dec31_dec_sub22_sv_out[2:0] + attribute \src "libresoc.v:103859.3-103913.6" + wire width 2 $1\dec31_dec_sub22_upd[1:0] + attribute \enum_base_type "SVEtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "EXTRA2" + attribute \enum_value_10 "EXTRA3" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 5 \dec31_dec_sub22_SV_Etype + attribute \enum_base_type "SVPtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "P1" + attribute \enum_value_10 "P2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 6 \dec31_dec_sub22_SV_Ptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 8 output 4 \dec31_dec_sub22_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 26 \dec31_dec_sub22_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 11 \dec31_dec_sub22_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 12 \dec31_dec_sub22_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 22 \dec31_dec_sub22_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 25 \dec31_dec_sub22_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 5 output 3 \dec31_dec_sub22_form + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 13 output 1 \dec31_dec_sub22_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 7 \dec31_dec_sub22_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 8 \dec31_dec_sub22_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 9 \dec31_dec_sub22_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 output 2 \dec31_dec_sub22_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 23 \dec31_dec_sub22_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 24 \dec31_dec_sub22_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 29 \dec31_dec_sub22_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 19 \dec31_dec_sub22_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 31 \dec31_dec_sub22_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 10 \dec31_dec_sub22_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 21 \dec31_dec_sub22_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 28 \dec31_dec_sub22_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 32 \dec31_dec_sub22_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 30 \dec31_dec_sub22_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 27 \dec31_dec_sub22_sgn_ext + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 17 \dec31_dec_sub22_sv_cr_in + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 18 \dec31_dec_sub22_sv_cr_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 13 \dec31_dec_sub22_sv_in1 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 14 \dec31_dec_sub22_sv_in2 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 15 \dec31_dec_sub22_sv_in3 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 16 \dec31_dec_sub22_sv_out + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 20 \dec31_dec_sub22_upd + attribute \src "libresoc.v:102975.7-102975.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + wire width 32 input 33 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + wire width 5 \opcode_switch + attribute \src "libresoc.v:102975.7-102975.20" + process $proc$libresoc.v:102975$4128 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:103309.3-103363.6" + process $proc$libresoc.v:103309$4096 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_function_unit[12:0] $1\dec31_dec_sub22_function_unit[12:0] + attribute \src "libresoc.v:103310.5-103310.29" + switch \initial + attribute \src "libresoc.v:103310.9-103310.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_function_unit[12:0] 13'0000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_function_unit[12:0] 13'0000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_function_unit[12:0] 13'0000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_function_unit[12:0] 13'0000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_function_unit[12:0] 13'0100000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_function_unit[12:0] 13'0000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_function_unit[12:0] 13'0000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_function_unit[12:0] 13'0000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_function_unit[12:0] 13'0000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_function_unit[12:0] 13'0000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_function_unit[12:0] 13'0000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_function_unit[12:0] 13'0000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_function_unit[12:0] 13'0000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_function_unit[12:0] 13'0000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_function_unit[12:0] 13'0000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_function_unit[12:0] 13'0000000000010 + case + assign $1\dec31_dec_sub22_function_unit[12:0] 13'0000000000000 + end + sync always + update \dec31_dec_sub22_function_unit $0\dec31_dec_sub22_function_unit[12:0] + end + attribute \src "libresoc.v:103364.3-103418.6" + process $proc$libresoc.v:103364$4097 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_cr_in[2:0] $1\dec31_dec_sub22_cr_in[2:0] + attribute \src "libresoc.v:103365.5-103365.29" + switch \initial + attribute \src "libresoc.v:103365.9-103365.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub22_cr_in $0\dec31_dec_sub22_cr_in[2:0] + end + attribute \src "libresoc.v:103419.3-103473.6" + process $proc$libresoc.v:103419$4098 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_cr_out[2:0] $1\dec31_dec_sub22_cr_out[2:0] + attribute \src "libresoc.v:103420.5-103420.29" + switch \initial + attribute \src "libresoc.v:103420.9-103420.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 + case + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub22_cr_out $0\dec31_dec_sub22_cr_out[2:0] + end + attribute \src "libresoc.v:103474.3-103528.6" + process $proc$libresoc.v:103474$4099 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_sv_in1[2:0] $1\dec31_dec_sub22_sv_in1[2:0] + attribute \src "libresoc.v:103475.5-103475.29" + switch \initial + attribute \src "libresoc.v:103475.9-103475.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_sv_in1[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_sv_in1[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_sv_in1[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_sv_in1[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_sv_in1[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_sv_in1[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_sv_in1[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_sv_in1[2:0] 3'000 + case + assign $1\dec31_dec_sub22_sv_in1[2:0] 3'000 + end + sync always + update \dec31_dec_sub22_sv_in1 $0\dec31_dec_sub22_sv_in1[2:0] + end + attribute \src "libresoc.v:103529.3-103583.6" + process $proc$libresoc.v:103529$4100 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_sv_in2[2:0] $1\dec31_dec_sub22_sv_in2[2:0] + attribute \src "libresoc.v:103530.5-103530.29" + switch \initial + attribute \src "libresoc.v:103530.9-103530.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_sv_in2[2:0] 3'000 + case + assign $1\dec31_dec_sub22_sv_in2[2:0] 3'000 + end + sync always + update \dec31_dec_sub22_sv_in2 $0\dec31_dec_sub22_sv_in2[2:0] + end + attribute \src "libresoc.v:103584.3-103638.6" + process $proc$libresoc.v:103584$4101 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_sv_in3[2:0] $1\dec31_dec_sub22_sv_in3[2:0] + attribute \src "libresoc.v:103585.5-103585.29" + switch \initial + attribute \src "libresoc.v:103585.9-103585.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_sv_in3[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_sv_in3[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_sv_in3[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_sv_in3[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_sv_in3[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_sv_in3[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_sv_in3[2:0] 3'000 + case + assign $1\dec31_dec_sub22_sv_in3[2:0] 3'000 + end + sync always + update \dec31_dec_sub22_sv_in3 $0\dec31_dec_sub22_sv_in3[2:0] + end + attribute \src "libresoc.v:103639.3-103693.6" + process $proc$libresoc.v:103639$4102 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_sv_out[2:0] $1\dec31_dec_sub22_sv_out[2:0] + attribute \src "libresoc.v:103640.5-103640.29" + switch \initial + attribute \src "libresoc.v:103640.9-103640.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_sv_out[2:0] 3'000 + case + assign $1\dec31_dec_sub22_sv_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub22_sv_out $0\dec31_dec_sub22_sv_out[2:0] + end + attribute \src "libresoc.v:103694.3-103748.6" + process $proc$libresoc.v:103694$4103 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_sv_cr_in[2:0] $1\dec31_dec_sub22_sv_cr_in[2:0] + attribute \src "libresoc.v:103695.5-103695.29" + switch \initial + attribute \src "libresoc.v:103695.9-103695.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_sv_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub22_sv_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub22_sv_cr_in $0\dec31_dec_sub22_sv_cr_in[2:0] + end + attribute \src "libresoc.v:103749.3-103803.6" + process $proc$libresoc.v:103749$4104 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_sv_cr_out[2:0] $1\dec31_dec_sub22_sv_cr_out[2:0] + attribute \src "libresoc.v:103750.5-103750.29" + switch \initial + attribute \src "libresoc.v:103750.9-103750.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_sv_cr_out[2:0] 3'000 + case + assign $1\dec31_dec_sub22_sv_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub22_sv_cr_out $0\dec31_dec_sub22_sv_cr_out[2:0] + end + attribute \src "libresoc.v:103804.3-103858.6" + process $proc$libresoc.v:103804$4105 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_ldst_len[3:0] $1\dec31_dec_sub22_ldst_len[3:0] + attribute \src "libresoc.v:103805.5-103805.29" + switch \initial + attribute \src "libresoc.v:103805.9-103805.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000 + case + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub22_ldst_len $0\dec31_dec_sub22_ldst_len[3:0] + end + attribute \src "libresoc.v:103859.3-103913.6" + process $proc$libresoc.v:103859$4106 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_upd[1:0] $1\dec31_dec_sub22_upd[1:0] + attribute \src "libresoc.v:103860.5-103860.29" + switch \initial + attribute \src "libresoc.v:103860.9-103860.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + case + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub22_upd $0\dec31_dec_sub22_upd[1:0] + end + attribute \src "libresoc.v:103914.3-103968.6" + process $proc$libresoc.v:103914$4107 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_internal_op[6:0] $1\dec31_dec_sub22_internal_op[6:0] + attribute \src "libresoc.v:103915.5-103915.29" + switch \initial + attribute \src "libresoc.v:103915.9-103915.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0000001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0000001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0000001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0000001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0011100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0000001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0000001 + case + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub22_internal_op $0\dec31_dec_sub22_internal_op[6:0] + end + attribute \src "libresoc.v:103969.3-104023.6" + process $proc$libresoc.v:103969$4108 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_rc_sel[1:0] $1\dec31_dec_sub22_rc_sel[1:0] + attribute \src "libresoc.v:103970.5-103970.29" + switch \initial + attribute \src "libresoc.v:103970.9-103970.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub22_rc_sel $0\dec31_dec_sub22_rc_sel[1:0] + end + attribute \src "libresoc.v:104024.3-104078.6" + process $proc$libresoc.v:104024$4109 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_cry_in[1:0] $1\dec31_dec_sub22_cry_in[1:0] + attribute \src "libresoc.v:104025.5-104025.29" + switch \initial + attribute \src "libresoc.v:104025.9-104025.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + case + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub22_cry_in $0\dec31_dec_sub22_cry_in[1:0] + end + attribute \src "libresoc.v:104079.3-104133.6" + process $proc$libresoc.v:104079$4110 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_asmcode[7:0] $1\dec31_dec_sub22_asmcode[7:0] + attribute \src "libresoc.v:104080.5-104080.29" + switch \initial + attribute \src "libresoc.v:104080.9-104080.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_asmcode[7:0] 8'00101110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_asmcode[7:0] 8'00101111 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_asmcode[7:0] 8'00110000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_asmcode[7:0] 8'00110001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_asmcode[7:0] 8'00110010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_asmcode[7:0] 8'01001001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_asmcode[7:0] 8'01001010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_asmcode[7:0] 8'01011101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_asmcode[7:0] 8'01100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_asmcode[7:0] 8'10101001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_asmcode[7:0] 8'10101111 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_asmcode[7:0] 8'10110100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_asmcode[7:0] 8'10110101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_asmcode[7:0] 8'10111010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_asmcode[7:0] 8'10111011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_asmcode[7:0] 8'11001010 + case + assign $1\dec31_dec_sub22_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub22_asmcode $0\dec31_dec_sub22_asmcode[7:0] + end + attribute \src "libresoc.v:104134.3-104188.6" + process $proc$libresoc.v:104134$4111 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_inv_a[0:0] $1\dec31_dec_sub22_inv_a[0:0] + attribute \src "libresoc.v:104135.5-104135.29" + switch \initial + attribute \src "libresoc.v:104135.9-104135.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + case + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub22_inv_a $0\dec31_dec_sub22_inv_a[0:0] + end + attribute \src "libresoc.v:104189.3-104243.6" + process $proc$libresoc.v:104189$4112 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_inv_out[0:0] $1\dec31_dec_sub22_inv_out[0:0] + attribute \src "libresoc.v:104190.5-104190.29" + switch \initial + attribute \src "libresoc.v:104190.9-104190.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub22_inv_out $0\dec31_dec_sub22_inv_out[0:0] + end + attribute \src "libresoc.v:104244.3-104298.6" + process $proc$libresoc.v:104244$4113 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_cry_out[0:0] $1\dec31_dec_sub22_cry_out[0:0] + attribute \src "libresoc.v:104245.5-104245.29" + switch \initial + attribute \src "libresoc.v:104245.9-104245.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + case + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub22_cry_out $0\dec31_dec_sub22_cry_out[0:0] + end + attribute \src "libresoc.v:104299.3-104353.6" + process $proc$libresoc.v:104299$4114 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_br[0:0] $1\dec31_dec_sub22_br[0:0] + attribute \src "libresoc.v:104300.5-104300.29" + switch \initial + attribute \src "libresoc.v:104300.9-104300.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_br[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_br[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_br[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_br[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_br[0:0] 1'0 + case + assign $1\dec31_dec_sub22_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub22_br $0\dec31_dec_sub22_br[0:0] + end + attribute \src "libresoc.v:104354.3-104408.6" + process $proc$libresoc.v:104354$4115 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_sgn_ext[0:0] $1\dec31_dec_sub22_sgn_ext[0:0] + attribute \src "libresoc.v:104355.5-104355.29" + switch \initial + attribute \src "libresoc.v:104355.9-104355.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub22_sgn_ext $0\dec31_dec_sub22_sgn_ext[0:0] + end + attribute \src "libresoc.v:104409.3-104463.6" + process $proc$libresoc.v:104409$4116 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_rsrv[0:0] $1\dec31_dec_sub22_rsrv[0:0] + attribute \src "libresoc.v:104410.5-104410.29" + switch \initial + attribute \src "libresoc.v:104410.9-104410.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_rsrv[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_rsrv[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_rsrv[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_rsrv[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub22_rsrv $0\dec31_dec_sub22_rsrv[0:0] + end + attribute \src "libresoc.v:104464.3-104518.6" + process $proc$libresoc.v:104464$4117 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_is_32b[0:0] $1\dec31_dec_sub22_is_32b[0:0] + attribute \src "libresoc.v:104465.5-104465.29" + switch \initial + attribute \src "libresoc.v:104465.9-104465.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + case + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub22_is_32b $0\dec31_dec_sub22_is_32b[0:0] + end + attribute \src "libresoc.v:104519.3-104573.6" + process $proc$libresoc.v:104519$4118 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_form[4:0] $1\dec31_dec_sub22_form[4:0] + attribute \src "libresoc.v:104520.5-104520.29" + switch \initial + attribute \src "libresoc.v:104520.9-104520.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_form[4:0] 5'01000 + case + assign $1\dec31_dec_sub22_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub22_form $0\dec31_dec_sub22_form[4:0] + end + attribute \src "libresoc.v:104574.3-104628.6" + process $proc$libresoc.v:104574$4119 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_sgn[0:0] $1\dec31_dec_sub22_sgn[0:0] + attribute \src "libresoc.v:104575.5-104575.29" + switch \initial + attribute \src "libresoc.v:104575.9-104575.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + case + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub22_sgn $0\dec31_dec_sub22_sgn[0:0] + end + attribute \src "libresoc.v:104629.3-104683.6" + process $proc$libresoc.v:104629$4120 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_lk[0:0] $1\dec31_dec_sub22_lk[0:0] + attribute \src "libresoc.v:104630.5-104630.29" + switch \initial + attribute \src "libresoc.v:104630.9-104630.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub22_lk $0\dec31_dec_sub22_lk[0:0] + end + attribute \src "libresoc.v:104684.3-104738.6" + process $proc$libresoc.v:104684$4121 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_sgl_pipe[0:0] $1\dec31_dec_sub22_sgl_pipe[0:0] + attribute \src "libresoc.v:104685.5-104685.29" + switch \initial + attribute \src "libresoc.v:104685.9-104685.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 + case + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub22_sgl_pipe $0\dec31_dec_sub22_sgl_pipe[0:0] + end + attribute \src "libresoc.v:104739.3-104793.6" + process $proc$libresoc.v:104739$4122 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_SV_Etype[1:0] $1\dec31_dec_sub22_SV_Etype[1:0] + attribute \src "libresoc.v:104740.5-104740.29" + switch \initial + attribute \src "libresoc.v:104740.9-104740.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_SV_Etype[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_SV_Etype[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_SV_Etype[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_SV_Etype[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_SV_Etype[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_SV_Etype[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_SV_Etype[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_SV_Etype[1:0] 2'00 + case + assign $1\dec31_dec_sub22_SV_Etype[1:0] 2'00 + end + sync always + update \dec31_dec_sub22_SV_Etype $0\dec31_dec_sub22_SV_Etype[1:0] + end + attribute \src "libresoc.v:104794.3-104848.6" + process $proc$libresoc.v:104794$4123 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_SV_Ptype[1:0] $1\dec31_dec_sub22_SV_Ptype[1:0] + attribute \src "libresoc.v:104795.5-104795.29" + switch \initial + attribute \src "libresoc.v:104795.9-104795.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_SV_Ptype[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_SV_Ptype[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_SV_Ptype[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_SV_Ptype[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_SV_Ptype[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_SV_Ptype[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_SV_Ptype[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_SV_Ptype[1:0] 2'00 + case + assign $1\dec31_dec_sub22_SV_Ptype[1:0] 2'00 + end + sync always + update \dec31_dec_sub22_SV_Ptype $0\dec31_dec_sub22_SV_Ptype[1:0] + end + attribute \src "libresoc.v:104849.3-104903.6" + process $proc$libresoc.v:104849$4124 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_in1_sel[2:0] $1\dec31_dec_sub22_in1_sel[2:0] + attribute \src "libresoc.v:104850.5-104850.29" + switch \initial + attribute \src "libresoc.v:104850.9-104850.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'000 + case + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub22_in1_sel $0\dec31_dec_sub22_in1_sel[2:0] + end + attribute \src "libresoc.v:104904.3-104958.6" + process $proc$libresoc.v:104904$4125 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_in2_sel[3:0] $1\dec31_dec_sub22_in2_sel[3:0] + attribute \src "libresoc.v:104905.5-104905.29" + switch \initial + attribute \src "libresoc.v:104905.9-104905.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0000 + case + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub22_in2_sel $0\dec31_dec_sub22_in2_sel[3:0] + end + attribute \src "libresoc.v:104959.3-105013.6" + process $proc$libresoc.v:104959$4126 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_in3_sel[1:0] $1\dec31_dec_sub22_in3_sel[1:0] + attribute \src "libresoc.v:104960.5-104960.29" + switch \initial + attribute \src "libresoc.v:104960.9-104960.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub22_in3_sel $0\dec31_dec_sub22_in3_sel[1:0] + end + attribute \src "libresoc.v:105014.3-105068.6" + process $proc$libresoc.v:105014$4127 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_out_sel[1:0] $1\dec31_dec_sub22_out_sel[1:0] + attribute \src "libresoc.v:105015.5-105015.29" + switch \initial + attribute \src "libresoc.v:105015.9-105015.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub22_out_sel $0\dec31_dec_sub22_out_sel[1:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:105074.1-106978.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub23" +attribute \generator "nMigen" +module \dec31_dec_sub23 + attribute \src "libresoc.v:106683.3-106731.6" + wire width 2 $0\dec31_dec_sub23_SV_Etype[1:0] + attribute \src "libresoc.v:106732.3-106780.6" + wire width 2 $0\dec31_dec_sub23_SV_Ptype[1:0] + attribute \src "libresoc.v:106095.3-106143.6" + wire width 8 $0\dec31_dec_sub23_asmcode[7:0] + attribute \src "libresoc.v:106291.3-106339.6" + wire $0\dec31_dec_sub23_br[0:0] + attribute \src "libresoc.v:105458.3-105506.6" + wire width 3 $0\dec31_dec_sub23_cr_in[2:0] + attribute \src "libresoc.v:105507.3-105555.6" + wire width 3 $0\dec31_dec_sub23_cr_out[2:0] + attribute \src "libresoc.v:106046.3-106094.6" + wire width 2 $0\dec31_dec_sub23_cry_in[1:0] + attribute \src "libresoc.v:106242.3-106290.6" + wire $0\dec31_dec_sub23_cry_out[0:0] + attribute \src "libresoc.v:106487.3-106535.6" + wire width 5 $0\dec31_dec_sub23_form[4:0] + attribute \src "libresoc.v:105409.3-105457.6" + wire width 13 $0\dec31_dec_sub23_function_unit[12:0] + attribute \src "libresoc.v:106781.3-106829.6" + wire width 3 $0\dec31_dec_sub23_in1_sel[2:0] + attribute \src "libresoc.v:106830.3-106878.6" + wire width 4 $0\dec31_dec_sub23_in2_sel[3:0] + attribute \src "libresoc.v:106879.3-106927.6" + wire width 2 $0\dec31_dec_sub23_in3_sel[1:0] + attribute \src "libresoc.v:105948.3-105996.6" + wire width 7 $0\dec31_dec_sub23_internal_op[6:0] + attribute \src "libresoc.v:106144.3-106192.6" + wire $0\dec31_dec_sub23_inv_a[0:0] + attribute \src "libresoc.v:106193.3-106241.6" + wire $0\dec31_dec_sub23_inv_out[0:0] + attribute \src "libresoc.v:106438.3-106486.6" + wire $0\dec31_dec_sub23_is_32b[0:0] + attribute \src "libresoc.v:105850.3-105898.6" + wire width 4 $0\dec31_dec_sub23_ldst_len[3:0] + attribute \src "libresoc.v:106585.3-106633.6" + wire $0\dec31_dec_sub23_lk[0:0] + attribute \src "libresoc.v:106928.3-106976.6" + wire width 2 $0\dec31_dec_sub23_out_sel[1:0] + attribute \src "libresoc.v:105997.3-106045.6" + wire width 2 $0\dec31_dec_sub23_rc_sel[1:0] + attribute \src "libresoc.v:106389.3-106437.6" + wire $0\dec31_dec_sub23_rsrv[0:0] + attribute \src "libresoc.v:106634.3-106682.6" + wire $0\dec31_dec_sub23_sgl_pipe[0:0] + attribute \src "libresoc.v:106536.3-106584.6" + wire $0\dec31_dec_sub23_sgn[0:0] + attribute \src "libresoc.v:106340.3-106388.6" + wire $0\dec31_dec_sub23_sgn_ext[0:0] + attribute \src "libresoc.v:105752.3-105800.6" + wire width 3 $0\dec31_dec_sub23_sv_cr_in[2:0] + attribute \src "libresoc.v:105801.3-105849.6" + wire width 3 $0\dec31_dec_sub23_sv_cr_out[2:0] + attribute \src "libresoc.v:105556.3-105604.6" + wire width 3 $0\dec31_dec_sub23_sv_in1[2:0] + attribute \src "libresoc.v:105605.3-105653.6" + wire width 3 $0\dec31_dec_sub23_sv_in2[2:0] + attribute \src "libresoc.v:105654.3-105702.6" + wire width 3 $0\dec31_dec_sub23_sv_in3[2:0] + attribute \src "libresoc.v:105703.3-105751.6" + wire width 3 $0\dec31_dec_sub23_sv_out[2:0] + attribute \src "libresoc.v:105899.3-105947.6" + wire width 2 $0\dec31_dec_sub23_upd[1:0] + attribute \src "libresoc.v:105075.7-105075.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:106683.3-106731.6" + wire width 2 $1\dec31_dec_sub23_SV_Etype[1:0] + attribute \src "libresoc.v:106732.3-106780.6" + wire width 2 $1\dec31_dec_sub23_SV_Ptype[1:0] + attribute \src "libresoc.v:106095.3-106143.6" + wire width 8 $1\dec31_dec_sub23_asmcode[7:0] + attribute \src "libresoc.v:106291.3-106339.6" + wire $1\dec31_dec_sub23_br[0:0] + attribute \src "libresoc.v:105458.3-105506.6" + wire width 3 $1\dec31_dec_sub23_cr_in[2:0] + attribute \src "libresoc.v:105507.3-105555.6" + wire width 3 $1\dec31_dec_sub23_cr_out[2:0] + attribute \src "libresoc.v:106046.3-106094.6" + wire width 2 $1\dec31_dec_sub23_cry_in[1:0] + attribute \src "libresoc.v:106242.3-106290.6" + wire $1\dec31_dec_sub23_cry_out[0:0] + attribute \src "libresoc.v:106487.3-106535.6" + wire width 5 $1\dec31_dec_sub23_form[4:0] + attribute \src "libresoc.v:105409.3-105457.6" + wire width 13 $1\dec31_dec_sub23_function_unit[12:0] + attribute \src "libresoc.v:106781.3-106829.6" + wire width 3 $1\dec31_dec_sub23_in1_sel[2:0] + attribute \src "libresoc.v:106830.3-106878.6" + wire width 4 $1\dec31_dec_sub23_in2_sel[3:0] + attribute \src "libresoc.v:106879.3-106927.6" + wire width 2 $1\dec31_dec_sub23_in3_sel[1:0] + attribute \src "libresoc.v:105948.3-105996.6" + wire width 7 $1\dec31_dec_sub23_internal_op[6:0] + attribute \src "libresoc.v:106144.3-106192.6" + wire $1\dec31_dec_sub23_inv_a[0:0] + attribute \src "libresoc.v:106193.3-106241.6" + wire $1\dec31_dec_sub23_inv_out[0:0] + attribute \src "libresoc.v:106438.3-106486.6" + wire $1\dec31_dec_sub23_is_32b[0:0] + attribute \src "libresoc.v:105850.3-105898.6" + wire width 4 $1\dec31_dec_sub23_ldst_len[3:0] + attribute \src "libresoc.v:106585.3-106633.6" + wire $1\dec31_dec_sub23_lk[0:0] + attribute \src "libresoc.v:106928.3-106976.6" + wire width 2 $1\dec31_dec_sub23_out_sel[1:0] + attribute \src "libresoc.v:105997.3-106045.6" + wire width 2 $1\dec31_dec_sub23_rc_sel[1:0] + attribute \src "libresoc.v:106389.3-106437.6" + wire $1\dec31_dec_sub23_rsrv[0:0] + attribute \src "libresoc.v:106634.3-106682.6" + wire $1\dec31_dec_sub23_sgl_pipe[0:0] + attribute \src "libresoc.v:106536.3-106584.6" + wire $1\dec31_dec_sub23_sgn[0:0] + attribute \src "libresoc.v:106340.3-106388.6" + wire $1\dec31_dec_sub23_sgn_ext[0:0] + attribute \src "libresoc.v:105752.3-105800.6" + wire width 3 $1\dec31_dec_sub23_sv_cr_in[2:0] + attribute \src "libresoc.v:105801.3-105849.6" + wire width 3 $1\dec31_dec_sub23_sv_cr_out[2:0] + attribute \src "libresoc.v:105556.3-105604.6" + wire width 3 $1\dec31_dec_sub23_sv_in1[2:0] + attribute \src "libresoc.v:105605.3-105653.6" + wire width 3 $1\dec31_dec_sub23_sv_in2[2:0] + attribute \src "libresoc.v:105654.3-105702.6" + wire width 3 $1\dec31_dec_sub23_sv_in3[2:0] + attribute \src "libresoc.v:105703.3-105751.6" + wire width 3 $1\dec31_dec_sub23_sv_out[2:0] + attribute \src "libresoc.v:105899.3-105947.6" + wire width 2 $1\dec31_dec_sub23_upd[1:0] + attribute \enum_base_type "SVEtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "EXTRA2" + attribute \enum_value_10 "EXTRA3" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 5 \dec31_dec_sub23_SV_Etype + attribute \enum_base_type "SVPtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "P1" + attribute \enum_value_10 "P2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 6 \dec31_dec_sub23_SV_Ptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 8 output 4 \dec31_dec_sub23_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 26 \dec31_dec_sub23_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 11 \dec31_dec_sub23_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 12 \dec31_dec_sub23_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 22 \dec31_dec_sub23_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 25 \dec31_dec_sub23_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 5 output 3 \dec31_dec_sub23_form + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 13 output 1 \dec31_dec_sub23_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 7 \dec31_dec_sub23_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 8 \dec31_dec_sub23_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 9 \dec31_dec_sub23_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 output 2 \dec31_dec_sub23_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 23 \dec31_dec_sub23_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 24 \dec31_dec_sub23_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 29 \dec31_dec_sub23_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 19 \dec31_dec_sub23_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 31 \dec31_dec_sub23_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 10 \dec31_dec_sub23_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 21 \dec31_dec_sub23_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 28 \dec31_dec_sub23_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 32 \dec31_dec_sub23_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 30 \dec31_dec_sub23_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 27 \dec31_dec_sub23_sgn_ext + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 17 \dec31_dec_sub23_sv_cr_in + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 18 \dec31_dec_sub23_sv_cr_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 13 \dec31_dec_sub23_sv_in1 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 14 \dec31_dec_sub23_sv_in2 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 15 \dec31_dec_sub23_sv_in3 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 16 \dec31_dec_sub23_sv_out + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 20 \dec31_dec_sub23_upd + attribute \src "libresoc.v:105075.7-105075.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + wire width 32 input 33 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + wire width 5 \opcode_switch + attribute \src "libresoc.v:105075.7-105075.20" + process $proc$libresoc.v:105075$4161 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:105409.3-105457.6" + process $proc$libresoc.v:105409$4129 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_function_unit[12:0] $1\dec31_dec_sub23_function_unit[12:0] + attribute \src "libresoc.v:105410.5-105410.29" + switch \initial + attribute \src "libresoc.v:105410.9-105410.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_function_unit[12:0] 13'0000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_function_unit[12:0] 13'0000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_function_unit[12:0] 13'0000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_function_unit[12:0] 13'0000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_function_unit[12:0] 13'0000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_function_unit[12:0] 13'0000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_function_unit[12:0] 13'0000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_function_unit[12:0] 13'0000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_function_unit[12:0] 13'0000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_function_unit[12:0] 13'0000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_function_unit[12:0] 13'0000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_function_unit[12:0] 13'0000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_function_unit[12:0] 13'0000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_function_unit[12:0] 13'0000000000100 + case + assign $1\dec31_dec_sub23_function_unit[12:0] 13'0000000000000 + end + sync always + update \dec31_dec_sub23_function_unit $0\dec31_dec_sub23_function_unit[12:0] + end + attribute \src "libresoc.v:105458.3-105506.6" + process $proc$libresoc.v:105458$4130 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_cr_in[2:0] $1\dec31_dec_sub23_cr_in[2:0] + attribute \src "libresoc.v:105459.5-105459.29" + switch \initial + attribute \src "libresoc.v:105459.9-105459.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub23_cr_in $0\dec31_dec_sub23_cr_in[2:0] + end + attribute \src "libresoc.v:105507.3-105555.6" + process $proc$libresoc.v:105507$4131 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_cr_out[2:0] $1\dec31_dec_sub23_cr_out[2:0] + attribute \src "libresoc.v:105508.5-105508.29" + switch \initial + attribute \src "libresoc.v:105508.9-105508.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 + case + assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub23_cr_out $0\dec31_dec_sub23_cr_out[2:0] + end + attribute \src "libresoc.v:105556.3-105604.6" + process $proc$libresoc.v:105556$4132 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_sv_in1[2:0] $1\dec31_dec_sub23_sv_in1[2:0] + attribute \src "libresoc.v:105557.5-105557.29" + switch \initial + attribute \src "libresoc.v:105557.9-105557.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_sv_in1[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_sv_in1[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_sv_in1[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_sv_in1[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_sv_in1[2:0] 3'010 + case + assign $1\dec31_dec_sub23_sv_in1[2:0] 3'000 + end + sync always + update \dec31_dec_sub23_sv_in1 $0\dec31_dec_sub23_sv_in1[2:0] + end + attribute \src "libresoc.v:105605.3-105653.6" + process $proc$libresoc.v:105605$4133 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_sv_in2[2:0] $1\dec31_dec_sub23_sv_in2[2:0] + attribute \src "libresoc.v:105606.5-105606.29" + switch \initial + attribute \src "libresoc.v:105606.9-105606.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_sv_in2[2:0] 3'011 + case + assign $1\dec31_dec_sub23_sv_in2[2:0] 3'000 + end + sync always + update \dec31_dec_sub23_sv_in2 $0\dec31_dec_sub23_sv_in2[2:0] + end + attribute \src "libresoc.v:105654.3-105702.6" + process $proc$libresoc.v:105654$4134 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_sv_in3[2:0] $1\dec31_dec_sub23_sv_in3[2:0] + attribute \src "libresoc.v:105655.5-105655.29" + switch \initial + attribute \src "libresoc.v:105655.9-105655.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_sv_in3[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_sv_in3[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_sv_in3[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_sv_in3[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_sv_in3[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_sv_in3[2:0] 3'001 + case + assign $1\dec31_dec_sub23_sv_in3[2:0] 3'000 + end + sync always + update \dec31_dec_sub23_sv_in3 $0\dec31_dec_sub23_sv_in3[2:0] + end + attribute \src "libresoc.v:105703.3-105751.6" + process $proc$libresoc.v:105703$4135 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_sv_out[2:0] $1\dec31_dec_sub23_sv_out[2:0] + attribute \src "libresoc.v:105704.5-105704.29" + switch \initial + attribute \src "libresoc.v:105704.9-105704.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_sv_out[2:0] 3'000 + case + assign $1\dec31_dec_sub23_sv_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub23_sv_out $0\dec31_dec_sub23_sv_out[2:0] + end + attribute \src "libresoc.v:105752.3-105800.6" + process $proc$libresoc.v:105752$4136 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_sv_cr_in[2:0] $1\dec31_dec_sub23_sv_cr_in[2:0] + attribute \src "libresoc.v:105753.5-105753.29" + switch \initial + attribute \src "libresoc.v:105753.9-105753.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_sv_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub23_sv_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub23_sv_cr_in $0\dec31_dec_sub23_sv_cr_in[2:0] + end + attribute \src "libresoc.v:105801.3-105849.6" + process $proc$libresoc.v:105801$4137 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_sv_cr_out[2:0] $1\dec31_dec_sub23_sv_cr_out[2:0] + attribute \src "libresoc.v:105802.5-105802.29" + switch \initial + attribute \src "libresoc.v:105802.9-105802.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_sv_cr_out[2:0] 3'000 + case + assign $1\dec31_dec_sub23_sv_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub23_sv_cr_out $0\dec31_dec_sub23_sv_cr_out[2:0] + end + attribute \src "libresoc.v:105850.3-105898.6" + process $proc$libresoc.v:105850$4138 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_ldst_len[3:0] $1\dec31_dec_sub23_ldst_len[3:0] + attribute \src "libresoc.v:105851.5-105851.29" + switch \initial + attribute \src "libresoc.v:105851.9-105851.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0100 + case + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub23_ldst_len $0\dec31_dec_sub23_ldst_len[3:0] + end + attribute \src "libresoc.v:105899.3-105947.6" + process $proc$libresoc.v:105899$4139 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_upd[1:0] $1\dec31_dec_sub23_upd[1:0] + attribute \src "libresoc.v:105900.5-105900.29" + switch \initial + attribute \src "libresoc.v:105900.9-105900.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_upd[1:0] 2'00 + case + assign $1\dec31_dec_sub23_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub23_upd $0\dec31_dec_sub23_upd[1:0] + end + attribute \src "libresoc.v:105948.3-105996.6" + process $proc$libresoc.v:105948$4140 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_internal_op[6:0] $1\dec31_dec_sub23_internal_op[6:0] + attribute \src "libresoc.v:105949.5-105949.29" + switch \initial + attribute \src "libresoc.v:105949.9-105949.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100110 + case + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub23_internal_op $0\dec31_dec_sub23_internal_op[6:0] + end + attribute \src "libresoc.v:105997.3-106045.6" + process $proc$libresoc.v:105997$4141 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_rc_sel[1:0] $1\dec31_dec_sub23_rc_sel[1:0] + attribute \src "libresoc.v:105998.5-105998.29" + switch \initial + attribute \src "libresoc.v:105998.9-105998.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub23_rc_sel $0\dec31_dec_sub23_rc_sel[1:0] + end + attribute \src "libresoc.v:106046.3-106094.6" + process $proc$libresoc.v:106046$4142 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_cry_in[1:0] $1\dec31_dec_sub23_cry_in[1:0] + attribute \src "libresoc.v:106047.5-106047.29" + switch \initial + attribute \src "libresoc.v:106047.9-106047.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 + case + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub23_cry_in $0\dec31_dec_sub23_cry_in[1:0] + end + attribute \src "libresoc.v:106095.3-106143.6" + process $proc$libresoc.v:106095$4143 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_asmcode[7:0] $1\dec31_dec_sub23_asmcode[7:0] + attribute \src "libresoc.v:106096.5-106096.29" + switch \initial + attribute \src "libresoc.v:106096.9-106096.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_asmcode[7:0] 8'01010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_asmcode[7:0] 8'01010001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_asmcode[7:0] 8'01011011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_asmcode[7:0] 8'01011100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_asmcode[7:0] 8'01100000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_asmcode[7:0] 8'01100001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_asmcode[7:0] 8'01101010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_asmcode[7:0] 8'01101011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_asmcode[7:0] 8'10101011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_asmcode[7:0] 8'10101100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_asmcode[7:0] 8'10110111 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_asmcode[7:0] 8'10111000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_asmcode[7:0] 8'10111101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_asmcode[7:0] 8'10111110 + case + assign $1\dec31_dec_sub23_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub23_asmcode $0\dec31_dec_sub23_asmcode[7:0] + end + attribute \src "libresoc.v:106144.3-106192.6" + process $proc$libresoc.v:106144$4144 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_inv_a[0:0] $1\dec31_dec_sub23_inv_a[0:0] + attribute \src "libresoc.v:106145.5-106145.29" + switch \initial + attribute \src "libresoc.v:106145.9-106145.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 + case + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub23_inv_a $0\dec31_dec_sub23_inv_a[0:0] + end + attribute \src "libresoc.v:106193.3-106241.6" + process $proc$libresoc.v:106193$4145 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_inv_out[0:0] $1\dec31_dec_sub23_inv_out[0:0] + attribute \src "libresoc.v:106194.5-106194.29" + switch \initial + attribute \src "libresoc.v:106194.9-106194.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub23_inv_out $0\dec31_dec_sub23_inv_out[0:0] + end + attribute \src "libresoc.v:106242.3-106290.6" + process $proc$libresoc.v:106242$4146 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_cry_out[0:0] $1\dec31_dec_sub23_cry_out[0:0] + attribute \src "libresoc.v:106243.5-106243.29" + switch \initial + attribute \src "libresoc.v:106243.9-106243.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 + case + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub23_cry_out $0\dec31_dec_sub23_cry_out[0:0] + end + attribute \src "libresoc.v:106291.3-106339.6" + process $proc$libresoc.v:106291$4147 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_br[0:0] $1\dec31_dec_sub23_br[0:0] + attribute \src "libresoc.v:106292.5-106292.29" + switch \initial + attribute \src "libresoc.v:106292.9-106292.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_br[0:0] 1'0 + case + assign $1\dec31_dec_sub23_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub23_br $0\dec31_dec_sub23_br[0:0] + end + attribute \src "libresoc.v:106340.3-106388.6" + process $proc$libresoc.v:106340$4148 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_sgn_ext[0:0] $1\dec31_dec_sub23_sgn_ext[0:0] + attribute \src "libresoc.v:106341.5-106341.29" + switch \initial + attribute \src "libresoc.v:106341.9-106341.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub23_sgn_ext $0\dec31_dec_sub23_sgn_ext[0:0] + end + attribute \src "libresoc.v:106389.3-106437.6" + process $proc$libresoc.v:106389$4149 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_rsrv[0:0] $1\dec31_dec_sub23_rsrv[0:0] + attribute \src "libresoc.v:106390.5-106390.29" + switch \initial + attribute \src "libresoc.v:106390.9-106390.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub23_rsrv $0\dec31_dec_sub23_rsrv[0:0] + end + attribute \src "libresoc.v:106438.3-106486.6" + process $proc$libresoc.v:106438$4150 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_is_32b[0:0] $1\dec31_dec_sub23_is_32b[0:0] + attribute \src "libresoc.v:106439.5-106439.29" + switch \initial + attribute \src "libresoc.v:106439.9-106439.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + case + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub23_is_32b $0\dec31_dec_sub23_is_32b[0:0] + end + attribute \src "libresoc.v:106487.3-106535.6" + process $proc$libresoc.v:106487$4151 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_form[4:0] $1\dec31_dec_sub23_form[4:0] + attribute \src "libresoc.v:106488.5-106488.29" + switch \initial + attribute \src "libresoc.v:106488.9-106488.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_form[4:0] 5'01000 + case + assign $1\dec31_dec_sub23_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub23_form $0\dec31_dec_sub23_form[4:0] + end + attribute \src "libresoc.v:106536.3-106584.6" + process $proc$libresoc.v:106536$4152 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_sgn[0:0] $1\dec31_dec_sub23_sgn[0:0] + attribute \src "libresoc.v:106537.5-106537.29" + switch \initial + attribute \src "libresoc.v:106537.9-106537.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 + case + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub23_sgn $0\dec31_dec_sub23_sgn[0:0] + end + attribute \src "libresoc.v:106585.3-106633.6" + process $proc$libresoc.v:106585$4153 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_lk[0:0] $1\dec31_dec_sub23_lk[0:0] + attribute \src "libresoc.v:106586.5-106586.29" + switch \initial + attribute \src "libresoc.v:106586.9-106586.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub23_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub23_lk $0\dec31_dec_sub23_lk[0:0] + end + attribute \src "libresoc.v:106634.3-106682.6" + process $proc$libresoc.v:106634$4154 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_sgl_pipe[0:0] $1\dec31_dec_sub23_sgl_pipe[0:0] + attribute \src "libresoc.v:106635.5-106635.29" + switch \initial + attribute \src "libresoc.v:106635.9-106635.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 + case + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub23_sgl_pipe $0\dec31_dec_sub23_sgl_pipe[0:0] + end + attribute \src "libresoc.v:106683.3-106731.6" + process $proc$libresoc.v:106683$4155 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_SV_Etype[1:0] $1\dec31_dec_sub23_SV_Etype[1:0] + attribute \src "libresoc.v:106684.5-106684.29" + switch \initial + attribute \src "libresoc.v:106684.9-106684.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_SV_Etype[1:0] 2'01 + case + assign $1\dec31_dec_sub23_SV_Etype[1:0] 2'00 + end + sync always + update \dec31_dec_sub23_SV_Etype $0\dec31_dec_sub23_SV_Etype[1:0] + end + attribute \src "libresoc.v:106732.3-106780.6" + process $proc$libresoc.v:106732$4156 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_SV_Ptype[1:0] $1\dec31_dec_sub23_SV_Ptype[1:0] + attribute \src "libresoc.v:106733.5-106733.29" + switch \initial + attribute \src "libresoc.v:106733.9-106733.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_SV_Ptype[1:0] 2'10 + case + assign $1\dec31_dec_sub23_SV_Ptype[1:0] 2'00 + end + sync always + update \dec31_dec_sub23_SV_Ptype $0\dec31_dec_sub23_SV_Ptype[1:0] + end + attribute \src "libresoc.v:106781.3-106829.6" + process $proc$libresoc.v:106781$4157 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_in1_sel[2:0] $1\dec31_dec_sub23_in1_sel[2:0] + attribute \src "libresoc.v:106782.5-106782.29" + switch \initial + attribute \src "libresoc.v:106782.9-106782.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 + case + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub23_in1_sel $0\dec31_dec_sub23_in1_sel[2:0] + end + attribute \src "libresoc.v:106830.3-106878.6" + process $proc$libresoc.v:106830$4158 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_in2_sel[3:0] $1\dec31_dec_sub23_in2_sel[3:0] + attribute \src "libresoc.v:106831.5-106831.29" + switch \initial + attribute \src "libresoc.v:106831.9-106831.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 + case + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub23_in2_sel $0\dec31_dec_sub23_in2_sel[3:0] + end + attribute \src "libresoc.v:106879.3-106927.6" + process $proc$libresoc.v:106879$4159 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_in3_sel[1:0] $1\dec31_dec_sub23_in3_sel[1:0] + attribute \src "libresoc.v:106880.5-106880.29" + switch \initial + attribute \src "libresoc.v:106880.9-106880.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'01 + case + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub23_in3_sel $0\dec31_dec_sub23_in3_sel[1:0] + end + attribute \src "libresoc.v:106928.3-106976.6" + process $proc$libresoc.v:106928$4160 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_out_sel[1:0] $1\dec31_dec_sub23_out_sel[1:0] + attribute \src "libresoc.v:106929.5-106929.29" + switch \initial + attribute \src "libresoc.v:106929.9-106929.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_out_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub23_out_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub23_out_sel $0\dec31_dec_sub23_out_sel[1:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:106982.1-107926.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub24" +attribute \generator "nMigen" +module \dec31_dec_sub24 + attribute \src "libresoc.v:107811.3-107829.6" + wire width 2 $0\dec31_dec_sub24_SV_Etype[1:0] + attribute \src "libresoc.v:107830.3-107848.6" + wire width 2 $0\dec31_dec_sub24_SV_Ptype[1:0] + attribute \src "libresoc.v:107583.3-107601.6" + wire width 8 $0\dec31_dec_sub24_asmcode[7:0] + attribute \src "libresoc.v:107659.3-107677.6" + wire $0\dec31_dec_sub24_br[0:0] + attribute \src "libresoc.v:107336.3-107354.6" + wire width 3 $0\dec31_dec_sub24_cr_in[2:0] + attribute \src "libresoc.v:107355.3-107373.6" + wire width 3 $0\dec31_dec_sub24_cr_out[2:0] + attribute \src "libresoc.v:107564.3-107582.6" + wire width 2 $0\dec31_dec_sub24_cry_in[1:0] + attribute \src "libresoc.v:107640.3-107658.6" + wire $0\dec31_dec_sub24_cry_out[0:0] + attribute \src "libresoc.v:107735.3-107753.6" + wire width 5 $0\dec31_dec_sub24_form[4:0] + attribute \src "libresoc.v:107317.3-107335.6" + wire width 13 $0\dec31_dec_sub24_function_unit[12:0] + attribute \src "libresoc.v:107849.3-107867.6" + wire width 3 $0\dec31_dec_sub24_in1_sel[2:0] + attribute \src "libresoc.v:107868.3-107886.6" + wire width 4 $0\dec31_dec_sub24_in2_sel[3:0] + attribute \src "libresoc.v:107887.3-107905.6" + wire width 2 $0\dec31_dec_sub24_in3_sel[1:0] + attribute \src "libresoc.v:107526.3-107544.6" + wire width 7 $0\dec31_dec_sub24_internal_op[6:0] + attribute \src "libresoc.v:107602.3-107620.6" + wire $0\dec31_dec_sub24_inv_a[0:0] + attribute \src "libresoc.v:107621.3-107639.6" + wire $0\dec31_dec_sub24_inv_out[0:0] + attribute \src "libresoc.v:107716.3-107734.6" + wire $0\dec31_dec_sub24_is_32b[0:0] + attribute \src "libresoc.v:107488.3-107506.6" + wire width 4 $0\dec31_dec_sub24_ldst_len[3:0] + attribute \src "libresoc.v:107773.3-107791.6" + wire $0\dec31_dec_sub24_lk[0:0] + attribute \src "libresoc.v:107906.3-107924.6" + wire width 2 $0\dec31_dec_sub24_out_sel[1:0] + attribute \src "libresoc.v:107545.3-107563.6" + wire width 2 $0\dec31_dec_sub24_rc_sel[1:0] + attribute \src "libresoc.v:107697.3-107715.6" + wire $0\dec31_dec_sub24_rsrv[0:0] + attribute \src "libresoc.v:107792.3-107810.6" + wire $0\dec31_dec_sub24_sgl_pipe[0:0] + attribute \src "libresoc.v:107754.3-107772.6" + wire $0\dec31_dec_sub24_sgn[0:0] + attribute \src "libresoc.v:107678.3-107696.6" + wire $0\dec31_dec_sub24_sgn_ext[0:0] + attribute \src "libresoc.v:107450.3-107468.6" + wire width 3 $0\dec31_dec_sub24_sv_cr_in[2:0] + attribute \src "libresoc.v:107469.3-107487.6" + wire width 3 $0\dec31_dec_sub24_sv_cr_out[2:0] + attribute \src "libresoc.v:107374.3-107392.6" + wire width 3 $0\dec31_dec_sub24_sv_in1[2:0] + attribute \src "libresoc.v:107393.3-107411.6" + wire width 3 $0\dec31_dec_sub24_sv_in2[2:0] + attribute \src "libresoc.v:107412.3-107430.6" + wire width 3 $0\dec31_dec_sub24_sv_in3[2:0] + attribute \src "libresoc.v:107431.3-107449.6" + wire width 3 $0\dec31_dec_sub24_sv_out[2:0] + attribute \src "libresoc.v:107507.3-107525.6" + wire width 2 $0\dec31_dec_sub24_upd[1:0] + attribute \src "libresoc.v:106983.7-106983.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:107811.3-107829.6" + wire width 2 $1\dec31_dec_sub24_SV_Etype[1:0] + attribute \src "libresoc.v:107830.3-107848.6" + wire width 2 $1\dec31_dec_sub24_SV_Ptype[1:0] + attribute \src "libresoc.v:107583.3-107601.6" + wire width 8 $1\dec31_dec_sub24_asmcode[7:0] + attribute \src "libresoc.v:107659.3-107677.6" + wire $1\dec31_dec_sub24_br[0:0] + attribute \src "libresoc.v:107336.3-107354.6" + wire width 3 $1\dec31_dec_sub24_cr_in[2:0] + attribute \src "libresoc.v:107355.3-107373.6" + wire width 3 $1\dec31_dec_sub24_cr_out[2:0] + attribute \src "libresoc.v:107564.3-107582.6" + wire width 2 $1\dec31_dec_sub24_cry_in[1:0] + attribute \src "libresoc.v:107640.3-107658.6" + wire $1\dec31_dec_sub24_cry_out[0:0] + attribute \src "libresoc.v:107735.3-107753.6" + wire width 5 $1\dec31_dec_sub24_form[4:0] + attribute \src "libresoc.v:107317.3-107335.6" + wire width 13 $1\dec31_dec_sub24_function_unit[12:0] + attribute \src "libresoc.v:107849.3-107867.6" + wire width 3 $1\dec31_dec_sub24_in1_sel[2:0] + attribute \src "libresoc.v:107868.3-107886.6" + wire width 4 $1\dec31_dec_sub24_in2_sel[3:0] + attribute \src "libresoc.v:107887.3-107905.6" + wire width 2 $1\dec31_dec_sub24_in3_sel[1:0] + attribute \src "libresoc.v:107526.3-107544.6" + wire width 7 $1\dec31_dec_sub24_internal_op[6:0] + attribute \src "libresoc.v:107602.3-107620.6" + wire $1\dec31_dec_sub24_inv_a[0:0] + attribute \src "libresoc.v:107621.3-107639.6" + wire $1\dec31_dec_sub24_inv_out[0:0] + attribute \src "libresoc.v:107716.3-107734.6" + wire $1\dec31_dec_sub24_is_32b[0:0] + attribute \src "libresoc.v:107488.3-107506.6" + wire width 4 $1\dec31_dec_sub24_ldst_len[3:0] + attribute \src "libresoc.v:107773.3-107791.6" + wire $1\dec31_dec_sub24_lk[0:0] + attribute \src "libresoc.v:107906.3-107924.6" + wire width 2 $1\dec31_dec_sub24_out_sel[1:0] + attribute \src "libresoc.v:107545.3-107563.6" + wire width 2 $1\dec31_dec_sub24_rc_sel[1:0] + attribute \src "libresoc.v:107697.3-107715.6" + wire $1\dec31_dec_sub24_rsrv[0:0] + attribute \src "libresoc.v:107792.3-107810.6" + wire $1\dec31_dec_sub24_sgl_pipe[0:0] + attribute \src "libresoc.v:107754.3-107772.6" + wire $1\dec31_dec_sub24_sgn[0:0] + attribute \src "libresoc.v:107678.3-107696.6" + wire $1\dec31_dec_sub24_sgn_ext[0:0] + attribute \src "libresoc.v:107450.3-107468.6" + wire width 3 $1\dec31_dec_sub24_sv_cr_in[2:0] + attribute \src "libresoc.v:107469.3-107487.6" + wire width 3 $1\dec31_dec_sub24_sv_cr_out[2:0] + attribute \src "libresoc.v:107374.3-107392.6" + wire width 3 $1\dec31_dec_sub24_sv_in1[2:0] + attribute \src "libresoc.v:107393.3-107411.6" + wire width 3 $1\dec31_dec_sub24_sv_in2[2:0] + attribute \src "libresoc.v:107412.3-107430.6" + wire width 3 $1\dec31_dec_sub24_sv_in3[2:0] + attribute \src "libresoc.v:107431.3-107449.6" + wire width 3 $1\dec31_dec_sub24_sv_out[2:0] + attribute \src "libresoc.v:107507.3-107525.6" + wire width 2 $1\dec31_dec_sub24_upd[1:0] + attribute \enum_base_type "SVEtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "EXTRA2" + attribute \enum_value_10 "EXTRA3" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 5 \dec31_dec_sub24_SV_Etype + attribute \enum_base_type "SVPtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "P1" + attribute \enum_value_10 "P2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 6 \dec31_dec_sub24_SV_Ptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 8 output 4 \dec31_dec_sub24_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 26 \dec31_dec_sub24_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 11 \dec31_dec_sub24_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 12 \dec31_dec_sub24_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 22 \dec31_dec_sub24_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 25 \dec31_dec_sub24_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 5 output 3 \dec31_dec_sub24_form + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 13 output 1 \dec31_dec_sub24_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 7 \dec31_dec_sub24_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 8 \dec31_dec_sub24_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 9 \dec31_dec_sub24_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 output 2 \dec31_dec_sub24_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 23 \dec31_dec_sub24_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 24 \dec31_dec_sub24_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 29 \dec31_dec_sub24_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 19 \dec31_dec_sub24_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 31 \dec31_dec_sub24_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 10 \dec31_dec_sub24_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 21 \dec31_dec_sub24_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 28 \dec31_dec_sub24_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 32 \dec31_dec_sub24_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 30 \dec31_dec_sub24_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 27 \dec31_dec_sub24_sgn_ext + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 17 \dec31_dec_sub24_sv_cr_in + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 18 \dec31_dec_sub24_sv_cr_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 13 \dec31_dec_sub24_sv_in1 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 14 \dec31_dec_sub24_sv_in2 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 15 \dec31_dec_sub24_sv_in3 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 16 \dec31_dec_sub24_sv_out + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 20 \dec31_dec_sub24_upd + attribute \src "libresoc.v:106983.7-106983.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + wire width 32 input 33 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + wire width 5 \opcode_switch + attribute \src "libresoc.v:106983.7-106983.20" + process $proc$libresoc.v:106983$4194 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:107317.3-107335.6" + process $proc$libresoc.v:107317$4162 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_function_unit[12:0] $1\dec31_dec_sub24_function_unit[12:0] + attribute \src "libresoc.v:107318.5-107318.29" + switch \initial + attribute \src "libresoc.v:107318.9-107318.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_function_unit[12:0] 13'0000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_function_unit[12:0] 13'0000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_function_unit[12:0] 13'0000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_function_unit[12:0] 13'0000000001000 + case + assign $1\dec31_dec_sub24_function_unit[12:0] 13'0000000000000 + end + sync always + update \dec31_dec_sub24_function_unit $0\dec31_dec_sub24_function_unit[12:0] + end + attribute \src "libresoc.v:107336.3-107354.6" + process $proc$libresoc.v:107336$4163 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_cr_in[2:0] $1\dec31_dec_sub24_cr_in[2:0] + attribute \src "libresoc.v:107337.5-107337.29" + switch \initial + attribute \src "libresoc.v:107337.9-107337.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub24_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub24_cr_in $0\dec31_dec_sub24_cr_in[2:0] + end + attribute \src "libresoc.v:107355.3-107373.6" + process $proc$libresoc.v:107355$4164 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_cr_out[2:0] $1\dec31_dec_sub24_cr_out[2:0] + attribute \src "libresoc.v:107356.5-107356.29" + switch \initial + attribute \src "libresoc.v:107356.9-107356.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_cr_out[2:0] 3'001 + case + assign $1\dec31_dec_sub24_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub24_cr_out $0\dec31_dec_sub24_cr_out[2:0] + end + attribute \src "libresoc.v:107374.3-107392.6" + process $proc$libresoc.v:107374$4165 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_sv_in1[2:0] $1\dec31_dec_sub24_sv_in1[2:0] + attribute \src "libresoc.v:107375.5-107375.29" + switch \initial + attribute \src "libresoc.v:107375.9-107375.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_sv_in1[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_sv_in1[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_sv_in1[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_sv_in1[2:0] 3'000 + case + assign $1\dec31_dec_sub24_sv_in1[2:0] 3'000 + end + sync always + update \dec31_dec_sub24_sv_in1 $0\dec31_dec_sub24_sv_in1[2:0] + end + attribute \src "libresoc.v:107393.3-107411.6" + process $proc$libresoc.v:107393$4166 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_sv_in2[2:0] $1\dec31_dec_sub24_sv_in2[2:0] + attribute \src "libresoc.v:107394.5-107394.29" + switch \initial + attribute \src "libresoc.v:107394.9-107394.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_sv_in2[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_sv_in2[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_sv_in2[2:0] 3'010 + case + assign $1\dec31_dec_sub24_sv_in2[2:0] 3'000 + end + sync always + update \dec31_dec_sub24_sv_in2 $0\dec31_dec_sub24_sv_in2[2:0] + end + attribute \src "libresoc.v:107412.3-107430.6" + process $proc$libresoc.v:107412$4167 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_sv_in3[2:0] $1\dec31_dec_sub24_sv_in3[2:0] + attribute \src "libresoc.v:107413.5-107413.29" + switch \initial + attribute \src "libresoc.v:107413.9-107413.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_sv_in3[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_sv_in3[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_sv_in3[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_sv_in3[2:0] 3'011 + case + assign $1\dec31_dec_sub24_sv_in3[2:0] 3'000 + end + sync always + update \dec31_dec_sub24_sv_in3 $0\dec31_dec_sub24_sv_in3[2:0] + end + attribute \src "libresoc.v:107431.3-107449.6" + process $proc$libresoc.v:107431$4168 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_sv_out[2:0] $1\dec31_dec_sub24_sv_out[2:0] + attribute \src "libresoc.v:107432.5-107432.29" + switch \initial + attribute \src "libresoc.v:107432.9-107432.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_sv_out[2:0] 3'001 + case + assign $1\dec31_dec_sub24_sv_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub24_sv_out $0\dec31_dec_sub24_sv_out[2:0] + end + attribute \src "libresoc.v:107450.3-107468.6" + process $proc$libresoc.v:107450$4169 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_sv_cr_in[2:0] $1\dec31_dec_sub24_sv_cr_in[2:0] + attribute \src "libresoc.v:107451.5-107451.29" + switch \initial + attribute \src "libresoc.v:107451.9-107451.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_sv_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub24_sv_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub24_sv_cr_in $0\dec31_dec_sub24_sv_cr_in[2:0] + end + attribute \src "libresoc.v:107469.3-107487.6" + process $proc$libresoc.v:107469$4170 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_sv_cr_out[2:0] $1\dec31_dec_sub24_sv_cr_out[2:0] + attribute \src "libresoc.v:107470.5-107470.29" + switch \initial + attribute \src "libresoc.v:107470.9-107470.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_sv_cr_out[2:0] 3'001 + case + assign $1\dec31_dec_sub24_sv_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub24_sv_cr_out $0\dec31_dec_sub24_sv_cr_out[2:0] + end + attribute \src "libresoc.v:107488.3-107506.6" + process $proc$libresoc.v:107488$4171 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_ldst_len[3:0] $1\dec31_dec_sub24_ldst_len[3:0] + attribute \src "libresoc.v:107489.5-107489.29" + switch \initial + attribute \src "libresoc.v:107489.9-107489.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_ldst_len[3:0] 4'0000 + case + assign $1\dec31_dec_sub24_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub24_ldst_len $0\dec31_dec_sub24_ldst_len[3:0] + end + attribute \src "libresoc.v:107507.3-107525.6" + process $proc$libresoc.v:107507$4172 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_upd[1:0] $1\dec31_dec_sub24_upd[1:0] + attribute \src "libresoc.v:107508.5-107508.29" + switch \initial + attribute \src "libresoc.v:107508.9-107508.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_upd[1:0] 2'00 + case + assign $1\dec31_dec_sub24_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub24_upd $0\dec31_dec_sub24_upd[1:0] + end + attribute \src "libresoc.v:107526.3-107544.6" + process $proc$libresoc.v:107526$4173 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_internal_op[6:0] $1\dec31_dec_sub24_internal_op[6:0] + attribute \src "libresoc.v:107527.5-107527.29" + switch \initial + attribute \src "libresoc.v:107527.9-107527.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_internal_op[6:0] 7'0111100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_internal_op[6:0] 7'0111101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_internal_op[6:0] 7'0111101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_internal_op[6:0] 7'0111101 + case + assign $1\dec31_dec_sub24_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub24_internal_op $0\dec31_dec_sub24_internal_op[6:0] + end + attribute \src "libresoc.v:107545.3-107563.6" + process $proc$libresoc.v:107545$4174 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_rc_sel[1:0] $1\dec31_dec_sub24_rc_sel[1:0] + attribute \src "libresoc.v:107546.5-107546.29" + switch \initial + attribute \src "libresoc.v:107546.9-107546.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_rc_sel[1:0] 2'10 + case + assign $1\dec31_dec_sub24_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub24_rc_sel $0\dec31_dec_sub24_rc_sel[1:0] + end + attribute \src "libresoc.v:107564.3-107582.6" + process $proc$libresoc.v:107564$4175 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_cry_in[1:0] $1\dec31_dec_sub24_cry_in[1:0] + attribute \src "libresoc.v:107565.5-107565.29" + switch \initial + attribute \src "libresoc.v:107565.9-107565.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_cry_in[1:0] 2'00 + case + assign $1\dec31_dec_sub24_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub24_cry_in $0\dec31_dec_sub24_cry_in[1:0] + end + attribute \src "libresoc.v:107583.3-107601.6" + process $proc$libresoc.v:107583$4176 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_asmcode[7:0] $1\dec31_dec_sub24_asmcode[7:0] + attribute \src "libresoc.v:107584.5-107584.29" + switch \initial + attribute \src "libresoc.v:107584.9-107584.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_asmcode[7:0] 8'10100000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_asmcode[7:0] 8'10100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_asmcode[7:0] 8'10100100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_asmcode[7:0] 8'10100110 + case + assign $1\dec31_dec_sub24_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub24_asmcode $0\dec31_dec_sub24_asmcode[7:0] + end + attribute \src "libresoc.v:107602.3-107620.6" + process $proc$libresoc.v:107602$4177 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_inv_a[0:0] $1\dec31_dec_sub24_inv_a[0:0] + attribute \src "libresoc.v:107603.5-107603.29" + switch \initial + attribute \src "libresoc.v:107603.9-107603.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_inv_a[0:0] 1'0 + case + assign $1\dec31_dec_sub24_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub24_inv_a $0\dec31_dec_sub24_inv_a[0:0] + end + attribute \src "libresoc.v:107621.3-107639.6" + process $proc$libresoc.v:107621$4178 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_inv_out[0:0] $1\dec31_dec_sub24_inv_out[0:0] + attribute \src "libresoc.v:107622.5-107622.29" + switch \initial + attribute \src "libresoc.v:107622.9-107622.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub24_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub24_inv_out $0\dec31_dec_sub24_inv_out[0:0] + end + attribute \src "libresoc.v:107640.3-107658.6" + process $proc$libresoc.v:107640$4179 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_cry_out[0:0] $1\dec31_dec_sub24_cry_out[0:0] + attribute \src "libresoc.v:107641.5-107641.29" + switch \initial + attribute \src "libresoc.v:107641.9-107641.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_cry_out[0:0] 1'0 + case + assign $1\dec31_dec_sub24_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub24_cry_out $0\dec31_dec_sub24_cry_out[0:0] + end + attribute \src "libresoc.v:107659.3-107677.6" + process $proc$libresoc.v:107659$4180 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_br[0:0] $1\dec31_dec_sub24_br[0:0] + attribute \src "libresoc.v:107660.5-107660.29" + switch \initial + attribute \src "libresoc.v:107660.9-107660.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_br[0:0] 1'0 + case + assign $1\dec31_dec_sub24_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub24_br $0\dec31_dec_sub24_br[0:0] + end + attribute \src "libresoc.v:107678.3-107696.6" + process $proc$libresoc.v:107678$4181 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_sgn_ext[0:0] $1\dec31_dec_sub24_sgn_ext[0:0] + attribute \src "libresoc.v:107679.5-107679.29" + switch \initial + attribute \src "libresoc.v:107679.9-107679.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub24_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub24_sgn_ext $0\dec31_dec_sub24_sgn_ext[0:0] + end + attribute \src "libresoc.v:107697.3-107715.6" + process $proc$libresoc.v:107697$4182 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_rsrv[0:0] $1\dec31_dec_sub24_rsrv[0:0] + attribute \src "libresoc.v:107698.5-107698.29" + switch \initial + attribute \src "libresoc.v:107698.9-107698.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub24_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub24_rsrv $0\dec31_dec_sub24_rsrv[0:0] + end + attribute \src "libresoc.v:107716.3-107734.6" + process $proc$libresoc.v:107716$4183 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_is_32b[0:0] $1\dec31_dec_sub24_is_32b[0:0] + attribute \src "libresoc.v:107717.5-107717.29" + switch \initial + attribute \src "libresoc.v:107717.9-107717.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_is_32b[0:0] 1'1 + case + assign $1\dec31_dec_sub24_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub24_is_32b $0\dec31_dec_sub24_is_32b[0:0] + end + attribute \src "libresoc.v:107735.3-107753.6" + process $proc$libresoc.v:107735$4184 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_form[4:0] $1\dec31_dec_sub24_form[4:0] + attribute \src "libresoc.v:107736.5-107736.29" + switch \initial + attribute \src "libresoc.v:107736.9-107736.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_form[4:0] 5'01000 + case + assign $1\dec31_dec_sub24_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub24_form $0\dec31_dec_sub24_form[4:0] + end + attribute \src "libresoc.v:107754.3-107772.6" + process $proc$libresoc.v:107754$4185 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_sgn[0:0] $1\dec31_dec_sub24_sgn[0:0] + attribute \src "libresoc.v:107755.5-107755.29" + switch \initial + attribute \src "libresoc.v:107755.9-107755.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_sgn[0:0] 1'0 + case + assign $1\dec31_dec_sub24_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub24_sgn $0\dec31_dec_sub24_sgn[0:0] + end + attribute \src "libresoc.v:107773.3-107791.6" + process $proc$libresoc.v:107773$4186 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_lk[0:0] $1\dec31_dec_sub24_lk[0:0] + attribute \src "libresoc.v:107774.5-107774.29" + switch \initial + attribute \src "libresoc.v:107774.9-107774.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub24_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub24_lk $0\dec31_dec_sub24_lk[0:0] + end + attribute \src "libresoc.v:107792.3-107810.6" + process $proc$libresoc.v:107792$4187 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_sgl_pipe[0:0] $1\dec31_dec_sub24_sgl_pipe[0:0] + attribute \src "libresoc.v:107793.5-107793.29" + switch \initial + attribute \src "libresoc.v:107793.9-107793.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_sgl_pipe[0:0] 1'0 + case + assign $1\dec31_dec_sub24_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub24_sgl_pipe $0\dec31_dec_sub24_sgl_pipe[0:0] + end + attribute \src "libresoc.v:107811.3-107829.6" + process $proc$libresoc.v:107811$4188 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_SV_Etype[1:0] $1\dec31_dec_sub24_SV_Etype[1:0] + attribute \src "libresoc.v:107812.5-107812.29" + switch \initial + attribute \src "libresoc.v:107812.9-107812.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_SV_Etype[1:0] 2'10 + case + assign $1\dec31_dec_sub24_SV_Etype[1:0] 2'00 + end + sync always + update \dec31_dec_sub24_SV_Etype $0\dec31_dec_sub24_SV_Etype[1:0] + end + attribute \src "libresoc.v:107830.3-107848.6" + process $proc$libresoc.v:107830$4189 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_SV_Ptype[1:0] $1\dec31_dec_sub24_SV_Ptype[1:0] + attribute \src "libresoc.v:107831.5-107831.29" + switch \initial + attribute \src "libresoc.v:107831.9-107831.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_SV_Ptype[1:0] 2'01 + case + assign $1\dec31_dec_sub24_SV_Ptype[1:0] 2'00 + end + sync always + update \dec31_dec_sub24_SV_Ptype $0\dec31_dec_sub24_SV_Ptype[1:0] + end + attribute \src "libresoc.v:107849.3-107867.6" + process $proc$libresoc.v:107849$4190 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_in1_sel[2:0] $1\dec31_dec_sub24_in1_sel[2:0] + attribute \src "libresoc.v:107850.5-107850.29" + switch \initial + attribute \src "libresoc.v:107850.9-107850.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_in1_sel[2:0] 3'000 + case + assign $1\dec31_dec_sub24_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub24_in1_sel $0\dec31_dec_sub24_in1_sel[2:0] + end + attribute \src "libresoc.v:107868.3-107886.6" + process $proc$libresoc.v:107868$4191 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_in2_sel[3:0] $1\dec31_dec_sub24_in2_sel[3:0] + attribute \src "libresoc.v:107869.5-107869.29" + switch \initial + attribute \src "libresoc.v:107869.9-107869.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_in2_sel[3:0] 4'1011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_in2_sel[3:0] 4'0001 + case + assign $1\dec31_dec_sub24_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub24_in2_sel $0\dec31_dec_sub24_in2_sel[3:0] + end + attribute \src "libresoc.v:107887.3-107905.6" + process $proc$libresoc.v:107887$4192 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_in3_sel[1:0] $1\dec31_dec_sub24_in3_sel[1:0] + attribute \src "libresoc.v:107888.5-107888.29" + switch \initial + attribute \src "libresoc.v:107888.9-107888.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_in3_sel[1:0] 2'01 + case + assign $1\dec31_dec_sub24_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub24_in3_sel $0\dec31_dec_sub24_in3_sel[1:0] + end + attribute \src "libresoc.v:107906.3-107924.6" + process $proc$libresoc.v:107906$4193 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_out_sel[1:0] $1\dec31_dec_sub24_out_sel[1:0] + attribute \src "libresoc.v:107907.5-107907.29" + switch \initial + attribute \src "libresoc.v:107907.9-107907.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_out_sel[1:0] 2'10 + case + assign $1\dec31_dec_sub24_out_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub24_out_sel $0\dec31_dec_sub24_out_sel[1:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:107930.1-109930.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub26" +attribute \generator "nMigen" +module \dec31_dec_sub26 + attribute \src "libresoc.v:109617.3-109668.6" + wire width 2 $0\dec31_dec_sub26_SV_Etype[1:0] + attribute \src "libresoc.v:109669.3-109720.6" + wire width 2 $0\dec31_dec_sub26_SV_Ptype[1:0] + attribute \src "libresoc.v:108993.3-109044.6" + wire width 8 $0\dec31_dec_sub26_asmcode[7:0] + attribute \src "libresoc.v:109201.3-109252.6" + wire $0\dec31_dec_sub26_br[0:0] + attribute \src "libresoc.v:108317.3-108368.6" + wire width 3 $0\dec31_dec_sub26_cr_in[2:0] + attribute \src "libresoc.v:108369.3-108420.6" + wire width 3 $0\dec31_dec_sub26_cr_out[2:0] + attribute \src "libresoc.v:108941.3-108992.6" + wire width 2 $0\dec31_dec_sub26_cry_in[1:0] + attribute \src "libresoc.v:109149.3-109200.6" + wire $0\dec31_dec_sub26_cry_out[0:0] + attribute \src "libresoc.v:109409.3-109460.6" + wire width 5 $0\dec31_dec_sub26_form[4:0] + attribute \src "libresoc.v:108265.3-108316.6" + wire width 13 $0\dec31_dec_sub26_function_unit[12:0] + attribute \src "libresoc.v:109721.3-109772.6" + wire width 3 $0\dec31_dec_sub26_in1_sel[2:0] + attribute \src "libresoc.v:109773.3-109824.6" + wire width 4 $0\dec31_dec_sub26_in2_sel[3:0] + attribute \src "libresoc.v:109825.3-109876.6" + wire width 2 $0\dec31_dec_sub26_in3_sel[1:0] + attribute \src "libresoc.v:108837.3-108888.6" + wire width 7 $0\dec31_dec_sub26_internal_op[6:0] + attribute \src "libresoc.v:109045.3-109096.6" + wire $0\dec31_dec_sub26_inv_a[0:0] + attribute \src "libresoc.v:109097.3-109148.6" + wire $0\dec31_dec_sub26_inv_out[0:0] + attribute \src "libresoc.v:109357.3-109408.6" + wire $0\dec31_dec_sub26_is_32b[0:0] + attribute \src "libresoc.v:108733.3-108784.6" + wire width 4 $0\dec31_dec_sub26_ldst_len[3:0] + attribute \src "libresoc.v:109513.3-109564.6" + wire $0\dec31_dec_sub26_lk[0:0] + attribute \src "libresoc.v:109877.3-109928.6" + wire width 2 $0\dec31_dec_sub26_out_sel[1:0] + attribute \src "libresoc.v:108889.3-108940.6" + wire width 2 $0\dec31_dec_sub26_rc_sel[1:0] + attribute \src "libresoc.v:109305.3-109356.6" + wire $0\dec31_dec_sub26_rsrv[0:0] + attribute \src "libresoc.v:109565.3-109616.6" + wire $0\dec31_dec_sub26_sgl_pipe[0:0] + attribute \src "libresoc.v:109461.3-109512.6" + wire $0\dec31_dec_sub26_sgn[0:0] + attribute \src "libresoc.v:109253.3-109304.6" + wire $0\dec31_dec_sub26_sgn_ext[0:0] + attribute \src "libresoc.v:108629.3-108680.6" + wire width 3 $0\dec31_dec_sub26_sv_cr_in[2:0] + attribute \src "libresoc.v:108681.3-108732.6" + wire width 3 $0\dec31_dec_sub26_sv_cr_out[2:0] + attribute \src "libresoc.v:108421.3-108472.6" + wire width 3 $0\dec31_dec_sub26_sv_in1[2:0] + attribute \src "libresoc.v:108473.3-108524.6" + wire width 3 $0\dec31_dec_sub26_sv_in2[2:0] + attribute \src "libresoc.v:108525.3-108576.6" + wire width 3 $0\dec31_dec_sub26_sv_in3[2:0] + attribute \src "libresoc.v:108577.3-108628.6" + wire width 3 $0\dec31_dec_sub26_sv_out[2:0] + attribute \src "libresoc.v:108785.3-108836.6" + wire width 2 $0\dec31_dec_sub26_upd[1:0] + attribute \src "libresoc.v:107931.7-107931.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:109617.3-109668.6" + wire width 2 $1\dec31_dec_sub26_SV_Etype[1:0] + attribute \src "libresoc.v:109669.3-109720.6" + wire width 2 $1\dec31_dec_sub26_SV_Ptype[1:0] + attribute \src "libresoc.v:108993.3-109044.6" + wire width 8 $1\dec31_dec_sub26_asmcode[7:0] + attribute \src "libresoc.v:109201.3-109252.6" + wire $1\dec31_dec_sub26_br[0:0] + attribute \src "libresoc.v:108317.3-108368.6" + wire width 3 $1\dec31_dec_sub26_cr_in[2:0] + attribute \src "libresoc.v:108369.3-108420.6" + wire width 3 $1\dec31_dec_sub26_cr_out[2:0] + attribute \src "libresoc.v:108941.3-108992.6" + wire width 2 $1\dec31_dec_sub26_cry_in[1:0] + attribute \src "libresoc.v:109149.3-109200.6" + wire $1\dec31_dec_sub26_cry_out[0:0] + attribute \src "libresoc.v:109409.3-109460.6" + wire width 5 $1\dec31_dec_sub26_form[4:0] + attribute \src "libresoc.v:108265.3-108316.6" + wire width 13 $1\dec31_dec_sub26_function_unit[12:0] + attribute \src "libresoc.v:109721.3-109772.6" + wire width 3 $1\dec31_dec_sub26_in1_sel[2:0] + attribute \src "libresoc.v:109773.3-109824.6" + wire width 4 $1\dec31_dec_sub26_in2_sel[3:0] + attribute \src "libresoc.v:109825.3-109876.6" + wire width 2 $1\dec31_dec_sub26_in3_sel[1:0] + attribute \src "libresoc.v:108837.3-108888.6" + wire width 7 $1\dec31_dec_sub26_internal_op[6:0] + attribute \src "libresoc.v:109045.3-109096.6" + wire $1\dec31_dec_sub26_inv_a[0:0] + attribute \src "libresoc.v:109097.3-109148.6" + wire $1\dec31_dec_sub26_inv_out[0:0] + attribute \src "libresoc.v:109357.3-109408.6" + wire $1\dec31_dec_sub26_is_32b[0:0] + attribute \src "libresoc.v:108733.3-108784.6" + wire width 4 $1\dec31_dec_sub26_ldst_len[3:0] + attribute \src "libresoc.v:109513.3-109564.6" + wire $1\dec31_dec_sub26_lk[0:0] + attribute \src "libresoc.v:109877.3-109928.6" + wire width 2 $1\dec31_dec_sub26_out_sel[1:0] + attribute \src "libresoc.v:108889.3-108940.6" + wire width 2 $1\dec31_dec_sub26_rc_sel[1:0] + attribute \src "libresoc.v:109305.3-109356.6" + wire $1\dec31_dec_sub26_rsrv[0:0] + attribute \src "libresoc.v:109565.3-109616.6" + wire $1\dec31_dec_sub26_sgl_pipe[0:0] + attribute \src "libresoc.v:109461.3-109512.6" + wire $1\dec31_dec_sub26_sgn[0:0] + attribute \src "libresoc.v:109253.3-109304.6" + wire $1\dec31_dec_sub26_sgn_ext[0:0] + attribute \src "libresoc.v:108629.3-108680.6" + wire width 3 $1\dec31_dec_sub26_sv_cr_in[2:0] + attribute \src "libresoc.v:108681.3-108732.6" + wire width 3 $1\dec31_dec_sub26_sv_cr_out[2:0] + attribute \src "libresoc.v:108421.3-108472.6" + wire width 3 $1\dec31_dec_sub26_sv_in1[2:0] + attribute \src "libresoc.v:108473.3-108524.6" + wire width 3 $1\dec31_dec_sub26_sv_in2[2:0] + attribute \src "libresoc.v:108525.3-108576.6" + wire width 3 $1\dec31_dec_sub26_sv_in3[2:0] + attribute \src "libresoc.v:108577.3-108628.6" + wire width 3 $1\dec31_dec_sub26_sv_out[2:0] + attribute \src "libresoc.v:108785.3-108836.6" + wire width 2 $1\dec31_dec_sub26_upd[1:0] + attribute \enum_base_type "SVEtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "EXTRA2" + attribute \enum_value_10 "EXTRA3" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 5 \dec31_dec_sub26_SV_Etype + attribute \enum_base_type "SVPtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "P1" + attribute \enum_value_10 "P2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 6 \dec31_dec_sub26_SV_Ptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 8 output 4 \dec31_dec_sub26_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 26 \dec31_dec_sub26_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 11 \dec31_dec_sub26_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 12 \dec31_dec_sub26_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 22 \dec31_dec_sub26_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 25 \dec31_dec_sub26_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 5 output 3 \dec31_dec_sub26_form + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 13 output 1 \dec31_dec_sub26_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 7 \dec31_dec_sub26_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 8 \dec31_dec_sub26_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 9 \dec31_dec_sub26_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 output 2 \dec31_dec_sub26_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 23 \dec31_dec_sub26_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 24 \dec31_dec_sub26_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 29 \dec31_dec_sub26_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 19 \dec31_dec_sub26_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 31 \dec31_dec_sub26_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 10 \dec31_dec_sub26_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 21 \dec31_dec_sub26_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 28 \dec31_dec_sub26_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 32 \dec31_dec_sub26_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 30 \dec31_dec_sub26_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 27 \dec31_dec_sub26_sgn_ext + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 17 \dec31_dec_sub26_sv_cr_in + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 18 \dec31_dec_sub26_sv_cr_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 13 \dec31_dec_sub26_sv_in1 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 14 \dec31_dec_sub26_sv_in2 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 15 \dec31_dec_sub26_sv_in3 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 16 \dec31_dec_sub26_sv_out + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 20 \dec31_dec_sub26_upd + attribute \src "libresoc.v:107931.7-107931.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + wire width 32 input 33 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + wire width 5 \opcode_switch + attribute \src "libresoc.v:107931.7-107931.20" + process $proc$libresoc.v:107931$4227 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:108265.3-108316.6" + process $proc$libresoc.v:108265$4195 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_function_unit[12:0] $1\dec31_dec_sub26_function_unit[12:0] + attribute \src "libresoc.v:108266.5-108266.29" + switch \initial + attribute \src "libresoc.v:108266.9-108266.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_function_unit[12:0] 13'0000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_function_unit[12:0] 13'0000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_function_unit[12:0] 13'0000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_function_unit[12:0] 13'0000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_function_unit[12:0] 13'0000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_function_unit[12:0] 13'0000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_function_unit[12:0] 13'0000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_function_unit[12:0] 13'0000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_function_unit[12:0] 13'0000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_function_unit[12:0] 13'0000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_function_unit[12:0] 13'0000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_function_unit[12:0] 13'0000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_function_unit[12:0] 13'0000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_function_unit[12:0] 13'0000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_function_unit[12:0] 13'0000000001000 + case + assign $1\dec31_dec_sub26_function_unit[12:0] 13'0000000000000 + end + sync always + update \dec31_dec_sub26_function_unit $0\dec31_dec_sub26_function_unit[12:0] + end + attribute \src "libresoc.v:108317.3-108368.6" + process $proc$libresoc.v:108317$4196 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_cr_in[2:0] $1\dec31_dec_sub26_cr_in[2:0] + attribute \src "libresoc.v:108318.5-108318.29" + switch \initial + attribute \src "libresoc.v:108318.9-108318.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub26_cr_in $0\dec31_dec_sub26_cr_in[2:0] + end + attribute \src "libresoc.v:108369.3-108420.6" + process $proc$libresoc.v:108369$4197 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_cr_out[2:0] $1\dec31_dec_sub26_cr_out[2:0] + attribute \src "libresoc.v:108370.5-108370.29" + switch \initial + attribute \src "libresoc.v:108370.9-108370.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 + case + assign $1\dec31_dec_sub26_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub26_cr_out $0\dec31_dec_sub26_cr_out[2:0] + end + attribute \src "libresoc.v:108421.3-108472.6" + process $proc$libresoc.v:108421$4198 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_sv_in1[2:0] $1\dec31_dec_sub26_sv_in1[2:0] + attribute \src "libresoc.v:108422.5-108422.29" + switch \initial + attribute \src "libresoc.v:108422.9-108422.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_sv_in1[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_sv_in1[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_sv_in1[2:0] 3'000 + case + assign $1\dec31_dec_sub26_sv_in1[2:0] 3'000 + end + sync always + update \dec31_dec_sub26_sv_in1 $0\dec31_dec_sub26_sv_in1[2:0] + end + attribute \src "libresoc.v:108473.3-108524.6" + process $proc$libresoc.v:108473$4199 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_sv_in2[2:0] $1\dec31_dec_sub26_sv_in2[2:0] + attribute \src "libresoc.v:108474.5-108474.29" + switch \initial + attribute \src "libresoc.v:108474.9-108474.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_sv_in2[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_sv_in2[2:0] 3'000 + case + assign $1\dec31_dec_sub26_sv_in2[2:0] 3'000 + end + sync always + update \dec31_dec_sub26_sv_in2 $0\dec31_dec_sub26_sv_in2[2:0] + end + attribute \src "libresoc.v:108525.3-108576.6" + process $proc$libresoc.v:108525$4200 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_sv_in3[2:0] $1\dec31_dec_sub26_sv_in3[2:0] + attribute \src "libresoc.v:108526.5-108526.29" + switch \initial + attribute \src "libresoc.v:108526.9-108526.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_sv_in3[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_sv_in3[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_sv_in3[2:0] 3'010 + case + assign $1\dec31_dec_sub26_sv_in3[2:0] 3'000 + end + sync always + update \dec31_dec_sub26_sv_in3 $0\dec31_dec_sub26_sv_in3[2:0] + end + attribute \src "libresoc.v:108577.3-108628.6" + process $proc$libresoc.v:108577$4201 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_sv_out[2:0] $1\dec31_dec_sub26_sv_out[2:0] + attribute \src "libresoc.v:108578.5-108578.29" + switch \initial + attribute \src "libresoc.v:108578.9-108578.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_sv_out[2:0] 3'001 + case + assign $1\dec31_dec_sub26_sv_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub26_sv_out $0\dec31_dec_sub26_sv_out[2:0] + end + attribute \src "libresoc.v:108629.3-108680.6" + process $proc$libresoc.v:108629$4202 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_sv_cr_in[2:0] $1\dec31_dec_sub26_sv_cr_in[2:0] + attribute \src "libresoc.v:108630.5-108630.29" + switch \initial + attribute \src "libresoc.v:108630.9-108630.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_sv_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub26_sv_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub26_sv_cr_in $0\dec31_dec_sub26_sv_cr_in[2:0] + end + attribute \src "libresoc.v:108681.3-108732.6" + process $proc$libresoc.v:108681$4203 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_sv_cr_out[2:0] $1\dec31_dec_sub26_sv_cr_out[2:0] + attribute \src "libresoc.v:108682.5-108682.29" + switch \initial + attribute \src "libresoc.v:108682.9-108682.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_sv_cr_out[2:0] 3'001 + case + assign $1\dec31_dec_sub26_sv_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub26_sv_cr_out $0\dec31_dec_sub26_sv_cr_out[2:0] + end + attribute \src "libresoc.v:108733.3-108784.6" + process $proc$libresoc.v:108733$4204 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_ldst_len[3:0] $1\dec31_dec_sub26_ldst_len[3:0] + attribute \src "libresoc.v:108734.5-108734.29" + switch \initial + attribute \src "libresoc.v:108734.9-108734.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0000 + case + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub26_ldst_len $0\dec31_dec_sub26_ldst_len[3:0] + end + attribute \src "libresoc.v:108785.3-108836.6" + process $proc$libresoc.v:108785$4205 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_upd[1:0] $1\dec31_dec_sub26_upd[1:0] + attribute \src "libresoc.v:108786.5-108786.29" + switch \initial + attribute \src "libresoc.v:108786.9-108786.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_upd[1:0] 2'00 + case + assign $1\dec31_dec_sub26_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub26_upd $0\dec31_dec_sub26_upd[1:0] + end + attribute \src "libresoc.v:108837.3-108888.6" + process $proc$libresoc.v:108837$4206 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_internal_op[6:0] $1\dec31_dec_sub26_internal_op[6:0] + attribute \src "libresoc.v:108838.5-108838.29" + switch \initial + attribute \src "libresoc.v:108838.9-108838.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0001110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0001110 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0001110 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0001110 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0011111 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0011111 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0011111 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0100000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0110110 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0110110 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0110110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0110111 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0110111 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0111101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0111101 + case + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub26_internal_op $0\dec31_dec_sub26_internal_op[6:0] + end + attribute \src "libresoc.v:108889.3-108940.6" + process $proc$libresoc.v:108889$4207 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_rc_sel[1:0] $1\dec31_dec_sub26_rc_sel[1:0] + attribute \src "libresoc.v:108890.5-108890.29" + switch \initial + attribute \src "libresoc.v:108890.9-108890.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 + case + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub26_rc_sel $0\dec31_dec_sub26_rc_sel[1:0] + end + attribute \src "libresoc.v:108941.3-108992.6" + process $proc$libresoc.v:108941$4208 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_cry_in[1:0] $1\dec31_dec_sub26_cry_in[1:0] + attribute \src "libresoc.v:108942.5-108942.29" + switch \initial + attribute \src "libresoc.v:108942.9-108942.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 + case + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub26_cry_in $0\dec31_dec_sub26_cry_in[1:0] + end + attribute \src "libresoc.v:108993.3-109044.6" + process $proc$libresoc.v:108993$4209 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_asmcode[7:0] $1\dec31_dec_sub26_asmcode[7:0] + attribute \src "libresoc.v:108994.5-108994.29" + switch \initial + attribute \src "libresoc.v:108994.9-108994.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_asmcode[7:0] 8'00100001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_asmcode[7:0] 8'00100010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_asmcode[7:0] 8'00100011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_asmcode[7:0] 8'00100100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_asmcode[7:0] 8'01000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_asmcode[7:0] 8'01000101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_asmcode[7:0] 8'01000110 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_asmcode[7:0] 8'01000111 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_asmcode[7:0] 8'10001100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_asmcode[7:0] 8'10001101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_asmcode[7:0] 8'10001110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_asmcode[7:0] 8'10001111 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_asmcode[7:0] 8'10010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_asmcode[7:0] 8'10100001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_asmcode[7:0] 8'10100010 + case + assign $1\dec31_dec_sub26_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub26_asmcode $0\dec31_dec_sub26_asmcode[7:0] + end + attribute \src "libresoc.v:109045.3-109096.6" + process $proc$libresoc.v:109045$4210 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_inv_a[0:0] $1\dec31_dec_sub26_inv_a[0:0] + attribute \src "libresoc.v:109046.5-109046.29" + switch \initial + attribute \src "libresoc.v:109046.9-109046.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 + case + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub26_inv_a $0\dec31_dec_sub26_inv_a[0:0] + end + attribute \src "libresoc.v:109097.3-109148.6" + process $proc$libresoc.v:109097$4211 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_inv_out[0:0] $1\dec31_dec_sub26_inv_out[0:0] + attribute \src "libresoc.v:109098.5-109098.29" + switch \initial + attribute \src "libresoc.v:109098.9-109098.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub26_inv_out $0\dec31_dec_sub26_inv_out[0:0] + end + attribute \src "libresoc.v:109149.3-109200.6" + process $proc$libresoc.v:109149$4212 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_cry_out[0:0] $1\dec31_dec_sub26_cry_out[0:0] + attribute \src "libresoc.v:109150.5-109150.29" + switch \initial + attribute \src "libresoc.v:109150.9-109150.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_cry_out[0:0] 1'1 + case + assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub26_cry_out $0\dec31_dec_sub26_cry_out[0:0] + end + attribute \src "libresoc.v:109201.3-109252.6" + process $proc$libresoc.v:109201$4213 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_br[0:0] $1\dec31_dec_sub26_br[0:0] + attribute \src "libresoc.v:109202.5-109202.29" + switch \initial + attribute \src "libresoc.v:109202.9-109202.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_br[0:0] 1'0 + case + assign $1\dec31_dec_sub26_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub26_br $0\dec31_dec_sub26_br[0:0] + end + attribute \src "libresoc.v:109253.3-109304.6" + process $proc$libresoc.v:109253$4214 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_sgn_ext[0:0] $1\dec31_dec_sub26_sgn_ext[0:0] + attribute \src "libresoc.v:109254.5-109254.29" + switch \initial + attribute \src "libresoc.v:109254.9-109254.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub26_sgn_ext $0\dec31_dec_sub26_sgn_ext[0:0] + end + attribute \src "libresoc.v:109305.3-109356.6" + process $proc$libresoc.v:109305$4215 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_rsrv[0:0] $1\dec31_dec_sub26_rsrv[0:0] + attribute \src "libresoc.v:109306.5-109306.29" + switch \initial + attribute \src "libresoc.v:109306.9-109306.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub26_rsrv $0\dec31_dec_sub26_rsrv[0:0] + end + attribute \src "libresoc.v:109357.3-109408.6" + process $proc$libresoc.v:109357$4216 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_is_32b[0:0] $1\dec31_dec_sub26_is_32b[0:0] + attribute \src "libresoc.v:109358.5-109358.29" + switch \initial + attribute \src "libresoc.v:109358.9-109358.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_is_32b[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + case + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub26_is_32b $0\dec31_dec_sub26_is_32b[0:0] + end + attribute \src "libresoc.v:109409.3-109460.6" + process $proc$libresoc.v:109409$4217 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_form[4:0] $1\dec31_dec_sub26_form[4:0] + attribute \src "libresoc.v:109410.5-109410.29" + switch \initial + attribute \src "libresoc.v:109410.9-109410.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_form[4:0] 5'10000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_form[4:0] 5'10000 + case + assign $1\dec31_dec_sub26_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub26_form $0\dec31_dec_sub26_form[4:0] + end + attribute \src "libresoc.v:109461.3-109512.6" + process $proc$libresoc.v:109461$4218 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_sgn[0:0] $1\dec31_dec_sub26_sgn[0:0] + attribute \src "libresoc.v:109462.5-109462.29" + switch \initial + attribute \src "libresoc.v:109462.9-109462.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_sgn[0:0] 1'1 + case + assign $1\dec31_dec_sub26_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub26_sgn $0\dec31_dec_sub26_sgn[0:0] + end + attribute \src "libresoc.v:109513.3-109564.6" + process $proc$libresoc.v:109513$4219 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_lk[0:0] $1\dec31_dec_sub26_lk[0:0] + attribute \src "libresoc.v:109514.5-109514.29" + switch \initial + attribute \src "libresoc.v:109514.9-109514.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub26_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub26_lk $0\dec31_dec_sub26_lk[0:0] + end + attribute \src "libresoc.v:109565.3-109616.6" + process $proc$libresoc.v:109565$4220 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_sgl_pipe[0:0] $1\dec31_dec_sub26_sgl_pipe[0:0] + attribute \src "libresoc.v:109566.5-109566.29" + switch \initial + attribute \src "libresoc.v:109566.9-109566.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + case + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub26_sgl_pipe $0\dec31_dec_sub26_sgl_pipe[0:0] + end + attribute \src "libresoc.v:109617.3-109668.6" + process $proc$libresoc.v:109617$4221 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_SV_Etype[1:0] $1\dec31_dec_sub26_SV_Etype[1:0] + attribute \src "libresoc.v:109618.5-109618.29" + switch \initial + attribute \src "libresoc.v:109618.9-109618.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_SV_Etype[1:0] 2'10 + case + assign $1\dec31_dec_sub26_SV_Etype[1:0] 2'00 + end + sync always + update \dec31_dec_sub26_SV_Etype $0\dec31_dec_sub26_SV_Etype[1:0] + end + attribute \src "libresoc.v:109669.3-109720.6" + process $proc$libresoc.v:109669$4222 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_SV_Ptype[1:0] $1\dec31_dec_sub26_SV_Ptype[1:0] + attribute \src "libresoc.v:109670.5-109670.29" + switch \initial + attribute \src "libresoc.v:109670.9-109670.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_SV_Ptype[1:0] 2'10 + case + assign $1\dec31_dec_sub26_SV_Ptype[1:0] 2'00 + end + sync always + update \dec31_dec_sub26_SV_Ptype $0\dec31_dec_sub26_SV_Ptype[1:0] + end + attribute \src "libresoc.v:109721.3-109772.6" + process $proc$libresoc.v:109721$4223 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_in1_sel[2:0] $1\dec31_dec_sub26_in1_sel[2:0] + attribute \src "libresoc.v:109722.5-109722.29" + switch \initial + attribute \src "libresoc.v:109722.9-109722.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'000 + case + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub26_in1_sel $0\dec31_dec_sub26_in1_sel[2:0] + end + attribute \src "libresoc.v:109773.3-109824.6" + process $proc$libresoc.v:109773$4224 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_in2_sel[3:0] $1\dec31_dec_sub26_in2_sel[3:0] + attribute \src "libresoc.v:109774.5-109774.29" + switch \initial + attribute \src "libresoc.v:109774.9-109774.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'1010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'1010 + case + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub26_in2_sel $0\dec31_dec_sub26_in2_sel[3:0] + end + attribute \src "libresoc.v:109825.3-109876.6" + process $proc$libresoc.v:109825$4225 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_in3_sel[1:0] $1\dec31_dec_sub26_in3_sel[1:0] + attribute \src "libresoc.v:109826.5-109826.29" + switch \initial + attribute \src "libresoc.v:109826.9-109826.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'01 + case + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub26_in3_sel $0\dec31_dec_sub26_in3_sel[1:0] + end + attribute \src "libresoc.v:109877.3-109928.6" + process $proc$libresoc.v:109877$4226 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_out_sel[1:0] $1\dec31_dec_sub26_out_sel[1:0] + attribute \src "libresoc.v:109878.5-109878.29" + switch \initial + attribute \src "libresoc.v:109878.9-109878.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 + case + assign $1\dec31_dec_sub26_out_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub26_out_sel $0\dec31_dec_sub26_out_sel[1:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:109934.1-110878.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub27" +attribute \generator "nMigen" +module \dec31_dec_sub27 + attribute \src "libresoc.v:110763.3-110781.6" + wire width 2 $0\dec31_dec_sub27_SV_Etype[1:0] + attribute \src "libresoc.v:110782.3-110800.6" + wire width 2 $0\dec31_dec_sub27_SV_Ptype[1:0] + attribute \src "libresoc.v:110535.3-110553.6" + wire width 8 $0\dec31_dec_sub27_asmcode[7:0] + attribute \src "libresoc.v:110611.3-110629.6" + wire $0\dec31_dec_sub27_br[0:0] + attribute \src "libresoc.v:110288.3-110306.6" + wire width 3 $0\dec31_dec_sub27_cr_in[2:0] + attribute \src "libresoc.v:110307.3-110325.6" + wire width 3 $0\dec31_dec_sub27_cr_out[2:0] + attribute \src "libresoc.v:110516.3-110534.6" + wire width 2 $0\dec31_dec_sub27_cry_in[1:0] + attribute \src "libresoc.v:110592.3-110610.6" + wire $0\dec31_dec_sub27_cry_out[0:0] + attribute \src "libresoc.v:110687.3-110705.6" + wire width 5 $0\dec31_dec_sub27_form[4:0] + attribute \src "libresoc.v:110269.3-110287.6" + wire width 13 $0\dec31_dec_sub27_function_unit[12:0] + attribute \src "libresoc.v:110801.3-110819.6" + wire width 3 $0\dec31_dec_sub27_in1_sel[2:0] + attribute \src "libresoc.v:110820.3-110838.6" + wire width 4 $0\dec31_dec_sub27_in2_sel[3:0] + attribute \src "libresoc.v:110839.3-110857.6" + wire width 2 $0\dec31_dec_sub27_in3_sel[1:0] + attribute \src "libresoc.v:110478.3-110496.6" + wire width 7 $0\dec31_dec_sub27_internal_op[6:0] + attribute \src "libresoc.v:110554.3-110572.6" + wire $0\dec31_dec_sub27_inv_a[0:0] + attribute \src "libresoc.v:110573.3-110591.6" + wire $0\dec31_dec_sub27_inv_out[0:0] + attribute \src "libresoc.v:110668.3-110686.6" + wire $0\dec31_dec_sub27_is_32b[0:0] + attribute \src "libresoc.v:110440.3-110458.6" + wire width 4 $0\dec31_dec_sub27_ldst_len[3:0] + attribute \src "libresoc.v:110725.3-110743.6" + wire $0\dec31_dec_sub27_lk[0:0] + attribute \src "libresoc.v:110858.3-110876.6" + wire width 2 $0\dec31_dec_sub27_out_sel[1:0] + attribute \src "libresoc.v:110497.3-110515.6" + wire width 2 $0\dec31_dec_sub27_rc_sel[1:0] + attribute \src "libresoc.v:110649.3-110667.6" + wire $0\dec31_dec_sub27_rsrv[0:0] + attribute \src "libresoc.v:110744.3-110762.6" + wire $0\dec31_dec_sub27_sgl_pipe[0:0] + attribute \src "libresoc.v:110706.3-110724.6" + wire $0\dec31_dec_sub27_sgn[0:0] + attribute \src "libresoc.v:110630.3-110648.6" + wire $0\dec31_dec_sub27_sgn_ext[0:0] + attribute \src "libresoc.v:110402.3-110420.6" + wire width 3 $0\dec31_dec_sub27_sv_cr_in[2:0] + attribute \src "libresoc.v:110421.3-110439.6" + wire width 3 $0\dec31_dec_sub27_sv_cr_out[2:0] + attribute \src "libresoc.v:110326.3-110344.6" + wire width 3 $0\dec31_dec_sub27_sv_in1[2:0] + attribute \src "libresoc.v:110345.3-110363.6" + wire width 3 $0\dec31_dec_sub27_sv_in2[2:0] + attribute \src "libresoc.v:110364.3-110382.6" + wire width 3 $0\dec31_dec_sub27_sv_in3[2:0] + attribute \src "libresoc.v:110383.3-110401.6" + wire width 3 $0\dec31_dec_sub27_sv_out[2:0] + attribute \src "libresoc.v:110459.3-110477.6" + wire width 2 $0\dec31_dec_sub27_upd[1:0] + attribute \src "libresoc.v:109935.7-109935.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:110763.3-110781.6" + wire width 2 $1\dec31_dec_sub27_SV_Etype[1:0] + attribute \src "libresoc.v:110782.3-110800.6" + wire width 2 $1\dec31_dec_sub27_SV_Ptype[1:0] + attribute \src "libresoc.v:110535.3-110553.6" + wire width 8 $1\dec31_dec_sub27_asmcode[7:0] + attribute \src "libresoc.v:110611.3-110629.6" + wire $1\dec31_dec_sub27_br[0:0] + attribute \src "libresoc.v:110288.3-110306.6" + wire width 3 $1\dec31_dec_sub27_cr_in[2:0] + attribute \src "libresoc.v:110307.3-110325.6" + wire width 3 $1\dec31_dec_sub27_cr_out[2:0] + attribute \src "libresoc.v:110516.3-110534.6" + wire width 2 $1\dec31_dec_sub27_cry_in[1:0] + attribute \src "libresoc.v:110592.3-110610.6" + wire $1\dec31_dec_sub27_cry_out[0:0] + attribute \src "libresoc.v:110687.3-110705.6" + wire width 5 $1\dec31_dec_sub27_form[4:0] + attribute \src "libresoc.v:110269.3-110287.6" + wire width 13 $1\dec31_dec_sub27_function_unit[12:0] + attribute \src "libresoc.v:110801.3-110819.6" + wire width 3 $1\dec31_dec_sub27_in1_sel[2:0] + attribute \src "libresoc.v:110820.3-110838.6" + wire width 4 $1\dec31_dec_sub27_in2_sel[3:0] + attribute \src "libresoc.v:110839.3-110857.6" + wire width 2 $1\dec31_dec_sub27_in3_sel[1:0] + attribute \src "libresoc.v:110478.3-110496.6" + wire width 7 $1\dec31_dec_sub27_internal_op[6:0] + attribute \src "libresoc.v:110554.3-110572.6" + wire $1\dec31_dec_sub27_inv_a[0:0] + attribute \src "libresoc.v:110573.3-110591.6" + wire $1\dec31_dec_sub27_inv_out[0:0] + attribute \src "libresoc.v:110668.3-110686.6" + wire $1\dec31_dec_sub27_is_32b[0:0] + attribute \src "libresoc.v:110440.3-110458.6" + wire width 4 $1\dec31_dec_sub27_ldst_len[3:0] + attribute \src "libresoc.v:110725.3-110743.6" + wire $1\dec31_dec_sub27_lk[0:0] + attribute \src "libresoc.v:110858.3-110876.6" + wire width 2 $1\dec31_dec_sub27_out_sel[1:0] + attribute \src "libresoc.v:110497.3-110515.6" + wire width 2 $1\dec31_dec_sub27_rc_sel[1:0] + attribute \src "libresoc.v:110649.3-110667.6" + wire $1\dec31_dec_sub27_rsrv[0:0] + attribute \src "libresoc.v:110744.3-110762.6" + wire $1\dec31_dec_sub27_sgl_pipe[0:0] + attribute \src "libresoc.v:110706.3-110724.6" + wire $1\dec31_dec_sub27_sgn[0:0] + attribute \src "libresoc.v:110630.3-110648.6" + wire $1\dec31_dec_sub27_sgn_ext[0:0] + attribute \src "libresoc.v:110402.3-110420.6" + wire width 3 $1\dec31_dec_sub27_sv_cr_in[2:0] + attribute \src "libresoc.v:110421.3-110439.6" + wire width 3 $1\dec31_dec_sub27_sv_cr_out[2:0] + attribute \src "libresoc.v:110326.3-110344.6" + wire width 3 $1\dec31_dec_sub27_sv_in1[2:0] + attribute \src "libresoc.v:110345.3-110363.6" + wire width 3 $1\dec31_dec_sub27_sv_in2[2:0] + attribute \src "libresoc.v:110364.3-110382.6" + wire width 3 $1\dec31_dec_sub27_sv_in3[2:0] + attribute \src "libresoc.v:110383.3-110401.6" + wire width 3 $1\dec31_dec_sub27_sv_out[2:0] + attribute \src "libresoc.v:110459.3-110477.6" + wire width 2 $1\dec31_dec_sub27_upd[1:0] + attribute \enum_base_type "SVEtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "EXTRA2" + attribute \enum_value_10 "EXTRA3" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 5 \dec31_dec_sub27_SV_Etype + attribute \enum_base_type "SVPtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "P1" + attribute \enum_value_10 "P2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 6 \dec31_dec_sub27_SV_Ptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 8 output 4 \dec31_dec_sub27_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 26 \dec31_dec_sub27_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 11 \dec31_dec_sub27_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 12 \dec31_dec_sub27_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 22 \dec31_dec_sub27_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 25 \dec31_dec_sub27_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 5 output 3 \dec31_dec_sub27_form + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 13 output 1 \dec31_dec_sub27_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 7 \dec31_dec_sub27_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 8 \dec31_dec_sub27_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 9 \dec31_dec_sub27_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 output 2 \dec31_dec_sub27_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 23 \dec31_dec_sub27_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 24 \dec31_dec_sub27_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 29 \dec31_dec_sub27_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 19 \dec31_dec_sub27_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 31 \dec31_dec_sub27_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 10 \dec31_dec_sub27_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 21 \dec31_dec_sub27_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 28 \dec31_dec_sub27_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 32 \dec31_dec_sub27_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 30 \dec31_dec_sub27_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 27 \dec31_dec_sub27_sgn_ext + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 17 \dec31_dec_sub27_sv_cr_in + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 18 \dec31_dec_sub27_sv_cr_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 13 \dec31_dec_sub27_sv_in1 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 14 \dec31_dec_sub27_sv_in2 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 15 \dec31_dec_sub27_sv_in3 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 16 \dec31_dec_sub27_sv_out + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 20 \dec31_dec_sub27_upd + attribute \src "libresoc.v:109935.7-109935.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + wire width 32 input 33 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + wire width 5 \opcode_switch + attribute \src "libresoc.v:109935.7-109935.20" + process $proc$libresoc.v:109935$4260 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:110269.3-110287.6" + process $proc$libresoc.v:110269$4228 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_function_unit[12:0] $1\dec31_dec_sub27_function_unit[12:0] + attribute \src "libresoc.v:110270.5-110270.29" + switch \initial + attribute \src "libresoc.v:110270.9-110270.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_function_unit[12:0] 13'0000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_function_unit[12:0] 13'0000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_function_unit[12:0] 13'0000000001000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_function_unit[12:0] 13'0000000001000 + case + assign $1\dec31_dec_sub27_function_unit[12:0] 13'0000000000000 + end + sync always + update \dec31_dec_sub27_function_unit $0\dec31_dec_sub27_function_unit[12:0] + end + attribute \src "libresoc.v:110288.3-110306.6" + process $proc$libresoc.v:110288$4229 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_cr_in[2:0] $1\dec31_dec_sub27_cr_in[2:0] + attribute \src "libresoc.v:110289.5-110289.29" + switch \initial + attribute \src "libresoc.v:110289.9-110289.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub27_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub27_cr_in $0\dec31_dec_sub27_cr_in[2:0] + end + attribute \src "libresoc.v:110307.3-110325.6" + process $proc$libresoc.v:110307$4230 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_cr_out[2:0] $1\dec31_dec_sub27_cr_out[2:0] + attribute \src "libresoc.v:110308.5-110308.29" + switch \initial + attribute \src "libresoc.v:110308.9-110308.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_cr_out[2:0] 3'001 + case + assign $1\dec31_dec_sub27_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub27_cr_out $0\dec31_dec_sub27_cr_out[2:0] + end + attribute \src "libresoc.v:110326.3-110344.6" + process $proc$libresoc.v:110326$4231 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_sv_in1[2:0] $1\dec31_dec_sub27_sv_in1[2:0] + attribute \src "libresoc.v:110327.5-110327.29" + switch \initial + attribute \src "libresoc.v:110327.9-110327.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_sv_in1[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_sv_in1[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_sv_in1[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_sv_in1[2:0] 3'000 + case + assign $1\dec31_dec_sub27_sv_in1[2:0] 3'000 + end + sync always + update \dec31_dec_sub27_sv_in1 $0\dec31_dec_sub27_sv_in1[2:0] + end + attribute \src "libresoc.v:110345.3-110363.6" + process $proc$libresoc.v:110345$4232 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_sv_in2[2:0] $1\dec31_dec_sub27_sv_in2[2:0] + attribute \src "libresoc.v:110346.5-110346.29" + switch \initial + attribute \src "libresoc.v:110346.9-110346.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_sv_in2[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_sv_in2[2:0] 3'010 + case + assign $1\dec31_dec_sub27_sv_in2[2:0] 3'000 + end + sync always + update \dec31_dec_sub27_sv_in2 $0\dec31_dec_sub27_sv_in2[2:0] + end + attribute \src "libresoc.v:110364.3-110382.6" + process $proc$libresoc.v:110364$4233 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_sv_in3[2:0] $1\dec31_dec_sub27_sv_in3[2:0] + attribute \src "libresoc.v:110365.5-110365.29" + switch \initial + attribute \src "libresoc.v:110365.9-110365.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_sv_in3[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_sv_in3[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_sv_in3[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_sv_in3[2:0] 3'011 + case + assign $1\dec31_dec_sub27_sv_in3[2:0] 3'000 + end + sync always + update \dec31_dec_sub27_sv_in3 $0\dec31_dec_sub27_sv_in3[2:0] + end + attribute \src "libresoc.v:110383.3-110401.6" + process $proc$libresoc.v:110383$4234 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_sv_out[2:0] $1\dec31_dec_sub27_sv_out[2:0] + attribute \src "libresoc.v:110384.5-110384.29" + switch \initial + attribute \src "libresoc.v:110384.9-110384.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_sv_out[2:0] 3'001 + case + assign $1\dec31_dec_sub27_sv_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub27_sv_out $0\dec31_dec_sub27_sv_out[2:0] + end + attribute \src "libresoc.v:110402.3-110420.6" + process $proc$libresoc.v:110402$4235 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_sv_cr_in[2:0] $1\dec31_dec_sub27_sv_cr_in[2:0] + attribute \src "libresoc.v:110403.5-110403.29" + switch \initial + attribute \src "libresoc.v:110403.9-110403.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_sv_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub27_sv_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub27_sv_cr_in $0\dec31_dec_sub27_sv_cr_in[2:0] + end + attribute \src "libresoc.v:110421.3-110439.6" + process $proc$libresoc.v:110421$4236 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_sv_cr_out[2:0] $1\dec31_dec_sub27_sv_cr_out[2:0] + attribute \src "libresoc.v:110422.5-110422.29" + switch \initial + attribute \src "libresoc.v:110422.9-110422.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_sv_cr_out[2:0] 3'001 + case + assign $1\dec31_dec_sub27_sv_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub27_sv_cr_out $0\dec31_dec_sub27_sv_cr_out[2:0] + end + attribute \src "libresoc.v:110440.3-110458.6" + process $proc$libresoc.v:110440$4237 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_ldst_len[3:0] $1\dec31_dec_sub27_ldst_len[3:0] + attribute \src "libresoc.v:110441.5-110441.29" + switch \initial + attribute \src "libresoc.v:110441.9-110441.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_ldst_len[3:0] 4'0000 + case + assign $1\dec31_dec_sub27_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub27_ldst_len $0\dec31_dec_sub27_ldst_len[3:0] + end + attribute \src "libresoc.v:110459.3-110477.6" + process $proc$libresoc.v:110459$4238 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_upd[1:0] $1\dec31_dec_sub27_upd[1:0] + attribute \src "libresoc.v:110460.5-110460.29" + switch \initial + attribute \src "libresoc.v:110460.9-110460.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_upd[1:0] 2'00 + case + assign $1\dec31_dec_sub27_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub27_upd $0\dec31_dec_sub27_upd[1:0] + end + attribute \src "libresoc.v:110478.3-110496.6" + process $proc$libresoc.v:110478$4239 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_internal_op[6:0] $1\dec31_dec_sub27_internal_op[6:0] + attribute \src "libresoc.v:110479.5-110479.29" + switch \initial + attribute \src "libresoc.v:110479.9-110479.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_internal_op[6:0] 7'0100000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_internal_op[6:0] 7'0111100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_internal_op[6:0] 7'0111101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_internal_op[6:0] 7'0111101 + case + assign $1\dec31_dec_sub27_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub27_internal_op $0\dec31_dec_sub27_internal_op[6:0] + end + attribute \src "libresoc.v:110497.3-110515.6" + process $proc$libresoc.v:110497$4240 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_rc_sel[1:0] $1\dec31_dec_sub27_rc_sel[1:0] + attribute \src "libresoc.v:110498.5-110498.29" + switch \initial + attribute \src "libresoc.v:110498.9-110498.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_rc_sel[1:0] 2'10 + case + assign $1\dec31_dec_sub27_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub27_rc_sel $0\dec31_dec_sub27_rc_sel[1:0] + end + attribute \src "libresoc.v:110516.3-110534.6" + process $proc$libresoc.v:110516$4241 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_cry_in[1:0] $1\dec31_dec_sub27_cry_in[1:0] + attribute \src "libresoc.v:110517.5-110517.29" + switch \initial + attribute \src "libresoc.v:110517.9-110517.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_cry_in[1:0] 2'00 + case + assign $1\dec31_dec_sub27_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub27_cry_in $0\dec31_dec_sub27_cry_in[1:0] + end + attribute \src "libresoc.v:110535.3-110553.6" + process $proc$libresoc.v:110535$4242 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_asmcode[7:0] $1\dec31_dec_sub27_asmcode[7:0] + attribute \src "libresoc.v:110536.5-110536.29" + switch \initial + attribute \src "libresoc.v:110536.9-110536.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_asmcode[7:0] 8'01000111 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_asmcode[7:0] 8'10011111 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_asmcode[7:0] 8'10100010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_asmcode[7:0] 8'10100101 + case + assign $1\dec31_dec_sub27_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub27_asmcode $0\dec31_dec_sub27_asmcode[7:0] + end + attribute \src "libresoc.v:110554.3-110572.6" + process $proc$libresoc.v:110554$4243 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_inv_a[0:0] $1\dec31_dec_sub27_inv_a[0:0] + attribute \src "libresoc.v:110555.5-110555.29" + switch \initial + attribute \src "libresoc.v:110555.9-110555.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_inv_a[0:0] 1'0 + case + assign $1\dec31_dec_sub27_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub27_inv_a $0\dec31_dec_sub27_inv_a[0:0] + end + attribute \src "libresoc.v:110573.3-110591.6" + process $proc$libresoc.v:110573$4244 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_inv_out[0:0] $1\dec31_dec_sub27_inv_out[0:0] + attribute \src "libresoc.v:110574.5-110574.29" + switch \initial + attribute \src "libresoc.v:110574.9-110574.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub27_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub27_inv_out $0\dec31_dec_sub27_inv_out[0:0] + end + attribute \src "libresoc.v:110592.3-110610.6" + process $proc$libresoc.v:110592$4245 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_cry_out[0:0] $1\dec31_dec_sub27_cry_out[0:0] + attribute \src "libresoc.v:110593.5-110593.29" + switch \initial + attribute \src "libresoc.v:110593.9-110593.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_cry_out[0:0] 1'0 + case + assign $1\dec31_dec_sub27_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub27_cry_out $0\dec31_dec_sub27_cry_out[0:0] + end + attribute \src "libresoc.v:110611.3-110629.6" + process $proc$libresoc.v:110611$4246 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_br[0:0] $1\dec31_dec_sub27_br[0:0] + attribute \src "libresoc.v:110612.5-110612.29" + switch \initial + attribute \src "libresoc.v:110612.9-110612.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_br[0:0] 1'0 + case + assign $1\dec31_dec_sub27_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub27_br $0\dec31_dec_sub27_br[0:0] + end + attribute \src "libresoc.v:110630.3-110648.6" + process $proc$libresoc.v:110630$4247 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_sgn_ext[0:0] $1\dec31_dec_sub27_sgn_ext[0:0] + attribute \src "libresoc.v:110631.5-110631.29" + switch \initial + attribute \src "libresoc.v:110631.9-110631.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub27_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub27_sgn_ext $0\dec31_dec_sub27_sgn_ext[0:0] + end + attribute \src "libresoc.v:110649.3-110667.6" + process $proc$libresoc.v:110649$4248 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_rsrv[0:0] $1\dec31_dec_sub27_rsrv[0:0] + attribute \src "libresoc.v:110650.5-110650.29" + switch \initial + attribute \src "libresoc.v:110650.9-110650.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub27_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub27_rsrv $0\dec31_dec_sub27_rsrv[0:0] + end + attribute \src "libresoc.v:110668.3-110686.6" + process $proc$libresoc.v:110668$4249 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_is_32b[0:0] $1\dec31_dec_sub27_is_32b[0:0] + attribute \src "libresoc.v:110669.5-110669.29" + switch \initial + attribute \src "libresoc.v:110669.9-110669.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_is_32b[0:0] 1'0 + case + assign $1\dec31_dec_sub27_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub27_is_32b $0\dec31_dec_sub27_is_32b[0:0] + end + attribute \src "libresoc.v:110687.3-110705.6" + process $proc$libresoc.v:110687$4250 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_form[4:0] $1\dec31_dec_sub27_form[4:0] + attribute \src "libresoc.v:110688.5-110688.29" + switch \initial + attribute \src "libresoc.v:110688.9-110688.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_form[4:0] 5'10000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_form[4:0] 5'10000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_form[4:0] 5'01000 + case + assign $1\dec31_dec_sub27_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub27_form $0\dec31_dec_sub27_form[4:0] + end + attribute \src "libresoc.v:110706.3-110724.6" + process $proc$libresoc.v:110706$4251 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_sgn[0:0] $1\dec31_dec_sub27_sgn[0:0] + attribute \src "libresoc.v:110707.5-110707.29" + switch \initial + attribute \src "libresoc.v:110707.9-110707.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_sgn[0:0] 1'0 + case + assign $1\dec31_dec_sub27_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub27_sgn $0\dec31_dec_sub27_sgn[0:0] + end + attribute \src "libresoc.v:110725.3-110743.6" + process $proc$libresoc.v:110725$4252 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_lk[0:0] $1\dec31_dec_sub27_lk[0:0] + attribute \src "libresoc.v:110726.5-110726.29" + switch \initial + attribute \src "libresoc.v:110726.9-110726.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub27_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub27_lk $0\dec31_dec_sub27_lk[0:0] + end + attribute \src "libresoc.v:110744.3-110762.6" + process $proc$libresoc.v:110744$4253 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_sgl_pipe[0:0] $1\dec31_dec_sub27_sgl_pipe[0:0] + attribute \src "libresoc.v:110745.5-110745.29" + switch \initial + attribute \src "libresoc.v:110745.9-110745.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_sgl_pipe[0:0] 1'0 + case + assign $1\dec31_dec_sub27_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub27_sgl_pipe $0\dec31_dec_sub27_sgl_pipe[0:0] + end + attribute \src "libresoc.v:110763.3-110781.6" + process $proc$libresoc.v:110763$4254 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_SV_Etype[1:0] $1\dec31_dec_sub27_SV_Etype[1:0] + attribute \src "libresoc.v:110764.5-110764.29" + switch \initial + attribute \src "libresoc.v:110764.9-110764.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_SV_Etype[1:0] 2'10 + case + assign $1\dec31_dec_sub27_SV_Etype[1:0] 2'00 + end + sync always + update \dec31_dec_sub27_SV_Etype $0\dec31_dec_sub27_SV_Etype[1:0] + end + attribute \src "libresoc.v:110782.3-110800.6" + process $proc$libresoc.v:110782$4255 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_SV_Ptype[1:0] $1\dec31_dec_sub27_SV_Ptype[1:0] + attribute \src "libresoc.v:110783.5-110783.29" + switch \initial + attribute \src "libresoc.v:110783.9-110783.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_SV_Ptype[1:0] 2'01 + case + assign $1\dec31_dec_sub27_SV_Ptype[1:0] 2'00 + end + sync always + update \dec31_dec_sub27_SV_Ptype $0\dec31_dec_sub27_SV_Ptype[1:0] + end + attribute \src "libresoc.v:110801.3-110819.6" + process $proc$libresoc.v:110801$4256 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_in1_sel[2:0] $1\dec31_dec_sub27_in1_sel[2:0] + attribute \src "libresoc.v:110802.5-110802.29" + switch \initial + attribute \src "libresoc.v:110802.9-110802.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_in1_sel[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_in1_sel[2:0] 3'000 + case + assign $1\dec31_dec_sub27_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub27_in1_sel $0\dec31_dec_sub27_in1_sel[2:0] + end + attribute \src "libresoc.v:110820.3-110838.6" + process $proc$libresoc.v:110820$4257 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_in2_sel[3:0] $1\dec31_dec_sub27_in2_sel[3:0] + attribute \src "libresoc.v:110821.5-110821.29" + switch \initial + attribute \src "libresoc.v:110821.9-110821.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_in2_sel[3:0] 4'1010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_in2_sel[3:0] 4'1010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_in2_sel[3:0] 4'0001 + case + assign $1\dec31_dec_sub27_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub27_in2_sel $0\dec31_dec_sub27_in2_sel[3:0] + end + attribute \src "libresoc.v:110839.3-110857.6" + process $proc$libresoc.v:110839$4258 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_in3_sel[1:0] $1\dec31_dec_sub27_in3_sel[1:0] + attribute \src "libresoc.v:110840.5-110840.29" + switch \initial + attribute \src "libresoc.v:110840.9-110840.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_in3_sel[1:0] 2'01 + case + assign $1\dec31_dec_sub27_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub27_in3_sel $0\dec31_dec_sub27_in3_sel[1:0] + end + attribute \src "libresoc.v:110858.3-110876.6" + process $proc$libresoc.v:110858$4259 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_out_sel[1:0] $1\dec31_dec_sub27_out_sel[1:0] + attribute \src "libresoc.v:110859.5-110859.29" + switch \initial + attribute \src "libresoc.v:110859.9-110859.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_out_sel[1:0] 2'10 + case + assign $1\dec31_dec_sub27_out_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub27_out_sel $0\dec31_dec_sub27_out_sel[1:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:110882.1-112402.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub28" +attribute \generator "nMigen" +module \dec31_dec_sub28 + attribute \src "libresoc.v:112179.3-112215.6" + wire width 2 $0\dec31_dec_sub28_SV_Etype[1:0] + attribute \src "libresoc.v:112216.3-112252.6" + wire width 2 $0\dec31_dec_sub28_SV_Ptype[1:0] + attribute \src "libresoc.v:111735.3-111771.6" + wire width 8 $0\dec31_dec_sub28_asmcode[7:0] + attribute \src "libresoc.v:111883.3-111919.6" + wire $0\dec31_dec_sub28_br[0:0] + attribute \src "libresoc.v:111254.3-111290.6" + wire width 3 $0\dec31_dec_sub28_cr_in[2:0] + attribute \src "libresoc.v:111291.3-111327.6" + wire width 3 $0\dec31_dec_sub28_cr_out[2:0] + attribute \src "libresoc.v:111698.3-111734.6" + wire width 2 $0\dec31_dec_sub28_cry_in[1:0] + attribute \src "libresoc.v:111846.3-111882.6" + wire $0\dec31_dec_sub28_cry_out[0:0] + attribute \src "libresoc.v:112031.3-112067.6" + wire width 5 $0\dec31_dec_sub28_form[4:0] + attribute \src "libresoc.v:111217.3-111253.6" + wire width 13 $0\dec31_dec_sub28_function_unit[12:0] + attribute \src "libresoc.v:112253.3-112289.6" + wire width 3 $0\dec31_dec_sub28_in1_sel[2:0] + attribute \src "libresoc.v:112290.3-112326.6" + wire width 4 $0\dec31_dec_sub28_in2_sel[3:0] + attribute \src "libresoc.v:112327.3-112363.6" + wire width 2 $0\dec31_dec_sub28_in3_sel[1:0] + attribute \src "libresoc.v:111624.3-111660.6" + wire width 7 $0\dec31_dec_sub28_internal_op[6:0] + attribute \src "libresoc.v:111772.3-111808.6" + wire $0\dec31_dec_sub28_inv_a[0:0] + attribute \src "libresoc.v:111809.3-111845.6" + wire $0\dec31_dec_sub28_inv_out[0:0] + attribute \src "libresoc.v:111994.3-112030.6" + wire $0\dec31_dec_sub28_is_32b[0:0] + attribute \src "libresoc.v:111550.3-111586.6" + wire width 4 $0\dec31_dec_sub28_ldst_len[3:0] + attribute \src "libresoc.v:112105.3-112141.6" + wire $0\dec31_dec_sub28_lk[0:0] + attribute \src "libresoc.v:112364.3-112400.6" + wire width 2 $0\dec31_dec_sub28_out_sel[1:0] + attribute \src "libresoc.v:111661.3-111697.6" + wire width 2 $0\dec31_dec_sub28_rc_sel[1:0] + attribute \src "libresoc.v:111957.3-111993.6" + wire $0\dec31_dec_sub28_rsrv[0:0] + attribute \src "libresoc.v:112142.3-112178.6" + wire $0\dec31_dec_sub28_sgl_pipe[0:0] + attribute \src "libresoc.v:112068.3-112104.6" + wire $0\dec31_dec_sub28_sgn[0:0] + attribute \src "libresoc.v:111920.3-111956.6" + wire $0\dec31_dec_sub28_sgn_ext[0:0] + attribute \src "libresoc.v:111476.3-111512.6" + wire width 3 $0\dec31_dec_sub28_sv_cr_in[2:0] + attribute \src "libresoc.v:111513.3-111549.6" + wire width 3 $0\dec31_dec_sub28_sv_cr_out[2:0] + attribute \src "libresoc.v:111328.3-111364.6" + wire width 3 $0\dec31_dec_sub28_sv_in1[2:0] + attribute \src "libresoc.v:111365.3-111401.6" + wire width 3 $0\dec31_dec_sub28_sv_in2[2:0] + attribute \src "libresoc.v:111402.3-111438.6" + wire width 3 $0\dec31_dec_sub28_sv_in3[2:0] + attribute \src "libresoc.v:111439.3-111475.6" + wire width 3 $0\dec31_dec_sub28_sv_out[2:0] + attribute \src "libresoc.v:111587.3-111623.6" + wire width 2 $0\dec31_dec_sub28_upd[1:0] + attribute \src "libresoc.v:110883.7-110883.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:112179.3-112215.6" + wire width 2 $1\dec31_dec_sub28_SV_Etype[1:0] + attribute \src "libresoc.v:112216.3-112252.6" + wire width 2 $1\dec31_dec_sub28_SV_Ptype[1:0] + attribute \src "libresoc.v:111735.3-111771.6" + wire width 8 $1\dec31_dec_sub28_asmcode[7:0] + attribute \src "libresoc.v:111883.3-111919.6" + wire $1\dec31_dec_sub28_br[0:0] + attribute \src "libresoc.v:111254.3-111290.6" + wire width 3 $1\dec31_dec_sub28_cr_in[2:0] + attribute \src "libresoc.v:111291.3-111327.6" + wire width 3 $1\dec31_dec_sub28_cr_out[2:0] + attribute \src "libresoc.v:111698.3-111734.6" + wire width 2 $1\dec31_dec_sub28_cry_in[1:0] + attribute \src "libresoc.v:111846.3-111882.6" + wire $1\dec31_dec_sub28_cry_out[0:0] + attribute \src "libresoc.v:112031.3-112067.6" + wire width 5 $1\dec31_dec_sub28_form[4:0] + attribute \src "libresoc.v:111217.3-111253.6" + wire width 13 $1\dec31_dec_sub28_function_unit[12:0] + attribute \src "libresoc.v:112253.3-112289.6" + wire width 3 $1\dec31_dec_sub28_in1_sel[2:0] + attribute \src "libresoc.v:112290.3-112326.6" + wire width 4 $1\dec31_dec_sub28_in2_sel[3:0] + attribute \src "libresoc.v:112327.3-112363.6" + wire width 2 $1\dec31_dec_sub28_in3_sel[1:0] + attribute \src "libresoc.v:111624.3-111660.6" + wire width 7 $1\dec31_dec_sub28_internal_op[6:0] + attribute \src "libresoc.v:111772.3-111808.6" + wire $1\dec31_dec_sub28_inv_a[0:0] + attribute \src "libresoc.v:111809.3-111845.6" + wire $1\dec31_dec_sub28_inv_out[0:0] + attribute \src "libresoc.v:111994.3-112030.6" + wire $1\dec31_dec_sub28_is_32b[0:0] + attribute \src "libresoc.v:111550.3-111586.6" + wire width 4 $1\dec31_dec_sub28_ldst_len[3:0] + attribute \src "libresoc.v:112105.3-112141.6" + wire $1\dec31_dec_sub28_lk[0:0] + attribute \src "libresoc.v:112364.3-112400.6" + wire width 2 $1\dec31_dec_sub28_out_sel[1:0] + attribute \src "libresoc.v:111661.3-111697.6" + wire width 2 $1\dec31_dec_sub28_rc_sel[1:0] + attribute \src "libresoc.v:111957.3-111993.6" + wire $1\dec31_dec_sub28_rsrv[0:0] + attribute \src "libresoc.v:112142.3-112178.6" + wire $1\dec31_dec_sub28_sgl_pipe[0:0] + attribute \src "libresoc.v:112068.3-112104.6" + wire $1\dec31_dec_sub28_sgn[0:0] + attribute \src "libresoc.v:111920.3-111956.6" + wire $1\dec31_dec_sub28_sgn_ext[0:0] + attribute \src "libresoc.v:111476.3-111512.6" + wire width 3 $1\dec31_dec_sub28_sv_cr_in[2:0] + attribute \src "libresoc.v:111513.3-111549.6" + wire width 3 $1\dec31_dec_sub28_sv_cr_out[2:0] + attribute \src "libresoc.v:111328.3-111364.6" + wire width 3 $1\dec31_dec_sub28_sv_in1[2:0] + attribute \src "libresoc.v:111365.3-111401.6" + wire width 3 $1\dec31_dec_sub28_sv_in2[2:0] + attribute \src "libresoc.v:111402.3-111438.6" + wire width 3 $1\dec31_dec_sub28_sv_in3[2:0] + attribute \src "libresoc.v:111439.3-111475.6" + wire width 3 $1\dec31_dec_sub28_sv_out[2:0] + attribute \src "libresoc.v:111587.3-111623.6" + wire width 2 $1\dec31_dec_sub28_upd[1:0] + attribute \enum_base_type "SVEtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "EXTRA2" + attribute \enum_value_10 "EXTRA3" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 5 \dec31_dec_sub28_SV_Etype + attribute \enum_base_type "SVPtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "P1" + attribute \enum_value_10 "P2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 6 \dec31_dec_sub28_SV_Ptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 8 output 4 \dec31_dec_sub28_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 26 \dec31_dec_sub28_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 11 \dec31_dec_sub28_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 12 \dec31_dec_sub28_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 22 \dec31_dec_sub28_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 25 \dec31_dec_sub28_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 5 output 3 \dec31_dec_sub28_form + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 13 output 1 \dec31_dec_sub28_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 7 \dec31_dec_sub28_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 8 \dec31_dec_sub28_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 9 \dec31_dec_sub28_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 output 2 \dec31_dec_sub28_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 23 \dec31_dec_sub28_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 24 \dec31_dec_sub28_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 29 \dec31_dec_sub28_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 19 \dec31_dec_sub28_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 31 \dec31_dec_sub28_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 10 \dec31_dec_sub28_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 21 \dec31_dec_sub28_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 28 \dec31_dec_sub28_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 32 \dec31_dec_sub28_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 30 \dec31_dec_sub28_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 27 \dec31_dec_sub28_sgn_ext + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 17 \dec31_dec_sub28_sv_cr_in + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 18 \dec31_dec_sub28_sv_cr_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 13 \dec31_dec_sub28_sv_in1 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 14 \dec31_dec_sub28_sv_in2 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 15 \dec31_dec_sub28_sv_in3 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 16 \dec31_dec_sub28_sv_out + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 20 \dec31_dec_sub28_upd + attribute \src "libresoc.v:110883.7-110883.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + wire width 32 input 33 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + wire width 5 \opcode_switch + attribute \src "libresoc.v:110883.7-110883.20" + process $proc$libresoc.v:110883$4293 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:111217.3-111253.6" + process $proc$libresoc.v:111217$4261 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_function_unit[12:0] $1\dec31_dec_sub28_function_unit[12:0] + attribute \src "libresoc.v:111218.5-111218.29" + switch \initial + attribute \src "libresoc.v:111218.9-111218.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_function_unit[12:0] 13'0000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_function_unit[12:0] 13'0000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_function_unit[12:0] 13'0000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_function_unit[12:0] 13'0000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_function_unit[12:0] 13'0000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_function_unit[12:0] 13'0000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_function_unit[12:0] 13'0000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_function_unit[12:0] 13'0000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_function_unit[12:0] 13'0000000010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_function_unit[12:0] 13'0000000010000 + case + assign $1\dec31_dec_sub28_function_unit[12:0] 13'0000000000000 + end + sync always + update \dec31_dec_sub28_function_unit $0\dec31_dec_sub28_function_unit[12:0] + end + attribute \src "libresoc.v:111254.3-111290.6" + process $proc$libresoc.v:111254$4262 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_cr_in[2:0] $1\dec31_dec_sub28_cr_in[2:0] + attribute \src "libresoc.v:111255.5-111255.29" + switch \initial + attribute \src "libresoc.v:111255.9-111255.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub28_cr_in $0\dec31_dec_sub28_cr_in[2:0] + end + attribute \src "libresoc.v:111291.3-111327.6" + process $proc$libresoc.v:111291$4263 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_cr_out[2:0] $1\dec31_dec_sub28_cr_out[2:0] + attribute \src "libresoc.v:111292.5-111292.29" + switch \initial + attribute \src "libresoc.v:111292.9-111292.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_cr_out[2:0] 3'001 + case + assign $1\dec31_dec_sub28_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub28_cr_out $0\dec31_dec_sub28_cr_out[2:0] + end + attribute \src "libresoc.v:111328.3-111364.6" + process $proc$libresoc.v:111328$4264 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_sv_in1[2:0] $1\dec31_dec_sub28_sv_in1[2:0] + attribute \src "libresoc.v:111329.5-111329.29" + switch \initial + attribute \src "libresoc.v:111329.9-111329.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_sv_in1[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_sv_in1[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_sv_in1[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_sv_in1[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_sv_in1[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_sv_in1[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_sv_in1[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_sv_in1[2:0] 3'011 + case + assign $1\dec31_dec_sub28_sv_in1[2:0] 3'000 + end + sync always + update \dec31_dec_sub28_sv_in1 $0\dec31_dec_sub28_sv_in1[2:0] + end + attribute \src "libresoc.v:111365.3-111401.6" + process $proc$libresoc.v:111365$4265 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_sv_in2[2:0] $1\dec31_dec_sub28_sv_in2[2:0] + attribute \src "libresoc.v:111366.5-111366.29" + switch \initial + attribute \src "libresoc.v:111366.9-111366.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_sv_in2[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_sv_in2[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_sv_in2[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_sv_in2[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_sv_in2[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_sv_in2[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_sv_in2[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_sv_in2[2:0] 3'010 + case + assign $1\dec31_dec_sub28_sv_in2[2:0] 3'000 + end + sync always + update \dec31_dec_sub28_sv_in2 $0\dec31_dec_sub28_sv_in2[2:0] + end + attribute \src "libresoc.v:111402.3-111438.6" + process $proc$libresoc.v:111402$4266 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_sv_in3[2:0] $1\dec31_dec_sub28_sv_in3[2:0] + attribute \src "libresoc.v:111403.5-111403.29" + switch \initial + attribute \src "libresoc.v:111403.9-111403.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_sv_in3[2:0] 3'000 + case + assign $1\dec31_dec_sub28_sv_in3[2:0] 3'000 + end + sync always + update \dec31_dec_sub28_sv_in3 $0\dec31_dec_sub28_sv_in3[2:0] + end + attribute \src "libresoc.v:111439.3-111475.6" + process $proc$libresoc.v:111439$4267 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_sv_out[2:0] $1\dec31_dec_sub28_sv_out[2:0] + attribute \src "libresoc.v:111440.5-111440.29" + switch \initial + attribute \src "libresoc.v:111440.9-111440.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_sv_out[2:0] 3'001 + case + assign $1\dec31_dec_sub28_sv_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub28_sv_out $0\dec31_dec_sub28_sv_out[2:0] + end + attribute \src "libresoc.v:111476.3-111512.6" + process $proc$libresoc.v:111476$4268 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_sv_cr_in[2:0] $1\dec31_dec_sub28_sv_cr_in[2:0] + attribute \src "libresoc.v:111477.5-111477.29" + switch \initial + attribute \src "libresoc.v:111477.9-111477.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_sv_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub28_sv_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub28_sv_cr_in $0\dec31_dec_sub28_sv_cr_in[2:0] + end + attribute \src "libresoc.v:111513.3-111549.6" + process $proc$libresoc.v:111513$4269 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_sv_cr_out[2:0] $1\dec31_dec_sub28_sv_cr_out[2:0] + attribute \src "libresoc.v:111514.5-111514.29" + switch \initial + attribute \src "libresoc.v:111514.9-111514.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_sv_cr_out[2:0] 3'001 + case + assign $1\dec31_dec_sub28_sv_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub28_sv_cr_out $0\dec31_dec_sub28_sv_cr_out[2:0] + end + attribute \src "libresoc.v:111550.3-111586.6" + process $proc$libresoc.v:111550$4270 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_ldst_len[3:0] $1\dec31_dec_sub28_ldst_len[3:0] + attribute \src "libresoc.v:111551.5-111551.29" + switch \initial + attribute \src "libresoc.v:111551.9-111551.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 + case + assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub28_ldst_len $0\dec31_dec_sub28_ldst_len[3:0] + end + attribute \src "libresoc.v:111587.3-111623.6" + process $proc$libresoc.v:111587$4271 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_upd[1:0] $1\dec31_dec_sub28_upd[1:0] + attribute \src "libresoc.v:111588.5-111588.29" + switch \initial + attribute \src "libresoc.v:111588.9-111588.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_upd[1:0] 2'00 + case + assign $1\dec31_dec_sub28_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub28_upd $0\dec31_dec_sub28_upd[1:0] + end + attribute \src "libresoc.v:111624.3-111660.6" + process $proc$libresoc.v:111624$4272 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_internal_op[6:0] $1\dec31_dec_sub28_internal_op[6:0] + attribute \src "libresoc.v:111625.5-111625.29" + switch \initial + attribute \src "libresoc.v:111625.9-111625.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_internal_op[6:0] 7'0000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_internal_op[6:0] 7'0000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_internal_op[6:0] 7'0001001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_internal_op[6:0] 7'0001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_internal_op[6:0] 7'1000011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_internal_op[6:0] 7'0000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_internal_op[6:0] 7'0110101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_internal_op[6:0] 7'0110101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_internal_op[6:0] 7'0110101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_internal_op[6:0] 7'1000011 + case + assign $1\dec31_dec_sub28_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub28_internal_op $0\dec31_dec_sub28_internal_op[6:0] + end + attribute \src "libresoc.v:111661.3-111697.6" + process $proc$libresoc.v:111661$4273 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_rc_sel[1:0] $1\dec31_dec_sub28_rc_sel[1:0] + attribute \src "libresoc.v:111662.5-111662.29" + switch \initial + attribute \src "libresoc.v:111662.9-111662.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_rc_sel[1:0] 2'10 + case + assign $1\dec31_dec_sub28_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub28_rc_sel $0\dec31_dec_sub28_rc_sel[1:0] + end + attribute \src "libresoc.v:111698.3-111734.6" + process $proc$libresoc.v:111698$4274 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_cry_in[1:0] $1\dec31_dec_sub28_cry_in[1:0] + attribute \src "libresoc.v:111699.5-111699.29" + switch \initial + attribute \src "libresoc.v:111699.9-111699.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 + case + assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub28_cry_in $0\dec31_dec_sub28_cry_in[1:0] + end + attribute \src "libresoc.v:111735.3-111771.6" + process $proc$libresoc.v:111735$4275 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_asmcode[7:0] $1\dec31_dec_sub28_asmcode[7:0] + attribute \src "libresoc.v:111736.5-111736.29" + switch \initial + attribute \src "libresoc.v:111736.9-111736.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_asmcode[7:0] 8'00001111 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_asmcode[7:0] 8'00010000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_asmcode[7:0] 8'00011001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_asmcode[7:0] 8'00011011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_asmcode[7:0] 8'01000011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_asmcode[7:0] 8'10000011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_asmcode[7:0] 8'10000111 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_asmcode[7:0] 8'10001000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_asmcode[7:0] 8'10001001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_asmcode[7:0] 8'11010001 + case + assign $1\dec31_dec_sub28_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub28_asmcode $0\dec31_dec_sub28_asmcode[7:0] + end + attribute \src "libresoc.v:111772.3-111808.6" + process $proc$libresoc.v:111772$4276 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_inv_a[0:0] $1\dec31_dec_sub28_inv_a[0:0] + attribute \src "libresoc.v:111773.5-111773.29" + switch \initial + attribute \src "libresoc.v:111773.9-111773.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_inv_a[0:0] 1'0 + case + assign $1\dec31_dec_sub28_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub28_inv_a $0\dec31_dec_sub28_inv_a[0:0] + end + attribute \src "libresoc.v:111809.3-111845.6" + process $proc$libresoc.v:111809$4277 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_inv_out[0:0] $1\dec31_dec_sub28_inv_out[0:0] + attribute \src "libresoc.v:111810.5-111810.29" + switch \initial + attribute \src "libresoc.v:111810.9-111810.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_inv_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_inv_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_inv_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub28_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub28_inv_out $0\dec31_dec_sub28_inv_out[0:0] + end + attribute \src "libresoc.v:111846.3-111882.6" + process $proc$libresoc.v:111846$4278 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_cry_out[0:0] $1\dec31_dec_sub28_cry_out[0:0] + attribute \src "libresoc.v:111847.5-111847.29" + switch \initial + attribute \src "libresoc.v:111847.9-111847.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 + case + assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub28_cry_out $0\dec31_dec_sub28_cry_out[0:0] + end + attribute \src "libresoc.v:111883.3-111919.6" + process $proc$libresoc.v:111883$4279 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_br[0:0] $1\dec31_dec_sub28_br[0:0] + attribute \src "libresoc.v:111884.5-111884.29" + switch \initial + attribute \src "libresoc.v:111884.9-111884.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_br[0:0] 1'0 + case + assign $1\dec31_dec_sub28_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub28_br $0\dec31_dec_sub28_br[0:0] + end + attribute \src "libresoc.v:111920.3-111956.6" + process $proc$libresoc.v:111920$4280 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_sgn_ext[0:0] $1\dec31_dec_sub28_sgn_ext[0:0] + attribute \src "libresoc.v:111921.5-111921.29" + switch \initial + attribute \src "libresoc.v:111921.9-111921.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub28_sgn_ext $0\dec31_dec_sub28_sgn_ext[0:0] + end + attribute \src "libresoc.v:111957.3-111993.6" + process $proc$libresoc.v:111957$4281 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_rsrv[0:0] $1\dec31_dec_sub28_rsrv[0:0] + attribute \src "libresoc.v:111958.5-111958.29" + switch \initial + attribute \src "libresoc.v:111958.9-111958.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub28_rsrv $0\dec31_dec_sub28_rsrv[0:0] + end + attribute \src "libresoc.v:111994.3-112030.6" + process $proc$libresoc.v:111994$4282 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_is_32b[0:0] $1\dec31_dec_sub28_is_32b[0:0] + attribute \src "libresoc.v:111995.5-111995.29" + switch \initial + attribute \src "libresoc.v:111995.9-111995.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 + case + assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub28_is_32b $0\dec31_dec_sub28_is_32b[0:0] + end + attribute \src "libresoc.v:112031.3-112067.6" + process $proc$libresoc.v:112031$4283 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_form[4:0] $1\dec31_dec_sub28_form[4:0] + attribute \src "libresoc.v:112032.5-112032.29" + switch \initial + attribute \src "libresoc.v:112032.9-112032.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_form[4:0] 5'01000 + case + assign $1\dec31_dec_sub28_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub28_form $0\dec31_dec_sub28_form[4:0] + end + attribute \src "libresoc.v:112068.3-112104.6" + process $proc$libresoc.v:112068$4284 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_sgn[0:0] $1\dec31_dec_sub28_sgn[0:0] + attribute \src "libresoc.v:112069.5-112069.29" + switch \initial + attribute \src "libresoc.v:112069.9-112069.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_sgn[0:0] 1'0 + case + assign $1\dec31_dec_sub28_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub28_sgn $0\dec31_dec_sub28_sgn[0:0] + end + attribute \src "libresoc.v:112105.3-112141.6" + process $proc$libresoc.v:112105$4285 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_lk[0:0] $1\dec31_dec_sub28_lk[0:0] + attribute \src "libresoc.v:112106.5-112106.29" + switch \initial + attribute \src "libresoc.v:112106.9-112106.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub28_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub28_lk $0\dec31_dec_sub28_lk[0:0] + end + attribute \src "libresoc.v:112142.3-112178.6" + process $proc$libresoc.v:112142$4286 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_sgl_pipe[0:0] $1\dec31_dec_sub28_sgl_pipe[0:0] + attribute \src "libresoc.v:112143.5-112143.29" + switch \initial + attribute \src "libresoc.v:112143.9-112143.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 + case + assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub28_sgl_pipe $0\dec31_dec_sub28_sgl_pipe[0:0] + end + attribute \src "libresoc.v:112179.3-112215.6" + process $proc$libresoc.v:112179$4287 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_SV_Etype[1:0] $1\dec31_dec_sub28_SV_Etype[1:0] + attribute \src "libresoc.v:112180.5-112180.29" + switch \initial + attribute \src "libresoc.v:112180.9-112180.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_SV_Etype[1:0] 2'10 + case + assign $1\dec31_dec_sub28_SV_Etype[1:0] 2'00 + end + sync always + update \dec31_dec_sub28_SV_Etype $0\dec31_dec_sub28_SV_Etype[1:0] + end + attribute \src "libresoc.v:112216.3-112252.6" + process $proc$libresoc.v:112216$4288 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_SV_Ptype[1:0] $1\dec31_dec_sub28_SV_Ptype[1:0] + attribute \src "libresoc.v:112217.5-112217.29" + switch \initial + attribute \src "libresoc.v:112217.9-112217.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_SV_Ptype[1:0] 2'01 + case + assign $1\dec31_dec_sub28_SV_Ptype[1:0] 2'00 + end + sync always + update \dec31_dec_sub28_SV_Ptype $0\dec31_dec_sub28_SV_Ptype[1:0] + end + attribute \src "libresoc.v:112253.3-112289.6" + process $proc$libresoc.v:112253$4289 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_in1_sel[2:0] $1\dec31_dec_sub28_in1_sel[2:0] + attribute \src "libresoc.v:112254.5-112254.29" + switch \initial + attribute \src "libresoc.v:112254.9-112254.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 + case + assign $1\dec31_dec_sub28_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub28_in1_sel $0\dec31_dec_sub28_in1_sel[2:0] + end + attribute \src "libresoc.v:112290.3-112326.6" + process $proc$libresoc.v:112290$4290 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_in2_sel[3:0] $1\dec31_dec_sub28_in2_sel[3:0] + attribute \src "libresoc.v:112291.5-112291.29" + switch \initial + attribute \src "libresoc.v:112291.9-112291.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 + case + assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub28_in2_sel $0\dec31_dec_sub28_in2_sel[3:0] + end + attribute \src "libresoc.v:112327.3-112363.6" + process $proc$libresoc.v:112327$4291 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_in3_sel[1:0] $1\dec31_dec_sub28_in3_sel[1:0] + attribute \src "libresoc.v:112328.5-112328.29" + switch \initial + attribute \src "libresoc.v:112328.9-112328.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub28_in3_sel $0\dec31_dec_sub28_in3_sel[1:0] + end + attribute \src "libresoc.v:112364.3-112400.6" + process $proc$libresoc.v:112364$4292 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_out_sel[1:0] $1\dec31_dec_sub28_out_sel[1:0] + attribute \src "libresoc.v:112365.5-112365.29" + switch \initial + attribute \src "libresoc.v:112365.9-112365.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_out_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_out_sel[1:0] 2'10 + case + assign $1\dec31_dec_sub28_out_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub28_out_sel $0\dec31_dec_sub28_out_sel[1:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:112406.1-113158.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub4" +attribute \generator "nMigen" +module \dec31_dec_sub4 + attribute \src "libresoc.v:113079.3-113091.6" + wire width 2 $0\dec31_dec_sub4_SV_Etype[1:0] + attribute \src "libresoc.v:113092.3-113104.6" + wire width 2 $0\dec31_dec_sub4_SV_Ptype[1:0] + attribute \src "libresoc.v:112923.3-112935.6" + wire width 8 $0\dec31_dec_sub4_asmcode[7:0] + attribute \src "libresoc.v:112975.3-112987.6" + wire $0\dec31_dec_sub4_br[0:0] + attribute \src "libresoc.v:112754.3-112766.6" + wire width 3 $0\dec31_dec_sub4_cr_in[2:0] + attribute \src "libresoc.v:112767.3-112779.6" + wire width 3 $0\dec31_dec_sub4_cr_out[2:0] + attribute \src "libresoc.v:112910.3-112922.6" + wire width 2 $0\dec31_dec_sub4_cry_in[1:0] + attribute \src "libresoc.v:112962.3-112974.6" + wire $0\dec31_dec_sub4_cry_out[0:0] + attribute \src "libresoc.v:113027.3-113039.6" + wire width 5 $0\dec31_dec_sub4_form[4:0] + attribute \src "libresoc.v:112741.3-112753.6" + wire width 13 $0\dec31_dec_sub4_function_unit[12:0] + attribute \src "libresoc.v:113105.3-113117.6" + wire width 3 $0\dec31_dec_sub4_in1_sel[2:0] + attribute \src "libresoc.v:113118.3-113130.6" + wire width 4 $0\dec31_dec_sub4_in2_sel[3:0] + attribute \src "libresoc.v:113131.3-113143.6" + wire width 2 $0\dec31_dec_sub4_in3_sel[1:0] + attribute \src "libresoc.v:112884.3-112896.6" + wire width 7 $0\dec31_dec_sub4_internal_op[6:0] + attribute \src "libresoc.v:112936.3-112948.6" + wire $0\dec31_dec_sub4_inv_a[0:0] + attribute \src "libresoc.v:112949.3-112961.6" + wire $0\dec31_dec_sub4_inv_out[0:0] + attribute \src "libresoc.v:113014.3-113026.6" + wire $0\dec31_dec_sub4_is_32b[0:0] + attribute \src "libresoc.v:112858.3-112870.6" + wire width 4 $0\dec31_dec_sub4_ldst_len[3:0] + attribute \src "libresoc.v:113053.3-113065.6" + wire $0\dec31_dec_sub4_lk[0:0] + attribute \src "libresoc.v:113144.3-113156.6" + wire width 2 $0\dec31_dec_sub4_out_sel[1:0] + attribute \src "libresoc.v:112897.3-112909.6" + wire width 2 $0\dec31_dec_sub4_rc_sel[1:0] + attribute \src "libresoc.v:113001.3-113013.6" + wire $0\dec31_dec_sub4_rsrv[0:0] + attribute \src "libresoc.v:113066.3-113078.6" + wire $0\dec31_dec_sub4_sgl_pipe[0:0] + attribute \src "libresoc.v:113040.3-113052.6" + wire $0\dec31_dec_sub4_sgn[0:0] + attribute \src "libresoc.v:112988.3-113000.6" + wire $0\dec31_dec_sub4_sgn_ext[0:0] + attribute \src "libresoc.v:112832.3-112844.6" + wire width 3 $0\dec31_dec_sub4_sv_cr_in[2:0] + attribute \src "libresoc.v:112845.3-112857.6" + wire width 3 $0\dec31_dec_sub4_sv_cr_out[2:0] + attribute \src "libresoc.v:112780.3-112792.6" + wire width 3 $0\dec31_dec_sub4_sv_in1[2:0] + attribute \src "libresoc.v:112793.3-112805.6" + wire width 3 $0\dec31_dec_sub4_sv_in2[2:0] + attribute \src "libresoc.v:112806.3-112818.6" + wire width 3 $0\dec31_dec_sub4_sv_in3[2:0] + attribute \src "libresoc.v:112819.3-112831.6" + wire width 3 $0\dec31_dec_sub4_sv_out[2:0] + attribute \src "libresoc.v:112871.3-112883.6" + wire width 2 $0\dec31_dec_sub4_upd[1:0] + attribute \src "libresoc.v:112407.7-112407.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:113079.3-113091.6" + wire width 2 $1\dec31_dec_sub4_SV_Etype[1:0] + attribute \src "libresoc.v:113092.3-113104.6" + wire width 2 $1\dec31_dec_sub4_SV_Ptype[1:0] + attribute \src "libresoc.v:112923.3-112935.6" + wire width 8 $1\dec31_dec_sub4_asmcode[7:0] + attribute \src "libresoc.v:112975.3-112987.6" + wire $1\dec31_dec_sub4_br[0:0] + attribute \src "libresoc.v:112754.3-112766.6" + wire width 3 $1\dec31_dec_sub4_cr_in[2:0] + attribute \src "libresoc.v:112767.3-112779.6" + wire width 3 $1\dec31_dec_sub4_cr_out[2:0] + attribute \src "libresoc.v:112910.3-112922.6" + wire width 2 $1\dec31_dec_sub4_cry_in[1:0] + attribute \src "libresoc.v:112962.3-112974.6" + wire $1\dec31_dec_sub4_cry_out[0:0] + attribute \src "libresoc.v:113027.3-113039.6" + wire width 5 $1\dec31_dec_sub4_form[4:0] + attribute \src "libresoc.v:112741.3-112753.6" + wire width 13 $1\dec31_dec_sub4_function_unit[12:0] + attribute \src "libresoc.v:113105.3-113117.6" + wire width 3 $1\dec31_dec_sub4_in1_sel[2:0] + attribute \src "libresoc.v:113118.3-113130.6" + wire width 4 $1\dec31_dec_sub4_in2_sel[3:0] + attribute \src "libresoc.v:113131.3-113143.6" + wire width 2 $1\dec31_dec_sub4_in3_sel[1:0] + attribute \src "libresoc.v:112884.3-112896.6" + wire width 7 $1\dec31_dec_sub4_internal_op[6:0] + attribute \src "libresoc.v:112936.3-112948.6" + wire $1\dec31_dec_sub4_inv_a[0:0] + attribute \src "libresoc.v:112949.3-112961.6" + wire $1\dec31_dec_sub4_inv_out[0:0] + attribute \src "libresoc.v:113014.3-113026.6" + wire $1\dec31_dec_sub4_is_32b[0:0] + attribute \src "libresoc.v:112858.3-112870.6" + wire width 4 $1\dec31_dec_sub4_ldst_len[3:0] + attribute \src "libresoc.v:113053.3-113065.6" + wire $1\dec31_dec_sub4_lk[0:0] + attribute \src "libresoc.v:113144.3-113156.6" + wire width 2 $1\dec31_dec_sub4_out_sel[1:0] + attribute \src "libresoc.v:112897.3-112909.6" + wire width 2 $1\dec31_dec_sub4_rc_sel[1:0] + attribute \src "libresoc.v:113001.3-113013.6" + wire $1\dec31_dec_sub4_rsrv[0:0] + attribute \src "libresoc.v:113066.3-113078.6" + wire $1\dec31_dec_sub4_sgl_pipe[0:0] + attribute \src "libresoc.v:113040.3-113052.6" + wire $1\dec31_dec_sub4_sgn[0:0] + attribute \src "libresoc.v:112988.3-113000.6" + wire $1\dec31_dec_sub4_sgn_ext[0:0] + attribute \src "libresoc.v:112832.3-112844.6" + wire width 3 $1\dec31_dec_sub4_sv_cr_in[2:0] + attribute \src "libresoc.v:112845.3-112857.6" + wire width 3 $1\dec31_dec_sub4_sv_cr_out[2:0] + attribute \src "libresoc.v:112780.3-112792.6" + wire width 3 $1\dec31_dec_sub4_sv_in1[2:0] + attribute \src "libresoc.v:112793.3-112805.6" + wire width 3 $1\dec31_dec_sub4_sv_in2[2:0] + attribute \src "libresoc.v:112806.3-112818.6" + wire width 3 $1\dec31_dec_sub4_sv_in3[2:0] + attribute \src "libresoc.v:112819.3-112831.6" + wire width 3 $1\dec31_dec_sub4_sv_out[2:0] + attribute \src "libresoc.v:112871.3-112883.6" + wire width 2 $1\dec31_dec_sub4_upd[1:0] + attribute \enum_base_type "SVEtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "EXTRA2" + attribute \enum_value_10 "EXTRA3" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 5 \dec31_dec_sub4_SV_Etype + attribute \enum_base_type "SVPtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "P1" + attribute \enum_value_10 "P2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 6 \dec31_dec_sub4_SV_Ptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 8 output 4 \dec31_dec_sub4_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 26 \dec31_dec_sub4_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 11 \dec31_dec_sub4_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 12 \dec31_dec_sub4_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 22 \dec31_dec_sub4_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 25 \dec31_dec_sub4_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 5 output 3 \dec31_dec_sub4_form + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 13 output 1 \dec31_dec_sub4_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 7 \dec31_dec_sub4_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 8 \dec31_dec_sub4_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 9 \dec31_dec_sub4_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 output 2 \dec31_dec_sub4_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 23 \dec31_dec_sub4_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 24 \dec31_dec_sub4_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 29 \dec31_dec_sub4_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 19 \dec31_dec_sub4_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 31 \dec31_dec_sub4_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 10 \dec31_dec_sub4_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 21 \dec31_dec_sub4_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 28 \dec31_dec_sub4_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 32 \dec31_dec_sub4_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 30 \dec31_dec_sub4_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 27 \dec31_dec_sub4_sgn_ext + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 17 \dec31_dec_sub4_sv_cr_in + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 18 \dec31_dec_sub4_sv_cr_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 13 \dec31_dec_sub4_sv_in1 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 14 \dec31_dec_sub4_sv_in2 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 15 \dec31_dec_sub4_sv_in3 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 16 \dec31_dec_sub4_sv_out + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 20 \dec31_dec_sub4_upd + attribute \src "libresoc.v:112407.7-112407.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + wire width 32 input 33 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + wire width 5 \opcode_switch + attribute \src "libresoc.v:112407.7-112407.20" + process $proc$libresoc.v:112407$4326 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:112741.3-112753.6" + process $proc$libresoc.v:112741$4294 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_function_unit[12:0] $1\dec31_dec_sub4_function_unit[12:0] + attribute \src "libresoc.v:112742.5-112742.29" + switch \initial + attribute \src "libresoc.v:112742.9-112742.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_function_unit[12:0] 13'0000010000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_function_unit[12:0] 13'0000010000000 + case + assign $1\dec31_dec_sub4_function_unit[12:0] 13'0000000000000 + end + sync always + update \dec31_dec_sub4_function_unit $0\dec31_dec_sub4_function_unit[12:0] + end + attribute \src "libresoc.v:112754.3-112766.6" + process $proc$libresoc.v:112754$4295 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_cr_in[2:0] $1\dec31_dec_sub4_cr_in[2:0] + attribute \src "libresoc.v:112755.5-112755.29" + switch \initial + attribute \src "libresoc.v:112755.9-112755.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub4_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub4_cr_in $0\dec31_dec_sub4_cr_in[2:0] + end + attribute \src "libresoc.v:112767.3-112779.6" + process $proc$libresoc.v:112767$4296 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_cr_out[2:0] $1\dec31_dec_sub4_cr_out[2:0] + attribute \src "libresoc.v:112768.5-112768.29" + switch \initial + attribute \src "libresoc.v:112768.9-112768.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_cr_out[2:0] 3'000 + case + assign $1\dec31_dec_sub4_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub4_cr_out $0\dec31_dec_sub4_cr_out[2:0] + end + attribute \src "libresoc.v:112780.3-112792.6" + process $proc$libresoc.v:112780$4297 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_sv_in1[2:0] $1\dec31_dec_sub4_sv_in1[2:0] + attribute \src "libresoc.v:112781.5-112781.29" + switch \initial + attribute \src "libresoc.v:112781.9-112781.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_sv_in1[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_sv_in1[2:0] 3'000 + case + assign $1\dec31_dec_sub4_sv_in1[2:0] 3'000 + end + sync always + update \dec31_dec_sub4_sv_in1 $0\dec31_dec_sub4_sv_in1[2:0] + end + attribute \src "libresoc.v:112793.3-112805.6" + process $proc$libresoc.v:112793$4298 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_sv_in2[2:0] $1\dec31_dec_sub4_sv_in2[2:0] + attribute \src "libresoc.v:112794.5-112794.29" + switch \initial + attribute \src "libresoc.v:112794.9-112794.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_sv_in2[2:0] 3'000 + case + assign $1\dec31_dec_sub4_sv_in2[2:0] 3'000 + end + sync always + update \dec31_dec_sub4_sv_in2 $0\dec31_dec_sub4_sv_in2[2:0] + end + attribute \src "libresoc.v:112806.3-112818.6" + process $proc$libresoc.v:112806$4299 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_sv_in3[2:0] $1\dec31_dec_sub4_sv_in3[2:0] + attribute \src "libresoc.v:112807.5-112807.29" + switch \initial + attribute \src "libresoc.v:112807.9-112807.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_sv_in3[2:0] 3'000 + case + assign $1\dec31_dec_sub4_sv_in3[2:0] 3'000 + end + sync always + update \dec31_dec_sub4_sv_in3 $0\dec31_dec_sub4_sv_in3[2:0] + end + attribute \src "libresoc.v:112819.3-112831.6" + process $proc$libresoc.v:112819$4300 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_sv_out[2:0] $1\dec31_dec_sub4_sv_out[2:0] + attribute \src "libresoc.v:112820.5-112820.29" + switch \initial + attribute \src "libresoc.v:112820.9-112820.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_sv_out[2:0] 3'000 + case + assign $1\dec31_dec_sub4_sv_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub4_sv_out $0\dec31_dec_sub4_sv_out[2:0] + end + attribute \src "libresoc.v:112832.3-112844.6" + process $proc$libresoc.v:112832$4301 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_sv_cr_in[2:0] $1\dec31_dec_sub4_sv_cr_in[2:0] + attribute \src "libresoc.v:112833.5-112833.29" + switch \initial + attribute \src "libresoc.v:112833.9-112833.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_sv_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub4_sv_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub4_sv_cr_in $0\dec31_dec_sub4_sv_cr_in[2:0] + end + attribute \src "libresoc.v:112845.3-112857.6" + process $proc$libresoc.v:112845$4302 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_sv_cr_out[2:0] $1\dec31_dec_sub4_sv_cr_out[2:0] + attribute \src "libresoc.v:112846.5-112846.29" + switch \initial + attribute \src "libresoc.v:112846.9-112846.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_sv_cr_out[2:0] 3'000 + case + assign $1\dec31_dec_sub4_sv_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub4_sv_cr_out $0\dec31_dec_sub4_sv_cr_out[2:0] + end + attribute \src "libresoc.v:112858.3-112870.6" + process $proc$libresoc.v:112858$4303 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_ldst_len[3:0] $1\dec31_dec_sub4_ldst_len[3:0] + attribute \src "libresoc.v:112859.5-112859.29" + switch \initial + attribute \src "libresoc.v:112859.9-112859.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_ldst_len[3:0] 4'0000 + case + assign $1\dec31_dec_sub4_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub4_ldst_len $0\dec31_dec_sub4_ldst_len[3:0] + end + attribute \src "libresoc.v:112871.3-112883.6" + process $proc$libresoc.v:112871$4304 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_upd[1:0] $1\dec31_dec_sub4_upd[1:0] + attribute \src "libresoc.v:112872.5-112872.29" + switch \initial + attribute \src "libresoc.v:112872.9-112872.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_upd[1:0] 2'00 + case + assign $1\dec31_dec_sub4_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub4_upd $0\dec31_dec_sub4_upd[1:0] + end + attribute \src "libresoc.v:112884.3-112896.6" + process $proc$libresoc.v:112884$4305 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_internal_op[6:0] $1\dec31_dec_sub4_internal_op[6:0] + attribute \src "libresoc.v:112885.5-112885.29" + switch \initial + attribute \src "libresoc.v:112885.9-112885.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_internal_op[6:0] 7'0111111 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_internal_op[6:0] 7'0111111 + case + assign $1\dec31_dec_sub4_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub4_internal_op $0\dec31_dec_sub4_internal_op[6:0] + end + attribute \src "libresoc.v:112897.3-112909.6" + process $proc$libresoc.v:112897$4306 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_rc_sel[1:0] $1\dec31_dec_sub4_rc_sel[1:0] + attribute \src "libresoc.v:112898.5-112898.29" + switch \initial + attribute \src "libresoc.v:112898.9-112898.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_rc_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub4_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub4_rc_sel $0\dec31_dec_sub4_rc_sel[1:0] + end + attribute \src "libresoc.v:112910.3-112922.6" + process $proc$libresoc.v:112910$4307 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_cry_in[1:0] $1\dec31_dec_sub4_cry_in[1:0] + attribute \src "libresoc.v:112911.5-112911.29" + switch \initial + attribute \src "libresoc.v:112911.9-112911.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_cry_in[1:0] 2'00 + case + assign $1\dec31_dec_sub4_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub4_cry_in $0\dec31_dec_sub4_cry_in[1:0] + end + attribute \src "libresoc.v:112923.3-112935.6" + process $proc$libresoc.v:112923$4308 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_asmcode[7:0] $1\dec31_dec_sub4_asmcode[7:0] + attribute \src "libresoc.v:112924.5-112924.29" + switch \initial + attribute \src "libresoc.v:112924.9-112924.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_asmcode[7:0] 8'11001011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_asmcode[7:0] 8'11001111 + case + assign $1\dec31_dec_sub4_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub4_asmcode $0\dec31_dec_sub4_asmcode[7:0] + end + attribute \src "libresoc.v:112936.3-112948.6" + process $proc$libresoc.v:112936$4309 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_inv_a[0:0] $1\dec31_dec_sub4_inv_a[0:0] + attribute \src "libresoc.v:112937.5-112937.29" + switch \initial + attribute \src "libresoc.v:112937.9-112937.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_inv_a[0:0] 1'0 + case + assign $1\dec31_dec_sub4_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub4_inv_a $0\dec31_dec_sub4_inv_a[0:0] + end + attribute \src "libresoc.v:112949.3-112961.6" + process $proc$libresoc.v:112949$4310 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_inv_out[0:0] $1\dec31_dec_sub4_inv_out[0:0] + attribute \src "libresoc.v:112950.5-112950.29" + switch \initial + attribute \src "libresoc.v:112950.9-112950.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub4_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub4_inv_out $0\dec31_dec_sub4_inv_out[0:0] + end + attribute \src "libresoc.v:112962.3-112974.6" + process $proc$libresoc.v:112962$4311 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_cry_out[0:0] $1\dec31_dec_sub4_cry_out[0:0] + attribute \src "libresoc.v:112963.5-112963.29" + switch \initial + attribute \src "libresoc.v:112963.9-112963.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_cry_out[0:0] 1'0 + case + assign $1\dec31_dec_sub4_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub4_cry_out $0\dec31_dec_sub4_cry_out[0:0] + end + attribute \src "libresoc.v:112975.3-112987.6" + process $proc$libresoc.v:112975$4312 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_br[0:0] $1\dec31_dec_sub4_br[0:0] + attribute \src "libresoc.v:112976.5-112976.29" + switch \initial + attribute \src "libresoc.v:112976.9-112976.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_br[0:0] 1'0 + case + assign $1\dec31_dec_sub4_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub4_br $0\dec31_dec_sub4_br[0:0] + end + attribute \src "libresoc.v:112988.3-113000.6" + process $proc$libresoc.v:112988$4313 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_sgn_ext[0:0] $1\dec31_dec_sub4_sgn_ext[0:0] + attribute \src "libresoc.v:112989.5-112989.29" + switch \initial + attribute \src "libresoc.v:112989.9-112989.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub4_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub4_sgn_ext $0\dec31_dec_sub4_sgn_ext[0:0] + end + attribute \src "libresoc.v:113001.3-113013.6" + process $proc$libresoc.v:113001$4314 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_rsrv[0:0] $1\dec31_dec_sub4_rsrv[0:0] + attribute \src "libresoc.v:113002.5-113002.29" + switch \initial + attribute \src "libresoc.v:113002.9-113002.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub4_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub4_rsrv $0\dec31_dec_sub4_rsrv[0:0] + end + attribute \src "libresoc.v:113014.3-113026.6" + process $proc$libresoc.v:113014$4315 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_is_32b[0:0] $1\dec31_dec_sub4_is_32b[0:0] + attribute \src "libresoc.v:113015.5-113015.29" + switch \initial + attribute \src "libresoc.v:113015.9-113015.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_is_32b[0:0] 1'1 + case + assign $1\dec31_dec_sub4_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub4_is_32b $0\dec31_dec_sub4_is_32b[0:0] + end + attribute \src "libresoc.v:113027.3-113039.6" + process $proc$libresoc.v:113027$4316 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_form[4:0] $1\dec31_dec_sub4_form[4:0] + attribute \src "libresoc.v:113028.5-113028.29" + switch \initial + attribute \src "libresoc.v:113028.9-113028.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_form[4:0] 5'01000 + case + assign $1\dec31_dec_sub4_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub4_form $0\dec31_dec_sub4_form[4:0] + end + attribute \src "libresoc.v:113040.3-113052.6" + process $proc$libresoc.v:113040$4317 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_sgn[0:0] $1\dec31_dec_sub4_sgn[0:0] + attribute \src "libresoc.v:113041.5-113041.29" + switch \initial + attribute \src "libresoc.v:113041.9-113041.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_sgn[0:0] 1'0 + case + assign $1\dec31_dec_sub4_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub4_sgn $0\dec31_dec_sub4_sgn[0:0] + end + attribute \src "libresoc.v:113053.3-113065.6" + process $proc$libresoc.v:113053$4318 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_lk[0:0] $1\dec31_dec_sub4_lk[0:0] + attribute \src "libresoc.v:113054.5-113054.29" + switch \initial + attribute \src "libresoc.v:113054.9-113054.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub4_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub4_lk $0\dec31_dec_sub4_lk[0:0] + end + attribute \src "libresoc.v:113066.3-113078.6" + process $proc$libresoc.v:113066$4319 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_sgl_pipe[0:0] $1\dec31_dec_sub4_sgl_pipe[0:0] + attribute \src "libresoc.v:113067.5-113067.29" + switch \initial + attribute \src "libresoc.v:113067.9-113067.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_sgl_pipe[0:0] 1'1 + case + assign $1\dec31_dec_sub4_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub4_sgl_pipe $0\dec31_dec_sub4_sgl_pipe[0:0] + end + attribute \src "libresoc.v:113079.3-113091.6" + process $proc$libresoc.v:113079$4320 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_SV_Etype[1:0] $1\dec31_dec_sub4_SV_Etype[1:0] + attribute \src "libresoc.v:113080.5-113080.29" + switch \initial + attribute \src "libresoc.v:113080.9-113080.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_SV_Etype[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_SV_Etype[1:0] 2'00 + case + assign $1\dec31_dec_sub4_SV_Etype[1:0] 2'00 + end + sync always + update \dec31_dec_sub4_SV_Etype $0\dec31_dec_sub4_SV_Etype[1:0] + end + attribute \src "libresoc.v:113092.3-113104.6" + process $proc$libresoc.v:113092$4321 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_SV_Ptype[1:0] $1\dec31_dec_sub4_SV_Ptype[1:0] + attribute \src "libresoc.v:113093.5-113093.29" + switch \initial + attribute \src "libresoc.v:113093.9-113093.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_SV_Ptype[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_SV_Ptype[1:0] 2'00 + case + assign $1\dec31_dec_sub4_SV_Ptype[1:0] 2'00 + end + sync always + update \dec31_dec_sub4_SV_Ptype $0\dec31_dec_sub4_SV_Ptype[1:0] + end + attribute \src "libresoc.v:113105.3-113117.6" + process $proc$libresoc.v:113105$4322 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_in1_sel[2:0] $1\dec31_dec_sub4_in1_sel[2:0] + attribute \src "libresoc.v:113106.5-113106.29" + switch \initial + attribute \src "libresoc.v:113106.9-113106.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_in1_sel[2:0] 3'001 + case + assign $1\dec31_dec_sub4_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub4_in1_sel $0\dec31_dec_sub4_in1_sel[2:0] + end + attribute \src "libresoc.v:113118.3-113130.6" + process $proc$libresoc.v:113118$4323 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_in2_sel[3:0] $1\dec31_dec_sub4_in2_sel[3:0] + attribute \src "libresoc.v:113119.5-113119.29" + switch \initial + attribute \src "libresoc.v:113119.9-113119.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_in2_sel[3:0] 4'0001 + case + assign $1\dec31_dec_sub4_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub4_in2_sel $0\dec31_dec_sub4_in2_sel[3:0] + end + attribute \src "libresoc.v:113131.3-113143.6" + process $proc$libresoc.v:113131$4324 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_in3_sel[1:0] $1\dec31_dec_sub4_in3_sel[1:0] + attribute \src "libresoc.v:113132.5-113132.29" + switch \initial + attribute \src "libresoc.v:113132.9-113132.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_in3_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub4_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub4_in3_sel $0\dec31_dec_sub4_in3_sel[1:0] + end + attribute \src "libresoc.v:113144.3-113156.6" + process $proc$libresoc.v:113144$4325 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_out_sel[1:0] $1\dec31_dec_sub4_out_sel[1:0] + attribute \src "libresoc.v:113145.5-113145.29" + switch \initial + attribute \src "libresoc.v:113145.9-113145.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_out_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub4_out_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub4_out_sel $0\dec31_dec_sub4_out_sel[1:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:113162.1-114874.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub8" +attribute \generator "nMigen" +module \dec31_dec_sub8 + attribute \src "libresoc.v:114615.3-114657.6" + wire width 2 $0\dec31_dec_sub8_SV_Etype[1:0] + attribute \src "libresoc.v:114658.3-114700.6" + wire width 2 $0\dec31_dec_sub8_SV_Ptype[1:0] + attribute \src "libresoc.v:114099.3-114141.6" + wire width 8 $0\dec31_dec_sub8_asmcode[7:0] + attribute \src "libresoc.v:114271.3-114313.6" + wire $0\dec31_dec_sub8_br[0:0] + attribute \src "libresoc.v:113540.3-113582.6" + wire width 3 $0\dec31_dec_sub8_cr_in[2:0] + attribute \src "libresoc.v:113583.3-113625.6" + wire width 3 $0\dec31_dec_sub8_cr_out[2:0] + attribute \src "libresoc.v:114056.3-114098.6" + wire width 2 $0\dec31_dec_sub8_cry_in[1:0] + attribute \src "libresoc.v:114228.3-114270.6" + wire $0\dec31_dec_sub8_cry_out[0:0] + attribute \src "libresoc.v:114443.3-114485.6" + wire width 5 $0\dec31_dec_sub8_form[4:0] + attribute \src "libresoc.v:113497.3-113539.6" + wire width 13 $0\dec31_dec_sub8_function_unit[12:0] + attribute \src "libresoc.v:114701.3-114743.6" + wire width 3 $0\dec31_dec_sub8_in1_sel[2:0] + attribute \src "libresoc.v:114744.3-114786.6" + wire width 4 $0\dec31_dec_sub8_in2_sel[3:0] + attribute \src "libresoc.v:114787.3-114829.6" + wire width 2 $0\dec31_dec_sub8_in3_sel[1:0] + attribute \src "libresoc.v:113970.3-114012.6" + wire width 7 $0\dec31_dec_sub8_internal_op[6:0] + attribute \src "libresoc.v:114142.3-114184.6" + wire $0\dec31_dec_sub8_inv_a[0:0] + attribute \src "libresoc.v:114185.3-114227.6" + wire $0\dec31_dec_sub8_inv_out[0:0] + attribute \src "libresoc.v:114400.3-114442.6" + wire $0\dec31_dec_sub8_is_32b[0:0] + attribute \src "libresoc.v:113884.3-113926.6" + wire width 4 $0\dec31_dec_sub8_ldst_len[3:0] + attribute \src "libresoc.v:114529.3-114571.6" + wire $0\dec31_dec_sub8_lk[0:0] + attribute \src "libresoc.v:114830.3-114872.6" + wire width 2 $0\dec31_dec_sub8_out_sel[1:0] + attribute \src "libresoc.v:114013.3-114055.6" + wire width 2 $0\dec31_dec_sub8_rc_sel[1:0] + attribute \src "libresoc.v:114357.3-114399.6" + wire $0\dec31_dec_sub8_rsrv[0:0] + attribute \src "libresoc.v:114572.3-114614.6" + wire $0\dec31_dec_sub8_sgl_pipe[0:0] + attribute \src "libresoc.v:114486.3-114528.6" + wire $0\dec31_dec_sub8_sgn[0:0] + attribute \src "libresoc.v:114314.3-114356.6" + wire $0\dec31_dec_sub8_sgn_ext[0:0] + attribute \src "libresoc.v:113798.3-113840.6" + wire width 3 $0\dec31_dec_sub8_sv_cr_in[2:0] + attribute \src "libresoc.v:113841.3-113883.6" + wire width 3 $0\dec31_dec_sub8_sv_cr_out[2:0] + attribute \src "libresoc.v:113626.3-113668.6" + wire width 3 $0\dec31_dec_sub8_sv_in1[2:0] + attribute \src "libresoc.v:113669.3-113711.6" + wire width 3 $0\dec31_dec_sub8_sv_in2[2:0] + attribute \src "libresoc.v:113712.3-113754.6" + wire width 3 $0\dec31_dec_sub8_sv_in3[2:0] + attribute \src "libresoc.v:113755.3-113797.6" + wire width 3 $0\dec31_dec_sub8_sv_out[2:0] + attribute \src "libresoc.v:113927.3-113969.6" + wire width 2 $0\dec31_dec_sub8_upd[1:0] + attribute \src "libresoc.v:113163.7-113163.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:114615.3-114657.6" + wire width 2 $1\dec31_dec_sub8_SV_Etype[1:0] + attribute \src "libresoc.v:114658.3-114700.6" + wire width 2 $1\dec31_dec_sub8_SV_Ptype[1:0] + attribute \src "libresoc.v:114099.3-114141.6" + wire width 8 $1\dec31_dec_sub8_asmcode[7:0] + attribute \src "libresoc.v:114271.3-114313.6" + wire $1\dec31_dec_sub8_br[0:0] + attribute \src "libresoc.v:113540.3-113582.6" + wire width 3 $1\dec31_dec_sub8_cr_in[2:0] + attribute \src "libresoc.v:113583.3-113625.6" + wire width 3 $1\dec31_dec_sub8_cr_out[2:0] + attribute \src "libresoc.v:114056.3-114098.6" + wire width 2 $1\dec31_dec_sub8_cry_in[1:0] + attribute \src "libresoc.v:114228.3-114270.6" + wire $1\dec31_dec_sub8_cry_out[0:0] + attribute \src "libresoc.v:114443.3-114485.6" + wire width 5 $1\dec31_dec_sub8_form[4:0] + attribute \src "libresoc.v:113497.3-113539.6" + wire width 13 $1\dec31_dec_sub8_function_unit[12:0] + attribute \src "libresoc.v:114701.3-114743.6" + wire width 3 $1\dec31_dec_sub8_in1_sel[2:0] + attribute \src "libresoc.v:114744.3-114786.6" + wire width 4 $1\dec31_dec_sub8_in2_sel[3:0] + attribute \src "libresoc.v:114787.3-114829.6" + wire width 2 $1\dec31_dec_sub8_in3_sel[1:0] + attribute \src "libresoc.v:113970.3-114012.6" + wire width 7 $1\dec31_dec_sub8_internal_op[6:0] + attribute \src "libresoc.v:114142.3-114184.6" + wire $1\dec31_dec_sub8_inv_a[0:0] + attribute \src "libresoc.v:114185.3-114227.6" + wire $1\dec31_dec_sub8_inv_out[0:0] + attribute \src "libresoc.v:114400.3-114442.6" + wire $1\dec31_dec_sub8_is_32b[0:0] + attribute \src "libresoc.v:113884.3-113926.6" + wire width 4 $1\dec31_dec_sub8_ldst_len[3:0] + attribute \src "libresoc.v:114529.3-114571.6" + wire $1\dec31_dec_sub8_lk[0:0] + attribute \src "libresoc.v:114830.3-114872.6" + wire width 2 $1\dec31_dec_sub8_out_sel[1:0] + attribute \src "libresoc.v:114013.3-114055.6" + wire width 2 $1\dec31_dec_sub8_rc_sel[1:0] + attribute \src "libresoc.v:114357.3-114399.6" + wire $1\dec31_dec_sub8_rsrv[0:0] + attribute \src "libresoc.v:114572.3-114614.6" + wire $1\dec31_dec_sub8_sgl_pipe[0:0] + attribute \src "libresoc.v:114486.3-114528.6" + wire $1\dec31_dec_sub8_sgn[0:0] + attribute \src "libresoc.v:114314.3-114356.6" + wire $1\dec31_dec_sub8_sgn_ext[0:0] + attribute \src "libresoc.v:113798.3-113840.6" + wire width 3 $1\dec31_dec_sub8_sv_cr_in[2:0] + attribute \src "libresoc.v:113841.3-113883.6" + wire width 3 $1\dec31_dec_sub8_sv_cr_out[2:0] + attribute \src "libresoc.v:113626.3-113668.6" + wire width 3 $1\dec31_dec_sub8_sv_in1[2:0] + attribute \src "libresoc.v:113669.3-113711.6" + wire width 3 $1\dec31_dec_sub8_sv_in2[2:0] + attribute \src "libresoc.v:113712.3-113754.6" + wire width 3 $1\dec31_dec_sub8_sv_in3[2:0] + attribute \src "libresoc.v:113755.3-113797.6" + wire width 3 $1\dec31_dec_sub8_sv_out[2:0] + attribute \src "libresoc.v:113927.3-113969.6" + wire width 2 $1\dec31_dec_sub8_upd[1:0] + attribute \enum_base_type "SVEtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "EXTRA2" + attribute \enum_value_10 "EXTRA3" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 5 \dec31_dec_sub8_SV_Etype + attribute \enum_base_type "SVPtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "P1" + attribute \enum_value_10 "P2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 6 \dec31_dec_sub8_SV_Ptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 8 output 4 \dec31_dec_sub8_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 26 \dec31_dec_sub8_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 11 \dec31_dec_sub8_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 12 \dec31_dec_sub8_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 22 \dec31_dec_sub8_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 25 \dec31_dec_sub8_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 5 output 3 \dec31_dec_sub8_form + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 13 output 1 \dec31_dec_sub8_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 7 \dec31_dec_sub8_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 8 \dec31_dec_sub8_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 9 \dec31_dec_sub8_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 output 2 \dec31_dec_sub8_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 23 \dec31_dec_sub8_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 24 \dec31_dec_sub8_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 29 \dec31_dec_sub8_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 19 \dec31_dec_sub8_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 31 \dec31_dec_sub8_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 10 \dec31_dec_sub8_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 21 \dec31_dec_sub8_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 28 \dec31_dec_sub8_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 32 \dec31_dec_sub8_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 30 \dec31_dec_sub8_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 27 \dec31_dec_sub8_sgn_ext + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 17 \dec31_dec_sub8_sv_cr_in + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 18 \dec31_dec_sub8_sv_cr_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 13 \dec31_dec_sub8_sv_in1 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 14 \dec31_dec_sub8_sv_in2 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 15 \dec31_dec_sub8_sv_in3 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 16 \dec31_dec_sub8_sv_out + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 20 \dec31_dec_sub8_upd + attribute \src "libresoc.v:113163.7-113163.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + wire width 32 input 33 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + wire width 5 \opcode_switch + attribute \src "libresoc.v:113163.7-113163.20" + process $proc$libresoc.v:113163$4359 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:113497.3-113539.6" + process $proc$libresoc.v:113497$4327 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_function_unit[12:0] $1\dec31_dec_sub8_function_unit[12:0] + attribute \src "libresoc.v:113498.5-113498.29" + switch \initial + attribute \src "libresoc.v:113498.9-113498.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_function_unit[12:0] 13'0000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_function_unit[12:0] 13'0000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_function_unit[12:0] 13'0000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_function_unit[12:0] 13'0000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_function_unit[12:0] 13'0000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_function_unit[12:0] 13'0000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_function_unit[12:0] 13'0000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_function_unit[12:0] 13'0000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_function_unit[12:0] 13'0000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_function_unit[12:0] 13'0000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_function_unit[12:0] 13'0000000000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_function_unit[12:0] 13'0000000000010 + case + assign $1\dec31_dec_sub8_function_unit[12:0] 13'0000000000000 + end + sync always + update \dec31_dec_sub8_function_unit $0\dec31_dec_sub8_function_unit[12:0] + end + attribute \src "libresoc.v:113540.3-113582.6" + process $proc$libresoc.v:113540$4328 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_cr_in[2:0] $1\dec31_dec_sub8_cr_in[2:0] + attribute \src "libresoc.v:113541.5-113541.29" + switch \initial + attribute \src "libresoc.v:113541.9-113541.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub8_cr_in $0\dec31_dec_sub8_cr_in[2:0] + end + attribute \src "libresoc.v:113583.3-113625.6" + process $proc$libresoc.v:113583$4329 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_cr_out[2:0] $1\dec31_dec_sub8_cr_out[2:0] + attribute \src "libresoc.v:113584.5-113584.29" + switch \initial + attribute \src "libresoc.v:113584.9-113584.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 + case + assign $1\dec31_dec_sub8_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub8_cr_out $0\dec31_dec_sub8_cr_out[2:0] + end + attribute \src "libresoc.v:113626.3-113668.6" + process $proc$libresoc.v:113626$4330 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_sv_in1[2:0] $1\dec31_dec_sub8_sv_in1[2:0] + attribute \src "libresoc.v:113627.5-113627.29" + switch \initial + attribute \src "libresoc.v:113627.9-113627.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_sv_in1[2:0] 3'010 + case + assign $1\dec31_dec_sub8_sv_in1[2:0] 3'000 + end + sync always + update \dec31_dec_sub8_sv_in1 $0\dec31_dec_sub8_sv_in1[2:0] + end + attribute \src "libresoc.v:113669.3-113711.6" + process $proc$libresoc.v:113669$4331 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_sv_in2[2:0] $1\dec31_dec_sub8_sv_in2[2:0] + attribute \src "libresoc.v:113670.5-113670.29" + switch \initial + attribute \src "libresoc.v:113670.9-113670.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_sv_in2[2:0] 3'000 + case + assign $1\dec31_dec_sub8_sv_in2[2:0] 3'000 + end + sync always + update \dec31_dec_sub8_sv_in2 $0\dec31_dec_sub8_sv_in2[2:0] + end + attribute \src "libresoc.v:113712.3-113754.6" + process $proc$libresoc.v:113712$4332 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_sv_in3[2:0] $1\dec31_dec_sub8_sv_in3[2:0] + attribute \src "libresoc.v:113713.5-113713.29" + switch \initial + attribute \src "libresoc.v:113713.9-113713.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_sv_in3[2:0] 3'000 + case + assign $1\dec31_dec_sub8_sv_in3[2:0] 3'000 + end + sync always + update \dec31_dec_sub8_sv_in3 $0\dec31_dec_sub8_sv_in3[2:0] + end + attribute \src "libresoc.v:113755.3-113797.6" + process $proc$libresoc.v:113755$4333 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_sv_out[2:0] $1\dec31_dec_sub8_sv_out[2:0] + attribute \src "libresoc.v:113756.5-113756.29" + switch \initial + attribute \src "libresoc.v:113756.9-113756.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_sv_out[2:0] 3'001 + case + assign $1\dec31_dec_sub8_sv_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub8_sv_out $0\dec31_dec_sub8_sv_out[2:0] + end + attribute \src "libresoc.v:113798.3-113840.6" + process $proc$libresoc.v:113798$4334 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_sv_cr_in[2:0] $1\dec31_dec_sub8_sv_cr_in[2:0] + attribute \src "libresoc.v:113799.5-113799.29" + switch \initial + attribute \src "libresoc.v:113799.9-113799.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_sv_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub8_sv_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub8_sv_cr_in $0\dec31_dec_sub8_sv_cr_in[2:0] + end + attribute \src "libresoc.v:113841.3-113883.6" + process $proc$libresoc.v:113841$4335 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_sv_cr_out[2:0] $1\dec31_dec_sub8_sv_cr_out[2:0] + attribute \src "libresoc.v:113842.5-113842.29" + switch \initial + attribute \src "libresoc.v:113842.9-113842.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_sv_cr_out[2:0] 3'001 + case + assign $1\dec31_dec_sub8_sv_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub8_sv_cr_out $0\dec31_dec_sub8_sv_cr_out[2:0] + end + attribute \src "libresoc.v:113884.3-113926.6" + process $proc$libresoc.v:113884$4336 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_ldst_len[3:0] $1\dec31_dec_sub8_ldst_len[3:0] + attribute \src "libresoc.v:113885.5-113885.29" + switch \initial + attribute \src "libresoc.v:113885.9-113885.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 + case + assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub8_ldst_len $0\dec31_dec_sub8_ldst_len[3:0] + end + attribute \src "libresoc.v:113927.3-113969.6" + process $proc$libresoc.v:113927$4337 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_upd[1:0] $1\dec31_dec_sub8_upd[1:0] + attribute \src "libresoc.v:113928.5-113928.29" + switch \initial + attribute \src "libresoc.v:113928.9-113928.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_upd[1:0] 2'00 + case + assign $1\dec31_dec_sub8_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub8_upd $0\dec31_dec_sub8_upd[1:0] + end + attribute \src "libresoc.v:113970.3-114012.6" + process $proc$libresoc.v:113970$4338 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_internal_op[6:0] $1\dec31_dec_sub8_internal_op[6:0] + attribute \src "libresoc.v:113971.5-113971.29" + switch \initial + attribute \src "libresoc.v:113971.9-113971.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 + case + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub8_internal_op $0\dec31_dec_sub8_internal_op[6:0] + end + attribute \src "libresoc.v:114013.3-114055.6" + process $proc$libresoc.v:114013$4339 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_rc_sel[1:0] $1\dec31_dec_sub8_rc_sel[1:0] + attribute \src "libresoc.v:114014.5-114014.29" + switch \initial + attribute \src "libresoc.v:114014.9-114014.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 + case + assign $1\dec31_dec_sub8_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub8_rc_sel $0\dec31_dec_sub8_rc_sel[1:0] + end + attribute \src "libresoc.v:114056.3-114098.6" + process $proc$libresoc.v:114056$4340 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_cry_in[1:0] $1\dec31_dec_sub8_cry_in[1:0] + attribute \src "libresoc.v:114057.5-114057.29" + switch \initial + attribute \src "libresoc.v:114057.9-114057.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_cry_in[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_cry_in[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_cry_in[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_cry_in[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_cry_in[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_cry_in[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_cry_in[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_cry_in[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_cry_in[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_cry_in[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_cry_in[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_cry_in[1:0] 2'10 + case + assign $1\dec31_dec_sub8_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub8_cry_in $0\dec31_dec_sub8_cry_in[1:0] + end + attribute \src "libresoc.v:114099.3-114141.6" + process $proc$libresoc.v:114099$4341 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_asmcode[7:0] $1\dec31_dec_sub8_asmcode[7:0] + attribute \src "libresoc.v:114100.5-114100.29" + switch \initial + attribute \src "libresoc.v:114100.9-114100.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_asmcode[7:0] 8'10000100 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_asmcode[7:0] 8'10000101 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_asmcode[7:0] 8'10111111 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_asmcode[7:0] 8'11000111 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_asmcode[7:0] 8'11000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_asmcode[7:0] 8'11000001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_asmcode[7:0] 8'11000010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_asmcode[7:0] 8'11000011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_asmcode[7:0] 8'11000101 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_asmcode[7:0] 8'11000110 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_asmcode[7:0] 8'11001000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_asmcode[7:0] 8'11001001 + case + assign $1\dec31_dec_sub8_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub8_asmcode $0\dec31_dec_sub8_asmcode[7:0] + end + attribute \src "libresoc.v:114142.3-114184.6" + process $proc$libresoc.v:114142$4342 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_inv_a[0:0] $1\dec31_dec_sub8_inv_a[0:0] + attribute \src "libresoc.v:114143.5-114143.29" + switch \initial + attribute \src "libresoc.v:114143.9-114143.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 + case + assign $1\dec31_dec_sub8_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub8_inv_a $0\dec31_dec_sub8_inv_a[0:0] + end + attribute \src "libresoc.v:114185.3-114227.6" + process $proc$libresoc.v:114185$4343 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_inv_out[0:0] $1\dec31_dec_sub8_inv_out[0:0] + attribute \src "libresoc.v:114186.5-114186.29" + switch \initial + attribute \src "libresoc.v:114186.9-114186.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub8_inv_out $0\dec31_dec_sub8_inv_out[0:0] + end + attribute \src "libresoc.v:114228.3-114270.6" + process $proc$libresoc.v:114228$4344 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_cry_out[0:0] $1\dec31_dec_sub8_cry_out[0:0] + attribute \src "libresoc.v:114229.5-114229.29" + switch \initial + attribute \src "libresoc.v:114229.9-114229.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_cry_out[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_cry_out[0:0] 1'1 + case + assign $1\dec31_dec_sub8_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub8_cry_out $0\dec31_dec_sub8_cry_out[0:0] + end + attribute \src "libresoc.v:114271.3-114313.6" + process $proc$libresoc.v:114271$4345 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_br[0:0] $1\dec31_dec_sub8_br[0:0] + attribute \src "libresoc.v:114272.5-114272.29" + switch \initial + attribute \src "libresoc.v:114272.9-114272.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_br[0:0] 1'0 + case + assign $1\dec31_dec_sub8_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub8_br $0\dec31_dec_sub8_br[0:0] + end + attribute \src "libresoc.v:114314.3-114356.6" + process $proc$libresoc.v:114314$4346 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_sgn_ext[0:0] $1\dec31_dec_sub8_sgn_ext[0:0] + attribute \src "libresoc.v:114315.5-114315.29" + switch \initial + attribute \src "libresoc.v:114315.9-114315.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub8_sgn_ext $0\dec31_dec_sub8_sgn_ext[0:0] + end + attribute \src "libresoc.v:114357.3-114399.6" + process $proc$libresoc.v:114357$4347 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_rsrv[0:0] $1\dec31_dec_sub8_rsrv[0:0] + attribute \src "libresoc.v:114358.5-114358.29" + switch \initial + attribute \src "libresoc.v:114358.9-114358.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub8_rsrv $0\dec31_dec_sub8_rsrv[0:0] + end + attribute \src "libresoc.v:114400.3-114442.6" + process $proc$libresoc.v:114400$4348 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_is_32b[0:0] $1\dec31_dec_sub8_is_32b[0:0] + attribute \src "libresoc.v:114401.5-114401.29" + switch \initial + attribute \src "libresoc.v:114401.9-114401.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + case + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub8_is_32b $0\dec31_dec_sub8_is_32b[0:0] + end + attribute \src "libresoc.v:114443.3-114485.6" + process $proc$libresoc.v:114443$4349 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_form[4:0] $1\dec31_dec_sub8_form[4:0] + attribute \src "libresoc.v:114444.5-114444.29" + switch \initial + attribute \src "libresoc.v:114444.9-114444.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_form[4:0] 5'10001 + case + assign $1\dec31_dec_sub8_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub8_form $0\dec31_dec_sub8_form[4:0] + end + attribute \src "libresoc.v:114486.3-114528.6" + process $proc$libresoc.v:114486$4350 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_sgn[0:0] $1\dec31_dec_sub8_sgn[0:0] + attribute \src "libresoc.v:114487.5-114487.29" + switch \initial + attribute \src "libresoc.v:114487.9-114487.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_sgn[0:0] 1'0 + case + assign $1\dec31_dec_sub8_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub8_sgn $0\dec31_dec_sub8_sgn[0:0] + end + attribute \src "libresoc.v:114529.3-114571.6" + process $proc$libresoc.v:114529$4351 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_lk[0:0] $1\dec31_dec_sub8_lk[0:0] + attribute \src "libresoc.v:114530.5-114530.29" + switch \initial + attribute \src "libresoc.v:114530.9-114530.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub8_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub8_lk $0\dec31_dec_sub8_lk[0:0] + end + attribute \src "libresoc.v:114572.3-114614.6" + process $proc$libresoc.v:114572$4352 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_sgl_pipe[0:0] $1\dec31_dec_sub8_sgl_pipe[0:0] + attribute \src "libresoc.v:114573.5-114573.29" + switch \initial + attribute \src "libresoc.v:114573.9-114573.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 + case + assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub8_sgl_pipe $0\dec31_dec_sub8_sgl_pipe[0:0] + end + attribute \src "libresoc.v:114615.3-114657.6" + process $proc$libresoc.v:114615$4353 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_SV_Etype[1:0] $1\dec31_dec_sub8_SV_Etype[1:0] + attribute \src "libresoc.v:114616.5-114616.29" + switch \initial + attribute \src "libresoc.v:114616.9-114616.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_SV_Etype[1:0] 2'10 + case + assign $1\dec31_dec_sub8_SV_Etype[1:0] 2'00 + end + sync always + update \dec31_dec_sub8_SV_Etype $0\dec31_dec_sub8_SV_Etype[1:0] + end + attribute \src "libresoc.v:114658.3-114700.6" + process $proc$libresoc.v:114658$4354 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_SV_Ptype[1:0] $1\dec31_dec_sub8_SV_Ptype[1:0] + attribute \src "libresoc.v:114659.5-114659.29" + switch \initial + attribute \src "libresoc.v:114659.9-114659.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_SV_Ptype[1:0] 2'10 + case + assign $1\dec31_dec_sub8_SV_Ptype[1:0] 2'00 + end + sync always + update \dec31_dec_sub8_SV_Ptype $0\dec31_dec_sub8_SV_Ptype[1:0] + end + attribute \src "libresoc.v:114701.3-114743.6" + process $proc$libresoc.v:114701$4355 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_in1_sel[2:0] $1\dec31_dec_sub8_in1_sel[2:0] + attribute \src "libresoc.v:114702.5-114702.29" + switch \initial + attribute \src "libresoc.v:114702.9-114702.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 + case + assign $1\dec31_dec_sub8_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub8_in1_sel $0\dec31_dec_sub8_in1_sel[2:0] + end + attribute \src "libresoc.v:114744.3-114786.6" + process $proc$libresoc.v:114744$4356 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_in2_sel[3:0] $1\dec31_dec_sub8_in2_sel[3:0] + attribute \src "libresoc.v:114745.5-114745.29" + switch \initial + attribute \src "libresoc.v:114745.9-114745.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_in2_sel[3:0] 4'1001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_in2_sel[3:0] 4'1001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0000 + case + assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub8_in2_sel $0\dec31_dec_sub8_in2_sel[3:0] + end + attribute \src "libresoc.v:114787.3-114829.6" + process $proc$libresoc.v:114787$4357 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_in3_sel[1:0] $1\dec31_dec_sub8_in3_sel[1:0] + attribute \src "libresoc.v:114788.5-114788.29" + switch \initial + attribute \src "libresoc.v:114788.9-114788.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub8_in3_sel $0\dec31_dec_sub8_in3_sel[1:0] + end + attribute \src "libresoc.v:114830.3-114872.6" + process $proc$libresoc.v:114830$4358 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_out_sel[1:0] $1\dec31_dec_sub8_out_sel[1:0] + attribute \src "libresoc.v:114831.5-114831.29" + switch \initial + attribute \src "libresoc.v:114831.9-114831.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 + case + assign $1\dec31_dec_sub8_out_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub8_out_sel $0\dec31_dec_sub8_out_sel[1:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:114878.1-116974.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub9" +attribute \generator "nMigen" +module \dec31_dec_sub9 + attribute \src "libresoc.v:116643.3-116697.6" + wire width 2 $0\dec31_dec_sub9_SV_Etype[1:0] + attribute \src "libresoc.v:116698.3-116752.6" + wire width 2 $0\dec31_dec_sub9_SV_Ptype[1:0] + attribute \src "libresoc.v:115983.3-116037.6" + wire width 8 $0\dec31_dec_sub9_asmcode[7:0] + attribute \src "libresoc.v:116203.3-116257.6" + wire $0\dec31_dec_sub9_br[0:0] + attribute \src "libresoc.v:115268.3-115322.6" + wire width 3 $0\dec31_dec_sub9_cr_in[2:0] + attribute \src "libresoc.v:115323.3-115377.6" + wire width 3 $0\dec31_dec_sub9_cr_out[2:0] + attribute \src "libresoc.v:115928.3-115982.6" + wire width 2 $0\dec31_dec_sub9_cry_in[1:0] + attribute \src "libresoc.v:116148.3-116202.6" + wire $0\dec31_dec_sub9_cry_out[0:0] + attribute \src "libresoc.v:116423.3-116477.6" + wire width 5 $0\dec31_dec_sub9_form[4:0] + attribute \src "libresoc.v:115213.3-115267.6" + wire width 13 $0\dec31_dec_sub9_function_unit[12:0] + attribute \src "libresoc.v:116753.3-116807.6" + wire width 3 $0\dec31_dec_sub9_in1_sel[2:0] + attribute \src "libresoc.v:116808.3-116862.6" + wire width 4 $0\dec31_dec_sub9_in2_sel[3:0] + attribute \src "libresoc.v:116863.3-116917.6" + wire width 2 $0\dec31_dec_sub9_in3_sel[1:0] + attribute \src "libresoc.v:115818.3-115872.6" + wire width 7 $0\dec31_dec_sub9_internal_op[6:0] + attribute \src "libresoc.v:116038.3-116092.6" + wire $0\dec31_dec_sub9_inv_a[0:0] + attribute \src "libresoc.v:116093.3-116147.6" + wire $0\dec31_dec_sub9_inv_out[0:0] + attribute \src "libresoc.v:116368.3-116422.6" + wire $0\dec31_dec_sub9_is_32b[0:0] + attribute \src "libresoc.v:115708.3-115762.6" + wire width 4 $0\dec31_dec_sub9_ldst_len[3:0] + attribute \src "libresoc.v:116533.3-116587.6" + wire $0\dec31_dec_sub9_lk[0:0] + attribute \src "libresoc.v:116918.3-116972.6" + wire width 2 $0\dec31_dec_sub9_out_sel[1:0] + attribute \src "libresoc.v:115873.3-115927.6" + wire width 2 $0\dec31_dec_sub9_rc_sel[1:0] + attribute \src "libresoc.v:116313.3-116367.6" + wire $0\dec31_dec_sub9_rsrv[0:0] + attribute \src "libresoc.v:116588.3-116642.6" + wire $0\dec31_dec_sub9_sgl_pipe[0:0] + attribute \src "libresoc.v:116478.3-116532.6" + wire $0\dec31_dec_sub9_sgn[0:0] + attribute \src "libresoc.v:116258.3-116312.6" + wire $0\dec31_dec_sub9_sgn_ext[0:0] + attribute \src "libresoc.v:115598.3-115652.6" + wire width 3 $0\dec31_dec_sub9_sv_cr_in[2:0] + attribute \src "libresoc.v:115653.3-115707.6" + wire width 3 $0\dec31_dec_sub9_sv_cr_out[2:0] + attribute \src "libresoc.v:115378.3-115432.6" + wire width 3 $0\dec31_dec_sub9_sv_in1[2:0] + attribute \src "libresoc.v:115433.3-115487.6" + wire width 3 $0\dec31_dec_sub9_sv_in2[2:0] + attribute \src "libresoc.v:115488.3-115542.6" + wire width 3 $0\dec31_dec_sub9_sv_in3[2:0] + attribute \src "libresoc.v:115543.3-115597.6" + wire width 3 $0\dec31_dec_sub9_sv_out[2:0] + attribute \src "libresoc.v:115763.3-115817.6" + wire width 2 $0\dec31_dec_sub9_upd[1:0] + attribute \src "libresoc.v:114879.7-114879.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:116643.3-116697.6" + wire width 2 $1\dec31_dec_sub9_SV_Etype[1:0] + attribute \src "libresoc.v:116698.3-116752.6" + wire width 2 $1\dec31_dec_sub9_SV_Ptype[1:0] + attribute \src "libresoc.v:115983.3-116037.6" + wire width 8 $1\dec31_dec_sub9_asmcode[7:0] + attribute \src "libresoc.v:116203.3-116257.6" + wire $1\dec31_dec_sub9_br[0:0] + attribute \src "libresoc.v:115268.3-115322.6" + wire width 3 $1\dec31_dec_sub9_cr_in[2:0] + attribute \src "libresoc.v:115323.3-115377.6" + wire width 3 $1\dec31_dec_sub9_cr_out[2:0] + attribute \src "libresoc.v:115928.3-115982.6" + wire width 2 $1\dec31_dec_sub9_cry_in[1:0] + attribute \src "libresoc.v:116148.3-116202.6" + wire $1\dec31_dec_sub9_cry_out[0:0] + attribute \src "libresoc.v:116423.3-116477.6" + wire width 5 $1\dec31_dec_sub9_form[4:0] + attribute \src "libresoc.v:115213.3-115267.6" + wire width 13 $1\dec31_dec_sub9_function_unit[12:0] + attribute \src "libresoc.v:116753.3-116807.6" + wire width 3 $1\dec31_dec_sub9_in1_sel[2:0] + attribute \src "libresoc.v:116808.3-116862.6" + wire width 4 $1\dec31_dec_sub9_in2_sel[3:0] + attribute \src "libresoc.v:116863.3-116917.6" + wire width 2 $1\dec31_dec_sub9_in3_sel[1:0] + attribute \src "libresoc.v:115818.3-115872.6" + wire width 7 $1\dec31_dec_sub9_internal_op[6:0] + attribute \src "libresoc.v:116038.3-116092.6" + wire $1\dec31_dec_sub9_inv_a[0:0] + attribute \src "libresoc.v:116093.3-116147.6" + wire $1\dec31_dec_sub9_inv_out[0:0] + attribute \src "libresoc.v:116368.3-116422.6" + wire $1\dec31_dec_sub9_is_32b[0:0] + attribute \src "libresoc.v:115708.3-115762.6" + wire width 4 $1\dec31_dec_sub9_ldst_len[3:0] + attribute \src "libresoc.v:116533.3-116587.6" + wire $1\dec31_dec_sub9_lk[0:0] + attribute \src "libresoc.v:116918.3-116972.6" + wire width 2 $1\dec31_dec_sub9_out_sel[1:0] + attribute \src "libresoc.v:115873.3-115927.6" + wire width 2 $1\dec31_dec_sub9_rc_sel[1:0] + attribute \src "libresoc.v:116313.3-116367.6" + wire $1\dec31_dec_sub9_rsrv[0:0] + attribute \src "libresoc.v:116588.3-116642.6" + wire $1\dec31_dec_sub9_sgl_pipe[0:0] + attribute \src "libresoc.v:116478.3-116532.6" + wire $1\dec31_dec_sub9_sgn[0:0] + attribute \src "libresoc.v:116258.3-116312.6" + wire $1\dec31_dec_sub9_sgn_ext[0:0] + attribute \src "libresoc.v:115598.3-115652.6" + wire width 3 $1\dec31_dec_sub9_sv_cr_in[2:0] + attribute \src "libresoc.v:115653.3-115707.6" + wire width 3 $1\dec31_dec_sub9_sv_cr_out[2:0] + attribute \src "libresoc.v:115378.3-115432.6" + wire width 3 $1\dec31_dec_sub9_sv_in1[2:0] + attribute \src "libresoc.v:115433.3-115487.6" + wire width 3 $1\dec31_dec_sub9_sv_in2[2:0] + attribute \src "libresoc.v:115488.3-115542.6" + wire width 3 $1\dec31_dec_sub9_sv_in3[2:0] + attribute \src "libresoc.v:115543.3-115597.6" + wire width 3 $1\dec31_dec_sub9_sv_out[2:0] + attribute \src "libresoc.v:115763.3-115817.6" + wire width 2 $1\dec31_dec_sub9_upd[1:0] + attribute \enum_base_type "SVEtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "EXTRA2" + attribute \enum_value_10 "EXTRA3" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 5 \dec31_dec_sub9_SV_Etype + attribute \enum_base_type "SVPtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "P1" + attribute \enum_value_10 "P2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 6 \dec31_dec_sub9_SV_Ptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 8 output 4 \dec31_dec_sub9_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 26 \dec31_dec_sub9_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 11 \dec31_dec_sub9_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 12 \dec31_dec_sub9_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 22 \dec31_dec_sub9_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 25 \dec31_dec_sub9_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 5 output 3 \dec31_dec_sub9_form + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 13 output 1 \dec31_dec_sub9_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 7 \dec31_dec_sub9_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 8 \dec31_dec_sub9_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 9 \dec31_dec_sub9_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 output 2 \dec31_dec_sub9_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 23 \dec31_dec_sub9_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 24 \dec31_dec_sub9_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 29 \dec31_dec_sub9_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 19 \dec31_dec_sub9_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 31 \dec31_dec_sub9_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 10 \dec31_dec_sub9_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 21 \dec31_dec_sub9_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 28 \dec31_dec_sub9_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 32 \dec31_dec_sub9_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 30 \dec31_dec_sub9_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 27 \dec31_dec_sub9_sgn_ext + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 17 \dec31_dec_sub9_sv_cr_in + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 18 \dec31_dec_sub9_sv_cr_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 13 \dec31_dec_sub9_sv_in1 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 14 \dec31_dec_sub9_sv_in2 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 15 \dec31_dec_sub9_sv_in3 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 16 \dec31_dec_sub9_sv_out + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 20 \dec31_dec_sub9_upd + attribute \src "libresoc.v:114879.7-114879.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + wire width 32 input 33 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + wire width 5 \opcode_switch + attribute \src "libresoc.v:114879.7-114879.20" + process $proc$libresoc.v:114879$4392 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:115213.3-115267.6" + process $proc$libresoc.v:115213$4360 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_function_unit[12:0] $1\dec31_dec_sub9_function_unit[12:0] + attribute \src "libresoc.v:115214.5-115214.29" + switch \initial + attribute \src "libresoc.v:115214.9-115214.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_function_unit[12:0] 13'0001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_function_unit[12:0] 13'0001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_function_unit[12:0] 13'0001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_function_unit[12:0] 13'0001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_function_unit[12:0] 13'0001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_function_unit[12:0] 13'0001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_function_unit[12:0] 13'0001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_function_unit[12:0] 13'0001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_function_unit[12:0] 13'0001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_function_unit[12:0] 13'0001000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_function_unit[12:0] 13'0000100000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_function_unit[12:0] 13'0000100000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_function_unit[12:0] 13'0000100000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_function_unit[12:0] 13'0000100000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_function_unit[12:0] 13'0000100000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_function_unit[12:0] 13'0000100000000 + case + assign $1\dec31_dec_sub9_function_unit[12:0] 13'0000000000000 + end + sync always + update \dec31_dec_sub9_function_unit $0\dec31_dec_sub9_function_unit[12:0] + end + attribute \src "libresoc.v:115268.3-115322.6" + process $proc$libresoc.v:115268$4361 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_cr_in[2:0] $1\dec31_dec_sub9_cr_in[2:0] + attribute \src "libresoc.v:115269.5-115269.29" + switch \initial + attribute \src "libresoc.v:115269.9-115269.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub9_cr_in $0\dec31_dec_sub9_cr_in[2:0] + end + attribute \src "libresoc.v:115323.3-115377.6" + process $proc$libresoc.v:115323$4362 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_cr_out[2:0] $1\dec31_dec_sub9_cr_out[2:0] + attribute \src "libresoc.v:115324.5-115324.29" + switch \initial + attribute \src "libresoc.v:115324.9-115324.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 + case + assign $1\dec31_dec_sub9_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub9_cr_out $0\dec31_dec_sub9_cr_out[2:0] + end + attribute \src "libresoc.v:115378.3-115432.6" + process $proc$libresoc.v:115378$4363 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_sv_in1[2:0] $1\dec31_dec_sub9_sv_in1[2:0] + attribute \src "libresoc.v:115379.5-115379.29" + switch \initial + attribute \src "libresoc.v:115379.9-115379.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_sv_in1[2:0] 3'010 + case + assign $1\dec31_dec_sub9_sv_in1[2:0] 3'000 + end + sync always + update \dec31_dec_sub9_sv_in1 $0\dec31_dec_sub9_sv_in1[2:0] + end + attribute \src "libresoc.v:115433.3-115487.6" + process $proc$libresoc.v:115433$4364 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_sv_in2[2:0] $1\dec31_dec_sub9_sv_in2[2:0] + attribute \src "libresoc.v:115434.5-115434.29" + switch \initial + attribute \src "libresoc.v:115434.9-115434.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_sv_in2[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_sv_in2[2:0] 3'011 + case + assign $1\dec31_dec_sub9_sv_in2[2:0] 3'000 + end + sync always + update \dec31_dec_sub9_sv_in2 $0\dec31_dec_sub9_sv_in2[2:0] + end + attribute \src "libresoc.v:115488.3-115542.6" + process $proc$libresoc.v:115488$4365 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_sv_in3[2:0] $1\dec31_dec_sub9_sv_in3[2:0] + attribute \src "libresoc.v:115489.5-115489.29" + switch \initial + attribute \src "libresoc.v:115489.9-115489.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_sv_in3[2:0] 3'000 + case + assign $1\dec31_dec_sub9_sv_in3[2:0] 3'000 + end + sync always + update \dec31_dec_sub9_sv_in3 $0\dec31_dec_sub9_sv_in3[2:0] + end + attribute \src "libresoc.v:115543.3-115597.6" + process $proc$libresoc.v:115543$4366 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_sv_out[2:0] $1\dec31_dec_sub9_sv_out[2:0] + attribute \src "libresoc.v:115544.5-115544.29" + switch \initial + attribute \src "libresoc.v:115544.9-115544.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_sv_out[2:0] 3'001 + case + assign $1\dec31_dec_sub9_sv_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub9_sv_out $0\dec31_dec_sub9_sv_out[2:0] + end + attribute \src "libresoc.v:115598.3-115652.6" + process $proc$libresoc.v:115598$4367 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_sv_cr_in[2:0] $1\dec31_dec_sub9_sv_cr_in[2:0] + attribute \src "libresoc.v:115599.5-115599.29" + switch \initial + attribute \src "libresoc.v:115599.9-115599.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_sv_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub9_sv_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub9_sv_cr_in $0\dec31_dec_sub9_sv_cr_in[2:0] + end + attribute \src "libresoc.v:115653.3-115707.6" + process $proc$libresoc.v:115653$4368 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_sv_cr_out[2:0] $1\dec31_dec_sub9_sv_cr_out[2:0] + attribute \src "libresoc.v:115654.5-115654.29" + switch \initial + attribute \src "libresoc.v:115654.9-115654.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_sv_cr_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_sv_cr_out[2:0] 3'001 + case + assign $1\dec31_dec_sub9_sv_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub9_sv_cr_out $0\dec31_dec_sub9_sv_cr_out[2:0] + end + attribute \src "libresoc.v:115708.3-115762.6" + process $proc$libresoc.v:115708$4369 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_ldst_len[3:0] $1\dec31_dec_sub9_ldst_len[3:0] + attribute \src "libresoc.v:115709.5-115709.29" + switch \initial + attribute \src "libresoc.v:115709.9-115709.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + case + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub9_ldst_len $0\dec31_dec_sub9_ldst_len[3:0] + end + attribute \src "libresoc.v:115763.3-115817.6" + process $proc$libresoc.v:115763$4370 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_upd[1:0] $1\dec31_dec_sub9_upd[1:0] + attribute \src "libresoc.v:115764.5-115764.29" + switch \initial + attribute \src "libresoc.v:115764.9-115764.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + case + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub9_upd $0\dec31_dec_sub9_upd[1:0] + end + attribute \src "libresoc.v:115818.3-115872.6" + process $proc$libresoc.v:115818$4371 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_internal_op[6:0] $1\dec31_dec_sub9_internal_op[6:0] + attribute \src "libresoc.v:115819.5-115819.29" + switch \initial + attribute \src "libresoc.v:115819.9-115819.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011110 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011110 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011110 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011110 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011101 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0101111 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0101111 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0110011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0110011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0110011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0110011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0110010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0110010 + case + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub9_internal_op $0\dec31_dec_sub9_internal_op[6:0] + end + attribute \src "libresoc.v:115873.3-115927.6" + process $proc$libresoc.v:115873$4372 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_rc_sel[1:0] $1\dec31_dec_sub9_rc_sel[1:0] + attribute \src "libresoc.v:115874.5-115874.29" + switch \initial + attribute \src "libresoc.v:115874.9-115874.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 + case + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub9_rc_sel $0\dec31_dec_sub9_rc_sel[1:0] + end + attribute \src "libresoc.v:115928.3-115982.6" + process $proc$libresoc.v:115928$4373 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_cry_in[1:0] $1\dec31_dec_sub9_cry_in[1:0] + attribute \src "libresoc.v:115929.5-115929.29" + switch \initial + attribute \src "libresoc.v:115929.9-115929.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + case + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub9_cry_in $0\dec31_dec_sub9_cry_in[1:0] + end + attribute \src "libresoc.v:115983.3-116037.6" + process $proc$libresoc.v:115983$4374 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_asmcode[7:0] $1\dec31_dec_sub9_asmcode[7:0] + attribute \src "libresoc.v:115984.5-115984.29" + switch \initial + attribute \src "libresoc.v:115984.9-115984.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_asmcode[7:0] 8'00110110 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_asmcode[7:0] 8'00110111 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_asmcode[7:0] 8'00110100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_asmcode[7:0] 8'00110101 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_asmcode[7:0] 8'00111001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_asmcode[7:0] 8'00111010 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_asmcode[7:0] 8'00110011 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_asmcode[7:0] 8'00111000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_asmcode[7:0] 8'01110100 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_asmcode[7:0] 8'01110010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_asmcode[7:0] 8'01111010 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_asmcode[7:0] 8'01111011 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_asmcode[7:0] 8'01111010 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_asmcode[7:0] 8'01111011 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_asmcode[7:0] 8'01111110 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_asmcode[7:0] 8'01111111 + case + assign $1\dec31_dec_sub9_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub9_asmcode $0\dec31_dec_sub9_asmcode[7:0] + end + attribute \src "libresoc.v:116038.3-116092.6" + process $proc$libresoc.v:116038$4375 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_inv_a[0:0] $1\dec31_dec_sub9_inv_a[0:0] + attribute \src "libresoc.v:116039.5-116039.29" + switch \initial + attribute \src "libresoc.v:116039.9-116039.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + case + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub9_inv_a $0\dec31_dec_sub9_inv_a[0:0] + end + attribute \src "libresoc.v:116093.3-116147.6" + process $proc$libresoc.v:116093$4376 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_inv_out[0:0] $1\dec31_dec_sub9_inv_out[0:0] + attribute \src "libresoc.v:116094.5-116094.29" + switch \initial + attribute \src "libresoc.v:116094.9-116094.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub9_inv_out $0\dec31_dec_sub9_inv_out[0:0] + end + attribute \src "libresoc.v:116148.3-116202.6" + process $proc$libresoc.v:116148$4377 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_cry_out[0:0] $1\dec31_dec_sub9_cry_out[0:0] + attribute \src "libresoc.v:116149.5-116149.29" + switch \initial + attribute \src "libresoc.v:116149.9-116149.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + case + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub9_cry_out $0\dec31_dec_sub9_cry_out[0:0] + end + attribute \src "libresoc.v:116203.3-116257.6" + process $proc$libresoc.v:116203$4378 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_br[0:0] $1\dec31_dec_sub9_br[0:0] + attribute \src "libresoc.v:116204.5-116204.29" + switch \initial + attribute \src "libresoc.v:116204.9-116204.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_br[0:0] 1'0 + case + assign $1\dec31_dec_sub9_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub9_br $0\dec31_dec_sub9_br[0:0] + end + attribute \src "libresoc.v:116258.3-116312.6" + process $proc$libresoc.v:116258$4379 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_sgn_ext[0:0] $1\dec31_dec_sub9_sgn_ext[0:0] + attribute \src "libresoc.v:116259.5-116259.29" + switch \initial + attribute \src "libresoc.v:116259.9-116259.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub9_sgn_ext $0\dec31_dec_sub9_sgn_ext[0:0] + end + attribute \src "libresoc.v:116313.3-116367.6" + process $proc$libresoc.v:116313$4380 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_rsrv[0:0] $1\dec31_dec_sub9_rsrv[0:0] + attribute \src "libresoc.v:116314.5-116314.29" + switch \initial + attribute \src "libresoc.v:116314.9-116314.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub9_rsrv $0\dec31_dec_sub9_rsrv[0:0] + end + attribute \src "libresoc.v:116368.3-116422.6" + process $proc$libresoc.v:116368$4381 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_is_32b[0:0] $1\dec31_dec_sub9_is_32b[0:0] + attribute \src "libresoc.v:116369.5-116369.29" + switch \initial + attribute \src "libresoc.v:116369.9-116369.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + case + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub9_is_32b $0\dec31_dec_sub9_is_32b[0:0] + end + attribute \src "libresoc.v:116423.3-116477.6" + process $proc$libresoc.v:116423$4382 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_form[4:0] $1\dec31_dec_sub9_form[4:0] + attribute \src "libresoc.v:116424.5-116424.29" + switch \initial + attribute \src "libresoc.v:116424.9-116424.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_form[4:0] 5'01000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_form[4:0] 5'10001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_form[4:0] 5'10001 + case + assign $1\dec31_dec_sub9_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub9_form $0\dec31_dec_sub9_form[4:0] + end + attribute \src "libresoc.v:116478.3-116532.6" + process $proc$libresoc.v:116478$4383 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_sgn[0:0] $1\dec31_dec_sub9_sgn[0:0] + attribute \src "libresoc.v:116479.5-116479.29" + switch \initial + attribute \src "libresoc.v:116479.9-116479.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'1 + case + assign $1\dec31_dec_sub9_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub9_sgn $0\dec31_dec_sub9_sgn[0:0] + end + attribute \src "libresoc.v:116533.3-116587.6" + process $proc$libresoc.v:116533$4384 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_lk[0:0] $1\dec31_dec_sub9_lk[0:0] + attribute \src "libresoc.v:116534.5-116534.29" + switch \initial + attribute \src "libresoc.v:116534.9-116534.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub9_lk $0\dec31_dec_sub9_lk[0:0] + end + attribute \src "libresoc.v:116588.3-116642.6" + process $proc$libresoc.v:116588$4385 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_sgl_pipe[0:0] $1\dec31_dec_sub9_sgl_pipe[0:0] + attribute \src "libresoc.v:116589.5-116589.29" + switch \initial + attribute \src "libresoc.v:116589.9-116589.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + case + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub9_sgl_pipe $0\dec31_dec_sub9_sgl_pipe[0:0] + end + attribute \src "libresoc.v:116643.3-116697.6" + process $proc$libresoc.v:116643$4386 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_SV_Etype[1:0] $1\dec31_dec_sub9_SV_Etype[1:0] + attribute \src "libresoc.v:116644.5-116644.29" + switch \initial + attribute \src "libresoc.v:116644.9-116644.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_SV_Etype[1:0] 2'10 + case + assign $1\dec31_dec_sub9_SV_Etype[1:0] 2'00 + end + sync always + update \dec31_dec_sub9_SV_Etype $0\dec31_dec_sub9_SV_Etype[1:0] + end + attribute \src "libresoc.v:116698.3-116752.6" + process $proc$libresoc.v:116698$4387 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_SV_Ptype[1:0] $1\dec31_dec_sub9_SV_Ptype[1:0] + attribute \src "libresoc.v:116699.5-116699.29" + switch \initial + attribute \src "libresoc.v:116699.9-116699.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_SV_Ptype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_SV_Ptype[1:0] 2'01 + case + assign $1\dec31_dec_sub9_SV_Ptype[1:0] 2'00 + end + sync always + update \dec31_dec_sub9_SV_Ptype $0\dec31_dec_sub9_SV_Ptype[1:0] + end + attribute \src "libresoc.v:116753.3-116807.6" + process $proc$libresoc.v:116753$4388 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_in1_sel[2:0] $1\dec31_dec_sub9_in1_sel[2:0] + attribute \src "libresoc.v:116754.5-116754.29" + switch \initial + attribute \src "libresoc.v:116754.9-116754.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + case + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub9_in1_sel $0\dec31_dec_sub9_in1_sel[2:0] + end + attribute \src "libresoc.v:116808.3-116862.6" + process $proc$libresoc.v:116808$4389 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_in2_sel[3:0] $1\dec31_dec_sub9_in2_sel[3:0] + attribute \src "libresoc.v:116809.5-116809.29" + switch \initial + attribute \src "libresoc.v:116809.9-116809.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 + case + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub9_in2_sel $0\dec31_dec_sub9_in2_sel[3:0] + end + attribute \src "libresoc.v:116863.3-116917.6" + process $proc$libresoc.v:116863$4390 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_in3_sel[1:0] $1\dec31_dec_sub9_in3_sel[1:0] + attribute \src "libresoc.v:116864.5-116864.29" + switch \initial + attribute \src "libresoc.v:116864.9-116864.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub9_in3_sel $0\dec31_dec_sub9_in3_sel[1:0] + end + attribute \src "libresoc.v:116918.3-116972.6" + process $proc$libresoc.v:116918$4391 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_out_sel[1:0] $1\dec31_dec_sub9_out_sel[1:0] + attribute \src "libresoc.v:116919.5-116919.29" + switch \initial + attribute \src "libresoc.v:116919.9-116919.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 + case + assign $1\dec31_dec_sub9_out_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub9_out_sel $0\dec31_dec_sub9_out_sel[1:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "libresoc.v:116978.1-117826.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec58" +attribute \generator "nMigen" +module \dec58 + attribute \src "libresoc.v:117729.3-117744.6" + wire width 2 $0\dec58_SV_Etype[1:0] + attribute \src "libresoc.v:117745.3-117760.6" + wire width 2 $0\dec58_SV_Ptype[1:0] + attribute \src "libresoc.v:117537.3-117552.6" + wire width 8 $0\dec58_asmcode[7:0] + attribute \src "libresoc.v:117601.3-117616.6" + wire $0\dec58_br[0:0] + attribute \src "libresoc.v:117329.3-117344.6" + wire width 3 $0\dec58_cr_in[2:0] + attribute \src "libresoc.v:117345.3-117360.6" + wire width 3 $0\dec58_cr_out[2:0] + attribute \src "libresoc.v:117521.3-117536.6" + wire width 2 $0\dec58_cry_in[1:0] + attribute \src "libresoc.v:117585.3-117600.6" + wire $0\dec58_cry_out[0:0] + attribute \src "libresoc.v:117665.3-117680.6" + wire width 5 $0\dec58_form[4:0] + attribute \src "libresoc.v:117313.3-117328.6" + wire width 13 $0\dec58_function_unit[12:0] + attribute \src "libresoc.v:117761.3-117776.6" + wire width 3 $0\dec58_in1_sel[2:0] + attribute \src "libresoc.v:117777.3-117792.6" + wire width 4 $0\dec58_in2_sel[3:0] + attribute \src "libresoc.v:117793.3-117808.6" + wire width 2 $0\dec58_in3_sel[1:0] + attribute \src "libresoc.v:117489.3-117504.6" + wire width 7 $0\dec58_internal_op[6:0] + attribute \src "libresoc.v:117553.3-117568.6" + wire $0\dec58_inv_a[0:0] + attribute \src "libresoc.v:117569.3-117584.6" + wire $0\dec58_inv_out[0:0] + attribute \src "libresoc.v:117649.3-117664.6" + wire $0\dec58_is_32b[0:0] + attribute \src "libresoc.v:117457.3-117472.6" + wire width 4 $0\dec58_ldst_len[3:0] + attribute \src "libresoc.v:117697.3-117712.6" + wire $0\dec58_lk[0:0] + attribute \src "libresoc.v:117809.3-117824.6" + wire width 2 $0\dec58_out_sel[1:0] + attribute \src "libresoc.v:117505.3-117520.6" + wire width 2 $0\dec58_rc_sel[1:0] + attribute \src "libresoc.v:117633.3-117648.6" + wire $0\dec58_rsrv[0:0] + attribute \src "libresoc.v:117713.3-117728.6" + wire $0\dec58_sgl_pipe[0:0] + attribute \src "libresoc.v:117681.3-117696.6" + wire $0\dec58_sgn[0:0] + attribute \src "libresoc.v:117617.3-117632.6" + wire $0\dec58_sgn_ext[0:0] + attribute \src "libresoc.v:117425.3-117440.6" + wire width 3 $0\dec58_sv_cr_in[2:0] + attribute \src "libresoc.v:117441.3-117456.6" + wire width 3 $0\dec58_sv_cr_out[2:0] + attribute \src "libresoc.v:117361.3-117376.6" + wire width 3 $0\dec58_sv_in1[2:0] + attribute \src "libresoc.v:117377.3-117392.6" + wire width 3 $0\dec58_sv_in2[2:0] + attribute \src "libresoc.v:117393.3-117408.6" + wire width 3 $0\dec58_sv_in3[2:0] + attribute \src "libresoc.v:117409.3-117424.6" + wire width 3 $0\dec58_sv_out[2:0] + attribute \src "libresoc.v:117473.3-117488.6" + wire width 2 $0\dec58_upd[1:0] + attribute \src "libresoc.v:116979.7-116979.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:117729.3-117744.6" + wire width 2 $1\dec58_SV_Etype[1:0] + attribute \src "libresoc.v:117745.3-117760.6" + wire width 2 $1\dec58_SV_Ptype[1:0] + attribute \src "libresoc.v:117537.3-117552.6" + wire width 8 $1\dec58_asmcode[7:0] + attribute \src "libresoc.v:117601.3-117616.6" + wire $1\dec58_br[0:0] + attribute \src "libresoc.v:117329.3-117344.6" + wire width 3 $1\dec58_cr_in[2:0] + attribute \src "libresoc.v:117345.3-117360.6" + wire width 3 $1\dec58_cr_out[2:0] + attribute \src "libresoc.v:117521.3-117536.6" + wire width 2 $1\dec58_cry_in[1:0] + attribute \src "libresoc.v:117585.3-117600.6" + wire $1\dec58_cry_out[0:0] + attribute \src "libresoc.v:117665.3-117680.6" + wire width 5 $1\dec58_form[4:0] + attribute \src "libresoc.v:117313.3-117328.6" + wire width 13 $1\dec58_function_unit[12:0] + attribute \src "libresoc.v:117761.3-117776.6" + wire width 3 $1\dec58_in1_sel[2:0] + attribute \src "libresoc.v:117777.3-117792.6" + wire width 4 $1\dec58_in2_sel[3:0] + attribute \src "libresoc.v:117793.3-117808.6" + wire width 2 $1\dec58_in3_sel[1:0] + attribute \src "libresoc.v:117489.3-117504.6" + wire width 7 $1\dec58_internal_op[6:0] + attribute \src "libresoc.v:117553.3-117568.6" + wire $1\dec58_inv_a[0:0] + attribute \src "libresoc.v:117569.3-117584.6" + wire $1\dec58_inv_out[0:0] + attribute \src "libresoc.v:117649.3-117664.6" + wire $1\dec58_is_32b[0:0] + attribute \src "libresoc.v:117457.3-117472.6" + wire width 4 $1\dec58_ldst_len[3:0] + attribute \src "libresoc.v:117697.3-117712.6" + wire $1\dec58_lk[0:0] + attribute \src "libresoc.v:117809.3-117824.6" + wire width 2 $1\dec58_out_sel[1:0] + attribute \src "libresoc.v:117505.3-117520.6" + wire width 2 $1\dec58_rc_sel[1:0] + attribute \src "libresoc.v:117633.3-117648.6" + wire $1\dec58_rsrv[0:0] + attribute \src "libresoc.v:117713.3-117728.6" + wire $1\dec58_sgl_pipe[0:0] + attribute \src "libresoc.v:117681.3-117696.6" + wire $1\dec58_sgn[0:0] + attribute \src "libresoc.v:117617.3-117632.6" + wire $1\dec58_sgn_ext[0:0] + attribute \src "libresoc.v:117425.3-117440.6" + wire width 3 $1\dec58_sv_cr_in[2:0] + attribute \src "libresoc.v:117441.3-117456.6" + wire width 3 $1\dec58_sv_cr_out[2:0] + attribute \src "libresoc.v:117361.3-117376.6" + wire width 3 $1\dec58_sv_in1[2:0] + attribute \src "libresoc.v:117377.3-117392.6" + wire width 3 $1\dec58_sv_in2[2:0] + attribute \src "libresoc.v:117393.3-117408.6" + wire width 3 $1\dec58_sv_in3[2:0] + attribute \src "libresoc.v:117409.3-117424.6" + wire width 3 $1\dec58_sv_out[2:0] + attribute \src "libresoc.v:117473.3-117488.6" + wire width 2 $1\dec58_upd[1:0] + attribute \enum_base_type "SVEtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "EXTRA2" + attribute \enum_value_10 "EXTRA3" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 5 \dec58_SV_Etype + attribute \enum_base_type "SVPtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "P1" + attribute \enum_value_10 "P2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 6 \dec58_SV_Ptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 8 output 4 \dec58_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 26 \dec58_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 11 \dec58_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 12 \dec58_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 22 \dec58_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 25 \dec58_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 5 output 3 \dec58_form + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 13 output 1 \dec58_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 7 \dec58_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 8 \dec58_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 9 \dec58_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 output 2 \dec58_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 23 \dec58_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 24 \dec58_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 29 \dec58_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 19 \dec58_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 31 \dec58_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 10 \dec58_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 21 \dec58_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 28 \dec58_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 32 \dec58_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 30 \dec58_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 27 \dec58_sgn_ext + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 17 \dec58_sv_cr_in + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 18 \dec58_sv_cr_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 13 \dec58_sv_in1 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 14 \dec58_sv_in2 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 15 \dec58_sv_in3 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 16 \dec58_sv_out + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 20 \dec58_upd + attribute \src "libresoc.v:116979.7-116979.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + wire width 32 input 33 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + wire width 2 \opcode_switch + attribute \src "libresoc.v:116979.7-116979.20" + process $proc$libresoc.v:116979$4425 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:117313.3-117328.6" + process $proc$libresoc.v:117313$4393 + assign { } { } + assign { } { } + assign $0\dec58_function_unit[12:0] $1\dec58_function_unit[12:0] + attribute \src "libresoc.v:117314.5-117314.29" + switch \initial + attribute \src "libresoc.v:117314.9-117314.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_function_unit[12:0] 13'0000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_function_unit[12:0] 13'0000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_function_unit[12:0] 13'0000000000100 + case + assign $1\dec58_function_unit[12:0] 13'0000000000000 + end + sync always + update \dec58_function_unit $0\dec58_function_unit[12:0] + end + attribute \src "libresoc.v:117329.3-117344.6" + process $proc$libresoc.v:117329$4394 + assign { } { } + assign { } { } + assign $0\dec58_cr_in[2:0] $1\dec58_cr_in[2:0] + attribute \src "libresoc.v:117330.5-117330.29" + switch \initial + attribute \src "libresoc.v:117330.9-117330.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_cr_in[2:0] 3'000 + case + assign $1\dec58_cr_in[2:0] 3'000 + end + sync always + update \dec58_cr_in $0\dec58_cr_in[2:0] + end + attribute \src "libresoc.v:117345.3-117360.6" + process $proc$libresoc.v:117345$4395 + assign { } { } + assign { } { } + assign $0\dec58_cr_out[2:0] $1\dec58_cr_out[2:0] + attribute \src "libresoc.v:117346.5-117346.29" + switch \initial + attribute \src "libresoc.v:117346.9-117346.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_cr_out[2:0] 3'000 + case + assign $1\dec58_cr_out[2:0] 3'000 + end + sync always + update \dec58_cr_out $0\dec58_cr_out[2:0] + end + attribute \src "libresoc.v:117361.3-117376.6" + process $proc$libresoc.v:117361$4396 + assign { } { } + assign { } { } + assign $0\dec58_sv_in1[2:0] $1\dec58_sv_in1[2:0] + attribute \src "libresoc.v:117362.5-117362.29" + switch \initial + attribute \src "libresoc.v:117362.9-117362.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_sv_in1[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_sv_in1[2:0] 3'010 + case + assign $1\dec58_sv_in1[2:0] 3'000 + end + sync always + update \dec58_sv_in1 $0\dec58_sv_in1[2:0] + end + attribute \src "libresoc.v:117377.3-117392.6" + process $proc$libresoc.v:117377$4397 + assign { } { } + assign { } { } + assign $0\dec58_sv_in2[2:0] $1\dec58_sv_in2[2:0] + attribute \src "libresoc.v:117378.5-117378.29" + switch \initial + attribute \src "libresoc.v:117378.9-117378.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_sv_in2[2:0] 3'000 + case + assign $1\dec58_sv_in2[2:0] 3'000 + end + sync always + update \dec58_sv_in2 $0\dec58_sv_in2[2:0] + end + attribute \src "libresoc.v:117393.3-117408.6" + process $proc$libresoc.v:117393$4398 + assign { } { } + assign { } { } + assign $0\dec58_sv_in3[2:0] $1\dec58_sv_in3[2:0] + attribute \src "libresoc.v:117394.5-117394.29" + switch \initial + attribute \src "libresoc.v:117394.9-117394.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_sv_in3[2:0] 3'000 + case + assign $1\dec58_sv_in3[2:0] 3'000 + end + sync always + update \dec58_sv_in3 $0\dec58_sv_in3[2:0] + end + attribute \src "libresoc.v:117409.3-117424.6" + process $proc$libresoc.v:117409$4399 + assign { } { } + assign { } { } + assign $0\dec58_sv_out[2:0] $1\dec58_sv_out[2:0] + attribute \src "libresoc.v:117410.5-117410.29" + switch \initial + attribute \src "libresoc.v:117410.9-117410.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_sv_out[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_sv_out[2:0] 3'001 + case + assign $1\dec58_sv_out[2:0] 3'000 + end + sync always + update \dec58_sv_out $0\dec58_sv_out[2:0] + end + attribute \src "libresoc.v:117425.3-117440.6" + process $proc$libresoc.v:117425$4400 + assign { } { } + assign { } { } + assign $0\dec58_sv_cr_in[2:0] $1\dec58_sv_cr_in[2:0] + attribute \src "libresoc.v:117426.5-117426.29" + switch \initial + attribute \src "libresoc.v:117426.9-117426.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_sv_cr_in[2:0] 3'000 + case + assign $1\dec58_sv_cr_in[2:0] 3'000 + end + sync always + update \dec58_sv_cr_in $0\dec58_sv_cr_in[2:0] + end + attribute \src "libresoc.v:117441.3-117456.6" + process $proc$libresoc.v:117441$4401 + assign { } { } + assign { } { } + assign $0\dec58_sv_cr_out[2:0] $1\dec58_sv_cr_out[2:0] + attribute \src "libresoc.v:117442.5-117442.29" + switch \initial + attribute \src "libresoc.v:117442.9-117442.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_sv_cr_out[2:0] 3'000 + case + assign $1\dec58_sv_cr_out[2:0] 3'000 + end + sync always + update \dec58_sv_cr_out $0\dec58_sv_cr_out[2:0] + end + attribute \src "libresoc.v:117457.3-117472.6" + process $proc$libresoc.v:117457$4402 + assign { } { } + assign { } { } + assign $0\dec58_ldst_len[3:0] $1\dec58_ldst_len[3:0] + attribute \src "libresoc.v:117458.5-117458.29" + switch \initial + attribute \src "libresoc.v:117458.9-117458.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_ldst_len[3:0] 4'0100 + case + assign $1\dec58_ldst_len[3:0] 4'0000 + end + sync always + update \dec58_ldst_len $0\dec58_ldst_len[3:0] + end + attribute \src "libresoc.v:117473.3-117488.6" + process $proc$libresoc.v:117473$4403 + assign { } { } + assign { } { } + assign $0\dec58_upd[1:0] $1\dec58_upd[1:0] + attribute \src "libresoc.v:117474.5-117474.29" + switch \initial + attribute \src "libresoc.v:117474.9-117474.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_upd[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_upd[1:0] 2'00 + case + assign $1\dec58_upd[1:0] 2'00 + end + sync always + update \dec58_upd $0\dec58_upd[1:0] + end + attribute \src "libresoc.v:117489.3-117504.6" + process $proc$libresoc.v:117489$4404 + assign { } { } + assign { } { } + assign $0\dec58_internal_op[6:0] $1\dec58_internal_op[6:0] + attribute \src "libresoc.v:117490.5-117490.29" + switch \initial + attribute \src "libresoc.v:117490.9-117490.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_internal_op[6:0] 7'0100101 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_internal_op[6:0] 7'0100101 + case + assign $1\dec58_internal_op[6:0] 7'0000000 + end + sync always + update \dec58_internal_op $0\dec58_internal_op[6:0] + end + attribute \src "libresoc.v:117505.3-117520.6" + process $proc$libresoc.v:117505$4405 + assign { } { } + assign { } { } + assign $0\dec58_rc_sel[1:0] $1\dec58_rc_sel[1:0] + attribute \src "libresoc.v:117506.5-117506.29" + switch \initial + attribute \src "libresoc.v:117506.9-117506.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_rc_sel[1:0] 2'00 + case + assign $1\dec58_rc_sel[1:0] 2'00 + end + sync always + update \dec58_rc_sel $0\dec58_rc_sel[1:0] + end + attribute \src "libresoc.v:117521.3-117536.6" + process $proc$libresoc.v:117521$4406 + assign { } { } + assign { } { } + assign $0\dec58_cry_in[1:0] $1\dec58_cry_in[1:0] + attribute \src "libresoc.v:117522.5-117522.29" + switch \initial + attribute \src "libresoc.v:117522.9-117522.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_cry_in[1:0] 2'00 + case + assign $1\dec58_cry_in[1:0] 2'00 + end + sync always + update \dec58_cry_in $0\dec58_cry_in[1:0] + end + attribute \src "libresoc.v:117537.3-117552.6" + process $proc$libresoc.v:117537$4407 + assign { } { } + assign { } { } + assign $0\dec58_asmcode[7:0] $1\dec58_asmcode[7:0] + attribute \src "libresoc.v:117538.5-117538.29" + switch \initial + attribute \src "libresoc.v:117538.9-117538.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_asmcode[7:0] 8'01010010 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_asmcode[7:0] 8'01010101 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_asmcode[7:0] 8'01100010 + case + assign $1\dec58_asmcode[7:0] 8'00000000 + end + sync always + update \dec58_asmcode $0\dec58_asmcode[7:0] + end + attribute \src "libresoc.v:117553.3-117568.6" + process $proc$libresoc.v:117553$4408 + assign { } { } + assign { } { } + assign $0\dec58_inv_a[0:0] $1\dec58_inv_a[0:0] + attribute \src "libresoc.v:117554.5-117554.29" + switch \initial + attribute \src "libresoc.v:117554.9-117554.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_inv_a[0:0] 1'0 + case + assign $1\dec58_inv_a[0:0] 1'0 + end + sync always + update \dec58_inv_a $0\dec58_inv_a[0:0] + end + attribute \src "libresoc.v:117569.3-117584.6" + process $proc$libresoc.v:117569$4409 + assign { } { } + assign { } { } + assign $0\dec58_inv_out[0:0] $1\dec58_inv_out[0:0] + attribute \src "libresoc.v:117570.5-117570.29" + switch \initial + attribute \src "libresoc.v:117570.9-117570.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_inv_out[0:0] 1'0 + case + assign $1\dec58_inv_out[0:0] 1'0 + end + sync always + update \dec58_inv_out $0\dec58_inv_out[0:0] + end + attribute \src "libresoc.v:117585.3-117600.6" + process $proc$libresoc.v:117585$4410 + assign { } { } + assign { } { } + assign $0\dec58_cry_out[0:0] $1\dec58_cry_out[0:0] + attribute \src "libresoc.v:117586.5-117586.29" + switch \initial + attribute \src "libresoc.v:117586.9-117586.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_cry_out[0:0] 1'0 + case + assign $1\dec58_cry_out[0:0] 1'0 + end + sync always + update \dec58_cry_out $0\dec58_cry_out[0:0] + end + attribute \src "libresoc.v:117601.3-117616.6" + process $proc$libresoc.v:117601$4411 + assign { } { } + assign { } { } + assign $0\dec58_br[0:0] $1\dec58_br[0:0] + attribute \src "libresoc.v:117602.5-117602.29" + switch \initial + attribute \src "libresoc.v:117602.9-117602.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_br[0:0] 1'0 + case + assign $1\dec58_br[0:0] 1'0 + end + sync always + update \dec58_br $0\dec58_br[0:0] + end + attribute \src "libresoc.v:117617.3-117632.6" + process $proc$libresoc.v:117617$4412 + assign { } { } + assign { } { } + assign $0\dec58_sgn_ext[0:0] $1\dec58_sgn_ext[0:0] + attribute \src "libresoc.v:117618.5-117618.29" + switch \initial + attribute \src "libresoc.v:117618.9-117618.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_sgn_ext[0:0] 1'1 + case + assign $1\dec58_sgn_ext[0:0] 1'0 + end + sync always + update \dec58_sgn_ext $0\dec58_sgn_ext[0:0] + end + attribute \src "libresoc.v:117633.3-117648.6" + process $proc$libresoc.v:117633$4413 + assign { } { } + assign { } { } + assign $0\dec58_rsrv[0:0] $1\dec58_rsrv[0:0] + attribute \src "libresoc.v:117634.5-117634.29" + switch \initial + attribute \src "libresoc.v:117634.9-117634.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_rsrv[0:0] 1'0 + case + assign $1\dec58_rsrv[0:0] 1'0 + end + sync always + update \dec58_rsrv $0\dec58_rsrv[0:0] + end + attribute \src "libresoc.v:117649.3-117664.6" + process $proc$libresoc.v:117649$4414 + assign { } { } + assign { } { } + assign $0\dec58_is_32b[0:0] $1\dec58_is_32b[0:0] + attribute \src "libresoc.v:117650.5-117650.29" + switch \initial + attribute \src "libresoc.v:117650.9-117650.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_is_32b[0:0] 1'0 + case + assign $1\dec58_is_32b[0:0] 1'0 + end + sync always + update \dec58_is_32b $0\dec58_is_32b[0:0] + end + attribute \src "libresoc.v:117665.3-117680.6" + process $proc$libresoc.v:117665$4415 + assign { } { } + assign { } { } + assign $0\dec58_form[4:0] $1\dec58_form[4:0] + attribute \src "libresoc.v:117666.5-117666.29" + switch \initial + attribute \src "libresoc.v:117666.9-117666.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_form[4:0] 5'00101 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_form[4:0] 5'00101 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_form[4:0] 5'00101 + case + assign $1\dec58_form[4:0] 5'00000 + end + sync always + update \dec58_form $0\dec58_form[4:0] + end + attribute \src "libresoc.v:117681.3-117696.6" + process $proc$libresoc.v:117681$4416 + assign { } { } + assign { } { } + assign $0\dec58_sgn[0:0] $1\dec58_sgn[0:0] + attribute \src "libresoc.v:117682.5-117682.29" + switch \initial + attribute \src "libresoc.v:117682.9-117682.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_sgn[0:0] 1'0 + case + assign $1\dec58_sgn[0:0] 1'0 + end + sync always + update \dec58_sgn $0\dec58_sgn[0:0] + end + attribute \src "libresoc.v:117697.3-117712.6" + process $proc$libresoc.v:117697$4417 + assign { } { } + assign { } { } + assign $0\dec58_lk[0:0] $1\dec58_lk[0:0] + attribute \src "libresoc.v:117698.5-117698.29" + switch \initial + attribute \src "libresoc.v:117698.9-117698.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_lk[0:0] 1'0 + case + assign $1\dec58_lk[0:0] 1'0 + end + sync always + update \dec58_lk $0\dec58_lk[0:0] + end + attribute \src "libresoc.v:117713.3-117728.6" + process $proc$libresoc.v:117713$4418 + assign { } { } + assign { } { } + assign $0\dec58_sgl_pipe[0:0] $1\dec58_sgl_pipe[0:0] + attribute \src "libresoc.v:117714.5-117714.29" + switch \initial + attribute \src "libresoc.v:117714.9-117714.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_sgl_pipe[0:0] 1'1 + case + assign $1\dec58_sgl_pipe[0:0] 1'0 + end + sync always + update \dec58_sgl_pipe $0\dec58_sgl_pipe[0:0] + end + attribute \src "libresoc.v:117729.3-117744.6" + process $proc$libresoc.v:117729$4419 + assign { } { } + assign { } { } + assign $0\dec58_SV_Etype[1:0] $1\dec58_SV_Etype[1:0] + attribute \src "libresoc.v:117730.5-117730.29" + switch \initial + attribute \src "libresoc.v:117730.9-117730.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_SV_Etype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_SV_Etype[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_SV_Etype[1:0] 2'10 + case + assign $1\dec58_SV_Etype[1:0] 2'00 + end + sync always + update \dec58_SV_Etype $0\dec58_SV_Etype[1:0] + end + attribute \src "libresoc.v:117745.3-117760.6" + process $proc$libresoc.v:117745$4420 + assign { } { } + assign { } { } + assign $0\dec58_SV_Ptype[1:0] $1\dec58_SV_Ptype[1:0] + attribute \src "libresoc.v:117746.5-117746.29" + switch \initial + attribute \src "libresoc.v:117746.9-117746.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_SV_Ptype[1:0] 2'10 + case + assign $1\dec58_SV_Ptype[1:0] 2'00 + end + sync always + update \dec58_SV_Ptype $0\dec58_SV_Ptype[1:0] + end + attribute \src "libresoc.v:117761.3-117776.6" + process $proc$libresoc.v:117761$4421 + assign { } { } + assign { } { } + assign $0\dec58_in1_sel[2:0] $1\dec58_in1_sel[2:0] + attribute \src "libresoc.v:117762.5-117762.29" + switch \initial + attribute \src "libresoc.v:117762.9-117762.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_in1_sel[2:0] 3'010 + case + assign $1\dec58_in1_sel[2:0] 3'000 + end + sync always + update \dec58_in1_sel $0\dec58_in1_sel[2:0] + end + attribute \src "libresoc.v:117777.3-117792.6" + process $proc$libresoc.v:117777$4422 + assign { } { } + assign { } { } + assign $0\dec58_in2_sel[3:0] $1\dec58_in2_sel[3:0] + attribute \src "libresoc.v:117778.5-117778.29" + switch \initial + attribute \src "libresoc.v:117778.9-117778.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_in2_sel[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_in2_sel[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_in2_sel[3:0] 4'1000 + case + assign $1\dec58_in2_sel[3:0] 4'0000 + end + sync always + update \dec58_in2_sel $0\dec58_in2_sel[3:0] + end + attribute \src "libresoc.v:117793.3-117808.6" + process $proc$libresoc.v:117793$4423 + assign { } { } + assign { } { } + assign $0\dec58_in3_sel[1:0] $1\dec58_in3_sel[1:0] + attribute \src "libresoc.v:117794.5-117794.29" + switch \initial + attribute \src "libresoc.v:117794.9-117794.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_in3_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_in3_sel[1:0] 2'00 + case + assign $1\dec58_in3_sel[1:0] 2'00 + end + sync always + update \dec58_in3_sel $0\dec58_in3_sel[1:0] + end + attribute \src "libresoc.v:117809.3-117824.6" + process $proc$libresoc.v:117809$4424 + assign { } { } + assign { } { } + assign $0\dec58_out_sel[1:0] $1\dec58_out_sel[1:0] + attribute \src "libresoc.v:117810.5-117810.29" + switch \initial + attribute \src "libresoc.v:117810.9-117810.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_out_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_out_sel[1:0] 2'01 + case + assign $1\dec58_out_sel[1:0] 2'00 + end + sync always + update \dec58_out_sel $0\dec58_out_sel[1:0] + end + connect \opcode_switch \opcode_in [1:0] +end +attribute \src "libresoc.v:117830.1-118582.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec62" +attribute \generator "nMigen" +module \dec62 + attribute \src "libresoc.v:118503.3-118515.6" + wire width 2 $0\dec62_SV_Etype[1:0] + attribute \src "libresoc.v:118516.3-118528.6" + wire width 2 $0\dec62_SV_Ptype[1:0] + attribute \src "libresoc.v:118347.3-118359.6" + wire width 8 $0\dec62_asmcode[7:0] + attribute \src "libresoc.v:118399.3-118411.6" + wire $0\dec62_br[0:0] + attribute \src "libresoc.v:118178.3-118190.6" + wire width 3 $0\dec62_cr_in[2:0] + attribute \src "libresoc.v:118191.3-118203.6" + wire width 3 $0\dec62_cr_out[2:0] + attribute \src "libresoc.v:118334.3-118346.6" + wire width 2 $0\dec62_cry_in[1:0] + attribute \src "libresoc.v:118386.3-118398.6" + wire $0\dec62_cry_out[0:0] + attribute \src "libresoc.v:118451.3-118463.6" + wire width 5 $0\dec62_form[4:0] + attribute \src "libresoc.v:118165.3-118177.6" + wire width 13 $0\dec62_function_unit[12:0] + attribute \src "libresoc.v:118529.3-118541.6" + wire width 3 $0\dec62_in1_sel[2:0] + attribute \src "libresoc.v:118542.3-118554.6" + wire width 4 $0\dec62_in2_sel[3:0] + attribute \src "libresoc.v:118555.3-118567.6" + wire width 2 $0\dec62_in3_sel[1:0] + attribute \src "libresoc.v:118308.3-118320.6" + wire width 7 $0\dec62_internal_op[6:0] + attribute \src "libresoc.v:118360.3-118372.6" + wire $0\dec62_inv_a[0:0] + attribute \src "libresoc.v:118373.3-118385.6" + wire $0\dec62_inv_out[0:0] + attribute \src "libresoc.v:118438.3-118450.6" + wire $0\dec62_is_32b[0:0] + attribute \src "libresoc.v:118282.3-118294.6" + wire width 4 $0\dec62_ldst_len[3:0] + attribute \src "libresoc.v:118477.3-118489.6" + wire $0\dec62_lk[0:0] + attribute \src "libresoc.v:118568.3-118580.6" + wire width 2 $0\dec62_out_sel[1:0] + attribute \src "libresoc.v:118321.3-118333.6" + wire width 2 $0\dec62_rc_sel[1:0] + attribute \src "libresoc.v:118425.3-118437.6" + wire $0\dec62_rsrv[0:0] + attribute \src "libresoc.v:118490.3-118502.6" + wire $0\dec62_sgl_pipe[0:0] + attribute \src "libresoc.v:118464.3-118476.6" + wire $0\dec62_sgn[0:0] + attribute \src "libresoc.v:118412.3-118424.6" + wire $0\dec62_sgn_ext[0:0] + attribute \src "libresoc.v:118256.3-118268.6" + wire width 3 $0\dec62_sv_cr_in[2:0] + attribute \src "libresoc.v:118269.3-118281.6" + wire width 3 $0\dec62_sv_cr_out[2:0] + attribute \src "libresoc.v:118204.3-118216.6" + wire width 3 $0\dec62_sv_in1[2:0] + attribute \src "libresoc.v:118217.3-118229.6" + wire width 3 $0\dec62_sv_in2[2:0] + attribute \src "libresoc.v:118230.3-118242.6" + wire width 3 $0\dec62_sv_in3[2:0] + attribute \src "libresoc.v:118243.3-118255.6" + wire width 3 $0\dec62_sv_out[2:0] + attribute \src "libresoc.v:118295.3-118307.6" + wire width 2 $0\dec62_upd[1:0] + attribute \src "libresoc.v:117831.7-117831.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:118503.3-118515.6" + wire width 2 $1\dec62_SV_Etype[1:0] + attribute \src "libresoc.v:118516.3-118528.6" + wire width 2 $1\dec62_SV_Ptype[1:0] + attribute \src "libresoc.v:118347.3-118359.6" + wire width 8 $1\dec62_asmcode[7:0] + attribute \src "libresoc.v:118399.3-118411.6" + wire $1\dec62_br[0:0] + attribute \src "libresoc.v:118178.3-118190.6" + wire width 3 $1\dec62_cr_in[2:0] + attribute \src "libresoc.v:118191.3-118203.6" + wire width 3 $1\dec62_cr_out[2:0] + attribute \src "libresoc.v:118334.3-118346.6" + wire width 2 $1\dec62_cry_in[1:0] + attribute \src "libresoc.v:118386.3-118398.6" + wire $1\dec62_cry_out[0:0] + attribute \src "libresoc.v:118451.3-118463.6" + wire width 5 $1\dec62_form[4:0] + attribute \src "libresoc.v:118165.3-118177.6" + wire width 13 $1\dec62_function_unit[12:0] + attribute \src "libresoc.v:118529.3-118541.6" + wire width 3 $1\dec62_in1_sel[2:0] + attribute \src "libresoc.v:118542.3-118554.6" + wire width 4 $1\dec62_in2_sel[3:0] + attribute \src "libresoc.v:118555.3-118567.6" + wire width 2 $1\dec62_in3_sel[1:0] + attribute \src "libresoc.v:118308.3-118320.6" + wire width 7 $1\dec62_internal_op[6:0] + attribute \src "libresoc.v:118360.3-118372.6" + wire $1\dec62_inv_a[0:0] + attribute \src "libresoc.v:118373.3-118385.6" + wire $1\dec62_inv_out[0:0] + attribute \src "libresoc.v:118438.3-118450.6" + wire $1\dec62_is_32b[0:0] + attribute \src "libresoc.v:118282.3-118294.6" + wire width 4 $1\dec62_ldst_len[3:0] + attribute \src "libresoc.v:118477.3-118489.6" + wire $1\dec62_lk[0:0] + attribute \src "libresoc.v:118568.3-118580.6" + wire width 2 $1\dec62_out_sel[1:0] + attribute \src "libresoc.v:118321.3-118333.6" + wire width 2 $1\dec62_rc_sel[1:0] + attribute \src "libresoc.v:118425.3-118437.6" + wire $1\dec62_rsrv[0:0] + attribute \src "libresoc.v:118490.3-118502.6" + wire $1\dec62_sgl_pipe[0:0] + attribute \src "libresoc.v:118464.3-118476.6" + wire $1\dec62_sgn[0:0] + attribute \src "libresoc.v:118412.3-118424.6" + wire $1\dec62_sgn_ext[0:0] + attribute \src "libresoc.v:118256.3-118268.6" + wire width 3 $1\dec62_sv_cr_in[2:0] + attribute \src "libresoc.v:118269.3-118281.6" + wire width 3 $1\dec62_sv_cr_out[2:0] + attribute \src "libresoc.v:118204.3-118216.6" + wire width 3 $1\dec62_sv_in1[2:0] + attribute \src "libresoc.v:118217.3-118229.6" + wire width 3 $1\dec62_sv_in2[2:0] + attribute \src "libresoc.v:118230.3-118242.6" + wire width 3 $1\dec62_sv_in3[2:0] + attribute \src "libresoc.v:118243.3-118255.6" + wire width 3 $1\dec62_sv_out[2:0] + attribute \src "libresoc.v:118295.3-118307.6" + wire width 2 $1\dec62_upd[1:0] + attribute \enum_base_type "SVEtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "EXTRA2" + attribute \enum_value_10 "EXTRA3" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 5 \dec62_SV_Etype + attribute \enum_base_type "SVPtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "P1" + attribute \enum_value_10 "P2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 6 \dec62_SV_Ptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 8 output 4 \dec62_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 26 \dec62_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 11 \dec62_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 12 \dec62_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 22 \dec62_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 25 \dec62_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 5 output 3 \dec62_form + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 13 output 1 \dec62_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 7 \dec62_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 8 \dec62_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 9 \dec62_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 output 2 \dec62_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 23 \dec62_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 24 \dec62_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 29 \dec62_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 output 19 \dec62_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 31 \dec62_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 10 \dec62_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 21 \dec62_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 28 \dec62_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 32 \dec62_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 30 \dec62_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire output 27 \dec62_sgn_ext + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 17 \dec62_sv_cr_in + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 18 \dec62_sv_cr_out + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 13 \dec62_sv_in1 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 14 \dec62_sv_in2 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 15 \dec62_sv_in3 + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 output 16 \dec62_sv_out + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 output 20 \dec62_upd + attribute \src "libresoc.v:117831.7-117831.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + wire width 32 input 33 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:340" + wire width 2 \opcode_switch + attribute \src "libresoc.v:117831.7-117831.20" + process $proc$libresoc.v:117831$4458 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:118165.3-118177.6" + process $proc$libresoc.v:118165$4426 + assign { } { } + assign { } { } + assign $0\dec62_function_unit[12:0] $1\dec62_function_unit[12:0] + attribute \src "libresoc.v:118166.5-118166.29" + switch \initial + attribute \src "libresoc.v:118166.9-118166.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_function_unit[12:0] 13'0000000000100 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_function_unit[12:0] 13'0000000000100 + case + assign $1\dec62_function_unit[12:0] 13'0000000000000 + end + sync always + update \dec62_function_unit $0\dec62_function_unit[12:0] + end + attribute \src "libresoc.v:118178.3-118190.6" + process $proc$libresoc.v:118178$4427 + assign { } { } + assign { } { } + assign $0\dec62_cr_in[2:0] $1\dec62_cr_in[2:0] + attribute \src "libresoc.v:118179.5-118179.29" + switch \initial + attribute \src "libresoc.v:118179.9-118179.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_cr_in[2:0] 3'000 + case + assign $1\dec62_cr_in[2:0] 3'000 + end + sync always + update \dec62_cr_in $0\dec62_cr_in[2:0] + end + attribute \src "libresoc.v:118191.3-118203.6" + process $proc$libresoc.v:118191$4428 + assign { } { } + assign { } { } + assign $0\dec62_cr_out[2:0] $1\dec62_cr_out[2:0] + attribute \src "libresoc.v:118192.5-118192.29" + switch \initial + attribute \src "libresoc.v:118192.9-118192.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_cr_out[2:0] 3'000 + case + assign $1\dec62_cr_out[2:0] 3'000 + end + sync always + update \dec62_cr_out $0\dec62_cr_out[2:0] + end + attribute \src "libresoc.v:118204.3-118216.6" + process $proc$libresoc.v:118204$4429 + assign { } { } + assign { } { } + assign $0\dec62_sv_in1[2:0] $1\dec62_sv_in1[2:0] + attribute \src "libresoc.v:118205.5-118205.29" + switch \initial + attribute \src "libresoc.v:118205.9-118205.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_sv_in1[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_sv_in1[2:0] 3'011 + case + assign $1\dec62_sv_in1[2:0] 3'000 + end + sync always + update \dec62_sv_in1 $0\dec62_sv_in1[2:0] + end + attribute \src "libresoc.v:118217.3-118229.6" + process $proc$libresoc.v:118217$4430 + assign { } { } + assign { } { } + assign $0\dec62_sv_in2[2:0] $1\dec62_sv_in2[2:0] + attribute \src "libresoc.v:118218.5-118218.29" + switch \initial + attribute \src "libresoc.v:118218.9-118218.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_sv_in2[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_sv_in2[2:0] 3'000 + case + assign $1\dec62_sv_in2[2:0] 3'000 + end + sync always + update \dec62_sv_in2 $0\dec62_sv_in2[2:0] + end + attribute \src "libresoc.v:118230.3-118242.6" + process $proc$libresoc.v:118230$4431 + assign { } { } + assign { } { } + assign $0\dec62_sv_in3[2:0] $1\dec62_sv_in3[2:0] + attribute \src "libresoc.v:118231.5-118231.29" + switch \initial + attribute \src "libresoc.v:118231.9-118231.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_sv_in3[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_sv_in3[2:0] 3'010 + case + assign $1\dec62_sv_in3[2:0] 3'000 + end + sync always + update \dec62_sv_in3 $0\dec62_sv_in3[2:0] + end + attribute \src "libresoc.v:118243.3-118255.6" + process $proc$libresoc.v:118243$4432 + assign { } { } + assign { } { } + assign $0\dec62_sv_out[2:0] $1\dec62_sv_out[2:0] + attribute \src "libresoc.v:118244.5-118244.29" + switch \initial + attribute \src "libresoc.v:118244.9-118244.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_sv_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_sv_out[2:0] 3'000 + case + assign $1\dec62_sv_out[2:0] 3'000 + end + sync always + update \dec62_sv_out $0\dec62_sv_out[2:0] + end + attribute \src "libresoc.v:118256.3-118268.6" + process $proc$libresoc.v:118256$4433 + assign { } { } + assign { } { } + assign $0\dec62_sv_cr_in[2:0] $1\dec62_sv_cr_in[2:0] + attribute \src "libresoc.v:118257.5-118257.29" + switch \initial + attribute \src "libresoc.v:118257.9-118257.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_sv_cr_in[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_sv_cr_in[2:0] 3'000 + case + assign $1\dec62_sv_cr_in[2:0] 3'000 + end + sync always + update \dec62_sv_cr_in $0\dec62_sv_cr_in[2:0] + end + attribute \src "libresoc.v:118269.3-118281.6" + process $proc$libresoc.v:118269$4434 + assign { } { } + assign { } { } + assign $0\dec62_sv_cr_out[2:0] $1\dec62_sv_cr_out[2:0] + attribute \src "libresoc.v:118270.5-118270.29" + switch \initial + attribute \src "libresoc.v:118270.9-118270.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_sv_cr_out[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_sv_cr_out[2:0] 3'000 + case + assign $1\dec62_sv_cr_out[2:0] 3'000 + end + sync always + update \dec62_sv_cr_out $0\dec62_sv_cr_out[2:0] + end + attribute \src "libresoc.v:118282.3-118294.6" + process $proc$libresoc.v:118282$4435 + assign { } { } + assign { } { } + assign $0\dec62_ldst_len[3:0] $1\dec62_ldst_len[3:0] + attribute \src "libresoc.v:118283.5-118283.29" + switch \initial + attribute \src "libresoc.v:118283.9-118283.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_ldst_len[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_ldst_len[3:0] 4'1000 + case + assign $1\dec62_ldst_len[3:0] 4'0000 + end + sync always + update \dec62_ldst_len $0\dec62_ldst_len[3:0] + end + attribute \src "libresoc.v:118295.3-118307.6" + process $proc$libresoc.v:118295$4436 + assign { } { } + assign { } { } + assign $0\dec62_upd[1:0] $1\dec62_upd[1:0] + attribute \src "libresoc.v:118296.5-118296.29" + switch \initial + attribute \src "libresoc.v:118296.9-118296.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_upd[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_upd[1:0] 2'01 + case + assign $1\dec62_upd[1:0] 2'00 + end + sync always + update \dec62_upd $0\dec62_upd[1:0] + end + attribute \src "libresoc.v:118308.3-118320.6" + process $proc$libresoc.v:118308$4437 + assign { } { } + assign { } { } + assign $0\dec62_internal_op[6:0] $1\dec62_internal_op[6:0] + attribute \src "libresoc.v:118309.5-118309.29" + switch \initial + attribute \src "libresoc.v:118309.9-118309.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_internal_op[6:0] 7'0100110 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_internal_op[6:0] 7'0100110 + case + assign $1\dec62_internal_op[6:0] 7'0000000 + end + sync always + update \dec62_internal_op $0\dec62_internal_op[6:0] + end + attribute \src "libresoc.v:118321.3-118333.6" + process $proc$libresoc.v:118321$4438 + assign { } { } + assign { } { } + assign $0\dec62_rc_sel[1:0] $1\dec62_rc_sel[1:0] + attribute \src "libresoc.v:118322.5-118322.29" + switch \initial + attribute \src "libresoc.v:118322.9-118322.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_rc_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_rc_sel[1:0] 2'00 + case + assign $1\dec62_rc_sel[1:0] 2'00 + end + sync always + update \dec62_rc_sel $0\dec62_rc_sel[1:0] + end + attribute \src "libresoc.v:118334.3-118346.6" + process $proc$libresoc.v:118334$4439 + assign { } { } + assign { } { } + assign $0\dec62_cry_in[1:0] $1\dec62_cry_in[1:0] + attribute \src "libresoc.v:118335.5-118335.29" + switch \initial + attribute \src "libresoc.v:118335.9-118335.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_cry_in[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_cry_in[1:0] 2'00 + case + assign $1\dec62_cry_in[1:0] 2'00 + end + sync always + update \dec62_cry_in $0\dec62_cry_in[1:0] + end + attribute \src "libresoc.v:118347.3-118359.6" + process $proc$libresoc.v:118347$4440 + assign { } { } + assign { } { } + assign $0\dec62_asmcode[7:0] $1\dec62_asmcode[7:0] + attribute \src "libresoc.v:118348.5-118348.29" + switch \initial + attribute \src "libresoc.v:118348.9-118348.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_asmcode[7:0] 8'10101101 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_asmcode[7:0] 8'10110000 + case + assign $1\dec62_asmcode[7:0] 8'00000000 + end + sync always + update \dec62_asmcode $0\dec62_asmcode[7:0] + end + attribute \src "libresoc.v:118360.3-118372.6" + process $proc$libresoc.v:118360$4441 + assign { } { } + assign { } { } + assign $0\dec62_inv_a[0:0] $1\dec62_inv_a[0:0] + attribute \src "libresoc.v:118361.5-118361.29" + switch \initial + attribute \src "libresoc.v:118361.9-118361.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_inv_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_inv_a[0:0] 1'0 + case + assign $1\dec62_inv_a[0:0] 1'0 + end + sync always + update \dec62_inv_a $0\dec62_inv_a[0:0] + end + attribute \src "libresoc.v:118373.3-118385.6" + process $proc$libresoc.v:118373$4442 + assign { } { } + assign { } { } + assign $0\dec62_inv_out[0:0] $1\dec62_inv_out[0:0] + attribute \src "libresoc.v:118374.5-118374.29" + switch \initial + attribute \src "libresoc.v:118374.9-118374.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_inv_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_inv_out[0:0] 1'0 + case + assign $1\dec62_inv_out[0:0] 1'0 + end + sync always + update \dec62_inv_out $0\dec62_inv_out[0:0] + end + attribute \src "libresoc.v:118386.3-118398.6" + process $proc$libresoc.v:118386$4443 + assign { } { } + assign { } { } + assign $0\dec62_cry_out[0:0] $1\dec62_cry_out[0:0] + attribute \src "libresoc.v:118387.5-118387.29" + switch \initial + attribute \src "libresoc.v:118387.9-118387.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_cry_out[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_cry_out[0:0] 1'0 + case + assign $1\dec62_cry_out[0:0] 1'0 + end + sync always + update \dec62_cry_out $0\dec62_cry_out[0:0] + end + attribute \src "libresoc.v:118399.3-118411.6" + process $proc$libresoc.v:118399$4444 + assign { } { } + assign { } { } + assign $0\dec62_br[0:0] $1\dec62_br[0:0] + attribute \src "libresoc.v:118400.5-118400.29" + switch \initial + attribute \src "libresoc.v:118400.9-118400.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_br[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_br[0:0] 1'0 + case + assign $1\dec62_br[0:0] 1'0 + end + sync always + update \dec62_br $0\dec62_br[0:0] + end + attribute \src "libresoc.v:118412.3-118424.6" + process $proc$libresoc.v:118412$4445 + assign { } { } + assign { } { } + assign $0\dec62_sgn_ext[0:0] $1\dec62_sgn_ext[0:0] + attribute \src "libresoc.v:118413.5-118413.29" + switch \initial + attribute \src "libresoc.v:118413.9-118413.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_sgn_ext[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_sgn_ext[0:0] 1'0 + case + assign $1\dec62_sgn_ext[0:0] 1'0 + end + sync always + update \dec62_sgn_ext $0\dec62_sgn_ext[0:0] + end + attribute \src "libresoc.v:118425.3-118437.6" + process $proc$libresoc.v:118425$4446 + assign { } { } + assign { } { } + assign $0\dec62_rsrv[0:0] $1\dec62_rsrv[0:0] + attribute \src "libresoc.v:118426.5-118426.29" + switch \initial + attribute \src "libresoc.v:118426.9-118426.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_rsrv[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_rsrv[0:0] 1'0 + case + assign $1\dec62_rsrv[0:0] 1'0 + end + sync always + update \dec62_rsrv $0\dec62_rsrv[0:0] + end + attribute \src "libresoc.v:118438.3-118450.6" + process $proc$libresoc.v:118438$4447 + assign { } { } + assign { } { } + assign $0\dec62_is_32b[0:0] $1\dec62_is_32b[0:0] + attribute \src "libresoc.v:118439.5-118439.29" + switch \initial + attribute \src "libresoc.v:118439.9-118439.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_is_32b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_is_32b[0:0] 1'0 + case + assign $1\dec62_is_32b[0:0] 1'0 + end + sync always + update \dec62_is_32b $0\dec62_is_32b[0:0] + end + attribute \src "libresoc.v:118451.3-118463.6" + process $proc$libresoc.v:118451$4448 + assign { } { } + assign { } { } + assign $0\dec62_form[4:0] $1\dec62_form[4:0] + attribute \src "libresoc.v:118452.5-118452.29" + switch \initial + attribute \src "libresoc.v:118452.9-118452.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_form[4:0] 5'00101 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_form[4:0] 5'00101 + case + assign $1\dec62_form[4:0] 5'00000 + end + sync always + update \dec62_form $0\dec62_form[4:0] + end + attribute \src "libresoc.v:118464.3-118476.6" + process $proc$libresoc.v:118464$4449 + assign { } { } + assign { } { } + assign $0\dec62_sgn[0:0] $1\dec62_sgn[0:0] + attribute \src "libresoc.v:118465.5-118465.29" + switch \initial + attribute \src "libresoc.v:118465.9-118465.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_sgn[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_sgn[0:0] 1'0 + case + assign $1\dec62_sgn[0:0] 1'0 + end + sync always + update \dec62_sgn $0\dec62_sgn[0:0] + end + attribute \src "libresoc.v:118477.3-118489.6" + process $proc$libresoc.v:118477$4450 + assign { } { } + assign { } { } + assign $0\dec62_lk[0:0] $1\dec62_lk[0:0] + attribute \src "libresoc.v:118478.5-118478.29" + switch \initial + attribute \src "libresoc.v:118478.9-118478.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_lk[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_lk[0:0] 1'0 + case + assign $1\dec62_lk[0:0] 1'0 + end + sync always + update \dec62_lk $0\dec62_lk[0:0] + end + attribute \src "libresoc.v:118490.3-118502.6" + process $proc$libresoc.v:118490$4451 + assign { } { } + assign { } { } + assign $0\dec62_sgl_pipe[0:0] $1\dec62_sgl_pipe[0:0] + attribute \src "libresoc.v:118491.5-118491.29" + switch \initial + attribute \src "libresoc.v:118491.9-118491.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_sgl_pipe[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_sgl_pipe[0:0] 1'1 + case + assign $1\dec62_sgl_pipe[0:0] 1'0 + end + sync always + update \dec62_sgl_pipe $0\dec62_sgl_pipe[0:0] + end + attribute \src "libresoc.v:118503.3-118515.6" + process $proc$libresoc.v:118503$4452 + assign { } { } + assign { } { } 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_SV_Ptype[1:0] 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_SV_Ptype[1:0] 2'10 + case + assign $1\dec62_SV_Ptype[1:0] 2'00 + end + sync always + update \dec62_SV_Ptype $0\dec62_SV_Ptype[1:0] + end + attribute \src "libresoc.v:118529.3-118541.6" + process $proc$libresoc.v:118529$4454 + assign { } { } + assign { } { } + assign $0\dec62_in1_sel[2:0] $1\dec62_in1_sel[2:0] + attribute \src "libresoc.v:118530.5-118530.29" + switch \initial + attribute \src "libresoc.v:118530.9-118530.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_in1_sel[2:0] 3'010 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_in1_sel[2:0] 3'010 + case + assign $1\dec62_in1_sel[2:0] 3'000 + end + sync always + update \dec62_in1_sel $0\dec62_in1_sel[2:0] + end + attribute \src "libresoc.v:118542.3-118554.6" + process $proc$libresoc.v:118542$4455 + assign { } { } + assign { } { } + assign $0\dec62_in2_sel[3:0] $1\dec62_in2_sel[3:0] + attribute \src "libresoc.v:118543.5-118543.29" + switch \initial + attribute \src "libresoc.v:118543.9-118543.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_in2_sel[3:0] 4'1000 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_in2_sel[3:0] 4'1000 + case + assign $1\dec62_in2_sel[3:0] 4'0000 + end + sync always + update \dec62_in2_sel $0\dec62_in2_sel[3:0] + end + attribute \src "libresoc.v:118555.3-118567.6" + process $proc$libresoc.v:118555$4456 + assign { } { } + assign { } { } + assign $0\dec62_in3_sel[1:0] $1\dec62_in3_sel[1:0] + attribute \src "libresoc.v:118556.5-118556.29" + switch \initial + attribute \src "libresoc.v:118556.9-118556.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_in3_sel[1:0] 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_in3_sel[1:0] 2'01 + case + assign $1\dec62_in3_sel[1:0] 2'00 + end + sync always + update \dec62_in3_sel $0\dec62_in3_sel[1:0] + end + attribute \src "libresoc.v:118568.3-118580.6" + process $proc$libresoc.v:118568$4457 + assign { } { } + assign { } { } + assign $0\dec62_out_sel[1:0] $1\dec62_out_sel[1:0] + attribute \src "libresoc.v:118569.5-118569.29" + switch \initial + attribute \src "libresoc.v:118569.9-118569.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:441" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_out_sel[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_out_sel[1:0] 2'00 + case + assign $1\dec62_out_sel[1:0] 2'00 + end + sync always + update \dec62_out_sel $0\dec62_out_sel[1:0] + end + connect \opcode_switch \opcode_in [1:0] +end +attribute \src "libresoc.v:118586.1-119177.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU" +attribute \generator "nMigen" +module \dec_ALU + attribute \src "libresoc.v:119139.3-119150.6" + wire width 13 $0\ALU__fn_unit[12:0] + attribute \src "libresoc.v:118587.7-118587.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:119139.3-119150.6" + wire width 13 $1\ALU__fn_unit[12:0] + attribute \src "libresoc.v:119043.18-119043.109" + wire $and$libresoc.v:119043$4465_Y + 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + wire \$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + wire \$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:917" + wire \$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + wire \$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + wire \$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:918" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:918" + wire \$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 18 \ALU__data_len + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 output 3 \ALU__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 4 \ALU__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 5 \ALU__imm_data__ok + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 14 \ALU__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 19 \ALU__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 2 \ALU__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 10 \ALU__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 12 \ALU__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 16 \ALU__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 17 \ALU__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 8 \ALU__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 9 \ALU__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 15 \ALU__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 7 \ALU__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 6 \ALU__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 13 \ALU__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 11 \ALU__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" + wire input 1 \bigendian + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \dec_ALU_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \dec_ALU_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \dec_ALU_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 14 \dec_ALU_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \dec_ALU_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \dec_ALU_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 14 \dec_ALU_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 8 \dec_ALU_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 24 \dec_ALU_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire \dec_ALU_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \dec_ALU_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire \dec_ALU_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \dec_ALU_SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 16 \dec_ALU_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 10 \dec_ALU_SPR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 16 \dec_ALU_UI + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec_ALU_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec_ALU_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \dec_ALU_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \dec_ALU_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 13 \dec_ALU_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec_ALU_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 \dec_ALU_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 \dec_ALU_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \dec_ALU_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \dec_ALU_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \dec_ALU_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 \dec_ALU_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \dec_ALU_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \dec_ALU_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 6 \dec_ALU_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \dec_XL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 3 \dec_X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 3 \dec_X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:296" + wire \dec_ai_immz_out + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:295" + wire width 3 \dec_ai_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \dec_bi_imm_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_bi_imm_b_ok + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:365" + wire width 4 \dec_bi_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:651" + wire width 32 \dec_cr_in_insn_in + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:650" + wire width 3 \dec_cr_in_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_cr_out_cr_bitfield_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:719" + wire width 32 \dec_cr_out_insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:717" + wire \dec_cr_out_rc_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:718" + wire width 3 \dec_cr_out_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_oe_oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_oe_oe_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:607" + wire width 2 \dec_oe_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + wire width 32 \dec_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_rc_rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_rc_rc_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:570" + wire width 2 \dec_rc_sel_in + attribute \src "libresoc.v:118587.7-118587.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:571" + wire width 32 \insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:608" + wire width 32 \insn_in$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 32 input 20 \raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:910" + wire width 10 \spr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + cell $and $and$libresoc.v:119043$4465 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$6 + connect \B \$20 + connect \Y $and$libresoc.v:119043$4465_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + cell $eq $eq$libresoc.v:119037$4459 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 10 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 10'0000010011 + connect \Y $eq$libresoc.v:119037$4459_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + cell $eq $eq$libresoc.v:119039$4461 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 10 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 10'1011010000 + connect \Y $eq$libresoc.v:119039$4461_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + cell $eq $eq$libresoc.v:119041$4463 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 6'110000 + connect \Y $eq$libresoc.v:119041$4463_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:917" + cell $eq $eq$libresoc.v:119044$4466 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \dec_ALU_internal_op + connect \B 7'0110001 + connect \Y $eq$libresoc.v:119044$4466_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:918" + cell $eq $eq$libresoc.v:119045$4467 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \dec_ALU_internal_op + connect \B 7'0101110 + connect \Y $eq$libresoc.v:119045$4467_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + cell $eq $eq$libresoc.v:119047$4469 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 10 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 10'0000010010 + connect \Y $eq$libresoc.v:119047$4469_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + cell $or $or$libresoc.v:119038$4460 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \B \$10 + connect \Y $or$libresoc.v:119038$4460_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + cell $or $or$libresoc.v:119040$4462 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$12 + connect \B \$14 + connect \Y $or$libresoc.v:119040$4462_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + cell $or $or$libresoc.v:119042$4464 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$16 + connect \B \$18 + connect \Y $or$libresoc.v:119042$4464_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:918" + cell $or $or$libresoc.v:119046$4468 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$2 + connect \B \$4 + connect \Y $or$libresoc.v:119046$4468_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:119048.7-119086.4" + cell \dec \dec + connect \ALU_BA \dec_ALU_BA + connect \ALU_BB \dec_ALU_BB + connect \ALU_BC \dec_ALU_BC + connect \ALU_BD \dec_ALU_BD + connect \ALU_BI \dec_ALU_BI + connect \ALU_BT \dec_ALU_BT + connect \ALU_DS \dec_ALU_DS + connect \ALU_FXM \dec_ALU_FXM + connect \ALU_LI \dec_ALU_LI + connect \ALU_OE \dec_ALU_OE + connect \ALU_RA \dec_ALU_RA + connect \ALU_Rc \dec_ALU_Rc + connect \ALU_SH32 \dec_ALU_SH32 + connect \ALU_SI \dec_ALU_SI + connect \ALU_SPR \dec_ALU_SPR + connect \ALU_UI \dec_ALU_UI + connect \ALU_cr_in \dec_ALU_cr_in + connect \ALU_cr_out \dec_ALU_cr_out + connect \ALU_cry_in \dec_ALU_cry_in + connect \ALU_cry_out \dec_ALU_cry_out + connect \ALU_function_unit \dec_ALU_function_unit + connect \ALU_in1_sel \dec_ALU_in1_sel + connect \ALU_in2_sel \dec_ALU_in2_sel + connect \ALU_internal_op \dec_ALU_internal_op + connect \ALU_inv_a \dec_ALU_inv_a + connect \ALU_inv_out \dec_ALU_inv_out + connect \ALU_is_32b \dec_ALU_is_32b + connect \ALU_ldst_len \dec_ALU_ldst_len + connect \ALU_rc_sel \dec_ALU_rc_sel + connect \ALU_sgn \dec_ALU_sgn + connect \ALU_sh \dec_ALU_sh + connect \XL_BT \dec_XL_BT + connect \X_BF \dec_X_BF + connect \X_BFA \dec_X_BFA + connect \bigendian \bigendian + connect \opcode_in \dec_opcode_in + connect \raw_opcode_in \raw_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:119087.10-119091.4" + cell \dec_ai \dec_ai + connect \ALU_RA \dec_ALU_RA + connect \immz_out \dec_ai_immz_out + connect \sel_in \dec_ai_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:119092.10-119103.4" + cell \dec_bi \dec_bi + connect \ALU_BD \dec_ALU_BD + connect \ALU_DS \dec_ALU_DS + connect \ALU_LI \dec_ALU_LI + connect \ALU_SH32 \dec_ALU_SH32 + connect \ALU_SI \dec_ALU_SI + connect \ALU_UI \dec_ALU_UI + connect \ALU_sh \dec_ALU_sh + connect \imm_b \dec_bi_imm_b + connect \imm_b_ok \dec_bi_imm_b_ok + connect \sel_in \dec_bi_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:119104.13-119115.4" + cell \dec_cr_in \dec_cr_in + connect \ALU_BA \dec_ALU_BA + connect \ALU_BB \dec_ALU_BB + connect \ALU_BC \dec_ALU_BC + connect \ALU_BI \dec_ALU_BI + connect \ALU_BT \dec_ALU_BT + connect \ALU_FXM \dec_ALU_FXM + connect \ALU_internal_op \dec_ALU_internal_op + connect \X_BFA \dec_X_BFA + connect \insn_in \dec_cr_in_insn_in + connect \sel_in \dec_cr_in_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:119116.14-119125.4" + cell \dec_cr_out \dec_cr_out + connect \ALU_FXM \dec_ALU_FXM + connect \ALU_internal_op \dec_ALU_internal_op + connect \XL_BT \dec_XL_BT + connect \X_BF \dec_X_BF + connect \cr_bitfield_ok \dec_cr_out_cr_bitfield_ok + connect \insn_in \dec_cr_out_insn_in + connect \rc_in \dec_cr_out_rc_in + connect \sel_in \dec_cr_out_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:119126.10-119132.4" + cell \dec_oe \dec_oe + connect \ALU_OE \dec_ALU_OE + connect \ALU_internal_op \dec_ALU_internal_op + connect \oe \dec_oe_oe + connect \oe_ok \dec_oe_oe_ok + connect \sel_in \dec_oe_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:119133.10-119138.4" + cell \dec_rc \dec_rc + connect \ALU_Rc \dec_ALU_Rc + connect \rc \dec_rc_rc + connect \rc_ok \dec_rc_rc_ok + connect \sel_in \dec_rc_sel_in + end + attribute \src "libresoc.v:118587.7-118587.20" + process $proc$libresoc.v:118587$4471 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:119139.3-119150.6" + process $proc$libresoc.v:119139$4470 + assign { } { } + assign $0\ALU__fn_unit[12:0] $1\ALU__fn_unit[12:0] + attribute \src "libresoc.v:119140.5-119140.29" + switch \initial + attribute \src "libresoc.v:119140.9-119140.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + switch \$22 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ALU__fn_unit[12:0] 13'0100000000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\ALU__fn_unit[12:0] \dec_ALU_function_unit + end + sync always + update \ALU__fn_unit $0\ALU__fn_unit[12:0] + end + connect \$10 $eq$libresoc.v:119037$4459_Y + connect \$12 $or$libresoc.v:119038$4460_Y + connect \$14 $eq$libresoc.v:119039$4461_Y + connect \$16 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connect \dec_ai_sel_in \dec_ALU_in1_sel + connect \spr { \dec_ALU_SPR [4:0] \dec_ALU_SPR [9:5] } + connect \ALU__insn_type \dec_ALU_internal_op + connect \dec_cr_out_rc_in \dec_rc_rc + connect \dec_cr_out_sel_in \dec_ALU_cr_out + connect \dec_cr_in_sel_in \dec_ALU_cr_in + connect \dec_oe_sel_in \dec_ALU_rc_sel + connect \dec_rc_sel_in \dec_ALU_rc_sel + connect \dec_cr_out_insn_in \dec_opcode_in + connect \dec_cr_in_insn_in \dec_opcode_in + connect \insn_in$1 \dec_opcode_in + connect \insn_in \dec_opcode_in + connect \ALU__insn \dec_opcode_in +end +attribute \src "libresoc.v:119181.1-119690.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_BRANCH" +attribute \generator "nMigen" +module \dec_BRANCH + attribute \src "libresoc.v:119652.3-119663.6" + wire width 13 $0\BRANCH__fn_unit[12:0] + attribute \src "libresoc.v:119664.3-119673.6" + wire $0\BRANCH__lk[0:0] + attribute \src "libresoc.v:119182.7-119182.20" + wire $0\initial[0:0] + attribute \src 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output 9 \BRANCH__lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" + wire input 2 \bigendian + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:9" + wire width 64 input 11 \core_pc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \dec_BRANCH_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \dec_BRANCH_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \dec_BRANCH_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 14 \dec_BRANCH_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \dec_BRANCH_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \dec_BRANCH_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 14 \dec_BRANCH_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 8 \dec_BRANCH_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 24 \dec_BRANCH_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire \dec_BRANCH_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire \dec_BRANCH_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire \dec_BRANCH_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \dec_BRANCH_SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 16 \dec_BRANCH_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 10 \dec_BRANCH_SPR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 16 \dec_BRANCH_UI + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec_BRANCH_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec_BRANCH_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 13 \dec_BRANCH_function_unit + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 \dec_BRANCH_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 \dec_BRANCH_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \dec_BRANCH_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \dec_BRANCH_lk + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \dec_BRANCH_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 6 \dec_BRANCH_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \dec_XL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 3 \dec_X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 3 \dec_X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \dec_bi_imm_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_bi_imm_b_ok + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:365" + wire width 4 \dec_bi_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:651" + wire width 32 \dec_cr_in_insn_in + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:650" + wire width 3 \dec_cr_in_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:719" + wire width 32 \dec_cr_out_insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:717" + wire \dec_cr_out_rc_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:718" + wire width 3 \dec_cr_out_sel_in + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:607" + wire width 2 \dec_oe_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + wire width 32 \dec_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_rc_rc + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:570" + wire width 2 \dec_rc_sel_in + attribute \src "libresoc.v:119182.7-119182.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:571" + wire width 32 \insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:608" + wire width 32 \insn_in$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 32 input 1 \raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:910" + wire width 10 \spr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + cell $and $and$libresoc.v:119571$4478 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$6 + connect \B \$20 + connect \Y $and$libresoc.v:119571$4478_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + cell $eq $eq$libresoc.v:119565$4472 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 10 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 10'0000010011 + connect \Y $eq$libresoc.v:119565$4472_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + cell $eq $eq$libresoc.v:119567$4474 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 10 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 10'1011010000 + connect \Y $eq$libresoc.v:119567$4474_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + cell $eq $eq$libresoc.v:119569$4476 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 6'110000 + connect \Y $eq$libresoc.v:119569$4476_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:917" + cell $eq $eq$libresoc.v:119572$4479 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \dec_BRANCH_internal_op + connect \B 7'0110001 + connect \Y $eq$libresoc.v:119572$4479_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:918" + cell $eq $eq$libresoc.v:119573$4480 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \dec_BRANCH_internal_op + connect \B 7'0101110 + connect \Y $eq$libresoc.v:119573$4480_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + cell $eq $eq$libresoc.v:119575$4482 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 10 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 10'0000010010 + connect \Y $eq$libresoc.v:119575$4482_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + cell $or $or$libresoc.v:119566$4473 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \B \$10 + connect \Y $or$libresoc.v:119566$4473_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + cell $or $or$libresoc.v:119568$4475 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$12 + connect \B \$14 + connect \Y $or$libresoc.v:119568$4475_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + cell $or $or$libresoc.v:119570$4477 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$16 + connect \B \$18 + connect \Y $or$libresoc.v:119570$4477_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:918" + cell $or $or$libresoc.v:119574$4481 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$2 + connect \B \$4 + connect \Y $or$libresoc.v:119574$4481_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:119576.13-119608.4" + cell \dec$146 \dec + connect \BRANCH_BA \dec_BRANCH_BA + connect \BRANCH_BB \dec_BRANCH_BB + connect \BRANCH_BC \dec_BRANCH_BC + connect \BRANCH_BD \dec_BRANCH_BD + connect \BRANCH_BI \dec_BRANCH_BI + connect \BRANCH_BT \dec_BRANCH_BT + connect \BRANCH_DS \dec_BRANCH_DS + connect \BRANCH_FXM \dec_BRANCH_FXM + connect \BRANCH_LI \dec_BRANCH_LI + connect \BRANCH_LK \dec_BRANCH_LK + connect \BRANCH_OE \dec_BRANCH_OE + connect \BRANCH_Rc \dec_BRANCH_Rc + connect \BRANCH_SH32 \dec_BRANCH_SH32 + connect \BRANCH_SI \dec_BRANCH_SI + connect \BRANCH_SPR \dec_BRANCH_SPR + connect \BRANCH_UI \dec_BRANCH_UI + connect \BRANCH_cr_in \dec_BRANCH_cr_in + connect \BRANCH_cr_out \dec_BRANCH_cr_out + connect \BRANCH_function_unit \dec_BRANCH_function_unit + connect \BRANCH_in2_sel \dec_BRANCH_in2_sel + connect \BRANCH_internal_op \dec_BRANCH_internal_op + connect \BRANCH_is_32b \dec_BRANCH_is_32b + connect \BRANCH_lk \dec_BRANCH_lk + connect \BRANCH_rc_sel \dec_BRANCH_rc_sel + connect \BRANCH_sh \dec_BRANCH_sh + connect \XL_BT \dec_XL_BT + connect \X_BF \dec_X_BF + connect \X_BFA \dec_X_BFA + connect \bigendian \bigendian + connect \opcode_in \dec_opcode_in + connect \raw_opcode_in \raw_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:119609.16-119620.4" + cell \dec_bi$153 \dec_bi + connect \BRANCH_BD \dec_BRANCH_BD + connect \BRANCH_DS \dec_BRANCH_DS + connect \BRANCH_LI \dec_BRANCH_LI + connect \BRANCH_SH32 \dec_BRANCH_SH32 + connect \BRANCH_SI \dec_BRANCH_SI + connect \BRANCH_UI \dec_BRANCH_UI + connect \BRANCH_sh \dec_BRANCH_sh + connect \imm_b \dec_bi_imm_b + connect \imm_b_ok \dec_bi_imm_b_ok + connect \sel_in \dec_bi_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:119621.19-119632.4" + cell \dec_cr_in$149 \dec_cr_in + connect \BRANCH_BA \dec_BRANCH_BA + connect \BRANCH_BB \dec_BRANCH_BB + connect \BRANCH_BC \dec_BRANCH_BC + connect \BRANCH_BI \dec_BRANCH_BI + connect \BRANCH_BT \dec_BRANCH_BT + connect \BRANCH_FXM \dec_BRANCH_FXM + connect \BRANCH_internal_op \dec_BRANCH_internal_op + connect \X_BFA \dec_X_BFA + connect \insn_in \dec_cr_in_insn_in + connect \sel_in \dec_cr_in_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:119633.20-119641.4" + cell \dec_cr_out$151 \dec_cr_out + connect \BRANCH_FXM \dec_BRANCH_FXM + connect \BRANCH_internal_op \dec_BRANCH_internal_op + connect \XL_BT \dec_XL_BT + connect \X_BF \dec_X_BF + connect \insn_in \dec_cr_out_insn_in + connect \rc_in \dec_cr_out_rc_in + connect \sel_in \dec_cr_out_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:119642.16-119646.4" + cell \dec_oe$148 \dec_oe + connect \BRANCH_OE \dec_BRANCH_OE + connect \BRANCH_internal_op \dec_BRANCH_internal_op + connect \sel_in \dec_oe_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:119647.16-119651.4" + cell \dec_rc$147 \dec_rc + connect \BRANCH_Rc \dec_BRANCH_Rc + connect \rc \dec_rc_rc + connect \sel_in \dec_rc_sel_in + end + attribute \src "libresoc.v:119182.7-119182.20" + process $proc$libresoc.v:119182$4485 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:119652.3-119663.6" + process $proc$libresoc.v:119652$4483 + assign { } { } + assign $0\BRANCH__fn_unit[12:0] $1\BRANCH__fn_unit[12:0] + attribute \src "libresoc.v:119653.5-119653.29" + switch \initial + attribute \src "libresoc.v:119653.9-119653.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + switch \$22 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\BRANCH__fn_unit[12:0] 13'0100000000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\BRANCH__fn_unit[12:0] \dec_BRANCH_function_unit + end + sync always + update \BRANCH__fn_unit $0\BRANCH__fn_unit[12:0] + end + attribute \src "libresoc.v:119664.3-119673.6" + process $proc$libresoc.v:119664$4484 + assign { } { } + assign { } { } + assign $0\BRANCH__lk[0:0] $1\BRANCH__lk[0:0] + attribute \src "libresoc.v:119665.5-119665.29" + switch \initial + attribute \src "libresoc.v:119665.9-119665.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:957" + switch \dec_BRANCH_lk + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\BRANCH__lk[0:0] \dec_BRANCH_LK + case + assign $1\BRANCH__lk[0:0] 1'0 + end + sync always + update \BRANCH__lk $0\BRANCH__lk[0:0] + end + connect \$10 $eq$libresoc.v:119565$4472_Y + connect \$12 $or$libresoc.v:119566$4473_Y + connect \$14 $eq$libresoc.v:119567$4474_Y + connect \$16 $or$libresoc.v:119568$4475_Y + connect \$18 $eq$libresoc.v:119569$4476_Y + connect \$20 $or$libresoc.v:119570$4477_Y + connect \$22 $and$libresoc.v:119571$4478_Y + connect \$2 $eq$libresoc.v:119572$4479_Y + connect \$4 $eq$libresoc.v:119573$4480_Y + connect \$6 $or$libresoc.v:119574$4481_Y + connect \$8 $eq$libresoc.v:119575$4482_Y + connect \BRANCH__is_32bit \dec_BRANCH_is_32b + connect { \BRANCH__imm_data__ok \BRANCH__imm_data__data } { \dec_bi_imm_b_ok \dec_bi_imm_b } + connect \dec_bi_sel_in \dec_BRANCH_in2_sel + connect \spr { \dec_BRANCH_SPR [4:0] \dec_BRANCH_SPR [9:5] } + connect \BRANCH__insn_type \dec_BRANCH_internal_op + connect \BRANCH__cia \core_pc + connect \dec_cr_out_rc_in \dec_rc_rc + connect \dec_cr_out_sel_in \dec_BRANCH_cr_out + connect \dec_cr_in_sel_in \dec_BRANCH_cr_in + connect \dec_oe_sel_in \dec_BRANCH_rc_sel + connect \dec_rc_sel_in \dec_BRANCH_rc_sel + connect \dec_cr_out_insn_in \dec_opcode_in + connect \dec_cr_in_insn_in \dec_opcode_in + connect \insn_in$1 \dec_opcode_in + connect \insn_in \dec_opcode_in + connect \BRANCH__insn \dec_opcode_in +end +attribute \src "libresoc.v:119694.1-120095.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_CR" +attribute \generator "nMigen" +module \dec_CR + attribute \src "libresoc.v:120071.3-120082.6" + wire width 13 $0\CR__fn_unit[12:0] + attribute \src "libresoc.v:119695.7-119695.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:120071.3-120082.6" + wire width 13 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + wire \$8 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 output 3 \CR__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 4 \CR__insn + attribute \enum_base_type "MicrOp" + attribute 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"OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute 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\dec_CR_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire \dec_CR_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire \dec_CR_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 10 \dec_CR_SPR + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec_CR_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 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attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 \dec_CR_internal_op + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \dec_CR_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \dec_XL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 3 \dec_X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 3 \dec_X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:651" + wire width 32 \dec_cr_in_insn_in + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute 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\enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:607" + wire width 2 \dec_oe_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + wire width 32 \dec_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_rc_rc + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:570" + wire width 2 \dec_rc_sel_in + attribute \src "libresoc.v:119695.7-119695.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:571" + wire width 32 \insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:608" + wire width 32 \insn_in$1 + attribute \src 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:918" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:918" + wire \$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 18 \DIV__data_len + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 output 3 \DIV__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 4 \DIV__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 5 \DIV__imm_data__ok + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 12 \DIV__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 19 \DIV__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 2 \DIV__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 10 \DIV__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 13 \DIV__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 16 \DIV__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 17 \DIV__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 8 \DIV__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 9 \DIV__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 15 \DIV__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 7 \DIV__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 6 \DIV__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 14 \DIV__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 11 \DIV__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" + wire input 1 \bigendian + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \dec_DIV_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \dec_DIV_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \dec_DIV_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 14 \dec_DIV_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \dec_DIV_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \dec_DIV_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 14 \dec_DIV_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 8 \dec_DIV_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 24 \dec_DIV_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire \dec_DIV_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \dec_DIV_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire \dec_DIV_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \dec_DIV_SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 16 \dec_DIV_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 10 \dec_DIV_SPR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 16 \dec_DIV_UI + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec_DIV_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec_DIV_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \dec_DIV_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \dec_DIV_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 13 \dec_DIV_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec_DIV_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 \dec_DIV_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 \dec_DIV_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \dec_DIV_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \dec_DIV_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \dec_DIV_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 \dec_DIV_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \dec_DIV_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \dec_DIV_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 6 \dec_DIV_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \dec_XL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 3 \dec_X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 3 \dec_X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:296" + wire \dec_ai_immz_out + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:295" + wire width 3 \dec_ai_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \dec_bi_imm_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_bi_imm_b_ok + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:365" + wire width 4 \dec_bi_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:651" + wire width 32 \dec_cr_in_insn_in + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:650" + wire width 3 \dec_cr_in_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_cr_out_cr_bitfield_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:719" + wire width 32 \dec_cr_out_insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:717" + wire \dec_cr_out_rc_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:718" + wire width 3 \dec_cr_out_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_oe_oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_oe_oe_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:607" + wire width 2 \dec_oe_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + wire width 32 \dec_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_rc_rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_rc_rc_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:570" + wire width 2 \dec_rc_sel_in + attribute \src "libresoc.v:120100.7-120100.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:571" + wire width 32 \insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:608" + wire width 32 \insn_in$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 32 input 20 \raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:910" + wire width 10 \spr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + cell $and $and$libresoc.v:120556$4505 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$6 + connect \B \$20 + connect \Y $and$libresoc.v:120556$4505_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + cell $eq $eq$libresoc.v:120550$4499 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 10 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 10'0000010011 + connect \Y $eq$libresoc.v:120550$4499_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + cell $eq $eq$libresoc.v:120552$4501 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 10 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 10'1011010000 + connect \Y $eq$libresoc.v:120552$4501_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + cell $eq $eq$libresoc.v:120554$4503 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 6'110000 + connect \Y $eq$libresoc.v:120554$4503_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:917" + cell $eq $eq$libresoc.v:120557$4506 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \dec_DIV_internal_op + connect \B 7'0110001 + connect \Y $eq$libresoc.v:120557$4506_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:918" + cell $eq $eq$libresoc.v:120558$4507 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \dec_DIV_internal_op + connect \B 7'0101110 + connect \Y $eq$libresoc.v:120558$4507_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + cell $eq $eq$libresoc.v:120560$4509 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 10 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 10'0000010010 + connect \Y $eq$libresoc.v:120560$4509_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + cell $or $or$libresoc.v:120551$4500 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \B \$10 + connect \Y $or$libresoc.v:120551$4500_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + cell $or $or$libresoc.v:120553$4502 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$12 + connect \B \$14 + connect \Y $or$libresoc.v:120553$4502_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + cell $or $or$libresoc.v:120555$4504 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$16 + connect \B \$18 + connect \Y $or$libresoc.v:120555$4504_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:918" + cell $or $or$libresoc.v:120559$4508 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$2 + connect \B \$4 + connect \Y $or$libresoc.v:120559$4508_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:120561.13-120599.4" + cell \dec$170 \dec + connect \DIV_BA \dec_DIV_BA + connect \DIV_BB \dec_DIV_BB + connect \DIV_BC \dec_DIV_BC + connect \DIV_BD \dec_DIV_BD + connect \DIV_BI \dec_DIV_BI + connect \DIV_BT \dec_DIV_BT + connect \DIV_DS \dec_DIV_DS + connect \DIV_FXM \dec_DIV_FXM + connect \DIV_LI \dec_DIV_LI + connect \DIV_OE \dec_DIV_OE + connect \DIV_RA \dec_DIV_RA + connect \DIV_Rc \dec_DIV_Rc + connect \DIV_SH32 \dec_DIV_SH32 + connect \DIV_SI \dec_DIV_SI + connect \DIV_SPR \dec_DIV_SPR + connect \DIV_UI \dec_DIV_UI + connect \DIV_cr_in \dec_DIV_cr_in + connect \DIV_cr_out \dec_DIV_cr_out + connect \DIV_cry_in \dec_DIV_cry_in + connect \DIV_cry_out \dec_DIV_cry_out + connect \DIV_function_unit \dec_DIV_function_unit + connect \DIV_in1_sel \dec_DIV_in1_sel + connect \DIV_in2_sel \dec_DIV_in2_sel + connect \DIV_internal_op \dec_DIV_internal_op + connect \DIV_inv_a \dec_DIV_inv_a + connect \DIV_inv_out \dec_DIV_inv_out + connect \DIV_is_32b \dec_DIV_is_32b + connect \DIV_ldst_len \dec_DIV_ldst_len + connect \DIV_rc_sel \dec_DIV_rc_sel + connect \DIV_sgn \dec_DIV_sgn + connect \DIV_sh \dec_DIV_sh + connect \XL_BT \dec_XL_BT + connect \X_BF \dec_X_BF + connect \X_BFA \dec_X_BFA + connect \bigendian \bigendian + connect \opcode_in \dec_opcode_in + connect \raw_opcode_in \raw_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:120600.16-120604.4" + cell \dec_ai$177 \dec_ai + connect \DIV_RA \dec_DIV_RA + connect \immz_out \dec_ai_immz_out + connect \sel_in \dec_ai_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:120605.16-120616.4" + cell \dec_bi$178 \dec_bi + connect \DIV_BD \dec_DIV_BD + connect \DIV_DS \dec_DIV_DS + connect \DIV_LI \dec_DIV_LI + connect \DIV_SH32 \dec_DIV_SH32 + connect \DIV_SI \dec_DIV_SI + connect \DIV_UI \dec_DIV_UI + connect \DIV_sh \dec_DIV_sh + connect \imm_b \dec_bi_imm_b + connect \imm_b_ok \dec_bi_imm_b_ok + connect \sel_in \dec_bi_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:120617.19-120628.4" + cell \dec_cr_in$173 \dec_cr_in + connect \DIV_BA \dec_DIV_BA + connect \DIV_BB \dec_DIV_BB + connect \DIV_BC \dec_DIV_BC + connect \DIV_BI \dec_DIV_BI + connect \DIV_BT \dec_DIV_BT + connect \DIV_FXM \dec_DIV_FXM + connect \DIV_internal_op \dec_DIV_internal_op + connect \X_BFA \dec_X_BFA + connect \insn_in \dec_cr_in_insn_in + connect \sel_in \dec_cr_in_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:120629.20-120638.4" + cell \dec_cr_out$175 \dec_cr_out + connect \DIV_FXM \dec_DIV_FXM + connect \DIV_internal_op \dec_DIV_internal_op + connect \XL_BT \dec_XL_BT + connect \X_BF \dec_X_BF + connect \cr_bitfield_ok \dec_cr_out_cr_bitfield_ok + connect \insn_in \dec_cr_out_insn_in + connect \rc_in \dec_cr_out_rc_in + connect \sel_in \dec_cr_out_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:120639.16-120645.4" + cell \dec_oe$172 \dec_oe + connect \DIV_OE \dec_DIV_OE + connect \DIV_internal_op \dec_DIV_internal_op + connect \oe \dec_oe_oe + connect \oe_ok \dec_oe_oe_ok + connect \sel_in \dec_oe_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:120646.16-120651.4" + cell \dec_rc$171 \dec_rc + connect \DIV_Rc \dec_DIV_Rc + connect \rc \dec_rc_rc + connect \rc_ok \dec_rc_rc_ok + connect \sel_in \dec_rc_sel_in + end + attribute \src "libresoc.v:120100.7-120100.20" + process $proc$libresoc.v:120100$4511 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:120652.3-120663.6" + process $proc$libresoc.v:120652$4510 + assign { } { } + assign $0\DIV__fn_unit[12:0] $1\DIV__fn_unit[12:0] + attribute \src "libresoc.v:120653.5-120653.29" + switch \initial + attribute \src "libresoc.v:120653.9-120653.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + switch \$22 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\DIV__fn_unit[12:0] 13'0100000000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\DIV__fn_unit[12:0] \dec_DIV_function_unit + end + sync always + update \DIV__fn_unit $0\DIV__fn_unit[12:0] + end + connect \$10 $eq$libresoc.v:120550$4499_Y + connect \$12 $or$libresoc.v:120551$4500_Y + connect \$14 $eq$libresoc.v:120552$4501_Y + connect \$16 $or$libresoc.v:120553$4502_Y + connect \$18 $eq$libresoc.v:120554$4503_Y + connect \$20 $or$libresoc.v:120555$4504_Y + connect \$22 $and$libresoc.v:120556$4505_Y + connect \$2 $eq$libresoc.v:120557$4506_Y + connect \$4 $eq$libresoc.v:120558$4507_Y + connect \$6 $or$libresoc.v:120559$4508_Y + connect \$8 $eq$libresoc.v:120560$4509_Y + connect \DIV__is_signed \dec_DIV_sgn + connect \DIV__is_32bit \dec_DIV_is_32b + connect \DIV__output_carry \dec_DIV_cry_out + connect \DIV__input_carry \dec_DIV_cry_in + connect \DIV__invert_out \dec_DIV_inv_out + connect \DIV__invert_in \dec_DIV_inv_a + connect \DIV__data_len \dec_DIV_ldst_len + connect \DIV__write_cr0 \dec_cr_out_cr_bitfield_ok + connect { \DIV__oe__ok \DIV__oe__oe } { \dec_oe_oe_ok \dec_oe_oe } + connect { \DIV__rc__ok \DIV__rc__rc } { \dec_rc_rc_ok \dec_rc_rc } + connect { \DIV__imm_data__ok \DIV__imm_data__data } { \dec_bi_imm_b_ok \dec_bi_imm_b } + connect \dec_bi_sel_in \dec_DIV_in2_sel + connect \DIV__zero_a \dec_ai_immz_out + connect \dec_ai_sel_in \dec_DIV_in1_sel + connect \spr { \dec_DIV_SPR [4:0] \dec_DIV_SPR [9:5] } + connect \DIV__insn_type \dec_DIV_internal_op + connect \dec_cr_out_rc_in \dec_rc_rc + connect \dec_cr_out_sel_in \dec_DIV_cr_out + connect \dec_cr_in_sel_in \dec_DIV_cr_in + connect \dec_oe_sel_in \dec_DIV_rc_sel + connect \dec_rc_sel_in \dec_DIV_rc_sel + connect \dec_cr_out_insn_in \dec_opcode_in + connect \dec_cr_in_insn_in \dec_opcode_in + connect \insn_in$1 \dec_opcode_in + connect \insn_in \dec_opcode_in + connect \DIV__insn \dec_opcode_in +end +attribute \src "libresoc.v:120694.1-121275.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST" +attribute \generator "nMigen" +module \dec_LDST + attribute \src "libresoc.v:121239.3-121250.6" + wire width 13 $0\LDST__fn_unit[12:0] + attribute \src "libresoc.v:120695.7-120695.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:121239.3-121250.6" + wire width 13 $1\LDST__fn_unit[12:0] + attribute \src "libresoc.v:121145.18-121145.109" + wire $and$libresoc.v:121145$4518_Y + attribute \src "libresoc.v:121139.18-121139.112" + wire $eq$libresoc.v:121139$4512_Y + attribute \src "libresoc.v:121141.18-121141.112" + wire $eq$libresoc.v:121141$4514_Y + attribute \src "libresoc.v:121143.18-121143.110" + wire $eq$libresoc.v:121143$4516_Y + attribute \src "libresoc.v:121146.17-121146.126" + wire $eq$libresoc.v:121146$4519_Y + attribute \src "libresoc.v:121147.17-121147.126" + wire $eq$libresoc.v:121147$4520_Y + attribute \src "libresoc.v:121149.17-121149.111" + wire $eq$libresoc.v:121149$4522_Y + attribute \src "libresoc.v:121140.18-121140.109" + wire $or$libresoc.v:121140$4513_Y + attribute \src "libresoc.v:121142.18-121142.110" + wire $or$libresoc.v:121142$4515_Y + attribute \src "libresoc.v:121144.18-121144.110" + wire $or$libresoc.v:121144$4517_Y + attribute \src "libresoc.v:121148.17-121148.107" + wire $or$libresoc.v:121148$4521_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + wire \$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + wire \$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + wire \$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:917" + wire \$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + wire \$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + wire \$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:918" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:918" + wire \$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 14 \LDST__byte_reverse + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 13 \LDST__data_len + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 output 3 \LDST__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 4 \LDST__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 5 \LDST__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 17 \LDST__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 2 \LDST__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 11 \LDST__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 12 \LDST__is_signed + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 16 \LDST__ldst_mode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 9 \LDST__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 10 \LDST__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 8 \LDST__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 7 \LDST__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 15 \LDST__sign_extend + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 6 \LDST__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" + wire input 1 \bigendian + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \dec_LDST_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \dec_LDST_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \dec_LDST_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 14 \dec_LDST_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \dec_LDST_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \dec_LDST_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 14 \dec_LDST_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 8 \dec_LDST_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 24 \dec_LDST_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire \dec_LDST_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \dec_LDST_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire \dec_LDST_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \dec_LDST_SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 16 \dec_LDST_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 10 \dec_LDST_SPR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 16 \dec_LDST_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \dec_LDST_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec_LDST_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec_LDST_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 13 \dec_LDST_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec_LDST_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 \dec_LDST_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 \dec_LDST_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \dec_LDST_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 \dec_LDST_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \dec_LDST_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \dec_LDST_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \dec_LDST_sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 6 \dec_LDST_sh + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \dec_LDST_upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \dec_XL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 3 \dec_X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 3 \dec_X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:296" + wire \dec_ai_immz_out + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:295" + wire width 3 \dec_ai_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \dec_bi_imm_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_bi_imm_b_ok + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:365" + wire width 4 \dec_bi_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:651" + wire width 32 \dec_cr_in_insn_in + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:650" + wire width 3 \dec_cr_in_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:719" + wire width 32 \dec_cr_out_insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:717" + wire \dec_cr_out_rc_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:718" + wire width 3 \dec_cr_out_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_oe_oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_oe_oe_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:607" + wire width 2 \dec_oe_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + wire width 32 \dec_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_rc_rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_rc_rc_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:570" + wire width 2 \dec_rc_sel_in + attribute \src "libresoc.v:120695.7-120695.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:571" + wire width 32 \insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:608" + wire width 32 \insn_in$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 32 input 18 \raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:910" + wire width 10 \spr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + cell $and $and$libresoc.v:121145$4518 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$6 + connect \B \$20 + connect \Y $and$libresoc.v:121145$4518_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + cell $eq $eq$libresoc.v:121139$4512 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 10 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 10'0000010011 + connect \Y $eq$libresoc.v:121139$4512_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + cell $eq $eq$libresoc.v:121141$4514 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 10 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 10'1011010000 + connect \Y $eq$libresoc.v:121141$4514_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + cell $eq $eq$libresoc.v:121143$4516 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 6'110000 + connect \Y $eq$libresoc.v:121143$4516_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:917" + cell $eq $eq$libresoc.v:121146$4519 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \dec_LDST_internal_op + connect \B 7'0110001 + connect \Y $eq$libresoc.v:121146$4519_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:918" + cell $eq $eq$libresoc.v:121147$4520 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \dec_LDST_internal_op + connect \B 7'0101110 + connect \Y $eq$libresoc.v:121147$4520_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + cell $eq $eq$libresoc.v:121149$4522 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 10 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 10'0000010010 + connect \Y $eq$libresoc.v:121149$4522_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + cell $or $or$libresoc.v:121140$4513 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \B \$10 + connect \Y $or$libresoc.v:121140$4513_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + cell $or $or$libresoc.v:121142$4515 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$12 + connect \B \$14 + connect \Y $or$libresoc.v:121142$4515_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + cell $or $or$libresoc.v:121144$4517 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$16 + connect \B \$18 + connect \Y $or$libresoc.v:121144$4517_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:918" + cell $or $or$libresoc.v:121148$4521 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$2 + connect \B \$4 + connect \Y $or$libresoc.v:121148$4521_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:121150.13-121187.4" + cell \dec$195 \dec + connect \LDST_BA \dec_LDST_BA + connect \LDST_BB \dec_LDST_BB + connect \LDST_BC \dec_LDST_BC + connect \LDST_BD \dec_LDST_BD + connect \LDST_BI \dec_LDST_BI + connect \LDST_BT \dec_LDST_BT + connect \LDST_DS \dec_LDST_DS + connect \LDST_FXM \dec_LDST_FXM + connect \LDST_LI \dec_LDST_LI + connect \LDST_OE \dec_LDST_OE + connect \LDST_RA \dec_LDST_RA + connect \LDST_Rc \dec_LDST_Rc + connect \LDST_SH32 \dec_LDST_SH32 + connect \LDST_SI \dec_LDST_SI + connect \LDST_SPR \dec_LDST_SPR + connect \LDST_UI \dec_LDST_UI + connect \LDST_br \dec_LDST_br + connect \LDST_cr_in \dec_LDST_cr_in + connect \LDST_cr_out \dec_LDST_cr_out + connect \LDST_function_unit \dec_LDST_function_unit + connect \LDST_in1_sel \dec_LDST_in1_sel + connect \LDST_in2_sel \dec_LDST_in2_sel + connect \LDST_internal_op \dec_LDST_internal_op + connect \LDST_is_32b \dec_LDST_is_32b + connect \LDST_ldst_len \dec_LDST_ldst_len + connect \LDST_rc_sel \dec_LDST_rc_sel + connect \LDST_sgn \dec_LDST_sgn + connect \LDST_sgn_ext \dec_LDST_sgn_ext + connect \LDST_sh \dec_LDST_sh + connect \LDST_upd \dec_LDST_upd + connect \XL_BT \dec_XL_BT + connect \X_BF \dec_X_BF + connect \X_BFA \dec_X_BFA + connect \bigendian \bigendian + connect \opcode_in \dec_opcode_in + connect \raw_opcode_in \raw_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:121188.16-121192.4" + cell \dec_ai$202 \dec_ai + connect \LDST_RA \dec_LDST_RA + connect \immz_out \dec_ai_immz_out + connect \sel_in \dec_ai_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:121193.16-121204.4" + cell \dec_bi$203 \dec_bi + connect \LDST_BD \dec_LDST_BD + connect \LDST_DS \dec_LDST_DS + connect \LDST_LI \dec_LDST_LI + connect \LDST_SH32 \dec_LDST_SH32 + connect \LDST_SI \dec_LDST_SI + connect \LDST_UI \dec_LDST_UI + connect \LDST_sh \dec_LDST_sh + connect \imm_b \dec_bi_imm_b + connect \imm_b_ok \dec_bi_imm_b_ok + connect \sel_in \dec_bi_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:121205.19-121216.4" + cell \dec_cr_in$198 \dec_cr_in + connect \LDST_BA \dec_LDST_BA + connect \LDST_BB \dec_LDST_BB + connect \LDST_BC \dec_LDST_BC + connect \LDST_BI \dec_LDST_BI + connect \LDST_BT \dec_LDST_BT + connect \LDST_FXM \dec_LDST_FXM + connect \LDST_internal_op \dec_LDST_internal_op + connect \X_BFA \dec_X_BFA + connect \insn_in \dec_cr_in_insn_in + connect \sel_in \dec_cr_in_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:121217.20-121225.4" + cell \dec_cr_out$200 \dec_cr_out + connect \LDST_FXM \dec_LDST_FXM + connect \LDST_internal_op \dec_LDST_internal_op + connect \XL_BT \dec_XL_BT + connect \X_BF \dec_X_BF + connect \insn_in \dec_cr_out_insn_in + connect \rc_in \dec_cr_out_rc_in + connect \sel_in \dec_cr_out_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:121226.16-121232.4" + cell \dec_oe$197 \dec_oe + connect \LDST_OE \dec_LDST_OE + connect \LDST_internal_op \dec_LDST_internal_op + connect \oe \dec_oe_oe + connect \oe_ok \dec_oe_oe_ok + connect \sel_in \dec_oe_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:121233.16-121238.4" + cell \dec_rc$196 \dec_rc + connect \LDST_Rc \dec_LDST_Rc + connect \rc \dec_rc_rc + connect \rc_ok \dec_rc_rc_ok + connect \sel_in \dec_rc_sel_in + end + attribute \src "libresoc.v:120695.7-120695.20" + process $proc$libresoc.v:120695$4524 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:121239.3-121250.6" + process $proc$libresoc.v:121239$4523 + assign { } { } + assign $0\LDST__fn_unit[12:0] $1\LDST__fn_unit[12:0] + attribute \src "libresoc.v:121240.5-121240.29" + switch \initial + attribute \src "libresoc.v:121240.9-121240.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + switch \$22 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\LDST__fn_unit[12:0] 13'0100000000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\LDST__fn_unit[12:0] \dec_LDST_function_unit + end + sync always + update \LDST__fn_unit $0\LDST__fn_unit[12:0] + end + connect \$10 $eq$libresoc.v:121139$4512_Y + connect \$12 $or$libresoc.v:121140$4513_Y + connect \$14 $eq$libresoc.v:121141$4514_Y + connect \$16 $or$libresoc.v:121142$4515_Y + connect \$18 $eq$libresoc.v:121143$4516_Y + connect \$20 $or$libresoc.v:121144$4517_Y + connect \$22 $and$libresoc.v:121145$4518_Y + connect \$2 $eq$libresoc.v:121146$4519_Y + connect \$4 $eq$libresoc.v:121147$4520_Y + connect \$6 $or$libresoc.v:121148$4521_Y + connect \$8 $eq$libresoc.v:121149$4522_Y + connect \LDST__ldst_mode \dec_LDST_upd + connect \LDST__sign_extend \dec_LDST_sgn_ext + connect \LDST__byte_reverse \dec_LDST_br + connect \LDST__is_signed \dec_LDST_sgn + connect \LDST__is_32bit \dec_LDST_is_32b + connect \LDST__data_len \dec_LDST_ldst_len + connect { \LDST__oe__ok \LDST__oe__oe } { \dec_oe_oe_ok \dec_oe_oe } + connect { \LDST__rc__ok \LDST__rc__rc } { \dec_rc_rc_ok \dec_rc_rc } + connect { \LDST__imm_data__ok \LDST__imm_data__data } { \dec_bi_imm_b_ok \dec_bi_imm_b } + connect \dec_bi_sel_in \dec_LDST_in2_sel + connect \LDST__zero_a \dec_ai_immz_out + connect \dec_ai_sel_in \dec_LDST_in1_sel + connect \spr { \dec_LDST_SPR [4:0] \dec_LDST_SPR [9:5] } + connect \LDST__insn_type \dec_LDST_internal_op + connect \dec_cr_out_rc_in \dec_rc_rc + connect \dec_cr_out_sel_in \dec_LDST_cr_out + connect \dec_cr_in_sel_in \dec_LDST_cr_in + connect \dec_oe_sel_in \dec_LDST_rc_sel + connect \dec_rc_sel_in \dec_LDST_rc_sel + connect \dec_cr_out_insn_in \dec_opcode_in + connect \dec_cr_in_insn_in \dec_opcode_in + connect \insn_in$1 \dec_opcode_in + connect \insn_in \dec_opcode_in + connect \LDST__insn \dec_opcode_in +end +attribute \src "libresoc.v:121279.1-121870.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LOGICAL" +attribute \generator "nMigen" +module \dec_LOGICAL + attribute \src "libresoc.v:121832.3-121843.6" + wire width 13 $0\LOGICAL__fn_unit[12:0] + attribute \src "libresoc.v:121280.7-121280.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:121832.3-121843.6" + wire width 13 $1\LOGICAL__fn_unit[12:0] + attribute \src "libresoc.v:121736.18-121736.109" + wire $and$libresoc.v:121736$4531_Y + attribute \src "libresoc.v:121730.18-121730.112" + wire $eq$libresoc.v:121730$4525_Y + attribute \src "libresoc.v:121732.18-121732.112" + wire $eq$libresoc.v:121732$4527_Y + attribute \src "libresoc.v:121734.18-121734.110" + wire $eq$libresoc.v:121734$4529_Y + attribute \src "libresoc.v:121737.17-121737.129" + wire $eq$libresoc.v:121737$4532_Y + attribute \src "libresoc.v:121738.17-121738.129" + wire $eq$libresoc.v:121738$4533_Y + attribute \src "libresoc.v:121740.17-121740.111" + wire $eq$libresoc.v:121740$4535_Y + attribute \src "libresoc.v:121731.18-121731.109" + wire $or$libresoc.v:121731$4526_Y + attribute \src "libresoc.v:121733.18-121733.110" + wire $or$libresoc.v:121733$4528_Y + attribute \src "libresoc.v:121735.18-121735.110" + wire $or$libresoc.v:121735$4530_Y + attribute \src "libresoc.v:121739.17-121739.107" + wire $or$libresoc.v:121739$4534_Y + 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 18 \LOGICAL__data_len + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 output 3 \LOGICAL__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 4 \LOGICAL__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 5 \LOGICAL__imm_data__ok + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 12 \LOGICAL__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 19 \LOGICAL__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 2 \LOGICAL__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 10 \LOGICAL__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 13 \LOGICAL__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 16 \LOGICAL__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 17 \LOGICAL__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 8 \LOGICAL__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 9 \LOGICAL__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 15 \LOGICAL__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 7 \LOGICAL__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 6 \LOGICAL__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 14 \LOGICAL__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 11 \LOGICAL__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" + wire input 1 \bigendian + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \dec_LOGICAL_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \dec_LOGICAL_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \dec_LOGICAL_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 14 \dec_LOGICAL_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \dec_LOGICAL_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \dec_LOGICAL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 14 \dec_LOGICAL_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 8 \dec_LOGICAL_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 24 \dec_LOGICAL_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire \dec_LOGICAL_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \dec_LOGICAL_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire \dec_LOGICAL_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \dec_LOGICAL_SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 16 \dec_LOGICAL_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 10 \dec_LOGICAL_SPR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 16 \dec_LOGICAL_UI + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec_LOGICAL_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec_LOGICAL_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \dec_LOGICAL_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \dec_LOGICAL_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 13 \dec_LOGICAL_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec_LOGICAL_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 \dec_LOGICAL_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 \dec_LOGICAL_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \dec_LOGICAL_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \dec_LOGICAL_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \dec_LOGICAL_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 \dec_LOGICAL_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \dec_LOGICAL_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \dec_LOGICAL_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 6 \dec_LOGICAL_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \dec_XL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 3 \dec_X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 3 \dec_X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:296" + wire \dec_ai_immz_out + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:295" + wire width 3 \dec_ai_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \dec_bi_imm_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_bi_imm_b_ok + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:365" + wire width 4 \dec_bi_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:651" + wire width 32 \dec_cr_in_insn_in + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:650" + wire width 3 \dec_cr_in_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_cr_out_cr_bitfield_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:719" + wire width 32 \dec_cr_out_insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:717" + wire \dec_cr_out_rc_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:718" + wire width 3 \dec_cr_out_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_oe_oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_oe_oe_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:607" + wire width 2 \dec_oe_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + wire width 32 \dec_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_rc_rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_rc_rc_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:570" + wire width 2 \dec_rc_sel_in + attribute \src "libresoc.v:121280.7-121280.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:571" + wire width 32 \insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:608" + wire width 32 \insn_in$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 32 input 20 \raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:910" + wire width 10 \spr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + cell $and $and$libresoc.v:121736$4531 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$6 + connect \B \$20 + connect \Y $and$libresoc.v:121736$4531_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + cell $eq $eq$libresoc.v:121730$4525 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 10 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 10'0000010011 + connect \Y $eq$libresoc.v:121730$4525_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + cell $eq $eq$libresoc.v:121732$4527 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 10 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 10'1011010000 + connect \Y $eq$libresoc.v:121732$4527_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + cell $eq $eq$libresoc.v:121734$4529 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 6'110000 + connect \Y $eq$libresoc.v:121734$4529_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:917" + cell $eq $eq$libresoc.v:121737$4532 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \dec_LOGICAL_internal_op + connect \B 7'0110001 + connect \Y $eq$libresoc.v:121737$4532_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:918" + cell $eq $eq$libresoc.v:121738$4533 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \dec_LOGICAL_internal_op + connect \B 7'0101110 + connect \Y $eq$libresoc.v:121738$4533_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + cell $eq $eq$libresoc.v:121740$4535 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 10 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 10'0000010010 + connect \Y $eq$libresoc.v:121740$4535_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + cell $or $or$libresoc.v:121731$4526 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \B \$10 + connect \Y $or$libresoc.v:121731$4526_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + cell $or $or$libresoc.v:121733$4528 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$12 + connect \B \$14 + connect \Y $or$libresoc.v:121733$4528_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + cell $or $or$libresoc.v:121735$4530 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$16 + connect \B \$18 + connect \Y $or$libresoc.v:121735$4530_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:918" + cell $or $or$libresoc.v:121739$4534 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$2 + connect \B \$4 + connect \Y $or$libresoc.v:121739$4534_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:121741.13-121779.4" + cell \dec$154 \dec + connect \LOGICAL_BA \dec_LOGICAL_BA + connect \LOGICAL_BB \dec_LOGICAL_BB + connect \LOGICAL_BC \dec_LOGICAL_BC + connect \LOGICAL_BD \dec_LOGICAL_BD + connect \LOGICAL_BI \dec_LOGICAL_BI + connect \LOGICAL_BT \dec_LOGICAL_BT + connect \LOGICAL_DS \dec_LOGICAL_DS + connect \LOGICAL_FXM \dec_LOGICAL_FXM + connect \LOGICAL_LI \dec_LOGICAL_LI + connect \LOGICAL_OE \dec_LOGICAL_OE + connect \LOGICAL_RA \dec_LOGICAL_RA + connect \LOGICAL_Rc \dec_LOGICAL_Rc + connect \LOGICAL_SH32 \dec_LOGICAL_SH32 + connect \LOGICAL_SI \dec_LOGICAL_SI + connect \LOGICAL_SPR \dec_LOGICAL_SPR + connect \LOGICAL_UI \dec_LOGICAL_UI + connect \LOGICAL_cr_in \dec_LOGICAL_cr_in + connect \LOGICAL_cr_out \dec_LOGICAL_cr_out + connect \LOGICAL_cry_in \dec_LOGICAL_cry_in + connect \LOGICAL_cry_out \dec_LOGICAL_cry_out + connect \LOGICAL_function_unit \dec_LOGICAL_function_unit + connect \LOGICAL_in1_sel \dec_LOGICAL_in1_sel + connect \LOGICAL_in2_sel \dec_LOGICAL_in2_sel + connect \LOGICAL_internal_op \dec_LOGICAL_internal_op + connect \LOGICAL_inv_a \dec_LOGICAL_inv_a + connect \LOGICAL_inv_out \dec_LOGICAL_inv_out + connect \LOGICAL_is_32b \dec_LOGICAL_is_32b + connect \LOGICAL_ldst_len \dec_LOGICAL_ldst_len + connect \LOGICAL_rc_sel \dec_LOGICAL_rc_sel + connect \LOGICAL_sgn \dec_LOGICAL_sgn + connect \LOGICAL_sh \dec_LOGICAL_sh + connect \XL_BT \dec_XL_BT + connect \X_BF \dec_X_BF + connect \X_BFA \dec_X_BFA + connect \bigendian \bigendian + connect \opcode_in \dec_opcode_in + connect \raw_opcode_in \raw_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:121780.16-121784.4" + cell \dec_ai$161 \dec_ai + connect \LOGICAL_RA \dec_LOGICAL_RA + connect \immz_out \dec_ai_immz_out + connect \sel_in \dec_ai_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:121785.16-121796.4" + cell \dec_bi$162 \dec_bi + connect \LOGICAL_BD \dec_LOGICAL_BD + connect \LOGICAL_DS \dec_LOGICAL_DS + connect \LOGICAL_LI \dec_LOGICAL_LI + connect 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\dec_XL_BT + connect \X_BF \dec_X_BF + connect \cr_bitfield_ok \dec_cr_out_cr_bitfield_ok + connect \insn_in \dec_cr_out_insn_in + connect \rc_in \dec_cr_out_rc_in + connect \sel_in \dec_cr_out_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:121819.16-121825.4" + cell \dec_oe$156 \dec_oe + connect \LOGICAL_OE \dec_LOGICAL_OE + connect \LOGICAL_internal_op \dec_LOGICAL_internal_op + connect \oe \dec_oe_oe + connect \oe_ok \dec_oe_oe_ok + connect \sel_in \dec_oe_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:121826.16-121831.4" + cell \dec_rc$155 \dec_rc + connect \LOGICAL_Rc \dec_LOGICAL_Rc + connect \rc \dec_rc_rc + connect \rc_ok \dec_rc_rc_ok + connect \sel_in \dec_rc_sel_in + end + attribute \src "libresoc.v:121280.7-121280.20" + process $proc$libresoc.v:121280$4537 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:121832.3-121843.6" + process $proc$libresoc.v:121832$4536 + assign { } { } + assign $0\LOGICAL__fn_unit[12:0] $1\LOGICAL__fn_unit[12:0] + attribute \src "libresoc.v:121833.5-121833.29" + switch \initial + attribute \src "libresoc.v:121833.9-121833.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + switch \$22 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\LOGICAL__fn_unit[12:0] 13'0100000000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\LOGICAL__fn_unit[12:0] \dec_LOGICAL_function_unit + end + sync always + update \LOGICAL__fn_unit $0\LOGICAL__fn_unit[12:0] + end + connect \$10 $eq$libresoc.v:121730$4525_Y + connect \$12 $or$libresoc.v:121731$4526_Y + connect \$14 $eq$libresoc.v:121732$4527_Y + connect \$16 $or$libresoc.v:121733$4528_Y + connect \$18 $eq$libresoc.v:121734$4529_Y + connect \$20 $or$libresoc.v:121735$4530_Y + connect \$22 $and$libresoc.v:121736$4531_Y + connect \$2 $eq$libresoc.v:121737$4532_Y + connect \$4 $eq$libresoc.v:121738$4533_Y + connect \$6 $or$libresoc.v:121739$4534_Y + connect \$8 $eq$libresoc.v:121740$4535_Y + connect \LOGICAL__is_signed \dec_LOGICAL_sgn + connect \LOGICAL__is_32bit \dec_LOGICAL_is_32b + connect \LOGICAL__output_carry \dec_LOGICAL_cry_out + connect \LOGICAL__input_carry \dec_LOGICAL_cry_in + connect \LOGICAL__invert_out \dec_LOGICAL_inv_out + connect \LOGICAL__invert_in \dec_LOGICAL_inv_a + connect \LOGICAL__data_len \dec_LOGICAL_ldst_len + connect \LOGICAL__write_cr0 \dec_cr_out_cr_bitfield_ok + connect { \LOGICAL__oe__ok \LOGICAL__oe__oe } { \dec_oe_oe_ok \dec_oe_oe } + connect { \LOGICAL__rc__ok \LOGICAL__rc__rc } { \dec_rc_rc_ok \dec_rc_rc } + connect { \LOGICAL__imm_data__ok \LOGICAL__imm_data__data } { \dec_bi_imm_b_ok \dec_bi_imm_b } + connect \dec_bi_sel_in \dec_LOGICAL_in2_sel + connect \LOGICAL__zero_a \dec_ai_immz_out + connect \dec_ai_sel_in \dec_LOGICAL_in1_sel + connect \spr { \dec_LOGICAL_SPR [4:0] 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"Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 output 3 \MUL__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 4 \MUL__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 5 \MUL__imm_data__ok + attribute \src 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\enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute 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"/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 6 \MUL__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 10 \MUL__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" + wire input 1 \bigendian + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \dec_MUL_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \dec_MUL_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \dec_MUL_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 14 \dec_MUL_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \dec_MUL_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \dec_MUL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 14 \dec_MUL_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 8 \dec_MUL_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 24 \dec_MUL_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire \dec_MUL_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire \dec_MUL_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \dec_MUL_SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 16 \dec_MUL_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 10 \dec_MUL_SPR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 16 \dec_MUL_UI + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec_MUL_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec_MUL_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 13 \dec_MUL_function_unit + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 \dec_MUL_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 \dec_MUL_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \dec_MUL_is_32b + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \dec_MUL_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \dec_MUL_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 6 \dec_MUL_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \dec_XL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 3 \dec_X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 3 \dec_X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \dec_bi_imm_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_bi_imm_b_ok + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:365" + wire width 4 \dec_bi_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:651" + wire width 32 \dec_cr_in_insn_in + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:650" + wire width 3 \dec_cr_in_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_cr_out_cr_bitfield_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:719" + wire width 32 \dec_cr_out_insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:717" + wire \dec_cr_out_rc_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:718" + wire width 3 \dec_cr_out_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_oe_oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_oe_oe_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:607" + wire width 2 \dec_oe_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + wire width 32 \dec_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_rc_rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_rc_rc_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:570" + wire width 2 \dec_rc_sel_in + attribute \src "libresoc.v:121875.7-121875.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:571" + wire width 32 \insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:608" + wire width 32 \insn_in$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 32 input 14 \raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:910" + wire width 10 \spr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + cell $and $and$libresoc.v:122275$4544 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$6 + connect \B \$20 + connect \Y $and$libresoc.v:122275$4544_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + cell $eq $eq$libresoc.v:122269$4538 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 10 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 10'0000010011 + connect \Y $eq$libresoc.v:122269$4538_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + cell $eq $eq$libresoc.v:122271$4540 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 10 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 10'1011010000 + connect \Y $eq$libresoc.v:122271$4540_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + cell $eq $eq$libresoc.v:122273$4542 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 6'110000 + connect \Y $eq$libresoc.v:122273$4542_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:917" + cell $eq $eq$libresoc.v:122276$4545 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \dec_MUL_internal_op + connect \B 7'0110001 + connect \Y $eq$libresoc.v:122276$4545_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:918" + cell $eq $eq$libresoc.v:122277$4546 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \dec_MUL_internal_op + connect \B 7'0101110 + connect \Y $eq$libresoc.v:122277$4546_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + cell $eq $eq$libresoc.v:122279$4548 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 10 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 10'0000010010 + connect \Y $eq$libresoc.v:122279$4548_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + cell $or $or$libresoc.v:122270$4539 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \B \$10 + connect \Y $or$libresoc.v:122270$4539_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + cell $or $or$libresoc.v:122272$4541 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$12 + connect \B \$14 + connect \Y $or$libresoc.v:122272$4541_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + cell $or $or$libresoc.v:122274$4543 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$16 + connect \B \$18 + connect \Y $or$libresoc.v:122274$4543_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:918" + cell $or $or$libresoc.v:122278$4547 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$2 + connect \B \$4 + connect \Y $or$libresoc.v:122278$4547_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:122280.13-122311.4" + cell \dec$179 \dec + connect \MUL_BA \dec_MUL_BA + connect \MUL_BB \dec_MUL_BB + connect \MUL_BC \dec_MUL_BC + connect \MUL_BD \dec_MUL_BD + connect \MUL_BI \dec_MUL_BI + connect \MUL_BT \dec_MUL_BT + connect \MUL_DS \dec_MUL_DS + connect \MUL_FXM \dec_MUL_FXM + connect \MUL_LI \dec_MUL_LI + connect \MUL_OE \dec_MUL_OE + connect \MUL_Rc \dec_MUL_Rc + connect \MUL_SH32 \dec_MUL_SH32 + connect \MUL_SI \dec_MUL_SI + connect \MUL_SPR \dec_MUL_SPR + connect \MUL_UI \dec_MUL_UI + connect \MUL_cr_in \dec_MUL_cr_in + connect \MUL_cr_out \dec_MUL_cr_out + connect \MUL_function_unit \dec_MUL_function_unit + connect \MUL_in2_sel \dec_MUL_in2_sel + connect \MUL_internal_op \dec_MUL_internal_op + connect \MUL_is_32b \dec_MUL_is_32b + connect \MUL_rc_sel \dec_MUL_rc_sel + connect \MUL_sgn \dec_MUL_sgn + connect \MUL_sh \dec_MUL_sh + connect \XL_BT \dec_XL_BT + connect \X_BF \dec_X_BF + connect \X_BFA \dec_X_BFA + connect \bigendian \bigendian + connect \opcode_in \dec_opcode_in + connect \raw_opcode_in \raw_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:122312.16-122323.4" + cell \dec_bi$186 \dec_bi + connect \MUL_BD \dec_MUL_BD + connect \MUL_DS \dec_MUL_DS + connect \MUL_LI \dec_MUL_LI + connect \MUL_SH32 \dec_MUL_SH32 + connect \MUL_SI \dec_MUL_SI + connect \MUL_UI \dec_MUL_UI + connect \MUL_sh \dec_MUL_sh + connect \imm_b \dec_bi_imm_b + connect \imm_b_ok \dec_bi_imm_b_ok + connect \sel_in \dec_bi_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:122324.19-122335.4" + cell \dec_cr_in$182 \dec_cr_in + connect \MUL_BA \dec_MUL_BA + connect \MUL_BB \dec_MUL_BB + connect \MUL_BC \dec_MUL_BC + connect \MUL_BI \dec_MUL_BI + connect \MUL_BT \dec_MUL_BT + connect \MUL_FXM \dec_MUL_FXM + connect \MUL_internal_op \dec_MUL_internal_op + connect \X_BFA \dec_X_BFA + connect \insn_in \dec_cr_in_insn_in + connect \sel_in \dec_cr_in_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:122336.20-122345.4" + cell \dec_cr_out$184 \dec_cr_out + connect \MUL_FXM \dec_MUL_FXM + connect \MUL_internal_op \dec_MUL_internal_op + connect \XL_BT \dec_XL_BT + connect \X_BF \dec_X_BF + connect \cr_bitfield_ok \dec_cr_out_cr_bitfield_ok + connect \insn_in \dec_cr_out_insn_in + connect \rc_in \dec_cr_out_rc_in + connect \sel_in \dec_cr_out_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:122346.16-122352.4" + cell \dec_oe$181 \dec_oe + connect \MUL_OE \dec_MUL_OE + connect \MUL_internal_op \dec_MUL_internal_op + connect \oe \dec_oe_oe + connect \oe_ok \dec_oe_oe_ok + connect \sel_in \dec_oe_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:122353.16-122358.4" + cell \dec_rc$180 \dec_rc + connect \MUL_Rc \dec_MUL_Rc + connect \rc \dec_rc_rc + connect \rc_ok \dec_rc_rc_ok + connect \sel_in \dec_rc_sel_in + end + attribute \src "libresoc.v:121875.7-121875.20" + process $proc$libresoc.v:121875$4550 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:122359.3-122370.6" + process $proc$libresoc.v:122359$4549 + assign { } { } + assign $0\MUL__fn_unit[12:0] $1\MUL__fn_unit[12:0] + attribute \src "libresoc.v:122360.5-122360.29" + switch \initial + attribute \src "libresoc.v:122360.9-122360.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + switch \$22 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\MUL__fn_unit[12:0] 13'0100000000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\MUL__fn_unit[12:0] \dec_MUL_function_unit + end + sync always + update \MUL__fn_unit $0\MUL__fn_unit[12:0] + end + connect \$10 $eq$libresoc.v:122269$4538_Y + connect \$12 $or$libresoc.v:122270$4539_Y + connect \$14 $eq$libresoc.v:122271$4540_Y + connect \$16 $or$libresoc.v:122272$4541_Y + connect \$18 $eq$libresoc.v:122273$4542_Y + connect \$20 $or$libresoc.v:122274$4543_Y + connect \$22 $and$libresoc.v:122275$4544_Y + connect \$2 $eq$libresoc.v:122276$4545_Y + connect \$4 $eq$libresoc.v:122277$4546_Y + connect \$6 $or$libresoc.v:122278$4547_Y + connect \$8 $eq$libresoc.v:122279$4548_Y + connect \MUL__is_signed \dec_MUL_sgn + connect \MUL__is_32bit \dec_MUL_is_32b + connect \MUL__write_cr0 \dec_cr_out_cr_bitfield_ok + connect { \MUL__oe__ok \MUL__oe__oe } { \dec_oe_oe_ok \dec_oe_oe } + connect { \MUL__rc__ok \MUL__rc__rc } { \dec_rc_rc_ok \dec_rc_rc } + connect { \MUL__imm_data__ok \MUL__imm_data__data } { \dec_bi_imm_b_ok \dec_bi_imm_b } + connect \dec_bi_sel_in \dec_MUL_in2_sel + connect \spr { \dec_MUL_SPR [4:0] \dec_MUL_SPR [9:5] } + connect \MUL__insn_type \dec_MUL_internal_op + connect \dec_cr_out_rc_in \dec_rc_rc + connect \dec_cr_out_sel_in \dec_MUL_cr_out + connect \dec_cr_in_sel_in \dec_MUL_cr_in + connect \dec_oe_sel_in \dec_MUL_rc_sel + connect \dec_rc_sel_in \dec_MUL_rc_sel + connect \dec_cr_out_insn_in \dec_opcode_in + connect \dec_cr_in_insn_in \dec_opcode_in + connect \insn_in$1 \dec_opcode_in + connect \insn_in \dec_opcode_in + connect \MUL__insn \dec_opcode_in +end +attribute \src "libresoc.v:122394.1-122942.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SHIFT_ROT" +attribute \generator "nMigen" +module \dec_SHIFT_ROT + attribute \src "libresoc.v:122906.3-122917.6" + wire width 13 $0\SHIFT_ROT__fn_unit[12:0] + attribute \src "libresoc.v:122395.7-122395.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:122906.3-122917.6" + wire width 13 $1\SHIFT_ROT__fn_unit[12:0] + attribute \src "libresoc.v:122819.18-122819.109" + wire $and$libresoc.v:122819$4557_Y + attribute \src "libresoc.v:122813.18-122813.112" + wire $eq$libresoc.v:122813$4551_Y + attribute \src "libresoc.v:122815.18-122815.112" + wire $eq$libresoc.v:122815$4553_Y + attribute \src "libresoc.v:122817.18-122817.110" + wire $eq$libresoc.v:122817$4555_Y + attribute \src "libresoc.v:122820.17-122820.131" + wire $eq$libresoc.v:122820$4558_Y + attribute \src "libresoc.v:122821.17-122821.131" + wire $eq$libresoc.v:122821$4559_Y + attribute \src "libresoc.v:122823.17-122823.111" + wire $eq$libresoc.v:122823$4561_Y + attribute \src "libresoc.v:122814.18-122814.109" + wire $or$libresoc.v:122814$4552_Y + attribute \src "libresoc.v:122816.18-122816.110" + wire $or$libresoc.v:122816$4554_Y + attribute \src "libresoc.v:122818.18-122818.110" + wire $or$libresoc.v:122818$4556_Y + attribute \src "libresoc.v:122822.17-122822.107" + wire $or$libresoc.v:122822$4560_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + wire \$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + wire \$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + wire \$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:917" + wire \$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + wire \$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + wire \$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:918" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:918" + wire \$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + wire \$8 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 output 3 \SHIFT_ROT__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 4 \SHIFT_ROT__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 5 \SHIFT_ROT__imm_data__ok + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 12 \SHIFT_ROT__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 14 \SHIFT_ROT__input_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 18 \SHIFT_ROT__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 2 \SHIFT_ROT__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 11 \SHIFT_ROT__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 16 \SHIFT_ROT__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 17 \SHIFT_ROT__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 8 \SHIFT_ROT__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 9 \SHIFT_ROT__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 13 \SHIFT_ROT__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 15 \SHIFT_ROT__output_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 7 \SHIFT_ROT__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 6 \SHIFT_ROT__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 10 \SHIFT_ROT__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" + wire input 1 \bigendian + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \dec_SHIFT_ROT_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \dec_SHIFT_ROT_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \dec_SHIFT_ROT_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 14 \dec_SHIFT_ROT_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \dec_SHIFT_ROT_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \dec_SHIFT_ROT_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 14 \dec_SHIFT_ROT_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 8 \dec_SHIFT_ROT_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 24 \dec_SHIFT_ROT_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire \dec_SHIFT_ROT_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire \dec_SHIFT_ROT_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \dec_SHIFT_ROT_SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 16 \dec_SHIFT_ROT_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 10 \dec_SHIFT_ROT_SPR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 16 \dec_SHIFT_ROT_UI + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec_SHIFT_ROT_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec_SHIFT_ROT_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \dec_SHIFT_ROT_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \dec_SHIFT_ROT_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 13 \dec_SHIFT_ROT_function_unit + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 4 \dec_SHIFT_ROT_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 \dec_SHIFT_ROT_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \dec_SHIFT_ROT_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \dec_SHIFT_ROT_is_32b + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \dec_SHIFT_ROT_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \dec_SHIFT_ROT_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 6 \dec_SHIFT_ROT_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \dec_XL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 3 \dec_X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 3 \dec_X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \dec_bi_imm_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_bi_imm_b_ok + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:365" + wire width 4 \dec_bi_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:651" + wire width 32 \dec_cr_in_insn_in + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:650" + wire width 3 \dec_cr_in_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_cr_out_cr_bitfield_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:719" + wire width 32 \dec_cr_out_insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:717" + wire \dec_cr_out_rc_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:718" + wire width 3 \dec_cr_out_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_oe_oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_oe_oe_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:607" + wire width 2 \dec_oe_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + wire width 32 \dec_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_rc_rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_rc_rc_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:570" + wire width 2 \dec_rc_sel_in + attribute \src "libresoc.v:122395.7-122395.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:571" + wire width 32 \insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:608" + wire width 32 \insn_in$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 32 input 19 \raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:910" + wire width 10 \spr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + cell $and $and$libresoc.v:122819$4557 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$6 + connect \B \$20 + connect \Y $and$libresoc.v:122819$4557_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + cell $eq $eq$libresoc.v:122813$4551 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 10 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 10'0000010011 + connect \Y $eq$libresoc.v:122813$4551_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + cell $eq $eq$libresoc.v:122815$4553 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 10 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 10'1011010000 + connect \Y $eq$libresoc.v:122815$4553_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + cell $eq $eq$libresoc.v:122817$4555 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 6'110000 + connect \Y $eq$libresoc.v:122817$4555_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:917" + cell $eq $eq$libresoc.v:122820$4558 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \dec_SHIFT_ROT_internal_op + connect \B 7'0110001 + connect \Y $eq$libresoc.v:122820$4558_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:918" + cell $eq $eq$libresoc.v:122821$4559 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \dec_SHIFT_ROT_internal_op + connect \B 7'0101110 + connect \Y $eq$libresoc.v:122821$4559_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + cell $eq $eq$libresoc.v:122823$4561 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 10 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 10'0000010010 + connect \Y $eq$libresoc.v:122823$4561_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + cell $or $or$libresoc.v:122814$4552 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \B \$10 + connect \Y $or$libresoc.v:122814$4552_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + cell $or $or$libresoc.v:122816$4554 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$12 + connect \B \$14 + connect \Y $or$libresoc.v:122816$4554_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + cell $or $or$libresoc.v:122818$4556 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$16 + connect \B \$18 + connect \Y $or$libresoc.v:122818$4556_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:918" + cell $or $or$libresoc.v:122822$4560 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$2 + connect \B \$4 + connect \Y $or$libresoc.v:122822$4560_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:122824.13-122858.4" + cell \dec$187 \dec + connect \SHIFT_ROT_BA \dec_SHIFT_ROT_BA + connect \SHIFT_ROT_BB \dec_SHIFT_ROT_BB + connect \SHIFT_ROT_BC \dec_SHIFT_ROT_BC + connect \SHIFT_ROT_BD \dec_SHIFT_ROT_BD + connect \SHIFT_ROT_BI \dec_SHIFT_ROT_BI + connect \SHIFT_ROT_BT \dec_SHIFT_ROT_BT + connect \SHIFT_ROT_DS \dec_SHIFT_ROT_DS + connect \SHIFT_ROT_FXM \dec_SHIFT_ROT_FXM + connect \SHIFT_ROT_LI \dec_SHIFT_ROT_LI + connect \SHIFT_ROT_OE \dec_SHIFT_ROT_OE + connect \SHIFT_ROT_Rc \dec_SHIFT_ROT_Rc + connect \SHIFT_ROT_SH32 \dec_SHIFT_ROT_SH32 + connect \SHIFT_ROT_SI \dec_SHIFT_ROT_SI + connect \SHIFT_ROT_SPR \dec_SHIFT_ROT_SPR + connect \SHIFT_ROT_UI \dec_SHIFT_ROT_UI + connect \SHIFT_ROT_cr_in \dec_SHIFT_ROT_cr_in + connect \SHIFT_ROT_cr_out \dec_SHIFT_ROT_cr_out + connect \SHIFT_ROT_cry_in \dec_SHIFT_ROT_cry_in + connect \SHIFT_ROT_cry_out \dec_SHIFT_ROT_cry_out + connect \SHIFT_ROT_function_unit \dec_SHIFT_ROT_function_unit + connect \SHIFT_ROT_in2_sel \dec_SHIFT_ROT_in2_sel + connect \SHIFT_ROT_internal_op \dec_SHIFT_ROT_internal_op + connect \SHIFT_ROT_inv_a \dec_SHIFT_ROT_inv_a + connect \SHIFT_ROT_is_32b \dec_SHIFT_ROT_is_32b + connect \SHIFT_ROT_rc_sel \dec_SHIFT_ROT_rc_sel + connect \SHIFT_ROT_sgn \dec_SHIFT_ROT_sgn + connect \SHIFT_ROT_sh \dec_SHIFT_ROT_sh + connect \XL_BT \dec_XL_BT + connect \X_BF \dec_X_BF + connect \X_BFA \dec_X_BFA + connect \bigendian \bigendian + connect \opcode_in \dec_opcode_in + connect \raw_opcode_in \raw_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:122859.16-122870.4" + cell \dec_bi$194 \dec_bi + connect \SHIFT_ROT_BD \dec_SHIFT_ROT_BD + connect \SHIFT_ROT_DS \dec_SHIFT_ROT_DS + connect \SHIFT_ROT_LI \dec_SHIFT_ROT_LI + connect \SHIFT_ROT_SH32 \dec_SHIFT_ROT_SH32 + connect \SHIFT_ROT_SI \dec_SHIFT_ROT_SI + connect \SHIFT_ROT_UI \dec_SHIFT_ROT_UI + connect \SHIFT_ROT_sh \dec_SHIFT_ROT_sh + connect \imm_b \dec_bi_imm_b + connect \imm_b_ok \dec_bi_imm_b_ok + connect \sel_in \dec_bi_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:122871.19-122882.4" + cell \dec_cr_in$190 \dec_cr_in + connect \SHIFT_ROT_BA \dec_SHIFT_ROT_BA + connect \SHIFT_ROT_BB \dec_SHIFT_ROT_BB + connect \SHIFT_ROT_BC \dec_SHIFT_ROT_BC + connect \SHIFT_ROT_BI \dec_SHIFT_ROT_BI + connect \SHIFT_ROT_BT \dec_SHIFT_ROT_BT + connect \SHIFT_ROT_FXM \dec_SHIFT_ROT_FXM + connect \SHIFT_ROT_internal_op \dec_SHIFT_ROT_internal_op + connect \X_BFA \dec_X_BFA + connect \insn_in \dec_cr_in_insn_in + connect \sel_in \dec_cr_in_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:122883.20-122892.4" + cell \dec_cr_out$192 \dec_cr_out + connect \SHIFT_ROT_FXM \dec_SHIFT_ROT_FXM + connect \SHIFT_ROT_internal_op \dec_SHIFT_ROT_internal_op + connect \XL_BT \dec_XL_BT + connect \X_BF \dec_X_BF + connect \cr_bitfield_ok \dec_cr_out_cr_bitfield_ok + connect \insn_in \dec_cr_out_insn_in + connect \rc_in \dec_cr_out_rc_in + connect \sel_in \dec_cr_out_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:122893.16-122899.4" + cell \dec_oe$189 \dec_oe + connect \SHIFT_ROT_OE \dec_SHIFT_ROT_OE + connect \SHIFT_ROT_internal_op \dec_SHIFT_ROT_internal_op + connect \oe \dec_oe_oe + connect \oe_ok \dec_oe_oe_ok + connect \sel_in \dec_oe_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:122900.16-122905.4" + cell \dec_rc$188 \dec_rc + connect \SHIFT_ROT_Rc \dec_SHIFT_ROT_Rc + connect \rc \dec_rc_rc + connect \rc_ok \dec_rc_rc_ok + connect \sel_in \dec_rc_sel_in + end + attribute \src "libresoc.v:122395.7-122395.20" + process $proc$libresoc.v:122395$4563 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:122906.3-122917.6" + process $proc$libresoc.v:122906$4562 + assign { } { } + assign $0\SHIFT_ROT__fn_unit[12:0] $1\SHIFT_ROT__fn_unit[12:0] + attribute \src "libresoc.v:122907.5-122907.29" + switch \initial + attribute \src "libresoc.v:122907.9-122907.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + switch \$22 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\SHIFT_ROT__fn_unit[12:0] 13'0100000000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\SHIFT_ROT__fn_unit[12:0] \dec_SHIFT_ROT_function_unit + end + sync always + update \SHIFT_ROT__fn_unit $0\SHIFT_ROT__fn_unit[12:0] + end + connect \$10 $eq$libresoc.v:122813$4551_Y + connect \$12 $or$libresoc.v:122814$4552_Y + connect \$14 $eq$libresoc.v:122815$4553_Y + connect \$16 $or$libresoc.v:122816$4554_Y + connect \$18 $eq$libresoc.v:122817$4555_Y + connect \$20 $or$libresoc.v:122818$4556_Y + connect \$22 $and$libresoc.v:122819$4557_Y + connect \$2 $eq$libresoc.v:122820$4558_Y + connect \$4 $eq$libresoc.v:122821$4559_Y + connect \$6 $or$libresoc.v:122822$4560_Y + connect \$8 $eq$libresoc.v:122823$4561_Y + connect \SHIFT_ROT__is_signed \dec_SHIFT_ROT_sgn + connect \SHIFT_ROT__is_32bit \dec_SHIFT_ROT_is_32b + connect \SHIFT_ROT__output_carry \dec_SHIFT_ROT_cry_out + connect \SHIFT_ROT__input_carry \dec_SHIFT_ROT_cry_in + connect \SHIFT_ROT__invert_in \dec_SHIFT_ROT_inv_a + connect \SHIFT_ROT__output_cr \dec_SHIFT_ROT_cr_out [0] + connect \SHIFT_ROT__input_cr \dec_SHIFT_ROT_cr_in [0] + connect \SHIFT_ROT__write_cr0 \dec_cr_out_cr_bitfield_ok + connect { \SHIFT_ROT__oe__ok \SHIFT_ROT__oe__oe } { \dec_oe_oe_ok \dec_oe_oe } + connect { \SHIFT_ROT__rc__ok \SHIFT_ROT__rc__rc } { \dec_rc_rc_ok \dec_rc_rc } + connect { \SHIFT_ROT__imm_data__ok \SHIFT_ROT__imm_data__data } { \dec_bi_imm_b_ok \dec_bi_imm_b } + connect \dec_bi_sel_in \dec_SHIFT_ROT_in2_sel + connect \spr { \dec_SHIFT_ROT_SPR [4:0] \dec_SHIFT_ROT_SPR [9:5] } + connect \SHIFT_ROT__insn_type \dec_SHIFT_ROT_internal_op + connect \dec_cr_out_rc_in \dec_rc_rc + connect \dec_cr_out_sel_in \dec_SHIFT_ROT_cr_out + connect \dec_cr_in_sel_in \dec_SHIFT_ROT_cr_in + connect \dec_oe_sel_in \dec_SHIFT_ROT_rc_sel + connect \dec_rc_sel_in \dec_SHIFT_ROT_rc_sel + connect \dec_cr_out_insn_in \dec_opcode_in + connect \dec_cr_in_insn_in \dec_opcode_in + connect \insn_in$1 \dec_opcode_in + connect \insn_in \dec_opcode_in + connect \SHIFT_ROT__insn \dec_opcode_in +end +attribute \src "libresoc.v:122946.1-123353.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SPR" +attribute \generator "nMigen" +module \dec_SPR + attribute \src "libresoc.v:123328.3-123339.6" + wire width 13 $0\SPR__fn_unit[12:0] + attribute \src "libresoc.v:122947.7-122947.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:123328.3-123339.6" + wire width 13 $1\SPR__fn_unit[12:0] + attribute \src "libresoc.v:123269.18-123269.109" + wire $and$libresoc.v:123269$4570_Y + attribute \src "libresoc.v:123263.18-123263.112" + wire $eq$libresoc.v:123263$4564_Y + attribute \src "libresoc.v:123265.18-123265.112" + wire $eq$libresoc.v:123265$4566_Y + attribute \src "libresoc.v:123267.18-123267.110" + wire $eq$libresoc.v:123267$4568_Y + attribute \src "libresoc.v:123270.17-123270.125" + wire $eq$libresoc.v:123270$4571_Y + attribute \src "libresoc.v:123271.17-123271.125" + wire $eq$libresoc.v:123271$4572_Y + attribute \src "libresoc.v:123273.17-123273.111" + wire $eq$libresoc.v:123273$4574_Y + attribute \src "libresoc.v:123264.18-123264.109" + wire $or$libresoc.v:123264$4565_Y + attribute \src "libresoc.v:123266.18-123266.110" + wire $or$libresoc.v:123266$4567_Y + attribute \src "libresoc.v:123268.18-123268.110" + wire $or$libresoc.v:123268$4569_Y + attribute \src "libresoc.v:123272.17-123272.107" + wire $or$libresoc.v:123272$4573_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + wire \$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + wire \$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + wire \$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:917" + wire \$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + wire \$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + wire \$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:918" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:918" + wire \$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + wire \$8 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 output 3 \SPR__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 4 \SPR__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 2 \SPR__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 5 \SPR__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:464" + wire input 1 \bigendian + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \dec_SPR_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \dec_SPR_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \dec_SPR_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \dec_SPR_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 \dec_SPR_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 8 \dec_SPR_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire \dec_SPR_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire \dec_SPR_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 10 \dec_SPR_SPR + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec_SPR_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 3 \dec_SPR_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 13 \dec_SPR_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 \dec_SPR_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:196" + wire \dec_SPR_is_32b + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 \dec_SPR_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 \dec_XL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 3 \dec_X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 3 \dec_X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:651" + wire width 32 \dec_cr_in_insn_in + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:650" + wire width 3 \dec_cr_in_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:719" + wire width 32 \dec_cr_out_insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:717" + wire \dec_cr_out_rc_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:718" + wire width 3 \dec_cr_out_sel_in + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:607" + wire width 2 \dec_oe_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:303" + wire width 32 \dec_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec_rc_rc + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:570" + wire width 2 \dec_rc_sel_in + attribute \src "libresoc.v:122947.7-122947.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:571" + wire width 32 \insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:608" + wire width 32 \insn_in$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:463" + wire width 32 input 6 \raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:910" + wire width 10 \spr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + cell $and $and$libresoc.v:123269$4570 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$6 + connect \B \$20 + connect \Y $and$libresoc.v:123269$4570_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + cell $eq $eq$libresoc.v:123263$4564 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 10 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 10'0000010011 + connect \Y $eq$libresoc.v:123263$4564_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + cell $eq $eq$libresoc.v:123265$4566 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 10 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 10'1011010000 + connect \Y $eq$libresoc.v:123265$4566_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + cell $eq $eq$libresoc.v:123267$4568 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 6'110000 + connect \Y $eq$libresoc.v:123267$4568_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:917" + cell $eq $eq$libresoc.v:123270$4571 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \dec_SPR_internal_op + connect \B 7'0110001 + connect \Y $eq$libresoc.v:123270$4571_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:918" + cell $eq $eq$libresoc.v:123271$4572 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \dec_SPR_internal_op + connect \B 7'0101110 + connect \Y $eq$libresoc.v:123271$4572_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + cell $eq $eq$libresoc.v:123273$4574 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 10 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 10'0000010010 + connect \Y $eq$libresoc.v:123273$4574_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + cell $or $or$libresoc.v:123264$4565 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \B \$10 + connect \Y $or$libresoc.v:123264$4565_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + cell $or $or$libresoc.v:123266$4567 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$12 + connect \B \$14 + connect \Y $or$libresoc.v:123266$4567_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + cell $or $or$libresoc.v:123268$4569 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$16 + connect \B \$18 + connect \Y $or$libresoc.v:123268$4569_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:918" + cell $or $or$libresoc.v:123272$4573 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$2 + connect \B \$4 + connect \Y $or$libresoc.v:123272$4573_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:123274.13-123296.4" + cell \dec$163 \dec + connect \SPR_BA \dec_SPR_BA + connect \SPR_BB \dec_SPR_BB + connect \SPR_BC \dec_SPR_BC + connect \SPR_BI \dec_SPR_BI + connect \SPR_BT \dec_SPR_BT + connect \SPR_FXM \dec_SPR_FXM + connect \SPR_OE \dec_SPR_OE + connect \SPR_Rc \dec_SPR_Rc + connect \SPR_SPR \dec_SPR_SPR + connect \SPR_cr_in \dec_SPR_cr_in + connect \SPR_cr_out \dec_SPR_cr_out + connect \SPR_function_unit \dec_SPR_function_unit + connect \SPR_internal_op \dec_SPR_internal_op + connect \SPR_is_32b \dec_SPR_is_32b + connect \SPR_rc_sel \dec_SPR_rc_sel + connect \XL_BT \dec_XL_BT + connect \X_BF \dec_X_BF + connect \X_BFA \dec_X_BFA + connect \bigendian \bigendian + connect \opcode_in \dec_opcode_in + connect \raw_opcode_in \raw_opcode_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:123297.19-123308.4" + cell \dec_cr_in$166 \dec_cr_in + connect \SPR_BA \dec_SPR_BA + connect \SPR_BB \dec_SPR_BB + connect \SPR_BC \dec_SPR_BC + connect \SPR_BI \dec_SPR_BI + connect \SPR_BT \dec_SPR_BT + connect \SPR_FXM \dec_SPR_FXM + connect \SPR_internal_op \dec_SPR_internal_op + connect \X_BFA \dec_X_BFA + connect \insn_in \dec_cr_in_insn_in + connect \sel_in \dec_cr_in_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:123309.20-123317.4" + cell \dec_cr_out$168 \dec_cr_out + connect \SPR_FXM \dec_SPR_FXM + connect \SPR_internal_op \dec_SPR_internal_op + connect \XL_BT \dec_XL_BT + connect \X_BF \dec_X_BF + connect \insn_in \dec_cr_out_insn_in + connect \rc_in \dec_cr_out_rc_in + connect \sel_in \dec_cr_out_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:123318.16-123322.4" + cell \dec_oe$165 \dec_oe + connect \SPR_OE \dec_SPR_OE + connect \SPR_internal_op \dec_SPR_internal_op + connect \sel_in \dec_oe_sel_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:123323.16-123327.4" + cell \dec_rc$164 \dec_rc + connect \SPR_Rc \dec_SPR_Rc + connect \rc \dec_rc_rc + connect \sel_in \dec_rc_sel_in + end + attribute \src "libresoc.v:122947.7-122947.20" + process $proc$libresoc.v:122947$4576 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:123328.3-123339.6" + process $proc$libresoc.v:123328$4575 + assign { } { } + assign $0\SPR__fn_unit[12:0] $1\SPR__fn_unit[12:0] + attribute \src "libresoc.v:123329.5-123329.29" + switch \initial + attribute \src "libresoc.v:123329.9-123329.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + switch \$22 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\SPR__fn_unit[12:0] 13'0100000000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\SPR__fn_unit[12:0] \dec_SPR_function_unit + end + sync always + update \SPR__fn_unit $0\SPR__fn_unit[12:0] + end + connect \$10 $eq$libresoc.v:123263$4564_Y + connect \$12 $or$libresoc.v:123264$4565_Y + connect \$14 $eq$libresoc.v:123265$4566_Y + connect \$16 $or$libresoc.v:123266$4567_Y + connect \$18 $eq$libresoc.v:123267$4568_Y + connect \$20 $or$libresoc.v:123268$4569_Y + connect \$22 $and$libresoc.v:123269$4570_Y + connect \$2 $eq$libresoc.v:123270$4571_Y + connect \$4 $eq$libresoc.v:123271$4572_Y + connect \$6 $or$libresoc.v:123272$4573_Y + connect \$8 $eq$libresoc.v:123273$4574_Y + connect \SPR__is_32bit \dec_SPR_is_32b + connect \spr { \dec_SPR_SPR [4:0] \dec_SPR_SPR [9:5] } + connect \SPR__insn_type \dec_SPR_internal_op + connect \dec_cr_out_rc_in \dec_rc_rc + connect \dec_cr_out_sel_in \dec_SPR_cr_out + connect \dec_cr_in_sel_in \dec_SPR_cr_in + connect \dec_oe_sel_in \dec_SPR_rc_sel + connect \dec_rc_sel_in \dec_SPR_rc_sel + connect \dec_cr_out_insn_in \dec_opcode_in + connect \dec_cr_in_insn_in \dec_opcode_in + connect \insn_in$1 \dec_opcode_in + connect \insn_in \dec_opcode_in + connect \SPR__insn \dec_opcode_in +end +attribute \src "libresoc.v:123357.1-123869.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_a" +attribute \generator "nMigen" +module \dec_a + attribute \src "libresoc.v:123797.3-123832.6" + wire width 3 $0\fast_a[2:0] + attribute \src "libresoc.v:123797.3-123832.6" + wire $0\fast_a_ok[0:0] + attribute \src "libresoc.v:123358.7-123358.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:123765.3-123780.6" + wire width 5 $0\reg_a[4:0] + attribute \src "libresoc.v:123781.3-123796.6" + wire $0\reg_a_ok[0:0] + attribute \src "libresoc.v:123833.3-123843.6" + wire width 10 $0\spr[9:0] + attribute \src "libresoc.v:123855.3-123866.6" + wire width 10 $0\spr_a[9:0] + attribute \src "libresoc.v:123855.3-123866.6" + wire $0\spr_a_ok[0:0] + attribute \src "libresoc.v:123844.3-123854.6" + wire width 10 $0\sprmap_spr_i[9:0] + attribute \src "libresoc.v:123797.3-123832.6" + wire width 3 $1\fast_a[2:0] + attribute \src "libresoc.v:123797.3-123832.6" + wire $1\fast_a_ok[0:0] + attribute \src "libresoc.v:123765.3-123780.6" + wire width 5 $1\reg_a[4:0] + attribute \src "libresoc.v:123781.3-123796.6" + wire $1\reg_a_ok[0:0] + attribute \src "libresoc.v:123833.3-123843.6" + wire width 10 $1\spr[9:0] + attribute \src "libresoc.v:123855.3-123866.6" + wire width 10 $1\spr_a[9:0] + attribute \src "libresoc.v:123855.3-123866.6" + wire $1\spr_a_ok[0:0] + attribute \src "libresoc.v:123844.3-123854.6" + wire width 10 $1\sprmap_spr_i[9:0] + attribute \src "libresoc.v:123797.3-123832.6" + wire width 3 $2\fast_a[2:0] + attribute \src "libresoc.v:123797.3-123832.6" + wire $2\fast_a_ok[0:0] + attribute \src "libresoc.v:123765.3-123780.6" + wire width 5 $2\reg_a[4:0] + attribute \src "libresoc.v:123781.3-123796.6" + wire $2\reg_a_ok[0:0] + attribute \src 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$ne$libresoc.v:123747$4581_Y + attribute \src "libresoc.v:123756.17-123756.108" + wire $ne$libresoc.v:123756$4590_Y + attribute \src "libresoc.v:123752.18-123752.105" + wire $not$libresoc.v:123752$4586_Y + attribute \src "libresoc.v:123753.18-123753.108" + wire $not$libresoc.v:123753$4587_Y + attribute \src "libresoc.v:123743.17-123743.107" + wire $or$libresoc.v:123743$4577_Y + attribute \src "libresoc.v:123750.18-123750.110" + wire $or$libresoc.v:123750$4584_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:245" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:246" + wire \$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:246" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:246" + wire \$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:263" + wire \$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" + wire \$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:245" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:246" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:246" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:246" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 input 11 \BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 input 10 \RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 input 9 \RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 10 input 1 \SPR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 10 input 12 \XL_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 output 7 \fast_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 8 \fast_a_ok + attribute \src "libresoc.v:123358.7-123358.15" + wire \initial + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 input 13 \internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:242" + wire width 5 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 5 output 3 \reg_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 4 \reg_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:252" + wire width 5 \rs + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:228" + wire width 3 input 2 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" + wire width 10 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\enum_value_0010011001 "FSCR" + attribute \enum_value_0010011101 "UAMOR" + attribute \enum_value_0010011110 "GSR" + attribute \enum_value_0010011111 "PSPB" + attribute \enum_value_0010110000 "DPDES" + attribute \enum_value_0010110100 "DAWR0" + attribute \enum_value_0010111010 "RPR" + attribute \enum_value_0010111011 "CIABR" + attribute \enum_value_0010111100 "DAWRX0" + attribute \enum_value_0010111110 "HFSCR" + attribute \enum_value_0100000000 "VRSAVE" + attribute \enum_value_0100000011 "SPRG3" + attribute \enum_value_0100001100 "TB" + attribute \enum_value_0100001101 "TBU" + attribute \enum_value_0100010000 "SPRG0_priv" + attribute \enum_value_0100010001 "SPRG1_priv" + attribute \enum_value_0100010010 "SPRG2_priv" + attribute \enum_value_0100010011 "SPRG3_priv" + attribute \enum_value_0100011011 "CIR" + attribute \enum_value_0100011100 "TBL" + attribute \enum_value_0100011101 "TBU_hypv" + attribute \enum_value_0100011110 "TBU40" + attribute \enum_value_0100011111 "PVR" + attribute \enum_value_0100110000 "HSPRG0" + attribute \enum_value_0100110001 "HSPRG1" + attribute \enum_value_0100110010 "HDSISR" + attribute \enum_value_0100110011 "HDAR" + attribute \enum_value_0100110100 "SPURR" + attribute \enum_value_0100110101 "PURR" + attribute \enum_value_0100110110 "HDEC" + attribute \enum_value_0100111001 "HRMOR" + attribute \enum_value_0100111010 "HSRR0" + attribute \enum_value_0100111011 "HSRR1" + attribute \enum_value_0100111110 "LPCR" + attribute \enum_value_0100111111 "LPIDR" + attribute \enum_value_0101010000 "HMER" + attribute \enum_value_0101010001 "HMEER" + attribute \enum_value_0101010010 "PCR" + attribute \enum_value_0101010011 "HEIR" + attribute \enum_value_0101011101 "AMOR" + attribute \enum_value_0110111110 "TIR" + attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1011000000 "SVSTATE" + attribute \enum_value_1011010000 "SVSRR0" + attribute \enum_value_1100000000 "SIER" + attribute \enum_value_1100000001 "MMCR2" + attribute \enum_value_1100000010 "MMCRA" + attribute \enum_value_1100000011 "PMC1" + attribute \enum_value_1100000100 "PMC2" + attribute \enum_value_1100000101 "PMC3" + attribute \enum_value_1100000110 "PMC4" + attribute \enum_value_1100000111 "PMC5" + attribute \enum_value_1100001000 "PMC6" + attribute \enum_value_1100001011 "MMCR0" + attribute \enum_value_1100001100 "SIAR" + attribute \enum_value_1100001101 "SDAR" + attribute \enum_value_1100001110 "MMCR1" + attribute \enum_value_1100010000 "SIER_priv" + attribute \enum_value_1100010001 "MMCR2_priv" + attribute \enum_value_1100010010 "MMCRA_priv" + attribute \enum_value_1100010011 "PMC1_priv" + attribute \enum_value_1100010100 "PMC2_priv" + attribute \enum_value_1100010101 "PMC3_priv" + attribute \enum_value_1100010110 "PMC4_priv" + attribute \enum_value_1100010111 "PMC5_priv" + attribute \enum_value_1100011000 "PMC6_priv" + attribute \enum_value_1100011011 "MMCR0_priv" + attribute \enum_value_1100011100 "SIAR_priv" + attribute \enum_value_1100011101 "SDAR_priv" + attribute \enum_value_1100011110 "MMCR1_priv" + attribute \enum_value_1100100000 "BESCRS" + attribute \enum_value_1100100001 "BESCRSU" + attribute \enum_value_1100100010 "BESCRR" + attribute \enum_value_1100100011 "BESCRRU" + attribute \enum_value_1100100100 "EBBHR" + attribute \enum_value_1100100101 "EBBRR" + attribute \enum_value_1100100110 "BESCR" + attribute \enum_value_1100101000 "reserved808" + attribute \enum_value_1100101001 "reserved809" + attribute \enum_value_1100101010 "reserved810" + attribute \enum_value_1100101011 "reserved811" + attribute \enum_value_1100101111 "TAR" + attribute \enum_value_1100110000 "ASDR" + attribute \enum_value_1100110111 "PSSCR" + attribute \enum_value_1101010000 "IC" + attribute \enum_value_1101010001 "VTB" + attribute \enum_value_1101010111 "PSSCR_hypv" + attribute \enum_value_1110000000 "PPR" + attribute \enum_value_1110000010 "PPR32" + attribute \enum_value_1111111111 "PIR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 10 output 5 \spr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 6 \spr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 \sprmap_fast_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \sprmap_fast_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + wire width 10 \sprmap_spr_i + attribute \enum_base_type "SPR" + attribute \enum_value_0000000001 "XER" + attribute \enum_value_0000000011 "DSCR" + attribute \enum_value_0000001000 "LR" + attribute \enum_value_0000001001 "CTR" + attribute \enum_value_0000001101 "AMR" + attribute \enum_value_0000010001 "DSCR_priv" + attribute \enum_value_0000010010 "DSISR" + attribute \enum_value_0000010011 "DAR" + attribute \enum_value_0000010110 "DEC" + attribute \enum_value_0000011010 "SRR0" + attribute \enum_value_0000011011 "SRR1" + attribute \enum_value_0000011100 "CFAR" + attribute \enum_value_0000011101 "AMR_priv" + attribute \enum_value_0000110000 "PIDR" + attribute \enum_value_0000111101 "IAMR" + attribute \enum_value_0010000000 "TFHAR" + attribute \enum_value_0010000001 "TFIAR" + attribute \enum_value_0010000010 "TEXASR" + attribute \enum_value_0010000011 "TEXASRU" + attribute \enum_value_0010001000 "CTRL" + attribute \enum_value_0010010000 "TIDR" + attribute \enum_value_0010011000 "CTRL_priv" + attribute \enum_value_0010011001 "FSCR" + attribute \enum_value_0010011101 "UAMOR" + attribute \enum_value_0010011110 "GSR" + attribute \enum_value_0010011111 "PSPB" + attribute \enum_value_0010110000 "DPDES" + attribute \enum_value_0010110100 "DAWR0" + attribute \enum_value_0010111010 "RPR" + attribute \enum_value_0010111011 "CIABR" + attribute \enum_value_0010111100 "DAWRX0" + attribute \enum_value_0010111110 "HFSCR" + attribute \enum_value_0100000000 "VRSAVE" + attribute \enum_value_0100000011 "SPRG3" + attribute \enum_value_0100001100 "TB" + attribute \enum_value_0100001101 "TBU" + attribute \enum_value_0100010000 "SPRG0_priv" + attribute \enum_value_0100010001 "SPRG1_priv" + attribute \enum_value_0100010010 "SPRG2_priv" + attribute \enum_value_0100010011 "SPRG3_priv" + attribute \enum_value_0100011011 "CIR" + attribute \enum_value_0100011100 "TBL" + attribute \enum_value_0100011101 "TBU_hypv" + attribute \enum_value_0100011110 "TBU40" + attribute \enum_value_0100011111 "PVR" + attribute \enum_value_0100110000 "HSPRG0" + attribute \enum_value_0100110001 "HSPRG1" + attribute \enum_value_0100110010 "HDSISR" + attribute \enum_value_0100110011 "HDAR" + attribute \enum_value_0100110100 "SPURR" + attribute \enum_value_0100110101 "PURR" + attribute \enum_value_0100110110 "HDEC" + attribute \enum_value_0100111001 "HRMOR" + attribute \enum_value_0100111010 "HSRR0" + attribute \enum_value_0100111011 "HSRR1" + attribute \enum_value_0100111110 "LPCR" + attribute \enum_value_0100111111 "LPIDR" + attribute \enum_value_0101010000 "HMER" + attribute \enum_value_0101010001 "HMEER" + attribute \enum_value_0101010010 "PCR" + attribute \enum_value_0101010011 "HEIR" + attribute \enum_value_0101011101 "AMOR" + attribute \enum_value_0110111110 "TIR" + attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1011000000 "SVSTATE" + attribute \enum_value_1011010000 "SVSRR0" + attribute \enum_value_1100000000 "SIER" + attribute \enum_value_1100000001 "MMCR2" + attribute \enum_value_1100000010 "MMCRA" + attribute \enum_value_1100000011 "PMC1" + attribute \enum_value_1100000100 "PMC2" + attribute \enum_value_1100000101 "PMC3" + attribute \enum_value_1100000110 "PMC4" + attribute \enum_value_1100000111 "PMC5" + attribute \enum_value_1100001000 "PMC6" + attribute \enum_value_1100001011 "MMCR0" + attribute \enum_value_1100001100 "SIAR" + attribute \enum_value_1100001101 "SDAR" + attribute \enum_value_1100001110 "MMCR1" + attribute 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\A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \XL_XO [9] + connect \Y $not$libresoc.v:124167$4626_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + cell $pos $pos$libresoc.v:124164$4622 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 7 + connect \A $extend$libresoc.v:124164$4621_Y + connect \Y $pos$libresoc.v:124164$4622_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + cell $pos $pos$libresoc.v:124165$4624 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 7 + connect \A $extend$libresoc.v:124165$4623_Y + connect \Y $pos$libresoc.v:124165$4624_Y + end + attribute \src "libresoc.v:124038.7-124038.20" + process $proc$libresoc.v:124038$4631 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:124168.3-124182.6" + process $proc$libresoc.v:124168$4627 + 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\sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\reg_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'1101 + assign { } { } + assign $1\reg_b_ok[0:0] 1'1 + case + assign $1\reg_b_ok[0:0] 1'0 + end + sync always + update \reg_b_ok $0\reg_b_ok[0:0] + end + attribute \src "libresoc.v:124198.3-124215.6" + process $proc$libresoc.v:124198$4629 + assign { } { } + assign { } { } + assign $0\fast_b[2:0] $1\fast_b[2:0] + attribute \src "libresoc.v:124199.5-124199.29" + switch \initial + attribute \src "libresoc.v:124199.9-124199.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:347" + switch \$5 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fast_b[2:0] $2\fast_b[2:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:350" + switch { \XL_XO [5] \$7 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign 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"libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $2\fast_b_ok[0:0] 1'1 + case + assign $2\fast_b_ok[0:0] 1'0 + end + case + assign $1\fast_b_ok[0:0] 1'0 + end + sync always + update \fast_b_ok $0\fast_b_ok[0:0] + end + connect \$9 $eq$libresoc.v:124162$4619_Y + connect \$11 $not$libresoc.v:124163$4620_Y + connect \$1 $pos$libresoc.v:124164$4622_Y + connect \$3 $pos$libresoc.v:124165$4624_Y + connect \$5 $eq$libresoc.v:124166$4625_Y + connect \$7 $not$libresoc.v:124167$4626_Y +end +attribute \src "libresoc.v:124238.1-124491.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec_bi" +attribute \generator "nMigen" +module \dec_bi + attribute \src "libresoc.v:124465.3-124475.6" + wire width 16 $0\bd[15:0] + attribute \src "libresoc.v:124476.3-124486.6" + wire width 16 $0\ds[15:0] + attribute \src "libresoc.v:124327.3-124373.6" + wire width 64 $0\imm_b[63:0] + attribute \src "libresoc.v:124374.3-124420.6" + wire $0\imm_b_ok[0:0] + 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wire width 17 \$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:399" + wire width 17 \$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:404" + wire width 17 \$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:404" + wire width 17 \$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:390" + wire width 64 \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:390" + wire width 47 \$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:408" + wire width 64 \$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 64 \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 14 input 8 \ALU_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 14 input 9 \ALU_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 24 input 7 \ALU_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 input 5 \ALU_SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 16 input 3 \ALU_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 16 input 4 \ALU_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 6 input 6 \ALU_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:398" + wire width 16 \bd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:403" + wire width 16 \ds + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 1 \imm_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 2 \imm_b_ok + attribute \src "libresoc.v:124239.7-124239.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:393" + wire width 26 \li + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:365" + wire width 4 input 10 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:378" + wire width 16 \si + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:383" + wire width 32 \si_hi + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:388" + wire width 16 \ui + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + cell $pos $extend$libresoc.v:124317$4632 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 64 + connect \A \ALU_sh + connect \Y $extend$libresoc.v:124317$4632_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + cell $pos $extend$libresoc.v:124318$4634 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 64 + connect \A \ALU_SH32 + connect \Y $extend$libresoc.v:124318$4634_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + cell $pos $extend$libresoc.v:124321$4638 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \Y_WIDTH 64 + connect \A \ALU_UI + connect \Y $extend$libresoc.v:124321$4638_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:390" + cell $pos $extend$libresoc.v:124325$4643 + parameter \A_SIGNED 0 + parameter \A_WIDTH 47 + parameter \Y_WIDTH 64 + connect \A \$4 + connect \Y $extend$libresoc.v:124325$4643_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + cell $pos $pos$libresoc.v:124317$4633 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:124317$4632_Y + connect \Y $pos$libresoc.v:124317$4633_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + cell $pos $pos$libresoc.v:124318$4635 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:124318$4634_Y + connect \Y $pos$libresoc.v:124318$4635_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + cell $pos $pos$libresoc.v:124321$4639 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:124321$4638_Y + connect \Y $pos$libresoc.v:124321$4639_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:390" + cell $pos $pos$libresoc.v:124325$4644 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:124325$4643_Y + connect \Y $pos$libresoc.v:124325$4644_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:384" + cell $sshl $sshl$libresoc.v:124319$4636 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 47 + connect \A \ALU_SI + connect \B 5'10000 + connect \Y $sshl$libresoc.v:124319$4636_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:394" + cell $sshl $sshl$libresoc.v:124320$4637 + parameter \A_SIGNED 0 + parameter \A_WIDTH 24 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 27 + connect \A \ALU_LI + connect \B 2'10 + connect \Y $sshl$libresoc.v:124320$4637_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:399" + cell $sshl $sshl$libresoc.v:124322$4640 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 17 + connect \A \ALU_BD + connect \B 2'10 + connect \Y $sshl$libresoc.v:124322$4640_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:404" + cell $sshl $sshl$libresoc.v:124323$4641 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 17 + connect \A \ALU_DS + connect \B 2'10 + connect \Y $sshl$libresoc.v:124323$4641_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:390" + cell $sshl $sshl$libresoc.v:124324$4642 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 47 + connect \A \ui + connect \B 5'10000 + connect \Y $sshl$libresoc.v:124324$4642_Y + end + attribute \src "libresoc.v:124239.7-124239.20" + process $proc$libresoc.v:124239$4653 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:124327.3-124373.6" + process $proc$libresoc.v:124327$4645 + assign { } { } + assign { } { } + assign $0\imm_b[63:0] $1\imm_b[63:0] + attribute \src "libresoc.v:124328.5-124328.29" + switch \initial + attribute \src "libresoc.v:124328.9-124328.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\imm_b[63:0] \$1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\imm_b[63:0] { \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si } + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\imm_b[63:0] { \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi } + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\imm_b[63:0] \$3 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\imm_b[63:0] { \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li } + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\imm_b[63:0] { \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd } + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\imm_b[63:0] { \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds } + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\imm_b[63:0] \$7 + attribute \src "libresoc.v:0.0-0.0" + case 4'1010 + assign { } { } + assign $1\imm_b[63:0] \$9 + attribute \src "libresoc.v:0.0-0.0" + case 4'1011 + assign { } { } + assign $1\imm_b[63:0] \$11 + case + assign $1\imm_b[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \imm_b $0\imm_b[63:0] + end + attribute \src "libresoc.v:124374.3-124420.6" + process $proc$libresoc.v:124374$4646 + assign { } { } + assign { } { } + assign $0\imm_b_ok[0:0] $1\imm_b_ok[0:0] + attribute \src "libresoc.v:124375.5-124375.29" + switch \initial + attribute \src "libresoc.v:124375.9-124375.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'1010 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'1011 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + case + assign $1\imm_b_ok[0:0] 1'0 + end + sync always + update \imm_b_ok $0\imm_b_ok[0:0] + end + attribute \src "libresoc.v:124421.3-124431.6" + process $proc$libresoc.v:124421$4647 + assign { } { } + assign { } { } + assign $0\si[15:0] $1\si[15:0] + attribute \src "libresoc.v:124422.5-124422.29" + switch \initial + attribute \src "libresoc.v:124422.9-124422.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\si[15:0] \ALU_SI + case + assign $1\si[15:0] 16'0000000000000000 + end + sync always + update \si $0\si[15:0] + end + attribute \src "libresoc.v:124432.3-124442.6" + process $proc$libresoc.v:124432$4648 + assign { } { } + assign { } { } + assign $0\si_hi[31:0] $1\si_hi[31:0] + attribute \src "libresoc.v:124433.5-124433.29" + switch \initial + attribute \src "libresoc.v:124433.9-124433.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\si_hi[31:0] \$13 [31:0] + case + assign $1\si_hi[31:0] 0 + end + sync always + update \si_hi $0\si_hi[31:0] + end + attribute \src "libresoc.v:124443.3-124453.6" + process $proc$libresoc.v:124443$4649 + assign { } { } + assign { } { } + assign $0\ui[15:0] $1\ui[15:0] + attribute \src "libresoc.v:124444.5-124444.29" + switch \initial + attribute \src "libresoc.v:124444.9-124444.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\ui[15:0] \ALU_UI + case + assign $1\ui[15:0] 16'0000000000000000 + end + sync always + update \ui $0\ui[15:0] + end + attribute \src "libresoc.v:124454.3-124464.6" + process $proc$libresoc.v:124454$4650 + assign { } { } + assign { } { } + assign $0\li[25:0] $1\li[25:0] + attribute \src "libresoc.v:124455.5-124455.29" + switch \initial + attribute \src "libresoc.v:124455.9-124455.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\li[25:0] \$16 [25:0] + case + assign $1\li[25:0] 26'00000000000000000000000000 + end + sync always + update \li $0\li[25:0] + end + attribute \src "libresoc.v:124465.3-124475.6" + process $proc$libresoc.v:124465$4651 + assign { } { } + assign { } { } + assign $0\bd[15:0] $1\bd[15:0] + attribute \src "libresoc.v:124466.5-124466.29" + switch \initial + attribute \src "libresoc.v:124466.9-124466.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\bd[15:0] \$19 [15:0] + case + assign $1\bd[15:0] 16'0000000000000000 + end + sync always + update \bd $0\bd[15:0] + end + attribute \src "libresoc.v:124476.3-124486.6" + process $proc$libresoc.v:124476$4652 + assign { } { } + assign { } { } + assign $0\ds[15:0] $1\ds[15:0] + attribute \src "libresoc.v:124477.5-124477.29" + switch \initial + attribute \src "libresoc.v:124477.9-124477.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\ds[15:0] \$22 [15:0] + case + assign $1\ds[15:0] 16'0000000000000000 + end + sync always + update \ds $0\ds[15:0] + end + connect \$9 $pos$libresoc.v:124317$4633_Y + connect \$11 $pos$libresoc.v:124318$4635_Y + connect \$14 $sshl$libresoc.v:124319$4636_Y + connect \$17 $sshl$libresoc.v:124320$4637_Y + connect \$1 $pos$libresoc.v:124321$4639_Y + connect \$20 $sshl$libresoc.v:124322$4640_Y + connect \$23 $sshl$libresoc.v:124323$4641_Y + connect \$4 $sshl$libresoc.v:124324$4642_Y + connect \$3 $pos$libresoc.v:124325$4644_Y + connect \$7 64'1111111111111111111111111111111111111111111111111111111111111111 + connect \$13 \$14 + connect \$16 \$17 + connect \$19 \$20 + connect \$22 \$23 +end +attribute \src "libresoc.v:124495.1-124748.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_BRANCH.dec_bi" +attribute \generator "nMigen" +module \dec_bi$153 + attribute \src "libresoc.v:124722.3-124732.6" + wire width 16 $0\bd[15:0] + attribute \src "libresoc.v:124733.3-124743.6" + wire width 16 $0\ds[15:0] + attribute \src "libresoc.v:124584.3-124630.6" + wire width 64 $0\imm_b[63:0] + attribute \src "libresoc.v:124631.3-124677.6" + wire $0\imm_b_ok[0:0] + attribute \src "libresoc.v:124496.7-124496.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:124711.3-124721.6" + wire width 26 $0\li[25:0] + attribute \src "libresoc.v:124678.3-124688.6" + wire width 16 $0\si[15:0] + attribute \src "libresoc.v:124689.3-124699.6" + wire width 32 $0\si_hi[31:0] + attribute \src "libresoc.v:124700.3-124710.6" + wire width 16 $0\ui[15:0] + attribute \src "libresoc.v:124722.3-124732.6" + wire width 16 $1\bd[15:0] + attribute \src "libresoc.v:124733.3-124743.6" + wire width 16 $1\ds[15:0] + attribute \src "libresoc.v:124584.3-124630.6" + wire width 64 $1\imm_b[63:0] + attribute \src "libresoc.v:124631.3-124677.6" + wire $1\imm_b_ok[0:0] + attribute \src "libresoc.v:124711.3-124721.6" + wire width 26 $1\li[25:0] + attribute \src "libresoc.v:124678.3-124688.6" + wire width 16 $1\si[15:0] + attribute \src "libresoc.v:124689.3-124699.6" + wire width 32 $1\si_hi[31:0] + attribute \src "libresoc.v:124700.3-124710.6" + wire width 16 $1\ui[15:0] + attribute \src "libresoc.v:124574.17-124574.107" + wire width 64 $extend$libresoc.v:124574$4654_Y + attribute \src "libresoc.v:124575.18-124575.110" + wire width 64 $extend$libresoc.v:124575$4656_Y + attribute \src "libresoc.v:124578.17-124578.107" + wire width 64 $extend$libresoc.v:124578$4660_Y + attribute \src "libresoc.v:124582.17-124582.102" + wire width 64 $extend$libresoc.v:124582$4665_Y + attribute \src "libresoc.v:124574.17-124574.107" + wire width 64 $pos$libresoc.v:124574$4655_Y + attribute \src "libresoc.v:124575.18-124575.110" + wire width 64 $pos$libresoc.v:124575$4657_Y + attribute \src "libresoc.v:124578.17-124578.107" + wire width 64 $pos$libresoc.v:124578$4661_Y + attribute \src "libresoc.v:124582.17-124582.102" + wire width 64 $pos$libresoc.v:124582$4666_Y + attribute \src "libresoc.v:124576.18-124576.117" + wire width 47 $sshl$libresoc.v:124576$4658_Y + attribute \src "libresoc.v:124577.18-124577.116" + wire width 27 $sshl$libresoc.v:124577$4659_Y + attribute \src "libresoc.v:124579.18-124579.116" + wire width 17 $sshl$libresoc.v:124579$4662_Y + attribute \src "libresoc.v:124580.18-124580.116" + wire width 17 $sshl$libresoc.v:124580$4663_Y + attribute \src "libresoc.v:124581.17-124581.109" + wire width 47 $sshl$libresoc.v:124581$4664_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 64 \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 64 \$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:384" + wire width 47 \$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:384" + wire width 47 \$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:394" + wire width 27 \$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:394" + wire width 27 \$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:399" + wire width 17 \$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:399" + wire width 17 \$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:404" + wire width 17 \$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:404" + wire width 17 \$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:390" + wire width 64 \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:390" + wire width 47 \$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:408" + wire width 64 \$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 64 \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 14 input 8 \BRANCH_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 14 input 9 \BRANCH_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 24 input 7 \BRANCH_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 input 5 \BRANCH_SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 16 input 3 \BRANCH_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 16 input 4 \BRANCH_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 6 input 6 \BRANCH_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:398" + wire width 16 \bd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:403" + wire width 16 \ds + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 1 \imm_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 2 \imm_b_ok + attribute \src "libresoc.v:124496.7-124496.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:393" + wire width 26 \li + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:365" + wire width 4 input 10 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:378" + wire width 16 \si + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:383" + wire width 32 \si_hi + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:388" + wire width 16 \ui + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + cell $pos $extend$libresoc.v:124574$4654 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 64 + connect \A \BRANCH_sh + connect \Y $extend$libresoc.v:124574$4654_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + cell $pos $extend$libresoc.v:124575$4656 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 64 + connect \A \BRANCH_SH32 + connect \Y $extend$libresoc.v:124575$4656_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + cell $pos $extend$libresoc.v:124578$4660 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \Y_WIDTH 64 + connect \A \BRANCH_UI + connect \Y $extend$libresoc.v:124578$4660_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:390" + cell $pos $extend$libresoc.v:124582$4665 + parameter \A_SIGNED 0 + parameter \A_WIDTH 47 + parameter \Y_WIDTH 64 + connect \A \$4 + connect \Y $extend$libresoc.v:124582$4665_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + cell $pos $pos$libresoc.v:124574$4655 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:124574$4654_Y + connect \Y $pos$libresoc.v:124574$4655_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + cell $pos $pos$libresoc.v:124575$4657 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:124575$4656_Y + connect \Y $pos$libresoc.v:124575$4657_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + cell $pos $pos$libresoc.v:124578$4661 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:124578$4660_Y + connect \Y $pos$libresoc.v:124578$4661_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:390" + cell $pos $pos$libresoc.v:124582$4666 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:124582$4665_Y + connect \Y $pos$libresoc.v:124582$4666_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:384" + cell $sshl $sshl$libresoc.v:124576$4658 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 47 + connect \A \BRANCH_SI + connect \B 5'10000 + connect \Y $sshl$libresoc.v:124576$4658_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:394" + cell $sshl $sshl$libresoc.v:124577$4659 + parameter \A_SIGNED 0 + parameter \A_WIDTH 24 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 27 + connect \A \BRANCH_LI + connect \B 2'10 + connect \Y $sshl$libresoc.v:124577$4659_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:399" + cell $sshl $sshl$libresoc.v:124579$4662 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 17 + connect \A \BRANCH_BD + connect \B 2'10 + connect \Y $sshl$libresoc.v:124579$4662_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:404" + cell $sshl $sshl$libresoc.v:124580$4663 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 17 + connect \A \BRANCH_DS + connect \B 2'10 + connect \Y $sshl$libresoc.v:124580$4663_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:390" + cell $sshl $sshl$libresoc.v:124581$4664 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 47 + connect \A \ui + connect \B 5'10000 + connect \Y $sshl$libresoc.v:124581$4664_Y + end + attribute \src "libresoc.v:124496.7-124496.20" + process $proc$libresoc.v:124496$4675 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:124584.3-124630.6" + process $proc$libresoc.v:124584$4667 + assign { } { } + assign { } { } + assign $0\imm_b[63:0] $1\imm_b[63:0] + attribute \src "libresoc.v:124585.5-124585.29" + switch \initial + attribute \src "libresoc.v:124585.9-124585.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\imm_b[63:0] \$1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\imm_b[63:0] { \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si } + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\imm_b[63:0] { \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi } + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\imm_b[63:0] \$3 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\imm_b[63:0] { \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li } + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\imm_b[63:0] { \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd } + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\imm_b[63:0] { \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds } + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\imm_b[63:0] \$7 + attribute \src "libresoc.v:0.0-0.0" + case 4'1010 + assign { } { } + assign $1\imm_b[63:0] \$9 + attribute \src "libresoc.v:0.0-0.0" + case 4'1011 + assign { } { } + assign $1\imm_b[63:0] \$11 + case + assign $1\imm_b[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \imm_b $0\imm_b[63:0] + end + attribute \src "libresoc.v:124631.3-124677.6" + process $proc$libresoc.v:124631$4668 + assign { } { } + assign { } { } + assign $0\imm_b_ok[0:0] $1\imm_b_ok[0:0] + attribute \src "libresoc.v:124632.5-124632.29" + switch \initial + attribute \src "libresoc.v:124632.9-124632.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'1010 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'1011 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + case + assign $1\imm_b_ok[0:0] 1'0 + end + sync always + update \imm_b_ok $0\imm_b_ok[0:0] + end + attribute \src "libresoc.v:124678.3-124688.6" + process $proc$libresoc.v:124678$4669 + assign { } { } + assign { } { } + assign $0\si[15:0] $1\si[15:0] + attribute \src "libresoc.v:124679.5-124679.29" + switch \initial + attribute \src "libresoc.v:124679.9-124679.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\si[15:0] \BRANCH_SI + case + assign $1\si[15:0] 16'0000000000000000 + end + sync always + update \si $0\si[15:0] + end + attribute \src "libresoc.v:124689.3-124699.6" + process $proc$libresoc.v:124689$4670 + assign { } { } + assign { } { } + assign $0\si_hi[31:0] $1\si_hi[31:0] + attribute \src "libresoc.v:124690.5-124690.29" + switch \initial + attribute \src "libresoc.v:124690.9-124690.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\si_hi[31:0] \$13 [31:0] + case + assign $1\si_hi[31:0] 0 + end + sync always + update \si_hi $0\si_hi[31:0] + end + attribute \src "libresoc.v:124700.3-124710.6" + process $proc$libresoc.v:124700$4671 + assign { } { } + assign { } { } + assign $0\ui[15:0] $1\ui[15:0] + attribute \src "libresoc.v:124701.5-124701.29" + switch \initial + attribute \src "libresoc.v:124701.9-124701.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\ui[15:0] \BRANCH_UI + case + assign $1\ui[15:0] 16'0000000000000000 + end + sync always + update \ui $0\ui[15:0] + end + attribute \src "libresoc.v:124711.3-124721.6" + process $proc$libresoc.v:124711$4672 + assign { } { } + assign { } { } + assign $0\li[25:0] $1\li[25:0] + attribute \src "libresoc.v:124712.5-124712.29" + switch \initial + attribute \src "libresoc.v:124712.9-124712.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\li[25:0] \$16 [25:0] + case + assign $1\li[25:0] 26'00000000000000000000000000 + end + sync always + update \li $0\li[25:0] + end + attribute \src "libresoc.v:124722.3-124732.6" + process $proc$libresoc.v:124722$4673 + assign { } { } + assign { } { } + assign $0\bd[15:0] $1\bd[15:0] + attribute \src "libresoc.v:124723.5-124723.29" + switch \initial + attribute \src "libresoc.v:124723.9-124723.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\bd[15:0] \$19 [15:0] + case + assign $1\bd[15:0] 16'0000000000000000 + end + sync always + update \bd $0\bd[15:0] + end + attribute \src "libresoc.v:124733.3-124743.6" + process $proc$libresoc.v:124733$4674 + assign { } { } + assign { } { } + assign $0\ds[15:0] $1\ds[15:0] + attribute \src "libresoc.v:124734.5-124734.29" + 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:384" + wire width 47 \$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:384" + wire width 47 \$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:394" + wire width 27 \$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:394" + wire width 27 \$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:399" + wire width 17 \$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:399" + wire width 17 \$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:404" + wire width 17 \$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:404" + wire width 17 \$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:390" + wire width 64 \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:390" + wire width 47 \$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:408" + wire width 64 \$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 64 \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 14 input 8 \LOGICAL_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 14 input 9 \LOGICAL_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 24 input 7 \LOGICAL_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 input 5 \LOGICAL_SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 16 input 3 \LOGICAL_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 16 input 4 \LOGICAL_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 6 input 6 \LOGICAL_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:398" + wire width 16 \bd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:403" + wire width 16 \ds + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 1 \imm_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 2 \imm_b_ok + attribute \src "libresoc.v:124753.7-124753.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:393" + wire width 26 \li + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:365" + wire width 4 input 10 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:378" + wire width 16 \si + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:383" + wire width 32 \si_hi + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:388" + wire width 16 \ui + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + cell $pos $extend$libresoc.v:124831$4676 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 64 + connect \A \LOGICAL_sh + connect \Y $extend$libresoc.v:124831$4676_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + cell $pos $extend$libresoc.v:124832$4678 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 64 + connect \A \LOGICAL_SH32 + connect \Y $extend$libresoc.v:124832$4678_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + cell $pos $extend$libresoc.v:124835$4682 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \Y_WIDTH 64 + connect \A \LOGICAL_UI + connect \Y $extend$libresoc.v:124835$4682_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:390" + cell $pos $extend$libresoc.v:124839$4687 + parameter \A_SIGNED 0 + parameter \A_WIDTH 47 + parameter \Y_WIDTH 64 + connect \A \$4 + connect \Y $extend$libresoc.v:124839$4687_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + cell $pos $pos$libresoc.v:124831$4677 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:124831$4676_Y + connect \Y $pos$libresoc.v:124831$4677_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + cell $pos $pos$libresoc.v:124832$4679 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:124832$4678_Y + connect \Y $pos$libresoc.v:124832$4679_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + cell $pos $pos$libresoc.v:124835$4683 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:124835$4682_Y + connect \Y $pos$libresoc.v:124835$4683_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:390" + cell $pos $pos$libresoc.v:124839$4688 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:124839$4687_Y + connect \Y $pos$libresoc.v:124839$4688_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:384" + cell $sshl $sshl$libresoc.v:124833$4680 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 47 + connect \A \LOGICAL_SI + connect \B 5'10000 + connect \Y $sshl$libresoc.v:124833$4680_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:394" + cell $sshl $sshl$libresoc.v:124834$4681 + parameter \A_SIGNED 0 + parameter \A_WIDTH 24 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 27 + connect \A \LOGICAL_LI + connect \B 2'10 + connect \Y $sshl$libresoc.v:124834$4681_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:399" + cell $sshl $sshl$libresoc.v:124836$4684 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 17 + connect \A \LOGICAL_BD + connect \B 2'10 + connect \Y $sshl$libresoc.v:124836$4684_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:404" + cell $sshl $sshl$libresoc.v:124837$4685 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 17 + connect \A \LOGICAL_DS + connect \B 2'10 + connect \Y $sshl$libresoc.v:124837$4685_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:390" + cell $sshl $sshl$libresoc.v:124838$4686 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 47 + connect \A \ui + connect \B 5'10000 + connect \Y $sshl$libresoc.v:124838$4686_Y + end + attribute \src "libresoc.v:124753.7-124753.20" + process $proc$libresoc.v:124753$4697 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:124841.3-124887.6" + process $proc$libresoc.v:124841$4689 + assign { } { } + assign { } { } + assign $0\imm_b[63:0] $1\imm_b[63:0] + attribute \src "libresoc.v:124842.5-124842.29" + switch \initial + attribute \src "libresoc.v:124842.9-124842.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\imm_b[63:0] \$1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\imm_b[63:0] { \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si } + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\imm_b[63:0] { \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi } + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\imm_b[63:0] \$3 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\imm_b[63:0] { \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li } + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\imm_b[63:0] { \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd } + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\imm_b[63:0] { \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds } + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\imm_b[63:0] \$7 + attribute \src "libresoc.v:0.0-0.0" + case 4'1010 + assign { } { } + assign $1\imm_b[63:0] \$9 + attribute \src "libresoc.v:0.0-0.0" + case 4'1011 + assign { } { } + assign $1\imm_b[63:0] \$11 + case + assign $1\imm_b[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \imm_b $0\imm_b[63:0] + end + attribute \src "libresoc.v:124888.3-124934.6" + process $proc$libresoc.v:124888$4690 + assign { } { } + assign { } { } + assign $0\imm_b_ok[0:0] $1\imm_b_ok[0:0] + attribute \src "libresoc.v:124889.5-124889.29" + switch \initial + attribute \src "libresoc.v:124889.9-124889.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'1010 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'1011 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + case + assign $1\imm_b_ok[0:0] 1'0 + end + sync always + update \imm_b_ok $0\imm_b_ok[0:0] + end + attribute \src "libresoc.v:124935.3-124945.6" + process $proc$libresoc.v:124935$4691 + assign { } { } + assign { } { } + assign $0\si[15:0] $1\si[15:0] + attribute \src "libresoc.v:124936.5-124936.29" + switch \initial + attribute \src "libresoc.v:124936.9-124936.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\si[15:0] \LOGICAL_SI + case + assign $1\si[15:0] 16'0000000000000000 + end + sync always + update \si $0\si[15:0] + end + attribute \src "libresoc.v:124946.3-124956.6" + process $proc$libresoc.v:124946$4692 + assign { } { } + assign { } { } + assign $0\si_hi[31:0] $1\si_hi[31:0] + attribute \src "libresoc.v:124947.5-124947.29" + switch \initial + attribute \src "libresoc.v:124947.9-124947.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\si_hi[31:0] \$13 [31:0] + case + assign $1\si_hi[31:0] 0 + end + sync always + update \si_hi $0\si_hi[31:0] + end + attribute \src "libresoc.v:124957.3-124967.6" + process $proc$libresoc.v:124957$4693 + assign { } { } + assign { } { } + assign $0\ui[15:0] $1\ui[15:0] + attribute \src "libresoc.v:124958.5-124958.29" + switch \initial + attribute \src "libresoc.v:124958.9-124958.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\ui[15:0] \LOGICAL_UI + case + assign $1\ui[15:0] 16'0000000000000000 + end + sync always + update \ui $0\ui[15:0] + end + attribute \src "libresoc.v:124968.3-124978.6" + process $proc$libresoc.v:124968$4694 + assign { } { } + assign { } { } + assign $0\li[25:0] $1\li[25:0] + attribute \src "libresoc.v:124969.5-124969.29" + switch \initial + attribute \src "libresoc.v:124969.9-124969.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\li[25:0] \$16 [25:0] + case + assign $1\li[25:0] 26'00000000000000000000000000 + end + sync always + update \li $0\li[25:0] + end + attribute \src "libresoc.v:124979.3-124989.6" + process $proc$libresoc.v:124979$4695 + assign { } { } + assign { } { } + assign $0\bd[15:0] $1\bd[15:0] + attribute \src "libresoc.v:124980.5-124980.29" + switch \initial + attribute \src "libresoc.v:124980.9-124980.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\bd[15:0] \$19 [15:0] + case + assign $1\bd[15:0] 16'0000000000000000 + end + sync always + update \bd $0\bd[15:0] + end + attribute \src "libresoc.v:124990.3-125000.6" + process $proc$libresoc.v:124990$4696 + assign { } { } + assign { } { } + assign $0\ds[15:0] $1\ds[15:0] + attribute \src "libresoc.v:124991.5-124991.29" + switch \initial + attribute \src "libresoc.v:124991.9-124991.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\ds[15:0] \$22 [15:0] + case + assign $1\ds[15:0] 16'0000000000000000 + end + sync always + update \ds $0\ds[15:0] + end + connect \$9 $pos$libresoc.v:124831$4677_Y + connect \$11 $pos$libresoc.v:124832$4679_Y + connect \$14 $sshl$libresoc.v:124833$4680_Y + connect \$17 $sshl$libresoc.v:124834$4681_Y + connect \$1 $pos$libresoc.v:124835$4683_Y + connect \$20 $sshl$libresoc.v:124836$4684_Y + connect \$23 $sshl$libresoc.v:124837$4685_Y + connect \$4 $sshl$libresoc.v:124838$4686_Y + connect \$3 $pos$libresoc.v:124839$4688_Y + connect \$7 64'1111111111111111111111111111111111111111111111111111111111111111 + connect \$13 \$14 + connect \$16 \$17 + connect \$19 \$20 + connect \$22 \$23 +end +attribute \src "libresoc.v:125009.1-125262.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_DIV.dec_bi" +attribute \generator "nMigen" +module \dec_bi$178 + attribute \src "libresoc.v:125236.3-125246.6" + wire width 16 $0\bd[15:0] + attribute \src "libresoc.v:125247.3-125257.6" + wire width 16 $0\ds[15:0] + attribute \src "libresoc.v:125098.3-125144.6" + wire width 64 $0\imm_b[63:0] + attribute \src "libresoc.v:125145.3-125191.6" + wire $0\imm_b_ok[0:0] + attribute \src "libresoc.v:125010.7-125010.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:125225.3-125235.6" + wire width 26 $0\li[25:0] + attribute \src "libresoc.v:125192.3-125202.6" + wire width 16 $0\si[15:0] + attribute \src "libresoc.v:125203.3-125213.6" + wire width 32 $0\si_hi[31:0] + attribute \src "libresoc.v:125214.3-125224.6" + wire width 16 $0\ui[15:0] + attribute \src "libresoc.v:125236.3-125246.6" + wire width 16 $1\bd[15:0] + attribute \src "libresoc.v:125247.3-125257.6" + wire width 16 $1\ds[15:0] + attribute \src "libresoc.v:125098.3-125144.6" + wire width 64 $1\imm_b[63:0] + attribute \src "libresoc.v:125145.3-125191.6" + wire $1\imm_b_ok[0:0] + attribute \src "libresoc.v:125225.3-125235.6" + wire width 26 $1\li[25:0] + attribute \src "libresoc.v:125192.3-125202.6" + wire width 16 $1\si[15:0] + attribute \src "libresoc.v:125203.3-125213.6" + wire width 32 $1\si_hi[31:0] + attribute \src "libresoc.v:125214.3-125224.6" + wire width 16 $1\ui[15:0] + attribute \src "libresoc.v:125088.17-125088.104" + wire width 64 $extend$libresoc.v:125088$4698_Y + attribute \src "libresoc.v:125089.18-125089.107" + wire width 64 $extend$libresoc.v:125089$4700_Y + attribute \src "libresoc.v:125092.17-125092.104" + wire width 64 $extend$libresoc.v:125092$4704_Y + attribute \src "libresoc.v:125096.17-125096.102" + wire width 64 $extend$libresoc.v:125096$4709_Y + attribute \src "libresoc.v:125088.17-125088.104" + wire width 64 $pos$libresoc.v:125088$4699_Y + attribute \src "libresoc.v:125089.18-125089.107" + wire width 64 $pos$libresoc.v:125089$4701_Y + attribute \src "libresoc.v:125092.17-125092.104" + wire width 64 $pos$libresoc.v:125092$4705_Y + attribute \src "libresoc.v:125096.17-125096.102" + wire width 64 $pos$libresoc.v:125096$4710_Y + attribute \src "libresoc.v:125090.18-125090.114" + wire width 47 $sshl$libresoc.v:125090$4702_Y + attribute \src "libresoc.v:125091.18-125091.113" + wire width 27 $sshl$libresoc.v:125091$4703_Y + attribute \src "libresoc.v:125093.18-125093.113" + wire width 17 $sshl$libresoc.v:125093$4706_Y + attribute \src "libresoc.v:125094.18-125094.113" + wire width 17 $sshl$libresoc.v:125094$4707_Y + attribute \src "libresoc.v:125095.17-125095.109" + wire width 47 $sshl$libresoc.v:125095$4708_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 64 \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 64 \$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:384" + wire width 47 \$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:384" + wire width 47 \$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:394" + wire width 27 \$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:394" + wire width 27 \$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:399" + wire width 17 \$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:399" + wire width 17 \$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:404" + wire width 17 \$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:404" + wire width 17 \$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:390" + wire width 64 \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:390" + wire width 47 \$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:408" + wire width 64 \$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 64 \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 14 input 8 \DIV_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 14 input 9 \DIV_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 24 input 7 \DIV_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 input 5 \DIV_SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 16 input 3 \DIV_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 16 input 4 \DIV_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 6 input 6 \DIV_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:398" + wire width 16 \bd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:403" + wire width 16 \ds + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 1 \imm_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 2 \imm_b_ok + attribute \src "libresoc.v:125010.7-125010.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:393" + wire width 26 \li + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:365" + wire width 4 input 10 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:378" + wire width 16 \si + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:383" + wire width 32 \si_hi + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:388" + wire width 16 \ui + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + cell $pos $extend$libresoc.v:125088$4698 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 64 + connect \A \DIV_sh + connect \Y $extend$libresoc.v:125088$4698_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + cell $pos $extend$libresoc.v:125089$4700 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 64 + connect \A \DIV_SH32 + connect \Y $extend$libresoc.v:125089$4700_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + cell $pos $extend$libresoc.v:125092$4704 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \Y_WIDTH 64 + connect \A \DIV_UI + connect \Y $extend$libresoc.v:125092$4704_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:390" + cell $pos $extend$libresoc.v:125096$4709 + parameter \A_SIGNED 0 + parameter \A_WIDTH 47 + parameter \Y_WIDTH 64 + connect \A \$4 + connect \Y $extend$libresoc.v:125096$4709_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + cell $pos $pos$libresoc.v:125088$4699 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:125088$4698_Y + connect \Y $pos$libresoc.v:125088$4699_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + cell $pos $pos$libresoc.v:125089$4701 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:125089$4700_Y + connect \Y $pos$libresoc.v:125089$4701_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + cell $pos $pos$libresoc.v:125092$4705 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:125092$4704_Y + connect \Y $pos$libresoc.v:125092$4705_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:390" + cell $pos $pos$libresoc.v:125096$4710 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:125096$4709_Y + connect \Y $pos$libresoc.v:125096$4710_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:384" + cell $sshl $sshl$libresoc.v:125090$4702 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 47 + connect \A \DIV_SI + connect \B 5'10000 + connect \Y $sshl$libresoc.v:125090$4702_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:394" + cell $sshl $sshl$libresoc.v:125091$4703 + parameter \A_SIGNED 0 + parameter \A_WIDTH 24 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 27 + connect \A \DIV_LI + connect \B 2'10 + connect \Y $sshl$libresoc.v:125091$4703_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:399" + cell $sshl $sshl$libresoc.v:125093$4706 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 17 + connect \A \DIV_BD + connect \B 2'10 + connect \Y $sshl$libresoc.v:125093$4706_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:404" + cell $sshl $sshl$libresoc.v:125094$4707 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 17 + connect \A \DIV_DS + connect \B 2'10 + connect \Y $sshl$libresoc.v:125094$4707_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:390" + cell $sshl $sshl$libresoc.v:125095$4708 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 47 + connect \A \ui + connect \B 5'10000 + connect \Y $sshl$libresoc.v:125095$4708_Y + end + attribute \src "libresoc.v:125010.7-125010.20" + process $proc$libresoc.v:125010$4719 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:125098.3-125144.6" + process $proc$libresoc.v:125098$4711 + assign { } { } + assign { } { } + assign $0\imm_b[63:0] $1\imm_b[63:0] + attribute \src "libresoc.v:125099.5-125099.29" + switch \initial + attribute \src "libresoc.v:125099.9-125099.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\imm_b[63:0] \$1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\imm_b[63:0] { \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si } + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\imm_b[63:0] { \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi } + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\imm_b[63:0] \$3 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\imm_b[63:0] { \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li } + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\imm_b[63:0] { \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd } + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\imm_b[63:0] { \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds } + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\imm_b[63:0] \$7 + attribute \src "libresoc.v:0.0-0.0" + case 4'1010 + assign { } { } + assign $1\imm_b[63:0] \$9 + attribute \src "libresoc.v:0.0-0.0" + case 4'1011 + assign { } { } + assign $1\imm_b[63:0] \$11 + case + assign $1\imm_b[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \imm_b $0\imm_b[63:0] + end + attribute \src "libresoc.v:125145.3-125191.6" + process $proc$libresoc.v:125145$4712 + assign { } { } + assign { } { } + assign $0\imm_b_ok[0:0] $1\imm_b_ok[0:0] + attribute \src "libresoc.v:125146.5-125146.29" + switch \initial + attribute \src "libresoc.v:125146.9-125146.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'1010 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'1011 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + case + assign $1\imm_b_ok[0:0] 1'0 + end + sync always + update \imm_b_ok $0\imm_b_ok[0:0] + end + attribute \src "libresoc.v:125192.3-125202.6" + process $proc$libresoc.v:125192$4713 + assign { } { } + assign { } { } + assign $0\si[15:0] $1\si[15:0] + attribute \src "libresoc.v:125193.5-125193.29" + switch \initial + attribute \src "libresoc.v:125193.9-125193.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\si[15:0] \DIV_SI + case + assign $1\si[15:0] 16'0000000000000000 + end + sync always + update \si $0\si[15:0] + end + attribute \src "libresoc.v:125203.3-125213.6" + process $proc$libresoc.v:125203$4714 + assign { } { } + assign { } { } + assign $0\si_hi[31:0] $1\si_hi[31:0] + attribute \src "libresoc.v:125204.5-125204.29" + switch \initial + attribute \src "libresoc.v:125204.9-125204.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\si_hi[31:0] \$13 [31:0] + case + assign $1\si_hi[31:0] 0 + end + sync always + update \si_hi $0\si_hi[31:0] + end + attribute \src "libresoc.v:125214.3-125224.6" + process $proc$libresoc.v:125214$4715 + assign { } { } + assign { } { } + assign $0\ui[15:0] $1\ui[15:0] + attribute \src "libresoc.v:125215.5-125215.29" + switch \initial + attribute \src "libresoc.v:125215.9-125215.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\ui[15:0] \DIV_UI + case + assign $1\ui[15:0] 16'0000000000000000 + end + sync always + update \ui $0\ui[15:0] + end + attribute \src "libresoc.v:125225.3-125235.6" + process $proc$libresoc.v:125225$4716 + assign { } { } + assign { } { } + assign $0\li[25:0] $1\li[25:0] + attribute \src "libresoc.v:125226.5-125226.29" + switch \initial + attribute \src "libresoc.v:125226.9-125226.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\li[25:0] \$16 [25:0] + case + assign $1\li[25:0] 26'00000000000000000000000000 + end + sync always + update \li $0\li[25:0] + end + attribute \src "libresoc.v:125236.3-125246.6" + process $proc$libresoc.v:125236$4717 + assign { } { } + assign { } { } + assign $0\bd[15:0] $1\bd[15:0] + attribute \src "libresoc.v:125237.5-125237.29" + switch \initial + attribute \src "libresoc.v:125237.9-125237.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\bd[15:0] \$19 [15:0] + case + assign $1\bd[15:0] 16'0000000000000000 + end + sync always + update \bd $0\bd[15:0] + end + attribute \src "libresoc.v:125247.3-125257.6" + process $proc$libresoc.v:125247$4718 + assign { } { } + assign { } { } + assign $0\ds[15:0] $1\ds[15:0] + attribute \src "libresoc.v:125248.5-125248.29" + switch \initial + attribute \src "libresoc.v:125248.9-125248.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\ds[15:0] \$22 [15:0] + case + assign $1\ds[15:0] 16'0000000000000000 + end + sync always + update \ds $0\ds[15:0] + end + connect \$9 $pos$libresoc.v:125088$4699_Y + connect \$11 $pos$libresoc.v:125089$4701_Y + connect \$14 $sshl$libresoc.v:125090$4702_Y + connect \$17 $sshl$libresoc.v:125091$4703_Y + connect \$1 $pos$libresoc.v:125092$4705_Y + connect \$20 $sshl$libresoc.v:125093$4706_Y + connect \$23 $sshl$libresoc.v:125094$4707_Y + connect \$4 $sshl$libresoc.v:125095$4708_Y + connect \$3 $pos$libresoc.v:125096$4710_Y + connect \$7 64'1111111111111111111111111111111111111111111111111111111111111111 + connect \$13 \$14 + connect \$16 \$17 + connect \$19 \$20 + connect \$22 \$23 +end +attribute \src "libresoc.v:125266.1-125519.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_MUL.dec_bi" +attribute \generator "nMigen" +module \dec_bi$186 + attribute \src "libresoc.v:125493.3-125503.6" + wire width 16 $0\bd[15:0] + attribute \src "libresoc.v:125504.3-125514.6" + wire width 16 $0\ds[15:0] + attribute \src "libresoc.v:125355.3-125401.6" + wire width 64 $0\imm_b[63:0] + attribute \src "libresoc.v:125402.3-125448.6" + wire $0\imm_b_ok[0:0] + attribute \src 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"libresoc.v:125345.17-125345.104" + wire width 64 $extend$libresoc.v:125345$4720_Y + attribute \src "libresoc.v:125346.18-125346.107" + wire width 64 $extend$libresoc.v:125346$4722_Y + attribute \src "libresoc.v:125349.17-125349.104" + wire width 64 $extend$libresoc.v:125349$4726_Y + attribute \src "libresoc.v:125353.17-125353.102" + wire width 64 $extend$libresoc.v:125353$4731_Y + attribute \src "libresoc.v:125345.17-125345.104" + wire width 64 $pos$libresoc.v:125345$4721_Y + attribute \src "libresoc.v:125346.18-125346.107" + wire width 64 $pos$libresoc.v:125346$4723_Y + attribute \src "libresoc.v:125349.17-125349.104" + wire width 64 $pos$libresoc.v:125349$4727_Y + attribute \src "libresoc.v:125353.17-125353.102" + wire width 64 $pos$libresoc.v:125353$4732_Y + attribute \src "libresoc.v:125347.18-125347.114" + wire width 47 $sshl$libresoc.v:125347$4724_Y + attribute \src "libresoc.v:125348.18-125348.113" + wire width 27 $sshl$libresoc.v:125348$4725_Y + attribute \src "libresoc.v:125350.18-125350.113" + wire width 17 $sshl$libresoc.v:125350$4728_Y + attribute \src "libresoc.v:125351.18-125351.113" + wire width 17 $sshl$libresoc.v:125351$4729_Y + attribute \src "libresoc.v:125352.17-125352.109" + wire width 47 $sshl$libresoc.v:125352$4730_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 64 \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 64 \$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:384" + wire width 47 \$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:384" + wire width 47 \$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:394" + wire width 27 \$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:394" + wire width 27 \$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:399" + wire width 17 \$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:399" + wire width 17 \$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:404" + wire width 17 \$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:404" + wire width 17 \$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:390" + wire width 64 \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:390" + wire width 47 \$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:408" + wire width 64 \$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 64 \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 14 input 8 \MUL_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 14 input 9 \MUL_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 24 input 7 \MUL_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 input 5 \MUL_SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 16 input 3 \MUL_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 16 input 4 \MUL_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 6 input 6 \MUL_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:398" + wire width 16 \bd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:403" + wire width 16 \ds + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 1 \imm_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 2 \imm_b_ok + attribute \src "libresoc.v:125267.7-125267.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:393" + wire width 26 \li + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:365" + wire width 4 input 10 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:378" + wire width 16 \si + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:383" + wire width 32 \si_hi + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:388" + wire width 16 \ui + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + cell $pos $extend$libresoc.v:125345$4720 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 64 + connect \A \MUL_sh + connect \Y $extend$libresoc.v:125345$4720_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + cell $pos $extend$libresoc.v:125346$4722 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 64 + connect \A \MUL_SH32 + connect \Y $extend$libresoc.v:125346$4722_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + cell $pos $extend$libresoc.v:125349$4726 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \Y_WIDTH 64 + connect \A \MUL_UI + connect \Y $extend$libresoc.v:125349$4726_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:390" + cell $pos $extend$libresoc.v:125353$4731 + parameter \A_SIGNED 0 + parameter \A_WIDTH 47 + parameter \Y_WIDTH 64 + connect \A \$4 + connect \Y $extend$libresoc.v:125353$4731_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + cell $pos $pos$libresoc.v:125345$4721 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:125345$4720_Y + connect \Y $pos$libresoc.v:125345$4721_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + cell $pos $pos$libresoc.v:125346$4723 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:125346$4722_Y + connect \Y $pos$libresoc.v:125346$4723_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + cell $pos $pos$libresoc.v:125349$4727 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:125349$4726_Y + connect \Y $pos$libresoc.v:125349$4727_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:390" + cell $pos $pos$libresoc.v:125353$4732 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:125353$4731_Y + connect \Y $pos$libresoc.v:125353$4732_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:384" + cell $sshl $sshl$libresoc.v:125347$4724 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 47 + connect \A \MUL_SI + connect \B 5'10000 + connect \Y $sshl$libresoc.v:125347$4724_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:394" + cell $sshl $sshl$libresoc.v:125348$4725 + parameter \A_SIGNED 0 + parameter \A_WIDTH 24 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 27 + connect \A \MUL_LI + connect \B 2'10 + connect \Y $sshl$libresoc.v:125348$4725_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:399" + cell $sshl $sshl$libresoc.v:125350$4728 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 17 + connect \A \MUL_BD + connect \B 2'10 + connect \Y $sshl$libresoc.v:125350$4728_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:404" + cell $sshl $sshl$libresoc.v:125351$4729 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 17 + connect \A \MUL_DS + connect \B 2'10 + connect \Y $sshl$libresoc.v:125351$4729_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:390" + cell $sshl $sshl$libresoc.v:125352$4730 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 47 + connect \A \ui + connect \B 5'10000 + connect \Y $sshl$libresoc.v:125352$4730_Y + end + attribute \src "libresoc.v:125267.7-125267.20" + process $proc$libresoc.v:125267$4741 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:125355.3-125401.6" + process $proc$libresoc.v:125355$4733 + assign { } { } + assign { } { } + assign $0\imm_b[63:0] $1\imm_b[63:0] + attribute \src "libresoc.v:125356.5-125356.29" + switch \initial + attribute \src "libresoc.v:125356.9-125356.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\imm_b[63:0] \$1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\imm_b[63:0] { \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si } + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\imm_b[63:0] { \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi } + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\imm_b[63:0] \$3 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\imm_b[63:0] { \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li } + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\imm_b[63:0] { \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd } + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\imm_b[63:0] { \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds } + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\imm_b[63:0] \$7 + attribute \src "libresoc.v:0.0-0.0" + case 4'1010 + assign { } { } + assign $1\imm_b[63:0] \$9 + attribute \src "libresoc.v:0.0-0.0" + case 4'1011 + assign { } { } + assign $1\imm_b[63:0] \$11 + case + assign $1\imm_b[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \imm_b $0\imm_b[63:0] + end + attribute \src "libresoc.v:125402.3-125448.6" + process $proc$libresoc.v:125402$4734 + assign { } { } + assign { } { } + assign $0\imm_b_ok[0:0] $1\imm_b_ok[0:0] + attribute \src "libresoc.v:125403.5-125403.29" + switch \initial + attribute \src "libresoc.v:125403.9-125403.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'1010 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'1011 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + case + assign $1\imm_b_ok[0:0] 1'0 + end + sync always + update \imm_b_ok $0\imm_b_ok[0:0] + end + attribute \src "libresoc.v:125449.3-125459.6" + process $proc$libresoc.v:125449$4735 + assign { } { } + assign { } { } + assign $0\si[15:0] $1\si[15:0] + attribute \src "libresoc.v:125450.5-125450.29" + switch \initial + attribute \src "libresoc.v:125450.9-125450.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\si[15:0] \MUL_SI + case + assign $1\si[15:0] 16'0000000000000000 + end + sync always + update \si $0\si[15:0] + end + attribute \src "libresoc.v:125460.3-125470.6" + process $proc$libresoc.v:125460$4736 + assign { } { } + assign { } { } + assign $0\si_hi[31:0] $1\si_hi[31:0] + attribute \src "libresoc.v:125461.5-125461.29" + switch \initial + attribute \src "libresoc.v:125461.9-125461.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\si_hi[31:0] \$13 [31:0] + case + assign $1\si_hi[31:0] 0 + end + sync always + update \si_hi $0\si_hi[31:0] + end + attribute \src "libresoc.v:125471.3-125481.6" + process $proc$libresoc.v:125471$4737 + assign { } { } + assign { } { } + assign $0\ui[15:0] $1\ui[15:0] + attribute \src "libresoc.v:125472.5-125472.29" + switch \initial + attribute \src "libresoc.v:125472.9-125472.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\ui[15:0] \MUL_UI + case + assign $1\ui[15:0] 16'0000000000000000 + end + sync always + update \ui $0\ui[15:0] + end + attribute \src "libresoc.v:125482.3-125492.6" + process $proc$libresoc.v:125482$4738 + assign { } { } + assign { } { } + assign $0\li[25:0] $1\li[25:0] + attribute \src "libresoc.v:125483.5-125483.29" + switch \initial + attribute \src "libresoc.v:125483.9-125483.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\li[25:0] \$16 [25:0] + case + assign $1\li[25:0] 26'00000000000000000000000000 + end + sync always + update \li $0\li[25:0] + end + attribute \src "libresoc.v:125493.3-125503.6" + process $proc$libresoc.v:125493$4739 + assign { } { } + assign { } { } + assign $0\bd[15:0] $1\bd[15:0] + attribute \src "libresoc.v:125494.5-125494.29" + switch \initial + attribute \src "libresoc.v:125494.9-125494.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\bd[15:0] \$19 [15:0] + case + assign $1\bd[15:0] 16'0000000000000000 + end + sync always + update \bd $0\bd[15:0] + end + attribute \src "libresoc.v:125504.3-125514.6" + process $proc$libresoc.v:125504$4740 + assign { } { } + assign { } { } + assign $0\ds[15:0] $1\ds[15:0] + attribute \src "libresoc.v:125505.5-125505.29" + switch \initial + attribute \src "libresoc.v:125505.9-125505.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\ds[15:0] \$22 [15:0] + case + assign $1\ds[15:0] 16'0000000000000000 + end + sync always + update \ds $0\ds[15:0] + end + connect \$9 $pos$libresoc.v:125345$4721_Y + connect \$11 $pos$libresoc.v:125346$4723_Y + connect \$14 $sshl$libresoc.v:125347$4724_Y + connect \$17 $sshl$libresoc.v:125348$4725_Y + connect \$1 $pos$libresoc.v:125349$4727_Y + connect \$20 $sshl$libresoc.v:125350$4728_Y + connect \$23 $sshl$libresoc.v:125351$4729_Y + connect \$4 $sshl$libresoc.v:125352$4730_Y + connect \$3 $pos$libresoc.v:125353$4732_Y + connect \$7 64'1111111111111111111111111111111111111111111111111111111111111111 + connect \$13 \$14 + connect \$16 \$17 + connect \$19 \$20 + connect \$22 \$23 +end +attribute \src "libresoc.v:125523.1-125776.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SHIFT_ROT.dec_bi" +attribute \generator "nMigen" +module \dec_bi$194 + attribute \src "libresoc.v:125750.3-125760.6" + wire width 16 $0\bd[15:0] + attribute \src "libresoc.v:125761.3-125771.6" + wire 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$1\si[15:0] + attribute \src "libresoc.v:125717.3-125727.6" + wire width 32 $1\si_hi[31:0] + attribute \src "libresoc.v:125728.3-125738.6" + wire width 16 $1\ui[15:0] + attribute \src "libresoc.v:125602.17-125602.110" + wire width 64 $extend$libresoc.v:125602$4742_Y + attribute \src "libresoc.v:125603.18-125603.113" + wire width 64 $extend$libresoc.v:125603$4744_Y + attribute \src "libresoc.v:125606.17-125606.110" + wire width 64 $extend$libresoc.v:125606$4748_Y + attribute \src "libresoc.v:125610.17-125610.102" + wire width 64 $extend$libresoc.v:125610$4753_Y + attribute \src "libresoc.v:125602.17-125602.110" + wire width 64 $pos$libresoc.v:125602$4743_Y + attribute \src "libresoc.v:125603.18-125603.113" + wire width 64 $pos$libresoc.v:125603$4745_Y + attribute \src "libresoc.v:125606.17-125606.110" + wire width 64 $pos$libresoc.v:125606$4749_Y + attribute \src "libresoc.v:125610.17-125610.102" + wire width 64 $pos$libresoc.v:125610$4754_Y + attribute \src "libresoc.v:125604.18-125604.120" + wire width 47 $sshl$libresoc.v:125604$4746_Y + attribute \src "libresoc.v:125605.18-125605.119" + wire width 27 $sshl$libresoc.v:125605$4747_Y + attribute \src "libresoc.v:125607.18-125607.119" + wire width 17 $sshl$libresoc.v:125607$4750_Y + attribute \src "libresoc.v:125608.18-125608.119" + wire width 17 $sshl$libresoc.v:125608$4751_Y + attribute \src "libresoc.v:125609.17-125609.109" + wire width 47 $sshl$libresoc.v:125609$4752_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 64 \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 64 \$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:384" + wire width 47 \$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:384" + wire width 47 \$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:394" + wire width 27 \$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:394" + wire width 27 \$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:399" + wire width 17 \$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:399" + wire width 17 \$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:404" + wire width 17 \$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:404" + wire width 17 \$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:390" + wire width 64 \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:390" + wire width 47 \$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:408" + wire width 64 \$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 64 \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 14 input 8 \SHIFT_ROT_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 14 input 9 \SHIFT_ROT_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 24 input 7 \SHIFT_ROT_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 input 5 \SHIFT_ROT_SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 16 input 3 \SHIFT_ROT_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 16 input 4 \SHIFT_ROT_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 6 input 6 \SHIFT_ROT_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:398" + wire width 16 \bd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:403" + wire width 16 \ds + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 1 \imm_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 2 \imm_b_ok + attribute \src "libresoc.v:125524.7-125524.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:393" + wire width 26 \li + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:365" + wire width 4 input 10 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:378" + wire width 16 \si + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:383" + wire width 32 \si_hi + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:388" + wire width 16 \ui + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + cell $pos $extend$libresoc.v:125602$4742 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 64 + connect \A \SHIFT_ROT_sh + connect \Y $extend$libresoc.v:125602$4742_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + cell $pos $extend$libresoc.v:125603$4744 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 64 + connect \A \SHIFT_ROT_SH32 + connect \Y $extend$libresoc.v:125603$4744_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + cell $pos $extend$libresoc.v:125606$4748 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \Y_WIDTH 64 + connect \A \SHIFT_ROT_UI + connect \Y $extend$libresoc.v:125606$4748_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:390" + cell $pos $extend$libresoc.v:125610$4753 + parameter \A_SIGNED 0 + parameter \A_WIDTH 47 + parameter \Y_WIDTH 64 + connect \A \$4 + connect \Y $extend$libresoc.v:125610$4753_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + cell $pos $pos$libresoc.v:125602$4743 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:125602$4742_Y + connect \Y $pos$libresoc.v:125602$4743_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + cell $pos $pos$libresoc.v:125603$4745 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:125603$4744_Y + connect \Y $pos$libresoc.v:125603$4745_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + cell $pos $pos$libresoc.v:125606$4749 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:125606$4748_Y + connect \Y $pos$libresoc.v:125606$4749_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:390" + cell $pos $pos$libresoc.v:125610$4754 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:125610$4753_Y + connect \Y $pos$libresoc.v:125610$4754_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:384" + cell $sshl $sshl$libresoc.v:125604$4746 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 47 + connect \A \SHIFT_ROT_SI + connect \B 5'10000 + connect \Y $sshl$libresoc.v:125604$4746_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:394" + cell $sshl $sshl$libresoc.v:125605$4747 + parameter \A_SIGNED 0 + parameter \A_WIDTH 24 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 27 + connect \A \SHIFT_ROT_LI + connect \B 2'10 + connect \Y $sshl$libresoc.v:125605$4747_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:399" + cell $sshl $sshl$libresoc.v:125607$4750 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 17 + connect \A \SHIFT_ROT_BD + connect \B 2'10 + connect \Y $sshl$libresoc.v:125607$4750_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:404" + cell $sshl $sshl$libresoc.v:125608$4751 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 17 + connect \A \SHIFT_ROT_DS + connect \B 2'10 + connect \Y $sshl$libresoc.v:125608$4751_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:390" + cell $sshl $sshl$libresoc.v:125609$4752 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 47 + connect \A \ui + connect \B 5'10000 + connect \Y $sshl$libresoc.v:125609$4752_Y + end + attribute \src "libresoc.v:125524.7-125524.20" + process $proc$libresoc.v:125524$4763 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:125612.3-125658.6" + process $proc$libresoc.v:125612$4755 + assign { } { } + assign { } { } + assign $0\imm_b[63:0] $1\imm_b[63:0] + attribute \src "libresoc.v:125613.5-125613.29" + switch \initial + attribute \src "libresoc.v:125613.9-125613.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\imm_b[63:0] \$1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\imm_b[63:0] { \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si } + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\imm_b[63:0] { \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi } + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\imm_b[63:0] \$3 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\imm_b[63:0] { \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li } + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\imm_b[63:0] { \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd } + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\imm_b[63:0] { \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds } + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\imm_b[63:0] \$7 + attribute \src "libresoc.v:0.0-0.0" + case 4'1010 + assign { } { } + assign $1\imm_b[63:0] \$9 + attribute \src "libresoc.v:0.0-0.0" + case 4'1011 + assign { } { } + assign $1\imm_b[63:0] \$11 + case + assign $1\imm_b[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \imm_b $0\imm_b[63:0] + end + attribute \src "libresoc.v:125659.3-125705.6" + process $proc$libresoc.v:125659$4756 + assign { } { } + assign { } { } + assign $0\imm_b_ok[0:0] $1\imm_b_ok[0:0] + attribute \src "libresoc.v:125660.5-125660.29" + switch \initial + attribute \src "libresoc.v:125660.9-125660.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'1010 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'1011 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + case + assign $1\imm_b_ok[0:0] 1'0 + end + sync always + update \imm_b_ok $0\imm_b_ok[0:0] + end + attribute \src "libresoc.v:125706.3-125716.6" + process $proc$libresoc.v:125706$4757 + assign { } { } + assign { } { } + assign $0\si[15:0] $1\si[15:0] + attribute \src "libresoc.v:125707.5-125707.29" + switch \initial + attribute \src "libresoc.v:125707.9-125707.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\si[15:0] \SHIFT_ROT_SI + case + assign $1\si[15:0] 16'0000000000000000 + end + sync always + update \si $0\si[15:0] + end + attribute \src "libresoc.v:125717.3-125727.6" + process $proc$libresoc.v:125717$4758 + assign { } { } + assign { } { } + assign $0\si_hi[31:0] $1\si_hi[31:0] + attribute \src "libresoc.v:125718.5-125718.29" + switch \initial + attribute \src "libresoc.v:125718.9-125718.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\si_hi[31:0] \$13 [31:0] + case + assign $1\si_hi[31:0] 0 + end + sync always + update \si_hi $0\si_hi[31:0] + end + attribute \src "libresoc.v:125728.3-125738.6" + process $proc$libresoc.v:125728$4759 + assign { } { } + assign { } { } + assign $0\ui[15:0] $1\ui[15:0] + attribute \src "libresoc.v:125729.5-125729.29" + switch \initial + attribute \src "libresoc.v:125729.9-125729.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\ui[15:0] \SHIFT_ROT_UI + case + assign $1\ui[15:0] 16'0000000000000000 + end + sync always + update \ui $0\ui[15:0] + end + attribute \src "libresoc.v:125739.3-125749.6" + process $proc$libresoc.v:125739$4760 + assign { } { } + assign { } { } + assign $0\li[25:0] $1\li[25:0] + attribute \src "libresoc.v:125740.5-125740.29" + switch \initial + attribute \src "libresoc.v:125740.9-125740.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\li[25:0] \$16 [25:0] + case + assign $1\li[25:0] 26'00000000000000000000000000 + end + sync always + update \li $0\li[25:0] + end + attribute \src "libresoc.v:125750.3-125760.6" + process $proc$libresoc.v:125750$4761 + assign { } { } + assign { } { } + assign $0\bd[15:0] $1\bd[15:0] + attribute \src "libresoc.v:125751.5-125751.29" + switch \initial + attribute \src "libresoc.v:125751.9-125751.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\bd[15:0] \$19 [15:0] + case + assign $1\bd[15:0] 16'0000000000000000 + end + sync always + update \bd $0\bd[15:0] + end + attribute \src "libresoc.v:125761.3-125771.6" + process $proc$libresoc.v:125761$4762 + assign { } { } + assign { } { } + assign $0\ds[15:0] $1\ds[15:0] + attribute \src "libresoc.v:125762.5-125762.29" + switch \initial + attribute \src "libresoc.v:125762.9-125762.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\ds[15:0] \$22 [15:0] + case + assign $1\ds[15:0] 16'0000000000000000 + end + sync always + update \ds $0\ds[15:0] + end + connect \$9 $pos$libresoc.v:125602$4743_Y + connect \$11 $pos$libresoc.v:125603$4745_Y + connect \$14 $sshl$libresoc.v:125604$4746_Y + connect \$17 $sshl$libresoc.v:125605$4747_Y + connect \$1 $pos$libresoc.v:125606$4749_Y + connect \$20 $sshl$libresoc.v:125607$4750_Y + connect \$23 $sshl$libresoc.v:125608$4751_Y + connect \$4 $sshl$libresoc.v:125609$4752_Y + connect \$3 $pos$libresoc.v:125610$4754_Y + connect \$7 64'1111111111111111111111111111111111111111111111111111111111111111 + connect \$13 \$14 + connect \$16 \$17 + connect \$19 \$20 + connect \$22 \$23 +end +attribute \src "libresoc.v:125780.1-126033.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec_bi" +attribute \generator "nMigen" +module \dec_bi$203 + attribute \src "libresoc.v:126007.3-126017.6" + wire width 16 $0\bd[15:0] + attribute \src "libresoc.v:126018.3-126028.6" + wire width 16 $0\ds[15:0] + attribute \src "libresoc.v:125869.3-125915.6" + wire width 64 $0\imm_b[63:0] + attribute \src "libresoc.v:125916.3-125962.6" + wire $0\imm_b_ok[0:0] + attribute \src "libresoc.v:125781.7-125781.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:125996.3-126006.6" + wire width 26 $0\li[25:0] + attribute \src "libresoc.v:125963.3-125973.6" + wire width 16 $0\si[15:0] + attribute \src "libresoc.v:125974.3-125984.6" + wire width 32 $0\si_hi[31:0] + attribute \src "libresoc.v:125985.3-125995.6" + wire width 16 $0\ui[15:0] + attribute \src "libresoc.v:126007.3-126017.6" + wire width 16 $1\bd[15:0] + attribute \src "libresoc.v:126018.3-126028.6" + wire width 16 $1\ds[15:0] + attribute \src "libresoc.v:125869.3-125915.6" + wire width 64 $1\imm_b[63:0] + attribute \src "libresoc.v:125916.3-125962.6" + wire $1\imm_b_ok[0:0] + attribute \src "libresoc.v:125996.3-126006.6" + wire width 26 $1\li[25:0] + attribute \src "libresoc.v:125963.3-125973.6" + wire width 16 $1\si[15:0] + attribute \src "libresoc.v:125974.3-125984.6" + wire width 32 $1\si_hi[31:0] + attribute \src "libresoc.v:125985.3-125995.6" + wire width 16 $1\ui[15:0] + attribute \src "libresoc.v:125859.17-125859.105" + wire width 64 $extend$libresoc.v:125859$4764_Y + attribute \src "libresoc.v:125860.18-125860.108" + wire width 64 $extend$libresoc.v:125860$4766_Y + attribute \src "libresoc.v:125863.17-125863.105" + wire width 64 $extend$libresoc.v:125863$4770_Y + attribute \src "libresoc.v:125867.17-125867.102" + wire width 64 $extend$libresoc.v:125867$4775_Y + attribute \src "libresoc.v:125859.17-125859.105" + wire width 64 $pos$libresoc.v:125859$4765_Y + attribute \src "libresoc.v:125860.18-125860.108" + wire width 64 $pos$libresoc.v:125860$4767_Y + attribute \src "libresoc.v:125863.17-125863.105" + wire width 64 $pos$libresoc.v:125863$4771_Y + attribute \src "libresoc.v:125867.17-125867.102" + wire width 64 $pos$libresoc.v:125867$4776_Y + attribute \src "libresoc.v:125861.18-125861.115" + wire width 47 $sshl$libresoc.v:125861$4768_Y + attribute \src "libresoc.v:125862.18-125862.114" + wire width 27 $sshl$libresoc.v:125862$4769_Y + attribute \src "libresoc.v:125864.18-125864.114" + wire width 17 $sshl$libresoc.v:125864$4772_Y + attribute \src "libresoc.v:125865.18-125865.114" + wire width 17 $sshl$libresoc.v:125865$4773_Y + attribute \src "libresoc.v:125866.17-125866.109" + wire width 47 $sshl$libresoc.v:125866$4774_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 64 \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 64 \$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:384" + wire width 47 \$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:384" + wire width 47 \$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:394" + wire width 27 \$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:394" + wire width 27 \$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:399" + wire width 17 \$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:399" + wire width 17 \$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:404" + wire width 17 \$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:404" + wire width 17 \$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:390" + wire width 64 \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:390" + wire width 47 \$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:408" + wire width 64 \$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 64 \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 14 input 8 \LDST_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 14 input 9 \LDST_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 24 input 7 \LDST_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 input 5 \LDST_SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 16 input 3 \LDST_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 16 input 4 \LDST_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 6 input 6 \LDST_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:398" + wire width 16 \bd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:403" + wire width 16 \ds + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 1 \imm_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 2 \imm_b_ok + attribute \src "libresoc.v:125781.7-125781.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:393" + wire width 26 \li + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:365" + wire width 4 input 10 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:378" + wire width 16 \si + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:383" + wire width 32 \si_hi + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:388" + wire width 16 \ui + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + cell $pos $extend$libresoc.v:125859$4764 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 64 + connect \A \LDST_sh + connect \Y $extend$libresoc.v:125859$4764_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + cell $pos $extend$libresoc.v:125860$4766 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 64 + connect \A \LDST_SH32 + connect \Y $extend$libresoc.v:125860$4766_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + cell $pos $extend$libresoc.v:125863$4770 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \Y_WIDTH 64 + connect \A \LDST_UI + connect \Y $extend$libresoc.v:125863$4770_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:390" + cell $pos $extend$libresoc.v:125867$4775 + parameter \A_SIGNED 0 + parameter \A_WIDTH 47 + parameter \Y_WIDTH 64 + connect \A \$4 + connect \Y $extend$libresoc.v:125867$4775_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + cell $pos $pos$libresoc.v:125859$4765 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:125859$4764_Y + connect \Y $pos$libresoc.v:125859$4765_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + cell $pos $pos$libresoc.v:125860$4767 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:125860$4766_Y + connect \Y $pos$libresoc.v:125860$4767_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + cell $pos $pos$libresoc.v:125863$4771 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:125863$4770_Y + connect \Y $pos$libresoc.v:125863$4771_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:390" + cell $pos $pos$libresoc.v:125867$4776 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:125867$4775_Y + connect \Y $pos$libresoc.v:125867$4776_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:384" + cell $sshl $sshl$libresoc.v:125861$4768 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 47 + connect \A \LDST_SI + connect \B 5'10000 + connect \Y $sshl$libresoc.v:125861$4768_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:394" + cell $sshl $sshl$libresoc.v:125862$4769 + parameter \A_SIGNED 0 + parameter \A_WIDTH 24 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 27 + connect \A \LDST_LI + connect \B 2'10 + connect \Y $sshl$libresoc.v:125862$4769_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:399" + cell $sshl $sshl$libresoc.v:125864$4772 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 17 + connect \A \LDST_BD + connect \B 2'10 + connect \Y $sshl$libresoc.v:125864$4772_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:404" + cell $sshl $sshl$libresoc.v:125865$4773 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 17 + connect \A \LDST_DS + connect \B 2'10 + connect \Y $sshl$libresoc.v:125865$4773_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:390" + cell $sshl $sshl$libresoc.v:125866$4774 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 47 + connect \A \ui + connect \B 5'10000 + connect \Y $sshl$libresoc.v:125866$4774_Y + end + attribute \src "libresoc.v:125781.7-125781.20" + process $proc$libresoc.v:125781$4785 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:125869.3-125915.6" + process $proc$libresoc.v:125869$4777 + assign { } { } + assign { } { } + assign $0\imm_b[63:0] $1\imm_b[63:0] + attribute \src "libresoc.v:125870.5-125870.29" + switch \initial + attribute \src "libresoc.v:125870.9-125870.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\imm_b[63:0] \$1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\imm_b[63:0] { \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si } + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\imm_b[63:0] { \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi } + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\imm_b[63:0] \$3 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\imm_b[63:0] { \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li } + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\imm_b[63:0] { \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd } + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\imm_b[63:0] { \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds } + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\imm_b[63:0] \$7 + attribute \src "libresoc.v:0.0-0.0" + case 4'1010 + assign { } { } + assign $1\imm_b[63:0] \$9 + attribute \src "libresoc.v:0.0-0.0" + case 4'1011 + assign { } { } + assign $1\imm_b[63:0] \$11 + case + assign $1\imm_b[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \imm_b $0\imm_b[63:0] + end + attribute \src "libresoc.v:125916.3-125962.6" + process $proc$libresoc.v:125916$4778 + assign { } { } + assign { } { } + assign $0\imm_b_ok[0:0] $1\imm_b_ok[0:0] + attribute \src "libresoc.v:125917.5-125917.29" + switch \initial + attribute \src "libresoc.v:125917.9-125917.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'1010 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 4'1011 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + case + assign $1\imm_b_ok[0:0] 1'0 + end + sync always + update \imm_b_ok $0\imm_b_ok[0:0] + end + attribute \src "libresoc.v:125963.3-125973.6" + process $proc$libresoc.v:125963$4779 + assign { } { } + assign { } { } + assign $0\si[15:0] $1\si[15:0] + attribute \src "libresoc.v:125964.5-125964.29" + switch \initial + attribute \src "libresoc.v:125964.9-125964.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\si[15:0] \LDST_SI + case + assign $1\si[15:0] 16'0000000000000000 + end + sync always + update \si $0\si[15:0] + end + attribute \src "libresoc.v:125974.3-125984.6" + process $proc$libresoc.v:125974$4780 + assign { } { } + assign { } { } + assign $0\si_hi[31:0] $1\si_hi[31:0] + attribute \src "libresoc.v:125975.5-125975.29" + switch \initial + attribute \src "libresoc.v:125975.9-125975.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\si_hi[31:0] \$13 [31:0] + case + assign $1\si_hi[31:0] 0 + end + sync always + update \si_hi $0\si_hi[31:0] + end + attribute \src "libresoc.v:125985.3-125995.6" + process $proc$libresoc.v:125985$4781 + assign { } { } + assign { } { } + assign $0\ui[15:0] $1\ui[15:0] + attribute \src "libresoc.v:125986.5-125986.29" + switch \initial + attribute \src "libresoc.v:125986.9-125986.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\ui[15:0] \LDST_UI + case + assign $1\ui[15:0] 16'0000000000000000 + end + sync always + update \ui $0\ui[15:0] + end + attribute \src "libresoc.v:125996.3-126006.6" + process $proc$libresoc.v:125996$4782 + assign { } { } + assign { } { } + assign $0\li[25:0] $1\li[25:0] + attribute \src "libresoc.v:125997.5-125997.29" + switch \initial + attribute \src "libresoc.v:125997.9-125997.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\li[25:0] \$16 [25:0] + case + assign $1\li[25:0] 26'00000000000000000000000000 + end + sync always + update \li $0\li[25:0] + end + attribute \src "libresoc.v:126007.3-126017.6" + process $proc$libresoc.v:126007$4783 + assign { } { } + assign { } { } + assign $0\bd[15:0] $1\bd[15:0] + attribute \src "libresoc.v:126008.5-126008.29" + switch \initial + attribute \src "libresoc.v:126008.9-126008.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\bd[15:0] \$19 [15:0] + case + assign $1\bd[15:0] 16'0000000000000000 + end + sync always + update \bd $0\bd[15:0] + end + attribute \src "libresoc.v:126018.3-126028.6" + process $proc$libresoc.v:126018$4784 + assign { } { } + assign { } { } + assign $0\ds[15:0] $1\ds[15:0] + attribute \src "libresoc.v:126019.5-126019.29" + switch \initial + attribute \src "libresoc.v:126019.9-126019.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\ds[15:0] \$22 [15:0] + case + assign $1\ds[15:0] 16'0000000000000000 + end + sync always + update \ds $0\ds[15:0] + end + connect \$9 $pos$libresoc.v:125859$4765_Y + connect \$11 $pos$libresoc.v:125860$4767_Y + connect \$14 $sshl$libresoc.v:125861$4768_Y + connect \$17 $sshl$libresoc.v:125862$4769_Y + connect \$1 $pos$libresoc.v:125863$4771_Y + connect \$20 $sshl$libresoc.v:125864$4772_Y + connect \$23 $sshl$libresoc.v:125865$4773_Y + connect \$4 $sshl$libresoc.v:125866$4774_Y + connect \$3 $pos$libresoc.v:125867$4776_Y + connect \$7 64'1111111111111111111111111111111111111111111111111111111111111111 + connect \$13 \$14 + connect \$16 \$17 + connect \$19 \$20 + connect \$22 \$23 +end +attribute \src "libresoc.v:126037.1-126085.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_c" +attribute \generator "nMigen" +module \dec_c + attribute \src "libresoc.v:126038.7-126038.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:126055.3-126069.6" + wire width 5 $0\reg_c[4:0] + attribute \src "libresoc.v:126070.3-126084.6" + wire $0\reg_c_ok[0:0] + attribute \src "libresoc.v:126055.3-126069.6" + wire width 5 $1\reg_c[4:0] + attribute \src "libresoc.v:126070.3-126084.6" + wire $1\reg_c_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 input 4 \RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 input 3 \RS + attribute \src "libresoc.v:126038.7-126038.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 5 output 1 \reg_c + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 2 \reg_c_ok + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:428" + wire width 2 input 5 \sel_in + attribute \src "libresoc.v:126038.7-126038.20" + process $proc$libresoc.v:126038$4788 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:126055.3-126069.6" + process $proc$libresoc.v:126055$4786 + assign { } { } + assign { } { } + assign $0\reg_c[4:0] $1\reg_c[4:0] + attribute \src "libresoc.v:126056.5-126056.29" + switch \initial + attribute \src "libresoc.v:126056.9-126056.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:439" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\reg_c[4:0] \RB + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\reg_c[4:0] \RS + case + assign $1\reg_c[4:0] 5'00000 + end + sync always + update \reg_c $0\reg_c[4:0] + end + attribute \src "libresoc.v:126070.3-126084.6" + process $proc$libresoc.v:126070$4787 + assign { } { } + assign { } { } + assign $0\reg_c_ok[0:0] $1\reg_c_ok[0:0] + attribute \src "libresoc.v:126071.5-126071.29" + switch \initial + attribute \src "libresoc.v:126071.9-126071.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:439" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\reg_c_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\reg_c_ok[0:0] 1'1 + case + assign $1\reg_c_ok[0:0] 1'0 + end + sync always + update \reg_c_ok $0\reg_c_ok[0:0] + end +end +attribute \src "libresoc.v:126089.1-126387.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec_cr_in" +attribute \generator "nMigen" +module \dec_cr_in + attribute \src "libresoc.v:126292.3-126318.6" + wire width 3 $0\cr_bitfield[2:0] + attribute \src "libresoc.v:126319.3-126329.6" + wire width 3 $0\cr_bitfield_b[2:0] + attribute \src "libresoc.v:126259.3-126269.6" + wire $0\cr_bitfield_b_ok[0:0] + attribute \src "libresoc.v:126330.3-126340.6" + wire width 3 $0\cr_bitfield_o[2:0] + attribute \src "libresoc.v:126270.3-126280.6" + wire $0\cr_bitfield_o_ok[0:0] + attribute \src "libresoc.v:126232.3-126258.6" + wire $0\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:126368.3-126386.6" + wire width 8 $0\cr_fxm[7:0] + attribute \src "libresoc.v:126281.3-126291.6" + wire $0\cr_fxm_ok[0:0] + attribute \src "libresoc.v:126090.7-126090.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:126341.3-126351.6" + wire $0\move_one[0:0] + attribute \src "libresoc.v:126352.3-126367.6" + wire width 8 $0\ppick_i[7:0] + attribute \src "libresoc.v:126292.3-126318.6" + wire width 3 $1\cr_bitfield[2:0] + attribute \src "libresoc.v:126319.3-126329.6" + wire width 3 $1\cr_bitfield_b[2:0] + attribute \src "libresoc.v:126259.3-126269.6" + wire $1\cr_bitfield_b_ok[0:0] + attribute \src "libresoc.v:126330.3-126340.6" + wire width 3 $1\cr_bitfield_o[2:0] + attribute \src "libresoc.v:126270.3-126280.6" + wire $1\cr_bitfield_o_ok[0:0] + attribute \src "libresoc.v:126232.3-126258.6" + wire $1\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:126368.3-126386.6" + wire width 8 $1\cr_fxm[7:0] + attribute \src "libresoc.v:126281.3-126291.6" + wire $1\cr_fxm_ok[0:0] + attribute \src "libresoc.v:126341.3-126351.6" + wire $1\move_one[0:0] + attribute \src "libresoc.v:126352.3-126367.6" + wire width 8 $1\ppick_i[7:0] + attribute \src "libresoc.v:126368.3-126386.6" + wire width 8 $2\cr_fxm[7:0] + attribute \src "libresoc.v:126352.3-126367.6" + wire width 8 $2\ppick_i[7:0] + attribute \src "libresoc.v:126225.17-126225.112" + wire $and$libresoc.v:126225$4790_Y + attribute \src "libresoc.v:126227.17-126227.112" + wire $and$libresoc.v:126227$4792_Y + attribute \src "libresoc.v:126224.17-126224.121" + wire $eq$libresoc.v:126224$4789_Y + attribute \src "libresoc.v:126226.17-126226.121" + wire $eq$libresoc.v:126226$4791_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 input 4 \ALU_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 input 3 \ALU_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 input 8 \ALU_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 input 7 \ALU_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 input 5 \ALU_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 8 input 6 \ALU_FXM + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 input 2 \ALU_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 3 input 9 \X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 \cr_bitfield + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 \cr_bitfield_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_bitfield_b_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 \cr_bitfield_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_bitfield_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_bitfield_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 8 \cr_fxm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_fxm_ok + attribute \src "libresoc.v:126090.7-126090.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:651" + wire width 32 input 10 \insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:695" + wire \move_one + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 8 \ppick_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" + wire width 8 \ppick_o + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:650" + wire width 3 input 1 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" + cell $and $and$libresoc.v:126225$4790 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$1 + connect \B \move_one + connect \Y $and$libresoc.v:126225$4790_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" + cell $and $and$libresoc.v:126227$4792 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$5 + connect \B \move_one + connect \Y $and$libresoc.v:126227$4792_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" + cell $eq $eq$libresoc.v:126224$4789 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \ALU_internal_op + connect \B 7'0101101 + connect \Y $eq$libresoc.v:126224$4789_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" + cell $eq $eq$libresoc.v:126226$4791 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \ALU_internal_op + connect \B 7'0101101 + connect \Y $eq$libresoc.v:126226$4791_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:126228.9-126231.4" + cell \ppick \ppick + connect \i \ppick_i + connect \o \ppick_o + end + attribute \src "libresoc.v:126090.7-126090.20" + process $proc$libresoc.v:126090$4803 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:126232.3-126258.6" + process $proc$libresoc.v:126232$4793 + assign { } { } + assign { } { } + assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:126233.5-126233.29" + switch \initial + attribute \src "libresoc.v:126233.9-126233.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 3'101 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + case + assign $1\cr_bitfield_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] + end + attribute \src "libresoc.v:126259.3-126269.6" + process $proc$libresoc.v:126259$4794 + assign { } { } + assign { } { } + assign $0\cr_bitfield_b_ok[0:0] $1\cr_bitfield_b_ok[0:0] + attribute \src "libresoc.v:126260.5-126260.29" + switch \initial + attribute \src "libresoc.v:126260.9-126260.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_b_ok[0:0] 1'1 + case + assign $1\cr_bitfield_b_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_b_ok $0\cr_bitfield_b_ok[0:0] + end + attribute \src "libresoc.v:126270.3-126280.6" + process $proc$libresoc.v:126270$4795 + assign { } { } + assign { } { } + assign $0\cr_bitfield_o_ok[0:0] $1\cr_bitfield_o_ok[0:0] + attribute \src "libresoc.v:126271.5-126271.29" + switch \initial + attribute \src "libresoc.v:126271.9-126271.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_o_ok[0:0] 1'1 + case + assign $1\cr_bitfield_o_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_o_ok $0\cr_bitfield_o_ok[0:0] + end + attribute \src "libresoc.v:126281.3-126291.6" + process $proc$libresoc.v:126281$4796 + assign { } { } + assign { } { } + assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] + attribute \src "libresoc.v:126282.5-126282.29" + switch \initial + attribute \src "libresoc.v:126282.9-126282.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'110 + assign { } { } + assign $1\cr_fxm_ok[0:0] 1'1 + case + assign $1\cr_fxm_ok[0:0] 1'0 + end + sync always + update \cr_fxm_ok $0\cr_fxm_ok[0:0] + end + attribute \src "libresoc.v:126292.3-126318.6" + process $proc$libresoc.v:126292$4797 + assign { } { } + assign { } { } + assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] + attribute \src "libresoc.v:126293.5-126293.29" + switch \initial + attribute \src "libresoc.v:126293.9-126293.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\cr_bitfield[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\cr_bitfield[2:0] \ALU_BI [4:2] + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\cr_bitfield[2:0] \X_BFA + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield[2:0] \ALU_BA [4:2] + attribute \src "libresoc.v:0.0-0.0" + case 3'101 + assign { } { } + assign $1\cr_bitfield[2:0] \ALU_BC [4:2] + case + assign $1\cr_bitfield[2:0] 3'000 + end + sync always + update \cr_bitfield $0\cr_bitfield[2:0] + end + attribute \src "libresoc.v:126319.3-126329.6" + process $proc$libresoc.v:126319$4798 + assign { } { } + assign { } { } + assign $0\cr_bitfield_b[2:0] $1\cr_bitfield_b[2:0] + attribute \src "libresoc.v:126320.5-126320.29" + switch \initial + attribute \src "libresoc.v:126320.9-126320.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_b[2:0] \ALU_BB [4:2] + case + assign $1\cr_bitfield_b[2:0] 3'000 + end + sync always + update \cr_bitfield_b $0\cr_bitfield_b[2:0] + end + attribute \src "libresoc.v:126330.3-126340.6" + process $proc$libresoc.v:126330$4799 + assign { } { } + assign { } { } + assign $0\cr_bitfield_o[2:0] $1\cr_bitfield_o[2:0] + attribute \src "libresoc.v:126331.5-126331.29" + switch \initial + attribute \src "libresoc.v:126331.9-126331.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_o[2:0] \ALU_BT [4:2] + case + assign $1\cr_bitfield_o[2:0] 3'000 + end + sync always + update \cr_bitfield_o $0\cr_bitfield_o[2:0] + end + attribute \src "libresoc.v:126341.3-126351.6" + process $proc$libresoc.v:126341$4800 + assign { } { } + assign { } { } + assign $0\move_one[0:0] $1\move_one[0:0] + attribute \src "libresoc.v:126342.5-126342.29" + switch \initial + attribute \src "libresoc.v:126342.9-126342.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'110 + assign { } { } + assign $1\move_one[0:0] \insn_in [20] + case + assign $1\move_one[0:0] 1'0 + end + sync always + update \move_one $0\move_one[0:0] + end + attribute \src "libresoc.v:126352.3-126367.6" + process $proc$libresoc.v:126352$4801 + assign { } { } + assign { } { } + assign $0\ppick_i[7:0] $1\ppick_i[7:0] + attribute \src "libresoc.v:126353.5-126353.29" + switch \initial + attribute \src "libresoc.v:126353.9-126353.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'110 + assign { } { } + assign $1\ppick_i[7:0] $2\ppick_i[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ppick_i[7:0] \ALU_FXM + case + assign $2\ppick_i[7:0] 8'00000000 + end + case + assign $1\ppick_i[7:0] 8'00000000 + end + sync always + update \ppick_i $0\ppick_i[7:0] + end + attribute \src "libresoc.v:126368.3-126386.6" + process $proc$libresoc.v:126368$4802 + assign { } { } + assign { } { } + assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] + attribute \src "libresoc.v:126369.5-126369.29" + switch \initial + attribute \src "libresoc.v:126369.9-126369.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'110 + assign { } { } + assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" + switch \$7 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_fxm[7:0] \ppick_o + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cr_fxm[7:0] 8'11111111 + end + case + assign $1\cr_fxm[7:0] 8'00000000 + end + sync always + update \cr_fxm $0\cr_fxm[7:0] + end + connect \$1 $eq$libresoc.v:126224$4789_Y + connect \$3 $and$libresoc.v:126225$4790_Y + connect \$5 $eq$libresoc.v:126226$4791_Y + connect \$7 $and$libresoc.v:126227$4792_Y +end +attribute \src "libresoc.v:126391.1-126689.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_CR.dec_cr_in" +attribute \generator "nMigen" +module \dec_cr_in$142 + attribute \src "libresoc.v:126594.3-126620.6" + wire width 3 $0\cr_bitfield[2:0] + attribute \src "libresoc.v:126621.3-126631.6" + wire width 3 $0\cr_bitfield_b[2:0] + attribute \src "libresoc.v:126561.3-126571.6" + wire $0\cr_bitfield_b_ok[0:0] + attribute \src "libresoc.v:126632.3-126642.6" + wire width 3 $0\cr_bitfield_o[2:0] + attribute \src "libresoc.v:126572.3-126582.6" + wire $0\cr_bitfield_o_ok[0:0] + attribute \src "libresoc.v:126534.3-126560.6" + wire $0\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:126670.3-126688.6" + wire width 8 $0\cr_fxm[7:0] + attribute \src "libresoc.v:126583.3-126593.6" + wire $0\cr_fxm_ok[0:0] + attribute \src "libresoc.v:126392.7-126392.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:126643.3-126653.6" + wire $0\move_one[0:0] + attribute \src "libresoc.v:126654.3-126669.6" + wire width 8 $0\ppick_i[7:0] + attribute \src "libresoc.v:126594.3-126620.6" + wire width 3 $1\cr_bitfield[2:0] + attribute \src "libresoc.v:126621.3-126631.6" + wire width 3 $1\cr_bitfield_b[2:0] + attribute \src "libresoc.v:126561.3-126571.6" + wire $1\cr_bitfield_b_ok[0:0] + attribute \src "libresoc.v:126632.3-126642.6" + wire width 3 $1\cr_bitfield_o[2:0] + attribute \src "libresoc.v:126572.3-126582.6" + wire $1\cr_bitfield_o_ok[0:0] + attribute \src "libresoc.v:126534.3-126560.6" + wire $1\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:126670.3-126688.6" + wire width 8 $1\cr_fxm[7:0] + attribute \src "libresoc.v:126583.3-126593.6" + wire $1\cr_fxm_ok[0:0] + attribute \src "libresoc.v:126643.3-126653.6" + wire $1\move_one[0:0] + attribute \src "libresoc.v:126654.3-126669.6" + wire width 8 $1\ppick_i[7:0] + attribute \src "libresoc.v:126670.3-126688.6" + wire width 8 $2\cr_fxm[7:0] + attribute \src "libresoc.v:126654.3-126669.6" + wire width 8 $2\ppick_i[7:0] + attribute \src "libresoc.v:126527.17-126527.112" + wire $and$libresoc.v:126527$4805_Y + attribute \src "libresoc.v:126529.17-126529.112" + wire $and$libresoc.v:126529$4807_Y + attribute \src "libresoc.v:126526.17-126526.120" + wire $eq$libresoc.v:126526$4804_Y + attribute \src "libresoc.v:126528.17-126528.120" + wire $eq$libresoc.v:126528$4806_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 input 4 \CR_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 input 3 \CR_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 input 8 \CR_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 input 7 \CR_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 input 5 \CR_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 8 input 6 \CR_FXM + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 input 2 \CR_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 3 input 9 \X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 \cr_bitfield + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 \cr_bitfield_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_bitfield_b_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 \cr_bitfield_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_bitfield_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_bitfield_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 8 \cr_fxm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_fxm_ok + attribute \src "libresoc.v:126392.7-126392.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:651" + wire width 32 input 10 \insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:695" + wire \move_one + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 8 \ppick_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" + wire width 8 \ppick_o + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:650" + wire width 3 input 1 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" + cell $and $and$libresoc.v:126527$4805 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$1 + connect \B \move_one + connect \Y $and$libresoc.v:126527$4805_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" + cell $and $and$libresoc.v:126529$4807 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$5 + connect \B \move_one + connect \Y $and$libresoc.v:126529$4807_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" + cell $eq $eq$libresoc.v:126526$4804 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \CR_internal_op + connect \B 7'0101101 + connect \Y $eq$libresoc.v:126526$4804_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" + cell $eq $eq$libresoc.v:126528$4806 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \CR_internal_op + connect \B 7'0101101 + connect \Y $eq$libresoc.v:126528$4806_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:126530.15-126533.4" + cell \ppick$143 \ppick + connect \i \ppick_i + connect \o \ppick_o + end + attribute \src "libresoc.v:126392.7-126392.20" + process $proc$libresoc.v:126392$4818 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:126534.3-126560.6" + process $proc$libresoc.v:126534$4808 + assign { } { } + assign { } { } + assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:126535.5-126535.29" + switch \initial + attribute \src "libresoc.v:126535.9-126535.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 3'101 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + case + assign $1\cr_bitfield_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] + end + attribute \src "libresoc.v:126561.3-126571.6" + process $proc$libresoc.v:126561$4809 + assign { } { } + assign { } { } + assign $0\cr_bitfield_b_ok[0:0] $1\cr_bitfield_b_ok[0:0] + attribute \src "libresoc.v:126562.5-126562.29" + switch \initial + attribute \src "libresoc.v:126562.9-126562.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_b_ok[0:0] 1'1 + case + assign $1\cr_bitfield_b_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_b_ok $0\cr_bitfield_b_ok[0:0] + end + attribute \src "libresoc.v:126572.3-126582.6" + process $proc$libresoc.v:126572$4810 + assign { } { } + assign { } { } + assign $0\cr_bitfield_o_ok[0:0] $1\cr_bitfield_o_ok[0:0] + attribute \src "libresoc.v:126573.5-126573.29" + switch \initial + attribute \src "libresoc.v:126573.9-126573.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_o_ok[0:0] 1'1 + case + assign $1\cr_bitfield_o_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_o_ok $0\cr_bitfield_o_ok[0:0] + end + attribute \src "libresoc.v:126583.3-126593.6" + process $proc$libresoc.v:126583$4811 + assign { } { } + assign { } { } + assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] + attribute \src "libresoc.v:126584.5-126584.29" + switch \initial + attribute \src "libresoc.v:126584.9-126584.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'110 + assign { } { } + assign $1\cr_fxm_ok[0:0] 1'1 + case + assign $1\cr_fxm_ok[0:0] 1'0 + end + sync always + update \cr_fxm_ok $0\cr_fxm_ok[0:0] + end + attribute \src "libresoc.v:126594.3-126620.6" + process $proc$libresoc.v:126594$4812 + assign { } { } + assign { } { } + assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] + attribute \src "libresoc.v:126595.5-126595.29" + switch \initial + attribute \src "libresoc.v:126595.9-126595.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\cr_bitfield[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\cr_bitfield[2:0] \CR_BI [4:2] + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\cr_bitfield[2:0] \X_BFA + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield[2:0] \CR_BA [4:2] + attribute \src "libresoc.v:0.0-0.0" + case 3'101 + assign { } { } + assign $1\cr_bitfield[2:0] \CR_BC [4:2] + case + assign $1\cr_bitfield[2:0] 3'000 + end + sync always + update \cr_bitfield $0\cr_bitfield[2:0] + end + attribute \src "libresoc.v:126621.3-126631.6" + process $proc$libresoc.v:126621$4813 + assign { } { } + assign { } { } + assign $0\cr_bitfield_b[2:0] $1\cr_bitfield_b[2:0] + attribute \src "libresoc.v:126622.5-126622.29" + switch \initial + attribute \src "libresoc.v:126622.9-126622.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_b[2:0] \CR_BB [4:2] + case + assign $1\cr_bitfield_b[2:0] 3'000 + end + sync always + update \cr_bitfield_b $0\cr_bitfield_b[2:0] + end + attribute \src "libresoc.v:126632.3-126642.6" + process $proc$libresoc.v:126632$4814 + assign { } { } + assign { } { } + assign $0\cr_bitfield_o[2:0] $1\cr_bitfield_o[2:0] + attribute \src "libresoc.v:126633.5-126633.29" + switch \initial + attribute \src "libresoc.v:126633.9-126633.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_o[2:0] \CR_BT [4:2] + case + assign $1\cr_bitfield_o[2:0] 3'000 + end + sync always + update \cr_bitfield_o $0\cr_bitfield_o[2:0] + end + attribute \src "libresoc.v:126643.3-126653.6" + process $proc$libresoc.v:126643$4815 + assign { } { } + assign { } { } + assign $0\move_one[0:0] $1\move_one[0:0] + attribute \src "libresoc.v:126644.5-126644.29" + switch \initial + attribute \src "libresoc.v:126644.9-126644.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'110 + assign { } { } + assign $1\move_one[0:0] \insn_in [20] + case + assign $1\move_one[0:0] 1'0 + end + sync always + update \move_one $0\move_one[0:0] + end + attribute \src "libresoc.v:126654.3-126669.6" + process $proc$libresoc.v:126654$4816 + assign { } { } + assign { } { } + assign $0\ppick_i[7:0] $1\ppick_i[7:0] + attribute \src "libresoc.v:126655.5-126655.29" + switch \initial + attribute \src "libresoc.v:126655.9-126655.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'110 + assign { } { } + assign $1\ppick_i[7:0] $2\ppick_i[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ppick_i[7:0] \CR_FXM + case + assign $2\ppick_i[7:0] 8'00000000 + end + case + assign $1\ppick_i[7:0] 8'00000000 + end + sync always + update \ppick_i $0\ppick_i[7:0] + end + attribute \src "libresoc.v:126670.3-126688.6" + process $proc$libresoc.v:126670$4817 + assign { } { } + assign { } { } + assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] + attribute \src "libresoc.v:126671.5-126671.29" + switch \initial + attribute \src "libresoc.v:126671.9-126671.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'110 + assign { } { } + assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" + switch \$7 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_fxm[7:0] \ppick_o + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cr_fxm[7:0] 8'11111111 + end + case + assign $1\cr_fxm[7:0] 8'00000000 + end + sync always + update \cr_fxm $0\cr_fxm[7:0] + end + connect \$1 $eq$libresoc.v:126526$4804_Y + connect \$3 $and$libresoc.v:126527$4805_Y + connect \$5 $eq$libresoc.v:126528$4806_Y + connect \$7 $and$libresoc.v:126529$4807_Y +end +attribute \src "libresoc.v:126693.1-126991.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_BRANCH.dec_cr_in" +attribute \generator "nMigen" +module \dec_cr_in$149 + attribute \src "libresoc.v:126896.3-126922.6" + wire width 3 $0\cr_bitfield[2:0] + attribute \src "libresoc.v:126923.3-126933.6" + wire width 3 $0\cr_bitfield_b[2:0] + attribute \src "libresoc.v:126863.3-126873.6" + wire $0\cr_bitfield_b_ok[0:0] + attribute \src "libresoc.v:126934.3-126944.6" + wire width 3 $0\cr_bitfield_o[2:0] + attribute \src "libresoc.v:126874.3-126884.6" + wire $0\cr_bitfield_o_ok[0:0] + attribute \src "libresoc.v:126836.3-126862.6" + wire $0\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:126972.3-126990.6" + wire width 8 $0\cr_fxm[7:0] + attribute \src "libresoc.v:126885.3-126895.6" + wire $0\cr_fxm_ok[0:0] + attribute \src "libresoc.v:126694.7-126694.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:126945.3-126955.6" + wire $0\move_one[0:0] + attribute \src "libresoc.v:126956.3-126971.6" + wire width 8 $0\ppick_i[7:0] + attribute \src "libresoc.v:126896.3-126922.6" + wire width 3 $1\cr_bitfield[2:0] + attribute \src "libresoc.v:126923.3-126933.6" + wire width 3 $1\cr_bitfield_b[2:0] + attribute \src "libresoc.v:126863.3-126873.6" + wire $1\cr_bitfield_b_ok[0:0] + attribute \src "libresoc.v:126934.3-126944.6" + wire width 3 $1\cr_bitfield_o[2:0] + attribute \src "libresoc.v:126874.3-126884.6" + wire $1\cr_bitfield_o_ok[0:0] + attribute \src "libresoc.v:126836.3-126862.6" + wire $1\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:126972.3-126990.6" + wire width 8 $1\cr_fxm[7:0] + attribute \src "libresoc.v:126885.3-126895.6" + wire $1\cr_fxm_ok[0:0] + attribute \src "libresoc.v:126945.3-126955.6" + wire $1\move_one[0:0] + attribute \src "libresoc.v:126956.3-126971.6" + wire width 8 $1\ppick_i[7:0] + attribute \src "libresoc.v:126972.3-126990.6" + wire width 8 $2\cr_fxm[7:0] + attribute \src "libresoc.v:126956.3-126971.6" + wire width 8 $2\ppick_i[7:0] + attribute \src "libresoc.v:126829.17-126829.112" + wire $and$libresoc.v:126829$4820_Y + attribute \src "libresoc.v:126831.17-126831.112" + wire $and$libresoc.v:126831$4822_Y + attribute \src "libresoc.v:126828.17-126828.124" + wire $eq$libresoc.v:126828$4819_Y + attribute \src "libresoc.v:126830.17-126830.124" + wire $eq$libresoc.v:126830$4821_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 input 4 \BRANCH_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 input 3 \BRANCH_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 input 8 \BRANCH_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 input 7 \BRANCH_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 input 5 \BRANCH_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 8 input 6 \BRANCH_FXM + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 input 2 \BRANCH_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 3 input 9 \X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 \cr_bitfield + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 \cr_bitfield_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_bitfield_b_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 \cr_bitfield_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_bitfield_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_bitfield_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 8 \cr_fxm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_fxm_ok + attribute \src "libresoc.v:126694.7-126694.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:651" + wire width 32 input 10 \insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:695" + wire \move_one + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 8 \ppick_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" + wire width 8 \ppick_o + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:650" + wire width 3 input 1 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" + cell $and $and$libresoc.v:126829$4820 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$1 + connect \B \move_one + connect \Y $and$libresoc.v:126829$4820_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" + cell $and $and$libresoc.v:126831$4822 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$5 + connect \B \move_one + connect \Y $and$libresoc.v:126831$4822_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" + cell $eq $eq$libresoc.v:126828$4819 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \BRANCH_internal_op + connect \B 7'0101101 + connect \Y $eq$libresoc.v:126828$4819_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" + cell $eq $eq$libresoc.v:126830$4821 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \BRANCH_internal_op + connect \B 7'0101101 + connect \Y $eq$libresoc.v:126830$4821_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:126832.15-126835.4" + cell \ppick$150 \ppick + connect \i \ppick_i + connect \o \ppick_o + end + attribute \src "libresoc.v:126694.7-126694.20" + process $proc$libresoc.v:126694$4833 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:126836.3-126862.6" + process $proc$libresoc.v:126836$4823 + assign { } { } + assign { } { } + assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:126837.5-126837.29" + switch \initial + attribute \src "libresoc.v:126837.9-126837.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 3'101 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + case + assign $1\cr_bitfield_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] + end + attribute \src "libresoc.v:126863.3-126873.6" + process $proc$libresoc.v:126863$4824 + assign { } { } + assign { } { } + assign $0\cr_bitfield_b_ok[0:0] $1\cr_bitfield_b_ok[0:0] + attribute \src "libresoc.v:126864.5-126864.29" + switch \initial + attribute \src "libresoc.v:126864.9-126864.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_b_ok[0:0] 1'1 + case + assign $1\cr_bitfield_b_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_b_ok $0\cr_bitfield_b_ok[0:0] + end + attribute \src "libresoc.v:126874.3-126884.6" + process $proc$libresoc.v:126874$4825 + assign { } { } + assign { } { } + assign $0\cr_bitfield_o_ok[0:0] $1\cr_bitfield_o_ok[0:0] + attribute \src "libresoc.v:126875.5-126875.29" + switch \initial + attribute \src "libresoc.v:126875.9-126875.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_o_ok[0:0] 1'1 + case + assign $1\cr_bitfield_o_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_o_ok $0\cr_bitfield_o_ok[0:0] + end + attribute \src "libresoc.v:126885.3-126895.6" + process $proc$libresoc.v:126885$4826 + assign { } { } + assign { } { } + assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] + attribute \src "libresoc.v:126886.5-126886.29" + switch \initial + attribute \src "libresoc.v:126886.9-126886.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'110 + assign { } { } + assign $1\cr_fxm_ok[0:0] 1'1 + case + assign $1\cr_fxm_ok[0:0] 1'0 + end + sync always + update \cr_fxm_ok $0\cr_fxm_ok[0:0] + end + attribute \src "libresoc.v:126896.3-126922.6" + process $proc$libresoc.v:126896$4827 + assign { } { } + assign { } { } + assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] + attribute \src "libresoc.v:126897.5-126897.29" + switch \initial + attribute \src "libresoc.v:126897.9-126897.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\cr_bitfield[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\cr_bitfield[2:0] \BRANCH_BI [4:2] + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\cr_bitfield[2:0] \X_BFA + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield[2:0] \BRANCH_BA [4:2] + attribute \src "libresoc.v:0.0-0.0" + case 3'101 + assign { } { } + assign $1\cr_bitfield[2:0] \BRANCH_BC [4:2] + case + assign $1\cr_bitfield[2:0] 3'000 + end + sync always + update \cr_bitfield $0\cr_bitfield[2:0] + end + attribute \src "libresoc.v:126923.3-126933.6" + process $proc$libresoc.v:126923$4828 + assign { } { } + assign { } { } + assign $0\cr_bitfield_b[2:0] $1\cr_bitfield_b[2:0] + attribute \src "libresoc.v:126924.5-126924.29" + switch \initial + attribute \src "libresoc.v:126924.9-126924.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_b[2:0] \BRANCH_BB [4:2] + case + assign $1\cr_bitfield_b[2:0] 3'000 + end + sync always + update \cr_bitfield_b $0\cr_bitfield_b[2:0] + end + attribute \src "libresoc.v:126934.3-126944.6" + process $proc$libresoc.v:126934$4829 + assign { } { } + assign { } { } + assign $0\cr_bitfield_o[2:0] $1\cr_bitfield_o[2:0] + attribute \src "libresoc.v:126935.5-126935.29" + switch \initial + attribute \src "libresoc.v:126935.9-126935.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_o[2:0] \BRANCH_BT [4:2] + case + assign $1\cr_bitfield_o[2:0] 3'000 + end + sync always + update \cr_bitfield_o $0\cr_bitfield_o[2:0] + end + attribute \src "libresoc.v:126945.3-126955.6" + process $proc$libresoc.v:126945$4830 + assign { } { } + assign { } { } + assign $0\move_one[0:0] $1\move_one[0:0] + attribute \src "libresoc.v:126946.5-126946.29" + switch \initial + attribute \src "libresoc.v:126946.9-126946.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'110 + assign { } { } + assign $1\move_one[0:0] \insn_in [20] + case + assign $1\move_one[0:0] 1'0 + end + sync always + update \move_one $0\move_one[0:0] + end + attribute \src "libresoc.v:126956.3-126971.6" + process $proc$libresoc.v:126956$4831 + assign { } { } + assign { } { } + assign $0\ppick_i[7:0] $1\ppick_i[7:0] + attribute \src "libresoc.v:126957.5-126957.29" + switch \initial + attribute \src "libresoc.v:126957.9-126957.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'110 + assign { } { } + assign $1\ppick_i[7:0] $2\ppick_i[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ppick_i[7:0] \BRANCH_FXM + case + assign $2\ppick_i[7:0] 8'00000000 + end + case + assign $1\ppick_i[7:0] 8'00000000 + end + sync always + update \ppick_i $0\ppick_i[7:0] + end + attribute \src "libresoc.v:126972.3-126990.6" + process $proc$libresoc.v:126972$4832 + assign { } { } + assign { } { } + assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] + attribute \src "libresoc.v:126973.5-126973.29" + switch \initial + attribute \src "libresoc.v:126973.9-126973.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'110 + assign { } { } + assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" + switch \$7 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign 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$1\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:127274.3-127292.6" + wire width 8 $1\cr_fxm[7:0] + attribute \src "libresoc.v:127187.3-127197.6" + wire $1\cr_fxm_ok[0:0] + attribute \src "libresoc.v:127247.3-127257.6" + wire $1\move_one[0:0] + attribute \src "libresoc.v:127258.3-127273.6" + wire width 8 $1\ppick_i[7:0] + attribute \src "libresoc.v:127274.3-127292.6" + wire width 8 $2\cr_fxm[7:0] + attribute \src "libresoc.v:127258.3-127273.6" + wire width 8 $2\ppick_i[7:0] + attribute \src "libresoc.v:127131.17-127131.112" + wire $and$libresoc.v:127131$4835_Y + attribute \src "libresoc.v:127133.17-127133.112" + wire $and$libresoc.v:127133$4837_Y + attribute \src "libresoc.v:127130.17-127130.125" + wire $eq$libresoc.v:127130$4834_Y + attribute \src "libresoc.v:127132.17-127132.125" + wire $eq$libresoc.v:127132$4836_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 input 4 \LOGICAL_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 input 3 \LOGICAL_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 input 8 \LOGICAL_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 input 7 \LOGICAL_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 input 5 \LOGICAL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 8 input 6 \LOGICAL_FXM + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 input 2 \LOGICAL_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 3 input 9 \X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 \cr_bitfield + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 \cr_bitfield_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_bitfield_b_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 \cr_bitfield_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_bitfield_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_bitfield_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 8 \cr_fxm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_fxm_ok + attribute \src "libresoc.v:126996.7-126996.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:651" + wire width 32 input 10 \insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:695" + wire \move_one + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 8 \ppick_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" + wire width 8 \ppick_o + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:650" + wire width 3 input 1 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" + cell $and $and$libresoc.v:127131$4835 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$1 + connect \B \move_one + connect \Y $and$libresoc.v:127131$4835_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" + cell $and $and$libresoc.v:127133$4837 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$5 + connect \B \move_one + connect \Y $and$libresoc.v:127133$4837_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" + cell $eq $eq$libresoc.v:127130$4834 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \LOGICAL_internal_op + connect \B 7'0101101 + connect \Y $eq$libresoc.v:127130$4834_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" + cell $eq $eq$libresoc.v:127132$4836 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \LOGICAL_internal_op + connect \B 7'0101101 + connect \Y $eq$libresoc.v:127132$4836_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:127134.15-127137.4" + cell \ppick$158 \ppick + connect \i \ppick_i + connect \o \ppick_o + end + attribute \src "libresoc.v:126996.7-126996.20" + process $proc$libresoc.v:126996$4848 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:127138.3-127164.6" + process $proc$libresoc.v:127138$4838 + assign { } { } + assign { } { } + assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:127139.5-127139.29" + switch \initial + attribute \src "libresoc.v:127139.9-127139.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 3'101 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + case + assign $1\cr_bitfield_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] + end + attribute \src "libresoc.v:127165.3-127175.6" + process $proc$libresoc.v:127165$4839 + assign { } { } + assign { } { } + assign $0\cr_bitfield_b_ok[0:0] $1\cr_bitfield_b_ok[0:0] + attribute \src "libresoc.v:127166.5-127166.29" + switch \initial + attribute \src "libresoc.v:127166.9-127166.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_b_ok[0:0] 1'1 + case + assign $1\cr_bitfield_b_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_b_ok $0\cr_bitfield_b_ok[0:0] + end + attribute \src "libresoc.v:127176.3-127186.6" + process $proc$libresoc.v:127176$4840 + assign { } { } + assign { } { } + assign $0\cr_bitfield_o_ok[0:0] $1\cr_bitfield_o_ok[0:0] + attribute \src "libresoc.v:127177.5-127177.29" + switch \initial + attribute \src "libresoc.v:127177.9-127177.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_o_ok[0:0] 1'1 + case + assign $1\cr_bitfield_o_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_o_ok $0\cr_bitfield_o_ok[0:0] + end + attribute \src "libresoc.v:127187.3-127197.6" + process $proc$libresoc.v:127187$4841 + assign { } { } + assign { } { } + assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] + attribute \src "libresoc.v:127188.5-127188.29" + switch \initial + attribute \src "libresoc.v:127188.9-127188.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'110 + assign { } { } + assign $1\cr_fxm_ok[0:0] 1'1 + case + assign $1\cr_fxm_ok[0:0] 1'0 + end + sync always + update \cr_fxm_ok $0\cr_fxm_ok[0:0] + end + attribute \src "libresoc.v:127198.3-127224.6" + process $proc$libresoc.v:127198$4842 + assign { } { } + assign { } { } + assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] + attribute \src "libresoc.v:127199.5-127199.29" + switch \initial + attribute \src "libresoc.v:127199.9-127199.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\cr_bitfield[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\cr_bitfield[2:0] \LOGICAL_BI [4:2] + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\cr_bitfield[2:0] \X_BFA + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield[2:0] \LOGICAL_BA [4:2] + attribute \src "libresoc.v:0.0-0.0" + case 3'101 + assign { } { } + assign $1\cr_bitfield[2:0] \LOGICAL_BC [4:2] + case + assign $1\cr_bitfield[2:0] 3'000 + end + sync always + update \cr_bitfield $0\cr_bitfield[2:0] + end + attribute \src "libresoc.v:127225.3-127235.6" + process $proc$libresoc.v:127225$4843 + assign { } { } + assign { } { } + assign $0\cr_bitfield_b[2:0] $1\cr_bitfield_b[2:0] + attribute \src "libresoc.v:127226.5-127226.29" + switch \initial + attribute \src "libresoc.v:127226.9-127226.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_b[2:0] \LOGICAL_BB [4:2] + case + assign $1\cr_bitfield_b[2:0] 3'000 + end + sync always + update \cr_bitfield_b $0\cr_bitfield_b[2:0] + end + attribute \src "libresoc.v:127236.3-127246.6" + process $proc$libresoc.v:127236$4844 + assign { } { } + assign { } { } + assign $0\cr_bitfield_o[2:0] $1\cr_bitfield_o[2:0] + attribute \src "libresoc.v:127237.5-127237.29" + switch \initial + attribute \src "libresoc.v:127237.9-127237.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_o[2:0] \LOGICAL_BT [4:2] + case + assign $1\cr_bitfield_o[2:0] 3'000 + end + sync always + update \cr_bitfield_o $0\cr_bitfield_o[2:0] + end + attribute \src "libresoc.v:127247.3-127257.6" + process $proc$libresoc.v:127247$4845 + assign { } { } + assign { } { } + assign $0\move_one[0:0] $1\move_one[0:0] + attribute \src "libresoc.v:127248.5-127248.29" + switch \initial + attribute \src "libresoc.v:127248.9-127248.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'110 + assign { } { } + assign $1\move_one[0:0] \insn_in [20] + case + assign $1\move_one[0:0] 1'0 + end + sync always + update \move_one $0\move_one[0:0] + end + attribute \src "libresoc.v:127258.3-127273.6" + process $proc$libresoc.v:127258$4846 + assign { } { } + assign { } { } + assign $0\ppick_i[7:0] $1\ppick_i[7:0] + attribute \src "libresoc.v:127259.5-127259.29" + switch \initial + attribute \src "libresoc.v:127259.9-127259.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'110 + assign { } { } + assign $1\ppick_i[7:0] $2\ppick_i[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ppick_i[7:0] \LOGICAL_FXM + case + assign $2\ppick_i[7:0] 8'00000000 + end + case + assign $1\ppick_i[7:0] 8'00000000 + end + sync always + update \ppick_i $0\ppick_i[7:0] + end + attribute \src "libresoc.v:127274.3-127292.6" + process $proc$libresoc.v:127274$4847 + assign { } { } + assign { } { } + assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] + attribute \src "libresoc.v:127275.5-127275.29" + switch \initial + attribute \src "libresoc.v:127275.9-127275.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'110 + assign { } { } + assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" + switch \$7 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_fxm[7:0] \ppick_o + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cr_fxm[7:0] 8'11111111 + end + case + assign $1\cr_fxm[7:0] 8'00000000 + end + sync always + update \cr_fxm $0\cr_fxm[7:0] + end + connect \$1 $eq$libresoc.v:127130$4834_Y + connect \$3 $and$libresoc.v:127131$4835_Y + connect \$5 $eq$libresoc.v:127132$4836_Y + connect \$7 $and$libresoc.v:127133$4837_Y +end +attribute \src "libresoc.v:127297.1-127595.10" +attribute \cells_not_processed 1 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$and$libresoc.v:127433$4850_Y + attribute \src "libresoc.v:127435.17-127435.112" + wire $and$libresoc.v:127435$4852_Y + attribute \src "libresoc.v:127432.17-127432.121" + wire $eq$libresoc.v:127432$4849_Y + attribute \src "libresoc.v:127434.17-127434.121" + wire $eq$libresoc.v:127434$4851_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 input 4 \SPR_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 input 3 \SPR_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 input 8 \SPR_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 input 7 \SPR_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 input 5 \SPR_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 8 input 6 \SPR_FXM + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 input 2 \SPR_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 3 input 9 \X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 \cr_bitfield + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 \cr_bitfield_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_bitfield_b_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 \cr_bitfield_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_bitfield_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_bitfield_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 8 \cr_fxm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_fxm_ok + attribute \src "libresoc.v:127298.7-127298.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:651" + wire width 32 input 10 \insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:695" + wire \move_one + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 8 \ppick_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" + wire width 8 \ppick_o + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:650" + wire width 3 input 1 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" + cell $and $and$libresoc.v:127433$4850 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$1 + connect \B \move_one + connect \Y $and$libresoc.v:127433$4850_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" + cell $and $and$libresoc.v:127435$4852 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$5 + connect \B \move_one + connect \Y $and$libresoc.v:127435$4852_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" + cell $eq $eq$libresoc.v:127432$4849 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \SPR_internal_op + connect \B 7'0101101 + connect \Y $eq$libresoc.v:127432$4849_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" + cell $eq $eq$libresoc.v:127434$4851 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \SPR_internal_op + connect \B 7'0101101 + connect \Y $eq$libresoc.v:127434$4851_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:127436.15-127439.4" + cell \ppick$167 \ppick + connect \i \ppick_i + connect \o \ppick_o + end + attribute \src "libresoc.v:127298.7-127298.20" + process $proc$libresoc.v:127298$4863 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:127440.3-127466.6" + process $proc$libresoc.v:127440$4853 + assign { } { } + assign { } { } + assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:127441.5-127441.29" + switch \initial + attribute \src "libresoc.v:127441.9-127441.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 3'101 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + case + assign $1\cr_bitfield_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] + end + attribute \src "libresoc.v:127467.3-127477.6" + process $proc$libresoc.v:127467$4854 + assign { } { } + assign { } { } + assign $0\cr_bitfield_b_ok[0:0] $1\cr_bitfield_b_ok[0:0] + attribute \src "libresoc.v:127468.5-127468.29" + switch \initial + attribute \src "libresoc.v:127468.9-127468.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_b_ok[0:0] 1'1 + case + assign $1\cr_bitfield_b_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_b_ok $0\cr_bitfield_b_ok[0:0] + end + attribute \src "libresoc.v:127478.3-127488.6" + process $proc$libresoc.v:127478$4855 + assign { } { } + assign { } { } + assign $0\cr_bitfield_o_ok[0:0] $1\cr_bitfield_o_ok[0:0] + attribute \src "libresoc.v:127479.5-127479.29" + switch \initial + attribute \src "libresoc.v:127479.9-127479.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_o_ok[0:0] 1'1 + case + assign $1\cr_bitfield_o_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_o_ok $0\cr_bitfield_o_ok[0:0] + end + attribute \src "libresoc.v:127489.3-127499.6" + process $proc$libresoc.v:127489$4856 + assign { } { } + assign { } { } + assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] + attribute \src "libresoc.v:127490.5-127490.29" + switch \initial + attribute \src "libresoc.v:127490.9-127490.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'110 + assign { } { } + assign $1\cr_fxm_ok[0:0] 1'1 + case + assign $1\cr_fxm_ok[0:0] 1'0 + end + sync always + update \cr_fxm_ok $0\cr_fxm_ok[0:0] + end + attribute \src "libresoc.v:127500.3-127526.6" + process $proc$libresoc.v:127500$4857 + assign { } { } + assign { } { } + assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] + attribute \src "libresoc.v:127501.5-127501.29" + switch \initial + attribute \src "libresoc.v:127501.9-127501.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\cr_bitfield[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\cr_bitfield[2:0] \SPR_BI [4:2] + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\cr_bitfield[2:0] \X_BFA + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield[2:0] \SPR_BA [4:2] + attribute \src "libresoc.v:0.0-0.0" + case 3'101 + assign { } { } + assign $1\cr_bitfield[2:0] \SPR_BC [4:2] + case + assign $1\cr_bitfield[2:0] 3'000 + end + sync always + update \cr_bitfield $0\cr_bitfield[2:0] + end + attribute \src "libresoc.v:127527.3-127537.6" + process $proc$libresoc.v:127527$4858 + assign { } { } + assign { } { } + assign $0\cr_bitfield_b[2:0] $1\cr_bitfield_b[2:0] + attribute \src "libresoc.v:127528.5-127528.29" + switch \initial + attribute \src "libresoc.v:127528.9-127528.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_b[2:0] \SPR_BB [4:2] + case + assign $1\cr_bitfield_b[2:0] 3'000 + end + sync always + update \cr_bitfield_b $0\cr_bitfield_b[2:0] + end + attribute \src "libresoc.v:127538.3-127548.6" + process $proc$libresoc.v:127538$4859 + assign { } { } + assign { } { } + assign $0\cr_bitfield_o[2:0] $1\cr_bitfield_o[2:0] + attribute \src "libresoc.v:127539.5-127539.29" + switch \initial + attribute \src "libresoc.v:127539.9-127539.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_o[2:0] \SPR_BT [4:2] + case + assign $1\cr_bitfield_o[2:0] 3'000 + end + sync always + update \cr_bitfield_o $0\cr_bitfield_o[2:0] + end + attribute \src "libresoc.v:127549.3-127559.6" + process $proc$libresoc.v:127549$4860 + assign { } { } + assign { } { } + assign $0\move_one[0:0] $1\move_one[0:0] + attribute \src "libresoc.v:127550.5-127550.29" + switch \initial + attribute \src "libresoc.v:127550.9-127550.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'110 + assign { } { } + assign $1\move_one[0:0] \insn_in [20] + case + assign $1\move_one[0:0] 1'0 + end + sync always + update \move_one $0\move_one[0:0] + end + attribute \src "libresoc.v:127560.3-127575.6" + process $proc$libresoc.v:127560$4861 + assign { } { } + assign { } { } + assign $0\ppick_i[7:0] $1\ppick_i[7:0] + attribute \src "libresoc.v:127561.5-127561.29" + switch \initial + attribute \src "libresoc.v:127561.9-127561.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'110 + assign { } { } + assign $1\ppick_i[7:0] $2\ppick_i[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ppick_i[7:0] \SPR_FXM + case + assign $2\ppick_i[7:0] 8'00000000 + end + case + assign $1\ppick_i[7:0] 8'00000000 + end + sync always + update \ppick_i $0\ppick_i[7:0] + end + attribute \src "libresoc.v:127576.3-127594.6" + process $proc$libresoc.v:127576$4862 + assign { } { } + assign { } { } + assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] + attribute \src "libresoc.v:127577.5-127577.29" + switch \initial + attribute \src "libresoc.v:127577.9-127577.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'110 + assign { } { } + assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" + switch \$7 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_fxm[7:0] \ppick_o + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cr_fxm[7:0] 8'11111111 + end + case + assign $1\cr_fxm[7:0] 8'00000000 + end + sync always + update \cr_fxm $0\cr_fxm[7:0] + end + connect \$1 $eq$libresoc.v:127432$4849_Y + connect \$3 $and$libresoc.v:127433$4850_Y + connect \$5 $eq$libresoc.v:127434$4851_Y + connect \$7 $and$libresoc.v:127435$4852_Y +end +attribute \src "libresoc.v:127599.1-127897.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_DIV.dec_cr_in" +attribute \generator "nMigen" +module \dec_cr_in$173 + attribute \src "libresoc.v:127802.3-127828.6" + wire width 3 $0\cr_bitfield[2:0] + attribute \src "libresoc.v:127829.3-127839.6" + wire width 3 $0\cr_bitfield_b[2:0] + attribute \src "libresoc.v:127769.3-127779.6" + wire $0\cr_bitfield_b_ok[0:0] + attribute \src "libresoc.v:127840.3-127850.6" + wire width 3 $0\cr_bitfield_o[2:0] + attribute \src "libresoc.v:127780.3-127790.6" + wire $0\cr_bitfield_o_ok[0:0] + attribute \src "libresoc.v:127742.3-127768.6" + wire $0\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:127878.3-127896.6" + wire width 8 $0\cr_fxm[7:0] + attribute \src "libresoc.v:127791.3-127801.6" + wire $0\cr_fxm_ok[0:0] + attribute \src "libresoc.v:127600.7-127600.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:127851.3-127861.6" + wire $0\move_one[0:0] + attribute \src "libresoc.v:127862.3-127877.6" + wire width 8 $0\ppick_i[7:0] + attribute \src "libresoc.v:127802.3-127828.6" + wire width 3 $1\cr_bitfield[2:0] + attribute \src "libresoc.v:127829.3-127839.6" + wire width 3 $1\cr_bitfield_b[2:0] + attribute \src "libresoc.v:127769.3-127779.6" + wire $1\cr_bitfield_b_ok[0:0] + attribute \src "libresoc.v:127840.3-127850.6" + wire width 3 $1\cr_bitfield_o[2:0] + attribute \src "libresoc.v:127780.3-127790.6" + wire $1\cr_bitfield_o_ok[0:0] + attribute \src "libresoc.v:127742.3-127768.6" + wire $1\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:127878.3-127896.6" + wire width 8 $1\cr_fxm[7:0] + attribute \src "libresoc.v:127791.3-127801.6" + wire $1\cr_fxm_ok[0:0] + attribute \src "libresoc.v:127851.3-127861.6" + wire $1\move_one[0:0] + attribute \src "libresoc.v:127862.3-127877.6" + wire width 8 $1\ppick_i[7:0] + attribute \src "libresoc.v:127878.3-127896.6" + wire width 8 $2\cr_fxm[7:0] + attribute \src "libresoc.v:127862.3-127877.6" + wire width 8 $2\ppick_i[7:0] + attribute \src "libresoc.v:127735.17-127735.112" + wire $and$libresoc.v:127735$4865_Y + attribute \src "libresoc.v:127737.17-127737.112" + wire $and$libresoc.v:127737$4867_Y + attribute \src "libresoc.v:127734.17-127734.121" + wire $eq$libresoc.v:127734$4864_Y + attribute \src "libresoc.v:127736.17-127736.121" + wire $eq$libresoc.v:127736$4866_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 input 4 \DIV_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 input 3 \DIV_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 input 8 \DIV_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 input 7 \DIV_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 input 5 \DIV_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 8 input 6 \DIV_FXM + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 input 2 \DIV_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 3 input 9 \X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 \cr_bitfield + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 \cr_bitfield_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_bitfield_b_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 \cr_bitfield_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_bitfield_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_bitfield_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 8 \cr_fxm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_fxm_ok + attribute \src "libresoc.v:127600.7-127600.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:651" + wire width 32 input 10 \insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:695" + wire \move_one + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 8 \ppick_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" + wire width 8 \ppick_o + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:650" + wire width 3 input 1 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" + cell $and $and$libresoc.v:127735$4865 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$1 + connect \B \move_one + connect \Y $and$libresoc.v:127735$4865_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" + cell $and $and$libresoc.v:127737$4867 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$5 + connect \B \move_one + connect \Y $and$libresoc.v:127737$4867_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" + cell $eq $eq$libresoc.v:127734$4864 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \DIV_internal_op + connect \B 7'0101101 + connect \Y $eq$libresoc.v:127734$4864_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" + cell $eq $eq$libresoc.v:127736$4866 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \DIV_internal_op + connect \B 7'0101101 + connect \Y $eq$libresoc.v:127736$4866_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:127738.15-127741.4" + cell \ppick$174 \ppick + connect \i \ppick_i + connect \o \ppick_o + end + attribute \src "libresoc.v:127600.7-127600.20" + process $proc$libresoc.v:127600$4878 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:127742.3-127768.6" + process $proc$libresoc.v:127742$4868 + assign { } { } + assign { } { } + assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:127743.5-127743.29" + switch \initial + attribute \src "libresoc.v:127743.9-127743.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 3'101 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + case + assign $1\cr_bitfield_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] + end + attribute \src "libresoc.v:127769.3-127779.6" + process $proc$libresoc.v:127769$4869 + assign { } { } + assign { } { } + assign $0\cr_bitfield_b_ok[0:0] $1\cr_bitfield_b_ok[0:0] + attribute \src "libresoc.v:127770.5-127770.29" + switch \initial + attribute \src "libresoc.v:127770.9-127770.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_b_ok[0:0] 1'1 + case + assign $1\cr_bitfield_b_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_b_ok $0\cr_bitfield_b_ok[0:0] + end + attribute \src "libresoc.v:127780.3-127790.6" + process $proc$libresoc.v:127780$4870 + assign { } { } + assign { } { } + assign $0\cr_bitfield_o_ok[0:0] $1\cr_bitfield_o_ok[0:0] + attribute \src "libresoc.v:127781.5-127781.29" + switch \initial + attribute \src "libresoc.v:127781.9-127781.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_o_ok[0:0] 1'1 + case + assign $1\cr_bitfield_o_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_o_ok $0\cr_bitfield_o_ok[0:0] + end + attribute \src "libresoc.v:127791.3-127801.6" + process $proc$libresoc.v:127791$4871 + assign { } { } + assign { } { } + assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] + attribute \src "libresoc.v:127792.5-127792.29" + switch \initial + attribute \src "libresoc.v:127792.9-127792.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'110 + assign { } { } + assign $1\cr_fxm_ok[0:0] 1'1 + case + assign $1\cr_fxm_ok[0:0] 1'0 + end + sync always + update \cr_fxm_ok $0\cr_fxm_ok[0:0] + end + attribute \src "libresoc.v:127802.3-127828.6" + process $proc$libresoc.v:127802$4872 + assign { } { } + assign { } { } + assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] + attribute \src "libresoc.v:127803.5-127803.29" + switch \initial + attribute \src "libresoc.v:127803.9-127803.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\cr_bitfield[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\cr_bitfield[2:0] \DIV_BI [4:2] + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\cr_bitfield[2:0] \X_BFA + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield[2:0] \DIV_BA [4:2] + attribute \src "libresoc.v:0.0-0.0" + case 3'101 + assign { } { } + assign $1\cr_bitfield[2:0] \DIV_BC [4:2] + case + assign $1\cr_bitfield[2:0] 3'000 + end + sync always + update \cr_bitfield $0\cr_bitfield[2:0] + end + attribute \src "libresoc.v:127829.3-127839.6" + process $proc$libresoc.v:127829$4873 + assign { } { } + assign { } { } + assign $0\cr_bitfield_b[2:0] $1\cr_bitfield_b[2:0] + attribute \src "libresoc.v:127830.5-127830.29" + switch \initial + attribute \src "libresoc.v:127830.9-127830.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_b[2:0] \DIV_BB [4:2] + case + assign $1\cr_bitfield_b[2:0] 3'000 + end + sync always + update \cr_bitfield_b $0\cr_bitfield_b[2:0] + end + attribute \src "libresoc.v:127840.3-127850.6" + process $proc$libresoc.v:127840$4874 + assign { } { } + assign { } { } + assign $0\cr_bitfield_o[2:0] $1\cr_bitfield_o[2:0] + attribute \src "libresoc.v:127841.5-127841.29" + switch \initial + attribute \src "libresoc.v:127841.9-127841.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_o[2:0] \DIV_BT [4:2] + case + assign $1\cr_bitfield_o[2:0] 3'000 + end + sync always + update \cr_bitfield_o $0\cr_bitfield_o[2:0] + end + attribute \src "libresoc.v:127851.3-127861.6" + process $proc$libresoc.v:127851$4875 + assign { } { } + assign { } { } + assign $0\move_one[0:0] $1\move_one[0:0] + attribute \src "libresoc.v:127852.5-127852.29" + switch \initial + attribute \src "libresoc.v:127852.9-127852.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'110 + assign { } { } + assign $1\move_one[0:0] \insn_in [20] + case + assign $1\move_one[0:0] 1'0 + end + sync always + update \move_one $0\move_one[0:0] + end + attribute \src "libresoc.v:127862.3-127877.6" + process $proc$libresoc.v:127862$4876 + assign { } { } + assign { } { } + assign $0\ppick_i[7:0] $1\ppick_i[7:0] + attribute \src "libresoc.v:127863.5-127863.29" + switch \initial + attribute \src "libresoc.v:127863.9-127863.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'110 + assign { } { } + assign $1\ppick_i[7:0] $2\ppick_i[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ppick_i[7:0] \DIV_FXM + case + assign $2\ppick_i[7:0] 8'00000000 + end + case + assign $1\ppick_i[7:0] 8'00000000 + end + sync always + update \ppick_i $0\ppick_i[7:0] + end + attribute \src "libresoc.v:127878.3-127896.6" + process $proc$libresoc.v:127878$4877 + assign { } { } + assign { } { } + assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] + attribute \src "libresoc.v:127879.5-127879.29" + switch \initial + attribute \src "libresoc.v:127879.9-127879.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'110 + assign { } { } + assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" + switch \$7 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_fxm[7:0] \ppick_o + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cr_fxm[7:0] 8'11111111 + end + case + assign $1\cr_fxm[7:0] 8'00000000 + end + sync always + update \cr_fxm $0\cr_fxm[7:0] + end + connect \$1 $eq$libresoc.v:127734$4864_Y + connect \$3 $and$libresoc.v:127735$4865_Y + connect \$5 $eq$libresoc.v:127736$4866_Y + connect \$7 $and$libresoc.v:127737$4867_Y +end +attribute \src "libresoc.v:127901.1-128199.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_MUL.dec_cr_in" +attribute \generator "nMigen" +module \dec_cr_in$182 + attribute \src "libresoc.v:128104.3-128130.6" + wire width 3 $0\cr_bitfield[2:0] + attribute \src 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$1\cr_bitfield_b_ok[0:0] + attribute \src "libresoc.v:128142.3-128152.6" + wire width 3 $1\cr_bitfield_o[2:0] + attribute \src "libresoc.v:128082.3-128092.6" + wire $1\cr_bitfield_o_ok[0:0] + attribute \src "libresoc.v:128044.3-128070.6" + wire $1\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:128180.3-128198.6" + wire width 8 $1\cr_fxm[7:0] + attribute \src "libresoc.v:128093.3-128103.6" + wire $1\cr_fxm_ok[0:0] + attribute \src "libresoc.v:128153.3-128163.6" + wire $1\move_one[0:0] + attribute \src "libresoc.v:128164.3-128179.6" + wire width 8 $1\ppick_i[7:0] + attribute \src "libresoc.v:128180.3-128198.6" + wire width 8 $2\cr_fxm[7:0] + attribute \src "libresoc.v:128164.3-128179.6" + wire width 8 $2\ppick_i[7:0] + attribute \src "libresoc.v:128037.17-128037.112" + wire $and$libresoc.v:128037$4880_Y + attribute \src "libresoc.v:128039.17-128039.112" + wire $and$libresoc.v:128039$4882_Y + attribute \src "libresoc.v:128036.17-128036.121" + wire $eq$libresoc.v:128036$4879_Y + attribute \src "libresoc.v:128038.17-128038.121" + wire $eq$libresoc.v:128038$4881_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 input 4 \MUL_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 input 3 \MUL_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 input 8 \MUL_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 input 7 \MUL_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 input 5 \MUL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 8 input 6 \MUL_FXM + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 input 2 \MUL_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 3 input 9 \X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 \cr_bitfield + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 \cr_bitfield_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_bitfield_b_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 \cr_bitfield_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_bitfield_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_bitfield_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 8 \cr_fxm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_fxm_ok + attribute \src "libresoc.v:127902.7-127902.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:651" + wire width 32 input 10 \insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:695" + wire \move_one + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 8 \ppick_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" + wire width 8 \ppick_o + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:650" + wire width 3 input 1 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" + cell $and $and$libresoc.v:128037$4880 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$1 + connect \B \move_one + connect \Y $and$libresoc.v:128037$4880_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" + cell $and $and$libresoc.v:128039$4882 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$5 + connect \B \move_one + connect \Y $and$libresoc.v:128039$4882_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" + cell $eq $eq$libresoc.v:128036$4879 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \MUL_internal_op + connect \B 7'0101101 + connect \Y $eq$libresoc.v:128036$4879_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" + cell $eq $eq$libresoc.v:128038$4881 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \MUL_internal_op + connect \B 7'0101101 + connect \Y $eq$libresoc.v:128038$4881_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:128040.15-128043.4" + cell \ppick$183 \ppick + connect \i \ppick_i + connect \o \ppick_o + end + attribute \src "libresoc.v:127902.7-127902.20" + process $proc$libresoc.v:127902$4893 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:128044.3-128070.6" + process $proc$libresoc.v:128044$4883 + assign { } { } + assign { } { } + assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:128045.5-128045.29" + switch \initial + attribute \src "libresoc.v:128045.9-128045.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 3'101 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + case + assign $1\cr_bitfield_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] + end + attribute \src "libresoc.v:128071.3-128081.6" + process $proc$libresoc.v:128071$4884 + assign { } { } + assign { } { } + assign $0\cr_bitfield_b_ok[0:0] $1\cr_bitfield_b_ok[0:0] + attribute \src "libresoc.v:128072.5-128072.29" + switch \initial + attribute \src "libresoc.v:128072.9-128072.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_b_ok[0:0] 1'1 + case + assign $1\cr_bitfield_b_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_b_ok $0\cr_bitfield_b_ok[0:0] + end + attribute \src "libresoc.v:128082.3-128092.6" + process $proc$libresoc.v:128082$4885 + assign { } { } + assign { } { } + assign $0\cr_bitfield_o_ok[0:0] $1\cr_bitfield_o_ok[0:0] + attribute \src "libresoc.v:128083.5-128083.29" + switch \initial + attribute \src "libresoc.v:128083.9-128083.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_o_ok[0:0] 1'1 + case + assign $1\cr_bitfield_o_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_o_ok $0\cr_bitfield_o_ok[0:0] + end + attribute \src "libresoc.v:128093.3-128103.6" + process $proc$libresoc.v:128093$4886 + assign { } { } + assign { } { } + assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] + attribute \src "libresoc.v:128094.5-128094.29" + switch \initial + attribute \src "libresoc.v:128094.9-128094.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'110 + assign { } { } + assign $1\cr_fxm_ok[0:0] 1'1 + case + assign $1\cr_fxm_ok[0:0] 1'0 + end + sync always + update \cr_fxm_ok $0\cr_fxm_ok[0:0] + end + attribute \src "libresoc.v:128104.3-128130.6" + process $proc$libresoc.v:128104$4887 + assign { } { } + assign { } { } + assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] + attribute \src "libresoc.v:128105.5-128105.29" + switch \initial + attribute \src "libresoc.v:128105.9-128105.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\cr_bitfield[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\cr_bitfield[2:0] \MUL_BI [4:2] + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\cr_bitfield[2:0] \X_BFA + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield[2:0] \MUL_BA [4:2] + attribute \src "libresoc.v:0.0-0.0" + case 3'101 + assign { } { } + assign $1\cr_bitfield[2:0] \MUL_BC [4:2] + case + assign $1\cr_bitfield[2:0] 3'000 + end + sync always + update \cr_bitfield $0\cr_bitfield[2:0] + end + attribute \src "libresoc.v:128131.3-128141.6" + process $proc$libresoc.v:128131$4888 + assign { } { } + assign { } { } + assign $0\cr_bitfield_b[2:0] $1\cr_bitfield_b[2:0] + attribute \src "libresoc.v:128132.5-128132.29" + switch \initial + attribute \src "libresoc.v:128132.9-128132.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_b[2:0] \MUL_BB [4:2] + case + assign $1\cr_bitfield_b[2:0] 3'000 + end + sync always + update \cr_bitfield_b $0\cr_bitfield_b[2:0] + end + attribute \src "libresoc.v:128142.3-128152.6" + process $proc$libresoc.v:128142$4889 + assign { } { } + assign { } { } + assign $0\cr_bitfield_o[2:0] $1\cr_bitfield_o[2:0] + attribute \src "libresoc.v:128143.5-128143.29" + switch \initial + attribute \src "libresoc.v:128143.9-128143.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_o[2:0] \MUL_BT [4:2] + case + assign $1\cr_bitfield_o[2:0] 3'000 + end + sync always + update \cr_bitfield_o $0\cr_bitfield_o[2:0] + end + attribute \src "libresoc.v:128153.3-128163.6" + process $proc$libresoc.v:128153$4890 + assign { } { } + assign { } { } + assign $0\move_one[0:0] $1\move_one[0:0] + attribute \src "libresoc.v:128154.5-128154.29" + switch \initial + attribute \src "libresoc.v:128154.9-128154.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'110 + assign { } { } + assign $1\move_one[0:0] \insn_in [20] + case + assign $1\move_one[0:0] 1'0 + end + sync always + update \move_one $0\move_one[0:0] + end + attribute \src "libresoc.v:128164.3-128179.6" + process $proc$libresoc.v:128164$4891 + assign { } { } + assign { } { } + assign $0\ppick_i[7:0] $1\ppick_i[7:0] + attribute \src "libresoc.v:128165.5-128165.29" + switch \initial + attribute \src "libresoc.v:128165.9-128165.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'110 + assign { } { } + assign $1\ppick_i[7:0] $2\ppick_i[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ppick_i[7:0] \MUL_FXM + case + assign $2\ppick_i[7:0] 8'00000000 + end + case + assign $1\ppick_i[7:0] 8'00000000 + end + sync always + update \ppick_i $0\ppick_i[7:0] + end + attribute \src "libresoc.v:128180.3-128198.6" + process $proc$libresoc.v:128180$4892 + assign { } { } + assign { } { } + assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] + attribute \src "libresoc.v:128181.5-128181.29" + switch \initial + attribute \src "libresoc.v:128181.9-128181.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'110 + assign { } { } + assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" + switch \$7 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_fxm[7:0] \ppick_o + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cr_fxm[7:0] 8'11111111 + end + case + assign $1\cr_fxm[7:0] 8'00000000 + end + sync always + update \cr_fxm $0\cr_fxm[7:0] + end + connect \$1 $eq$libresoc.v:128036$4879_Y + connect \$3 $and$libresoc.v:128037$4880_Y + connect \$5 $eq$libresoc.v:128038$4881_Y + connect \$7 $and$libresoc.v:128039$4882_Y +end +attribute \src "libresoc.v:128203.1-128501.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SHIFT_ROT.dec_cr_in" +attribute \generator "nMigen" +module \dec_cr_in$190 + attribute \src "libresoc.v:128406.3-128432.6" + wire width 3 $0\cr_bitfield[2:0] + attribute \src "libresoc.v:128433.3-128443.6" + wire width 3 $0\cr_bitfield_b[2:0] + attribute \src "libresoc.v:128373.3-128383.6" + wire $0\cr_bitfield_b_ok[0:0] + attribute \src "libresoc.v:128444.3-128454.6" + wire width 3 $0\cr_bitfield_o[2:0] + attribute \src "libresoc.v:128384.3-128394.6" + wire $0\cr_bitfield_o_ok[0:0] + attribute \src "libresoc.v:128346.3-128372.6" + wire $0\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:128482.3-128500.6" + wire width 8 $0\cr_fxm[7:0] + attribute \src "libresoc.v:128395.3-128405.6" + wire $0\cr_fxm_ok[0:0] + attribute \src "libresoc.v:128204.7-128204.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:128455.3-128465.6" + wire $0\move_one[0:0] + attribute \src "libresoc.v:128466.3-128481.6" + wire width 8 $0\ppick_i[7:0] + attribute \src "libresoc.v:128406.3-128432.6" + wire width 3 $1\cr_bitfield[2:0] + attribute \src "libresoc.v:128433.3-128443.6" + wire width 3 $1\cr_bitfield_b[2:0] + attribute \src "libresoc.v:128373.3-128383.6" + wire $1\cr_bitfield_b_ok[0:0] + attribute \src "libresoc.v:128444.3-128454.6" + wire width 3 $1\cr_bitfield_o[2:0] + attribute \src "libresoc.v:128384.3-128394.6" + wire $1\cr_bitfield_o_ok[0:0] + attribute \src "libresoc.v:128346.3-128372.6" + wire $1\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:128482.3-128500.6" + wire width 8 $1\cr_fxm[7:0] + attribute \src "libresoc.v:128395.3-128405.6" + wire $1\cr_fxm_ok[0:0] + attribute \src "libresoc.v:128455.3-128465.6" + wire $1\move_one[0:0] + attribute \src "libresoc.v:128466.3-128481.6" + wire width 8 $1\ppick_i[7:0] + attribute \src "libresoc.v:128482.3-128500.6" + wire width 8 $2\cr_fxm[7:0] + attribute \src "libresoc.v:128466.3-128481.6" + wire width 8 $2\ppick_i[7:0] + attribute \src "libresoc.v:128339.17-128339.112" + wire $and$libresoc.v:128339$4895_Y + attribute \src "libresoc.v:128341.17-128341.112" + wire $and$libresoc.v:128341$4897_Y + attribute \src "libresoc.v:128338.17-128338.127" + wire $eq$libresoc.v:128338$4894_Y + attribute \src "libresoc.v:128340.17-128340.127" + wire $eq$libresoc.v:128340$4896_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 input 4 \SHIFT_ROT_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 input 3 \SHIFT_ROT_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 input 8 \SHIFT_ROT_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 input 7 \SHIFT_ROT_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 input 5 \SHIFT_ROT_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 8 input 6 \SHIFT_ROT_FXM + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 input 2 \SHIFT_ROT_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 3 input 9 \X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 \cr_bitfield + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 \cr_bitfield_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_bitfield_b_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 \cr_bitfield_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_bitfield_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_bitfield_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 8 \cr_fxm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_fxm_ok + attribute \src "libresoc.v:128204.7-128204.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:651" + wire width 32 input 10 \insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:695" + wire \move_one + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 8 \ppick_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" + wire width 8 \ppick_o + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:650" + wire width 3 input 1 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" + cell $and $and$libresoc.v:128339$4895 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$1 + connect \B \move_one + connect \Y $and$libresoc.v:128339$4895_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" + cell $and $and$libresoc.v:128341$4897 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$5 + connect \B \move_one + connect \Y $and$libresoc.v:128341$4897_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" + cell $eq $eq$libresoc.v:128338$4894 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \SHIFT_ROT_internal_op + connect \B 7'0101101 + connect \Y $eq$libresoc.v:128338$4894_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" + cell $eq $eq$libresoc.v:128340$4896 + parameter \A_SIGNED 0 + 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+ attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:650" + wire width 3 input 1 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" + cell $and $and$libresoc.v:128641$4910 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$1 + connect \B \move_one + connect \Y $and$libresoc.v:128641$4910_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" + cell $and $and$libresoc.v:128643$4912 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$5 + connect \B \move_one + connect \Y $and$libresoc.v:128643$4912_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" + cell $eq $eq$libresoc.v:128640$4909 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \LDST_internal_op + connect \B 7'0101101 + connect \Y $eq$libresoc.v:128640$4909_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" + cell $eq $eq$libresoc.v:128642$4911 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \LDST_internal_op + connect \B 7'0101101 + connect \Y $eq$libresoc.v:128642$4911_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:128644.15-128647.4" + cell \ppick$199 \ppick + connect \i \ppick_i + connect \o \ppick_o + end + attribute \src "libresoc.v:128506.7-128506.20" + process $proc$libresoc.v:128506$4923 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:128648.3-128674.6" + process $proc$libresoc.v:128648$4913 + assign { } { } + assign { } { } + assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:128649.5-128649.29" + switch \initial + attribute \src "libresoc.v:128649.9-128649.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 3'101 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + case + assign $1\cr_bitfield_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] + end + attribute \src "libresoc.v:128675.3-128685.6" + process $proc$libresoc.v:128675$4914 + assign { } { } + assign { } { } + assign $0\cr_bitfield_b_ok[0:0] $1\cr_bitfield_b_ok[0:0] + attribute \src "libresoc.v:128676.5-128676.29" + switch \initial + attribute \src "libresoc.v:128676.9-128676.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_b_ok[0:0] 1'1 + case + assign $1\cr_bitfield_b_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_b_ok $0\cr_bitfield_b_ok[0:0] + end + attribute \src "libresoc.v:128686.3-128696.6" + process $proc$libresoc.v:128686$4915 + assign { } { } + assign { } { } + assign $0\cr_bitfield_o_ok[0:0] $1\cr_bitfield_o_ok[0:0] + attribute \src "libresoc.v:128687.5-128687.29" + switch \initial + attribute \src "libresoc.v:128687.9-128687.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_o_ok[0:0] 1'1 + case + assign $1\cr_bitfield_o_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_o_ok $0\cr_bitfield_o_ok[0:0] + end + attribute \src "libresoc.v:128697.3-128707.6" + process $proc$libresoc.v:128697$4916 + assign { } { } + assign { } { } + assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] + attribute \src "libresoc.v:128698.5-128698.29" + switch \initial + attribute \src "libresoc.v:128698.9-128698.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'110 + assign { } { } + assign $1\cr_fxm_ok[0:0] 1'1 + case + assign $1\cr_fxm_ok[0:0] 1'0 + end + sync always + update \cr_fxm_ok $0\cr_fxm_ok[0:0] + end + attribute \src "libresoc.v:128708.3-128734.6" + process $proc$libresoc.v:128708$4917 + assign { } { } + assign { } { } + assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] + attribute \src "libresoc.v:128709.5-128709.29" + switch \initial + attribute \src "libresoc.v:128709.9-128709.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\cr_bitfield[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\cr_bitfield[2:0] \LDST_BI [4:2] + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\cr_bitfield[2:0] \X_BFA + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield[2:0] \LDST_BA [4:2] + attribute \src "libresoc.v:0.0-0.0" + case 3'101 + assign { } { } + assign $1\cr_bitfield[2:0] \LDST_BC [4:2] + case + assign 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"OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 input 2 \internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:695" + wire \move_one + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 8 \ppick_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" + wire width 8 \ppick_o + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \enum_value_111 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:650" + wire width 3 input 1 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" + cell $and $and$libresoc.v:128951$4925 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$1 + connect \B \move_one + connect \Y $and$libresoc.v:128951$4925_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" + cell $and $and$libresoc.v:128953$4927 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$5 + connect \B \move_one + connect \Y $and$libresoc.v:128953$4927_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" + cell $eq $eq$libresoc.v:128950$4924 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \internal_op + connect \B 7'0101101 + connect \Y $eq$libresoc.v:128950$4924_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" + cell $eq $eq$libresoc.v:128952$4926 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \internal_op + connect \B 7'0101101 + connect \Y $eq$libresoc.v:128952$4926_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:128954.15-128957.4" + cell \ppick$208 \ppick + connect \i \ppick_i + connect \o \ppick_o + end + attribute \src "libresoc.v:128808.7-128808.20" + process $proc$libresoc.v:128808$4938 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:128958.3-128984.6" + process $proc$libresoc.v:128958$4928 + assign { } { } + assign { } { } + assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:128959.5-128959.29" + switch \initial + attribute \src "libresoc.v:128959.9-128959.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 3'101 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + case + assign $1\cr_bitfield_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] + end + attribute \src "libresoc.v:128985.3-128995.6" + process $proc$libresoc.v:128985$4929 + assign { } { } + assign { } { } + assign $0\cr_bitfield_b_ok[0:0] $1\cr_bitfield_b_ok[0:0] + attribute \src "libresoc.v:128986.5-128986.29" + switch \initial + attribute \src "libresoc.v:128986.9-128986.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_b_ok[0:0] 1'1 + case + assign $1\cr_bitfield_b_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_b_ok $0\cr_bitfield_b_ok[0:0] + end + attribute \src "libresoc.v:128996.3-129006.6" + process $proc$libresoc.v:128996$4930 + assign { } { } + assign { } { } + assign $0\cr_bitfield_o_ok[0:0] $1\cr_bitfield_o_ok[0:0] + attribute \src "libresoc.v:128997.5-128997.29" + switch \initial + attribute \src "libresoc.v:128997.9-128997.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_o_ok[0:0] 1'1 + case + assign $1\cr_bitfield_o_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_o_ok $0\cr_bitfield_o_ok[0:0] + end + attribute \src "libresoc.v:129007.3-129017.6" + process $proc$libresoc.v:129007$4931 + assign { } { } + assign { } { } + assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] + attribute \src "libresoc.v:129008.5-129008.29" + switch \initial + attribute \src "libresoc.v:129008.9-129008.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'110 + assign { } { } + assign $1\cr_fxm_ok[0:0] 1'1 + case + assign $1\cr_fxm_ok[0:0] 1'0 + end + sync always + update \cr_fxm_ok $0\cr_fxm_ok[0:0] + end + attribute \src "libresoc.v:129018.3-129044.6" + process $proc$libresoc.v:129018$4932 + assign { } { } + assign { } { } + assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] + attribute \src "libresoc.v:129019.5-129019.29" + switch \initial + attribute \src "libresoc.v:129019.9-129019.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\cr_bitfield[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\cr_bitfield[2:0] \BI [4:2] + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\cr_bitfield[2:0] \X_BFA + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield[2:0] \BA [4:2] + attribute \src "libresoc.v:0.0-0.0" + case 3'101 + assign { } { } + assign $1\cr_bitfield[2:0] \BC [4:2] + case + assign $1\cr_bitfield[2:0] 3'000 + end + sync always + update \cr_bitfield $0\cr_bitfield[2:0] + end + attribute \src "libresoc.v:129045.3-129055.6" + process $proc$libresoc.v:129045$4933 + assign { } { } + assign { } { } + assign $0\cr_bitfield_b[2:0] $1\cr_bitfield_b[2:0] + attribute \src "libresoc.v:129046.5-129046.29" + switch \initial + attribute \src "libresoc.v:129046.9-129046.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_b[2:0] \BB [4:2] + case + assign $1\cr_bitfield_b[2:0] 3'000 + end + sync always + update \cr_bitfield_b $0\cr_bitfield_b[2:0] + end + attribute \src "libresoc.v:129056.3-129066.6" + process $proc$libresoc.v:129056$4934 + assign { } { } + assign { } { } + assign $0\cr_bitfield_o[2:0] $1\cr_bitfield_o[2:0] + attribute \src "libresoc.v:129057.5-129057.29" + switch \initial + attribute \src "libresoc.v:129057.9-129057.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_o[2:0] \BT [4:2] + case + assign $1\cr_bitfield_o[2:0] 3'000 + end + sync always + update \cr_bitfield_o $0\cr_bitfield_o[2:0] + end + attribute \src "libresoc.v:129067.3-129077.6" + process $proc$libresoc.v:129067$4935 + assign { } { } + assign { } { } + assign $0\move_one[0:0] $1\move_one[0:0] + attribute \src "libresoc.v:129068.5-129068.29" + switch \initial + attribute \src "libresoc.v:129068.9-129068.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'110 + assign { } { } + assign $1\move_one[0:0] \insn_in [20] + case + assign $1\move_one[0:0] 1'0 + end + sync always + update \move_one $0\move_one[0:0] + end + attribute \src "libresoc.v:129078.3-129093.6" + process $proc$libresoc.v:129078$4936 + assign { } { } + assign { } { } + assign $0\ppick_i[7:0] $1\ppick_i[7:0] + attribute \src "libresoc.v:129079.5-129079.29" + switch \initial + attribute \src "libresoc.v:129079.9-129079.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'110 + assign { } { } + assign $1\ppick_i[7:0] $2\ppick_i[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ppick_i[7:0] \FXM + case + assign $2\ppick_i[7:0] 8'00000000 + end + case + assign $1\ppick_i[7:0] 8'00000000 + end + sync always + update \ppick_i $0\ppick_i[7:0] + end + attribute \src "libresoc.v:129094.3-129112.6" + process $proc$libresoc.v:129094$4937 + assign { } { } + assign { } { } + assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] + attribute \src "libresoc.v:129095.5-129095.29" + switch \initial + attribute \src "libresoc.v:129095.9-129095.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:671" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'110 + assign { } { } + assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697" + switch \$7 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_fxm[7:0] \ppick_o + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cr_fxm[7:0] 8'11111111 + end + case + assign $1\cr_fxm[7:0] 8'00000000 + end + sync always + update \cr_fxm $0\cr_fxm[7:0] + end + connect \$1 $eq$libresoc.v:128950$4924_Y + connect \$3 $and$libresoc.v:128951$4925_Y + connect \$5 $eq$libresoc.v:128952$4926_Y + connect \$7 $and$libresoc.v:128953$4927_Y +end +attribute \src "libresoc.v:129117.1-129358.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec_cr_out" +attribute \generator "nMigen" +module \dec_cr_out + attribute \src "libresoc.v:129272.3-129290.6" + wire width 3 $0\cr_bitfield[2:0] + attribute \src "libresoc.v:129242.3-129260.6" + wire $0\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:129323.3-129357.6" + wire width 8 $0\cr_fxm[7:0] + attribute \src "libresoc.v:129261.3-129271.6" + wire $0\cr_fxm_ok[0:0] + attribute \src "libresoc.v:129118.7-129118.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:129291.3-129301.6" + wire $0\move_one[0:0] + attribute \src "libresoc.v:129302.3-129322.6" + wire width 8 $0\ppick_i[7:0] + attribute \src "libresoc.v:129272.3-129290.6" + wire width 3 $1\cr_bitfield[2:0] + attribute \src "libresoc.v:129242.3-129260.6" + wire $1\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:129323.3-129357.6" + wire width 8 $1\cr_fxm[7:0] + attribute \src "libresoc.v:129261.3-129271.6" + wire $1\cr_fxm_ok[0:0] + attribute \src "libresoc.v:129291.3-129301.6" + wire $1\move_one[0:0] + attribute \src "libresoc.v:129302.3-129322.6" + wire width 8 $1\ppick_i[7:0] + attribute \src "libresoc.v:129323.3-129357.6" + wire width 8 $2\cr_fxm[7:0] + attribute \src "libresoc.v:129302.3-129322.6" + wire width 8 $2\ppick_i[7:0] + attribute \src "libresoc.v:129323.3-129357.6" + wire width 8 $3\cr_fxm[7:0] + attribute \src "libresoc.v:129302.3-129322.6" + wire width 8 $3\ppick_i[7:0] + attribute \src "libresoc.v:129323.3-129357.6" + wire width 8 $4\cr_fxm[7:0] + attribute \src "libresoc.v:129235.17-129235.121" + wire $eq$libresoc.v:129235$4939_Y + attribute \src "libresoc.v:129236.17-129236.121" + wire $eq$libresoc.v:129236$4940_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:749" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:749" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 8 input 5 \ALU_FXM + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 input 3 \ALU_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 input 7 \XL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 3 input 6 \X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 \cr_bitfield + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 4 \cr_bitfield_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 8 \cr_fxm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_fxm_ok + attribute \src "libresoc.v:129118.7-129118.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:719" + wire width 32 input 8 \insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:747" + wire \move_one + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" + wire \ppick_en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 8 \ppick_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" + wire width 8 \ppick_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:717" + wire input 2 \rc_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:718" + wire width 3 input 1 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:749" + cell $eq $eq$libresoc.v:129235$4939 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \ALU_internal_op + connect \B 7'0110000 + connect \Y $eq$libresoc.v:129235$4939_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:749" + cell $eq $eq$libresoc.v:129236$4940 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \ALU_internal_op + connect \B 7'0110000 + connect \Y $eq$libresoc.v:129236$4940_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:129237.15-129241.4" + cell \ppick$138 \ppick + connect \en_o \ppick_en_o + connect \i \ppick_i + connect \o \ppick_o + end + attribute \src "libresoc.v:129118.7-129118.20" + process $proc$libresoc.v:129118$4947 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:129242.3-129260.6" + process $proc$libresoc.v:129242$4941 + assign { } { } + assign { } { } + assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:129243.5-129243.29" + switch \initial + attribute \src "libresoc.v:129243.9-129243.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:733" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\cr_bitfield_ok[0:0] \rc_in + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + case + assign $1\cr_bitfield_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] + end + attribute \src "libresoc.v:129261.3-129271.6" + process $proc$libresoc.v:129261$4942 + assign { } { } + assign { } { } + assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] + attribute \src "libresoc.v:129262.5-129262.29" + switch \initial + attribute \src "libresoc.v:129262.9-129262.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:733" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_fxm_ok[0:0] 1'1 + case + assign $1\cr_fxm_ok[0:0] 1'0 + end + sync always + update \cr_fxm_ok $0\cr_fxm_ok[0:0] + end + attribute \src "libresoc.v:129272.3-129290.6" + process $proc$libresoc.v:129272$4943 + assign { } { } + assign { } { } + assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] + attribute \src "libresoc.v:129273.5-129273.29" + switch \initial + attribute \src "libresoc.v:129273.9-129273.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:733" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\cr_bitfield[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\cr_bitfield[2:0] \X_BF + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\cr_bitfield[2:0] \XL_BT [4:2] + case + assign $1\cr_bitfield[2:0] 3'000 + end + sync always + update \cr_bitfield $0\cr_bitfield[2:0] + end + attribute \src "libresoc.v:129291.3-129301.6" + process $proc$libresoc.v:129291$4944 + assign { } { } + assign { } { } + assign $0\move_one[0:0] $1\move_one[0:0] + attribute \src "libresoc.v:129292.5-129292.29" + switch \initial + attribute \src "libresoc.v:129292.9-129292.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:733" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\move_one[0:0] \insn_in [20] + case + assign $1\move_one[0:0] 1'0 + end + sync always + update \move_one $0\move_one[0:0] + end + attribute \src "libresoc.v:129302.3-129322.6" + process $proc$libresoc.v:129302$4945 + assign { } { } + assign { } { } + assign $0\ppick_i[7:0] $1\ppick_i[7:0] + attribute \src "libresoc.v:129303.5-129303.29" + switch \initial + attribute \src "libresoc.v:129303.9-129303.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:733" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\ppick_i[7:0] $2\ppick_i[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:749" + switch \$1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ppick_i[7:0] $3\ppick_i[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:750" + switch \move_one + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\ppick_i[7:0] \ALU_FXM + case + assign $3\ppick_i[7:0] 8'00000000 + end + case + assign $2\ppick_i[7:0] 8'00000000 + end + case + assign $1\ppick_i[7:0] 8'00000000 + end + sync always + update \ppick_i $0\ppick_i[7:0] + end + attribute \src "libresoc.v:129323.3-129357.6" + process $proc$libresoc.v:129323$4946 + assign { } { } + assign { } { } + assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] + attribute \src "libresoc.v:129324.5-129324.29" + switch \initial + attribute \src "libresoc.v:129324.9-129324.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:733" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:749" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_fxm[7:0] $3\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:750" + switch \move_one + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\cr_fxm[7:0] $4\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:753" + switch \ppick_en_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\cr_fxm[7:0] \ppick_o + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $4\cr_fxm[7:0] 8'00000001 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $3\cr_fxm[7:0] \ALU_FXM + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cr_fxm[7:0] 8'11111111 + end + case + assign $1\cr_fxm[7:0] 8'00000000 + end + sync always + update \cr_fxm $0\cr_fxm[7:0] + end + connect \$1 $eq$libresoc.v:129235$4939_Y + connect \$3 $eq$libresoc.v:129236$4940_Y +end +attribute \src "libresoc.v:129362.1-129602.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_CR.dec_cr_out" +attribute \generator "nMigen" +module \dec_cr_out$144 + attribute \src "libresoc.v:129516.3-129534.6" + wire width 3 $0\cr_bitfield[2:0] + attribute \src "libresoc.v:129486.3-129504.6" + wire $0\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:129567.3-129601.6" + wire width 8 $0\cr_fxm[7:0] + attribute \src "libresoc.v:129505.3-129515.6" + wire $0\cr_fxm_ok[0:0] + attribute \src "libresoc.v:129363.7-129363.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:129535.3-129545.6" + wire $0\move_one[0:0] + attribute \src "libresoc.v:129546.3-129566.6" + wire width 8 $0\ppick_i[7:0] + attribute \src "libresoc.v:129516.3-129534.6" + wire width 3 $1\cr_bitfield[2:0] + attribute \src "libresoc.v:129486.3-129504.6" + wire $1\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:129567.3-129601.6" + wire width 8 $1\cr_fxm[7:0] + attribute \src "libresoc.v:129505.3-129515.6" + wire $1\cr_fxm_ok[0:0] + attribute \src "libresoc.v:129535.3-129545.6" + wire $1\move_one[0:0] + attribute \src "libresoc.v:129546.3-129566.6" + wire width 8 $1\ppick_i[7:0] + attribute \src "libresoc.v:129567.3-129601.6" + wire width 8 $2\cr_fxm[7:0] + attribute \src "libresoc.v:129546.3-129566.6" + wire width 8 $2\ppick_i[7:0] + attribute \src "libresoc.v:129567.3-129601.6" + wire width 8 $3\cr_fxm[7:0] + attribute \src "libresoc.v:129546.3-129566.6" + wire width 8 $3\ppick_i[7:0] + attribute \src "libresoc.v:129567.3-129601.6" + wire width 8 $4\cr_fxm[7:0] + attribute \src "libresoc.v:129479.17-129479.120" + wire $eq$libresoc.v:129479$4948_Y + attribute \src "libresoc.v:129480.17-129480.120" + wire $eq$libresoc.v:129480$4949_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:749" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:749" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 8 input 4 \CR_FXM + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 input 3 \CR_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 input 6 \XL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 3 input 5 \X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 \cr_bitfield + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_bitfield_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 8 \cr_fxm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_fxm_ok + attribute \src "libresoc.v:129363.7-129363.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:719" + wire width 32 input 7 \insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:747" + wire \move_one + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" + wire \ppick_en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 8 \ppick_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" + wire width 8 \ppick_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:717" + wire input 2 \rc_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:718" + wire width 3 input 1 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:749" + cell $eq $eq$libresoc.v:129479$4948 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \CR_internal_op + connect \B 7'0110000 + connect \Y $eq$libresoc.v:129479$4948_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:749" + cell $eq $eq$libresoc.v:129480$4949 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \CR_internal_op + connect \B 7'0110000 + connect \Y $eq$libresoc.v:129480$4949_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:129481.15-129485.4" + cell \ppick$145 \ppick + connect \en_o \ppick_en_o + connect \i \ppick_i + connect \o \ppick_o + end + attribute \src "libresoc.v:129363.7-129363.20" + process $proc$libresoc.v:129363$4956 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:129486.3-129504.6" + process $proc$libresoc.v:129486$4950 + assign { } { } + assign { } { } + assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:129487.5-129487.29" + switch \initial + attribute \src "libresoc.v:129487.9-129487.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:733" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\cr_bitfield_ok[0:0] \rc_in + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + case + assign $1\cr_bitfield_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] + end + attribute \src "libresoc.v:129505.3-129515.6" + process $proc$libresoc.v:129505$4951 + assign { } { } + assign { } { } + assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] + attribute \src "libresoc.v:129506.5-129506.29" + switch \initial + attribute \src "libresoc.v:129506.9-129506.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:733" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_fxm_ok[0:0] 1'1 + case + assign $1\cr_fxm_ok[0:0] 1'0 + end + sync always + update \cr_fxm_ok $0\cr_fxm_ok[0:0] + end + attribute \src "libresoc.v:129516.3-129534.6" + process $proc$libresoc.v:129516$4952 + assign { } { } + assign { } { } + assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] + attribute \src "libresoc.v:129517.5-129517.29" + switch \initial + attribute \src "libresoc.v:129517.9-129517.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:733" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\cr_bitfield[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\cr_bitfield[2:0] \X_BF + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\cr_bitfield[2:0] \XL_BT [4:2] + case + assign $1\cr_bitfield[2:0] 3'000 + end + sync always + update \cr_bitfield $0\cr_bitfield[2:0] + end + attribute \src "libresoc.v:129535.3-129545.6" + process $proc$libresoc.v:129535$4953 + assign { } { } + assign { } { } + assign $0\move_one[0:0] $1\move_one[0:0] + attribute \src "libresoc.v:129536.5-129536.29" + switch \initial + attribute \src "libresoc.v:129536.9-129536.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:733" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\move_one[0:0] \insn_in [20] + case + assign $1\move_one[0:0] 1'0 + end + sync always + update \move_one $0\move_one[0:0] + end + attribute \src "libresoc.v:129546.3-129566.6" + process $proc$libresoc.v:129546$4954 + assign { } { } + assign { } { } + assign $0\ppick_i[7:0] $1\ppick_i[7:0] + attribute \src "libresoc.v:129547.5-129547.29" + switch \initial + attribute \src "libresoc.v:129547.9-129547.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:733" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\ppick_i[7:0] $2\ppick_i[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:749" + switch \$1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ppick_i[7:0] $3\ppick_i[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:750" + switch \move_one + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\ppick_i[7:0] \CR_FXM + case + assign $3\ppick_i[7:0] 8'00000000 + end + case + assign $2\ppick_i[7:0] 8'00000000 + end + case + assign $1\ppick_i[7:0] 8'00000000 + end + sync always + update \ppick_i $0\ppick_i[7:0] + end + attribute \src "libresoc.v:129567.3-129601.6" + process $proc$libresoc.v:129567$4955 + assign { } { } + assign { } { } + assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] + attribute \src "libresoc.v:129568.5-129568.29" + switch \initial + attribute \src "libresoc.v:129568.9-129568.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:733" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:749" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_fxm[7:0] $3\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:750" + switch \move_one + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\cr_fxm[7:0] $4\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:753" + switch \ppick_en_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\cr_fxm[7:0] \ppick_o + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $4\cr_fxm[7:0] 8'00000001 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $3\cr_fxm[7:0] \CR_FXM + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cr_fxm[7:0] 8'11111111 + end + case + assign $1\cr_fxm[7:0] 8'00000000 + end + sync always + update \cr_fxm $0\cr_fxm[7:0] + end + connect \$1 $eq$libresoc.v:129479$4948_Y + connect \$3 $eq$libresoc.v:129480$4949_Y +end +attribute \src "libresoc.v:129606.1-129846.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_BRANCH.dec_cr_out" +attribute \generator "nMigen" +module \dec_cr_out$151 + attribute \src "libresoc.v:129760.3-129778.6" + wire width 3 $0\cr_bitfield[2:0] + attribute \src "libresoc.v:129730.3-129748.6" + wire $0\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:129811.3-129845.6" + wire width 8 $0\cr_fxm[7:0] + attribute \src "libresoc.v:129749.3-129759.6" + wire $0\cr_fxm_ok[0:0] + attribute \src "libresoc.v:129607.7-129607.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:129779.3-129789.6" + wire $0\move_one[0:0] + attribute \src "libresoc.v:129790.3-129810.6" + wire width 8 $0\ppick_i[7:0] + attribute \src "libresoc.v:129760.3-129778.6" + wire width 3 $1\cr_bitfield[2:0] + attribute \src "libresoc.v:129730.3-129748.6" + wire $1\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:129811.3-129845.6" + wire width 8 $1\cr_fxm[7:0] + attribute \src "libresoc.v:129749.3-129759.6" + wire $1\cr_fxm_ok[0:0] + attribute \src "libresoc.v:129779.3-129789.6" + wire $1\move_one[0:0] + attribute \src "libresoc.v:129790.3-129810.6" + wire width 8 $1\ppick_i[7:0] + attribute \src "libresoc.v:129811.3-129845.6" + wire width 8 $2\cr_fxm[7:0] + attribute \src "libresoc.v:129790.3-129810.6" + wire width 8 $2\ppick_i[7:0] + attribute \src "libresoc.v:129811.3-129845.6" + wire width 8 $3\cr_fxm[7:0] + attribute \src "libresoc.v:129790.3-129810.6" + wire width 8 $3\ppick_i[7:0] + attribute \src "libresoc.v:129811.3-129845.6" + wire width 8 $4\cr_fxm[7:0] + attribute \src "libresoc.v:129723.17-129723.124" + wire $eq$libresoc.v:129723$4957_Y + attribute \src "libresoc.v:129724.17-129724.124" + wire $eq$libresoc.v:129724$4958_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:749" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:749" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 8 input 4 \BRANCH_FXM + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 input 3 \BRANCH_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 input 6 \XL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 3 input 5 \X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 \cr_bitfield + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_bitfield_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 8 \cr_fxm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_fxm_ok + attribute \src "libresoc.v:129607.7-129607.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:719" + wire width 32 input 7 \insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:747" + wire \move_one + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" + wire \ppick_en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 8 \ppick_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" + wire width 8 \ppick_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:717" + wire input 2 \rc_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:718" + wire width 3 input 1 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:749" + cell $eq $eq$libresoc.v:129723$4957 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \BRANCH_internal_op + connect \B 7'0110000 + connect \Y $eq$libresoc.v:129723$4957_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:749" + cell $eq $eq$libresoc.v:129724$4958 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \BRANCH_internal_op + connect \B 7'0110000 + connect \Y $eq$libresoc.v:129724$4958_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:129725.15-129729.4" + cell \ppick$152 \ppick + connect \en_o \ppick_en_o + connect \i \ppick_i + connect \o \ppick_o + end + attribute \src "libresoc.v:129607.7-129607.20" + process $proc$libresoc.v:129607$4965 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:129730.3-129748.6" + process $proc$libresoc.v:129730$4959 + assign { } { } + assign { } { } + assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:129731.5-129731.29" + switch \initial + attribute \src "libresoc.v:129731.9-129731.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:733" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\cr_bitfield_ok[0:0] \rc_in + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + case + assign $1\cr_bitfield_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] + end + attribute \src "libresoc.v:129749.3-129759.6" + process $proc$libresoc.v:129749$4960 + assign { } { } + assign { } { } + assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] + attribute \src "libresoc.v:129750.5-129750.29" + switch \initial + attribute \src "libresoc.v:129750.9-129750.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:733" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_fxm_ok[0:0] 1'1 + case + assign $1\cr_fxm_ok[0:0] 1'0 + end + sync always + update \cr_fxm_ok $0\cr_fxm_ok[0:0] + end + attribute \src "libresoc.v:129760.3-129778.6" + process $proc$libresoc.v:129760$4961 + assign { } { } + assign { } { } + assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] + attribute \src "libresoc.v:129761.5-129761.29" + switch \initial + attribute \src "libresoc.v:129761.9-129761.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:733" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\cr_bitfield[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\cr_bitfield[2:0] \X_BF + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\cr_bitfield[2:0] \XL_BT [4:2] + case + assign $1\cr_bitfield[2:0] 3'000 + end + sync always + update \cr_bitfield $0\cr_bitfield[2:0] + end + attribute \src "libresoc.v:129779.3-129789.6" + process $proc$libresoc.v:129779$4962 + assign { } { } + assign { } { } + assign $0\move_one[0:0] $1\move_one[0:0] + attribute \src "libresoc.v:129780.5-129780.29" + switch \initial + attribute \src "libresoc.v:129780.9-129780.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:733" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\move_one[0:0] \insn_in [20] + case + assign $1\move_one[0:0] 1'0 + end + sync always + update \move_one $0\move_one[0:0] + end + attribute \src "libresoc.v:129790.3-129810.6" + process $proc$libresoc.v:129790$4963 + assign { } { } + assign { } { } + assign $0\ppick_i[7:0] $1\ppick_i[7:0] + attribute \src "libresoc.v:129791.5-129791.29" + switch \initial + attribute \src "libresoc.v:129791.9-129791.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:733" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\ppick_i[7:0] $2\ppick_i[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:749" + switch \$1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ppick_i[7:0] $3\ppick_i[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:750" + switch \move_one + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\ppick_i[7:0] \BRANCH_FXM + case + assign $3\ppick_i[7:0] 8'00000000 + end + case + assign $2\ppick_i[7:0] 8'00000000 + end + case + assign $1\ppick_i[7:0] 8'00000000 + end + sync always + update \ppick_i $0\ppick_i[7:0] + end + attribute \src "libresoc.v:129811.3-129845.6" + process $proc$libresoc.v:129811$4964 + assign { } { } + assign { } { } + assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] + attribute \src "libresoc.v:129812.5-129812.29" + switch \initial + attribute \src "libresoc.v:129812.9-129812.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:733" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:749" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_fxm[7:0] $3\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:750" + switch \move_one + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\cr_fxm[7:0] $4\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:753" + switch \ppick_en_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\cr_fxm[7:0] \ppick_o + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $4\cr_fxm[7:0] 8'00000001 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $3\cr_fxm[7:0] \BRANCH_FXM + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cr_fxm[7:0] 8'11111111 + end + case + assign $1\cr_fxm[7:0] 8'00000000 + end + sync always + update \cr_fxm $0\cr_fxm[7:0] + end + connect \$1 $eq$libresoc.v:129723$4957_Y + connect \$3 $eq$libresoc.v:129724$4958_Y +end +attribute \src "libresoc.v:129850.1-130091.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LOGICAL.dec_cr_out" +attribute \generator "nMigen" +module \dec_cr_out$159 + attribute \src "libresoc.v:130005.3-130023.6" + wire width 3 $0\cr_bitfield[2:0] + attribute \src "libresoc.v:129975.3-129993.6" + wire $0\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:130056.3-130090.6" + wire width 8 $0\cr_fxm[7:0] + attribute \src "libresoc.v:129994.3-130004.6" + wire $0\cr_fxm_ok[0:0] + attribute \src "libresoc.v:129851.7-129851.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:130024.3-130034.6" + wire $0\move_one[0:0] + attribute \src "libresoc.v:130035.3-130055.6" + wire width 8 $0\ppick_i[7:0] + attribute \src "libresoc.v:130005.3-130023.6" + wire width 3 $1\cr_bitfield[2:0] + attribute \src "libresoc.v:129975.3-129993.6" + wire $1\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:130056.3-130090.6" + wire width 8 $1\cr_fxm[7:0] + attribute \src "libresoc.v:129994.3-130004.6" + wire $1\cr_fxm_ok[0:0] + attribute \src "libresoc.v:130024.3-130034.6" + wire $1\move_one[0:0] + attribute \src "libresoc.v:130035.3-130055.6" + wire width 8 $1\ppick_i[7:0] + attribute \src "libresoc.v:130056.3-130090.6" + wire width 8 $2\cr_fxm[7:0] + attribute \src "libresoc.v:130035.3-130055.6" + wire width 8 $2\ppick_i[7:0] + attribute \src "libresoc.v:130056.3-130090.6" + wire width 8 $3\cr_fxm[7:0] + attribute \src "libresoc.v:130035.3-130055.6" + wire width 8 $3\ppick_i[7:0] + attribute \src "libresoc.v:130056.3-130090.6" + wire width 8 $4\cr_fxm[7:0] + attribute \src "libresoc.v:129968.17-129968.125" + wire $eq$libresoc.v:129968$4966_Y + attribute \src "libresoc.v:129969.17-129969.125" + wire $eq$libresoc.v:129969$4967_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:749" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:749" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 8 input 5 \LOGICAL_FXM + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 input 3 \LOGICAL_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 input 7 \XL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 3 input 6 \X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 \cr_bitfield + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 4 \cr_bitfield_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 8 \cr_fxm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_fxm_ok + attribute \src "libresoc.v:129851.7-129851.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:719" + wire width 32 input 8 \insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:747" + wire \move_one + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" + wire \ppick_en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 8 \ppick_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" + wire width 8 \ppick_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:717" + wire input 2 \rc_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:718" + wire width 3 input 1 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:749" + cell $eq $eq$libresoc.v:129968$4966 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \LOGICAL_internal_op + connect \B 7'0110000 + connect \Y $eq$libresoc.v:129968$4966_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:749" + cell $eq $eq$libresoc.v:129969$4967 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \LOGICAL_internal_op + connect \B 7'0110000 + connect \Y $eq$libresoc.v:129969$4967_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:129970.15-129974.4" + cell \ppick$160 \ppick + connect \en_o \ppick_en_o + connect \i \ppick_i + connect \o \ppick_o + end + attribute \src "libresoc.v:129851.7-129851.20" + process $proc$libresoc.v:129851$4974 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:129975.3-129993.6" + process $proc$libresoc.v:129975$4968 + assign { } { } + assign { } { } + assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:129976.5-129976.29" + switch \initial + attribute \src "libresoc.v:129976.9-129976.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:733" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\cr_bitfield_ok[0:0] \rc_in + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + case + assign $1\cr_bitfield_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] + end + attribute \src "libresoc.v:129994.3-130004.6" + process $proc$libresoc.v:129994$4969 + assign { } { } + assign { } { } + assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] + attribute \src "libresoc.v:129995.5-129995.29" + switch \initial + attribute \src "libresoc.v:129995.9-129995.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:733" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_fxm_ok[0:0] 1'1 + case + assign $1\cr_fxm_ok[0:0] 1'0 + end + sync always + update \cr_fxm_ok $0\cr_fxm_ok[0:0] + end + attribute \src "libresoc.v:130005.3-130023.6" + process $proc$libresoc.v:130005$4970 + assign { } { } + assign { } { } + assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] + attribute \src "libresoc.v:130006.5-130006.29" + switch \initial + attribute \src "libresoc.v:130006.9-130006.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:733" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\cr_bitfield[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\cr_bitfield[2:0] \X_BF + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\cr_bitfield[2:0] \XL_BT [4:2] + case + assign $1\cr_bitfield[2:0] 3'000 + end + sync always + update \cr_bitfield $0\cr_bitfield[2:0] + end + attribute \src "libresoc.v:130024.3-130034.6" + process $proc$libresoc.v:130024$4971 + assign { } { } + assign { } { } + assign $0\move_one[0:0] $1\move_one[0:0] + attribute \src "libresoc.v:130025.5-130025.29" + switch \initial + attribute \src "libresoc.v:130025.9-130025.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:733" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\move_one[0:0] \insn_in [20] + case + assign $1\move_one[0:0] 1'0 + end + sync always + update \move_one $0\move_one[0:0] + end + attribute \src "libresoc.v:130035.3-130055.6" + process $proc$libresoc.v:130035$4972 + assign { } { } + assign { } { } + assign $0\ppick_i[7:0] $1\ppick_i[7:0] + attribute \src "libresoc.v:130036.5-130036.29" + switch \initial + attribute \src "libresoc.v:130036.9-130036.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:733" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\ppick_i[7:0] $2\ppick_i[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:749" + switch \$1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ppick_i[7:0] $3\ppick_i[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:750" + switch \move_one + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\ppick_i[7:0] \LOGICAL_FXM + case + assign $3\ppick_i[7:0] 8'00000000 + end + case + assign $2\ppick_i[7:0] 8'00000000 + end + case + assign $1\ppick_i[7:0] 8'00000000 + end + sync always + update \ppick_i $0\ppick_i[7:0] + end + attribute \src "libresoc.v:130056.3-130090.6" + process $proc$libresoc.v:130056$4973 + assign { } { } + assign { } { } + assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] + attribute \src "libresoc.v:130057.5-130057.29" + switch \initial + attribute \src "libresoc.v:130057.9-130057.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:733" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:749" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_fxm[7:0] $3\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:750" + switch \move_one + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\cr_fxm[7:0] $4\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:753" + switch \ppick_en_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\cr_fxm[7:0] \ppick_o + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $4\cr_fxm[7:0] 8'00000001 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $3\cr_fxm[7:0] \LOGICAL_FXM + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cr_fxm[7:0] 8'11111111 + end + case + assign $1\cr_fxm[7:0] 8'00000000 + end + sync always + update \cr_fxm $0\cr_fxm[7:0] + end + connect \$1 $eq$libresoc.v:129968$4966_Y + connect \$3 $eq$libresoc.v:129969$4967_Y +end +attribute \src "libresoc.v:130095.1-130335.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SPR.dec_cr_out" +attribute \generator "nMigen" +module \dec_cr_out$168 + attribute \src "libresoc.v:130249.3-130267.6" + wire width 3 $0\cr_bitfield[2:0] + attribute \src "libresoc.v:130219.3-130237.6" + wire $0\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:130300.3-130334.6" + wire width 8 $0\cr_fxm[7:0] + attribute \src "libresoc.v:130238.3-130248.6" + wire $0\cr_fxm_ok[0:0] + attribute \src "libresoc.v:130096.7-130096.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:130268.3-130278.6" + wire $0\move_one[0:0] + attribute \src "libresoc.v:130279.3-130299.6" + wire width 8 $0\ppick_i[7:0] + attribute \src "libresoc.v:130249.3-130267.6" + wire width 3 $1\cr_bitfield[2:0] + attribute \src "libresoc.v:130219.3-130237.6" + wire $1\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:130300.3-130334.6" + wire width 8 $1\cr_fxm[7:0] + attribute \src "libresoc.v:130238.3-130248.6" + wire $1\cr_fxm_ok[0:0] + attribute \src "libresoc.v:130268.3-130278.6" + wire $1\move_one[0:0] + attribute \src "libresoc.v:130279.3-130299.6" + wire width 8 $1\ppick_i[7:0] + attribute \src "libresoc.v:130300.3-130334.6" + wire width 8 $2\cr_fxm[7:0] + attribute \src "libresoc.v:130279.3-130299.6" + wire width 8 $2\ppick_i[7:0] + attribute \src "libresoc.v:130300.3-130334.6" + wire width 8 $3\cr_fxm[7:0] + attribute \src "libresoc.v:130279.3-130299.6" + wire width 8 $3\ppick_i[7:0] + attribute \src "libresoc.v:130300.3-130334.6" + wire width 8 $4\cr_fxm[7:0] + attribute \src "libresoc.v:130212.17-130212.121" + wire $eq$libresoc.v:130212$4975_Y + attribute \src "libresoc.v:130213.17-130213.121" + wire $eq$libresoc.v:130213$4976_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:749" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:749" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 8 input 4 \SPR_FXM + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 input 3 \SPR_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 input 6 \XL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 3 input 5 \X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 \cr_bitfield + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_bitfield_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 8 \cr_fxm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_fxm_ok + attribute \src "libresoc.v:130096.7-130096.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:719" + wire width 32 input 7 \insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:747" + wire \move_one + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" + wire \ppick_en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 8 \ppick_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" + wire width 8 \ppick_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:717" + wire input 2 \rc_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:718" + wire width 3 input 1 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:749" + cell $eq $eq$libresoc.v:130212$4975 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \SPR_internal_op + connect \B 7'0110000 + connect \Y $eq$libresoc.v:130212$4975_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:749" + cell $eq $eq$libresoc.v:130213$4976 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \SPR_internal_op + connect \B 7'0110000 + connect \Y $eq$libresoc.v:130213$4976_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:130214.15-130218.4" + cell \ppick$169 \ppick + connect \en_o \ppick_en_o + connect \i \ppick_i + connect \o \ppick_o + end + attribute \src "libresoc.v:130096.7-130096.20" + process $proc$libresoc.v:130096$4983 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:130219.3-130237.6" + process $proc$libresoc.v:130219$4977 + assign { } { } + assign { } { } + assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:130220.5-130220.29" + switch \initial + attribute \src "libresoc.v:130220.9-130220.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:733" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\cr_bitfield_ok[0:0] \rc_in + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + case + assign $1\cr_bitfield_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] + end + attribute \src "libresoc.v:130238.3-130248.6" + process $proc$libresoc.v:130238$4978 + assign { } { } + assign { } { } + assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] + attribute \src "libresoc.v:130239.5-130239.29" + switch \initial + attribute \src "libresoc.v:130239.9-130239.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:733" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_fxm_ok[0:0] 1'1 + case + assign $1\cr_fxm_ok[0:0] 1'0 + end + sync always + update \cr_fxm_ok $0\cr_fxm_ok[0:0] + end + attribute \src "libresoc.v:130249.3-130267.6" + process $proc$libresoc.v:130249$4979 + assign { } { } + assign { } { } + assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] + attribute \src "libresoc.v:130250.5-130250.29" + switch \initial + attribute \src "libresoc.v:130250.9-130250.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:733" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\cr_bitfield[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\cr_bitfield[2:0] \X_BF + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\cr_bitfield[2:0] \XL_BT [4:2] + case + assign $1\cr_bitfield[2:0] 3'000 + end + sync always + update \cr_bitfield $0\cr_bitfield[2:0] + end + attribute \src "libresoc.v:130268.3-130278.6" + process $proc$libresoc.v:130268$4980 + assign { } { } + assign { } { } + assign $0\move_one[0:0] $1\move_one[0:0] + attribute \src "libresoc.v:130269.5-130269.29" + switch \initial + attribute \src "libresoc.v:130269.9-130269.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:733" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\move_one[0:0] \insn_in [20] + case + assign $1\move_one[0:0] 1'0 + end + sync always + update \move_one $0\move_one[0:0] + end + attribute \src "libresoc.v:130279.3-130299.6" + process $proc$libresoc.v:130279$4981 + assign { } { } + assign { } { } + assign $0\ppick_i[7:0] $1\ppick_i[7:0] + attribute \src "libresoc.v:130280.5-130280.29" + switch \initial + attribute \src "libresoc.v:130280.9-130280.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:733" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\ppick_i[7:0] $2\ppick_i[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:749" + switch \$1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ppick_i[7:0] $3\ppick_i[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:750" + switch \move_one + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\ppick_i[7:0] \SPR_FXM + case + assign $3\ppick_i[7:0] 8'00000000 + end + case + assign $2\ppick_i[7:0] 8'00000000 + end + case + assign $1\ppick_i[7:0] 8'00000000 + end + sync always + update \ppick_i $0\ppick_i[7:0] + end + attribute \src "libresoc.v:130300.3-130334.6" + process $proc$libresoc.v:130300$4982 + assign { } { } + assign { } { } + assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] + attribute \src "libresoc.v:130301.5-130301.29" + switch \initial + attribute \src "libresoc.v:130301.9-130301.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:733" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:749" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_fxm[7:0] $3\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:750" + switch \move_one + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\cr_fxm[7:0] $4\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:753" + switch \ppick_en_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\cr_fxm[7:0] \ppick_o + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $4\cr_fxm[7:0] 8'00000001 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $3\cr_fxm[7:0] \SPR_FXM + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cr_fxm[7:0] 8'11111111 + end + case + assign $1\cr_fxm[7:0] 8'00000000 + end + sync always + update \cr_fxm $0\cr_fxm[7:0] + end + connect \$1 $eq$libresoc.v:130212$4975_Y + connect \$3 $eq$libresoc.v:130213$4976_Y +end +attribute \src "libresoc.v:130339.1-130580.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_DIV.dec_cr_out" +attribute \generator "nMigen" +module \dec_cr_out$175 + attribute \src "libresoc.v:130494.3-130512.6" + wire width 3 $0\cr_bitfield[2:0] + attribute \src "libresoc.v:130464.3-130482.6" + wire $0\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:130545.3-130579.6" + wire width 8 $0\cr_fxm[7:0] + attribute \src "libresoc.v:130483.3-130493.6" + wire $0\cr_fxm_ok[0:0] + attribute \src "libresoc.v:130340.7-130340.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:130513.3-130523.6" + wire $0\move_one[0:0] + attribute \src "libresoc.v:130524.3-130544.6" + wire width 8 $0\ppick_i[7:0] + attribute \src "libresoc.v:130494.3-130512.6" + wire width 3 $1\cr_bitfield[2:0] + attribute \src "libresoc.v:130464.3-130482.6" + wire $1\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:130545.3-130579.6" + wire width 8 $1\cr_fxm[7:0] + attribute \src "libresoc.v:130483.3-130493.6" + wire $1\cr_fxm_ok[0:0] + attribute \src "libresoc.v:130513.3-130523.6" + wire $1\move_one[0:0] + attribute \src "libresoc.v:130524.3-130544.6" + wire width 8 $1\ppick_i[7:0] + attribute \src "libresoc.v:130545.3-130579.6" + wire width 8 $2\cr_fxm[7:0] + attribute \src "libresoc.v:130524.3-130544.6" + wire width 8 $2\ppick_i[7:0] + attribute \src "libresoc.v:130545.3-130579.6" + wire width 8 $3\cr_fxm[7:0] + attribute \src "libresoc.v:130524.3-130544.6" + wire width 8 $3\ppick_i[7:0] + attribute \src "libresoc.v:130545.3-130579.6" + wire width 8 $4\cr_fxm[7:0] + attribute \src "libresoc.v:130457.17-130457.121" + wire $eq$libresoc.v:130457$4984_Y + attribute \src "libresoc.v:130458.17-130458.121" + wire $eq$libresoc.v:130458$4985_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:749" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:749" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 8 input 5 \DIV_FXM + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 input 3 \DIV_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 input 7 \XL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 3 input 6 \X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 \cr_bitfield + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 4 \cr_bitfield_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 8 \cr_fxm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_fxm_ok + attribute \src "libresoc.v:130340.7-130340.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:719" + wire width 32 input 8 \insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:747" + wire \move_one + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" + wire \ppick_en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 8 \ppick_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" + wire width 8 \ppick_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:717" + wire input 2 \rc_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:718" + wire width 3 input 1 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:749" + cell $eq $eq$libresoc.v:130457$4984 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \DIV_internal_op + connect \B 7'0110000 + connect \Y $eq$libresoc.v:130457$4984_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:749" + cell $eq $eq$libresoc.v:130458$4985 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \DIV_internal_op + connect \B 7'0110000 + connect \Y $eq$libresoc.v:130458$4985_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:130459.15-130463.4" + cell \ppick$176 \ppick + connect \en_o \ppick_en_o + connect \i \ppick_i + connect \o \ppick_o + end + attribute \src "libresoc.v:130340.7-130340.20" + process $proc$libresoc.v:130340$4992 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:130464.3-130482.6" + process $proc$libresoc.v:130464$4986 + assign { } { } + assign { } { } + assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:130465.5-130465.29" + switch \initial + attribute \src "libresoc.v:130465.9-130465.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:733" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\cr_bitfield_ok[0:0] \rc_in + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + case + assign $1\cr_bitfield_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] + end + attribute \src "libresoc.v:130483.3-130493.6" + process $proc$libresoc.v:130483$4987 + assign { } { } + assign { } { } + assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] + attribute \src "libresoc.v:130484.5-130484.29" + switch \initial + attribute \src "libresoc.v:130484.9-130484.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:733" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_fxm_ok[0:0] 1'1 + case + assign $1\cr_fxm_ok[0:0] 1'0 + end + sync always + update \cr_fxm_ok $0\cr_fxm_ok[0:0] + end + attribute \src "libresoc.v:130494.3-130512.6" + process $proc$libresoc.v:130494$4988 + assign { } { } + assign { } { } + assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] + attribute \src "libresoc.v:130495.5-130495.29" + switch \initial + attribute \src "libresoc.v:130495.9-130495.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:733" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\cr_bitfield[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\cr_bitfield[2:0] \X_BF + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\cr_bitfield[2:0] \XL_BT [4:2] + case + assign $1\cr_bitfield[2:0] 3'000 + end + sync always + update \cr_bitfield $0\cr_bitfield[2:0] + end + attribute \src "libresoc.v:130513.3-130523.6" + process $proc$libresoc.v:130513$4989 + assign { } { } + assign { } { } + assign $0\move_one[0:0] $1\move_one[0:0] + attribute \src "libresoc.v:130514.5-130514.29" + switch \initial + attribute \src "libresoc.v:130514.9-130514.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:733" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\move_one[0:0] \insn_in [20] + case + assign $1\move_one[0:0] 1'0 + end + sync always + update \move_one $0\move_one[0:0] + end + attribute \src "libresoc.v:130524.3-130544.6" + process $proc$libresoc.v:130524$4990 + assign { } { } + assign { } { } + assign $0\ppick_i[7:0] $1\ppick_i[7:0] + attribute \src "libresoc.v:130525.5-130525.29" + switch \initial + attribute \src "libresoc.v:130525.9-130525.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:733" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\ppick_i[7:0] $2\ppick_i[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:749" + switch \$1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ppick_i[7:0] $3\ppick_i[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:750" + switch \move_one + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\ppick_i[7:0] \DIV_FXM + case + assign $3\ppick_i[7:0] 8'00000000 + end + case + assign $2\ppick_i[7:0] 8'00000000 + end + case + assign $1\ppick_i[7:0] 8'00000000 + end + sync always + update \ppick_i $0\ppick_i[7:0] + end + attribute \src "libresoc.v:130545.3-130579.6" + process $proc$libresoc.v:130545$4991 + assign { } { } + assign { } { } + assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] + attribute \src "libresoc.v:130546.5-130546.29" + switch \initial + attribute \src "libresoc.v:130546.9-130546.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:733" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:749" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_fxm[7:0] $3\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:750" + switch \move_one + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\cr_fxm[7:0] $4\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:753" + switch \ppick_en_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\cr_fxm[7:0] \ppick_o + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $4\cr_fxm[7:0] 8'00000001 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $3\cr_fxm[7:0] \DIV_FXM + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cr_fxm[7:0] 8'11111111 + end + case + assign $1\cr_fxm[7:0] 8'00000000 + end + sync always + update \cr_fxm $0\cr_fxm[7:0] + end + connect \$1 $eq$libresoc.v:130457$4984_Y + connect \$3 $eq$libresoc.v:130458$4985_Y +end +attribute \src "libresoc.v:130584.1-130825.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_MUL.dec_cr_out" +attribute \generator "nMigen" +module \dec_cr_out$184 + attribute \src "libresoc.v:130739.3-130757.6" + wire width 3 $0\cr_bitfield[2:0] + attribute \src "libresoc.v:130709.3-130727.6" + wire $0\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:130790.3-130824.6" + wire width 8 $0\cr_fxm[7:0] + attribute \src "libresoc.v:130728.3-130738.6" + wire $0\cr_fxm_ok[0:0] + attribute \src "libresoc.v:130585.7-130585.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:130758.3-130768.6" + wire $0\move_one[0:0] + attribute \src "libresoc.v:130769.3-130789.6" + wire width 8 $0\ppick_i[7:0] + attribute \src "libresoc.v:130739.3-130757.6" + wire width 3 $1\cr_bitfield[2:0] + attribute \src "libresoc.v:130709.3-130727.6" + wire $1\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:130790.3-130824.6" + wire width 8 $1\cr_fxm[7:0] + attribute \src "libresoc.v:130728.3-130738.6" + wire $1\cr_fxm_ok[0:0] + attribute \src "libresoc.v:130758.3-130768.6" + wire $1\move_one[0:0] + attribute \src "libresoc.v:130769.3-130789.6" + wire width 8 $1\ppick_i[7:0] + attribute \src "libresoc.v:130790.3-130824.6" + wire width 8 $2\cr_fxm[7:0] + attribute \src "libresoc.v:130769.3-130789.6" + wire width 8 $2\ppick_i[7:0] + attribute \src "libresoc.v:130790.3-130824.6" + wire width 8 $3\cr_fxm[7:0] + attribute \src "libresoc.v:130769.3-130789.6" + wire width 8 $3\ppick_i[7:0] + attribute \src "libresoc.v:130790.3-130824.6" + wire width 8 $4\cr_fxm[7:0] + attribute \src "libresoc.v:130702.17-130702.121" + wire $eq$libresoc.v:130702$4993_Y + attribute \src "libresoc.v:130703.17-130703.121" + wire $eq$libresoc.v:130703$4994_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:749" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:749" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 8 input 5 \MUL_FXM + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 input 3 \MUL_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 input 7 \XL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 3 input 6 \X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 \cr_bitfield + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 4 \cr_bitfield_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 8 \cr_fxm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_fxm_ok + attribute \src "libresoc.v:130585.7-130585.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:719" + wire width 32 input 8 \insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:747" + wire \move_one + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" + wire \ppick_en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 8 \ppick_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" + wire width 8 \ppick_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:717" + wire input 2 \rc_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:718" + wire width 3 input 1 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:749" + cell $eq $eq$libresoc.v:130702$4993 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \MUL_internal_op + connect \B 7'0110000 + connect \Y $eq$libresoc.v:130702$4993_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:749" + cell $eq $eq$libresoc.v:130703$4994 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \MUL_internal_op + connect \B 7'0110000 + connect \Y $eq$libresoc.v:130703$4994_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:130704.15-130708.4" + cell \ppick$185 \ppick + connect \en_o \ppick_en_o + connect \i \ppick_i + connect \o \ppick_o + end + attribute \src "libresoc.v:130585.7-130585.20" + process $proc$libresoc.v:130585$5001 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:130709.3-130727.6" + process $proc$libresoc.v:130709$4995 + assign { } { } + assign { } { } + assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:130710.5-130710.29" + switch \initial + attribute \src "libresoc.v:130710.9-130710.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:733" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\cr_bitfield_ok[0:0] \rc_in + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + case + assign $1\cr_bitfield_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] + end + attribute \src "libresoc.v:130728.3-130738.6" + process $proc$libresoc.v:130728$4996 + assign { } { } + assign { } { } + assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] + attribute \src "libresoc.v:130729.5-130729.29" + switch \initial + attribute \src "libresoc.v:130729.9-130729.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:733" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_fxm_ok[0:0] 1'1 + case + assign $1\cr_fxm_ok[0:0] 1'0 + end + sync always + update \cr_fxm_ok $0\cr_fxm_ok[0:0] + end + attribute \src "libresoc.v:130739.3-130757.6" + process $proc$libresoc.v:130739$4997 + assign { } { } + assign { } { } + assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] + attribute \src "libresoc.v:130740.5-130740.29" + switch \initial + attribute \src "libresoc.v:130740.9-130740.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:733" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\cr_bitfield[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\cr_bitfield[2:0] \X_BF + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\cr_bitfield[2:0] \XL_BT [4:2] + case + assign $1\cr_bitfield[2:0] 3'000 + end + sync always + update \cr_bitfield $0\cr_bitfield[2:0] + end + attribute \src "libresoc.v:130758.3-130768.6" + process $proc$libresoc.v:130758$4998 + assign { } { } + assign { } { } + assign $0\move_one[0:0] $1\move_one[0:0] + attribute \src "libresoc.v:130759.5-130759.29" + switch \initial + attribute \src "libresoc.v:130759.9-130759.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:733" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\move_one[0:0] \insn_in [20] + case + assign $1\move_one[0:0] 1'0 + end + sync always + update \move_one $0\move_one[0:0] + end + attribute \src "libresoc.v:130769.3-130789.6" + process $proc$libresoc.v:130769$4999 + assign { } { } + assign { } { } + assign $0\ppick_i[7:0] $1\ppick_i[7:0] + attribute \src "libresoc.v:130770.5-130770.29" + switch \initial + attribute \src "libresoc.v:130770.9-130770.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:733" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\ppick_i[7:0] $2\ppick_i[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:749" + switch \$1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ppick_i[7:0] $3\ppick_i[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:750" + switch \move_one + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\ppick_i[7:0] \MUL_FXM + case + assign $3\ppick_i[7:0] 8'00000000 + end + case + assign $2\ppick_i[7:0] 8'00000000 + end + case + assign $1\ppick_i[7:0] 8'00000000 + end + sync always + update \ppick_i $0\ppick_i[7:0] + end + attribute \src "libresoc.v:130790.3-130824.6" + process $proc$libresoc.v:130790$5000 + assign { } { } + assign { } { } + assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] + attribute \src "libresoc.v:130791.5-130791.29" + switch \initial + attribute \src "libresoc.v:130791.9-130791.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:733" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:749" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_fxm[7:0] $3\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:750" + switch \move_one + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\cr_fxm[7:0] $4\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:753" + switch \ppick_en_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\cr_fxm[7:0] \ppick_o + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $4\cr_fxm[7:0] 8'00000001 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $3\cr_fxm[7:0] \MUL_FXM + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cr_fxm[7:0] 8'11111111 + end + case + assign $1\cr_fxm[7:0] 8'00000000 + end + sync always + update \cr_fxm $0\cr_fxm[7:0] + end + connect \$1 $eq$libresoc.v:130702$4993_Y + connect \$3 $eq$libresoc.v:130703$4994_Y +end +attribute \src "libresoc.v:130829.1-131070.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SHIFT_ROT.dec_cr_out" +attribute \generator "nMigen" +module \dec_cr_out$192 + attribute \src "libresoc.v:130984.3-131002.6" + wire width 3 $0\cr_bitfield[2:0] + attribute \src "libresoc.v:130954.3-130972.6" + wire $0\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:131035.3-131069.6" + wire width 8 $0\cr_fxm[7:0] + attribute \src "libresoc.v:130973.3-130983.6" + wire $0\cr_fxm_ok[0:0] + attribute \src "libresoc.v:130830.7-130830.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:131003.3-131013.6" + wire $0\move_one[0:0] + attribute \src "libresoc.v:131014.3-131034.6" + wire width 8 $0\ppick_i[7:0] + attribute \src "libresoc.v:130984.3-131002.6" + wire width 3 $1\cr_bitfield[2:0] + attribute \src "libresoc.v:130954.3-130972.6" + wire $1\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:131035.3-131069.6" + wire width 8 $1\cr_fxm[7:0] + attribute \src "libresoc.v:130973.3-130983.6" + wire $1\cr_fxm_ok[0:0] + attribute \src "libresoc.v:131003.3-131013.6" + wire $1\move_one[0:0] + attribute \src "libresoc.v:131014.3-131034.6" + wire width 8 $1\ppick_i[7:0] + attribute \src "libresoc.v:131035.3-131069.6" + wire width 8 $2\cr_fxm[7:0] + attribute \src "libresoc.v:131014.3-131034.6" + wire width 8 $2\ppick_i[7:0] + attribute \src "libresoc.v:131035.3-131069.6" + wire width 8 $3\cr_fxm[7:0] + attribute \src "libresoc.v:131014.3-131034.6" + wire width 8 $3\ppick_i[7:0] + attribute \src "libresoc.v:131035.3-131069.6" + wire width 8 $4\cr_fxm[7:0] + attribute \src "libresoc.v:130947.17-130947.127" + wire $eq$libresoc.v:130947$5002_Y + attribute \src "libresoc.v:130948.17-130948.127" + wire $eq$libresoc.v:130948$5003_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:749" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:749" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 8 input 5 \SHIFT_ROT_FXM + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 input 3 \SHIFT_ROT_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 input 7 \XL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 3 input 6 \X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 \cr_bitfield + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 4 \cr_bitfield_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 8 \cr_fxm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_fxm_ok + attribute \src "libresoc.v:130830.7-130830.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:719" + wire width 32 input 8 \insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:747" + wire \move_one + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" + wire \ppick_en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 8 \ppick_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" + wire width 8 \ppick_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:717" + wire input 2 \rc_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:718" + wire width 3 input 1 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:749" + cell $eq $eq$libresoc.v:130947$5002 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \SHIFT_ROT_internal_op + connect \B 7'0110000 + connect \Y $eq$libresoc.v:130947$5002_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:749" + cell $eq $eq$libresoc.v:130948$5003 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \SHIFT_ROT_internal_op + connect \B 7'0110000 + connect \Y $eq$libresoc.v:130948$5003_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:130949.15-130953.4" + cell \ppick$193 \ppick + connect \en_o \ppick_en_o + connect \i \ppick_i + connect \o \ppick_o + end + attribute \src "libresoc.v:130830.7-130830.20" + process $proc$libresoc.v:130830$5010 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:130954.3-130972.6" + process $proc$libresoc.v:130954$5004 + assign { } { } + assign { } { } + assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:130955.5-130955.29" + switch \initial + attribute \src "libresoc.v:130955.9-130955.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:733" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\cr_bitfield_ok[0:0] \rc_in + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + case + assign $1\cr_bitfield_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] + end + attribute \src "libresoc.v:130973.3-130983.6" + process $proc$libresoc.v:130973$5005 + assign { } { } + assign { } { } + assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] + attribute \src "libresoc.v:130974.5-130974.29" + switch \initial + attribute \src "libresoc.v:130974.9-130974.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:733" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_fxm_ok[0:0] 1'1 + case + assign $1\cr_fxm_ok[0:0] 1'0 + end + sync always + update \cr_fxm_ok $0\cr_fxm_ok[0:0] + end + attribute \src "libresoc.v:130984.3-131002.6" + process $proc$libresoc.v:130984$5006 + assign { } { } + assign { } { } + assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] + attribute \src "libresoc.v:130985.5-130985.29" + switch \initial + attribute \src "libresoc.v:130985.9-130985.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:733" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\cr_bitfield[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\cr_bitfield[2:0] \X_BF + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\cr_bitfield[2:0] \XL_BT [4:2] + case + assign $1\cr_bitfield[2:0] 3'000 + end + sync always + update \cr_bitfield $0\cr_bitfield[2:0] + end + attribute \src "libresoc.v:131003.3-131013.6" + process $proc$libresoc.v:131003$5007 + assign { } { } + assign { } { } + assign $0\move_one[0:0] $1\move_one[0:0] + attribute \src "libresoc.v:131004.5-131004.29" + switch \initial + attribute \src "libresoc.v:131004.9-131004.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:733" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\move_one[0:0] \insn_in [20] + case + assign $1\move_one[0:0] 1'0 + end + sync always + update \move_one $0\move_one[0:0] + end + attribute \src "libresoc.v:131014.3-131034.6" + process $proc$libresoc.v:131014$5008 + assign { } { } + assign { } { } + assign $0\ppick_i[7:0] $1\ppick_i[7:0] + attribute \src "libresoc.v:131015.5-131015.29" + switch \initial + attribute \src "libresoc.v:131015.9-131015.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:733" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\ppick_i[7:0] $2\ppick_i[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:749" + switch \$1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ppick_i[7:0] $3\ppick_i[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:750" + switch \move_one + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\ppick_i[7:0] \SHIFT_ROT_FXM + case + assign $3\ppick_i[7:0] 8'00000000 + end + case + assign $2\ppick_i[7:0] 8'00000000 + end + case + assign $1\ppick_i[7:0] 8'00000000 + end + sync always + update \ppick_i $0\ppick_i[7:0] + end + attribute \src "libresoc.v:131035.3-131069.6" + process $proc$libresoc.v:131035$5009 + assign { } { } + assign { } { } + assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] + attribute \src "libresoc.v:131036.5-131036.29" + switch \initial + attribute \src "libresoc.v:131036.9-131036.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:733" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:749" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_fxm[7:0] $3\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:750" + switch \move_one + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\cr_fxm[7:0] $4\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:753" + switch \ppick_en_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\cr_fxm[7:0] \ppick_o + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $4\cr_fxm[7:0] 8'00000001 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $3\cr_fxm[7:0] \SHIFT_ROT_FXM + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cr_fxm[7:0] 8'11111111 + end + case + assign $1\cr_fxm[7:0] 8'00000000 + end + sync always + update \cr_fxm $0\cr_fxm[7:0] + end + connect \$1 $eq$libresoc.v:130947$5002_Y + connect \$3 $eq$libresoc.v:130948$5003_Y +end +attribute \src "libresoc.v:131074.1-131314.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec_cr_out" +attribute \generator "nMigen" +module \dec_cr_out$200 + attribute \src "libresoc.v:131228.3-131246.6" + wire width 3 $0\cr_bitfield[2:0] + attribute \src "libresoc.v:131198.3-131216.6" + wire $0\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:131279.3-131313.6" + wire width 8 $0\cr_fxm[7:0] + attribute \src "libresoc.v:131217.3-131227.6" + wire $0\cr_fxm_ok[0:0] + attribute \src "libresoc.v:131075.7-131075.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:131247.3-131257.6" + wire $0\move_one[0:0] + attribute \src "libresoc.v:131258.3-131278.6" + wire width 8 $0\ppick_i[7:0] + attribute \src "libresoc.v:131228.3-131246.6" + wire width 3 $1\cr_bitfield[2:0] + attribute \src "libresoc.v:131198.3-131216.6" + wire $1\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:131279.3-131313.6" + wire width 8 $1\cr_fxm[7:0] + attribute \src "libresoc.v:131217.3-131227.6" + wire $1\cr_fxm_ok[0:0] + attribute \src "libresoc.v:131247.3-131257.6" + wire $1\move_one[0:0] + attribute \src "libresoc.v:131258.3-131278.6" + wire width 8 $1\ppick_i[7:0] + attribute \src "libresoc.v:131279.3-131313.6" + wire width 8 $2\cr_fxm[7:0] + attribute \src "libresoc.v:131258.3-131278.6" + wire width 8 $2\ppick_i[7:0] + attribute \src "libresoc.v:131279.3-131313.6" + wire width 8 $3\cr_fxm[7:0] + attribute \src "libresoc.v:131258.3-131278.6" + wire width 8 $3\ppick_i[7:0] + attribute \src "libresoc.v:131279.3-131313.6" + wire width 8 $4\cr_fxm[7:0] + attribute \src "libresoc.v:131191.17-131191.122" + wire $eq$libresoc.v:131191$5011_Y + attribute \src "libresoc.v:131192.17-131192.122" + wire $eq$libresoc.v:131192$5012_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:749" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:749" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 8 input 4 \LDST_FXM + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 input 3 \LDST_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 input 6 \XL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 3 input 5 \X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 \cr_bitfield + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_bitfield_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 8 \cr_fxm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_fxm_ok + attribute \src "libresoc.v:131075.7-131075.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:719" + wire width 32 input 7 \insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:747" + wire \move_one + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" + wire \ppick_en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 8 \ppick_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" + wire width 8 \ppick_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:717" + wire input 2 \rc_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:718" + wire width 3 input 1 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:749" + cell $eq $eq$libresoc.v:131191$5011 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \LDST_internal_op + connect \B 7'0110000 + connect \Y $eq$libresoc.v:131191$5011_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:749" + cell $eq $eq$libresoc.v:131192$5012 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \LDST_internal_op + connect \B 7'0110000 + connect \Y $eq$libresoc.v:131192$5012_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:131193.15-131197.4" + cell \ppick$201 \ppick + connect \en_o \ppick_en_o + connect \i \ppick_i + connect \o \ppick_o + end + attribute \src "libresoc.v:131075.7-131075.20" + process $proc$libresoc.v:131075$5019 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:131198.3-131216.6" + process $proc$libresoc.v:131198$5013 + assign { } { } + assign { } { } + assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:131199.5-131199.29" + switch \initial + attribute \src "libresoc.v:131199.9-131199.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:733" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\cr_bitfield_ok[0:0] \rc_in + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + case + assign $1\cr_bitfield_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] + end + attribute \src "libresoc.v:131217.3-131227.6" + process $proc$libresoc.v:131217$5014 + assign { } { } + assign { } { } + assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] + attribute \src "libresoc.v:131218.5-131218.29" + switch \initial + attribute \src "libresoc.v:131218.9-131218.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:733" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_fxm_ok[0:0] 1'1 + case + assign $1\cr_fxm_ok[0:0] 1'0 + end + sync always + update \cr_fxm_ok $0\cr_fxm_ok[0:0] + end + attribute \src "libresoc.v:131228.3-131246.6" + process $proc$libresoc.v:131228$5015 + assign { } { } + assign { } { } + assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] + attribute \src "libresoc.v:131229.5-131229.29" + switch \initial + attribute \src "libresoc.v:131229.9-131229.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:733" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\cr_bitfield[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\cr_bitfield[2:0] \X_BF + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\cr_bitfield[2:0] \XL_BT [4:2] + case + assign $1\cr_bitfield[2:0] 3'000 + end + sync always + update \cr_bitfield $0\cr_bitfield[2:0] + end + attribute \src "libresoc.v:131247.3-131257.6" + process $proc$libresoc.v:131247$5016 + assign { } { } + assign { } { } + assign $0\move_one[0:0] $1\move_one[0:0] + attribute \src "libresoc.v:131248.5-131248.29" + switch \initial + attribute \src "libresoc.v:131248.9-131248.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:733" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\move_one[0:0] \insn_in [20] + case + assign $1\move_one[0:0] 1'0 + end + sync always + update \move_one $0\move_one[0:0] + end + attribute \src "libresoc.v:131258.3-131278.6" + process $proc$libresoc.v:131258$5017 + assign { } { } + assign { } { } + assign $0\ppick_i[7:0] $1\ppick_i[7:0] + attribute \src "libresoc.v:131259.5-131259.29" + switch \initial + attribute \src "libresoc.v:131259.9-131259.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:733" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\ppick_i[7:0] $2\ppick_i[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:749" + switch \$1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ppick_i[7:0] $3\ppick_i[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:750" + switch \move_one + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\ppick_i[7:0] \LDST_FXM + case + assign $3\ppick_i[7:0] 8'00000000 + end + case + assign $2\ppick_i[7:0] 8'00000000 + end + case + assign $1\ppick_i[7:0] 8'00000000 + end + sync always + update \ppick_i $0\ppick_i[7:0] + end + attribute \src "libresoc.v:131279.3-131313.6" + process $proc$libresoc.v:131279$5018 + assign { } { } + assign { } { } + assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] + attribute \src "libresoc.v:131280.5-131280.29" + switch \initial + attribute \src "libresoc.v:131280.9-131280.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:733" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:749" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_fxm[7:0] $3\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:750" + switch \move_one + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\cr_fxm[7:0] $4\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:753" + switch \ppick_en_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\cr_fxm[7:0] \ppick_o + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $4\cr_fxm[7:0] 8'00000001 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $3\cr_fxm[7:0] \LDST_FXM + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cr_fxm[7:0] 8'11111111 + end + case + assign $1\cr_fxm[7:0] 8'00000000 + end + sync always + update \cr_fxm $0\cr_fxm[7:0] + end + connect \$1 $eq$libresoc.v:131191$5011_Y + connect \$3 $eq$libresoc.v:131192$5012_Y +end +attribute \src "libresoc.v:131318.1-131562.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_cr_out" +attribute \generator "nMigen" +module \dec_cr_out$209 + attribute \src "libresoc.v:131476.3-131494.6" + wire width 3 $0\cr_bitfield[2:0] + attribute \src "libresoc.v:131446.3-131464.6" + wire $0\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:131527.3-131561.6" + wire width 8 $0\cr_fxm[7:0] + attribute \src "libresoc.v:131465.3-131475.6" + wire $0\cr_fxm_ok[0:0] + attribute \src "libresoc.v:131319.7-131319.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:131495.3-131505.6" + wire $0\move_one[0:0] + attribute \src "libresoc.v:131506.3-131526.6" + wire width 8 $0\ppick_i[7:0] + attribute \src "libresoc.v:131476.3-131494.6" + wire width 3 $1\cr_bitfield[2:0] + attribute \src "libresoc.v:131446.3-131464.6" + wire $1\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:131527.3-131561.6" + wire width 8 $1\cr_fxm[7:0] + attribute \src "libresoc.v:131465.3-131475.6" + wire $1\cr_fxm_ok[0:0] + attribute \src "libresoc.v:131495.3-131505.6" + wire $1\move_one[0:0] + attribute \src "libresoc.v:131506.3-131526.6" + wire width 8 $1\ppick_i[7:0] + attribute \src "libresoc.v:131527.3-131561.6" + wire width 8 $2\cr_fxm[7:0] + attribute \src "libresoc.v:131506.3-131526.6" + wire width 8 $2\ppick_i[7:0] + attribute \src "libresoc.v:131527.3-131561.6" + wire width 8 $3\cr_fxm[7:0] + attribute \src "libresoc.v:131506.3-131526.6" + wire width 8 $3\ppick_i[7:0] + attribute \src "libresoc.v:131527.3-131561.6" + wire width 8 $4\cr_fxm[7:0] + attribute \src "libresoc.v:131439.17-131439.117" + wire $eq$libresoc.v:131439$5020_Y + attribute \src "libresoc.v:131440.17-131440.117" + wire $eq$libresoc.v:131440$5021_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:749" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:749" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 8 input 8 \FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 5 input 10 \XL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:481" + wire width 3 input 9 \X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 output 6 \cr_bitfield + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 7 \cr_bitfield_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 8 output 4 \cr_fxm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 5 \cr_fxm_ok + attribute \src "libresoc.v:131319.7-131319.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:719" + wire width 32 input 11 \insn_in + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 input 3 \internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:747" + wire \move_one + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" + wire \ppick_en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 8 \ppick_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" + wire width 8 \ppick_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:717" + wire input 2 \rc_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \enum_value_101 "CR1" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:718" + wire width 3 input 1 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:749" + cell $eq $eq$libresoc.v:131439$5020 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \internal_op + connect \B 7'0110000 + connect \Y $eq$libresoc.v:131439$5020_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:749" + cell $eq $eq$libresoc.v:131440$5021 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \internal_op + connect \B 7'0110000 + connect \Y $eq$libresoc.v:131440$5021_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:131441.15-131445.4" + cell \ppick$210 \ppick + connect \en_o \ppick_en_o + connect \i \ppick_i + connect \o \ppick_o + end + attribute \src "libresoc.v:131319.7-131319.20" + process $proc$libresoc.v:131319$5028 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:131446.3-131464.6" + process $proc$libresoc.v:131446$5022 + assign { } { } + assign { } { } + assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] + attribute \src "libresoc.v:131447.5-131447.29" + switch \initial + attribute \src "libresoc.v:131447.9-131447.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:733" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\cr_bitfield_ok[0:0] \rc_in + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + case + assign $1\cr_bitfield_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] + end + attribute \src "libresoc.v:131465.3-131475.6" + process $proc$libresoc.v:131465$5023 + assign { } { } + assign { } { } + assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] + attribute \src "libresoc.v:131466.5-131466.29" + switch \initial + attribute \src "libresoc.v:131466.9-131466.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:733" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_fxm_ok[0:0] 1'1 + case + assign $1\cr_fxm_ok[0:0] 1'0 + end + sync always + update \cr_fxm_ok $0\cr_fxm_ok[0:0] + end + attribute \src "libresoc.v:131476.3-131494.6" + process $proc$libresoc.v:131476$5024 + assign { } { } + assign { } { } + assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] + attribute \src "libresoc.v:131477.5-131477.29" + switch \initial + attribute \src "libresoc.v:131477.9-131477.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:733" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\cr_bitfield[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\cr_bitfield[2:0] \X_BF + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\cr_bitfield[2:0] \XL_BT [4:2] + case + assign $1\cr_bitfield[2:0] 3'000 + end + sync always + update \cr_bitfield $0\cr_bitfield[2:0] + end + attribute \src "libresoc.v:131495.3-131505.6" + process $proc$libresoc.v:131495$5025 + assign { } { } + assign { } { } + assign $0\move_one[0:0] $1\move_one[0:0] + attribute \src "libresoc.v:131496.5-131496.29" + switch \initial + attribute \src "libresoc.v:131496.9-131496.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:733" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\move_one[0:0] \insn_in [20] + case + assign $1\move_one[0:0] 1'0 + end + sync always + update \move_one $0\move_one[0:0] + end + attribute \src "libresoc.v:131506.3-131526.6" + process $proc$libresoc.v:131506$5026 + assign { } { } + assign { } { } + assign $0\ppick_i[7:0] $1\ppick_i[7:0] + attribute \src "libresoc.v:131507.5-131507.29" + switch \initial + attribute \src "libresoc.v:131507.9-131507.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:733" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\ppick_i[7:0] $2\ppick_i[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:749" + switch \$1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ppick_i[7:0] $3\ppick_i[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:750" + switch \move_one + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\ppick_i[7:0] \FXM + case + assign $3\ppick_i[7:0] 8'00000000 + end + case + assign $2\ppick_i[7:0] 8'00000000 + end + case + assign $1\ppick_i[7:0] 8'00000000 + end + sync always + update \ppick_i $0\ppick_i[7:0] + end + attribute \src "libresoc.v:131527.3-131561.6" + process $proc$libresoc.v:131527$5027 + assign { } { } + assign { } { } + assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] + attribute \src "libresoc.v:131528.5-131528.29" + switch \initial + attribute \src "libresoc.v:131528.9-131528.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:733" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:749" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_fxm[7:0] $3\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:750" + switch \move_one + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\cr_fxm[7:0] $4\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:753" + switch \ppick_en_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\cr_fxm[7:0] \ppick_o + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $4\cr_fxm[7:0] 8'00000001 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $3\cr_fxm[7:0] \FXM + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cr_fxm[7:0] 8'11111111 + end + case + assign $1\cr_fxm[7:0] 8'00000000 + end + sync always + update \cr_fxm $0\cr_fxm[7:0] + end + connect \$1 $eq$libresoc.v:131439$5020_Y + connect \$3 $eq$libresoc.v:131440$5021_Y +end +attribute \src "libresoc.v:131566.1-132047.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_o" +attribute \generator "nMigen" +module \dec_o + attribute \src "libresoc.v:132008.3-132046.6" + wire width 3 $0\fast_o[2:0] + attribute \src "libresoc.v:132008.3-132046.6" + wire $0\fast_o_ok[0:0] + attribute \src "libresoc.v:131567.7-131567.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:131934.3-131948.6" + wire width 5 $0\reg_o[4:0] + attribute \src "libresoc.v:131949.3-131963.6" + wire $0\reg_o_ok[0:0] + attribute \src "libresoc.v:131964.3-131974.6" + wire width 10 $0\spr[9:0] + attribute \src "libresoc.v:131991.3-132007.6" + wire width 10 $0\spr_o[9:0] + attribute \src "libresoc.v:131991.3-132007.6" + wire $0\spr_o_ok[0:0] + attribute \src "libresoc.v:131975.3-131990.6" + wire width 10 $0\sprmap_spr_i[9:0] + attribute \src "libresoc.v:132008.3-132046.6" + wire width 3 $1\fast_o[2:0] + attribute \src "libresoc.v:132008.3-132046.6" + wire $1\fast_o_ok[0:0] + attribute \src "libresoc.v:131934.3-131948.6" + wire width 5 $1\reg_o[4:0] + attribute \src "libresoc.v:131949.3-131963.6" + wire $1\reg_o_ok[0:0] + attribute \src "libresoc.v:131964.3-131974.6" + wire width 10 $1\spr[9:0] + attribute \src "libresoc.v:131991.3-132007.6" + wire width 10 $1\spr_o[9:0] + attribute \src "libresoc.v:131991.3-132007.6" + wire $1\spr_o_ok[0:0] + attribute \src "libresoc.v:131975.3-131990.6" + wire width 10 $1\sprmap_spr_i[9:0] + attribute \src "libresoc.v:132008.3-132046.6" + wire width 3 $2\fast_o[2:0] + attribute \src "libresoc.v:132008.3-132046.6" + wire $2\fast_o_ok[0:0] + attribute \src "libresoc.v:131991.3-132007.6" + wire width 10 $2\spr_o[9:0] + attribute \src "libresoc.v:131991.3-132007.6" + wire $2\spr_o_ok[0:0] + attribute \src "libresoc.v:131975.3-131990.6" + wire width 10 $2\sprmap_spr_i[9:0] + attribute \src "libresoc.v:132008.3-132046.6" + wire width 3 $3\fast_o[2:0] + attribute \src "libresoc.v:132008.3-132046.6" + wire $3\fast_o_ok[0:0] + attribute \src "libresoc.v:132008.3-132046.6" + wire width 3 $4\fast_o[2:0] + attribute \src "libresoc.v:132008.3-132046.6" + wire $4\fast_o_ok[0:0] + attribute \src "libresoc.v:131923.17-131923.117" + wire $eq$libresoc.v:131923$5029_Y + attribute \src "libresoc.v:131924.17-131924.117" + wire $eq$libresoc.v:131924$5030_Y + attribute \src "libresoc.v:131925.17-131925.117" + wire $eq$libresoc.v:131925$5031_Y + attribute \src "libresoc.v:131926.17-131926.104" + wire $not$libresoc.v:131926$5032_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:484" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:484" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:484" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:494" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 input 11 \BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 input 10 \RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 input 9 \RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 10 input 1 \SPR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 output 7 \fast_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 8 \fast_o_ok + attribute \src "libresoc.v:131567.7-131567.15" + wire \initial + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 input 12 \internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 5 output 3 \reg_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 4 \reg_o_ok + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:459" + wire width 2 input 2 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:481" + wire width 10 \spr + attribute \enum_base_type "SPR" + attribute \enum_value_0000000001 "XER" + attribute \enum_value_0000000011 "DSCR" + attribute \enum_value_0000001000 "LR" + attribute \enum_value_0000001001 "CTR" + attribute \enum_value_0000001101 "AMR" + attribute \enum_value_0000010001 "DSCR_priv" + attribute \enum_value_0000010010 "DSISR" + attribute \enum_value_0000010011 "DAR" + attribute \enum_value_0000010110 "DEC" + attribute \enum_value_0000011010 "SRR0" + attribute \enum_value_0000011011 "SRR1" + attribute \enum_value_0000011100 "CFAR" + attribute \enum_value_0000011101 "AMR_priv" + attribute \enum_value_0000110000 "PIDR" + attribute \enum_value_0000111101 "IAMR" + attribute \enum_value_0010000000 "TFHAR" + attribute \enum_value_0010000001 "TFIAR" + attribute \enum_value_0010000010 "TEXASR" + attribute \enum_value_0010000011 "TEXASRU" + attribute \enum_value_0010001000 "CTRL" + attribute \enum_value_0010010000 "TIDR" + attribute \enum_value_0010011000 "CTRL_priv" + attribute \enum_value_0010011001 "FSCR" + attribute \enum_value_0010011101 "UAMOR" + attribute \enum_value_0010011110 "GSR" + attribute \enum_value_0010011111 "PSPB" + attribute \enum_value_0010110000 "DPDES" + attribute \enum_value_0010110100 "DAWR0" + attribute \enum_value_0010111010 "RPR" + attribute \enum_value_0010111011 "CIABR" + attribute \enum_value_0010111100 "DAWRX0" + attribute \enum_value_0010111110 "HFSCR" + attribute \enum_value_0100000000 "VRSAVE" + attribute \enum_value_0100000011 "SPRG3" + attribute \enum_value_0100001100 "TB" + attribute \enum_value_0100001101 "TBU" + attribute \enum_value_0100010000 "SPRG0_priv" + attribute \enum_value_0100010001 "SPRG1_priv" + attribute \enum_value_0100010010 "SPRG2_priv" + attribute \enum_value_0100010011 "SPRG3_priv" + attribute \enum_value_0100011011 "CIR" + attribute \enum_value_0100011100 "TBL" + attribute \enum_value_0100011101 "TBU_hypv" + attribute \enum_value_0100011110 "TBU40" + attribute \enum_value_0100011111 "PVR" + attribute \enum_value_0100110000 "HSPRG0" + attribute \enum_value_0100110001 "HSPRG1" + attribute \enum_value_0100110010 "HDSISR" + attribute \enum_value_0100110011 "HDAR" + attribute \enum_value_0100110100 "SPURR" + attribute \enum_value_0100110101 "PURR" + attribute \enum_value_0100110110 "HDEC" + attribute \enum_value_0100111001 "HRMOR" + attribute \enum_value_0100111010 "HSRR0" + attribute \enum_value_0100111011 "HSRR1" + attribute \enum_value_0100111110 "LPCR" + attribute \enum_value_0100111111 "LPIDR" + attribute \enum_value_0101010000 "HMER" + attribute \enum_value_0101010001 "HMEER" + attribute \enum_value_0101010010 "PCR" + attribute \enum_value_0101010011 "HEIR" + attribute \enum_value_0101011101 "AMOR" + attribute \enum_value_0110111110 "TIR" + attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1011000000 "SVSTATE" + attribute \enum_value_1011010000 "SVSRR0" + attribute \enum_value_1100000000 "SIER" + attribute \enum_value_1100000001 "MMCR2" + attribute \enum_value_1100000010 "MMCRA" + attribute \enum_value_1100000011 "PMC1" + attribute \enum_value_1100000100 "PMC2" + attribute \enum_value_1100000101 "PMC3" + attribute \enum_value_1100000110 "PMC4" + attribute \enum_value_1100000111 "PMC5" + attribute \enum_value_1100001000 "PMC6" + attribute \enum_value_1100001011 "MMCR0" + attribute \enum_value_1100001100 "SIAR" + attribute \enum_value_1100001101 "SDAR" + attribute \enum_value_1100001110 "MMCR1" + attribute \enum_value_1100010000 "SIER_priv" + attribute \enum_value_1100010001 "MMCR2_priv" + attribute \enum_value_1100010010 "MMCRA_priv" + attribute \enum_value_1100010011 "PMC1_priv" + attribute \enum_value_1100010100 "PMC2_priv" + attribute \enum_value_1100010101 "PMC3_priv" + attribute \enum_value_1100010110 "PMC4_priv" + attribute \enum_value_1100010111 "PMC5_priv" + attribute \enum_value_1100011000 "PMC6_priv" + attribute \enum_value_1100011011 "MMCR0_priv" + attribute \enum_value_1100011100 "SIAR_priv" + attribute \enum_value_1100011101 "SDAR_priv" + attribute \enum_value_1100011110 "MMCR1_priv" + attribute \enum_value_1100100000 "BESCRS" + attribute \enum_value_1100100001 "BESCRSU" + attribute \enum_value_1100100010 "BESCRR" + attribute \enum_value_1100100011 "BESCRRU" + attribute \enum_value_1100100100 "EBBHR" + attribute \enum_value_1100100101 "EBBRR" + attribute \enum_value_1100100110 "BESCR" + attribute \enum_value_1100101000 "reserved808" + attribute \enum_value_1100101001 "reserved809" + attribute \enum_value_1100101010 "reserved810" + attribute \enum_value_1100101011 "reserved811" + attribute \enum_value_1100101111 "TAR" + attribute \enum_value_1100110000 "ASDR" + attribute \enum_value_1100110111 "PSSCR" + attribute \enum_value_1101010000 "IC" + attribute \enum_value_1101010001 "VTB" + attribute \enum_value_1101010111 "PSSCR_hypv" + attribute \enum_value_1110000000 "PPR" + attribute \enum_value_1110000010 "PPR32" + attribute \enum_value_1111111111 "PIR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 10 output 5 \spr_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 6 \spr_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 \sprmap_fast_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \sprmap_fast_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + wire width 10 \sprmap_spr_i + attribute \enum_base_type "SPR" + attribute \enum_value_0000000001 "XER" + attribute \enum_value_0000000011 "DSCR" + attribute \enum_value_0000001000 "LR" + attribute \enum_value_0000001001 "CTR" + attribute \enum_value_0000001101 "AMR" + attribute \enum_value_0000010001 "DSCR_priv" + attribute \enum_value_0000010010 "DSISR" + attribute \enum_value_0000010011 "DAR" + attribute \enum_value_0000010110 "DEC" + attribute \enum_value_0000011010 "SRR0" + attribute \enum_value_0000011011 "SRR1" + attribute \enum_value_0000011100 "CFAR" + attribute \enum_value_0000011101 "AMR_priv" + attribute \enum_value_0000110000 "PIDR" + attribute \enum_value_0000111101 "IAMR" + attribute \enum_value_0010000000 "TFHAR" + attribute \enum_value_0010000001 "TFIAR" + attribute \enum_value_0010000010 "TEXASR" + attribute \enum_value_0010000011 "TEXASRU" + attribute \enum_value_0010001000 "CTRL" + attribute \enum_value_0010010000 "TIDR" + attribute \enum_value_0010011000 "CTRL_priv" + attribute \enum_value_0010011001 "FSCR" + attribute \enum_value_0010011101 "UAMOR" + attribute \enum_value_0010011110 "GSR" + attribute \enum_value_0010011111 "PSPB" + attribute \enum_value_0010110000 "DPDES" + attribute \enum_value_0010110100 "DAWR0" + attribute \enum_value_0010111010 "RPR" + attribute \enum_value_0010111011 "CIABR" + attribute \enum_value_0010111100 "DAWRX0" + attribute \enum_value_0010111110 "HFSCR" + attribute \enum_value_0100000000 "VRSAVE" + attribute \enum_value_0100000011 "SPRG3" + attribute \enum_value_0100001100 "TB" + attribute \enum_value_0100001101 "TBU" + attribute \enum_value_0100010000 "SPRG0_priv" + attribute \enum_value_0100010001 "SPRG1_priv" + attribute \enum_value_0100010010 "SPRG2_priv" + attribute \enum_value_0100010011 "SPRG3_priv" + attribute \enum_value_0100011011 "CIR" + attribute \enum_value_0100011100 "TBL" + attribute \enum_value_0100011101 "TBU_hypv" + attribute \enum_value_0100011110 "TBU40" + attribute \enum_value_0100011111 "PVR" + attribute \enum_value_0100110000 "HSPRG0" + attribute \enum_value_0100110001 "HSPRG1" + attribute \enum_value_0100110010 "HDSISR" + attribute \enum_value_0100110011 "HDAR" + attribute \enum_value_0100110100 "SPURR" + attribute \enum_value_0100110101 "PURR" + attribute \enum_value_0100110110 "HDEC" + attribute \enum_value_0100111001 "HRMOR" + attribute \enum_value_0100111010 "HSRR0" + attribute \enum_value_0100111011 "HSRR1" + attribute \enum_value_0100111110 "LPCR" + attribute \enum_value_0100111111 "LPIDR" + attribute \enum_value_0101010000 "HMER" + attribute \enum_value_0101010001 "HMEER" + attribute \enum_value_0101010010 "PCR" + attribute \enum_value_0101010011 "HEIR" + attribute \enum_value_0101011101 "AMOR" + attribute \enum_value_0110111110 "TIR" + attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1011000000 "SVSTATE" + attribute \enum_value_1011010000 "SVSRR0" + attribute \enum_value_1100000000 "SIER" + attribute \enum_value_1100000001 "MMCR2" + attribute \enum_value_1100000010 "MMCRA" + attribute \enum_value_1100000011 "PMC1" + attribute \enum_value_1100000100 "PMC2" + attribute \enum_value_1100000101 "PMC3" + attribute \enum_value_1100000110 "PMC4" + attribute \enum_value_1100000111 "PMC5" + attribute \enum_value_1100001000 "PMC6" + attribute \enum_value_1100001011 "MMCR0" + attribute \enum_value_1100001100 "SIAR" + attribute \enum_value_1100001101 "SDAR" + attribute \enum_value_1100001110 "MMCR1" + attribute \enum_value_1100010000 "SIER_priv" + attribute \enum_value_1100010001 "MMCR2_priv" + attribute \enum_value_1100010010 "MMCRA_priv" + attribute \enum_value_1100010011 "PMC1_priv" + attribute \enum_value_1100010100 "PMC2_priv" + attribute \enum_value_1100010101 "PMC3_priv" + attribute \enum_value_1100010110 "PMC4_priv" + attribute \enum_value_1100010111 "PMC5_priv" + attribute \enum_value_1100011000 "PMC6_priv" + attribute \enum_value_1100011011 "MMCR0_priv" + attribute \enum_value_1100011100 "SIAR_priv" + attribute \enum_value_1100011101 "SDAR_priv" + attribute \enum_value_1100011110 "MMCR1_priv" + attribute \enum_value_1100100000 "BESCRS" + attribute \enum_value_1100100001 "BESCRSU" + attribute \enum_value_1100100010 "BESCRR" + attribute \enum_value_1100100011 "BESCRRU" + attribute \enum_value_1100100100 "EBBHR" + attribute \enum_value_1100100101 "EBBRR" + attribute \enum_value_1100100110 "BESCR" + attribute \enum_value_1100101000 "reserved808" + attribute \enum_value_1100101001 "reserved809" + attribute \enum_value_1100101010 "reserved810" + attribute \enum_value_1100101011 "reserved811" + attribute \enum_value_1100101111 "TAR" + attribute \enum_value_1100110000 "ASDR" + attribute \enum_value_1100110111 "PSSCR" + attribute \enum_value_1101010000 "IC" + attribute \enum_value_1101010001 "VTB" + attribute \enum_value_1101010111 "PSSCR_hypv" + attribute \enum_value_1110000000 "PPR" + attribute \enum_value_1110000010 "PPR32" + attribute \enum_value_1111111111 "PIR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 10 \sprmap_spr_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \sprmap_spr_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:484" + cell $eq $eq$libresoc.v:131923$5029 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \internal_op + connect \B 7'0110001 + connect \Y $eq$libresoc.v:131923$5029_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:484" + cell $eq $eq$libresoc.v:131924$5030 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \internal_op + connect \B 7'0110001 + connect \Y $eq$libresoc.v:131924$5030_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:484" + cell $eq $eq$libresoc.v:131925$5031 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \internal_op + connect \B 7'0110001 + connect \Y $eq$libresoc.v:131925$5031_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:494" + cell $not $not$libresoc.v:131926$5032 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \BO [2] + connect \Y $not$libresoc.v:131926$5032_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:131927.16-131933.4" + cell \sprmap$211 \sprmap + connect \fast_o \sprmap_fast_o + connect \fast_o_ok \sprmap_fast_o_ok + connect \spr_i \sprmap_spr_i + connect \spr_o \sprmap_spr_o + connect \spr_o_ok \sprmap_spr_o_ok + end + attribute \src "libresoc.v:131567.7-131567.20" + process $proc$libresoc.v:131567$5039 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:131934.3-131948.6" + process $proc$libresoc.v:131934$5033 + assign { } { } + assign { } { } + assign $0\reg_o[4:0] $1\reg_o[4:0] + attribute \src "libresoc.v:131935.5-131935.29" + switch \initial + attribute \src "libresoc.v:131935.9-131935.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:473" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\reg_o[4:0] \RT + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\reg_o[4:0] \RA + case + assign $1\reg_o[4:0] 5'00000 + end + sync always + update \reg_o $0\reg_o[4:0] + end + attribute \src "libresoc.v:131949.3-131963.6" + process $proc$libresoc.v:131949$5034 + assign { } { } + assign { } { } + assign $0\reg_o_ok[0:0] $1\reg_o_ok[0:0] + attribute \src "libresoc.v:131950.5-131950.29" + switch \initial + attribute \src "libresoc.v:131950.9-131950.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:473" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\reg_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\reg_o_ok[0:0] 1'1 + case + assign $1\reg_o_ok[0:0] 1'0 + end + sync always + update \reg_o_ok $0\reg_o_ok[0:0] + end + attribute \src "libresoc.v:131964.3-131974.6" + process $proc$libresoc.v:131964$5035 + assign { } { } + assign { } { } + assign $0\spr[9:0] $1\spr[9:0] + attribute \src "libresoc.v:131965.5-131965.29" + switch \initial + attribute \src "libresoc.v:131965.9-131965.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:473" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'11 + assign { } { } + assign $1\spr[9:0] { \SPR [4:0] \SPR [9:5] } + case + assign $1\spr[9:0] 10'0000000000 + end + sync always + update \spr $0\spr[9:0] + end + attribute \src "libresoc.v:131975.3-131990.6" + process $proc$libresoc.v:131975$5036 + assign { } { } + assign { } { } + assign $0\sprmap_spr_i[9:0] $1\sprmap_spr_i[9:0] + attribute \src "libresoc.v:131976.5-131976.29" + switch \initial + attribute \src "libresoc.v:131976.9-131976.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:473" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'11 + assign { } { } + assign $1\sprmap_spr_i[9:0] $2\sprmap_spr_i[9:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:484" + switch \$1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\sprmap_spr_i[9:0] \spr + case + assign $2\sprmap_spr_i[9:0] 10'0000000000 + end + case + assign $1\sprmap_spr_i[9:0] 10'0000000000 + end + sync always + update \sprmap_spr_i $0\sprmap_spr_i[9:0] + end + attribute \src "libresoc.v:131991.3-132007.6" + process $proc$libresoc.v:131991$5037 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\spr_o[9:0] $1\spr_o[9:0] + assign $0\spr_o_ok[0:0] $1\spr_o_ok[0:0] + attribute \src "libresoc.v:131992.5-131992.29" + switch \initial + attribute \src "libresoc.v:131992.9-131992.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:473" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'11 + assign { } { } + assign { } { } + assign $1\spr_o[9:0] $2\spr_o[9:0] + assign $1\spr_o_ok[0:0] $2\spr_o_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:484" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\spr_o_ok[0:0] $2\spr_o[9:0] } { \sprmap_spr_o_ok \sprmap_spr_o } + case + assign $2\spr_o[9:0] 10'0000000000 + assign $2\spr_o_ok[0:0] 1'0 + end + case + assign $1\spr_o[9:0] 10'0000000000 + assign $1\spr_o_ok[0:0] 1'0 + end + sync always + update \spr_o $0\spr_o[9:0] + update \spr_o_ok $0\spr_o_ok[0:0] + end + attribute \src "libresoc.v:132008.3-132046.6" + process $proc$libresoc.v:132008$5038 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\fast_o[2:0] $3\fast_o[2:0] + assign $0\fast_o_ok[0:0] $3\fast_o_ok[0:0] + attribute \src "libresoc.v:132009.5-132009.29" + switch \initial + attribute \src "libresoc.v:132009.9-132009.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:473" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'11 + assign { } { } + assign { } { } + assign $1\fast_o[2:0] $2\fast_o[2:0] + assign $1\fast_o_ok[0:0] $2\fast_o_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:484" + switch \$5 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\fast_o_ok[0:0] $2\fast_o[2:0] } { \sprmap_fast_o_ok \sprmap_fast_o } + case + assign $2\fast_o[2:0] 3'000 + assign $2\fast_o_ok[0:0] 1'0 + end + case + assign $1\fast_o[2:0] 3'000 + assign $1\fast_o_ok[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:490" + switch \internal_op + attribute \src "libresoc.v:0.0-0.0" + case 7'0000111 , 7'0001000 + assign { } { } + assign { } { } + assign $3\fast_o[2:0] $4\fast_o[2:0] + assign $3\fast_o_ok[0:0] $4\fast_o_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:494" + switch \$7 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $4\fast_o[2:0] 3'000 + assign $4\fast_o_ok[0:0] 1'1 + case + assign $4\fast_o[2:0] $1\fast_o[2:0] + assign $4\fast_o_ok[0:0] $1\fast_o_ok[0:0] + end + attribute \src "libresoc.v:0.0-0.0" + case 7'1000110 + assign { } { } + assign { } { } + assign $3\fast_o[2:0] 3'011 + assign $3\fast_o_ok[0:0] 1'1 + case + assign $3\fast_o[2:0] $1\fast_o[2:0] + assign $3\fast_o_ok[0:0] $1\fast_o_ok[0:0] + end + sync always + update \fast_o $0\fast_o[2:0] + update \fast_o_ok $0\fast_o_ok[0:0] + end + connect \$1 $eq$libresoc.v:131923$5029_Y + connect \$3 $eq$libresoc.v:131924$5030_Y + connect \$5 $eq$libresoc.v:131925$5031_Y + connect \$7 $not$libresoc.v:131926$5032_Y +end +attribute \src "libresoc.v:132051.1-132218.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_o2" +attribute \generator "nMigen" +module \dec_o2 + attribute \src "libresoc.v:132178.3-132197.6" + wire width 3 $0\fast_o2[2:0] + attribute \src "libresoc.v:132198.3-132217.6" + wire $0\fast_o2_ok[0:0] + attribute \src "libresoc.v:132052.7-132052.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:132158.3-132167.6" + wire width 5 $0\reg_o2[4:0] + attribute \src "libresoc.v:132168.3-132177.6" + wire $0\reg_o2_ok[0:0] + attribute \src "libresoc.v:132178.3-132197.6" + wire width 3 $1\fast_o2[2:0] + attribute \src "libresoc.v:132198.3-132217.6" + wire $1\fast_o2_ok[0:0] + attribute \src "libresoc.v:132158.3-132167.6" + wire width 5 $1\reg_o2[4:0] + attribute \src "libresoc.v:132168.3-132177.6" + wire $1\reg_o2_ok[0:0] + attribute \src "libresoc.v:132178.3-132197.6" + wire width 3 $2\fast_o2[2:0] + attribute \src "libresoc.v:132198.3-132217.6" + wire $2\fast_o2_ok[0:0] + attribute \src "libresoc.v:132156.17-132156.108" + wire $eq$libresoc.v:132156$5040_Y + attribute \src "libresoc.v:132157.17-132157.108" + wire $eq$libresoc.v:132157$5041_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:540" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:540" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire width 5 input 7 \RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 output 4 \fast_o2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 5 \fast_o2_ok + attribute \src "libresoc.v:132052.7-132052.15" + wire \initial + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 input 8 \internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" + wire input 1 \lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 5 output 2 \reg_o2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 3 \reg_o2_ok + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 2 input 6 \upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:540" + cell $eq $eq$libresoc.v:132156$5040 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \upd + connect \B 2'01 + connect \Y $eq$libresoc.v:132156$5040_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:540" + cell $eq $eq$libresoc.v:132157$5041 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \upd + connect \B 2'01 + connect \Y $eq$libresoc.v:132157$5041_Y + end + attribute \src "libresoc.v:132052.7-132052.20" + process $proc$libresoc.v:132052$5046 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:132158.3-132167.6" + process $proc$libresoc.v:132158$5042 + assign { } { } + assign { } { } + assign $0\reg_o2[4:0] $1\reg_o2[4:0] + attribute \src "libresoc.v:132159.5-132159.29" + switch \initial + attribute \src "libresoc.v:132159.9-132159.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:540" + switch \$1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\reg_o2[4:0] \RA + case + assign $1\reg_o2[4:0] 5'00000 + end + sync always + update \reg_o2 $0\reg_o2[4:0] + end + attribute \src "libresoc.v:132168.3-132177.6" + process $proc$libresoc.v:132168$5043 + assign { } { } + assign { } { } + assign $0\reg_o2_ok[0:0] $1\reg_o2_ok[0:0] + attribute \src "libresoc.v:132169.5-132169.29" + switch \initial + attribute \src "libresoc.v:132169.9-132169.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:540" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\reg_o2_ok[0:0] 1'1 + case + assign $1\reg_o2_ok[0:0] 1'0 + end + sync always + update \reg_o2_ok $0\reg_o2_ok[0:0] + end + attribute \src "libresoc.v:132178.3-132197.6" + process $proc$libresoc.v:132178$5044 + assign { } { } + assign { } { } + assign $0\fast_o2[2:0] $1\fast_o2[2:0] + attribute \src "libresoc.v:132179.5-132179.29" + switch \initial + attribute \src "libresoc.v:132179.9-132179.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:546" + switch \internal_op + attribute \src "libresoc.v:0.0-0.0" + case 7'0000111 , 7'0000110 , 7'0001000 + assign { } { } + assign $1\fast_o2[2:0] $2\fast_o2[2:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:550" + switch \lk + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\fast_o2[2:0] 3'001 + case + assign $2\fast_o2[2:0] 3'000 + end + attribute \src "libresoc.v:0.0-0.0" + case 7'1000110 + assign { } { } + assign $1\fast_o2[2:0] 3'100 + case + assign $1\fast_o2[2:0] 3'000 + end + sync always + update \fast_o2 $0\fast_o2[2:0] + end + attribute \src "libresoc.v:132198.3-132217.6" + process $proc$libresoc.v:132198$5045 + assign { } { } + assign { } { } + assign $0\fast_o2_ok[0:0] $1\fast_o2_ok[0:0] + attribute \src "libresoc.v:132199.5-132199.29" + switch \initial + attribute \src "libresoc.v:132199.9-132199.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:546" + switch \internal_op + attribute \src "libresoc.v:0.0-0.0" + case 7'0000111 , 7'0000110 , 7'0001000 + assign { } { } + assign $1\fast_o2_ok[0:0] $2\fast_o2_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:550" + switch \lk + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\fast_o2_ok[0:0] 1'1 + case + assign $2\fast_o2_ok[0:0] 1'0 + end + attribute \src "libresoc.v:0.0-0.0" + case 7'1000110 + assign { } { } + assign $1\fast_o2_ok[0:0] 1'1 + case + assign $1\fast_o2_ok[0:0] 1'0 + end + sync always + update \fast_o2_ok $0\fast_o2_ok[0:0] + end + connect \$1 $eq$libresoc.v:132156$5040_Y + connect \$3 $eq$libresoc.v:132157$5041_Y +end +attribute \src "libresoc.v:132222.1-132356.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec_oe" +attribute \generator "nMigen" +module \dec_oe + attribute \src "libresoc.v:132223.7-132223.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:132314.3-132334.6" + wire $0\oe[0:0] + attribute \src "libresoc.v:132335.3-132355.6" + wire $0\oe_ok[0:0] + attribute \src "libresoc.v:132314.3-132334.6" + wire $1\oe[0:0] + attribute \src "libresoc.v:132335.3-132355.6" + wire $1\oe_ok[0:0] + attribute \src "libresoc.v:132314.3-132334.6" + wire $2\oe[0:0] + attribute \src "libresoc.v:132335.3-132355.6" + wire $2\oe_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire input 4 \ALU_OE + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 input 1 \ALU_internal_op + attribute \src "libresoc.v:132223.7-132223.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 2 \oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 3 \oe_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:607" + wire width 2 input 5 \sel_in + attribute \src "libresoc.v:132223.7-132223.20" + process $proc$libresoc.v:132223$5049 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:132314.3-132334.6" + process $proc$libresoc.v:132314$5047 + assign { } { } + assign { } { } + assign $0\oe[0:0] $1\oe[0:0] + attribute \src "libresoc.v:132315.5-132315.29" + switch \initial + attribute \src "libresoc.v:132315.9-132315.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:616" + switch \ALU_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 + assign $1\oe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\oe[0:0] $2\oe[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:633" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $2\oe[0:0] \ALU_OE + case + assign $2\oe[0:0] 1'0 + end + end + sync always + update \oe $0\oe[0:0] + end + attribute \src "libresoc.v:132335.3-132355.6" + process $proc$libresoc.v:132335$5048 + assign { } { } + assign { } { } + assign $0\oe_ok[0:0] $1\oe_ok[0:0] + attribute \src "libresoc.v:132336.5-132336.29" + switch \initial + attribute \src "libresoc.v:132336.9-132336.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:616" + switch \ALU_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 + assign $1\oe_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\oe_ok[0:0] $2\oe_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:633" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $2\oe_ok[0:0] 1'1 + case + assign $2\oe_ok[0:0] 1'0 + end + end + sync always + update \oe_ok $0\oe_ok[0:0] + end +end +attribute \src "libresoc.v:132360.1-132492.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_CR.dec_oe" +attribute \generator "nMigen" +module \dec_oe$141 + attribute \src "libresoc.v:132361.7-132361.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:132450.3-132470.6" + wire $0\oe[0:0] + attribute \src "libresoc.v:132471.3-132491.6" + wire $0\oe_ok[0:0] + attribute \src "libresoc.v:132450.3-132470.6" + wire $1\oe[0:0] + attribute \src "libresoc.v:132471.3-132491.6" + wire $1\oe_ok[0:0] + attribute \src "libresoc.v:132450.3-132470.6" + wire $2\oe[0:0] + attribute \src "libresoc.v:132471.3-132491.6" + wire $2\oe_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire input 2 \CR_OE + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 input 1 \CR_internal_op + attribute \src "libresoc.v:132361.7-132361.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \oe_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:607" + wire width 2 input 3 \sel_in + attribute \src "libresoc.v:132361.7-132361.20" + process $proc$libresoc.v:132361$5052 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:132450.3-132470.6" + process $proc$libresoc.v:132450$5050 + assign { } { } + assign { } { } + assign $0\oe[0:0] $1\oe[0:0] + attribute \src "libresoc.v:132451.5-132451.29" + switch \initial + attribute \src "libresoc.v:132451.9-132451.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:616" + switch \CR_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 + assign $1\oe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\oe[0:0] $2\oe[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:633" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $2\oe[0:0] \CR_OE + case + assign $2\oe[0:0] 1'0 + end + end + sync always + update \oe $0\oe[0:0] + end + attribute \src "libresoc.v:132471.3-132491.6" + process $proc$libresoc.v:132471$5051 + assign { } { } + assign { } { } + assign $0\oe_ok[0:0] $1\oe_ok[0:0] + attribute \src "libresoc.v:132472.5-132472.29" + switch \initial + attribute \src "libresoc.v:132472.9-132472.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:616" + switch \CR_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 + assign $1\oe_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\oe_ok[0:0] $2\oe_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:633" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $2\oe_ok[0:0] 1'1 + case + assign $2\oe_ok[0:0] 1'0 + end + end + sync always + update \oe_ok $0\oe_ok[0:0] + end +end +attribute \src "libresoc.v:132496.1-132628.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_BRANCH.dec_oe" +attribute \generator "nMigen" +module \dec_oe$148 + attribute \src "libresoc.v:132497.7-132497.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:132586.3-132606.6" + wire $0\oe[0:0] + attribute \src "libresoc.v:132607.3-132627.6" + wire $0\oe_ok[0:0] + attribute \src "libresoc.v:132586.3-132606.6" + wire $1\oe[0:0] + attribute \src "libresoc.v:132607.3-132627.6" + wire $1\oe_ok[0:0] + attribute \src "libresoc.v:132586.3-132606.6" + wire $2\oe[0:0] + attribute \src "libresoc.v:132607.3-132627.6" + wire $2\oe_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire input 2 \BRANCH_OE + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 input 1 \BRANCH_internal_op + attribute \src "libresoc.v:132497.7-132497.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \oe_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:607" + wire width 2 input 3 \sel_in + attribute \src "libresoc.v:132497.7-132497.20" + process $proc$libresoc.v:132497$5055 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:132586.3-132606.6" + process $proc$libresoc.v:132586$5053 + assign { } { } + assign { } { } + assign $0\oe[0:0] $1\oe[0:0] + attribute \src "libresoc.v:132587.5-132587.29" + switch \initial + attribute \src "libresoc.v:132587.9-132587.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:616" + switch \BRANCH_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 + assign $1\oe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\oe[0:0] $2\oe[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:633" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $2\oe[0:0] \BRANCH_OE + case + assign $2\oe[0:0] 1'0 + end + end + sync always + update \oe $0\oe[0:0] + end + attribute \src "libresoc.v:132607.3-132627.6" + process $proc$libresoc.v:132607$5054 + assign { } { } + assign { } { } + assign $0\oe_ok[0:0] $1\oe_ok[0:0] + attribute \src "libresoc.v:132608.5-132608.29" + switch \initial + attribute \src "libresoc.v:132608.9-132608.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:616" + switch \BRANCH_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 + assign $1\oe_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\oe_ok[0:0] $2\oe_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:633" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $2\oe_ok[0:0] 1'1 + case + assign $2\oe_ok[0:0] 1'0 + end + end + sync always + update \oe_ok $0\oe_ok[0:0] + end +end +attribute \src "libresoc.v:132632.1-132766.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LOGICAL.dec_oe" +attribute \generator "nMigen" +module \dec_oe$156 + attribute \src "libresoc.v:132633.7-132633.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:132724.3-132744.6" + wire $0\oe[0:0] + attribute \src "libresoc.v:132745.3-132765.6" + wire $0\oe_ok[0:0] + attribute \src "libresoc.v:132724.3-132744.6" + wire $1\oe[0:0] + attribute \src "libresoc.v:132745.3-132765.6" + wire $1\oe_ok[0:0] + attribute \src "libresoc.v:132724.3-132744.6" + wire $2\oe[0:0] + attribute \src "libresoc.v:132745.3-132765.6" + wire $2\oe_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire input 4 \LOGICAL_OE + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 input 1 \LOGICAL_internal_op + attribute \src "libresoc.v:132633.7-132633.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 2 \oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 3 \oe_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:607" + wire width 2 input 5 \sel_in + attribute \src "libresoc.v:132633.7-132633.20" + process $proc$libresoc.v:132633$5058 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:132724.3-132744.6" + process $proc$libresoc.v:132724$5056 + assign { } { } + assign { } { } + assign $0\oe[0:0] $1\oe[0:0] + attribute \src "libresoc.v:132725.5-132725.29" + switch \initial + attribute \src "libresoc.v:132725.9-132725.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:616" + switch \LOGICAL_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 + assign $1\oe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\oe[0:0] $2\oe[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:633" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $2\oe[0:0] \LOGICAL_OE + case + assign $2\oe[0:0] 1'0 + end + end + sync always + update \oe $0\oe[0:0] + end + attribute \src "libresoc.v:132745.3-132765.6" + process $proc$libresoc.v:132745$5057 + assign { } { } + assign { } { } + assign $0\oe_ok[0:0] $1\oe_ok[0:0] + attribute \src "libresoc.v:132746.5-132746.29" + switch \initial + attribute \src "libresoc.v:132746.9-132746.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:616" + switch \LOGICAL_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 + assign $1\oe_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\oe_ok[0:0] $2\oe_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:633" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $2\oe_ok[0:0] 1'1 + case + assign $2\oe_ok[0:0] 1'0 + end + end + sync always + update \oe_ok $0\oe_ok[0:0] + end +end +attribute \src "libresoc.v:132770.1-132902.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SPR.dec_oe" +attribute \generator "nMigen" +module \dec_oe$165 + attribute \src "libresoc.v:132771.7-132771.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:132860.3-132880.6" + wire $0\oe[0:0] + attribute \src "libresoc.v:132881.3-132901.6" + wire $0\oe_ok[0:0] + attribute \src "libresoc.v:132860.3-132880.6" + wire $1\oe[0:0] + attribute \src "libresoc.v:132881.3-132901.6" + wire $1\oe_ok[0:0] + attribute \src "libresoc.v:132860.3-132880.6" + wire $2\oe[0:0] + attribute \src "libresoc.v:132881.3-132901.6" + wire $2\oe_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire input 2 \SPR_OE + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 input 1 \SPR_internal_op + attribute \src "libresoc.v:132771.7-132771.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \oe_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:607" + wire width 2 input 3 \sel_in + attribute \src "libresoc.v:132771.7-132771.20" + process $proc$libresoc.v:132771$5061 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:132860.3-132880.6" + process $proc$libresoc.v:132860$5059 + assign { } { } + assign { } { } + assign $0\oe[0:0] $1\oe[0:0] + attribute \src "libresoc.v:132861.5-132861.29" + switch \initial + attribute \src "libresoc.v:132861.9-132861.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:616" + switch \SPR_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 + assign $1\oe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\oe[0:0] $2\oe[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:633" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $2\oe[0:0] \SPR_OE + case + assign $2\oe[0:0] 1'0 + end + end + sync always + update \oe $0\oe[0:0] + end + attribute \src "libresoc.v:132881.3-132901.6" + process $proc$libresoc.v:132881$5060 + assign { } { } + assign { } { } + assign $0\oe_ok[0:0] $1\oe_ok[0:0] + attribute \src "libresoc.v:132882.5-132882.29" + switch \initial + attribute \src "libresoc.v:132882.9-132882.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:616" + switch \SPR_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 + assign $1\oe_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\oe_ok[0:0] $2\oe_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:633" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $2\oe_ok[0:0] 1'1 + case + assign $2\oe_ok[0:0] 1'0 + end + end + sync always + update \oe_ok $0\oe_ok[0:0] + end +end +attribute \src "libresoc.v:132906.1-133040.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_DIV.dec_oe" +attribute \generator "nMigen" +module \dec_oe$172 + attribute \src "libresoc.v:132907.7-132907.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:132998.3-133018.6" + wire $0\oe[0:0] + attribute \src "libresoc.v:133019.3-133039.6" + wire $0\oe_ok[0:0] + attribute \src "libresoc.v:132998.3-133018.6" + wire $1\oe[0:0] + attribute \src "libresoc.v:133019.3-133039.6" + wire $1\oe_ok[0:0] + attribute \src "libresoc.v:132998.3-133018.6" + wire $2\oe[0:0] + attribute \src "libresoc.v:133019.3-133039.6" + wire $2\oe_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire input 4 \DIV_OE + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 input 1 \DIV_internal_op + attribute \src "libresoc.v:132907.7-132907.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 2 \oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 3 \oe_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:607" + wire width 2 input 5 \sel_in + attribute \src "libresoc.v:132907.7-132907.20" + process $proc$libresoc.v:132907$5064 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:132998.3-133018.6" + process $proc$libresoc.v:132998$5062 + assign { } { } + assign { } { } + assign $0\oe[0:0] $1\oe[0:0] + attribute \src "libresoc.v:132999.5-132999.29" + switch \initial + attribute \src "libresoc.v:132999.9-132999.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:616" + switch \DIV_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 + assign $1\oe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\oe[0:0] $2\oe[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:633" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $2\oe[0:0] \DIV_OE + case + assign $2\oe[0:0] 1'0 + end + end + sync always + update \oe $0\oe[0:0] + end + attribute \src "libresoc.v:133019.3-133039.6" + process $proc$libresoc.v:133019$5063 + assign { } { } + assign { } { } + assign $0\oe_ok[0:0] $1\oe_ok[0:0] + attribute \src "libresoc.v:133020.5-133020.29" + switch \initial + attribute \src "libresoc.v:133020.9-133020.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:616" + switch \DIV_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 + assign $1\oe_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\oe_ok[0:0] $2\oe_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:633" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $2\oe_ok[0:0] 1'1 + case + assign $2\oe_ok[0:0] 1'0 + end + end + sync always + update \oe_ok $0\oe_ok[0:0] + end +end +attribute \src "libresoc.v:133044.1-133178.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_MUL.dec_oe" +attribute \generator "nMigen" +module \dec_oe$181 + attribute \src "libresoc.v:133045.7-133045.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:133136.3-133156.6" + wire $0\oe[0:0] + attribute \src "libresoc.v:133157.3-133177.6" + wire $0\oe_ok[0:0] + attribute \src "libresoc.v:133136.3-133156.6" + wire $1\oe[0:0] + attribute \src "libresoc.v:133157.3-133177.6" + wire $1\oe_ok[0:0] + attribute \src "libresoc.v:133136.3-133156.6" + wire $2\oe[0:0] + attribute \src "libresoc.v:133157.3-133177.6" + wire $2\oe_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire input 4 \MUL_OE + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 input 1 \MUL_internal_op + attribute \src "libresoc.v:133045.7-133045.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 2 \oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 3 \oe_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:607" + wire width 2 input 5 \sel_in + attribute \src "libresoc.v:133045.7-133045.20" + process $proc$libresoc.v:133045$5067 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:133136.3-133156.6" + process $proc$libresoc.v:133136$5065 + assign { } { } + assign { } { } + assign $0\oe[0:0] $1\oe[0:0] + attribute \src "libresoc.v:133137.5-133137.29" + switch \initial + attribute \src "libresoc.v:133137.9-133137.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:616" + switch \MUL_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 + assign $1\oe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\oe[0:0] $2\oe[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:633" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $2\oe[0:0] \MUL_OE + case + assign $2\oe[0:0] 1'0 + end + end + sync always + update \oe $0\oe[0:0] + end + attribute \src "libresoc.v:133157.3-133177.6" + process $proc$libresoc.v:133157$5066 + assign { } { } + assign { } { } + assign $0\oe_ok[0:0] $1\oe_ok[0:0] + attribute \src "libresoc.v:133158.5-133158.29" + switch \initial + attribute \src "libresoc.v:133158.9-133158.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:616" + switch \MUL_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 + assign $1\oe_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\oe_ok[0:0] $2\oe_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:633" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $2\oe_ok[0:0] 1'1 + case + assign $2\oe_ok[0:0] 1'0 + end + end + sync always + update \oe_ok $0\oe_ok[0:0] + end +end +attribute \src "libresoc.v:133182.1-133316.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SHIFT_ROT.dec_oe" +attribute \generator "nMigen" +module \dec_oe$189 + attribute \src "libresoc.v:133183.7-133183.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:133274.3-133294.6" + wire $0\oe[0:0] + attribute \src "libresoc.v:133295.3-133315.6" + wire $0\oe_ok[0:0] + attribute \src "libresoc.v:133274.3-133294.6" + wire $1\oe[0:0] + attribute \src "libresoc.v:133295.3-133315.6" + wire $1\oe_ok[0:0] + attribute \src "libresoc.v:133274.3-133294.6" + wire $2\oe[0:0] + attribute \src "libresoc.v:133295.3-133315.6" + wire $2\oe_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire input 4 \SHIFT_ROT_OE + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 input 1 \SHIFT_ROT_internal_op + attribute \src "libresoc.v:133183.7-133183.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 2 \oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 3 \oe_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:607" + wire width 2 input 5 \sel_in + attribute \src "libresoc.v:133183.7-133183.20" + process $proc$libresoc.v:133183$5070 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:133274.3-133294.6" + process $proc$libresoc.v:133274$5068 + assign { } { } + assign { } { } + assign $0\oe[0:0] $1\oe[0:0] + attribute \src "libresoc.v:133275.5-133275.29" + switch \initial + attribute \src "libresoc.v:133275.9-133275.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:616" + switch \SHIFT_ROT_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 + assign $1\oe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\oe[0:0] $2\oe[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:633" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $2\oe[0:0] \SHIFT_ROT_OE + case + assign $2\oe[0:0] 1'0 + end + end + sync always + update \oe $0\oe[0:0] + end + attribute \src "libresoc.v:133295.3-133315.6" + process $proc$libresoc.v:133295$5069 + assign { } { } + assign { } { } + assign $0\oe_ok[0:0] $1\oe_ok[0:0] + attribute \src "libresoc.v:133296.5-133296.29" + switch \initial + attribute \src "libresoc.v:133296.9-133296.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:616" + switch \SHIFT_ROT_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 + assign $1\oe_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\oe_ok[0:0] $2\oe_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:633" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $2\oe_ok[0:0] 1'1 + case + assign $2\oe_ok[0:0] 1'0 + end + end + sync always + update \oe_ok $0\oe_ok[0:0] + end +end +attribute \src "libresoc.v:133320.1-133454.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec_oe" +attribute \generator "nMigen" +module \dec_oe$197 + attribute \src "libresoc.v:133321.7-133321.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:133412.3-133432.6" + wire $0\oe[0:0] + attribute \src "libresoc.v:133433.3-133453.6" + wire $0\oe_ok[0:0] + attribute \src "libresoc.v:133412.3-133432.6" + wire $1\oe[0:0] + attribute \src "libresoc.v:133433.3-133453.6" + wire $1\oe_ok[0:0] + attribute \src "libresoc.v:133412.3-133432.6" + wire $2\oe[0:0] + attribute \src "libresoc.v:133433.3-133453.6" + wire $2\oe_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire input 4 \LDST_OE + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 input 1 \LDST_internal_op + attribute \src "libresoc.v:133321.7-133321.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 2 \oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 3 \oe_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:607" + wire width 2 input 5 \sel_in + attribute \src "libresoc.v:133321.7-133321.20" + process $proc$libresoc.v:133321$5073 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:133412.3-133432.6" + process $proc$libresoc.v:133412$5071 + assign { } { } + assign { } { } + assign $0\oe[0:0] $1\oe[0:0] + attribute \src "libresoc.v:133413.5-133413.29" + switch \initial + attribute \src "libresoc.v:133413.9-133413.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:616" + switch \LDST_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 + assign $1\oe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\oe[0:0] $2\oe[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:633" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $2\oe[0:0] \LDST_OE + case + assign $2\oe[0:0] 1'0 + end + end + sync always + update \oe $0\oe[0:0] + end + attribute \src "libresoc.v:133433.3-133453.6" + process $proc$libresoc.v:133433$5072 + assign { } { } + assign { } { } + assign $0\oe_ok[0:0] $1\oe_ok[0:0] + attribute \src "libresoc.v:133434.5-133434.29" + switch \initial + attribute \src "libresoc.v:133434.9-133434.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:616" + switch \LDST_internal_op + attribute \src "libresoc.v:0.0-0.0" + case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 + assign $1\oe_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\oe_ok[0:0] $2\oe_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:633" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $2\oe_ok[0:0] 1'1 + case + assign $2\oe_ok[0:0] 1'0 + end + end + sync always + update \oe_ok $0\oe_ok[0:0] + end +end +attribute \src "libresoc.v:133458.1-133592.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_oe" +attribute \generator "nMigen" +module \dec_oe$206 + attribute \src "libresoc.v:133459.7-133459.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:133550.3-133570.6" + wire $0\oe[0:0] + attribute \src "libresoc.v:133571.3-133591.6" + wire $0\oe_ok[0:0] + attribute \src "libresoc.v:133550.3-133570.6" + wire $1\oe[0:0] + attribute \src "libresoc.v:133571.3-133591.6" + wire $1\oe_ok[0:0] + attribute \src "libresoc.v:133550.3-133570.6" + wire $2\oe[0:0] + attribute \src "libresoc.v:133571.3-133591.6" + wire $2\oe_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire input 4 \OE + attribute \src "libresoc.v:133459.7-133459.15" + wire \initial + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:187" + wire width 7 input 1 \internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 2 \oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 3 \oe_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:607" + wire width 2 input 5 \sel_in + attribute \src "libresoc.v:133459.7-133459.20" + process $proc$libresoc.v:133459$5076 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:133550.3-133570.6" + process $proc$libresoc.v:133550$5074 + assign { } { } + assign { } { } + assign $0\oe[0:0] $1\oe[0:0] + attribute \src "libresoc.v:133551.5-133551.29" + switch \initial + attribute \src "libresoc.v:133551.9-133551.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:616" + switch \internal_op + attribute \src "libresoc.v:0.0-0.0" + case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 + assign $1\oe[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\oe[0:0] $2\oe[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:633" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $2\oe[0:0] \OE + case + assign $2\oe[0:0] 1'0 + end + end + sync always + update \oe $0\oe[0:0] + end + attribute \src "libresoc.v:133571.3-133591.6" + process $proc$libresoc.v:133571$5075 + assign { } { } + assign { } { } + assign $0\oe_ok[0:0] $1\oe_ok[0:0] + attribute \src "libresoc.v:133572.5-133572.29" + switch \initial + attribute \src "libresoc.v:133572.9-133572.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:616" + switch \internal_op + attribute \src "libresoc.v:0.0-0.0" + case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 + assign $1\oe_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\oe_ok[0:0] $2\oe_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:633" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $2\oe_ok[0:0] 1'1 + case + assign $2\oe_ok[0:0] 1'0 + end + end + sync always + update \oe_ok $0\oe_ok[0:0] + end +end +attribute \src "libresoc.v:133596.1-133650.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec_rc" +attribute \generator "nMigen" +module \dec_rc + attribute \src "libresoc.v:133597.7-133597.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:133612.3-133630.6" + wire $0\rc[0:0] + attribute \src "libresoc.v:133631.3-133649.6" + wire $0\rc_ok[0:0] + attribute \src "libresoc.v:133612.3-133630.6" + wire $1\rc[0:0] + attribute \src "libresoc.v:133631.3-133649.6" + wire $1\rc_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire input 3 \ALU_Rc + attribute \src "libresoc.v:133597.7-133597.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 1 \rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 2 \rc_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:570" + wire width 2 input 4 \sel_in + attribute \src "libresoc.v:133597.7-133597.20" + process $proc$libresoc.v:133597$5079 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:133612.3-133630.6" + process $proc$libresoc.v:133612$5077 + assign { } { } + assign { } { } + assign $0\rc[0:0] $1\rc[0:0] + attribute \src "libresoc.v:133613.5-133613.29" + switch \initial + attribute \src "libresoc.v:133613.9-133613.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\rc[0:0] \ALU_Rc + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\rc[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\rc[0:0] 1'0 + case + assign $1\rc[0:0] 1'0 + end + sync always + update \rc $0\rc[0:0] + end + attribute \src "libresoc.v:133631.3-133649.6" + process $proc$libresoc.v:133631$5078 + assign { } { } + assign { } { } + assign $0\rc_ok[0:0] $1\rc_ok[0:0] + attribute \src "libresoc.v:133632.5-133632.29" + switch \initial + attribute \src "libresoc.v:133632.9-133632.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\rc_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\rc_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\rc_ok[0:0] 1'1 + case + assign $1\rc_ok[0:0] 1'0 + end + sync always + update \rc_ok $0\rc_ok[0:0] + end +end +attribute \src "libresoc.v:133654.1-133707.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_CR.dec_rc" +attribute \generator "nMigen" +module \dec_rc$140 + attribute \src "libresoc.v:133655.7-133655.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:133669.3-133687.6" + wire $0\rc[0:0] + attribute \src "libresoc.v:133688.3-133706.6" + wire $0\rc_ok[0:0] + attribute \src "libresoc.v:133669.3-133687.6" + wire $1\rc[0:0] + attribute \src "libresoc.v:133688.3-133706.6" + wire $1\rc_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire input 2 \CR_Rc + attribute \src "libresoc.v:133655.7-133655.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 1 \rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \rc_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:570" + wire width 2 input 3 \sel_in + attribute \src "libresoc.v:133655.7-133655.20" + process $proc$libresoc.v:133655$5082 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:133669.3-133687.6" + process $proc$libresoc.v:133669$5080 + assign { } { } + assign { } { } + assign $0\rc[0:0] $1\rc[0:0] + attribute \src "libresoc.v:133670.5-133670.29" + switch \initial + attribute \src "libresoc.v:133670.9-133670.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\rc[0:0] \CR_Rc + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\rc[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\rc[0:0] 1'0 + case + assign $1\rc[0:0] 1'0 + end + sync always + update \rc $0\rc[0:0] + end + attribute \src "libresoc.v:133688.3-133706.6" + process $proc$libresoc.v:133688$5081 + assign { } { } + assign { } { } + assign $0\rc_ok[0:0] $1\rc_ok[0:0] + attribute \src "libresoc.v:133689.5-133689.29" + switch \initial + attribute \src "libresoc.v:133689.9-133689.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\rc_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\rc_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\rc_ok[0:0] 1'1 + case + assign $1\rc_ok[0:0] 1'0 + end + sync always + update \rc_ok $0\rc_ok[0:0] + end +end +attribute \src "libresoc.v:133711.1-133764.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_BRANCH.dec_rc" +attribute \generator "nMigen" +module \dec_rc$147 + attribute \src "libresoc.v:133712.7-133712.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:133726.3-133744.6" + wire $0\rc[0:0] + attribute \src "libresoc.v:133745.3-133763.6" + wire $0\rc_ok[0:0] + attribute \src "libresoc.v:133726.3-133744.6" + wire $1\rc[0:0] + attribute \src "libresoc.v:133745.3-133763.6" + wire $1\rc_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire input 2 \BRANCH_Rc + attribute \src "libresoc.v:133712.7-133712.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 1 \rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \rc_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:570" + wire width 2 input 3 \sel_in + attribute \src "libresoc.v:133712.7-133712.20" + process $proc$libresoc.v:133712$5085 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:133726.3-133744.6" + process $proc$libresoc.v:133726$5083 + assign { } { } + assign { } { } + assign $0\rc[0:0] $1\rc[0:0] + attribute \src "libresoc.v:133727.5-133727.29" + switch \initial + attribute \src "libresoc.v:133727.9-133727.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\rc[0:0] \BRANCH_Rc + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\rc[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\rc[0:0] 1'0 + case + assign $1\rc[0:0] 1'0 + end + sync always + update \rc $0\rc[0:0] + end + attribute \src "libresoc.v:133745.3-133763.6" + process $proc$libresoc.v:133745$5084 + assign { } { } + assign { } { } + assign $0\rc_ok[0:0] $1\rc_ok[0:0] + attribute \src "libresoc.v:133746.5-133746.29" + switch \initial + attribute \src "libresoc.v:133746.9-133746.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\rc_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\rc_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\rc_ok[0:0] 1'1 + case + assign $1\rc_ok[0:0] 1'0 + end + sync always + update \rc_ok $0\rc_ok[0:0] + end +end +attribute \src "libresoc.v:133768.1-133822.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LOGICAL.dec_rc" +attribute \generator "nMigen" +module \dec_rc$155 + attribute \src "libresoc.v:133769.7-133769.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:133784.3-133802.6" + wire $0\rc[0:0] + attribute \src "libresoc.v:133803.3-133821.6" + wire $0\rc_ok[0:0] + attribute \src "libresoc.v:133784.3-133802.6" + wire $1\rc[0:0] + attribute \src "libresoc.v:133803.3-133821.6" + wire $1\rc_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire input 3 \LOGICAL_Rc + attribute \src "libresoc.v:133769.7-133769.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 1 \rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 2 \rc_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:570" + wire width 2 input 4 \sel_in + attribute \src "libresoc.v:133769.7-133769.20" + process $proc$libresoc.v:133769$5088 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:133784.3-133802.6" + process $proc$libresoc.v:133784$5086 + assign { } { } + assign { } { } + assign $0\rc[0:0] $1\rc[0:0] + attribute \src "libresoc.v:133785.5-133785.29" + switch \initial + attribute \src "libresoc.v:133785.9-133785.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\rc[0:0] \LOGICAL_Rc + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\rc[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\rc[0:0] 1'0 + case + assign $1\rc[0:0] 1'0 + end + sync always + update \rc $0\rc[0:0] + end + attribute \src "libresoc.v:133803.3-133821.6" + process $proc$libresoc.v:133803$5087 + assign { } { } + assign { } { } + assign $0\rc_ok[0:0] $1\rc_ok[0:0] + attribute \src "libresoc.v:133804.5-133804.29" + switch \initial + attribute \src "libresoc.v:133804.9-133804.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\rc_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\rc_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\rc_ok[0:0] 1'1 + case + assign $1\rc_ok[0:0] 1'0 + end + sync always + update \rc_ok $0\rc_ok[0:0] + end +end +attribute \src "libresoc.v:133826.1-133879.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SPR.dec_rc" +attribute \generator "nMigen" +module \dec_rc$164 + attribute \src "libresoc.v:133827.7-133827.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:133841.3-133859.6" + wire $0\rc[0:0] + attribute \src "libresoc.v:133860.3-133878.6" + wire $0\rc_ok[0:0] + attribute \src "libresoc.v:133841.3-133859.6" + wire $1\rc[0:0] + attribute \src "libresoc.v:133860.3-133878.6" + wire $1\rc_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire input 2 \SPR_Rc + attribute \src "libresoc.v:133827.7-133827.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 1 \rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \rc_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:570" + wire width 2 input 3 \sel_in + attribute \src "libresoc.v:133827.7-133827.20" + process $proc$libresoc.v:133827$5091 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:133841.3-133859.6" + process $proc$libresoc.v:133841$5089 + assign { } { } + assign { } { } + assign $0\rc[0:0] $1\rc[0:0] + attribute \src "libresoc.v:133842.5-133842.29" + switch \initial + attribute \src "libresoc.v:133842.9-133842.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\rc[0:0] \SPR_Rc + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\rc[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\rc[0:0] 1'0 + case + assign $1\rc[0:0] 1'0 + end + sync always + update \rc $0\rc[0:0] + end + attribute \src "libresoc.v:133860.3-133878.6" + process $proc$libresoc.v:133860$5090 + assign { } { } + assign { } { } + assign $0\rc_ok[0:0] $1\rc_ok[0:0] + attribute \src "libresoc.v:133861.5-133861.29" + switch \initial + attribute \src "libresoc.v:133861.9-133861.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\rc_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\rc_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\rc_ok[0:0] 1'1 + case + assign $1\rc_ok[0:0] 1'0 + end + sync always + update \rc_ok $0\rc_ok[0:0] + end +end +attribute \src "libresoc.v:133883.1-133937.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_DIV.dec_rc" +attribute \generator "nMigen" +module \dec_rc$171 + attribute \src "libresoc.v:133884.7-133884.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:133899.3-133917.6" + wire $0\rc[0:0] + attribute \src "libresoc.v:133918.3-133936.6" + wire $0\rc_ok[0:0] + attribute \src "libresoc.v:133899.3-133917.6" + wire $1\rc[0:0] + attribute \src "libresoc.v:133918.3-133936.6" + wire $1\rc_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire input 3 \DIV_Rc + attribute \src "libresoc.v:133884.7-133884.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 1 \rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 2 \rc_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:570" + wire width 2 input 4 \sel_in + attribute \src "libresoc.v:133884.7-133884.20" + process $proc$libresoc.v:133884$5094 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:133899.3-133917.6" + process $proc$libresoc.v:133899$5092 + assign { } { } + assign { } { } + assign $0\rc[0:0] $1\rc[0:0] + attribute \src "libresoc.v:133900.5-133900.29" + switch \initial + attribute \src "libresoc.v:133900.9-133900.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\rc[0:0] \DIV_Rc + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\rc[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\rc[0:0] 1'0 + case + assign $1\rc[0:0] 1'0 + end + sync always + update \rc $0\rc[0:0] + end + attribute \src "libresoc.v:133918.3-133936.6" + process $proc$libresoc.v:133918$5093 + assign { } { } + assign { } { } + assign $0\rc_ok[0:0] $1\rc_ok[0:0] + attribute \src "libresoc.v:133919.5-133919.29" + switch \initial + attribute \src "libresoc.v:133919.9-133919.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\rc_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\rc_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\rc_ok[0:0] 1'1 + case + assign $1\rc_ok[0:0] 1'0 + end + sync always + update \rc_ok $0\rc_ok[0:0] + end +end +attribute \src "libresoc.v:133941.1-133995.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_MUL.dec_rc" +attribute \generator "nMigen" +module \dec_rc$180 + attribute \src "libresoc.v:133942.7-133942.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:133957.3-133975.6" + wire $0\rc[0:0] + attribute \src "libresoc.v:133976.3-133994.6" + wire $0\rc_ok[0:0] + attribute \src "libresoc.v:133957.3-133975.6" + wire $1\rc[0:0] + attribute \src "libresoc.v:133976.3-133994.6" + wire $1\rc_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire input 3 \MUL_Rc + attribute \src "libresoc.v:133942.7-133942.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 1 \rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 2 \rc_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:570" + wire width 2 input 4 \sel_in + attribute \src "libresoc.v:133942.7-133942.20" + process $proc$libresoc.v:133942$5097 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:133957.3-133975.6" + process $proc$libresoc.v:133957$5095 + assign { } { } + assign { } { } + assign $0\rc[0:0] $1\rc[0:0] + attribute \src "libresoc.v:133958.5-133958.29" + switch \initial + attribute \src "libresoc.v:133958.9-133958.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\rc[0:0] \MUL_Rc + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\rc[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\rc[0:0] 1'0 + case + assign $1\rc[0:0] 1'0 + end + sync always + update \rc $0\rc[0:0] + end + attribute \src "libresoc.v:133976.3-133994.6" + process $proc$libresoc.v:133976$5096 + assign { } { } + assign { } { } + assign $0\rc_ok[0:0] $1\rc_ok[0:0] + attribute \src "libresoc.v:133977.5-133977.29" + switch \initial + attribute \src "libresoc.v:133977.9-133977.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\rc_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\rc_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\rc_ok[0:0] 1'1 + case + assign $1\rc_ok[0:0] 1'0 + end + sync always + update \rc_ok $0\rc_ok[0:0] + end +end +attribute \src "libresoc.v:133999.1-134053.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SHIFT_ROT.dec_rc" +attribute \generator "nMigen" +module \dec_rc$188 + attribute \src "libresoc.v:134000.7-134000.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:134015.3-134033.6" + wire $0\rc[0:0] + attribute \src "libresoc.v:134034.3-134052.6" + wire $0\rc_ok[0:0] + attribute \src "libresoc.v:134015.3-134033.6" + wire $1\rc[0:0] + attribute \src "libresoc.v:134034.3-134052.6" + wire $1\rc_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire input 3 \SHIFT_ROT_Rc + attribute \src "libresoc.v:134000.7-134000.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 1 \rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 2 \rc_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:570" + wire width 2 input 4 \sel_in + attribute \src "libresoc.v:134000.7-134000.20" + process $proc$libresoc.v:134000$5100 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:134015.3-134033.6" + process $proc$libresoc.v:134015$5098 + assign { } { } + assign { } { } + assign $0\rc[0:0] $1\rc[0:0] + attribute \src "libresoc.v:134016.5-134016.29" + switch \initial + attribute \src "libresoc.v:134016.9-134016.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\rc[0:0] \SHIFT_ROT_Rc + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\rc[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\rc[0:0] 1'0 + case + assign $1\rc[0:0] 1'0 + end + sync always + update \rc $0\rc[0:0] + end + attribute \src "libresoc.v:134034.3-134052.6" + process $proc$libresoc.v:134034$5099 + assign { } { } + assign { } { } + assign $0\rc_ok[0:0] $1\rc_ok[0:0] + attribute \src "libresoc.v:134035.5-134035.29" + switch \initial + attribute \src "libresoc.v:134035.9-134035.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\rc_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\rc_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\rc_ok[0:0] 1'1 + case + assign $1\rc_ok[0:0] 1'0 + end + sync always + update \rc_ok $0\rc_ok[0:0] + end +end +attribute \src "libresoc.v:134057.1-134111.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec_rc" +attribute \generator "nMigen" +module \dec_rc$196 + attribute \src "libresoc.v:134058.7-134058.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:134073.3-134091.6" + wire $0\rc[0:0] + attribute \src "libresoc.v:134092.3-134110.6" + wire $0\rc_ok[0:0] + attribute \src "libresoc.v:134073.3-134091.6" + wire $1\rc[0:0] + attribute \src "libresoc.v:134092.3-134110.6" + wire $1\rc_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire input 3 \LDST_Rc + attribute \src "libresoc.v:134058.7-134058.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 1 \rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 2 \rc_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:570" + wire width 2 input 4 \sel_in + attribute \src "libresoc.v:134058.7-134058.20" + process $proc$libresoc.v:134058$5103 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:134073.3-134091.6" + process $proc$libresoc.v:134073$5101 + assign { } { } + assign { } { } + assign $0\rc[0:0] $1\rc[0:0] + attribute \src "libresoc.v:134074.5-134074.29" + switch \initial + attribute \src "libresoc.v:134074.9-134074.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\rc[0:0] \LDST_Rc + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\rc[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\rc[0:0] 1'0 + case + assign $1\rc[0:0] 1'0 + end + sync always + update \rc $0\rc[0:0] + end + attribute \src "libresoc.v:134092.3-134110.6" + process $proc$libresoc.v:134092$5102 + assign { } { } + assign { } { } + assign $0\rc_ok[0:0] $1\rc_ok[0:0] + attribute \src "libresoc.v:134093.5-134093.29" + switch \initial + attribute \src "libresoc.v:134093.9-134093.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\rc_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\rc_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\rc_ok[0:0] 1'1 + case + assign $1\rc_ok[0:0] 1'0 + end + sync always + update \rc_ok $0\rc_ok[0:0] + end +end +attribute \src "libresoc.v:134115.1-134169.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_rc" +attribute \generator "nMigen" +module \dec_rc$205 + attribute \src "libresoc.v:134116.7-134116.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:134131.3-134149.6" + wire $0\rc[0:0] + attribute \src "libresoc.v:134150.3-134168.6" + wire $0\rc_ok[0:0] + attribute \src "libresoc.v:134131.3-134149.6" + wire $1\rc[0:0] + attribute \src "libresoc.v:134150.3-134168.6" + wire $1\rc_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:468" + wire input 3 \Rc + attribute \src "libresoc.v:134116.7-134116.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 1 \rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 2 \rc_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:570" + wire width 2 input 4 \sel_in + attribute \src "libresoc.v:134116.7-134116.20" + process $proc$libresoc.v:134116$5106 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:134131.3-134149.6" + process $proc$libresoc.v:134131$5104 + assign { } { } + assign { } { } + assign $0\rc[0:0] $1\rc[0:0] + attribute \src "libresoc.v:134132.5-134132.29" + switch \initial + attribute \src "libresoc.v:134132.9-134132.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\rc[0:0] \Rc + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\rc[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\rc[0:0] 1'0 + case + assign $1\rc[0:0] 1'0 + end + sync always + update \rc $0\rc[0:0] + end + attribute \src "libresoc.v:134150.3-134168.6" + process $proc$libresoc.v:134150$5105 + assign { } { } + assign { } { } + assign $0\rc_ok[0:0] $1\rc_ok[0:0] + attribute \src "libresoc.v:134151.5-134151.29" + switch \initial + attribute \src "libresoc.v:134151.9-134151.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + switch \sel_in + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\rc_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\rc_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\rc_ok[0:0] 1'1 + case + assign $1\rc_ok[0:0] 1'0 + end + sync always + update \rc_ok $0\rc_ok[0:0] + end +end +attribute \src "libresoc.v:134173.1-135413.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0" +attribute \generator "nMigen" +module \div0 + attribute \src "libresoc.v:134970.3-134971.25" + wire $0\all_rd_dly[0:0] + attribute \src "libresoc.v:135157.3-135195.6" + wire width 4 $0\alu_div0_logical_op__data_len$next[3:0]$5246 + attribute \src "libresoc.v:134942.3-134943.75" + wire width 4 $0\alu_div0_logical_op__data_len[3:0] + attribute \src "libresoc.v:135157.3-135195.6" + wire width 13 $0\alu_div0_logical_op__fn_unit$next[12:0]$5247 + attribute \src "libresoc.v:134912.3-134913.73" + wire width 13 $0\alu_div0_logical_op__fn_unit[12:0] + attribute \src "libresoc.v:135157.3-135195.6" + wire width 64 $0\alu_div0_logical_op__imm_data__data$next[63:0]$5248 + attribute \src "libresoc.v:134914.3-134915.87" + wire width 64 $0\alu_div0_logical_op__imm_data__data[63:0] + attribute \src "libresoc.v:135157.3-135195.6" + wire $0\alu_div0_logical_op__imm_data__ok$next[0:0]$5249 + attribute \src "libresoc.v:134916.3-134917.83" + wire $0\alu_div0_logical_op__imm_data__ok[0:0] + attribute \src "libresoc.v:135157.3-135195.6" + wire width 2 $0\alu_div0_logical_op__input_carry$next[1:0]$5250 + attribute \src "libresoc.v:134930.3-134931.81" + wire width 2 $0\alu_div0_logical_op__input_carry[1:0] + attribute \src "libresoc.v:135157.3-135195.6" + wire width 32 $0\alu_div0_logical_op__insn$next[31:0]$5251 + attribute \src "libresoc.v:134944.3-134945.67" + wire width 32 $0\alu_div0_logical_op__insn[31:0] + attribute \src "libresoc.v:135157.3-135195.6" + wire width 7 $0\alu_div0_logical_op__insn_type$next[6:0]$5252 + attribute \src "libresoc.v:134910.3-134911.77" + wire width 7 $0\alu_div0_logical_op__insn_type[6:0] + attribute \src "libresoc.v:135157.3-135195.6" + wire $0\alu_div0_logical_op__invert_in$next[0:0]$5253 + attribute \src "libresoc.v:134926.3-134927.77" + wire $0\alu_div0_logical_op__invert_in[0:0] + attribute \src "libresoc.v:135157.3-135195.6" + wire $0\alu_div0_logical_op__invert_out$next[0:0]$5254 + attribute \src "libresoc.v:134932.3-134933.79" + wire $0\alu_div0_logical_op__invert_out[0:0] + attribute \src "libresoc.v:135157.3-135195.6" + wire $0\alu_div0_logical_op__is_32bit$next[0:0]$5255 + attribute \src "libresoc.v:134938.3-134939.75" + wire $0\alu_div0_logical_op__is_32bit[0:0] + attribute \src "libresoc.v:135157.3-135195.6" + wire $0\alu_div0_logical_op__is_signed$next[0:0]$5256 + attribute \src "libresoc.v:134940.3-134941.77" + wire $0\alu_div0_logical_op__is_signed[0:0] + attribute \src "libresoc.v:135157.3-135195.6" + wire $0\alu_div0_logical_op__oe__oe$next[0:0]$5257 + attribute \src "libresoc.v:134922.3-134923.71" + wire $0\alu_div0_logical_op__oe__oe[0:0] + attribute \src "libresoc.v:135157.3-135195.6" + wire $0\alu_div0_logical_op__oe__ok$next[0:0]$5258 + attribute \src "libresoc.v:134924.3-134925.71" + wire $0\alu_div0_logical_op__oe__ok[0:0] + attribute \src "libresoc.v:135157.3-135195.6" + wire $0\alu_div0_logical_op__output_carry$next[0:0]$5259 + attribute \src "libresoc.v:134936.3-134937.83" + wire $0\alu_div0_logical_op__output_carry[0:0] + attribute \src "libresoc.v:135157.3-135195.6" + wire $0\alu_div0_logical_op__rc__ok$next[0:0]$5260 + attribute \src "libresoc.v:134920.3-134921.71" + wire $0\alu_div0_logical_op__rc__ok[0:0] + attribute \src "libresoc.v:135157.3-135195.6" + wire $0\alu_div0_logical_op__rc__rc$next[0:0]$5261 + attribute \src "libresoc.v:134918.3-134919.71" + wire $0\alu_div0_logical_op__rc__rc[0:0] + attribute \src "libresoc.v:135157.3-135195.6" + wire $0\alu_div0_logical_op__write_cr0$next[0:0]$5262 + attribute \src "libresoc.v:134934.3-134935.77" + wire $0\alu_div0_logical_op__write_cr0[0:0] + attribute \src "libresoc.v:135157.3-135195.6" + wire $0\alu_div0_logical_op__zero_a$next[0:0]$5263 + attribute \src "libresoc.v:134928.3-134929.71" + wire $0\alu_div0_logical_op__zero_a[0:0] + attribute \src "libresoc.v:134968.3-134969.40" + wire $0\alu_done_dly[0:0] + attribute \src "libresoc.v:135323.3-135331.6" + wire $0\alu_l_r_alu$next[0:0]$5333 + attribute \src "libresoc.v:134884.3-134885.39" + wire $0\alu_l_r_alu[0:0] + attribute \src "libresoc.v:135314.3-135322.6" + wire $0\alui_l_r_alui$next[0:0]$5330 + attribute \src "libresoc.v:134886.3-134887.43" + wire $0\alui_l_r_alui[0:0] + attribute \src "libresoc.v:135196.3-135217.6" + wire width 64 $0\data_r0__o$next[63:0]$5289 + attribute \src "libresoc.v:134906.3-134907.37" + wire width 64 $0\data_r0__o[63:0] + attribute \src "libresoc.v:135196.3-135217.6" + wire $0\data_r0__o_ok$next[0:0]$5290 + attribute \src "libresoc.v:134908.3-134909.43" + wire $0\data_r0__o_ok[0:0] + attribute \src "libresoc.v:135218.3-135239.6" + wire width 4 $0\data_r1__cr_a$next[3:0]$5297 + attribute \src "libresoc.v:134902.3-134903.43" + wire width 4 $0\data_r1__cr_a[3:0] + attribute \src "libresoc.v:135218.3-135239.6" + wire $0\data_r1__cr_a_ok$next[0:0]$5298 + attribute \src "libresoc.v:134904.3-134905.49" + wire $0\data_r1__cr_a_ok[0:0] + attribute \src "libresoc.v:135240.3-135261.6" + wire width 2 $0\data_r2__xer_ov$next[1:0]$5305 + attribute \src "libresoc.v:134898.3-134899.47" + wire width 2 $0\data_r2__xer_ov[1:0] + attribute \src "libresoc.v:135240.3-135261.6" + wire $0\data_r2__xer_ov_ok$next[0:0]$5306 + attribute \src "libresoc.v:134900.3-134901.53" + wire $0\data_r2__xer_ov_ok[0:0] + attribute \src "libresoc.v:135262.3-135283.6" + wire $0\data_r3__xer_so$next[0:0]$5313 + attribute \src "libresoc.v:134894.3-134895.47" + wire $0\data_r3__xer_so[0:0] + attribute \src "libresoc.v:135262.3-135283.6" + wire $0\data_r3__xer_so_ok$next[0:0]$5314 + attribute \src "libresoc.v:134896.3-134897.53" + wire $0\data_r3__xer_so_ok[0:0] + attribute \src "libresoc.v:135332.3-135341.6" + wire width 64 $0\dest1_o[63:0] + attribute \src "libresoc.v:135342.3-135351.6" + wire width 4 $0\dest2_o[3:0] + attribute \src "libresoc.v:135352.3-135361.6" + wire width 2 $0\dest3_o[1:0] + attribute \src "libresoc.v:135362.3-135371.6" + wire $0\dest4_o[0:0] + attribute \src "libresoc.v:134174.7-134174.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:135112.3-135120.6" + wire $0\opc_l_r_opc$next[0:0]$5231 + attribute \src "libresoc.v:134954.3-134955.39" + wire $0\opc_l_r_opc[0:0] + attribute \src "libresoc.v:135103.3-135111.6" + wire $0\opc_l_s_opc$next[0:0]$5228 + attribute \src "libresoc.v:134956.3-134957.39" + wire $0\opc_l_s_opc[0:0] + attribute \src "libresoc.v:135372.3-135380.6" + wire width 4 $0\prev_wr_go$next[3:0]$5340 + attribute \src "libresoc.v:134966.3-134967.37" + wire width 4 $0\prev_wr_go[3:0] + attribute \src "libresoc.v:135057.3-135066.6" + wire $0\req_done[0:0] + attribute \src "libresoc.v:135148.3-135156.6" + wire width 4 $0\req_l_r_req$next[3:0]$5243 + attribute \src "libresoc.v:134946.3-134947.39" + wire width 4 $0\req_l_r_req[3:0] + attribute \src "libresoc.v:135139.3-135147.6" + wire width 4 $0\req_l_s_req$next[3:0]$5240 + attribute \src "libresoc.v:134948.3-134949.39" + wire width 4 $0\req_l_s_req[3:0] + attribute \src "libresoc.v:135076.3-135084.6" + wire $0\rok_l_r_rdok$next[0:0]$5219 + attribute \src "libresoc.v:134962.3-134963.41" + wire $0\rok_l_r_rdok[0:0] + attribute \src "libresoc.v:135067.3-135075.6" + wire $0\rok_l_s_rdok$next[0:0]$5216 + attribute \src "libresoc.v:134964.3-134965.41" + wire $0\rok_l_s_rdok[0:0] + attribute \src "libresoc.v:135094.3-135102.6" + wire $0\rst_l_r_rst$next[0:0]$5225 + attribute \src "libresoc.v:134958.3-134959.39" + wire $0\rst_l_r_rst[0:0] + attribute \src "libresoc.v:135085.3-135093.6" + wire $0\rst_l_s_rst$next[0:0]$5222 + attribute \src "libresoc.v:134960.3-134961.39" + wire $0\rst_l_s_rst[0:0] + attribute \src "libresoc.v:135130.3-135138.6" + wire width 3 $0\src_l_r_src$next[2:0]$5237 + attribute \src "libresoc.v:134950.3-134951.39" + wire width 3 $0\src_l_r_src[2:0] + attribute \src "libresoc.v:135121.3-135129.6" + wire width 3 $0\src_l_s_src$next[2:0]$5234 + attribute \src "libresoc.v:134952.3-134953.39" + wire width 3 $0\src_l_s_src[2:0] + attribute \src "libresoc.v:135284.3-135293.6" + wire width 64 $0\src_r0$next[63:0]$5321 + attribute \src "libresoc.v:134892.3-134893.29" + wire width 64 $0\src_r0[63:0] + attribute \src "libresoc.v:135294.3-135303.6" + wire width 64 $0\src_r1$next[63:0]$5324 + attribute \src "libresoc.v:134890.3-134891.29" + wire width 64 $0\src_r1[63:0] + attribute \src "libresoc.v:135304.3-135313.6" + wire $0\src_r2$next[0:0]$5327 + attribute \src "libresoc.v:134888.3-134889.29" + wire $0\src_r2[0:0] + attribute \src "libresoc.v:134304.7-134304.24" + wire $1\all_rd_dly[0:0] + attribute \src "libresoc.v:135157.3-135195.6" + wire width 4 $1\alu_div0_logical_op__data_len$next[3:0]$5264 + attribute \src "libresoc.v:134314.13-134314.49" + wire width 4 $1\alu_div0_logical_op__data_len[3:0] + attribute \src "libresoc.v:135157.3-135195.6" + wire width 13 $1\alu_div0_logical_op__fn_unit$next[12:0]$5265 + attribute \src "libresoc.v:134332.14-134332.53" + wire width 13 $1\alu_div0_logical_op__fn_unit[12:0] + attribute \src "libresoc.v:135157.3-135195.6" + wire width 64 $1\alu_div0_logical_op__imm_data__data$next[63:0]$5266 + attribute \src "libresoc.v:134336.14-134336.72" + wire width 64 $1\alu_div0_logical_op__imm_data__data[63:0] + attribute \src "libresoc.v:135157.3-135195.6" + wire $1\alu_div0_logical_op__imm_data__ok$next[0:0]$5267 + attribute \src "libresoc.v:134340.7-134340.47" + wire $1\alu_div0_logical_op__imm_data__ok[0:0] + attribute \src "libresoc.v:135157.3-135195.6" + wire width 2 $1\alu_div0_logical_op__input_carry$next[1:0]$5268 + attribute \src "libresoc.v:134348.13-134348.52" + wire width 2 $1\alu_div0_logical_op__input_carry[1:0] + attribute \src "libresoc.v:135157.3-135195.6" + wire width 32 $1\alu_div0_logical_op__insn$next[31:0]$5269 + attribute \src "libresoc.v:134352.14-134352.47" + wire width 32 $1\alu_div0_logical_op__insn[31:0] + attribute \src "libresoc.v:135157.3-135195.6" + wire width 7 $1\alu_div0_logical_op__insn_type$next[6:0]$5270 + attribute \src "libresoc.v:134430.13-134430.51" + wire width 7 $1\alu_div0_logical_op__insn_type[6:0] + attribute \src "libresoc.v:135157.3-135195.6" + wire $1\alu_div0_logical_op__invert_in$next[0:0]$5271 + attribute \src "libresoc.v:134434.7-134434.44" + wire $1\alu_div0_logical_op__invert_in[0:0] + attribute \src "libresoc.v:135157.3-135195.6" + wire $1\alu_div0_logical_op__invert_out$next[0:0]$5272 + attribute \src "libresoc.v:134438.7-134438.45" + wire $1\alu_div0_logical_op__invert_out[0:0] + attribute \src "libresoc.v:135157.3-135195.6" + wire $1\alu_div0_logical_op__is_32bit$next[0:0]$5273 + attribute \src "libresoc.v:134442.7-134442.43" + wire $1\alu_div0_logical_op__is_32bit[0:0] + attribute \src "libresoc.v:135157.3-135195.6" + wire $1\alu_div0_logical_op__is_signed$next[0:0]$5274 + attribute \src "libresoc.v:134446.7-134446.44" + wire $1\alu_div0_logical_op__is_signed[0:0] + attribute \src "libresoc.v:135157.3-135195.6" + wire $1\alu_div0_logical_op__oe__oe$next[0:0]$5275 + attribute \src "libresoc.v:134450.7-134450.41" + wire $1\alu_div0_logical_op__oe__oe[0:0] + attribute \src "libresoc.v:135157.3-135195.6" + wire $1\alu_div0_logical_op__oe__ok$next[0:0]$5276 + attribute \src "libresoc.v:134454.7-134454.41" + wire $1\alu_div0_logical_op__oe__ok[0:0] + attribute \src "libresoc.v:135157.3-135195.6" + wire $1\alu_div0_logical_op__output_carry$next[0:0]$5277 + attribute \src "libresoc.v:134458.7-134458.47" + wire $1\alu_div0_logical_op__output_carry[0:0] + attribute \src "libresoc.v:135157.3-135195.6" + wire $1\alu_div0_logical_op__rc__ok$next[0:0]$5278 + attribute \src "libresoc.v:134462.7-134462.41" + wire $1\alu_div0_logical_op__rc__ok[0:0] + attribute \src "libresoc.v:135157.3-135195.6" + wire $1\alu_div0_logical_op__rc__rc$next[0:0]$5279 + attribute \src "libresoc.v:134466.7-134466.41" + wire $1\alu_div0_logical_op__rc__rc[0:0] + attribute \src "libresoc.v:135157.3-135195.6" + wire $1\alu_div0_logical_op__write_cr0$next[0:0]$5280 + attribute \src "libresoc.v:134470.7-134470.44" + wire $1\alu_div0_logical_op__write_cr0[0:0] + attribute \src "libresoc.v:135157.3-135195.6" + wire $1\alu_div0_logical_op__zero_a$next[0:0]$5281 + attribute \src "libresoc.v:134474.7-134474.41" + wire $1\alu_div0_logical_op__zero_a[0:0] + attribute \src "libresoc.v:134500.7-134500.26" + wire $1\alu_done_dly[0:0] + attribute \src "libresoc.v:135323.3-135331.6" + wire $1\alu_l_r_alu$next[0:0]$5334 + attribute \src "libresoc.v:134508.7-134508.25" + wire $1\alu_l_r_alu[0:0] + attribute \src "libresoc.v:135314.3-135322.6" + wire $1\alui_l_r_alui$next[0:0]$5331 + attribute \src "libresoc.v:134520.7-134520.27" + wire $1\alui_l_r_alui[0:0] + attribute \src "libresoc.v:135196.3-135217.6" + wire width 64 $1\data_r0__o$next[63:0]$5291 + attribute \src "libresoc.v:134554.14-134554.47" + wire width 64 $1\data_r0__o[63:0] + attribute \src "libresoc.v:135196.3-135217.6" + wire $1\data_r0__o_ok$next[0:0]$5292 + attribute \src "libresoc.v:134558.7-134558.27" + wire $1\data_r0__o_ok[0:0] + attribute \src "libresoc.v:135218.3-135239.6" + wire width 4 $1\data_r1__cr_a$next[3:0]$5299 + attribute \src "libresoc.v:134562.13-134562.33" + wire width 4 $1\data_r1__cr_a[3:0] + attribute \src "libresoc.v:135218.3-135239.6" + wire $1\data_r1__cr_a_ok$next[0:0]$5300 + attribute \src "libresoc.v:134566.7-134566.30" + wire $1\data_r1__cr_a_ok[0:0] + attribute \src "libresoc.v:135240.3-135261.6" + wire width 2 $1\data_r2__xer_ov$next[1:0]$5307 + attribute \src "libresoc.v:134570.13-134570.35" + wire width 2 $1\data_r2__xer_ov[1:0] + attribute \src "libresoc.v:135240.3-135261.6" + wire $1\data_r2__xer_ov_ok$next[0:0]$5308 + attribute \src "libresoc.v:134574.7-134574.32" + wire $1\data_r2__xer_ov_ok[0:0] + attribute \src "libresoc.v:135262.3-135283.6" + wire $1\data_r3__xer_so$next[0:0]$5315 + attribute \src "libresoc.v:134578.7-134578.29" + wire $1\data_r3__xer_so[0:0] + attribute \src "libresoc.v:135262.3-135283.6" + wire $1\data_r3__xer_so_ok$next[0:0]$5316 + attribute \src "libresoc.v:134582.7-134582.32" + wire $1\data_r3__xer_so_ok[0:0] + attribute \src "libresoc.v:135332.3-135341.6" + wire width 64 $1\dest1_o[63:0] + attribute \src "libresoc.v:135342.3-135351.6" + wire width 4 $1\dest2_o[3:0] + attribute \src "libresoc.v:135352.3-135361.6" + wire width 2 $1\dest3_o[1:0] + attribute \src "libresoc.v:135362.3-135371.6" + wire $1\dest4_o[0:0] + attribute \src "libresoc.v:135112.3-135120.6" + wire $1\opc_l_r_opc$next[0:0]$5232 + attribute \src "libresoc.v:134602.7-134602.25" + wire $1\opc_l_r_opc[0:0] + attribute \src "libresoc.v:135103.3-135111.6" + wire $1\opc_l_s_opc$next[0:0]$5229 + attribute \src "libresoc.v:134606.7-134606.25" + wire $1\opc_l_s_opc[0:0] + attribute \src "libresoc.v:135372.3-135380.6" + wire width 4 $1\prev_wr_go$next[3:0]$5341 + attribute \src "libresoc.v:134738.13-134738.30" + wire width 4 $1\prev_wr_go[3:0] + attribute \src "libresoc.v:135057.3-135066.6" + wire $1\req_done[0:0] + attribute \src "libresoc.v:135148.3-135156.6" + wire width 4 $1\req_l_r_req$next[3:0]$5244 + attribute \src "libresoc.v:134746.13-134746.31" + wire width 4 $1\req_l_r_req[3:0] + attribute \src "libresoc.v:135139.3-135147.6" + wire width 4 $1\req_l_s_req$next[3:0]$5241 + attribute \src "libresoc.v:134750.13-134750.31" + wire width 4 $1\req_l_s_req[3:0] + attribute \src "libresoc.v:135076.3-135084.6" + wire $1\rok_l_r_rdok$next[0:0]$5220 + attribute \src "libresoc.v:134762.7-134762.26" + wire $1\rok_l_r_rdok[0:0] + attribute \src "libresoc.v:135067.3-135075.6" + wire $1\rok_l_s_rdok$next[0:0]$5217 + attribute \src "libresoc.v:134766.7-134766.26" + wire $1\rok_l_s_rdok[0:0] + attribute \src "libresoc.v:135094.3-135102.6" + wire $1\rst_l_r_rst$next[0:0]$5226 + attribute \src "libresoc.v:134770.7-134770.25" + wire $1\rst_l_r_rst[0:0] + attribute \src "libresoc.v:135085.3-135093.6" + wire $1\rst_l_s_rst$next[0:0]$5223 + attribute \src "libresoc.v:134774.7-134774.25" + wire $1\rst_l_s_rst[0:0] + attribute \src "libresoc.v:135130.3-135138.6" + wire width 3 $1\src_l_r_src$next[2:0]$5238 + attribute \src "libresoc.v:134788.13-134788.31" + wire width 3 $1\src_l_r_src[2:0] + attribute \src "libresoc.v:135121.3-135129.6" + wire width 3 $1\src_l_s_src$next[2:0]$5235 + attribute \src "libresoc.v:134792.13-134792.31" + wire width 3 $1\src_l_s_src[2:0] + attribute \src "libresoc.v:135284.3-135293.6" + wire width 64 $1\src_r0$next[63:0]$5322 + attribute \src "libresoc.v:134800.14-134800.43" + wire width 64 $1\src_r0[63:0] + attribute \src "libresoc.v:135294.3-135303.6" + wire width 64 $1\src_r1$next[63:0]$5325 + attribute \src "libresoc.v:134804.14-134804.43" + wire width 64 $1\src_r1[63:0] + attribute \src "libresoc.v:135304.3-135313.6" + wire $1\src_r2$next[0:0]$5328 + attribute \src "libresoc.v:134808.7-134808.20" + wire $1\src_r2[0:0] + attribute \src "libresoc.v:135157.3-135195.6" + wire width 64 $2\alu_div0_logical_op__imm_data__data$next[63:0]$5282 + attribute \src "libresoc.v:135157.3-135195.6" + wire $2\alu_div0_logical_op__imm_data__ok$next[0:0]$5283 + attribute \src "libresoc.v:135157.3-135195.6" + wire $2\alu_div0_logical_op__oe__oe$next[0:0]$5284 + attribute \src "libresoc.v:135157.3-135195.6" + wire $2\alu_div0_logical_op__oe__ok$next[0:0]$5285 + attribute \src "libresoc.v:135157.3-135195.6" + wire $2\alu_div0_logical_op__rc__ok$next[0:0]$5286 + attribute \src "libresoc.v:135157.3-135195.6" + wire $2\alu_div0_logical_op__rc__rc$next[0:0]$5287 + attribute \src "libresoc.v:135196.3-135217.6" + wire width 64 $2\data_r0__o$next[63:0]$5293 + attribute \src "libresoc.v:135196.3-135217.6" + wire $2\data_r0__o_ok$next[0:0]$5294 + attribute \src "libresoc.v:135218.3-135239.6" + wire width 4 $2\data_r1__cr_a$next[3:0]$5301 + attribute \src "libresoc.v:135218.3-135239.6" + wire $2\data_r1__cr_a_ok$next[0:0]$5302 + attribute \src "libresoc.v:135240.3-135261.6" + wire width 2 $2\data_r2__xer_ov$next[1:0]$5309 + attribute \src "libresoc.v:135240.3-135261.6" + wire $2\data_r2__xer_ov_ok$next[0:0]$5310 + attribute \src "libresoc.v:135262.3-135283.6" + wire $2\data_r3__xer_so$next[0:0]$5317 + attribute \src "libresoc.v:135262.3-135283.6" + wire $2\data_r3__xer_so_ok$next[0:0]$5318 + attribute \src "libresoc.v:135196.3-135217.6" + wire $3\data_r0__o_ok$next[0:0]$5295 + attribute \src "libresoc.v:135218.3-135239.6" + wire $3\data_r1__cr_a_ok$next[0:0]$5303 + attribute \src "libresoc.v:135240.3-135261.6" + wire $3\data_r2__xer_ov_ok$next[0:0]$5311 + attribute \src "libresoc.v:135262.3-135283.6" + wire $3\data_r3__xer_so_ok$next[0:0]$5319 + attribute \src "libresoc.v:134823.19-134823.133" + wire width 3 $and$libresoc.v:134823$5109_Y + attribute \src "libresoc.v:134825.19-134825.115" + wire width 3 $and$libresoc.v:134825$5111_Y + attribute \src "libresoc.v:134826.18-134826.110" + wire $and$libresoc.v:134826$5112_Y + attribute \src "libresoc.v:134827.19-134827.125" + wire $and$libresoc.v:134827$5113_Y + attribute \src "libresoc.v:134828.19-134828.125" + wire $and$libresoc.v:134828$5114_Y + attribute \src "libresoc.v:134829.19-134829.125" + wire $and$libresoc.v:134829$5115_Y + attribute \src "libresoc.v:134830.19-134830.125" + wire $and$libresoc.v:134830$5116_Y + attribute \src "libresoc.v:134831.19-134831.149" + wire width 4 $and$libresoc.v:134831$5117_Y + attribute \src "libresoc.v:134832.19-134832.121" + wire width 4 $and$libresoc.v:134832$5118_Y + attribute \src "libresoc.v:134833.19-134833.127" + wire $and$libresoc.v:134833$5119_Y + attribute \src "libresoc.v:134834.19-134834.127" + wire $and$libresoc.v:134834$5120_Y + attribute \src "libresoc.v:134835.19-134835.127" + wire $and$libresoc.v:134835$5121_Y + attribute \src "libresoc.v:134836.19-134836.127" + wire $and$libresoc.v:134836$5122_Y + attribute \src "libresoc.v:134838.18-134838.98" + wire $and$libresoc.v:134838$5124_Y + attribute \src "libresoc.v:134840.18-134840.100" + wire $and$libresoc.v:134840$5126_Y + attribute \src "libresoc.v:134841.18-134841.160" + wire width 4 $and$libresoc.v:134841$5127_Y + attribute \src "libresoc.v:134843.18-134843.119" + wire width 4 $and$libresoc.v:134843$5129_Y + attribute \src "libresoc.v:134846.17-134846.123" + wire $and$libresoc.v:134846$5132_Y + attribute \src "libresoc.v:134847.18-134847.116" + wire $and$libresoc.v:134847$5133_Y + attribute \src "libresoc.v:134852.18-134852.113" + wire $and$libresoc.v:134852$5138_Y + attribute \src "libresoc.v:134853.18-134853.125" + wire width 4 $and$libresoc.v:134853$5139_Y + attribute \src "libresoc.v:134855.18-134855.112" + wire $and$libresoc.v:134855$5141_Y + attribute \src "libresoc.v:134857.18-134857.126" + wire $and$libresoc.v:134857$5143_Y + attribute \src "libresoc.v:134858.18-134858.126" + wire $and$libresoc.v:134858$5144_Y + attribute \src "libresoc.v:134859.18-134859.117" + wire $and$libresoc.v:134859$5145_Y + attribute \src "libresoc.v:134865.18-134865.130" + wire $and$libresoc.v:134865$5151_Y + attribute \src "libresoc.v:134866.18-134866.124" + wire width 4 $and$libresoc.v:134866$5152_Y + attribute \src "libresoc.v:134868.18-134868.116" + wire $and$libresoc.v:134868$5154_Y + attribute \src "libresoc.v:134869.18-134869.119" + wire $and$libresoc.v:134869$5155_Y + attribute \src "libresoc.v:134870.18-134870.121" + wire $and$libresoc.v:134870$5156_Y + attribute \src "libresoc.v:134871.18-134871.121" + wire $and$libresoc.v:134871$5157_Y + attribute \src "libresoc.v:134881.18-134881.134" + wire $and$libresoc.v:134881$5167_Y + attribute \src "libresoc.v:134882.18-134882.132" + wire $and$libresoc.v:134882$5168_Y + attribute \src "libresoc.v:134883.18-134883.149" + wire width 3 $and$libresoc.v:134883$5169_Y + attribute \src "libresoc.v:134854.18-134854.113" + wire $eq$libresoc.v:134854$5140_Y + attribute \src "libresoc.v:134856.18-134856.119" + wire $eq$libresoc.v:134856$5142_Y + attribute \src "libresoc.v:134821.19-134821.130" + wire $not$libresoc.v:134821$5107_Y + attribute \src "libresoc.v:134822.19-134822.136" + wire $not$libresoc.v:134822$5108_Y + attribute \src "libresoc.v:134824.19-134824.115" + wire width 3 $not$libresoc.v:134824$5110_Y + attribute \src "libresoc.v:134837.18-134837.97" + wire $not$libresoc.v:134837$5123_Y + attribute \src "libresoc.v:134839.18-134839.99" + wire $not$libresoc.v:134839$5125_Y + attribute \src "libresoc.v:134842.18-134842.113" + wire width 4 $not$libresoc.v:134842$5128_Y + attribute \src "libresoc.v:134845.18-134845.106" + wire $not$libresoc.v:134845$5131_Y + attribute \src "libresoc.v:134851.18-134851.120" + wire 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\alu_div0_p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \alu_div0_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \alu_div0_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \alu_div0_xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \alu_div0_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \alu_div0_xer_so$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:196" + wire \alu_done + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" + wire \alu_done_dly + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" + wire \alu_done_dly$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" + wire \alu_done_rise + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire \alu_l_q_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \alu_l_r_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \alu_l_r_alu$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire \alu_l_s_alu + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:197" + wire \alu_pulse + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198" + wire width 4 \alu_pulsem + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire \alui_l_q_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \alui_l_r_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \alui_l_r_alui$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire \alui_l_s_alui + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 38 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 32 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" + wire output 21 \cu_busy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:108" + wire \cu_done_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:104" + wire \cu_go_die_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" + wire input 20 \cu_issue_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 input 24 \cu_rd__go_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 output 23 \cu_rd__rel_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" + wire width 3 input 22 \cu_rdmaskn_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:102" + wire \cu_shadown_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 4 input 30 \cu_wr__go_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 4 output 29 \cu_wr__rel_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:97" + wire width 4 \cu_wrmask_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 64 \data_r0__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 64 \data_r0__o$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r0__o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r0__o_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 4 \data_r1__cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 4 \data_r1__cr_a$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r1__cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r1__cr_a_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 2 \data_r2__xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 2 \data_r2__xer_ov$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r2__xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r2__xer_ov_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r3__xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r3__xer_so$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r3__xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r3__xer_so_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 31 \dest1_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 4 output 33 \dest2_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 2 output 35 \dest3_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire output 37 \dest4_o + attribute \src "libresoc.v:134174.7-134174.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 28 \o_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire \opc_l_q_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \opc_l_r_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \opc_l_r_opc$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire \opc_l_s_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire \opc_l_s_opc$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 18 \oper_i_alu_div0__data_len + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 input 3 \oper_i_alu_div0__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 4 \oper_i_alu_div0__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 5 \oper_i_alu_div0__imm_data__ok + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 12 \oper_i_alu_div0__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 19 \oper_i_alu_div0__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 2 \oper_i_alu_div0__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \oper_i_alu_div0__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \oper_i_alu_div0__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 16 \oper_i_alu_div0__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 17 \oper_i_alu_div0__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \oper_i_alu_div0__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \oper_i_alu_div0__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 15 \oper_i_alu_div0__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 7 \oper_i_alu_div0__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 6 \oper_i_alu_div0__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \oper_i_alu_div0__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 11 \oper_i_alu_div0__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" + wire width 4 \prev_wr_go + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" + wire width 4 \prev_wr_go$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212" + wire \req_done + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire width 4 \req_l_q_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 4 \req_l_r_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 4 \req_l_r_req$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire width 4 \req_l_s_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire width 4 \req_l_s_req$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226" + wire \reset + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:229" + wire width 3 \reset_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:228" + wire width 4 \reset_w + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire \rok_l_q_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \rok_l_r_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \rok_l_r_rdok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire \rok_l_s_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire \rok_l_s_rdok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \rst_l_r_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \rst_l_r_rst$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire \rst_l_s_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire \rst_l_s_rst$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227" + wire \rst_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 25 \src1_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 26 \src2_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire input 27 \src3_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire width 3 \src_l_q_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 3 \src_l_r_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 3 \src_l_r_src$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire width 3 \src_l_s_src + attribute \src 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+ connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } + connect \Y $or$libresoc.v:134864$5150_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" + cell $or $or$libresoc.v:134867$5153 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \reset_w + connect \B \prev_wr_go + connect \Y $or$libresoc.v:134867$5153_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $or $or$libresoc.v:134873$5159 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \$5 + connect \B \cu_rd__go_i + connect \Y $or$libresoc.v:134873$5159_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $reduce_and $reduce_and$libresoc.v:134878$5164 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \$7 + connect \Y $reduce_and$libresoc.v:134878$5164_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $reduce_or $reduce_or$libresoc.v:134844$5130 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \$26 + connect \Y $reduce_or$libresoc.v:134844$5130_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $reduce_or $reduce_or$libresoc.v:134848$5134 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \cu_wr__go_i + connect \Y $reduce_or$libresoc.v:134848$5134_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $reduce_or $reduce_or$libresoc.v:134849$5135 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \prev_wr_go + connect \Y $reduce_or$libresoc.v:134849$5135_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" + cell $mux $ternary$libresoc.v:134872$5158 + parameter \WIDTH 1 + connect \A \src_l_q_src [0] + connect \B \opc_l_q_opc + connect \S \alu_div0_logical_op__zero_a + connect \Y $ternary$libresoc.v:134872$5158_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" + cell $mux $ternary$libresoc.v:134874$5160 + parameter \WIDTH 64 + connect \A \src1_i + connect \B 64'0000000000000000000000000000000000000000000000000000000000000000 + connect \S \alu_div0_logical_op__zero_a + connect \Y $ternary$libresoc.v:134874$5160_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" + cell $mux $ternary$libresoc.v:134875$5161 + parameter \WIDTH 1 + connect \A \src_l_q_src [1] + connect \B \opc_l_q_opc + connect \S \alu_div0_logical_op__imm_data__ok + connect \Y $ternary$libresoc.v:134875$5161_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" + cell $mux $ternary$libresoc.v:134876$5162 + parameter \WIDTH 64 + connect \A \src2_i + connect \B \alu_div0_logical_op__imm_data__data + connect \S \alu_div0_logical_op__imm_data__ok + connect \Y $ternary$libresoc.v:134876$5162_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" + cell $mux $ternary$libresoc.v:134877$5163 + parameter \WIDTH 64 + connect \A \src_r0 + connect \B \src_or_imm + connect \S \src_sel + connect \Y $ternary$libresoc.v:134877$5163_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" + cell $mux $ternary$libresoc.v:134879$5165 + parameter \WIDTH 64 + connect \A \src_r1 + connect \B \src_or_imm$85 + connect \S \src_sel$82 + connect \Y $ternary$libresoc.v:134879$5165_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" + cell $mux $ternary$libresoc.v:134880$5166 + parameter \WIDTH 1 + connect \A \src_r2 + connect \B \src3_i + connect \S \src_l_q_src [2] + connect \Y $ternary$libresoc.v:134880$5166_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:134972.12-135008.4" + cell \alu_div0 \alu_div0 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cr_a \alu_div0_cr_a + connect \cr_a_ok \cr_a_ok + connect \logical_op__data_len \alu_div0_logical_op__data_len + connect \logical_op__fn_unit \alu_div0_logical_op__fn_unit + connect \logical_op__imm_data__data \alu_div0_logical_op__imm_data__data + connect \logical_op__imm_data__ok \alu_div0_logical_op__imm_data__ok + connect \logical_op__input_carry \alu_div0_logical_op__input_carry + connect \logical_op__insn \alu_div0_logical_op__insn + connect \logical_op__insn_type \alu_div0_logical_op__insn_type + connect \logical_op__invert_in \alu_div0_logical_op__invert_in + connect \logical_op__invert_out \alu_div0_logical_op__invert_out + connect \logical_op__is_32bit \alu_div0_logical_op__is_32bit + connect \logical_op__is_signed \alu_div0_logical_op__is_signed + connect \logical_op__oe__oe \alu_div0_logical_op__oe__oe + connect \logical_op__oe__ok \alu_div0_logical_op__oe__ok + connect \logical_op__output_carry \alu_div0_logical_op__output_carry + connect \logical_op__rc__ok \alu_div0_logical_op__rc__ok + connect \logical_op__rc__rc \alu_div0_logical_op__rc__rc + connect \logical_op__write_cr0 \alu_div0_logical_op__write_cr0 + connect \logical_op__zero_a \alu_div0_logical_op__zero_a + connect \n_ready_i \alu_div0_n_ready_i + connect \n_valid_o \alu_div0_n_valid_o + connect \o \alu_div0_o + connect \o_ok \o_ok + connect \p_ready_o \alu_div0_p_ready_o + connect \p_valid_i \alu_div0_p_valid_i + connect \ra \alu_div0_ra + connect \rb \alu_div0_rb + connect \xer_ov \alu_div0_xer_ov + connect \xer_ov_ok \xer_ov_ok + connect \xer_so \alu_div0_xer_so + connect \xer_so$1 \alu_div0_xer_so$1 + connect \xer_so_ok \xer_so_ok + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:135009.14-135015.4" + cell \alu_l$90 \alu_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_alu \alu_l_q_alu + connect \r_alu \alu_l_r_alu + connect \s_alu \alu_l_s_alu + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:135016.15-135022.4" + cell \alui_l$89 \alui_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_alui \alui_l_q_alui + connect \r_alui \alui_l_r_alui + connect \s_alui \alui_l_s_alui + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:135023.14-135029.4" + cell \opc_l$85 \opc_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_opc \opc_l_q_opc + connect \r_opc \opc_l_r_opc + connect \s_opc \opc_l_s_opc + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:135030.14-135036.4" + cell \req_l$86 \req_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_req \req_l_q_req + connect \r_req \req_l_r_req + connect \s_req \req_l_s_req + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:135037.14-135043.4" + cell \rok_l$88 \rok_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_rdok \rok_l_q_rdok + connect \r_rdok \rok_l_r_rdok + connect \s_rdok \rok_l_s_rdok + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:135044.14-135049.4" + cell \rst_l$87 \rst_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \r_rst \rst_l_r_rst + connect \s_rst \rst_l_s_rst + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:135050.14-135056.4" + cell \src_l$84 \src_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_src \src_l_q_src + connect \r_src \src_l_r_src + connect \s_src \src_l_s_src + end + attribute \src "libresoc.v:134174.7-134174.20" + process $proc$libresoc.v:134174$5342 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:134304.7-134304.24" + process $proc$libresoc.v:134304$5343 + assign { } { } + assign $1\all_rd_dly[0:0] 1'0 + sync always + sync init + update \all_rd_dly $1\all_rd_dly[0:0] + end + attribute \src "libresoc.v:134314.13-134314.49" + process $proc$libresoc.v:134314$5344 + assign { } { } + assign $1\alu_div0_logical_op__data_len[3:0] 4'0000 + sync always + sync init + update \alu_div0_logical_op__data_len $1\alu_div0_logical_op__data_len[3:0] + end + attribute \src "libresoc.v:134332.14-134332.53" + process $proc$libresoc.v:134332$5345 + assign { } { } + assign $1\alu_div0_logical_op__fn_unit[12:0] 13'0000000000000 + sync always + sync init + update \alu_div0_logical_op__fn_unit $1\alu_div0_logical_op__fn_unit[12:0] + end + attribute \src "libresoc.v:134336.14-134336.72" + process $proc$libresoc.v:134336$5346 + assign { } { } + assign $1\alu_div0_logical_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \alu_div0_logical_op__imm_data__data $1\alu_div0_logical_op__imm_data__data[63:0] + end + attribute \src "libresoc.v:134340.7-134340.47" + process $proc$libresoc.v:134340$5347 + assign { } { } + assign $1\alu_div0_logical_op__imm_data__ok[0:0] 1'0 + sync always + sync init + update \alu_div0_logical_op__imm_data__ok $1\alu_div0_logical_op__imm_data__ok[0:0] + end + attribute \src "libresoc.v:134348.13-134348.52" + process $proc$libresoc.v:134348$5348 + assign { } { } + assign $1\alu_div0_logical_op__input_carry[1:0] 2'00 + sync always + sync init + update \alu_div0_logical_op__input_carry $1\alu_div0_logical_op__input_carry[1:0] + end + attribute \src "libresoc.v:134352.14-134352.47" + process $proc$libresoc.v:134352$5349 + assign { } { } + assign $1\alu_div0_logical_op__insn[31:0] 0 + sync always + sync init + update \alu_div0_logical_op__insn $1\alu_div0_logical_op__insn[31:0] + end + attribute \src "libresoc.v:134430.13-134430.51" + process $proc$libresoc.v:134430$5350 + assign { } { } + assign $1\alu_div0_logical_op__insn_type[6:0] 7'0000000 + sync always + sync init + update \alu_div0_logical_op__insn_type $1\alu_div0_logical_op__insn_type[6:0] + end + attribute \src "libresoc.v:134434.7-134434.44" + process $proc$libresoc.v:134434$5351 + assign { } { } + assign $1\alu_div0_logical_op__invert_in[0:0] 1'0 + sync always + sync init + update \alu_div0_logical_op__invert_in $1\alu_div0_logical_op__invert_in[0:0] + end + attribute \src "libresoc.v:134438.7-134438.45" + process $proc$libresoc.v:134438$5352 + assign { } { } + assign $1\alu_div0_logical_op__invert_out[0:0] 1'0 + sync always + sync init + update \alu_div0_logical_op__invert_out $1\alu_div0_logical_op__invert_out[0:0] + end + attribute \src "libresoc.v:134442.7-134442.43" + process $proc$libresoc.v:134442$5353 + assign { } { } + assign $1\alu_div0_logical_op__is_32bit[0:0] 1'0 + sync always + sync init + update \alu_div0_logical_op__is_32bit $1\alu_div0_logical_op__is_32bit[0:0] + end + attribute \src "libresoc.v:134446.7-134446.44" + process $proc$libresoc.v:134446$5354 + assign { } { } + assign $1\alu_div0_logical_op__is_signed[0:0] 1'0 + sync always + sync init + update \alu_div0_logical_op__is_signed $1\alu_div0_logical_op__is_signed[0:0] + end + attribute \src "libresoc.v:134450.7-134450.41" + process $proc$libresoc.v:134450$5355 + assign { } { } + assign $1\alu_div0_logical_op__oe__oe[0:0] 1'0 + sync always + sync init + update \alu_div0_logical_op__oe__oe $1\alu_div0_logical_op__oe__oe[0:0] + end + attribute \src "libresoc.v:134454.7-134454.41" + process $proc$libresoc.v:134454$5356 + assign { } { } + assign $1\alu_div0_logical_op__oe__ok[0:0] 1'0 + sync always + sync init + update \alu_div0_logical_op__oe__ok $1\alu_div0_logical_op__oe__ok[0:0] + end + attribute \src "libresoc.v:134458.7-134458.47" + process $proc$libresoc.v:134458$5357 + assign { } { } + assign $1\alu_div0_logical_op__output_carry[0:0] 1'0 + sync always + sync init + update \alu_div0_logical_op__output_carry $1\alu_div0_logical_op__output_carry[0:0] + end + attribute \src "libresoc.v:134462.7-134462.41" + process $proc$libresoc.v:134462$5358 + assign { } { } + assign $1\alu_div0_logical_op__rc__ok[0:0] 1'0 + sync always + sync init + update \alu_div0_logical_op__rc__ok $1\alu_div0_logical_op__rc__ok[0:0] + end + attribute \src "libresoc.v:134466.7-134466.41" + process $proc$libresoc.v:134466$5359 + assign { } { } + assign $1\alu_div0_logical_op__rc__rc[0:0] 1'0 + sync always + sync init + update \alu_div0_logical_op__rc__rc $1\alu_div0_logical_op__rc__rc[0:0] + end + attribute \src "libresoc.v:134470.7-134470.44" + process $proc$libresoc.v:134470$5360 + assign { } { } + assign $1\alu_div0_logical_op__write_cr0[0:0] 1'0 + sync always + sync init + update \alu_div0_logical_op__write_cr0 $1\alu_div0_logical_op__write_cr0[0:0] + end + attribute \src "libresoc.v:134474.7-134474.41" + process $proc$libresoc.v:134474$5361 + assign { } { } + assign $1\alu_div0_logical_op__zero_a[0:0] 1'0 + sync always + sync init + update \alu_div0_logical_op__zero_a $1\alu_div0_logical_op__zero_a[0:0] + end + attribute \src "libresoc.v:134500.7-134500.26" + process $proc$libresoc.v:134500$5362 + assign { } { } + assign $1\alu_done_dly[0:0] 1'0 + sync always + sync init + update \alu_done_dly $1\alu_done_dly[0:0] + end + attribute \src "libresoc.v:134508.7-134508.25" + process $proc$libresoc.v:134508$5363 + assign { } { } + assign $1\alu_l_r_alu[0:0] 1'1 + sync always + sync init + update \alu_l_r_alu $1\alu_l_r_alu[0:0] + end + attribute \src "libresoc.v:134520.7-134520.27" + process $proc$libresoc.v:134520$5364 + assign { } { } + assign $1\alui_l_r_alui[0:0] 1'1 + sync always + sync init + update \alui_l_r_alui $1\alui_l_r_alui[0:0] + end + attribute \src "libresoc.v:134554.14-134554.47" + process $proc$libresoc.v:134554$5365 + assign { } { } + assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \data_r0__o $1\data_r0__o[63:0] + end + attribute \src "libresoc.v:134558.7-134558.27" + process $proc$libresoc.v:134558$5366 + assign { } { } + assign $1\data_r0__o_ok[0:0] 1'0 + sync always + sync init + update \data_r0__o_ok $1\data_r0__o_ok[0:0] + end + attribute \src "libresoc.v:134562.13-134562.33" + process $proc$libresoc.v:134562$5367 + assign { } { } + assign $1\data_r1__cr_a[3:0] 4'0000 + sync always + sync init + update \data_r1__cr_a $1\data_r1__cr_a[3:0] + end + attribute \src "libresoc.v:134566.7-134566.30" + process $proc$libresoc.v:134566$5368 + assign { } { } + assign $1\data_r1__cr_a_ok[0:0] 1'0 + sync always + sync init + update \data_r1__cr_a_ok $1\data_r1__cr_a_ok[0:0] + end + attribute \src "libresoc.v:134570.13-134570.35" + process $proc$libresoc.v:134570$5369 + assign { } { } + assign $1\data_r2__xer_ov[1:0] 2'00 + sync always + sync init + update \data_r2__xer_ov $1\data_r2__xer_ov[1:0] + end + attribute \src "libresoc.v:134574.7-134574.32" + process $proc$libresoc.v:134574$5370 + assign { } { } + assign $1\data_r2__xer_ov_ok[0:0] 1'0 + sync always + sync init + update \data_r2__xer_ov_ok $1\data_r2__xer_ov_ok[0:0] + end + attribute \src "libresoc.v:134578.7-134578.29" + process $proc$libresoc.v:134578$5371 + assign { } { } + assign $1\data_r3__xer_so[0:0] 1'0 + sync always + sync init + update \data_r3__xer_so $1\data_r3__xer_so[0:0] + end + attribute \src "libresoc.v:134582.7-134582.32" + process $proc$libresoc.v:134582$5372 + assign { } { } + assign $1\data_r3__xer_so_ok[0:0] 1'0 + sync always + sync init + update \data_r3__xer_so_ok $1\data_r3__xer_so_ok[0:0] + end + attribute \src "libresoc.v:134602.7-134602.25" + process $proc$libresoc.v:134602$5373 + assign { } { } + assign $1\opc_l_r_opc[0:0] 1'1 + sync always + sync init + update \opc_l_r_opc $1\opc_l_r_opc[0:0] + end + attribute \src "libresoc.v:134606.7-134606.25" + process $proc$libresoc.v:134606$5374 + assign { } { } + assign $1\opc_l_s_opc[0:0] 1'0 + sync always + sync init + update \opc_l_s_opc $1\opc_l_s_opc[0:0] + end + attribute \src "libresoc.v:134738.13-134738.30" + process $proc$libresoc.v:134738$5375 + assign { } { } + assign $1\prev_wr_go[3:0] 4'0000 + sync always + sync init + update \prev_wr_go $1\prev_wr_go[3:0] + end + attribute \src "libresoc.v:134746.13-134746.31" + process $proc$libresoc.v:134746$5376 + assign { } { } + assign $1\req_l_r_req[3:0] 4'1111 + sync always + sync init + update \req_l_r_req $1\req_l_r_req[3:0] + end + attribute \src "libresoc.v:134750.13-134750.31" + process $proc$libresoc.v:134750$5377 + assign { } { } + assign $1\req_l_s_req[3:0] 4'0000 + sync always + sync init + update \req_l_s_req $1\req_l_s_req[3:0] + end + attribute \src "libresoc.v:134762.7-134762.26" + process $proc$libresoc.v:134762$5378 + assign { } { } + assign $1\rok_l_r_rdok[0:0] 1'1 + sync always + sync init + update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] + end + attribute \src "libresoc.v:134766.7-134766.26" + process $proc$libresoc.v:134766$5379 + assign { } { } + assign $1\rok_l_s_rdok[0:0] 1'0 + sync always + sync init + update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] + end + attribute \src "libresoc.v:134770.7-134770.25" + process $proc$libresoc.v:134770$5380 + assign { } { } + assign $1\rst_l_r_rst[0:0] 1'1 + sync always + sync init + update \rst_l_r_rst $1\rst_l_r_rst[0:0] + end + attribute \src "libresoc.v:134774.7-134774.25" + process $proc$libresoc.v:134774$5381 + assign { } { } + assign $1\rst_l_s_rst[0:0] 1'0 + sync always + sync init + update \rst_l_s_rst $1\rst_l_s_rst[0:0] + end + attribute \src "libresoc.v:134788.13-134788.31" + process $proc$libresoc.v:134788$5382 + assign { } { } + assign $1\src_l_r_src[2:0] 3'111 + sync always + sync init + update \src_l_r_src $1\src_l_r_src[2:0] + end + attribute \src "libresoc.v:134792.13-134792.31" + process $proc$libresoc.v:134792$5383 + assign { } { } + assign $1\src_l_s_src[2:0] 3'000 + sync always + sync init + update \src_l_s_src $1\src_l_s_src[2:0] + end + attribute \src "libresoc.v:134800.14-134800.43" + process $proc$libresoc.v:134800$5384 + assign { } { } + assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \src_r0 $1\src_r0[63:0] + end + attribute \src "libresoc.v:134804.14-134804.43" + process $proc$libresoc.v:134804$5385 + assign { } { } + assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \src_r1 $1\src_r1[63:0] + end + attribute \src "libresoc.v:134808.7-134808.20" + process $proc$libresoc.v:134808$5386 + assign { } { } + assign $1\src_r2[0:0] 1'0 + sync always + sync init + update \src_r2 $1\src_r2[0:0] + end + attribute \src "libresoc.v:134884.3-134885.39" + process $proc$libresoc.v:134884$5170 + assign { } { } + assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next + sync posedge \coresync_clk + update \alu_l_r_alu $0\alu_l_r_alu[0:0] + end + attribute \src "libresoc.v:134886.3-134887.43" + process $proc$libresoc.v:134886$5171 + assign { } { } + assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next + sync posedge \coresync_clk + update \alui_l_r_alui $0\alui_l_r_alui[0:0] + end + attribute \src "libresoc.v:134888.3-134889.29" + process $proc$libresoc.v:134888$5172 + assign { } { } + assign $0\src_r2[0:0] \src_r2$next + sync posedge \coresync_clk + update \src_r2 $0\src_r2[0:0] + end + attribute \src "libresoc.v:134890.3-134891.29" + process $proc$libresoc.v:134890$5173 + assign { } { } + assign $0\src_r1[63:0] \src_r1$next + sync posedge \coresync_clk + update \src_r1 $0\src_r1[63:0] + end + attribute \src "libresoc.v:134892.3-134893.29" + process $proc$libresoc.v:134892$5174 + assign { } { } + assign $0\src_r0[63:0] \src_r0$next + sync posedge \coresync_clk + update \src_r0 $0\src_r0[63:0] + end + attribute \src "libresoc.v:134894.3-134895.47" + process $proc$libresoc.v:134894$5175 + assign { } { } + assign $0\data_r3__xer_so[0:0] \data_r3__xer_so$next + sync posedge \coresync_clk + update \data_r3__xer_so $0\data_r3__xer_so[0:0] + end + attribute \src "libresoc.v:134896.3-134897.53" + process $proc$libresoc.v:134896$5176 + assign { } { } + assign $0\data_r3__xer_so_ok[0:0] \data_r3__xer_so_ok$next + sync posedge \coresync_clk + update \data_r3__xer_so_ok $0\data_r3__xer_so_ok[0:0] + end + attribute \src "libresoc.v:134898.3-134899.47" + process $proc$libresoc.v:134898$5177 + assign { } { } + assign $0\data_r2__xer_ov[1:0] \data_r2__xer_ov$next + sync posedge \coresync_clk + update \data_r2__xer_ov $0\data_r2__xer_ov[1:0] + end + attribute \src "libresoc.v:134900.3-134901.53" + process $proc$libresoc.v:134900$5178 + assign { } { } + assign $0\data_r2__xer_ov_ok[0:0] \data_r2__xer_ov_ok$next + sync posedge \coresync_clk + update \data_r2__xer_ov_ok $0\data_r2__xer_ov_ok[0:0] + end + attribute \src "libresoc.v:134902.3-134903.43" + process $proc$libresoc.v:134902$5179 + assign { } { } + assign $0\data_r1__cr_a[3:0] \data_r1__cr_a$next + sync posedge \coresync_clk + update \data_r1__cr_a $0\data_r1__cr_a[3:0] + end + attribute \src "libresoc.v:134904.3-134905.49" + process $proc$libresoc.v:134904$5180 + assign { } { } + assign $0\data_r1__cr_a_ok[0:0] \data_r1__cr_a_ok$next + sync posedge \coresync_clk + update \data_r1__cr_a_ok $0\data_r1__cr_a_ok[0:0] + end + attribute \src "libresoc.v:134906.3-134907.37" + process $proc$libresoc.v:134906$5181 + assign { } { } + assign $0\data_r0__o[63:0] \data_r0__o$next + sync posedge \coresync_clk + update \data_r0__o $0\data_r0__o[63:0] + end + attribute \src "libresoc.v:134908.3-134909.43" + process $proc$libresoc.v:134908$5182 + assign { } { } + assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next + sync posedge \coresync_clk + update \data_r0__o_ok $0\data_r0__o_ok[0:0] + end + attribute \src "libresoc.v:134910.3-134911.77" + process $proc$libresoc.v:134910$5183 + assign { } { } + assign $0\alu_div0_logical_op__insn_type[6:0] \alu_div0_logical_op__insn_type$next + sync posedge \coresync_clk + update \alu_div0_logical_op__insn_type $0\alu_div0_logical_op__insn_type[6:0] + end + attribute \src "libresoc.v:134912.3-134913.73" + process $proc$libresoc.v:134912$5184 + assign { } { } + assign $0\alu_div0_logical_op__fn_unit[12:0] \alu_div0_logical_op__fn_unit$next + sync posedge \coresync_clk + update \alu_div0_logical_op__fn_unit $0\alu_div0_logical_op__fn_unit[12:0] + end + attribute \src "libresoc.v:134914.3-134915.87" + process $proc$libresoc.v:134914$5185 + assign { } { } + assign $0\alu_div0_logical_op__imm_data__data[63:0] \alu_div0_logical_op__imm_data__data$next + sync posedge \coresync_clk + update \alu_div0_logical_op__imm_data__data $0\alu_div0_logical_op__imm_data__data[63:0] + end + attribute \src "libresoc.v:134916.3-134917.83" + process $proc$libresoc.v:134916$5186 + assign { } { } + assign $0\alu_div0_logical_op__imm_data__ok[0:0] \alu_div0_logical_op__imm_data__ok$next + sync posedge \coresync_clk + update \alu_div0_logical_op__imm_data__ok $0\alu_div0_logical_op__imm_data__ok[0:0] + end + attribute \src "libresoc.v:134918.3-134919.71" + process $proc$libresoc.v:134918$5187 + assign { } { } + assign $0\alu_div0_logical_op__rc__rc[0:0] \alu_div0_logical_op__rc__rc$next + sync posedge \coresync_clk + update \alu_div0_logical_op__rc__rc $0\alu_div0_logical_op__rc__rc[0:0] + end + attribute \src "libresoc.v:134920.3-134921.71" + process $proc$libresoc.v:134920$5188 + assign { } { } + assign $0\alu_div0_logical_op__rc__ok[0:0] \alu_div0_logical_op__rc__ok$next + sync posedge \coresync_clk + update \alu_div0_logical_op__rc__ok $0\alu_div0_logical_op__rc__ok[0:0] + end + attribute \src "libresoc.v:134922.3-134923.71" + process $proc$libresoc.v:134922$5189 + assign { } { } + assign $0\alu_div0_logical_op__oe__oe[0:0] \alu_div0_logical_op__oe__oe$next + sync posedge \coresync_clk + update \alu_div0_logical_op__oe__oe $0\alu_div0_logical_op__oe__oe[0:0] + end + attribute \src "libresoc.v:134924.3-134925.71" + process $proc$libresoc.v:134924$5190 + assign { } { } + assign $0\alu_div0_logical_op__oe__ok[0:0] \alu_div0_logical_op__oe__ok$next + sync posedge \coresync_clk + update \alu_div0_logical_op__oe__ok $0\alu_div0_logical_op__oe__ok[0:0] + end + attribute \src "libresoc.v:134926.3-134927.77" + process $proc$libresoc.v:134926$5191 + assign { } { } + assign $0\alu_div0_logical_op__invert_in[0:0] \alu_div0_logical_op__invert_in$next + sync posedge \coresync_clk + update \alu_div0_logical_op__invert_in $0\alu_div0_logical_op__invert_in[0:0] + end + attribute \src "libresoc.v:134928.3-134929.71" + process $proc$libresoc.v:134928$5192 + assign { } { } + assign $0\alu_div0_logical_op__zero_a[0:0] \alu_div0_logical_op__zero_a$next + sync posedge \coresync_clk + update \alu_div0_logical_op__zero_a $0\alu_div0_logical_op__zero_a[0:0] + end + attribute \src "libresoc.v:134930.3-134931.81" + process $proc$libresoc.v:134930$5193 + assign { } { } + assign $0\alu_div0_logical_op__input_carry[1:0] \alu_div0_logical_op__input_carry$next + sync posedge \coresync_clk + update \alu_div0_logical_op__input_carry $0\alu_div0_logical_op__input_carry[1:0] + end + attribute \src "libresoc.v:134932.3-134933.79" + process $proc$libresoc.v:134932$5194 + assign { } { } + assign $0\alu_div0_logical_op__invert_out[0:0] \alu_div0_logical_op__invert_out$next + sync posedge \coresync_clk + update \alu_div0_logical_op__invert_out $0\alu_div0_logical_op__invert_out[0:0] + end + attribute \src "libresoc.v:134934.3-134935.77" + process $proc$libresoc.v:134934$5195 + assign { } { } + assign $0\alu_div0_logical_op__write_cr0[0:0] \alu_div0_logical_op__write_cr0$next + sync posedge \coresync_clk + update \alu_div0_logical_op__write_cr0 $0\alu_div0_logical_op__write_cr0[0:0] + end + attribute \src "libresoc.v:134936.3-134937.83" + process $proc$libresoc.v:134936$5196 + assign { } { } + assign $0\alu_div0_logical_op__output_carry[0:0] \alu_div0_logical_op__output_carry$next + sync posedge \coresync_clk + update \alu_div0_logical_op__output_carry $0\alu_div0_logical_op__output_carry[0:0] + end + attribute \src "libresoc.v:134938.3-134939.75" + process $proc$libresoc.v:134938$5197 + assign { } { } + assign $0\alu_div0_logical_op__is_32bit[0:0] \alu_div0_logical_op__is_32bit$next + sync posedge \coresync_clk + update \alu_div0_logical_op__is_32bit $0\alu_div0_logical_op__is_32bit[0:0] + end + attribute \src "libresoc.v:134940.3-134941.77" + process $proc$libresoc.v:134940$5198 + assign { } { } + assign $0\alu_div0_logical_op__is_signed[0:0] \alu_div0_logical_op__is_signed$next + sync posedge \coresync_clk + update \alu_div0_logical_op__is_signed $0\alu_div0_logical_op__is_signed[0:0] + end + attribute \src "libresoc.v:134942.3-134943.75" + process $proc$libresoc.v:134942$5199 + assign { } { } + assign $0\alu_div0_logical_op__data_len[3:0] \alu_div0_logical_op__data_len$next + sync posedge \coresync_clk + update \alu_div0_logical_op__data_len $0\alu_div0_logical_op__data_len[3:0] + end + attribute \src "libresoc.v:134944.3-134945.67" + process $proc$libresoc.v:134944$5200 + assign { } { } + assign $0\alu_div0_logical_op__insn[31:0] \alu_div0_logical_op__insn$next + sync posedge \coresync_clk + update \alu_div0_logical_op__insn $0\alu_div0_logical_op__insn[31:0] + end + attribute \src "libresoc.v:134946.3-134947.39" + process $proc$libresoc.v:134946$5201 + assign { } { } + assign $0\req_l_r_req[3:0] \req_l_r_req$next + sync posedge \coresync_clk + update \req_l_r_req $0\req_l_r_req[3:0] + end + attribute \src "libresoc.v:134948.3-134949.39" + process $proc$libresoc.v:134948$5202 + assign { } { } + assign $0\req_l_s_req[3:0] \req_l_s_req$next + sync posedge \coresync_clk + update \req_l_s_req $0\req_l_s_req[3:0] + end + attribute \src "libresoc.v:134950.3-134951.39" + process $proc$libresoc.v:134950$5203 + assign { } { } + assign $0\src_l_r_src[2:0] \src_l_r_src$next + sync posedge \coresync_clk + update \src_l_r_src $0\src_l_r_src[2:0] + end + attribute \src "libresoc.v:134952.3-134953.39" + process $proc$libresoc.v:134952$5204 + assign { } { } + assign $0\src_l_s_src[2:0] \src_l_s_src$next + sync posedge \coresync_clk + update \src_l_s_src $0\src_l_s_src[2:0] + end + attribute \src "libresoc.v:134954.3-134955.39" + process $proc$libresoc.v:134954$5205 + assign { } { } + assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next + sync posedge \coresync_clk + update \opc_l_r_opc $0\opc_l_r_opc[0:0] + end + attribute \src "libresoc.v:134956.3-134957.39" + process $proc$libresoc.v:134956$5206 + assign { } { } + assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next + sync posedge \coresync_clk + update \opc_l_s_opc $0\opc_l_s_opc[0:0] + end + attribute \src "libresoc.v:134958.3-134959.39" + process $proc$libresoc.v:134958$5207 + assign { } { } + assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next + sync posedge \coresync_clk + update \rst_l_r_rst $0\rst_l_r_rst[0:0] + end + attribute \src "libresoc.v:134960.3-134961.39" + process $proc$libresoc.v:134960$5208 + assign { } { } + assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next + sync posedge \coresync_clk + update \rst_l_s_rst $0\rst_l_s_rst[0:0] + end + attribute \src "libresoc.v:134962.3-134963.41" + process $proc$libresoc.v:134962$5209 + assign { } { } + assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next + sync posedge \coresync_clk + update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] + end + attribute \src "libresoc.v:134964.3-134965.41" + process $proc$libresoc.v:134964$5210 + assign { } { } + assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next + sync posedge \coresync_clk + update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] + end + attribute \src "libresoc.v:134966.3-134967.37" + process $proc$libresoc.v:134966$5211 + assign { } { } + assign $0\prev_wr_go[3:0] \prev_wr_go$next + sync posedge \coresync_clk + update \prev_wr_go $0\prev_wr_go[3:0] + end + attribute \src "libresoc.v:134968.3-134969.40" + process $proc$libresoc.v:134968$5212 + assign { } { } + assign $0\alu_done_dly[0:0] \alu_div0_n_valid_o + sync posedge \coresync_clk + update \alu_done_dly $0\alu_done_dly[0:0] + end + attribute \src "libresoc.v:134970.3-134971.25" + process $proc$libresoc.v:134970$5213 + assign { } { } + assign $0\all_rd_dly[0:0] \$10 + sync posedge \coresync_clk + update \all_rd_dly $0\all_rd_dly[0:0] + end + attribute \src "libresoc.v:135057.3-135066.6" + process $proc$libresoc.v:135057$5214 + assign { } { } + assign { } { } + assign $0\req_done[0:0] $1\req_done[0:0] + attribute \src "libresoc.v:135058.5-135058.29" + switch \initial + attribute \src "libresoc.v:135058.9-135058.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + switch \$54 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\req_done[0:0] 1'1 + case + assign $1\req_done[0:0] \$46 + end + sync always + update \req_done $0\req_done[0:0] + end + attribute \src "libresoc.v:135067.3-135075.6" + process $proc$libresoc.v:135067$5215 + assign { } { } + assign { } { } + assign $0\rok_l_s_rdok$next[0:0]$5216 $1\rok_l_s_rdok$next[0:0]$5217 + attribute \src "libresoc.v:135068.5-135068.29" + switch \initial + attribute \src "libresoc.v:135068.9-135068.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rok_l_s_rdok$next[0:0]$5217 1'0 + case + assign $1\rok_l_s_rdok$next[0:0]$5217 \cu_issue_i + end + sync always + update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$5216 + end + attribute \src "libresoc.v:135076.3-135084.6" + process $proc$libresoc.v:135076$5218 + assign { } { } + assign { } { } + assign $0\rok_l_r_rdok$next[0:0]$5219 $1\rok_l_r_rdok$next[0:0]$5220 + attribute \src "libresoc.v:135077.5-135077.29" + switch \initial + attribute \src "libresoc.v:135077.9-135077.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rok_l_r_rdok$next[0:0]$5220 1'1 + case + assign $1\rok_l_r_rdok$next[0:0]$5220 \$64 + end + sync always + update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$5219 + end + attribute \src "libresoc.v:135085.3-135093.6" + process $proc$libresoc.v:135085$5221 + assign { } { } + assign { } { } + assign $0\rst_l_s_rst$next[0:0]$5222 $1\rst_l_s_rst$next[0:0]$5223 + attribute \src "libresoc.v:135086.5-135086.29" + switch \initial + attribute \src "libresoc.v:135086.9-135086.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rst_l_s_rst$next[0:0]$5223 1'0 + case + assign $1\rst_l_s_rst$next[0:0]$5223 \all_rd + end + sync always + update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$5222 + end + attribute \src "libresoc.v:135094.3-135102.6" + process $proc$libresoc.v:135094$5224 + assign { } { } + assign { } { } + assign $0\rst_l_r_rst$next[0:0]$5225 $1\rst_l_r_rst$next[0:0]$5226 + attribute \src "libresoc.v:135095.5-135095.29" + switch \initial + attribute \src "libresoc.v:135095.9-135095.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rst_l_r_rst$next[0:0]$5226 1'1 + case + assign $1\rst_l_r_rst$next[0:0]$5226 \rst_r + end + sync always + update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$5225 + end + attribute \src "libresoc.v:135103.3-135111.6" + process $proc$libresoc.v:135103$5227 + assign { } { } + assign { } { } + assign $0\opc_l_s_opc$next[0:0]$5228 $1\opc_l_s_opc$next[0:0]$5229 + attribute \src "libresoc.v:135104.5-135104.29" + switch \initial + attribute \src "libresoc.v:135104.9-135104.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\opc_l_s_opc$next[0:0]$5229 1'0 + case + assign $1\opc_l_s_opc$next[0:0]$5229 \cu_issue_i + end + sync always + update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$5228 + end + attribute \src "libresoc.v:135112.3-135120.6" + process $proc$libresoc.v:135112$5230 + assign { } { } + assign { } { } + assign $0\opc_l_r_opc$next[0:0]$5231 $1\opc_l_r_opc$next[0:0]$5232 + attribute \src "libresoc.v:135113.5-135113.29" + switch \initial + attribute \src "libresoc.v:135113.9-135113.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\opc_l_r_opc$next[0:0]$5232 1'1 + case + assign $1\opc_l_r_opc$next[0:0]$5232 \req_done + end + sync always + update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$5231 + end + attribute \src "libresoc.v:135121.3-135129.6" + process $proc$libresoc.v:135121$5233 + assign { } { } + assign { } { } + assign $0\src_l_s_src$next[2:0]$5234 $1\src_l_s_src$next[2:0]$5235 + attribute \src "libresoc.v:135122.5-135122.29" + switch \initial + attribute \src "libresoc.v:135122.9-135122.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_l_s_src$next[2:0]$5235 3'000 + case + assign $1\src_l_s_src$next[2:0]$5235 { \cu_issue_i \cu_issue_i \cu_issue_i } + end + sync always + update \src_l_s_src$next $0\src_l_s_src$next[2:0]$5234 + end + attribute \src "libresoc.v:135130.3-135138.6" + process $proc$libresoc.v:135130$5236 + assign { } { } + assign { } { } + assign $0\src_l_r_src$next[2:0]$5237 $1\src_l_r_src$next[2:0]$5238 + attribute \src "libresoc.v:135131.5-135131.29" + switch \initial + attribute \src "libresoc.v:135131.9-135131.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_l_r_src$next[2:0]$5238 3'111 + case + assign $1\src_l_r_src$next[2:0]$5238 \reset_r + end + sync always + update \src_l_r_src$next $0\src_l_r_src$next[2:0]$5237 + end + attribute \src "libresoc.v:135139.3-135147.6" + process $proc$libresoc.v:135139$5239 + assign { } { } + assign { } { } + assign $0\req_l_s_req$next[3:0]$5240 $1\req_l_s_req$next[3:0]$5241 + attribute \src "libresoc.v:135140.5-135140.29" + switch \initial + attribute \src "libresoc.v:135140.9-135140.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\req_l_s_req$next[3:0]$5241 4'0000 + case + assign $1\req_l_s_req$next[3:0]$5241 \$66 + end + sync always + update \req_l_s_req$next $0\req_l_s_req$next[3:0]$5240 + end + attribute \src "libresoc.v:135148.3-135156.6" + process $proc$libresoc.v:135148$5242 + assign { } { } + assign { } { } + assign $0\req_l_r_req$next[3:0]$5243 $1\req_l_r_req$next[3:0]$5244 + attribute \src "libresoc.v:135149.5-135149.29" + switch \initial + attribute \src "libresoc.v:135149.9-135149.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\req_l_r_req$next[3:0]$5244 4'1111 + case + assign $1\req_l_r_req$next[3:0]$5244 \$68 + end + sync always + update \req_l_r_req$next $0\req_l_r_req$next[3:0]$5243 + end + attribute \src "libresoc.v:135157.3-135195.6" + process $proc$libresoc.v:135157$5245 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\alu_div0_logical_op__data_len$next[3:0]$5246 $1\alu_div0_logical_op__data_len$next[3:0]$5264 + assign $0\alu_div0_logical_op__fn_unit$next[12:0]$5247 $1\alu_div0_logical_op__fn_unit$next[12:0]$5265 + assign { } { } + assign { } { } + assign $0\alu_div0_logical_op__input_carry$next[1:0]$5250 $1\alu_div0_logical_op__input_carry$next[1:0]$5268 + assign $0\alu_div0_logical_op__insn$next[31:0]$5251 $1\alu_div0_logical_op__insn$next[31:0]$5269 + assign $0\alu_div0_logical_op__insn_type$next[6:0]$5252 $1\alu_div0_logical_op__insn_type$next[6:0]$5270 + assign $0\alu_div0_logical_op__invert_in$next[0:0]$5253 $1\alu_div0_logical_op__invert_in$next[0:0]$5271 + assign $0\alu_div0_logical_op__invert_out$next[0:0]$5254 $1\alu_div0_logical_op__invert_out$next[0:0]$5272 + assign $0\alu_div0_logical_op__is_32bit$next[0:0]$5255 $1\alu_div0_logical_op__is_32bit$next[0:0]$5273 + assign $0\alu_div0_logical_op__is_signed$next[0:0]$5256 $1\alu_div0_logical_op__is_signed$next[0:0]$5274 + assign { } { } + assign { } { } + assign $0\alu_div0_logical_op__output_carry$next[0:0]$5259 $1\alu_div0_logical_op__output_carry$next[0:0]$5277 + assign { } { } + assign { } { } + assign $0\alu_div0_logical_op__write_cr0$next[0:0]$5262 $1\alu_div0_logical_op__write_cr0$next[0:0]$5280 + assign $0\alu_div0_logical_op__zero_a$next[0:0]$5263 $1\alu_div0_logical_op__zero_a$next[0:0]$5281 + assign $0\alu_div0_logical_op__imm_data__data$next[63:0]$5248 $2\alu_div0_logical_op__imm_data__data$next[63:0]$5282 + assign $0\alu_div0_logical_op__imm_data__ok$next[0:0]$5249 $2\alu_div0_logical_op__imm_data__ok$next[0:0]$5283 + assign $0\alu_div0_logical_op__oe__oe$next[0:0]$5257 $2\alu_div0_logical_op__oe__oe$next[0:0]$5284 + assign $0\alu_div0_logical_op__oe__ok$next[0:0]$5258 $2\alu_div0_logical_op__oe__ok$next[0:0]$5285 + assign $0\alu_div0_logical_op__rc__ok$next[0:0]$5260 $2\alu_div0_logical_op__rc__ok$next[0:0]$5286 + assign $0\alu_div0_logical_op__rc__rc$next[0:0]$5261 $2\alu_div0_logical_op__rc__rc$next[0:0]$5287 + attribute \src "libresoc.v:135158.5-135158.29" + switch \initial + attribute \src "libresoc.v:135158.9-135158.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\alu_div0_logical_op__insn$next[31:0]$5269 $1\alu_div0_logical_op__data_len$next[3:0]$5264 $1\alu_div0_logical_op__is_signed$next[0:0]$5274 $1\alu_div0_logical_op__is_32bit$next[0:0]$5273 $1\alu_div0_logical_op__output_carry$next[0:0]$5277 $1\alu_div0_logical_op__write_cr0$next[0:0]$5280 $1\alu_div0_logical_op__invert_out$next[0:0]$5272 $1\alu_div0_logical_op__input_carry$next[1:0]$5268 $1\alu_div0_logical_op__zero_a$next[0:0]$5281 $1\alu_div0_logical_op__invert_in$next[0:0]$5271 $1\alu_div0_logical_op__oe__ok$next[0:0]$5276 $1\alu_div0_logical_op__oe__oe$next[0:0]$5275 $1\alu_div0_logical_op__rc__ok$next[0:0]$5278 $1\alu_div0_logical_op__rc__rc$next[0:0]$5279 $1\alu_div0_logical_op__imm_data__ok$next[0:0]$5267 $1\alu_div0_logical_op__imm_data__data$next[63:0]$5266 $1\alu_div0_logical_op__fn_unit$next[12:0]$5265 $1\alu_div0_logical_op__insn_type$next[6:0]$5270 } { \oper_i_alu_div0__insn \oper_i_alu_div0__data_len \oper_i_alu_div0__is_signed \oper_i_alu_div0__is_32bit \oper_i_alu_div0__output_carry \oper_i_alu_div0__write_cr0 \oper_i_alu_div0__invert_out \oper_i_alu_div0__input_carry \oper_i_alu_div0__zero_a \oper_i_alu_div0__invert_in \oper_i_alu_div0__oe__ok \oper_i_alu_div0__oe__oe \oper_i_alu_div0__rc__ok \oper_i_alu_div0__rc__rc \oper_i_alu_div0__imm_data__ok \oper_i_alu_div0__imm_data__data \oper_i_alu_div0__fn_unit \oper_i_alu_div0__insn_type } + case + assign $1\alu_div0_logical_op__data_len$next[3:0]$5264 \alu_div0_logical_op__data_len + assign $1\alu_div0_logical_op__fn_unit$next[12:0]$5265 \alu_div0_logical_op__fn_unit + assign $1\alu_div0_logical_op__imm_data__data$next[63:0]$5266 \alu_div0_logical_op__imm_data__data + assign $1\alu_div0_logical_op__imm_data__ok$next[0:0]$5267 \alu_div0_logical_op__imm_data__ok + assign $1\alu_div0_logical_op__input_carry$next[1:0]$5268 \alu_div0_logical_op__input_carry + assign $1\alu_div0_logical_op__insn$next[31:0]$5269 \alu_div0_logical_op__insn + assign $1\alu_div0_logical_op__insn_type$next[6:0]$5270 \alu_div0_logical_op__insn_type + assign $1\alu_div0_logical_op__invert_in$next[0:0]$5271 \alu_div0_logical_op__invert_in + assign $1\alu_div0_logical_op__invert_out$next[0:0]$5272 \alu_div0_logical_op__invert_out + assign $1\alu_div0_logical_op__is_32bit$next[0:0]$5273 \alu_div0_logical_op__is_32bit + assign $1\alu_div0_logical_op__is_signed$next[0:0]$5274 \alu_div0_logical_op__is_signed + assign $1\alu_div0_logical_op__oe__oe$next[0:0]$5275 \alu_div0_logical_op__oe__oe + assign $1\alu_div0_logical_op__oe__ok$next[0:0]$5276 \alu_div0_logical_op__oe__ok + assign $1\alu_div0_logical_op__output_carry$next[0:0]$5277 \alu_div0_logical_op__output_carry + assign $1\alu_div0_logical_op__rc__ok$next[0:0]$5278 \alu_div0_logical_op__rc__ok + assign $1\alu_div0_logical_op__rc__rc$next[0:0]$5279 \alu_div0_logical_op__rc__rc + assign $1\alu_div0_logical_op__write_cr0$next[0:0]$5280 \alu_div0_logical_op__write_cr0 + assign $1\alu_div0_logical_op__zero_a$next[0:0]$5281 \alu_div0_logical_op__zero_a + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $2\alu_div0_logical_op__imm_data__data$next[63:0]$5282 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\alu_div0_logical_op__imm_data__ok$next[0:0]$5283 1'0 + assign $2\alu_div0_logical_op__rc__rc$next[0:0]$5287 1'0 + assign $2\alu_div0_logical_op__rc__ok$next[0:0]$5286 1'0 + assign $2\alu_div0_logical_op__oe__oe$next[0:0]$5284 1'0 + assign $2\alu_div0_logical_op__oe__ok$next[0:0]$5285 1'0 + case + assign $2\alu_div0_logical_op__imm_data__data$next[63:0]$5282 $1\alu_div0_logical_op__imm_data__data$next[63:0]$5266 + assign $2\alu_div0_logical_op__imm_data__ok$next[0:0]$5283 $1\alu_div0_logical_op__imm_data__ok$next[0:0]$5267 + assign $2\alu_div0_logical_op__oe__oe$next[0:0]$5284 $1\alu_div0_logical_op__oe__oe$next[0:0]$5275 + assign $2\alu_div0_logical_op__oe__ok$next[0:0]$5285 $1\alu_div0_logical_op__oe__ok$next[0:0]$5276 + assign $2\alu_div0_logical_op__rc__ok$next[0:0]$5286 $1\alu_div0_logical_op__rc__ok$next[0:0]$5278 + assign $2\alu_div0_logical_op__rc__rc$next[0:0]$5287 $1\alu_div0_logical_op__rc__rc$next[0:0]$5279 + end + sync always + update \alu_div0_logical_op__data_len$next $0\alu_div0_logical_op__data_len$next[3:0]$5246 + update \alu_div0_logical_op__fn_unit$next $0\alu_div0_logical_op__fn_unit$next[12:0]$5247 + update \alu_div0_logical_op__imm_data__data$next $0\alu_div0_logical_op__imm_data__data$next[63:0]$5248 + update \alu_div0_logical_op__imm_data__ok$next $0\alu_div0_logical_op__imm_data__ok$next[0:0]$5249 + update \alu_div0_logical_op__input_carry$next $0\alu_div0_logical_op__input_carry$next[1:0]$5250 + update \alu_div0_logical_op__insn$next $0\alu_div0_logical_op__insn$next[31:0]$5251 + update \alu_div0_logical_op__insn_type$next $0\alu_div0_logical_op__insn_type$next[6:0]$5252 + update \alu_div0_logical_op__invert_in$next $0\alu_div0_logical_op__invert_in$next[0:0]$5253 + update \alu_div0_logical_op__invert_out$next $0\alu_div0_logical_op__invert_out$next[0:0]$5254 + update \alu_div0_logical_op__is_32bit$next $0\alu_div0_logical_op__is_32bit$next[0:0]$5255 + update \alu_div0_logical_op__is_signed$next $0\alu_div0_logical_op__is_signed$next[0:0]$5256 + update \alu_div0_logical_op__oe__oe$next $0\alu_div0_logical_op__oe__oe$next[0:0]$5257 + update \alu_div0_logical_op__oe__ok$next $0\alu_div0_logical_op__oe__ok$next[0:0]$5258 + update \alu_div0_logical_op__output_carry$next $0\alu_div0_logical_op__output_carry$next[0:0]$5259 + update \alu_div0_logical_op__rc__ok$next $0\alu_div0_logical_op__rc__ok$next[0:0]$5260 + update \alu_div0_logical_op__rc__rc$next $0\alu_div0_logical_op__rc__rc$next[0:0]$5261 + update \alu_div0_logical_op__write_cr0$next $0\alu_div0_logical_op__write_cr0$next[0:0]$5262 + update \alu_div0_logical_op__zero_a$next $0\alu_div0_logical_op__zero_a$next[0:0]$5263 + end + attribute \src "libresoc.v:135196.3-135217.6" + process $proc$libresoc.v:135196$5288 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r0__o$next[63:0]$5289 $2\data_r0__o$next[63:0]$5293 + assign { } { } + assign $0\data_r0__o_ok$next[0:0]$5290 $3\data_r0__o_ok$next[0:0]$5295 + attribute \src "libresoc.v:135197.5-135197.29" + switch \initial + attribute \src "libresoc.v:135197.9-135197.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r0__o_ok$next[0:0]$5292 $1\data_r0__o$next[63:0]$5291 } { \o_ok \alu_div0_o } + case + assign $1\data_r0__o$next[63:0]$5291 \data_r0__o + assign $1\data_r0__o_ok$next[0:0]$5292 \data_r0__o_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r0__o_ok$next[0:0]$5294 $2\data_r0__o$next[63:0]$5293 } 65'00000000000000000000000000000000000000000000000000000000000000000 + case + assign $2\data_r0__o$next[63:0]$5293 $1\data_r0__o$next[63:0]$5291 + assign $2\data_r0__o_ok$next[0:0]$5294 $1\data_r0__o_ok$next[0:0]$5292 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r0__o_ok$next[0:0]$5295 1'0 + case + assign $3\data_r0__o_ok$next[0:0]$5295 $2\data_r0__o_ok$next[0:0]$5294 + end + sync always + update \data_r0__o$next $0\data_r0__o$next[63:0]$5289 + update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$5290 + end + attribute \src "libresoc.v:135218.3-135239.6" + process $proc$libresoc.v:135218$5296 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r1__cr_a$next[3:0]$5297 $2\data_r1__cr_a$next[3:0]$5301 + assign { } { } + assign $0\data_r1__cr_a_ok$next[0:0]$5298 $3\data_r1__cr_a_ok$next[0:0]$5303 + attribute \src "libresoc.v:135219.5-135219.29" + switch \initial + attribute \src "libresoc.v:135219.9-135219.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r1__cr_a_ok$next[0:0]$5300 $1\data_r1__cr_a$next[3:0]$5299 } { \cr_a_ok \alu_div0_cr_a } + case + assign $1\data_r1__cr_a$next[3:0]$5299 \data_r1__cr_a + assign $1\data_r1__cr_a_ok$next[0:0]$5300 \data_r1__cr_a_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r1__cr_a_ok$next[0:0]$5302 $2\data_r1__cr_a$next[3:0]$5301 } 5'00000 + case + assign $2\data_r1__cr_a$next[3:0]$5301 $1\data_r1__cr_a$next[3:0]$5299 + assign $2\data_r1__cr_a_ok$next[0:0]$5302 $1\data_r1__cr_a_ok$next[0:0]$5300 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r1__cr_a_ok$next[0:0]$5303 1'0 + case + assign $3\data_r1__cr_a_ok$next[0:0]$5303 $2\data_r1__cr_a_ok$next[0:0]$5302 + end + sync always + update \data_r1__cr_a$next $0\data_r1__cr_a$next[3:0]$5297 + update \data_r1__cr_a_ok$next $0\data_r1__cr_a_ok$next[0:0]$5298 + end + attribute \src "libresoc.v:135240.3-135261.6" + process $proc$libresoc.v:135240$5304 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r2__xer_ov$next[1:0]$5305 $2\data_r2__xer_ov$next[1:0]$5309 + assign { } { } + assign $0\data_r2__xer_ov_ok$next[0:0]$5306 $3\data_r2__xer_ov_ok$next[0:0]$5311 + attribute \src "libresoc.v:135241.5-135241.29" + switch \initial + attribute \src "libresoc.v:135241.9-135241.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r2__xer_ov_ok$next[0:0]$5308 $1\data_r2__xer_ov$next[1:0]$5307 } { \xer_ov_ok \alu_div0_xer_ov } + case + assign $1\data_r2__xer_ov$next[1:0]$5307 \data_r2__xer_ov + assign $1\data_r2__xer_ov_ok$next[0:0]$5308 \data_r2__xer_ov_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r2__xer_ov_ok$next[0:0]$5310 $2\data_r2__xer_ov$next[1:0]$5309 } 3'000 + case + assign $2\data_r2__xer_ov$next[1:0]$5309 $1\data_r2__xer_ov$next[1:0]$5307 + assign $2\data_r2__xer_ov_ok$next[0:0]$5310 $1\data_r2__xer_ov_ok$next[0:0]$5308 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r2__xer_ov_ok$next[0:0]$5311 1'0 + case + assign $3\data_r2__xer_ov_ok$next[0:0]$5311 $2\data_r2__xer_ov_ok$next[0:0]$5310 + end + sync always + update \data_r2__xer_ov$next $0\data_r2__xer_ov$next[1:0]$5305 + update \data_r2__xer_ov_ok$next $0\data_r2__xer_ov_ok$next[0:0]$5306 + end + attribute \src "libresoc.v:135262.3-135283.6" + process $proc$libresoc.v:135262$5312 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r3__xer_so$next[0:0]$5313 $2\data_r3__xer_so$next[0:0]$5317 + assign { } { } + assign $0\data_r3__xer_so_ok$next[0:0]$5314 $3\data_r3__xer_so_ok$next[0:0]$5319 + attribute \src "libresoc.v:135263.5-135263.29" + switch \initial + attribute \src "libresoc.v:135263.9-135263.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r3__xer_so_ok$next[0:0]$5316 $1\data_r3__xer_so$next[0:0]$5315 } { \xer_so_ok \alu_div0_xer_so } + case + assign $1\data_r3__xer_so$next[0:0]$5315 \data_r3__xer_so + assign $1\data_r3__xer_so_ok$next[0:0]$5316 \data_r3__xer_so_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r3__xer_so_ok$next[0:0]$5318 $2\data_r3__xer_so$next[0:0]$5317 } 2'00 + case + assign $2\data_r3__xer_so$next[0:0]$5317 $1\data_r3__xer_so$next[0:0]$5315 + assign $2\data_r3__xer_so_ok$next[0:0]$5318 $1\data_r3__xer_so_ok$next[0:0]$5316 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r3__xer_so_ok$next[0:0]$5319 1'0 + case + assign $3\data_r3__xer_so_ok$next[0:0]$5319 $2\data_r3__xer_so_ok$next[0:0]$5318 + end + sync always + update \data_r3__xer_so$next $0\data_r3__xer_so$next[0:0]$5313 + update \data_r3__xer_so_ok$next $0\data_r3__xer_so_ok$next[0:0]$5314 + end + attribute \src "libresoc.v:135284.3-135293.6" + process $proc$libresoc.v:135284$5320 + assign { } { } + assign { } { } + assign $0\src_r0$next[63:0]$5321 $1\src_r0$next[63:0]$5322 + attribute \src "libresoc.v:135285.5-135285.29" + switch \initial + attribute \src "libresoc.v:135285.9-135285.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" + switch \src_sel + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r0$next[63:0]$5322 \src_or_imm + case + assign $1\src_r0$next[63:0]$5322 \src_r0 + end + sync always + update \src_r0$next $0\src_r0$next[63:0]$5321 + end + attribute \src "libresoc.v:135294.3-135303.6" + process $proc$libresoc.v:135294$5323 + assign { } { } + assign { } { } + assign $0\src_r1$next[63:0]$5324 $1\src_r1$next[63:0]$5325 + attribute \src "libresoc.v:135295.5-135295.29" + switch \initial + attribute \src "libresoc.v:135295.9-135295.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" + switch \src_sel$82 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r1$next[63:0]$5325 \src_or_imm$85 + case + assign $1\src_r1$next[63:0]$5325 \src_r1 + end + sync always + update \src_r1$next $0\src_r1$next[63:0]$5324 + end + attribute \src "libresoc.v:135304.3-135313.6" + process $proc$libresoc.v:135304$5326 + assign { } { } + assign { } { } + assign $0\src_r2$next[0:0]$5327 $1\src_r2$next[0:0]$5328 + attribute \src "libresoc.v:135305.5-135305.29" + switch \initial + attribute \src "libresoc.v:135305.9-135305.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" + switch \src_l_q_src [2] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r2$next[0:0]$5328 \src3_i + case + assign $1\src_r2$next[0:0]$5328 \src_r2 + end + sync always + update \src_r2$next $0\src_r2$next[0:0]$5327 + end + attribute \src "libresoc.v:135314.3-135322.6" + process $proc$libresoc.v:135314$5329 + assign { } { } + assign { } { } + assign $0\alui_l_r_alui$next[0:0]$5330 $1\alui_l_r_alui$next[0:0]$5331 + attribute \src "libresoc.v:135315.5-135315.29" + switch \initial + attribute \src "libresoc.v:135315.9-135315.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\alui_l_r_alui$next[0:0]$5331 1'1 + case + assign $1\alui_l_r_alui$next[0:0]$5331 \$94 + end + sync always + update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$5330 + end + attribute \src "libresoc.v:135323.3-135331.6" + process $proc$libresoc.v:135323$5332 + assign { } { } + assign { } { } + assign $0\alu_l_r_alu$next[0:0]$5333 $1\alu_l_r_alu$next[0:0]$5334 + attribute \src "libresoc.v:135324.5-135324.29" + switch \initial + attribute \src "libresoc.v:135324.9-135324.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\alu_l_r_alu$next[0:0]$5334 1'1 + case + assign $1\alu_l_r_alu$next[0:0]$5334 \$96 + end + sync always + update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$5333 + end + attribute \src "libresoc.v:135332.3-135341.6" + process $proc$libresoc.v:135332$5335 + assign { } { } + assign { } { } + assign $0\dest1_o[63:0] $1\dest1_o[63:0] + attribute \src "libresoc.v:135333.5-135333.29" + switch \initial + attribute \src "libresoc.v:135333.9-135333.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$122 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest1_o[63:0] \data_r0__o + case + assign $1\dest1_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \dest1_o $0\dest1_o[63:0] + end + attribute \src "libresoc.v:135342.3-135351.6" + process $proc$libresoc.v:135342$5336 + assign { } { } + assign { } { } + assign $0\dest2_o[3:0] $1\dest2_o[3:0] + attribute \src "libresoc.v:135343.5-135343.29" + switch \initial + attribute \src "libresoc.v:135343.9-135343.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$124 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest2_o[3:0] \data_r1__cr_a + case + assign $1\dest2_o[3:0] 4'0000 + end + sync always + update \dest2_o $0\dest2_o[3:0] + end + attribute \src "libresoc.v:135352.3-135361.6" + process $proc$libresoc.v:135352$5337 + assign { } { } + assign { } { } + assign $0\dest3_o[1:0] $1\dest3_o[1:0] + attribute \src "libresoc.v:135353.5-135353.29" + switch \initial + attribute \src "libresoc.v:135353.9-135353.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$126 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest3_o[1:0] \data_r2__xer_ov + case + assign $1\dest3_o[1:0] 2'00 + end + sync always + update \dest3_o $0\dest3_o[1:0] + end + attribute \src "libresoc.v:135362.3-135371.6" + process $proc$libresoc.v:135362$5338 + assign { } { } + assign { } { } + assign $0\dest4_o[0:0] $1\dest4_o[0:0] + attribute \src "libresoc.v:135363.5-135363.29" + switch \initial + attribute \src "libresoc.v:135363.9-135363.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$128 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest4_o[0:0] \data_r3__xer_so + case + assign $1\dest4_o[0:0] 1'0 + end + sync always + update \dest4_o $0\dest4_o[0:0] + end + attribute \src "libresoc.v:135372.3-135380.6" + process $proc$libresoc.v:135372$5339 + assign { } { } + assign { } { } + assign $0\prev_wr_go$next[3:0]$5340 $1\prev_wr_go$next[3:0]$5341 + attribute \src "libresoc.v:135373.5-135373.29" + switch \initial + attribute \src "libresoc.v:135373.9-135373.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\prev_wr_go$next[3:0]$5341 4'0000 + case + assign $1\prev_wr_go$next[3:0]$5341 \$20 + end + sync always + update \prev_wr_go$next $0\prev_wr_go$next[3:0]$5340 + end + connect \$100 $not$libresoc.v:134821$5107_Y + connect \$102 $not$libresoc.v:134822$5108_Y + connect \$104 $and$libresoc.v:134823$5109_Y + connect \$106 $not$libresoc.v:134824$5110_Y + connect \$108 $and$libresoc.v:134825$5111_Y + connect \$10 $and$libresoc.v:134826$5112_Y + connect \$110 $and$libresoc.v:134827$5113_Y + connect \$112 $and$libresoc.v:134828$5114_Y + connect \$114 $and$libresoc.v:134829$5115_Y + connect \$116 $and$libresoc.v:134830$5116_Y + connect \$118 $and$libresoc.v:134831$5117_Y + connect \$120 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$sub$libresoc.v:135469$5390_Y + end + attribute \src "libresoc.v:135431.7-135431.20" + process $proc$libresoc.v:135431$5396 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:135472.3-135483.6" + process $proc$libresoc.v:135472$5393 + assign { } { } + assign $0\value[127:0] $1\value[127:0] + attribute \src "libresoc.v:135473.5-135473.29" + switch \initial + attribute \src "libresoc.v:135473.9-135473.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:72" + switch \next_quotient_bit + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\value[127:0] \difference + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\value[127:0] \i_dividend_quotient + end + sync always + update \value $0\value[127:0] + end + attribute \src "libresoc.v:135484.3-135495.6" + process $proc$libresoc.v:135484$5394 + assign { } { } + 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attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 15 \trap_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 6 \trap_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 20 \trap_op__is_32bit$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 8 input 9 \trap_op__ldst_exc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 8 output 23 \trap_op__ldst_exc$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 4 \trap_op__msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 18 \trap_op__msr$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 input 8 \trap_op__trapaddr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 output 22 \trap_op__trapaddr$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 8 input 7 \trap_op__traptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 8 output 21 \trap_op__traptype$8 + connect \fast2$14 \fast2 + connect \fast1$13 \fast1 + connect \rb$12 \rb + connect \ra$11 \ra + connect { \trap_op__ldst_exc$10 \trap_op__trapaddr$9 \trap_op__traptype$8 \trap_op__is_32bit$7 \trap_op__cia$6 \trap_op__msr$5 \trap_op__insn$4 \trap_op__fn_unit$3 \trap_op__insn_type$2 } { \trap_op__ldst_exc \trap_op__trapaddr \trap_op__traptype \trap_op__is_32bit \trap_op__cia \trap_op__msr \trap_op__insn \trap_op__fn_unit \trap_op__insn_type } + connect \muxid$1 \muxid +end +attribute \src "libresoc.v:135759.1-135930.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fast" +attribute \generator "nMigen" +module \fast + attribute \src "libresoc.v:135854.3-135860.6" + wire width 3 $0$memwr$\memory$libresoc.v:135858$5405_ADDR[2:0]$5413 + attribute \src "libresoc.v:135854.3-135860.6" + wire width 64 $0$memwr$\memory$libresoc.v:135858$5405_DATA[63:0]$5414 + attribute \src "libresoc.v:135854.3-135860.6" + wire width 64 $0$memwr$\memory$libresoc.v:135858$5405_EN[63:0]$5415 + attribute \src "libresoc.v:135854.3-135860.6" + wire width 3 $0$memwr$\memory$libresoc.v:135859$5406_ADDR[2:0]$5416 + attribute \src "libresoc.v:135854.3-135860.6" + wire width 64 $0$memwr$\memory$libresoc.v:135859$5406_DATA[63:0]$5417 + attribute \src "libresoc.v:135854.3-135860.6" + wire width 64 $0$memwr$\memory$libresoc.v:135859$5406_EN[63:0]$5418 + attribute \src "libresoc.v:135854.3-135860.6" + wire width 3 $0\_0_[2:0] + attribute \src "libresoc.v:135854.3-135860.6" + wire width 3 $0\_1_[2:0] + attribute \src "libresoc.v:135854.3-135860.6" + wire width 3 $0\_2_[2:0] + attribute \src "libresoc.v:135760.7-135760.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:135911.3-135920.6" + wire width 64 $0\issue__data_o[63:0] + attribute \src "libresoc.v:135883.3-135891.6" + wire $0\ren_delay$10$next[0:0]$5427 + attribute \src "libresoc.v:135836.3-135837.43" + wire $0\ren_delay$10[0:0]$5410 + attribute \src "libresoc.v:135811.7-135811.28" + wire $0\ren_delay$10[0:0]$5447 + attribute \src "libresoc.v:135902.3-135910.6" + wire $0\ren_delay$11$next[0:0]$5431 + attribute \src "libresoc.v:135834.3-135835.43" + wire $0\ren_delay$11[0:0]$5408 + attribute \src "libresoc.v:135815.7-135815.28" + wire $0\ren_delay$11[0:0]$5449 + attribute \src "libresoc.v:135864.3-135872.6" + wire $0\ren_delay$next[0:0]$5423 + attribute \src "libresoc.v:135838.3-135839.35" + wire $0\ren_delay[0:0] + attribute \src "libresoc.v:135873.3-135882.6" + wire width 64 $0\src1__data_o[63:0] + attribute \src "libresoc.v:135892.3-135901.6" + wire width 64 $0\src2__data_o[63:0] + attribute \src "libresoc.v:135911.3-135920.6" + wire width 64 $1\issue__data_o[63:0] + attribute \src "libresoc.v:135883.3-135891.6" + wire $1\ren_delay$10$next[0:0]$5428 + attribute \src "libresoc.v:135902.3-135910.6" + wire $1\ren_delay$11$next[0:0]$5432 + attribute \src "libresoc.v:135864.3-135872.6" + wire $1\ren_delay$next[0:0]$5424 + attribute \src "libresoc.v:135809.7-135809.23" + wire $1\ren_delay[0:0] + attribute \src "libresoc.v:135873.3-135882.6" + wire width 64 $1\src1__data_o[63:0] + attribute \src "libresoc.v:135892.3-135901.6" + wire width 64 $1\src2__data_o[63:0] + attribute \src "libresoc.v:135861.26-135861.32" + wire width 64 $memrd$\memory$libresoc.v:135861$5419_DATA + attribute \src "libresoc.v:135862.30-135862.36" + wire width 64 $memrd$\memory$libresoc.v:135862$5420_DATA + attribute \src "libresoc.v:135863.30-135863.36" + wire width 64 $memrd$\memory$libresoc.v:135863$5421_DATA + attribute \src "libresoc.v:0.0-0.0" + wire width 3 $memwr$\memory$libresoc.v:135858$5405_ADDR + attribute \src "libresoc.v:0.0-0.0" + wire width 64 $memwr$\memory$libresoc.v:135858$5405_DATA + attribute \src "libresoc.v:0.0-0.0" + wire width 64 $memwr$\memory$libresoc.v:135858$5405_EN + attribute \src "libresoc.v:0.0-0.0" + wire width 3 $memwr$\memory$libresoc.v:135859$5406_ADDR + attribute \src "libresoc.v:0.0-0.0" + wire width 64 $memwr$\memory$libresoc.v:135859$5406_DATA + attribute \src "libresoc.v:0.0-0.0" + wire width 64 $memwr$\memory$libresoc.v:135859$5406_EN + attribute \src "libresoc.v:135851.13-135851.16" + wire width 3 \_0_ + attribute \src "libresoc.v:135852.13-135852.16" + wire width 3 \_1_ + attribute \src "libresoc.v:135853.13-135853.16" + wire width 3 \_2_ + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 17 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 3 input 15 \dest1__addr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 input 14 \dest1__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 16 \dest1__wen + attribute \src "libresoc.v:135760.7-135760.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 3 input 2 \issue__addr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 3 input 5 \issue__addr$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 input 7 \issue__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 output 4 \issue__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 3 \issue__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 6 \issue__wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" + wire width 3 \memory_r_addr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" + wire width 3 \memory_r_addr$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" + wire width 3 \memory_r_addr$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" + wire width 64 \memory_r_data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" + wire width 64 \memory_r_data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" + wire width 64 \memory_r_data$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" + wire width 3 \memory_w_addr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" + wire width 3 \memory_w_addr$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" + wire width 64 \memory_w_data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" + wire width 64 \memory_w_data$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" + wire \memory_w_en + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" + wire \memory_w_en$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" + wire \ren_delay + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" + wire \ren_delay$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" + wire \ren_delay$10$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" + wire \ren_delay$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" + wire \ren_delay$11$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" + wire \ren_delay$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 3 input 9 \src1__addr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 output 8 \src1__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 10 \src1__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 3 input 12 \src2__addr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 output 11 \src2__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 13 \src2__ren + attribute \src "libresoc.v:135840.14-135840.20" + memory width 64 size 8 \memory + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5434 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5434 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 0 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5435 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5435 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 1 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5436 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5436 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 2 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5437 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5437 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 3 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5438 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5438 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 4 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5439 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5439 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 5 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5440 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5440 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 6 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5441 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5441 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 7 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:135861.26-135861.32" + cell $memrd $memrd$\memory$libresoc.v:135861$5419 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\memory" + parameter \TRANSPARENT 0 + parameter \WIDTH 64 + connect \ADDR \_0_ + connect \CLK 1'x + connect \DATA $memrd$\memory$libresoc.v:135861$5419_DATA + connect \EN 1'x + end + attribute \src "libresoc.v:135862.30-135862.36" + cell $memrd $memrd$\memory$libresoc.v:135862$5420 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\memory" + parameter \TRANSPARENT 0 + parameter \WIDTH 64 + connect \ADDR \_1_ + connect \CLK 1'x + connect \DATA $memrd$\memory$libresoc.v:135862$5420_DATA + connect \EN 1'x + end + attribute \src "libresoc.v:135863.30-135863.36" + cell $memrd $memrd$\memory$libresoc.v:135863$5421 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\memory" + parameter \TRANSPARENT 0 + parameter \WIDTH 64 + connect \ADDR \_2_ + connect \CLK 1'x + connect \DATA $memrd$\memory$libresoc.v:135863$5421_DATA + connect \EN 1'x + end + attribute \src "libresoc.v:0.0-0.0" + cell $memwr $memwr$\memory$libresoc.v:0$5442 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\memory" + parameter \PRIORITY 5442 + parameter \WIDTH 64 + connect \ADDR $memwr$\memory$libresoc.v:135858$5405_ADDR + connect \CLK 1'x + connect \DATA $memwr$\memory$libresoc.v:135858$5405_DATA + connect \EN $memwr$\memory$libresoc.v:135858$5405_EN + end + attribute \src "libresoc.v:0.0-0.0" + cell $memwr $memwr$\memory$libresoc.v:0$5443 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\memory" + parameter \PRIORITY 5443 + parameter \WIDTH 64 + connect \ADDR $memwr$\memory$libresoc.v:135859$5406_ADDR + connect \CLK 1'x + connect \DATA $memwr$\memory$libresoc.v:135859$5406_DATA + connect \EN $memwr$\memory$libresoc.v:135859$5406_EN + end + attribute \src "libresoc.v:0.0-0.0" + process $proc$libresoc.v:0$5450 + sync always + sync init + end + attribute \src "libresoc.v:135760.7-135760.20" + process $proc$libresoc.v:135760$5444 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:135809.7-135809.23" + process $proc$libresoc.v:135809$5445 + assign { } { } + assign $1\ren_delay[0:0] 1'0 + sync always + sync init + update \ren_delay $1\ren_delay[0:0] + end + attribute \src "libresoc.v:135811.7-135811.28" + process $proc$libresoc.v:135811$5446 + assign { } { } + assign $0\ren_delay$10[0:0]$5447 1'0 + sync always + sync init + update \ren_delay$10 $0\ren_delay$10[0:0]$5447 + end + attribute \src "libresoc.v:135815.7-135815.28" + process $proc$libresoc.v:135815$5448 + assign { } { } + assign $0\ren_delay$11[0:0]$5449 1'0 + sync always + sync init + update \ren_delay$11 $0\ren_delay$11[0:0]$5449 + end + attribute \src "libresoc.v:135834.3-135835.43" + process $proc$libresoc.v:135834$5407 + assign { } { } + assign $0\ren_delay$11[0:0]$5408 \ren_delay$11$next + sync posedge \coresync_clk + update \ren_delay$11 $0\ren_delay$11[0:0]$5408 + end + attribute \src "libresoc.v:135836.3-135837.43" + process $proc$libresoc.v:135836$5409 + assign { } { } + assign $0\ren_delay$10[0:0]$5410 \ren_delay$10$next + sync posedge \coresync_clk + update \ren_delay$10 $0\ren_delay$10[0:0]$5410 + end + attribute \src "libresoc.v:135838.3-135839.35" + process $proc$libresoc.v:135838$5411 + assign { } { } + assign $0\ren_delay[0:0] \ren_delay$next + sync posedge \coresync_clk + update \ren_delay $0\ren_delay[0:0] + end + attribute \src "libresoc.v:135854.3-135860.6" + process $proc$libresoc.v:135854$5412 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0$memwr$\memory$libresoc.v:135859$5406_ADDR[2:0]$5416 3'xxx + assign $0$memwr$\memory$libresoc.v:135859$5406_DATA[63:0]$5417 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\memory$libresoc.v:135859$5406_EN[63:0]$5418 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\memory$libresoc.v:135858$5405_ADDR[2:0]$5413 3'xxx + assign $0$memwr$\memory$libresoc.v:135858$5405_DATA[63:0]$5414 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\memory$libresoc.v:135858$5405_EN[63:0]$5415 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\_0_[2:0] \src1__addr + assign $0\_1_[2:0] \src2__addr + assign $0\_2_[2:0] \issue__addr + attribute \src "libresoc.v:135858.5-135858.62" + switch \issue__wen + attribute \src "libresoc.v:135858.9-135858.19" + case 1'1 + assign $0$memwr$\memory$libresoc.v:135858$5405_ADDR[2:0]$5413 \issue__addr$1 + assign $0$memwr$\memory$libresoc.v:135858$5405_DATA[63:0]$5414 \issue__data_i + assign $0$memwr$\memory$libresoc.v:135858$5405_EN[63:0]$5415 64'1111111111111111111111111111111111111111111111111111111111111111 + case + end + attribute \src "libresoc.v:135859.5-135859.58" + switch \dest1__wen + attribute \src "libresoc.v:135859.9-135859.19" + case 1'1 + assign $0$memwr$\memory$libresoc.v:135859$5406_ADDR[2:0]$5416 \dest1__addr + assign $0$memwr$\memory$libresoc.v:135859$5406_DATA[63:0]$5417 \dest1__data_i + assign $0$memwr$\memory$libresoc.v:135859$5406_EN[63:0]$5418 64'1111111111111111111111111111111111111111111111111111111111111111 + case + end + sync posedge \coresync_clk + update \_0_ $0\_0_[2:0] + update \_1_ $0\_1_[2:0] + update \_2_ $0\_2_[2:0] + update $memwr$\memory$libresoc.v:135858$5405_ADDR $0$memwr$\memory$libresoc.v:135858$5405_ADDR[2:0]$5413 + update $memwr$\memory$libresoc.v:135858$5405_DATA $0$memwr$\memory$libresoc.v:135858$5405_DATA[63:0]$5414 + update $memwr$\memory$libresoc.v:135858$5405_EN $0$memwr$\memory$libresoc.v:135858$5405_EN[63:0]$5415 + update $memwr$\memory$libresoc.v:135859$5406_ADDR $0$memwr$\memory$libresoc.v:135859$5406_ADDR[2:0]$5416 + update $memwr$\memory$libresoc.v:135859$5406_DATA $0$memwr$\memory$libresoc.v:135859$5406_DATA[63:0]$5417 + update $memwr$\memory$libresoc.v:135859$5406_EN $0$memwr$\memory$libresoc.v:135859$5406_EN[63:0]$5418 + end + attribute \src "libresoc.v:135864.3-135872.6" + process $proc$libresoc.v:135864$5422 + assign { } { } + assign { } { } + assign $0\ren_delay$next[0:0]$5423 $1\ren_delay$next[0:0]$5424 + attribute \src "libresoc.v:135865.5-135865.29" + switch \initial + attribute \src "libresoc.v:135865.9-135865.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ren_delay$next[0:0]$5424 1'0 + case + assign $1\ren_delay$next[0:0]$5424 \src1__ren + end + sync always + update \ren_delay$next $0\ren_delay$next[0:0]$5423 + end + attribute \src "libresoc.v:135873.3-135882.6" + process $proc$libresoc.v:135873$5425 + assign { } { } + assign { } { } + assign $0\src1__data_o[63:0] $1\src1__data_o[63:0] + attribute \src "libresoc.v:135874.5-135874.29" + switch \initial + attribute \src "libresoc.v:135874.9-135874.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" + switch \ren_delay + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src1__data_o[63:0] \memory_r_data + case + assign $1\src1__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \src1__data_o $0\src1__data_o[63:0] + end + attribute \src "libresoc.v:135883.3-135891.6" + process $proc$libresoc.v:135883$5426 + assign { } { } + assign { } { } + assign $0\ren_delay$10$next[0:0]$5427 $1\ren_delay$10$next[0:0]$5428 + attribute \src "libresoc.v:135884.5-135884.29" + switch \initial + attribute \src "libresoc.v:135884.9-135884.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ren_delay$10$next[0:0]$5428 1'0 + case + assign $1\ren_delay$10$next[0:0]$5428 \src2__ren + end + sync always + update \ren_delay$10$next $0\ren_delay$10$next[0:0]$5427 + end + attribute \src "libresoc.v:135892.3-135901.6" + process $proc$libresoc.v:135892$5429 + assign { } { } + assign { } { } + assign $0\src2__data_o[63:0] $1\src2__data_o[63:0] + attribute \src "libresoc.v:135893.5-135893.29" + switch \initial + attribute \src "libresoc.v:135893.9-135893.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" + switch \ren_delay$10 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src2__data_o[63:0] \memory_r_data$4 + case + assign $1\src2__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \src2__data_o $0\src2__data_o[63:0] + end + attribute \src "libresoc.v:135902.3-135910.6" + process $proc$libresoc.v:135902$5430 + assign { } { } + assign { } { } + assign $0\ren_delay$11$next[0:0]$5431 $1\ren_delay$11$next[0:0]$5432 + attribute \src "libresoc.v:135903.5-135903.29" + switch \initial + attribute \src "libresoc.v:135903.9-135903.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ren_delay$11$next[0:0]$5432 1'0 + case + assign $1\ren_delay$11$next[0:0]$5432 \issue__ren + end + sync always + update \ren_delay$11$next $0\ren_delay$11$next[0:0]$5431 + end + attribute \src "libresoc.v:135911.3-135920.6" + process $proc$libresoc.v:135911$5433 + assign { } { } + assign { } { } + assign $0\issue__data_o[63:0] $1\issue__data_o[63:0] + attribute \src "libresoc.v:135912.5-135912.29" + switch \initial + attribute \src "libresoc.v:135912.9-135912.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" + switch \ren_delay$11 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\issue__data_o[63:0] \memory_r_data$6 + case + assign $1\issue__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \issue__data_o $0\issue__data_o[63:0] + end + connect \memory_r_data $memrd$\memory$libresoc.v:135861$5419_DATA + connect \memory_r_data$4 $memrd$\memory$libresoc.v:135862$5420_DATA + connect \memory_r_data$6 $memrd$\memory$libresoc.v:135863$5421_DATA + connect \memory_w_data$9 \issue__data_i + connect \memory_w_en$7 \issue__wen + connect \memory_w_addr$8 \issue__addr$1 + connect \memory_w_data \dest1__data_i + connect \memory_w_en \dest1__wen + connect \memory_w_addr \dest1__addr + connect \memory_r_addr$5 \issue__addr + connect \memory_r_addr$3 \src2__addr + connect \memory_r_addr \src1__addr +end +attribute \src "libresoc.v:135934.1-137864.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus" +attribute \generator "nMigen" +module \fus + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 330 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 257 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 258 \cr_a_ok$110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 259 \cr_a_ok$111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 260 \cr_a_ok$112 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 261 \cr_a_ok$113 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 262 \cr_a_ok$114 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire input 3 \cu_ad__go_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire output 4 \cu_ad__rel_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" + wire output 25 \cu_busy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" + wire output 75 \cu_busy_o$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" + wire output 82 \cu_busy_o$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" + wire output 103 \cu_busy_o$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" + wire output 31 \cu_busy_o$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" + wire output 118 \cu_busy_o$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" + wire output 138 \cu_busy_o$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" + wire output 157 \cu_busy_o$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" + wire output 42 \cu_busy_o$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" + wire output 54 \cu_busy_o$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" + wire input 24 \cu_issue_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" + wire input 30 \cu_issue_i$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" + wire input 74 \cu_issue_i$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" + wire input 81 \cu_issue_i$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" + wire input 102 \cu_issue_i$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" + wire input 117 \cu_issue_i$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" + wire input 137 \cu_issue_i$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" + wire input 156 \cu_issue_i$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" + wire input 41 \cu_issue_i$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" + wire input 53 \cu_issue_i$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 4 input 160 \cu_rd__go_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 6 input 163 \cu_rd__go_i$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 4 input 166 \cu_rd__go_i$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 input 169 \cu_rd__go_i$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 6 input 172 \cu_rd__go_i$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 input 175 \cu_rd__go_i$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 input 178 \cu_rd__go_i$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 5 input 181 \cu_rd__go_i$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 input 184 \cu_rd__go_i$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 input 209 \cu_rd__go_i$70 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 4 output 159 \cu_rd__rel_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 6 output 162 \cu_rd__rel_o$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 4 output 165 \cu_rd__rel_o$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 output 168 \cu_rd__rel_o$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 6 output 171 \cu_rd__rel_o$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 output 174 \cu_rd__rel_o$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 output 177 \cu_rd__rel_o$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 5 output 180 \cu_rd__rel_o$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 output 183 \cu_rd__rel_o$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 output 208 \cu_rd__rel_o$69 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" + wire width 4 input 26 \cu_rdmaskn_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" + wire width 3 input 76 \cu_rdmaskn_i$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" + wire width 6 input 83 \cu_rdmaskn_i$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" + wire width 3 input 104 \cu_rdmaskn_i$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" + wire width 3 input 119 \cu_rdmaskn_i$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" + wire width 5 input 139 \cu_rdmaskn_i$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" + wire width 3 input 158 \cu_rdmaskn_i$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" + wire width 6 input 32 \cu_rdmaskn_i$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" + wire width 3 input 43 \cu_rdmaskn_i$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" + wire width 4 input 55 \cu_rdmaskn_i$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire input 5 \cu_st__go_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire output 2 \cu_st__rel_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 5 input 221 \cu_wr__go_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 input 242 \cu_wr__go_i$100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 2 input 244 \cu_wr__go_i$102 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 input 293 \cu_wr__go_i$137 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 input 224 \cu_wr__go_i$82 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 5 input 227 \cu_wr__go_i$85 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 2 input 230 \cu_wr__go_i$88 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 6 input 233 \cu_wr__go_i$91 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 4 input 236 \cu_wr__go_i$94 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 4 input 239 \cu_wr__go_i$97 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 5 output 220 \cu_wr__rel_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 2 output 243 \cu_wr__rel_o$101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 output 292 \cu_wr__rel_o$136 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 output 223 \cu_wr__rel_o$81 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 5 output 226 \cu_wr__rel_o$84 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 2 output 229 \cu_wr__rel_o$87 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 6 output 232 \cu_wr__rel_o$90 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 4 output 235 \cu_wr__rel_o$93 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 4 output 238 \cu_wr__rel_o$96 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 output 241 \cu_wr__rel_o$99 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 245 \dest1_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 246 \dest1_o$103 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 247 \dest1_o$104 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 248 \dest1_o$105 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 249 \dest1_o$106 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 250 \dest1_o$107 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 251 \dest1_o$108 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 252 \dest1_o$109 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 298 \dest1_o$141 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 32 output 256 \dest2_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 4 output 263 \dest2_o$115 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 4 output 265 \dest2_o$116 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 4 output 266 \dest2_o$117 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 4 output 267 \dest2_o$118 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 4 output 268 \dest2_o$119 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 299 \dest2_o$142 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 301 \dest2_o$144 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 310 \dest2_o$150 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 4 output 264 \dest3_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 2 output 272 \dest3_o$122 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 2 output 274 \dest3_o$123 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 2 output 281 \dest3_o$127 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 2 output 282 \dest3_o$128 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 300 \dest3_o$143 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 302 \dest3_o$145 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 305 \dest3_o$147 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 2 output 279 \dest4_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire output 288 \dest4_o$133 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire output 289 \dest4_o$134 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire output 290 \dest4_o$135 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 306 \dest4_o$148 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 2 output 280 \dest5_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire output 287 \dest5_o$132 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 308 \dest5_o$149 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 2 output 273 \dest6_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 254 \ea + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 291 \fast1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 294 \fast1_ok$138 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 295 \fast1_ok$139 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 296 \fast2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 297 \fast2_ok$140 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 255 \full_cr_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 96 output 315 \ldst_port0_addr_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 316 \ldst_port0_addr_i_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:109" + wire input 325 \ldst_port0_addr_ok_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:105" + wire input 311 \ldst_port0_busy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102" + wire width 4 output 314 \ldst_port0_data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire input 317 \ldst_port0_exc_$signal + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire input 318 \ldst_port0_exc_$signal$151 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire input 319 \ldst_port0_exc_$signal$152 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire input 320 \ldst_port0_exc_$signal$153 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire input 321 \ldst_port0_exc_$signal$154 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire input 322 \ldst_port0_exc_$signal$155 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire input 323 \ldst_port0_exc_$signal$156 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire input 324 \ldst_port0_exc_$signal$157 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:98" + wire output 312 \ldst_port0_is_ld_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" + wire output 313 \ldst_port0_is_st_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 input 326 \ldst_port0_ld_data_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire input 327 \ldst_port0_ld_data_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 328 \ldst_port0_st_data_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 329 \ldst_port0_st_data_i_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 307 \msr_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 303 \nia_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 304 \nia_ok$146 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 253 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 219 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 222 \o_ok$80 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 225 \o_ok$83 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 228 \o_ok$86 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 231 \o_ok$89 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 234 \o_ok$92 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 237 \o_ok$95 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 240 \o_ok$98 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 22 \oper_i_alu_alu0__data_len + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 input 7 \oper_i_alu_alu0__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 8 \oper_i_alu_alu0__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \oper_i_alu_alu0__imm_data__ok + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 18 \oper_i_alu_alu0__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 23 \oper_i_alu_alu0__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 6 \oper_i_alu_alu0__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \oper_i_alu_alu0__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 16 \oper_i_alu_alu0__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 20 \oper_i_alu_alu0__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 21 \oper_i_alu_alu0__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \oper_i_alu_alu0__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \oper_i_alu_alu0__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 19 \oper_i_alu_alu0__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 11 \oper_i_alu_alu0__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \oper_i_alu_alu0__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 17 \oper_i_alu_alu0__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 15 \oper_i_alu_alu0__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 33 \oper_i_alu_branch0__cia + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 input 35 \oper_i_alu_branch0__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 37 \oper_i_alu_branch0__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 38 \oper_i_alu_branch0__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 36 \oper_i_alu_branch0__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 34 \oper_i_alu_branch0__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 40 \oper_i_alu_branch0__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 39 \oper_i_alu_branch0__lk + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 input 28 \oper_i_alu_cr0__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 29 \oper_i_alu_cr0__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 27 \oper_i_alu_cr0__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 100 \oper_i_alu_div0__data_len + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 input 85 \oper_i_alu_div0__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 86 \oper_i_alu_div0__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 87 \oper_i_alu_div0__imm_data__ok + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 94 \oper_i_alu_div0__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 101 \oper_i_alu_div0__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 84 \oper_i_alu_div0__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 92 \oper_i_alu_div0__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 95 \oper_i_alu_div0__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 98 \oper_i_alu_div0__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 99 \oper_i_alu_div0__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 90 \oper_i_alu_div0__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 91 \oper_i_alu_div0__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 97 \oper_i_alu_div0__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 89 \oper_i_alu_div0__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 88 \oper_i_alu_div0__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 96 \oper_i_alu_div0__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 93 \oper_i_alu_div0__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 72 \oper_i_alu_logical0__data_len + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 input 57 \oper_i_alu_logical0__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 58 \oper_i_alu_logical0__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 59 \oper_i_alu_logical0__imm_data__ok + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 66 \oper_i_alu_logical0__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 73 \oper_i_alu_logical0__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 56 \oper_i_alu_logical0__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 64 \oper_i_alu_logical0__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 67 \oper_i_alu_logical0__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 70 \oper_i_alu_logical0__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 71 \oper_i_alu_logical0__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 62 \oper_i_alu_logical0__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 63 \oper_i_alu_logical0__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 69 \oper_i_alu_logical0__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 61 \oper_i_alu_logical0__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 60 \oper_i_alu_logical0__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 68 \oper_i_alu_logical0__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 65 \oper_i_alu_logical0__zero_a + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 input 106 \oper_i_alu_mul0__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 107 \oper_i_alu_mul0__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 108 \oper_i_alu_mul0__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 116 \oper_i_alu_mul0__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 105 \oper_i_alu_mul0__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 114 \oper_i_alu_mul0__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 115 \oper_i_alu_mul0__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 111 \oper_i_alu_mul0__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 112 \oper_i_alu_mul0__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 110 \oper_i_alu_mul0__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 109 \oper_i_alu_mul0__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 113 \oper_i_alu_mul0__write_cr0 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 input 121 \oper_i_alu_shift_rot0__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 122 \oper_i_alu_shift_rot0__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 123 \oper_i_alu_shift_rot0__imm_data__ok + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 130 \oper_i_alu_shift_rot0__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 132 \oper_i_alu_shift_rot0__input_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 136 \oper_i_alu_shift_rot0__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 120 \oper_i_alu_shift_rot0__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 129 \oper_i_alu_shift_rot0__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 134 \oper_i_alu_shift_rot0__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 135 \oper_i_alu_shift_rot0__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 126 \oper_i_alu_shift_rot0__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 127 \oper_i_alu_shift_rot0__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 131 \oper_i_alu_shift_rot0__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 133 \oper_i_alu_shift_rot0__output_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 125 \oper_i_alu_shift_rot0__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 124 \oper_i_alu_shift_rot0__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 128 \oper_i_alu_shift_rot0__write_cr0 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 input 78 \oper_i_alu_spr0__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 79 \oper_i_alu_spr0__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 77 \oper_i_alu_spr0__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 80 \oper_i_alu_spr0__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 48 \oper_i_alu_trap0__cia + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 input 45 \oper_i_alu_trap0__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 46 \oper_i_alu_trap0__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 44 \oper_i_alu_trap0__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 49 \oper_i_alu_trap0__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 8 input 52 \oper_i_alu_trap0__ldst_exc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 47 \oper_i_alu_trap0__msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 input 51 \oper_i_alu_trap0__trapaddr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 8 input 50 \oper_i_alu_trap0__traptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 152 \oper_i_ldst_ldst0__byte_reverse + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 151 \oper_i_ldst_ldst0__data_len + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 input 141 \oper_i_ldst_ldst0__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 142 \oper_i_ldst_ldst0__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 143 \oper_i_ldst_ldst0__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 155 \oper_i_ldst_ldst0__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 140 \oper_i_ldst_ldst0__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 149 \oper_i_ldst_ldst0__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 150 \oper_i_ldst_ldst0__is_signed + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 154 \oper_i_ldst_ldst0__ldst_mode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 147 \oper_i_ldst_ldst0__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 148 \oper_i_ldst_ldst0__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 146 \oper_i_ldst_ldst0__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 145 \oper_i_ldst_ldst0__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 153 \oper_i_ldst_ldst0__sign_extend + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 144 \oper_i_ldst_ldst0__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 309 \spr1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 161 \src1_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 164 \src1_i$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 167 \src1_i$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 170 \src1_i$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 173 \src1_i$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 176 \src1_i$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 179 \src1_i$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 182 \src1_i$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 185 \src1_i$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 213 \src1_i$74 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 186 \src2_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 187 \src2_i$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 188 \src2_i$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 189 \src2_i$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 190 \src2_i$55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 191 \src2_i$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 192 \src2_i$57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 193 \src2_i$58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 216 \src2_i$77 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 218 \src2_i$79 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 194 \src3_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 195 \src3_i$59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire input 196 \src3_i$60 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire input 197 \src3_i$61 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire input 199 \src3_i$62 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire input 200 \src3_i$63 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 32 input 206 \src3_i$67 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 4 input 210 \src3_i$71 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 214 \src3_i$75 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 215 \src3_i$76 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire input 198 \src4_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire input 201 \src4_i$64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 2 input 202 \src4_i$65 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 4 input 207 \src4_i$68 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 217 \src4_i$78 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 2 input 204 \src5_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 2 input 205 \src5_i$66 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 4 input 211 \src5_i$72 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 2 input 203 \src6_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 4 input 212 \src6_i$73 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 269 \xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 270 \xer_ca_ok$120 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 271 \xer_ca_ok$121 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 275 \xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 276 \xer_ov_ok$124 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 277 \xer_ov_ok$125 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 278 \xer_ov_ok$126 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 283 \xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 284 \xer_so_ok$129 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 285 \xer_so_ok$130 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 286 \xer_so_ok$131 + attribute \module_not_derived 1 + attribute \src "libresoc.v:137496.8-137538.4" + cell \alu0 \alu0 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cr_a_ok \cr_a_ok + connect \cu_busy_o \cu_busy_o + connect \cu_issue_i \cu_issue_i + connect \cu_rd__go_i \cu_rd__go_i + connect \cu_rd__rel_o \cu_rd__rel_o + connect \cu_rdmaskn_i \cu_rdmaskn_i + connect \cu_wr__go_i \cu_wr__go_i + connect \cu_wr__rel_o \cu_wr__rel_o + connect \dest1_o \dest1_o + connect \dest2_o \dest2_o$115 + connect \dest3_o \dest3_o$122 + connect \dest4_o \dest4_o + connect \dest5_o \dest5_o$132 + connect \o_ok \o_ok + connect \oper_i_alu_alu0__data_len \oper_i_alu_alu0__data_len + connect \oper_i_alu_alu0__fn_unit \oper_i_alu_alu0__fn_unit + connect \oper_i_alu_alu0__imm_data__data \oper_i_alu_alu0__imm_data__data + connect \oper_i_alu_alu0__imm_data__ok \oper_i_alu_alu0__imm_data__ok + connect \oper_i_alu_alu0__input_carry \oper_i_alu_alu0__input_carry + connect \oper_i_alu_alu0__insn \oper_i_alu_alu0__insn + connect \oper_i_alu_alu0__insn_type \oper_i_alu_alu0__insn_type + connect \oper_i_alu_alu0__invert_in \oper_i_alu_alu0__invert_in + connect \oper_i_alu_alu0__invert_out \oper_i_alu_alu0__invert_out + connect \oper_i_alu_alu0__is_32bit \oper_i_alu_alu0__is_32bit + connect \oper_i_alu_alu0__is_signed \oper_i_alu_alu0__is_signed + connect \oper_i_alu_alu0__oe__oe \oper_i_alu_alu0__oe__oe + connect \oper_i_alu_alu0__oe__ok \oper_i_alu_alu0__oe__ok + connect \oper_i_alu_alu0__output_carry \oper_i_alu_alu0__output_carry + connect \oper_i_alu_alu0__rc__ok \oper_i_alu_alu0__rc__ok + connect \oper_i_alu_alu0__rc__rc \oper_i_alu_alu0__rc__rc + connect \oper_i_alu_alu0__write_cr0 \oper_i_alu_alu0__write_cr0 + connect \oper_i_alu_alu0__zero_a \oper_i_alu_alu0__zero_a + connect \src1_i \src1_i + connect \src2_i \src2_i + connect \src3_i \src3_i$60 + connect \src4_i \src4_i$65 + connect \xer_ca_ok \xer_ca_ok + connect \xer_ov_ok \xer_ov_ok + connect \xer_so_ok \xer_so_ok + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:137539.11-137566.4" + cell \branch0 \branch0 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cu_busy_o \cu_busy_o$5 + connect \cu_issue_i \cu_issue_i$4 + connect \cu_rd__go_i \cu_rd__go_i$70 + connect \cu_rd__rel_o \cu_rd__rel_o$69 + connect \cu_rdmaskn_i \cu_rdmaskn_i$6 + connect \cu_wr__go_i \cu_wr__go_i$137 + connect \cu_wr__rel_o \cu_wr__rel_o$136 + connect \dest1_o \dest1_o$141 + connect \dest2_o \dest2_o$144 + connect \dest3_o \dest3_o$147 + connect \fast1_ok \fast1_ok + connect \fast2_ok \fast2_ok + connect \nia_ok \nia_ok + connect \oper_i_alu_branch0__cia \oper_i_alu_branch0__cia + connect \oper_i_alu_branch0__fn_unit \oper_i_alu_branch0__fn_unit + connect \oper_i_alu_branch0__imm_data__data \oper_i_alu_branch0__imm_data__data + connect \oper_i_alu_branch0__imm_data__ok \oper_i_alu_branch0__imm_data__ok + connect \oper_i_alu_branch0__insn \oper_i_alu_branch0__insn + connect \oper_i_alu_branch0__insn_type \oper_i_alu_branch0__insn_type + connect \oper_i_alu_branch0__is_32bit \oper_i_alu_branch0__is_32bit + connect \oper_i_alu_branch0__lk \oper_i_alu_branch0__lk + connect \src1_i \src1_i$74 + connect \src2_i \src2_i$77 + connect \src3_i \src3_i$71 + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:137567.7-137592.4" + cell \cr0 \cr0 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cr_a_ok \cr_a_ok$110 + connect \cu_busy_o \cu_busy_o$2 + connect \cu_issue_i \cu_issue_i$1 + connect \cu_rd__go_i \cu_rd__go_i$29 + connect \cu_rd__rel_o \cu_rd__rel_o$28 + connect \cu_rdmaskn_i \cu_rdmaskn_i$3 + connect \cu_wr__go_i \cu_wr__go_i$82 + connect \cu_wr__rel_o \cu_wr__rel_o$81 + connect \dest1_o \dest1_o$103 + connect \dest2_o \dest2_o + connect \dest3_o \dest3_o + connect \full_cr_ok \full_cr_ok + connect \o_ok \o_ok$80 + connect \oper_i_alu_cr0__fn_unit \oper_i_alu_cr0__fn_unit + connect \oper_i_alu_cr0__insn \oper_i_alu_cr0__insn + connect \oper_i_alu_cr0__insn_type \oper_i_alu_cr0__insn_type + connect \src1_i \src1_i$30 + connect \src2_i \src2_i$52 + connect \src3_i \src3_i$67 + connect \src4_i \src4_i$68 + connect \src5_i \src5_i$72 + connect \src6_i \src6_i$73 + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:137593.8-137632.4" + cell \div0 \div0 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cr_a_ok \cr_a_ok$112 + connect \cu_busy_o \cu_busy_o$17 + connect \cu_issue_i \cu_issue_i$16 + connect \cu_rd__go_i \cu_rd__go_i$41 + connect \cu_rd__rel_o \cu_rd__rel_o$40 + connect \cu_rdmaskn_i \cu_rdmaskn_i$18 + connect \cu_wr__go_i \cu_wr__go_i$94 + connect \cu_wr__rel_o \cu_wr__rel_o$93 + connect \dest1_o \dest1_o$107 + connect \dest2_o \dest2_o$117 + connect \dest3_o \dest3_o$127 + connect \dest4_o \dest4_o$134 + connect \o_ok \o_ok$92 + connect \oper_i_alu_div0__data_len \oper_i_alu_div0__data_len + connect \oper_i_alu_div0__fn_unit \oper_i_alu_div0__fn_unit + connect \oper_i_alu_div0__imm_data__data \oper_i_alu_div0__imm_data__data + connect \oper_i_alu_div0__imm_data__ok \oper_i_alu_div0__imm_data__ok + connect \oper_i_alu_div0__input_carry \oper_i_alu_div0__input_carry + connect \oper_i_alu_div0__insn \oper_i_alu_div0__insn + connect \oper_i_alu_div0__insn_type \oper_i_alu_div0__insn_type + connect \oper_i_alu_div0__invert_in \oper_i_alu_div0__invert_in + connect \oper_i_alu_div0__invert_out \oper_i_alu_div0__invert_out + connect \oper_i_alu_div0__is_32bit \oper_i_alu_div0__is_32bit + connect \oper_i_alu_div0__is_signed \oper_i_alu_div0__is_signed + connect \oper_i_alu_div0__oe__oe \oper_i_alu_div0__oe__oe + connect \oper_i_alu_div0__oe__ok \oper_i_alu_div0__oe__ok + connect \oper_i_alu_div0__output_carry \oper_i_alu_div0__output_carry + connect \oper_i_alu_div0__rc__ok \oper_i_alu_div0__rc__ok + connect \oper_i_alu_div0__rc__rc \oper_i_alu_div0__rc__rc + connect \oper_i_alu_div0__write_cr0 \oper_i_alu_div0__write_cr0 + connect \oper_i_alu_div0__zero_a \oper_i_alu_div0__zero_a + connect \src1_i \src1_i$42 + connect \src2_i \src2_i$55 + connect \src3_i \src3_i$62 + connect \xer_ov_ok \xer_ov_ok$125 + connect \xer_so_ok \xer_so_ok$130 + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:137633.9-137687.4" + cell \ldst0 \ldst0 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cu_ad__go_i \cu_ad__go_i + connect \cu_ad__rel_o \cu_ad__rel_o + connect \cu_busy_o \cu_busy_o$26 + connect \cu_issue_i \cu_issue_i$25 + connect \cu_rd__go_i \cu_rd__go_i$50 + connect \cu_rd__rel_o \cu_rd__rel_o$49 + connect \cu_rdmaskn_i \cu_rdmaskn_i$27 + connect \cu_st__go_i \cu_st__go_i + connect \cu_st__rel_o \cu_st__rel_o + connect \cu_wr__go_i \cu_wr__go_i$102 + connect \cu_wr__rel_o \cu_wr__rel_o$101 + connect \ea \ea + connect \ldst_port0_addr_i \ldst_port0_addr_i + connect \ldst_port0_addr_i_ok \ldst_port0_addr_i_ok + connect \ldst_port0_addr_ok_o \ldst_port0_addr_ok_o + connect \ldst_port0_busy_o \ldst_port0_busy_o + connect \ldst_port0_data_len \ldst_port0_data_len + connect \ldst_port0_exc_$signal \ldst_port0_exc_$signal + connect \ldst_port0_exc_$signal$1 \ldst_port0_exc_$signal$151 + connect \ldst_port0_exc_$signal$2 \ldst_port0_exc_$signal$152 + connect \ldst_port0_exc_$signal$3 \ldst_port0_exc_$signal$153 + connect \ldst_port0_exc_$signal$4 \ldst_port0_exc_$signal$154 + connect \ldst_port0_exc_$signal$5 \ldst_port0_exc_$signal$155 + connect \ldst_port0_exc_$signal$6 \ldst_port0_exc_$signal$156 + connect \ldst_port0_exc_$signal$7 \ldst_port0_exc_$signal$157 + connect \ldst_port0_is_ld_i \ldst_port0_is_ld_i + connect \ldst_port0_is_st_i \ldst_port0_is_st_i + connect \ldst_port0_ld_data_o \ldst_port0_ld_data_o + connect \ldst_port0_ld_data_o_ok \ldst_port0_ld_data_o_ok + connect \ldst_port0_st_data_i \ldst_port0_st_data_i + connect \ldst_port0_st_data_i_ok \ldst_port0_st_data_i_ok + connect \o \o + connect \oper_i_ldst_ldst0__byte_reverse \oper_i_ldst_ldst0__byte_reverse + connect \oper_i_ldst_ldst0__data_len \oper_i_ldst_ldst0__data_len + connect \oper_i_ldst_ldst0__fn_unit \oper_i_ldst_ldst0__fn_unit + connect \oper_i_ldst_ldst0__imm_data__data \oper_i_ldst_ldst0__imm_data__data + connect \oper_i_ldst_ldst0__imm_data__ok \oper_i_ldst_ldst0__imm_data__ok + connect \oper_i_ldst_ldst0__insn \oper_i_ldst_ldst0__insn + connect \oper_i_ldst_ldst0__insn_type \oper_i_ldst_ldst0__insn_type + connect \oper_i_ldst_ldst0__is_32bit \oper_i_ldst_ldst0__is_32bit + connect \oper_i_ldst_ldst0__is_signed \oper_i_ldst_ldst0__is_signed + connect \oper_i_ldst_ldst0__ldst_mode \oper_i_ldst_ldst0__ldst_mode + connect \oper_i_ldst_ldst0__oe__oe \oper_i_ldst_ldst0__oe__oe + connect \oper_i_ldst_ldst0__oe__ok \oper_i_ldst_ldst0__oe__ok + connect \oper_i_ldst_ldst0__rc__ok \oper_i_ldst_ldst0__rc__ok + connect \oper_i_ldst_ldst0__rc__rc \oper_i_ldst_ldst0__rc__rc + connect \oper_i_ldst_ldst0__sign_extend \oper_i_ldst_ldst0__sign_extend + connect \oper_i_ldst_ldst0__zero_a \oper_i_ldst_ldst0__zero_a + connect \src1_i \src1_i$51 + connect \src2_i \src2_i$58 + connect \src3_i \src3_i$59 + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:137688.12-137723.4" + cell \logical0 \logical0 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cr_a_ok \cr_a_ok$111 + connect \cu_busy_o \cu_busy_o$11 + connect \cu_issue_i \cu_issue_i$10 + connect \cu_rd__go_i \cu_rd__go_i$35 + connect \cu_rd__rel_o \cu_rd__rel_o$34 + connect \cu_rdmaskn_i \cu_rdmaskn_i$12 + connect \cu_wr__go_i \cu_wr__go_i$88 + connect \cu_wr__rel_o \cu_wr__rel_o$87 + connect \dest1_o \dest1_o$105 + connect \dest2_o \dest2_o$116 + connect \o_ok \o_ok$86 + connect \oper_i_alu_logical0__data_len \oper_i_alu_logical0__data_len + connect \oper_i_alu_logical0__fn_unit \oper_i_alu_logical0__fn_unit + connect \oper_i_alu_logical0__imm_data__data \oper_i_alu_logical0__imm_data__data + connect \oper_i_alu_logical0__imm_data__ok \oper_i_alu_logical0__imm_data__ok + connect \oper_i_alu_logical0__input_carry \oper_i_alu_logical0__input_carry + connect \oper_i_alu_logical0__insn \oper_i_alu_logical0__insn + connect \oper_i_alu_logical0__insn_type \oper_i_alu_logical0__insn_type + connect \oper_i_alu_logical0__invert_in \oper_i_alu_logical0__invert_in + connect \oper_i_alu_logical0__invert_out \oper_i_alu_logical0__invert_out + connect \oper_i_alu_logical0__is_32bit \oper_i_alu_logical0__is_32bit + connect \oper_i_alu_logical0__is_signed \oper_i_alu_logical0__is_signed + connect \oper_i_alu_logical0__oe__oe \oper_i_alu_logical0__oe__oe + connect \oper_i_alu_logical0__oe__ok \oper_i_alu_logical0__oe__ok + connect \oper_i_alu_logical0__output_carry \oper_i_alu_logical0__output_carry + connect \oper_i_alu_logical0__rc__ok \oper_i_alu_logical0__rc__ok + connect \oper_i_alu_logical0__rc__rc \oper_i_alu_logical0__rc__rc + connect \oper_i_alu_logical0__write_cr0 \oper_i_alu_logical0__write_cr0 + connect \oper_i_alu_logical0__zero_a \oper_i_alu_logical0__zero_a + connect \src1_i \src1_i$36 + connect \src2_i \src2_i$54 + connect \src3_i \src3_i$61 + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:137724.8-137757.4" + cell \mul0 \mul0 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cr_a_ok \cr_a_ok$113 + connect \cu_busy_o \cu_busy_o$20 + connect \cu_issue_i \cu_issue_i$19 + connect \cu_rd__go_i \cu_rd__go_i$44 + connect \cu_rd__rel_o \cu_rd__rel_o$43 + connect \cu_rdmaskn_i \cu_rdmaskn_i$21 + connect \cu_wr__go_i \cu_wr__go_i$97 + connect \cu_wr__rel_o \cu_wr__rel_o$96 + connect \dest1_o \dest1_o$108 + connect \dest2_o \dest2_o$118 + connect \dest3_o \dest3_o$128 + connect \dest4_o \dest4_o$135 + connect \o_ok \o_ok$95 + connect \oper_i_alu_mul0__fn_unit \oper_i_alu_mul0__fn_unit + connect \oper_i_alu_mul0__imm_data__data \oper_i_alu_mul0__imm_data__data + connect \oper_i_alu_mul0__imm_data__ok \oper_i_alu_mul0__imm_data__ok + connect \oper_i_alu_mul0__insn \oper_i_alu_mul0__insn + connect \oper_i_alu_mul0__insn_type \oper_i_alu_mul0__insn_type + connect \oper_i_alu_mul0__is_32bit \oper_i_alu_mul0__is_32bit + connect \oper_i_alu_mul0__is_signed \oper_i_alu_mul0__is_signed + connect \oper_i_alu_mul0__oe__oe \oper_i_alu_mul0__oe__oe + connect \oper_i_alu_mul0__oe__ok \oper_i_alu_mul0__oe__ok + connect \oper_i_alu_mul0__rc__ok \oper_i_alu_mul0__rc__ok + connect \oper_i_alu_mul0__rc__rc \oper_i_alu_mul0__rc__rc + connect \oper_i_alu_mul0__write_cr0 \oper_i_alu_mul0__write_cr0 + connect \src1_i \src1_i$45 + connect \src2_i \src2_i$56 + connect \src3_i \src3_i$63 + connect \xer_ov_ok \xer_ov_ok$126 + connect \xer_so_ok \xer_so_ok$131 + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:137758.13-137796.4" + cell \shiftrot0 \shiftrot0 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cr_a_ok \cr_a_ok$114 + connect \cu_busy_o \cu_busy_o$23 + connect \cu_issue_i \cu_issue_i$22 + connect \cu_rd__go_i \cu_rd__go_i$47 + connect \cu_rd__rel_o \cu_rd__rel_o$46 + connect \cu_rdmaskn_i \cu_rdmaskn_i$24 + connect \cu_wr__go_i \cu_wr__go_i$100 + connect \cu_wr__rel_o \cu_wr__rel_o$99 + connect \dest1_o \dest1_o$109 + connect \dest2_o \dest2_o$119 + connect \dest3_o \dest3_o$123 + connect \o_ok \o_ok$98 + connect \oper_i_alu_shift_rot0__fn_unit \oper_i_alu_shift_rot0__fn_unit + connect \oper_i_alu_shift_rot0__imm_data__data \oper_i_alu_shift_rot0__imm_data__data + connect \oper_i_alu_shift_rot0__imm_data__ok \oper_i_alu_shift_rot0__imm_data__ok + connect \oper_i_alu_shift_rot0__input_carry \oper_i_alu_shift_rot0__input_carry + connect \oper_i_alu_shift_rot0__input_cr \oper_i_alu_shift_rot0__input_cr + connect \oper_i_alu_shift_rot0__insn \oper_i_alu_shift_rot0__insn + connect \oper_i_alu_shift_rot0__insn_type \oper_i_alu_shift_rot0__insn_type + connect \oper_i_alu_shift_rot0__invert_in \oper_i_alu_shift_rot0__invert_in + connect \oper_i_alu_shift_rot0__is_32bit \oper_i_alu_shift_rot0__is_32bit + connect \oper_i_alu_shift_rot0__is_signed \oper_i_alu_shift_rot0__is_signed + connect \oper_i_alu_shift_rot0__oe__oe \oper_i_alu_shift_rot0__oe__oe + connect \oper_i_alu_shift_rot0__oe__ok \oper_i_alu_shift_rot0__oe__ok + connect \oper_i_alu_shift_rot0__output_carry \oper_i_alu_shift_rot0__output_carry + connect \oper_i_alu_shift_rot0__output_cr \oper_i_alu_shift_rot0__output_cr + connect \oper_i_alu_shift_rot0__rc__ok \oper_i_alu_shift_rot0__rc__ok + connect \oper_i_alu_shift_rot0__rc__rc \oper_i_alu_shift_rot0__rc__rc + connect \oper_i_alu_shift_rot0__write_cr0 \oper_i_alu_shift_rot0__write_cr0 + connect \src1_i \src1_i$48 + connect \src2_i \src2_i$57 + connect \src3_i \src3_i + connect \src4_i \src4_i$64 + connect \src5_i \src5_i + connect \xer_ca_ok \xer_ca_ok$121 + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:137797.8-137829.4" + cell \spr0 \spr0 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cu_busy_o \cu_busy_o$14 + connect \cu_issue_i \cu_issue_i$13 + connect \cu_rd__go_i \cu_rd__go_i$38 + connect \cu_rd__rel_o \cu_rd__rel_o$37 + connect \cu_rdmaskn_i \cu_rdmaskn_i$15 + connect \cu_wr__go_i \cu_wr__go_i$91 + connect \cu_wr__rel_o \cu_wr__rel_o$90 + connect \dest1_o \dest1_o$106 + connect \dest2_o \dest2_o$150 + connect \dest3_o \dest3_o$143 + connect \dest4_o \dest4_o$133 + connect \dest5_o \dest5_o + connect \dest6_o \dest6_o + connect \fast1_ok \fast1_ok$139 + connect \o_ok \o_ok$89 + connect \oper_i_alu_spr0__fn_unit \oper_i_alu_spr0__fn_unit + connect \oper_i_alu_spr0__insn \oper_i_alu_spr0__insn + connect \oper_i_alu_spr0__insn_type \oper_i_alu_spr0__insn_type + connect \oper_i_alu_spr0__is_32bit \oper_i_alu_spr0__is_32bit + connect \spr1_ok \spr1_ok + connect \src1_i \src1_i$39 + connect \src2_i \src2_i$79 + connect \src3_i \src3_i$76 + connect \src4_i \src4_i + connect \src5_i \src5_i$66 + connect \src6_i \src6_i + connect \xer_ca_ok \xer_ca_ok$120 + connect \xer_ov_ok \xer_ov_ok$124 + connect \xer_so_ok \xer_so_ok$129 + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:137830.9-137863.4" + cell \trap0 \trap0 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cu_busy_o \cu_busy_o$8 + connect \cu_issue_i \cu_issue_i$7 + connect \cu_rd__go_i \cu_rd__go_i$32 + connect \cu_rd__rel_o \cu_rd__rel_o$31 + connect \cu_rdmaskn_i \cu_rdmaskn_i$9 + connect \cu_wr__go_i \cu_wr__go_i$85 + connect \cu_wr__rel_o \cu_wr__rel_o$84 + connect \dest1_o \dest1_o$104 + connect \dest2_o \dest2_o$142 + connect \dest3_o \dest3_o$145 + connect \dest4_o \dest4_o$148 + connect \dest5_o \dest5_o$149 + connect \fast1_ok \fast1_ok$138 + connect \fast2_ok \fast2_ok$140 + connect \msr_ok \msr_ok + connect \nia_ok \nia_ok$146 + connect \o_ok \o_ok$83 + connect \oper_i_alu_trap0__cia \oper_i_alu_trap0__cia + connect \oper_i_alu_trap0__fn_unit \oper_i_alu_trap0__fn_unit + connect \oper_i_alu_trap0__insn \oper_i_alu_trap0__insn + connect \oper_i_alu_trap0__insn_type \oper_i_alu_trap0__insn_type + connect \oper_i_alu_trap0__is_32bit \oper_i_alu_trap0__is_32bit + connect \oper_i_alu_trap0__ldst_exc \oper_i_alu_trap0__ldst_exc + connect \oper_i_alu_trap0__msr \oper_i_alu_trap0__msr + connect \oper_i_alu_trap0__trapaddr \oper_i_alu_trap0__trapaddr + connect \oper_i_alu_trap0__traptype \oper_i_alu_trap0__traptype + connect \src1_i \src1_i$33 + connect \src2_i \src2_i$53 + connect \src3_i \src3_i$75 + connect \src4_i \src4_i$78 + end +end +attribute \src "libresoc.v:137868.1-137926.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.l0.l0.idx_l" +attribute \generator "nMigen" +module \idx_l + attribute \src "libresoc.v:137869.7-137869.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:137914.3-137922.6" + wire $0\q_int$next[0:0]$5461 + attribute \src "libresoc.v:137912.3-137913.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:137914.3-137922.6" + wire $1\q_int$next[0:0]$5462 + attribute \src "libresoc.v:137893.7-137893.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:137904.17-137904.96" + wire $and$libresoc.v:137904$5451_Y + attribute \src "libresoc.v:137909.17-137909.96" + wire $and$libresoc.v:137909$5456_Y + attribute \src "libresoc.v:137906.18-137906.95" + wire $not$libresoc.v:137906$5453_Y + attribute \src "libresoc.v:137908.17-137908.94" + wire $not$libresoc.v:137908$5455_Y + attribute \src "libresoc.v:137911.17-137911.94" + wire $not$libresoc.v:137911$5458_Y + attribute \src "libresoc.v:137905.18-137905.100" + wire $or$libresoc.v:137905$5452_Y + attribute \src "libresoc.v:137907.18-137907.101" + wire $or$libresoc.v:137907$5454_Y + attribute \src "libresoc.v:137910.17-137910.99" + wire $or$libresoc.v:137910$5457_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 1 \coresync_rst + attribute \src "libresoc.v:137869.7-137869.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire output 2 \q_idx_l + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" + wire \qlq_idx_l + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \qn_idx_l + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire input 4 \r_idx_l + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire input 3 \s_idx_l + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:137904$5451 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:137904$5451_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:137909$5456 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:137909$5456_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:137906$5453 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_idx_l + connect \Y $not$libresoc.v:137906$5453_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:137908$5455 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_idx_l + connect \Y $not$libresoc.v:137908$5455_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:137911$5458 + parameter \A_SIGNED 0 + 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connect \B \s_idx_l + connect \Y $or$libresoc.v:137910$5457_Y + end + attribute \src "libresoc.v:137869.7-137869.20" + process $proc$libresoc.v:137869$5463 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:137893.7-137893.19" + process $proc$libresoc.v:137893$5464 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:137912.3-137913.27" + process $proc$libresoc.v:137912$5459 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:137914.3-137922.6" + process $proc$libresoc.v:137914$5460 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$5461 $1\q_int$next[0:0]$5462 + attribute \src "libresoc.v:137915.5-137915.29" + switch \initial + attribute \src "libresoc.v:137915.9-137915.17" + case 1'1 + case + end + attribute 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\$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" + wire \$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" + wire \$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" + wire \$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" + wire \$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" + wire \$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" + wire \$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86" + wire \$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:91" + wire \$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86" + wire \$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:91" + wire \$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:31" + wire \a_busy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:24" + wire width 48 input 2 \a_pc_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:25" + wire \a_stall_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:26" + wire input 3 \a_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:194" + wire input 15 \clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:35" + wire width 45 \f_badaddr_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:35" + wire width 45 \f_badaddr_o$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:32" + wire output 5 \f_busy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:34" + wire \f_fetch_err_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:34" + wire \f_fetch_err_o$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:33" + wire width 64 output 6 \f_instr_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:27" + wire \f_stall_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:28" + wire input 4 \f_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire input 9 \ibus__ack + attribute \src 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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire \ibus__stb$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:69" + wire width 64 \ibus_rdata + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:69" + wire width 64 \ibus_rdata$next + attribute \src "libresoc.v:137931.7-137931.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:194" + wire input 1 \rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:92" + wire input 7 \wb_icache_en + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" + cell $and $and$libresoc.v:138048$5467 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \a_valid_i + connect \B \$11 + connect \Y $and$libresoc.v:138048$5467_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" + cell $and $and$libresoc.v:138054$5473 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \a_valid_i + connect \B \$21 + connect \Y $and$libresoc.v:138054$5473_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" + cell $and $and$libresoc.v:138059$5478 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \a_valid_i + connect \B \$31 + connect \Y $and$libresoc.v:138059$5478_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" + cell $and $and$libresoc.v:138062$5481 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \a_valid_i + connect \B \$1 + connect \Y $and$libresoc.v:138062$5481_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" + cell $and $and$libresoc.v:138065$5484 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \a_valid_i + connect \B \$41 + connect \Y $and$libresoc.v:138065$5484_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86" + cell $and $and$libresoc.v:138066$5485 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ibus__cyc + connect \B \ibus__err + connect \Y $and$libresoc.v:138066$5485_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86" + cell $and $and$libresoc.v:138068$5487 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ibus__cyc + connect \B \ibus__err + connect \Y $and$libresoc.v:138068$5487_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" + cell $not $not$libresoc.v:138047$5466 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \a_stall_i + connect \Y $not$libresoc.v:138047$5466_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" + cell $not $not$libresoc.v:138050$5469 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \f_valid_i + connect \Y $not$libresoc.v:138050$5469_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" + cell $not $not$libresoc.v:138051$5470 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \a_stall_i + connect \Y $not$libresoc.v:138051$5470_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" + cell $not $not$libresoc.v:138053$5472 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \a_stall_i + connect \Y $not$libresoc.v:138053$5472_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" + cell $not $not$libresoc.v:138056$5475 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \f_valid_i + connect \Y $not$libresoc.v:138056$5475_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" + cell $not $not$libresoc.v:138058$5477 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \a_stall_i + connect \Y $not$libresoc.v:138058$5477_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" + cell $not $not$libresoc.v:138061$5480 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \f_valid_i + connect \Y $not$libresoc.v:138061$5480_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" + cell $not $not$libresoc.v:138064$5483 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \a_stall_i + connect \Y $not$libresoc.v:138064$5483_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:91" + cell $not $not$libresoc.v:138067$5486 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \f_stall_i + connect \Y $not$libresoc.v:138067$5486_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:91" + cell $not $not$libresoc.v:138069$5488 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \f_stall_i + connect \Y $not$libresoc.v:138069$5488_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" + cell $not $not$libresoc.v:138071$5490 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \f_valid_i + connect \Y $not$libresoc.v:138071$5490_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" + cell $or $or$libresoc.v:138046$5465 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$5 + connect \B \$7 + connect \Y $or$libresoc.v:138046$5465_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" + cell $or $or$libresoc.v:138049$5468 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ibus__ack + connect \B \ibus__err + connect \Y $or$libresoc.v:138049$5468_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" + cell $or $or$libresoc.v:138052$5471 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$15 + connect \B \$17 + connect \Y $or$libresoc.v:138052$5471_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" + cell $or $or$libresoc.v:138055$5474 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ibus__ack + connect \B \ibus__err + connect \Y $or$libresoc.v:138055$5474_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" + cell $or $or$libresoc.v:138057$5476 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$25 + connect \B \$27 + connect \Y $or$libresoc.v:138057$5476_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" + cell $or $or$libresoc.v:138060$5479 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ibus__ack + connect \B \ibus__err + connect \Y $or$libresoc.v:138060$5479_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" + cell $or $or$libresoc.v:138063$5482 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$35 + connect \B \$37 + connect \Y $or$libresoc.v:138063$5482_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" + cell $or $or$libresoc.v:138070$5489 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ibus__ack + connect \B \ibus__err + connect \Y $or$libresoc.v:138070$5489_Y + end + attribute \src "libresoc.v:137931.7-137931.20" + process $proc$libresoc.v:137931$5540 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:137995.14-137995.44" + process $proc$libresoc.v:137995$5541 + assign { } { } + assign $1\f_badaddr_o[44:0] 45'000000000000000000000000000000000000000000000 + sync always + sync init + update \f_badaddr_o $1\f_badaddr_o[44:0] + end + attribute \src "libresoc.v:138002.7-138002.27" + process $proc$libresoc.v:138002$5542 + assign { } { } + assign $1\f_fetch_err_o[0:0] 1'0 + sync always + sync init + update \f_fetch_err_o $1\f_fetch_err_o[0:0] + end + attribute \src "libresoc.v:138016.14-138016.42" + process $proc$libresoc.v:138016$5543 + assign { } { } + assign $1\ibus__adr[44:0] 45'000000000000000000000000000000000000000000000 + sync always + sync init + update \ibus__adr $1\ibus__adr[44:0] + end + attribute \src "libresoc.v:138021.7-138021.23" + process $proc$libresoc.v:138021$5544 + assign { } { } + assign $1\ibus__cyc[0:0] 1'0 + sync always + sync init + update \ibus__cyc $1\ibus__cyc[0:0] + end + attribute \src "libresoc.v:138030.13-138030.30" + process $proc$libresoc.v:138030$5545 + assign { } { } + assign $1\ibus__sel[7:0] 8'00000000 + sync always + sync init + update \ibus__sel $1\ibus__sel[7:0] + end + attribute \src "libresoc.v:138035.7-138035.23" + process $proc$libresoc.v:138035$5546 + assign { } { } + assign $1\ibus__stb[0:0] 1'0 + sync always + sync init + update \ibus__stb $1\ibus__stb[0:0] + end + attribute \src "libresoc.v:138039.14-138039.47" + process $proc$libresoc.v:138039$5547 + assign { } { } + assign $1\ibus_rdata[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \ibus_rdata $1\ibus_rdata[63:0] + end + attribute \src "libresoc.v:138072.3-138073.39" + process $proc$libresoc.v:138072$5491 + assign { } { } + assign $0\f_badaddr_o[44:0] \f_badaddr_o$next + sync posedge \clk + update \f_badaddr_o $0\f_badaddr_o[44:0] + end + attribute \src "libresoc.v:138074.3-138075.43" + process $proc$libresoc.v:138074$5492 + assign { } { } + assign $0\f_fetch_err_o[0:0] \f_fetch_err_o$next + sync posedge \clk + update \f_fetch_err_o $0\f_fetch_err_o[0:0] + end + attribute \src "libresoc.v:138076.3-138077.35" + process $proc$libresoc.v:138076$5493 + assign { } { } + assign $0\ibus__adr[44:0] \ibus__adr$next + sync posedge \clk + update \ibus__adr $0\ibus__adr[44:0] + end + attribute \src "libresoc.v:138078.3-138079.37" + process $proc$libresoc.v:138078$5494 + assign { } { } + assign $0\ibus_rdata[63:0] \ibus_rdata$next + sync posedge \clk + update \ibus_rdata $0\ibus_rdata[63:0] + end + attribute \src "libresoc.v:138080.3-138081.35" + process $proc$libresoc.v:138080$5495 + assign { } { } + assign $0\ibus__sel[7:0] \ibus__sel$next + sync posedge \clk + update \ibus__sel $0\ibus__sel[7:0] + end + attribute \src "libresoc.v:138082.3-138083.35" + process $proc$libresoc.v:138082$5496 + assign { } { } + assign $0\ibus__stb[0:0] \ibus__stb$next + sync posedge \clk + update \ibus__stb $0\ibus__stb[0:0] + end + attribute \src "libresoc.v:138084.3-138085.35" + process $proc$libresoc.v:138084$5497 + assign { } { } + assign $0\ibus__cyc[0:0] \ibus__cyc$next + sync posedge \clk + update \ibus__cyc $0\ibus__cyc[0:0] + end + attribute \src "libresoc.v:138086.3-138113.6" + process $proc$libresoc.v:138086$5498 + assign { } { } + assign { } { } + assign { } { } + assign $0\ibus__cyc$next[0:0]$5499 $4\ibus__cyc$next[0:0]$5503 + attribute \src "libresoc.v:138087.5-138087.29" + switch \initial + attribute \src "libresoc.v:138087.9-138087.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67" + switch \wb_icache_en + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ibus__cyc$next[0:0]$5500 $2\ibus__cyc$next[0:0]$5501 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:70" + switch { \$3 \ibus__cyc } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $2\ibus__cyc$next[0:0]$5501 $3\ibus__cyc$next[0:0]$5502 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" + switch \$9 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\ibus__cyc$next[0:0]$5502 1'0 + case + assign $3\ibus__cyc$next[0:0]$5502 \ibus__cyc + end + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $2\ibus__cyc$next[0:0]$5501 1'1 + case + assign $2\ibus__cyc$next[0:0]$5501 \ibus__cyc + end + case + assign $1\ibus__cyc$next[0:0]$5500 \ibus__cyc + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\ibus__cyc$next[0:0]$5503 1'0 + case + assign $4\ibus__cyc$next[0:0]$5503 $1\ibus__cyc$next[0:0]$5500 + end + sync always + update \ibus__cyc$next $0\ibus__cyc$next[0:0]$5499 + end + attribute \src "libresoc.v:138114.3-138141.6" + process $proc$libresoc.v:138114$5504 + assign { } { } + assign { } { } + assign { } { } + assign $0\ibus__stb$next[0:0]$5505 $4\ibus__stb$next[0:0]$5509 + attribute \src "libresoc.v:138115.5-138115.29" + switch \initial + attribute \src "libresoc.v:138115.9-138115.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67" + switch \wb_icache_en + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ibus__stb$next[0:0]$5506 $2\ibus__stb$next[0:0]$5507 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:70" + switch { \$13 \ibus__cyc } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $2\ibus__stb$next[0:0]$5507 $3\ibus__stb$next[0:0]$5508 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" + switch \$19 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\ibus__stb$next[0:0]$5508 1'0 + case + assign $3\ibus__stb$next[0:0]$5508 \ibus__stb + end + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $2\ibus__stb$next[0:0]$5507 1'1 + case + assign $2\ibus__stb$next[0:0]$5507 \ibus__stb + end + case + assign $1\ibus__stb$next[0:0]$5506 \ibus__stb + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\ibus__stb$next[0:0]$5509 1'0 + case + assign $4\ibus__stb$next[0:0]$5509 $1\ibus__stb$next[0:0]$5506 + end + sync always + update \ibus__stb$next $0\ibus__stb$next[0:0]$5505 + end + attribute \src "libresoc.v:138142.3-138169.6" + process $proc$libresoc.v:138142$5510 + assign { } { } + assign { } { } + assign { } { } + assign $0\ibus__sel$next[7:0]$5511 $4\ibus__sel$next[7:0]$5515 + attribute \src "libresoc.v:138143.5-138143.29" + switch \initial + attribute \src "libresoc.v:138143.9-138143.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67" + switch \wb_icache_en + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ibus__sel$next[7:0]$5512 $2\ibus__sel$next[7:0]$5513 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:70" + switch { \$23 \ibus__cyc } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $2\ibus__sel$next[7:0]$5513 $3\ibus__sel$next[7:0]$5514 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" + switch \$29 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\ibus__sel$next[7:0]$5514 8'00000000 + case + assign $3\ibus__sel$next[7:0]$5514 \ibus__sel + end + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $2\ibus__sel$next[7:0]$5513 8'11111111 + case + assign $2\ibus__sel$next[7:0]$5513 \ibus__sel + end + case + assign $1\ibus__sel$next[7:0]$5512 \ibus__sel + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\ibus__sel$next[7:0]$5515 8'00000000 + case + assign $4\ibus__sel$next[7:0]$5515 $1\ibus__sel$next[7:0]$5512 + end + sync always + update \ibus__sel$next $0\ibus__sel$next[7:0]$5511 + end + attribute \src "libresoc.v:138170.3-138194.6" + process $proc$libresoc.v:138170$5516 + assign { } { } + assign { } { } + assign { } { } + assign $0\ibus_rdata$next[63:0]$5517 $4\ibus_rdata$next[63:0]$5521 + attribute \src "libresoc.v:138171.5-138171.29" + switch \initial + attribute \src "libresoc.v:138171.9-138171.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67" + switch \wb_icache_en + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ibus_rdata$next[63:0]$5518 $2\ibus_rdata$next[63:0]$5519 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:70" + switch { \$33 \ibus__cyc } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $2\ibus_rdata$next[63:0]$5519 $3\ibus_rdata$next[63:0]$5520 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" + switch \$39 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\ibus_rdata$next[63:0]$5520 \ibus__dat_r + case + assign $3\ibus_rdata$next[63:0]$5520 \ibus_rdata + end + case + assign $2\ibus_rdata$next[63:0]$5519 \ibus_rdata + end + case + assign $1\ibus_rdata$next[63:0]$5518 \ibus_rdata + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\ibus_rdata$next[63:0]$5521 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $4\ibus_rdata$next[63:0]$5521 $1\ibus_rdata$next[63:0]$5518 + end + sync always + update \ibus_rdata$next $0\ibus_rdata$next[63:0]$5517 + end + attribute \src "libresoc.v:138195.3-138217.6" + process $proc$libresoc.v:138195$5522 + assign { } { } + assign { } { } + assign { } { } + assign $0\ibus__adr$next[44:0]$5523 $3\ibus__adr$next[44:0]$5526 + attribute \src "libresoc.v:138196.5-138196.29" + switch \initial + attribute \src "libresoc.v:138196.9-138196.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67" + switch \wb_icache_en + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ibus__adr$next[44:0]$5524 $2\ibus__adr$next[44:0]$5525 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:70" + switch { \$43 \ibus__cyc } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign $2\ibus__adr$next[44:0]$5525 \ibus__adr + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $2\ibus__adr$next[44:0]$5525 \a_pc_i [47:3] + case + assign $2\ibus__adr$next[44:0]$5525 \ibus__adr + end + case + assign $1\ibus__adr$next[44:0]$5524 \ibus__adr + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\ibus__adr$next[44:0]$5526 45'000000000000000000000000000000000000000000000 + case + assign $3\ibus__adr$next[44:0]$5526 $1\ibus__adr$next[44:0]$5524 + end + sync always + update \ibus__adr$next $0\ibus__adr$next[44:0]$5523 + end + attribute \src "libresoc.v:138218.3-138240.6" + process $proc$libresoc.v:138218$5527 + assign { } { } + assign { } { } + assign { } { } + assign $0\f_fetch_err_o$next[0:0]$5528 $3\f_fetch_err_o$next[0:0]$5531 + attribute \src "libresoc.v:138219.5-138219.29" + switch \initial + attribute \src "libresoc.v:138219.9-138219.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67" + switch \wb_icache_en + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\f_fetch_err_o$next[0:0]$5529 $2\f_fetch_err_o$next[0:0]$5530 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86" + switch { \$47 \$45 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $2\f_fetch_err_o$next[0:0]$5530 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $2\f_fetch_err_o$next[0:0]$5530 1'0 + case + assign $2\f_fetch_err_o$next[0:0]$5530 \f_fetch_err_o + end + case + assign $1\f_fetch_err_o$next[0:0]$5529 \f_fetch_err_o + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\f_fetch_err_o$next[0:0]$5531 1'0 + case + assign $3\f_fetch_err_o$next[0:0]$5531 $1\f_fetch_err_o$next[0:0]$5529 + end + sync always + update \f_fetch_err_o$next $0\f_fetch_err_o$next[0:0]$5528 + end + attribute \src "libresoc.v:138241.3-138260.6" + process $proc$libresoc.v:138241$5532 + assign { } { } + assign { } { } + assign { } { } + assign $0\f_badaddr_o$next[44:0]$5533 $3\f_badaddr_o$next[44:0]$5536 + attribute \src "libresoc.v:138242.5-138242.29" + switch \initial + attribute \src "libresoc.v:138242.9-138242.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67" + switch \wb_icache_en + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\f_badaddr_o$next[44:0]$5534 $2\f_badaddr_o$next[44:0]$5535 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86" + switch { \$51 \$49 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $2\f_badaddr_o$next[44:0]$5535 \ibus__adr + case + assign $2\f_badaddr_o$next[44:0]$5535 \f_badaddr_o + end + case + assign $1\f_badaddr_o$next[44:0]$5534 \f_badaddr_o + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\f_badaddr_o$next[44:0]$5536 45'000000000000000000000000000000000000000000000 + case + assign $3\f_badaddr_o$next[44:0]$5536 $1\f_badaddr_o$next[44:0]$5534 + end + sync always + update \f_badaddr_o$next $0\f_badaddr_o$next[44:0]$5533 + end + attribute \src "libresoc.v:138261.3-138270.6" + process $proc$libresoc.v:138261$5537 + assign { } { } + assign { } { } + assign $0\a_busy_o[0:0] $1\a_busy_o[0:0] + attribute \src "libresoc.v:138262.5-138262.29" + switch \initial + attribute \src "libresoc.v:138262.9-138262.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67" + switch \wb_icache_en + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\a_busy_o[0:0] \ibus__cyc + case + assign $1\a_busy_o[0:0] 1'0 + end + sync always + update \a_busy_o $0\a_busy_o[0:0] + end + attribute \src "libresoc.v:138271.3-138288.6" + process $proc$libresoc.v:138271$5538 + assign { } { } + assign { } { } + assign $0\f_busy_o[0:0] $1\f_busy_o[0:0] + attribute \src "libresoc.v:138272.5-138272.29" + switch \initial + attribute \src "libresoc.v:138272.9-138272.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67" + switch \wb_icache_en + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\f_busy_o[0:0] $2\f_busy_o[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:96" + switch \f_fetch_err_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\f_busy_o[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\f_busy_o[0:0] \ibus__cyc + end + case + assign $1\f_busy_o[0:0] 1'0 + end + sync always + update \f_busy_o $0\f_busy_o[0:0] + end + attribute \src "libresoc.v:138289.3-138306.6" + process $proc$libresoc.v:138289$5539 + assign { } { } + assign { } { } + assign $0\f_instr_o[63:0] $1\f_instr_o[63:0] + attribute \src "libresoc.v:138290.5-138290.29" + switch \initial + attribute \src "libresoc.v:138290.9-138290.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67" + switch \wb_icache_en + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\f_instr_o[63:0] $2\f_instr_o[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:96" + switch \f_fetch_err_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $2\f_instr_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\f_instr_o[63:0] \ibus_rdata + end + case + assign $1\f_instr_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \f_instr_o $0\f_instr_o[63:0] + end + connect \$9 $or$libresoc.v:138046$5465_Y + connect \$11 $not$libresoc.v:138047$5466_Y + connect \$13 $and$libresoc.v:138048$5467_Y + connect \$15 $or$libresoc.v:138049$5468_Y + connect \$17 $not$libresoc.v:138050$5469_Y + connect \$1 $not$libresoc.v:138051$5470_Y + connect \$19 $or$libresoc.v:138052$5471_Y + connect \$21 $not$libresoc.v:138053$5472_Y + connect \$23 $and$libresoc.v:138054$5473_Y + connect \$25 $or$libresoc.v:138055$5474_Y + connect \$27 $not$libresoc.v:138056$5475_Y + connect \$29 $or$libresoc.v:138057$5476_Y + connect \$31 $not$libresoc.v:138058$5477_Y + connect \$33 $and$libresoc.v:138059$5478_Y + connect \$35 $or$libresoc.v:138060$5479_Y + connect \$37 $not$libresoc.v:138061$5480_Y + connect \$3 $and$libresoc.v:138062$5481_Y + connect \$39 $or$libresoc.v:138063$5482_Y + connect \$41 $not$libresoc.v:138064$5483_Y + connect \$43 $and$libresoc.v:138065$5484_Y + connect \$45 $and$libresoc.v:138066$5485_Y + connect \$47 $not$libresoc.v:138067$5486_Y + connect \$49 $and$libresoc.v:138068$5487_Y + connect \$51 $not$libresoc.v:138069$5488_Y + connect \$5 $or$libresoc.v:138070$5489_Y + connect \$7 $not$libresoc.v:138071$5490_Y + connect \a_stall_i 1'0 + connect \f_stall_i 1'0 +end +attribute \src "libresoc.v:138313.1-138413.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.in1_svdec" +attribute \generator "nMigen" +module \in1_svdec + attribute \src "libresoc.v:138314.7-138314.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:138400.3-138411.6" + wire width 7 $0\reg_out[6:0] + attribute \src "libresoc.v:138341.3-138399.6" + wire width 3 $0\spec[2:0] + attribute \src "libresoc.v:138400.3-138411.6" + wire width 7 $1\reg_out[6:0] + attribute \src "libresoc.v:138341.3-138399.6" + wire width 3 $1\spec[2:0] + attribute \src "libresoc.v:138341.3-138399.6" + wire width 2 $2\spec[2:1] + attribute \src "libresoc.v:138341.3-138399.6" + wire width 3 $3\spec[2:0] + attribute \enum_base_type "SVEtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "EXTRA2" + attribute \enum_value_10 "EXTRA3" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:90" + wire width 2 input 1 \etype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:89" + wire width 9 input 6 \extra + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:91" + wire width 3 input 5 \idx + attribute \src "libresoc.v:138314.7-138314.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:149" + wire output 3 \isvec + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:147" + wire width 5 input 2 \reg_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:148" + wire width 7 output 4 \reg_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" + wire width 3 \spec + attribute \src "libresoc.v:138314.7-138314.20" + process $proc$libresoc.v:138314$5550 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:138341.3-138399.6" + process $proc$libresoc.v:138341$5548 + assign { } { } + assign { } { } + assign $0\spec[2:0] $1\spec[2:0] + attribute \src "libresoc.v:138342.5-138342.29" + switch \initial + attribute \src "libresoc.v:138342.9-138342.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:104" + switch \etype + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign $1\spec[2:0] [0] 1'0 + assign $1\spec[2:0] [2:1] $2\spec[2:1] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:107" + switch \idx + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $2\spec[2:1] [1] \extra [8] + assign $2\spec[2:1] [0] \extra [7] + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $2\spec[2:1] [1] \extra [6] + assign $2\spec[2:1] [0] \extra [5] + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $2\spec[2:1] [1] \extra [4] + assign $2\spec[2:1] [0] \extra [3] + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $2\spec[2:1] [1] \extra [2] + assign $2\spec[2:1] [0] \extra [1] + case + assign $2\spec[2:1] 2'00 + end + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\spec[2:0] $3\spec[2:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:122" + switch \idx + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $3\spec[2:0] \extra [8:6] + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $3\spec[2:0] \extra [5:3] + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $3\spec[2:0] \extra [2:0] + case + assign $3\spec[2:0] 3'000 + end + case + assign $1\spec[2:0] 3'000 + end + sync always + update \spec $0\spec[2:0] + end + attribute \src "libresoc.v:138400.3-138411.6" + process $proc$libresoc.v:138400$5549 + assign { } { } + assign $0\reg_out[6:0] $1\reg_out[6:0] + attribute \src "libresoc.v:138401.5-138401.29" + switch \initial + attribute \src "libresoc.v:138401.9-138401.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:166" + switch \isvec + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\reg_out[6:0] { \reg_in \spec [1:0] } + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\reg_out[6:0] { \spec [1:0] \reg_in } + end + sync always + update \reg_out $0\reg_out[6:0] + end + connect \isvec \spec [2] +end +attribute \src "libresoc.v:138417.1-138517.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.in2_svdec" +attribute \generator "nMigen" +module \in2_svdec + attribute \src "libresoc.v:138418.7-138418.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:138504.3-138515.6" + wire width 7 $0\reg_out[6:0] + attribute \src "libresoc.v:138445.3-138503.6" + wire width 3 $0\spec[2:0] + attribute \src "libresoc.v:138504.3-138515.6" + wire width 7 $1\reg_out[6:0] + attribute \src "libresoc.v:138445.3-138503.6" + wire width 3 $1\spec[2:0] + attribute \src "libresoc.v:138445.3-138503.6" + wire width 2 $2\spec[2:1] + attribute \src "libresoc.v:138445.3-138503.6" + wire width 3 $3\spec[2:0] + attribute \enum_base_type "SVEtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "EXTRA2" + attribute \enum_value_10 "EXTRA3" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:90" + wire width 2 input 1 \etype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:89" + wire width 9 input 6 \extra + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:91" + wire width 3 input 5 \idx + attribute \src "libresoc.v:138418.7-138418.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:149" + wire output 3 \isvec + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:147" + wire width 5 input 2 \reg_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:148" + wire width 7 output 4 \reg_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" + wire width 3 \spec + attribute \src "libresoc.v:138418.7-138418.20" + process $proc$libresoc.v:138418$5553 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:138445.3-138503.6" + process $proc$libresoc.v:138445$5551 + assign { } { } + assign { } { } + assign $0\spec[2:0] $1\spec[2:0] + attribute \src "libresoc.v:138446.5-138446.29" + switch \initial + attribute \src "libresoc.v:138446.9-138446.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:104" + switch \etype + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign $1\spec[2:0] [0] 1'0 + assign $1\spec[2:0] [2:1] $2\spec[2:1] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:107" + switch \idx + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $2\spec[2:1] [1] \extra [8] + assign $2\spec[2:1] [0] \extra [7] + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $2\spec[2:1] [1] \extra [6] + assign $2\spec[2:1] [0] \extra [5] + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $2\spec[2:1] [1] \extra [4] + assign $2\spec[2:1] [0] \extra [3] + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $2\spec[2:1] [1] \extra [2] + assign $2\spec[2:1] [0] \extra [1] + case + assign $2\spec[2:1] 2'00 + end + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\spec[2:0] $3\spec[2:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:122" + switch \idx + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $3\spec[2:0] \extra [8:6] + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $3\spec[2:0] \extra [5:3] + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $3\spec[2:0] \extra [2:0] + case + assign $3\spec[2:0] 3'000 + end + case + assign $1\spec[2:0] 3'000 + end + sync always + update \spec $0\spec[2:0] + end + attribute \src "libresoc.v:138504.3-138515.6" + process $proc$libresoc.v:138504$5552 + assign { } { } + assign $0\reg_out[6:0] $1\reg_out[6:0] + attribute \src "libresoc.v:138505.5-138505.29" + switch \initial + attribute \src "libresoc.v:138505.9-138505.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:166" + switch \isvec + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\reg_out[6:0] { \reg_in \spec [1:0] } + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\reg_out[6:0] { \spec [1:0] \reg_in } + end + sync always + update \reg_out $0\reg_out[6:0] + end + connect \isvec \spec [2] +end +attribute \src "libresoc.v:138521.1-138621.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.in3_svdec" +attribute \generator "nMigen" +module \in3_svdec + attribute \src "libresoc.v:138522.7-138522.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:138608.3-138619.6" + wire width 7 $0\reg_out[6:0] + attribute \src "libresoc.v:138549.3-138607.6" + wire width 3 $0\spec[2:0] + attribute \src "libresoc.v:138608.3-138619.6" + wire width 7 $1\reg_out[6:0] + attribute \src "libresoc.v:138549.3-138607.6" + wire width 3 $1\spec[2:0] + attribute \src "libresoc.v:138549.3-138607.6" + wire width 2 $2\spec[2:1] + attribute \src "libresoc.v:138549.3-138607.6" + wire width 3 $3\spec[2:0] + attribute \enum_base_type "SVEtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "EXTRA2" + attribute \enum_value_10 "EXTRA3" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:90" + wire width 2 input 1 \etype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:89" + wire width 9 input 6 \extra + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:91" + wire width 3 input 5 \idx + attribute \src "libresoc.v:138522.7-138522.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:149" + wire output 3 \isvec + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:147" + wire width 5 input 2 \reg_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:148" + wire width 7 output 4 \reg_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" + wire width 3 \spec + attribute \src "libresoc.v:138522.7-138522.20" + process $proc$libresoc.v:138522$5556 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:138549.3-138607.6" + process $proc$libresoc.v:138549$5554 + assign { } { } + assign { } { } + assign $0\spec[2:0] $1\spec[2:0] + attribute \src "libresoc.v:138550.5-138550.29" + switch \initial + attribute \src "libresoc.v:138550.9-138550.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:104" + switch \etype + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign $1\spec[2:0] [0] 1'0 + assign $1\spec[2:0] [2:1] $2\spec[2:1] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:107" + switch \idx + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $2\spec[2:1] [1] \extra [8] + assign $2\spec[2:1] [0] \extra [7] + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $2\spec[2:1] [1] \extra [6] + assign $2\spec[2:1] [0] \extra [5] + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $2\spec[2:1] [1] \extra [4] + assign $2\spec[2:1] [0] \extra [3] + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $2\spec[2:1] [1] \extra [2] + assign $2\spec[2:1] [0] \extra [1] + case + assign $2\spec[2:1] 2'00 + end + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\spec[2:0] $3\spec[2:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:122" + switch \idx + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $3\spec[2:0] \extra [8:6] + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $3\spec[2:0] \extra [5:3] + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $3\spec[2:0] \extra [2:0] + case + assign $3\spec[2:0] 3'000 + end + case + assign $1\spec[2:0] 3'000 + end + sync always + update \spec $0\spec[2:0] + end + attribute \src "libresoc.v:138608.3-138619.6" + process $proc$libresoc.v:138608$5555 + assign { } { } + assign $0\reg_out[6:0] $1\reg_out[6:0] + attribute \src "libresoc.v:138609.5-138609.29" + switch \initial + attribute \src "libresoc.v:138609.9-138609.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:166" + switch \isvec + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\reg_out[6:0] { \reg_in \spec [1:0] } + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\reg_out[6:0] { \spec [1:0] \reg_in } + end + sync always + update \reg_out $0\reg_out[6:0] + end + connect \isvec \spec [2] +end +attribute \src "libresoc.v:138625.1-138948.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe1.input" +attribute \generator "nMigen" +module \input + attribute \src "libresoc.v:138911.3-138922.6" + wire width 64 $0\a[63:0] + attribute \src "libresoc.v:138626.7-138626.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:138923.3-138941.6" + wire width 2 $0\xer_ca$23[1:0]$5560 + attribute \src "libresoc.v:138911.3-138922.6" + wire width 64 $1\a[63:0] + attribute \src "libresoc.v:138923.3-138941.6" + wire width 2 $1\xer_ca$23[1:0]$5561 + attribute \src "libresoc.v:138910.18-138910.100" + wire width 64 $not$libresoc.v:138910$5557_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28" + wire width 64 \$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:20" + wire width 64 \a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 17 \alu_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 40 \alu_op__data_len$18 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 input 2 \alu_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 output 25 \alu_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 3 \alu_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 26 \alu_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 4 \alu_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 27 \alu_op__imm_data__ok$5 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 13 \alu_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 36 \alu_op__input_carry$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 18 \alu_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 41 \alu_op__insn$19 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \alu_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 24 \alu_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \alu_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 32 \alu_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 11 \alu_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 34 \alu_op__invert_out$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 15 \alu_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 38 \alu_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 16 \alu_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 39 \alu_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 7 \alu_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 30 \alu_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \alu_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 31 \alu_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \alu_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 37 \alu_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 6 \alu_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 29 \alu_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 5 \alu_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 28 \alu_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \alu_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 35 \alu_op__write_cr0$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \alu_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 33 \alu_op__zero_a$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:39" + wire width 64 \b + attribute \src "libresoc.v:138626.7-138626.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 input 46 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 output 23 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 19 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 42 \ra$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 20 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 43 \rb$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 input 22 \xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 output 45 \xer_ca$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 21 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire output 44 \xer_so$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28" + cell $not $not$libresoc.v:138910$5557 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \ra + connect \Y $not$libresoc.v:138910$5557_Y + end + attribute \src "libresoc.v:138626.7-138626.20" + process $proc$libresoc.v:138626$5562 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:138911.3-138922.6" + process $proc$libresoc.v:138911$5558 + assign { } { } + assign $0\a[63:0] $1\a[63:0] + attribute \src "libresoc.v:138912.5-138912.29" + switch \initial + attribute \src "libresoc.v:138912.9-138912.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:27" + switch \alu_op__invert_in + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\a[63:0] \$24 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\a[63:0] \ra + end + sync always + update \a $0\a[63:0] + end + attribute \src "libresoc.v:138923.3-138941.6" + process $proc$libresoc.v:138923$5559 + assign { } { } + assign { } { } + assign $0\xer_ca$23[1:0]$5560 $1\xer_ca$23[1:0]$5561 + attribute \src "libresoc.v:138924.5-138924.29" + switch \initial + attribute \src "libresoc.v:138924.9-138924.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:55" + switch \alu_op__input_carry + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\xer_ca$23[1:0]$5561 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\xer_ca$23[1:0]$5561 2'11 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\xer_ca$23[1:0]$5561 \xer_ca + case + assign $1\xer_ca$23[1:0]$5561 2'00 + end + sync always + update \xer_ca$23 $0\xer_ca$23[1:0]$5560 + end + connect \$24 $not$libresoc.v:138910$5557_Y + connect { \alu_op__insn$19 \alu_op__data_len$18 \alu_op__is_signed$17 \alu_op__is_32bit$16 \alu_op__output_carry$15 \alu_op__input_carry$14 \alu_op__write_cr0$13 \alu_op__invert_out$12 \alu_op__zero_a$11 \alu_op__invert_in$10 \alu_op__oe__ok$9 \alu_op__oe__oe$8 \alu_op__rc__ok$7 \alu_op__rc__rc$6 \alu_op__imm_data__ok$5 \alu_op__imm_data__data$4 \alu_op__fn_unit$3 \alu_op__insn_type$2 } { \alu_op__insn \alu_op__data_len \alu_op__is_signed \alu_op__is_32bit \alu_op__output_carry \alu_op__input_carry \alu_op__write_cr0 \alu_op__invert_out \alu_op__zero_a \alu_op__invert_in \alu_op__oe__ok \alu_op__oe__oe \alu_op__rc__ok \alu_op__rc__rc \alu_op__imm_data__ok \alu_op__imm_data__data \alu_op__fn_unit \alu_op__insn_type } + connect \muxid$1 \muxid + connect \xer_so$22 \xer_so + connect \rb$21 \rb + connect \b \rb + connect \ra$20 \a +end +attribute \src "libresoc.v:138952.1-139276.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1.input" +attribute \generator "nMigen" +module \input$113 + attribute \src "libresoc.v:139238.3-139249.6" + wire width 64 $0\a[63:0] + attribute \src "libresoc.v:138953.7-138953.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:139250.3-139268.6" + wire width 2 $0\xer_ca$23[1:0]$5566 + attribute \src "libresoc.v:139238.3-139249.6" + wire width 64 $1\a[63:0] + attribute \src "libresoc.v:139250.3-139268.6" + wire width 2 $1\xer_ca$23[1:0]$5567 + attribute \src "libresoc.v:139237.18-139237.100" + wire width 64 $not$libresoc.v:139237$5563_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28" + wire width 64 \$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:20" + wire width 64 \a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:39" + wire width 64 \b + attribute \src "libresoc.v:138953.7-138953.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 input 46 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 output 23 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 18 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 41 \ra$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 19 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 42 \rb$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 20 \rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 43 \rc$21 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 input 2 \sr_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 output 25 \sr_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 3 \sr_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 26 \sr_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 4 \sr_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 27 \sr_op__imm_data__ok$5 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 11 \sr_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 34 \sr_op__input_carry$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \sr_op__input_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 36 \sr_op__input_cr$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 17 \sr_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 40 \sr_op__insn$18 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \sr_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 24 \sr_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \sr_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 33 \sr_op__invert_in$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 15 \sr_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 38 \sr_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 16 \sr_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 39 \sr_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 7 \sr_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 30 \sr_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \sr_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 31 \sr_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \sr_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 35 \sr_op__output_carry$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \sr_op__output_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 37 \sr_op__output_cr$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 6 \sr_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 29 \sr_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 5 \sr_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 28 \sr_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \sr_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 32 \sr_op__write_cr0$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 input 22 \xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 output 45 \xer_ca$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 21 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire output 44 \xer_so$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28" + cell $not $not$libresoc.v:139237$5563 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \ra + connect \Y $not$libresoc.v:139237$5563_Y + end + attribute \src "libresoc.v:138953.7-138953.20" + process $proc$libresoc.v:138953$5568 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:139238.3-139249.6" + process $proc$libresoc.v:139238$5564 + assign { } { } + assign $0\a[63:0] $1\a[63:0] + attribute \src "libresoc.v:139239.5-139239.29" + switch \initial + attribute \src "libresoc.v:139239.9-139239.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:27" + switch \sr_op__invert_in + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\a[63:0] \$24 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\a[63:0] \ra + end + sync always + update \a $0\a[63:0] + end + attribute \src "libresoc.v:139250.3-139268.6" + process $proc$libresoc.v:139250$5565 + assign { } { } + assign { } { } + assign $0\xer_ca$23[1:0]$5566 $1\xer_ca$23[1:0]$5567 + attribute \src "libresoc.v:139251.5-139251.29" + switch \initial + attribute \src "libresoc.v:139251.9-139251.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:55" + switch \sr_op__input_carry + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\xer_ca$23[1:0]$5567 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\xer_ca$23[1:0]$5567 2'11 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\xer_ca$23[1:0]$5567 \xer_ca + case + assign $1\xer_ca$23[1:0]$5567 2'00 + end + sync always + update \xer_ca$23 $0\xer_ca$23[1:0]$5566 + end + connect \$24 $not$libresoc.v:139237$5563_Y + connect \rc$21 \rc + connect { \sr_op__insn$18 \sr_op__is_signed$17 \sr_op__is_32bit$16 \sr_op__output_cr$15 \sr_op__input_cr$14 \sr_op__output_carry$13 \sr_op__input_carry$12 \sr_op__invert_in$11 \sr_op__write_cr0$10 \sr_op__oe__ok$9 \sr_op__oe__oe$8 \sr_op__rc__ok$7 \sr_op__rc__rc$6 \sr_op__imm_data__ok$5 \sr_op__imm_data__data$4 \sr_op__fn_unit$3 \sr_op__insn_type$2 } { \sr_op__insn \sr_op__is_signed \sr_op__is_32bit \sr_op__output_cr \sr_op__input_cr \sr_op__output_carry \sr_op__input_carry \sr_op__invert_in \sr_op__write_cr0 \sr_op__oe__ok \sr_op__oe__oe \sr_op__rc__ok \sr_op__rc__rc \sr_op__imm_data__ok \sr_op__imm_data__data \sr_op__fn_unit \sr_op__insn_type } + connect \muxid$1 \muxid + connect \xer_so$22 \xer_so + connect \rb$20 \b + connect \b \rb + connect \ra$19 \a +end +attribute \src "libresoc.v:139280.1-139579.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe1.input" +attribute \generator "nMigen" +module \input$50 + attribute \src "libresoc.v:139561.3-139572.6" + wire width 64 $0\b[63:0] + attribute \src "libresoc.v:139281.7-139281.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:139561.3-139572.6" + wire width 64 $1\b[63:0] + attribute \src "libresoc.v:139560.18-139560.100" + wire width 64 $not$libresoc.v:139560$5569_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:43" + wire width 64 \$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:20" + wire width 64 \a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:39" + wire width 64 \b + attribute \src "libresoc.v:139281.7-139281.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 17 \logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 39 \logical_op__data_len$18 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 input 2 \logical_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 output 24 \logical_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 3 \logical_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 25 \logical_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 4 \logical_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 26 \logical_op__imm_data__ok$5 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 11 \logical_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 33 \logical_op__input_carry$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 18 \logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 40 \logical_op__insn$19 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \logical_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 23 \logical_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 31 \logical_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 34 \logical_op__invert_out$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 15 \logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 37 \logical_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 16 \logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 38 \logical_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 7 \logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 29 \logical_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 30 \logical_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 36 \logical_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 6 \logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 28 \logical_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 5 \logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 27 \logical_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 35 \logical_op__write_cr0$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 32 \logical_op__zero_a$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 input 44 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 output 22 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 19 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 41 \ra$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 20 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 42 \rb$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 21 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire output 43 \xer_so$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:43" + cell $not $not$libresoc.v:139560$5569 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \rb + connect \Y $not$libresoc.v:139560$5569_Y + end + attribute \src "libresoc.v:139281.7-139281.20" + process $proc$libresoc.v:139281$5571 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:139561.3-139572.6" + process $proc$libresoc.v:139561$5570 + assign { } { } + assign $0\b[63:0] $1\b[63:0] + attribute \src "libresoc.v:139562.5-139562.29" + switch \initial + attribute \src "libresoc.v:139562.9-139562.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:42" + switch \logical_op__invert_in + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\b[63:0] \$23 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\b[63:0] \rb + end + sync always + update \b $0\b[63:0] + end + connect \$23 $not$libresoc.v:139560$5569_Y + connect { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } + connect \muxid$1 \muxid + connect \xer_so$22 \xer_so + connect \rb$21 \b + connect \ra$20 \a + connect \a \ra +end +attribute \src "libresoc.v:139583.1-139882.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_start.input" +attribute \generator "nMigen" +module \input$78 + attribute \src "libresoc.v:139864.3-139875.6" + wire width 64 $0\a[63:0] + attribute \src "libresoc.v:139584.7-139584.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:139864.3-139875.6" + wire width 64 $1\a[63:0] + attribute \src "libresoc.v:139863.18-139863.100" + wire width 64 $not$libresoc.v:139863$5572_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28" + wire width 64 \$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:20" + wire width 64 \a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:39" + wire width 64 \b + attribute \src "libresoc.v:139584.7-139584.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 17 \logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 39 \logical_op__data_len$18 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 input 2 \logical_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 output 24 \logical_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 3 \logical_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 25 \logical_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 4 \logical_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 26 \logical_op__imm_data__ok$5 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 11 \logical_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 33 \logical_op__input_carry$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 18 \logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 40 \logical_op__insn$19 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \logical_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 23 \logical_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 31 \logical_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 34 \logical_op__invert_out$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 15 \logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 37 \logical_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 16 \logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 38 \logical_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 7 \logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 29 \logical_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 30 \logical_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 36 \logical_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 6 \logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 28 \logical_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 5 \logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 27 \logical_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 35 \logical_op__write_cr0$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 32 \logical_op__zero_a$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 input 44 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 output 22 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 19 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 41 \ra$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 20 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 42 \rb$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 21 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire output 43 \xer_so$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28" + cell $not $not$libresoc.v:139863$5572 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \ra + connect \Y $not$libresoc.v:139863$5572_Y + end + attribute \src "libresoc.v:139584.7-139584.20" + process $proc$libresoc.v:139584$5574 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:139864.3-139875.6" + process $proc$libresoc.v:139864$5573 + assign { } { } + assign $0\a[63:0] $1\a[63:0] + attribute \src "libresoc.v:139865.5-139865.29" + switch \initial + attribute \src "libresoc.v:139865.9-139865.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:27" + switch \logical_op__invert_in + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\a[63:0] \$23 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\a[63:0] \ra + end + sync always + update \a $0\a[63:0] + end + connect \$23 $not$libresoc.v:139863$5572_Y + connect { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } + connect \muxid$1 \muxid + connect \xer_so$22 \xer_so + connect \rb$21 \rb + connect \b \rb + connect \ra$20 \a +end +attribute \src "libresoc.v:139886.1-140138.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe1.input" +attribute \generator "nMigen" +module \input$95 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:20" + wire width 64 \a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:39" + wire width 64 \b + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 input 2 \mul_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 output 18 \mul_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 3 \mul_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 19 \mul_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 4 \mul_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 20 \mul_op__imm_data__ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 12 \mul_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 28 \mul_op__insn$13 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \mul_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 17 \mul_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \mul_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 26 \mul_op__is_32bit$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 11 \mul_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 27 \mul_op__is_signed$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 7 \mul_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 23 \mul_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \mul_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 24 \mul_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 6 \mul_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 22 \mul_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 5 \mul_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 21 \mul_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \mul_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 25 \mul_op__write_cr0$10 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 input 32 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 output 16 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 13 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 29 \ra$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 14 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 30 \rb$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 15 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire output 31 \xer_so$16 + connect { \mul_op__insn$13 \mul_op__is_signed$12 \mul_op__is_32bit$11 \mul_op__write_cr0$10 \mul_op__oe__ok$9 \mul_op__oe__oe$8 \mul_op__rc__ok$7 \mul_op__rc__rc$6 \mul_op__imm_data__ok$5 \mul_op__imm_data__data$4 \mul_op__fn_unit$3 \mul_op__insn_type$2 } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__oe__ok \mul_op__oe__oe \mul_op__rc__ok \mul_op__rc__rc \mul_op__imm_data__ok \mul_op__imm_data__data \mul_op__fn_unit \mul_op__insn_type } + connect \muxid$1 \muxid + connect \xer_so$16 \xer_so + connect \rb$15 \rb + connect \b \rb + connect \ra$14 \a + connect \a \ra +end +attribute \src "libresoc.v:140142.1-140361.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.int" +attribute \generator "nMigen" +module \int + attribute \src "libresoc.v:140267.3-140273.6" + wire width 5 $0$memwr$\memory$libresoc.v:140272$5607_ADDR[4:0]$5616 + attribute \src "libresoc.v:140267.3-140273.6" + wire width 64 $0$memwr$\memory$libresoc.v:140272$5607_DATA[63:0]$5617 + attribute \src "libresoc.v:140267.3-140273.6" + wire width 64 $0$memwr$\memory$libresoc.v:140272$5607_EN[63:0]$5618 + attribute \src "libresoc.v:140267.3-140273.6" + wire width 5 $0\_0_[4:0] + attribute \src "libresoc.v:140267.3-140273.6" + wire width 5 $0\_1_[4:0] + attribute \src "libresoc.v:140267.3-140273.6" + wire width 5 $0\_2_[4:0] + attribute \src "libresoc.v:140267.3-140273.6" + wire width 5 $0\_3_[4:0] + attribute \src "libresoc.v:140296.3-140305.6" + wire width 64 $0\dmi__data_o[63:0] + attribute \src "libresoc.v:140143.7-140143.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:140287.3-140295.6" + wire $0\ren_delay$10$next[0:0]$5627 + attribute \src "libresoc.v:140220.3-140221.43" + wire $0\ren_delay$10[0:0]$5609 + attribute \src "libresoc.v:140186.7-140186.28" + wire $0\ren_delay$10[0:0]$5675 + attribute \src "libresoc.v:140316.3-140324.6" + wire $0\ren_delay$8$next[0:0]$5632 + attribute \src "libresoc.v:140224.3-140225.41" + wire $0\ren_delay$8[0:0]$5613 + attribute \src "libresoc.v:140190.7-140190.27" + wire $0\ren_delay$8[0:0]$5677 + attribute \src "libresoc.v:140335.3-140343.6" + wire $0\ren_delay$9$next[0:0]$5636 + attribute \src "libresoc.v:140222.3-140223.41" + wire $0\ren_delay$9[0:0]$5611 + attribute \src "libresoc.v:140194.7-140194.27" + wire $0\ren_delay$9[0:0]$5679 + attribute \src "libresoc.v:140278.3-140286.6" + wire $0\ren_delay$next[0:0]$5624 + attribute \src "libresoc.v:140226.3-140227.35" + wire $0\ren_delay[0:0] + attribute \src "libresoc.v:140306.3-140315.6" + wire width 64 $0\src1__data_o[63:0] + attribute \src "libresoc.v:140325.3-140334.6" + wire width 64 $0\src2__data_o[63:0] + attribute \src "libresoc.v:140344.3-140353.6" + wire width 64 $0\src3__data_o[63:0] + attribute \src "libresoc.v:140296.3-140305.6" + wire width 64 $1\dmi__data_o[63:0] + attribute \src "libresoc.v:140287.3-140295.6" + wire $1\ren_delay$10$next[0:0]$5628 + attribute \src "libresoc.v:140316.3-140324.6" + wire $1\ren_delay$8$next[0:0]$5633 + attribute \src "libresoc.v:140335.3-140343.6" + wire $1\ren_delay$9$next[0:0]$5637 + attribute \src "libresoc.v:140278.3-140286.6" + wire $1\ren_delay$next[0:0]$5625 + attribute \src "libresoc.v:140184.7-140184.23" + wire $1\ren_delay[0:0] + attribute \src "libresoc.v:140306.3-140315.6" + wire width 64 $1\src1__data_o[63:0] + attribute \src "libresoc.v:140325.3-140334.6" + wire width 64 $1\src2__data_o[63:0] + attribute \src "libresoc.v:140344.3-140353.6" + wire width 64 $1\src3__data_o[63:0] + attribute \src "libresoc.v:140274.26-140274.32" + wire width 64 $memrd$\memory$libresoc.v:140274$5619_DATA + attribute \src "libresoc.v:140275.30-140275.36" + wire width 64 $memrd$\memory$libresoc.v:140275$5620_DATA + attribute \src "libresoc.v:140276.30-140276.36" + wire width 64 $memrd$\memory$libresoc.v:140276$5621_DATA + attribute \src "libresoc.v:140277.30-140277.36" + wire width 64 $memrd$\memory$libresoc.v:140277$5622_DATA + attribute \src "libresoc.v:0.0-0.0" + wire width 5 $memwr$\memory$libresoc.v:140272$5607_ADDR + attribute \src "libresoc.v:0.0-0.0" + wire width 64 $memwr$\memory$libresoc.v:140272$5607_DATA + attribute \src "libresoc.v:0.0-0.0" + wire width 64 $memwr$\memory$libresoc.v:140272$5607_EN + attribute \src "libresoc.v:140263.13-140263.16" + wire width 5 \_0_ + attribute \src "libresoc.v:140264.13-140264.16" + wire width 5 \_1_ + attribute \src "libresoc.v:140265.13-140265.16" + wire width 5 \_2_ + attribute \src "libresoc.v:140266.13-140266.16" + wire width 5 \_3_ + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 17 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 5 input 15 \dest1__addr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 input 14 \dest1__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 16 \dest1__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 5 input 2 \dmi__addr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 output 4 \dmi__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 3 \dmi__ren + attribute \src "libresoc.v:140143.7-140143.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" + wire width 5 \memory_r_addr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" + wire width 5 \memory_r_addr$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" + wire width 5 \memory_r_addr$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" + wire width 5 \memory_r_addr$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" + wire width 64 \memory_r_data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" + wire width 64 \memory_r_data$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" + wire width 64 \memory_r_data$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" + wire width 64 \memory_r_data$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" + wire width 5 \memory_w_addr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" + wire width 64 \memory_w_data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" + wire \memory_w_en + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" + wire \ren_delay + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" + wire \ren_delay$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" + wire \ren_delay$10$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" + wire \ren_delay$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" + wire \ren_delay$8$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" + wire \ren_delay$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" + wire \ren_delay$9$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" + wire \ren_delay$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 5 input 6 \src1__addr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 output 5 \src1__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 7 \src1__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 5 input 9 \src2__addr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 output 8 \src2__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 10 \src2__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 5 input 12 \src3__addr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 output 11 \src3__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 13 \src3__ren + attribute \src "libresoc.v:140228.14-140228.20" + memory width 64 size 32 \memory + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5639 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5639 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 0 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5640 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5640 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 1 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5641 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5641 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 2 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5642 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5642 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 3 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5643 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5643 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 4 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5644 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5644 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 5 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5645 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5645 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 6 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5646 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5646 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 7 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5647 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5647 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 8 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5648 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5648 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 9 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5649 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5649 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 10 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5650 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5650 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 11 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5651 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5651 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 12 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5652 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5652 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 13 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5653 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5653 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 14 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5654 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5654 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 15 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5655 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5655 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 16 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5656 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5656 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 17 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5657 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5657 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 18 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5658 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5658 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 19 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5659 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5659 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 20 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5660 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5660 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 21 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5661 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5661 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 22 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5662 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5662 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 23 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5663 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5663 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 24 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5664 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5664 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 25 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5665 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5665 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 26 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5666 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5666 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 27 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5667 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5667 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 28 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5668 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5668 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 29 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5669 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5669 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 30 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$5670 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5670 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 31 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:140274.26-140274.32" + cell $memrd $memrd$\memory$libresoc.v:140274$5619 + parameter \ABITS 5 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\memory" + parameter \TRANSPARENT 0 + parameter \WIDTH 64 + connect \ADDR \_0_ + connect \CLK 1'x + connect \DATA $memrd$\memory$libresoc.v:140274$5619_DATA + connect \EN 1'x + end + attribute \src "libresoc.v:140275.30-140275.36" + cell $memrd $memrd$\memory$libresoc.v:140275$5620 + parameter \ABITS 5 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\memory" + parameter \TRANSPARENT 0 + parameter \WIDTH 64 + connect \ADDR \_1_ + connect \CLK 1'x + connect \DATA $memrd$\memory$libresoc.v:140275$5620_DATA + connect \EN 1'x + end + attribute \src "libresoc.v:140276.30-140276.36" + cell $memrd $memrd$\memory$libresoc.v:140276$5621 + parameter \ABITS 5 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\memory" + parameter \TRANSPARENT 0 + parameter \WIDTH 64 + connect \ADDR \_2_ + connect \CLK 1'x + connect \DATA $memrd$\memory$libresoc.v:140276$5621_DATA + connect \EN 1'x + end + attribute \src "libresoc.v:140277.30-140277.36" + cell $memrd $memrd$\memory$libresoc.v:140277$5622 + parameter \ABITS 5 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\memory" + parameter \TRANSPARENT 0 + parameter \WIDTH 64 + connect \ADDR \_3_ + connect \CLK 1'x + connect \DATA $memrd$\memory$libresoc.v:140277$5622_DATA + connect \EN 1'x + end + attribute \src "libresoc.v:0.0-0.0" + cell $memwr $memwr$\memory$libresoc.v:0$5671 + parameter \ABITS 5 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\memory" + parameter \PRIORITY 5671 + parameter \WIDTH 64 + connect \ADDR $memwr$\memory$libresoc.v:140272$5607_ADDR + connect \CLK 1'x + connect \DATA $memwr$\memory$libresoc.v:140272$5607_DATA + connect \EN $memwr$\memory$libresoc.v:140272$5607_EN + end + attribute \src "libresoc.v:0.0-0.0" + process $proc$libresoc.v:0$5680 + sync always + sync init + end + attribute \src "libresoc.v:140143.7-140143.20" + process $proc$libresoc.v:140143$5672 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:140184.7-140184.23" + process $proc$libresoc.v:140184$5673 + assign { } { } + assign $1\ren_delay[0:0] 1'0 + sync always + sync init + update \ren_delay $1\ren_delay[0:0] + end + attribute \src "libresoc.v:140186.7-140186.28" + process $proc$libresoc.v:140186$5674 + assign { } { } + assign $0\ren_delay$10[0:0]$5675 1'0 + sync always + sync init + update \ren_delay$10 $0\ren_delay$10[0:0]$5675 + end + attribute \src "libresoc.v:140190.7-140190.27" + process $proc$libresoc.v:140190$5676 + assign { } { } + assign $0\ren_delay$8[0:0]$5677 1'0 + sync always + sync init + update \ren_delay$8 $0\ren_delay$8[0:0]$5677 + end + attribute \src "libresoc.v:140194.7-140194.27" + process $proc$libresoc.v:140194$5678 + assign { } { } + assign $0\ren_delay$9[0:0]$5679 1'0 + sync always + sync init + update \ren_delay$9 $0\ren_delay$9[0:0]$5679 + end + attribute \src "libresoc.v:140220.3-140221.43" + process $proc$libresoc.v:140220$5608 + assign { } { } + assign $0\ren_delay$10[0:0]$5609 \ren_delay$10$next + sync posedge \coresync_clk + update \ren_delay$10 $0\ren_delay$10[0:0]$5609 + end + attribute \src "libresoc.v:140222.3-140223.41" + process $proc$libresoc.v:140222$5610 + assign { } { } + assign $0\ren_delay$9[0:0]$5611 \ren_delay$9$next + sync posedge \coresync_clk + update \ren_delay$9 $0\ren_delay$9[0:0]$5611 + end + attribute \src "libresoc.v:140224.3-140225.41" + process $proc$libresoc.v:140224$5612 + assign { } { } + assign $0\ren_delay$8[0:0]$5613 \ren_delay$8$next + sync posedge \coresync_clk + update \ren_delay$8 $0\ren_delay$8[0:0]$5613 + end + attribute \src "libresoc.v:140226.3-140227.35" + process $proc$libresoc.v:140226$5614 + assign { } { } + assign $0\ren_delay[0:0] \ren_delay$next + sync posedge \coresync_clk + update \ren_delay $0\ren_delay[0:0] + end + attribute \src "libresoc.v:140267.3-140273.6" + process $proc$libresoc.v:140267$5615 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0$memwr$\memory$libresoc.v:140272$5607_ADDR[4:0]$5616 5'xxxxx + assign $0$memwr$\memory$libresoc.v:140272$5607_DATA[63:0]$5617 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\memory$libresoc.v:140272$5607_EN[63:0]$5618 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\_0_[4:0] \src1__addr + assign $0\_1_[4:0] \src2__addr + assign $0\_2_[4:0] \src3__addr + assign $0\_3_[4:0] \dmi__addr + attribute \src "libresoc.v:140272.5-140272.58" + switch \dest1__wen + attribute \src "libresoc.v:140272.9-140272.19" + case 1'1 + assign $0$memwr$\memory$libresoc.v:140272$5607_ADDR[4:0]$5616 \dest1__addr + assign $0$memwr$\memory$libresoc.v:140272$5607_DATA[63:0]$5617 \dest1__data_i + assign $0$memwr$\memory$libresoc.v:140272$5607_EN[63:0]$5618 64'1111111111111111111111111111111111111111111111111111111111111111 + case + end + sync posedge \coresync_clk + update \_0_ $0\_0_[4:0] + update \_1_ $0\_1_[4:0] + update \_2_ $0\_2_[4:0] + update \_3_ $0\_3_[4:0] + update $memwr$\memory$libresoc.v:140272$5607_ADDR $0$memwr$\memory$libresoc.v:140272$5607_ADDR[4:0]$5616 + update $memwr$\memory$libresoc.v:140272$5607_DATA $0$memwr$\memory$libresoc.v:140272$5607_DATA[63:0]$5617 + update $memwr$\memory$libresoc.v:140272$5607_EN $0$memwr$\memory$libresoc.v:140272$5607_EN[63:0]$5618 + end + attribute \src "libresoc.v:140278.3-140286.6" + process $proc$libresoc.v:140278$5623 + assign { } { } + assign { } { } + assign $0\ren_delay$next[0:0]$5624 $1\ren_delay$next[0:0]$5625 + attribute \src "libresoc.v:140279.5-140279.29" + switch \initial + attribute \src "libresoc.v:140279.9-140279.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ren_delay$next[0:0]$5625 1'0 + case + assign $1\ren_delay$next[0:0]$5625 \src1__ren + end + sync always + update \ren_delay$next $0\ren_delay$next[0:0]$5624 + end + attribute \src "libresoc.v:140287.3-140295.6" + process $proc$libresoc.v:140287$5626 + assign { } { } + assign { } { } + assign $0\ren_delay$10$next[0:0]$5627 $1\ren_delay$10$next[0:0]$5628 + attribute \src "libresoc.v:140288.5-140288.29" + switch \initial + attribute \src "libresoc.v:140288.9-140288.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ren_delay$10$next[0:0]$5628 1'0 + case + assign $1\ren_delay$10$next[0:0]$5628 \dmi__ren + end + sync always + update \ren_delay$10$next $0\ren_delay$10$next[0:0]$5627 + end + attribute \src "libresoc.v:140296.3-140305.6" + process $proc$libresoc.v:140296$5629 + assign { } { } + assign { } { } + assign $0\dmi__data_o[63:0] $1\dmi__data_o[63:0] + attribute \src "libresoc.v:140297.5-140297.29" + switch \initial + attribute \src "libresoc.v:140297.9-140297.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" + switch \ren_delay$10 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dmi__data_o[63:0] \memory_r_data$7 + case + assign $1\dmi__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \dmi__data_o $0\dmi__data_o[63:0] + end + attribute \src "libresoc.v:140306.3-140315.6" + process $proc$libresoc.v:140306$5630 + assign { } { } + assign { } { } + assign $0\src1__data_o[63:0] $1\src1__data_o[63:0] + attribute \src "libresoc.v:140307.5-140307.29" + switch \initial + attribute \src "libresoc.v:140307.9-140307.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" + switch \ren_delay + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src1__data_o[63:0] \memory_r_data + case + assign $1\src1__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \src1__data_o $0\src1__data_o[63:0] + end + attribute \src "libresoc.v:140316.3-140324.6" + process $proc$libresoc.v:140316$5631 + assign { } { } + assign { } { } + assign $0\ren_delay$8$next[0:0]$5632 $1\ren_delay$8$next[0:0]$5633 + attribute \src "libresoc.v:140317.5-140317.29" + switch \initial + attribute \src "libresoc.v:140317.9-140317.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ren_delay$8$next[0:0]$5633 1'0 + case + assign $1\ren_delay$8$next[0:0]$5633 \src2__ren + end + sync always + update \ren_delay$8$next $0\ren_delay$8$next[0:0]$5632 + end + attribute \src "libresoc.v:140325.3-140334.6" + process $proc$libresoc.v:140325$5634 + assign { } { } + assign { } { } + assign $0\src2__data_o[63:0] $1\src2__data_o[63:0] + attribute \src "libresoc.v:140326.5-140326.29" + switch \initial + attribute \src "libresoc.v:140326.9-140326.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" + switch \ren_delay$8 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src2__data_o[63:0] \memory_r_data$3 + case + assign $1\src2__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \src2__data_o $0\src2__data_o[63:0] + end + attribute \src "libresoc.v:140335.3-140343.6" + process $proc$libresoc.v:140335$5635 + assign { } { } + assign { } { } + assign $0\ren_delay$9$next[0:0]$5636 $1\ren_delay$9$next[0:0]$5637 + attribute \src "libresoc.v:140336.5-140336.29" + switch \initial + attribute \src "libresoc.v:140336.9-140336.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ren_delay$9$next[0:0]$5637 1'0 + case + assign $1\ren_delay$9$next[0:0]$5637 \src3__ren + end + sync always + update \ren_delay$9$next $0\ren_delay$9$next[0:0]$5636 + end + attribute \src "libresoc.v:140344.3-140353.6" + process $proc$libresoc.v:140344$5638 + assign { } { } + assign { } { } + assign $0\src3__data_o[63:0] $1\src3__data_o[63:0] + attribute \src "libresoc.v:140345.5-140345.29" + switch \initial + attribute \src "libresoc.v:140345.9-140345.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" + switch \ren_delay$9 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src3__data_o[63:0] \memory_r_data$5 + case + assign $1\src3__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \src3__data_o $0\src3__data_o[63:0] + end + connect \memory_r_data $memrd$\memory$libresoc.v:140274$5619_DATA + connect \memory_r_data$3 $memrd$\memory$libresoc.v:140275$5620_DATA + connect \memory_r_data$5 $memrd$\memory$libresoc.v:140276$5621_DATA + connect \memory_r_data$7 $memrd$\memory$libresoc.v:140277$5622_DATA + connect \memory_w_data \dest1__data_i + connect \memory_w_en \dest1__wen + connect \memory_w_addr \dest1__addr + connect \memory_r_addr$6 \dmi__addr + connect \memory_r_addr$4 \src3__addr + connect \memory_r_addr$2 \src2__addr + connect \memory_r_addr \src1__addr +end +attribute \src "libresoc.v:140365.1-143079.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.jtag" +attribute \generator "nMigen" +module \jtag + attribute \src "libresoc.v:142511.3-142537.6" + wire $0\TAP_bus__tdo[0:0] + attribute \src "libresoc.v:142159.3-142174.6" + wire $0\TAP_tdo[0:0] + attribute \src "libresoc.v:142672.3-142704.6" + wire width 4 $0\dmi0__addr_i$next[3:0]$6091 + attribute \src "libresoc.v:142062.3-142063.41" + wire width 4 $0\dmi0__addr_i[3:0] + attribute \src "libresoc.v:142758.3-142784.6" + wire width 64 $0\dmi0__din$next[63:0]$6104 + attribute \src "libresoc.v:142058.3-142059.35" + wire width 64 $0\dmi0__din[63:0] + attribute \src "libresoc.v:142361.3-142377.6" + wire $0\dmi0_addrsr__oe$next[0:0]$6028 + attribute \src "libresoc.v:142090.3-142091.47" + wire $0\dmi0_addrsr__oe[0:0] + attribute \src "libresoc.v:142378.3-142398.6" + wire width 8 $0\dmi0_addrsr_reg$next[7:0]$6032 + attribute \src "libresoc.v:142088.3-142089.47" + wire width 8 $0\dmi0_addrsr_reg[7:0] + attribute \src "libresoc.v:142343.3-142351.6" + wire $0\dmi0_addrsr_update_core$next[0:0]$6022 + attribute \src "libresoc.v:142094.3-142095.63" + wire $0\dmi0_addrsr_update_core[0:0] + attribute \src "libresoc.v:142352.3-142360.6" + wire $0\dmi0_addrsr_update_core_prev$next[0:0]$6025 + attribute \src "libresoc.v:142092.3-142093.73" + wire $0\dmi0_addrsr_update_core_prev[0:0] + attribute \src "libresoc.v:142785.3-142805.6" + wire width 64 $0\dmi0_datasr__i$next[63:0]$6109 + attribute \src "libresoc.v:142056.3-142057.45" + wire width 64 $0\dmi0_datasr__i[63:0] + attribute \src "libresoc.v:142417.3-142433.6" + wire width 2 $0\dmi0_datasr__oe$next[1:0]$6043 + attribute \src "libresoc.v:142082.3-142083.47" + wire width 2 $0\dmi0_datasr__oe[1:0] + attribute \src "libresoc.v:142434.3-142454.6" + wire width 64 $0\dmi0_datasr_reg$next[63:0]$6047 + attribute \src "libresoc.v:142080.3-142081.47" + wire width 64 $0\dmi0_datasr_reg[63:0] + attribute \src "libresoc.v:142399.3-142407.6" + wire $0\dmi0_datasr_update_core$next[0:0]$6037 + attribute \src "libresoc.v:142086.3-142087.63" + wire $0\dmi0_datasr_update_core[0:0] + attribute \src "libresoc.v:142408.3-142416.6" + wire $0\dmi0_datasr_update_core_prev$next[0:0]$6040 + attribute \src "libresoc.v:142084.3-142085.73" + wire $0\dmi0_datasr_update_core_prev[0:0] + attribute \src "libresoc.v:142705.3-142757.6" + wire width 3 $0\fsm_state$503$next[2:0]$6097 + attribute \src "libresoc.v:142060.3-142061.45" + wire width 3 $0\fsm_state$503[2:0]$5943 + attribute \src "libresoc.v:141011.13-141011.35" + wire width 3 $0\fsm_state$503[2:0]$6143 + attribute \src "libresoc.v:142571.3-142623.6" + wire width 3 $0\fsm_state$next[2:0]$6074 + attribute \src "libresoc.v:142068.3-142069.35" + wire width 3 $0\fsm_state[2:0] + attribute \src "libresoc.v:140366.7-140366.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:142853.3-142873.6" + wire width 154 $0\io_bd$next[153:0]$6126 + attribute \src "libresoc.v:142120.3-142121.27" + wire width 154 $0\io_bd[153:0] + attribute \src "libresoc.v:142835.3-142852.6" + wire width 154 $0\io_sr$next[153:0]$6122 + attribute \src "libresoc.v:142122.3-142123.27" + wire width 154 $0\io_sr[153:0] + attribute \src "libresoc.v:142538.3-142570.6" + wire width 29 $0\jtag_wb__adr$next[28:0]$6068 + attribute \src "libresoc.v:142070.3-142071.41" + wire width 29 $0\jtag_wb__adr[28:0] + attribute \src "libresoc.v:142624.3-142650.6" + wire width 64 $0\jtag_wb__dat_w$next[63:0]$6081 + attribute \src "libresoc.v:142066.3-142067.45" + wire width 64 $0\jtag_wb__dat_w[63:0] + attribute \src "libresoc.v:142249.3-142265.6" + wire $0\jtag_wb_addrsr__oe$next[0:0]$5998 + attribute \src "libresoc.v:142106.3-142107.53" + wire $0\jtag_wb_addrsr__oe[0:0] + attribute \src "libresoc.v:142266.3-142286.6" + wire width 29 $0\jtag_wb_addrsr_reg$next[28:0]$6002 + attribute \src "libresoc.v:142104.3-142105.53" + wire width 29 $0\jtag_wb_addrsr_reg[28:0] + attribute \src "libresoc.v:142231.3-142239.6" + wire $0\jtag_wb_addrsr_update_core$next[0:0]$5992 + attribute \src "libresoc.v:142110.3-142111.69" + wire $0\jtag_wb_addrsr_update_core[0:0] + attribute \src "libresoc.v:142240.3-142248.6" + wire $0\jtag_wb_addrsr_update_core_prev$next[0:0]$5995 + attribute \src "libresoc.v:142108.3-142109.79" + wire $0\jtag_wb_addrsr_update_core_prev[0:0] + attribute \src "libresoc.v:142651.3-142671.6" + wire width 64 $0\jtag_wb_datasr__i$next[63:0]$6086 + attribute \src "libresoc.v:142064.3-142065.51" + wire width 64 $0\jtag_wb_datasr__i[63:0] + attribute \src "libresoc.v:142305.3-142321.6" + wire width 2 $0\jtag_wb_datasr__oe$next[1:0]$6013 + attribute \src "libresoc.v:142098.3-142099.53" + wire width 2 $0\jtag_wb_datasr__oe[1:0] + attribute \src "libresoc.v:142322.3-142342.6" + wire width 64 $0\jtag_wb_datasr_reg$next[63:0]$6017 + attribute \src "libresoc.v:142096.3-142097.53" + wire width 64 $0\jtag_wb_datasr_reg[63:0] + attribute \src "libresoc.v:142287.3-142295.6" + wire $0\jtag_wb_datasr_update_core$next[0:0]$6007 + attribute \src "libresoc.v:142102.3-142103.69" + wire $0\jtag_wb_datasr_update_core[0:0] + attribute \src "libresoc.v:142296.3-142304.6" + wire $0\jtag_wb_datasr_update_core_prev$next[0:0]$6010 + attribute \src "libresoc.v:142100.3-142101.79" + wire $0\jtag_wb_datasr_update_core_prev[0:0] + attribute \src "libresoc.v:142193.3-142209.6" + wire $0\sr0__oe$next[0:0]$5983 + attribute \src "libresoc.v:142114.3-142115.31" + wire $0\sr0__oe[0:0] + attribute \src "libresoc.v:142210.3-142230.6" + wire width 3 $0\sr0_reg$next[2:0]$5987 + attribute \src "libresoc.v:142112.3-142113.31" + wire width 3 $0\sr0_reg[2:0] + attribute \src "libresoc.v:142175.3-142183.6" + wire $0\sr0_update_core$next[0:0]$5977 + attribute \src "libresoc.v:142118.3-142119.47" + wire $0\sr0_update_core[0:0] + attribute \src "libresoc.v:142184.3-142192.6" + wire $0\sr0_update_core_prev$next[0:0]$5980 + attribute \src "libresoc.v:142116.3-142117.57" + wire $0\sr0_update_core_prev[0:0] + attribute \src "libresoc.v:142825.3-142834.6" + wire width 2 $0\sr5__i[1:0] + attribute \src "libresoc.v:142473.3-142489.6" + wire $0\sr5__oe$next[0:0]$6058 + attribute \src "libresoc.v:142074.3-142075.31" + wire $0\sr5__oe[0:0] + attribute \src "libresoc.v:142490.3-142510.6" + wire width 2 $0\sr5_reg$next[1:0]$6062 + attribute \src "libresoc.v:142072.3-142073.31" + wire width 2 $0\sr5_reg[1:0] + attribute \src "libresoc.v:142455.3-142463.6" + wire $0\sr5_update_core$next[0:0]$6052 + attribute \src "libresoc.v:142078.3-142079.47" + wire $0\sr5_update_core[0:0] + attribute \src "libresoc.v:142464.3-142472.6" + wire $0\sr5_update_core_prev$next[0:0]$6055 + attribute \src "libresoc.v:142076.3-142077.57" + wire $0\sr5_update_core_prev[0:0] + attribute \src "libresoc.v:142806.3-142824.6" + wire $0\wb_dcache_en$next[0:0]$6114 + attribute \src "libresoc.v:142054.3-142055.41" + wire $0\wb_dcache_en[0:0] + attribute \src "libresoc.v:142806.3-142824.6" + wire $0\wb_icache_en$next[0:0]$6115 + attribute \src "libresoc.v:142052.3-142053.41" + wire $0\wb_icache_en[0:0] + attribute \src "libresoc.v:142511.3-142537.6" + wire $1\TAP_bus__tdo[0:0] + attribute \src "libresoc.v:142159.3-142174.6" + wire $1\TAP_tdo[0:0] + attribute \src "libresoc.v:142672.3-142704.6" + wire width 4 $1\dmi0__addr_i$next[3:0]$6092 + attribute \src "libresoc.v:140924.13-140924.32" + wire width 4 $1\dmi0__addr_i[3:0] + attribute \src "libresoc.v:142758.3-142784.6" + wire width 64 $1\dmi0__din$next[63:0]$6105 + attribute \src "libresoc.v:140929.14-140929.46" + wire width 64 $1\dmi0__din[63:0] + attribute \src "libresoc.v:142361.3-142377.6" + wire $1\dmi0_addrsr__oe$next[0:0]$6029 + attribute \src "libresoc.v:140943.7-140943.29" + wire $1\dmi0_addrsr__oe[0:0] + attribute \src "libresoc.v:142378.3-142398.6" + wire width 8 $1\dmi0_addrsr_reg$next[7:0]$6033 + attribute \src "libresoc.v:140951.13-140951.36" + wire width 8 $1\dmi0_addrsr_reg[7:0] + attribute \src "libresoc.v:142343.3-142351.6" + wire $1\dmi0_addrsr_update_core$next[0:0]$6023 + attribute \src "libresoc.v:140959.7-140959.37" + wire $1\dmi0_addrsr_update_core[0:0] + attribute \src "libresoc.v:142352.3-142360.6" + wire $1\dmi0_addrsr_update_core_prev$next[0:0]$6026 + attribute \src "libresoc.v:140963.7-140963.42" + wire $1\dmi0_addrsr_update_core_prev[0:0] + attribute \src "libresoc.v:142785.3-142805.6" + wire width 64 $1\dmi0_datasr__i$next[63:0]$6110 + attribute \src "libresoc.v:140967.14-140967.51" + wire width 64 $1\dmi0_datasr__i[63:0] + attribute \src "libresoc.v:142417.3-142433.6" + wire width 2 $1\dmi0_datasr__oe$next[1:0]$6044 + attribute \src "libresoc.v:140973.13-140973.35" + wire width 2 $1\dmi0_datasr__oe[1:0] + attribute \src "libresoc.v:142434.3-142454.6" + wire width 64 $1\dmi0_datasr_reg$next[63:0]$6048 + attribute \src "libresoc.v:140981.14-140981.52" + wire width 64 $1\dmi0_datasr_reg[63:0] + attribute \src "libresoc.v:142399.3-142407.6" + wire $1\dmi0_datasr_update_core$next[0:0]$6038 + attribute \src "libresoc.v:140989.7-140989.37" + wire $1\dmi0_datasr_update_core[0:0] + attribute \src "libresoc.v:142408.3-142416.6" + wire $1\dmi0_datasr_update_core_prev$next[0:0]$6041 + attribute \src "libresoc.v:140993.7-140993.42" + wire $1\dmi0_datasr_update_core_prev[0:0] + attribute \src "libresoc.v:142705.3-142757.6" + wire width 3 $1\fsm_state$503$next[2:0]$6098 + attribute \src "libresoc.v:142571.3-142623.6" + wire width 3 $1\fsm_state$next[2:0]$6075 + attribute \src "libresoc.v:141009.13-141009.29" + wire width 3 $1\fsm_state[2:0] + attribute \src "libresoc.v:142853.3-142873.6" + wire width 154 $1\io_bd$next[153:0]$6127 + attribute \src "libresoc.v:141209.15-141209.67" + wire width 154 $1\io_bd[153:0] + attribute \src "libresoc.v:142835.3-142852.6" + wire width 154 $1\io_sr$next[153:0]$6123 + attribute \src "libresoc.v:141221.15-141221.67" + wire width 154 $1\io_sr[153:0] + attribute \src "libresoc.v:142538.3-142570.6" + wire width 29 $1\jtag_wb__adr$next[28:0]$6069 + attribute \src "libresoc.v:141230.14-141230.41" + wire width 29 $1\jtag_wb__adr[28:0] + attribute \src "libresoc.v:142624.3-142650.6" + wire width 64 $1\jtag_wb__dat_w$next[63:0]$6082 + attribute \src "libresoc.v:141239.14-141239.51" + wire width 64 $1\jtag_wb__dat_w[63:0] + attribute \src "libresoc.v:142249.3-142265.6" + wire $1\jtag_wb_addrsr__oe$next[0:0]$5999 + attribute \src "libresoc.v:141253.7-141253.32" + wire $1\jtag_wb_addrsr__oe[0:0] + attribute \src "libresoc.v:142266.3-142286.6" + wire width 29 $1\jtag_wb_addrsr_reg$next[28:0]$6003 + attribute \src "libresoc.v:141261.14-141261.47" + wire width 29 $1\jtag_wb_addrsr_reg[28:0] + attribute \src "libresoc.v:142231.3-142239.6" + wire $1\jtag_wb_addrsr_update_core$next[0:0]$5993 + attribute \src "libresoc.v:141269.7-141269.40" + wire $1\jtag_wb_addrsr_update_core[0:0] + attribute \src "libresoc.v:142240.3-142248.6" + wire $1\jtag_wb_addrsr_update_core_prev$next[0:0]$5996 + attribute \src "libresoc.v:141273.7-141273.45" + wire $1\jtag_wb_addrsr_update_core_prev[0:0] + attribute \src "libresoc.v:142651.3-142671.6" + wire width 64 $1\jtag_wb_datasr__i$next[63:0]$6087 + attribute \src "libresoc.v:141277.14-141277.54" + wire width 64 $1\jtag_wb_datasr__i[63:0] + attribute \src "libresoc.v:142305.3-142321.6" + wire width 2 $1\jtag_wb_datasr__oe$next[1:0]$6014 + attribute \src "libresoc.v:141283.13-141283.38" + wire width 2 $1\jtag_wb_datasr__oe[1:0] + attribute \src "libresoc.v:142322.3-142342.6" + wire width 64 $1\jtag_wb_datasr_reg$next[63:0]$6018 + attribute \src "libresoc.v:141291.14-141291.55" + wire width 64 $1\jtag_wb_datasr_reg[63:0] + attribute \src "libresoc.v:142287.3-142295.6" + wire $1\jtag_wb_datasr_update_core$next[0:0]$6008 + attribute \src "libresoc.v:141299.7-141299.40" + wire $1\jtag_wb_datasr_update_core[0:0] + attribute \src "libresoc.v:142296.3-142304.6" + wire $1\jtag_wb_datasr_update_core_prev$next[0:0]$6011 + attribute \src "libresoc.v:141303.7-141303.45" + wire $1\jtag_wb_datasr_update_core_prev[0:0] + attribute \src "libresoc.v:142193.3-142209.6" + wire $1\sr0__oe$next[0:0]$5984 + attribute \src "libresoc.v:141733.7-141733.21" + wire $1\sr0__oe[0:0] + attribute \src "libresoc.v:142210.3-142230.6" + wire width 3 $1\sr0_reg$next[2:0]$5988 + attribute \src "libresoc.v:141741.13-141741.27" + wire width 3 $1\sr0_reg[2:0] + attribute \src "libresoc.v:142175.3-142183.6" + wire $1\sr0_update_core$next[0:0]$5978 + attribute \src "libresoc.v:141749.7-141749.29" + wire $1\sr0_update_core[0:0] + attribute \src "libresoc.v:142184.3-142192.6" + wire $1\sr0_update_core_prev$next[0:0]$5981 + attribute \src "libresoc.v:141753.7-141753.34" + wire $1\sr0_update_core_prev[0:0] + attribute \src "libresoc.v:142825.3-142834.6" + wire width 2 $1\sr5__i[1:0] + attribute \src "libresoc.v:142473.3-142489.6" + wire $1\sr5__oe$next[0:0]$6059 + attribute \src "libresoc.v:141763.7-141763.21" + wire $1\sr5__oe[0:0] + attribute \src "libresoc.v:142490.3-142510.6" + wire width 2 $1\sr5_reg$next[1:0]$6063 + attribute \src "libresoc.v:141771.13-141771.27" + wire width 2 $1\sr5_reg[1:0] + attribute \src "libresoc.v:142455.3-142463.6" + wire $1\sr5_update_core$next[0:0]$6053 + attribute \src "libresoc.v:141779.7-141779.29" + wire $1\sr5_update_core[0:0] + attribute \src "libresoc.v:142464.3-142472.6" + wire $1\sr5_update_core_prev$next[0:0]$6056 + attribute \src "libresoc.v:141783.7-141783.34" + wire $1\sr5_update_core_prev[0:0] + attribute \src "libresoc.v:142806.3-142824.6" + wire $1\wb_dcache_en$next[0:0]$6116 + attribute \src "libresoc.v:141788.7-141788.26" + wire $1\wb_dcache_en[0:0] + attribute \src "libresoc.v:142806.3-142824.6" + wire $1\wb_icache_en$next[0:0]$6117 + attribute \src "libresoc.v:141793.7-141793.26" + wire $1\wb_icache_en[0:0] + attribute \src "libresoc.v:142672.3-142704.6" + wire width 4 $2\dmi0__addr_i$next[3:0]$6093 + attribute \src "libresoc.v:142758.3-142784.6" + wire width 64 $2\dmi0__din$next[63:0]$6106 + attribute \src "libresoc.v:142361.3-142377.6" + wire $2\dmi0_addrsr__oe$next[0:0]$6030 + attribute \src "libresoc.v:142378.3-142398.6" + wire width 8 $2\dmi0_addrsr_reg$next[7:0]$6034 + attribute \src "libresoc.v:142785.3-142805.6" + wire width 64 $2\dmi0_datasr__i$next[63:0]$6111 + attribute \src "libresoc.v:142417.3-142433.6" + wire width 2 $2\dmi0_datasr__oe$next[1:0]$6045 + attribute \src "libresoc.v:142434.3-142454.6" + wire width 64 $2\dmi0_datasr_reg$next[63:0]$6049 + attribute \src "libresoc.v:142705.3-142757.6" + wire width 3 $2\fsm_state$503$next[2:0]$6099 + attribute \src "libresoc.v:142571.3-142623.6" + wire width 3 $2\fsm_state$next[2:0]$6076 + attribute \src "libresoc.v:142853.3-142873.6" + wire width 154 $2\io_bd$next[153:0]$6128 + attribute \src "libresoc.v:142835.3-142852.6" + wire width 154 $2\io_sr$next[153:0]$6124 + attribute \src "libresoc.v:142538.3-142570.6" + wire width 29 $2\jtag_wb__adr$next[28:0]$6070 + attribute \src "libresoc.v:142624.3-142650.6" + wire width 64 $2\jtag_wb__dat_w$next[63:0]$6083 + attribute \src "libresoc.v:142249.3-142265.6" + wire $2\jtag_wb_addrsr__oe$next[0:0]$6000 + attribute \src "libresoc.v:142266.3-142286.6" + wire width 29 $2\jtag_wb_addrsr_reg$next[28:0]$6004 + attribute \src "libresoc.v:142651.3-142671.6" + wire width 64 $2\jtag_wb_datasr__i$next[63:0]$6088 + attribute \src "libresoc.v:142305.3-142321.6" + wire width 2 $2\jtag_wb_datasr__oe$next[1:0]$6015 + attribute \src "libresoc.v:142322.3-142342.6" + wire width 64 $2\jtag_wb_datasr_reg$next[63:0]$6019 + attribute \src "libresoc.v:142193.3-142209.6" + wire $2\sr0__oe$next[0:0]$5985 + attribute \src "libresoc.v:142210.3-142230.6" + wire width 3 $2\sr0_reg$next[2:0]$5989 + attribute \src "libresoc.v:142473.3-142489.6" + wire $2\sr5__oe$next[0:0]$6060 + attribute \src "libresoc.v:142490.3-142510.6" + wire width 2 $2\sr5_reg$next[1:0]$6064 + attribute \src "libresoc.v:142806.3-142824.6" + wire $2\wb_dcache_en$next[0:0]$6118 + attribute \src "libresoc.v:142806.3-142824.6" + wire $2\wb_icache_en$next[0:0]$6119 + attribute \src "libresoc.v:142672.3-142704.6" + wire width 4 $3\dmi0__addr_i$next[3:0]$6094 + attribute \src "libresoc.v:142758.3-142784.6" + wire width 64 $3\dmi0__din$next[63:0]$6107 + attribute \src "libresoc.v:142378.3-142398.6" + wire width 8 $3\dmi0_addrsr_reg$next[7:0]$6035 + attribute \src "libresoc.v:142785.3-142805.6" + wire width 64 $3\dmi0_datasr__i$next[63:0]$6112 + attribute \src "libresoc.v:142434.3-142454.6" + wire width 64 $3\dmi0_datasr_reg$next[63:0]$6050 + attribute \src "libresoc.v:142705.3-142757.6" + wire width 3 $3\fsm_state$503$next[2:0]$6100 + attribute \src "libresoc.v:142571.3-142623.6" + wire width 3 $3\fsm_state$next[2:0]$6077 + attribute \src "libresoc.v:142538.3-142570.6" + wire width 29 $3\jtag_wb__adr$next[28:0]$6071 + attribute \src "libresoc.v:142624.3-142650.6" + wire width 64 $3\jtag_wb__dat_w$next[63:0]$6084 + attribute \src "libresoc.v:142266.3-142286.6" + wire width 29 $3\jtag_wb_addrsr_reg$next[28:0]$6005 + attribute \src "libresoc.v:142651.3-142671.6" + wire width 64 $3\jtag_wb_datasr__i$next[63:0]$6089 + attribute \src "libresoc.v:142322.3-142342.6" + wire width 64 $3\jtag_wb_datasr_reg$next[63:0]$6020 + attribute \src "libresoc.v:142210.3-142230.6" + wire width 3 $3\sr0_reg$next[2:0]$5990 + attribute \src "libresoc.v:142490.3-142510.6" + wire width 2 $3\sr5_reg$next[1:0]$6065 + attribute \src "libresoc.v:142672.3-142704.6" + wire width 4 $4\dmi0__addr_i$next[3:0]$6095 + attribute \src "libresoc.v:142705.3-142757.6" + wire width 3 $4\fsm_state$503$next[2:0]$6101 + attribute \src "libresoc.v:142571.3-142623.6" + wire width 3 $4\fsm_state$next[2:0]$6078 + attribute \src "libresoc.v:142538.3-142570.6" + wire width 29 $4\jtag_wb__adr$next[28:0]$6072 + attribute \src "libresoc.v:142705.3-142757.6" + wire width 3 $5\fsm_state$503$next[2:0]$6102 + attribute \src "libresoc.v:142571.3-142623.6" + wire width 3 $5\fsm_state$next[2:0]$6079 + attribute \src "libresoc.v:142016.19-142016.112" + wire width 30 $add$libresoc.v:142016$5901_Y + attribute \src "libresoc.v:142018.19-142018.112" + wire width 30 $add$libresoc.v:142018$5903_Y + attribute \src "libresoc.v:142024.19-142024.112" + wire width 5 $add$libresoc.v:142024$5910_Y + attribute \src "libresoc.v:142025.19-142025.112" + wire width 5 $add$libresoc.v:142025$5911_Y + attribute \src "libresoc.v:141840.18-141840.112" + wire $and$libresoc.v:141840$5725_Y + attribute \src "libresoc.v:141907.18-141907.108" + wire $and$libresoc.v:141907$5792_Y + attribute \src "libresoc.v:141918.18-141918.110" + wire $and$libresoc.v:141918$5803_Y + attribute \src "libresoc.v:141946.19-141946.110" + wire $and$libresoc.v:141946$5831_Y + attribute \src "libresoc.v:141949.19-141949.114" + wire $and$libresoc.v:141949$5834_Y + attribute \src "libresoc.v:141952.19-141952.112" + wire $and$libresoc.v:141952$5837_Y + attribute \src "libresoc.v:141954.19-141954.113" + wire $and$libresoc.v:141954$5839_Y + attribute \src "libresoc.v:141956.19-141956.121" + wire $and$libresoc.v:141956$5841_Y + attribute \src "libresoc.v:141959.19-141959.114" + wire $and$libresoc.v:141959$5844_Y + attribute \src "libresoc.v:141961.19-141961.112" + wire $and$libresoc.v:141961$5846_Y + attribute \src "libresoc.v:141965.19-141965.113" + wire $and$libresoc.v:141965$5850_Y + attribute \src "libresoc.v:141967.19-141967.132" + wire $and$libresoc.v:141967$5852_Y + attribute \src "libresoc.v:141971.19-141971.114" + wire $and$libresoc.v:141971$5856_Y + attribute \src "libresoc.v:141973.19-141973.112" + wire $and$libresoc.v:141973$5858_Y + attribute \src "libresoc.v:141976.19-141976.113" + wire $and$libresoc.v:141976$5861_Y + attribute \src "libresoc.v:141978.19-141978.132" + wire $and$libresoc.v:141978$5863_Y + attribute \src "libresoc.v:141981.19-141981.114" + wire $and$libresoc.v:141981$5866_Y + attribute \src "libresoc.v:141983.19-141983.112" + wire $and$libresoc.v:141983$5868_Y + attribute \src "libresoc.v:141985.18-141985.108" + wire $and$libresoc.v:141985$5870_Y + attribute \src "libresoc.v:141986.19-141986.113" + wire $and$libresoc.v:141986$5871_Y + attribute \src "libresoc.v:141988.19-141988.129" + wire $and$libresoc.v:141988$5873_Y + attribute \src "libresoc.v:141992.19-141992.114" + wire $and$libresoc.v:141992$5877_Y + attribute \src "libresoc.v:141994.19-141994.112" + wire $and$libresoc.v:141994$5879_Y + attribute \src "libresoc.v:141996.18-141996.111" + wire $and$libresoc.v:141996$5881_Y + attribute \src "libresoc.v:141997.19-141997.113" + wire $and$libresoc.v:141997$5882_Y + attribute \src "libresoc.v:141999.19-141999.129" + wire $and$libresoc.v:141999$5884_Y + attribute \src "libresoc.v:142002.19-142002.114" + wire $and$libresoc.v:142002$5887_Y + attribute \src "libresoc.v:142004.19-142004.112" + wire $and$libresoc.v:142004$5889_Y + attribute \src "libresoc.v:142006.19-142006.113" + wire $and$libresoc.v:142006$5891_Y + attribute \src "libresoc.v:142009.19-142009.121" + wire $and$libresoc.v:142009$5894_Y + attribute \src "libresoc.v:142041.17-142041.106" + wire $and$libresoc.v:142041$5927_Y + attribute \src "libresoc.v:141796.17-141796.110" + wire $eq$libresoc.v:141796$5681_Y + attribute \src "libresoc.v:141807.18-141807.111" + wire $eq$libresoc.v:141807$5692_Y + attribute \src "libresoc.v:141818.18-141818.111" + wire $eq$libresoc.v:141818$5703_Y + attribute \src "libresoc.v:141851.17-141851.110" + wire $eq$libresoc.v:141851$5736_Y + attribute \src "libresoc.v:141852.18-141852.111" + wire $eq$libresoc.v:141852$5737_Y + attribute \src "libresoc.v:141863.18-141863.111" + wire $eq$libresoc.v:141863$5748_Y + attribute \src "libresoc.v:141885.18-141885.111" + wire $eq$libresoc.v:141885$5770_Y + attribute \src "libresoc.v:141929.18-141929.111" + wire $eq$libresoc.v:141929$5814_Y + attribute \src "libresoc.v:141940.18-141940.111" + wire $eq$libresoc.v:141940$5825_Y + attribute \src "libresoc.v:141941.19-141941.112" + wire $eq$libresoc.v:141941$5826_Y + attribute \src "libresoc.v:141942.19-141942.112" + wire $eq$libresoc.v:141942$5827_Y + attribute \src "libresoc.v:141944.19-141944.112" + wire $eq$libresoc.v:141944$5829_Y + attribute \src "libresoc.v:141947.19-141947.112" + wire $eq$libresoc.v:141947$5832_Y + attribute \src "libresoc.v:141957.19-141957.112" + wire $eq$libresoc.v:141957$5842_Y + attribute \src "libresoc.v:141962.17-141962.110" + wire $eq$libresoc.v:141962$5847_Y + attribute \src "libresoc.v:141963.18-141963.111" + wire $eq$libresoc.v:141963$5848_Y + attribute \src "libresoc.v:141968.19-141968.112" + wire $eq$libresoc.v:141968$5853_Y + attribute \src "libresoc.v:141969.19-141969.112" + wire $eq$libresoc.v:141969$5854_Y + attribute \src "libresoc.v:141979.19-141979.112" + wire $eq$libresoc.v:141979$5864_Y + attribute \src "libresoc.v:141989.19-141989.112" + wire $eq$libresoc.v:141989$5874_Y + attribute \src "libresoc.v:141990.19-141990.112" + wire $eq$libresoc.v:141990$5875_Y + attribute \src "libresoc.v:142000.19-142000.112" + wire $eq$libresoc.v:142000$5885_Y + attribute \src "libresoc.v:142007.18-142007.111" + wire $eq$libresoc.v:142007$5892_Y + attribute \src "libresoc.v:142010.19-142010.110" + wire $eq$libresoc.v:142010$5895_Y + attribute \src "libresoc.v:142012.19-142012.110" + wire $eq$libresoc.v:142012$5897_Y + attribute \src "libresoc.v:142013.19-142013.110" + wire $eq$libresoc.v:142013$5898_Y + attribute \src "libresoc.v:142015.19-142015.110" + wire $eq$libresoc.v:142015$5900_Y + attribute \src "libresoc.v:142017.18-142017.111" + wire $eq$libresoc.v:142017$5902_Y + attribute \src "libresoc.v:142020.19-142020.116" + wire $eq$libresoc.v:142020$5906_Y + attribute \src "libresoc.v:142021.19-142021.116" + wire $eq$libresoc.v:142021$5907_Y + attribute \src "libresoc.v:142023.19-142023.116" + wire $eq$libresoc.v:142023$5909_Y + attribute \src "libresoc.v:142019.19-142019.106" + wire width 8 $extend$libresoc.v:142019$5904_Y + attribute \src "libresoc.v:141948.19-141948.109" + wire $ne$libresoc.v:141948$5833_Y + attribute \src "libresoc.v:141950.19-141950.109" + wire $ne$libresoc.v:141950$5835_Y + attribute \src "libresoc.v:141953.19-141953.109" + wire $ne$libresoc.v:141953$5838_Y + attribute \src "libresoc.v:141958.19-141958.120" + wire $ne$libresoc.v:141958$5843_Y + attribute \src "libresoc.v:141960.19-141960.120" + wire $ne$libresoc.v:141960$5845_Y + attribute \src "libresoc.v:141964.19-141964.120" + wire $ne$libresoc.v:141964$5849_Y + attribute \src "libresoc.v:141970.19-141970.120" + wire $ne$libresoc.v:141970$5855_Y + attribute \src "libresoc.v:141972.19-141972.120" + wire $ne$libresoc.v:141972$5857_Y + attribute \src "libresoc.v:141975.19-141975.120" + wire $ne$libresoc.v:141975$5860_Y + attribute \src "libresoc.v:141980.19-141980.117" + wire $ne$libresoc.v:141980$5865_Y + attribute \src "libresoc.v:141982.19-141982.117" + wire $ne$libresoc.v:141982$5867_Y + attribute \src "libresoc.v:141984.19-141984.117" + wire $ne$libresoc.v:141984$5869_Y + attribute \src "libresoc.v:141991.19-141991.117" + wire $ne$libresoc.v:141991$5876_Y + attribute \src "libresoc.v:141993.19-141993.117" + wire $ne$libresoc.v:141993$5878_Y + attribute \src "libresoc.v:141995.19-141995.117" + wire $ne$libresoc.v:141995$5880_Y + attribute \src "libresoc.v:142001.19-142001.109" + wire $ne$libresoc.v:142001$5886_Y + attribute \src "libresoc.v:142003.19-142003.109" + wire $ne$libresoc.v:142003$5888_Y + attribute \src "libresoc.v:142005.19-142005.109" + wire $ne$libresoc.v:142005$5890_Y + attribute \src "libresoc.v:141955.19-141955.110" + wire $not$libresoc.v:141955$5840_Y + attribute \src "libresoc.v:141966.19-141966.121" + wire $not$libresoc.v:141966$5851_Y + attribute \src "libresoc.v:141977.19-141977.121" + wire $not$libresoc.v:141977$5862_Y + attribute \src "libresoc.v:141987.19-141987.118" + wire $not$libresoc.v:141987$5872_Y + attribute \src "libresoc.v:141998.19-141998.118" + wire $not$libresoc.v:141998$5883_Y + attribute \src "libresoc.v:142008.19-142008.110" + wire $not$libresoc.v:142008$5893_Y + attribute \src "libresoc.v:142011.19-142011.100" + wire $not$libresoc.v:142011$5896_Y + attribute \src "libresoc.v:141829.18-141829.104" + wire $or$libresoc.v:141829$5714_Y + attribute \src "libresoc.v:141874.18-141874.104" + wire $or$libresoc.v:141874$5759_Y + attribute \src "libresoc.v:141896.18-141896.104" + wire $or$libresoc.v:141896$5781_Y + attribute \src "libresoc.v:141943.19-141943.107" + wire $or$libresoc.v:141943$5828_Y + attribute \src "libresoc.v:141945.19-141945.107" + wire $or$libresoc.v:141945$5830_Y + attribute \src "libresoc.v:141951.18-141951.104" + wire $or$libresoc.v:141951$5836_Y + attribute \src "libresoc.v:141974.18-141974.104" + wire $or$libresoc.v:141974$5859_Y + attribute \src "libresoc.v:142014.19-142014.107" + wire $or$libresoc.v:142014$5899_Y + attribute \src "libresoc.v:142022.19-142022.107" + wire $or$libresoc.v:142022$5908_Y + attribute \src "libresoc.v:142030.17-142030.101" + wire $or$libresoc.v:142030$5916_Y + attribute \src "libresoc.v:142019.19-142019.106" + wire width 8 $pos$libresoc.v:142019$5905_Y + attribute \src "libresoc.v:141797.18-141797.133" + wire $ternary$libresoc.v:141797$5682_Y + attribute \src "libresoc.v:141798.19-141798.133" + wire $ternary$libresoc.v:141798$5683_Y + attribute \src "libresoc.v:141799.19-141799.134" + wire $ternary$libresoc.v:141799$5684_Y + attribute \src "libresoc.v:141800.19-141800.133" + wire $ternary$libresoc.v:141800$5685_Y + attribute \src "libresoc.v:141801.19-141801.132" + wire $ternary$libresoc.v:141801$5686_Y + attribute \src "libresoc.v:141802.19-141802.133" + wire $ternary$libresoc.v:141802$5687_Y + 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$ternary$libresoc.v:141886$5771_Y + attribute \src "libresoc.v:141887.19-141887.135" + wire $ternary$libresoc.v:141887$5772_Y + attribute \src "libresoc.v:141888.19-141888.133" + wire $ternary$libresoc.v:141888$5773_Y + attribute \src "libresoc.v:141889.19-141889.133" + wire $ternary$libresoc.v:141889$5774_Y + attribute \src "libresoc.v:141890.19-141890.133" + wire $ternary$libresoc.v:141890$5775_Y + attribute \src "libresoc.v:141891.19-141891.133" + wire $ternary$libresoc.v:141891$5776_Y + attribute \src "libresoc.v:141892.19-141892.133" + wire $ternary$libresoc.v:141892$5777_Y + attribute \src "libresoc.v:141893.19-141893.133" + wire $ternary$libresoc.v:141893$5778_Y + attribute \src "libresoc.v:141894.19-141894.133" + wire $ternary$libresoc.v:141894$5779_Y + attribute \src "libresoc.v:141895.19-141895.133" + wire $ternary$libresoc.v:141895$5780_Y + attribute \src "libresoc.v:141897.19-141897.133" + wire $ternary$libresoc.v:141897$5782_Y + attribute \src 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wire \$429 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" + wire \$43 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" + wire \$431 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" + wire \$433 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" + wire \$435 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" + wire \$437 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" + wire \$439 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + wire \$441 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + wire \$443 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" + wire \$445 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" + wire \$447 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" + wire \$449 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:403" + wire \$45 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" + wire \$451 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" + wire \$453 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" + wire \$455 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" + wire \$457 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" + wire \$459 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + wire \$461 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + wire \$463 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" + wire \$465 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" + wire \$467 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" + wire \$469 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:404" + wire \$47 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" + wire \$471 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" + wire \$473 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" + wire \$475 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" + wire \$477 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + wire \$479 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + wire \$481 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:790" + wire \$483 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:790" + wire \$484 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:791" + wire \$487 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:791" + wire \$489 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:405" + wire \$49 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:791" + wire \$491 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:792" + wire \$493 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:761" + wire width 30 \$495 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:761" + wire width 30 \$496 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:786" + wire width 30 \$498 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:786" + wire width 30 \$499 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" + wire width 8 \$501 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:523" + wire \$504 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:523" + wire \$506 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:523" + wire \$508 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" + wire \$51 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:524" + wire \$510 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:494" + wire width 5 \$512 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:494" + wire width 5 \$513 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:518" + wire width 5 \$515 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:518" + wire width 5 \$516 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" + wire \$53 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" + wire \$55 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + wire \$57 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + wire \$59 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + wire \$61 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + wire \$63 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + wire \$65 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + wire \$67 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + wire \$69 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + wire \$71 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + wire \$73 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + wire \$75 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + wire \$77 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + wire \$79 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + wire \$81 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + wire \$83 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + wire \$85 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + wire \$87 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + wire \$89 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + wire \$91 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + wire \$93 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + wire \$95 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + wire \$97 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + wire \$99 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" + wire input 328 \TAP_bus__tck + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" + wire input 164 \TAP_bus__tdi + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" + wire output 319 \TAP_bus__tdo + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" + wire input 329 \TAP_bus__tms + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:414" + wire \TAP_tdo + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:24" + wire \_fsm_capture + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:23" + wire \_fsm_isdr + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:22" + wire \_fsm_isir + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:25" + wire \_fsm_shift + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:26" + wire \_fsm_update + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:225" + wire \_idblock_TAP_id_tdo + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:375" + wire \_idblock_id_bypass + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:374" + wire \_idblock_select_id + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:127" + wire width 4 \_irblock_ir + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:128" + wire \_irblock_tdo + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:194" + wire input 330 \clk + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" + wire input 6 \dmi0__ack_o + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" + wire width 4 output 2 \dmi0__addr_i + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" + wire width 4 \dmi0__addr_i$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" + wire width 64 output 5 \dmi0__din + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" + wire width 64 \dmi0__din$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" + wire width 64 input 7 \dmi0__dout + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" + wire output 3 \dmi0__req_i + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" + wire output 4 \dmi0__we_i + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:471" + wire width 8 \dmi0_addrsr__i + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:471" + wire width 8 \dmi0_addrsr__o + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:471" + wire \dmi0_addrsr__oe + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:471" + wire \dmi0_addrsr__oe$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:646" + wire \dmi0_addrsr_capture + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:645" + wire \dmi0_addrsr_isir + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" + wire width 8 \dmi0_addrsr_reg + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" + wire width 8 \dmi0_addrsr_reg$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:647" + wire \dmi0_addrsr_shift + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:648" + wire \dmi0_addrsr_update + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" + wire \dmi0_addrsr_update_core + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" + wire \dmi0_addrsr_update_core$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" + wire \dmi0_addrsr_update_core_prev + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" + wire \dmi0_addrsr_update_core_prev$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:473" + wire width 64 \dmi0_datasr__i + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:473" + wire width 64 \dmi0_datasr__i$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:473" + wire width 64 \dmi0_datasr__o + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:473" + wire width 2 \dmi0_datasr__oe + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:473" + wire width 2 \dmi0_datasr__oe$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:646" + wire \dmi0_datasr_capture + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:645" + wire width 2 \dmi0_datasr_isir + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" + wire width 64 \dmi0_datasr_reg + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" + wire width 64 \dmi0_datasr_reg$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:647" + wire \dmi0_datasr_shift + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:648" + wire \dmi0_datasr_update + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" + wire \dmi0_datasr_update_core + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" + wire \dmi0_datasr_update_core$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" + wire \dmi0_datasr_update_core_prev + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" + wire \dmi0_datasr_update_core_prev$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 165 \eint_0__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 10 \eint_0__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 166 \eint_1__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 11 \eint_1__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 167 \eint_2__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 12 \eint_2__pad__i + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:754" + wire width 3 \fsm_state + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + wire width 3 \fsm_state$503 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + wire width 3 \fsm_state$503$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:754" + wire width 3 \fsm_state$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 174 \gpio_e10__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 20 \gpio_e10__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 21 \gpio_e10__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 19 \gpio_e10__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 175 \gpio_e10__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 176 \gpio_e10__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 177 \gpio_e11__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 23 \gpio_e11__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 24 \gpio_e11__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 22 \gpio_e11__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 178 \gpio_e11__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 179 \gpio_e11__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 180 \gpio_e12__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 26 \gpio_e12__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 27 \gpio_e12__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 25 \gpio_e12__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 181 \gpio_e12__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 182 \gpio_e12__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 183 \gpio_e13__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 29 \gpio_e13__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 30 \gpio_e13__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 28 \gpio_e13__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 184 \gpio_e13__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 185 \gpio_e13__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 186 \gpio_e14__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 32 \gpio_e14__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 33 \gpio_e14__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 31 \gpio_e14__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 187 \gpio_e14__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 188 \gpio_e14__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 189 \gpio_e15__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 35 \gpio_e15__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 36 \gpio_e15__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 34 \gpio_e15__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 190 \gpio_e15__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 191 \gpio_e15__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 168 \gpio_e8__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 14 \gpio_e8__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 15 \gpio_e8__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 13 \gpio_e8__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 169 \gpio_e8__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 170 \gpio_e8__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 171 \gpio_e9__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 17 \gpio_e9__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 18 \gpio_e9__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 16 \gpio_e9__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 172 \gpio_e9__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 173 \gpio_e9__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 192 \gpio_s0__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 38 \gpio_s0__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 39 \gpio_s0__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 37 \gpio_s0__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 193 \gpio_s0__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 194 \gpio_s0__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 195 \gpio_s1__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 41 \gpio_s1__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 42 \gpio_s1__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 40 \gpio_s1__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 196 \gpio_s1__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 197 \gpio_s1__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 198 \gpio_s2__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 44 \gpio_s2__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 45 \gpio_s2__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 43 \gpio_s2__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 199 \gpio_s2__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 200 \gpio_s2__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 201 \gpio_s3__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 47 \gpio_s3__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 48 \gpio_s3__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 46 \gpio_s3__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 202 \gpio_s3__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 203 \gpio_s3__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 204 \gpio_s4__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 50 \gpio_s4__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 51 \gpio_s4__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 49 \gpio_s4__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 205 \gpio_s4__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 206 \gpio_s4__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 207 \gpio_s5__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 53 \gpio_s5__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 54 \gpio_s5__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 52 \gpio_s5__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 208 \gpio_s5__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 209 \gpio_s5__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 210 \gpio_s6__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 56 \gpio_s6__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 57 \gpio_s6__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 55 \gpio_s6__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 211 \gpio_s6__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 212 \gpio_s6__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 213 \gpio_s7__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 59 \gpio_s7__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 60 \gpio_s7__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 58 \gpio_s7__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 214 \gpio_s7__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 215 \gpio_s7__pad__oe + attribute \src "libresoc.v:140366.7-140366.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:549" + wire width 154 \io_bd + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:549" + wire width 154 \io_bd$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:395" + wire \io_bd2core + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:394" + wire \io_bd2io + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:391" + wire \io_capture + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:392" + wire \io_shift + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:548" + wire width 154 \io_sr + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:548" + wire width 154 \io_sr$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:393" + wire \io_update + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire input 326 \jtag_wb__ack + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire width 29 output 320 \jtag_wb__adr + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire width 29 \jtag_wb__adr$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire output 322 \jtag_wb__cyc + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire width 64 input 327 \jtag_wb__dat_r + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire width 64 output 325 \jtag_wb__dat_w + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire width 64 \jtag_wb__dat_w$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire output 321 \jtag_wb__sel + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire output 323 \jtag_wb__stb + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire output 324 \jtag_wb__we + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:731" + wire width 29 \jtag_wb_addrsr__i + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:731" + wire width 29 \jtag_wb_addrsr__o + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:731" + wire \jtag_wb_addrsr__oe + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:731" + wire \jtag_wb_addrsr__oe$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:646" + wire \jtag_wb_addrsr_capture + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:645" + wire \jtag_wb_addrsr_isir + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" + wire width 29 \jtag_wb_addrsr_reg + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" + wire width 29 \jtag_wb_addrsr_reg$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:647" + wire \jtag_wb_addrsr_shift + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:648" + wire \jtag_wb_addrsr_update + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" + wire \jtag_wb_addrsr_update_core + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" + wire \jtag_wb_addrsr_update_core$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" + wire \jtag_wb_addrsr_update_core_prev + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" + wire \jtag_wb_addrsr_update_core_prev$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:735" + wire width 64 \jtag_wb_datasr__i + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:735" + wire width 64 \jtag_wb_datasr__i$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:735" + wire width 64 \jtag_wb_datasr__o + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:735" + wire width 2 \jtag_wb_datasr__oe + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:735" + wire width 2 \jtag_wb_datasr__oe$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:646" + wire \jtag_wb_datasr_capture + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:645" + wire width 2 \jtag_wb_datasr_isir + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" + wire width 64 \jtag_wb_datasr_reg + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" + wire width 64 \jtag_wb_datasr_reg$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:647" + wire \jtag_wb_datasr_shift + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:648" + wire \jtag_wb_datasr_update + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" + wire \jtag_wb_datasr_update_core + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" + wire \jtag_wb_datasr_update_core$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" + wire \jtag_wb_datasr_update_core_prev + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" + wire \jtag_wb_datasr_update_core_prev$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 61 \mspi0_clk__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 216 \mspi0_clk__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 62 \mspi0_cs_n__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 217 \mspi0_cs_n__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 219 \mspi0_miso__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 64 \mspi0_miso__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 63 \mspi0_mosi__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 218 \mspi0_mosi__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 65 \mspi1_clk__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 220 \mspi1_clk__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 66 \mspi1_cs_n__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 221 \mspi1_cs_n__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 223 \mspi1_miso__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 68 \mspi1_miso__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 67 \mspi1_mosi__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 222 \mspi1_mosi__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 72 \mtwi_scl__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 227 \mtwi_scl__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 224 \mtwi_sda__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 70 \mtwi_sda__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 71 \mtwi_sda__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 69 \mtwi_sda__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 225 \mtwi_sda__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 226 \mtwi_sda__pad__oe + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:29" + wire \negjtag_clk + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:29" + wire \negjtag_rst + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:28" + wire \posjtag_clk + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:28" + wire \posjtag_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 73 \pwm_0__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 228 \pwm_0__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 74 \pwm_1__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 229 \pwm_1__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:194" + wire input 1 \rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 78 \sd0_clk__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 233 \sd0_clk__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 230 \sd0_cmd__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 76 \sd0_cmd__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 77 \sd0_cmd__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 75 \sd0_cmd__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 231 \sd0_cmd__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 232 \sd0_cmd__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 234 \sd0_data0__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 80 \sd0_data0__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 81 \sd0_data0__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 79 \sd0_data0__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 235 \sd0_data0__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 236 \sd0_data0__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 237 \sd0_data1__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 83 \sd0_data1__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 84 \sd0_data1__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 82 \sd0_data1__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 238 \sd0_data1__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 239 \sd0_data1__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 240 \sd0_data2__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 86 \sd0_data2__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 87 \sd0_data2__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 85 \sd0_data2__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 241 \sd0_data2__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 242 \sd0_data2__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 243 \sd0_data3__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 89 \sd0_data3__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 90 \sd0_data3__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 88 \sd0_data3__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 244 \sd0_data3__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 245 \sd0_data3__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 116 \sdr_a_0__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 271 \sdr_a_0__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 134 \sdr_a_10__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 289 \sdr_a_10__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 135 \sdr_a_11__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 290 \sdr_a_11__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 136 \sdr_a_12__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 291 \sdr_a_12__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 117 \sdr_a_1__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 272 \sdr_a_1__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 118 \sdr_a_2__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 273 \sdr_a_2__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 119 \sdr_a_3__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 274 \sdr_a_3__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 120 \sdr_a_4__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 275 \sdr_a_4__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 121 \sdr_a_5__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 276 \sdr_a_5__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 122 \sdr_a_6__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 277 \sdr_a_6__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 123 \sdr_a_7__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 278 \sdr_a_7__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 124 \sdr_a_8__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 279 \sdr_a_8__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 125 \sdr_a_9__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 280 \sdr_a_9__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 126 \sdr_ba_0__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 281 \sdr_ba_0__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 127 \sdr_ba_1__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 282 \sdr_ba_1__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 131 \sdr_cas_n__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 286 \sdr_cas_n__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 129 \sdr_cke__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 284 \sdr_cke__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 128 \sdr_clock__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 283 \sdr_clock__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 133 \sdr_cs_n__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 288 \sdr_cs_n__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 91 \sdr_dm_0__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 246 \sdr_dm_0__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 292 \sdr_dm_1__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 138 \sdr_dm_1__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 139 \sdr_dm_1__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 137 \sdr_dm_1__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 293 \sdr_dm_1__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 294 \sdr_dm_1__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 247 \sdr_dq_0__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 93 \sdr_dq_0__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 94 \sdr_dq_0__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 92 \sdr_dq_0__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 248 \sdr_dq_0__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 249 \sdr_dq_0__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 301 \sdr_dq_10__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 147 \sdr_dq_10__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 148 \sdr_dq_10__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 146 \sdr_dq_10__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 302 \sdr_dq_10__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 303 \sdr_dq_10__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 304 \sdr_dq_11__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 150 \sdr_dq_11__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 151 \sdr_dq_11__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 149 \sdr_dq_11__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 305 \sdr_dq_11__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 306 \sdr_dq_11__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 307 \sdr_dq_12__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 153 \sdr_dq_12__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 154 \sdr_dq_12__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 152 \sdr_dq_12__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 308 \sdr_dq_12__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 309 \sdr_dq_12__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 310 \sdr_dq_13__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 156 \sdr_dq_13__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 157 \sdr_dq_13__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 155 \sdr_dq_13__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 311 \sdr_dq_13__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 312 \sdr_dq_13__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 313 \sdr_dq_14__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 159 \sdr_dq_14__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 160 \sdr_dq_14__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 158 \sdr_dq_14__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 314 \sdr_dq_14__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 315 \sdr_dq_14__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 316 \sdr_dq_15__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 162 \sdr_dq_15__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 163 \sdr_dq_15__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 161 \sdr_dq_15__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 317 \sdr_dq_15__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 318 \sdr_dq_15__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 250 \sdr_dq_1__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 96 \sdr_dq_1__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 97 \sdr_dq_1__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 95 \sdr_dq_1__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 251 \sdr_dq_1__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 252 \sdr_dq_1__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 253 \sdr_dq_2__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 99 \sdr_dq_2__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 100 \sdr_dq_2__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 98 \sdr_dq_2__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 254 \sdr_dq_2__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 255 \sdr_dq_2__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 256 \sdr_dq_3__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 102 \sdr_dq_3__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 103 \sdr_dq_3__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 101 \sdr_dq_3__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 257 \sdr_dq_3__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 258 \sdr_dq_3__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 259 \sdr_dq_4__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 105 \sdr_dq_4__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 106 \sdr_dq_4__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 104 \sdr_dq_4__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 260 \sdr_dq_4__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 261 \sdr_dq_4__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 262 \sdr_dq_5__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 108 \sdr_dq_5__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 109 \sdr_dq_5__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 107 \sdr_dq_5__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 263 \sdr_dq_5__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 264 \sdr_dq_5__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 265 \sdr_dq_6__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 111 \sdr_dq_6__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 112 \sdr_dq_6__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 110 \sdr_dq_6__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 266 \sdr_dq_6__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 267 \sdr_dq_6__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 268 \sdr_dq_7__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 114 \sdr_dq_7__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 115 \sdr_dq_7__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 113 \sdr_dq_7__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 269 \sdr_dq_7__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 270 \sdr_dq_7__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 295 \sdr_dq_8__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 141 \sdr_dq_8__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 142 \sdr_dq_8__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 140 \sdr_dq_8__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 296 \sdr_dq_8__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 297 \sdr_dq_8__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 298 \sdr_dq_9__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 144 \sdr_dq_9__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 145 \sdr_dq_9__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 143 \sdr_dq_9__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 299 \sdr_dq_9__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 300 \sdr_dq_9__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 130 \sdr_ras_n__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 285 \sdr_ras_n__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 132 \sdr_we_n__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 287 \sdr_we_n__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:80" + wire width 3 \sr0__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:80" + wire width 3 \sr0__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:80" + wire \sr0__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:80" + wire \sr0__oe$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:646" + wire \sr0_capture + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:645" + wire \sr0_isir + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" + wire width 3 \sr0_reg + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" + wire width 3 \sr0_reg$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:647" + wire \sr0_shift + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:648" + wire \sr0_update + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" + wire \sr0_update_core + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" + wire \sr0_update_core$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" + wire \sr0_update_core_prev + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" + wire \sr0_update_core_prev$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:91" + wire width 2 \sr5__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:91" + wire \sr5__ie + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:91" + wire width 2 \sr5__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:91" + wire \sr5__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:91" + wire \sr5__oe$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:646" + wire \sr5_capture + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:645" + wire \sr5_isir + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" + wire width 2 \sr5_reg + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" + wire width 2 \sr5_reg$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:647" + wire \sr5_shift + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:648" + wire \sr5_update + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" + wire \sr5_update_core + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" + wire \sr5_update_core$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" + wire \sr5_update_core_prev + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" + wire \sr5_update_core_prev$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:93" + wire output 8 \wb_dcache_en + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:93" + wire \wb_dcache_en$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:92" + wire output 9 \wb_icache_en + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:92" + wire \wb_icache_en$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:761" + cell $add $add$libresoc.v:142016$5901 + parameter \A_SIGNED 0 + parameter \A_WIDTH 29 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 30 + connect \A \jtag_wb__adr + connect \B 1'1 + connect \Y $add$libresoc.v:142016$5901_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:786" + cell $add $add$libresoc.v:142018$5903 + parameter \A_SIGNED 0 + parameter \A_WIDTH 29 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 30 + connect \A \jtag_wb__adr + connect \B 1'1 + connect \Y $add$libresoc.v:142018$5903_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:494" + cell $add $add$libresoc.v:142024$5910 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 5 + connect \A \dmi0__addr_i + connect \B 1'1 + connect \Y $add$libresoc.v:142024$5910_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:518" + cell $add $add$libresoc.v:142025$5911 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 5 + connect \A \dmi0__addr_i + connect \B 1'1 + connect \Y $add$libresoc.v:142025$5911_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:400" + cell $and $and$libresoc.v:141840$5725 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$15 + connect \B \_fsm_capture + connect \Y $and$libresoc.v:141840$5725_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" + cell $and $and$libresoc.v:141907$5792 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \_fsm_isdr + connect \B \$27 + connect \Y $and$libresoc.v:141907$5792_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:402" + cell $and $and$libresoc.v:141918$5803 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$29 + connect \B \_fsm_shift + connect \Y $and$libresoc.v:141918$5803_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" + cell $and $and$libresoc.v:141946$5831 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \_fsm_isdr + connect \B \$367 + connect \Y $and$libresoc.v:141946$5831_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" + cell $and $and$libresoc.v:141949$5834 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$373 + connect \B \_fsm_capture + connect \Y $and$libresoc.v:141949$5834_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" + cell $and $and$libresoc.v:141952$5837 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$377 + connect \B \_fsm_shift + connect \Y $and$libresoc.v:141952$5837_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" + cell $and $and$libresoc.v:141954$5839 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$381 + connect \B \_fsm_update + connect \Y $and$libresoc.v:141954$5839_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + cell $and $and$libresoc.v:141956$5841 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \sr0_update_core_prev + connect \B \$385 + connect \Y $and$libresoc.v:141956$5841_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" + cell $and $and$libresoc.v:141959$5844 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$391 + connect \B \_fsm_capture + connect \Y $and$libresoc.v:141959$5844_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" + cell $and $and$libresoc.v:141961$5846 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$395 + connect \B \_fsm_shift + connect \Y $and$libresoc.v:141961$5846_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" + cell $and $and$libresoc.v:141965$5850 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$399 + connect \B \_fsm_update + connect \Y $and$libresoc.v:141965$5850_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + cell $and $and$libresoc.v:141967$5852 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \jtag_wb_addrsr_update_core_prev + connect \B \$403 + connect \Y $and$libresoc.v:141967$5852_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" + cell $and $and$libresoc.v:141971$5856 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$411 + connect \B \_fsm_capture + connect \Y $and$libresoc.v:141971$5856_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" + cell $and $and$libresoc.v:141973$5858 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$415 + connect \B \_fsm_shift + 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\_fsm_capture + connect \Y $and$libresoc.v:141981$5866_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" + cell $and $and$libresoc.v:141983$5868 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$433 + connect \B \_fsm_shift + connect \Y $and$libresoc.v:141983$5868_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" + cell $and $and$libresoc.v:141985$5870 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \_fsm_isdr + connect \B \$41 + connect \Y $and$libresoc.v:141985$5870_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" + cell $and $and$libresoc.v:141986$5871 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$437 + connect \B \_fsm_update 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$ne$libresoc.v:141984$5869 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi0_addrsr_isir + connect \B 1'0 + connect \Y $ne$libresoc.v:141984$5869_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" + cell $ne $ne$libresoc.v:141991$5876 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi0_datasr_isir + connect \B 1'0 + connect \Y $ne$libresoc.v:141991$5876_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" + cell $ne $ne$libresoc.v:141993$5878 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi0_datasr_isir + connect \B 1'0 + connect \Y $ne$libresoc.v:141993$5878_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" + cell $ne $ne$libresoc.v:141995$5880 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi0_datasr_isir + connect \B 1'0 + connect \Y $ne$libresoc.v:141995$5880_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" + cell $ne $ne$libresoc.v:142001$5886 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \sr5_isir + connect \B 1'0 + connect \Y $ne$libresoc.v:142001$5886_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" + cell $ne $ne$libresoc.v:142003$5888 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \sr5_isir + connect \B 1'0 + connect \Y $ne$libresoc.v:142003$5888_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" + cell $ne $ne$libresoc.v:142005$5890 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \sr5_isir + connect \B 1'0 + connect \Y $ne$libresoc.v:142005$5890_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + cell $not $not$libresoc.v:141955$5840 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \sr0_update_core + connect \Y $not$libresoc.v:141955$5840_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + cell $not $not$libresoc.v:141966$5851 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \jtag_wb_addrsr_update_core + connect \Y $not$libresoc.v:141966$5851_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + cell $not $not$libresoc.v:141977$5862 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \jtag_wb_datasr_update_core + connect \Y $not$libresoc.v:141977$5862_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + cell $not $not$libresoc.v:141987$5872 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi0_addrsr_update_core + connect \Y $not$libresoc.v:141987$5872_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + cell $not $not$libresoc.v:141998$5883 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi0_datasr_update_core + connect \Y $not$libresoc.v:141998$5883_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + cell $not $not$libresoc.v:142008$5893 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \sr5_update_core + connect \Y $not$libresoc.v:142008$5893_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:790" + cell $not $not$libresoc.v:142011$5896 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$484 + connect \Y $not$libresoc.v:142011$5896_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" + cell $or $or$libresoc.v:141829$5714 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$11 + connect \B \$13 + connect \Y $or$libresoc.v:141829$5714_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" + cell $or $or$libresoc.v:141874$5759 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$19 + connect \B \$21 + connect \Y $or$libresoc.v:141874$5759_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" + cell $or $or$libresoc.v:141896$5781 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$23 + connect \B \$25 + connect \Y $or$libresoc.v:141896$5781_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" + cell $or $or$libresoc.v:141943$5828 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$359 + connect \B \$361 + connect \Y $or$libresoc.v:141943$5828_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" + cell $or $or$libresoc.v:141945$5830 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$363 + connect \B \$365 + connect \Y $or$libresoc.v:141945$5830_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" + cell $or $or$libresoc.v:141951$5836 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$33 + connect \B \$35 + connect \Y $or$libresoc.v:141951$5836_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" + cell $or $or$libresoc.v:141974$5859 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$37 + connect \B \$39 + connect \Y $or$libresoc.v:141974$5859_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:791" + cell $or $or$libresoc.v:142014$5899 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$487 + connect \B \$489 + connect \Y $or$libresoc.v:142014$5899_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:523" + cell $or $or$libresoc.v:142022$5908 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$504 + connect \B \$506 + connect \Y $or$libresoc.v:142022$5908_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377" + cell $or $or$libresoc.v:142030$5916 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$1 + connect \B \$3 + connect \Y $or$libresoc.v:142030$5916_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" + cell $pos $pos$libresoc.v:142019$5905 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $extend$libresoc.v:142019$5904_Y + connect \Y $pos$libresoc.v:142019$5905_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:141797$5682 + parameter \WIDTH 1 + connect \A \gpio_e15__pad__i + connect \B \io_bd [24] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:141797$5682_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:141798$5683 + parameter \WIDTH 1 + connect \A \gpio_e15__core__o + connect \B \io_bd [25] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:141798$5683_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:141799$5684 + parameter \WIDTH 1 + connect \A \gpio_e15__core__oe + connect \B \io_bd [26] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:141799$5684_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:141800$5685 + parameter \WIDTH 1 + connect \A \gpio_s0__pad__i + connect \B \io_bd [27] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:141800$5685_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:141801$5686 + parameter \WIDTH 1 + connect \A \gpio_s0__core__o + connect \B \io_bd [28] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:141801$5686_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:141802$5687 + parameter \WIDTH 1 + connect \A \gpio_s0__core__oe + connect \B \io_bd [29] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:141802$5687_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:141803$5688 + parameter \WIDTH 1 + connect \A \gpio_s1__pad__i + connect \B \io_bd [30] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:141803$5688_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:141804$5689 + parameter \WIDTH 1 + connect \A \gpio_s1__core__o + connect \B \io_bd [31] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:141804$5689_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:141805$5690 + parameter \WIDTH 1 + connect \A \gpio_s1__core__oe + connect \B \io_bd [32] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:141805$5690_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:141806$5691 + parameter \WIDTH 1 + connect \A \gpio_s2__pad__i + connect \B \io_bd [33] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:141806$5691_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:141808$5693 + parameter \WIDTH 1 + connect \A \gpio_s2__core__o + connect \B \io_bd [34] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:141808$5693_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:141809$5694 + parameter \WIDTH 1 + connect \A \gpio_s2__core__oe + connect \B \io_bd [35] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:141809$5694_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:141810$5695 + parameter \WIDTH 1 + connect \A \gpio_s3__pad__i + connect \B \io_bd [36] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:141810$5695_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:141811$5696 + parameter \WIDTH 1 + connect \A \gpio_s3__core__o + connect \B \io_bd [37] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:141811$5696_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:141812$5697 + parameter \WIDTH 1 + connect \A \gpio_s3__core__oe + connect \B \io_bd [38] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:141812$5697_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:141813$5698 + parameter \WIDTH 1 + connect \A \gpio_s4__pad__i + connect \B \io_bd [39] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:141813$5698_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:141814$5699 + parameter \WIDTH 1 + connect \A \gpio_s4__core__o + connect \B \io_bd [40] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:141814$5699_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:141815$5700 + parameter \WIDTH 1 + connect \A \gpio_s4__core__oe + connect \B \io_bd [41] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:141815$5700_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:141816$5701 + parameter \WIDTH 1 + connect \A \gpio_s5__pad__i + connect \B \io_bd [42] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:141816$5701_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:141817$5702 + parameter \WIDTH 1 + connect \A \gpio_s5__core__o + connect \B \io_bd [43] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:141817$5702_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:141819$5704 + parameter \WIDTH 1 + connect \A \gpio_s5__core__oe + connect \B \io_bd [44] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:141819$5704_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:141820$5705 + parameter \WIDTH 1 + connect \A \gpio_s6__pad__i + connect \B \io_bd [45] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:141820$5705_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:141821$5706 + parameter \WIDTH 1 + connect \A \gpio_s6__core__o + connect \B \io_bd [46] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:141821$5706_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:141822$5707 + parameter \WIDTH 1 + connect \A \gpio_s6__core__oe + connect \B \io_bd [47] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:141822$5707_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:141823$5708 + parameter \WIDTH 1 + connect \A \gpio_s7__pad__i + connect \B \io_bd [48] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:141823$5708_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:141824$5709 + parameter \WIDTH 1 + connect \A \gpio_s7__core__o + connect \B \io_bd [49] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:141824$5709_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:141825$5710 + parameter \WIDTH 1 + connect \A \gpio_s7__core__oe + connect \B \io_bd [50] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:141825$5710_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:141826$5711 + parameter \WIDTH 1 + connect \A \mspi0_clk__core__o + connect \B \io_bd [51] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:141826$5711_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:141827$5712 + parameter \WIDTH 1 + connect \A \mspi0_cs_n__core__o + connect \B \io_bd [52] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:141827$5712_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:141828$5713 + parameter \WIDTH 1 + connect \A \mspi0_mosi__core__o + connect \B \io_bd [53] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:141828$5713_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" + cell $mux $ternary$libresoc.v:141830$5715 + parameter \WIDTH 1 + connect \A \mspi0_miso__pad__i + connect \B \io_bd [54] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:141830$5715_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:141831$5716 + parameter \WIDTH 1 + connect \A \mspi1_clk__core__o + connect \B \io_bd [55] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:141831$5716_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:141832$5717 + parameter \WIDTH 1 + connect \A \mspi1_cs_n__core__o + connect \B \io_bd [56] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:141832$5717_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:141833$5718 + parameter \WIDTH 1 + connect \A \mspi1_mosi__core__o + connect \B \io_bd [57] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:141833$5718_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" + cell $mux $ternary$libresoc.v:141834$5719 + parameter \WIDTH 1 + connect \A \mspi1_miso__pad__i + connect \B \io_bd [58] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:141834$5719_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:141835$5720 + parameter \WIDTH 1 + connect \A \mtwi_sda__pad__i + connect \B \io_bd [59] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:141835$5720_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:141836$5721 + parameter \WIDTH 1 + connect \A \mtwi_sda__core__o + connect \B \io_bd [60] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:141836$5721_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:141837$5722 + parameter \WIDTH 1 + connect \A \mtwi_sda__core__oe + connect \B \io_bd [61] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:141837$5722_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:141838$5723 + parameter \WIDTH 1 + connect \A \mtwi_scl__core__o + connect \B \io_bd [62] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:141838$5723_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:141839$5724 + parameter \WIDTH 1 + connect \A \pwm_0__core__o + connect \B \io_bd [63] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:141839$5724_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:141841$5726 + parameter \WIDTH 1 + connect \A \pwm_1__core__o + connect \B \io_bd [64] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:141841$5726_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:141842$5727 + parameter \WIDTH 1 + connect \A \sd0_cmd__pad__i + connect \B \io_bd [65] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:141842$5727_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:141843$5728 + parameter \WIDTH 1 + connect \A \sd0_cmd__core__o + connect \B \io_bd [66] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:141843$5728_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:141844$5729 + parameter \WIDTH 1 + connect \A \sd0_cmd__core__oe + connect \B \io_bd [67] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:141844$5729_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:141845$5730 + parameter \WIDTH 1 + connect \A \sd0_clk__core__o + connect \B \io_bd [68] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:141845$5730_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:141846$5731 + parameter \WIDTH 1 + connect \A \sd0_data0__pad__i + connect \B \io_bd [69] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:141846$5731_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:141847$5732 + parameter \WIDTH 1 + connect \A \sd0_data0__core__o + connect \B \io_bd [70] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:141847$5732_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:141848$5733 + parameter \WIDTH 1 + connect \A \sd0_data0__core__oe + connect \B \io_bd [71] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:141848$5733_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:141849$5734 + parameter \WIDTH 1 + connect \A \sd0_data1__pad__i + connect \B \io_bd [72] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:141849$5734_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:141850$5735 + parameter \WIDTH 1 + connect \A \sd0_data1__core__o + connect \B \io_bd [73] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:141850$5735_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:141853$5738 + parameter \WIDTH 1 + connect \A \sd0_data1__core__oe + connect \B \io_bd [74] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:141853$5738_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:141854$5739 + parameter \WIDTH 1 + connect \A \sd0_data2__pad__i + connect \B \io_bd [75] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:141854$5739_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:141855$5740 + parameter \WIDTH 1 + connect \A \sd0_data2__core__o + connect \B \io_bd [76] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:141855$5740_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:141856$5741 + parameter \WIDTH 1 + connect \A \sd0_data2__core__oe + connect \B \io_bd [77] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:141856$5741_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:141857$5742 + parameter \WIDTH 1 + connect \A \sd0_data3__pad__i + connect \B \io_bd [78] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:141857$5742_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:141858$5743 + parameter \WIDTH 1 + connect \A \sd0_data3__core__o + connect \B \io_bd [79] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:141858$5743_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:141859$5744 + parameter \WIDTH 1 + connect \A \sd0_data3__core__oe + connect \B \io_bd [80] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:141859$5744_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:141860$5745 + parameter \WIDTH 1 + connect \A \sdr_dm_0__core__o + connect \B \io_bd [81] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:141860$5745_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:141861$5746 + parameter \WIDTH 1 + connect \A \sdr_dq_0__pad__i + connect \B \io_bd [82] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:141861$5746_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:141862$5747 + parameter \WIDTH 1 + connect \A \sdr_dq_0__core__o + connect \B \io_bd [83] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:141862$5747_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:141864$5749 + parameter \WIDTH 1 + connect \A \sdr_dq_0__core__oe + connect \B \io_bd [84] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:141864$5749_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:141865$5750 + parameter \WIDTH 1 + connect \A \sdr_dq_1__pad__i + connect \B \io_bd [85] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:141865$5750_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:141866$5751 + parameter \WIDTH 1 + connect \A \sdr_dq_1__core__o + connect \B \io_bd [86] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:141866$5751_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:141867$5752 + parameter \WIDTH 1 + connect \A \sdr_dq_1__core__oe + connect \B \io_bd [87] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:141867$5752_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:141868$5753 + parameter \WIDTH 1 + connect \A \sdr_dq_2__pad__i + connect \B \io_bd [88] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:141868$5753_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:141869$5754 + parameter \WIDTH 1 + connect \A \sdr_dq_2__core__o + connect \B \io_bd [89] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:141869$5754_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:141870$5755 + parameter \WIDTH 1 + connect \A \sdr_dq_2__core__oe + connect \B \io_bd [90] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:141870$5755_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:141871$5756 + parameter \WIDTH 1 + connect \A \sdr_dq_3__pad__i + connect \B \io_bd [91] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:141871$5756_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:141872$5757 + parameter \WIDTH 1 + connect \A \sdr_dq_3__core__o + connect \B \io_bd [92] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:141872$5757_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:141873$5758 + parameter \WIDTH 1 + connect \A \sdr_dq_3__core__oe + connect \B \io_bd [93] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:141873$5758_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:141875$5760 + parameter \WIDTH 1 + connect \A \sdr_dq_4__pad__i + connect \B \io_bd [94] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:141875$5760_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:141876$5761 + parameter \WIDTH 1 + connect \A \sdr_dq_4__core__o + connect \B \io_bd [95] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:141876$5761_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:141877$5762 + parameter \WIDTH 1 + connect \A \sdr_dq_4__core__oe + connect \B \io_bd [96] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:141877$5762_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:141878$5763 + parameter \WIDTH 1 + connect \A \sdr_dq_5__pad__i + connect \B \io_bd [97] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:141878$5763_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:141879$5764 + parameter \WIDTH 1 + connect \A \sdr_dq_5__core__o + connect \B \io_bd [98] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:141879$5764_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:141880$5765 + parameter \WIDTH 1 + connect \A \sdr_dq_5__core__oe + connect \B \io_bd [99] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:141880$5765_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:141881$5766 + parameter \WIDTH 1 + connect \A \sdr_dq_6__pad__i + connect \B \io_bd [100] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:141881$5766_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:141882$5767 + parameter \WIDTH 1 + connect \A \sdr_dq_6__core__o + connect \B \io_bd [101] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:141882$5767_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:141883$5768 + parameter \WIDTH 1 + connect \A \sdr_dq_6__core__oe + connect \B \io_bd [102] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:141883$5768_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:141884$5769 + parameter \WIDTH 1 + connect \A \sdr_dq_7__pad__i + connect \B \io_bd [103] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:141884$5769_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:141886$5771 + parameter \WIDTH 1 + connect \A \sdr_dq_7__core__o + connect \B \io_bd [104] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:141886$5771_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:141887$5772 + parameter \WIDTH 1 + connect \A \sdr_dq_7__core__oe + connect \B \io_bd [105] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:141887$5772_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:141888$5773 + parameter \WIDTH 1 + connect \A \sdr_a_0__core__o + connect \B \io_bd [106] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:141888$5773_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:141889$5774 + parameter \WIDTH 1 + connect \A \sdr_a_1__core__o + connect \B \io_bd [107] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:141889$5774_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:141890$5775 + parameter \WIDTH 1 + connect \A \sdr_a_2__core__o + connect \B \io_bd [108] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:141890$5775_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:141891$5776 + parameter \WIDTH 1 + connect \A \sdr_a_3__core__o + connect \B \io_bd [109] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:141891$5776_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:141892$5777 + parameter \WIDTH 1 + connect \A \sdr_a_4__core__o + connect \B \io_bd [110] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:141892$5777_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:141893$5778 + parameter \WIDTH 1 + connect \A \sdr_a_5__core__o + connect \B \io_bd [111] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:141893$5778_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:141894$5779 + parameter \WIDTH 1 + connect \A \sdr_a_6__core__o + connect \B \io_bd [112] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:141894$5779_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:141895$5780 + parameter \WIDTH 1 + connect \A \sdr_a_7__core__o + connect \B \io_bd [113] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:141895$5780_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:141897$5782 + parameter \WIDTH 1 + connect \A \sdr_a_8__core__o + connect \B \io_bd [114] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:141897$5782_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:141898$5783 + parameter \WIDTH 1 + connect \A \sdr_a_9__core__o + connect \B \io_bd [115] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:141898$5783_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:141899$5784 + parameter \WIDTH 1 + connect \A \sdr_ba_0__core__o + connect \B \io_bd [116] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:141899$5784_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:141900$5785 + parameter \WIDTH 1 + connect \A \sdr_ba_1__core__o + connect \B \io_bd [117] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:141900$5785_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:141901$5786 + parameter \WIDTH 1 + connect \A \sdr_clock__core__o + connect \B \io_bd [118] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:141901$5786_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:141902$5787 + parameter \WIDTH 1 + connect \A \sdr_cke__core__o + connect \B \io_bd [119] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:141902$5787_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:141903$5788 + parameter \WIDTH 1 + connect \A \sdr_ras_n__core__o + connect \B \io_bd [120] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:141903$5788_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:141904$5789 + parameter \WIDTH 1 + connect \A \sdr_cas_n__core__o + connect \B \io_bd [121] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:141904$5789_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:141905$5790 + parameter \WIDTH 1 + connect \A \sdr_we_n__core__o + connect \B \io_bd [122] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:141905$5790_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:141906$5791 + parameter \WIDTH 1 + connect \A \sdr_cs_n__core__o + connect \B \io_bd [123] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:141906$5791_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:141908$5793 + parameter \WIDTH 1 + connect \A \sdr_a_10__core__o + connect \B \io_bd [124] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:141908$5793_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:141909$5794 + parameter \WIDTH 1 + connect \A \sdr_a_11__core__o + connect \B \io_bd [125] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:141909$5794_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + cell $mux $ternary$libresoc.v:141910$5795 + parameter \WIDTH 1 + connect \A \sdr_a_12__core__o + connect \B \io_bd [126] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:141910$5795_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:141911$5796 + parameter \WIDTH 1 + connect \A \sdr_dm_1__pad__i + connect \B \io_bd [127] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:141911$5796_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:141912$5797 + parameter \WIDTH 1 + connect \A \sdr_dm_1__core__o + connect \B \io_bd [128] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:141912$5797_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:141913$5798 + parameter \WIDTH 1 + connect \A \sdr_dm_1__core__oe + connect \B \io_bd [129] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:141913$5798_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:141914$5799 + parameter \WIDTH 1 + connect \A \sdr_dq_8__pad__i + connect \B \io_bd [130] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:141914$5799_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:141915$5800 + parameter \WIDTH 1 + connect \A \sdr_dq_8__core__o + connect \B \io_bd [131] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:141915$5800_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:141916$5801 + parameter \WIDTH 1 + connect \A \sdr_dq_8__core__oe + connect \B \io_bd [132] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:141916$5801_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:141917$5802 + parameter \WIDTH 1 + connect \A \sdr_dq_9__pad__i + connect \B \io_bd [133] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:141917$5802_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:141919$5804 + parameter \WIDTH 1 + connect \A \sdr_dq_9__core__o + connect \B \io_bd [134] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:141919$5804_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:141920$5805 + parameter \WIDTH 1 + connect \A \sdr_dq_9__core__oe + connect \B \io_bd [135] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:141920$5805_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:141921$5806 + parameter \WIDTH 1 + connect \A \sdr_dq_10__pad__i + connect \B \io_bd [136] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:141921$5806_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:141922$5807 + parameter \WIDTH 1 + connect \A \sdr_dq_10__core__o + connect \B \io_bd [137] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:141922$5807_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:141923$5808 + parameter \WIDTH 1 + connect \A \sdr_dq_10__core__oe + connect \B \io_bd [138] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:141923$5808_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:141924$5809 + parameter \WIDTH 1 + connect \A \sdr_dq_11__pad__i + connect \B \io_bd [139] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:141924$5809_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:141925$5810 + parameter \WIDTH 1 + connect \A \sdr_dq_11__core__o + connect \B \io_bd [140] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:141925$5810_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:141926$5811 + parameter \WIDTH 1 + connect \A \sdr_dq_11__core__oe + connect \B \io_bd [141] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:141926$5811_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:141927$5812 + parameter \WIDTH 1 + connect \A \sdr_dq_12__pad__i + connect \B \io_bd [142] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:141927$5812_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:141928$5813 + parameter \WIDTH 1 + connect \A \sdr_dq_12__core__o + connect \B \io_bd [143] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:141928$5813_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:141930$5815 + parameter \WIDTH 1 + connect \A \sdr_dq_12__core__oe + connect \B \io_bd [144] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:141930$5815_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:141931$5816 + parameter \WIDTH 1 + connect \A \sdr_dq_13__pad__i + connect \B \io_bd [145] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:141931$5816_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:141932$5817 + parameter \WIDTH 1 + connect \A \sdr_dq_13__core__o + connect \B \io_bd [146] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:141932$5817_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:141933$5818 + parameter \WIDTH 1 + connect \A \sdr_dq_13__core__oe + connect \B \io_bd [147] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:141933$5818_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:141934$5819 + parameter \WIDTH 1 + connect \A \sdr_dq_14__pad__i + connect \B \io_bd [148] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:141934$5819_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:141935$5820 + parameter \WIDTH 1 + connect \A \sdr_dq_14__core__o + connect \B \io_bd [149] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:141935$5820_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:141936$5821 + parameter \WIDTH 1 + connect \A \sdr_dq_14__core__oe + connect \B \io_bd [150] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:141936$5821_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:141937$5822 + parameter \WIDTH 1 + connect \A \sdr_dq_15__pad__i + connect \B \io_bd [151] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:141937$5822_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:141938$5823 + parameter \WIDTH 1 + connect \A \sdr_dq_15__core__o + connect \B \io_bd [152] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:141938$5823_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:141939$5824 + parameter \WIDTH 1 + connect \A \sdr_dq_15__core__oe + connect \B \io_bd [153] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:141939$5824_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" + cell $mux $ternary$libresoc.v:142026$5912 + parameter \WIDTH 1 + connect \A \eint_0__pad__i + connect \B \io_bd [0] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:142026$5912_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" + cell $mux $ternary$libresoc.v:142027$5913 + parameter \WIDTH 1 + connect \A \eint_1__pad__i + connect \B \io_bd [1] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:142027$5913_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" + cell $mux $ternary$libresoc.v:142028$5914 + parameter \WIDTH 1 + connect \A \eint_2__pad__i + connect \B \io_bd [2] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:142028$5914_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:142029$5915 + parameter \WIDTH 1 + connect \A \gpio_e8__pad__i + connect \B \io_bd [3] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:142029$5915_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:142031$5917 + parameter \WIDTH 1 + connect \A \gpio_e8__core__o + connect \B \io_bd [4] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:142031$5917_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:142032$5918 + parameter \WIDTH 1 + connect \A \gpio_e8__core__oe + connect \B \io_bd [5] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:142032$5918_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:142033$5919 + parameter \WIDTH 1 + connect \A \gpio_e9__pad__i + connect \B \io_bd [6] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:142033$5919_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:142034$5920 + parameter \WIDTH 1 + connect \A \gpio_e9__core__o + connect \B \io_bd [7] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:142034$5920_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:142035$5921 + parameter \WIDTH 1 + connect \A \gpio_e9__core__oe + connect \B \io_bd [8] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:142035$5921_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:142036$5922 + parameter \WIDTH 1 + connect \A \gpio_e10__pad__i + connect \B \io_bd [9] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:142036$5922_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:142037$5923 + parameter \WIDTH 1 + connect \A \gpio_e10__core__o + connect \B \io_bd [10] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:142037$5923_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:142038$5924 + parameter \WIDTH 1 + connect \A \gpio_e10__core__oe + connect \B \io_bd [11] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:142038$5924_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:142039$5925 + parameter \WIDTH 1 + connect \A \gpio_e11__pad__i + connect \B \io_bd [12] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:142039$5925_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:142040$5926 + parameter \WIDTH 1 + connect \A \gpio_e11__core__o + connect \B \io_bd [13] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:142040$5926_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:142042$5928 + parameter \WIDTH 1 + connect \A \gpio_e11__core__oe + connect \B \io_bd [14] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:142042$5928_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:142043$5929 + parameter \WIDTH 1 + connect \A \gpio_e12__pad__i + connect \B \io_bd [15] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:142043$5929_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:142044$5930 + parameter \WIDTH 1 + connect \A \gpio_e12__core__o + connect \B \io_bd [16] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:142044$5930_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:142045$5931 + parameter \WIDTH 1 + connect \A \gpio_e12__core__oe + connect \B \io_bd [17] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:142045$5931_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:142046$5932 + parameter \WIDTH 1 + connect \A \gpio_e13__pad__i + connect \B \io_bd [18] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:142046$5932_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:142047$5933 + parameter \WIDTH 1 + connect \A \gpio_e13__core__o + connect \B \io_bd [19] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:142047$5933_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:142048$5934 + parameter \WIDTH 1 + connect \A \gpio_e13__core__oe + connect \B \io_bd [20] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:142048$5934_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + cell $mux $ternary$libresoc.v:142049$5935 + parameter \WIDTH 1 + connect \A \gpio_e14__pad__i + connect \B \io_bd [21] + connect \S \io_bd2core + connect \Y $ternary$libresoc.v:142049$5935_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + cell $mux $ternary$libresoc.v:142050$5936 + parameter \WIDTH 1 + connect \A \gpio_e14__core__o + connect \B \io_bd [22] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:142050$5936_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + cell $mux $ternary$libresoc.v:142051$5937 + parameter \WIDTH 1 + connect \A \gpio_e14__core__oe + connect \B \io_bd [23] + connect \S \io_bd2io + connect \Y $ternary$libresoc.v:142051$5937_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:142124.8-142136.4" + cell \_fsm \_fsm + connect \TAP_bus__tck \TAP_bus__tck + connect \TAP_bus__tms \TAP_bus__tms + connect \capture \_fsm_capture + connect \isdr \_fsm_isdr + connect \isir \_fsm_isir + connect \negjtag_clk \negjtag_clk + connect \negjtag_rst \negjtag_rst + connect \posjtag_clk \posjtag_clk + connect \posjtag_rst \posjtag_rst + connect \shift \_fsm_shift + connect \update \_fsm_update + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:142137.12-142147.4" + cell \_idblock \_idblock + connect \TAP_bus__tdi \TAP_bus__tdi + connect \TAP_id_tdo \_idblock_TAP_id_tdo + connect \capture \_fsm_capture + connect \id_bypass \_idblock_id_bypass + connect \posjtag_clk \posjtag_clk + connect \posjtag_rst \posjtag_rst + connect \select_id \_idblock_select_id + connect \shift \_fsm_shift + connect \update \_fsm_update + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:142148.12-142158.4" + cell \_irblock \_irblock + connect \TAP_bus__tdi \TAP_bus__tdi + connect \capture \_fsm_capture + connect \ir \_irblock_ir + connect \isir \_fsm_isir + connect \posjtag_clk \posjtag_clk + connect \posjtag_rst \posjtag_rst + connect \shift \_fsm_shift + connect \tdo \_irblock_tdo + connect \update \_fsm_update + end + attribute \src "libresoc.v:140366.7-140366.20" + process $proc$libresoc.v:140366$6129 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:140924.13-140924.32" + process $proc$libresoc.v:140924$6130 + assign { } { } + assign $1\dmi0__addr_i[3:0] 4'0000 + sync always + sync init + update \dmi0__addr_i $1\dmi0__addr_i[3:0] + end + attribute \src "libresoc.v:140929.14-140929.46" + process $proc$libresoc.v:140929$6131 + assign { } { } + assign $1\dmi0__din[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \dmi0__din $1\dmi0__din[63:0] + end + attribute \src "libresoc.v:140943.7-140943.29" + process $proc$libresoc.v:140943$6132 + assign { } { } + assign $1\dmi0_addrsr__oe[0:0] 1'0 + sync always + sync init + update \dmi0_addrsr__oe $1\dmi0_addrsr__oe[0:0] + end + attribute \src "libresoc.v:140951.13-140951.36" + process $proc$libresoc.v:140951$6133 + assign { } { } + assign $1\dmi0_addrsr_reg[7:0] 8'00000000 + sync always + sync init + update \dmi0_addrsr_reg $1\dmi0_addrsr_reg[7:0] + end + attribute \src "libresoc.v:140959.7-140959.37" + process $proc$libresoc.v:140959$6134 + assign { } { } + assign $1\dmi0_addrsr_update_core[0:0] 1'0 + sync always + sync init + update \dmi0_addrsr_update_core $1\dmi0_addrsr_update_core[0:0] + end + attribute \src "libresoc.v:140963.7-140963.42" + process $proc$libresoc.v:140963$6135 + assign { } { } + assign $1\dmi0_addrsr_update_core_prev[0:0] 1'0 + sync always + sync init + update \dmi0_addrsr_update_core_prev $1\dmi0_addrsr_update_core_prev[0:0] + end + attribute \src "libresoc.v:140967.14-140967.51" + process $proc$libresoc.v:140967$6136 + assign { } { } + assign $1\dmi0_datasr__i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \dmi0_datasr__i $1\dmi0_datasr__i[63:0] + end + attribute \src "libresoc.v:140973.13-140973.35" + process $proc$libresoc.v:140973$6137 + assign { } { } + assign $1\dmi0_datasr__oe[1:0] 2'00 + sync always + sync init + update \dmi0_datasr__oe $1\dmi0_datasr__oe[1:0] + end + attribute \src "libresoc.v:140981.14-140981.52" + process $proc$libresoc.v:140981$6138 + assign { } { } + assign $1\dmi0_datasr_reg[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \dmi0_datasr_reg $1\dmi0_datasr_reg[63:0] + end + attribute \src "libresoc.v:140989.7-140989.37" + process $proc$libresoc.v:140989$6139 + assign { } { } + assign $1\dmi0_datasr_update_core[0:0] 1'0 + sync always + sync init + update \dmi0_datasr_update_core $1\dmi0_datasr_update_core[0:0] + end + attribute \src "libresoc.v:140993.7-140993.42" + process $proc$libresoc.v:140993$6140 + assign { } { } + assign $1\dmi0_datasr_update_core_prev[0:0] 1'0 + sync always + sync init + update \dmi0_datasr_update_core_prev $1\dmi0_datasr_update_core_prev[0:0] + end + attribute \src "libresoc.v:141009.13-141009.29" + process $proc$libresoc.v:141009$6141 + assign { } { } + assign $1\fsm_state[2:0] 3'000 + sync always + sync init + update \fsm_state $1\fsm_state[2:0] + end + attribute \src "libresoc.v:141011.13-141011.35" + process $proc$libresoc.v:141011$6142 + assign { } { } + assign $0\fsm_state$503[2:0]$6143 3'000 + sync always + sync init + update \fsm_state$503 $0\fsm_state$503[2:0]$6143 + end + attribute \src "libresoc.v:141209.15-141209.67" + process $proc$libresoc.v:141209$6144 + assign { } { } + assign $1\io_bd[153:0] 154'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \io_bd $1\io_bd[153:0] + end + attribute \src "libresoc.v:141221.15-141221.67" + process $proc$libresoc.v:141221$6145 + assign { } { } + assign $1\io_sr[153:0] 154'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \io_sr $1\io_sr[153:0] + end + attribute \src "libresoc.v:141230.14-141230.41" + process $proc$libresoc.v:141230$6146 + assign { } { } + assign $1\jtag_wb__adr[28:0] 29'00000000000000000000000000000 + sync always + sync init + update \jtag_wb__adr $1\jtag_wb__adr[28:0] + end + attribute \src "libresoc.v:141239.14-141239.51" + process $proc$libresoc.v:141239$6147 + assign { } { } + assign $1\jtag_wb__dat_w[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \jtag_wb__dat_w $1\jtag_wb__dat_w[63:0] + end + attribute \src "libresoc.v:141253.7-141253.32" + process $proc$libresoc.v:141253$6148 + assign { } { } + assign $1\jtag_wb_addrsr__oe[0:0] 1'0 + sync always + sync init + update \jtag_wb_addrsr__oe $1\jtag_wb_addrsr__oe[0:0] + end + attribute \src "libresoc.v:141261.14-141261.47" + process $proc$libresoc.v:141261$6149 + assign { } { } + assign $1\jtag_wb_addrsr_reg[28:0] 29'00000000000000000000000000000 + sync always + sync init + update \jtag_wb_addrsr_reg $1\jtag_wb_addrsr_reg[28:0] + end + attribute \src "libresoc.v:141269.7-141269.40" + process $proc$libresoc.v:141269$6150 + assign { } { } + assign $1\jtag_wb_addrsr_update_core[0:0] 1'0 + sync always + sync init + update \jtag_wb_addrsr_update_core $1\jtag_wb_addrsr_update_core[0:0] + end + attribute \src "libresoc.v:141273.7-141273.45" + process $proc$libresoc.v:141273$6151 + assign { } { } + assign $1\jtag_wb_addrsr_update_core_prev[0:0] 1'0 + sync always + sync init + update \jtag_wb_addrsr_update_core_prev $1\jtag_wb_addrsr_update_core_prev[0:0] + end + attribute \src "libresoc.v:141277.14-141277.54" + process $proc$libresoc.v:141277$6152 + assign { } { } + assign $1\jtag_wb_datasr__i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \jtag_wb_datasr__i $1\jtag_wb_datasr__i[63:0] + end + attribute \src "libresoc.v:141283.13-141283.38" + process $proc$libresoc.v:141283$6153 + assign { } { } + assign $1\jtag_wb_datasr__oe[1:0] 2'00 + sync always + sync init + update \jtag_wb_datasr__oe $1\jtag_wb_datasr__oe[1:0] + end + attribute \src "libresoc.v:141291.14-141291.55" + process $proc$libresoc.v:141291$6154 + assign { } { } + assign $1\jtag_wb_datasr_reg[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \jtag_wb_datasr_reg $1\jtag_wb_datasr_reg[63:0] + end + attribute \src "libresoc.v:141299.7-141299.40" + process $proc$libresoc.v:141299$6155 + assign { } { } + assign $1\jtag_wb_datasr_update_core[0:0] 1'0 + sync always + sync init + update \jtag_wb_datasr_update_core $1\jtag_wb_datasr_update_core[0:0] + end + attribute \src "libresoc.v:141303.7-141303.45" + process $proc$libresoc.v:141303$6156 + assign { } { } + assign $1\jtag_wb_datasr_update_core_prev[0:0] 1'0 + sync always + sync init + update \jtag_wb_datasr_update_core_prev $1\jtag_wb_datasr_update_core_prev[0:0] + end + attribute \src "libresoc.v:141733.7-141733.21" + process $proc$libresoc.v:141733$6157 + assign { } { } + assign $1\sr0__oe[0:0] 1'0 + sync always + sync init + update \sr0__oe $1\sr0__oe[0:0] + end + attribute \src "libresoc.v:141741.13-141741.27" + process $proc$libresoc.v:141741$6158 + assign { } { } + assign $1\sr0_reg[2:0] 3'000 + sync always + sync init + update \sr0_reg $1\sr0_reg[2:0] + end + attribute \src "libresoc.v:141749.7-141749.29" + process $proc$libresoc.v:141749$6159 + assign { } { } + assign $1\sr0_update_core[0:0] 1'0 + sync always + sync init + update \sr0_update_core $1\sr0_update_core[0:0] + end + attribute \src "libresoc.v:141753.7-141753.34" + process $proc$libresoc.v:141753$6160 + assign { } { } + assign $1\sr0_update_core_prev[0:0] 1'0 + sync always + sync init + update \sr0_update_core_prev $1\sr0_update_core_prev[0:0] + end + attribute \src "libresoc.v:141763.7-141763.21" + process $proc$libresoc.v:141763$6161 + assign { } { } + assign $1\sr5__oe[0:0] 1'0 + sync always + sync init + update \sr5__oe $1\sr5__oe[0:0] + end + attribute \src "libresoc.v:141771.13-141771.27" + process $proc$libresoc.v:141771$6162 + assign { } { } + assign $1\sr5_reg[1:0] 2'00 + sync always + sync init + update \sr5_reg $1\sr5_reg[1:0] + end + attribute \src "libresoc.v:141779.7-141779.29" + process $proc$libresoc.v:141779$6163 + assign { } { } + assign $1\sr5_update_core[0:0] 1'0 + sync always + sync init + update \sr5_update_core $1\sr5_update_core[0:0] + end + attribute \src "libresoc.v:141783.7-141783.34" + process $proc$libresoc.v:141783$6164 + assign { } { } + assign $1\sr5_update_core_prev[0:0] 1'0 + sync always + sync init + update \sr5_update_core_prev $1\sr5_update_core_prev[0:0] + end + attribute \src "libresoc.v:141788.7-141788.26" + process $proc$libresoc.v:141788$6165 + assign { } { } + assign $1\wb_dcache_en[0:0] 1'1 + sync always + sync init + update \wb_dcache_en $1\wb_dcache_en[0:0] + end + attribute \src "libresoc.v:141793.7-141793.26" + process $proc$libresoc.v:141793$6166 + assign { } { } + assign $1\wb_icache_en[0:0] 1'1 + sync always + sync init + update \wb_icache_en $1\wb_icache_en[0:0] + end + attribute \src "libresoc.v:142052.3-142053.41" + process $proc$libresoc.v:142052$5938 + assign { } { } + assign $0\wb_icache_en[0:0] \wb_icache_en$next + sync posedge \clk + update \wb_icache_en $0\wb_icache_en[0:0] + end + attribute \src "libresoc.v:142054.3-142055.41" + process $proc$libresoc.v:142054$5939 + assign { } { } + assign $0\wb_dcache_en[0:0] \wb_dcache_en$next + sync posedge \clk + update \wb_dcache_en $0\wb_dcache_en[0:0] + end + attribute \src "libresoc.v:142056.3-142057.45" + process $proc$libresoc.v:142056$5940 + assign { } { } + assign $0\dmi0_datasr__i[63:0] \dmi0_datasr__i$next + sync posedge \clk + update \dmi0_datasr__i $0\dmi0_datasr__i[63:0] + end + attribute \src "libresoc.v:142058.3-142059.35" + process $proc$libresoc.v:142058$5941 + assign { } { } + assign $0\dmi0__din[63:0] \dmi0__din$next + sync posedge \clk + update \dmi0__din $0\dmi0__din[63:0] + end + attribute \src "libresoc.v:142060.3-142061.45" + process $proc$libresoc.v:142060$5942 + assign { } { } + assign $0\fsm_state$503[2:0]$5943 \fsm_state$503$next + sync posedge \clk + update \fsm_state$503 $0\fsm_state$503[2:0]$5943 + end + attribute \src "libresoc.v:142062.3-142063.41" + process $proc$libresoc.v:142062$5944 + assign { } { } + assign $0\dmi0__addr_i[3:0] \dmi0__addr_i$next + sync posedge \clk + update \dmi0__addr_i $0\dmi0__addr_i[3:0] + end + attribute \src "libresoc.v:142064.3-142065.51" + process $proc$libresoc.v:142064$5945 + assign { } { } + assign $0\jtag_wb_datasr__i[63:0] \jtag_wb_datasr__i$next + sync posedge \clk + update \jtag_wb_datasr__i $0\jtag_wb_datasr__i[63:0] + end + attribute \src "libresoc.v:142066.3-142067.45" + process $proc$libresoc.v:142066$5946 + assign { } { } + assign $0\jtag_wb__dat_w[63:0] \jtag_wb__dat_w$next + sync posedge \clk + update \jtag_wb__dat_w $0\jtag_wb__dat_w[63:0] + end + attribute \src "libresoc.v:142068.3-142069.35" + process $proc$libresoc.v:142068$5947 + assign { } { } + assign $0\fsm_state[2:0] \fsm_state$next + sync posedge \clk + update \fsm_state $0\fsm_state[2:0] + end + attribute \src "libresoc.v:142070.3-142071.41" + process $proc$libresoc.v:142070$5948 + assign { } { } + assign $0\jtag_wb__adr[28:0] \jtag_wb__adr$next + sync posedge \clk + update \jtag_wb__adr $0\jtag_wb__adr[28:0] + end + attribute \src "libresoc.v:142072.3-142073.31" + process $proc$libresoc.v:142072$5949 + assign { } { } + assign $0\sr5_reg[1:0] \sr5_reg$next + sync posedge \posjtag_clk + update \sr5_reg $0\sr5_reg[1:0] + end + attribute \src "libresoc.v:142074.3-142075.31" + process $proc$libresoc.v:142074$5950 + assign { } { } + assign $0\sr5__oe[0:0] \sr5__oe$next + sync posedge \clk + update \sr5__oe $0\sr5__oe[0:0] + end + attribute \src "libresoc.v:142076.3-142077.57" + process $proc$libresoc.v:142076$5951 + assign { } { } + assign $0\sr5_update_core_prev[0:0] \sr5_update_core_prev$next + sync posedge \clk + update \sr5_update_core_prev $0\sr5_update_core_prev[0:0] + end + attribute \src "libresoc.v:142078.3-142079.47" + process $proc$libresoc.v:142078$5952 + assign { } { } + assign $0\sr5_update_core[0:0] \sr5_update_core$next + sync posedge \clk + update \sr5_update_core $0\sr5_update_core[0:0] + end + attribute \src "libresoc.v:142080.3-142081.47" + process $proc$libresoc.v:142080$5953 + assign { } { } + assign $0\dmi0_datasr_reg[63:0] \dmi0_datasr_reg$next + sync posedge \posjtag_clk + update \dmi0_datasr_reg $0\dmi0_datasr_reg[63:0] + end + attribute \src "libresoc.v:142082.3-142083.47" + process $proc$libresoc.v:142082$5954 + assign { } { } + assign $0\dmi0_datasr__oe[1:0] \dmi0_datasr__oe$next + sync posedge \clk + update \dmi0_datasr__oe $0\dmi0_datasr__oe[1:0] + end + attribute \src "libresoc.v:142084.3-142085.73" + process $proc$libresoc.v:142084$5955 + assign { } { } + assign $0\dmi0_datasr_update_core_prev[0:0] \dmi0_datasr_update_core_prev$next + sync posedge \clk + update \dmi0_datasr_update_core_prev $0\dmi0_datasr_update_core_prev[0:0] + end + attribute \src "libresoc.v:142086.3-142087.63" + process $proc$libresoc.v:142086$5956 + assign { } { } + assign $0\dmi0_datasr_update_core[0:0] \dmi0_datasr_update_core$next + sync posedge \clk + update \dmi0_datasr_update_core $0\dmi0_datasr_update_core[0:0] + end + attribute \src "libresoc.v:142088.3-142089.47" + process $proc$libresoc.v:142088$5957 + assign { } { } + assign $0\dmi0_addrsr_reg[7:0] \dmi0_addrsr_reg$next + sync posedge \posjtag_clk + update \dmi0_addrsr_reg $0\dmi0_addrsr_reg[7:0] + end + attribute \src "libresoc.v:142090.3-142091.47" + process $proc$libresoc.v:142090$5958 + assign { } { } + assign $0\dmi0_addrsr__oe[0:0] \dmi0_addrsr__oe$next + sync posedge \clk + update \dmi0_addrsr__oe $0\dmi0_addrsr__oe[0:0] + end + attribute \src "libresoc.v:142092.3-142093.73" + process $proc$libresoc.v:142092$5959 + assign { } { } + assign $0\dmi0_addrsr_update_core_prev[0:0] \dmi0_addrsr_update_core_prev$next + sync posedge \clk + update \dmi0_addrsr_update_core_prev $0\dmi0_addrsr_update_core_prev[0:0] + end + attribute \src "libresoc.v:142094.3-142095.63" + process $proc$libresoc.v:142094$5960 + assign { } { } + assign $0\dmi0_addrsr_update_core[0:0] \dmi0_addrsr_update_core$next + sync posedge \clk + update \dmi0_addrsr_update_core $0\dmi0_addrsr_update_core[0:0] + end + attribute \src "libresoc.v:142096.3-142097.53" + process $proc$libresoc.v:142096$5961 + assign { } { } + assign $0\jtag_wb_datasr_reg[63:0] \jtag_wb_datasr_reg$next + sync posedge \posjtag_clk + update \jtag_wb_datasr_reg $0\jtag_wb_datasr_reg[63:0] + end + attribute \src "libresoc.v:142098.3-142099.53" + process $proc$libresoc.v:142098$5962 + assign { } { } + assign $0\jtag_wb_datasr__oe[1:0] \jtag_wb_datasr__oe$next + sync posedge \clk + update \jtag_wb_datasr__oe $0\jtag_wb_datasr__oe[1:0] + end + attribute \src "libresoc.v:142100.3-142101.79" + process $proc$libresoc.v:142100$5963 + assign { } { } + assign $0\jtag_wb_datasr_update_core_prev[0:0] \jtag_wb_datasr_update_core_prev$next + sync posedge \clk + update \jtag_wb_datasr_update_core_prev $0\jtag_wb_datasr_update_core_prev[0:0] + end + attribute \src "libresoc.v:142102.3-142103.69" + process $proc$libresoc.v:142102$5964 + assign { } { } + assign $0\jtag_wb_datasr_update_core[0:0] \jtag_wb_datasr_update_core$next + sync posedge \clk + update \jtag_wb_datasr_update_core $0\jtag_wb_datasr_update_core[0:0] + end + attribute \src "libresoc.v:142104.3-142105.53" + process $proc$libresoc.v:142104$5965 + assign { } { } + assign $0\jtag_wb_addrsr_reg[28:0] \jtag_wb_addrsr_reg$next + sync posedge \posjtag_clk + update \jtag_wb_addrsr_reg $0\jtag_wb_addrsr_reg[28:0] + end + attribute \src "libresoc.v:142106.3-142107.53" + process $proc$libresoc.v:142106$5966 + assign { } { } + assign $0\jtag_wb_addrsr__oe[0:0] \jtag_wb_addrsr__oe$next + sync posedge \clk + update \jtag_wb_addrsr__oe $0\jtag_wb_addrsr__oe[0:0] + end + attribute \src "libresoc.v:142108.3-142109.79" + process $proc$libresoc.v:142108$5967 + assign { } { } + assign $0\jtag_wb_addrsr_update_core_prev[0:0] \jtag_wb_addrsr_update_core_prev$next + sync posedge \clk + update \jtag_wb_addrsr_update_core_prev $0\jtag_wb_addrsr_update_core_prev[0:0] + end + attribute \src "libresoc.v:142110.3-142111.69" + process $proc$libresoc.v:142110$5968 + assign { } { } + assign $0\jtag_wb_addrsr_update_core[0:0] \jtag_wb_addrsr_update_core$next + sync posedge \clk + update \jtag_wb_addrsr_update_core $0\jtag_wb_addrsr_update_core[0:0] + end + attribute \src "libresoc.v:142112.3-142113.31" + process $proc$libresoc.v:142112$5969 + assign { } { } + assign $0\sr0_reg[2:0] \sr0_reg$next + sync posedge \posjtag_clk + update \sr0_reg $0\sr0_reg[2:0] + end + attribute \src "libresoc.v:142114.3-142115.31" + process $proc$libresoc.v:142114$5970 + assign { } { } + assign $0\sr0__oe[0:0] \sr0__oe$next + sync posedge \clk + update \sr0__oe $0\sr0__oe[0:0] + end + attribute \src "libresoc.v:142116.3-142117.57" + process $proc$libresoc.v:142116$5971 + assign { } { } + assign $0\sr0_update_core_prev[0:0] \sr0_update_core_prev$next + sync posedge \clk + update \sr0_update_core_prev $0\sr0_update_core_prev[0:0] + end + attribute \src "libresoc.v:142118.3-142119.47" + process $proc$libresoc.v:142118$5972 + assign { } { } + assign $0\sr0_update_core[0:0] \sr0_update_core$next + sync posedge \clk + update \sr0_update_core $0\sr0_update_core[0:0] + end + attribute \src "libresoc.v:142120.3-142121.27" + process $proc$libresoc.v:142120$5973 + assign { } { } + assign $0\io_bd[153:0] \io_bd$next + sync negedge \negjtag_clk + update \io_bd $0\io_bd[153:0] + end + attribute \src "libresoc.v:142122.3-142123.27" + process $proc$libresoc.v:142122$5974 + assign { } { } + assign $0\io_sr[153:0] \io_sr$next + sync posedge \posjtag_clk + update \io_sr $0\io_sr[153:0] + end + attribute \src "libresoc.v:142159.3-142174.6" + process $proc$libresoc.v:142159$5975 + assign { } { } + assign { } { } + assign $0\TAP_tdo[0:0] $1\TAP_tdo[0:0] + attribute \src "libresoc.v:142160.5-142160.29" + switch \initial + attribute \src "libresoc.v:142160.9-142160.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:415" + switch { \$369 \_idblock_select_id \_fsm_isir } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign { } { } + assign $1\TAP_tdo[0:0] \_irblock_tdo + attribute \src "libresoc.v:0.0-0.0" + case 3'-1- + assign { } { } + assign $1\TAP_tdo[0:0] \_idblock_TAP_id_tdo + attribute \src "libresoc.v:0.0-0.0" + case 3'1-- + assign { } { } + assign $1\TAP_tdo[0:0] \io_sr [153] + case + assign $1\TAP_tdo[0:0] 1'0 + end + sync always + update \TAP_tdo $0\TAP_tdo[0:0] + end + attribute \src "libresoc.v:142175.3-142183.6" + process $proc$libresoc.v:142175$5976 + assign { } { } + assign { } { } + assign $0\sr0_update_core$next[0:0]$5977 $1\sr0_update_core$next[0:0]$5978 + attribute \src "libresoc.v:142176.5-142176.29" + switch \initial + attribute \src "libresoc.v:142176.9-142176.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\sr0_update_core$next[0:0]$5978 1'0 + case + assign $1\sr0_update_core$next[0:0]$5978 \sr0_update + end + sync always + update \sr0_update_core$next $0\sr0_update_core$next[0:0]$5977 + end + attribute \src "libresoc.v:142184.3-142192.6" + process $proc$libresoc.v:142184$5979 + assign { } { } + assign { } { } + assign $0\sr0_update_core_prev$next[0:0]$5980 $1\sr0_update_core_prev$next[0:0]$5981 + attribute \src "libresoc.v:142185.5-142185.29" + switch \initial + attribute \src "libresoc.v:142185.9-142185.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\sr0_update_core_prev$next[0:0]$5981 1'0 + case + assign $1\sr0_update_core_prev$next[0:0]$5981 \sr0_update_core + end + sync always + update \sr0_update_core_prev$next $0\sr0_update_core_prev$next[0:0]$5980 + end + attribute \src "libresoc.v:142193.3-142209.6" + process $proc$libresoc.v:142193$5982 + assign { } { } + assign { } { } + assign $0\sr0__oe$next[0:0]$5983 $2\sr0__oe$next[0:0]$5985 + attribute \src "libresoc.v:142194.5-142194.29" + switch \initial + attribute \src "libresoc.v:142194.9-142194.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + switch \$387 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\sr0__oe$next[0:0]$5984 \sr0_isir + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\sr0__oe$next[0:0]$5984 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\sr0__oe$next[0:0]$5985 1'0 + case + assign $2\sr0__oe$next[0:0]$5985 $1\sr0__oe$next[0:0]$5984 + end + sync always + update \sr0__oe$next $0\sr0__oe$next[0:0]$5983 + end + attribute \src "libresoc.v:142210.3-142230.6" + process $proc$libresoc.v:142210$5986 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\sr0_reg$next[2:0]$5987 $3\sr0_reg$next[2:0]$5990 + attribute \src "libresoc.v:142211.5-142211.29" + switch \initial + attribute \src "libresoc.v:142211.9-142211.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:673" + switch \sr0_shift + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\sr0_reg$next[2:0]$5988 { \TAP_bus__tdi \sr0_reg [2:1] } + case + assign $1\sr0_reg$next[2:0]$5988 \sr0_reg + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" + switch \sr0_capture + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\sr0_reg$next[2:0]$5989 \sr0__i + case + assign $2\sr0_reg$next[2:0]$5989 $1\sr0_reg$next[2:0]$5988 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \posjtag_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\sr0_reg$next[2:0]$5990 3'000 + case + assign $3\sr0_reg$next[2:0]$5990 $2\sr0_reg$next[2:0]$5989 + end + sync always + update \sr0_reg$next $0\sr0_reg$next[2:0]$5987 + end + attribute \src "libresoc.v:142231.3-142239.6" + process $proc$libresoc.v:142231$5991 + assign { } { } + assign { } { } + assign $0\jtag_wb_addrsr_update_core$next[0:0]$5992 $1\jtag_wb_addrsr_update_core$next[0:0]$5993 + attribute \src "libresoc.v:142232.5-142232.29" + switch \initial + attribute \src "libresoc.v:142232.9-142232.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\jtag_wb_addrsr_update_core$next[0:0]$5993 1'0 + case + assign $1\jtag_wb_addrsr_update_core$next[0:0]$5993 \jtag_wb_addrsr_update + end + sync always + update \jtag_wb_addrsr_update_core$next $0\jtag_wb_addrsr_update_core$next[0:0]$5992 + end + attribute \src "libresoc.v:142240.3-142248.6" + process $proc$libresoc.v:142240$5994 + assign { } { } + assign { } { } + assign $0\jtag_wb_addrsr_update_core_prev$next[0:0]$5995 $1\jtag_wb_addrsr_update_core_prev$next[0:0]$5996 + attribute \src "libresoc.v:142241.5-142241.29" + switch \initial + attribute \src "libresoc.v:142241.9-142241.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\jtag_wb_addrsr_update_core_prev$next[0:0]$5996 1'0 + case + assign $1\jtag_wb_addrsr_update_core_prev$next[0:0]$5996 \jtag_wb_addrsr_update_core + end + sync always + update \jtag_wb_addrsr_update_core_prev$next $0\jtag_wb_addrsr_update_core_prev$next[0:0]$5995 + end + attribute \src "libresoc.v:142249.3-142265.6" + process $proc$libresoc.v:142249$5997 + assign { } { } + assign { } { } + assign $0\jtag_wb_addrsr__oe$next[0:0]$5998 $2\jtag_wb_addrsr__oe$next[0:0]$6000 + attribute \src "libresoc.v:142250.5-142250.29" + switch \initial + attribute \src "libresoc.v:142250.9-142250.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + switch \$405 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\jtag_wb_addrsr__oe$next[0:0]$5999 \jtag_wb_addrsr_isir + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\jtag_wb_addrsr__oe$next[0:0]$5999 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\jtag_wb_addrsr__oe$next[0:0]$6000 1'0 + case + assign $2\jtag_wb_addrsr__oe$next[0:0]$6000 $1\jtag_wb_addrsr__oe$next[0:0]$5999 + end + sync always + update \jtag_wb_addrsr__oe$next $0\jtag_wb_addrsr__oe$next[0:0]$5998 + end + attribute \src "libresoc.v:142266.3-142286.6" + process $proc$libresoc.v:142266$6001 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\jtag_wb_addrsr_reg$next[28:0]$6002 $3\jtag_wb_addrsr_reg$next[28:0]$6005 + attribute \src "libresoc.v:142267.5-142267.29" + switch \initial + attribute \src "libresoc.v:142267.9-142267.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:673" + switch \jtag_wb_addrsr_shift + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\jtag_wb_addrsr_reg$next[28:0]$6003 { \TAP_bus__tdi \jtag_wb_addrsr_reg [28:1] } + case + assign $1\jtag_wb_addrsr_reg$next[28:0]$6003 \jtag_wb_addrsr_reg + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" + switch \jtag_wb_addrsr_capture + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\jtag_wb_addrsr_reg$next[28:0]$6004 \jtag_wb_addrsr__i + case + assign $2\jtag_wb_addrsr_reg$next[28:0]$6004 $1\jtag_wb_addrsr_reg$next[28:0]$6003 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \posjtag_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\jtag_wb_addrsr_reg$next[28:0]$6005 29'00000000000000000000000000000 + case + assign $3\jtag_wb_addrsr_reg$next[28:0]$6005 $2\jtag_wb_addrsr_reg$next[28:0]$6004 + end + sync always + update \jtag_wb_addrsr_reg$next $0\jtag_wb_addrsr_reg$next[28:0]$6002 + end + attribute \src "libresoc.v:142287.3-142295.6" + process $proc$libresoc.v:142287$6006 + assign { } { } + assign { } { } + assign $0\jtag_wb_datasr_update_core$next[0:0]$6007 $1\jtag_wb_datasr_update_core$next[0:0]$6008 + attribute \src "libresoc.v:142288.5-142288.29" + switch \initial + attribute \src "libresoc.v:142288.9-142288.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\jtag_wb_datasr_update_core$next[0:0]$6008 1'0 + case + assign $1\jtag_wb_datasr_update_core$next[0:0]$6008 \jtag_wb_datasr_update + end + sync always + update \jtag_wb_datasr_update_core$next $0\jtag_wb_datasr_update_core$next[0:0]$6007 + end + attribute \src "libresoc.v:142296.3-142304.6" + process $proc$libresoc.v:142296$6009 + assign { } { } + assign { } { } + assign $0\jtag_wb_datasr_update_core_prev$next[0:0]$6010 $1\jtag_wb_datasr_update_core_prev$next[0:0]$6011 + attribute \src "libresoc.v:142297.5-142297.29" + switch \initial + attribute \src "libresoc.v:142297.9-142297.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\jtag_wb_datasr_update_core_prev$next[0:0]$6011 1'0 + case + assign $1\jtag_wb_datasr_update_core_prev$next[0:0]$6011 \jtag_wb_datasr_update_core + end + sync always + update \jtag_wb_datasr_update_core_prev$next $0\jtag_wb_datasr_update_core_prev$next[0:0]$6010 + end + attribute \src "libresoc.v:142305.3-142321.6" + process $proc$libresoc.v:142305$6012 + assign { } { } + assign { } { } + assign $0\jtag_wb_datasr__oe$next[1:0]$6013 $2\jtag_wb_datasr__oe$next[1:0]$6015 + attribute \src "libresoc.v:142306.5-142306.29" + switch \initial + attribute \src "libresoc.v:142306.9-142306.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + switch \$425 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\jtag_wb_datasr__oe$next[1:0]$6014 \jtag_wb_datasr_isir + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\jtag_wb_datasr__oe$next[1:0]$6014 2'00 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\jtag_wb_datasr__oe$next[1:0]$6015 2'00 + case + assign $2\jtag_wb_datasr__oe$next[1:0]$6015 $1\jtag_wb_datasr__oe$next[1:0]$6014 + end + sync always + update \jtag_wb_datasr__oe$next $0\jtag_wb_datasr__oe$next[1:0]$6013 + end + attribute \src "libresoc.v:142322.3-142342.6" + process $proc$libresoc.v:142322$6016 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\jtag_wb_datasr_reg$next[63:0]$6017 $3\jtag_wb_datasr_reg$next[63:0]$6020 + attribute \src "libresoc.v:142323.5-142323.29" + switch \initial + attribute \src "libresoc.v:142323.9-142323.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:673" + switch \jtag_wb_datasr_shift + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\jtag_wb_datasr_reg$next[63:0]$6018 { \TAP_bus__tdi \jtag_wb_datasr_reg [63:1] } + case + assign $1\jtag_wb_datasr_reg$next[63:0]$6018 \jtag_wb_datasr_reg + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" + switch \jtag_wb_datasr_capture + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\jtag_wb_datasr_reg$next[63:0]$6019 \jtag_wb_datasr__i + case + assign $2\jtag_wb_datasr_reg$next[63:0]$6019 $1\jtag_wb_datasr_reg$next[63:0]$6018 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \posjtag_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\jtag_wb_datasr_reg$next[63:0]$6020 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $3\jtag_wb_datasr_reg$next[63:0]$6020 $2\jtag_wb_datasr_reg$next[63:0]$6019 + end + sync always + update \jtag_wb_datasr_reg$next $0\jtag_wb_datasr_reg$next[63:0]$6017 + end + attribute \src "libresoc.v:142343.3-142351.6" + process $proc$libresoc.v:142343$6021 + assign { } { } + assign { } { } + assign $0\dmi0_addrsr_update_core$next[0:0]$6022 $1\dmi0_addrsr_update_core$next[0:0]$6023 + attribute \src "libresoc.v:142344.5-142344.29" + switch \initial + attribute \src "libresoc.v:142344.9-142344.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dmi0_addrsr_update_core$next[0:0]$6023 1'0 + case + assign $1\dmi0_addrsr_update_core$next[0:0]$6023 \dmi0_addrsr_update + end + sync always + update \dmi0_addrsr_update_core$next $0\dmi0_addrsr_update_core$next[0:0]$6022 + end + attribute \src "libresoc.v:142352.3-142360.6" + process $proc$libresoc.v:142352$6024 + assign { } { } + assign { } { } + assign $0\dmi0_addrsr_update_core_prev$next[0:0]$6025 $1\dmi0_addrsr_update_core_prev$next[0:0]$6026 + attribute \src "libresoc.v:142353.5-142353.29" + switch \initial + attribute \src "libresoc.v:142353.9-142353.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dmi0_addrsr_update_core_prev$next[0:0]$6026 1'0 + case + assign $1\dmi0_addrsr_update_core_prev$next[0:0]$6026 \dmi0_addrsr_update_core + end + sync always + update \dmi0_addrsr_update_core_prev$next $0\dmi0_addrsr_update_core_prev$next[0:0]$6025 + end + attribute \src "libresoc.v:142361.3-142377.6" + process $proc$libresoc.v:142361$6027 + assign { } { } + assign { } { } + assign $0\dmi0_addrsr__oe$next[0:0]$6028 $2\dmi0_addrsr__oe$next[0:0]$6030 + attribute \src "libresoc.v:142362.5-142362.29" + switch \initial + attribute \src "libresoc.v:142362.9-142362.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + switch \$443 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dmi0_addrsr__oe$next[0:0]$6029 \dmi0_addrsr_isir + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\dmi0_addrsr__oe$next[0:0]$6029 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\dmi0_addrsr__oe$next[0:0]$6030 1'0 + case + assign $2\dmi0_addrsr__oe$next[0:0]$6030 $1\dmi0_addrsr__oe$next[0:0]$6029 + end + sync always + update \dmi0_addrsr__oe$next $0\dmi0_addrsr__oe$next[0:0]$6028 + end + attribute \src "libresoc.v:142378.3-142398.6" + process $proc$libresoc.v:142378$6031 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\dmi0_addrsr_reg$next[7:0]$6032 $3\dmi0_addrsr_reg$next[7:0]$6035 + attribute \src "libresoc.v:142379.5-142379.29" + switch \initial + attribute \src "libresoc.v:142379.9-142379.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:673" + switch \dmi0_addrsr_shift + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dmi0_addrsr_reg$next[7:0]$6033 { \TAP_bus__tdi \dmi0_addrsr_reg [7:1] } + case + assign $1\dmi0_addrsr_reg$next[7:0]$6033 \dmi0_addrsr_reg + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" + switch \dmi0_addrsr_capture + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\dmi0_addrsr_reg$next[7:0]$6034 \dmi0_addrsr__i + case + assign $2\dmi0_addrsr_reg$next[7:0]$6034 $1\dmi0_addrsr_reg$next[7:0]$6033 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \posjtag_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\dmi0_addrsr_reg$next[7:0]$6035 8'00000000 + case + assign $3\dmi0_addrsr_reg$next[7:0]$6035 $2\dmi0_addrsr_reg$next[7:0]$6034 + end + sync always + update \dmi0_addrsr_reg$next $0\dmi0_addrsr_reg$next[7:0]$6032 + end + attribute \src "libresoc.v:142399.3-142407.6" + process $proc$libresoc.v:142399$6036 + assign { } { } + assign { } { } + assign $0\dmi0_datasr_update_core$next[0:0]$6037 $1\dmi0_datasr_update_core$next[0:0]$6038 + attribute \src "libresoc.v:142400.5-142400.29" + switch \initial + attribute \src "libresoc.v:142400.9-142400.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dmi0_datasr_update_core$next[0:0]$6038 1'0 + case + assign $1\dmi0_datasr_update_core$next[0:0]$6038 \dmi0_datasr_update + end + sync always + update \dmi0_datasr_update_core$next $0\dmi0_datasr_update_core$next[0:0]$6037 + end + attribute \src "libresoc.v:142408.3-142416.6" + process $proc$libresoc.v:142408$6039 + assign { } { } + assign { } { } + assign $0\dmi0_datasr_update_core_prev$next[0:0]$6040 $1\dmi0_datasr_update_core_prev$next[0:0]$6041 + attribute \src "libresoc.v:142409.5-142409.29" + switch \initial + attribute \src "libresoc.v:142409.9-142409.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dmi0_datasr_update_core_prev$next[0:0]$6041 1'0 + case + assign $1\dmi0_datasr_update_core_prev$next[0:0]$6041 \dmi0_datasr_update_core + end + sync always + update \dmi0_datasr_update_core_prev$next $0\dmi0_datasr_update_core_prev$next[0:0]$6040 + end + attribute \src "libresoc.v:142417.3-142433.6" + process $proc$libresoc.v:142417$6042 + assign { } { } + assign { } { } + assign $0\dmi0_datasr__oe$next[1:0]$6043 $2\dmi0_datasr__oe$next[1:0]$6045 + attribute \src "libresoc.v:142418.5-142418.29" + switch \initial + attribute \src "libresoc.v:142418.9-142418.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + switch \$463 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dmi0_datasr__oe$next[1:0]$6044 \dmi0_datasr_isir + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\dmi0_datasr__oe$next[1:0]$6044 2'00 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\dmi0_datasr__oe$next[1:0]$6045 2'00 + case + assign $2\dmi0_datasr__oe$next[1:0]$6045 $1\dmi0_datasr__oe$next[1:0]$6044 + end + sync always + update \dmi0_datasr__oe$next $0\dmi0_datasr__oe$next[1:0]$6043 + end + attribute \src "libresoc.v:142434.3-142454.6" + process $proc$libresoc.v:142434$6046 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\dmi0_datasr_reg$next[63:0]$6047 $3\dmi0_datasr_reg$next[63:0]$6050 + attribute \src "libresoc.v:142435.5-142435.29" + switch \initial + attribute \src "libresoc.v:142435.9-142435.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:673" + switch \dmi0_datasr_shift + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dmi0_datasr_reg$next[63:0]$6048 { \TAP_bus__tdi \dmi0_datasr_reg [63:1] } + case + assign $1\dmi0_datasr_reg$next[63:0]$6048 \dmi0_datasr_reg + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" + switch \dmi0_datasr_capture + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\dmi0_datasr_reg$next[63:0]$6049 \dmi0_datasr__i + case + assign $2\dmi0_datasr_reg$next[63:0]$6049 $1\dmi0_datasr_reg$next[63:0]$6048 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \posjtag_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\dmi0_datasr_reg$next[63:0]$6050 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $3\dmi0_datasr_reg$next[63:0]$6050 $2\dmi0_datasr_reg$next[63:0]$6049 + end + sync always + update \dmi0_datasr_reg$next $0\dmi0_datasr_reg$next[63:0]$6047 + end + attribute \src "libresoc.v:142455.3-142463.6" + process $proc$libresoc.v:142455$6051 + assign { } { } + assign { } { } + assign $0\sr5_update_core$next[0:0]$6052 $1\sr5_update_core$next[0:0]$6053 + attribute \src "libresoc.v:142456.5-142456.29" + switch \initial + attribute \src "libresoc.v:142456.9-142456.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\sr5_update_core$next[0:0]$6053 1'0 + case + assign $1\sr5_update_core$next[0:0]$6053 \sr5_update + end + sync always + update \sr5_update_core$next $0\sr5_update_core$next[0:0]$6052 + end + attribute \src "libresoc.v:142464.3-142472.6" + process $proc$libresoc.v:142464$6054 + assign { } { } + assign { } { } + assign $0\sr5_update_core_prev$next[0:0]$6055 $1\sr5_update_core_prev$next[0:0]$6056 + attribute \src "libresoc.v:142465.5-142465.29" + switch \initial + attribute \src "libresoc.v:142465.9-142465.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\sr5_update_core_prev$next[0:0]$6056 1'0 + case + assign $1\sr5_update_core_prev$next[0:0]$6056 \sr5_update_core + end + sync always + update \sr5_update_core_prev$next $0\sr5_update_core_prev$next[0:0]$6055 + end + attribute \src "libresoc.v:142473.3-142489.6" + process $proc$libresoc.v:142473$6057 + assign { } { } + assign { } { } + assign $0\sr5__oe$next[0:0]$6058 $2\sr5__oe$next[0:0]$6060 + attribute \src "libresoc.v:142474.5-142474.29" + switch \initial + attribute \src "libresoc.v:142474.9-142474.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + switch \$481 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\sr5__oe$next[0:0]$6059 \sr5_isir + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\sr5__oe$next[0:0]$6059 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\sr5__oe$next[0:0]$6060 1'0 + case + assign $2\sr5__oe$next[0:0]$6060 $1\sr5__oe$next[0:0]$6059 + end + sync always + update \sr5__oe$next $0\sr5__oe$next[0:0]$6058 + end + attribute \src "libresoc.v:142490.3-142510.6" + process $proc$libresoc.v:142490$6061 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\sr5_reg$next[1:0]$6062 $3\sr5_reg$next[1:0]$6065 + attribute \src "libresoc.v:142491.5-142491.29" + switch \initial + attribute \src "libresoc.v:142491.9-142491.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:673" + switch \sr5_shift + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\sr5_reg$next[1:0]$6063 { \TAP_bus__tdi \sr5_reg [1] } + case + assign $1\sr5_reg$next[1:0]$6063 \sr5_reg + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" + switch \sr5_capture + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\sr5_reg$next[1:0]$6064 \sr5__i + case + assign $2\sr5_reg$next[1:0]$6064 $1\sr5_reg$next[1:0]$6063 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \posjtag_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\sr5_reg$next[1:0]$6065 2'00 + case + assign $3\sr5_reg$next[1:0]$6065 $2\sr5_reg$next[1:0]$6064 + end + sync always + update \sr5_reg$next $0\sr5_reg$next[1:0]$6062 + end + attribute \src "libresoc.v:142511.3-142537.6" + process $proc$libresoc.v:142511$6066 + assign { } { } + assign $0\TAP_bus__tdo[0:0] $1\TAP_bus__tdo[0:0] + attribute \src "libresoc.v:142512.5-142512.29" + switch \initial + attribute \src "libresoc.v:142512.9-142512.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:685" + switch { \sr5_shift \dmi0_datasr_shift \dmi0_addrsr_shift \jtag_wb_datasr_shift \jtag_wb_addrsr_shift \sr0_shift } + attribute \src "libresoc.v:0.0-0.0" + case 6'-----1 + assign { } { } + assign $1\TAP_bus__tdo[0:0] \sr0_reg [0] + attribute \src "libresoc.v:0.0-0.0" + case 6'----1- + assign { } { } + assign $1\TAP_bus__tdo[0:0] \jtag_wb_addrsr_reg [0] + attribute \src "libresoc.v:0.0-0.0" + case 6'---1-- + assign { } { } + assign $1\TAP_bus__tdo[0:0] \jtag_wb_datasr_reg [0] + attribute \src "libresoc.v:0.0-0.0" + case 6'--1--- + assign { } { } + assign $1\TAP_bus__tdo[0:0] \dmi0_addrsr_reg [0] + attribute \src "libresoc.v:0.0-0.0" + case 6'-1---- + assign { } { } + assign $1\TAP_bus__tdo[0:0] \dmi0_datasr_reg [0] + attribute \src "libresoc.v:0.0-0.0" + case 6'1----- + assign { } { } + assign $1\TAP_bus__tdo[0:0] \sr5_reg [0] + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\TAP_bus__tdo[0:0] \TAP_tdo + end + sync always + update \TAP_bus__tdo $0\TAP_bus__tdo[0:0] + end + attribute \src "libresoc.v:142538.3-142570.6" + process $proc$libresoc.v:142538$6067 + assign { } { } + assign { } { } + assign { } { } + assign $0\jtag_wb__adr$next[28:0]$6068 $4\jtag_wb__adr$next[28:0]$6072 + attribute \src "libresoc.v:142539.5-142539.29" + switch \initial + attribute \src "libresoc.v:142539.9-142539.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:754" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 3'000 + assign { } { } + assign $1\jtag_wb__adr$next[28:0]$6069 $2\jtag_wb__adr$next[28:0]$6070 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:756" + switch { \jtag_wb_datasr__oe \jtag_wb_addrsr__oe } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign { } { } + assign $2\jtag_wb__adr$next[28:0]$6070 \jtag_wb_addrsr__o + attribute \src "libresoc.v:0.0-0.0" + case 3'-1- + assign { } { } + assign $2\jtag_wb__adr$next[28:0]$6070 \$495 [28:0] + case + assign $2\jtag_wb__adr$next[28:0]$6070 \jtag_wb__adr + end + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\jtag_wb__adr$next[28:0]$6069 $3\jtag_wb__adr$next[28:0]$6071 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:785" + switch \jtag_wb__ack + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\jtag_wb__adr$next[28:0]$6071 \$498 [28:0] + case + assign $3\jtag_wb__adr$next[28:0]$6071 \jtag_wb__adr + end + case + assign $1\jtag_wb__adr$next[28:0]$6069 \jtag_wb__adr + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\jtag_wb__adr$next[28:0]$6072 29'00000000000000000000000000000 + case + assign $4\jtag_wb__adr$next[28:0]$6072 $1\jtag_wb__adr$next[28:0]$6069 + end + sync always + update \jtag_wb__adr$next $0\jtag_wb__adr$next[28:0]$6068 + end + attribute \src "libresoc.v:142571.3-142623.6" + process $proc$libresoc.v:142571$6073 + assign { } { } + assign { } { } + assign { } { } + assign $0\fsm_state$next[2:0]$6074 $5\fsm_state$next[2:0]$6079 + attribute \src "libresoc.v:142572.5-142572.29" + switch \initial + attribute \src "libresoc.v:142572.9-142572.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:754" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 3'000 + assign { } { } + assign $1\fsm_state$next[2:0]$6075 $2\fsm_state$next[2:0]$6076 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:756" + switch { \jtag_wb_datasr__oe \jtag_wb_addrsr__oe } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign { } { } + assign $2\fsm_state$next[2:0]$6076 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 3'-1- + assign { } { } + assign $2\fsm_state$next[2:0]$6076 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 3'1-- + assign { } { } + assign $2\fsm_state$next[2:0]$6076 3'010 + case + assign $2\fsm_state$next[2:0]$6076 \fsm_state + end + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\fsm_state$next[2:0]$6075 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\fsm_state$next[2:0]$6075 $3\fsm_state$next[2:0]$6077 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:773" + switch \jtag_wb__ack + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fsm_state$next[2:0]$6077 3'000 + case + assign $3\fsm_state$next[2:0]$6077 \fsm_state + end + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\fsm_state$next[2:0]$6075 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\fsm_state$next[2:0]$6075 $4\fsm_state$next[2:0]$6078 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:785" + switch \jtag_wb__ack + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\fsm_state$next[2:0]$6078 3'001 + case + assign $4\fsm_state$next[2:0]$6078 \fsm_state + end + case + assign $1\fsm_state$next[2:0]$6075 \fsm_state + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\fsm_state$next[2:0]$6079 3'000 + case + assign $5\fsm_state$next[2:0]$6079 $1\fsm_state$next[2:0]$6075 + end + sync always + update \fsm_state$next $0\fsm_state$next[2:0]$6074 + end + attribute \src "libresoc.v:142624.3-142650.6" + process $proc$libresoc.v:142624$6080 + assign { } { } + assign { } { } + assign { } { } + assign $0\jtag_wb__dat_w$next[63:0]$6081 $3\jtag_wb__dat_w$next[63:0]$6084 + attribute \src "libresoc.v:142625.5-142625.29" + switch \initial + attribute \src "libresoc.v:142625.9-142625.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:754" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 3'000 + assign { } { } + assign $1\jtag_wb__dat_w$next[63:0]$6082 $2\jtag_wb__dat_w$next[63:0]$6083 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:756" + switch { \jtag_wb_datasr__oe \jtag_wb_addrsr__oe } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign $2\jtag_wb__dat_w$next[63:0]$6083 \jtag_wb__dat_w + attribute \src "libresoc.v:0.0-0.0" + case 3'-1- + assign $2\jtag_wb__dat_w$next[63:0]$6083 \jtag_wb__dat_w + attribute \src "libresoc.v:0.0-0.0" + case 3'1-- + assign { } { } + assign $2\jtag_wb__dat_w$next[63:0]$6083 \jtag_wb_datasr__o + case + assign $2\jtag_wb__dat_w$next[63:0]$6083 \jtag_wb__dat_w + end + case + assign $1\jtag_wb__dat_w$next[63:0]$6082 \jtag_wb__dat_w + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\jtag_wb__dat_w$next[63:0]$6084 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $3\jtag_wb__dat_w$next[63:0]$6084 $1\jtag_wb__dat_w$next[63:0]$6082 + end + sync always + update \jtag_wb__dat_w$next $0\jtag_wb__dat_w$next[63:0]$6081 + end + attribute \src "libresoc.v:142651.3-142671.6" + process $proc$libresoc.v:142651$6085 + assign { } { } + assign { } { } + assign { } { } + assign $0\jtag_wb_datasr__i$next[63:0]$6086 $3\jtag_wb_datasr__i$next[63:0]$6089 + attribute \src "libresoc.v:142652.5-142652.29" + switch \initial + attribute \src "libresoc.v:142652.9-142652.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:754" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\jtag_wb_datasr__i$next[63:0]$6087 $2\jtag_wb_datasr__i$next[63:0]$6088 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:773" + switch \jtag_wb__ack + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\jtag_wb_datasr__i$next[63:0]$6088 \jtag_wb__dat_r + case + assign $2\jtag_wb_datasr__i$next[63:0]$6088 \jtag_wb_datasr__i + end + case + assign $1\jtag_wb_datasr__i$next[63:0]$6087 \jtag_wb_datasr__i + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\jtag_wb_datasr__i$next[63:0]$6089 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $3\jtag_wb_datasr__i$next[63:0]$6089 $1\jtag_wb_datasr__i$next[63:0]$6087 + end + sync always + update \jtag_wb_datasr__i$next $0\jtag_wb_datasr__i$next[63:0]$6086 + end + attribute \src "libresoc.v:142672.3-142704.6" + process $proc$libresoc.v:142672$6090 + assign { } { } + assign { } { } + assign { } { } + assign $0\dmi0__addr_i$next[3:0]$6091 $4\dmi0__addr_i$next[3:0]$6095 + attribute \src "libresoc.v:142673.5-142673.29" + switch \initial + attribute \src "libresoc.v:142673.9-142673.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + switch \fsm_state$503 + attribute \src "libresoc.v:0.0-0.0" + case 3'000 + assign { } { } + assign $1\dmi0__addr_i$next[3:0]$6092 $2\dmi0__addr_i$next[3:0]$6093 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:489" + switch { \dmi0_datasr__oe \dmi0_addrsr__oe } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign { } { } + assign $2\dmi0__addr_i$next[3:0]$6093 \dmi0_addrsr__o [3:0] + attribute \src "libresoc.v:0.0-0.0" + case 3'-1- + assign { } { } + assign $2\dmi0__addr_i$next[3:0]$6093 \$512 [3:0] + case + assign $2\dmi0__addr_i$next[3:0]$6093 \dmi0__addr_i + end + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\dmi0__addr_i$next[3:0]$6092 $3\dmi0__addr_i$next[3:0]$6094 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:517" + switch \dmi0__ack_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\dmi0__addr_i$next[3:0]$6094 \$515 [3:0] + case + assign $3\dmi0__addr_i$next[3:0]$6094 \dmi0__addr_i + end + case + assign $1\dmi0__addr_i$next[3:0]$6092 \dmi0__addr_i + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\dmi0__addr_i$next[3:0]$6095 4'0000 + case + assign $4\dmi0__addr_i$next[3:0]$6095 $1\dmi0__addr_i$next[3:0]$6092 + end + sync always + update \dmi0__addr_i$next $0\dmi0__addr_i$next[3:0]$6091 + end + attribute \src "libresoc.v:142705.3-142757.6" + process $proc$libresoc.v:142705$6096 + assign { } { } + assign { } { } + assign { } { } + assign $0\fsm_state$503$next[2:0]$6097 $5\fsm_state$503$next[2:0]$6102 + attribute \src "libresoc.v:142706.5-142706.29" + switch \initial + attribute \src "libresoc.v:142706.9-142706.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + switch \fsm_state$503 + attribute \src "libresoc.v:0.0-0.0" + case 3'000 + assign { } { } + assign $1\fsm_state$503$next[2:0]$6098 $2\fsm_state$503$next[2:0]$6099 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:489" + switch { \dmi0_datasr__oe \dmi0_addrsr__oe } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign { } { } + assign $2\fsm_state$503$next[2:0]$6099 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 3'-1- + assign { } { } + assign $2\fsm_state$503$next[2:0]$6099 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 3'1-- + assign { } { } + assign $2\fsm_state$503$next[2:0]$6099 3'010 + case + assign $2\fsm_state$503$next[2:0]$6099 \fsm_state$503 + end + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\fsm_state$503$next[2:0]$6098 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\fsm_state$503$next[2:0]$6098 $3\fsm_state$503$next[2:0]$6100 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:506" + switch \dmi0__ack_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fsm_state$503$next[2:0]$6100 3'000 + case + assign $3\fsm_state$503$next[2:0]$6100 \fsm_state$503 + end + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\fsm_state$503$next[2:0]$6098 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\fsm_state$503$next[2:0]$6098 $4\fsm_state$503$next[2:0]$6101 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:517" + switch \dmi0__ack_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\fsm_state$503$next[2:0]$6101 3'001 + case + assign $4\fsm_state$503$next[2:0]$6101 \fsm_state$503 + end + case + assign $1\fsm_state$503$next[2:0]$6098 \fsm_state$503 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\fsm_state$503$next[2:0]$6102 3'000 + case + assign $5\fsm_state$503$next[2:0]$6102 $1\fsm_state$503$next[2:0]$6098 + end + sync always + update \fsm_state$503$next $0\fsm_state$503$next[2:0]$6097 + end + attribute \src "libresoc.v:142758.3-142784.6" + process $proc$libresoc.v:142758$6103 + assign { } { } + assign { } { } + assign { } { } + assign $0\dmi0__din$next[63:0]$6104 $3\dmi0__din$next[63:0]$6107 + attribute \src "libresoc.v:142759.5-142759.29" + switch \initial + attribute \src "libresoc.v:142759.9-142759.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + switch \fsm_state$503 + attribute \src "libresoc.v:0.0-0.0" + case 3'000 + assign { } { } + assign $1\dmi0__din$next[63:0]$6105 $2\dmi0__din$next[63:0]$6106 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:489" + switch { \dmi0_datasr__oe \dmi0_addrsr__oe } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign $2\dmi0__din$next[63:0]$6106 \dmi0__din + attribute \src "libresoc.v:0.0-0.0" + case 3'-1- + assign $2\dmi0__din$next[63:0]$6106 \dmi0__din + attribute \src "libresoc.v:0.0-0.0" + case 3'1-- + assign { } { } + assign $2\dmi0__din$next[63:0]$6106 \dmi0_datasr__o + case + assign $2\dmi0__din$next[63:0]$6106 \dmi0__din + end + case + assign $1\dmi0__din$next[63:0]$6105 \dmi0__din + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\dmi0__din$next[63:0]$6107 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $3\dmi0__din$next[63:0]$6107 $1\dmi0__din$next[63:0]$6105 + end + sync always + update \dmi0__din$next $0\dmi0__din$next[63:0]$6104 + end + attribute \src "libresoc.v:142785.3-142805.6" + process $proc$libresoc.v:142785$6108 + assign { } { } + assign { } { } + assign { } { } + assign $0\dmi0_datasr__i$next[63:0]$6109 $3\dmi0_datasr__i$next[63:0]$6112 + attribute \src "libresoc.v:142786.5-142786.29" + switch \initial + attribute \src "libresoc.v:142786.9-142786.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" + switch \fsm_state$503 + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\dmi0_datasr__i$next[63:0]$6110 $2\dmi0_datasr__i$next[63:0]$6111 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:506" + switch \dmi0__ack_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\dmi0_datasr__i$next[63:0]$6111 \dmi0__dout + case + assign $2\dmi0_datasr__i$next[63:0]$6111 \dmi0_datasr__i + end + case + assign $1\dmi0_datasr__i$next[63:0]$6110 \dmi0_datasr__i + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\dmi0_datasr__i$next[63:0]$6112 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $3\dmi0_datasr__i$next[63:0]$6112 $1\dmi0_datasr__i$next[63:0]$6110 + end + sync always + update \dmi0_datasr__i$next $0\dmi0_datasr__i$next[63:0]$6109 + end + attribute \src "libresoc.v:142806.3-142824.6" + process $proc$libresoc.v:142806$6113 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\wb_dcache_en$next[0:0]$6114 $2\wb_dcache_en$next[0:0]$6118 + assign $0\wb_icache_en$next[0:0]$6115 $2\wb_icache_en$next[0:0]$6119 + attribute \src "libresoc.v:142807.5-142807.29" + switch \initial + attribute \src "libresoc.v:142807.9-142807.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:102" + switch \sr5__oe + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\wb_dcache_en$next[0:0]$6116 $1\wb_icache_en$next[0:0]$6117 } \sr5__o + case + assign $1\wb_dcache_en$next[0:0]$6116 \wb_dcache_en + assign $1\wb_icache_en$next[0:0]$6117 \wb_icache_en + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $2\wb_icache_en$next[0:0]$6119 1'1 + assign $2\wb_dcache_en$next[0:0]$6118 1'1 + case + assign $2\wb_dcache_en$next[0:0]$6118 $1\wb_dcache_en$next[0:0]$6116 + assign $2\wb_icache_en$next[0:0]$6119 $1\wb_icache_en$next[0:0]$6117 + end + sync always + update \wb_dcache_en$next $0\wb_dcache_en$next[0:0]$6114 + update \wb_icache_en$next $0\wb_icache_en$next[0:0]$6115 + end + attribute \src "libresoc.v:142825.3-142834.6" + process $proc$libresoc.v:142825$6120 + assign { } { } + assign { } { } + assign $0\sr5__i[1:0] $1\sr5__i[1:0] + attribute \src "libresoc.v:142826.5-142826.29" + switch \initial + attribute \src "libresoc.v:142826.9-142826.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:105" + switch \sr5__ie + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\sr5__i[1:0] { \wb_dcache_en \wb_icache_en } + case + assign $1\sr5__i[1:0] 2'00 + end + sync always + update \sr5__i $0\sr5__i[1:0] + end + attribute \src "libresoc.v:142835.3-142852.6" + process $proc$libresoc.v:142835$6121 + assign { } { } + assign { } { } + assign { } { } + assign $0\io_sr$next[153:0]$6122 $2\io_sr$next[153:0]$6124 + attribute \src "libresoc.v:142836.5-142836.29" + switch \initial + attribute \src "libresoc.v:142836.9-142836.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:552" + switch { \io_update \io_shift \io_capture } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign { } { } + assign $1\io_sr$next[153:0]$6123 { \sdr_dq_15__core__oe \sdr_dq_15__core__o \sdr_dq_15__pad__i \sdr_dq_14__core__oe \sdr_dq_14__core__o \sdr_dq_14__pad__i \sdr_dq_13__core__oe \sdr_dq_13__core__o \sdr_dq_13__pad__i \sdr_dq_12__core__oe \sdr_dq_12__core__o \sdr_dq_12__pad__i \sdr_dq_11__core__oe \sdr_dq_11__core__o \sdr_dq_11__pad__i \sdr_dq_10__core__oe \sdr_dq_10__core__o \sdr_dq_10__pad__i \sdr_dq_9__core__oe \sdr_dq_9__core__o \sdr_dq_9__pad__i \sdr_dq_8__core__oe \sdr_dq_8__core__o \sdr_dq_8__pad__i \sdr_dm_1__core__oe \sdr_dm_1__core__o \sdr_dm_1__pad__i \sdr_a_12__core__o \sdr_a_11__core__o \sdr_a_10__core__o \sdr_cs_n__core__o \sdr_we_n__core__o \sdr_cas_n__core__o \sdr_ras_n__core__o \sdr_cke__core__o \sdr_clock__core__o \sdr_ba_1__core__o \sdr_ba_0__core__o \sdr_a_9__core__o \sdr_a_8__core__o \sdr_a_7__core__o \sdr_a_6__core__o \sdr_a_5__core__o \sdr_a_4__core__o \sdr_a_3__core__o \sdr_a_2__core__o \sdr_a_1__core__o \sdr_a_0__core__o \sdr_dq_7__core__oe \sdr_dq_7__core__o \sdr_dq_7__pad__i \sdr_dq_6__core__oe \sdr_dq_6__core__o \sdr_dq_6__pad__i \sdr_dq_5__core__oe \sdr_dq_5__core__o \sdr_dq_5__pad__i \sdr_dq_4__core__oe \sdr_dq_4__core__o \sdr_dq_4__pad__i \sdr_dq_3__core__oe \sdr_dq_3__core__o \sdr_dq_3__pad__i \sdr_dq_2__core__oe \sdr_dq_2__core__o \sdr_dq_2__pad__i \sdr_dq_1__core__oe \sdr_dq_1__core__o \sdr_dq_1__pad__i \sdr_dq_0__core__oe \sdr_dq_0__core__o \sdr_dq_0__pad__i \sdr_dm_0__core__o \sd0_data3__core__oe \sd0_data3__core__o \sd0_data3__pad__i \sd0_data2__core__oe \sd0_data2__core__o \sd0_data2__pad__i \sd0_data1__core__oe \sd0_data1__core__o \sd0_data1__pad__i \sd0_data0__core__oe \sd0_data0__core__o \sd0_data0__pad__i \sd0_clk__core__o \sd0_cmd__core__oe \sd0_cmd__core__o \sd0_cmd__pad__i \pwm_1__core__o \pwm_0__core__o \mtwi_scl__core__o \mtwi_sda__core__oe \mtwi_sda__core__o \mtwi_sda__pad__i \mspi1_miso__pad__i \mspi1_mosi__core__o \mspi1_cs_n__core__o \mspi1_clk__core__o \mspi0_miso__pad__i \mspi0_mosi__core__o \mspi0_cs_n__core__o \mspi0_clk__core__o \gpio_s7__core__oe \gpio_s7__core__o \gpio_s7__pad__i \gpio_s6__core__oe \gpio_s6__core__o \gpio_s6__pad__i \gpio_s5__core__oe \gpio_s5__core__o \gpio_s5__pad__i \gpio_s4__core__oe \gpio_s4__core__o \gpio_s4__pad__i \gpio_s3__core__oe \gpio_s3__core__o \gpio_s3__pad__i \gpio_s2__core__oe \gpio_s2__core__o \gpio_s2__pad__i \gpio_s1__core__oe \gpio_s1__core__o \gpio_s1__pad__i \gpio_s0__core__oe \gpio_s0__core__o \gpio_s0__pad__i \gpio_e15__core__oe \gpio_e15__core__o \gpio_e15__pad__i \gpio_e14__core__oe \gpio_e14__core__o \gpio_e14__pad__i \gpio_e13__core__oe \gpio_e13__core__o \gpio_e13__pad__i \gpio_e12__core__oe \gpio_e12__core__o \gpio_e12__pad__i \gpio_e11__core__oe \gpio_e11__core__o \gpio_e11__pad__i \gpio_e10__core__oe \gpio_e10__core__o \gpio_e10__pad__i \gpio_e9__core__oe \gpio_e9__core__o \gpio_e9__pad__i \gpio_e8__core__oe \gpio_e8__core__o \gpio_e8__pad__i \eint_2__pad__i \eint_1__pad__i \eint_0__pad__i } + attribute \src "libresoc.v:0.0-0.0" + case 3'-1- + assign { } { } + assign $1\io_sr$next[153:0]$6123 { \io_sr [152:0] \TAP_bus__tdi } + case + assign $1\io_sr$next[153:0]$6123 \io_sr + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \posjtag_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\io_sr$next[153:0]$6124 154'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + case + assign $2\io_sr$next[153:0]$6124 $1\io_sr$next[153:0]$6123 + end + sync always + update \io_sr$next $0\io_sr$next[153:0]$6122 + end + attribute \src "libresoc.v:142853.3-142873.6" + process $proc$libresoc.v:142853$6125 + assign { } { } + assign { } { } + assign { } { } + assign $0\io_bd$next[153:0]$6126 $2\io_bd$next[153:0]$6128 + attribute \src "libresoc.v:142854.5-142854.29" + switch \initial + attribute \src "libresoc.v:142854.9-142854.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:552" + switch { \io_update \io_shift \io_capture } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign $1\io_bd$next[153:0]$6127 \io_bd + attribute \src "libresoc.v:0.0-0.0" + case 3'-1- + assign $1\io_bd$next[153:0]$6127 \io_bd + attribute \src "libresoc.v:0.0-0.0" + case 3'1-- + assign { } { } + assign $1\io_bd$next[153:0]$6127 \io_sr + case + assign $1\io_bd$next[153:0]$6127 \io_bd + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \negjtag_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\io_bd$next[153:0]$6128 154'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + case + assign $2\io_bd$next[153:0]$6128 $1\io_bd$next[153:0]$6127 + end + sync always + update \io_bd$next $0\io_bd$next[153:0]$6126 + end + connect \$9 $eq$libresoc.v:141796$5681_Y + connect \$99 $ternary$libresoc.v:141797$5682_Y + connect \$101 $ternary$libresoc.v:141798$5683_Y + connect \$103 $ternary$libresoc.v:141799$5684_Y + connect \$105 $ternary$libresoc.v:141800$5685_Y + connect \$107 $ternary$libresoc.v:141801$5686_Y + connect \$109 $ternary$libresoc.v:141802$5687_Y + connect \$111 $ternary$libresoc.v:141803$5688_Y + connect \$113 $ternary$libresoc.v:141804$5689_Y + connect \$115 $ternary$libresoc.v:141805$5690_Y + connect \$117 $ternary$libresoc.v:141806$5691_Y + connect \$11 $eq$libresoc.v:141807$5692_Y + connect \$119 $ternary$libresoc.v:141808$5693_Y + connect \$121 $ternary$libresoc.v:141809$5694_Y + connect \$123 $ternary$libresoc.v:141810$5695_Y + connect \$125 $ternary$libresoc.v:141811$5696_Y + connect \$127 $ternary$libresoc.v:141812$5697_Y + connect \$129 $ternary$libresoc.v:141813$5698_Y + connect \$131 $ternary$libresoc.v:141814$5699_Y + connect \$133 $ternary$libresoc.v:141815$5700_Y + connect \$135 $ternary$libresoc.v:141816$5701_Y + connect \$137 $ternary$libresoc.v:141817$5702_Y + connect \$13 $eq$libresoc.v:141818$5703_Y + connect \$139 $ternary$libresoc.v:141819$5704_Y + connect \$141 $ternary$libresoc.v:141820$5705_Y + connect \$143 $ternary$libresoc.v:141821$5706_Y + connect \$145 $ternary$libresoc.v:141822$5707_Y + connect \$147 $ternary$libresoc.v:141823$5708_Y + connect \$149 $ternary$libresoc.v:141824$5709_Y + connect \$151 $ternary$libresoc.v:141825$5710_Y + connect \$153 $ternary$libresoc.v:141826$5711_Y + connect \$155 $ternary$libresoc.v:141827$5712_Y + connect \$157 $ternary$libresoc.v:141828$5713_Y + connect \$15 $or$libresoc.v:141829$5714_Y + connect \$159 $ternary$libresoc.v:141830$5715_Y + connect \$161 $ternary$libresoc.v:141831$5716_Y + connect \$163 $ternary$libresoc.v:141832$5717_Y + connect \$165 $ternary$libresoc.v:141833$5718_Y + connect \$167 $ternary$libresoc.v:141834$5719_Y + connect \$169 $ternary$libresoc.v:141835$5720_Y + connect \$171 $ternary$libresoc.v:141836$5721_Y + connect \$173 $ternary$libresoc.v:141837$5722_Y + connect \$175 $ternary$libresoc.v:141838$5723_Y + connect \$177 $ternary$libresoc.v:141839$5724_Y + connect \$17 $and$libresoc.v:141840$5725_Y + connect \$179 $ternary$libresoc.v:141841$5726_Y + connect \$181 $ternary$libresoc.v:141842$5727_Y + connect \$183 $ternary$libresoc.v:141843$5728_Y + connect \$185 $ternary$libresoc.v:141844$5729_Y + connect \$187 $ternary$libresoc.v:141845$5730_Y + connect \$189 $ternary$libresoc.v:141846$5731_Y + connect \$191 $ternary$libresoc.v:141847$5732_Y + connect \$193 $ternary$libresoc.v:141848$5733_Y + connect \$195 $ternary$libresoc.v:141849$5734_Y + connect \$197 $ternary$libresoc.v:141850$5735_Y + connect \$1 $eq$libresoc.v:141851$5736_Y + connect \$19 $eq$libresoc.v:141852$5737_Y + connect \$199 $ternary$libresoc.v:141853$5738_Y + connect \$201 $ternary$libresoc.v:141854$5739_Y + connect \$203 $ternary$libresoc.v:141855$5740_Y + connect \$205 $ternary$libresoc.v:141856$5741_Y + connect \$207 $ternary$libresoc.v:141857$5742_Y + connect \$209 $ternary$libresoc.v:141858$5743_Y + connect \$211 $ternary$libresoc.v:141859$5744_Y + connect \$213 $ternary$libresoc.v:141860$5745_Y + connect \$215 $ternary$libresoc.v:141861$5746_Y + connect \$217 $ternary$libresoc.v:141862$5747_Y + connect \$21 $eq$libresoc.v:141863$5748_Y + connect \$219 $ternary$libresoc.v:141864$5749_Y + connect \$221 $ternary$libresoc.v:141865$5750_Y + connect \$223 $ternary$libresoc.v:141866$5751_Y + connect \$225 $ternary$libresoc.v:141867$5752_Y + connect \$227 $ternary$libresoc.v:141868$5753_Y + connect \$229 $ternary$libresoc.v:141869$5754_Y + connect \$231 $ternary$libresoc.v:141870$5755_Y + connect \$233 $ternary$libresoc.v:141871$5756_Y + connect \$235 $ternary$libresoc.v:141872$5757_Y + connect \$237 $ternary$libresoc.v:141873$5758_Y + connect \$23 $or$libresoc.v:141874$5759_Y + connect \$239 $ternary$libresoc.v:141875$5760_Y + connect \$241 $ternary$libresoc.v:141876$5761_Y + connect \$243 $ternary$libresoc.v:141877$5762_Y + connect \$245 $ternary$libresoc.v:141878$5763_Y + connect \$247 $ternary$libresoc.v:141879$5764_Y + connect \$249 $ternary$libresoc.v:141880$5765_Y + connect \$251 $ternary$libresoc.v:141881$5766_Y + connect \$253 $ternary$libresoc.v:141882$5767_Y + connect \$255 $ternary$libresoc.v:141883$5768_Y + connect \$257 $ternary$libresoc.v:141884$5769_Y + connect \$25 $eq$libresoc.v:141885$5770_Y + connect \$259 $ternary$libresoc.v:141886$5771_Y + connect \$261 $ternary$libresoc.v:141887$5772_Y + connect \$263 $ternary$libresoc.v:141888$5773_Y + connect \$265 $ternary$libresoc.v:141889$5774_Y + connect \$267 $ternary$libresoc.v:141890$5775_Y + connect \$269 $ternary$libresoc.v:141891$5776_Y + connect \$271 $ternary$libresoc.v:141892$5777_Y + connect \$273 $ternary$libresoc.v:141893$5778_Y + connect \$275 $ternary$libresoc.v:141894$5779_Y + connect \$277 $ternary$libresoc.v:141895$5780_Y + connect \$27 $or$libresoc.v:141896$5781_Y + connect \$279 $ternary$libresoc.v:141897$5782_Y + connect \$281 $ternary$libresoc.v:141898$5783_Y + connect \$283 $ternary$libresoc.v:141899$5784_Y + connect \$285 $ternary$libresoc.v:141900$5785_Y + connect \$287 $ternary$libresoc.v:141901$5786_Y + connect \$289 $ternary$libresoc.v:141902$5787_Y + connect \$291 $ternary$libresoc.v:141903$5788_Y + connect \$293 $ternary$libresoc.v:141904$5789_Y + connect \$295 $ternary$libresoc.v:141905$5790_Y + connect \$297 $ternary$libresoc.v:141906$5791_Y + connect \$29 $and$libresoc.v:141907$5792_Y + connect \$299 $ternary$libresoc.v:141908$5793_Y + connect \$301 $ternary$libresoc.v:141909$5794_Y + connect \$303 $ternary$libresoc.v:141910$5795_Y + connect \$305 $ternary$libresoc.v:141911$5796_Y + connect \$307 $ternary$libresoc.v:141912$5797_Y + connect \$309 $ternary$libresoc.v:141913$5798_Y + connect \$311 $ternary$libresoc.v:141914$5799_Y + connect \$313 $ternary$libresoc.v:141915$5800_Y + connect \$315 $ternary$libresoc.v:141916$5801_Y + connect \$317 $ternary$libresoc.v:141917$5802_Y + connect \$31 $and$libresoc.v:141918$5803_Y + connect \$319 $ternary$libresoc.v:141919$5804_Y + connect \$321 $ternary$libresoc.v:141920$5805_Y + connect \$323 $ternary$libresoc.v:141921$5806_Y + connect \$325 $ternary$libresoc.v:141922$5807_Y + connect \$327 $ternary$libresoc.v:141923$5808_Y + connect \$329 $ternary$libresoc.v:141924$5809_Y + connect \$331 $ternary$libresoc.v:141925$5810_Y + connect \$333 $ternary$libresoc.v:141926$5811_Y + connect \$335 $ternary$libresoc.v:141927$5812_Y + connect \$337 $ternary$libresoc.v:141928$5813_Y + connect \$33 $eq$libresoc.v:141929$5814_Y + connect \$339 $ternary$libresoc.v:141930$5815_Y + connect \$341 $ternary$libresoc.v:141931$5816_Y + connect \$343 $ternary$libresoc.v:141932$5817_Y + connect \$345 $ternary$libresoc.v:141933$5818_Y + connect \$347 $ternary$libresoc.v:141934$5819_Y + connect \$349 $ternary$libresoc.v:141935$5820_Y + connect \$351 $ternary$libresoc.v:141936$5821_Y + connect \$353 $ternary$libresoc.v:141937$5822_Y + connect \$355 $ternary$libresoc.v:141938$5823_Y + connect \$357 $ternary$libresoc.v:141939$5824_Y + connect \$35 $eq$libresoc.v:141940$5825_Y + connect \$359 $eq$libresoc.v:141941$5826_Y + connect \$361 $eq$libresoc.v:141942$5827_Y + connect \$363 $or$libresoc.v:141943$5828_Y + connect \$365 $eq$libresoc.v:141944$5829_Y + connect \$367 $or$libresoc.v:141945$5830_Y + connect \$369 $and$libresoc.v:141946$5831_Y + connect \$371 $eq$libresoc.v:141947$5832_Y + connect \$373 $ne$libresoc.v:141948$5833_Y + connect \$375 $and$libresoc.v:141949$5834_Y + connect \$377 $ne$libresoc.v:141950$5835_Y + connect \$37 $or$libresoc.v:141951$5836_Y + connect \$379 $and$libresoc.v:141952$5837_Y + connect \$381 $ne$libresoc.v:141953$5838_Y + connect \$383 $and$libresoc.v:141954$5839_Y + connect \$385 $not$libresoc.v:141955$5840_Y + connect \$387 $and$libresoc.v:141956$5841_Y + connect \$389 $eq$libresoc.v:141957$5842_Y + connect \$391 $ne$libresoc.v:141958$5843_Y + connect \$393 $and$libresoc.v:141959$5844_Y + connect \$395 $ne$libresoc.v:141960$5845_Y + connect \$397 $and$libresoc.v:141961$5846_Y + connect \$3 $eq$libresoc.v:141962$5847_Y + connect \$39 $eq$libresoc.v:141963$5848_Y + connect \$399 $ne$libresoc.v:141964$5849_Y + connect \$401 $and$libresoc.v:141965$5850_Y + connect \$403 $not$libresoc.v:141966$5851_Y + connect \$405 $and$libresoc.v:141967$5852_Y + connect \$407 $eq$libresoc.v:141968$5853_Y + connect \$409 $eq$libresoc.v:141969$5854_Y + connect \$411 $ne$libresoc.v:141970$5855_Y + connect \$413 $and$libresoc.v:141971$5856_Y + connect \$415 $ne$libresoc.v:141972$5857_Y + connect \$417 $and$libresoc.v:141973$5858_Y + connect \$41 $or$libresoc.v:141974$5859_Y + connect \$419 $ne$libresoc.v:141975$5860_Y + connect \$421 $and$libresoc.v:141976$5861_Y + connect \$423 $not$libresoc.v:141977$5862_Y + connect \$425 $and$libresoc.v:141978$5863_Y + connect \$427 $eq$libresoc.v:141979$5864_Y + connect \$429 $ne$libresoc.v:141980$5865_Y + connect \$431 $and$libresoc.v:141981$5866_Y + connect \$433 $ne$libresoc.v:141982$5867_Y + connect \$435 $and$libresoc.v:141983$5868_Y + connect \$437 $ne$libresoc.v:141984$5869_Y + connect \$43 $and$libresoc.v:141985$5870_Y + connect \$439 $and$libresoc.v:141986$5871_Y + connect \$441 $not$libresoc.v:141987$5872_Y + connect \$443 $and$libresoc.v:141988$5873_Y + connect \$445 $eq$libresoc.v:141989$5874_Y + connect \$447 $eq$libresoc.v:141990$5875_Y + connect \$449 $ne$libresoc.v:141991$5876_Y + connect \$451 $and$libresoc.v:141992$5877_Y + connect \$453 $ne$libresoc.v:141993$5878_Y + connect \$455 $and$libresoc.v:141994$5879_Y + connect \$457 $ne$libresoc.v:141995$5880_Y + connect \$45 $and$libresoc.v:141996$5881_Y + connect \$459 $and$libresoc.v:141997$5882_Y + connect \$461 $not$libresoc.v:141998$5883_Y + connect \$463 $and$libresoc.v:141999$5884_Y + connect \$465 $eq$libresoc.v:142000$5885_Y + connect \$467 $ne$libresoc.v:142001$5886_Y + connect \$469 $and$libresoc.v:142002$5887_Y + connect \$471 $ne$libresoc.v:142003$5888_Y + connect \$473 $and$libresoc.v:142004$5889_Y + connect \$475 $ne$libresoc.v:142005$5890_Y + connect \$477 $and$libresoc.v:142006$5891_Y + connect \$47 $eq$libresoc.v:142007$5892_Y + connect \$479 $not$libresoc.v:142008$5893_Y + connect \$481 $and$libresoc.v:142009$5894_Y + connect \$484 $eq$libresoc.v:142010$5895_Y + connect \$483 $not$libresoc.v:142011$5896_Y + connect \$487 $eq$libresoc.v:142012$5897_Y + connect \$489 $eq$libresoc.v:142013$5898_Y + connect \$491 $or$libresoc.v:142014$5899_Y + connect \$493 $eq$libresoc.v:142015$5900_Y + connect \$496 $add$libresoc.v:142016$5901_Y + connect \$49 $eq$libresoc.v:142017$5902_Y + connect \$499 $add$libresoc.v:142018$5903_Y + connect \$501 $pos$libresoc.v:142019$5905_Y + connect \$504 $eq$libresoc.v:142020$5906_Y + connect \$506 $eq$libresoc.v:142021$5907_Y + connect \$508 $or$libresoc.v:142022$5908_Y + connect \$510 $eq$libresoc.v:142023$5909_Y + connect \$513 $add$libresoc.v:142024$5910_Y + connect \$516 $add$libresoc.v:142025$5911_Y + connect \$51 $ternary$libresoc.v:142026$5912_Y + connect \$53 $ternary$libresoc.v:142027$5913_Y + connect \$55 $ternary$libresoc.v:142028$5914_Y + connect \$57 $ternary$libresoc.v:142029$5915_Y + connect \$5 $or$libresoc.v:142030$5916_Y + connect \$59 $ternary$libresoc.v:142031$5917_Y + connect \$61 $ternary$libresoc.v:142032$5918_Y + connect \$63 $ternary$libresoc.v:142033$5919_Y + connect \$65 $ternary$libresoc.v:142034$5920_Y + connect \$67 $ternary$libresoc.v:142035$5921_Y + connect \$69 $ternary$libresoc.v:142036$5922_Y + connect \$71 $ternary$libresoc.v:142037$5923_Y + connect \$73 $ternary$libresoc.v:142038$5924_Y + connect \$75 $ternary$libresoc.v:142039$5925_Y + connect \$77 $ternary$libresoc.v:142040$5926_Y + connect \$7 $and$libresoc.v:142041$5927_Y + connect \$79 $ternary$libresoc.v:142042$5928_Y + connect \$81 $ternary$libresoc.v:142043$5929_Y + connect \$83 $ternary$libresoc.v:142044$5930_Y + connect \$85 $ternary$libresoc.v:142045$5931_Y + connect \$87 $ternary$libresoc.v:142046$5932_Y + connect \$89 $ternary$libresoc.v:142047$5933_Y + connect \$91 $ternary$libresoc.v:142048$5934_Y + connect \$93 $ternary$libresoc.v:142049$5935_Y + connect \$95 $ternary$libresoc.v:142050$5936_Y + connect \$97 $ternary$libresoc.v:142051$5937_Y + connect \$495 \$496 + connect \$498 \$499 + connect \$512 \$513 + connect \$515 \$516 + connect \sr5__ie 1'0 + connect \sr0__i \sr0__o + connect \dmi0__we_i \$510 + connect \dmi0__req_i \$508 + connect \dmi0_addrsr__i \$501 + connect \jtag_wb__we \$493 + connect \jtag_wb__stb \$491 + connect \jtag_wb__cyc \$483 + connect \jtag_wb__sel 1'1 + connect \jtag_wb_addrsr__i \jtag_wb__adr + connect \sr5_update \$477 + connect \sr5_shift \$473 + connect \sr5_capture \$469 + connect \sr5_isir \$465 + connect \sr5__o \sr5_reg + connect \dmi0_datasr_update \$459 + connect \dmi0_datasr_shift \$455 + connect \dmi0_datasr_capture \$451 + connect \dmi0_datasr_isir { \$447 \$445 } + connect \dmi0_datasr__o \dmi0_datasr_reg + connect \dmi0_addrsr_update \$439 + connect \dmi0_addrsr_shift \$435 + connect \dmi0_addrsr_capture \$431 + connect \dmi0_addrsr_isir \$427 + connect \dmi0_addrsr__o \dmi0_addrsr_reg + connect \jtag_wb_datasr_update \$421 + connect \jtag_wb_datasr_shift \$417 + connect \jtag_wb_datasr_capture \$413 + connect \jtag_wb_datasr_isir { \$409 \$407 } + connect \jtag_wb_datasr__o \jtag_wb_datasr_reg + connect \jtag_wb_addrsr_update \$401 + connect \jtag_wb_addrsr_shift \$397 + connect \jtag_wb_addrsr_capture \$393 + connect \jtag_wb_addrsr_isir \$389 + connect \jtag_wb_addrsr__o \jtag_wb_addrsr_reg + connect \sr0_update \$383 + connect \sr0_shift \$379 + connect \sr0_capture \$375 + connect \sr0_isir \$371 + connect \sr0__o \sr0_reg + connect \sdr_dq_15__pad__oe \$357 + connect \sdr_dq_15__pad__o \$355 + connect \sdr_dq_15__core__i \$353 + connect \sdr_dq_14__pad__oe \$351 + connect \sdr_dq_14__pad__o \$349 + connect \sdr_dq_14__core__i \$347 + connect \sdr_dq_13__pad__oe \$345 + connect \sdr_dq_13__pad__o \$343 + connect \sdr_dq_13__core__i \$341 + connect \sdr_dq_12__pad__oe \$339 + connect \sdr_dq_12__pad__o \$337 + connect \sdr_dq_12__core__i \$335 + connect \sdr_dq_11__pad__oe \$333 + connect \sdr_dq_11__pad__o \$331 + connect \sdr_dq_11__core__i \$329 + connect \sdr_dq_10__pad__oe \$327 + connect \sdr_dq_10__pad__o \$325 + connect \sdr_dq_10__core__i \$323 + connect \sdr_dq_9__pad__oe \$321 + connect \sdr_dq_9__pad__o \$319 + connect \sdr_dq_9__core__i \$317 + connect \sdr_dq_8__pad__oe \$315 + connect \sdr_dq_8__pad__o \$313 + connect \sdr_dq_8__core__i \$311 + connect \sdr_dm_1__pad__oe \$309 + connect \sdr_dm_1__pad__o \$307 + connect \sdr_dm_1__core__i \$305 + connect \sdr_a_12__pad__o \$303 + connect \sdr_a_11__pad__o \$301 + connect \sdr_a_10__pad__o \$299 + connect \sdr_cs_n__pad__o \$297 + connect \sdr_we_n__pad__o \$295 + connect \sdr_cas_n__pad__o \$293 + connect \sdr_ras_n__pad__o \$291 + connect \sdr_cke__pad__o \$289 + connect \sdr_clock__pad__o \$287 + connect \sdr_ba_1__pad__o \$285 + connect \sdr_ba_0__pad__o \$283 + connect \sdr_a_9__pad__o \$281 + connect \sdr_a_8__pad__o \$279 + connect \sdr_a_7__pad__o \$277 + connect \sdr_a_6__pad__o \$275 + connect \sdr_a_5__pad__o \$273 + connect \sdr_a_4__pad__o \$271 + connect \sdr_a_3__pad__o \$269 + connect \sdr_a_2__pad__o \$267 + connect \sdr_a_1__pad__o \$265 + connect \sdr_a_0__pad__o \$263 + connect \sdr_dq_7__pad__oe \$261 + connect \sdr_dq_7__pad__o \$259 + connect \sdr_dq_7__core__i \$257 + connect \sdr_dq_6__pad__oe \$255 + connect \sdr_dq_6__pad__o \$253 + connect \sdr_dq_6__core__i \$251 + connect \sdr_dq_5__pad__oe \$249 + connect \sdr_dq_5__pad__o \$247 + connect \sdr_dq_5__core__i \$245 + connect \sdr_dq_4__pad__oe \$243 + connect \sdr_dq_4__pad__o \$241 + connect \sdr_dq_4__core__i \$239 + connect \sdr_dq_3__pad__oe \$237 + connect \sdr_dq_3__pad__o \$235 + connect \sdr_dq_3__core__i \$233 + connect \sdr_dq_2__pad__oe \$231 + connect \sdr_dq_2__pad__o \$229 + connect \sdr_dq_2__core__i \$227 + connect \sdr_dq_1__pad__oe \$225 + connect \sdr_dq_1__pad__o \$223 + connect \sdr_dq_1__core__i \$221 + connect \sdr_dq_0__pad__oe \$219 + connect \sdr_dq_0__pad__o \$217 + connect \sdr_dq_0__core__i \$215 + connect \sdr_dm_0__pad__o \$213 + connect \sd0_data3__pad__oe \$211 + connect \sd0_data3__pad__o \$209 + connect \sd0_data3__core__i \$207 + connect \sd0_data2__pad__oe \$205 + connect \sd0_data2__pad__o \$203 + connect \sd0_data2__core__i \$201 + connect \sd0_data1__pad__oe \$199 + connect \sd0_data1__pad__o \$197 + connect \sd0_data1__core__i \$195 + connect \sd0_data0__pad__oe \$193 + connect \sd0_data0__pad__o \$191 + connect \sd0_data0__core__i \$189 + connect \sd0_clk__pad__o \$187 + connect \sd0_cmd__pad__oe \$185 + connect \sd0_cmd__pad__o \$183 + connect \sd0_cmd__core__i \$181 + connect \pwm_1__pad__o \$179 + connect \pwm_0__pad__o \$177 + connect \mtwi_scl__pad__o \$175 + connect \mtwi_sda__pad__oe \$173 + connect \mtwi_sda__pad__o \$171 + connect \mtwi_sda__core__i \$169 + connect \mspi1_miso__core__i \$167 + connect \mspi1_mosi__pad__o \$165 + connect \mspi1_cs_n__pad__o \$163 + connect \mspi1_clk__pad__o \$161 + connect \mspi0_miso__core__i \$159 + connect \mspi0_mosi__pad__o \$157 + connect \mspi0_cs_n__pad__o \$155 + connect \mspi0_clk__pad__o \$153 + connect \gpio_s7__pad__oe \$151 + connect \gpio_s7__pad__o \$149 + connect \gpio_s7__core__i \$147 + connect \gpio_s6__pad__oe \$145 + connect \gpio_s6__pad__o \$143 + connect \gpio_s6__core__i \$141 + connect \gpio_s5__pad__oe \$139 + connect \gpio_s5__pad__o \$137 + connect \gpio_s5__core__i \$135 + connect \gpio_s4__pad__oe \$133 + connect \gpio_s4__pad__o \$131 + connect \gpio_s4__core__i \$129 + connect \gpio_s3__pad__oe \$127 + connect \gpio_s3__pad__o \$125 + connect \gpio_s3__core__i \$123 + connect \gpio_s2__pad__oe \$121 + connect \gpio_s2__pad__o \$119 + connect \gpio_s2__core__i \$117 + connect \gpio_s1__pad__oe \$115 + connect \gpio_s1__pad__o \$113 + connect \gpio_s1__core__i \$111 + connect \gpio_s0__pad__oe \$109 + connect \gpio_s0__pad__o \$107 + connect \gpio_s0__core__i \$105 + connect \gpio_e15__pad__oe \$103 + connect \gpio_e15__pad__o \$101 + connect \gpio_e15__core__i \$99 + connect \gpio_e14__pad__oe \$97 + connect \gpio_e14__pad__o \$95 + connect \gpio_e14__core__i \$93 + connect \gpio_e13__pad__oe \$91 + connect \gpio_e13__pad__o \$89 + connect \gpio_e13__core__i \$87 + connect \gpio_e12__pad__oe \$85 + connect \gpio_e12__pad__o \$83 + connect \gpio_e12__core__i \$81 + connect \gpio_e11__pad__oe \$79 + connect \gpio_e11__pad__o \$77 + connect \gpio_e11__core__i \$75 + connect \gpio_e10__pad__oe \$73 + connect \gpio_e10__pad__o \$71 + connect \gpio_e10__core__i \$69 + connect \gpio_e9__pad__oe \$67 + connect \gpio_e9__pad__o \$65 + connect \gpio_e9__core__i \$63 + connect \gpio_e8__pad__oe \$61 + connect \gpio_e8__pad__o \$59 + connect \gpio_e8__core__i \$57 + connect \eint_2__core__i \$55 + connect \eint_1__core__i \$53 + connect \eint_0__core__i \$51 + connect \io_bd2core \$49 + connect \io_bd2io \$47 + connect \io_update \$45 + connect \io_shift \$31 + connect \io_capture \$17 + connect \_idblock_id_bypass \$9 + connect \_idblock_select_id \$7 +end +attribute \src "libresoc.v:143083.1-143272.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.l0" +attribute \generator "nMigen" +module \l0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 31 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire input 23 \dbus__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 45 output 28 \dbus__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire output 22 \dbus__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 64 input 27 \dbus__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 64 output 30 \dbus__dat_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire input 24 \dbus__err + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 8 output 26 \dbus__sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire output 25 \dbus__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire output 29 \dbus__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 96 input 6 \ldst_port0_addr_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire input 7 \ldst_port0_addr_i_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:109" + wire output 16 \ldst_port0_addr_ok_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:105" + wire output 2 \ldst_port0_busy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102" + wire width 4 input 5 \ldst_port0_data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire output 8 \ldst_port0_exc_$signal + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire output 9 \ldst_port0_exc_$signal$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire output 10 \ldst_port0_exc_$signal$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire output 11 \ldst_port0_exc_$signal$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire output 12 \ldst_port0_exc_$signal$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire output 13 \ldst_port0_exc_$signal$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire output 14 \ldst_port0_exc_$signal$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire output 15 \ldst_port0_exc_$signal$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:98" + wire input 3 \ldst_port0_is_ld_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" + wire input 4 \ldst_port0_is_st_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 17 \ldst_port0_ld_data_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 18 \ldst_port0_ld_data_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 input 19 \ldst_port0_st_data_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire input 20 \ldst_port0_st_data_i_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 48 \pimem_ldst_port0_addr_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pimem_ldst_port0_addr_i_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:109" + wire \pimem_ldst_port0_addr_ok_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:105" + wire \pimem_ldst_port0_busy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102" + wire width 4 \pimem_ldst_port0_data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \pimem_ldst_port0_exc_$signal + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:98" + wire \pimem_ldst_port0_is_ld_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" + wire \pimem_ldst_port0_is_st_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \pimem_ldst_port0_ld_data_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pimem_ldst_port0_ld_data_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \pimem_ldst_port0_st_data_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \pimem_ldst_port0_st_data_i_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:69" + wire width 64 \pimem_m_ld_data_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:61" + wire \pimem_m_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:50" + wire width 48 \pimem_x_addr_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:66" + wire \pimem_x_busy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:52" + wire \pimem_x_ld_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:51" + wire width 8 \pimem_x_mask_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:54" + wire width 64 \pimem_x_st_data_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:53" + wire \pimem_x_st_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:57" + wire \pimem_x_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:93" + wire input 21 \wb_dcache_en + attribute \module_not_derived 1 + attribute \src "libresoc.v:143188.12-143222.4" + cell \l0$130 \l0 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \ldst_port0_addr_i \ldst_port0_addr_i + connect \ldst_port0_addr_i$12 \pimem_ldst_port0_addr_i + connect \ldst_port0_addr_i_ok \ldst_port0_addr_i_ok + connect \ldst_port0_addr_i_ok$13 \pimem_ldst_port0_addr_i_ok + connect \ldst_port0_addr_ok_o \ldst_port0_addr_ok_o + connect \ldst_port0_addr_ok_o$14 \pimem_ldst_port0_addr_ok_o + connect \ldst_port0_busy_o \ldst_port0_busy_o + connect \ldst_port0_busy_o$10 \pimem_ldst_port0_busy_o + connect \ldst_port0_data_len \ldst_port0_data_len + connect \ldst_port0_data_len$11 \pimem_ldst_port0_data_len + connect \ldst_port0_exc_$signal \ldst_port0_exc_$signal + connect \ldst_port0_exc_$signal$1 \ldst_port0_exc_$signal$1 + connect \ldst_port0_exc_$signal$19 \pimem_ldst_port0_exc_$signal + connect \ldst_port0_exc_$signal$2 \ldst_port0_exc_$signal$2 + connect \ldst_port0_exc_$signal$3 \ldst_port0_exc_$signal$3 + connect \ldst_port0_exc_$signal$4 \ldst_port0_exc_$signal$4 + connect \ldst_port0_exc_$signal$5 \ldst_port0_exc_$signal$5 + connect \ldst_port0_exc_$signal$6 \ldst_port0_exc_$signal$6 + connect \ldst_port0_exc_$signal$7 \ldst_port0_exc_$signal$7 + connect \ldst_port0_is_ld_i \ldst_port0_is_ld_i + connect \ldst_port0_is_ld_i$8 \pimem_ldst_port0_is_ld_i + connect \ldst_port0_is_st_i \ldst_port0_is_st_i + connect \ldst_port0_is_st_i$9 \pimem_ldst_port0_is_st_i + connect \ldst_port0_ld_data_o \ldst_port0_ld_data_o + connect \ldst_port0_ld_data_o$15 \pimem_ldst_port0_ld_data_o + connect \ldst_port0_ld_data_o_ok \ldst_port0_ld_data_o_ok + connect \ldst_port0_ld_data_o_ok$16 \pimem_ldst_port0_ld_data_o_ok + connect \ldst_port0_st_data_i \ldst_port0_st_data_i + connect \ldst_port0_st_data_i$18 \pimem_ldst_port0_st_data_i + connect \ldst_port0_st_data_i_ok \ldst_port0_st_data_i_ok + connect \ldst_port0_st_data_i_ok$17 \pimem_ldst_port0_st_data_i_ok + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:143223.9-143245.4" + cell \lsmem \lsmem + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \dbus__ack \dbus__ack + connect \dbus__adr \dbus__adr + connect \dbus__cyc \dbus__cyc + connect \dbus__dat_r \dbus__dat_r + connect \dbus__dat_w \dbus__dat_w + connect \dbus__err \dbus__err + connect \dbus__sel \dbus__sel + connect \dbus__stb \dbus__stb + connect \dbus__we \dbus__we + connect \m_ld_data_o \pimem_m_ld_data_o + connect \m_valid_i \pimem_m_valid_i + connect \wb_dcache_en \wb_dcache_en + connect \x_addr_i \pimem_x_addr_i + connect \x_busy_o \pimem_x_busy_o + connect \x_ld_i \pimem_x_ld_i + connect \x_mask_i \pimem_x_mask_i + connect \x_st_data_i \pimem_x_st_data_i + connect \x_st_i \pimem_x_st_i + connect \x_valid_i \pimem_x_valid_i + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:143246.9-143270.4" + cell \pimem \pimem + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \ldst_port0_addr_i \pimem_ldst_port0_addr_i + connect \ldst_port0_addr_i_ok \pimem_ldst_port0_addr_i_ok + connect \ldst_port0_addr_ok_o \pimem_ldst_port0_addr_ok_o + connect \ldst_port0_busy_o \pimem_ldst_port0_busy_o + connect \ldst_port0_data_len \pimem_ldst_port0_data_len + connect \ldst_port0_exc_$signal \pimem_ldst_port0_exc_$signal + connect \ldst_port0_is_ld_i \pimem_ldst_port0_is_ld_i + connect \ldst_port0_is_st_i \pimem_ldst_port0_is_st_i + connect \ldst_port0_ld_data_o \pimem_ldst_port0_ld_data_o + connect \ldst_port0_ld_data_o_ok \pimem_ldst_port0_ld_data_o_ok + connect \ldst_port0_st_data_i \pimem_ldst_port0_st_data_i + connect \ldst_port0_st_data_i_ok \pimem_ldst_port0_st_data_i_ok + connect \m_ld_data_o \pimem_m_ld_data_o + connect \m_valid_i \pimem_m_valid_i + connect \x_addr_i \pimem_x_addr_i + connect \x_busy_o \pimem_x_busy_o + connect \x_ld_i \pimem_x_ld_i + connect \x_mask_i \pimem_x_mask_i + connect \x_st_data_i \pimem_x_st_data_i + connect \x_st_i \pimem_x_st_i + connect \x_valid_i \pimem_x_valid_i + end + connect \pimem_ldst_port0_exc_$signal 1'0 +end +attribute \src "libresoc.v:143276.1-143684.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.l0.l0" +attribute \generator "nMigen" +module \l0$130 + attribute \src "libresoc.v:143539.3-143553.6" + wire $0\idx_l$23$next[0:0]$6206 + attribute \src "libresoc.v:143439.3-143440.35" + wire $0\idx_l$23[0:0]$6173 + attribute \src "libresoc.v:143297.7-143297.24" + wire $0\idx_l$23[0:0]$6228 + attribute \src "libresoc.v:143594.3-143603.6" + wire $0\idx_l_r_idx_l[0:0] + attribute \src "libresoc.v:143584.3-143593.6" + wire $0\idx_l_s_idx_l[0:0] + attribute \src "libresoc.v:143277.7-143277.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:143460.3-143469.6" + wire width 48 $0\ldst_port0_addr_i$12[47:0]$6175 + attribute \src "libresoc.v:143470.3-143479.6" + wire $0\ldst_port0_addr_i_ok$13[0:0]$6178 + attribute \src "libresoc.v:143512.3-143521.6" + wire $0\ldst_port0_addr_ok_o[0:0] + attribute \src "libresoc.v:143502.3-143511.6" + wire $0\ldst_port0_busy_o[0:0] + attribute \src "libresoc.v:143574.3-143583.6" + wire $0\ldst_port0_cache_paradox[0:0] + attribute \src "libresoc.v:143649.3-143658.6" + wire width 4 $0\ldst_port0_data_len$11[3:0]$6223 + attribute \src "libresoc.v:143522.3-143538.6" + wire $0\ldst_port0_exc_$signal$1[0:0]$6190 + attribute \src "libresoc.v:143522.3-143538.6" + wire $0\ldst_port0_exc_$signal$2[0:0]$6191 + attribute \src "libresoc.v:143522.3-143538.6" + wire $0\ldst_port0_exc_$signal$3[0:0]$6192 + attribute \src "libresoc.v:143522.3-143538.6" + wire $0\ldst_port0_exc_$signal$4[0:0]$6193 + attribute \src "libresoc.v:143522.3-143538.6" + wire $0\ldst_port0_exc_$signal$5[0:0]$6194 + attribute \src "libresoc.v:143522.3-143538.6" + wire $0\ldst_port0_exc_$signal$6[0:0]$6195 + attribute \src "libresoc.v:143522.3-143538.6" + wire $0\ldst_port0_exc_$signal$7[0:0]$6196 + attribute \src "libresoc.v:143522.3-143538.6" + wire $0\ldst_port0_exc_$signal[0:0]$6189 + attribute \src "libresoc.v:143659.3-143668.6" + wire $0\ldst_port0_go_die_i[0:0] + attribute \src "libresoc.v:143629.3-143638.6" + wire $0\ldst_port0_is_ld_i$8[0:0]$6217 + attribute \src "libresoc.v:143639.3-143648.6" + wire $0\ldst_port0_is_st_i$9[0:0]$6220 + attribute \src "libresoc.v:143491.3-143501.6" + wire width 64 $0\ldst_port0_ld_data_o[63:0] + attribute \src "libresoc.v:143491.3-143501.6" + wire $0\ldst_port0_ld_data_o_ok[0:0] + attribute \src "libresoc.v:143564.3-143573.6" + wire $0\ldst_port0_ldst_error[0:0] + attribute \src "libresoc.v:143554.3-143563.6" + wire $0\ldst_port0_mmu_done[0:0] + attribute \src "libresoc.v:143480.3-143490.6" + wire width 64 $0\ldst_port0_st_data_i$18[63:0]$6181 + attribute \src "libresoc.v:143480.3-143490.6" + wire $0\ldst_port0_st_data_i_ok$17[0:0]$6182 + attribute \src "libresoc.v:143437.3-143438.36" + wire $0\reset_delay[0:0] + attribute \src "libresoc.v:143619.3-143628.6" + wire $0\reset_l_r_reset[0:0] + attribute \src "libresoc.v:143604.3-143618.6" + wire $0\reset_l_s_reset[0:0] + attribute \src "libresoc.v:143539.3-143553.6" + wire $1\idx_l$23$next[0:0]$6207 + attribute \src "libresoc.v:143594.3-143603.6" + wire $1\idx_l_r_idx_l[0:0] + attribute \src "libresoc.v:143584.3-143593.6" + wire $1\idx_l_s_idx_l[0:0] + attribute \src "libresoc.v:143460.3-143469.6" + wire width 48 $1\ldst_port0_addr_i$12[47:0]$6176 + attribute \src "libresoc.v:143470.3-143479.6" + wire $1\ldst_port0_addr_i_ok$13[0:0]$6179 + attribute \src "libresoc.v:143512.3-143521.6" + wire $1\ldst_port0_addr_ok_o[0:0] + attribute \src "libresoc.v:143502.3-143511.6" + wire $1\ldst_port0_busy_o[0:0] + attribute \src "libresoc.v:143574.3-143583.6" + wire $1\ldst_port0_cache_paradox[0:0] + attribute \src "libresoc.v:143649.3-143658.6" + wire width 4 $1\ldst_port0_data_len$11[3:0]$6224 + attribute \src "libresoc.v:143522.3-143538.6" + wire $1\ldst_port0_exc_$signal$1[0:0]$6198 + attribute \src "libresoc.v:143522.3-143538.6" + wire $1\ldst_port0_exc_$signal$2[0:0]$6199 + attribute \src "libresoc.v:143522.3-143538.6" + wire $1\ldst_port0_exc_$signal$3[0:0]$6200 + attribute \src "libresoc.v:143522.3-143538.6" + wire $1\ldst_port0_exc_$signal$4[0:0]$6201 + attribute \src "libresoc.v:143522.3-143538.6" + wire $1\ldst_port0_exc_$signal$5[0:0]$6202 + attribute \src "libresoc.v:143522.3-143538.6" + wire $1\ldst_port0_exc_$signal$6[0:0]$6203 + attribute \src "libresoc.v:143522.3-143538.6" + wire $1\ldst_port0_exc_$signal$7[0:0]$6204 + attribute \src "libresoc.v:143522.3-143538.6" + wire $1\ldst_port0_exc_$signal[0:0]$6197 + attribute \src "libresoc.v:143659.3-143668.6" + wire $1\ldst_port0_go_die_i[0:0] + attribute \src "libresoc.v:143629.3-143638.6" + wire $1\ldst_port0_is_ld_i$8[0:0]$6218 + attribute \src "libresoc.v:143639.3-143648.6" + wire $1\ldst_port0_is_st_i$9[0:0]$6221 + attribute \src "libresoc.v:143491.3-143501.6" + wire width 64 $1\ldst_port0_ld_data_o[63:0] + attribute \src "libresoc.v:143491.3-143501.6" + wire $1\ldst_port0_ld_data_o_ok[0:0] + attribute \src "libresoc.v:143564.3-143573.6" + wire $1\ldst_port0_ldst_error[0:0] + attribute \src "libresoc.v:143554.3-143563.6" + wire $1\ldst_port0_mmu_done[0:0] + attribute \src "libresoc.v:143480.3-143490.6" + wire width 64 $1\ldst_port0_st_data_i$18[63:0]$6183 + attribute \src "libresoc.v:143480.3-143490.6" + wire $1\ldst_port0_st_data_i_ok$17[0:0]$6184 + attribute \src "libresoc.v:143424.7-143424.25" + wire $1\reset_delay[0:0] + attribute \src "libresoc.v:143619.3-143628.6" + wire $1\reset_l_r_reset[0:0] + attribute \src "libresoc.v:143604.3-143618.6" + wire $1\reset_l_s_reset[0:0] + attribute \src "libresoc.v:143539.3-143553.6" + wire $2\idx_l$23$next[0:0]$6208 + attribute \src "libresoc.v:143604.3-143618.6" + wire $2\reset_l_s_reset[0:0] + attribute \src "libresoc.v:143435.18-143435.103" + wire $not$libresoc.v:143435$6169_Y + attribute \src "libresoc.v:143436.18-143436.118" + wire $not$libresoc.v:143436$6170_Y + attribute \src "libresoc.v:143433.18-143433.134" + wire $or$libresoc.v:143433$6167_Y + attribute \src "libresoc.v:143434.18-143434.120" + wire $ternary$libresoc.v:143434$6168_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:262" + wire \$20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" + wire \$22 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" + wire \$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:278" + wire \$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:288" + wire \$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:136" + wire width 96 \$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:136" + wire width 96 \$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 33 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" + wire \idx_l$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" + wire \idx_l$23$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire \idx_l_q_idx_l + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \idx_l_r_idx_l + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire \idx_l_s_idx_l + attribute \src "libresoc.v:143277.7-143277.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 96 input 6 \ldst_port0_addr_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 48 output 25 \ldst_port0_addr_i$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire input 7 \ldst_port0_addr_i_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 26 \ldst_port0_addr_i_ok$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:109" + wire output 16 \ldst_port0_addr_ok_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:109" + wire input 27 \ldst_port0_addr_ok_o$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:105" + wire output 2 \ldst_port0_busy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:105" + wire input 23 \ldst_port0_busy_o$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:128" + wire \ldst_port0_cache_paradox + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:128" + wire \ldst_port0_cache_paradox$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102" + wire width 4 input 5 \ldst_port0_data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102" + wire width 4 output 24 \ldst_port0_data_len$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire output 8 \ldst_port0_exc_$signal + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire output 9 \ldst_port0_exc_$signal$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire input 32 \ldst_port0_exc_$signal$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire output 10 \ldst_port0_exc_$signal$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire output 11 \ldst_port0_exc_$signal$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \ldst_port0_exc_$signal$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \ldst_port0_exc_$signal$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \ldst_port0_exc_$signal$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \ldst_port0_exc_$signal$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \ldst_port0_exc_$signal$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \ldst_port0_exc_$signal$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \ldst_port0_exc_$signal$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire output 12 \ldst_port0_exc_$signal$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire output 13 \ldst_port0_exc_$signal$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire output 14 \ldst_port0_exc_$signal$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire output 15 \ldst_port0_exc_$signal$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:106" + wire \ldst_port0_go_die_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:106" + wire \ldst_port0_go_die_i$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:98" + wire input 3 \ldst_port0_is_ld_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:98" + wire output 21 \ldst_port0_is_ld_i$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" + wire input 4 \ldst_port0_is_st_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" + wire output 22 \ldst_port0_is_st_i$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 17 \ldst_port0_ld_data_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 input 28 \ldst_port0_ld_data_o$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 18 \ldst_port0_ld_data_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire input 29 \ldst_port0_ld_data_o_ok$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:126" + wire \ldst_port0_ldst_error + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:126" + wire \ldst_port0_ldst_error$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:123" + wire \ldst_port0_mmu_done + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:123" + wire \ldst_port0_mmu_done$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 input 19 \ldst_port0_st_data_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 31 \ldst_port0_st_data_i$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire input 20 \ldst_port0_st_data_i_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 30 \ldst_port0_st_data_i_ok$17 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire \pick_i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire \pick_n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire \pick_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:292" + wire \reset_delay + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:292" + wire \reset_delay$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire \reset_l_q_reset + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \reset_l_r_reset + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire \reset_l_s_reset + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:278" + cell $not $not$libresoc.v:143435$6169 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \pick_n + connect \Y $not$libresoc.v:143435$6169_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:288" + cell $not $not$libresoc.v:143436$6170 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ldst_port0_busy_o$10 + connect \Y $not$libresoc.v:143436$6170_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:262" + cell $or $or$libresoc.v:143433$6167 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ldst_port0_is_ld_i + connect \B \ldst_port0_is_st_i + connect \Y $or$libresoc.v:143433$6167_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" + cell $mux $ternary$libresoc.v:143434$6168 + parameter \WIDTH 1 + connect \A \idx_l$23 + connect \B \pick_o + connect \S \idx_l_q_idx_l + connect \Y $ternary$libresoc.v:143434$6168_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:143441.9-143447.4" + cell \idx_l \idx_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_idx_l \idx_l_q_idx_l + connect \r_idx_l \idx_l_r_idx_l + connect \s_idx_l \idx_l_s_idx_l + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:143448.8-143452.4" + cell \pick \pick + connect \i \pick_i + connect \n \pick_n + connect \o \pick_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:143453.17-143459.4" + cell \reset_l$131 \reset_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_reset \reset_l_q_reset + connect \r_reset \reset_l_r_reset + connect \s_reset \reset_l_s_reset + end + attribute \src "libresoc.v:143277.7-143277.20" + process $proc$libresoc.v:143277$6226 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:143297.7-143297.24" + process $proc$libresoc.v:143297$6227 + assign { } { } + assign $0\idx_l$23[0:0]$6228 1'0 + sync always + sync init + update \idx_l$23 $0\idx_l$23[0:0]$6228 + end + attribute \src "libresoc.v:143424.7-143424.25" + process $proc$libresoc.v:143424$6229 + assign { } { } + assign $1\reset_delay[0:0] 1'0 + sync always + sync init + update \reset_delay $1\reset_delay[0:0] + end + attribute \src "libresoc.v:143437.3-143438.36" + process $proc$libresoc.v:143437$6171 + assign { } { } + assign $0\reset_delay[0:0] \reset_l_q_reset + sync posedge \coresync_clk + update \reset_delay $0\reset_delay[0:0] + end + attribute \src "libresoc.v:143439.3-143440.35" + process $proc$libresoc.v:143439$6172 + assign { } { } + assign $0\idx_l$23[0:0]$6173 \idx_l$23$next + sync posedge \coresync_clk + update \idx_l$23 $0\idx_l$23[0:0]$6173 + end + attribute \src "libresoc.v:143460.3-143469.6" + process $proc$libresoc.v:143460$6174 + assign { } { } + assign { } { } + assign $0\ldst_port0_addr_i$12[47:0]$6175 $1\ldst_port0_addr_i$12[47:0]$6176 + attribute \src "libresoc.v:143461.5-143461.29" + switch \initial + attribute \src "libresoc.v:143461.9-143461.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" + switch \idx_l_q_idx_l + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ldst_port0_addr_i$12[47:0]$6176 \$32 [47:0] + case + assign $1\ldst_port0_addr_i$12[47:0]$6176 48'000000000000000000000000000000000000000000000000 + end + sync always + update \ldst_port0_addr_i$12 $0\ldst_port0_addr_i$12[47:0]$6175 + end + attribute \src "libresoc.v:143470.3-143479.6" + process $proc$libresoc.v:143470$6177 + assign { } { } + assign { } { } + assign $0\ldst_port0_addr_i_ok$13[0:0]$6178 $1\ldst_port0_addr_i_ok$13[0:0]$6179 + attribute \src "libresoc.v:143471.5-143471.29" + switch \initial + attribute \src "libresoc.v:143471.9-143471.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" + switch \idx_l_q_idx_l + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ldst_port0_addr_i_ok$13[0:0]$6179 \ldst_port0_addr_i_ok + case + assign $1\ldst_port0_addr_i_ok$13[0:0]$6179 1'0 + end + sync always + update \ldst_port0_addr_i_ok$13 $0\ldst_port0_addr_i_ok$13[0:0]$6178 + end + attribute \src "libresoc.v:143480.3-143490.6" + process $proc$libresoc.v:143480$6180 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\ldst_port0_st_data_i$18[63:0]$6181 $1\ldst_port0_st_data_i$18[63:0]$6183 + assign $0\ldst_port0_st_data_i_ok$17[0:0]$6182 $1\ldst_port0_st_data_i_ok$17[0:0]$6184 + attribute \src "libresoc.v:143481.5-143481.29" + switch \initial + attribute \src "libresoc.v:143481.9-143481.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" + switch \idx_l_q_idx_l + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\ldst_port0_st_data_i_ok$17[0:0]$6184 $1\ldst_port0_st_data_i$18[63:0]$6183 } { \ldst_port0_st_data_i_ok \ldst_port0_st_data_i } + case + assign $1\ldst_port0_st_data_i$18[63:0]$6183 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\ldst_port0_st_data_i_ok$17[0:0]$6184 1'0 + end + sync always + update \ldst_port0_st_data_i$18 $0\ldst_port0_st_data_i$18[63:0]$6181 + update \ldst_port0_st_data_i_ok$17 $0\ldst_port0_st_data_i_ok$17[0:0]$6182 + end + attribute \src "libresoc.v:143491.3-143501.6" + process $proc$libresoc.v:143491$6185 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\ldst_port0_ld_data_o[63:0] $1\ldst_port0_ld_data_o[63:0] + assign $0\ldst_port0_ld_data_o_ok[0:0] $1\ldst_port0_ld_data_o_ok[0:0] + attribute \src "libresoc.v:143492.5-143492.29" + switch \initial + attribute \src "libresoc.v:143492.9-143492.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" + switch \idx_l_q_idx_l + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\ldst_port0_ld_data_o_ok[0:0] $1\ldst_port0_ld_data_o[63:0] } { \ldst_port0_ld_data_o_ok$16 \ldst_port0_ld_data_o$15 } + case + assign $1\ldst_port0_ld_data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\ldst_port0_ld_data_o_ok[0:0] 1'0 + end + sync always + update \ldst_port0_ld_data_o $0\ldst_port0_ld_data_o[63:0] + update \ldst_port0_ld_data_o_ok $0\ldst_port0_ld_data_o_ok[0:0] + end + attribute \src "libresoc.v:143502.3-143511.6" + process $proc$libresoc.v:143502$6186 + assign { } { } + assign { } { } + assign $0\ldst_port0_busy_o[0:0] $1\ldst_port0_busy_o[0:0] + attribute \src "libresoc.v:143503.5-143503.29" + switch \initial + attribute \src "libresoc.v:143503.9-143503.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" + switch \idx_l_q_idx_l + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ldst_port0_busy_o[0:0] \ldst_port0_busy_o$10 + case + assign $1\ldst_port0_busy_o[0:0] 1'0 + end + sync always + update \ldst_port0_busy_o $0\ldst_port0_busy_o[0:0] + end + attribute \src "libresoc.v:143512.3-143521.6" + process $proc$libresoc.v:143512$6187 + assign { } { } + assign { } { } + assign $0\ldst_port0_addr_ok_o[0:0] $1\ldst_port0_addr_ok_o[0:0] + attribute \src "libresoc.v:143513.5-143513.29" + switch \initial + attribute \src "libresoc.v:143513.9-143513.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" + switch \idx_l_q_idx_l + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ldst_port0_addr_ok_o[0:0] \ldst_port0_addr_ok_o$14 + case + assign $1\ldst_port0_addr_ok_o[0:0] 1'0 + end + sync always + update \ldst_port0_addr_ok_o $0\ldst_port0_addr_ok_o[0:0] + end + attribute \src "libresoc.v:143522.3-143538.6" + process $proc$libresoc.v:143522$6188 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\ldst_port0_exc_$signal[0:0]$6189 $1\ldst_port0_exc_$signal[0:0]$6197 + assign $0\ldst_port0_exc_$signal$1[0:0]$6190 $1\ldst_port0_exc_$signal$1[0:0]$6198 + assign $0\ldst_port0_exc_$signal$2[0:0]$6191 $1\ldst_port0_exc_$signal$2[0:0]$6199 + assign $0\ldst_port0_exc_$signal$3[0:0]$6192 $1\ldst_port0_exc_$signal$3[0:0]$6200 + assign $0\ldst_port0_exc_$signal$4[0:0]$6193 $1\ldst_port0_exc_$signal$4[0:0]$6201 + assign $0\ldst_port0_exc_$signal$5[0:0]$6194 $1\ldst_port0_exc_$signal$5[0:0]$6202 + assign $0\ldst_port0_exc_$signal$6[0:0]$6195 $1\ldst_port0_exc_$signal$6[0:0]$6203 + assign $0\ldst_port0_exc_$signal$7[0:0]$6196 $1\ldst_port0_exc_$signal$7[0:0]$6204 + attribute \src "libresoc.v:143523.5-143523.29" + switch \initial + attribute \src "libresoc.v:143523.9-143523.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" + switch \idx_l_q_idx_l + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\ldst_port0_exc_$signal$7[0:0]$6204 $1\ldst_port0_exc_$signal$6[0:0]$6203 $1\ldst_port0_exc_$signal$5[0:0]$6202 $1\ldst_port0_exc_$signal$4[0:0]$6201 $1\ldst_port0_exc_$signal$3[0:0]$6200 $1\ldst_port0_exc_$signal$2[0:0]$6199 $1\ldst_port0_exc_$signal$1[0:0]$6198 $1\ldst_port0_exc_$signal[0:0]$6197 } { \ldst_port0_exc_$signal$39 \ldst_port0_exc_$signal$38 \ldst_port0_exc_$signal$37 \ldst_port0_exc_$signal$36 \ldst_port0_exc_$signal$35 \ldst_port0_exc_$signal$34 \ldst_port0_exc_$signal$33 \ldst_port0_exc_$signal$19 } + case + assign $1\ldst_port0_exc_$signal[0:0]$6197 1'0 + assign $1\ldst_port0_exc_$signal$1[0:0]$6198 1'0 + assign $1\ldst_port0_exc_$signal$2[0:0]$6199 1'0 + assign $1\ldst_port0_exc_$signal$3[0:0]$6200 1'0 + assign $1\ldst_port0_exc_$signal$4[0:0]$6201 1'0 + assign $1\ldst_port0_exc_$signal$5[0:0]$6202 1'0 + assign $1\ldst_port0_exc_$signal$6[0:0]$6203 1'0 + assign $1\ldst_port0_exc_$signal$7[0:0]$6204 1'0 + end + sync always + update \ldst_port0_exc_$signal $0\ldst_port0_exc_$signal[0:0]$6189 + update \ldst_port0_exc_$signal$1 $0\ldst_port0_exc_$signal$1[0:0]$6190 + update \ldst_port0_exc_$signal$2 $0\ldst_port0_exc_$signal$2[0:0]$6191 + update \ldst_port0_exc_$signal$3 $0\ldst_port0_exc_$signal$3[0:0]$6192 + update \ldst_port0_exc_$signal$4 $0\ldst_port0_exc_$signal$4[0:0]$6193 + update \ldst_port0_exc_$signal$5 $0\ldst_port0_exc_$signal$5[0:0]$6194 + update \ldst_port0_exc_$signal$6 $0\ldst_port0_exc_$signal$6[0:0]$6195 + update \ldst_port0_exc_$signal$7 $0\ldst_port0_exc_$signal$7[0:0]$6196 + end + attribute \src "libresoc.v:143539.3-143553.6" + process $proc$libresoc.v:143539$6205 + assign { } { } + assign { } { } + assign { } { } + assign $0\idx_l$23$next[0:0]$6206 $2\idx_l$23$next[0:0]$6208 + attribute \src "libresoc.v:143540.5-143540.29" + switch \initial + attribute \src "libresoc.v:143540.9-143540.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" + switch \idx_l_q_idx_l + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\idx_l$23$next[0:0]$6207 \pick_o + case + assign $1\idx_l$23$next[0:0]$6207 \idx_l$23 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\idx_l$23$next[0:0]$6208 1'0 + case + assign $2\idx_l$23$next[0:0]$6208 $1\idx_l$23$next[0:0]$6207 + end + sync always + update \idx_l$23$next $0\idx_l$23$next[0:0]$6206 + end + attribute \src "libresoc.v:143554.3-143563.6" + process $proc$libresoc.v:143554$6209 + assign { } { } + assign { } { } + assign $0\ldst_port0_mmu_done[0:0] $1\ldst_port0_mmu_done[0:0] + attribute \src "libresoc.v:143555.5-143555.29" + switch \initial + attribute \src "libresoc.v:143555.9-143555.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" + switch \idx_l_q_idx_l + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ldst_port0_mmu_done[0:0] \ldst_port0_mmu_done$40 + case + assign $1\ldst_port0_mmu_done[0:0] 1'0 + end + sync always + update \ldst_port0_mmu_done $0\ldst_port0_mmu_done[0:0] + end + attribute \src "libresoc.v:143564.3-143573.6" + process $proc$libresoc.v:143564$6210 + assign { } { } + assign { } { } + assign $0\ldst_port0_ldst_error[0:0] $1\ldst_port0_ldst_error[0:0] + attribute \src "libresoc.v:143565.5-143565.29" + switch \initial + attribute \src "libresoc.v:143565.9-143565.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" + switch \idx_l_q_idx_l + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ldst_port0_ldst_error[0:0] \ldst_port0_ldst_error$41 + case + assign $1\ldst_port0_ldst_error[0:0] 1'0 + end + sync always + update \ldst_port0_ldst_error $0\ldst_port0_ldst_error[0:0] + end + attribute \src "libresoc.v:143574.3-143583.6" + process $proc$libresoc.v:143574$6211 + assign { } { } + assign { } { } + assign $0\ldst_port0_cache_paradox[0:0] $1\ldst_port0_cache_paradox[0:0] + attribute \src "libresoc.v:143575.5-143575.29" + switch \initial + attribute \src "libresoc.v:143575.9-143575.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" + switch \idx_l_q_idx_l + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ldst_port0_cache_paradox[0:0] \ldst_port0_cache_paradox$42 + case + assign $1\ldst_port0_cache_paradox[0:0] 1'0 + end + sync always + update \ldst_port0_cache_paradox $0\ldst_port0_cache_paradox[0:0] + end + attribute \src "libresoc.v:143584.3-143593.6" + process $proc$libresoc.v:143584$6212 + assign { } { } + assign { } { } + assign $0\idx_l_s_idx_l[0:0] $1\idx_l_s_idx_l[0:0] + attribute \src "libresoc.v:143585.5-143585.29" + switch \initial + attribute \src "libresoc.v:143585.9-143585.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:278" + switch \$26 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\idx_l_s_idx_l[0:0] 1'1 + case + assign $1\idx_l_s_idx_l[0:0] 1'0 + end + sync always + update \idx_l_s_idx_l $0\idx_l_s_idx_l[0:0] + end + attribute \src "libresoc.v:143594.3-143603.6" + process $proc$libresoc.v:143594$6213 + assign { } { } + assign { } { } + assign $0\idx_l_r_idx_l[0:0] $1\idx_l_r_idx_l[0:0] + attribute \src "libresoc.v:143595.5-143595.29" + switch \initial + attribute \src "libresoc.v:143595.9-143595.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:296" + switch \reset_l_q_reset + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\idx_l_r_idx_l[0:0] 1'1 + case + assign $1\idx_l_r_idx_l[0:0] 1'1 + end + sync always + update \idx_l_r_idx_l $0\idx_l_r_idx_l[0:0] + end + attribute \src "libresoc.v:143604.3-143618.6" + process $proc$libresoc.v:143604$6214 + assign { } { } + assign { } { } + assign $0\reset_l_s_reset[0:0] $1\reset_l_s_reset[0:0] + attribute \src "libresoc.v:143605.5-143605.29" + switch \initial + attribute \src "libresoc.v:143605.9-143605.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" + switch \idx_l_q_idx_l + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\reset_l_s_reset[0:0] $2\reset_l_s_reset[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:288" + switch \$28 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\reset_l_s_reset[0:0] 1'1 + case + assign $2\reset_l_s_reset[0:0] 1'0 + end + case + assign $1\reset_l_s_reset[0:0] 1'0 + end + sync always + update \reset_l_s_reset $0\reset_l_s_reset[0:0] + end + attribute \src "libresoc.v:143619.3-143628.6" + process $proc$libresoc.v:143619$6215 + assign { } { } + assign { } { } + assign $0\reset_l_r_reset[0:0] $1\reset_l_r_reset[0:0] + attribute \src "libresoc.v:143620.5-143620.29" + switch \initial + attribute \src "libresoc.v:143620.9-143620.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:296" + switch \reset_l_q_reset + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\reset_l_r_reset[0:0] 1'1 + case + assign $1\reset_l_r_reset[0:0] 1'0 + end + sync always + update \reset_l_r_reset $0\reset_l_r_reset[0:0] + end + attribute \src "libresoc.v:143629.3-143638.6" + process $proc$libresoc.v:143629$6216 + assign { } { } + assign { } { } + assign $0\ldst_port0_is_ld_i$8[0:0]$6217 $1\ldst_port0_is_ld_i$8[0:0]$6218 + attribute \src "libresoc.v:143630.5-143630.29" + switch \initial + attribute \src "libresoc.v:143630.9-143630.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" + switch \idx_l_q_idx_l + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ldst_port0_is_ld_i$8[0:0]$6218 \ldst_port0_is_ld_i + case + assign $1\ldst_port0_is_ld_i$8[0:0]$6218 1'0 + end + sync always + update \ldst_port0_is_ld_i$8 $0\ldst_port0_is_ld_i$8[0:0]$6217 + end + attribute \src "libresoc.v:143639.3-143648.6" + process $proc$libresoc.v:143639$6219 + assign { } { } + assign { } { } + assign $0\ldst_port0_is_st_i$9[0:0]$6220 $1\ldst_port0_is_st_i$9[0:0]$6221 + attribute \src "libresoc.v:143640.5-143640.29" + switch \initial + attribute \src "libresoc.v:143640.9-143640.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" + switch \idx_l_q_idx_l + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ldst_port0_is_st_i$9[0:0]$6221 \ldst_port0_is_st_i + case + assign $1\ldst_port0_is_st_i$9[0:0]$6221 1'0 + end + sync always + update \ldst_port0_is_st_i$9 $0\ldst_port0_is_st_i$9[0:0]$6220 + end + attribute \src "libresoc.v:143649.3-143658.6" + process $proc$libresoc.v:143649$6222 + assign { } { } + assign { } { } + assign $0\ldst_port0_data_len$11[3:0]$6223 $1\ldst_port0_data_len$11[3:0]$6224 + attribute \src "libresoc.v:143650.5-143650.29" + switch \initial + attribute \src "libresoc.v:143650.9-143650.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" + switch \idx_l_q_idx_l + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ldst_port0_data_len$11[3:0]$6224 \ldst_port0_data_len + case + assign $1\ldst_port0_data_len$11[3:0]$6224 4'0000 + end + sync always + update \ldst_port0_data_len$11 $0\ldst_port0_data_len$11[3:0]$6223 + end + attribute \src "libresoc.v:143659.3-143668.6" + process $proc$libresoc.v:143659$6225 + assign { } { } + assign { } { } + assign $0\ldst_port0_go_die_i[0:0] $1\ldst_port0_go_die_i[0:0] + attribute \src "libresoc.v:143660.5-143660.29" + switch \initial + attribute \src "libresoc.v:143660.9-143660.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" + switch \idx_l_q_idx_l + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ldst_port0_go_die_i[0:0] \ldst_port0_go_die_i$30 + case + assign $1\ldst_port0_go_die_i[0:0] 1'0 + end + sync always + update \ldst_port0_go_die_i $0\ldst_port0_go_die_i[0:0] + end + connect \$20 $or$libresoc.v:143433$6167_Y + connect \$24 $ternary$libresoc.v:143434$6168_Y + connect \$26 $not$libresoc.v:143435$6169_Y + connect \$28 $not$libresoc.v:143436$6170_Y + connect \$22 \$24 + connect \$32 \ldst_port0_addr_i + connect \ldst_port0_go_die_i$30 1'0 + connect \ldst_port0_exc_$signal$33 1'0 + connect \ldst_port0_exc_$signal$34 1'0 + connect \ldst_port0_exc_$signal$35 1'0 + connect \ldst_port0_exc_$signal$36 1'0 + connect \ldst_port0_exc_$signal$37 1'0 + connect \ldst_port0_exc_$signal$38 1'0 + connect \ldst_port0_exc_$signal$39 1'0 + connect \ldst_port0_mmu_done$40 1'0 + connect \ldst_port0_ldst_error$41 1'0 + connect \ldst_port0_cache_paradox$42 1'0 + connect \reset_delay$next \reset_l_q_reset + connect \pick_i \$20 +end +attribute \src "libresoc.v:143688.1-143746.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem.ld_active" +attribute \generator "nMigen" +module \ld_active + attribute \src "libresoc.v:143689.7-143689.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:143734.3-143742.6" + wire $0\q_int$next[0:0]$6240 + attribute \src "libresoc.v:143732.3-143733.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:143734.3-143742.6" + wire $1\q_int$next[0:0]$6241 + attribute \src "libresoc.v:143711.7-143711.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:143724.17-143724.96" + wire $and$libresoc.v:143724$6230_Y + attribute \src "libresoc.v:143729.17-143729.96" + wire $and$libresoc.v:143729$6235_Y + attribute \src "libresoc.v:143726.18-143726.99" + wire $not$libresoc.v:143726$6232_Y + attribute \src "libresoc.v:143728.17-143728.98" + wire $not$libresoc.v:143728$6234_Y + attribute \src "libresoc.v:143731.17-143731.98" + wire $not$libresoc.v:143731$6237_Y + attribute \src "libresoc.v:143725.18-143725.104" + wire $or$libresoc.v:143725$6231_Y + attribute \src "libresoc.v:143727.18-143727.105" + wire $or$libresoc.v:143727$6233_Y + attribute \src "libresoc.v:143730.17-143730.103" + wire $or$libresoc.v:143730$6236_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 1 \coresync_rst + attribute \src "libresoc.v:143689.7-143689.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire output 4 \q_ld_active + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" + wire \qlq_ld_active + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \qn_ld_active + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire input 2 \r_ld_active + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire input 3 \s_ld_active + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:143724$6230 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:143724$6230_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:143729$6235 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:143729$6235_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:143726$6232 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_ld_active + connect \Y $not$libresoc.v:143726$6232_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:143728$6234 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_ld_active + connect \Y $not$libresoc.v:143728$6234_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:143731$6237 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_ld_active + connect \Y $not$libresoc.v:143731$6237_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:143725$6231 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_ld_active + connect \Y $or$libresoc.v:143725$6231_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:143727$6233 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_ld_active + connect \B \q_int + connect \Y $or$libresoc.v:143727$6233_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:143730$6236 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_ld_active + connect \Y $or$libresoc.v:143730$6236_Y + end + attribute \src "libresoc.v:143689.7-143689.20" + process $proc$libresoc.v:143689$6242 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:143711.7-143711.19" + process $proc$libresoc.v:143711$6243 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:143732.3-143733.27" + process $proc$libresoc.v:143732$6238 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:143734.3-143742.6" + process $proc$libresoc.v:143734$6239 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$6240 $1\q_int$next[0:0]$6241 + attribute \src "libresoc.v:143735.5-143735.29" + switch \initial + attribute \src "libresoc.v:143735.9-143735.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$6241 1'0 + case + assign $1\q_int$next[0:0]$6241 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$6240 + end + connect \$9 $and$libresoc.v:143724$6230_Y + connect \$11 $or$libresoc.v:143725$6231_Y + connect \$13 $not$libresoc.v:143726$6232_Y + connect \$15 $or$libresoc.v:143727$6233_Y + connect \$1 $not$libresoc.v:143728$6234_Y + connect \$3 $and$libresoc.v:143729$6235_Y + connect \$5 $or$libresoc.v:143730$6236_Y + connect \$7 $not$libresoc.v:143731$6237_Y + connect \qlq_ld_active \$15 + connect \qn_ld_active \$13 + connect \q_ld_active \$11 +end +attribute \src "libresoc.v:143750.1-145109.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0" +attribute \generator "nMigen" +module \ldst0 + attribute \src "libresoc.v:144764.3-144772.6" + wire $0\adr_l_r_adr$next[0:0]$6386 + attribute \src "libresoc.v:144646.3-144647.39" + wire $0\adr_l_r_adr[0:0] + attribute \src "libresoc.v:144592.3-144593.21" + wire $0\alu_ok[0:0] + attribute \src "libresoc.v:144929.3-144938.6" + wire width 64 $0\dest1_o[63:0] + attribute \src "libresoc.v:144939.3-144948.6" + wire width 64 $0\dest2_o[63:0] + attribute \src "libresoc.v:144919.3-144928.6" + wire width 64 $0\ea_r$next[63:0]$6474 + attribute \src "libresoc.v:144594.3-144595.25" + wire width 64 $0\ea_r[63:0] + attribute \src "libresoc.v:143751.7-143751.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:144994.3-145013.6" + wire width 64 $0\ldd_o[63:0] + attribute \src "libresoc.v:144958.3-144981.6" + wire width 64 $0\lddata_r[63:0] + attribute \src "libresoc.v:144861.3-144870.6" + wire width 64 $0\ldo_r$next[63:0]$6459 + attribute \src "libresoc.v:144602.3-144603.27" + wire width 64 $0\ldo_r[63:0] + attribute \src "libresoc.v:144590.3-144591.33" + wire width 96 $0\ldst_port0_addr_i[95:0] + attribute \src "libresoc.v:144949.3-144957.6" + wire $0\ldst_port0_addr_i_ok$next[0:0]$6479 + attribute \src "libresoc.v:144588.3-144589.57" + wire $0\ldst_port0_addr_i_ok[0:0] + attribute \src "libresoc.v:145038.3-145049.6" + wire width 64 $0\ldst_port0_st_data_i[63:0] + attribute \src "libresoc.v:144809.3-144817.6" + wire $0\lsd_l_r_lsd$next[0:0]$6401 + attribute \src "libresoc.v:144636.3-144637.39" + wire $0\lsd_l_r_lsd[0:0] + attribute \src "libresoc.v:144737.3-144745.6" + wire $0\opc_l_r_opc$next[0:0]$6377 + attribute \src "libresoc.v:144652.3-144653.39" + wire $0\opc_l_r_opc[0:0] + attribute \src "libresoc.v:144728.3-144736.6" + wire $0\opc_l_s_opc$next[0:0]$6374 + attribute \src "libresoc.v:144654.3-144655.39" + wire $0\opc_l_s_opc[0:0] + attribute \src "libresoc.v:144818.3-144860.6" + wire $0\oper_r__byte_reverse$next[0:0]$6404 + attribute \src "libresoc.v:144628.3-144629.57" + wire $0\oper_r__byte_reverse[0:0] + attribute \src "libresoc.v:144818.3-144860.6" + wire width 4 $0\oper_r__data_len$next[3:0]$6405 + attribute \src "libresoc.v:144626.3-144627.49" + wire width 4 $0\oper_r__data_len[3:0] + attribute \src "libresoc.v:144818.3-144860.6" + wire width 13 $0\oper_r__fn_unit$next[12:0]$6406 + attribute \src "libresoc.v:144606.3-144607.47" + wire width 13 $0\oper_r__fn_unit[12:0] + attribute \src "libresoc.v:144818.3-144860.6" + wire width 64 $0\oper_r__imm_data__data$next[63:0]$6407 + attribute \src "libresoc.v:144608.3-144609.61" + wire width 64 $0\oper_r__imm_data__data[63:0] + attribute \src "libresoc.v:144818.3-144860.6" + wire $0\oper_r__imm_data__ok$next[0:0]$6408 + attribute \src "libresoc.v:144610.3-144611.57" + wire $0\oper_r__imm_data__ok[0:0] + attribute \src "libresoc.v:144818.3-144860.6" + wire width 32 $0\oper_r__insn$next[31:0]$6409 + attribute \src "libresoc.v:144634.3-144635.41" + wire width 32 $0\oper_r__insn[31:0] + attribute \src "libresoc.v:144818.3-144860.6" + wire width 7 $0\oper_r__insn_type$next[6:0]$6410 + attribute \src "libresoc.v:144604.3-144605.51" + wire width 7 $0\oper_r__insn_type[6:0] + attribute \src "libresoc.v:144818.3-144860.6" + wire $0\oper_r__is_32bit$next[0:0]$6411 + attribute \src "libresoc.v:144622.3-144623.49" + wire $0\oper_r__is_32bit[0:0] + attribute \src "libresoc.v:144818.3-144860.6" + wire $0\oper_r__is_signed$next[0:0]$6412 + attribute \src "libresoc.v:144624.3-144625.51" + wire $0\oper_r__is_signed[0:0] + attribute \src "libresoc.v:144818.3-144860.6" + wire width 2 $0\oper_r__ldst_mode$next[1:0]$6413 + attribute \src "libresoc.v:144632.3-144633.51" + wire width 2 $0\oper_r__ldst_mode[1:0] + attribute \src "libresoc.v:144818.3-144860.6" + wire $0\oper_r__oe__oe$next[0:0]$6414 + attribute \src "libresoc.v:144618.3-144619.45" + wire $0\oper_r__oe__oe[0:0] + attribute \src "libresoc.v:144818.3-144860.6" + wire $0\oper_r__oe__ok$next[0:0]$6415 + attribute \src "libresoc.v:144620.3-144621.45" + wire $0\oper_r__oe__ok[0:0] + attribute \src "libresoc.v:144818.3-144860.6" + wire $0\oper_r__rc__ok$next[0:0]$6416 + attribute \src "libresoc.v:144616.3-144617.45" + wire $0\oper_r__rc__ok[0:0] + attribute \src "libresoc.v:144818.3-144860.6" + wire $0\oper_r__rc__rc$next[0:0]$6417 + attribute \src "libresoc.v:144614.3-144615.45" + wire $0\oper_r__rc__rc[0:0] + attribute \src "libresoc.v:144818.3-144860.6" + wire $0\oper_r__sign_extend$next[0:0]$6418 + attribute \src "libresoc.v:144630.3-144631.55" + wire $0\oper_r__sign_extend[0:0] + attribute \src "libresoc.v:144818.3-144860.6" + wire $0\oper_r__zero_a$next[0:0]$6419 + attribute \src "libresoc.v:144612.3-144613.45" + wire $0\oper_r__zero_a[0:0] + attribute \src "libresoc.v:144656.3-144657.28" + wire $0\p_st_go[0:0] + attribute \src "libresoc.v:144982.3-144993.6" + wire width 64 $0\revnorev[63:0] + attribute \src "libresoc.v:144755.3-144763.6" + wire width 3 $0\src_l_r_src$next[2:0]$6383 + attribute \src "libresoc.v:144648.3-144649.39" + wire width 3 $0\src_l_r_src[2:0] + attribute \src "libresoc.v:144746.3-144754.6" + wire width 3 $0\src_l_s_src$next[2:0]$6380 + attribute \src "libresoc.v:144650.3-144651.39" + wire width 3 $0\src_l_s_src[2:0] + attribute \src "libresoc.v:144871.3-144886.6" + wire width 64 $0\src_r0$next[63:0]$6462 + attribute \src "libresoc.v:144600.3-144601.29" + wire width 64 $0\src_r0[63:0] + attribute \src "libresoc.v:144887.3-144902.6" + wire width 64 $0\src_r1$next[63:0]$6466 + attribute \src "libresoc.v:144598.3-144599.29" + wire width 64 $0\src_r1[63:0] + attribute \src "libresoc.v:144903.3-144918.6" + wire width 64 $0\src_r2$next[63:0]$6470 + attribute \src "libresoc.v:144596.3-144597.29" + wire width 64 $0\src_r2[63:0] + attribute \src "libresoc.v:145014.3-145037.6" + wire width 64 $0\stdata_r[63:0] + attribute \src "libresoc.v:144800.3-144808.6" + wire $0\sto_l_r_sto$next[0:0]$6398 + attribute \src "libresoc.v:144638.3-144639.39" + wire $0\sto_l_r_sto[0:0] + attribute \src "libresoc.v:144791.3-144799.6" + wire $0\upd_l_r_upd$next[0:0]$6395 + attribute \src "libresoc.v:144640.3-144641.39" + wire $0\upd_l_r_upd[0:0] + attribute \src "libresoc.v:144782.3-144790.6" + wire $0\upd_l_s_upd$next[0:0]$6392 + attribute \src "libresoc.v:144642.3-144643.39" + wire $0\upd_l_s_upd[0:0] + attribute \src "libresoc.v:144773.3-144781.6" + wire $0\wri_l_r_wri$next[0:0]$6389 + attribute \src "libresoc.v:144644.3-144645.39" + wire $0\wri_l_r_wri[0:0] + attribute \src "libresoc.v:144764.3-144772.6" + wire $1\adr_l_r_adr$next[0:0]$6387 + attribute \src "libresoc.v:143947.7-143947.25" + wire $1\adr_l_r_adr[0:0] + attribute \src "libresoc.v:143961.7-143961.20" + wire $1\alu_ok[0:0] + attribute \src "libresoc.v:144929.3-144938.6" + wire width 64 $1\dest1_o[63:0] + attribute \src "libresoc.v:144939.3-144948.6" + wire width 64 $1\dest2_o[63:0] + attribute \src "libresoc.v:144919.3-144928.6" + wire width 64 $1\ea_r$next[63:0]$6475 + attribute \src "libresoc.v:144007.14-144007.41" + wire width 64 $1\ea_r[63:0] + attribute \src "libresoc.v:144994.3-145013.6" + wire width 64 $1\ldd_o[63:0] + attribute \src "libresoc.v:144958.3-144981.6" + wire width 64 $1\lddata_r[63:0] + attribute \src "libresoc.v:144861.3-144870.6" + wire width 64 $1\ldo_r$next[63:0]$6460 + attribute \src "libresoc.v:144037.14-144037.42" + wire width 64 $1\ldo_r[63:0] + attribute \src "libresoc.v:144042.14-144042.62" + wire width 96 $1\ldst_port0_addr_i[95:0] + attribute \src "libresoc.v:144949.3-144957.6" + wire $1\ldst_port0_addr_i_ok$next[0:0]$6480 + attribute \src "libresoc.v:144047.7-144047.34" + wire $1\ldst_port0_addr_i_ok[0:0] + attribute \src "libresoc.v:145038.3-145049.6" + wire width 64 $1\ldst_port0_st_data_i[63:0] + attribute \src "libresoc.v:144809.3-144817.6" + wire $1\lsd_l_r_lsd$next[0:0]$6402 + attribute \src "libresoc.v:144096.7-144096.25" + wire $1\lsd_l_r_lsd[0:0] + attribute \src "libresoc.v:144737.3-144745.6" + wire $1\opc_l_r_opc$next[0:0]$6378 + attribute \src "libresoc.v:144110.7-144110.25" + wire $1\opc_l_r_opc[0:0] + attribute \src "libresoc.v:144728.3-144736.6" + wire $1\opc_l_s_opc$next[0:0]$6375 + attribute \src "libresoc.v:144114.7-144114.25" + wire $1\opc_l_s_opc[0:0] + attribute \src "libresoc.v:144818.3-144860.6" + wire $1\oper_r__byte_reverse$next[0:0]$6420 + attribute \src "libresoc.v:144243.7-144243.34" + wire $1\oper_r__byte_reverse[0:0] + attribute \src "libresoc.v:144818.3-144860.6" + wire width 4 $1\oper_r__data_len$next[3:0]$6421 + attribute \src "libresoc.v:144247.13-144247.36" + wire width 4 $1\oper_r__data_len[3:0] + attribute \src "libresoc.v:144818.3-144860.6" + wire width 13 $1\oper_r__fn_unit$next[12:0]$6422 + attribute \src "libresoc.v:144265.14-144265.40" + wire width 13 $1\oper_r__fn_unit[12:0] + attribute \src "libresoc.v:144818.3-144860.6" + wire width 64 $1\oper_r__imm_data__data$next[63:0]$6423 + attribute \src "libresoc.v:144269.14-144269.59" + wire width 64 $1\oper_r__imm_data__data[63:0] + attribute \src "libresoc.v:144818.3-144860.6" + wire $1\oper_r__imm_data__ok$next[0:0]$6424 + attribute \src "libresoc.v:144273.7-144273.34" + wire $1\oper_r__imm_data__ok[0:0] + attribute \src "libresoc.v:144818.3-144860.6" + wire width 32 $1\oper_r__insn$next[31:0]$6425 + attribute \src "libresoc.v:144277.14-144277.34" + wire width 32 $1\oper_r__insn[31:0] + attribute \src "libresoc.v:144818.3-144860.6" + wire width 7 $1\oper_r__insn_type$next[6:0]$6426 + attribute \src "libresoc.v:144355.13-144355.38" + wire width 7 $1\oper_r__insn_type[6:0] + attribute \src "libresoc.v:144818.3-144860.6" + wire $1\oper_r__is_32bit$next[0:0]$6427 + attribute \src "libresoc.v:144359.7-144359.30" + wire $1\oper_r__is_32bit[0:0] + attribute \src "libresoc.v:144818.3-144860.6" + wire $1\oper_r__is_signed$next[0:0]$6428 + attribute \src "libresoc.v:144363.7-144363.31" + wire $1\oper_r__is_signed[0:0] + attribute \src "libresoc.v:144818.3-144860.6" + wire width 2 $1\oper_r__ldst_mode$next[1:0]$6429 + attribute \src "libresoc.v:144372.13-144372.37" + wire width 2 $1\oper_r__ldst_mode[1:0] + attribute \src "libresoc.v:144818.3-144860.6" + wire $1\oper_r__oe__oe$next[0:0]$6430 + attribute \src "libresoc.v:144376.7-144376.28" + wire $1\oper_r__oe__oe[0:0] + attribute \src "libresoc.v:144818.3-144860.6" + wire $1\oper_r__oe__ok$next[0:0]$6431 + attribute \src "libresoc.v:144380.7-144380.28" + wire $1\oper_r__oe__ok[0:0] + attribute \src "libresoc.v:144818.3-144860.6" + wire $1\oper_r__rc__ok$next[0:0]$6432 + attribute \src "libresoc.v:144384.7-144384.28" + wire $1\oper_r__rc__ok[0:0] + attribute \src "libresoc.v:144818.3-144860.6" + wire $1\oper_r__rc__rc$next[0:0]$6433 + attribute \src "libresoc.v:144388.7-144388.28" + wire $1\oper_r__rc__rc[0:0] + attribute \src "libresoc.v:144818.3-144860.6" + wire $1\oper_r__sign_extend$next[0:0]$6434 + attribute \src "libresoc.v:144392.7-144392.33" + wire $1\oper_r__sign_extend[0:0] + attribute \src "libresoc.v:144818.3-144860.6" + wire $1\oper_r__zero_a$next[0:0]$6435 + attribute \src "libresoc.v:144396.7-144396.28" + wire $1\oper_r__zero_a[0:0] + attribute \src "libresoc.v:144400.7-144400.21" + wire $1\p_st_go[0:0] + attribute \src "libresoc.v:144982.3-144993.6" + wire width 64 $1\revnorev[63:0] + attribute \src "libresoc.v:144755.3-144763.6" + wire width 3 $1\src_l_r_src$next[2:0]$6384 + attribute \src "libresoc.v:144442.13-144442.31" + wire width 3 $1\src_l_r_src[2:0] + attribute \src "libresoc.v:144746.3-144754.6" + wire width 3 $1\src_l_s_src$next[2:0]$6381 + attribute \src "libresoc.v:144446.13-144446.31" + wire width 3 $1\src_l_s_src[2:0] + attribute \src "libresoc.v:144871.3-144886.6" + wire width 64 $1\src_r0$next[63:0]$6463 + attribute \src "libresoc.v:144450.14-144450.43" + wire width 64 $1\src_r0[63:0] + attribute \src "libresoc.v:144887.3-144902.6" + wire width 64 $1\src_r1$next[63:0]$6467 + attribute \src "libresoc.v:144454.14-144454.43" + wire width 64 $1\src_r1[63:0] + attribute \src "libresoc.v:144903.3-144918.6" + wire width 64 $1\src_r2$next[63:0]$6471 + attribute \src "libresoc.v:144458.14-144458.43" + wire width 64 $1\src_r2[63:0] + attribute \src "libresoc.v:145014.3-145037.6" + wire width 64 $1\stdata_r[63:0] + attribute \src "libresoc.v:144800.3-144808.6" + wire $1\sto_l_r_sto$next[0:0]$6399 + attribute \src "libresoc.v:144468.7-144468.25" + wire $1\sto_l_r_sto[0:0] + attribute \src "libresoc.v:144791.3-144799.6" + wire $1\upd_l_r_upd$next[0:0]$6396 + attribute \src "libresoc.v:144478.7-144478.25" + wire $1\upd_l_r_upd[0:0] + attribute \src "libresoc.v:144782.3-144790.6" + wire $1\upd_l_s_upd$next[0:0]$6393 + attribute \src "libresoc.v:144482.7-144482.25" + wire $1\upd_l_s_upd[0:0] + attribute \src "libresoc.v:144773.3-144781.6" + wire $1\wri_l_r_wri$next[0:0]$6390 + attribute \src "libresoc.v:144492.7-144492.25" + wire $1\wri_l_r_wri[0:0] + attribute \src "libresoc.v:144994.3-145013.6" + wire width 64 $2\ldd_o[63:0] + attribute \src "libresoc.v:144958.3-144981.6" + wire width 64 $2\lddata_r[63:0] + attribute \src "libresoc.v:144818.3-144860.6" + wire $2\oper_r__byte_reverse$next[0:0]$6436 + attribute \src "libresoc.v:144818.3-144860.6" + wire width 4 $2\oper_r__data_len$next[3:0]$6437 + attribute \src "libresoc.v:144818.3-144860.6" + wire width 13 $2\oper_r__fn_unit$next[12:0]$6438 + attribute \src "libresoc.v:144818.3-144860.6" + wire width 64 $2\oper_r__imm_data__data$next[63:0]$6439 + attribute \src "libresoc.v:144818.3-144860.6" + wire $2\oper_r__imm_data__ok$next[0:0]$6440 + attribute \src "libresoc.v:144818.3-144860.6" + wire width 32 $2\oper_r__insn$next[31:0]$6441 + attribute \src "libresoc.v:144818.3-144860.6" + wire width 7 $2\oper_r__insn_type$next[6:0]$6442 + attribute \src "libresoc.v:144818.3-144860.6" + wire $2\oper_r__is_32bit$next[0:0]$6443 + attribute \src "libresoc.v:144818.3-144860.6" + wire $2\oper_r__is_signed$next[0:0]$6444 + attribute \src "libresoc.v:144818.3-144860.6" + wire width 2 $2\oper_r__ldst_mode$next[1:0]$6445 + attribute \src "libresoc.v:144818.3-144860.6" + wire $2\oper_r__oe__oe$next[0:0]$6446 + attribute \src "libresoc.v:144818.3-144860.6" + wire $2\oper_r__oe__ok$next[0:0]$6447 + attribute \src "libresoc.v:144818.3-144860.6" + wire $2\oper_r__rc__ok$next[0:0]$6448 + attribute \src "libresoc.v:144818.3-144860.6" + wire $2\oper_r__rc__rc$next[0:0]$6449 + attribute \src "libresoc.v:144818.3-144860.6" + wire $2\oper_r__sign_extend$next[0:0]$6450 + attribute \src "libresoc.v:144818.3-144860.6" + wire $2\oper_r__zero_a$next[0:0]$6451 + attribute \src "libresoc.v:144871.3-144886.6" + wire width 64 $2\src_r0$next[63:0]$6464 + attribute \src "libresoc.v:144887.3-144902.6" + wire width 64 $2\src_r1$next[63:0]$6468 + attribute \src "libresoc.v:144903.3-144918.6" + wire width 64 $2\src_r2$next[63:0]$6472 + attribute \src "libresoc.v:145014.3-145037.6" + wire width 64 $2\stdata_r[63:0] + attribute \src "libresoc.v:144818.3-144860.6" + wire width 64 $3\oper_r__imm_data__data$next[63:0]$6452 + attribute \src "libresoc.v:144818.3-144860.6" + wire $3\oper_r__imm_data__ok$next[0:0]$6453 + attribute \src "libresoc.v:144818.3-144860.6" + wire $3\oper_r__oe__oe$next[0:0]$6454 + attribute \src "libresoc.v:144818.3-144860.6" + wire $3\oper_r__oe__ok$next[0:0]$6455 + attribute \src "libresoc.v:144818.3-144860.6" + wire $3\oper_r__rc__ok$next[0:0]$6456 + attribute \src "libresoc.v:144818.3-144860.6" + wire $3\oper_r__rc__rc$next[0:0]$6457 + attribute \src "libresoc.v:144574.18-144574.124" + wire width 65 $add$libresoc.v:144574$6324_Y + attribute \src "libresoc.v:144497.19-144497.118" + wire $and$libresoc.v:144497$6244_Y + attribute \src "libresoc.v:144498.19-144498.125" + wire $and$libresoc.v:144498$6245_Y + attribute \src "libresoc.v:144499.19-144499.120" + wire $and$libresoc.v:144499$6246_Y + attribute \src "libresoc.v:144500.19-144500.125" + wire $and$libresoc.v:144500$6247_Y + attribute \src "libresoc.v:144501.19-144501.118" + wire $and$libresoc.v:144501$6248_Y + attribute \src "libresoc.v:144503.19-144503.119" + wire $and$libresoc.v:144503$6250_Y + attribute \src "libresoc.v:144504.19-144504.123" + wire $and$libresoc.v:144504$6251_Y + attribute \src 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"/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \exc_$signal$183 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \exc_$signal$184 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \exc_$signal$185 + attribute \src "libresoc.v:143751.7-143751.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:110" + wire \ld_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:273" + wire \ld_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:281" + wire width 64 \ldd_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:385" + wire width 64 \ldd_r + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:17" + wire width 64 \lddata_r + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" + wire width 64 \ldo_r + attribute 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\B \cu_go_die_i + connect \Y $or$libresoc.v:144548$6298_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:357" + cell $or $or$libresoc.v:144560$6310 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_reset + connect \B \$43 + connect \Y $or$libresoc.v:144560$6310_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:357" + cell $or $or$libresoc.v:144564$6314 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_reset + connect \B \$51 + connect \Y $or$libresoc.v:144564$6314_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:360" + cell $or $or$libresoc.v:144565$6315 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \reset_w + connect \B { \$45 \$53 } + connect \Y $or$libresoc.v:144565$6315_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:368" + cell $or $or$libresoc.v:144567$6317 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \reset_s + connect \B \p_st_go + connect \Y $or$libresoc.v:144567$6317_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:372" + cell $or $or$libresoc.v:144568$6318 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \reset_s + connect \B \p_st_go + connect \Y $or$libresoc.v:144568$6318_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:372" + cell $or $or$libresoc.v:144569$6319 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$61 + connect \B \ld_ok + connect \Y $or$libresoc.v:144569$6319_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:295" + cell $or $or$libresoc.v:144582$6332 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_issue_i + connect \B \cu_go_die_i + connect \Y $or$libresoc.v:144582$6332_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:431" + cell $or $or$libresoc.v:144583$6333 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_rd__go_i [0] + connect \B \cu_rd__go_i [1] + connect \Y $or$libresoc.v:144583$6333_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:434" + cell $or $or$libresoc.v:144584$6334 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_rd__rel_o [0] + connect \B \cu_rd__rel_o [1] + connect \Y $or$libresoc.v:144584$6334_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:400" + cell $pos $pos$libresoc.v:144538$6286 + parameter \A_SIGNED 0 + parameter \A_WIDTH 96 + parameter \Y_WIDTH 96 + connect \A $extend$libresoc.v:144538$6285_Y + connect \Y $pos$libresoc.v:144538$6286_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:34" + cell $pos $pos$libresoc.v:144540$6289 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:144540$6288_Y + connect \Y $pos$libresoc.v:144540$6289_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:34" + cell $pos $pos$libresoc.v:144541$6290 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A { 48'000000000000000000000000000000000000000000000000 \ldst_port0_ld_data_o [7:0] \ldst_port0_ld_data_o [15:8] } + connect \Y $pos$libresoc.v:144541$6290_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:34" + cell $pos $pos$libresoc.v:144543$6292 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A { 32'00000000000000000000000000000000 \ldst_port0_ld_data_o [7:0] \ldst_port0_ld_data_o [15:8] \ldst_port0_ld_data_o [23:16] \ldst_port0_ld_data_o [31:24] } + connect \Y $pos$libresoc.v:144543$6292_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:34" + cell $pos $pos$libresoc.v:144545$6295 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:144545$6294_Y + connect \Y $pos$libresoc.v:144545$6295_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:34" + cell $pos $pos$libresoc.v:144546$6296 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A { 48'000000000000000000000000000000000000000000000000 \src_r2 [7:0] \src_r2 [15:8] } + connect \Y $pos$libresoc.v:144546$6296_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:34" + cell $pos $pos$libresoc.v:144547$6297 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A { 32'00000000000000000000000000000000 \src_r2 [7:0] \src_r2 [15:8] \src_r2 [23:16] \src_r2 [31:24] } + connect \Y $pos$libresoc.v:144547$6297_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" + cell $mux $ternary$libresoc.v:144570$6320 + parameter \WIDTH 64 + connect \A \ldo_r + connect \B \ldd_o + connect \S \ld_ok + connect \Y $ternary$libresoc.v:144570$6320_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" + cell $mux $ternary$libresoc.v:144571$6321 + parameter \WIDTH 64 + connect \A \ea_r + connect \B \alu_o + connect \S \alu_l_q_alu + connect \Y $ternary$libresoc.v:144571$6321_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:406" + cell $mux $ternary$libresoc.v:144572$6322 + parameter \WIDTH 64 + connect \A \src_r0 + connect \B 64'0000000000000000000000000000000000000000000000000000000000000000 + connect \S \oper_r__zero_a + connect \Y $ternary$libresoc.v:144572$6322_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:411" + cell $mux $ternary$libresoc.v:144573$6323 + parameter \WIDTH 64 + connect \A \src_r1 + connect \B \oper_r__imm_data__data + connect \S \oper_r__imm_data__ok + connect \Y $ternary$libresoc.v:144573$6323_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:144658.9-144664.4" + cell \adr_l \adr_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_adr \adr_l_q_adr + connect \r_adr \adr_l_r_adr + connect \s_adr \adr_l_s_adr + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:144665.15-144671.4" + cell \alu_l$128 \alu_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_alu \alu_l_q_alu + connect \r_alu \alu_l_r_alu + connect \s_alu \alu_l_s_alu + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:144672.9-144678.4" + cell \lod_l \lod_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \qn_lod \lod_l_qn_lod + connect \r_lod \lod_l_r_lod + connect \s_lod \lod_l_s_lod + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:144679.9-144685.4" + cell \lsd_l \lsd_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_lsd \lsd_l_q_lsd + connect \r_lsd \lsd_l_r_lsd + connect \s_lsd \lsd_l_s_lsd + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:144686.15-144692.4" + cell \opc_l$126 \opc_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_opc \opc_l_q_opc + connect \r_opc \opc_l_r_opc + connect \s_opc \opc_l_s_opc + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:144693.15-144699.4" + cell \rst_l$129 \rst_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_rst \rst_l_q_rst + connect \r_rst \rst_l_r_rst + connect \s_rst \rst_l_s_rst + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:144700.15-144706.4" + cell \src_l$127 \src_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_src \src_l_q_src + connect \r_src \src_l_r_src + connect \s_src \src_l_s_src + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:144707.9-144713.4" + cell \sto_l \sto_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_sto \sto_l_q_sto + connect \r_sto \sto_l_r_sto + connect \s_sto \sto_l_s_sto + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:144714.9-144720.4" + cell \upd_l \upd_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_upd \upd_l_q_upd + connect \r_upd \upd_l_r_upd + connect \s_upd \upd_l_s_upd + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:144721.9-144727.4" + cell \wri_l \wri_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_wri \wri_l_q_wri + connect \r_wri \wri_l_r_wri + connect \s_wri \wri_l_s_wri + end + attribute \src "libresoc.v:143751.7-143751.20" + process $proc$libresoc.v:143751$6486 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:143947.7-143947.25" + process $proc$libresoc.v:143947$6487 + assign { } { } + assign $1\adr_l_r_adr[0:0] 1'1 + sync always + sync init + update \adr_l_r_adr $1\adr_l_r_adr[0:0] + end + attribute \src "libresoc.v:143961.7-143961.20" + process $proc$libresoc.v:143961$6488 + assign { } { } + assign $1\alu_ok[0:0] 1'0 + sync always + sync init + update \alu_ok $1\alu_ok[0:0] + end + attribute \src "libresoc.v:144007.14-144007.41" + process $proc$libresoc.v:144007$6489 + assign { } { } + assign $1\ea_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \ea_r $1\ea_r[63:0] + end + attribute \src "libresoc.v:144037.14-144037.42" + process $proc$libresoc.v:144037$6490 + assign { } { } + assign $1\ldo_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \ldo_r $1\ldo_r[63:0] + end + attribute \src "libresoc.v:144042.14-144042.62" + process $proc$libresoc.v:144042$6491 + assign { } { } + assign $1\ldst_port0_addr_i[95:0] 96'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \ldst_port0_addr_i $1\ldst_port0_addr_i[95:0] + end + attribute \src "libresoc.v:144047.7-144047.34" + process $proc$libresoc.v:144047$6492 + assign { } { } + assign $1\ldst_port0_addr_i_ok[0:0] 1'0 + sync always + sync init + update \ldst_port0_addr_i_ok $1\ldst_port0_addr_i_ok[0:0] + end + attribute \src "libresoc.v:144096.7-144096.25" + process $proc$libresoc.v:144096$6493 + assign { } { } + assign $1\lsd_l_r_lsd[0:0] 1'1 + sync always + sync init + update \lsd_l_r_lsd $1\lsd_l_r_lsd[0:0] + end + attribute \src "libresoc.v:144110.7-144110.25" + process $proc$libresoc.v:144110$6494 + assign { } { } + assign $1\opc_l_r_opc[0:0] 1'1 + sync always + sync init + update \opc_l_r_opc $1\opc_l_r_opc[0:0] + end + attribute \src "libresoc.v:144114.7-144114.25" + process $proc$libresoc.v:144114$6495 + assign { } { } + assign $1\opc_l_s_opc[0:0] 1'0 + sync always + sync init + update \opc_l_s_opc $1\opc_l_s_opc[0:0] + end + attribute \src "libresoc.v:144243.7-144243.34" + process $proc$libresoc.v:144243$6496 + assign { } { } + assign $1\oper_r__byte_reverse[0:0] 1'0 + sync always + sync init + update \oper_r__byte_reverse $1\oper_r__byte_reverse[0:0] + end + attribute \src "libresoc.v:144247.13-144247.36" + process $proc$libresoc.v:144247$6497 + assign { } { } + assign $1\oper_r__data_len[3:0] 4'0000 + sync always + sync init + update \oper_r__data_len $1\oper_r__data_len[3:0] + end + attribute \src "libresoc.v:144265.14-144265.40" + process $proc$libresoc.v:144265$6498 + assign { } { } + assign $1\oper_r__fn_unit[12:0] 13'0000000000000 + sync always + sync init + update \oper_r__fn_unit $1\oper_r__fn_unit[12:0] + end + attribute \src "libresoc.v:144269.14-144269.59" + process $proc$libresoc.v:144269$6499 + assign { } { } + assign $1\oper_r__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \oper_r__imm_data__data $1\oper_r__imm_data__data[63:0] + end + attribute \src "libresoc.v:144273.7-144273.34" + process $proc$libresoc.v:144273$6500 + assign { } { } + assign $1\oper_r__imm_data__ok[0:0] 1'0 + sync always + sync init + update \oper_r__imm_data__ok $1\oper_r__imm_data__ok[0:0] + end + attribute \src "libresoc.v:144277.14-144277.34" + process $proc$libresoc.v:144277$6501 + assign { } { } + assign $1\oper_r__insn[31:0] 0 + sync always + sync init + update \oper_r__insn $1\oper_r__insn[31:0] + end + attribute \src "libresoc.v:144355.13-144355.38" + process $proc$libresoc.v:144355$6502 + assign { } { } + assign $1\oper_r__insn_type[6:0] 7'0000000 + sync always + sync init + update \oper_r__insn_type $1\oper_r__insn_type[6:0] + end + attribute \src "libresoc.v:144359.7-144359.30" + process $proc$libresoc.v:144359$6503 + assign { } { } + assign $1\oper_r__is_32bit[0:0] 1'0 + sync always + sync init + update \oper_r__is_32bit $1\oper_r__is_32bit[0:0] + end + attribute \src "libresoc.v:144363.7-144363.31" + process $proc$libresoc.v:144363$6504 + assign { } { } + assign $1\oper_r__is_signed[0:0] 1'0 + sync always + sync init + update \oper_r__is_signed $1\oper_r__is_signed[0:0] + end + attribute \src "libresoc.v:144372.13-144372.37" + process $proc$libresoc.v:144372$6505 + assign { } { } + assign $1\oper_r__ldst_mode[1:0] 2'00 + sync always + sync init + update \oper_r__ldst_mode $1\oper_r__ldst_mode[1:0] + end + attribute \src "libresoc.v:144376.7-144376.28" + process $proc$libresoc.v:144376$6506 + assign { } { } + assign $1\oper_r__oe__oe[0:0] 1'0 + sync always + sync init + update \oper_r__oe__oe $1\oper_r__oe__oe[0:0] + end + attribute \src "libresoc.v:144380.7-144380.28" + process $proc$libresoc.v:144380$6507 + assign { } { } + assign $1\oper_r__oe__ok[0:0] 1'0 + sync always + sync init + update \oper_r__oe__ok $1\oper_r__oe__ok[0:0] + end + attribute \src "libresoc.v:144384.7-144384.28" + process $proc$libresoc.v:144384$6508 + assign { } { } + assign $1\oper_r__rc__ok[0:0] 1'0 + sync always + sync init + update \oper_r__rc__ok $1\oper_r__rc__ok[0:0] + end + attribute \src "libresoc.v:144388.7-144388.28" + process $proc$libresoc.v:144388$6509 + assign { } { } + assign $1\oper_r__rc__rc[0:0] 1'0 + sync always + sync init + update \oper_r__rc__rc $1\oper_r__rc__rc[0:0] + end + attribute \src "libresoc.v:144392.7-144392.33" + process $proc$libresoc.v:144392$6510 + assign { } { } + assign $1\oper_r__sign_extend[0:0] 1'0 + sync always + sync init + update \oper_r__sign_extend $1\oper_r__sign_extend[0:0] + end + attribute \src "libresoc.v:144396.7-144396.28" + process $proc$libresoc.v:144396$6511 + assign { } { } + assign $1\oper_r__zero_a[0:0] 1'0 + sync always + sync init + update \oper_r__zero_a $1\oper_r__zero_a[0:0] + end + attribute \src "libresoc.v:144400.7-144400.21" + process $proc$libresoc.v:144400$6512 + assign { } { } + assign $1\p_st_go[0:0] 1'0 + sync always + sync init + update \p_st_go $1\p_st_go[0:0] + end + attribute \src "libresoc.v:144442.13-144442.31" + process $proc$libresoc.v:144442$6513 + assign { } { } + assign $1\src_l_r_src[2:0] 3'111 + sync always + sync init + update \src_l_r_src $1\src_l_r_src[2:0] + end + attribute \src "libresoc.v:144446.13-144446.31" + process $proc$libresoc.v:144446$6514 + assign { } { } + assign $1\src_l_s_src[2:0] 3'000 + sync always + sync init + update \src_l_s_src $1\src_l_s_src[2:0] + end + attribute \src "libresoc.v:144450.14-144450.43" + process $proc$libresoc.v:144450$6515 + assign { } { } + assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \src_r0 $1\src_r0[63:0] + end + attribute \src "libresoc.v:144454.14-144454.43" + process $proc$libresoc.v:144454$6516 + assign { } { } + assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \src_r1 $1\src_r1[63:0] + end + attribute \src "libresoc.v:144458.14-144458.43" + process $proc$libresoc.v:144458$6517 + assign { } { } + assign $1\src_r2[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \src_r2 $1\src_r2[63:0] + end + attribute \src "libresoc.v:144468.7-144468.25" + process $proc$libresoc.v:144468$6518 + assign { } { } + assign $1\sto_l_r_sto[0:0] 1'1 + sync always + sync init + update \sto_l_r_sto $1\sto_l_r_sto[0:0] + end + attribute \src "libresoc.v:144478.7-144478.25" + process $proc$libresoc.v:144478$6519 + assign { } { } + assign $1\upd_l_r_upd[0:0] 1'1 + sync always + sync init + update \upd_l_r_upd $1\upd_l_r_upd[0:0] + end + attribute \src "libresoc.v:144482.7-144482.25" + process $proc$libresoc.v:144482$6520 + assign { } { } + assign $1\upd_l_s_upd[0:0] 1'0 + sync always + sync init + update \upd_l_s_upd $1\upd_l_s_upd[0:0] + end + attribute \src "libresoc.v:144492.7-144492.25" + process $proc$libresoc.v:144492$6521 + assign { } { } + assign $1\wri_l_r_wri[0:0] 1'1 + sync always + sync init + update \wri_l_r_wri $1\wri_l_r_wri[0:0] + end + attribute \src "libresoc.v:144588.3-144589.57" + process $proc$libresoc.v:144588$6338 + assign { } { } + assign $0\ldst_port0_addr_i_ok[0:0] \ldst_port0_addr_i_ok$next + sync posedge \coresync_clk + update \ldst_port0_addr_i_ok $0\ldst_port0_addr_i_ok[0:0] + end + attribute \src "libresoc.v:144590.3-144591.33" + process $proc$libresoc.v:144590$6339 + assign { } { } + assign $0\ldst_port0_addr_i[95:0] \$175 + sync posedge \coresync_clk + update \ldst_port0_addr_i $0\ldst_port0_addr_i[95:0] + end + attribute \src "libresoc.v:144592.3-144593.21" + process $proc$libresoc.v:144592$6340 + assign { } { } + assign $0\alu_ok[0:0] \$96 + sync posedge \coresync_clk + update \alu_ok $0\alu_ok[0:0] + end + attribute \src "libresoc.v:144594.3-144595.25" + process $proc$libresoc.v:144594$6341 + assign { } { } + assign $0\ea_r[63:0] \ea_r$next + sync posedge \coresync_clk + update \ea_r $0\ea_r[63:0] + end + attribute \src "libresoc.v:144596.3-144597.29" + process $proc$libresoc.v:144596$6342 + assign { } { } + assign $0\src_r2[63:0] \src_r2$next + sync posedge \coresync_clk + update \src_r2 $0\src_r2[63:0] + end + attribute \src "libresoc.v:144598.3-144599.29" + process $proc$libresoc.v:144598$6343 + assign { } { } + assign $0\src_r1[63:0] \src_r1$next + sync posedge \coresync_clk + update \src_r1 $0\src_r1[63:0] + end + attribute \src "libresoc.v:144600.3-144601.29" + process $proc$libresoc.v:144600$6344 + assign { } { } + assign $0\src_r0[63:0] \src_r0$next + sync posedge \coresync_clk + update \src_r0 $0\src_r0[63:0] + end + attribute \src "libresoc.v:144602.3-144603.27" + process $proc$libresoc.v:144602$6345 + assign { } { } + assign $0\ldo_r[63:0] \ldo_r$next + sync posedge \coresync_clk + update \ldo_r $0\ldo_r[63:0] + end + attribute \src "libresoc.v:144604.3-144605.51" + process $proc$libresoc.v:144604$6346 + assign { } { } + assign $0\oper_r__insn_type[6:0] \oper_r__insn_type$next + sync posedge \coresync_clk + update \oper_r__insn_type $0\oper_r__insn_type[6:0] + end + attribute \src "libresoc.v:144606.3-144607.47" + process $proc$libresoc.v:144606$6347 + assign { } { } + assign $0\oper_r__fn_unit[12:0] \oper_r__fn_unit$next + sync posedge \coresync_clk + update \oper_r__fn_unit $0\oper_r__fn_unit[12:0] + end + attribute \src "libresoc.v:144608.3-144609.61" + process $proc$libresoc.v:144608$6348 + assign { } { } + assign $0\oper_r__imm_data__data[63:0] \oper_r__imm_data__data$next + sync posedge \coresync_clk + update \oper_r__imm_data__data $0\oper_r__imm_data__data[63:0] + end + attribute \src "libresoc.v:144610.3-144611.57" + process $proc$libresoc.v:144610$6349 + assign { } { } + assign $0\oper_r__imm_data__ok[0:0] \oper_r__imm_data__ok$next + sync posedge \coresync_clk + update \oper_r__imm_data__ok $0\oper_r__imm_data__ok[0:0] + end + attribute \src "libresoc.v:144612.3-144613.45" + process $proc$libresoc.v:144612$6350 + assign { } { } + assign $0\oper_r__zero_a[0:0] \oper_r__zero_a$next + sync posedge \coresync_clk + update \oper_r__zero_a $0\oper_r__zero_a[0:0] + end + attribute \src "libresoc.v:144614.3-144615.45" + process $proc$libresoc.v:144614$6351 + assign { } { } + assign $0\oper_r__rc__rc[0:0] \oper_r__rc__rc$next + sync posedge \coresync_clk + update \oper_r__rc__rc $0\oper_r__rc__rc[0:0] + end + attribute \src "libresoc.v:144616.3-144617.45" + process $proc$libresoc.v:144616$6352 + assign { } { } + assign $0\oper_r__rc__ok[0:0] \oper_r__rc__ok$next + sync posedge \coresync_clk + update \oper_r__rc__ok $0\oper_r__rc__ok[0:0] + end + attribute \src "libresoc.v:144618.3-144619.45" + process $proc$libresoc.v:144618$6353 + assign { } { } + assign $0\oper_r__oe__oe[0:0] \oper_r__oe__oe$next + sync posedge \coresync_clk + update \oper_r__oe__oe $0\oper_r__oe__oe[0:0] + end + attribute \src "libresoc.v:144620.3-144621.45" + process $proc$libresoc.v:144620$6354 + assign { } { } + assign $0\oper_r__oe__ok[0:0] \oper_r__oe__ok$next + sync posedge \coresync_clk + update \oper_r__oe__ok $0\oper_r__oe__ok[0:0] + end + attribute \src "libresoc.v:144622.3-144623.49" + process $proc$libresoc.v:144622$6355 + assign { } { } + assign $0\oper_r__is_32bit[0:0] \oper_r__is_32bit$next + sync posedge \coresync_clk + update \oper_r__is_32bit $0\oper_r__is_32bit[0:0] + end + attribute \src "libresoc.v:144624.3-144625.51" + process $proc$libresoc.v:144624$6356 + assign { } { } + assign $0\oper_r__is_signed[0:0] \oper_r__is_signed$next + sync posedge \coresync_clk + update \oper_r__is_signed $0\oper_r__is_signed[0:0] + end + attribute \src "libresoc.v:144626.3-144627.49" + process $proc$libresoc.v:144626$6357 + assign { } { } + assign $0\oper_r__data_len[3:0] \oper_r__data_len$next + sync posedge \coresync_clk + update \oper_r__data_len $0\oper_r__data_len[3:0] + end + attribute \src "libresoc.v:144628.3-144629.57" + process $proc$libresoc.v:144628$6358 + assign { } { } + assign $0\oper_r__byte_reverse[0:0] \oper_r__byte_reverse$next + sync posedge \coresync_clk + update \oper_r__byte_reverse $0\oper_r__byte_reverse[0:0] + end + attribute \src "libresoc.v:144630.3-144631.55" + process $proc$libresoc.v:144630$6359 + assign { } { } + assign $0\oper_r__sign_extend[0:0] \oper_r__sign_extend$next + sync posedge \coresync_clk + update \oper_r__sign_extend $0\oper_r__sign_extend[0:0] + end + attribute \src "libresoc.v:144632.3-144633.51" + process $proc$libresoc.v:144632$6360 + assign { } { } + assign $0\oper_r__ldst_mode[1:0] \oper_r__ldst_mode$next + sync posedge \coresync_clk + update \oper_r__ldst_mode $0\oper_r__ldst_mode[1:0] + end + attribute \src "libresoc.v:144634.3-144635.41" + process $proc$libresoc.v:144634$6361 + assign { } { } + assign $0\oper_r__insn[31:0] \oper_r__insn$next + sync posedge \coresync_clk + update \oper_r__insn $0\oper_r__insn[31:0] + end + attribute \src "libresoc.v:144636.3-144637.39" + process $proc$libresoc.v:144636$6362 + assign { } { } + assign $0\lsd_l_r_lsd[0:0] \lsd_l_r_lsd$next + sync posedge \coresync_clk + update \lsd_l_r_lsd $0\lsd_l_r_lsd[0:0] + end + attribute \src "libresoc.v:144638.3-144639.39" + process $proc$libresoc.v:144638$6363 + assign { } { } + assign $0\sto_l_r_sto[0:0] \sto_l_r_sto$next + sync posedge \coresync_clk + update \sto_l_r_sto $0\sto_l_r_sto[0:0] + end + attribute \src "libresoc.v:144640.3-144641.39" + process $proc$libresoc.v:144640$6364 + assign { } { } + assign $0\upd_l_r_upd[0:0] \upd_l_r_upd$next + sync posedge \coresync_clk + update \upd_l_r_upd $0\upd_l_r_upd[0:0] + end + attribute \src "libresoc.v:144642.3-144643.39" + process $proc$libresoc.v:144642$6365 + assign { } { } + assign $0\upd_l_s_upd[0:0] \upd_l_s_upd$next + sync posedge \coresync_clk + update \upd_l_s_upd $0\upd_l_s_upd[0:0] + end + attribute \src "libresoc.v:144644.3-144645.39" + process $proc$libresoc.v:144644$6366 + assign { } { } + assign $0\wri_l_r_wri[0:0] \wri_l_r_wri$next + sync posedge \coresync_clk + update \wri_l_r_wri $0\wri_l_r_wri[0:0] + end + attribute \src "libresoc.v:144646.3-144647.39" + process $proc$libresoc.v:144646$6367 + assign { } { } + assign $0\adr_l_r_adr[0:0] \adr_l_r_adr$next + sync posedge \coresync_clk + update \adr_l_r_adr $0\adr_l_r_adr[0:0] + end + attribute \src "libresoc.v:144648.3-144649.39" + process $proc$libresoc.v:144648$6368 + assign { } { } + assign $0\src_l_r_src[2:0] \src_l_r_src$next + sync posedge \coresync_clk + update \src_l_r_src $0\src_l_r_src[2:0] + end + attribute \src "libresoc.v:144650.3-144651.39" + process $proc$libresoc.v:144650$6369 + assign { } { } + assign $0\src_l_s_src[2:0] \src_l_s_src$next + sync posedge \coresync_clk + update \src_l_s_src $0\src_l_s_src[2:0] + end + attribute \src "libresoc.v:144652.3-144653.39" + process $proc$libresoc.v:144652$6370 + assign { } { } + assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next + sync posedge \coresync_clk + update \opc_l_r_opc $0\opc_l_r_opc[0:0] + end + attribute \src "libresoc.v:144654.3-144655.39" + process $proc$libresoc.v:144654$6371 + assign { } { } + assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next + sync posedge \coresync_clk + update \opc_l_s_opc $0\opc_l_s_opc[0:0] + end + attribute \src "libresoc.v:144656.3-144657.28" + process $proc$libresoc.v:144656$6372 + assign { } { } + assign $0\p_st_go[0:0] \cu_st__go_i + sync posedge \coresync_clk + update \p_st_go $0\p_st_go[0:0] + end + attribute \src "libresoc.v:144728.3-144736.6" + process $proc$libresoc.v:144728$6373 + assign { } { } + assign { } { } + assign $0\opc_l_s_opc$next[0:0]$6374 $1\opc_l_s_opc$next[0:0]$6375 + attribute \src "libresoc.v:144729.5-144729.29" + switch \initial + attribute \src "libresoc.v:144729.9-144729.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\opc_l_s_opc$next[0:0]$6375 1'0 + case + assign $1\opc_l_s_opc$next[0:0]$6375 \cu_issue_i + end + sync always + update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$6374 + end + attribute \src "libresoc.v:144737.3-144745.6" + process $proc$libresoc.v:144737$6376 + assign { } { } + assign { } { } + assign $0\opc_l_r_opc$next[0:0]$6377 $1\opc_l_r_opc$next[0:0]$6378 + attribute \src "libresoc.v:144738.5-144738.29" + switch \initial + attribute \src "libresoc.v:144738.9-144738.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\opc_l_r_opc$next[0:0]$6378 1'1 + case + assign $1\opc_l_r_opc$next[0:0]$6378 \reset_o + end + sync always + update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$6377 + end + attribute \src "libresoc.v:144746.3-144754.6" + process $proc$libresoc.v:144746$6379 + assign { } { } + assign { } { } + assign $0\src_l_s_src$next[2:0]$6380 $1\src_l_s_src$next[2:0]$6381 + attribute \src "libresoc.v:144747.5-144747.29" + switch \initial + attribute \src "libresoc.v:144747.9-144747.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_l_s_src$next[2:0]$6381 3'000 + case + assign $1\src_l_s_src$next[2:0]$6381 { \cu_issue_i \cu_issue_i \cu_issue_i } + end + sync always + update \src_l_s_src$next $0\src_l_s_src$next[2:0]$6380 + end + attribute \src "libresoc.v:144755.3-144763.6" + process $proc$libresoc.v:144755$6382 + assign { } { } + assign { } { } + assign $0\src_l_r_src$next[2:0]$6383 $1\src_l_r_src$next[2:0]$6384 + attribute \src "libresoc.v:144756.5-144756.29" + switch \initial + attribute \src "libresoc.v:144756.9-144756.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_l_r_src$next[2:0]$6384 3'111 + case + assign $1\src_l_r_src$next[2:0]$6384 \reset_r + end + sync always + update \src_l_r_src$next $0\src_l_r_src$next[2:0]$6383 + end + attribute \src "libresoc.v:144764.3-144772.6" + process $proc$libresoc.v:144764$6385 + assign { } { } + assign { } { } + assign $0\adr_l_r_adr$next[0:0]$6386 $1\adr_l_r_adr$next[0:0]$6387 + attribute \src "libresoc.v:144765.5-144765.29" + switch \initial + attribute \src "libresoc.v:144765.9-144765.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\adr_l_r_adr$next[0:0]$6387 1'1 + case + assign $1\adr_l_r_adr$next[0:0]$6387 \reset_a + end + sync always + update \adr_l_r_adr$next $0\adr_l_r_adr$next[0:0]$6386 + end + attribute \src "libresoc.v:144773.3-144781.6" + process $proc$libresoc.v:144773$6388 + assign { } { } + assign { } { } + assign $0\wri_l_r_wri$next[0:0]$6389 $1\wri_l_r_wri$next[0:0]$6390 + attribute \src "libresoc.v:144774.5-144774.29" + switch \initial + attribute \src "libresoc.v:144774.9-144774.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wri_l_r_wri$next[0:0]$6390 1'1 + case + assign $1\wri_l_r_wri$next[0:0]$6390 \$38 [0] + end + sync always + update \wri_l_r_wri$next $0\wri_l_r_wri$next[0:0]$6389 + end + attribute \src "libresoc.v:144782.3-144790.6" + process $proc$libresoc.v:144782$6391 + assign { } { } + assign { } { } + assign $0\upd_l_s_upd$next[0:0]$6392 $1\upd_l_s_upd$next[0:0]$6393 + attribute \src "libresoc.v:144783.5-144783.29" + switch \initial + attribute \src "libresoc.v:144783.9-144783.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\upd_l_s_upd$next[0:0]$6393 1'0 + case + assign $1\upd_l_s_upd$next[0:0]$6393 \reset_i + end + sync always + update \upd_l_s_upd$next $0\upd_l_s_upd$next[0:0]$6392 + end + attribute \src "libresoc.v:144791.3-144799.6" + process $proc$libresoc.v:144791$6394 + assign { } { } + assign { } { } + assign $0\upd_l_r_upd$next[0:0]$6395 $1\upd_l_r_upd$next[0:0]$6396 + attribute \src "libresoc.v:144792.5-144792.29" + switch \initial + attribute \src "libresoc.v:144792.9-144792.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\upd_l_r_upd$next[0:0]$6396 1'1 + case + assign $1\upd_l_r_upd$next[0:0]$6396 \reset_u + end + sync always + update \upd_l_r_upd$next $0\upd_l_r_upd$next[0:0]$6395 + end + attribute \src "libresoc.v:144800.3-144808.6" + process $proc$libresoc.v:144800$6397 + assign { } { } + assign { } { } + assign $0\sto_l_r_sto$next[0:0]$6398 $1\sto_l_r_sto$next[0:0]$6399 + attribute \src "libresoc.v:144801.5-144801.29" + switch \initial + attribute \src "libresoc.v:144801.9-144801.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\sto_l_r_sto$next[0:0]$6399 1'1 + case + assign $1\sto_l_r_sto$next[0:0]$6399 \$59 + end + sync always + update \sto_l_r_sto$next $0\sto_l_r_sto$next[0:0]$6398 + end + attribute \src "libresoc.v:144809.3-144817.6" + process $proc$libresoc.v:144809$6400 + assign { } { } + assign { } { } + assign $0\lsd_l_r_lsd$next[0:0]$6401 $1\lsd_l_r_lsd$next[0:0]$6402 + attribute \src "libresoc.v:144810.5-144810.29" + switch \initial + attribute \src "libresoc.v:144810.9-144810.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\lsd_l_r_lsd$next[0:0]$6402 1'1 + case + assign $1\lsd_l_r_lsd$next[0:0]$6402 \$63 + end + sync always + update \lsd_l_r_lsd$next $0\lsd_l_r_lsd$next[0:0]$6401 + end + attribute \src "libresoc.v:144818.3-144860.6" + process $proc$libresoc.v:144818$6403 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\oper_r__byte_reverse$next[0:0]$6404 $2\oper_r__byte_reverse$next[0:0]$6436 + assign $0\oper_r__data_len$next[3:0]$6405 $2\oper_r__data_len$next[3:0]$6437 + assign $0\oper_r__fn_unit$next[12:0]$6406 $2\oper_r__fn_unit$next[12:0]$6438 + assign { } { } + assign { } { } + assign $0\oper_r__insn$next[31:0]$6409 $2\oper_r__insn$next[31:0]$6441 + assign $0\oper_r__insn_type$next[6:0]$6410 $2\oper_r__insn_type$next[6:0]$6442 + assign $0\oper_r__is_32bit$next[0:0]$6411 $2\oper_r__is_32bit$next[0:0]$6443 + assign $0\oper_r__is_signed$next[0:0]$6412 $2\oper_r__is_signed$next[0:0]$6444 + assign $0\oper_r__ldst_mode$next[1:0]$6413 $2\oper_r__ldst_mode$next[1:0]$6445 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\oper_r__sign_extend$next[0:0]$6418 $2\oper_r__sign_extend$next[0:0]$6450 + assign $0\oper_r__zero_a$next[0:0]$6419 $2\oper_r__zero_a$next[0:0]$6451 + assign $0\oper_r__imm_data__data$next[63:0]$6407 $3\oper_r__imm_data__data$next[63:0]$6452 + assign $0\oper_r__imm_data__ok$next[0:0]$6408 $3\oper_r__imm_data__ok$next[0:0]$6453 + assign $0\oper_r__oe__oe$next[0:0]$6414 $3\oper_r__oe__oe$next[0:0]$6454 + assign $0\oper_r__oe__ok$next[0:0]$6415 $3\oper_r__oe__ok$next[0:0]$6455 + assign $0\oper_r__rc__ok$next[0:0]$6416 $3\oper_r__rc__ok$next[0:0]$6456 + assign $0\oper_r__rc__rc$next[0:0]$6417 $3\oper_r__rc__rc$next[0:0]$6457 + attribute \src "libresoc.v:144819.5-144819.29" + switch \initial + attribute \src "libresoc.v:144819.9-144819.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:379" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\oper_r__insn$next[31:0]$6425 $1\oper_r__ldst_mode$next[1:0]$6429 $1\oper_r__sign_extend$next[0:0]$6434 $1\oper_r__byte_reverse$next[0:0]$6420 $1\oper_r__data_len$next[3:0]$6421 $1\oper_r__is_signed$next[0:0]$6428 $1\oper_r__is_32bit$next[0:0]$6427 $1\oper_r__oe__ok$next[0:0]$6431 $1\oper_r__oe__oe$next[0:0]$6430 $1\oper_r__rc__ok$next[0:0]$6432 $1\oper_r__rc__rc$next[0:0]$6433 $1\oper_r__zero_a$next[0:0]$6435 $1\oper_r__imm_data__ok$next[0:0]$6424 $1\oper_r__imm_data__data$next[63:0]$6423 $1\oper_r__fn_unit$next[12:0]$6422 $1\oper_r__insn_type$next[6:0]$6426 } { \oper_i_ldst_ldst0__insn \oper_i_ldst_ldst0__ldst_mode \oper_i_ldst_ldst0__sign_extend \oper_i_ldst_ldst0__byte_reverse \oper_i_ldst_ldst0__data_len \oper_i_ldst_ldst0__is_signed \oper_i_ldst_ldst0__is_32bit \oper_i_ldst_ldst0__oe__ok \oper_i_ldst_ldst0__oe__oe \oper_i_ldst_ldst0__rc__ok \oper_i_ldst_ldst0__rc__rc \oper_i_ldst_ldst0__zero_a \oper_i_ldst_ldst0__imm_data__ok \oper_i_ldst_ldst0__imm_data__data \oper_i_ldst_ldst0__fn_unit \oper_i_ldst_ldst0__insn_type } + case + assign $1\oper_r__byte_reverse$next[0:0]$6420 \oper_r__byte_reverse + assign $1\oper_r__data_len$next[3:0]$6421 \oper_r__data_len + assign $1\oper_r__fn_unit$next[12:0]$6422 \oper_r__fn_unit + assign $1\oper_r__imm_data__data$next[63:0]$6423 \oper_r__imm_data__data + assign $1\oper_r__imm_data__ok$next[0:0]$6424 \oper_r__imm_data__ok + assign $1\oper_r__insn$next[31:0]$6425 \oper_r__insn + assign $1\oper_r__insn_type$next[6:0]$6426 \oper_r__insn_type + assign $1\oper_r__is_32bit$next[0:0]$6427 \oper_r__is_32bit + assign $1\oper_r__is_signed$next[0:0]$6428 \oper_r__is_signed + assign $1\oper_r__ldst_mode$next[1:0]$6429 \oper_r__ldst_mode + assign $1\oper_r__oe__oe$next[0:0]$6430 \oper_r__oe__oe + assign $1\oper_r__oe__ok$next[0:0]$6431 \oper_r__oe__ok + assign $1\oper_r__rc__ok$next[0:0]$6432 \oper_r__rc__ok + assign $1\oper_r__rc__rc$next[0:0]$6433 \oper_r__rc__rc + assign $1\oper_r__sign_extend$next[0:0]$6434 \oper_r__sign_extend + assign $1\oper_r__zero_a$next[0:0]$6435 \oper_r__zero_a + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:381" + switch \cu_done_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $2\oper_r__insn$next[31:0]$6441 $2\oper_r__ldst_mode$next[1:0]$6445 $2\oper_r__sign_extend$next[0:0]$6450 $2\oper_r__byte_reverse$next[0:0]$6436 $2\oper_r__data_len$next[3:0]$6437 $2\oper_r__is_signed$next[0:0]$6444 $2\oper_r__is_32bit$next[0:0]$6443 $2\oper_r__oe__ok$next[0:0]$6447 $2\oper_r__oe__oe$next[0:0]$6446 $2\oper_r__rc__ok$next[0:0]$6448 $2\oper_r__rc__rc$next[0:0]$6449 $2\oper_r__zero_a$next[0:0]$6451 $2\oper_r__imm_data__ok$next[0:0]$6440 $2\oper_r__imm_data__data$next[63:0]$6439 $2\oper_r__fn_unit$next[12:0]$6438 $2\oper_r__insn_type$next[6:0]$6442 } 132'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + case + assign $2\oper_r__byte_reverse$next[0:0]$6436 $1\oper_r__byte_reverse$next[0:0]$6420 + assign $2\oper_r__data_len$next[3:0]$6437 $1\oper_r__data_len$next[3:0]$6421 + assign $2\oper_r__fn_unit$next[12:0]$6438 $1\oper_r__fn_unit$next[12:0]$6422 + assign $2\oper_r__imm_data__data$next[63:0]$6439 $1\oper_r__imm_data__data$next[63:0]$6423 + assign $2\oper_r__imm_data__ok$next[0:0]$6440 $1\oper_r__imm_data__ok$next[0:0]$6424 + assign $2\oper_r__insn$next[31:0]$6441 $1\oper_r__insn$next[31:0]$6425 + assign $2\oper_r__insn_type$next[6:0]$6442 $1\oper_r__insn_type$next[6:0]$6426 + assign $2\oper_r__is_32bit$next[0:0]$6443 $1\oper_r__is_32bit$next[0:0]$6427 + assign $2\oper_r__is_signed$next[0:0]$6444 $1\oper_r__is_signed$next[0:0]$6428 + assign $2\oper_r__ldst_mode$next[1:0]$6445 $1\oper_r__ldst_mode$next[1:0]$6429 + assign $2\oper_r__oe__oe$next[0:0]$6446 $1\oper_r__oe__oe$next[0:0]$6430 + assign $2\oper_r__oe__ok$next[0:0]$6447 $1\oper_r__oe__ok$next[0:0]$6431 + assign $2\oper_r__rc__ok$next[0:0]$6448 $1\oper_r__rc__ok$next[0:0]$6432 + assign $2\oper_r__rc__rc$next[0:0]$6449 $1\oper_r__rc__rc$next[0:0]$6433 + assign $2\oper_r__sign_extend$next[0:0]$6450 $1\oper_r__sign_extend$next[0:0]$6434 + assign $2\oper_r__zero_a$next[0:0]$6451 $1\oper_r__zero_a$next[0:0]$6435 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $3\oper_r__imm_data__data$next[63:0]$6452 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\oper_r__imm_data__ok$next[0:0]$6453 1'0 + assign $3\oper_r__rc__rc$next[0:0]$6457 1'0 + assign $3\oper_r__rc__ok$next[0:0]$6456 1'0 + assign $3\oper_r__oe__oe$next[0:0]$6454 1'0 + assign $3\oper_r__oe__ok$next[0:0]$6455 1'0 + case + assign $3\oper_r__imm_data__data$next[63:0]$6452 $2\oper_r__imm_data__data$next[63:0]$6439 + assign $3\oper_r__imm_data__ok$next[0:0]$6453 $2\oper_r__imm_data__ok$next[0:0]$6440 + assign $3\oper_r__oe__oe$next[0:0]$6454 $2\oper_r__oe__oe$next[0:0]$6446 + assign $3\oper_r__oe__ok$next[0:0]$6455 $2\oper_r__oe__ok$next[0:0]$6447 + assign $3\oper_r__rc__ok$next[0:0]$6456 $2\oper_r__rc__ok$next[0:0]$6448 + assign $3\oper_r__rc__rc$next[0:0]$6457 $2\oper_r__rc__rc$next[0:0]$6449 + end + sync always + update \oper_r__byte_reverse$next $0\oper_r__byte_reverse$next[0:0]$6404 + update \oper_r__data_len$next $0\oper_r__data_len$next[3:0]$6405 + update \oper_r__fn_unit$next $0\oper_r__fn_unit$next[12:0]$6406 + update \oper_r__imm_data__data$next $0\oper_r__imm_data__data$next[63:0]$6407 + update \oper_r__imm_data__ok$next $0\oper_r__imm_data__ok$next[0:0]$6408 + update \oper_r__insn$next $0\oper_r__insn$next[31:0]$6409 + update \oper_r__insn_type$next $0\oper_r__insn_type$next[6:0]$6410 + update \oper_r__is_32bit$next $0\oper_r__is_32bit$next[0:0]$6411 + update \oper_r__is_signed$next $0\oper_r__is_signed$next[0:0]$6412 + update \oper_r__ldst_mode$next $0\oper_r__ldst_mode$next[1:0]$6413 + update \oper_r__oe__oe$next $0\oper_r__oe__oe$next[0:0]$6414 + update \oper_r__oe__ok$next $0\oper_r__oe__ok$next[0:0]$6415 + update \oper_r__rc__ok$next $0\oper_r__rc__ok$next[0:0]$6416 + update \oper_r__rc__rc$next $0\oper_r__rc__rc$next[0:0]$6417 + update \oper_r__sign_extend$next $0\oper_r__sign_extend$next[0:0]$6418 + update \oper_r__zero_a$next $0\oper_r__zero_a$next[0:0]$6419 + end + attribute \src "libresoc.v:144861.3-144870.6" + process $proc$libresoc.v:144861$6458 + assign { } { } + assign { } { } + assign $0\ldo_r$next[63:0]$6459 $1\ldo_r$next[63:0]$6460 + attribute \src "libresoc.v:144862.5-144862.29" + switch \initial + attribute \src "libresoc.v:144862.9-144862.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" + switch \ld_ok + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ldo_r$next[63:0]$6460 \ldd_o + case + assign $1\ldo_r$next[63:0]$6460 \ldo_r + end + sync always + update \ldo_r$next $0\ldo_r$next[63:0]$6459 + end + attribute \src "libresoc.v:144871.3-144886.6" + process $proc$libresoc.v:144871$6461 + assign { } { } + assign { } { } + assign { } { } + assign $0\src_r0$next[63:0]$6462 $2\src_r0$next[63:0]$6464 + attribute \src "libresoc.v:144872.5-144872.29" + switch \initial + attribute \src "libresoc.v:144872.9-144872.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:393" + switch \cu_rd__go_i [0] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r0$next[63:0]$6463 \src1_i + case + assign $1\src_r0$next[63:0]$6463 \src_r0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:395" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src_r0$next[63:0]$6464 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $2\src_r0$next[63:0]$6464 $1\src_r0$next[63:0]$6463 + end + sync always + update \src_r0$next $0\src_r0$next[63:0]$6462 + end + attribute \src "libresoc.v:144887.3-144902.6" + process $proc$libresoc.v:144887$6465 + assign { } { } + assign { } { } + assign { } { } + assign $0\src_r1$next[63:0]$6466 $2\src_r1$next[63:0]$6468 + attribute \src "libresoc.v:144888.5-144888.29" + switch \initial + attribute \src "libresoc.v:144888.9-144888.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:393" + switch \cu_rd__go_i [1] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r1$next[63:0]$6467 \src2_i + case + assign $1\src_r1$next[63:0]$6467 \src_r1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:395" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src_r1$next[63:0]$6468 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $2\src_r1$next[63:0]$6468 $1\src_r1$next[63:0]$6467 + end + sync always + update \src_r1$next $0\src_r1$next[63:0]$6466 + end + attribute \src "libresoc.v:144903.3-144918.6" + process $proc$libresoc.v:144903$6469 + assign { } { } + assign { } { } + assign { } { } + assign $0\src_r2$next[63:0]$6470 $2\src_r2$next[63:0]$6472 + attribute \src "libresoc.v:144904.5-144904.29" + switch \initial + attribute \src "libresoc.v:144904.9-144904.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:393" + switch \cu_rd__go_i [2] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r2$next[63:0]$6471 \src3_i + case + assign $1\src_r2$next[63:0]$6471 \src_r2 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:395" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src_r2$next[63:0]$6472 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $2\src_r2$next[63:0]$6472 $1\src_r2$next[63:0]$6471 + end + sync always + update \src_r2$next $0\src_r2$next[63:0]$6470 + end + attribute \src "libresoc.v:144919.3-144928.6" + process $proc$libresoc.v:144919$6473 + assign { } { } + assign { } { } + assign $0\ea_r$next[63:0]$6474 $1\ea_r$next[63:0]$6475 + attribute \src "libresoc.v:144920.5-144920.29" + switch \initial + attribute \src "libresoc.v:144920.9-144920.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" + switch \alu_l_q_alu + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ea_r$next[63:0]$6475 \alu_o + case + assign $1\ea_r$next[63:0]$6475 \ea_r + end + sync always + update \ea_r$next $0\ea_r$next[63:0]$6474 + end + attribute \src "libresoc.v:144929.3-144938.6" + process $proc$libresoc.v:144929$6476 + assign { } { } + assign { } { } + assign $0\dest1_o[63:0] $1\dest1_o[63:0] + attribute \src "libresoc.v:144930.5-144930.29" + switch \initial + attribute \src "libresoc.v:144930.9-144930.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:472" + switch \cu_wr__go_i [0] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest1_o[63:0] \ldd_r + case + assign $1\dest1_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \dest1_o $0\dest1_o[63:0] + end + attribute \src "libresoc.v:144939.3-144948.6" + process $proc$libresoc.v:144939$6477 + assign { } { } + assign { } { } + assign $0\dest2_o[63:0] $1\dest2_o[63:0] + attribute \src "libresoc.v:144940.5-144940.29" + switch \initial + attribute \src "libresoc.v:144940.9-144940.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:477" + switch \$164 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest2_o[63:0] \addr_r + case + assign $1\dest2_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \dest2_o $0\dest2_o[63:0] + end + attribute \src "libresoc.v:144949.3-144957.6" + process $proc$libresoc.v:144949$6478 + assign { } { } + assign { } { } + assign $0\ldst_port0_addr_i_ok$next[0:0]$6479 $1\ldst_port0_addr_i_ok$next[0:0]$6480 + attribute \src "libresoc.v:144950.5-144950.29" + switch \initial + attribute \src "libresoc.v:144950.9-144950.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ldst_port0_addr_i_ok$next[0:0]$6480 1'0 + case + assign $1\ldst_port0_addr_i_ok$next[0:0]$6480 \$177 + end + sync always + update \ldst_port0_addr_i_ok$next $0\ldst_port0_addr_i_ok$next[0:0]$6479 + end + attribute \src "libresoc.v:144958.3-144981.6" + process $proc$libresoc.v:144958$6481 + assign { } { } + assign { } { } + assign $0\lddata_r[63:0] $1\lddata_r[63:0] + attribute \src "libresoc.v:144959.5-144959.29" + switch \initial + attribute \src "libresoc.v:144959.9-144959.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:500" + switch \oper_r__byte_reverse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\lddata_r[63:0] $2\lddata_r[63:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:28" + switch \oper_r__data_len + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $2\lddata_r[63:0] \$186 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $2\lddata_r[63:0] \$188 + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $2\lddata_r[63:0] \$190 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $2\lddata_r[63:0] { \ldst_port0_ld_data_o [7:0] \ldst_port0_ld_data_o [15:8] \ldst_port0_ld_data_o [23:16] \ldst_port0_ld_data_o [31:24] \ldst_port0_ld_data_o [39:32] \ldst_port0_ld_data_o [47:40] \ldst_port0_ld_data_o [55:48] \ldst_port0_ld_data_o [63:56] } + case + assign $2\lddata_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + case + assign $1\lddata_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \lddata_r $0\lddata_r[63:0] + end + attribute \src "libresoc.v:144982.3-144993.6" + process $proc$libresoc.v:144982$6482 + assign { } { } + assign $0\revnorev[63:0] $1\revnorev[63:0] + attribute \src "libresoc.v:144983.5-144983.29" + switch \initial + attribute \src "libresoc.v:144983.9-144983.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:500" + switch \oper_r__byte_reverse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\revnorev[63:0] \lddata_r + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\revnorev[63:0] \ldst_port0_ld_data_o + end + sync always + update \revnorev $0\revnorev[63:0] + end + attribute \src "libresoc.v:144994.3-145013.6" + process $proc$libresoc.v:144994$6483 + assign { } { } + assign $0\ldd_o[63:0] $1\ldd_o[63:0] + attribute \src "libresoc.v:144995.5-144995.29" + switch \initial + attribute \src "libresoc.v:144995.9-144995.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:509" + switch \oper_r__sign_extend + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ldd_o[63:0] $2\ldd_o[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:511" + switch \$192 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ldd_o[63:0] { \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15:0] } + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\ldd_o[63:0] { \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31:0] } + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\ldd_o[63:0] \revnorev + end + sync always + update \ldd_o $0\ldd_o[63:0] + end + attribute \src "libresoc.v:145014.3-145037.6" + process $proc$libresoc.v:145014$6484 + assign { } { } + assign { } { } + assign $0\stdata_r[63:0] $1\stdata_r[63:0] + attribute \src "libresoc.v:145015.5-145015.29" + switch \initial + attribute \src "libresoc.v:145015.9-145015.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:523" + switch \oper_r__byte_reverse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\stdata_r[63:0] $2\stdata_r[63:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:28" + switch \oper_r__data_len + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $2\stdata_r[63:0] \$194 + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $2\stdata_r[63:0] \$196 + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $2\stdata_r[63:0] \$198 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $2\stdata_r[63:0] { \src_r2 [7:0] \src_r2 [15:8] \src_r2 [23:16] \src_r2 [31:24] \src_r2 [39:32] \src_r2 [47:40] \src_r2 [55:48] \src_r2 [63:56] } + case + assign $2\stdata_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + case + assign $1\stdata_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \stdata_r $0\stdata_r[63:0] + end + attribute \src "libresoc.v:145038.3-145049.6" + process $proc$libresoc.v:145038$6485 + assign { } { } + assign $0\ldst_port0_st_data_i[63:0] $1\ldst_port0_st_data_i[63:0] + attribute \src "libresoc.v:145039.5-145039.29" + switch \initial + attribute \src "libresoc.v:145039.9-145039.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:523" + switch \oper_r__byte_reverse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ldst_port0_st_data_i[63:0] \stdata_r + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\ldst_port0_st_data_i[63:0] \src_r2 + end + sync always + update \ldst_port0_st_data_i $0\ldst_port0_st_data_i[63:0] + end + connect \$100 $and$libresoc.v:144497$6244_Y + connect \$102 $and$libresoc.v:144498$6245_Y + connect \$104 $and$libresoc.v:144499$6246_Y + connect \$106 $and$libresoc.v:144500$6247_Y + connect \$108 $and$libresoc.v:144501$6248_Y + connect \$10 $or$libresoc.v:144502$6249_Y + connect \$110 $and$libresoc.v:144503$6250_Y + connect \$112 $and$libresoc.v:144504$6251_Y + connect \$114 $and$libresoc.v:144505$6252_Y + connect \$116 $and$libresoc.v:144506$6253_Y + connect \$118 $and$libresoc.v:144507$6254_Y + connect \$120 $and$libresoc.v:144508$6255_Y + connect \$122 $and$libresoc.v:144509$6256_Y + connect \$124 $and$libresoc.v:144510$6257_Y + connect \$126 $eq$libresoc.v:144511$6258_Y + connect \$128 $and$libresoc.v:144512$6259_Y + connect \$12 $or$libresoc.v:144513$6260_Y + connect \$130 $and$libresoc.v:144514$6261_Y + connect \$132 $and$libresoc.v:144515$6262_Y + connect \$134 $or$libresoc.v:144516$6263_Y + connect \$136 $or$libresoc.v:144517$6264_Y + connect \$138 $or$libresoc.v:144518$6265_Y + connect \$140 $and$libresoc.v:144519$6266_Y + connect \$142 $and$libresoc.v:144520$6267_Y + connect \$145 $or$libresoc.v:144521$6268_Y + connect \$147 $or$libresoc.v:144522$6269_Y + connect \$144 $not$libresoc.v:144523$6270_Y + connect \$14 $or$libresoc.v:144524$6271_Y + connect \$150 $and$libresoc.v:144525$6272_Y + connect \$152 $or$libresoc.v:144526$6273_Y + connect \$154 $and$libresoc.v:144527$6274_Y + connect \$156 $not$libresoc.v:144528$6275_Y + connect \$158 $or$libresoc.v:144529$6276_Y + connect \$160 $and$libresoc.v:144530$6277_Y + connect \$162 $eq$libresoc.v:144531$6278_Y + connect \$164 $and$libresoc.v:144532$6279_Y + connect \$167 $eq$libresoc.v:144533$6280_Y + connect \$16 $or$libresoc.v:144534$6281_Y + connect \$169 $and$libresoc.v:144535$6282_Y + connect \$171 $and$libresoc.v:144536$6283_Y + connect \$173 $and$libresoc.v:144537$6284_Y + connect \$175 $pos$libresoc.v:144538$6286_Y + connect \$177 $and$libresoc.v:144539$6287_Y + connect \$186 $pos$libresoc.v:144540$6289_Y + connect \$188 $pos$libresoc.v:144541$6290_Y + connect \$18 $or$libresoc.v:144542$6291_Y + connect \$190 $pos$libresoc.v:144543$6292_Y + connect \$192 $eq$libresoc.v:144544$6293_Y + connect \$194 $pos$libresoc.v:144545$6295_Y + connect \$196 $pos$libresoc.v:144546$6296_Y + connect \$198 $pos$libresoc.v:144547$6297_Y + connect \$20 $or$libresoc.v:144548$6298_Y + connect \$22 $eq$libresoc.v:144549$6299_Y + connect \$24 $eq$libresoc.v:144550$6300_Y + connect \$26 $and$libresoc.v:144551$6301_Y + connect \$28 $and$libresoc.v:144552$6302_Y + connect \$30 $not$libresoc.v:144553$6303_Y + connect \$32 $and$libresoc.v:144554$6304_Y + connect \$34 $not$libresoc.v:144555$6305_Y + connect \$36 $and$libresoc.v:144556$6306_Y + connect \$39 $not$libresoc.v:144557$6307_Y + connect \$41 $eq$libresoc.v:144558$6308_Y + connect \$43 $and$libresoc.v:144559$6309_Y + connect \$45 $or$libresoc.v:144560$6310_Y + connect \$47 $not$libresoc.v:144561$6311_Y + connect \$49 $eq$libresoc.v:144562$6312_Y + connect \$51 $and$libresoc.v:144563$6313_Y + connect \$53 $or$libresoc.v:144564$6314_Y + connect \$55 $or$libresoc.v:144565$6315_Y + connect \$57 $and$libresoc.v:144566$6316_Y + connect \$59 $or$libresoc.v:144567$6317_Y + connect \$61 $or$libresoc.v:144568$6318_Y + connect \$63 $or$libresoc.v:144569$6319_Y + connect \$65 $ternary$libresoc.v:144570$6320_Y + connect \$67 $ternary$libresoc.v:144571$6321_Y + connect \$69 $ternary$libresoc.v:144572$6322_Y + connect \$71 $ternary$libresoc.v:144573$6323_Y + connect \$74 $add$libresoc.v:144574$6324_Y + connect \$76 $and$libresoc.v:144575$6325_Y + connect \$78 $not$libresoc.v:144576$6326_Y + connect \$80 $and$libresoc.v:144577$6327_Y + connect \$82 $not$libresoc.v:144578$6328_Y + connect \$84 $and$libresoc.v:144579$6329_Y + connect \$86 $and$libresoc.v:144580$6330_Y + connect \$88 $and$libresoc.v:144581$6331_Y + connect \$8 $or$libresoc.v:144582$6332_Y + connect \$90 $or$libresoc.v:144583$6333_Y + connect \$93 $or$libresoc.v:144584$6334_Y + connect \$92 $not$libresoc.v:144585$6335_Y + connect \$96 $and$libresoc.v:144586$6336_Y + connect \$98 $not$libresoc.v:144587$6337_Y + connect \$38 \$55 + connect \$73 \$74 + connect \$166 \$169 + connect \cu_go_die_i 1'0 + connect \cu_shadown_i 1'1 + connect \ldst_port0_st_data_i_ok \cu_st__go_i + connect \ld_ok \ldst_port0_ld_data_o_ok + connect \addr_ok \ldst_port0_addr_ok_o + connect { \exc_$signal$185 \exc_$signal$184 \exc_$signal$183 \exc_$signal$182 \exc_$signal$181 \exc_$signal$180 \exc_$signal$179 \exc_$signal } { \ldst_port0_exc_$signal$7 \ldst_port0_exc_$signal$6 \ldst_port0_exc_$signal$5 \ldst_port0_exc_$signal$4 \ldst_port0_exc_$signal$3 \ldst_port0_exc_$signal$2 \ldst_port0_exc_$signal$1 \ldst_port0_exc_$signal } + connect \ldst_port0_addr_i$next \$175 + connect \ldst_port0_data_len \oper_r__data_len + connect \ldst_port0_is_st_i \$173 + connect \ldst_port0_is_ld_i \$171 + connect \cu_wrmask_o \$169 [1:0] + connect \ea \dest2_o + connect \o \dest1_o + connect \cu_done_o \$160 + connect \wr_reset \$154 + connect \wr_any \$138 + connect \cu_wr__rel_o [1] \$132 + connect \cu_wr__rel_o [0] \$122 + connect \cu_st__rel_o \$112 + connect \cu_ad__rel_o \$104 + connect \rd_done \$100 + connect \alu_valid \$96 + connect \rda_any \$90 + connect \cu_rd__rel_o [2] \$88 + connect \cu_rd__rel_o [1:0] \$84 [1:0] + connect \cu_busy_o \opc_l_q_opc + connect \alu_ok$next \alu_valid + connect \alu_o \$74 [63:0] + connect \src2_or_imm \$71 + connect \src1_or_z \$69 + connect \addr_r \$67 + connect \ldd_r \$65 + connect \rst_l_r_rst \cu_issue_i + connect \rst_l_s_rst \addr_ok + connect \lsd_l_s_lsd \cu_issue_i + connect \sto_l_s_sto \$57 + connect \wri_l_s_wri \cu_issue_i + connect \lod_l_r_lod \ld_ok + connect \lod_l_s_lod \reset_i + connect \adr_l_s_adr \reset_i + connect \alu_l_r_alu \$36 + connect \alu_l_s_alu \reset_i + connect \st_o \op_is_st + connect \ld_o \op_is_ld + connect \stwd_mem_o \$28 + connect \load_mem_o \$26 + connect \op_is_ld \$24 + connect \op_is_st \$22 + connect \p_st_go$next \cu_st__go_i + connect \reset_a \$20 + connect \reset_r \$18 + connect \reset_s \$16 + connect \reset_u \$14 + connect \reset_w \$12 + connect \reset_o \$10 + connect \reset_i \$8 +end +attribute \src "libresoc.v:145113.1-145700.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1.main.rotator.left_mask" +attribute \generator "nMigen" +module \left_mask + attribute \src "libresoc.v:145114.7-145114.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:145312.3-145699.6" + wire width 64 $0\mask[63:0] + attribute \src "libresoc.v:145312.3-145699.6" + wire $10\mask[9:9] + attribute \src "libresoc.v:145312.3-145699.6" + wire $11\mask[10:10] + attribute \src "libresoc.v:145312.3-145699.6" + wire $12\mask[11:11] + attribute \src "libresoc.v:145312.3-145699.6" + wire $13\mask[12:12] + attribute \src "libresoc.v:145312.3-145699.6" + wire $14\mask[13:13] + attribute \src "libresoc.v:145312.3-145699.6" + wire $15\mask[14:14] + attribute \src "libresoc.v:145312.3-145699.6" + wire $16\mask[15:15] + attribute \src "libresoc.v:145312.3-145699.6" + wire $17\mask[16:16] + attribute \src "libresoc.v:145312.3-145699.6" + wire $18\mask[17:17] + attribute \src "libresoc.v:145312.3-145699.6" + wire $19\mask[18:18] + attribute \src "libresoc.v:145312.3-145699.6" + wire $1\mask[0:0] + attribute \src "libresoc.v:145312.3-145699.6" + wire $20\mask[19:19] + attribute \src "libresoc.v:145312.3-145699.6" + wire $21\mask[20:20] + attribute \src "libresoc.v:145312.3-145699.6" + wire $22\mask[21:21] + attribute \src "libresoc.v:145312.3-145699.6" + wire $23\mask[22:22] + attribute \src "libresoc.v:145312.3-145699.6" + wire $24\mask[23:23] + attribute \src "libresoc.v:145312.3-145699.6" + wire $25\mask[24:24] + attribute \src "libresoc.v:145312.3-145699.6" + wire $26\mask[25:25] + attribute \src "libresoc.v:145312.3-145699.6" + wire $27\mask[26:26] + attribute \src "libresoc.v:145312.3-145699.6" + wire $28\mask[27:27] + attribute \src "libresoc.v:145312.3-145699.6" + wire $29\mask[28:28] + attribute \src "libresoc.v:145312.3-145699.6" + wire $2\mask[1:1] + attribute \src "libresoc.v:145312.3-145699.6" + wire $30\mask[29:29] + attribute \src "libresoc.v:145312.3-145699.6" + wire $31\mask[30:30] + attribute \src "libresoc.v:145312.3-145699.6" + wire $32\mask[31:31] + attribute \src "libresoc.v:145312.3-145699.6" + wire $33\mask[32:32] + attribute \src "libresoc.v:145312.3-145699.6" + wire $34\mask[33:33] + attribute \src "libresoc.v:145312.3-145699.6" + wire $35\mask[34:34] + attribute \src "libresoc.v:145312.3-145699.6" + wire $36\mask[35:35] + attribute \src "libresoc.v:145312.3-145699.6" + wire $37\mask[36:36] + attribute \src "libresoc.v:145312.3-145699.6" + wire $38\mask[37:37] + attribute \src "libresoc.v:145312.3-145699.6" + wire $39\mask[38:38] + attribute \src "libresoc.v:145312.3-145699.6" + wire $3\mask[2:2] + attribute \src "libresoc.v:145312.3-145699.6" + wire $40\mask[39:39] + attribute \src "libresoc.v:145312.3-145699.6" + wire $41\mask[40:40] + attribute \src "libresoc.v:145312.3-145699.6" + wire $42\mask[41:41] + attribute \src "libresoc.v:145312.3-145699.6" + wire $43\mask[42:42] + attribute \src "libresoc.v:145312.3-145699.6" + wire $44\mask[43:43] + attribute \src "libresoc.v:145312.3-145699.6" + wire $45\mask[44:44] + attribute \src "libresoc.v:145312.3-145699.6" + wire $46\mask[45:45] + attribute \src "libresoc.v:145312.3-145699.6" + wire $47\mask[46:46] + attribute \src "libresoc.v:145312.3-145699.6" + wire $48\mask[47:47] + attribute \src "libresoc.v:145312.3-145699.6" + wire $49\mask[48:48] + attribute \src "libresoc.v:145312.3-145699.6" + wire $4\mask[3:3] + attribute \src "libresoc.v:145312.3-145699.6" + wire $50\mask[49:49] + attribute \src "libresoc.v:145312.3-145699.6" + wire $51\mask[50:50] + attribute \src "libresoc.v:145312.3-145699.6" + wire $52\mask[51:51] + attribute \src "libresoc.v:145312.3-145699.6" + wire $53\mask[52:52] + attribute \src "libresoc.v:145312.3-145699.6" + wire $54\mask[53:53] + attribute \src "libresoc.v:145312.3-145699.6" + wire $55\mask[54:54] + attribute \src "libresoc.v:145312.3-145699.6" + wire $56\mask[55:55] + attribute \src "libresoc.v:145312.3-145699.6" + wire $57\mask[56:56] + attribute \src "libresoc.v:145312.3-145699.6" + wire $58\mask[57:57] + attribute \src "libresoc.v:145312.3-145699.6" + wire $59\mask[58:58] + attribute \src "libresoc.v:145312.3-145699.6" + wire $5\mask[4:4] + attribute \src "libresoc.v:145312.3-145699.6" + wire $60\mask[59:59] + attribute \src "libresoc.v:145312.3-145699.6" + wire $61\mask[60:60] + attribute \src "libresoc.v:145312.3-145699.6" + wire $62\mask[61:61] + attribute \src "libresoc.v:145312.3-145699.6" + wire $63\mask[62:62] + attribute \src "libresoc.v:145312.3-145699.6" + wire $64\mask[63:63] + attribute \src "libresoc.v:145312.3-145699.6" + wire $6\mask[5:5] + attribute \src "libresoc.v:145312.3-145699.6" + wire $7\mask[6:6] + attribute \src "libresoc.v:145312.3-145699.6" + wire $8\mask[7:7] + attribute \src "libresoc.v:145312.3-145699.6" + wire $9\mask[8:8] + attribute \src "libresoc.v:145248.17-145248.96" + wire $gt$libresoc.v:145248$6522_Y + attribute \src "libresoc.v:145249.18-145249.98" + wire $gt$libresoc.v:145249$6523_Y + attribute \src "libresoc.v:145250.19-145250.99" + wire $gt$libresoc.v:145250$6524_Y + attribute \src "libresoc.v:145251.19-145251.99" + wire $gt$libresoc.v:145251$6525_Y + attribute \src "libresoc.v:145252.19-145252.99" + wire $gt$libresoc.v:145252$6526_Y + attribute \src "libresoc.v:145253.19-145253.99" + wire $gt$libresoc.v:145253$6527_Y + attribute \src "libresoc.v:145254.19-145254.99" + wire $gt$libresoc.v:145254$6528_Y + attribute \src "libresoc.v:145255.19-145255.99" + wire $gt$libresoc.v:145255$6529_Y + attribute \src "libresoc.v:145256.19-145256.99" + wire $gt$libresoc.v:145256$6530_Y + attribute \src "libresoc.v:145257.19-145257.99" + wire $gt$libresoc.v:145257$6531_Y + attribute \src "libresoc.v:145258.19-145258.99" + wire $gt$libresoc.v:145258$6532_Y + attribute \src "libresoc.v:145259.18-145259.97" + wire $gt$libresoc.v:145259$6533_Y + attribute \src "libresoc.v:145260.19-145260.99" + wire $gt$libresoc.v:145260$6534_Y + attribute \src "libresoc.v:145261.19-145261.99" + wire $gt$libresoc.v:145261$6535_Y + attribute \src "libresoc.v:145262.19-145262.99" + wire $gt$libresoc.v:145262$6536_Y + attribute \src "libresoc.v:145263.19-145263.99" + wire $gt$libresoc.v:145263$6537_Y + attribute \src "libresoc.v:145264.19-145264.99" + wire $gt$libresoc.v:145264$6538_Y + attribute \src "libresoc.v:145265.18-145265.97" + wire $gt$libresoc.v:145265$6539_Y + attribute \src "libresoc.v:145266.18-145266.97" + wire $gt$libresoc.v:145266$6540_Y + attribute \src "libresoc.v:145267.18-145267.97" + wire $gt$libresoc.v:145267$6541_Y + attribute \src "libresoc.v:145268.17-145268.96" + wire $gt$libresoc.v:145268$6542_Y + attribute \src "libresoc.v:145269.18-145269.97" + wire $gt$libresoc.v:145269$6543_Y + attribute \src "libresoc.v:145270.18-145270.97" + wire $gt$libresoc.v:145270$6544_Y + attribute \src "libresoc.v:145271.18-145271.97" + wire $gt$libresoc.v:145271$6545_Y + attribute \src "libresoc.v:145272.18-145272.97" + wire $gt$libresoc.v:145272$6546_Y + attribute \src "libresoc.v:145273.18-145273.97" + wire $gt$libresoc.v:145273$6547_Y + attribute \src "libresoc.v:145274.18-145274.97" + wire $gt$libresoc.v:145274$6548_Y + attribute \src "libresoc.v:145275.18-145275.97" + wire $gt$libresoc.v:145275$6549_Y + attribute \src "libresoc.v:145276.18-145276.98" + wire $gt$libresoc.v:145276$6550_Y + attribute \src "libresoc.v:145277.18-145277.98" + wire $gt$libresoc.v:145277$6551_Y + attribute \src "libresoc.v:145278.18-145278.98" + wire $gt$libresoc.v:145278$6552_Y + attribute \src "libresoc.v:145279.17-145279.96" + wire $gt$libresoc.v:145279$6553_Y + attribute \src "libresoc.v:145280.18-145280.98" + wire $gt$libresoc.v:145280$6554_Y + attribute \src "libresoc.v:145281.18-145281.98" + wire $gt$libresoc.v:145281$6555_Y + attribute \src "libresoc.v:145282.18-145282.98" + wire $gt$libresoc.v:145282$6556_Y + attribute \src "libresoc.v:145283.18-145283.98" + wire $gt$libresoc.v:145283$6557_Y + attribute \src "libresoc.v:145284.18-145284.98" + wire $gt$libresoc.v:145284$6558_Y + attribute \src "libresoc.v:145285.18-145285.98" + wire $gt$libresoc.v:145285$6559_Y + attribute \src "libresoc.v:145286.18-145286.98" + wire $gt$libresoc.v:145286$6560_Y + attribute \src "libresoc.v:145287.18-145287.98" + wire $gt$libresoc.v:145287$6561_Y + attribute \src "libresoc.v:145288.18-145288.98" + wire $gt$libresoc.v:145288$6562_Y + attribute \src "libresoc.v:145289.18-145289.98" + wire $gt$libresoc.v:145289$6563_Y + attribute \src "libresoc.v:145290.17-145290.96" + wire $gt$libresoc.v:145290$6564_Y + attribute \src "libresoc.v:145291.18-145291.98" + wire $gt$libresoc.v:145291$6565_Y + attribute \src "libresoc.v:145292.18-145292.98" + wire $gt$libresoc.v:145292$6566_Y + attribute \src "libresoc.v:145293.18-145293.98" + wire $gt$libresoc.v:145293$6567_Y + attribute \src "libresoc.v:145294.18-145294.98" + wire $gt$libresoc.v:145294$6568_Y + attribute \src "libresoc.v:145295.18-145295.98" + wire $gt$libresoc.v:145295$6569_Y + attribute \src "libresoc.v:145296.18-145296.98" + wire $gt$libresoc.v:145296$6570_Y + attribute \src "libresoc.v:145297.18-145297.98" + wire $gt$libresoc.v:145297$6571_Y + attribute \src "libresoc.v:145298.18-145298.98" + wire $gt$libresoc.v:145298$6572_Y + attribute \src "libresoc.v:145299.18-145299.98" + wire $gt$libresoc.v:145299$6573_Y + attribute \src "libresoc.v:145300.18-145300.98" + wire $gt$libresoc.v:145300$6574_Y + attribute \src "libresoc.v:145301.17-145301.96" + wire $gt$libresoc.v:145301$6575_Y + attribute \src "libresoc.v:145302.18-145302.98" + wire $gt$libresoc.v:145302$6576_Y + attribute \src "libresoc.v:145303.18-145303.98" + wire $gt$libresoc.v:145303$6577_Y + attribute \src "libresoc.v:145304.18-145304.98" + wire $gt$libresoc.v:145304$6578_Y + attribute \src "libresoc.v:145305.18-145305.98" + wire $gt$libresoc.v:145305$6579_Y + attribute \src "libresoc.v:145306.18-145306.98" + wire $gt$libresoc.v:145306$6580_Y + attribute \src "libresoc.v:145307.18-145307.98" + wire $gt$libresoc.v:145307$6581_Y + attribute \src "libresoc.v:145308.18-145308.98" + wire $gt$libresoc.v:145308$6582_Y + attribute \src "libresoc.v:145309.18-145309.98" + wire $gt$libresoc.v:145309$6583_Y + attribute \src "libresoc.v:145310.18-145310.98" + wire $gt$libresoc.v:145310$6584_Y + attribute \src "libresoc.v:145311.18-145311.98" + wire $gt$libresoc.v:145311$6585_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$101 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$103 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$105 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$107 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$109 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$111 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$113 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$115 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$117 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$119 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$121 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$123 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$125 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$127 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$17 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$21 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$25 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$29 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$33 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$35 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$37 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$39 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$41 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$43 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$45 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$47 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$49 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$51 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$53 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$55 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$57 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$59 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$61 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$63 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$65 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$67 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$69 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$71 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$73 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$75 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$77 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$79 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$81 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$83 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$85 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$87 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$89 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$91 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$93 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$95 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$97 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$99 + attribute \src "libresoc.v:145114.7-145114.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:20" + wire width 64 output 1 \mask + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:19" + wire width 7 input 2 \shift + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:145248$6522 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 3'100 + connect \Y $gt$libresoc.v:145248$6522_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:145249$6523 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'110001 + connect \Y $gt$libresoc.v:145249$6523_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:145250$6524 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'110010 + connect \Y $gt$libresoc.v:145250$6524_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:145251$6525 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'110011 + connect \Y $gt$libresoc.v:145251$6525_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:145252$6526 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'110100 + connect \Y $gt$libresoc.v:145252$6526_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:145253$6527 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'110101 + connect \Y $gt$libresoc.v:145253$6527_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:145254$6528 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'110110 + connect \Y $gt$libresoc.v:145254$6528_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:145255$6529 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'110111 + connect \Y $gt$libresoc.v:145255$6529_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:145256$6530 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'111000 + connect \Y $gt$libresoc.v:145256$6530_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:145257$6531 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'111001 + connect \Y $gt$libresoc.v:145257$6531_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:145258$6532 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'111010 + connect \Y $gt$libresoc.v:145258$6532_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:145259$6533 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 3'101 + connect \Y $gt$libresoc.v:145259$6533_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:145260$6534 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'111011 + connect \Y $gt$libresoc.v:145260$6534_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:145261$6535 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'111100 + connect \Y $gt$libresoc.v:145261$6535_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:145262$6536 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'111101 + connect \Y $gt$libresoc.v:145262$6536_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:145263$6537 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'111110 + connect \Y $gt$libresoc.v:145263$6537_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:145264$6538 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'111111 + connect \Y $gt$libresoc.v:145264$6538_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:145265$6539 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 3'110 + connect \Y $gt$libresoc.v:145265$6539_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:145266$6540 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 3'111 + connect \Y $gt$libresoc.v:145266$6540_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:145267$6541 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 4'1000 + connect \Y $gt$libresoc.v:145267$6541_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:145268$6542 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 1'0 + connect \Y $gt$libresoc.v:145268$6542_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:145269$6543 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 4'1001 + connect \Y $gt$libresoc.v:145269$6543_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:145270$6544 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 4'1010 + connect \Y $gt$libresoc.v:145270$6544_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:145271$6545 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 4'1011 + connect \Y $gt$libresoc.v:145271$6545_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:145272$6546 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 4'1100 + connect \Y $gt$libresoc.v:145272$6546_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:145273$6547 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 4'1101 + connect \Y $gt$libresoc.v:145273$6547_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:145274$6548 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 4'1110 + connect \Y $gt$libresoc.v:145274$6548_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:145275$6549 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 4'1111 + connect \Y $gt$libresoc.v:145275$6549_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:145276$6550 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'10000 + connect \Y $gt$libresoc.v:145276$6550_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:145277$6551 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'10001 + connect \Y $gt$libresoc.v:145277$6551_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:145278$6552 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'10010 + connect \Y $gt$libresoc.v:145278$6552_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:145279$6553 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 1'1 + connect \Y $gt$libresoc.v:145279$6553_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:145280$6554 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'10011 + connect \Y $gt$libresoc.v:145280$6554_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:145281$6555 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'10100 + connect \Y $gt$libresoc.v:145281$6555_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:145282$6556 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'10101 + connect \Y $gt$libresoc.v:145282$6556_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:145283$6557 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'10110 + connect \Y $gt$libresoc.v:145283$6557_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:145284$6558 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'10111 + connect \Y $gt$libresoc.v:145284$6558_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:145285$6559 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'11000 + connect \Y $gt$libresoc.v:145285$6559_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:145286$6560 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'11001 + connect \Y $gt$libresoc.v:145286$6560_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:145287$6561 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'11010 + connect \Y $gt$libresoc.v:145287$6561_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:145288$6562 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'11011 + connect \Y $gt$libresoc.v:145288$6562_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:145289$6563 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'11100 + connect \Y $gt$libresoc.v:145289$6563_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:145290$6564 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 2'10 + connect \Y $gt$libresoc.v:145290$6564_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:145291$6565 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'11101 + connect \Y $gt$libresoc.v:145291$6565_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:145292$6566 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'11110 + connect \Y $gt$libresoc.v:145292$6566_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:145293$6567 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'11111 + connect \Y $gt$libresoc.v:145293$6567_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:145294$6568 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'100000 + connect \Y $gt$libresoc.v:145294$6568_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:145295$6569 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'100001 + connect \Y $gt$libresoc.v:145295$6569_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:145296$6570 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'100010 + connect \Y $gt$libresoc.v:145296$6570_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:145297$6571 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'100011 + connect \Y $gt$libresoc.v:145297$6571_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:145298$6572 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'100100 + connect \Y $gt$libresoc.v:145298$6572_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:145299$6573 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'100101 + connect \Y $gt$libresoc.v:145299$6573_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:145300$6574 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'100110 + connect \Y $gt$libresoc.v:145300$6574_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:145301$6575 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 2'11 + connect \Y $gt$libresoc.v:145301$6575_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:145302$6576 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'100111 + connect \Y $gt$libresoc.v:145302$6576_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:145303$6577 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'101000 + connect \Y $gt$libresoc.v:145303$6577_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:145304$6578 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'101001 + connect \Y $gt$libresoc.v:145304$6578_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:145305$6579 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'101010 + connect \Y $gt$libresoc.v:145305$6579_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:145306$6580 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'101011 + connect \Y $gt$libresoc.v:145306$6580_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:145307$6581 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'101100 + connect \Y $gt$libresoc.v:145307$6581_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:145308$6582 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'101101 + connect \Y $gt$libresoc.v:145308$6582_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:145309$6583 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'101110 + connect \Y $gt$libresoc.v:145309$6583_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:145310$6584 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'101111 + connect \Y $gt$libresoc.v:145310$6584_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:145311$6585 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'110000 + connect \Y $gt$libresoc.v:145311$6585_Y + end + attribute \src "libresoc.v:145114.7-145114.20" + process $proc$libresoc.v:145114$6587 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:145312.3-145699.6" + process $proc$libresoc.v:145312$6586 + assign { } { } + assign { } { } + assign $0\mask[63:0] [0] $1\mask[0:0] + assign $0\mask[63:0] [1] $2\mask[1:1] + assign $0\mask[63:0] [2] $3\mask[2:2] + assign $0\mask[63:0] [3] $4\mask[3:3] + assign $0\mask[63:0] [4] $5\mask[4:4] + assign $0\mask[63:0] [5] $6\mask[5:5] + assign $0\mask[63:0] [6] $7\mask[6:6] + assign $0\mask[63:0] [7] $8\mask[7:7] + assign $0\mask[63:0] [8] $9\mask[8:8] + assign $0\mask[63:0] [9] $10\mask[9:9] + assign $0\mask[63:0] [10] $11\mask[10:10] + assign $0\mask[63:0] [11] $12\mask[11:11] + assign $0\mask[63:0] [12] $13\mask[12:12] + assign $0\mask[63:0] [13] $14\mask[13:13] + assign $0\mask[63:0] [14] $15\mask[14:14] + assign $0\mask[63:0] [15] $16\mask[15:15] + assign $0\mask[63:0] [16] $17\mask[16:16] + assign $0\mask[63:0] [17] $18\mask[17:17] + assign $0\mask[63:0] [18] $19\mask[18:18] + assign $0\mask[63:0] [19] $20\mask[19:19] + assign $0\mask[63:0] [20] $21\mask[20:20] + assign $0\mask[63:0] [21] $22\mask[21:21] + assign $0\mask[63:0] [22] $23\mask[22:22] + assign $0\mask[63:0] [23] $24\mask[23:23] + assign $0\mask[63:0] [24] $25\mask[24:24] + assign $0\mask[63:0] [25] $26\mask[25:25] + assign $0\mask[63:0] [26] $27\mask[26:26] + assign $0\mask[63:0] [27] $28\mask[27:27] + assign $0\mask[63:0] [28] $29\mask[28:28] + assign $0\mask[63:0] [29] $30\mask[29:29] + assign $0\mask[63:0] [30] $31\mask[30:30] + assign $0\mask[63:0] [31] $32\mask[31:31] + assign $0\mask[63:0] [32] $33\mask[32:32] + assign $0\mask[63:0] [33] $34\mask[33:33] + assign $0\mask[63:0] [34] $35\mask[34:34] + assign $0\mask[63:0] [35] $36\mask[35:35] + assign $0\mask[63:0] [36] $37\mask[36:36] + assign $0\mask[63:0] [37] $38\mask[37:37] + assign $0\mask[63:0] [38] $39\mask[38:38] + assign $0\mask[63:0] [39] $40\mask[39:39] + assign $0\mask[63:0] [40] $41\mask[40:40] + assign $0\mask[63:0] [41] $42\mask[41:41] + assign $0\mask[63:0] [42] $43\mask[42:42] + assign $0\mask[63:0] [43] $44\mask[43:43] + assign $0\mask[63:0] [44] $45\mask[44:44] + assign $0\mask[63:0] [45] $46\mask[45:45] + assign $0\mask[63:0] [46] $47\mask[46:46] + assign $0\mask[63:0] [47] $48\mask[47:47] + assign $0\mask[63:0] [48] $49\mask[48:48] + assign $0\mask[63:0] [49] $50\mask[49:49] + assign $0\mask[63:0] [50] $51\mask[50:50] + assign $0\mask[63:0] [51] $52\mask[51:51] + assign $0\mask[63:0] [52] $53\mask[52:52] + assign $0\mask[63:0] [53] $54\mask[53:53] + assign $0\mask[63:0] [54] $55\mask[54:54] + assign $0\mask[63:0] [55] $56\mask[55:55] + assign $0\mask[63:0] [56] $57\mask[56:56] + assign $0\mask[63:0] [57] $58\mask[57:57] + assign $0\mask[63:0] [58] $59\mask[58:58] + assign $0\mask[63:0] [59] $60\mask[59:59] + assign $0\mask[63:0] [60] $61\mask[60:60] + assign $0\mask[63:0] [61] $62\mask[61:61] + assign $0\mask[63:0] [62] $63\mask[62:62] + assign $0\mask[63:0] [63] $64\mask[63:63] + attribute \src "libresoc.v:145313.5-145313.29" + switch \initial + attribute \src "libresoc.v:145313.9-145313.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\mask[0:0] 1'1 + case + assign $1\mask[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\mask[1:1] 1'1 + case + assign $2\mask[1:1] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$5 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\mask[2:2] 1'1 + case + assign $3\mask[2:2] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$7 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\mask[3:3] 1'1 + case + assign $4\mask[3:3] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$9 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\mask[4:4] 1'1 + case + assign $5\mask[4:4] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$11 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\mask[5:5] 1'1 + case + assign $6\mask[5:5] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$13 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\mask[6:6] 1'1 + case + assign $7\mask[6:6] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$15 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $8\mask[7:7] 1'1 + case + assign $8\mask[7:7] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$17 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $9\mask[8:8] 1'1 + case + assign $9\mask[8:8] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$19 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $10\mask[9:9] 1'1 + case + assign $10\mask[9:9] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$21 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $11\mask[10:10] 1'1 + case + assign $11\mask[10:10] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$23 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $12\mask[11:11] 1'1 + case + assign $12\mask[11:11] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$25 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $13\mask[12:12] 1'1 + case + assign $13\mask[12:12] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$27 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $14\mask[13:13] 1'1 + case + assign $14\mask[13:13] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$29 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $15\mask[14:14] 1'1 + case + assign $15\mask[14:14] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$31 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $16\mask[15:15] 1'1 + case + assign $16\mask[15:15] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$33 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $17\mask[16:16] 1'1 + case + assign $17\mask[16:16] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$35 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $18\mask[17:17] 1'1 + case + assign $18\mask[17:17] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$37 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $19\mask[18:18] 1'1 + case + assign $19\mask[18:18] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$39 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $20\mask[19:19] 1'1 + case + assign $20\mask[19:19] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$41 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $21\mask[20:20] 1'1 + case + assign $21\mask[20:20] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$43 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $22\mask[21:21] 1'1 + case + assign $22\mask[21:21] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$45 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $23\mask[22:22] 1'1 + case + assign $23\mask[22:22] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$47 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $24\mask[23:23] 1'1 + case + assign $24\mask[23:23] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$49 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $25\mask[24:24] 1'1 + case + assign $25\mask[24:24] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$51 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $26\mask[25:25] 1'1 + case + assign $26\mask[25:25] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$53 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $27\mask[26:26] 1'1 + case + assign $27\mask[26:26] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$55 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $28\mask[27:27] 1'1 + case + assign $28\mask[27:27] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$57 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $29\mask[28:28] 1'1 + case + assign $29\mask[28:28] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$59 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $30\mask[29:29] 1'1 + case + assign $30\mask[29:29] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$61 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $31\mask[30:30] 1'1 + case + assign $31\mask[30:30] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$63 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $32\mask[31:31] 1'1 + case + assign $32\mask[31:31] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$65 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $33\mask[32:32] 1'1 + case + assign $33\mask[32:32] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$67 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $34\mask[33:33] 1'1 + case + assign $34\mask[33:33] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$69 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $35\mask[34:34] 1'1 + case + assign $35\mask[34:34] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$71 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $36\mask[35:35] 1'1 + case + assign $36\mask[35:35] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$73 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $37\mask[36:36] 1'1 + case + assign $37\mask[36:36] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$75 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $38\mask[37:37] 1'1 + case + assign $38\mask[37:37] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$77 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $39\mask[38:38] 1'1 + case + assign $39\mask[38:38] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$79 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $40\mask[39:39] 1'1 + case + assign $40\mask[39:39] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$81 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $41\mask[40:40] 1'1 + case + assign $41\mask[40:40] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$83 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $42\mask[41:41] 1'1 + case + assign $42\mask[41:41] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$85 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $43\mask[42:42] 1'1 + case + assign $43\mask[42:42] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$87 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $44\mask[43:43] 1'1 + case + assign $44\mask[43:43] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$89 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $45\mask[44:44] 1'1 + case + assign $45\mask[44:44] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$91 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $46\mask[45:45] 1'1 + case + assign $46\mask[45:45] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$93 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $47\mask[46:46] 1'1 + case + assign $47\mask[46:46] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$95 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $48\mask[47:47] 1'1 + case + assign $48\mask[47:47] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$97 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $49\mask[48:48] 1'1 + case + assign $49\mask[48:48] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$99 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $50\mask[49:49] 1'1 + case + assign $50\mask[49:49] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$101 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $51\mask[50:50] 1'1 + case + assign $51\mask[50:50] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$103 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $52\mask[51:51] 1'1 + case + assign $52\mask[51:51] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$105 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $53\mask[52:52] 1'1 + case + assign $53\mask[52:52] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$107 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $54\mask[53:53] 1'1 + case + assign $54\mask[53:53] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$109 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $55\mask[54:54] 1'1 + case + assign $55\mask[54:54] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$111 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $56\mask[55:55] 1'1 + case + assign $56\mask[55:55] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$113 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $57\mask[56:56] 1'1 + case + assign $57\mask[56:56] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$115 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $58\mask[57:57] 1'1 + case + assign $58\mask[57:57] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$117 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $59\mask[58:58] 1'1 + case + assign $59\mask[58:58] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$119 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $60\mask[59:59] 1'1 + case + assign $60\mask[59:59] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$121 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $61\mask[60:60] 1'1 + case + assign $61\mask[60:60] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$123 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $62\mask[61:61] 1'1 + case + assign $62\mask[61:61] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$125 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $63\mask[62:62] 1'1 + case + assign $63\mask[62:62] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$127 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $64\mask[63:63] 1'1 + case + assign $64\mask[63:63] 1'0 + end + sync always + update \mask $0\mask[63:0] + end + connect \$9 $gt$libresoc.v:145248$6522_Y + connect \$99 $gt$libresoc.v:145249$6523_Y + connect \$101 $gt$libresoc.v:145250$6524_Y + connect \$103 $gt$libresoc.v:145251$6525_Y + connect \$105 $gt$libresoc.v:145252$6526_Y + connect \$107 $gt$libresoc.v:145253$6527_Y + connect \$109 $gt$libresoc.v:145254$6528_Y + connect \$111 $gt$libresoc.v:145255$6529_Y + connect \$113 $gt$libresoc.v:145256$6530_Y + connect \$115 $gt$libresoc.v:145257$6531_Y + connect \$117 $gt$libresoc.v:145258$6532_Y + connect \$11 $gt$libresoc.v:145259$6533_Y + connect \$119 $gt$libresoc.v:145260$6534_Y + connect \$121 $gt$libresoc.v:145261$6535_Y + connect \$123 $gt$libresoc.v:145262$6536_Y + connect \$125 $gt$libresoc.v:145263$6537_Y + connect \$127 $gt$libresoc.v:145264$6538_Y + connect \$13 $gt$libresoc.v:145265$6539_Y + connect \$15 $gt$libresoc.v:145266$6540_Y + connect \$17 $gt$libresoc.v:145267$6541_Y + connect \$1 $gt$libresoc.v:145268$6542_Y + connect \$19 $gt$libresoc.v:145269$6543_Y + connect \$21 $gt$libresoc.v:145270$6544_Y + connect \$23 $gt$libresoc.v:145271$6545_Y + connect \$25 $gt$libresoc.v:145272$6546_Y + connect \$27 $gt$libresoc.v:145273$6547_Y + connect \$29 $gt$libresoc.v:145274$6548_Y + connect \$31 $gt$libresoc.v:145275$6549_Y + connect \$33 $gt$libresoc.v:145276$6550_Y + connect \$35 $gt$libresoc.v:145277$6551_Y + connect \$37 $gt$libresoc.v:145278$6552_Y + connect \$3 $gt$libresoc.v:145279$6553_Y + connect \$39 $gt$libresoc.v:145280$6554_Y + connect \$41 $gt$libresoc.v:145281$6555_Y + connect \$43 $gt$libresoc.v:145282$6556_Y + connect \$45 $gt$libresoc.v:145283$6557_Y + connect \$47 $gt$libresoc.v:145284$6558_Y + connect \$49 $gt$libresoc.v:145285$6559_Y + connect \$51 $gt$libresoc.v:145286$6560_Y + connect \$53 $gt$libresoc.v:145287$6561_Y + connect \$55 $gt$libresoc.v:145288$6562_Y + connect \$57 $gt$libresoc.v:145289$6563_Y + connect \$5 $gt$libresoc.v:145290$6564_Y + connect \$59 $gt$libresoc.v:145291$6565_Y + connect \$61 $gt$libresoc.v:145292$6566_Y + connect \$63 $gt$libresoc.v:145293$6567_Y + connect \$65 $gt$libresoc.v:145294$6568_Y + connect \$67 $gt$libresoc.v:145295$6569_Y + connect \$69 $gt$libresoc.v:145296$6570_Y + connect \$71 $gt$libresoc.v:145297$6571_Y + connect \$73 $gt$libresoc.v:145298$6572_Y + connect \$75 $gt$libresoc.v:145299$6573_Y + connect \$77 $gt$libresoc.v:145300$6574_Y + connect \$7 $gt$libresoc.v:145301$6575_Y + connect \$79 $gt$libresoc.v:145302$6576_Y + connect \$81 $gt$libresoc.v:145303$6577_Y + connect \$83 $gt$libresoc.v:145304$6578_Y + connect \$85 $gt$libresoc.v:145305$6579_Y + connect \$87 $gt$libresoc.v:145306$6580_Y + connect \$89 $gt$libresoc.v:145307$6581_Y + connect \$91 $gt$libresoc.v:145308$6582_Y + connect \$93 $gt$libresoc.v:145309$6583_Y + connect \$95 $gt$libresoc.v:145310$6584_Y + connect \$97 $gt$libresoc.v:145311$6585_Y +end +attribute \src "libresoc.v:145704.1-145733.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem.lenexp" +attribute \generator "nMigen" +module \lenexp + attribute \src "libresoc.v:145728.17-145728.101" + wire width 64 $extend$libresoc.v:145728$6591_Y + attribute \src "libresoc.v:145728.17-145728.101" + wire width 64 $pos$libresoc.v:145728$6592_Y + attribute \src "libresoc.v:145725.17-145725.111" + wire width 20 $sshl$libresoc.v:145725$6588_Y + attribute \src "libresoc.v:145727.17-145727.113" + wire width 32 $sshl$libresoc.v:145727$6590_Y + attribute \src "libresoc.v:145726.17-145726.107" + wire width 21 $sub$libresoc.v:145726$6589_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:150" + wire width 21 \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:150" + wire width 20 \$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:150" + wire width 21 \$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:151" + wire width 64 \$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:151" + wire width 32 \$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:131" + wire width 4 input 1 \addr_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:148" + wire width 17 \binlen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:130" + wire width 4 input 4 \len_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:132" + wire width 64 output 2 \lexp_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:134" + wire width 176 output 3 \rexp_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:151" + cell $pos $extend$libresoc.v:145728$6591 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \Y_WIDTH 64 + connect \A \$7 + connect \Y $extend$libresoc.v:145728$6591_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:151" + cell $pos $pos$libresoc.v:145728$6592 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:145728$6591_Y + connect \Y $pos$libresoc.v:145728$6592_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:150" + cell $sshl $sshl$libresoc.v:145725$6588 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 20 + connect \A 5'00001 + connect \B \len_i + connect \Y $sshl$libresoc.v:145725$6588_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:151" + cell $sshl $sshl$libresoc.v:145727$6590 + parameter \A_SIGNED 0 + parameter \A_WIDTH 17 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 32 + connect \A \binlen + connect \B \addr_i + connect \Y $sshl$libresoc.v:145727$6590_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:150" + cell $sub $sub$libresoc.v:145726$6589 + parameter \A_SIGNED 0 + parameter \A_WIDTH 20 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 21 + connect \A \$2 + connect \B 1'1 + connect \Y $sub$libresoc.v:145726$6589_Y + end + connect \$2 $sshl$libresoc.v:145725$6588_Y + connect \$4 $sub$libresoc.v:145726$6589_Y + connect \$7 $sshl$libresoc.v:145727$6590_Y + connect \$6 $pos$libresoc.v:145728$6592_Y + connect \$1 \$4 + connect \rexp_o { \lexp_o [21] \lexp_o [21] \lexp_o [21] \lexp_o [21] \lexp_o [21] \lexp_o [21] \lexp_o [21] \lexp_o [21:20] \lexp_o [20] \lexp_o [20] \lexp_o [20] \lexp_o [20] \lexp_o [20] \lexp_o [20] \lexp_o [20:19] \lexp_o [19] \lexp_o [19] \lexp_o [19] \lexp_o [19] \lexp_o [19] \lexp_o [19] \lexp_o [19:18] \lexp_o [18] \lexp_o [18] \lexp_o [18] \lexp_o [18] \lexp_o [18] \lexp_o [18] \lexp_o [18:17] \lexp_o [17] \lexp_o [17] \lexp_o [17] \lexp_o [17] \lexp_o [17] \lexp_o [17] \lexp_o [17:16] \lexp_o [16] \lexp_o [16] \lexp_o [16] \lexp_o [16] \lexp_o [16] \lexp_o [16] \lexp_o [16:15] \lexp_o [15] \lexp_o [15] \lexp_o [15] \lexp_o [15] \lexp_o [15] \lexp_o [15] \lexp_o [15:14] \lexp_o [14] \lexp_o [14] \lexp_o [14] \lexp_o [14] \lexp_o [14] \lexp_o [14] \lexp_o [14:13] \lexp_o [13] \lexp_o [13] \lexp_o [13] \lexp_o [13] \lexp_o [13] \lexp_o [13] \lexp_o [13:12] \lexp_o [12] \lexp_o [12] \lexp_o [12] \lexp_o [12] \lexp_o [12] \lexp_o [12] \lexp_o [12:11] \lexp_o [11] \lexp_o [11] \lexp_o [11] \lexp_o [11] \lexp_o [11] \lexp_o [11] \lexp_o [11:10] \lexp_o [10] \lexp_o [10] \lexp_o [10] \lexp_o [10] \lexp_o [10] \lexp_o [10] \lexp_o [10:9] \lexp_o [9] \lexp_o [9] \lexp_o [9] \lexp_o [9] \lexp_o [9] \lexp_o [9] \lexp_o [9:8] \lexp_o [8] \lexp_o [8] \lexp_o [8] \lexp_o [8] \lexp_o [8] \lexp_o [8] \lexp_o [8:7] \lexp_o [7] \lexp_o [7] \lexp_o [7] \lexp_o [7] \lexp_o [7] \lexp_o [7] \lexp_o [7:6] \lexp_o [6] \lexp_o [6] \lexp_o [6] \lexp_o [6] \lexp_o [6] \lexp_o [6] \lexp_o [6:5] \lexp_o [5] \lexp_o [5] \lexp_o [5] \lexp_o [5] \lexp_o [5] \lexp_o [5] \lexp_o [5:4] \lexp_o [4] \lexp_o [4] \lexp_o [4] \lexp_o [4] \lexp_o [4] \lexp_o [4] \lexp_o [4:3] \lexp_o [3] \lexp_o [3] \lexp_o [3] \lexp_o [3] \lexp_o [3] \lexp_o [3] \lexp_o [3:2] \lexp_o [2] \lexp_o [2] \lexp_o [2] \lexp_o [2] \lexp_o [2] \lexp_o [2] \lexp_o [2:1] \lexp_o [1] \lexp_o [1] \lexp_o [1] \lexp_o [1] \lexp_o [1] \lexp_o [1] \lexp_o [1:0] \lexp_o [0] \lexp_o [0] \lexp_o [0] \lexp_o [0] \lexp_o [0] \lexp_o [0] \lexp_o [0] } + connect \lexp_o \$6 + connect \binlen \$4 [16:0] +end +attribute \src "libresoc.v:145737.1-145795.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.lod_l" +attribute \generator "nMigen" +module \lod_l + attribute \src "libresoc.v:145738.7-145738.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:145783.3-145791.6" + wire $0\q_int$next[0:0]$6603 + attribute \src "libresoc.v:145781.3-145782.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:145783.3-145791.6" + wire $1\q_int$next[0:0]$6604 + attribute \src "libresoc.v:145760.7-145760.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:145773.17-145773.96" + wire $and$libresoc.v:145773$6593_Y + attribute \src "libresoc.v:145778.17-145778.96" + wire $and$libresoc.v:145778$6598_Y + attribute \src "libresoc.v:145775.18-145775.93" + wire $not$libresoc.v:145775$6595_Y + attribute \src "libresoc.v:145777.17-145777.92" + wire $not$libresoc.v:145777$6597_Y + attribute \src "libresoc.v:145780.17-145780.92" + wire $not$libresoc.v:145780$6600_Y + attribute \src "libresoc.v:145774.18-145774.98" + wire $or$libresoc.v:145774$6594_Y + attribute \src "libresoc.v:145776.18-145776.99" + wire $or$libresoc.v:145776$6596_Y + attribute \src "libresoc.v:145779.17-145779.97" + wire $or$libresoc.v:145779$6599_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 1 \coresync_rst + attribute \src "libresoc.v:145738.7-145738.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire \q_lod + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" + wire \qlq_lod + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire output 4 \qn_lod + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire input 3 \r_lod + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire input 2 \s_lod + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:145773$6593 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:145773$6593_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:145778$6598 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:145778$6598_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:145775$6595 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_lod + connect \Y $not$libresoc.v:145775$6595_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:145777$6597 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_lod + connect \Y $not$libresoc.v:145777$6597_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:145780$6600 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_lod + connect \Y $not$libresoc.v:145780$6600_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:145774$6594 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_lod + connect \Y $or$libresoc.v:145774$6594_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:145776$6596 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_lod + connect \B \q_int + connect \Y $or$libresoc.v:145776$6596_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:145779$6599 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_lod + connect \Y $or$libresoc.v:145779$6599_Y + end + attribute \src "libresoc.v:145738.7-145738.20" + process $proc$libresoc.v:145738$6605 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:145760.7-145760.19" + process $proc$libresoc.v:145760$6606 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:145781.3-145782.27" + process $proc$libresoc.v:145781$6601 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:145783.3-145791.6" + process $proc$libresoc.v:145783$6602 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$6603 $1\q_int$next[0:0]$6604 + attribute \src "libresoc.v:145784.5-145784.29" + switch \initial + attribute \src "libresoc.v:145784.9-145784.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$6604 1'0 + case + assign $1\q_int$next[0:0]$6604 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$6603 + end + connect \$9 $and$libresoc.v:145773$6593_Y + connect \$11 $or$libresoc.v:145774$6594_Y + connect \$13 $not$libresoc.v:145775$6595_Y + connect \$15 $or$libresoc.v:145776$6596_Y + connect \$1 $not$libresoc.v:145777$6597_Y + connect \$3 $and$libresoc.v:145778$6598_Y + connect \$5 $or$libresoc.v:145779$6599_Y + connect \$7 $not$libresoc.v:145780$6600_Y + connect \qlq_lod \$15 + connect \qn_lod \$13 + connect \q_lod \$11 +end +attribute \src "libresoc.v:145799.1-146915.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0" +attribute \generator "nMigen" +module \logical0 + attribute \src "libresoc.v:146540.3-146541.24" + wire $0\all_rd_dly[0:0] + attribute \src "libresoc.v:146538.3-146539.44" + wire $0\alu_done_dly[0:0] + attribute \src "libresoc.v:146845.3-146853.6" + wire $0\alu_l_r_alu$next[0:0]$6807 + attribute \src "libresoc.v:146462.3-146463.39" + wire $0\alu_l_r_alu[0:0] + attribute \src "libresoc.v:146723.3-146761.6" + wire width 4 $0\alu_logical0_logical_op__data_len$next[3:0]$6736 + attribute \src "libresoc.v:146512.3-146513.83" + wire width 4 $0\alu_logical0_logical_op__data_len[3:0] + attribute \src "libresoc.v:146723.3-146761.6" + wire width 13 $0\alu_logical0_logical_op__fn_unit$next[12:0]$6737 + attribute \src "libresoc.v:146482.3-146483.81" + wire width 13 $0\alu_logical0_logical_op__fn_unit[12:0] + attribute \src "libresoc.v:146723.3-146761.6" + wire width 64 $0\alu_logical0_logical_op__imm_data__data$next[63:0]$6738 + attribute \src "libresoc.v:146484.3-146485.95" + wire width 64 $0\alu_logical0_logical_op__imm_data__data[63:0] + attribute \src "libresoc.v:146723.3-146761.6" + wire $0\alu_logical0_logical_op__imm_data__ok$next[0:0]$6739 + attribute \src "libresoc.v:146486.3-146487.91" + wire $0\alu_logical0_logical_op__imm_data__ok[0:0] + attribute \src "libresoc.v:146723.3-146761.6" + wire width 2 $0\alu_logical0_logical_op__input_carry$next[1:0]$6740 + attribute \src "libresoc.v:146500.3-146501.89" + wire width 2 $0\alu_logical0_logical_op__input_carry[1:0] + attribute \src "libresoc.v:146723.3-146761.6" + wire width 32 $0\alu_logical0_logical_op__insn$next[31:0]$6741 + attribute \src "libresoc.v:146514.3-146515.75" + wire width 32 $0\alu_logical0_logical_op__insn[31:0] + attribute \src "libresoc.v:146723.3-146761.6" + wire width 7 $0\alu_logical0_logical_op__insn_type$next[6:0]$6742 + attribute \src "libresoc.v:146480.3-146481.85" + wire width 7 $0\alu_logical0_logical_op__insn_type[6:0] + attribute \src "libresoc.v:146723.3-146761.6" + wire $0\alu_logical0_logical_op__invert_in$next[0:0]$6743 + attribute \src "libresoc.v:146496.3-146497.85" + wire $0\alu_logical0_logical_op__invert_in[0:0] + attribute \src "libresoc.v:146723.3-146761.6" + wire $0\alu_logical0_logical_op__invert_out$next[0:0]$6744 + attribute \src "libresoc.v:146502.3-146503.87" + wire $0\alu_logical0_logical_op__invert_out[0:0] + attribute \src "libresoc.v:146723.3-146761.6" + wire $0\alu_logical0_logical_op__is_32bit$next[0:0]$6745 + attribute \src "libresoc.v:146508.3-146509.83" + wire $0\alu_logical0_logical_op__is_32bit[0:0] + attribute \src "libresoc.v:146723.3-146761.6" + wire $0\alu_logical0_logical_op__is_signed$next[0:0]$6746 + attribute \src "libresoc.v:146510.3-146511.85" + wire $0\alu_logical0_logical_op__is_signed[0:0] + attribute \src "libresoc.v:146723.3-146761.6" + wire $0\alu_logical0_logical_op__oe__oe$next[0:0]$6747 + attribute \src "libresoc.v:146492.3-146493.79" + wire $0\alu_logical0_logical_op__oe__oe[0:0] + attribute \src "libresoc.v:146723.3-146761.6" + wire $0\alu_logical0_logical_op__oe__ok$next[0:0]$6748 + attribute \src "libresoc.v:146494.3-146495.79" + wire $0\alu_logical0_logical_op__oe__ok[0:0] + attribute \src "libresoc.v:146723.3-146761.6" + wire $0\alu_logical0_logical_op__output_carry$next[0:0]$6749 + attribute \src "libresoc.v:146506.3-146507.91" + wire $0\alu_logical0_logical_op__output_carry[0:0] + attribute \src "libresoc.v:146723.3-146761.6" + wire $0\alu_logical0_logical_op__rc__ok$next[0:0]$6750 + attribute \src "libresoc.v:146490.3-146491.79" + wire $0\alu_logical0_logical_op__rc__ok[0:0] + attribute \src "libresoc.v:146723.3-146761.6" + wire $0\alu_logical0_logical_op__rc__rc$next[0:0]$6751 + attribute \src "libresoc.v:146488.3-146489.79" + wire $0\alu_logical0_logical_op__rc__rc[0:0] + attribute \src "libresoc.v:146723.3-146761.6" + wire $0\alu_logical0_logical_op__write_cr0$next[0:0]$6752 + attribute \src "libresoc.v:146504.3-146505.85" + wire $0\alu_logical0_logical_op__write_cr0[0:0] + attribute \src "libresoc.v:146723.3-146761.6" + wire $0\alu_logical0_logical_op__zero_a$next[0:0]$6753 + attribute \src "libresoc.v:146498.3-146499.79" + wire $0\alu_logical0_logical_op__zero_a[0:0] + attribute \src "libresoc.v:146836.3-146844.6" + wire $0\alui_l_r_alui$next[0:0]$6804 + attribute \src "libresoc.v:146464.3-146465.43" + wire $0\alui_l_r_alui[0:0] + attribute \src "libresoc.v:146762.3-146783.6" + wire width 64 $0\data_r0__o$next[63:0]$6779 + attribute \src "libresoc.v:146476.3-146477.37" + wire width 64 $0\data_r0__o[63:0] + attribute \src "libresoc.v:146762.3-146783.6" + wire $0\data_r0__o_ok$next[0:0]$6780 + attribute \src "libresoc.v:146478.3-146479.43" + wire $0\data_r0__o_ok[0:0] + attribute \src "libresoc.v:146784.3-146805.6" + wire width 4 $0\data_r1__cr_a$next[3:0]$6787 + attribute \src "libresoc.v:146472.3-146473.43" + wire width 4 $0\data_r1__cr_a[3:0] + attribute \src "libresoc.v:146784.3-146805.6" + wire $0\data_r1__cr_a_ok$next[0:0]$6788 + attribute \src "libresoc.v:146474.3-146475.49" + wire $0\data_r1__cr_a_ok[0:0] + attribute \src "libresoc.v:146854.3-146863.6" + wire width 64 $0\dest1_o[63:0] + attribute \src "libresoc.v:146864.3-146873.6" + wire width 4 $0\dest2_o[3:0] + attribute \src "libresoc.v:145800.7-145800.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:146678.3-146686.6" + wire $0\opc_l_r_opc$next[0:0]$6721 + attribute \src "libresoc.v:146524.3-146525.39" + wire $0\opc_l_r_opc[0:0] + attribute \src "libresoc.v:146669.3-146677.6" + wire $0\opc_l_s_opc$next[0:0]$6718 + attribute \src "libresoc.v:146526.3-146527.39" + wire $0\opc_l_s_opc[0:0] + attribute \src "libresoc.v:146874.3-146882.6" + wire width 2 $0\prev_wr_go$next[1:0]$6812 + attribute \src "libresoc.v:146536.3-146537.37" + wire width 2 $0\prev_wr_go[1:0] + attribute \src "libresoc.v:146623.3-146632.6" + wire $0\req_done[0:0] + attribute \src "libresoc.v:146714.3-146722.6" + wire width 2 $0\req_l_r_req$next[1:0]$6733 + attribute \src "libresoc.v:146516.3-146517.39" + wire width 2 $0\req_l_r_req[1:0] + attribute \src "libresoc.v:146705.3-146713.6" + wire width 2 $0\req_l_s_req$next[1:0]$6730 + attribute \src "libresoc.v:146518.3-146519.39" + wire width 2 $0\req_l_s_req[1:0] + attribute \src "libresoc.v:146642.3-146650.6" + wire $0\rok_l_r_rdok$next[0:0]$6709 + attribute \src "libresoc.v:146532.3-146533.41" + wire $0\rok_l_r_rdok[0:0] + attribute \src "libresoc.v:146633.3-146641.6" + wire $0\rok_l_s_rdok$next[0:0]$6706 + attribute \src "libresoc.v:146534.3-146535.41" + wire $0\rok_l_s_rdok[0:0] + attribute \src "libresoc.v:146660.3-146668.6" + wire $0\rst_l_r_rst$next[0:0]$6715 + attribute \src "libresoc.v:146528.3-146529.39" + wire $0\rst_l_r_rst[0:0] + attribute \src "libresoc.v:146651.3-146659.6" + wire $0\rst_l_s_rst$next[0:0]$6712 + attribute \src "libresoc.v:146530.3-146531.39" + wire $0\rst_l_s_rst[0:0] + attribute \src "libresoc.v:146696.3-146704.6" + wire width 3 $0\src_l_r_src$next[2:0]$6727 + attribute \src "libresoc.v:146520.3-146521.39" + wire width 3 $0\src_l_r_src[2:0] + attribute \src "libresoc.v:146687.3-146695.6" + wire width 3 $0\src_l_s_src$next[2:0]$6724 + attribute \src "libresoc.v:146522.3-146523.39" + wire width 3 $0\src_l_s_src[2:0] + attribute \src "libresoc.v:146806.3-146815.6" + wire width 64 $0\src_r0$next[63:0]$6795 + attribute \src "libresoc.v:146470.3-146471.29" + wire width 64 $0\src_r0[63:0] + attribute \src "libresoc.v:146816.3-146825.6" + wire width 64 $0\src_r1$next[63:0]$6798 + attribute \src "libresoc.v:146468.3-146469.29" + wire width 64 $0\src_r1[63:0] + attribute \src "libresoc.v:146826.3-146835.6" + wire $0\src_r2$next[0:0]$6801 + attribute \src "libresoc.v:146466.3-146467.29" + wire $0\src_r2[0:0] + attribute \src "libresoc.v:145918.7-145918.24" + wire $1\all_rd_dly[0:0] + attribute \src "libresoc.v:145928.7-145928.26" + wire $1\alu_done_dly[0:0] + attribute \src "libresoc.v:146845.3-146853.6" + wire $1\alu_l_r_alu$next[0:0]$6808 + attribute \src "libresoc.v:145936.7-145936.25" + wire $1\alu_l_r_alu[0:0] + attribute \src "libresoc.v:146723.3-146761.6" + wire width 4 $1\alu_logical0_logical_op__data_len$next[3:0]$6754 + attribute \src "libresoc.v:145944.13-145944.53" + wire width 4 $1\alu_logical0_logical_op__data_len[3:0] + attribute \src "libresoc.v:146723.3-146761.6" + wire width 13 $1\alu_logical0_logical_op__fn_unit$next[12:0]$6755 + attribute \src "libresoc.v:145962.14-145962.57" + wire width 13 $1\alu_logical0_logical_op__fn_unit[12:0] + attribute \src "libresoc.v:146723.3-146761.6" + wire width 64 $1\alu_logical0_logical_op__imm_data__data$next[63:0]$6756 + attribute \src "libresoc.v:145966.14-145966.76" + wire width 64 $1\alu_logical0_logical_op__imm_data__data[63:0] + attribute \src "libresoc.v:146723.3-146761.6" + wire $1\alu_logical0_logical_op__imm_data__ok$next[0:0]$6757 + attribute \src "libresoc.v:145970.7-145970.51" + wire $1\alu_logical0_logical_op__imm_data__ok[0:0] + attribute \src "libresoc.v:146723.3-146761.6" + wire width 2 $1\alu_logical0_logical_op__input_carry$next[1:0]$6758 + attribute \src "libresoc.v:145978.13-145978.56" + wire width 2 $1\alu_logical0_logical_op__input_carry[1:0] + attribute \src "libresoc.v:146723.3-146761.6" + wire width 32 $1\alu_logical0_logical_op__insn$next[31:0]$6759 + attribute \src "libresoc.v:145982.14-145982.51" + wire width 32 $1\alu_logical0_logical_op__insn[31:0] + attribute \src "libresoc.v:146723.3-146761.6" + wire width 7 $1\alu_logical0_logical_op__insn_type$next[6:0]$6760 + attribute \src "libresoc.v:146060.13-146060.55" + wire width 7 $1\alu_logical0_logical_op__insn_type[6:0] + attribute \src "libresoc.v:146723.3-146761.6" + wire $1\alu_logical0_logical_op__invert_in$next[0:0]$6761 + attribute \src "libresoc.v:146064.7-146064.48" + wire $1\alu_logical0_logical_op__invert_in[0:0] + attribute \src "libresoc.v:146723.3-146761.6" + wire $1\alu_logical0_logical_op__invert_out$next[0:0]$6762 + attribute \src "libresoc.v:146068.7-146068.49" + wire $1\alu_logical0_logical_op__invert_out[0:0] + attribute \src "libresoc.v:146723.3-146761.6" + wire $1\alu_logical0_logical_op__is_32bit$next[0:0]$6763 + attribute \src "libresoc.v:146072.7-146072.47" + wire $1\alu_logical0_logical_op__is_32bit[0:0] + attribute \src "libresoc.v:146723.3-146761.6" + wire $1\alu_logical0_logical_op__is_signed$next[0:0]$6764 + attribute \src "libresoc.v:146076.7-146076.48" + wire $1\alu_logical0_logical_op__is_signed[0:0] + attribute \src "libresoc.v:146723.3-146761.6" + wire $1\alu_logical0_logical_op__oe__oe$next[0:0]$6765 + attribute \src "libresoc.v:146080.7-146080.45" + wire $1\alu_logical0_logical_op__oe__oe[0:0] + attribute \src "libresoc.v:146723.3-146761.6" + wire $1\alu_logical0_logical_op__oe__ok$next[0:0]$6766 + attribute \src "libresoc.v:146084.7-146084.45" + wire $1\alu_logical0_logical_op__oe__ok[0:0] + attribute \src "libresoc.v:146723.3-146761.6" + wire $1\alu_logical0_logical_op__output_carry$next[0:0]$6767 + attribute \src "libresoc.v:146088.7-146088.51" + wire $1\alu_logical0_logical_op__output_carry[0:0] + attribute \src "libresoc.v:146723.3-146761.6" + wire $1\alu_logical0_logical_op__rc__ok$next[0:0]$6768 + attribute \src "libresoc.v:146092.7-146092.45" + wire $1\alu_logical0_logical_op__rc__ok[0:0] + attribute \src "libresoc.v:146723.3-146761.6" + wire $1\alu_logical0_logical_op__rc__rc$next[0:0]$6769 + attribute \src "libresoc.v:146096.7-146096.45" + wire $1\alu_logical0_logical_op__rc__rc[0:0] + attribute \src "libresoc.v:146723.3-146761.6" + wire $1\alu_logical0_logical_op__write_cr0$next[0:0]$6770 + attribute \src "libresoc.v:146100.7-146100.48" + wire $1\alu_logical0_logical_op__write_cr0[0:0] + attribute \src "libresoc.v:146723.3-146761.6" + wire $1\alu_logical0_logical_op__zero_a$next[0:0]$6771 + attribute \src "libresoc.v:146104.7-146104.45" + wire $1\alu_logical0_logical_op__zero_a[0:0] + attribute \src "libresoc.v:146836.3-146844.6" + wire $1\alui_l_r_alui$next[0:0]$6805 + attribute \src "libresoc.v:146130.7-146130.27" + wire $1\alui_l_r_alui[0:0] + attribute \src "libresoc.v:146762.3-146783.6" + wire width 64 $1\data_r0__o$next[63:0]$6781 + attribute \src "libresoc.v:146164.14-146164.47" + wire width 64 $1\data_r0__o[63:0] + attribute \src "libresoc.v:146762.3-146783.6" + wire $1\data_r0__o_ok$next[0:0]$6782 + attribute \src "libresoc.v:146168.7-146168.27" + wire $1\data_r0__o_ok[0:0] + attribute \src "libresoc.v:146784.3-146805.6" + wire width 4 $1\data_r1__cr_a$next[3:0]$6789 + attribute \src "libresoc.v:146172.13-146172.33" + wire width 4 $1\data_r1__cr_a[3:0] + attribute \src "libresoc.v:146784.3-146805.6" + wire $1\data_r1__cr_a_ok$next[0:0]$6790 + attribute \src "libresoc.v:146176.7-146176.30" + wire $1\data_r1__cr_a_ok[0:0] + attribute \src "libresoc.v:146854.3-146863.6" + wire width 64 $1\dest1_o[63:0] + attribute \src "libresoc.v:146864.3-146873.6" + wire width 4 $1\dest2_o[3:0] + attribute \src "libresoc.v:146678.3-146686.6" + wire $1\opc_l_r_opc$next[0:0]$6722 + attribute \src "libresoc.v:146190.7-146190.25" + wire $1\opc_l_r_opc[0:0] + attribute \src "libresoc.v:146669.3-146677.6" + wire $1\opc_l_s_opc$next[0:0]$6719 + attribute \src "libresoc.v:146194.7-146194.25" + wire $1\opc_l_s_opc[0:0] + attribute \src "libresoc.v:146874.3-146882.6" + wire width 2 $1\prev_wr_go$next[1:0]$6813 + attribute \src "libresoc.v:146326.13-146326.30" + wire width 2 $1\prev_wr_go[1:0] + attribute \src "libresoc.v:146623.3-146632.6" + wire $1\req_done[0:0] + attribute \src "libresoc.v:146714.3-146722.6" + wire width 2 $1\req_l_r_req$next[1:0]$6734 + attribute \src "libresoc.v:146334.13-146334.31" + wire width 2 $1\req_l_r_req[1:0] + attribute \src "libresoc.v:146705.3-146713.6" + wire width 2 $1\req_l_s_req$next[1:0]$6731 + attribute \src "libresoc.v:146338.13-146338.31" + wire width 2 $1\req_l_s_req[1:0] + attribute \src "libresoc.v:146642.3-146650.6" + wire $1\rok_l_r_rdok$next[0:0]$6710 + attribute \src "libresoc.v:146350.7-146350.26" + wire $1\rok_l_r_rdok[0:0] + attribute \src "libresoc.v:146633.3-146641.6" + wire $1\rok_l_s_rdok$next[0:0]$6707 + attribute \src "libresoc.v:146354.7-146354.26" + wire $1\rok_l_s_rdok[0:0] + attribute \src "libresoc.v:146660.3-146668.6" + wire $1\rst_l_r_rst$next[0:0]$6716 + attribute \src "libresoc.v:146358.7-146358.25" + wire $1\rst_l_r_rst[0:0] + attribute \src "libresoc.v:146651.3-146659.6" + wire $1\rst_l_s_rst$next[0:0]$6713 + attribute \src "libresoc.v:146362.7-146362.25" + wire $1\rst_l_s_rst[0:0] + attribute \src "libresoc.v:146696.3-146704.6" + wire width 3 $1\src_l_r_src$next[2:0]$6728 + attribute \src "libresoc.v:146376.13-146376.31" + wire width 3 $1\src_l_r_src[2:0] + attribute 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\enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \alu_logical0_logical_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \alu_logical0_logical_op__input_carry$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \alu_logical0_logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \alu_logical0_logical_op__insn$next + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \alu_logical0_logical_op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \alu_logical0_logical_op__insn_type$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_logical0_logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_logical0_logical_op__invert_in$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_logical0_logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_logical0_logical_op__invert_out$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_logical0_logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_logical0_logical_op__is_32bit$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_logical0_logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_logical0_logical_op__is_signed$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_logical0_logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_logical0_logical_op__oe__oe$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_logical0_logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_logical0_logical_op__oe__ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_logical0_logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_logical0_logical_op__output_carry$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_logical0_logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_logical0_logical_op__rc__ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_logical0_logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_logical0_logical_op__rc__rc$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_logical0_logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_logical0_logical_op__write_cr0$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_logical0_logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_logical0_logical_op__zero_a$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire \alu_logical0_n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire \alu_logical0_n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \alu_logical0_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" + wire \alu_logical0_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" + wire \alu_logical0_p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \alu_logical0_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \alu_logical0_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \alu_logical0_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:197" + wire \alu_pulse + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198" + wire width 2 \alu_pulsem + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire \alui_l_q_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \alui_l_r_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \alui_l_r_alui$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire \alui_l_s_alui + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 34 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 32 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" + wire output 21 \cu_busy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:108" + wire \cu_done_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:104" + wire \cu_go_die_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" + wire input 20 \cu_issue_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 input 24 \cu_rd__go_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 output 23 \cu_rd__rel_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" + wire width 3 input 22 \cu_rdmaskn_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:102" + wire \cu_shadown_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 2 input 30 \cu_wr__go_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 2 output 29 \cu_wr__rel_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:97" + wire width 2 \cu_wrmask_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 64 \data_r0__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 64 \data_r0__o$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r0__o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r0__o_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 4 \data_r1__cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 4 \data_r1__cr_a$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r1__cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r1__cr_a_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 31 \dest1_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 4 output 33 \dest2_o + attribute \src "libresoc.v:145800.7-145800.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 28 \o_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire \opc_l_q_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \opc_l_r_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \opc_l_r_opc$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire \opc_l_s_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire \opc_l_s_opc$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 18 \oper_i_alu_logical0__data_len + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 input 3 \oper_i_alu_logical0__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 4 \oper_i_alu_logical0__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 5 \oper_i_alu_logical0__imm_data__ok + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 12 \oper_i_alu_logical0__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 19 \oper_i_alu_logical0__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute 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"/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + cell $not $not$libresoc.v:146429$6631 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_logical0_n_ready_i + connect \Y $not$libresoc.v:146429$6631_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $not $not$libresoc.v:146435$6637 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \cu_rd__rel_o + connect \Y $not$libresoc.v:146435$6637_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" + cell $not $not$libresoc.v:146460$6662 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_logical0_logical_op__zero_a + connect \Y $not$libresoc.v:146460$6662_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" + cell $not $not$libresoc.v:146461$6663 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_logical0_logical_op__imm_data__ok + connect \Y $not$libresoc.v:146461$6663_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $or $or$libresoc.v:146428$6630 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$31 + connect \B \$33 + connect \Y $or$libresoc.v:146428$6630_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" + cell $or $or$libresoc.v:146439$6641 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \req_done + connect \B \cu_go_die_i + connect \Y $or$libresoc.v:146439$6641_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" + cell $or $or$libresoc.v:146440$6642 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_issue_i + connect \B \cu_go_die_i + connect \Y $or$libresoc.v:146440$6642_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" + cell $or $or$libresoc.v:146441$6643 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \cu_wr__go_i + connect \B { \cu_go_die_i \cu_go_die_i } + connect \Y $or$libresoc.v:146441$6643_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" + cell $or $or$libresoc.v:146442$6644 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \cu_rd__go_i + connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } + connect \Y $or$libresoc.v:146442$6644_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" + cell $or $or$libresoc.v:146445$6647 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \reset_w + connect \B \prev_wr_go + connect \Y $or$libresoc.v:146445$6647_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $or $or$libresoc.v:146446$6648 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \$4 + connect \B \cu_rd__go_i + connect \Y $or$libresoc.v:146446$6648_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $reduce_and $reduce_and$libresoc.v:146452$6654 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \$6 + connect \Y $reduce_and$libresoc.v:146452$6654_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $reduce_or $reduce_or$libresoc.v:146423$6625 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \$25 + connect \Y $reduce_or$libresoc.v:146423$6625_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $reduce_or $reduce_or$libresoc.v:146426$6628 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \cu_wr__go_i + connect \Y $reduce_or$libresoc.v:146426$6628_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $reduce_or $reduce_or$libresoc.v:146427$6629 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \prev_wr_go + connect \Y $reduce_or$libresoc.v:146427$6629_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" + cell $mux $ternary$libresoc.v:146449$6651 + parameter \WIDTH 1 + connect \A \src_l_q_src [0] + connect \B \opc_l_q_opc + connect \S \alu_logical0_logical_op__zero_a + connect \Y $ternary$libresoc.v:146449$6651_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" + cell $mux $ternary$libresoc.v:146450$6652 + parameter \WIDTH 64 + connect \A \src1_i + connect \B 64'0000000000000000000000000000000000000000000000000000000000000000 + connect \S \alu_logical0_logical_op__zero_a + connect \Y $ternary$libresoc.v:146450$6652_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" + cell $mux $ternary$libresoc.v:146451$6653 + parameter \WIDTH 1 + connect \A \src_l_q_src [1] + connect \B \opc_l_q_opc + connect \S \alu_logical0_logical_op__imm_data__ok + connect \Y $ternary$libresoc.v:146451$6653_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" + cell $mux $ternary$libresoc.v:146453$6655 + parameter \WIDTH 64 + connect \A \src2_i + connect \B \alu_logical0_logical_op__imm_data__data + connect \S \alu_logical0_logical_op__imm_data__ok + connect \Y $ternary$libresoc.v:146453$6655_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" + cell $mux $ternary$libresoc.v:146454$6656 + parameter \WIDTH 64 + connect \A \src_r0 + connect \B \src_or_imm + connect \S \src_sel + connect \Y $ternary$libresoc.v:146454$6656_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" + cell $mux $ternary$libresoc.v:146455$6657 + parameter \WIDTH 64 + connect \A \src_r1 + connect \B \src_or_imm$80 + connect \S \src_sel$77 + connect \Y $ternary$libresoc.v:146455$6657_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" + cell $mux $ternary$libresoc.v:146456$6658 + parameter \WIDTH 1 + connect \A \src_r2 + connect \B \src3_i + connect \S \src_l_q_src [2] + connect \Y $ternary$libresoc.v:146456$6658_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:146542.14-146548.4" + cell \alu_l$61 \alu_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_alu \alu_l_q_alu + connect \r_alu \alu_l_r_alu + connect \s_alu \alu_l_s_alu + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:146549.16-146581.4" + cell \alu_logical0 \alu_logical0 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cr_a \alu_logical0_cr_a + connect \cr_a_ok \cr_a_ok + connect \logical_op__data_len \alu_logical0_logical_op__data_len + connect \logical_op__fn_unit \alu_logical0_logical_op__fn_unit + connect \logical_op__imm_data__data \alu_logical0_logical_op__imm_data__data + connect \logical_op__imm_data__ok \alu_logical0_logical_op__imm_data__ok + connect \logical_op__input_carry \alu_logical0_logical_op__input_carry + connect \logical_op__insn \alu_logical0_logical_op__insn + connect \logical_op__insn_type \alu_logical0_logical_op__insn_type + connect \logical_op__invert_in \alu_logical0_logical_op__invert_in + connect \logical_op__invert_out \alu_logical0_logical_op__invert_out + connect \logical_op__is_32bit \alu_logical0_logical_op__is_32bit + connect \logical_op__is_signed \alu_logical0_logical_op__is_signed + connect \logical_op__oe__oe \alu_logical0_logical_op__oe__oe + connect \logical_op__oe__ok \alu_logical0_logical_op__oe__ok + connect \logical_op__output_carry \alu_logical0_logical_op__output_carry + connect \logical_op__rc__ok \alu_logical0_logical_op__rc__ok + connect \logical_op__rc__rc \alu_logical0_logical_op__rc__rc + connect \logical_op__write_cr0 \alu_logical0_logical_op__write_cr0 + connect \logical_op__zero_a \alu_logical0_logical_op__zero_a + connect \n_ready_i \alu_logical0_n_ready_i + connect \n_valid_o \alu_logical0_n_valid_o + connect \o \alu_logical0_o + connect \o_ok \o_ok + connect \p_ready_o \alu_logical0_p_ready_o + connect \p_valid_i \alu_logical0_p_valid_i + connect \ra \alu_logical0_ra + connect \rb \alu_logical0_rb + connect \xer_so \alu_logical0_xer_so + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:146582.15-146588.4" + cell \alui_l$60 \alui_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_alui \alui_l_q_alui + connect \r_alui \alui_l_r_alui + connect \s_alui \alui_l_s_alui + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:146589.14-146595.4" + cell \opc_l$56 \opc_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_opc \opc_l_q_opc + connect \r_opc \opc_l_r_opc + connect \s_opc \opc_l_s_opc + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:146596.14-146602.4" + cell \req_l$57 \req_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_req \req_l_q_req + connect \r_req \req_l_r_req + connect \s_req \req_l_s_req + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:146603.14-146609.4" + cell \rok_l$59 \rok_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_rdok \rok_l_q_rdok + connect \r_rdok \rok_l_r_rdok + connect \s_rdok \rok_l_s_rdok + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:146610.14-146615.4" + cell \rst_l$58 \rst_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \r_rst \rst_l_r_rst + connect \s_rst \rst_l_s_rst + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:146616.14-146622.4" + cell \src_l$55 \src_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_src \src_l_q_src + connect \r_src \src_l_r_src + connect \s_src \src_l_s_src + end + attribute \src "libresoc.v:145800.7-145800.20" + process $proc$libresoc.v:145800$6814 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:145918.7-145918.24" + process $proc$libresoc.v:145918$6815 + assign { } { } + assign $1\all_rd_dly[0:0] 1'0 + sync always + sync init + update \all_rd_dly $1\all_rd_dly[0:0] + end + attribute \src "libresoc.v:145928.7-145928.26" + process $proc$libresoc.v:145928$6816 + assign { } { } + assign $1\alu_done_dly[0:0] 1'0 + sync always + sync init + update \alu_done_dly $1\alu_done_dly[0:0] + end + attribute \src "libresoc.v:145936.7-145936.25" + process $proc$libresoc.v:145936$6817 + assign { } { } + assign $1\alu_l_r_alu[0:0] 1'1 + sync always + sync init + update \alu_l_r_alu $1\alu_l_r_alu[0:0] + end + attribute \src "libresoc.v:145944.13-145944.53" + process $proc$libresoc.v:145944$6818 + assign { } { } + assign $1\alu_logical0_logical_op__data_len[3:0] 4'0000 + sync always + sync init + update \alu_logical0_logical_op__data_len $1\alu_logical0_logical_op__data_len[3:0] + end + attribute \src "libresoc.v:145962.14-145962.57" + process $proc$libresoc.v:145962$6819 + assign { } { } + assign $1\alu_logical0_logical_op__fn_unit[12:0] 13'0000000000000 + sync always + sync init + update \alu_logical0_logical_op__fn_unit $1\alu_logical0_logical_op__fn_unit[12:0] + end + attribute \src "libresoc.v:145966.14-145966.76" + process $proc$libresoc.v:145966$6820 + assign { } { } + assign $1\alu_logical0_logical_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \alu_logical0_logical_op__imm_data__data $1\alu_logical0_logical_op__imm_data__data[63:0] + end + attribute \src "libresoc.v:145970.7-145970.51" + process $proc$libresoc.v:145970$6821 + assign { } { } + assign $1\alu_logical0_logical_op__imm_data__ok[0:0] 1'0 + sync always + sync init + update \alu_logical0_logical_op__imm_data__ok $1\alu_logical0_logical_op__imm_data__ok[0:0] + end + attribute \src "libresoc.v:145978.13-145978.56" + process $proc$libresoc.v:145978$6822 + assign { } { } + assign $1\alu_logical0_logical_op__input_carry[1:0] 2'00 + sync always + sync init + update \alu_logical0_logical_op__input_carry $1\alu_logical0_logical_op__input_carry[1:0] + end + attribute \src "libresoc.v:145982.14-145982.51" + process $proc$libresoc.v:145982$6823 + assign { } { } + assign $1\alu_logical0_logical_op__insn[31:0] 0 + sync always + sync init + update \alu_logical0_logical_op__insn $1\alu_logical0_logical_op__insn[31:0] + end + attribute \src "libresoc.v:146060.13-146060.55" + process $proc$libresoc.v:146060$6824 + assign { } { } + assign $1\alu_logical0_logical_op__insn_type[6:0] 7'0000000 + sync always + sync init + update \alu_logical0_logical_op__insn_type $1\alu_logical0_logical_op__insn_type[6:0] + end + attribute \src "libresoc.v:146064.7-146064.48" + process $proc$libresoc.v:146064$6825 + assign { } { } + assign $1\alu_logical0_logical_op__invert_in[0:0] 1'0 + sync always + sync init + update \alu_logical0_logical_op__invert_in $1\alu_logical0_logical_op__invert_in[0:0] + end + attribute \src "libresoc.v:146068.7-146068.49" + process $proc$libresoc.v:146068$6826 + assign { } { } + assign $1\alu_logical0_logical_op__invert_out[0:0] 1'0 + sync always + sync init + update \alu_logical0_logical_op__invert_out $1\alu_logical0_logical_op__invert_out[0:0] + end + attribute \src "libresoc.v:146072.7-146072.47" + process $proc$libresoc.v:146072$6827 + assign { } { } + assign $1\alu_logical0_logical_op__is_32bit[0:0] 1'0 + sync always + sync init + update \alu_logical0_logical_op__is_32bit $1\alu_logical0_logical_op__is_32bit[0:0] + end + attribute \src "libresoc.v:146076.7-146076.48" + process $proc$libresoc.v:146076$6828 + assign { } { } + assign $1\alu_logical0_logical_op__is_signed[0:0] 1'0 + sync always + sync init + update \alu_logical0_logical_op__is_signed $1\alu_logical0_logical_op__is_signed[0:0] + end + attribute \src "libresoc.v:146080.7-146080.45" + process $proc$libresoc.v:146080$6829 + assign { } { } + assign $1\alu_logical0_logical_op__oe__oe[0:0] 1'0 + sync always + sync init + update \alu_logical0_logical_op__oe__oe $1\alu_logical0_logical_op__oe__oe[0:0] + end + attribute \src "libresoc.v:146084.7-146084.45" + process $proc$libresoc.v:146084$6830 + assign { } { } + assign $1\alu_logical0_logical_op__oe__ok[0:0] 1'0 + sync always + sync init + update \alu_logical0_logical_op__oe__ok $1\alu_logical0_logical_op__oe__ok[0:0] + end + attribute \src "libresoc.v:146088.7-146088.51" + process $proc$libresoc.v:146088$6831 + assign { } { } + assign $1\alu_logical0_logical_op__output_carry[0:0] 1'0 + sync always + sync init + update \alu_logical0_logical_op__output_carry $1\alu_logical0_logical_op__output_carry[0:0] + end + attribute \src "libresoc.v:146092.7-146092.45" + process $proc$libresoc.v:146092$6832 + assign { } { } + assign $1\alu_logical0_logical_op__rc__ok[0:0] 1'0 + sync always + sync init + update \alu_logical0_logical_op__rc__ok $1\alu_logical0_logical_op__rc__ok[0:0] + end + attribute \src "libresoc.v:146096.7-146096.45" + process $proc$libresoc.v:146096$6833 + assign { } { } + assign $1\alu_logical0_logical_op__rc__rc[0:0] 1'0 + sync always + sync init + update \alu_logical0_logical_op__rc__rc $1\alu_logical0_logical_op__rc__rc[0:0] + end + attribute \src "libresoc.v:146100.7-146100.48" + process $proc$libresoc.v:146100$6834 + assign { } { } + assign $1\alu_logical0_logical_op__write_cr0[0:0] 1'0 + sync always + sync init + update \alu_logical0_logical_op__write_cr0 $1\alu_logical0_logical_op__write_cr0[0:0] + end + attribute \src "libresoc.v:146104.7-146104.45" + process $proc$libresoc.v:146104$6835 + assign { } { } + assign $1\alu_logical0_logical_op__zero_a[0:0] 1'0 + sync always + sync init + update \alu_logical0_logical_op__zero_a $1\alu_logical0_logical_op__zero_a[0:0] + end + attribute \src "libresoc.v:146130.7-146130.27" + process $proc$libresoc.v:146130$6836 + assign { } { } + assign $1\alui_l_r_alui[0:0] 1'1 + sync always + sync init + update \alui_l_r_alui $1\alui_l_r_alui[0:0] + end + attribute \src "libresoc.v:146164.14-146164.47" + process $proc$libresoc.v:146164$6837 + assign { } { } + assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \data_r0__o $1\data_r0__o[63:0] + end + attribute \src "libresoc.v:146168.7-146168.27" + process $proc$libresoc.v:146168$6838 + assign { } { } + assign $1\data_r0__o_ok[0:0] 1'0 + sync always + sync init + update \data_r0__o_ok $1\data_r0__o_ok[0:0] + end + attribute \src "libresoc.v:146172.13-146172.33" + process $proc$libresoc.v:146172$6839 + assign { } { } + assign $1\data_r1__cr_a[3:0] 4'0000 + sync always + sync init + update \data_r1__cr_a $1\data_r1__cr_a[3:0] + end + attribute \src "libresoc.v:146176.7-146176.30" + process $proc$libresoc.v:146176$6840 + assign { } { } + assign $1\data_r1__cr_a_ok[0:0] 1'0 + sync always + sync init + update \data_r1__cr_a_ok $1\data_r1__cr_a_ok[0:0] + end + attribute \src "libresoc.v:146190.7-146190.25" + process $proc$libresoc.v:146190$6841 + assign { } { } + assign $1\opc_l_r_opc[0:0] 1'1 + sync always + sync init + update \opc_l_r_opc $1\opc_l_r_opc[0:0] + end + attribute \src "libresoc.v:146194.7-146194.25" + process $proc$libresoc.v:146194$6842 + assign { } { } + assign $1\opc_l_s_opc[0:0] 1'0 + sync always + sync init + update \opc_l_s_opc $1\opc_l_s_opc[0:0] + end + attribute \src "libresoc.v:146326.13-146326.30" + process $proc$libresoc.v:146326$6843 + assign { } { } + assign $1\prev_wr_go[1:0] 2'00 + sync always + sync init + update \prev_wr_go $1\prev_wr_go[1:0] + end + attribute \src "libresoc.v:146334.13-146334.31" + process $proc$libresoc.v:146334$6844 + assign { } { } + assign $1\req_l_r_req[1:0] 2'11 + sync always + sync init + update \req_l_r_req $1\req_l_r_req[1:0] + end + attribute \src "libresoc.v:146338.13-146338.31" + process $proc$libresoc.v:146338$6845 + assign { } { } + assign $1\req_l_s_req[1:0] 2'00 + sync always + sync init + update \req_l_s_req $1\req_l_s_req[1:0] + end + attribute \src "libresoc.v:146350.7-146350.26" + process $proc$libresoc.v:146350$6846 + assign { } { } + assign $1\rok_l_r_rdok[0:0] 1'1 + sync always + sync init + update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] + end + attribute \src "libresoc.v:146354.7-146354.26" + process $proc$libresoc.v:146354$6847 + assign { } { } + assign $1\rok_l_s_rdok[0:0] 1'0 + sync always + sync init + update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] + end + attribute \src "libresoc.v:146358.7-146358.25" + process $proc$libresoc.v:146358$6848 + assign { } { } + assign $1\rst_l_r_rst[0:0] 1'1 + sync always + sync init + update \rst_l_r_rst $1\rst_l_r_rst[0:0] + end + attribute \src "libresoc.v:146362.7-146362.25" + process $proc$libresoc.v:146362$6849 + assign { } { } + assign $1\rst_l_s_rst[0:0] 1'0 + sync always + sync init + update \rst_l_s_rst $1\rst_l_s_rst[0:0] + end + attribute \src "libresoc.v:146376.13-146376.31" + process $proc$libresoc.v:146376$6850 + assign { } { } + assign $1\src_l_r_src[2:0] 3'111 + sync always + sync init + update \src_l_r_src $1\src_l_r_src[2:0] + end + attribute \src "libresoc.v:146380.13-146380.31" + process $proc$libresoc.v:146380$6851 + assign { } { } + assign $1\src_l_s_src[2:0] 3'000 + sync always + sync init + update \src_l_s_src $1\src_l_s_src[2:0] + end + attribute \src "libresoc.v:146388.14-146388.43" + process $proc$libresoc.v:146388$6852 + assign { } { } + assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \src_r0 $1\src_r0[63:0] + end + attribute \src "libresoc.v:146392.14-146392.43" + process $proc$libresoc.v:146392$6853 + assign { } { } + assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \src_r1 $1\src_r1[63:0] + end + attribute \src "libresoc.v:146396.7-146396.20" + process $proc$libresoc.v:146396$6854 + assign { } { } + assign $1\src_r2[0:0] 1'0 + sync always + sync init + update \src_r2 $1\src_r2[0:0] + end + attribute \src "libresoc.v:146462.3-146463.39" + process $proc$libresoc.v:146462$6664 + assign { } { } + assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next + sync posedge \coresync_clk + update \alu_l_r_alu $0\alu_l_r_alu[0:0] + end + attribute \src "libresoc.v:146464.3-146465.43" + process $proc$libresoc.v:146464$6665 + assign { } { } + assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next + sync posedge \coresync_clk + update \alui_l_r_alui $0\alui_l_r_alui[0:0] + end + attribute \src "libresoc.v:146466.3-146467.29" + process $proc$libresoc.v:146466$6666 + assign { } { } + assign $0\src_r2[0:0] \src_r2$next + sync posedge \coresync_clk + update \src_r2 $0\src_r2[0:0] + end + attribute \src "libresoc.v:146468.3-146469.29" + process $proc$libresoc.v:146468$6667 + assign { } { } + assign $0\src_r1[63:0] \src_r1$next + sync posedge \coresync_clk + update \src_r1 $0\src_r1[63:0] + end + attribute \src "libresoc.v:146470.3-146471.29" + process $proc$libresoc.v:146470$6668 + assign { } { } + assign $0\src_r0[63:0] \src_r0$next + sync posedge \coresync_clk + update \src_r0 $0\src_r0[63:0] + end + attribute \src "libresoc.v:146472.3-146473.43" + process $proc$libresoc.v:146472$6669 + assign { } { } + assign $0\data_r1__cr_a[3:0] \data_r1__cr_a$next + sync posedge \coresync_clk + update \data_r1__cr_a $0\data_r1__cr_a[3:0] + end + attribute \src "libresoc.v:146474.3-146475.49" + process $proc$libresoc.v:146474$6670 + assign { } { } + assign $0\data_r1__cr_a_ok[0:0] \data_r1__cr_a_ok$next + sync posedge \coresync_clk + update \data_r1__cr_a_ok $0\data_r1__cr_a_ok[0:0] + end + attribute \src "libresoc.v:146476.3-146477.37" + process $proc$libresoc.v:146476$6671 + assign { } { } + assign $0\data_r0__o[63:0] \data_r0__o$next + sync posedge \coresync_clk + update \data_r0__o $0\data_r0__o[63:0] + end + attribute \src "libresoc.v:146478.3-146479.43" + process $proc$libresoc.v:146478$6672 + assign { } { } + assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next + sync posedge \coresync_clk + update \data_r0__o_ok $0\data_r0__o_ok[0:0] + end + attribute \src "libresoc.v:146480.3-146481.85" + process $proc$libresoc.v:146480$6673 + assign { } { } + assign $0\alu_logical0_logical_op__insn_type[6:0] \alu_logical0_logical_op__insn_type$next + sync posedge \coresync_clk + update \alu_logical0_logical_op__insn_type $0\alu_logical0_logical_op__insn_type[6:0] + end + attribute \src "libresoc.v:146482.3-146483.81" + process $proc$libresoc.v:146482$6674 + assign { } { } + assign $0\alu_logical0_logical_op__fn_unit[12:0] \alu_logical0_logical_op__fn_unit$next + sync posedge \coresync_clk + update \alu_logical0_logical_op__fn_unit $0\alu_logical0_logical_op__fn_unit[12:0] + end + attribute \src "libresoc.v:146484.3-146485.95" + process $proc$libresoc.v:146484$6675 + assign { } { } + assign $0\alu_logical0_logical_op__imm_data__data[63:0] \alu_logical0_logical_op__imm_data__data$next + sync posedge \coresync_clk + update \alu_logical0_logical_op__imm_data__data $0\alu_logical0_logical_op__imm_data__data[63:0] + end + attribute \src "libresoc.v:146486.3-146487.91" + process $proc$libresoc.v:146486$6676 + assign { } { } + assign $0\alu_logical0_logical_op__imm_data__ok[0:0] \alu_logical0_logical_op__imm_data__ok$next + sync posedge \coresync_clk + update \alu_logical0_logical_op__imm_data__ok $0\alu_logical0_logical_op__imm_data__ok[0:0] + end + attribute \src "libresoc.v:146488.3-146489.79" + process $proc$libresoc.v:146488$6677 + assign { } { } + assign $0\alu_logical0_logical_op__rc__rc[0:0] \alu_logical0_logical_op__rc__rc$next + sync posedge \coresync_clk + update \alu_logical0_logical_op__rc__rc $0\alu_logical0_logical_op__rc__rc[0:0] + end + attribute \src "libresoc.v:146490.3-146491.79" + process $proc$libresoc.v:146490$6678 + assign { } { } + assign $0\alu_logical0_logical_op__rc__ok[0:0] \alu_logical0_logical_op__rc__ok$next + sync posedge \coresync_clk + update \alu_logical0_logical_op__rc__ok $0\alu_logical0_logical_op__rc__ok[0:0] + end + attribute \src "libresoc.v:146492.3-146493.79" + process $proc$libresoc.v:146492$6679 + assign { } { } + assign $0\alu_logical0_logical_op__oe__oe[0:0] \alu_logical0_logical_op__oe__oe$next + sync posedge \coresync_clk + update \alu_logical0_logical_op__oe__oe $0\alu_logical0_logical_op__oe__oe[0:0] + end + attribute \src "libresoc.v:146494.3-146495.79" + process $proc$libresoc.v:146494$6680 + assign { } { } + assign $0\alu_logical0_logical_op__oe__ok[0:0] \alu_logical0_logical_op__oe__ok$next + sync posedge \coresync_clk + update \alu_logical0_logical_op__oe__ok $0\alu_logical0_logical_op__oe__ok[0:0] + end + attribute \src "libresoc.v:146496.3-146497.85" + process $proc$libresoc.v:146496$6681 + assign { } { } + assign $0\alu_logical0_logical_op__invert_in[0:0] \alu_logical0_logical_op__invert_in$next + sync posedge \coresync_clk + update \alu_logical0_logical_op__invert_in $0\alu_logical0_logical_op__invert_in[0:0] + end + attribute \src "libresoc.v:146498.3-146499.79" + process $proc$libresoc.v:146498$6682 + assign { } { } + assign $0\alu_logical0_logical_op__zero_a[0:0] \alu_logical0_logical_op__zero_a$next + sync posedge \coresync_clk + update \alu_logical0_logical_op__zero_a $0\alu_logical0_logical_op__zero_a[0:0] + end + attribute \src "libresoc.v:146500.3-146501.89" + process $proc$libresoc.v:146500$6683 + assign { } { } + assign $0\alu_logical0_logical_op__input_carry[1:0] \alu_logical0_logical_op__input_carry$next + sync posedge \coresync_clk + update \alu_logical0_logical_op__input_carry $0\alu_logical0_logical_op__input_carry[1:0] + end + attribute \src "libresoc.v:146502.3-146503.87" + process $proc$libresoc.v:146502$6684 + assign { } { } + assign $0\alu_logical0_logical_op__invert_out[0:0] \alu_logical0_logical_op__invert_out$next + sync posedge \coresync_clk + update \alu_logical0_logical_op__invert_out $0\alu_logical0_logical_op__invert_out[0:0] + end + attribute \src "libresoc.v:146504.3-146505.85" + process $proc$libresoc.v:146504$6685 + assign { } { } + assign $0\alu_logical0_logical_op__write_cr0[0:0] \alu_logical0_logical_op__write_cr0$next + sync posedge \coresync_clk + update \alu_logical0_logical_op__write_cr0 $0\alu_logical0_logical_op__write_cr0[0:0] + end + attribute \src "libresoc.v:146506.3-146507.91" + process $proc$libresoc.v:146506$6686 + assign { } { } + assign $0\alu_logical0_logical_op__output_carry[0:0] \alu_logical0_logical_op__output_carry$next + sync posedge \coresync_clk + update \alu_logical0_logical_op__output_carry $0\alu_logical0_logical_op__output_carry[0:0] + end + attribute \src "libresoc.v:146508.3-146509.83" + process $proc$libresoc.v:146508$6687 + assign { } { } + assign $0\alu_logical0_logical_op__is_32bit[0:0] \alu_logical0_logical_op__is_32bit$next + sync posedge \coresync_clk + update \alu_logical0_logical_op__is_32bit $0\alu_logical0_logical_op__is_32bit[0:0] + end + attribute \src "libresoc.v:146510.3-146511.85" + process $proc$libresoc.v:146510$6688 + assign { } { } + assign $0\alu_logical0_logical_op__is_signed[0:0] \alu_logical0_logical_op__is_signed$next + sync posedge \coresync_clk + update \alu_logical0_logical_op__is_signed $0\alu_logical0_logical_op__is_signed[0:0] + end + attribute \src "libresoc.v:146512.3-146513.83" + process $proc$libresoc.v:146512$6689 + assign { } { } + assign $0\alu_logical0_logical_op__data_len[3:0] \alu_logical0_logical_op__data_len$next + sync posedge \coresync_clk + update \alu_logical0_logical_op__data_len $0\alu_logical0_logical_op__data_len[3:0] + end + attribute \src "libresoc.v:146514.3-146515.75" + process $proc$libresoc.v:146514$6690 + assign { } { } + assign $0\alu_logical0_logical_op__insn[31:0] \alu_logical0_logical_op__insn$next + sync posedge \coresync_clk + update \alu_logical0_logical_op__insn $0\alu_logical0_logical_op__insn[31:0] + end + attribute \src "libresoc.v:146516.3-146517.39" + process $proc$libresoc.v:146516$6691 + assign { } { } + assign $0\req_l_r_req[1:0] \req_l_r_req$next + sync posedge \coresync_clk + update \req_l_r_req $0\req_l_r_req[1:0] + end + attribute \src "libresoc.v:146518.3-146519.39" + process $proc$libresoc.v:146518$6692 + assign { } { } + assign $0\req_l_s_req[1:0] \req_l_s_req$next + sync posedge \coresync_clk + update \req_l_s_req $0\req_l_s_req[1:0] + end + attribute \src "libresoc.v:146520.3-146521.39" + process $proc$libresoc.v:146520$6693 + assign { } { } + assign $0\src_l_r_src[2:0] \src_l_r_src$next + sync posedge \coresync_clk + update \src_l_r_src $0\src_l_r_src[2:0] + end + attribute \src "libresoc.v:146522.3-146523.39" + process $proc$libresoc.v:146522$6694 + assign { } { } + assign $0\src_l_s_src[2:0] \src_l_s_src$next + sync posedge \coresync_clk + update \src_l_s_src $0\src_l_s_src[2:0] + end + attribute \src "libresoc.v:146524.3-146525.39" + process $proc$libresoc.v:146524$6695 + assign { } { } + assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next + sync posedge \coresync_clk + update \opc_l_r_opc $0\opc_l_r_opc[0:0] + end + attribute \src "libresoc.v:146526.3-146527.39" + process $proc$libresoc.v:146526$6696 + assign { } { } + assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next + sync posedge \coresync_clk + update \opc_l_s_opc $0\opc_l_s_opc[0:0] + end + attribute \src "libresoc.v:146528.3-146529.39" + process $proc$libresoc.v:146528$6697 + assign { } { } + assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next + sync posedge \coresync_clk + update \rst_l_r_rst $0\rst_l_r_rst[0:0] + end + attribute \src "libresoc.v:146530.3-146531.39" + process $proc$libresoc.v:146530$6698 + assign { } { } + assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next + sync posedge \coresync_clk + update \rst_l_s_rst $0\rst_l_s_rst[0:0] + end + attribute \src "libresoc.v:146532.3-146533.41" + process $proc$libresoc.v:146532$6699 + assign { } { } + assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next + sync posedge \coresync_clk + update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] + end + attribute \src "libresoc.v:146534.3-146535.41" + process $proc$libresoc.v:146534$6700 + assign { } { } + assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next + sync posedge \coresync_clk + update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] + end + attribute \src "libresoc.v:146536.3-146537.37" + process $proc$libresoc.v:146536$6701 + assign { } { } + assign $0\prev_wr_go[1:0] \prev_wr_go$next + sync posedge \coresync_clk + update \prev_wr_go $0\prev_wr_go[1:0] + end + attribute \src "libresoc.v:146538.3-146539.44" + process $proc$libresoc.v:146538$6702 + assign { } { } + assign $0\alu_done_dly[0:0] \alu_logical0_n_valid_o + sync posedge \coresync_clk + update \alu_done_dly $0\alu_done_dly[0:0] + end + attribute \src "libresoc.v:146540.3-146541.24" + process $proc$libresoc.v:146540$6703 + assign { } { } + assign $0\all_rd_dly[0:0] \$9 + sync posedge \coresync_clk + update \all_rd_dly $0\all_rd_dly[0:0] + end + attribute \src "libresoc.v:146623.3-146632.6" + process $proc$libresoc.v:146623$6704 + assign { } { } + assign { } { } + assign $0\req_done[0:0] $1\req_done[0:0] + attribute \src "libresoc.v:146624.5-146624.29" + switch \initial + attribute \src "libresoc.v:146624.9-146624.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + switch \$53 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\req_done[0:0] 1'1 + case + assign $1\req_done[0:0] \$45 + end + sync always + update \req_done $0\req_done[0:0] + end + attribute \src "libresoc.v:146633.3-146641.6" + process $proc$libresoc.v:146633$6705 + assign { } { } + assign { } { } + assign $0\rok_l_s_rdok$next[0:0]$6706 $1\rok_l_s_rdok$next[0:0]$6707 + attribute \src "libresoc.v:146634.5-146634.29" + switch \initial + attribute \src "libresoc.v:146634.9-146634.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rok_l_s_rdok$next[0:0]$6707 1'0 + case + assign $1\rok_l_s_rdok$next[0:0]$6707 \cu_issue_i + end + sync always + update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$6706 + end + attribute \src "libresoc.v:146642.3-146650.6" + process $proc$libresoc.v:146642$6708 + assign { } { } + assign { } { } + assign $0\rok_l_r_rdok$next[0:0]$6709 $1\rok_l_r_rdok$next[0:0]$6710 + attribute \src "libresoc.v:146643.5-146643.29" + switch \initial + attribute \src "libresoc.v:146643.9-146643.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rok_l_r_rdok$next[0:0]$6710 1'1 + case + assign $1\rok_l_r_rdok$next[0:0]$6710 \$63 + end + sync always + update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$6709 + end + attribute \src "libresoc.v:146651.3-146659.6" + process $proc$libresoc.v:146651$6711 + assign { } { } + assign { } { } + assign $0\rst_l_s_rst$next[0:0]$6712 $1\rst_l_s_rst$next[0:0]$6713 + attribute \src "libresoc.v:146652.5-146652.29" + switch \initial + attribute \src "libresoc.v:146652.9-146652.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rst_l_s_rst$next[0:0]$6713 1'0 + case + assign $1\rst_l_s_rst$next[0:0]$6713 \all_rd + end + sync always + update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$6712 + end + attribute \src "libresoc.v:146660.3-146668.6" + process $proc$libresoc.v:146660$6714 + assign { } { } + assign { } { } + assign $0\rst_l_r_rst$next[0:0]$6715 $1\rst_l_r_rst$next[0:0]$6716 + attribute \src "libresoc.v:146661.5-146661.29" + switch \initial + attribute \src "libresoc.v:146661.9-146661.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rst_l_r_rst$next[0:0]$6716 1'1 + case + assign $1\rst_l_r_rst$next[0:0]$6716 \rst_r + end + sync always + update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$6715 + end + attribute \src "libresoc.v:146669.3-146677.6" + process $proc$libresoc.v:146669$6717 + assign { } { } + assign { } { } + assign $0\opc_l_s_opc$next[0:0]$6718 $1\opc_l_s_opc$next[0:0]$6719 + attribute \src "libresoc.v:146670.5-146670.29" + switch \initial + attribute \src "libresoc.v:146670.9-146670.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\opc_l_s_opc$next[0:0]$6719 1'0 + case + assign $1\opc_l_s_opc$next[0:0]$6719 \cu_issue_i + end + sync always + update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$6718 + end + attribute \src "libresoc.v:146678.3-146686.6" + process $proc$libresoc.v:146678$6720 + assign { } { } + assign { } { } + assign $0\opc_l_r_opc$next[0:0]$6721 $1\opc_l_r_opc$next[0:0]$6722 + attribute \src "libresoc.v:146679.5-146679.29" + switch \initial + attribute \src "libresoc.v:146679.9-146679.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\opc_l_r_opc$next[0:0]$6722 1'1 + case + assign $1\opc_l_r_opc$next[0:0]$6722 \req_done + end + sync always + update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$6721 + end + attribute \src "libresoc.v:146687.3-146695.6" + process $proc$libresoc.v:146687$6723 + assign { } { } + assign { } { } + assign $0\src_l_s_src$next[2:0]$6724 $1\src_l_s_src$next[2:0]$6725 + attribute \src "libresoc.v:146688.5-146688.29" + switch \initial + attribute \src "libresoc.v:146688.9-146688.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_l_s_src$next[2:0]$6725 3'000 + case + assign $1\src_l_s_src$next[2:0]$6725 { \cu_issue_i \cu_issue_i \cu_issue_i } + end + sync always + update \src_l_s_src$next $0\src_l_s_src$next[2:0]$6724 + end + attribute \src "libresoc.v:146696.3-146704.6" + process $proc$libresoc.v:146696$6726 + assign { } { } + assign { } { } + assign $0\src_l_r_src$next[2:0]$6727 $1\src_l_r_src$next[2:0]$6728 + attribute \src "libresoc.v:146697.5-146697.29" + switch \initial + attribute \src "libresoc.v:146697.9-146697.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_l_r_src$next[2:0]$6728 3'111 + case + assign $1\src_l_r_src$next[2:0]$6728 \reset_r + end + sync always + update \src_l_r_src$next $0\src_l_r_src$next[2:0]$6727 + end + attribute \src "libresoc.v:146705.3-146713.6" + process $proc$libresoc.v:146705$6729 + assign { } { } + assign { } { } + assign $0\req_l_s_req$next[1:0]$6730 $1\req_l_s_req$next[1:0]$6731 + attribute \src "libresoc.v:146706.5-146706.29" + switch \initial + attribute \src "libresoc.v:146706.9-146706.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\req_l_s_req$next[1:0]$6731 2'00 + case + assign $1\req_l_s_req$next[1:0]$6731 \$65 + end + sync always + update \req_l_s_req$next $0\req_l_s_req$next[1:0]$6730 + end + attribute \src "libresoc.v:146714.3-146722.6" + process $proc$libresoc.v:146714$6732 + assign { } { } + assign { } { } + assign $0\req_l_r_req$next[1:0]$6733 $1\req_l_r_req$next[1:0]$6734 + attribute \src "libresoc.v:146715.5-146715.29" + switch \initial + attribute \src "libresoc.v:146715.9-146715.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\req_l_r_req$next[1:0]$6734 2'11 + case + assign $1\req_l_r_req$next[1:0]$6734 \$67 + end + sync always + update \req_l_r_req$next $0\req_l_r_req$next[1:0]$6733 + end + attribute \src "libresoc.v:146723.3-146761.6" + process $proc$libresoc.v:146723$6735 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\alu_logical0_logical_op__data_len$next[3:0]$6736 $1\alu_logical0_logical_op__data_len$next[3:0]$6754 + assign $0\alu_logical0_logical_op__fn_unit$next[12:0]$6737 $1\alu_logical0_logical_op__fn_unit$next[12:0]$6755 + assign { } { } + assign { } { } + assign $0\alu_logical0_logical_op__input_carry$next[1:0]$6740 $1\alu_logical0_logical_op__input_carry$next[1:0]$6758 + assign $0\alu_logical0_logical_op__insn$next[31:0]$6741 $1\alu_logical0_logical_op__insn$next[31:0]$6759 + assign $0\alu_logical0_logical_op__insn_type$next[6:0]$6742 $1\alu_logical0_logical_op__insn_type$next[6:0]$6760 + assign $0\alu_logical0_logical_op__invert_in$next[0:0]$6743 $1\alu_logical0_logical_op__invert_in$next[0:0]$6761 + assign $0\alu_logical0_logical_op__invert_out$next[0:0]$6744 $1\alu_logical0_logical_op__invert_out$next[0:0]$6762 + assign $0\alu_logical0_logical_op__is_32bit$next[0:0]$6745 $1\alu_logical0_logical_op__is_32bit$next[0:0]$6763 + assign $0\alu_logical0_logical_op__is_signed$next[0:0]$6746 $1\alu_logical0_logical_op__is_signed$next[0:0]$6764 + assign { } { } + assign { } { } + assign $0\alu_logical0_logical_op__output_carry$next[0:0]$6749 $1\alu_logical0_logical_op__output_carry$next[0:0]$6767 + assign { } { } + assign { } { } + assign $0\alu_logical0_logical_op__write_cr0$next[0:0]$6752 $1\alu_logical0_logical_op__write_cr0$next[0:0]$6770 + assign $0\alu_logical0_logical_op__zero_a$next[0:0]$6753 $1\alu_logical0_logical_op__zero_a$next[0:0]$6771 + assign $0\alu_logical0_logical_op__imm_data__data$next[63:0]$6738 $2\alu_logical0_logical_op__imm_data__data$next[63:0]$6772 + assign $0\alu_logical0_logical_op__imm_data__ok$next[0:0]$6739 $2\alu_logical0_logical_op__imm_data__ok$next[0:0]$6773 + assign $0\alu_logical0_logical_op__oe__oe$next[0:0]$6747 $2\alu_logical0_logical_op__oe__oe$next[0:0]$6774 + assign $0\alu_logical0_logical_op__oe__ok$next[0:0]$6748 $2\alu_logical0_logical_op__oe__ok$next[0:0]$6775 + assign $0\alu_logical0_logical_op__rc__ok$next[0:0]$6750 $2\alu_logical0_logical_op__rc__ok$next[0:0]$6776 + assign $0\alu_logical0_logical_op__rc__rc$next[0:0]$6751 $2\alu_logical0_logical_op__rc__rc$next[0:0]$6777 + attribute \src "libresoc.v:146724.5-146724.29" + switch \initial + attribute \src "libresoc.v:146724.9-146724.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\alu_logical0_logical_op__insn$next[31:0]$6759 $1\alu_logical0_logical_op__data_len$next[3:0]$6754 $1\alu_logical0_logical_op__is_signed$next[0:0]$6764 $1\alu_logical0_logical_op__is_32bit$next[0:0]$6763 $1\alu_logical0_logical_op__output_carry$next[0:0]$6767 $1\alu_logical0_logical_op__write_cr0$next[0:0]$6770 $1\alu_logical0_logical_op__invert_out$next[0:0]$6762 $1\alu_logical0_logical_op__input_carry$next[1:0]$6758 $1\alu_logical0_logical_op__zero_a$next[0:0]$6771 $1\alu_logical0_logical_op__invert_in$next[0:0]$6761 $1\alu_logical0_logical_op__oe__ok$next[0:0]$6766 $1\alu_logical0_logical_op__oe__oe$next[0:0]$6765 $1\alu_logical0_logical_op__rc__ok$next[0:0]$6768 $1\alu_logical0_logical_op__rc__rc$next[0:0]$6769 $1\alu_logical0_logical_op__imm_data__ok$next[0:0]$6757 $1\alu_logical0_logical_op__imm_data__data$next[63:0]$6756 $1\alu_logical0_logical_op__fn_unit$next[12:0]$6755 $1\alu_logical0_logical_op__insn_type$next[6:0]$6760 } { \oper_i_alu_logical0__insn \oper_i_alu_logical0__data_len \oper_i_alu_logical0__is_signed \oper_i_alu_logical0__is_32bit \oper_i_alu_logical0__output_carry \oper_i_alu_logical0__write_cr0 \oper_i_alu_logical0__invert_out \oper_i_alu_logical0__input_carry \oper_i_alu_logical0__zero_a \oper_i_alu_logical0__invert_in \oper_i_alu_logical0__oe__ok \oper_i_alu_logical0__oe__oe \oper_i_alu_logical0__rc__ok \oper_i_alu_logical0__rc__rc \oper_i_alu_logical0__imm_data__ok \oper_i_alu_logical0__imm_data__data \oper_i_alu_logical0__fn_unit \oper_i_alu_logical0__insn_type } + case + assign $1\alu_logical0_logical_op__data_len$next[3:0]$6754 \alu_logical0_logical_op__data_len + assign $1\alu_logical0_logical_op__fn_unit$next[12:0]$6755 \alu_logical0_logical_op__fn_unit + assign $1\alu_logical0_logical_op__imm_data__data$next[63:0]$6756 \alu_logical0_logical_op__imm_data__data + assign $1\alu_logical0_logical_op__imm_data__ok$next[0:0]$6757 \alu_logical0_logical_op__imm_data__ok + assign $1\alu_logical0_logical_op__input_carry$next[1:0]$6758 \alu_logical0_logical_op__input_carry + assign $1\alu_logical0_logical_op__insn$next[31:0]$6759 \alu_logical0_logical_op__insn + assign $1\alu_logical0_logical_op__insn_type$next[6:0]$6760 \alu_logical0_logical_op__insn_type + assign $1\alu_logical0_logical_op__invert_in$next[0:0]$6761 \alu_logical0_logical_op__invert_in + assign $1\alu_logical0_logical_op__invert_out$next[0:0]$6762 \alu_logical0_logical_op__invert_out + assign $1\alu_logical0_logical_op__is_32bit$next[0:0]$6763 \alu_logical0_logical_op__is_32bit + assign $1\alu_logical0_logical_op__is_signed$next[0:0]$6764 \alu_logical0_logical_op__is_signed + assign $1\alu_logical0_logical_op__oe__oe$next[0:0]$6765 \alu_logical0_logical_op__oe__oe + assign $1\alu_logical0_logical_op__oe__ok$next[0:0]$6766 \alu_logical0_logical_op__oe__ok + assign $1\alu_logical0_logical_op__output_carry$next[0:0]$6767 \alu_logical0_logical_op__output_carry + assign $1\alu_logical0_logical_op__rc__ok$next[0:0]$6768 \alu_logical0_logical_op__rc__ok + assign $1\alu_logical0_logical_op__rc__rc$next[0:0]$6769 \alu_logical0_logical_op__rc__rc + assign $1\alu_logical0_logical_op__write_cr0$next[0:0]$6770 \alu_logical0_logical_op__write_cr0 + assign $1\alu_logical0_logical_op__zero_a$next[0:0]$6771 \alu_logical0_logical_op__zero_a + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $2\alu_logical0_logical_op__imm_data__data$next[63:0]$6772 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\alu_logical0_logical_op__imm_data__ok$next[0:0]$6773 1'0 + assign $2\alu_logical0_logical_op__rc__rc$next[0:0]$6777 1'0 + assign $2\alu_logical0_logical_op__rc__ok$next[0:0]$6776 1'0 + assign $2\alu_logical0_logical_op__oe__oe$next[0:0]$6774 1'0 + assign $2\alu_logical0_logical_op__oe__ok$next[0:0]$6775 1'0 + case + assign $2\alu_logical0_logical_op__imm_data__data$next[63:0]$6772 $1\alu_logical0_logical_op__imm_data__data$next[63:0]$6756 + assign $2\alu_logical0_logical_op__imm_data__ok$next[0:0]$6773 $1\alu_logical0_logical_op__imm_data__ok$next[0:0]$6757 + assign $2\alu_logical0_logical_op__oe__oe$next[0:0]$6774 $1\alu_logical0_logical_op__oe__oe$next[0:0]$6765 + assign $2\alu_logical0_logical_op__oe__ok$next[0:0]$6775 $1\alu_logical0_logical_op__oe__ok$next[0:0]$6766 + assign $2\alu_logical0_logical_op__rc__ok$next[0:0]$6776 $1\alu_logical0_logical_op__rc__ok$next[0:0]$6768 + assign $2\alu_logical0_logical_op__rc__rc$next[0:0]$6777 $1\alu_logical0_logical_op__rc__rc$next[0:0]$6769 + end + sync always + update \alu_logical0_logical_op__data_len$next $0\alu_logical0_logical_op__data_len$next[3:0]$6736 + update \alu_logical0_logical_op__fn_unit$next $0\alu_logical0_logical_op__fn_unit$next[12:0]$6737 + update \alu_logical0_logical_op__imm_data__data$next $0\alu_logical0_logical_op__imm_data__data$next[63:0]$6738 + update \alu_logical0_logical_op__imm_data__ok$next $0\alu_logical0_logical_op__imm_data__ok$next[0:0]$6739 + update \alu_logical0_logical_op__input_carry$next $0\alu_logical0_logical_op__input_carry$next[1:0]$6740 + update \alu_logical0_logical_op__insn$next $0\alu_logical0_logical_op__insn$next[31:0]$6741 + update \alu_logical0_logical_op__insn_type$next $0\alu_logical0_logical_op__insn_type$next[6:0]$6742 + update \alu_logical0_logical_op__invert_in$next $0\alu_logical0_logical_op__invert_in$next[0:0]$6743 + update \alu_logical0_logical_op__invert_out$next $0\alu_logical0_logical_op__invert_out$next[0:0]$6744 + update \alu_logical0_logical_op__is_32bit$next $0\alu_logical0_logical_op__is_32bit$next[0:0]$6745 + update \alu_logical0_logical_op__is_signed$next $0\alu_logical0_logical_op__is_signed$next[0:0]$6746 + update \alu_logical0_logical_op__oe__oe$next $0\alu_logical0_logical_op__oe__oe$next[0:0]$6747 + update \alu_logical0_logical_op__oe__ok$next $0\alu_logical0_logical_op__oe__ok$next[0:0]$6748 + update \alu_logical0_logical_op__output_carry$next $0\alu_logical0_logical_op__output_carry$next[0:0]$6749 + update \alu_logical0_logical_op__rc__ok$next $0\alu_logical0_logical_op__rc__ok$next[0:0]$6750 + update \alu_logical0_logical_op__rc__rc$next $0\alu_logical0_logical_op__rc__rc$next[0:0]$6751 + update \alu_logical0_logical_op__write_cr0$next $0\alu_logical0_logical_op__write_cr0$next[0:0]$6752 + update \alu_logical0_logical_op__zero_a$next $0\alu_logical0_logical_op__zero_a$next[0:0]$6753 + end + attribute \src "libresoc.v:146762.3-146783.6" + process $proc$libresoc.v:146762$6778 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r0__o$next[63:0]$6779 $2\data_r0__o$next[63:0]$6783 + assign { } { } + assign $0\data_r0__o_ok$next[0:0]$6780 $3\data_r0__o_ok$next[0:0]$6785 + attribute \src "libresoc.v:146763.5-146763.29" + switch \initial + attribute \src "libresoc.v:146763.9-146763.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r0__o_ok$next[0:0]$6782 $1\data_r0__o$next[63:0]$6781 } { \o_ok \alu_logical0_o } + case + assign $1\data_r0__o$next[63:0]$6781 \data_r0__o + assign $1\data_r0__o_ok$next[0:0]$6782 \data_r0__o_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r0__o_ok$next[0:0]$6784 $2\data_r0__o$next[63:0]$6783 } 65'00000000000000000000000000000000000000000000000000000000000000000 + case + assign $2\data_r0__o$next[63:0]$6783 $1\data_r0__o$next[63:0]$6781 + assign $2\data_r0__o_ok$next[0:0]$6784 $1\data_r0__o_ok$next[0:0]$6782 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r0__o_ok$next[0:0]$6785 1'0 + case + assign $3\data_r0__o_ok$next[0:0]$6785 $2\data_r0__o_ok$next[0:0]$6784 + end + sync always + update \data_r0__o$next $0\data_r0__o$next[63:0]$6779 + update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$6780 + end + attribute \src "libresoc.v:146784.3-146805.6" + process $proc$libresoc.v:146784$6786 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r1__cr_a$next[3:0]$6787 $2\data_r1__cr_a$next[3:0]$6791 + assign { } { } + assign $0\data_r1__cr_a_ok$next[0:0]$6788 $3\data_r1__cr_a_ok$next[0:0]$6793 + attribute \src "libresoc.v:146785.5-146785.29" + switch \initial + attribute \src "libresoc.v:146785.9-146785.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r1__cr_a_ok$next[0:0]$6790 $1\data_r1__cr_a$next[3:0]$6789 } { \cr_a_ok \alu_logical0_cr_a } + case + assign $1\data_r1__cr_a$next[3:0]$6789 \data_r1__cr_a + assign $1\data_r1__cr_a_ok$next[0:0]$6790 \data_r1__cr_a_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r1__cr_a_ok$next[0:0]$6792 $2\data_r1__cr_a$next[3:0]$6791 } 5'00000 + case + assign $2\data_r1__cr_a$next[3:0]$6791 $1\data_r1__cr_a$next[3:0]$6789 + assign $2\data_r1__cr_a_ok$next[0:0]$6792 $1\data_r1__cr_a_ok$next[0:0]$6790 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r1__cr_a_ok$next[0:0]$6793 1'0 + case + assign $3\data_r1__cr_a_ok$next[0:0]$6793 $2\data_r1__cr_a_ok$next[0:0]$6792 + end + sync always + update \data_r1__cr_a$next $0\data_r1__cr_a$next[3:0]$6787 + update \data_r1__cr_a_ok$next $0\data_r1__cr_a_ok$next[0:0]$6788 + end + attribute \src "libresoc.v:146806.3-146815.6" + process $proc$libresoc.v:146806$6794 + assign { } { } + assign { } { } + assign $0\src_r0$next[63:0]$6795 $1\src_r0$next[63:0]$6796 + attribute \src "libresoc.v:146807.5-146807.29" + switch \initial + attribute \src "libresoc.v:146807.9-146807.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" + switch \src_sel + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r0$next[63:0]$6796 \src_or_imm + case + assign $1\src_r0$next[63:0]$6796 \src_r0 + end + sync always + update \src_r0$next $0\src_r0$next[63:0]$6795 + end + attribute \src "libresoc.v:146816.3-146825.6" + process $proc$libresoc.v:146816$6797 + assign { } { } + assign { } { } + assign $0\src_r1$next[63:0]$6798 $1\src_r1$next[63:0]$6799 + attribute \src "libresoc.v:146817.5-146817.29" + switch \initial + attribute \src "libresoc.v:146817.9-146817.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" + switch \src_sel$77 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r1$next[63:0]$6799 \src_or_imm$80 + case + assign $1\src_r1$next[63:0]$6799 \src_r1 + end + sync always + update \src_r1$next $0\src_r1$next[63:0]$6798 + end + attribute \src "libresoc.v:146826.3-146835.6" + process $proc$libresoc.v:146826$6800 + assign { } { } + assign { } { } + assign $0\src_r2$next[0:0]$6801 $1\src_r2$next[0:0]$6802 + attribute \src "libresoc.v:146827.5-146827.29" + switch \initial + attribute \src "libresoc.v:146827.9-146827.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" + switch \src_l_q_src [2] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r2$next[0:0]$6802 \src3_i + case + assign $1\src_r2$next[0:0]$6802 \src_r2 + end + sync always + update \src_r2$next $0\src_r2$next[0:0]$6801 + end + attribute \src "libresoc.v:146836.3-146844.6" + process $proc$libresoc.v:146836$6803 + assign { } { } + assign { } { } + assign $0\alui_l_r_alui$next[0:0]$6804 $1\alui_l_r_alui$next[0:0]$6805 + attribute \src "libresoc.v:146837.5-146837.29" + switch \initial + attribute \src "libresoc.v:146837.9-146837.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\alui_l_r_alui$next[0:0]$6805 1'1 + case + assign $1\alui_l_r_alui$next[0:0]$6805 \$89 + end + sync always + update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$6804 + end + attribute \src "libresoc.v:146845.3-146853.6" + process $proc$libresoc.v:146845$6806 + assign { } { } + assign { } { } + assign $0\alu_l_r_alu$next[0:0]$6807 $1\alu_l_r_alu$next[0:0]$6808 + attribute \src "libresoc.v:146846.5-146846.29" + switch \initial + attribute \src "libresoc.v:146846.9-146846.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\alu_l_r_alu$next[0:0]$6808 1'1 + case + assign $1\alu_l_r_alu$next[0:0]$6808 \$91 + end + sync always + update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$6807 + end + attribute \src "libresoc.v:146854.3-146863.6" + process $proc$libresoc.v:146854$6809 + assign { } { } + assign { } { } + assign $0\dest1_o[63:0] $1\dest1_o[63:0] + attribute \src "libresoc.v:146855.5-146855.29" + switch \initial + attribute \src "libresoc.v:146855.9-146855.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$113 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest1_o[63:0] \data_r0__o + case + assign $1\dest1_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \dest1_o $0\dest1_o[63:0] + end + attribute \src "libresoc.v:146864.3-146873.6" + process $proc$libresoc.v:146864$6810 + assign { } { } + assign { } { } + assign $0\dest2_o[3:0] $1\dest2_o[3:0] + attribute \src "libresoc.v:146865.5-146865.29" + switch \initial + attribute \src "libresoc.v:146865.9-146865.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$115 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest2_o[3:0] \data_r1__cr_a + case + assign $1\dest2_o[3:0] 4'0000 + end + sync always + update \dest2_o $0\dest2_o[3:0] + end + attribute \src "libresoc.v:146874.3-146882.6" + process $proc$libresoc.v:146874$6811 + assign { } { } + assign { } { } + assign $0\prev_wr_go$next[1:0]$6812 $1\prev_wr_go$next[1:0]$6813 + attribute \src "libresoc.v:146875.5-146875.29" + switch \initial + attribute \src "libresoc.v:146875.9-146875.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\prev_wr_go$next[1:0]$6813 2'00 + case + assign $1\prev_wr_go$next[1:0]$6813 \$19 + end + sync always + update \prev_wr_go$next $0\prev_wr_go$next[1:0]$6812 + end + connect \$9 $and$libresoc.v:146405$6607_Y + connect \$99 $and$libresoc.v:146406$6608_Y + connect \$101 $not$libresoc.v:146407$6609_Y + connect \$103 $and$libresoc.v:146408$6610_Y + connect \$105 $and$libresoc.v:146409$6611_Y + connect \$107 $and$libresoc.v:146410$6612_Y + connect \$109 $and$libresoc.v:146411$6613_Y + connect \$111 $and$libresoc.v:146412$6614_Y + connect \$113 $and$libresoc.v:146413$6615_Y + connect \$115 $and$libresoc.v:146414$6616_Y + connect \$11 $not$libresoc.v:146415$6617_Y + connect \$13 $and$libresoc.v:146416$6618_Y + connect \$15 $not$libresoc.v:146417$6619_Y + connect \$17 $and$libresoc.v:146418$6620_Y + connect \$1 $and$libresoc.v:146419$6621_Y + connect \$19 $and$libresoc.v:146420$6622_Y + connect \$23 $not$libresoc.v:146421$6623_Y + connect \$25 $and$libresoc.v:146422$6624_Y + connect \$22 $reduce_or$libresoc.v:146423$6625_Y + connect \$21 $not$libresoc.v:146424$6626_Y + connect \$29 $and$libresoc.v:146425$6627_Y + connect \$31 $reduce_or$libresoc.v:146426$6628_Y + connect \$33 $reduce_or$libresoc.v:146427$6629_Y + connect \$35 $or$libresoc.v:146428$6630_Y + connect \$37 $not$libresoc.v:146429$6631_Y + connect \$39 $and$libresoc.v:146430$6632_Y + connect \$41 $and$libresoc.v:146431$6633_Y + connect \$43 $eq$libresoc.v:146432$6634_Y + connect \$45 $and$libresoc.v:146433$6635_Y + connect \$47 $eq$libresoc.v:146434$6636_Y + connect \$4 $not$libresoc.v:146435$6637_Y + connect \$49 $and$libresoc.v:146436$6638_Y + connect \$51 $and$libresoc.v:146437$6639_Y + connect \$53 $and$libresoc.v:146438$6640_Y + connect \$55 $or$libresoc.v:146439$6641_Y + connect \$57 $or$libresoc.v:146440$6642_Y + connect \$59 $or$libresoc.v:146441$6643_Y + connect \$61 $or$libresoc.v:146442$6644_Y + connect \$63 $and$libresoc.v:146443$6645_Y + connect \$65 $and$libresoc.v:146444$6646_Y + connect \$67 $or$libresoc.v:146445$6647_Y + connect \$6 $or$libresoc.v:146446$6648_Y + connect \$69 $and$libresoc.v:146447$6649_Y + connect \$71 $and$libresoc.v:146448$6650_Y + connect \$73 $ternary$libresoc.v:146449$6651_Y + connect \$75 $ternary$libresoc.v:146450$6652_Y + connect \$78 $ternary$libresoc.v:146451$6653_Y + connect \$3 $reduce_and$libresoc.v:146452$6654_Y + connect \$81 $ternary$libresoc.v:146453$6655_Y + connect \$83 $ternary$libresoc.v:146454$6656_Y + connect \$85 $ternary$libresoc.v:146455$6657_Y + connect \$87 $ternary$libresoc.v:146456$6658_Y + connect \$89 $and$libresoc.v:146457$6659_Y + connect \$91 $and$libresoc.v:146458$6660_Y + connect \$93 $and$libresoc.v:146459$6661_Y + connect \$95 $not$libresoc.v:146460$6662_Y + connect \$97 $not$libresoc.v:146461$6663_Y + connect \cu_go_die_i 1'0 + connect \cu_shadown_i 1'1 + connect \cu_wr__rel_o \$111 + connect \cu_rd__rel_o \$103 + connect \cu_busy_o \opc_l_q_opc + connect \alu_l_s_alu \all_rd_pulse + connect \alu_logical0_n_ready_i \alu_l_q_alu + connect \alui_l_s_alui \all_rd_pulse + connect \alu_logical0_p_valid_i \alui_l_q_alui + connect \alu_logical0_xer_so \$87 + connect \alu_logical0_rb \$85 + connect \alu_logical0_ra \$83 + connect \src_or_imm$80 \$81 + connect \src_sel$77 \$78 + connect \src_or_imm \$75 + connect \src_sel \$73 + connect \cu_wrmask_o { \$71 \$69 } + connect \reset_r \$61 + connect \reset_w \$59 + connect \rst_r \$57 + connect \reset \$55 + connect \wr_any \$35 + connect \cu_done_o \$29 + connect \alu_pulsem { \alu_pulse \alu_pulse } + connect \alu_pulse \alu_done_rise + connect \alu_done_rise \$17 + connect \alu_done_dly$next \alu_done + connect \alu_done \alu_logical0_n_valid_o + connect \all_rd_pulse \all_rd_rise + connect \all_rd_rise \$13 + connect \all_rd_dly$next \all_rd + connect \all_rd \$9 +end +attribute \src "libresoc.v:146919.1-148296.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe1" +attribute \generator "nMigen" +module \logical_pipe1 + attribute \src "libresoc.v:148235.3-148253.6" + wire width 4 $0\cr_a$next[3:0]$6939 + attribute \src "libresoc.v:147995.3-147996.25" + wire width 4 $0\cr_a[3:0] + attribute \src "libresoc.v:148235.3-148253.6" + wire $0\cr_a_ok$next[0:0]$6940 + attribute \src "libresoc.v:147997.3-147998.31" + wire $0\cr_a_ok[0:0] + attribute \src "libresoc.v:146920.7-146920.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:148174.3-148215.6" + wire width 4 $0\logical_op__data_len$next[3:0]$6890 + attribute \src "libresoc.v:148035.3-148036.57" + wire width 4 $0\logical_op__data_len[3:0] + attribute \src "libresoc.v:148174.3-148215.6" + wire width 13 $0\logical_op__fn_unit$next[12:0]$6891 + attribute \src "libresoc.v:148005.3-148006.55" + wire width 13 $0\logical_op__fn_unit[12:0] + attribute \src "libresoc.v:148174.3-148215.6" + wire width 64 $0\logical_op__imm_data__data$next[63:0]$6892 + attribute \src "libresoc.v:148007.3-148008.69" + wire width 64 $0\logical_op__imm_data__data[63:0] + attribute \src "libresoc.v:148174.3-148215.6" + wire $0\logical_op__imm_data__ok$next[0:0]$6893 + attribute \src "libresoc.v:148009.3-148010.65" + wire $0\logical_op__imm_data__ok[0:0] + attribute \src "libresoc.v:148174.3-148215.6" + wire width 2 $0\logical_op__input_carry$next[1:0]$6894 + attribute \src "libresoc.v:148023.3-148024.63" + wire width 2 $0\logical_op__input_carry[1:0] + attribute \src "libresoc.v:148174.3-148215.6" + wire width 32 $0\logical_op__insn$next[31:0]$6895 + attribute \src "libresoc.v:148037.3-148038.49" + wire width 32 $0\logical_op__insn[31:0] + attribute \src "libresoc.v:148174.3-148215.6" + wire width 7 $0\logical_op__insn_type$next[6:0]$6896 + attribute \src "libresoc.v:148003.3-148004.59" + wire width 7 $0\logical_op__insn_type[6:0] + attribute \src "libresoc.v:148174.3-148215.6" + wire $0\logical_op__invert_in$next[0:0]$6897 + attribute \src "libresoc.v:148019.3-148020.59" + wire $0\logical_op__invert_in[0:0] + attribute \src "libresoc.v:148174.3-148215.6" + wire $0\logical_op__invert_out$next[0:0]$6898 + attribute \src "libresoc.v:148025.3-148026.61" + wire $0\logical_op__invert_out[0:0] + attribute \src "libresoc.v:148174.3-148215.6" + wire $0\logical_op__is_32bit$next[0:0]$6899 + attribute \src "libresoc.v:148031.3-148032.57" + wire $0\logical_op__is_32bit[0:0] + attribute \src "libresoc.v:148174.3-148215.6" + wire $0\logical_op__is_signed$next[0:0]$6900 + attribute \src "libresoc.v:148033.3-148034.59" + wire $0\logical_op__is_signed[0:0] + attribute \src "libresoc.v:148174.3-148215.6" + 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attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \input_logical_op__insn_type$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__invert_in$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__invert_out$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__is_32bit$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__is_signed$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__oe__oe$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__oe__ok$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__output_carry$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__rc__ok$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__rc__rc$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__write_cr0$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__zero_a$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \input_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \input_muxid$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_ra$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_rb$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \input_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \input_xer_so$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 21 \logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 48 \logical_op__data_len$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \logical_op__data_len$83 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \logical_op__data_len$next + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 output 6 \logical_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 input 33 \logical_op__fn_unit$3 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \logical_op__fn_unit$68 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \logical_op__fn_unit$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 7 \logical_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 34 \logical_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \logical_op__imm_data__data$69 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \logical_op__imm_data__data$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 8 \logical_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 35 \logical_op__imm_data__ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__imm_data__ok$70 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__imm_data__ok$next + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 15 \logical_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 42 \logical_op__input_carry$12 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \logical_op__input_carry$77 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \logical_op__input_carry$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 22 \logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 49 \logical_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \logical_op__insn$84 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \logical_op__insn$next + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 5 \logical_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 32 \logical_op__insn_type$2 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \logical_op__insn_type$67 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \logical_op__insn_type$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 13 \logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 40 \logical_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_in$75 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_in$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 16 \logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 43 \logical_op__invert_out$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_out$78 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_out$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 19 \logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 46 \logical_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_32bit$81 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_32bit$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 20 \logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 47 \logical_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_signed$82 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_signed$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 11 \logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__oe$73 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 38 \logical_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__oe$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 12 \logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__ok$74 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 39 \logical_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 18 \logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 45 \logical_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__output_carry$80 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__output_carry$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 10 \logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 37 \logical_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__ok$72 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 9 \logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 36 \logical_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__rc$71 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__rc$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 17 \logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 44 \logical_op__write_cr0$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__write_cr0$79 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__write_cr0$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 14 \logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 41 \logical_op__zero_a$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__zero_a$76 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__zero_a$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \main_logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \main_logical_op__data_len$60 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \main_logical_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \main_logical_op__fn_unit$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \main_logical_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \main_logical_op__imm_data__data$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_logical_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_logical_op__imm_data__ok$47 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \main_logical_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \main_logical_op__input_carry$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \main_logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \main_logical_op__insn$61 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \main_logical_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \main_logical_op__insn_type$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_logical_op__invert_in$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_logical_op__invert_out$55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_logical_op__is_32bit$58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_logical_op__is_signed$59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_logical_op__oe__oe$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_logical_op__oe__ok$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_logical_op__output_carry$57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_logical_op__rc__ok$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_logical_op__rc__rc$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_logical_op__write_cr0$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_logical_op__zero_a$53 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \main_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \main_muxid$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \main_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \main_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \main_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \main_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \main_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \main_xer_so$62 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 output 4 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 input 31 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid$66 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + wire \n_i_rdy_data + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire input 3 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire output 2 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 23 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \o$85 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \o$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 24 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \o_ok$86 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \o_ok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" + wire output 30 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" + wire input 29 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" + wire \p_valid_i$63 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" + wire \p_valid_i_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire \r_busy$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 50 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 51 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 27 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 52 \xer_so$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so$91 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 28 \xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so_ok$92 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so_ok$93 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so_ok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" + cell $and $and$libresoc.v:147990$6855 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i$63 + connect \B \p_ready_o + connect \Y $and$libresoc.v:147990$6855_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:148043.14-148088.4" + cell \input$50 \input + connect \logical_op__data_len \input_logical_op__data_len + connect \logical_op__data_len$18 \input_logical_op__data_len$38 + connect \logical_op__fn_unit \input_logical_op__fn_unit + connect \logical_op__fn_unit$3 \input_logical_op__fn_unit$23 + connect \logical_op__imm_data__data \input_logical_op__imm_data__data + connect \logical_op__imm_data__data$4 \input_logical_op__imm_data__data$24 + connect \logical_op__imm_data__ok \input_logical_op__imm_data__ok + connect \logical_op__imm_data__ok$5 \input_logical_op__imm_data__ok$25 + connect \logical_op__input_carry \input_logical_op__input_carry + connect \logical_op__input_carry$12 \input_logical_op__input_carry$32 + connect \logical_op__insn \input_logical_op__insn + connect \logical_op__insn$19 \input_logical_op__insn$39 + connect \logical_op__insn_type \input_logical_op__insn_type + connect \logical_op__insn_type$2 \input_logical_op__insn_type$22 + connect \logical_op__invert_in \input_logical_op__invert_in + connect \logical_op__invert_in$10 \input_logical_op__invert_in$30 + connect \logical_op__invert_out \input_logical_op__invert_out + connect \logical_op__invert_out$13 \input_logical_op__invert_out$33 + connect \logical_op__is_32bit \input_logical_op__is_32bit + connect \logical_op__is_32bit$16 \input_logical_op__is_32bit$36 + connect \logical_op__is_signed \input_logical_op__is_signed + connect \logical_op__is_signed$17 \input_logical_op__is_signed$37 + connect \logical_op__oe__oe \input_logical_op__oe__oe + connect \logical_op__oe__oe$8 \input_logical_op__oe__oe$28 + connect \logical_op__oe__ok \input_logical_op__oe__ok + connect \logical_op__oe__ok$9 \input_logical_op__oe__ok$29 + connect \logical_op__output_carry \input_logical_op__output_carry + connect \logical_op__output_carry$15 \input_logical_op__output_carry$35 + connect \logical_op__rc__ok \input_logical_op__rc__ok + connect \logical_op__rc__ok$7 \input_logical_op__rc__ok$27 + connect \logical_op__rc__rc \input_logical_op__rc__rc + connect \logical_op__rc__rc$6 \input_logical_op__rc__rc$26 + connect \logical_op__write_cr0 \input_logical_op__write_cr0 + connect \logical_op__write_cr0$14 \input_logical_op__write_cr0$34 + connect \logical_op__zero_a \input_logical_op__zero_a + connect \logical_op__zero_a$11 \input_logical_op__zero_a$31 + connect \muxid \input_muxid + connect \muxid$1 \input_muxid$21 + connect \ra \input_ra + connect \ra$20 \input_ra$40 + connect \rb \input_rb + connect \rb$21 \input_rb$41 + connect \xer_so \input_xer_so + connect \xer_so$22 \input_xer_so$42 + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:148089.13-148134.4" + cell \main$51 \main + connect \logical_op__data_len \main_logical_op__data_len + connect \logical_op__data_len$18 \main_logical_op__data_len$60 + connect \logical_op__fn_unit \main_logical_op__fn_unit + connect \logical_op__fn_unit$3 \main_logical_op__fn_unit$45 + connect \logical_op__imm_data__data \main_logical_op__imm_data__data + connect \logical_op__imm_data__data$4 \main_logical_op__imm_data__data$46 + connect \logical_op__imm_data__ok \main_logical_op__imm_data__ok + connect \logical_op__imm_data__ok$5 \main_logical_op__imm_data__ok$47 + connect \logical_op__input_carry \main_logical_op__input_carry + connect \logical_op__input_carry$12 \main_logical_op__input_carry$54 + connect \logical_op__insn \main_logical_op__insn + connect \logical_op__insn$19 \main_logical_op__insn$61 + connect \logical_op__insn_type \main_logical_op__insn_type + connect \logical_op__insn_type$2 \main_logical_op__insn_type$44 + connect \logical_op__invert_in \main_logical_op__invert_in + connect \logical_op__invert_in$10 \main_logical_op__invert_in$52 + connect \logical_op__invert_out \main_logical_op__invert_out + connect \logical_op__invert_out$13 \main_logical_op__invert_out$55 + connect \logical_op__is_32bit \main_logical_op__is_32bit + connect \logical_op__is_32bit$16 \main_logical_op__is_32bit$58 + connect \logical_op__is_signed \main_logical_op__is_signed + connect \logical_op__is_signed$17 \main_logical_op__is_signed$59 + connect \logical_op__oe__oe \main_logical_op__oe__oe + connect \logical_op__oe__oe$8 \main_logical_op__oe__oe$50 + connect \logical_op__oe__ok \main_logical_op__oe__ok + connect \logical_op__oe__ok$9 \main_logical_op__oe__ok$51 + connect \logical_op__output_carry \main_logical_op__output_carry + connect \logical_op__output_carry$15 \main_logical_op__output_carry$57 + connect \logical_op__rc__ok \main_logical_op__rc__ok + connect \logical_op__rc__ok$7 \main_logical_op__rc__ok$49 + connect \logical_op__rc__rc \main_logical_op__rc__rc + connect \logical_op__rc__rc$6 \main_logical_op__rc__rc$48 + connect \logical_op__write_cr0 \main_logical_op__write_cr0 + connect \logical_op__write_cr0$14 \main_logical_op__write_cr0$56 + connect \logical_op__zero_a \main_logical_op__zero_a + connect \logical_op__zero_a$11 \main_logical_op__zero_a$53 + connect \muxid \main_muxid + connect \muxid$1 \main_muxid$43 + connect \o \main_o + connect \o_ok \main_o_ok + connect \ra \main_ra + connect \rb \main_rb + connect \xer_so \main_xer_so + connect \xer_so$20 \main_xer_so$62 + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:148135.10-148138.4" + cell \n$49 \n + connect \n_ready_i \n_ready_i + connect \n_valid_o \n_valid_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:148139.10-148142.4" + cell \p$48 \p + connect \p_ready_o \p_ready_o + connect \p_valid_i \p_valid_i + end + attribute \src "libresoc.v:146920.7-146920.20" + process $proc$libresoc.v:146920$6950 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:146929.13-146929.24" + process $proc$libresoc.v:146929$6951 + assign { } { } + assign $1\cr_a[3:0] 4'0000 + sync always + sync init + update \cr_a $1\cr_a[3:0] + end + attribute \src "libresoc.v:146938.7-146938.21" + process $proc$libresoc.v:146938$6952 + assign { } { } + assign $1\cr_a_ok[0:0] 1'0 + sync always + sync init + update \cr_a_ok $1\cr_a_ok[0:0] + end + attribute \src "libresoc.v:147219.13-147219.40" + process $proc$libresoc.v:147219$6953 + assign { } { } + assign $1\logical_op__data_len[3:0] 4'0000 + sync always + sync init + update \logical_op__data_len $1\logical_op__data_len[3:0] + end + attribute \src "libresoc.v:147242.14-147242.44" + process $proc$libresoc.v:147242$6954 + assign { } { } + assign $1\logical_op__fn_unit[12:0] 13'0000000000000 + sync always + sync init + update \logical_op__fn_unit $1\logical_op__fn_unit[12:0] + end + attribute \src "libresoc.v:147279.14-147279.63" + process $proc$libresoc.v:147279$6955 + assign { } { } + assign $1\logical_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \logical_op__imm_data__data $1\logical_op__imm_data__data[63:0] + end + attribute \src "libresoc.v:147288.7-147288.38" + process $proc$libresoc.v:147288$6956 + assign { } { } + assign $1\logical_op__imm_data__ok[0:0] 1'0 + sync always + sync init + update \logical_op__imm_data__ok $1\logical_op__imm_data__ok[0:0] + end + attribute \src "libresoc.v:147301.13-147301.43" + process $proc$libresoc.v:147301$6957 + assign { } { } + assign $1\logical_op__input_carry[1:0] 2'00 + sync always + sync init + update \logical_op__input_carry $1\logical_op__input_carry[1:0] + end + attribute \src "libresoc.v:147318.14-147318.38" + process $proc$libresoc.v:147318$6958 + assign { } { } + assign $1\logical_op__insn[31:0] 0 + sync always + sync init + update \logical_op__insn $1\logical_op__insn[31:0] + end + attribute \src "libresoc.v:147401.13-147401.42" + process $proc$libresoc.v:147401$6959 + assign { } { } + assign $1\logical_op__insn_type[6:0] 7'0000000 + sync always + sync init + update \logical_op__insn_type $1\logical_op__insn_type[6:0] + end + attribute \src "libresoc.v:147558.7-147558.35" + process $proc$libresoc.v:147558$6960 + assign { } { } + assign $1\logical_op__invert_in[0:0] 1'0 + sync always + sync init + update \logical_op__invert_in $1\logical_op__invert_in[0:0] + end + attribute \src "libresoc.v:147567.7-147567.36" + process $proc$libresoc.v:147567$6961 + assign { } { } + assign $1\logical_op__invert_out[0:0] 1'0 + sync always + sync init + update \logical_op__invert_out $1\logical_op__invert_out[0:0] + end + attribute \src "libresoc.v:147576.7-147576.34" + process $proc$libresoc.v:147576$6962 + assign { } { } + assign $1\logical_op__is_32bit[0:0] 1'0 + sync always + sync init + update \logical_op__is_32bit $1\logical_op__is_32bit[0:0] + end + attribute \src "libresoc.v:147585.7-147585.35" + process $proc$libresoc.v:147585$6963 + assign { } { } + assign $1\logical_op__is_signed[0:0] 1'0 + sync always + sync init + update \logical_op__is_signed $1\logical_op__is_signed[0:0] + end + attribute \src "libresoc.v:147594.7-147594.32" + process $proc$libresoc.v:147594$6964 + assign { } { } + assign $1\logical_op__oe__oe[0:0] 1'0 + sync always + sync init + update \logical_op__oe__oe $1\logical_op__oe__oe[0:0] + end + attribute \src "libresoc.v:147603.7-147603.32" + process $proc$libresoc.v:147603$6965 + assign { } { } + assign $1\logical_op__oe__ok[0:0] 1'0 + sync always + sync init + update \logical_op__oe__ok $1\logical_op__oe__ok[0:0] + end + attribute \src "libresoc.v:147612.7-147612.38" + process $proc$libresoc.v:147612$6966 + assign { } { } + assign $1\logical_op__output_carry[0:0] 1'0 + sync always + sync init + update \logical_op__output_carry $1\logical_op__output_carry[0:0] + end + attribute \src "libresoc.v:147621.7-147621.32" + process $proc$libresoc.v:147621$6967 + assign { } { } + assign $1\logical_op__rc__ok[0:0] 1'0 + sync always + sync init + update \logical_op__rc__ok $1\logical_op__rc__ok[0:0] + end + attribute \src "libresoc.v:147630.7-147630.32" + process $proc$libresoc.v:147630$6968 + assign { } { } + assign $1\logical_op__rc__rc[0:0] 1'0 + sync always + sync init + update \logical_op__rc__rc $1\logical_op__rc__rc[0:0] + end + attribute \src "libresoc.v:147639.7-147639.35" + process $proc$libresoc.v:147639$6969 + assign { } { } + assign $1\logical_op__write_cr0[0:0] 1'0 + sync always + sync init + update \logical_op__write_cr0 $1\logical_op__write_cr0[0:0] + end + attribute \src "libresoc.v:147648.7-147648.32" + process $proc$libresoc.v:147648$6970 + assign { } { } + assign $1\logical_op__zero_a[0:0] 1'0 + sync always + sync init + update \logical_op__zero_a $1\logical_op__zero_a[0:0] + end + attribute \src "libresoc.v:147929.13-147929.25" + process $proc$libresoc.v:147929$6971 + assign { } { } + assign $1\muxid[1:0] 2'00 + sync always + sync init + update \muxid $1\muxid[1:0] + end + attribute \src "libresoc.v:147944.14-147944.38" + process $proc$libresoc.v:147944$6972 + assign { } { } + assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \o $1\o[63:0] + end + attribute \src "libresoc.v:147951.7-147951.18" + process $proc$libresoc.v:147951$6973 + assign { } { } + assign $1\o_ok[0:0] 1'0 + sync always + sync init + update \o_ok $1\o_ok[0:0] + end + attribute \src "libresoc.v:147965.7-147965.20" + process $proc$libresoc.v:147965$6974 + assign { } { } + assign $1\r_busy[0:0] 1'0 + sync always + sync init + update \r_busy $1\r_busy[0:0] + end + attribute \src "libresoc.v:147974.7-147974.20" + process $proc$libresoc.v:147974$6975 + assign { } { } + assign $1\xer_so[0:0] 1'0 + sync always + sync init + update \xer_so $1\xer_so[0:0] + end + attribute \src "libresoc.v:147983.7-147983.23" + process $proc$libresoc.v:147983$6976 + assign { } { } + assign $1\xer_so_ok[0:0] 1'0 + sync always + sync init + update \xer_so_ok $1\xer_so_ok[0:0] + end + attribute \src "libresoc.v:147991.3-147992.29" + process $proc$libresoc.v:147991$6856 + assign { } { } + assign $0\xer_so[0:0] \xer_so$next + sync posedge \coresync_clk + update \xer_so $0\xer_so[0:0] + end + attribute \src "libresoc.v:147993.3-147994.35" + process $proc$libresoc.v:147993$6857 + assign { } { } + assign $0\xer_so_ok[0:0] \xer_so_ok$next + sync posedge \coresync_clk + update \xer_so_ok $0\xer_so_ok[0:0] + end + attribute \src "libresoc.v:147995.3-147996.25" + process $proc$libresoc.v:147995$6858 + assign { } { } + assign $0\cr_a[3:0] \cr_a$next + sync posedge \coresync_clk + update \cr_a $0\cr_a[3:0] + end + attribute \src "libresoc.v:147997.3-147998.31" + process $proc$libresoc.v:147997$6859 + assign { } { } + assign $0\cr_a_ok[0:0] \cr_a_ok$next + sync posedge \coresync_clk + update \cr_a_ok $0\cr_a_ok[0:0] + end + attribute \src "libresoc.v:147999.3-148000.19" + process $proc$libresoc.v:147999$6860 + assign { } { } + assign $0\o[63:0] \o$next + sync posedge \coresync_clk + update \o $0\o[63:0] + end + attribute \src "libresoc.v:148001.3-148002.25" + process $proc$libresoc.v:148001$6861 + assign { } { } + assign $0\o_ok[0:0] \o_ok$next + sync posedge \coresync_clk + update \o_ok $0\o_ok[0:0] + end + attribute \src "libresoc.v:148003.3-148004.59" + process $proc$libresoc.v:148003$6862 + assign { } { } + assign $0\logical_op__insn_type[6:0] \logical_op__insn_type$next + sync posedge \coresync_clk + update \logical_op__insn_type $0\logical_op__insn_type[6:0] + end + attribute \src "libresoc.v:148005.3-148006.55" + process $proc$libresoc.v:148005$6863 + assign { } { } + assign $0\logical_op__fn_unit[12:0] \logical_op__fn_unit$next + sync posedge \coresync_clk + update \logical_op__fn_unit $0\logical_op__fn_unit[12:0] + end + attribute \src "libresoc.v:148007.3-148008.69" + process $proc$libresoc.v:148007$6864 + assign { } { } + assign $0\logical_op__imm_data__data[63:0] \logical_op__imm_data__data$next + sync posedge \coresync_clk + update \logical_op__imm_data__data $0\logical_op__imm_data__data[63:0] + end + attribute \src "libresoc.v:148009.3-148010.65" + process $proc$libresoc.v:148009$6865 + assign { } { } + assign $0\logical_op__imm_data__ok[0:0] \logical_op__imm_data__ok$next + sync posedge \coresync_clk + update \logical_op__imm_data__ok $0\logical_op__imm_data__ok[0:0] + end + attribute \src "libresoc.v:148011.3-148012.53" + process $proc$libresoc.v:148011$6866 + assign { } { } + assign $0\logical_op__rc__rc[0:0] \logical_op__rc__rc$next + sync posedge \coresync_clk + update \logical_op__rc__rc $0\logical_op__rc__rc[0:0] + end + attribute \src "libresoc.v:148013.3-148014.53" + process $proc$libresoc.v:148013$6867 + assign { } { } + assign $0\logical_op__rc__ok[0:0] \logical_op__rc__ok$next + sync posedge \coresync_clk + update \logical_op__rc__ok $0\logical_op__rc__ok[0:0] + end + attribute \src "libresoc.v:148015.3-148016.53" + process $proc$libresoc.v:148015$6868 + assign { } { } + assign $0\logical_op__oe__oe[0:0] \logical_op__oe__oe$next + sync posedge \coresync_clk + update \logical_op__oe__oe $0\logical_op__oe__oe[0:0] + end + attribute \src "libresoc.v:148017.3-148018.53" + process $proc$libresoc.v:148017$6869 + assign { } { } + assign $0\logical_op__oe__ok[0:0] \logical_op__oe__ok$next + sync posedge \coresync_clk + update \logical_op__oe__ok $0\logical_op__oe__ok[0:0] + end + attribute \src "libresoc.v:148019.3-148020.59" + process $proc$libresoc.v:148019$6870 + assign { } { } + assign $0\logical_op__invert_in[0:0] \logical_op__invert_in$next + sync posedge \coresync_clk + update \logical_op__invert_in $0\logical_op__invert_in[0:0] + end + attribute \src "libresoc.v:148021.3-148022.53" + process $proc$libresoc.v:148021$6871 + assign { } { } + assign $0\logical_op__zero_a[0:0] \logical_op__zero_a$next + sync posedge \coresync_clk + update \logical_op__zero_a $0\logical_op__zero_a[0:0] + end + attribute \src "libresoc.v:148023.3-148024.63" + process $proc$libresoc.v:148023$6872 + assign { } { } + assign $0\logical_op__input_carry[1:0] \logical_op__input_carry$next + sync posedge \coresync_clk + update \logical_op__input_carry $0\logical_op__input_carry[1:0] + end + attribute \src "libresoc.v:148025.3-148026.61" + process $proc$libresoc.v:148025$6873 + assign { } { } + assign $0\logical_op__invert_out[0:0] \logical_op__invert_out$next + sync posedge \coresync_clk + update \logical_op__invert_out $0\logical_op__invert_out[0:0] + end + attribute \src "libresoc.v:148027.3-148028.59" + process $proc$libresoc.v:148027$6874 + assign { } { } + assign $0\logical_op__write_cr0[0:0] \logical_op__write_cr0$next + sync posedge \coresync_clk + update \logical_op__write_cr0 $0\logical_op__write_cr0[0:0] + end + attribute \src "libresoc.v:148029.3-148030.65" + process $proc$libresoc.v:148029$6875 + assign { } { } + assign $0\logical_op__output_carry[0:0] \logical_op__output_carry$next + sync posedge \coresync_clk + update \logical_op__output_carry $0\logical_op__output_carry[0:0] + end + attribute \src "libresoc.v:148031.3-148032.57" + process $proc$libresoc.v:148031$6876 + assign { } { } + assign $0\logical_op__is_32bit[0:0] \logical_op__is_32bit$next + sync posedge \coresync_clk + update \logical_op__is_32bit $0\logical_op__is_32bit[0:0] + end + attribute \src "libresoc.v:148033.3-148034.59" + process $proc$libresoc.v:148033$6877 + assign { } { } + assign $0\logical_op__is_signed[0:0] \logical_op__is_signed$next + sync posedge \coresync_clk + update \logical_op__is_signed $0\logical_op__is_signed[0:0] + end + attribute \src "libresoc.v:148035.3-148036.57" + process $proc$libresoc.v:148035$6878 + assign { } { } + assign $0\logical_op__data_len[3:0] \logical_op__data_len$next + sync posedge \coresync_clk + update \logical_op__data_len $0\logical_op__data_len[3:0] + end + attribute \src "libresoc.v:148037.3-148038.49" + process $proc$libresoc.v:148037$6879 + assign { } { } + assign $0\logical_op__insn[31:0] \logical_op__insn$next + sync posedge \coresync_clk + update \logical_op__insn $0\logical_op__insn[31:0] + end + attribute \src "libresoc.v:148039.3-148040.27" + process $proc$libresoc.v:148039$6880 + assign { } { } + assign $0\muxid[1:0] \muxid$next + sync posedge \coresync_clk + update \muxid $0\muxid[1:0] + end + attribute \src "libresoc.v:148041.3-148042.29" + process $proc$libresoc.v:148041$6881 + assign { } { } + assign $0\r_busy[0:0] \r_busy$next + sync posedge \coresync_clk + update \r_busy $0\r_busy[0:0] + end + attribute \src "libresoc.v:148143.3-148160.6" + process $proc$libresoc.v:148143$6882 + assign { } { } + assign { } { } + assign { } { } + assign $0\r_busy$next[0:0]$6883 $2\r_busy$next[0:0]$6885 + attribute \src "libresoc.v:148144.5-148144.29" + switch \initial + attribute \src "libresoc.v:148144.9-148144.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\r_busy$next[0:0]$6884 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\r_busy$next[0:0]$6884 1'0 + case + assign $1\r_busy$next[0:0]$6884 \r_busy + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r_busy$next[0:0]$6885 1'0 + case + assign $2\r_busy$next[0:0]$6885 $1\r_busy$next[0:0]$6884 + end + sync always + update \r_busy$next $0\r_busy$next[0:0]$6883 + end + attribute \src "libresoc.v:148161.3-148173.6" + process $proc$libresoc.v:148161$6886 + assign { } { } + assign { } { } + assign $0\muxid$next[1:0]$6887 $1\muxid$next[1:0]$6888 + attribute \src "libresoc.v:148162.5-148162.29" + switch \initial + attribute \src "libresoc.v:148162.9-148162.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\muxid$next[1:0]$6888 \muxid$66 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\muxid$next[1:0]$6888 \muxid$66 + case + assign $1\muxid$next[1:0]$6888 \muxid + end + sync always + update \muxid$next $0\muxid$next[1:0]$6887 + end + attribute \src "libresoc.v:148174.3-148215.6" + process $proc$libresoc.v:148174$6889 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\logical_op__data_len$next[3:0]$6890 $1\logical_op__data_len$next[3:0]$6908 + assign $0\logical_op__fn_unit$next[12:0]$6891 $1\logical_op__fn_unit$next[12:0]$6909 + assign { } { } + assign { } { } + assign $0\logical_op__input_carry$next[1:0]$6894 $1\logical_op__input_carry$next[1:0]$6912 + assign $0\logical_op__insn$next[31:0]$6895 $1\logical_op__insn$next[31:0]$6913 + assign $0\logical_op__insn_type$next[6:0]$6896 $1\logical_op__insn_type$next[6:0]$6914 + assign $0\logical_op__invert_in$next[0:0]$6897 $1\logical_op__invert_in$next[0:0]$6915 + assign $0\logical_op__invert_out$next[0:0]$6898 $1\logical_op__invert_out$next[0:0]$6916 + assign $0\logical_op__is_32bit$next[0:0]$6899 $1\logical_op__is_32bit$next[0:0]$6917 + assign $0\logical_op__is_signed$next[0:0]$6900 $1\logical_op__is_signed$next[0:0]$6918 + assign { } { } + assign { } { } + assign $0\logical_op__output_carry$next[0:0]$6903 $1\logical_op__output_carry$next[0:0]$6921 + assign { } { } + assign { } { } + assign $0\logical_op__write_cr0$next[0:0]$6906 $1\logical_op__write_cr0$next[0:0]$6924 + assign $0\logical_op__zero_a$next[0:0]$6907 $1\logical_op__zero_a$next[0:0]$6925 + assign $0\logical_op__imm_data__data$next[63:0]$6892 $2\logical_op__imm_data__data$next[63:0]$6926 + assign $0\logical_op__imm_data__ok$next[0:0]$6893 $2\logical_op__imm_data__ok$next[0:0]$6927 + assign $0\logical_op__oe__oe$next[0:0]$6901 $2\logical_op__oe__oe$next[0:0]$6928 + assign $0\logical_op__oe__ok$next[0:0]$6902 $2\logical_op__oe__ok$next[0:0]$6929 + assign $0\logical_op__rc__ok$next[0:0]$6904 $2\logical_op__rc__ok$next[0:0]$6930 + assign $0\logical_op__rc__rc$next[0:0]$6905 $2\logical_op__rc__rc$next[0:0]$6931 + attribute \src "libresoc.v:148175.5-148175.29" + switch \initial + attribute \src "libresoc.v:148175.9-148175.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\logical_op__insn$next[31:0]$6913 $1\logical_op__data_len$next[3:0]$6908 $1\logical_op__is_signed$next[0:0]$6918 $1\logical_op__is_32bit$next[0:0]$6917 $1\logical_op__output_carry$next[0:0]$6921 $1\logical_op__write_cr0$next[0:0]$6924 $1\logical_op__invert_out$next[0:0]$6916 $1\logical_op__input_carry$next[1:0]$6912 $1\logical_op__zero_a$next[0:0]$6925 $1\logical_op__invert_in$next[0:0]$6915 $1\logical_op__oe__ok$next[0:0]$6920 $1\logical_op__oe__oe$next[0:0]$6919 $1\logical_op__rc__ok$next[0:0]$6922 $1\logical_op__rc__rc$next[0:0]$6923 $1\logical_op__imm_data__ok$next[0:0]$6911 $1\logical_op__imm_data__data$next[63:0]$6910 $1\logical_op__fn_unit$next[12:0]$6909 $1\logical_op__insn_type$next[6:0]$6914 } { \logical_op__insn$84 \logical_op__data_len$83 \logical_op__is_signed$82 \logical_op__is_32bit$81 \logical_op__output_carry$80 \logical_op__write_cr0$79 \logical_op__invert_out$78 \logical_op__input_carry$77 \logical_op__zero_a$76 \logical_op__invert_in$75 \logical_op__oe__ok$74 \logical_op__oe__oe$73 \logical_op__rc__ok$72 \logical_op__rc__rc$71 \logical_op__imm_data__ok$70 \logical_op__imm_data__data$69 \logical_op__fn_unit$68 \logical_op__insn_type$67 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\logical_op__insn$next[31:0]$6913 $1\logical_op__data_len$next[3:0]$6908 $1\logical_op__is_signed$next[0:0]$6918 $1\logical_op__is_32bit$next[0:0]$6917 $1\logical_op__output_carry$next[0:0]$6921 $1\logical_op__write_cr0$next[0:0]$6924 $1\logical_op__invert_out$next[0:0]$6916 $1\logical_op__input_carry$next[1:0]$6912 $1\logical_op__zero_a$next[0:0]$6925 $1\logical_op__invert_in$next[0:0]$6915 $1\logical_op__oe__ok$next[0:0]$6920 $1\logical_op__oe__oe$next[0:0]$6919 $1\logical_op__rc__ok$next[0:0]$6922 $1\logical_op__rc__rc$next[0:0]$6923 $1\logical_op__imm_data__ok$next[0:0]$6911 $1\logical_op__imm_data__data$next[63:0]$6910 $1\logical_op__fn_unit$next[12:0]$6909 $1\logical_op__insn_type$next[6:0]$6914 } { \logical_op__insn$84 \logical_op__data_len$83 \logical_op__is_signed$82 \logical_op__is_32bit$81 \logical_op__output_carry$80 \logical_op__write_cr0$79 \logical_op__invert_out$78 \logical_op__input_carry$77 \logical_op__zero_a$76 \logical_op__invert_in$75 \logical_op__oe__ok$74 \logical_op__oe__oe$73 \logical_op__rc__ok$72 \logical_op__rc__rc$71 \logical_op__imm_data__ok$70 \logical_op__imm_data__data$69 \logical_op__fn_unit$68 \logical_op__insn_type$67 } + case + assign $1\logical_op__data_len$next[3:0]$6908 \logical_op__data_len + assign $1\logical_op__fn_unit$next[12:0]$6909 \logical_op__fn_unit + assign $1\logical_op__imm_data__data$next[63:0]$6910 \logical_op__imm_data__data + assign $1\logical_op__imm_data__ok$next[0:0]$6911 \logical_op__imm_data__ok + assign $1\logical_op__input_carry$next[1:0]$6912 \logical_op__input_carry + assign $1\logical_op__insn$next[31:0]$6913 \logical_op__insn + assign $1\logical_op__insn_type$next[6:0]$6914 \logical_op__insn_type + assign $1\logical_op__invert_in$next[0:0]$6915 \logical_op__invert_in + assign $1\logical_op__invert_out$next[0:0]$6916 \logical_op__invert_out + assign $1\logical_op__is_32bit$next[0:0]$6917 \logical_op__is_32bit + assign $1\logical_op__is_signed$next[0:0]$6918 \logical_op__is_signed + assign $1\logical_op__oe__oe$next[0:0]$6919 \logical_op__oe__oe + assign $1\logical_op__oe__ok$next[0:0]$6920 \logical_op__oe__ok + assign $1\logical_op__output_carry$next[0:0]$6921 \logical_op__output_carry + assign $1\logical_op__rc__ok$next[0:0]$6922 \logical_op__rc__ok + assign $1\logical_op__rc__rc$next[0:0]$6923 \logical_op__rc__rc + assign $1\logical_op__write_cr0$next[0:0]$6924 \logical_op__write_cr0 + assign $1\logical_op__zero_a$next[0:0]$6925 \logical_op__zero_a + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $2\logical_op__imm_data__data$next[63:0]$6926 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\logical_op__imm_data__ok$next[0:0]$6927 1'0 + assign $2\logical_op__rc__rc$next[0:0]$6931 1'0 + assign $2\logical_op__rc__ok$next[0:0]$6930 1'0 + assign $2\logical_op__oe__oe$next[0:0]$6928 1'0 + assign $2\logical_op__oe__ok$next[0:0]$6929 1'0 + case + assign $2\logical_op__imm_data__data$next[63:0]$6926 $1\logical_op__imm_data__data$next[63:0]$6910 + assign $2\logical_op__imm_data__ok$next[0:0]$6927 $1\logical_op__imm_data__ok$next[0:0]$6911 + assign $2\logical_op__oe__oe$next[0:0]$6928 $1\logical_op__oe__oe$next[0:0]$6919 + assign $2\logical_op__oe__ok$next[0:0]$6929 $1\logical_op__oe__ok$next[0:0]$6920 + assign $2\logical_op__rc__ok$next[0:0]$6930 $1\logical_op__rc__ok$next[0:0]$6922 + assign $2\logical_op__rc__rc$next[0:0]$6931 $1\logical_op__rc__rc$next[0:0]$6923 + end + sync always + update \logical_op__data_len$next $0\logical_op__data_len$next[3:0]$6890 + update \logical_op__fn_unit$next $0\logical_op__fn_unit$next[12:0]$6891 + update \logical_op__imm_data__data$next $0\logical_op__imm_data__data$next[63:0]$6892 + update \logical_op__imm_data__ok$next $0\logical_op__imm_data__ok$next[0:0]$6893 + update \logical_op__input_carry$next $0\logical_op__input_carry$next[1:0]$6894 + update \logical_op__insn$next $0\logical_op__insn$next[31:0]$6895 + update \logical_op__insn_type$next $0\logical_op__insn_type$next[6:0]$6896 + update \logical_op__invert_in$next $0\logical_op__invert_in$next[0:0]$6897 + update \logical_op__invert_out$next $0\logical_op__invert_out$next[0:0]$6898 + update \logical_op__is_32bit$next $0\logical_op__is_32bit$next[0:0]$6899 + update \logical_op__is_signed$next $0\logical_op__is_signed$next[0:0]$6900 + update \logical_op__oe__oe$next $0\logical_op__oe__oe$next[0:0]$6901 + update \logical_op__oe__ok$next $0\logical_op__oe__ok$next[0:0]$6902 + update \logical_op__output_carry$next $0\logical_op__output_carry$next[0:0]$6903 + update \logical_op__rc__ok$next $0\logical_op__rc__ok$next[0:0]$6904 + update \logical_op__rc__rc$next $0\logical_op__rc__rc$next[0:0]$6905 + update \logical_op__write_cr0$next $0\logical_op__write_cr0$next[0:0]$6906 + update \logical_op__zero_a$next $0\logical_op__zero_a$next[0:0]$6907 + end + attribute \src "libresoc.v:148216.3-148234.6" + process $proc$libresoc.v:148216$6932 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\o$next[63:0]$6933 $1\o$next[63:0]$6935 + assign { } { } + assign $0\o_ok$next[0:0]$6934 $2\o_ok$next[0:0]$6937 + attribute \src "libresoc.v:148217.5-148217.29" + switch \initial + attribute \src "libresoc.v:148217.9-148217.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\o_ok$next[0:0]$6936 $1\o$next[63:0]$6935 } { \o_ok$86 \o$85 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\o_ok$next[0:0]$6936 $1\o$next[63:0]$6935 } { \o_ok$86 \o$85 } + case + assign $1\o$next[63:0]$6935 \o + assign $1\o_ok$next[0:0]$6936 \o_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\o_ok$next[0:0]$6937 1'0 + case + assign $2\o_ok$next[0:0]$6937 $1\o_ok$next[0:0]$6936 + end + sync always + update \o$next $0\o$next[63:0]$6933 + update \o_ok$next $0\o_ok$next[0:0]$6934 + end + attribute \src "libresoc.v:148235.3-148253.6" + process $proc$libresoc.v:148235$6938 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\cr_a$next[3:0]$6939 $1\cr_a$next[3:0]$6941 + assign { } { } + assign $0\cr_a_ok$next[0:0]$6940 $2\cr_a_ok$next[0:0]$6943 + attribute \src "libresoc.v:148236.5-148236.29" + switch \initial + attribute \src "libresoc.v:148236.9-148236.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\cr_a_ok$next[0:0]$6942 $1\cr_a$next[3:0]$6941 } { \cr_a_ok$88 \cr_a$87 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\cr_a_ok$next[0:0]$6942 $1\cr_a$next[3:0]$6941 } { \cr_a_ok$88 \cr_a$87 } + case + assign $1\cr_a$next[3:0]$6941 \cr_a + assign $1\cr_a_ok$next[0:0]$6942 \cr_a_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_a_ok$next[0:0]$6943 1'0 + case + assign $2\cr_a_ok$next[0:0]$6943 $1\cr_a_ok$next[0:0]$6942 + end + sync always + update \cr_a$next $0\cr_a$next[3:0]$6939 + update \cr_a_ok$next $0\cr_a_ok$next[0:0]$6940 + end + attribute \src "libresoc.v:148254.3-148272.6" + process $proc$libresoc.v:148254$6944 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\xer_so$next[0:0]$6945 $1\xer_so$next[0:0]$6947 + assign { } { } + assign $0\xer_so_ok$next[0:0]$6946 $2\xer_so_ok$next[0:0]$6949 + attribute \src "libresoc.v:148255.5-148255.29" + switch \initial + attribute \src "libresoc.v:148255.9-148255.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\xer_so_ok$next[0:0]$6948 $1\xer_so$next[0:0]$6947 } { \xer_so_ok$92 \xer_so$91 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\xer_so_ok$next[0:0]$6948 $1\xer_so$next[0:0]$6947 } { \xer_so_ok$92 \xer_so$91 } + case + assign $1\xer_so$next[0:0]$6947 \xer_so + assign $1\xer_so_ok$next[0:0]$6948 \xer_so_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\xer_so_ok$next[0:0]$6949 1'0 + case + assign $2\xer_so_ok$next[0:0]$6949 $1\xer_so_ok$next[0:0]$6948 + end + sync always + update \xer_so$next $0\xer_so$next[0:0]$6945 + update \xer_so_ok$next $0\xer_so_ok$next[0:0]$6946 + end + connect \$64 $and$libresoc.v:147990$6855_Y + connect \cr_a$89 4'0000 + connect \cr_a_ok$90 1'0 + connect \xer_so_ok$93 1'0 + connect \p_ready_o \n_i_rdy_data + connect \n_valid_o \r_busy + connect { \xer_so_ok$92 \xer_so$91 } { 1'0 \main_xer_so$62 } + connect { \cr_a_ok$88 \cr_a$87 } 5'00000 + connect { \o_ok$86 \o$85 } { \main_o_ok \main_o } + connect { \logical_op__insn$84 \logical_op__data_len$83 \logical_op__is_signed$82 \logical_op__is_32bit$81 \logical_op__output_carry$80 \logical_op__write_cr0$79 \logical_op__invert_out$78 \logical_op__input_carry$77 \logical_op__zero_a$76 \logical_op__invert_in$75 \logical_op__oe__ok$74 \logical_op__oe__oe$73 \logical_op__rc__ok$72 \logical_op__rc__rc$71 \logical_op__imm_data__ok$70 \logical_op__imm_data__data$69 \logical_op__fn_unit$68 \logical_op__insn_type$67 } { \main_logical_op__insn$61 \main_logical_op__data_len$60 \main_logical_op__is_signed$59 \main_logical_op__is_32bit$58 \main_logical_op__output_carry$57 \main_logical_op__write_cr0$56 \main_logical_op__invert_out$55 \main_logical_op__input_carry$54 \main_logical_op__zero_a$53 \main_logical_op__invert_in$52 \main_logical_op__oe__ok$51 \main_logical_op__oe__oe$50 \main_logical_op__rc__ok$49 \main_logical_op__rc__rc$48 \main_logical_op__imm_data__ok$47 \main_logical_op__imm_data__data$46 \main_logical_op__fn_unit$45 \main_logical_op__insn_type$44 } + connect \muxid$66 \main_muxid$43 + connect \p_valid_i_p_ready_o \$64 + connect \n_i_rdy_data \n_ready_i + connect \p_valid_i$63 \p_valid_i + connect \main_xer_so \input_xer_so$42 + connect \main_rb \input_rb$41 + connect \main_ra \input_ra$40 + connect { \main_logical_op__insn \main_logical_op__data_len \main_logical_op__is_signed \main_logical_op__is_32bit \main_logical_op__output_carry \main_logical_op__write_cr0 \main_logical_op__invert_out \main_logical_op__input_carry \main_logical_op__zero_a \main_logical_op__invert_in \main_logical_op__oe__ok \main_logical_op__oe__oe \main_logical_op__rc__ok \main_logical_op__rc__rc \main_logical_op__imm_data__ok \main_logical_op__imm_data__data \main_logical_op__fn_unit \main_logical_op__insn_type } { \input_logical_op__insn$39 \input_logical_op__data_len$38 \input_logical_op__is_signed$37 \input_logical_op__is_32bit$36 \input_logical_op__output_carry$35 \input_logical_op__write_cr0$34 \input_logical_op__invert_out$33 \input_logical_op__input_carry$32 \input_logical_op__zero_a$31 \input_logical_op__invert_in$30 \input_logical_op__oe__ok$29 \input_logical_op__oe__oe$28 \input_logical_op__rc__ok$27 \input_logical_op__rc__rc$26 \input_logical_op__imm_data__ok$25 \input_logical_op__imm_data__data$24 \input_logical_op__fn_unit$23 \input_logical_op__insn_type$22 } + connect \main_muxid \input_muxid$21 + connect \input_xer_so \xer_so$20 + connect \input_rb \rb + connect \input_ra \ra + connect { \input_logical_op__insn \input_logical_op__data_len \input_logical_op__is_signed \input_logical_op__is_32bit \input_logical_op__output_carry \input_logical_op__write_cr0 \input_logical_op__invert_out \input_logical_op__input_carry \input_logical_op__zero_a \input_logical_op__invert_in \input_logical_op__oe__ok \input_logical_op__oe__oe \input_logical_op__rc__ok \input_logical_op__rc__rc \input_logical_op__imm_data__ok \input_logical_op__imm_data__data \input_logical_op__fn_unit \input_logical_op__insn_type } { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } + connect \input_muxid \muxid$1 +end +attribute \src "libresoc.v:148300.1-149323.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe2" +attribute \generator "nMigen" +module \logical_pipe2 + attribute \src "libresoc.v:149290.3-149308.6" + wire width 4 $0\cr_a$22$next[3:0]$7082 + attribute \src "libresoc.v:149094.3-149095.33" + wire width 4 $0\cr_a$22[3:0]$6979 + attribute \src "libresoc.v:148312.13-148312.29" + wire width 4 $0\cr_a$22[3:0]$7089 + attribute \src "libresoc.v:149290.3-149308.6" + wire $0\cr_a_ok$23$next[0:0]$7083 + attribute \src "libresoc.v:149096.3-149097.39" + wire $0\cr_a_ok$23[0:0]$6981 + attribute \src "libresoc.v:148321.7-148321.26" + wire $0\cr_a_ok$23[0:0]$7091 + attribute \src "libresoc.v:148301.7-148301.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:149229.3-149270.6" + wire width 4 $0\logical_op__data_len$18$next[3:0]$7033 + attribute \src "libresoc.v:149134.3-149135.65" + wire width 4 $0\logical_op__data_len$18[3:0]$7019 + attribute \src "libresoc.v:148332.13-148332.45" + wire width 4 $0\logical_op__data_len$18[3:0]$7093 + attribute \src "libresoc.v:149229.3-149270.6" + wire width 13 $0\logical_op__fn_unit$3$next[12:0]$7034 + attribute \src "libresoc.v:149104.3-149105.61" + wire width 13 $0\logical_op__fn_unit$3[12:0]$6989 + attribute \src "libresoc.v:148369.14-148369.48" + wire width 13 $0\logical_op__fn_unit$3[12:0]$7095 + attribute \src "libresoc.v:149229.3-149270.6" + wire width 64 $0\logical_op__imm_data__data$4$next[63:0]$7035 + attribute \src "libresoc.v:149106.3-149107.75" + wire width 64 $0\logical_op__imm_data__data$4[63:0]$6991 + attribute \src "libresoc.v:148392.14-148392.67" + wire width 64 $0\logical_op__imm_data__data$4[63:0]$7097 + attribute \src "libresoc.v:149229.3-149270.6" + wire $0\logical_op__imm_data__ok$5$next[0:0]$7036 + attribute \src "libresoc.v:149108.3-149109.71" + wire $0\logical_op__imm_data__ok$5[0:0]$6993 + attribute \src "libresoc.v:148401.7-148401.42" + wire $0\logical_op__imm_data__ok$5[0:0]$7099 + attribute \src "libresoc.v:149229.3-149270.6" + wire width 2 $0\logical_op__input_carry$12$next[1:0]$7037 + attribute \src "libresoc.v:149122.3-149123.71" + wire width 2 $0\logical_op__input_carry$12[1:0]$7007 + attribute \src "libresoc.v:148418.13-148418.48" + wire width 2 $0\logical_op__input_carry$12[1:0]$7101 + attribute \src "libresoc.v:149229.3-149270.6" + wire width 32 $0\logical_op__insn$19$next[31:0]$7038 + attribute \src "libresoc.v:149136.3-149137.57" + wire width 32 $0\logical_op__insn$19[31:0]$7021 + attribute \src "libresoc.v:148431.14-148431.43" + wire width 32 $0\logical_op__insn$19[31:0]$7103 + attribute \src "libresoc.v:149229.3-149270.6" + wire width 7 $0\logical_op__insn_type$2$next[6:0]$7039 + attribute \src "libresoc.v:149102.3-149103.65" + wire width 7 $0\logical_op__insn_type$2[6:0]$6987 + attribute \src "libresoc.v:148588.13-148588.46" + wire width 7 $0\logical_op__insn_type$2[6:0]$7105 + attribute \src "libresoc.v:149229.3-149270.6" + wire $0\logical_op__invert_in$10$next[0:0]$7040 + attribute \src "libresoc.v:149118.3-149119.67" + wire $0\logical_op__invert_in$10[0:0]$7003 + attribute \src "libresoc.v:148671.7-148671.40" + wire $0\logical_op__invert_in$10[0:0]$7107 + attribute \src "libresoc.v:149229.3-149270.6" + wire $0\logical_op__invert_out$13$next[0:0]$7041 + attribute \src "libresoc.v:149124.3-149125.69" + wire $0\logical_op__invert_out$13[0:0]$7009 + attribute \src "libresoc.v:148680.7-148680.41" + wire $0\logical_op__invert_out$13[0:0]$7109 + attribute \src "libresoc.v:149229.3-149270.6" + wire $0\logical_op__is_32bit$16$next[0:0]$7042 + attribute \src "libresoc.v:149130.3-149131.65" + wire $0\logical_op__is_32bit$16[0:0]$7015 + attribute \src "libresoc.v:148689.7-148689.39" + wire $0\logical_op__is_32bit$16[0:0]$7111 + attribute \src "libresoc.v:149229.3-149270.6" + wire $0\logical_op__is_signed$17$next[0:0]$7043 + attribute \src "libresoc.v:149132.3-149133.67" + wire $0\logical_op__is_signed$17[0:0]$7017 + attribute \src "libresoc.v:148698.7-148698.40" + wire $0\logical_op__is_signed$17[0:0]$7113 + attribute \src "libresoc.v:149229.3-149270.6" + wire $0\logical_op__oe__oe$8$next[0:0]$7044 + attribute \src "libresoc.v:149114.3-149115.59" + wire $0\logical_op__oe__oe$8[0:0]$6999 + attribute \src "libresoc.v:148709.7-148709.36" + wire $0\logical_op__oe__oe$8[0:0]$7115 + attribute \src "libresoc.v:149229.3-149270.6" + wire $0\logical_op__oe__ok$9$next[0:0]$7045 + attribute \src "libresoc.v:149116.3-149117.59" + wire $0\logical_op__oe__ok$9[0:0]$7001 + attribute \src "libresoc.v:148718.7-148718.36" + wire $0\logical_op__oe__ok$9[0:0]$7117 + attribute \src "libresoc.v:149229.3-149270.6" + wire $0\logical_op__output_carry$15$next[0:0]$7046 + attribute \src "libresoc.v:149128.3-149129.73" + wire $0\logical_op__output_carry$15[0:0]$7013 + attribute \src "libresoc.v:148725.7-148725.43" + wire $0\logical_op__output_carry$15[0:0]$7119 + attribute \src "libresoc.v:149229.3-149270.6" + wire $0\logical_op__rc__ok$7$next[0:0]$7047 + attribute \src "libresoc.v:149112.3-149113.59" + wire $0\logical_op__rc__ok$7[0:0]$6997 + attribute \src "libresoc.v:148736.7-148736.36" + wire $0\logical_op__rc__ok$7[0:0]$7121 + attribute \src "libresoc.v:149229.3-149270.6" + wire $0\logical_op__rc__rc$6$next[0:0]$7048 + attribute \src "libresoc.v:149110.3-149111.59" + wire $0\logical_op__rc__rc$6[0:0]$6995 + attribute \src "libresoc.v:148745.7-148745.36" + wire $0\logical_op__rc__rc$6[0:0]$7123 + attribute \src "libresoc.v:149229.3-149270.6" + wire $0\logical_op__write_cr0$14$next[0:0]$7049 + attribute \src "libresoc.v:149126.3-149127.67" + wire $0\logical_op__write_cr0$14[0:0]$7011 + attribute \src "libresoc.v:148752.7-148752.40" + wire $0\logical_op__write_cr0$14[0:0]$7125 + attribute \src "libresoc.v:149229.3-149270.6" + wire $0\logical_op__zero_a$11$next[0:0]$7050 + attribute \src "libresoc.v:149120.3-149121.61" + wire $0\logical_op__zero_a$11[0:0]$7005 + attribute \src "libresoc.v:148761.7-148761.37" + wire $0\logical_op__zero_a$11[0:0]$7127 + attribute \src "libresoc.v:149216.3-149228.6" + wire width 2 $0\muxid$1$next[1:0]$7030 + attribute \src "libresoc.v:149138.3-149139.33" + wire width 2 $0\muxid$1[1:0]$7023 + attribute \src "libresoc.v:148770.13-148770.29" + wire width 2 $0\muxid$1[1:0]$7129 + attribute \src "libresoc.v:149271.3-149289.6" + wire width 64 $0\o$20$next[63:0]$7076 + attribute \src "libresoc.v:149098.3-149099.27" + wire width 64 $0\o$20[63:0]$6983 + attribute \src "libresoc.v:148785.14-148785.43" + wire width 64 $0\o$20[63:0]$7131 + attribute \src "libresoc.v:149271.3-149289.6" + wire $0\o_ok$21$next[0:0]$7077 + attribute \src "libresoc.v:149100.3-149101.33" + wire $0\o_ok$21[0:0]$6985 + attribute \src "libresoc.v:148794.7-148794.23" + wire $0\o_ok$21[0:0]$7133 + attribute \src "libresoc.v:149198.3-149215.6" + wire $0\r_busy$next[0:0]$7026 + attribute \src "libresoc.v:149140.3-149141.29" + wire $0\r_busy[0:0] + attribute \src "libresoc.v:149290.3-149308.6" + wire width 4 $1\cr_a$22$next[3:0]$7084 + attribute \src "libresoc.v:149290.3-149308.6" + wire $1\cr_a_ok$23$next[0:0]$7085 + attribute \src "libresoc.v:149229.3-149270.6" + wire width 4 $1\logical_op__data_len$18$next[3:0]$7051 + attribute \src "libresoc.v:149229.3-149270.6" + wire width 13 $1\logical_op__fn_unit$3$next[12:0]$7052 + attribute \src "libresoc.v:149229.3-149270.6" + wire width 64 $1\logical_op__imm_data__data$4$next[63:0]$7053 + attribute \src "libresoc.v:149229.3-149270.6" + wire $1\logical_op__imm_data__ok$5$next[0:0]$7054 + attribute \src "libresoc.v:149229.3-149270.6" + wire width 2 $1\logical_op__input_carry$12$next[1:0]$7055 + attribute \src "libresoc.v:149229.3-149270.6" + wire width 32 $1\logical_op__insn$19$next[31:0]$7056 + attribute \src "libresoc.v:149229.3-149270.6" + wire width 7 $1\logical_op__insn_type$2$next[6:0]$7057 + attribute \src "libresoc.v:149229.3-149270.6" + wire $1\logical_op__invert_in$10$next[0:0]$7058 + attribute \src "libresoc.v:149229.3-149270.6" + wire $1\logical_op__invert_out$13$next[0:0]$7059 + attribute \src "libresoc.v:149229.3-149270.6" + wire $1\logical_op__is_32bit$16$next[0:0]$7060 + attribute \src "libresoc.v:149229.3-149270.6" + wire $1\logical_op__is_signed$17$next[0:0]$7061 + attribute \src "libresoc.v:149229.3-149270.6" + wire $1\logical_op__oe__oe$8$next[0:0]$7062 + attribute \src "libresoc.v:149229.3-149270.6" + wire $1\logical_op__oe__ok$9$next[0:0]$7063 + attribute \src "libresoc.v:149229.3-149270.6" + wire $1\logical_op__output_carry$15$next[0:0]$7064 + attribute \src "libresoc.v:149229.3-149270.6" + wire $1\logical_op__rc__ok$7$next[0:0]$7065 + attribute \src "libresoc.v:149229.3-149270.6" + wire $1\logical_op__rc__rc$6$next[0:0]$7066 + attribute \src "libresoc.v:149229.3-149270.6" + wire $1\logical_op__write_cr0$14$next[0:0]$7067 + attribute \src "libresoc.v:149229.3-149270.6" + wire $1\logical_op__zero_a$11$next[0:0]$7068 + attribute \src "libresoc.v:149216.3-149228.6" + wire width 2 $1\muxid$1$next[1:0]$7031 + attribute \src "libresoc.v:149271.3-149289.6" + wire width 64 $1\o$20$next[63:0]$7078 + attribute \src "libresoc.v:149271.3-149289.6" + wire $1\o_ok$21$next[0:0]$7079 + attribute \src "libresoc.v:149198.3-149215.6" + wire $1\r_busy$next[0:0]$7027 + attribute \src "libresoc.v:149084.7-149084.20" + wire $1\r_busy[0:0] + attribute \src "libresoc.v:149290.3-149308.6" + wire $2\cr_a_ok$23$next[0:0]$7086 + attribute \src "libresoc.v:149229.3-149270.6" + wire width 64 $2\logical_op__imm_data__data$4$next[63:0]$7069 + attribute \src "libresoc.v:149229.3-149270.6" + wire $2\logical_op__imm_data__ok$5$next[0:0]$7070 + attribute \src "libresoc.v:149229.3-149270.6" + wire $2\logical_op__oe__oe$8$next[0:0]$7071 + attribute \src "libresoc.v:149229.3-149270.6" + wire $2\logical_op__oe__ok$9$next[0:0]$7072 + attribute \src "libresoc.v:149229.3-149270.6" + wire $2\logical_op__rc__ok$7$next[0:0]$7073 + attribute \src "libresoc.v:149229.3-149270.6" + wire $2\logical_op__rc__rc$6$next[0:0]$7074 + attribute \src "libresoc.v:149271.3-149289.6" + wire $2\o_ok$21$next[0:0]$7080 + attribute \src "libresoc.v:149198.3-149215.6" + wire $2\r_busy$next[0:0]$7028 + attribute \src "libresoc.v:149093.18-149093.118" + wire $and$libresoc.v:149093$6977_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" + wire \$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 54 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 input 25 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 output 52 \cr_a$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \cr_a$22$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \cr_a$72 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire input 26 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 53 \cr_a_ok$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_a_ok$23$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_a_ok$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_a_ok$73 + attribute \src "libresoc.v:148301.7-148301.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 21 \logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 48 \logical_op__data_len$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \logical_op__data_len$18$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \logical_op__data_len$68 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 input 6 \logical_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 output 33 \logical_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \logical_op__fn_unit$3$next + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \logical_op__fn_unit$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 7 \logical_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 34 \logical_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \logical_op__imm_data__data$4$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \logical_op__imm_data__data$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \logical_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 35 \logical_op__imm_data__ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__imm_data__ok$5$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__imm_data__ok$55 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 15 \logical_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 42 \logical_op__input_carry$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \logical_op__input_carry$12$next + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \logical_op__input_carry$62 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 22 \logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 49 \logical_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \logical_op__insn$19$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \logical_op__insn$69 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 5 \logical_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 32 \logical_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \logical_op__insn_type$2$next + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \logical_op__insn_type$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 40 \logical_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_in$10$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_in$60 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 16 \logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 43 \logical_op__invert_out$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_out$13$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_out$63 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 19 \logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 46 \logical_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_32bit$16$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_32bit$66 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 20 \logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 47 \logical_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_signed$17$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_signed$67 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 11 \logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__oe$58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 38 \logical_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__oe$8$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__ok$59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 39 \logical_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__ok$9$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 18 \logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 45 \logical_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__output_carry$15$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__output_carry$65 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__ok$57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 37 \logical_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__ok$7$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__rc$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 36 \logical_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__rc$6$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 17 \logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 44 \logical_op__write_cr0$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__write_cr0$14$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__write_cr0$64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 41 \logical_op__zero_a$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__zero_a$11$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__zero_a$61 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 input 4 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 output 31 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid$1$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid$51 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + wire \n_i_rdy_data + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire input 30 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire output 29 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 input 23 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 50 \o$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \o$20$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \o$70 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire input 24 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 51 \o_ok$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \o_ok$21$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \o_ok$71 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \output_cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \output_cr_a$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \output_cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \output_logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \output_logical_op__data_len$41 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \output_logical_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \output_logical_op__fn_unit$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \output_logical_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \output_logical_op__imm_data__data$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__imm_data__ok$28 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \output_logical_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \output_logical_op__input_carry$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \output_logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \output_logical_op__insn$42 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \output_logical_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \output_logical_op__insn_type$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__invert_in$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__invert_out$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__is_32bit$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__is_signed$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__oe__oe$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__oe__ok$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__output_carry$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__rc__ok$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__rc__rc$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__write_cr0$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__zero_a$34 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \output_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \output_muxid$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \output_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \output_o$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \output_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \output_o_ok$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \output_xer_so + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" + wire output 3 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" + wire input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" + wire \p_valid_i$48 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" + wire \p_valid_i_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire \r_busy$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire input 27 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire input 28 \xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so_ok$47 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" + cell $and $and$libresoc.v:149093$6977 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i$48 + connect \B \p_ready_o + connect \Y $and$libresoc.v:149093$6977_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:149142.10-149145.4" + cell \n$53 \n + connect \n_ready_i \n_ready_i + connect \n_valid_o \n_valid_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:149146.15-149193.4" + cell \output$54 \output + connect \cr_a \output_cr_a + connect \cr_a$22 \output_cr_a$45 + connect \cr_a_ok \output_cr_a_ok + connect \logical_op__data_len \output_logical_op__data_len + connect \logical_op__data_len$18 \output_logical_op__data_len$41 + connect \logical_op__fn_unit \output_logical_op__fn_unit + connect \logical_op__fn_unit$3 \output_logical_op__fn_unit$26 + connect \logical_op__imm_data__data \output_logical_op__imm_data__data + connect \logical_op__imm_data__data$4 \output_logical_op__imm_data__data$27 + connect \logical_op__imm_data__ok \output_logical_op__imm_data__ok + connect \logical_op__imm_data__ok$5 \output_logical_op__imm_data__ok$28 + connect \logical_op__input_carry \output_logical_op__input_carry + connect \logical_op__input_carry$12 \output_logical_op__input_carry$35 + connect \logical_op__insn \output_logical_op__insn + connect \logical_op__insn$19 \output_logical_op__insn$42 + connect \logical_op__insn_type \output_logical_op__insn_type + connect \logical_op__insn_type$2 \output_logical_op__insn_type$25 + connect \logical_op__invert_in \output_logical_op__invert_in + connect \logical_op__invert_in$10 \output_logical_op__invert_in$33 + connect \logical_op__invert_out \output_logical_op__invert_out + connect \logical_op__invert_out$13 \output_logical_op__invert_out$36 + connect \logical_op__is_32bit \output_logical_op__is_32bit + connect \logical_op__is_32bit$16 \output_logical_op__is_32bit$39 + connect \logical_op__is_signed \output_logical_op__is_signed + connect \logical_op__is_signed$17 \output_logical_op__is_signed$40 + connect \logical_op__oe__oe \output_logical_op__oe__oe + connect \logical_op__oe__oe$8 \output_logical_op__oe__oe$31 + connect \logical_op__oe__ok \output_logical_op__oe__ok + connect \logical_op__oe__ok$9 \output_logical_op__oe__ok$32 + connect \logical_op__output_carry \output_logical_op__output_carry + connect \logical_op__output_carry$15 \output_logical_op__output_carry$38 + connect \logical_op__rc__ok \output_logical_op__rc__ok + connect \logical_op__rc__ok$7 \output_logical_op__rc__ok$30 + connect \logical_op__rc__rc \output_logical_op__rc__rc + connect \logical_op__rc__rc$6 \output_logical_op__rc__rc$29 + connect \logical_op__write_cr0 \output_logical_op__write_cr0 + connect \logical_op__write_cr0$14 \output_logical_op__write_cr0$37 + connect \logical_op__zero_a \output_logical_op__zero_a + connect \logical_op__zero_a$11 \output_logical_op__zero_a$34 + connect \muxid \output_muxid + connect \muxid$1 \output_muxid$24 + connect \o \output_o + connect \o$20 \output_o$43 + connect \o_ok \output_o_ok + connect \o_ok$21 \output_o_ok$44 + connect \xer_so \output_xer_so + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:149194.10-149197.4" + cell \p$52 \p + connect \p_ready_o \p_ready_o + connect \p_valid_i \p_valid_i + end + attribute \src "libresoc.v:148301.7-148301.20" + process $proc$libresoc.v:148301$7087 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:148312.13-148312.29" + process $proc$libresoc.v:148312$7088 + assign { } { } + assign $0\cr_a$22[3:0]$7089 4'0000 + sync always + sync init + update \cr_a$22 $0\cr_a$22[3:0]$7089 + end + attribute \src "libresoc.v:148321.7-148321.26" + process $proc$libresoc.v:148321$7090 + assign { } { } + assign $0\cr_a_ok$23[0:0]$7091 1'0 + sync always + sync init + update \cr_a_ok$23 $0\cr_a_ok$23[0:0]$7091 + end + attribute \src "libresoc.v:148332.13-148332.45" + process $proc$libresoc.v:148332$7092 + assign { } { } + assign $0\logical_op__data_len$18[3:0]$7093 4'0000 + sync always + sync init + update \logical_op__data_len$18 $0\logical_op__data_len$18[3:0]$7093 + end + attribute \src "libresoc.v:148369.14-148369.48" + process $proc$libresoc.v:148369$7094 + assign { } { } + assign $0\logical_op__fn_unit$3[12:0]$7095 13'0000000000000 + sync always + sync init + update \logical_op__fn_unit$3 $0\logical_op__fn_unit$3[12:0]$7095 + end + attribute \src "libresoc.v:148392.14-148392.67" + process $proc$libresoc.v:148392$7096 + assign { } { } + assign $0\logical_op__imm_data__data$4[63:0]$7097 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \logical_op__imm_data__data$4 $0\logical_op__imm_data__data$4[63:0]$7097 + end + attribute \src "libresoc.v:148401.7-148401.42" + process $proc$libresoc.v:148401$7098 + assign { } { } + assign $0\logical_op__imm_data__ok$5[0:0]$7099 1'0 + sync always + sync init + update \logical_op__imm_data__ok$5 $0\logical_op__imm_data__ok$5[0:0]$7099 + end + attribute \src "libresoc.v:148418.13-148418.48" + process $proc$libresoc.v:148418$7100 + assign { } { } + assign $0\logical_op__input_carry$12[1:0]$7101 2'00 + sync always + sync init + update \logical_op__input_carry$12 $0\logical_op__input_carry$12[1:0]$7101 + end + attribute \src "libresoc.v:148431.14-148431.43" + process $proc$libresoc.v:148431$7102 + assign { } { } + assign $0\logical_op__insn$19[31:0]$7103 0 + sync always + sync init + update \logical_op__insn$19 $0\logical_op__insn$19[31:0]$7103 + end + attribute \src "libresoc.v:148588.13-148588.46" + process $proc$libresoc.v:148588$7104 + assign { } { } + assign $0\logical_op__insn_type$2[6:0]$7105 7'0000000 + sync always + sync init + update \logical_op__insn_type$2 $0\logical_op__insn_type$2[6:0]$7105 + end + attribute \src "libresoc.v:148671.7-148671.40" + process $proc$libresoc.v:148671$7106 + assign { } { } + assign $0\logical_op__invert_in$10[0:0]$7107 1'0 + sync always + sync init + update \logical_op__invert_in$10 $0\logical_op__invert_in$10[0:0]$7107 + end + attribute \src "libresoc.v:148680.7-148680.41" + process $proc$libresoc.v:148680$7108 + assign { } { } + assign $0\logical_op__invert_out$13[0:0]$7109 1'0 + sync always + sync init + update \logical_op__invert_out$13 $0\logical_op__invert_out$13[0:0]$7109 + end + attribute \src "libresoc.v:148689.7-148689.39" + process $proc$libresoc.v:148689$7110 + assign { } { } + assign $0\logical_op__is_32bit$16[0:0]$7111 1'0 + sync always + sync init + update \logical_op__is_32bit$16 $0\logical_op__is_32bit$16[0:0]$7111 + end + attribute \src "libresoc.v:148698.7-148698.40" + process $proc$libresoc.v:148698$7112 + assign { } { } + assign $0\logical_op__is_signed$17[0:0]$7113 1'0 + sync always + sync init + update \logical_op__is_signed$17 $0\logical_op__is_signed$17[0:0]$7113 + end + attribute \src "libresoc.v:148709.7-148709.36" + process $proc$libresoc.v:148709$7114 + assign { } { } + assign $0\logical_op__oe__oe$8[0:0]$7115 1'0 + sync always + sync init + update \logical_op__oe__oe$8 $0\logical_op__oe__oe$8[0:0]$7115 + end + attribute \src "libresoc.v:148718.7-148718.36" + process $proc$libresoc.v:148718$7116 + assign { } { } + assign $0\logical_op__oe__ok$9[0:0]$7117 1'0 + sync always + sync init + update \logical_op__oe__ok$9 $0\logical_op__oe__ok$9[0:0]$7117 + end + attribute \src "libresoc.v:148725.7-148725.43" + process $proc$libresoc.v:148725$7118 + assign { } { } + assign $0\logical_op__output_carry$15[0:0]$7119 1'0 + sync always + sync init + update \logical_op__output_carry$15 $0\logical_op__output_carry$15[0:0]$7119 + end + attribute \src "libresoc.v:148736.7-148736.36" + process $proc$libresoc.v:148736$7120 + assign { } { } + assign $0\logical_op__rc__ok$7[0:0]$7121 1'0 + sync always + sync init + update \logical_op__rc__ok$7 $0\logical_op__rc__ok$7[0:0]$7121 + end + attribute \src "libresoc.v:148745.7-148745.36" + process $proc$libresoc.v:148745$7122 + assign { } { } + assign $0\logical_op__rc__rc$6[0:0]$7123 1'0 + sync always + sync init + update \logical_op__rc__rc$6 $0\logical_op__rc__rc$6[0:0]$7123 + end + attribute \src "libresoc.v:148752.7-148752.40" + process $proc$libresoc.v:148752$7124 + assign { } { } + assign $0\logical_op__write_cr0$14[0:0]$7125 1'0 + sync always + sync init + update \logical_op__write_cr0$14 $0\logical_op__write_cr0$14[0:0]$7125 + end + attribute \src "libresoc.v:148761.7-148761.37" + process $proc$libresoc.v:148761$7126 + assign { } { } + assign $0\logical_op__zero_a$11[0:0]$7127 1'0 + sync always + sync init + update \logical_op__zero_a$11 $0\logical_op__zero_a$11[0:0]$7127 + end + attribute \src "libresoc.v:148770.13-148770.29" + process $proc$libresoc.v:148770$7128 + assign { } { } + assign $0\muxid$1[1:0]$7129 2'00 + sync always + sync init + update \muxid$1 $0\muxid$1[1:0]$7129 + end + attribute \src "libresoc.v:148785.14-148785.43" + process $proc$libresoc.v:148785$7130 + assign { } { } + assign $0\o$20[63:0]$7131 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \o$20 $0\o$20[63:0]$7131 + end + attribute \src "libresoc.v:148794.7-148794.23" + process $proc$libresoc.v:148794$7132 + assign { } { } + assign $0\o_ok$21[0:0]$7133 1'0 + sync always + sync init + update \o_ok$21 $0\o_ok$21[0:0]$7133 + end + attribute \src "libresoc.v:149084.7-149084.20" + process $proc$libresoc.v:149084$7134 + assign { } { } + assign $1\r_busy[0:0] 1'0 + sync always + sync init + update \r_busy $1\r_busy[0:0] + end + attribute \src "libresoc.v:149094.3-149095.33" + process $proc$libresoc.v:149094$6978 + assign { } { } + assign $0\cr_a$22[3:0]$6979 \cr_a$22$next + sync posedge \coresync_clk + update \cr_a$22 $0\cr_a$22[3:0]$6979 + end + attribute \src "libresoc.v:149096.3-149097.39" + process $proc$libresoc.v:149096$6980 + assign { } { } + assign $0\cr_a_ok$23[0:0]$6981 \cr_a_ok$23$next + sync posedge \coresync_clk + update \cr_a_ok$23 $0\cr_a_ok$23[0:0]$6981 + end + attribute \src "libresoc.v:149098.3-149099.27" + process $proc$libresoc.v:149098$6982 + assign { } { } + assign $0\o$20[63:0]$6983 \o$20$next + sync posedge \coresync_clk + update \o$20 $0\o$20[63:0]$6983 + end + attribute \src "libresoc.v:149100.3-149101.33" + process $proc$libresoc.v:149100$6984 + assign { } { } + assign $0\o_ok$21[0:0]$6985 \o_ok$21$next + sync posedge \coresync_clk + update \o_ok$21 $0\o_ok$21[0:0]$6985 + end + attribute \src "libresoc.v:149102.3-149103.65" + process $proc$libresoc.v:149102$6986 + assign { } { } + assign $0\logical_op__insn_type$2[6:0]$6987 \logical_op__insn_type$2$next + sync posedge \coresync_clk + update \logical_op__insn_type$2 $0\logical_op__insn_type$2[6:0]$6987 + end + attribute \src "libresoc.v:149104.3-149105.61" + process $proc$libresoc.v:149104$6988 + assign { } { } + assign $0\logical_op__fn_unit$3[12:0]$6989 \logical_op__fn_unit$3$next + sync posedge \coresync_clk + update \logical_op__fn_unit$3 $0\logical_op__fn_unit$3[12:0]$6989 + end + attribute \src "libresoc.v:149106.3-149107.75" + process $proc$libresoc.v:149106$6990 + assign { } { } + assign $0\logical_op__imm_data__data$4[63:0]$6991 \logical_op__imm_data__data$4$next + sync posedge \coresync_clk + update \logical_op__imm_data__data$4 $0\logical_op__imm_data__data$4[63:0]$6991 + end + attribute \src "libresoc.v:149108.3-149109.71" + process $proc$libresoc.v:149108$6992 + assign { } { } + assign $0\logical_op__imm_data__ok$5[0:0]$6993 \logical_op__imm_data__ok$5$next + sync posedge \coresync_clk + update \logical_op__imm_data__ok$5 $0\logical_op__imm_data__ok$5[0:0]$6993 + end + attribute \src "libresoc.v:149110.3-149111.59" + process $proc$libresoc.v:149110$6994 + assign { } { } + assign $0\logical_op__rc__rc$6[0:0]$6995 \logical_op__rc__rc$6$next + sync posedge \coresync_clk + update \logical_op__rc__rc$6 $0\logical_op__rc__rc$6[0:0]$6995 + end + attribute \src "libresoc.v:149112.3-149113.59" + process $proc$libresoc.v:149112$6996 + assign { } { } + assign $0\logical_op__rc__ok$7[0:0]$6997 \logical_op__rc__ok$7$next + sync posedge \coresync_clk + update \logical_op__rc__ok$7 $0\logical_op__rc__ok$7[0:0]$6997 + end + attribute \src "libresoc.v:149114.3-149115.59" + process $proc$libresoc.v:149114$6998 + assign { } { } + assign $0\logical_op__oe__oe$8[0:0]$6999 \logical_op__oe__oe$8$next + sync posedge \coresync_clk + update \logical_op__oe__oe$8 $0\logical_op__oe__oe$8[0:0]$6999 + end + attribute \src "libresoc.v:149116.3-149117.59" + process $proc$libresoc.v:149116$7000 + assign { } { } + assign $0\logical_op__oe__ok$9[0:0]$7001 \logical_op__oe__ok$9$next + sync posedge \coresync_clk + update \logical_op__oe__ok$9 $0\logical_op__oe__ok$9[0:0]$7001 + end + attribute \src "libresoc.v:149118.3-149119.67" + process $proc$libresoc.v:149118$7002 + assign { } { } + assign $0\logical_op__invert_in$10[0:0]$7003 \logical_op__invert_in$10$next + sync posedge \coresync_clk + update \logical_op__invert_in$10 $0\logical_op__invert_in$10[0:0]$7003 + end + attribute \src "libresoc.v:149120.3-149121.61" + process $proc$libresoc.v:149120$7004 + assign { } { } + assign $0\logical_op__zero_a$11[0:0]$7005 \logical_op__zero_a$11$next + sync posedge \coresync_clk + update \logical_op__zero_a$11 $0\logical_op__zero_a$11[0:0]$7005 + end + attribute \src "libresoc.v:149122.3-149123.71" + process $proc$libresoc.v:149122$7006 + assign { } { } + assign $0\logical_op__input_carry$12[1:0]$7007 \logical_op__input_carry$12$next + sync posedge \coresync_clk + update \logical_op__input_carry$12 $0\logical_op__input_carry$12[1:0]$7007 + end + attribute \src "libresoc.v:149124.3-149125.69" + process $proc$libresoc.v:149124$7008 + assign { } { } + assign $0\logical_op__invert_out$13[0:0]$7009 \logical_op__invert_out$13$next + sync posedge \coresync_clk + update \logical_op__invert_out$13 $0\logical_op__invert_out$13[0:0]$7009 + end + attribute \src "libresoc.v:149126.3-149127.67" + process $proc$libresoc.v:149126$7010 + assign { } { } + assign $0\logical_op__write_cr0$14[0:0]$7011 \logical_op__write_cr0$14$next + sync posedge \coresync_clk + update \logical_op__write_cr0$14 $0\logical_op__write_cr0$14[0:0]$7011 + end + attribute \src "libresoc.v:149128.3-149129.73" + process $proc$libresoc.v:149128$7012 + assign { } { } + assign $0\logical_op__output_carry$15[0:0]$7013 \logical_op__output_carry$15$next + sync posedge \coresync_clk + update \logical_op__output_carry$15 $0\logical_op__output_carry$15[0:0]$7013 + end + attribute \src "libresoc.v:149130.3-149131.65" + process $proc$libresoc.v:149130$7014 + assign { } { } + assign $0\logical_op__is_32bit$16[0:0]$7015 \logical_op__is_32bit$16$next + sync posedge \coresync_clk + update \logical_op__is_32bit$16 $0\logical_op__is_32bit$16[0:0]$7015 + end + attribute \src "libresoc.v:149132.3-149133.67" + process $proc$libresoc.v:149132$7016 + assign { } { } + assign $0\logical_op__is_signed$17[0:0]$7017 \logical_op__is_signed$17$next + sync posedge \coresync_clk + update \logical_op__is_signed$17 $0\logical_op__is_signed$17[0:0]$7017 + end + attribute \src "libresoc.v:149134.3-149135.65" + process $proc$libresoc.v:149134$7018 + assign { } { } + assign $0\logical_op__data_len$18[3:0]$7019 \logical_op__data_len$18$next + sync posedge \coresync_clk + update \logical_op__data_len$18 $0\logical_op__data_len$18[3:0]$7019 + end + attribute \src "libresoc.v:149136.3-149137.57" + process $proc$libresoc.v:149136$7020 + assign { } { } + assign $0\logical_op__insn$19[31:0]$7021 \logical_op__insn$19$next + sync posedge \coresync_clk + update \logical_op__insn$19 $0\logical_op__insn$19[31:0]$7021 + end + attribute \src "libresoc.v:149138.3-149139.33" + process $proc$libresoc.v:149138$7022 + assign { } { } + assign $0\muxid$1[1:0]$7023 \muxid$1$next + sync posedge \coresync_clk + update \muxid$1 $0\muxid$1[1:0]$7023 + end + attribute \src "libresoc.v:149140.3-149141.29" + process $proc$libresoc.v:149140$7024 + assign { } { } + assign $0\r_busy[0:0] \r_busy$next + sync posedge \coresync_clk + update \r_busy $0\r_busy[0:0] + end + attribute \src "libresoc.v:149198.3-149215.6" + process $proc$libresoc.v:149198$7025 + assign { } { } + assign { } { } + assign { } { } + assign $0\r_busy$next[0:0]$7026 $2\r_busy$next[0:0]$7028 + attribute \src "libresoc.v:149199.5-149199.29" + switch \initial + attribute \src "libresoc.v:149199.9-149199.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\r_busy$next[0:0]$7027 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\r_busy$next[0:0]$7027 1'0 + case + assign $1\r_busy$next[0:0]$7027 \r_busy + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r_busy$next[0:0]$7028 1'0 + case + assign $2\r_busy$next[0:0]$7028 $1\r_busy$next[0:0]$7027 + end + sync always + update \r_busy$next $0\r_busy$next[0:0]$7026 + end + attribute \src "libresoc.v:149216.3-149228.6" + process $proc$libresoc.v:149216$7029 + assign { } { } + assign { } { } + assign $0\muxid$1$next[1:0]$7030 $1\muxid$1$next[1:0]$7031 + attribute \src "libresoc.v:149217.5-149217.29" + switch \initial + attribute \src "libresoc.v:149217.9-149217.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\muxid$1$next[1:0]$7031 \muxid$51 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\muxid$1$next[1:0]$7031 \muxid$51 + case + assign $1\muxid$1$next[1:0]$7031 \muxid$1 + end + sync always + update \muxid$1$next $0\muxid$1$next[1:0]$7030 + end + attribute \src "libresoc.v:149229.3-149270.6" + process $proc$libresoc.v:149229$7032 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\logical_op__data_len$18$next[3:0]$7033 $1\logical_op__data_len$18$next[3:0]$7051 + assign $0\logical_op__fn_unit$3$next[12:0]$7034 $1\logical_op__fn_unit$3$next[12:0]$7052 + assign { } { } + assign { } { } + assign $0\logical_op__input_carry$12$next[1:0]$7037 $1\logical_op__input_carry$12$next[1:0]$7055 + assign $0\logical_op__insn$19$next[31:0]$7038 $1\logical_op__insn$19$next[31:0]$7056 + assign $0\logical_op__insn_type$2$next[6:0]$7039 $1\logical_op__insn_type$2$next[6:0]$7057 + assign $0\logical_op__invert_in$10$next[0:0]$7040 $1\logical_op__invert_in$10$next[0:0]$7058 + assign $0\logical_op__invert_out$13$next[0:0]$7041 $1\logical_op__invert_out$13$next[0:0]$7059 + assign $0\logical_op__is_32bit$16$next[0:0]$7042 $1\logical_op__is_32bit$16$next[0:0]$7060 + assign $0\logical_op__is_signed$17$next[0:0]$7043 $1\logical_op__is_signed$17$next[0:0]$7061 + assign { } { } + assign { } { } + assign $0\logical_op__output_carry$15$next[0:0]$7046 $1\logical_op__output_carry$15$next[0:0]$7064 + assign { } { } + assign { } { } + assign $0\logical_op__write_cr0$14$next[0:0]$7049 $1\logical_op__write_cr0$14$next[0:0]$7067 + assign $0\logical_op__zero_a$11$next[0:0]$7050 $1\logical_op__zero_a$11$next[0:0]$7068 + assign $0\logical_op__imm_data__data$4$next[63:0]$7035 $2\logical_op__imm_data__data$4$next[63:0]$7069 + assign $0\logical_op__imm_data__ok$5$next[0:0]$7036 $2\logical_op__imm_data__ok$5$next[0:0]$7070 + assign $0\logical_op__oe__oe$8$next[0:0]$7044 $2\logical_op__oe__oe$8$next[0:0]$7071 + assign $0\logical_op__oe__ok$9$next[0:0]$7045 $2\logical_op__oe__ok$9$next[0:0]$7072 + assign $0\logical_op__rc__ok$7$next[0:0]$7047 $2\logical_op__rc__ok$7$next[0:0]$7073 + assign $0\logical_op__rc__rc$6$next[0:0]$7048 $2\logical_op__rc__rc$6$next[0:0]$7074 + attribute \src "libresoc.v:149230.5-149230.29" + switch \initial + attribute \src "libresoc.v:149230.9-149230.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\logical_op__insn$19$next[31:0]$7056 $1\logical_op__data_len$18$next[3:0]$7051 $1\logical_op__is_signed$17$next[0:0]$7061 $1\logical_op__is_32bit$16$next[0:0]$7060 $1\logical_op__output_carry$15$next[0:0]$7064 $1\logical_op__write_cr0$14$next[0:0]$7067 $1\logical_op__invert_out$13$next[0:0]$7059 $1\logical_op__input_carry$12$next[1:0]$7055 $1\logical_op__zero_a$11$next[0:0]$7068 $1\logical_op__invert_in$10$next[0:0]$7058 $1\logical_op__oe__ok$9$next[0:0]$7063 $1\logical_op__oe__oe$8$next[0:0]$7062 $1\logical_op__rc__ok$7$next[0:0]$7065 $1\logical_op__rc__rc$6$next[0:0]$7066 $1\logical_op__imm_data__ok$5$next[0:0]$7054 $1\logical_op__imm_data__data$4$next[63:0]$7053 $1\logical_op__fn_unit$3$next[12:0]$7052 $1\logical_op__insn_type$2$next[6:0]$7057 } { \logical_op__insn$69 \logical_op__data_len$68 \logical_op__is_signed$67 \logical_op__is_32bit$66 \logical_op__output_carry$65 \logical_op__write_cr0$64 \logical_op__invert_out$63 \logical_op__input_carry$62 \logical_op__zero_a$61 \logical_op__invert_in$60 \logical_op__oe__ok$59 \logical_op__oe__oe$58 \logical_op__rc__ok$57 \logical_op__rc__rc$56 \logical_op__imm_data__ok$55 \logical_op__imm_data__data$54 \logical_op__fn_unit$53 \logical_op__insn_type$52 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\logical_op__insn$19$next[31:0]$7056 $1\logical_op__data_len$18$next[3:0]$7051 $1\logical_op__is_signed$17$next[0:0]$7061 $1\logical_op__is_32bit$16$next[0:0]$7060 $1\logical_op__output_carry$15$next[0:0]$7064 $1\logical_op__write_cr0$14$next[0:0]$7067 $1\logical_op__invert_out$13$next[0:0]$7059 $1\logical_op__input_carry$12$next[1:0]$7055 $1\logical_op__zero_a$11$next[0:0]$7068 $1\logical_op__invert_in$10$next[0:0]$7058 $1\logical_op__oe__ok$9$next[0:0]$7063 $1\logical_op__oe__oe$8$next[0:0]$7062 $1\logical_op__rc__ok$7$next[0:0]$7065 $1\logical_op__rc__rc$6$next[0:0]$7066 $1\logical_op__imm_data__ok$5$next[0:0]$7054 $1\logical_op__imm_data__data$4$next[63:0]$7053 $1\logical_op__fn_unit$3$next[12:0]$7052 $1\logical_op__insn_type$2$next[6:0]$7057 } { \logical_op__insn$69 \logical_op__data_len$68 \logical_op__is_signed$67 \logical_op__is_32bit$66 \logical_op__output_carry$65 \logical_op__write_cr0$64 \logical_op__invert_out$63 \logical_op__input_carry$62 \logical_op__zero_a$61 \logical_op__invert_in$60 \logical_op__oe__ok$59 \logical_op__oe__oe$58 \logical_op__rc__ok$57 \logical_op__rc__rc$56 \logical_op__imm_data__ok$55 \logical_op__imm_data__data$54 \logical_op__fn_unit$53 \logical_op__insn_type$52 } + case + assign $1\logical_op__data_len$18$next[3:0]$7051 \logical_op__data_len$18 + assign $1\logical_op__fn_unit$3$next[12:0]$7052 \logical_op__fn_unit$3 + assign $1\logical_op__imm_data__data$4$next[63:0]$7053 \logical_op__imm_data__data$4 + assign $1\logical_op__imm_data__ok$5$next[0:0]$7054 \logical_op__imm_data__ok$5 + assign $1\logical_op__input_carry$12$next[1:0]$7055 \logical_op__input_carry$12 + assign $1\logical_op__insn$19$next[31:0]$7056 \logical_op__insn$19 + assign $1\logical_op__insn_type$2$next[6:0]$7057 \logical_op__insn_type$2 + assign $1\logical_op__invert_in$10$next[0:0]$7058 \logical_op__invert_in$10 + assign $1\logical_op__invert_out$13$next[0:0]$7059 \logical_op__invert_out$13 + assign $1\logical_op__is_32bit$16$next[0:0]$7060 \logical_op__is_32bit$16 + assign $1\logical_op__is_signed$17$next[0:0]$7061 \logical_op__is_signed$17 + assign $1\logical_op__oe__oe$8$next[0:0]$7062 \logical_op__oe__oe$8 + assign $1\logical_op__oe__ok$9$next[0:0]$7063 \logical_op__oe__ok$9 + assign $1\logical_op__output_carry$15$next[0:0]$7064 \logical_op__output_carry$15 + assign $1\logical_op__rc__ok$7$next[0:0]$7065 \logical_op__rc__ok$7 + assign $1\logical_op__rc__rc$6$next[0:0]$7066 \logical_op__rc__rc$6 + assign $1\logical_op__write_cr0$14$next[0:0]$7067 \logical_op__write_cr0$14 + assign $1\logical_op__zero_a$11$next[0:0]$7068 \logical_op__zero_a$11 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $2\logical_op__imm_data__data$4$next[63:0]$7069 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\logical_op__imm_data__ok$5$next[0:0]$7070 1'0 + assign $2\logical_op__rc__rc$6$next[0:0]$7074 1'0 + assign $2\logical_op__rc__ok$7$next[0:0]$7073 1'0 + assign $2\logical_op__oe__oe$8$next[0:0]$7071 1'0 + assign $2\logical_op__oe__ok$9$next[0:0]$7072 1'0 + case + assign $2\logical_op__imm_data__data$4$next[63:0]$7069 $1\logical_op__imm_data__data$4$next[63:0]$7053 + assign $2\logical_op__imm_data__ok$5$next[0:0]$7070 $1\logical_op__imm_data__ok$5$next[0:0]$7054 + assign $2\logical_op__oe__oe$8$next[0:0]$7071 $1\logical_op__oe__oe$8$next[0:0]$7062 + assign $2\logical_op__oe__ok$9$next[0:0]$7072 $1\logical_op__oe__ok$9$next[0:0]$7063 + assign $2\logical_op__rc__ok$7$next[0:0]$7073 $1\logical_op__rc__ok$7$next[0:0]$7065 + assign $2\logical_op__rc__rc$6$next[0:0]$7074 $1\logical_op__rc__rc$6$next[0:0]$7066 + end + sync always + update \logical_op__data_len$18$next $0\logical_op__data_len$18$next[3:0]$7033 + update \logical_op__fn_unit$3$next $0\logical_op__fn_unit$3$next[12:0]$7034 + update \logical_op__imm_data__data$4$next $0\logical_op__imm_data__data$4$next[63:0]$7035 + update \logical_op__imm_data__ok$5$next $0\logical_op__imm_data__ok$5$next[0:0]$7036 + update \logical_op__input_carry$12$next $0\logical_op__input_carry$12$next[1:0]$7037 + update \logical_op__insn$19$next $0\logical_op__insn$19$next[31:0]$7038 + update \logical_op__insn_type$2$next $0\logical_op__insn_type$2$next[6:0]$7039 + update \logical_op__invert_in$10$next $0\logical_op__invert_in$10$next[0:0]$7040 + update \logical_op__invert_out$13$next $0\logical_op__invert_out$13$next[0:0]$7041 + update \logical_op__is_32bit$16$next $0\logical_op__is_32bit$16$next[0:0]$7042 + update \logical_op__is_signed$17$next $0\logical_op__is_signed$17$next[0:0]$7043 + update \logical_op__oe__oe$8$next $0\logical_op__oe__oe$8$next[0:0]$7044 + update \logical_op__oe__ok$9$next $0\logical_op__oe__ok$9$next[0:0]$7045 + update \logical_op__output_carry$15$next $0\logical_op__output_carry$15$next[0:0]$7046 + update \logical_op__rc__ok$7$next $0\logical_op__rc__ok$7$next[0:0]$7047 + update \logical_op__rc__rc$6$next $0\logical_op__rc__rc$6$next[0:0]$7048 + update \logical_op__write_cr0$14$next $0\logical_op__write_cr0$14$next[0:0]$7049 + update \logical_op__zero_a$11$next $0\logical_op__zero_a$11$next[0:0]$7050 + end + attribute \src "libresoc.v:149271.3-149289.6" + process $proc$libresoc.v:149271$7075 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\o$20$next[63:0]$7076 $1\o$20$next[63:0]$7078 + assign { } { } + assign $0\o_ok$21$next[0:0]$7077 $2\o_ok$21$next[0:0]$7080 + attribute \src "libresoc.v:149272.5-149272.29" + switch \initial + attribute \src "libresoc.v:149272.9-149272.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\o_ok$21$next[0:0]$7079 $1\o$20$next[63:0]$7078 } { \o_ok$71 \o$70 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\o_ok$21$next[0:0]$7079 $1\o$20$next[63:0]$7078 } { \o_ok$71 \o$70 } + case + assign $1\o$20$next[63:0]$7078 \o$20 + assign $1\o_ok$21$next[0:0]$7079 \o_ok$21 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\o_ok$21$next[0:0]$7080 1'0 + case + assign $2\o_ok$21$next[0:0]$7080 $1\o_ok$21$next[0:0]$7079 + end + sync always + update \o$20$next $0\o$20$next[63:0]$7076 + update \o_ok$21$next $0\o_ok$21$next[0:0]$7077 + end + attribute \src "libresoc.v:149290.3-149308.6" + process $proc$libresoc.v:149290$7081 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\cr_a$22$next[3:0]$7082 $1\cr_a$22$next[3:0]$7084 + assign { } { } + assign $0\cr_a_ok$23$next[0:0]$7083 $2\cr_a_ok$23$next[0:0]$7086 + attribute \src "libresoc.v:149291.5-149291.29" + switch \initial + attribute \src "libresoc.v:149291.9-149291.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\cr_a_ok$23$next[0:0]$7085 $1\cr_a$22$next[3:0]$7084 } { \cr_a_ok$73 \cr_a$72 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\cr_a_ok$23$next[0:0]$7085 $1\cr_a$22$next[3:0]$7084 } { \cr_a_ok$73 \cr_a$72 } + case + assign $1\cr_a$22$next[3:0]$7084 \cr_a$22 + assign $1\cr_a_ok$23$next[0:0]$7085 \cr_a_ok$23 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_a_ok$23$next[0:0]$7086 1'0 + case + assign $2\cr_a_ok$23$next[0:0]$7086 $1\cr_a_ok$23$next[0:0]$7085 + end + sync always + update \cr_a$22$next $0\cr_a$22$next[3:0]$7082 + update \cr_a_ok$23$next $0\cr_a_ok$23$next[0:0]$7083 + end + connect \$49 $and$libresoc.v:149093$6977_Y + connect \p_ready_o \n_i_rdy_data + connect \n_valid_o \r_busy + connect { \cr_a_ok$73 \cr_a$72 } { \output_cr_a_ok \output_cr_a$45 } + connect { \o_ok$71 \o$70 } { \output_o_ok$44 \output_o$43 } + connect { \logical_op__insn$69 \logical_op__data_len$68 \logical_op__is_signed$67 \logical_op__is_32bit$66 \logical_op__output_carry$65 \logical_op__write_cr0$64 \logical_op__invert_out$63 \logical_op__input_carry$62 \logical_op__zero_a$61 \logical_op__invert_in$60 \logical_op__oe__ok$59 \logical_op__oe__oe$58 \logical_op__rc__ok$57 \logical_op__rc__rc$56 \logical_op__imm_data__ok$55 \logical_op__imm_data__data$54 \logical_op__fn_unit$53 \logical_op__insn_type$52 } { \output_logical_op__insn$42 \output_logical_op__data_len$41 \output_logical_op__is_signed$40 \output_logical_op__is_32bit$39 \output_logical_op__output_carry$38 \output_logical_op__write_cr0$37 \output_logical_op__invert_out$36 \output_logical_op__input_carry$35 \output_logical_op__zero_a$34 \output_logical_op__invert_in$33 \output_logical_op__oe__ok$32 \output_logical_op__oe__oe$31 \output_logical_op__rc__ok$30 \output_logical_op__rc__rc$29 \output_logical_op__imm_data__ok$28 \output_logical_op__imm_data__data$27 \output_logical_op__fn_unit$26 \output_logical_op__insn_type$25 } + connect \muxid$51 \output_muxid$24 + connect \p_valid_i_p_ready_o \$49 + connect \n_i_rdy_data \n_ready_i + connect \p_valid_i$48 \p_valid_i + connect { \xer_so_ok$47 \output_xer_so } { \xer_so_ok \xer_so } + connect { \cr_a_ok$46 \output_cr_a } { \cr_a_ok \cr_a } + connect { \output_o_ok \output_o } { \o_ok \o } + connect { \output_logical_op__insn \output_logical_op__data_len \output_logical_op__is_signed \output_logical_op__is_32bit \output_logical_op__output_carry \output_logical_op__write_cr0 \output_logical_op__invert_out \output_logical_op__input_carry \output_logical_op__zero_a \output_logical_op__invert_in \output_logical_op__oe__ok \output_logical_op__oe__oe \output_logical_op__rc__ok \output_logical_op__rc__rc \output_logical_op__imm_data__ok \output_logical_op__imm_data__data \output_logical_op__fn_unit \output_logical_op__insn_type } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } + connect \output_muxid \muxid +end +attribute \src "ls180.v:4.1-11026.10" +attribute \cells_not_processed 1 +module \ls180 + attribute \src "ls180.v:10350.1-10368.4" + wire width 6 $0$memwr$\mem$ls180.v:10352$1_ADDR[5:0]$2892 + attribute \src "ls180.v:10350.1-10368.4" + wire width 64 $0$memwr$\mem$ls180.v:10352$1_DATA[63:0]$2893 + attribute \src "ls180.v:10350.1-10368.4" + wire width 64 $0$memwr$\mem$ls180.v:10352$1_EN[63:0]$2894 + attribute \src "ls180.v:10350.1-10368.4" + wire width 6 $0$memwr$\mem$ls180.v:10354$2_ADDR[5:0]$2895 + attribute \src "ls180.v:10350.1-10368.4" + wire width 64 $0$memwr$\mem$ls180.v:10354$2_DATA[63:0]$2896 + attribute \src "ls180.v:10350.1-10368.4" + wire width 64 $0$memwr$\mem$ls180.v:10354$2_EN[63:0]$2897 + attribute \src "ls180.v:10350.1-10368.4" + wire width 6 $0$memwr$\mem$ls180.v:10356$3_ADDR[5:0]$2898 + attribute \src "ls180.v:10350.1-10368.4" + wire width 64 $0$memwr$\mem$ls180.v:10356$3_DATA[63:0]$2899 + attribute \src "ls180.v:10350.1-10368.4" + wire width 64 $0$memwr$\mem$ls180.v:10356$3_EN[63:0]$2900 + attribute \src "ls180.v:10350.1-10368.4" + wire width 6 $0$memwr$\mem$ls180.v:10358$4_ADDR[5:0]$2901 + attribute \src "ls180.v:10350.1-10368.4" + wire width 64 $0$memwr$\mem$ls180.v:10358$4_DATA[63:0]$2902 + attribute \src "ls180.v:10350.1-10368.4" + wire width 64 $0$memwr$\mem$ls180.v:10358$4_EN[63:0]$2903 + attribute \src "ls180.v:10350.1-10368.4" + wire width 6 $0$memwr$\mem$ls180.v:10360$5_ADDR[5:0]$2904 + attribute \src "ls180.v:10350.1-10368.4" + wire width 64 $0$memwr$\mem$ls180.v:10360$5_DATA[63:0]$2905 + attribute \src "ls180.v:10350.1-10368.4" + wire width 64 $0$memwr$\mem$ls180.v:10360$5_EN[63:0]$2906 + attribute \src "ls180.v:10350.1-10368.4" + wire width 6 $0$memwr$\mem$ls180.v:10362$6_ADDR[5:0]$2907 + attribute \src "ls180.v:10350.1-10368.4" + wire width 64 $0$memwr$\mem$ls180.v:10362$6_DATA[63:0]$2908 + attribute \src "ls180.v:10350.1-10368.4" + wire width 64 $0$memwr$\mem$ls180.v:10362$6_EN[63:0]$2909 + attribute \src "ls180.v:10350.1-10368.4" + wire width 6 $0$memwr$\mem$ls180.v:10364$7_ADDR[5:0]$2910 + attribute \src "ls180.v:10350.1-10368.4" + wire width 64 $0$memwr$\mem$ls180.v:10364$7_DATA[63:0]$2911 + attribute \src "ls180.v:10350.1-10368.4" + wire width 64 $0$memwr$\mem$ls180.v:10364$7_EN[63:0]$2912 + attribute \src "ls180.v:10350.1-10368.4" + wire width 6 $0$memwr$\mem$ls180.v:10366$8_ADDR[5:0]$2913 + attribute \src "ls180.v:10350.1-10368.4" + wire width 64 $0$memwr$\mem$ls180.v:10366$8_DATA[63:0]$2914 + attribute \src "ls180.v:10350.1-10368.4" + wire width 64 $0$memwr$\mem$ls180.v:10366$8_EN[63:0]$2915 + attribute \src "ls180.v:10378.1-10396.4" + wire width 6 $0$memwr$\mem_1$ls180.v:10380$9_ADDR[5:0]$2918 + attribute \src "ls180.v:10378.1-10396.4" + wire width 64 $0$memwr$\mem_1$ls180.v:10380$9_DATA[63:0]$2919 + attribute \src "ls180.v:10378.1-10396.4" + wire width 64 $0$memwr$\mem_1$ls180.v:10380$9_EN[63:0]$2920 + attribute \src "ls180.v:10378.1-10396.4" + wire width 6 $0$memwr$\mem_1$ls180.v:10382$10_ADDR[5:0]$2921 + attribute \src "ls180.v:10378.1-10396.4" + wire width 64 $0$memwr$\mem_1$ls180.v:10382$10_DATA[63:0]$2922 + attribute \src "ls180.v:10378.1-10396.4" + wire width 64 $0$memwr$\mem_1$ls180.v:10382$10_EN[63:0]$2923 + attribute \src "ls180.v:10378.1-10396.4" + wire width 6 $0$memwr$\mem_1$ls180.v:10384$11_ADDR[5:0]$2924 + attribute \src "ls180.v:10378.1-10396.4" + wire width 64 $0$memwr$\mem_1$ls180.v:10384$11_DATA[63:0]$2925 + attribute \src "ls180.v:10378.1-10396.4" + wire width 64 $0$memwr$\mem_1$ls180.v:10384$11_EN[63:0]$2926 + attribute \src "ls180.v:10378.1-10396.4" + wire width 6 $0$memwr$\mem_1$ls180.v:10386$12_ADDR[5:0]$2927 + attribute \src "ls180.v:10378.1-10396.4" + wire width 64 $0$memwr$\mem_1$ls180.v:10386$12_DATA[63:0]$2928 + attribute \src "ls180.v:10378.1-10396.4" + wire width 64 $0$memwr$\mem_1$ls180.v:10386$12_EN[63:0]$2929 + attribute \src "ls180.v:10378.1-10396.4" + wire width 6 $0$memwr$\mem_1$ls180.v:10388$13_ADDR[5:0]$2930 + attribute \src "ls180.v:10378.1-10396.4" + wire width 64 $0$memwr$\mem_1$ls180.v:10388$13_DATA[63:0]$2931 + attribute \src "ls180.v:10378.1-10396.4" + wire width 64 $0$memwr$\mem_1$ls180.v:10388$13_EN[63:0]$2932 + attribute \src "ls180.v:10378.1-10396.4" + wire width 6 $0$memwr$\mem_1$ls180.v:10390$14_ADDR[5:0]$2933 + attribute \src "ls180.v:10378.1-10396.4" + wire width 64 $0$memwr$\mem_1$ls180.v:10390$14_DATA[63:0]$2934 + attribute \src "ls180.v:10378.1-10396.4" + wire width 64 $0$memwr$\mem_1$ls180.v:10390$14_EN[63:0]$2935 + attribute \src "ls180.v:10378.1-10396.4" + wire width 6 $0$memwr$\mem_1$ls180.v:10392$15_ADDR[5:0]$2936 + attribute \src "ls180.v:10378.1-10396.4" + wire width 64 $0$memwr$\mem_1$ls180.v:10392$15_DATA[63:0]$2937 + attribute \src "ls180.v:10378.1-10396.4" + wire width 64 $0$memwr$\mem_1$ls180.v:10392$15_EN[63:0]$2938 + attribute \src "ls180.v:10378.1-10396.4" + wire width 6 $0$memwr$\mem_1$ls180.v:10394$16_ADDR[5:0]$2939 + attribute \src "ls180.v:10378.1-10396.4" + wire width 64 $0$memwr$\mem_1$ls180.v:10394$16_DATA[63:0]$2940 + attribute \src "ls180.v:10378.1-10396.4" + wire width 64 $0$memwr$\mem_1$ls180.v:10394$16_EN[63:0]$2941 + attribute \src "ls180.v:10406.1-10424.4" + wire width 6 $0$memwr$\mem_2$ls180.v:10408$17_ADDR[5:0]$2944 + attribute \src "ls180.v:10406.1-10424.4" + wire width 64 $0$memwr$\mem_2$ls180.v:10408$17_DATA[63:0]$2945 + attribute \src "ls180.v:10406.1-10424.4" + wire width 64 $0$memwr$\mem_2$ls180.v:10408$17_EN[63:0]$2946 + attribute \src "ls180.v:10406.1-10424.4" + wire width 6 $0$memwr$\mem_2$ls180.v:10410$18_ADDR[5:0]$2947 + attribute \src "ls180.v:10406.1-10424.4" + wire width 64 $0$memwr$\mem_2$ls180.v:10410$18_DATA[63:0]$2948 + attribute \src "ls180.v:10406.1-10424.4" + wire width 64 $0$memwr$\mem_2$ls180.v:10410$18_EN[63:0]$2949 + attribute \src "ls180.v:10406.1-10424.4" + wire width 6 $0$memwr$\mem_2$ls180.v:10412$19_ADDR[5:0]$2950 + attribute \src "ls180.v:10406.1-10424.4" + wire width 64 $0$memwr$\mem_2$ls180.v:10412$19_DATA[63:0]$2951 + attribute \src "ls180.v:10406.1-10424.4" + wire width 64 $0$memwr$\mem_2$ls180.v:10412$19_EN[63:0]$2952 + attribute \src "ls180.v:10406.1-10424.4" + wire width 6 $0$memwr$\mem_2$ls180.v:10414$20_ADDR[5:0]$2953 + attribute \src "ls180.v:10406.1-10424.4" + wire width 64 $0$memwr$\mem_2$ls180.v:10414$20_DATA[63:0]$2954 + attribute \src "ls180.v:10406.1-10424.4" + wire width 64 $0$memwr$\mem_2$ls180.v:10414$20_EN[63:0]$2955 + attribute \src "ls180.v:10406.1-10424.4" + wire width 6 $0$memwr$\mem_2$ls180.v:10416$21_ADDR[5:0]$2956 + attribute \src "ls180.v:10406.1-10424.4" + wire width 64 $0$memwr$\mem_2$ls180.v:10416$21_DATA[63:0]$2957 + attribute \src "ls180.v:10406.1-10424.4" + wire width 64 $0$memwr$\mem_2$ls180.v:10416$21_EN[63:0]$2958 + attribute \src "ls180.v:10406.1-10424.4" + wire width 6 $0$memwr$\mem_2$ls180.v:10418$22_ADDR[5:0]$2959 + attribute \src "ls180.v:10406.1-10424.4" + wire width 64 $0$memwr$\mem_2$ls180.v:10418$22_DATA[63:0]$2960 + attribute \src "ls180.v:10406.1-10424.4" + wire width 64 $0$memwr$\mem_2$ls180.v:10418$22_EN[63:0]$2961 + attribute \src "ls180.v:10406.1-10424.4" + wire width 6 $0$memwr$\mem_2$ls180.v:10420$23_ADDR[5:0]$2962 + attribute \src "ls180.v:10406.1-10424.4" + wire width 64 $0$memwr$\mem_2$ls180.v:10420$23_DATA[63:0]$2963 + attribute \src "ls180.v:10406.1-10424.4" + wire width 64 $0$memwr$\mem_2$ls180.v:10420$23_EN[63:0]$2964 + attribute \src "ls180.v:10406.1-10424.4" + wire width 6 $0$memwr$\mem_2$ls180.v:10422$24_ADDR[5:0]$2965 + attribute \src "ls180.v:10406.1-10424.4" + wire width 64 $0$memwr$\mem_2$ls180.v:10422$24_DATA[63:0]$2966 + attribute \src "ls180.v:10406.1-10424.4" + wire width 64 $0$memwr$\mem_2$ls180.v:10422$24_EN[63:0]$2967 + attribute \src "ls180.v:10434.1-10452.4" + wire width 6 $0$memwr$\mem_3$ls180.v:10436$25_ADDR[5:0]$2970 + attribute \src "ls180.v:10434.1-10452.4" + wire width 64 $0$memwr$\mem_3$ls180.v:10436$25_DATA[63:0]$2971 + attribute \src "ls180.v:10434.1-10452.4" + wire width 64 $0$memwr$\mem_3$ls180.v:10436$25_EN[63:0]$2972 + attribute \src "ls180.v:10434.1-10452.4" + wire width 6 $0$memwr$\mem_3$ls180.v:10438$26_ADDR[5:0]$2973 + attribute \src "ls180.v:10434.1-10452.4" + wire width 64 $0$memwr$\mem_3$ls180.v:10438$26_DATA[63:0]$2974 + attribute \src "ls180.v:10434.1-10452.4" + wire width 64 $0$memwr$\mem_3$ls180.v:10438$26_EN[63:0]$2975 + attribute \src "ls180.v:10434.1-10452.4" + wire width 6 $0$memwr$\mem_3$ls180.v:10440$27_ADDR[5:0]$2976 + attribute \src "ls180.v:10434.1-10452.4" + wire width 64 $0$memwr$\mem_3$ls180.v:10440$27_DATA[63:0]$2977 + attribute \src "ls180.v:10434.1-10452.4" + wire width 64 $0$memwr$\mem_3$ls180.v:10440$27_EN[63:0]$2978 + attribute \src "ls180.v:10434.1-10452.4" + wire width 6 $0$memwr$\mem_3$ls180.v:10442$28_ADDR[5:0]$2979 + attribute \src "ls180.v:10434.1-10452.4" + wire width 64 $0$memwr$\mem_3$ls180.v:10442$28_DATA[63:0]$2980 + attribute \src "ls180.v:10434.1-10452.4" + wire width 64 $0$memwr$\mem_3$ls180.v:10442$28_EN[63:0]$2981 + attribute \src "ls180.v:10434.1-10452.4" + wire width 6 $0$memwr$\mem_3$ls180.v:10444$29_ADDR[5:0]$2982 + attribute \src "ls180.v:10434.1-10452.4" + wire width 64 $0$memwr$\mem_3$ls180.v:10444$29_DATA[63:0]$2983 + attribute \src "ls180.v:10434.1-10452.4" + wire width 64 $0$memwr$\mem_3$ls180.v:10444$29_EN[63:0]$2984 + attribute \src "ls180.v:10434.1-10452.4" + wire width 6 $0$memwr$\mem_3$ls180.v:10446$30_ADDR[5:0]$2985 + attribute \src "ls180.v:10434.1-10452.4" + wire width 64 $0$memwr$\mem_3$ls180.v:10446$30_DATA[63:0]$2986 + attribute \src "ls180.v:10434.1-10452.4" + wire width 64 $0$memwr$\mem_3$ls180.v:10446$30_EN[63:0]$2987 + attribute \src "ls180.v:10434.1-10452.4" + wire width 6 $0$memwr$\mem_3$ls180.v:10448$31_ADDR[5:0]$2988 + attribute \src "ls180.v:10434.1-10452.4" + wire width 64 $0$memwr$\mem_3$ls180.v:10448$31_DATA[63:0]$2989 + attribute \src "ls180.v:10434.1-10452.4" + wire width 64 $0$memwr$\mem_3$ls180.v:10448$31_EN[63:0]$2990 + attribute \src "ls180.v:10434.1-10452.4" + wire width 6 $0$memwr$\mem_3$ls180.v:10450$32_ADDR[5:0]$2991 + attribute \src "ls180.v:10434.1-10452.4" + wire width 64 $0$memwr$\mem_3$ls180.v:10450$32_DATA[63:0]$2992 + attribute \src "ls180.v:10434.1-10452.4" + wire width 64 $0$memwr$\mem_3$ls180.v:10450$32_EN[63:0]$2993 + attribute \src "ls180.v:10462.1-10480.4" + wire width 6 $0$memwr$\mem_4$ls180.v:10464$33_ADDR[5:0]$2996 + attribute \src "ls180.v:10462.1-10480.4" + wire width 64 $0$memwr$\mem_4$ls180.v:10464$33_DATA[63:0]$2997 + attribute \src "ls180.v:10462.1-10480.4" + wire width 64 $0$memwr$\mem_4$ls180.v:10464$33_EN[63:0]$2998 + attribute \src "ls180.v:10462.1-10480.4" + wire width 6 $0$memwr$\mem_4$ls180.v:10466$34_ADDR[5:0]$2999 + attribute \src "ls180.v:10462.1-10480.4" + wire width 64 $0$memwr$\mem_4$ls180.v:10466$34_DATA[63:0]$3000 + attribute \src "ls180.v:10462.1-10480.4" + wire width 64 $0$memwr$\mem_4$ls180.v:10466$34_EN[63:0]$3001 + attribute \src "ls180.v:10462.1-10480.4" + wire width 6 $0$memwr$\mem_4$ls180.v:10468$35_ADDR[5:0]$3002 + attribute \src "ls180.v:10462.1-10480.4" + wire width 64 $0$memwr$\mem_4$ls180.v:10468$35_DATA[63:0]$3003 + attribute \src "ls180.v:10462.1-10480.4" + wire width 64 $0$memwr$\mem_4$ls180.v:10468$35_EN[63:0]$3004 + attribute \src "ls180.v:10462.1-10480.4" + wire width 6 $0$memwr$\mem_4$ls180.v:10470$36_ADDR[5:0]$3005 + attribute \src "ls180.v:10462.1-10480.4" + wire width 64 $0$memwr$\mem_4$ls180.v:10470$36_DATA[63:0]$3006 + attribute \src "ls180.v:10462.1-10480.4" + wire width 64 $0$memwr$\mem_4$ls180.v:10470$36_EN[63:0]$3007 + attribute \src "ls180.v:10462.1-10480.4" + wire width 6 $0$memwr$\mem_4$ls180.v:10472$37_ADDR[5:0]$3008 + attribute \src "ls180.v:10462.1-10480.4" + wire width 64 $0$memwr$\mem_4$ls180.v:10472$37_DATA[63:0]$3009 + attribute \src "ls180.v:10462.1-10480.4" + wire width 64 $0$memwr$\mem_4$ls180.v:10472$37_EN[63:0]$3010 + attribute \src "ls180.v:10462.1-10480.4" + wire width 6 $0$memwr$\mem_4$ls180.v:10474$38_ADDR[5:0]$3011 + attribute \src "ls180.v:10462.1-10480.4" + wire width 64 $0$memwr$\mem_4$ls180.v:10474$38_DATA[63:0]$3012 + attribute \src "ls180.v:10462.1-10480.4" + wire width 64 $0$memwr$\mem_4$ls180.v:10474$38_EN[63:0]$3013 + attribute \src "ls180.v:10462.1-10480.4" + wire width 6 $0$memwr$\mem_4$ls180.v:10476$39_ADDR[5:0]$3014 + attribute \src "ls180.v:10462.1-10480.4" + wire width 64 $0$memwr$\mem_4$ls180.v:10476$39_DATA[63:0]$3015 + attribute \src "ls180.v:10462.1-10480.4" + wire width 64 $0$memwr$\mem_4$ls180.v:10476$39_EN[63:0]$3016 + attribute \src "ls180.v:10462.1-10480.4" + wire width 6 $0$memwr$\mem_4$ls180.v:10478$40_ADDR[5:0]$3017 + attribute \src "ls180.v:10462.1-10480.4" + wire width 64 $0$memwr$\mem_4$ls180.v:10478$40_DATA[63:0]$3018 + attribute \src "ls180.v:10462.1-10480.4" + wire width 64 $0$memwr$\mem_4$ls180.v:10478$40_EN[63:0]$3019 + attribute \src "ls180.v:10490.1-10494.4" + wire width 3 $0$memwr$\storage$ls180.v:10492$41_ADDR[2:0]$3022 + attribute \src "ls180.v:10490.1-10494.4" + wire width 25 $0$memwr$\storage$ls180.v:10492$41_DATA[24:0]$3023 + attribute \src "ls180.v:10490.1-10494.4" + wire width 25 $0$memwr$\storage$ls180.v:10492$41_EN[24:0]$3024 + attribute \src "ls180.v:10504.1-10508.4" + wire width 3 $0$memwr$\storage_1$ls180.v:10506$42_ADDR[2:0]$3029 + attribute \src "ls180.v:10504.1-10508.4" + wire width 25 $0$memwr$\storage_1$ls180.v:10506$42_DATA[24:0]$3030 + attribute \src "ls180.v:10504.1-10508.4" + wire width 25 $0$memwr$\storage_1$ls180.v:10506$42_EN[24:0]$3031 + attribute \src "ls180.v:10518.1-10522.4" + wire width 3 $0$memwr$\storage_2$ls180.v:10520$43_ADDR[2:0]$3036 + attribute \src "ls180.v:10518.1-10522.4" + wire width 25 $0$memwr$\storage_2$ls180.v:10520$43_DATA[24:0]$3037 + attribute \src "ls180.v:10518.1-10522.4" + wire width 25 $0$memwr$\storage_2$ls180.v:10520$43_EN[24:0]$3038 + attribute \src "ls180.v:10532.1-10536.4" + wire width 3 $0$memwr$\storage_3$ls180.v:10534$44_ADDR[2:0]$3043 + attribute \src "ls180.v:10532.1-10536.4" + wire width 25 $0$memwr$\storage_3$ls180.v:10534$44_DATA[24:0]$3044 + attribute \src "ls180.v:10532.1-10536.4" + wire width 25 $0$memwr$\storage_3$ls180.v:10534$44_EN[24:0]$3045 + attribute \src "ls180.v:10547.1-10551.4" + wire width 4 $0$memwr$\storage_4$ls180.v:10549$45_ADDR[3:0]$3050 + attribute \src "ls180.v:10547.1-10551.4" + wire width 10 $0$memwr$\storage_4$ls180.v:10549$45_DATA[9:0]$3051 + attribute \src "ls180.v:10547.1-10551.4" + wire width 10 $0$memwr$\storage_4$ls180.v:10549$45_EN[9:0]$3052 + attribute \src "ls180.v:10564.1-10568.4" + wire width 4 $0$memwr$\storage_5$ls180.v:10566$46_ADDR[3:0]$3057 + attribute \src "ls180.v:10564.1-10568.4" + wire width 10 $0$memwr$\storage_5$ls180.v:10566$46_DATA[9:0]$3058 + attribute \src "ls180.v:10564.1-10568.4" + wire width 10 $0$memwr$\storage_5$ls180.v:10566$46_EN[9:0]$3059 + attribute \src "ls180.v:10580.1-10584.4" + wire width 5 $0$memwr$\storage_6$ls180.v:10582$47_ADDR[4:0]$3064 + attribute \src "ls180.v:10580.1-10584.4" + wire width 10 $0$memwr$\storage_6$ls180.v:10582$47_DATA[9:0]$3065 + attribute \src "ls180.v:10580.1-10584.4" + wire width 10 $0$memwr$\storage_6$ls180.v:10582$47_EN[9:0]$3066 + attribute \src "ls180.v:10594.1-10598.4" + wire width 5 $0$memwr$\storage_7$ls180.v:10596$48_ADDR[4:0]$3071 + attribute \src "ls180.v:10594.1-10598.4" + wire width 10 $0$memwr$\storage_7$ls180.v:10596$48_DATA[9:0]$3072 + attribute \src "ls180.v:10594.1-10598.4" + wire width 10 $0$memwr$\storage_7$ls180.v:10596$48_EN[9:0]$3073 + attribute \src "ls180.v:3399.1-3492.4" + wire width 3 $0\builder_bankmachine0_next_state[2:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 3 $0\builder_bankmachine0_state[2:0] + attribute \src "ls180.v:3556.1-3649.4" + wire width 3 $0\builder_bankmachine1_next_state[2:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 3 $0\builder_bankmachine1_state[2:0] + attribute \src "ls180.v:3713.1-3806.4" + wire width 3 $0\builder_bankmachine2_next_state[2:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 3 $0\builder_bankmachine2_state[2:0] + attribute \src "ls180.v:3870.1-3963.4" + wire width 3 $0\builder_bankmachine3_next_state[2:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 3 $0\builder_bankmachine3_state[2:0] + attribute \src "ls180.v:6788.1-6804.4" + wire $0\builder_comb_rhs_array_muxed0[0:0] + attribute \src "ls180.v:7009.1-7025.4" + wire $0\builder_comb_rhs_array_muxed10[0:0] + attribute \src "ls180.v:7026.1-7042.4" + wire $0\builder_comb_rhs_array_muxed11[0:0] + attribute \src "ls180.v:7094.1-7101.4" + wire width 22 $0\builder_comb_rhs_array_muxed12[21:0] + attribute \src "ls180.v:7102.1-7109.4" + wire $0\builder_comb_rhs_array_muxed13[0:0] + attribute \src "ls180.v:7110.1-7117.4" + wire $0\builder_comb_rhs_array_muxed14[0:0] + attribute \src "ls180.v:7118.1-7125.4" + wire width 22 $0\builder_comb_rhs_array_muxed15[21:0] + attribute \src "ls180.v:7126.1-7133.4" + wire $0\builder_comb_rhs_array_muxed16[0:0] + attribute \src "ls180.v:7134.1-7141.4" + wire $0\builder_comb_rhs_array_muxed17[0:0] + attribute \src "ls180.v:7142.1-7149.4" + wire width 22 $0\builder_comb_rhs_array_muxed18[21:0] + attribute \src "ls180.v:7150.1-7157.4" + wire $0\builder_comb_rhs_array_muxed19[0:0] + attribute \src "ls180.v:6805.1-6821.4" + wire width 13 $0\builder_comb_rhs_array_muxed1[12:0] + attribute \src "ls180.v:7158.1-7165.4" + wire $0\builder_comb_rhs_array_muxed20[0:0] + attribute \src "ls180.v:7166.1-7173.4" + wire width 22 $0\builder_comb_rhs_array_muxed21[21:0] + attribute \src "ls180.v:7174.1-7181.4" + wire $0\builder_comb_rhs_array_muxed22[0:0] + attribute \src "ls180.v:7182.1-7189.4" + wire $0\builder_comb_rhs_array_muxed23[0:0] + attribute \src "ls180.v:7190.1-7209.4" + wire width 32 $0\builder_comb_rhs_array_muxed24[31:0] + attribute \src "ls180.v:7210.1-7229.4" + wire width 64 $0\builder_comb_rhs_array_muxed25[63:0] + attribute \src "ls180.v:7230.1-7249.4" + wire width 8 $0\builder_comb_rhs_array_muxed26[7:0] + attribute \src "ls180.v:7250.1-7269.4" + wire $0\builder_comb_rhs_array_muxed27[0:0] + attribute \src "ls180.v:7270.1-7289.4" + wire $0\builder_comb_rhs_array_muxed28[0:0] + attribute \src "ls180.v:7290.1-7309.4" + wire $0\builder_comb_rhs_array_muxed29[0:0] + attribute \src "ls180.v:6822.1-6838.4" + wire width 2 $0\builder_comb_rhs_array_muxed2[1:0] + attribute \src "ls180.v:7310.1-7329.4" + wire width 3 $0\builder_comb_rhs_array_muxed30[2:0] + attribute \src "ls180.v:7330.1-7349.4" + wire width 2 $0\builder_comb_rhs_array_muxed31[1:0] + attribute \src "ls180.v:6839.1-6855.4" + wire $0\builder_comb_rhs_array_muxed3[0:0] + attribute \src "ls180.v:6856.1-6872.4" + wire $0\builder_comb_rhs_array_muxed4[0:0] + attribute \src "ls180.v:6873.1-6889.4" + wire $0\builder_comb_rhs_array_muxed5[0:0] + attribute \src "ls180.v:6941.1-6957.4" + wire $0\builder_comb_rhs_array_muxed6[0:0] + attribute \src "ls180.v:6958.1-6974.4" + wire width 13 $0\builder_comb_rhs_array_muxed7[12:0] + attribute \src "ls180.v:6975.1-6991.4" + wire width 2 $0\builder_comb_rhs_array_muxed8[1:0] + attribute \src "ls180.v:6992.1-7008.4" + wire $0\builder_comb_rhs_array_muxed9[0:0] + attribute \src "ls180.v:6890.1-6906.4" + wire $0\builder_comb_t_array_muxed0[0:0] + attribute \src "ls180.v:6907.1-6923.4" + wire $0\builder_comb_t_array_muxed1[0:0] + attribute \src "ls180.v:6924.1-6940.4" + wire $0\builder_comb_t_array_muxed2[0:0] + attribute \src "ls180.v:7043.1-7059.4" + wire $0\builder_comb_t_array_muxed3[0:0] + attribute \src "ls180.v:7060.1-7076.4" + wire $0\builder_comb_t_array_muxed4[0:0] + attribute \src "ls180.v:7077.1-7093.4" + wire $0\builder_comb_t_array_muxed5[0:0] + attribute \src "ls180.v:2903.1-2949.4" + wire $0\builder_converter0_next_state[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\builder_converter0_state[0:0] + attribute \src "ls180.v:2963.1-3009.4" + wire $0\builder_converter1_next_state[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\builder_converter1_state[0:0] + attribute \src "ls180.v:3023.1-3069.4" + wire $0\builder_converter2_next_state[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\builder_converter2_state[0:0] + attribute \src "ls180.v:4216.1-4262.4" + wire $0\builder_converter_next_state[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\builder_converter_state[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 20 $0\builder_count[19:0] + attribute \src "ls180.v:6028.1-6039.4" + wire $0\builder_error[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 3 $0\builder_grant[2:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 8 $0\builder_interface0_bank_bus_dat_r[7:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 8 $0\builder_interface10_bank_bus_dat_r[7:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 8 $0\builder_interface11_bank_bus_dat_r[7:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 8 $0\builder_interface12_bank_bus_dat_r[7:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 8 $0\builder_interface13_bank_bus_dat_r[7:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 8 $0\builder_interface14_bank_bus_dat_r[7:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 8 $0\builder_interface1_bank_bus_dat_r[7:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 8 $0\builder_interface2_bank_bus_dat_r[7:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 8 $0\builder_interface3_bank_bus_dat_r[7:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 8 $0\builder_interface4_bank_bus_dat_r[7:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 8 $0\builder_interface5_bank_bus_dat_r[7:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 8 $0\builder_interface6_bank_bus_dat_r[7:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 8 $0\builder_interface7_bank_bus_dat_r[7:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 8 $0\builder_interface8_bank_bus_dat_r[7:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 8 $0\builder_interface9_bank_bus_dat_r[7:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 14 $0\builder_libresocsim_adr[13:0] + attribute \src "ls180.v:5845.1-5881.4" + wire width 14 $0\builder_libresocsim_adr_next_value1[13:0] + attribute \src "ls180.v:5845.1-5881.4" + wire $0\builder_libresocsim_adr_next_value_ce1[0:0] + attribute \src "ls180.v:1990.5-1990.55" + wire $0\builder_libresocsim_converted_interface_ack[0:0] + attribute \src "ls180.v:1986.12-1986.65" + wire width 64 $0\builder_libresocsim_converted_interface_dat_r[63:0] + attribute \src "ls180.v:1994.5-1994.55" + wire $0\builder_libresocsim_converted_interface_err[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 8 $0\builder_libresocsim_dat_w[7:0] + attribute \src "ls180.v:5845.1-5881.4" + wire width 8 $0\builder_libresocsim_dat_w_next_value0[7:0] + attribute \src "ls180.v:5845.1-5881.4" + wire $0\builder_libresocsim_dat_w_next_value_ce0[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\builder_libresocsim_we[0:0] + attribute \src "ls180.v:5845.1-5881.4" + wire $0\builder_libresocsim_we_next_value2[0:0] + attribute \src "ls180.v:5845.1-5881.4" + wire $0\builder_libresocsim_we_next_value_ce2[0:0] + attribute \src "ls180.v:5845.1-5881.4" + wire $0\builder_libresocsim_wishbone_ack[0:0] + attribute \src "ls180.v:1976.12-1976.52" + wire width 30 $0\builder_libresocsim_wishbone_adr[29:0] + attribute \src "ls180.v:1980.5-1980.44" + wire $0\builder_libresocsim_wishbone_cyc[0:0] + attribute \src "ls180.v:5845.1-5881.4" + wire width 32 $0\builder_libresocsim_wishbone_dat_r[31:0] + attribute \src "ls180.v:1977.12-1977.54" + wire width 32 $0\builder_libresocsim_wishbone_dat_w[31:0] + attribute \src "ls180.v:1979.11-1979.50" + wire width 4 $0\builder_libresocsim_wishbone_sel[3:0] + attribute \src "ls180.v:1981.5-1981.44" + wire $0\builder_libresocsim_wishbone_stb[0:0] + attribute \src "ls180.v:1983.5-1983.43" + wire $0\builder_libresocsim_wishbone_we[0:0] + attribute \src "ls180.v:1875.5-1875.27" + wire $0\builder_locked0[0:0] + attribute \src "ls180.v:1876.5-1876.27" + wire $0\builder_locked1[0:0] + attribute \src "ls180.v:1877.5-1877.27" + wire $0\builder_locked2[0:0] + attribute \src "ls180.v:1878.5-1878.27" + wire $0\builder_locked3[0:0] + attribute \src "ls180.v:4088.1-4160.4" + wire width 3 $0\builder_multiplexer_next_state[2:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 3 $0\builder_multiplexer_state[2:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\builder_multiregimpl0_regs0[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\builder_multiregimpl0_regs1[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\builder_multiregimpl10_regs0[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\builder_multiregimpl10_regs1[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\builder_multiregimpl11_regs0[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\builder_multiregimpl11_regs1[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\builder_multiregimpl12_regs0[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\builder_multiregimpl12_regs1[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\builder_multiregimpl13_regs0[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\builder_multiregimpl13_regs1[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\builder_multiregimpl14_regs0[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\builder_multiregimpl14_regs1[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\builder_multiregimpl15_regs0[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\builder_multiregimpl15_regs1[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\builder_multiregimpl16_regs0[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\builder_multiregimpl16_regs1[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\builder_multiregimpl1_regs0[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\builder_multiregimpl1_regs1[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\builder_multiregimpl2_regs0[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\builder_multiregimpl2_regs1[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\builder_multiregimpl3_regs0[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\builder_multiregimpl3_regs1[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\builder_multiregimpl4_regs0[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\builder_multiregimpl4_regs1[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\builder_multiregimpl5_regs0[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\builder_multiregimpl5_regs1[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\builder_multiregimpl6_regs0[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\builder_multiregimpl6_regs1[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\builder_multiregimpl7_regs0[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\builder_multiregimpl7_regs1[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\builder_multiregimpl8_regs0[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\builder_multiregimpl8_regs1[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\builder_multiregimpl9_regs0[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\builder_multiregimpl9_regs1[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\builder_new_master_rdata_valid0[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\builder_new_master_rdata_valid1[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\builder_new_master_rdata_valid2[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\builder_new_master_rdata_valid3[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\builder_new_master_wdata_ready[0:0] + attribute \src "ls180.v:5845.1-5881.4" + wire width 2 $0\builder_next_state[1:0] + attribute \src "ls180.v:3305.1-3335.4" + wire width 2 $0\builder_refresher_next_state[1:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 2 $0\builder_refresher_state[1:0] + attribute \src "ls180.v:5643.1-5682.4" + wire width 2 $0\builder_sdblock2memdma_next_state[1:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 2 $0\builder_sdblock2memdma_state[1:0] + attribute \src "ls180.v:5210.1-5289.4" + wire $0\builder_sdcore_crcupstreaminserter_next_state[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\builder_sdcore_crcupstreaminserter_state[0:0] + attribute \src "ls180.v:5392.1-5582.4" + wire width 3 $0\builder_sdcore_fsm_next_state[2:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 3 $0\builder_sdcore_fsm_state[2:0] + attribute \src "ls180.v:5702.1-5739.4" + wire $0\builder_sdmem2blockdma_fsm_next_state[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\builder_sdmem2blockdma_fsm_state[0:0] + attribute \src "ls180.v:5740.1-5776.4" + wire width 2 $0\builder_sdmem2blockdma_resetinserter_next_state[1:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 2 $0\builder_sdmem2blockdma_resetinserter_state[1:0] + attribute \src "ls180.v:4885.1-4957.4" + wire width 3 $0\builder_sdphy_fsm_next_state[2:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 3 $0\builder_sdphy_fsm_state[2:0] + attribute \src "ls180.v:4730.1-4823.4" + wire width 3 $0\builder_sdphy_sdphycmdr_next_state[2:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 3 $0\builder_sdphy_sdphycmdr_state[2:0] + attribute \src "ls180.v:4620.1-4696.4" + wire width 2 $0\builder_sdphy_sdphycmdw_next_state[1:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 2 $0\builder_sdphy_sdphycmdw_state[1:0] + attribute \src "ls180.v:4857.1-4884.4" + wire $0\builder_sdphy_sdphycrcr_next_state[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\builder_sdphy_sdphycrcr_state[0:0] + attribute \src "ls180.v:4991.1-5092.4" + wire width 3 $0\builder_sdphy_sdphydatar_next_state[2:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 3 $0\builder_sdphy_sdphydatar_state[2:0] + attribute \src "ls180.v:4586.1-4619.4" + wire $0\builder_sdphy_sdphyinit_next_state[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\builder_sdphy_sdphyinit_state[0:0] + attribute \src "ls180.v:6028.1-6039.4" + wire $0\builder_shared_ack[0:0] + attribute \src "ls180.v:6028.1-6039.4" + wire width 32 $0\builder_shared_dat_r[31:0] + attribute \src "ls180.v:5906.1-5921.4" + wire width 13 $0\builder_slave_sel[12:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 13 $0\builder_slave_sel_r[12:0] + attribute \src "ls180.v:4417.1-4465.4" + wire width 2 $0\builder_spimaster0_next_state[1:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 2 $0\builder_spimaster0_state[1:0] + attribute \src "ls180.v:4476.1-4524.4" + wire width 2 $0\builder_spimaster1_next_state[1:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 2 $0\builder_spimaster1_state[1:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 2 $0\builder_state[1:0] + attribute \src "ls180.v:7469.1-7497.4" + wire $0\builder_sync_f_array_muxed0[0:0] + attribute \src "ls180.v:7498.1-7526.4" + wire $0\builder_sync_f_array_muxed1[0:0] + attribute \src "ls180.v:7350.1-7366.4" + wire width 2 $0\builder_sync_rhs_array_muxed0[1:0] + attribute \src "ls180.v:7367.1-7383.4" + wire width 13 $0\builder_sync_rhs_array_muxed1[12:0] + attribute \src "ls180.v:7384.1-7400.4" + wire $0\builder_sync_rhs_array_muxed2[0:0] + attribute \src "ls180.v:7401.1-7417.4" + wire $0\builder_sync_rhs_array_muxed3[0:0] + attribute \src "ls180.v:7418.1-7434.4" + wire $0\builder_sync_rhs_array_muxed4[0:0] + attribute \src "ls180.v:7435.1-7451.4" + wire $0\builder_sync_rhs_array_muxed5[0:0] + attribute \src "ls180.v:7452.1-7468.4" + wire $0\builder_sync_rhs_array_muxed6[0:0] + attribute \src "ls180.v:4396.1-4400.4" + wire width 16 $0\gpio_o[15:0] + attribute \src "ls180.v:4401.1-4405.4" + wire width 16 $0\gpio_oe[15:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_cmd_consumed[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_converter0_counter[0:0] + attribute \src "ls180.v:2903.1-2949.4" + wire $0\main_converter0_counter_converter0_next_value[0:0] + attribute \src "ls180.v:2903.1-2949.4" + wire $0\main_converter0_counter_converter0_next_value_ce[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 64 $0\main_converter0_dat_r[63:0] + attribute \src "ls180.v:2903.1-2949.4" + wire $0\main_converter0_skip[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_converter1_counter[0:0] + attribute \src "ls180.v:2963.1-3009.4" + wire $0\main_converter1_counter_converter1_next_value[0:0] + attribute \src "ls180.v:2963.1-3009.4" + wire $0\main_converter1_counter_converter1_next_value_ce[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 64 $0\main_converter1_dat_r[63:0] + attribute \src "ls180.v:2963.1-3009.4" + wire $0\main_converter1_skip[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_converter_counter[0:0] + attribute \src "ls180.v:4216.1-4262.4" + wire $0\main_converter_counter_converter_next_value[0:0] + attribute \src "ls180.v:4216.1-4262.4" + wire $0\main_converter_counter_converter_next_value_ce[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 32 $0\main_converter_dat_r[31:0] + attribute \src "ls180.v:4216.1-4262.4" + wire $0\main_converter_skip[0:0] + attribute \src "ls180.v:7630.1-7700.4" + wire width 16 $0\main_dfi_p0_rddata[15:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_dfi_p0_rddata_valid[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 24 $0\main_dummy[23:0] + attribute \src "ls180.v:1082.12-1082.53" + wire width 16 $0\main_gpiotristateasic0_oe_storage[15:0] + attribute \src "ls180.v:1084.12-1084.54" + wire width 16 $0\main_gpiotristateasic0_out_storage[15:0] + attribute \src "ls180.v:7584.1-7594.4" + wire width 16 $0\main_gpiotristateasic0_status[15:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_gpiotristateasic1_oe_re[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 16 $0\main_gpiotristateasic1_oe_storage[15:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_gpiotristateasic1_out_re[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 16 $0\main_gpiotristateasic1_out_storage[15:0] + attribute \src "ls180.v:7595.1-7605.4" + wire width 16 $0\main_gpiotristateasic1_status[15:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_i2c_re[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 3 $0\main_i2c_storage[2:0] + attribute \src "ls180.v:7626.1-7628.4" + wire $0\main_int_rst[0:0] + attribute \src "ls180.v:1663.11-1663.41" + wire width 2 $0\main_interface0_bus_bte[1:0] + attribute \src "ls180.v:1662.11-1662.41" + wire width 3 $0\main_interface0_bus_cti[2:0] + attribute \src "ls180.v:2903.1-2949.4" + wire $0\main_interface0_converted_interface_ack[0:0] + attribute \src "ls180.v:316.5-316.51" + wire $0\main_interface0_converted_interface_err[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_interface0_ram_bus_ack[0:0] + attribute \src "ls180.v:256.5-256.39" + wire $0\main_interface0_ram_bus_err[0:0] + attribute \src "ls180.v:5702.1-5739.4" + wire width 32 $0\main_interface1_bus_adr[31:0] + attribute \src "ls180.v:1754.11-1754.41" + wire width 2 $0\main_interface1_bus_bte[1:0] + attribute \src "ls180.v:1753.11-1753.41" + wire width 3 $0\main_interface1_bus_cti[2:0] + attribute \src "ls180.v:5702.1-5739.4" + wire $0\main_interface1_bus_cyc[0:0] + attribute \src "ls180.v:1746.12-1746.45" + wire width 64 $0\main_interface1_bus_dat_w[63:0] + attribute \src "ls180.v:5702.1-5739.4" + wire width 8 $0\main_interface1_bus_sel[7:0] + attribute \src "ls180.v:5702.1-5739.4" + wire $0\main_interface1_bus_stb[0:0] + attribute \src "ls180.v:5702.1-5739.4" + wire $0\main_interface1_bus_we[0:0] + attribute \src "ls180.v:2963.1-3009.4" + wire $0\main_interface1_converted_interface_ack[0:0] + attribute \src "ls180.v:331.5-331.51" + wire $0\main_interface1_converted_interface_err[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_interface1_ram_bus_ack[0:0] + attribute \src "ls180.v:271.5-271.39" + wire $0\main_interface1_ram_bus_err[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_interface2_ram_bus_ack[0:0] + attribute \src "ls180.v:286.5-286.39" + wire $0\main_interface2_ram_bus_err[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_interface3_ram_bus_ack[0:0] + attribute \src "ls180.v:301.5-301.39" + wire $0\main_interface3_ram_bus_err[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 32 $0\main_libresocsim_bus_errors[31:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_libresocsim_en_re[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_libresocsim_en_storage[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_libresocsim_eventmanager_re[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_libresocsim_eventmanager_storage[0:0] + attribute \src "ls180.v:75.11-75.52" + wire width 2 $0\main_libresocsim_libresoc_dbus_bte[1:0] + attribute \src "ls180.v:74.11-74.52" + wire width 3 $0\main_libresocsim_libresoc_dbus_cti[2:0] + attribute \src "ls180.v:86.11-86.52" + wire width 2 $0\main_libresocsim_libresoc_ibus_bte[1:0] + attribute \src "ls180.v:85.11-85.52" + wire width 3 $0\main_libresocsim_libresoc_ibus_cti[2:0] + attribute \src "ls180.v:2884.1-2889.4" + wire width 16 $0\main_libresocsim_libresoc_interrupt[15:0] + attribute \src "ls180.v:115.11-115.55" + wire width 2 $0\main_libresocsim_libresoc_jtag_wb_bte[1:0] + attribute \src "ls180.v:114.11-114.55" + wire width 3 $0\main_libresocsim_libresoc_jtag_wb_cti[2:0] + attribute \src "ls180.v:2903.1-2949.4" + wire width 30 $0\main_libresocsim_libresoc_xics_icp_adr[29:0] + attribute \src "ls180.v:2903.1-2949.4" + wire $0\main_libresocsim_libresoc_xics_icp_cyc[0:0] + attribute \src "ls180.v:2891.1-2901.4" + wire width 32 $0\main_libresocsim_libresoc_xics_icp_dat_w[31:0] + attribute \src "ls180.v:2903.1-2949.4" + wire width 4 $0\main_libresocsim_libresoc_xics_icp_sel[3:0] + attribute \src "ls180.v:2903.1-2949.4" + wire $0\main_libresocsim_libresoc_xics_icp_stb[0:0] + attribute \src "ls180.v:2903.1-2949.4" + wire $0\main_libresocsim_libresoc_xics_icp_we[0:0] + attribute \src "ls180.v:2963.1-3009.4" + wire width 30 $0\main_libresocsim_libresoc_xics_ics_adr[29:0] + attribute \src "ls180.v:2963.1-3009.4" + wire $0\main_libresocsim_libresoc_xics_ics_cyc[0:0] + attribute \src "ls180.v:2951.1-2961.4" + wire width 32 $0\main_libresocsim_libresoc_xics_ics_dat_w[31:0] + attribute \src "ls180.v:2963.1-3009.4" + wire width 4 $0\main_libresocsim_libresoc_xics_ics_sel[3:0] + attribute \src "ls180.v:2963.1-3009.4" + wire $0\main_libresocsim_libresoc_xics_ics_stb[0:0] + attribute \src "ls180.v:2963.1-3009.4" + wire $0\main_libresocsim_libresoc_xics_ics_we[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_libresocsim_load_re[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 32 $0\main_libresocsim_load_storage[31:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_libresocsim_ram_bus_ack[0:0] + attribute \src "ls180.v:214.5-214.40" + wire $0\main_libresocsim_ram_bus_err[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_libresocsim_reload_re[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 32 $0\main_libresocsim_reload_storage[31:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_libresocsim_reset_re[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_libresocsim_reset_storage[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_libresocsim_scratch_re[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 32 $0\main_libresocsim_scratch_storage[31:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_libresocsim_update_value_re[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_libresocsim_update_value_storage[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 32 $0\main_libresocsim_value[31:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 32 $0\main_libresocsim_value_status[31:0] + attribute \src "ls180.v:3072.1-3082.4" + wire width 8 $0\main_libresocsim_we[7:0] + attribute \src "ls180.v:3088.1-3093.4" + wire $0\main_libresocsim_zero_clear[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_libresocsim_zero_old_trigger[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_libresocsim_zero_pending[0:0] + attribute \src "ls180.v:4216.1-4262.4" + wire width 30 $0\main_litedram_wb_adr[29:0] + attribute \src "ls180.v:4216.1-4262.4" + wire $0\main_litedram_wb_cyc[0:0] + attribute \src "ls180.v:4204.1-4214.4" + wire width 16 $0\main_litedram_wb_dat_w[15:0] + attribute \src "ls180.v:4216.1-4262.4" + wire width 2 $0\main_litedram_wb_sel[1:0] + attribute \src "ls180.v:4216.1-4262.4" + wire $0\main_litedram_wb_stb[0:0] + attribute \src "ls180.v:4216.1-4262.4" + wire $0\main_litedram_wb_we[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 32 $0\main_pwm0_counter[31:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_pwm0_enable_re[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_pwm0_enable_storage[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_pwm0_period_re[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 32 $0\main_pwm0_period_storage[31:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_pwm0_width_re[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 32 $0\main_pwm0_width_storage[31:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 32 $0\main_pwm1_counter[31:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_pwm1_enable_re[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_pwm1_enable_storage[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_pwm1_period_re[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 32 $0\main_pwm1_period_storage[31:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_pwm1_width_re[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 32 $0\main_pwm1_width_storage[31:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 3 $0\main_rddata_en[2:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 3 $0\main_sdblock2mem_converter_demux[2:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdblock2mem_converter_source_first[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdblock2mem_converter_source_last[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 64 $0\main_sdblock2mem_converter_source_payload_data[63:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 4 $0\main_sdblock2mem_converter_source_payload_valid_token_count[3:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdblock2mem_converter_strobe_all[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 5 $0\main_sdblock2mem_fifo_consume[4:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 6 $0\main_sdblock2mem_fifo_level[5:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 5 $0\main_sdblock2mem_fifo_produce[4:0] + attribute \src "ls180.v:1687.5-1687.41" + wire $0\main_sdblock2mem_fifo_replace[0:0] + attribute \src "ls180.v:5610.1-5617.4" + wire width 5 $0\main_sdblock2mem_fifo_wrport_adr[4:0] + attribute \src "ls180.v:5643.1-5682.4" + wire width 32 $0\main_sdblock2mem_sink_sink_payload_address[31:0] + attribute \src "ls180.v:5643.1-5682.4" + wire width 64 $0\main_sdblock2mem_sink_sink_payload_data1[63:0] + attribute \src "ls180.v:5643.1-5682.4" + wire $0\main_sdblock2mem_sink_sink_valid1[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdblock2mem_wishbonedmawriter_base_re[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 64 $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdblock2mem_wishbonedmawriter_enable_re[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdblock2mem_wishbonedmawriter_length_re[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 32 $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdblock2mem_wishbonedmawriter_loop_re[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 32 $0\main_sdblock2mem_wishbonedmawriter_offset[31:0] + attribute \src "ls180.v:5643.1-5682.4" + wire width 32 $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] + attribute \src "ls180.v:5643.1-5682.4" + wire $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] + attribute \src "ls180.v:5643.1-5682.4" + wire $0\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] + attribute \src "ls180.v:5643.1-5682.4" + wire $0\main_sdblock2mem_wishbonedmawriter_status[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdcore_block_count_re[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 32 $0\main_sdcore_block_count_storage[31:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdcore_block_length_re[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 10 $0\main_sdcore_block_length_storage[9:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdcore_cmd_argument_re[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 32 $0\main_sdcore_cmd_argument_storage[31:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdcore_cmd_command_re[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 32 $0\main_sdcore_cmd_command_storage[31:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 3 $0\main_sdcore_cmd_count[2:0] + attribute \src "ls180.v:5392.1-5582.4" + wire width 3 $0\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] + attribute \src "ls180.v:5392.1-5582.4" + wire $0\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdcore_cmd_done[0:0] + attribute \src "ls180.v:5392.1-5582.4" + wire $0\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] + attribute \src "ls180.v:5392.1-5582.4" + wire $0\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdcore_cmd_error[0:0] + attribute \src "ls180.v:5392.1-5582.4" + wire $0\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] + attribute \src "ls180.v:5392.1-5582.4" + wire $0\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 128 $0\main_sdcore_cmd_response_status[127:0] + attribute \src "ls180.v:5392.1-5582.4" + wire width 128 $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] + attribute \src "ls180.v:5392.1-5582.4" + wire $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] + attribute \src "ls180.v:1496.5-1496.34" + wire $0\main_sdcore_cmd_send_w[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdcore_cmd_timeout[0:0] + attribute \src "ls180.v:5392.1-5582.4" + wire $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] + attribute \src "ls180.v:5392.1-5582.4" + wire $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 4 $0\main_sdcore_crc16_checker_cnt[3:0] + attribute \src "ls180.v:5298.1-5305.4" + wire $0\main_sdcore_crc16_checker_crc0_clr[0:0] + attribute \src "ls180.v:5354.1-5361.4" + wire width 16 $0\main_sdcore_crc16_checker_crc0_crc[15:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 16 $0\main_sdcore_crc16_checker_crc0_crcreg0[15:0] + attribute \src "ls180.v:5308.1-5315.4" + wire $0\main_sdcore_crc16_checker_crc1_clr[0:0] + attribute \src "ls180.v:5364.1-5371.4" + wire width 16 $0\main_sdcore_crc16_checker_crc1_crc[15:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 16 $0\main_sdcore_crc16_checker_crc1_crcreg0[15:0] + attribute \src "ls180.v:5318.1-5325.4" + wire $0\main_sdcore_crc16_checker_crc2_clr[0:0] + attribute \src "ls180.v:5374.1-5381.4" + wire width 16 $0\main_sdcore_crc16_checker_crc2_crc[15:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 16 $0\main_sdcore_crc16_checker_crc2_crcreg0[15:0] + attribute \src "ls180.v:5328.1-5335.4" + wire $0\main_sdcore_crc16_checker_crc3_clr[0:0] + attribute \src "ls180.v:5384.1-5391.4" + wire width 16 $0\main_sdcore_crc16_checker_crc3_crc[15:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 16 $0\main_sdcore_crc16_checker_crc3_crcreg0[15:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 16 $0\main_sdcore_crc16_checker_crctmp0[15:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 16 $0\main_sdcore_crc16_checker_crctmp1[15:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 16 $0\main_sdcore_crc16_checker_crctmp2[15:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 16 $0\main_sdcore_crc16_checker_crctmp3[15:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 16 $0\main_sdcore_crc16_checker_fifo0[15:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 16 $0\main_sdcore_crc16_checker_fifo1[15:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 16 $0\main_sdcore_crc16_checker_fifo2[15:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 16 $0\main_sdcore_crc16_checker_fifo3[15:0] + attribute \src "ls180.v:5392.1-5582.4" + wire $0\main_sdcore_crc16_checker_sink_first[0:0] + attribute \src "ls180.v:5392.1-5582.4" + wire $0\main_sdcore_crc16_checker_sink_last[0:0] + attribute \src "ls180.v:5392.1-5582.4" + wire width 8 $0\main_sdcore_crc16_checker_sink_payload_data[7:0] + attribute \src "ls180.v:5343.1-5350.4" + wire $0\main_sdcore_crc16_checker_sink_ready[0:0] + attribute \src "ls180.v:5392.1-5582.4" + wire $0\main_sdcore_crc16_checker_sink_valid[0:0] + attribute \src "ls180.v:1602.5-1602.50" + wire $0\main_sdcore_crc16_checker_source_first[0:0] + attribute \src "ls180.v:5337.1-5342.4" + wire $0\main_sdcore_crc16_checker_source_valid[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 8 $0\main_sdcore_crc16_checker_val[7:0] + attribute \src "ls180.v:5290.1-5295.4" + wire $0\main_sdcore_crc16_checker_valid[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 3 $0\main_sdcore_crc16_inserter_cnt[2:0] + attribute \src "ls180.v:5210.1-5289.4" + wire width 3 $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] + attribute \src "ls180.v:5210.1-5289.4" + wire $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] + attribute \src "ls180.v:5172.1-5179.4" + wire width 16 $0\main_sdcore_crc16_inserter_crc0_crc[15:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 16 $0\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] + attribute \src "ls180.v:5182.1-5189.4" + wire width 16 $0\main_sdcore_crc16_inserter_crc1_crc[15:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 16 $0\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] + attribute \src "ls180.v:5192.1-5199.4" + wire width 16 $0\main_sdcore_crc16_inserter_crc2_crc[15:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 16 $0\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] + attribute \src "ls180.v:5202.1-5209.4" + wire width 16 $0\main_sdcore_crc16_inserter_crc3_crc[15:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 16 $0\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 16 $0\main_sdcore_crc16_inserter_crctmp0[15:0] + attribute \src "ls180.v:5210.1-5289.4" + wire width 16 $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] + attribute \src "ls180.v:5210.1-5289.4" + wire $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 16 $0\main_sdcore_crc16_inserter_crctmp1[15:0] + attribute \src "ls180.v:5210.1-5289.4" + wire width 16 $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] + attribute \src "ls180.v:5210.1-5289.4" + wire $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 16 $0\main_sdcore_crc16_inserter_crctmp2[15:0] + attribute \src "ls180.v:5210.1-5289.4" + wire width 16 $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] + attribute \src "ls180.v:5210.1-5289.4" + wire $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 16 $0\main_sdcore_crc16_inserter_crctmp3[15:0] + attribute \src "ls180.v:5210.1-5289.4" + wire width 16 $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] + attribute \src "ls180.v:5210.1-5289.4" + wire $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] + attribute \src "ls180.v:5210.1-5289.4" + wire $0\main_sdcore_crc16_inserter_sink_ready[0:0] + attribute \src "ls180.v:1559.5-1559.51" + wire $0\main_sdcore_crc16_inserter_source_first[0:0] + attribute \src "ls180.v:5210.1-5289.4" + wire $0\main_sdcore_crc16_inserter_source_last[0:0] + attribute \src "ls180.v:5210.1-5289.4" + wire width 8 $0\main_sdcore_crc16_inserter_source_payload_data[7:0] + attribute \src "ls180.v:5392.1-5582.4" + wire $0\main_sdcore_crc16_inserter_source_ready[0:0] + attribute \src "ls180.v:5210.1-5289.4" + wire $0\main_sdcore_crc16_inserter_source_valid[0:0] + attribute \src "ls180.v:5150.1-5157.4" + wire width 7 $0\main_sdcore_crc7_inserter_crc[6:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 7 $0\main_sdcore_crc7_inserter_crcreg0[6:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 32 $0\main_sdcore_data_count[31:0] + attribute \src "ls180.v:5392.1-5582.4" + wire width 32 $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] + attribute \src "ls180.v:5392.1-5582.4" + wire $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdcore_data_done[0:0] + attribute \src "ls180.v:5392.1-5582.4" + wire $0\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] + attribute \src "ls180.v:5392.1-5582.4" + wire $0\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdcore_data_error[0:0] + attribute \src "ls180.v:5392.1-5582.4" + wire $0\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] + attribute \src "ls180.v:5392.1-5582.4" + wire $0\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdcore_data_timeout[0:0] + attribute \src "ls180.v:5392.1-5582.4" + wire $0\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] + attribute \src "ls180.v:5392.1-5582.4" + wire $0\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 3 $0\main_sdmem2block_converter_mux[2:0] + attribute \src "ls180.v:5788.1-5816.4" + wire width 8 $0\main_sdmem2block_converter_source_payload_data[7:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdmem2block_dma_base_re[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 64 $0\main_sdmem2block_dma_base_storage[63:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 64 $0\main_sdmem2block_dma_data[63:0] + attribute \src "ls180.v:5702.1-5739.4" + wire width 64 $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[63:0] + attribute \src "ls180.v:5702.1-5739.4" + wire $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] + attribute \src "ls180.v:5740.1-5776.4" + wire $0\main_sdmem2block_dma_done_status[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdmem2block_dma_enable_re[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdmem2block_dma_enable_storage[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdmem2block_dma_length_re[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 32 $0\main_sdmem2block_dma_length_storage[31:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdmem2block_dma_loop_re[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdmem2block_dma_loop_storage[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 32 $0\main_sdmem2block_dma_offset[31:0] + attribute \src "ls180.v:5740.1-5776.4" + wire width 32 $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] + attribute \src "ls180.v:5740.1-5776.4" + wire $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] + attribute \src "ls180.v:5740.1-5776.4" + wire $0\main_sdmem2block_dma_sink_last[0:0] + attribute \src "ls180.v:5740.1-5776.4" + wire width 32 $0\main_sdmem2block_dma_sink_payload_address[31:0] + attribute \src "ls180.v:5702.1-5739.4" + wire $0\main_sdmem2block_dma_sink_ready[0:0] + attribute \src "ls180.v:5740.1-5776.4" + wire $0\main_sdmem2block_dma_sink_valid[0:0] + attribute \src "ls180.v:1767.5-1767.45" + wire $0\main_sdmem2block_dma_source_first[0:0] + attribute \src "ls180.v:5702.1-5739.4" + wire $0\main_sdmem2block_dma_source_last[0:0] + attribute \src "ls180.v:5702.1-5739.4" + wire width 64 $0\main_sdmem2block_dma_source_payload_data[63:0] + attribute \src "ls180.v:5702.1-5739.4" + wire $0\main_sdmem2block_dma_source_valid[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 5 $0\main_sdmem2block_fifo_consume[4:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 6 $0\main_sdmem2block_fifo_level[5:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 5 $0\main_sdmem2block_fifo_produce[4:0] + attribute \src "ls180.v:1823.5-1823.41" + wire $0\main_sdmem2block_fifo_replace[0:0] + attribute \src "ls180.v:5830.1-5837.4" + wire width 5 $0\main_sdmem2block_fifo_wrport_adr[4:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdphy_clocker_clk0[0:0] + attribute \src "ls180.v:4556.1-4584.4" + wire $0\main_sdphy_clocker_clk1[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdphy_clocker_clk_d[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 9 $0\main_sdphy_clocker_clks[8:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdphy_clocker_re[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 9 $0\main_sdphy_clocker_storage[8:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdphy_cmdr_cmdr_buf_source_first[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdphy_cmdr_cmdr_buf_source_last[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 8 $0\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 3 $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] + attribute \src "ls180.v:1288.5-1288.53" + wire $0\main_sdphy_cmdr_cmdr_converter_sink_first[0:0] + attribute \src "ls180.v:1289.5-1289.52" + wire $0\main_sdphy_cmdr_cmdr_converter_sink_last[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdphy_cmdr_cmdr_converter_source_first[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdphy_cmdr_cmdr_converter_source_last[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 8 $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 4 $0\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] + attribute \src "ls180.v:1269.5-1269.46" + wire $0\main_sdphy_cmdr_cmdr_pads_in_ready[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdphy_cmdr_cmdr_reset[0:0] + attribute \src "ls180.v:4730.1-4823.4" + wire $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] + attribute \src "ls180.v:4730.1-4823.4" + wire $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdphy_cmdr_cmdr_run[0:0] + attribute \src "ls180.v:4730.1-4823.4" + wire $0\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 8 $0\main_sdphy_cmdr_count[7:0] + attribute \src "ls180.v:4730.1-4823.4" + wire width 8 $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] + attribute \src "ls180.v:4730.1-4823.4" + wire $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] + attribute \src "ls180.v:1242.5-1242.49" + wire $0\main_sdphy_cmdr_pads_in_pads_in_first[0:0] + attribute \src "ls180.v:1243.5-1243.48" + wire $0\main_sdphy_cmdr_pads_in_pads_in_last[0:0] + attribute \src "ls180.v:1244.5-1244.55" + wire $0\main_sdphy_cmdr_pads_in_pads_in_payload_clk[0:0] + attribute \src "ls180.v:1246.5-1246.57" + wire $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_o[0:0] + attribute \src "ls180.v:1247.5-1247.58" + wire $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_oe[0:0] + attribute \src "ls180.v:1249.11-1249.64" + wire width 4 $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_o[3:0] + attribute \src "ls180.v:1250.5-1250.59" + wire $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_oe[0:0] + attribute \src "ls180.v:4730.1-4823.4" + wire $0\main_sdphy_cmdr_pads_out_payload_clk[0:0] + attribute \src "ls180.v:4730.1-4823.4" + wire $0\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] + attribute \src "ls180.v:4730.1-4823.4" + wire $0\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] + attribute \src "ls180.v:1255.11-1255.57" + wire width 4 $0\main_sdphy_cmdr_pads_out_payload_data_o[3:0] + attribute \src "ls180.v:1256.5-1256.52" + wire $0\main_sdphy_cmdr_pads_out_payload_data_oe[0:0] + attribute \src "ls180.v:5392.1-5582.4" + wire $0\main_sdphy_cmdr_sink_last[0:0] + attribute \src "ls180.v:5392.1-5582.4" + wire width 8 $0\main_sdphy_cmdr_sink_payload_length[7:0] + attribute \src "ls180.v:4730.1-4823.4" + wire $0\main_sdphy_cmdr_sink_ready[0:0] + attribute \src "ls180.v:5392.1-5582.4" + wire $0\main_sdphy_cmdr_sink_valid[0:0] + attribute \src "ls180.v:4730.1-4823.4" + wire $0\main_sdphy_cmdr_source_last[0:0] + attribute \src "ls180.v:4730.1-4823.4" + wire width 8 $0\main_sdphy_cmdr_source_payload_data[7:0] + attribute \src "ls180.v:4730.1-4823.4" + wire width 3 $0\main_sdphy_cmdr_source_payload_status[2:0] + attribute \src "ls180.v:5392.1-5582.4" + wire $0\main_sdphy_cmdr_source_ready[0:0] + attribute \src "ls180.v:4730.1-4823.4" + wire $0\main_sdphy_cmdr_source_valid[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 32 $0\main_sdphy_cmdr_timeout[31:0] + attribute \src "ls180.v:4730.1-4823.4" + wire width 32 $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] + attribute \src "ls180.v:4730.1-4823.4" + wire $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 8 $0\main_sdphy_cmdw_count[7:0] + attribute \src "ls180.v:4620.1-4696.4" + wire width 8 $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] + attribute \src "ls180.v:4620.1-4696.4" + wire $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] + attribute \src "ls180.v:4620.1-4696.4" + wire $0\main_sdphy_cmdw_done[0:0] + attribute \src "ls180.v:4620.1-4696.4" + wire $0\main_sdphy_cmdw_pads_out_payload_clk[0:0] + attribute \src "ls180.v:4620.1-4696.4" + wire $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] + attribute \src "ls180.v:4620.1-4696.4" + wire $0\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] + attribute \src "ls180.v:1232.11-1232.57" + wire width 4 $0\main_sdphy_cmdw_pads_out_payload_data_o[3:0] + attribute \src "ls180.v:1233.5-1233.52" + wire $0\main_sdphy_cmdw_pads_out_payload_data_oe[0:0] + attribute \src "ls180.v:5392.1-5582.4" + wire $0\main_sdphy_cmdw_sink_last[0:0] + attribute \src "ls180.v:5392.1-5582.4" + wire width 8 $0\main_sdphy_cmdw_sink_payload_data[7:0] + attribute \src "ls180.v:4620.1-4696.4" + wire $0\main_sdphy_cmdw_sink_ready[0:0] + attribute \src "ls180.v:5392.1-5582.4" + wire $0\main_sdphy_cmdw_sink_valid[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 10 $0\main_sdphy_datar_count[9:0] + attribute \src "ls180.v:4991.1-5092.4" + wire width 10 $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] + attribute \src "ls180.v:4991.1-5092.4" + wire $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdphy_datar_datar_buf_source_first[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdphy_datar_datar_buf_source_last[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 8 $0\main_sdphy_datar_datar_buf_source_payload_data[7:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdphy_datar_datar_buf_source_valid[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdphy_datar_datar_converter_demux[0:0] + attribute \src "ls180.v:1444.5-1444.55" + wire $0\main_sdphy_datar_datar_converter_sink_first[0:0] + attribute \src "ls180.v:1445.5-1445.54" + wire $0\main_sdphy_datar_datar_converter_sink_last[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdphy_datar_datar_converter_source_first[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdphy_datar_datar_converter_source_last[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 8 $0\main_sdphy_datar_datar_converter_source_payload_data[7:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 2 $0\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdphy_datar_datar_converter_strobe_all[0:0] + attribute \src "ls180.v:1425.5-1425.48" + wire $0\main_sdphy_datar_datar_pads_in_ready[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdphy_datar_datar_reset[0:0] + attribute \src "ls180.v:4991.1-5092.4" + wire $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] + attribute \src "ls180.v:4991.1-5092.4" + wire $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdphy_datar_datar_run[0:0] + attribute \src "ls180.v:4991.1-5092.4" + wire $0\main_sdphy_datar_datar_source_source_ready0[0:0] + attribute \src "ls180.v:1396.5-1396.50" + wire $0\main_sdphy_datar_pads_in_pads_in_first[0:0] + attribute \src "ls180.v:1397.5-1397.49" + wire $0\main_sdphy_datar_pads_in_pads_in_last[0:0] + attribute \src "ls180.v:1398.5-1398.56" + wire $0\main_sdphy_datar_pads_in_pads_in_payload_clk[0:0] + attribute \src "ls180.v:1400.5-1400.58" + wire $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_o[0:0] + attribute \src "ls180.v:1401.5-1401.59" + wire $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_oe[0:0] + attribute \src "ls180.v:1403.11-1403.65" + wire width 4 $0\main_sdphy_datar_pads_in_pads_in_payload_data_o[3:0] + attribute \src "ls180.v:1404.5-1404.60" + wire $0\main_sdphy_datar_pads_in_pads_in_payload_data_oe[0:0] + attribute \src "ls180.v:4991.1-5092.4" + wire $0\main_sdphy_datar_pads_out_payload_clk[0:0] + attribute \src "ls180.v:1407.5-1407.51" + wire $0\main_sdphy_datar_pads_out_payload_cmd_o[0:0] + attribute \src "ls180.v:1408.5-1408.52" + wire $0\main_sdphy_datar_pads_out_payload_cmd_oe[0:0] + attribute \src "ls180.v:1409.11-1409.58" + wire width 4 $0\main_sdphy_datar_pads_out_payload_data_o[3:0] + attribute \src "ls180.v:1410.5-1410.53" + wire $0\main_sdphy_datar_pads_out_payload_data_oe[0:0] + attribute \src "ls180.v:5392.1-5582.4" + wire $0\main_sdphy_datar_sink_last[0:0] + attribute \src "ls180.v:5392.1-5582.4" + wire width 10 $0\main_sdphy_datar_sink_payload_block_length[9:0] + attribute \src "ls180.v:4991.1-5092.4" + wire $0\main_sdphy_datar_sink_ready[0:0] + attribute \src "ls180.v:5392.1-5582.4" + wire $0\main_sdphy_datar_sink_valid[0:0] + attribute \src "ls180.v:1417.5-1417.41" + wire $0\main_sdphy_datar_source_first[0:0] + attribute \src "ls180.v:4991.1-5092.4" + wire $0\main_sdphy_datar_source_last[0:0] + attribute \src "ls180.v:4991.1-5092.4" + wire width 8 $0\main_sdphy_datar_source_payload_data[7:0] + attribute \src "ls180.v:4991.1-5092.4" + wire width 3 $0\main_sdphy_datar_source_payload_status[2:0] + attribute \src "ls180.v:5392.1-5582.4" + wire $0\main_sdphy_datar_source_ready[0:0] + attribute \src "ls180.v:4991.1-5092.4" + wire $0\main_sdphy_datar_source_valid[0:0] + attribute \src "ls180.v:4991.1-5092.4" + wire $0\main_sdphy_datar_stop[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 32 $0\main_sdphy_datar_timeout[31:0] + attribute \src "ls180.v:4991.1-5092.4" + wire width 32 $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] + attribute \src "ls180.v:4991.1-5092.4" + wire $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 8 $0\main_sdphy_dataw_count[7:0] + attribute \src "ls180.v:4885.1-4957.4" + wire width 8 $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] + attribute \src "ls180.v:4885.1-4957.4" + wire $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdphy_dataw_crcr_buf_source_first[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdphy_dataw_crcr_buf_source_last[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 8 $0\main_sdphy_dataw_crcr_buf_source_payload_data[7:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdphy_dataw_crcr_buf_source_valid[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 3 $0\main_sdphy_dataw_crcr_converter_demux[2:0] + attribute \src "ls180.v:1366.5-1366.54" + wire $0\main_sdphy_dataw_crcr_converter_sink_first[0:0] + attribute \src "ls180.v:1367.5-1367.53" + wire $0\main_sdphy_dataw_crcr_converter_sink_last[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdphy_dataw_crcr_converter_source_first[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdphy_dataw_crcr_converter_source_last[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 8 $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 4 $0\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdphy_dataw_crcr_converter_strobe_all[0:0] + attribute \src "ls180.v:1347.5-1347.47" + wire $0\main_sdphy_dataw_crcr_pads_in_ready[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdphy_dataw_crcr_reset[0:0] + attribute \src "ls180.v:4857.1-4884.4" + wire $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] + attribute \src "ls180.v:4857.1-4884.4" + wire $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdphy_dataw_crcr_run[0:0] + attribute \src "ls180.v:4857.1-4884.4" + wire $0\main_sdphy_dataw_crcr_source_source_ready0[0:0] + attribute \src "ls180.v:4857.1-4884.4" + wire $0\main_sdphy_dataw_error[0:0] + attribute \src "ls180.v:1334.5-1334.50" + wire $0\main_sdphy_dataw_pads_in_pads_in_first[0:0] + attribute \src "ls180.v:1335.5-1335.49" + wire $0\main_sdphy_dataw_pads_in_pads_in_last[0:0] + attribute \src "ls180.v:1336.5-1336.56" + wire $0\main_sdphy_dataw_pads_in_pads_in_payload_clk[0:0] + attribute \src "ls180.v:1337.5-1337.58" + wire $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_i[0:0] + attribute \src "ls180.v:1338.5-1338.58" + wire $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_o[0:0] + attribute \src "ls180.v:1339.5-1339.59" + wire $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_oe[0:0] + attribute \src "ls180.v:1340.11-1340.65" + wire width 4 $0\main_sdphy_dataw_pads_in_pads_in_payload_data_i[3:0] + attribute \src "ls180.v:1341.11-1341.65" + wire width 4 $0\main_sdphy_dataw_pads_in_pads_in_payload_data_o[3:0] + attribute \src "ls180.v:1342.5-1342.60" + wire $0\main_sdphy_dataw_pads_in_pads_in_payload_data_oe[0:0] + attribute \src "ls180.v:1332.5-1332.50" + wire $0\main_sdphy_dataw_pads_in_pads_in_valid[0:0] + attribute \src "ls180.v:4885.1-4957.4" + wire $0\main_sdphy_dataw_pads_out_payload_clk[0:0] + attribute \src "ls180.v:1321.5-1321.51" + wire $0\main_sdphy_dataw_pads_out_payload_cmd_o[0:0] + attribute \src "ls180.v:1322.5-1322.52" + wire $0\main_sdphy_dataw_pads_out_payload_cmd_oe[0:0] + attribute \src "ls180.v:4885.1-4957.4" + wire width 4 $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] + attribute \src "ls180.v:4885.1-4957.4" + wire $0\main_sdphy_dataw_pads_out_payload_data_oe[0:0] + attribute \src "ls180.v:5392.1-5582.4" + wire $0\main_sdphy_dataw_sink_first[0:0] + attribute \src "ls180.v:5392.1-5582.4" + wire $0\main_sdphy_dataw_sink_last[0:0] + attribute \src "ls180.v:5392.1-5582.4" + wire width 8 $0\main_sdphy_dataw_sink_payload_data[7:0] + attribute \src "ls180.v:4885.1-4957.4" + wire $0\main_sdphy_dataw_sink_ready[0:0] + attribute \src "ls180.v:5392.1-5582.4" + wire $0\main_sdphy_dataw_sink_valid[0:0] + attribute \src "ls180.v:4885.1-4957.4" + wire $0\main_sdphy_dataw_start[0:0] + attribute \src "ls180.v:4885.1-4957.4" + wire $0\main_sdphy_dataw_stop[0:0] + attribute \src "ls180.v:4857.1-4884.4" + wire $0\main_sdphy_dataw_valid[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 8 $0\main_sdphy_init_count[7:0] + attribute \src "ls180.v:4586.1-4619.4" + wire width 8 $0\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] + attribute \src "ls180.v:4586.1-4619.4" + wire $0\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] + attribute \src "ls180.v:1214.5-1214.40" + wire $0\main_sdphy_init_initialize_w[0:0] + attribute \src "ls180.v:4586.1-4619.4" + wire $0\main_sdphy_init_pads_out_payload_clk[0:0] + attribute \src "ls180.v:4586.1-4619.4" + wire $0\main_sdphy_init_pads_out_payload_cmd_o[0:0] + attribute \src "ls180.v:4586.1-4619.4" + wire $0\main_sdphy_init_pads_out_payload_cmd_oe[0:0] + attribute \src "ls180.v:4586.1-4619.4" + wire width 4 $0\main_sdphy_init_pads_out_payload_data_o[3:0] + attribute \src "ls180.v:4586.1-4619.4" + wire $0\main_sdphy_init_pads_out_payload_data_oe[0:0] + attribute \src "ls180.v:7630.1-7700.4" + wire $0\main_sdphy_sdpads_cmd_i[0:0] + attribute \src "ls180.v:7630.1-7700.4" + wire width 4 $0\main_sdphy_sdpads_data_i[3:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdram_address_re[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 13 $0\main_sdram_address_storage[12:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdram_baddress_re[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 2 $0\main_sdram_baddress_storage[1:0] + attribute \src "ls180.v:3361.1-3368.4" + wire $0\main_sdram_bankmachine0_auto_precharge[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 3 $0\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 4 $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 3 $0\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] + attribute \src "ls180.v:536.5-536.64" + wire $0\main_sdram_bankmachine0_cmd_buffer_lookahead_replace[0:0] + attribute \src "ls180.v:519.5-519.67" + wire $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first[0:0] + attribute \src "ls180.v:520.5-520.66" + wire $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last[0:0] + attribute \src "ls180.v:3383.1-3390.4" + wire width 3 $0\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 22 $0\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] + attribute \src "ls180.v:3350.1-3357.4" + wire width 13 $0\main_sdram_bankmachine0_cmd_payload_a[12:0] + attribute \src "ls180.v:3399.1-3492.4" + wire $0\main_sdram_bankmachine0_cmd_payload_cas[0:0] + attribute \src "ls180.v:3399.1-3492.4" + wire $0\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] + attribute \src "ls180.v:3399.1-3492.4" + wire $0\main_sdram_bankmachine0_cmd_payload_is_read[0:0] + attribute \src "ls180.v:3399.1-3492.4" + wire $0\main_sdram_bankmachine0_cmd_payload_is_write[0:0] + attribute \src "ls180.v:3399.1-3492.4" + wire $0\main_sdram_bankmachine0_cmd_payload_ras[0:0] + attribute \src "ls180.v:3399.1-3492.4" + wire $0\main_sdram_bankmachine0_cmd_payload_we[0:0] + attribute \src "ls180.v:4048.1-4056.4" + wire $0\main_sdram_bankmachine0_cmd_ready[0:0] + attribute \src "ls180.v:3399.1-3492.4" + wire $0\main_sdram_bankmachine0_cmd_valid[0:0] + attribute \src "ls180.v:3399.1-3492.4" + wire $0\main_sdram_bankmachine0_refresh_gnt[0:0] + attribute \src "ls180.v:3399.1-3492.4" + wire $0\main_sdram_bankmachine0_req_rdata_valid[0:0] + attribute \src "ls180.v:3399.1-3492.4" + wire $0\main_sdram_bankmachine0_req_wdata_ready[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 13 $0\main_sdram_bankmachine0_row[12:0] + attribute \src "ls180.v:3399.1-3492.4" + wire $0\main_sdram_bankmachine0_row_close[0:0] + attribute \src "ls180.v:3399.1-3492.4" + wire $0\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] + attribute \src "ls180.v:3399.1-3492.4" + wire $0\main_sdram_bankmachine0_row_open[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdram_bankmachine0_row_opened[0:0] + attribute \src "ls180.v:578.32-578.76" + wire $0\main_sdram_bankmachine0_trascon_ready[0:0] + attribute \src "ls180.v:576.32-576.75" + wire $0\main_sdram_bankmachine0_trccon_ready[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 3 $0\main_sdram_bankmachine0_twtpcon_count[2:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdram_bankmachine0_twtpcon_ready[0:0] + attribute \src "ls180.v:3518.1-3525.4" + wire $0\main_sdram_bankmachine1_auto_precharge[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 3 $0\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 4 $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 3 $0\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] + attribute \src "ls180.v:618.5-618.64" + wire $0\main_sdram_bankmachine1_cmd_buffer_lookahead_replace[0:0] + attribute \src "ls180.v:601.5-601.67" + wire $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first[0:0] + attribute \src "ls180.v:602.5-602.66" + wire $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last[0:0] + attribute \src "ls180.v:3540.1-3547.4" + wire width 3 $0\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 22 $0\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] + attribute \src "ls180.v:3507.1-3514.4" + wire width 13 $0\main_sdram_bankmachine1_cmd_payload_a[12:0] + attribute \src "ls180.v:3556.1-3649.4" + wire $0\main_sdram_bankmachine1_cmd_payload_cas[0:0] + attribute \src "ls180.v:3556.1-3649.4" + wire $0\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] + attribute \src "ls180.v:3556.1-3649.4" + wire $0\main_sdram_bankmachine1_cmd_payload_is_read[0:0] + attribute \src "ls180.v:3556.1-3649.4" + wire $0\main_sdram_bankmachine1_cmd_payload_is_write[0:0] + attribute \src "ls180.v:3556.1-3649.4" + wire $0\main_sdram_bankmachine1_cmd_payload_ras[0:0] + attribute \src "ls180.v:3556.1-3649.4" + wire $0\main_sdram_bankmachine1_cmd_payload_we[0:0] + attribute \src "ls180.v:4057.1-4065.4" + wire $0\main_sdram_bankmachine1_cmd_ready[0:0] + attribute \src "ls180.v:3556.1-3649.4" + wire $0\main_sdram_bankmachine1_cmd_valid[0:0] + attribute \src "ls180.v:3556.1-3649.4" + wire $0\main_sdram_bankmachine1_refresh_gnt[0:0] + attribute \src "ls180.v:3556.1-3649.4" + wire $0\main_sdram_bankmachine1_req_rdata_valid[0:0] + attribute \src "ls180.v:3556.1-3649.4" + wire $0\main_sdram_bankmachine1_req_wdata_ready[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 13 $0\main_sdram_bankmachine1_row[12:0] + attribute \src "ls180.v:3556.1-3649.4" + wire $0\main_sdram_bankmachine1_row_close[0:0] + attribute \src "ls180.v:3556.1-3649.4" + wire $0\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] + attribute \src "ls180.v:3556.1-3649.4" + wire $0\main_sdram_bankmachine1_row_open[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdram_bankmachine1_row_opened[0:0] + attribute \src "ls180.v:660.32-660.76" + wire $0\main_sdram_bankmachine1_trascon_ready[0:0] + attribute \src "ls180.v:658.32-658.75" + wire $0\main_sdram_bankmachine1_trccon_ready[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 3 $0\main_sdram_bankmachine1_twtpcon_count[2:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdram_bankmachine1_twtpcon_ready[0:0] + attribute \src "ls180.v:3675.1-3682.4" + wire $0\main_sdram_bankmachine2_auto_precharge[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 3 $0\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 4 $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 3 $0\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] + attribute \src "ls180.v:700.5-700.64" + wire $0\main_sdram_bankmachine2_cmd_buffer_lookahead_replace[0:0] + attribute \src "ls180.v:683.5-683.67" + wire $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first[0:0] + attribute \src "ls180.v:684.5-684.66" + wire $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last[0:0] + attribute \src "ls180.v:3697.1-3704.4" + wire width 3 $0\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 22 $0\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] + attribute \src "ls180.v:3664.1-3671.4" + wire width 13 $0\main_sdram_bankmachine2_cmd_payload_a[12:0] + attribute \src "ls180.v:3713.1-3806.4" + wire $0\main_sdram_bankmachine2_cmd_payload_cas[0:0] + attribute \src "ls180.v:3713.1-3806.4" + wire $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] + attribute \src "ls180.v:3713.1-3806.4" + wire $0\main_sdram_bankmachine2_cmd_payload_is_read[0:0] + attribute \src "ls180.v:3713.1-3806.4" + wire $0\main_sdram_bankmachine2_cmd_payload_is_write[0:0] + attribute \src "ls180.v:3713.1-3806.4" + wire $0\main_sdram_bankmachine2_cmd_payload_ras[0:0] + attribute \src "ls180.v:3713.1-3806.4" + wire $0\main_sdram_bankmachine2_cmd_payload_we[0:0] + attribute \src "ls180.v:4066.1-4074.4" + wire $0\main_sdram_bankmachine2_cmd_ready[0:0] + attribute \src "ls180.v:3713.1-3806.4" + wire $0\main_sdram_bankmachine2_cmd_valid[0:0] + attribute \src "ls180.v:3713.1-3806.4" + wire $0\main_sdram_bankmachine2_refresh_gnt[0:0] + attribute \src "ls180.v:3713.1-3806.4" + wire $0\main_sdram_bankmachine2_req_rdata_valid[0:0] + attribute \src "ls180.v:3713.1-3806.4" + wire $0\main_sdram_bankmachine2_req_wdata_ready[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 13 $0\main_sdram_bankmachine2_row[12:0] + attribute \src "ls180.v:3713.1-3806.4" + wire $0\main_sdram_bankmachine2_row_close[0:0] + attribute \src "ls180.v:3713.1-3806.4" + wire $0\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] + attribute \src "ls180.v:3713.1-3806.4" + wire $0\main_sdram_bankmachine2_row_open[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdram_bankmachine2_row_opened[0:0] + attribute \src "ls180.v:742.32-742.76" + wire $0\main_sdram_bankmachine2_trascon_ready[0:0] + attribute \src "ls180.v:740.32-740.75" + wire $0\main_sdram_bankmachine2_trccon_ready[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 3 $0\main_sdram_bankmachine2_twtpcon_count[2:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdram_bankmachine2_twtpcon_ready[0:0] + attribute \src "ls180.v:3832.1-3839.4" + wire $0\main_sdram_bankmachine3_auto_precharge[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 3 $0\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 4 $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 3 $0\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] + attribute \src "ls180.v:782.5-782.64" + wire $0\main_sdram_bankmachine3_cmd_buffer_lookahead_replace[0:0] + attribute \src "ls180.v:765.5-765.67" + wire $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first[0:0] + attribute \src "ls180.v:766.5-766.66" + wire $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last[0:0] + attribute \src "ls180.v:3854.1-3861.4" + wire width 3 $0\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 22 $0\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] + attribute \src "ls180.v:3821.1-3828.4" + wire width 13 $0\main_sdram_bankmachine3_cmd_payload_a[12:0] + attribute \src "ls180.v:3870.1-3963.4" + wire $0\main_sdram_bankmachine3_cmd_payload_cas[0:0] + attribute \src "ls180.v:3870.1-3963.4" + wire $0\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] + attribute \src "ls180.v:3870.1-3963.4" + wire $0\main_sdram_bankmachine3_cmd_payload_is_read[0:0] + attribute \src "ls180.v:3870.1-3963.4" + wire $0\main_sdram_bankmachine3_cmd_payload_is_write[0:0] + attribute \src "ls180.v:3870.1-3963.4" + wire $0\main_sdram_bankmachine3_cmd_payload_ras[0:0] + attribute \src "ls180.v:3870.1-3963.4" + wire $0\main_sdram_bankmachine3_cmd_payload_we[0:0] + attribute \src "ls180.v:4075.1-4083.4" + wire $0\main_sdram_bankmachine3_cmd_ready[0:0] + attribute \src "ls180.v:3870.1-3963.4" + wire $0\main_sdram_bankmachine3_cmd_valid[0:0] + attribute \src "ls180.v:3870.1-3963.4" + wire $0\main_sdram_bankmachine3_refresh_gnt[0:0] + attribute \src "ls180.v:3870.1-3963.4" + wire $0\main_sdram_bankmachine3_req_rdata_valid[0:0] + attribute \src "ls180.v:3870.1-3963.4" + wire $0\main_sdram_bankmachine3_req_wdata_ready[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 13 $0\main_sdram_bankmachine3_row[12:0] + attribute \src "ls180.v:3870.1-3963.4" + wire $0\main_sdram_bankmachine3_row_close[0:0] + attribute \src "ls180.v:3870.1-3963.4" + wire $0\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] + attribute \src "ls180.v:3870.1-3963.4" + wire $0\main_sdram_bankmachine3_row_open[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdram_bankmachine3_row_opened[0:0] + attribute \src "ls180.v:824.32-824.76" + wire $0\main_sdram_bankmachine3_trascon_ready[0:0] + attribute \src "ls180.v:822.32-822.75" + wire $0\main_sdram_bankmachine3_trccon_ready[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 3 $0\main_sdram_bankmachine3_twtpcon_count[2:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdram_bankmachine3_twtpcon_ready[0:0] + attribute \src "ls180.v:3997.1-4002.4" + wire $0\main_sdram_choose_cmd_cmd_payload_cas[0:0] + attribute \src "ls180.v:4003.1-4008.4" + wire $0\main_sdram_choose_cmd_cmd_payload_ras[0:0] + attribute \src "ls180.v:4009.1-4014.4" + wire $0\main_sdram_choose_cmd_cmd_payload_we[0:0] + attribute \src "ls180.v:832.5-832.43" + wire $0\main_sdram_choose_cmd_cmd_ready[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 2 $0\main_sdram_choose_cmd_grant[1:0] + attribute \src "ls180.v:3983.1-3989.4" + wire width 4 $0\main_sdram_choose_cmd_valids[3:0] + attribute \src "ls180.v:830.5-830.48" + wire $0\main_sdram_choose_cmd_want_activates[0:0] + attribute \src "ls180.v:829.5-829.43" + wire $0\main_sdram_choose_cmd_want_cmds[0:0] + attribute \src "ls180.v:827.5-827.44" + wire $0\main_sdram_choose_cmd_want_reads[0:0] + attribute \src "ls180.v:828.5-828.45" + wire $0\main_sdram_choose_cmd_want_writes[0:0] + attribute \src "ls180.v:4030.1-4035.4" + wire $0\main_sdram_choose_req_cmd_payload_cas[0:0] + attribute \src "ls180.v:4036.1-4041.4" + wire $0\main_sdram_choose_req_cmd_payload_ras[0:0] + attribute \src "ls180.v:4042.1-4047.4" + wire $0\main_sdram_choose_req_cmd_payload_we[0:0] + attribute \src "ls180.v:4088.1-4160.4" + wire $0\main_sdram_choose_req_cmd_ready[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 2 $0\main_sdram_choose_req_grant[1:0] + attribute \src "ls180.v:4016.1-4022.4" + wire width 4 $0\main_sdram_choose_req_valids[3:0] + attribute \src "ls180.v:4088.1-4160.4" + wire $0\main_sdram_choose_req_want_activates[0:0] + attribute \src "ls180.v:4088.1-4160.4" + wire $0\main_sdram_choose_req_want_reads[0:0] + attribute \src "ls180.v:4088.1-4160.4" + wire $0\main_sdram_choose_req_want_writes[0:0] + attribute \src "ls180.v:3305.1-3335.4" + wire $0\main_sdram_cmd_last[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 13 $0\main_sdram_cmd_payload_a[12:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 2 $0\main_sdram_cmd_payload_ba[1:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdram_cmd_payload_cas[0:0] + attribute \src "ls180.v:480.5-480.42" + wire $0\main_sdram_cmd_payload_is_read[0:0] + attribute \src "ls180.v:481.5-481.43" + wire $0\main_sdram_cmd_payload_is_write[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdram_cmd_payload_ras[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdram_cmd_payload_we[0:0] + attribute \src "ls180.v:4088.1-4160.4" + wire $0\main_sdram_cmd_ready[0:0] + attribute \src "ls180.v:3305.1-3335.4" + wire $0\main_sdram_cmd_valid[0:0] + attribute \src "ls180.v:416.5-416.38" + wire $0\main_sdram_command_issue_w[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdram_command_re[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 6 $0\main_sdram_command_storage[5:0] + attribute \src "ls180.v:465.5-465.35" + wire $0\main_sdram_dfi_p0_act_n[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 13 $0\main_sdram_dfi_p0_address[12:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 2 $0\main_sdram_dfi_p0_bank[1:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdram_dfi_p0_cas_n[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdram_dfi_p0_cs_n[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdram_dfi_p0_ras_n[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdram_dfi_p0_rddata_en[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdram_dfi_p0_we_n[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdram_dfi_p0_wrdata_en[0:0] + attribute \src "ls180.v:4088.1-4160.4" + wire $0\main_sdram_en0[0:0] + attribute \src "ls180.v:4088.1-4160.4" + wire $0\main_sdram_en1[0:0] + attribute \src "ls180.v:4184.1-4197.4" + wire width 16 $0\main_sdram_interface_wdata[15:0] + attribute \src "ls180.v:4184.1-4197.4" + wire width 2 $0\main_sdram_interface_wdata_we[1:0] + attribute \src "ls180.v:366.5-366.36" + wire $0\main_sdram_inti_p0_act_n[0:0] + attribute \src "ls180.v:3246.1-3262.4" + wire $0\main_sdram_inti_p0_cas_n[0:0] + attribute \src "ls180.v:3246.1-3262.4" + wire $0\main_sdram_inti_p0_cs_n[0:0] + attribute \src "ls180.v:3246.1-3262.4" + wire $0\main_sdram_inti_p0_ras_n[0:0] + attribute \src "ls180.v:3188.1-3242.4" + wire width 16 $0\main_sdram_inti_p0_rddata[15:0] + attribute \src "ls180.v:3188.1-3242.4" + wire $0\main_sdram_inti_p0_rddata_valid[0:0] + attribute \src "ls180.v:3246.1-3262.4" + wire $0\main_sdram_inti_p0_we_n[0:0] + attribute \src "ls180.v:3188.1-3242.4" + wire $0\main_sdram_master_p0_act_n[0:0] + attribute \src "ls180.v:3188.1-3242.4" + wire width 13 $0\main_sdram_master_p0_address[12:0] + attribute \src "ls180.v:3188.1-3242.4" + wire width 2 $0\main_sdram_master_p0_bank[1:0] + attribute \src "ls180.v:3188.1-3242.4" + wire $0\main_sdram_master_p0_cas_n[0:0] + attribute \src "ls180.v:3188.1-3242.4" + wire $0\main_sdram_master_p0_cke[0:0] + attribute \src "ls180.v:3188.1-3242.4" + wire $0\main_sdram_master_p0_cs_n[0:0] + attribute \src "ls180.v:3188.1-3242.4" + wire $0\main_sdram_master_p0_odt[0:0] + attribute \src "ls180.v:3188.1-3242.4" + wire $0\main_sdram_master_p0_ras_n[0:0] + attribute \src "ls180.v:3188.1-3242.4" + wire $0\main_sdram_master_p0_rddata_en[0:0] + attribute \src "ls180.v:3188.1-3242.4" + wire $0\main_sdram_master_p0_reset_n[0:0] + attribute \src "ls180.v:3188.1-3242.4" + wire $0\main_sdram_master_p0_we_n[0:0] + attribute \src "ls180.v:3188.1-3242.4" + wire width 16 $0\main_sdram_master_p0_wrdata[15:0] + attribute \src "ls180.v:3188.1-3242.4" + wire $0\main_sdram_master_p0_wrdata_en[0:0] + attribute \src "ls180.v:3188.1-3242.4" + wire width 2 $0\main_sdram_master_p0_wrdata_mask[1:0] + attribute \src "ls180.v:863.12-863.36" + wire width 13 $0\main_sdram_nop_a[12:0] + attribute \src "ls180.v:864.11-864.35" + wire width 2 $0\main_sdram_nop_ba[1:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdram_postponer_count[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdram_postponer_req_o[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdram_re[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdram_sequencer_count[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 4 $0\main_sdram_sequencer_counter[3:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdram_sequencer_done1[0:0] + attribute \src "ls180.v:3305.1-3335.4" + wire $0\main_sdram_sequencer_start0[0:0] + attribute \src "ls180.v:3188.1-3242.4" + wire width 16 $0\main_sdram_slave_p0_rddata[15:0] + attribute \src "ls180.v:3188.1-3242.4" + wire $0\main_sdram_slave_p0_rddata_valid[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 16 $0\main_sdram_status[15:0] + attribute \src "ls180.v:866.5-866.31" + wire $0\main_sdram_steerer0[0:0] + attribute \src "ls180.v:867.5-867.31" + wire $0\main_sdram_steerer1[0:0] + attribute \src "ls180.v:4088.1-4160.4" + wire width 2 $0\main_sdram_steerer_sel[1:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 4 $0\main_sdram_storage[3:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdram_tccdcon_count[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdram_tccdcon_ready[0:0] + attribute \src "ls180.v:871.32-871.63" + wire $0\main_sdram_tfawcon_ready[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 5 $0\main_sdram_time0[4:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 4 $0\main_sdram_time1[3:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 10 $0\main_sdram_timer_count1[9:0] + attribute \src "ls180.v:869.32-869.63" + wire $0\main_sdram_trrdcon_ready[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 3 $0\main_sdram_twtrcon_count[2:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdram_twtrcon_ready[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_sdram_wrdata_re[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 16 $0\main_sdram_wrdata_storage[15:0] + attribute \src "ls180.v:3023.1-3069.4" + wire $0\main_socbushandler_converted_interface_ack[0:0] + attribute \src "ls180.v:918.5-918.54" + wire $0\main_socbushandler_converted_interface_err[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_socbushandler_counter[0:0] + attribute \src "ls180.v:3023.1-3069.4" + wire $0\main_socbushandler_counter_converter2_next_value[0:0] + attribute \src "ls180.v:3023.1-3069.4" + wire $0\main_socbushandler_counter_converter2_next_value_ce[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 64 $0\main_socbushandler_dat_r[63:0] + attribute \src "ls180.v:3023.1-3069.4" + wire $0\main_socbushandler_skip[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 16 $0\main_spimaster11_storage[15:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_spimaster12_re[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 8 $0\main_spimaster16_storage[7:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_spimaster17_re[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_spimaster1_re[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 16 $0\main_spimaster1_storage[15:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_spimaster21_storage[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_spimaster22_re[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_spimaster23_storage[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_spimaster24_re[0:0] + attribute \src "ls180.v:4417.1-4465.4" + wire $0\main_spimaster25_clk_enable[0:0] + attribute \src "ls180.v:4417.1-4465.4" + wire $0\main_spimaster26_cs_enable[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 3 $0\main_spimaster27_count[2:0] + attribute \src "ls180.v:4417.1-4465.4" + wire width 3 $0\main_spimaster27_count_spimaster0_next_value[2:0] + attribute \src "ls180.v:4417.1-4465.4" + wire $0\main_spimaster27_count_spimaster0_next_value_ce[0:0] + attribute \src "ls180.v:4417.1-4465.4" + wire $0\main_spimaster28_mosi_latch[0:0] + attribute \src "ls180.v:4417.1-4465.4" + wire $0\main_spimaster29_miso_latch[0:0] + attribute \src "ls180.v:4417.1-4465.4" + wire $0\main_spimaster2_done[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 16 $0\main_spimaster30_clk_divider[15:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 8 $0\main_spimaster33_mosi_data[7:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 3 $0\main_spimaster34_mosi_sel[2:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 8 $0\main_spimaster35_miso_data[7:0] + attribute \src "ls180.v:4417.1-4465.4" + wire $0\main_spimaster3_irq[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 8 $0\main_spimaster5_miso[7:0] + attribute \src "ls180.v:1105.12-1105.47" + wire width 16 $0\main_spimaster8_clk_divider[15:0] + attribute \src "ls180.v:6553.1-6558.4" + wire $0\main_spimaster9_start[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 16 $0\main_spisdcard_clk_divider1[15:0] + attribute \src "ls180.v:4476.1-4524.4" + wire $0\main_spisdcard_clk_enable[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_spisdcard_control_re[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 16 $0\main_spisdcard_control_storage[15:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 3 $0\main_spisdcard_count[2:0] + attribute \src "ls180.v:4476.1-4524.4" + wire width 3 $0\main_spisdcard_count_spimaster1_next_value[2:0] + attribute \src "ls180.v:4476.1-4524.4" + wire $0\main_spisdcard_count_spimaster1_next_value_ce[0:0] + attribute \src "ls180.v:4476.1-4524.4" + wire $0\main_spisdcard_cs_enable[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_spisdcard_cs_re[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_spisdcard_cs_storage[0:0] + attribute \src "ls180.v:4476.1-4524.4" + wire $0\main_spisdcard_done0[0:0] + attribute \src "ls180.v:4476.1-4524.4" + wire $0\main_spisdcard_irq[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_spisdcard_loopback_re[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_spisdcard_loopback_storage[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 8 $0\main_spisdcard_miso[7:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 8 $0\main_spisdcard_miso_data[7:0] + attribute \src "ls180.v:4476.1-4524.4" + wire $0\main_spisdcard_miso_latch[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 8 $0\main_spisdcard_mosi_data[7:0] + attribute \src "ls180.v:4476.1-4524.4" + wire $0\main_spisdcard_mosi_latch[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_spisdcard_mosi_re[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 3 $0\main_spisdcard_mosi_sel[2:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 8 $0\main_spisdcard_mosi_storage[7:0] + attribute \src "ls180.v:6599.1-6604.4" + wire $0\main_spisdcard_start1[0:0] + attribute \src "ls180.v:3097.1-3107.4" + wire width 8 $0\main_sram0_we[7:0] + attribute \src "ls180.v:3111.1-3121.4" + wire width 8 $0\main_sram1_we[7:0] + attribute \src "ls180.v:3125.1-3135.4" + wire width 8 $0\main_sram2_we[7:0] + attribute \src "ls180.v:3139.1-3149.4" + wire width 8 $0\main_sram3_we[7:0] + attribute \src "ls180.v:4324.1-4328.4" + wire width 2 $0\main_uart_eventmanager_pending_w[1:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_uart_eventmanager_re[0:0] + attribute \src "ls180.v:4313.1-4317.4" + wire width 2 $0\main_uart_eventmanager_status_w[1:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 2 $0\main_uart_eventmanager_storage[1:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 32 $0\main_uart_phy_phase_accumulator_rx[31:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 32 $0\main_uart_phy_phase_accumulator_tx[31:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_uart_phy_re[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 4 $0\main_uart_phy_rx_bitcount[3:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_uart_phy_rx_busy[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_uart_phy_rx_r[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 8 $0\main_uart_phy_rx_reg[7:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_uart_phy_sink_ready[0:0] + attribute \src "ls180.v:954.5-954.38" + wire $0\main_uart_phy_source_first[0:0] + attribute \src "ls180.v:955.5-955.37" + wire $0\main_uart_phy_source_last[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 8 $0\main_uart_phy_source_payload_data[7:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_uart_phy_source_valid[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 32 $0\main_uart_phy_storage[31:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 4 $0\main_uart_phy_tx_bitcount[3:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_uart_phy_tx_busy[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 8 $0\main_uart_phy_tx_reg[7:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_uart_phy_uart_clk_rxen[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_uart_phy_uart_clk_txen[0:0] + attribute \src "ls180.v:1081.5-1081.27" + wire $0\main_uart_reset[0:0] + attribute \src "ls180.v:4318.1-4323.4" + wire $0\main_uart_rx_clear[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 4 $0\main_uart_rx_fifo_consume[3:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 5 $0\main_uart_rx_fifo_level0[4:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 4 $0\main_uart_rx_fifo_produce[3:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_uart_rx_fifo_readable[0:0] + attribute \src "ls180.v:1063.5-1063.37" + wire $0\main_uart_rx_fifo_replace[0:0] + attribute \src "ls180.v:4376.1-4383.4" + wire width 4 $0\main_uart_rx_fifo_wrport_adr[3:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_uart_rx_old_trigger[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_uart_rx_pending[0:0] + attribute \src "ls180.v:4307.1-4312.4" + wire $0\main_uart_tx_clear[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 4 $0\main_uart_tx_fifo_consume[3:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 5 $0\main_uart_tx_fifo_level0[4:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 4 $0\main_uart_tx_fifo_produce[3:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_uart_tx_fifo_readable[0:0] + attribute \src "ls180.v:1026.5-1026.37" + wire $0\main_uart_tx_fifo_replace[0:0] + attribute \src "ls180.v:1009.5-1009.40" + wire $0\main_uart_tx_fifo_sink_first[0:0] + attribute \src "ls180.v:1010.5-1010.39" + wire $0\main_uart_tx_fifo_sink_last[0:0] + attribute \src "ls180.v:4346.1-4353.4" + wire width 4 $0\main_uart_tx_fifo_wrport_adr[3:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_uart_tx_old_trigger[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_uart_tx_pending[0:0] + attribute \src "ls180.v:4216.1-4262.4" + wire $0\main_wb_sdram_ack[0:0] + attribute \src "ls180.v:3023.1-3069.4" + wire width 30 $0\main_wb_sdram_adr[29:0] + attribute \src "ls180.v:3023.1-3069.4" + wire $0\main_wb_sdram_cyc[0:0] + attribute \src "ls180.v:3011.1-3021.4" + wire width 32 $0\main_wb_sdram_dat_w[31:0] + attribute \src "ls180.v:3023.1-3069.4" + wire width 4 $0\main_wb_sdram_sel[3:0] + attribute \src "ls180.v:3023.1-3069.4" + wire $0\main_wb_sdram_stb[0:0] + attribute \src "ls180.v:3023.1-3069.4" + wire $0\main_wb_sdram_we[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\main_wdata_consumed[0:0] + attribute \src "ls180.v:10350.1-10368.4" + wire width 6 $0\memadr[5:0] + attribute \src "ls180.v:10378.1-10396.4" + wire width 6 $0\memadr_1[5:0] + attribute \src "ls180.v:10406.1-10424.4" + wire width 6 $0\memadr_2[5:0] + attribute \src "ls180.v:10434.1-10452.4" + wire width 6 $0\memadr_3[5:0] + attribute \src "ls180.v:10462.1-10480.4" + wire width 6 $0\memadr_4[5:0] + attribute \src "ls180.v:10490.1-10494.4" + wire width 25 $0\memdat[24:0] + attribute \src "ls180.v:10504.1-10508.4" + wire width 25 $0\memdat_1[24:0] + attribute \src "ls180.v:10518.1-10522.4" + wire width 25 $0\memdat_2[24:0] + attribute \src "ls180.v:10532.1-10536.4" + wire width 25 $0\memdat_3[24:0] + attribute \src "ls180.v:10547.1-10551.4" + wire width 10 $0\memdat_4[9:0] + attribute \src "ls180.v:10553.1-10556.4" + wire width 10 $0\memdat_5[9:0] + attribute \src "ls180.v:10564.1-10568.4" + wire width 10 $0\memdat_6[9:0] + attribute \src "ls180.v:10570.1-10573.4" + wire width 10 $0\memdat_7[9:0] + attribute \src "ls180.v:10580.1-10584.4" + wire width 10 $0\memdat_8[9:0] + attribute \src "ls180.v:10594.1-10598.4" + wire width 10 $0\memdat_9[9:0] + attribute \src "ls180.v:7702.1-10346.4" + wire width 2 $0\pwm[1:0] + attribute \src "ls180.v:7630.1-7700.4" + wire $0\sdcard_clk[0:0] + attribute \src "ls180.v:7630.1-7700.4" + wire $0\sdcard_cmd_o[0:0] + attribute \src "ls180.v:7630.1-7700.4" + wire $0\sdcard_cmd_oe[0:0] + attribute \src "ls180.v:7630.1-7700.4" + wire width 4 $0\sdcard_data_o[3:0] + attribute \src "ls180.v:7630.1-7700.4" + wire $0\sdcard_data_oe[0:0] + attribute \src "ls180.v:7630.1-7700.4" + wire width 13 $0\sdram_a[12:0] + attribute \src "ls180.v:7630.1-7700.4" + wire width 2 $0\sdram_ba[1:0] + attribute \src "ls180.v:7630.1-7700.4" + wire $0\sdram_cas_n[0:0] + attribute \src "ls180.v:7630.1-7700.4" + wire $0\sdram_cke[0:0] + attribute \src "ls180.v:7630.1-7700.4" + wire $0\sdram_clock[0:0] + attribute \src "ls180.v:7630.1-7700.4" + wire $0\sdram_cs_n[0:0] + attribute \src "ls180.v:7630.1-7700.4" + wire width 2 $0\sdram_dm[1:0] + attribute \src "ls180.v:7630.1-7700.4" + wire width 16 $0\sdram_dq_o[15:0] + attribute \src "ls180.v:7630.1-7700.4" + wire $0\sdram_dq_oe[0:0] + attribute \src "ls180.v:7630.1-7700.4" + wire $0\sdram_ras_n[0:0] + attribute \src "ls180.v:7630.1-7700.4" + wire $0\sdram_we_n[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\spimaster_clk[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\spimaster_cs_n[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\spimaster_mosi[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\spisdcard_clk[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\spisdcard_cs_n[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\spisdcard_mosi[0:0] + attribute \src "ls180.v:7702.1-10346.4" + wire $0\uart_tx[0:0] + attribute \src "ls180.v:1854.11-1854.49" + wire width 3 $1\builder_bankmachine0_next_state[2:0] + attribute \src "ls180.v:1853.11-1853.44" + wire width 3 $1\builder_bankmachine0_state[2:0] + attribute \src "ls180.v:1856.11-1856.49" + wire width 3 $1\builder_bankmachine1_next_state[2:0] + attribute \src "ls180.v:1855.11-1855.44" + wire width 3 $1\builder_bankmachine1_state[2:0] + attribute \src "ls180.v:1858.11-1858.49" + wire width 3 $1\builder_bankmachine2_next_state[2:0] + attribute \src "ls180.v:1857.11-1857.44" + wire width 3 $1\builder_bankmachine2_state[2:0] + attribute \src "ls180.v:1860.11-1860.49" + wire width 3 $1\builder_bankmachine3_next_state[2:0] + attribute \src "ls180.v:1859.11-1859.44" + wire width 3 $1\builder_bankmachine3_state[2:0] + attribute \src "ls180.v:2713.5-2713.41" + wire $1\builder_comb_rhs_array_muxed0[0:0] + attribute \src "ls180.v:2726.5-2726.42" + wire $1\builder_comb_rhs_array_muxed10[0:0] + attribute \src "ls180.v:2727.5-2727.42" + wire $1\builder_comb_rhs_array_muxed11[0:0] + attribute \src "ls180.v:2731.12-2731.50" + wire width 22 $1\builder_comb_rhs_array_muxed12[21:0] + attribute \src "ls180.v:2732.5-2732.42" + wire $1\builder_comb_rhs_array_muxed13[0:0] + attribute \src "ls180.v:2733.5-2733.42" + wire $1\builder_comb_rhs_array_muxed14[0:0] + attribute \src "ls180.v:2734.12-2734.50" + wire width 22 $1\builder_comb_rhs_array_muxed15[21:0] + attribute \src "ls180.v:2735.5-2735.42" + wire $1\builder_comb_rhs_array_muxed16[0:0] + attribute \src "ls180.v:2736.5-2736.42" + wire $1\builder_comb_rhs_array_muxed17[0:0] + attribute \src "ls180.v:2737.12-2737.50" + wire width 22 $1\builder_comb_rhs_array_muxed18[21:0] + attribute \src "ls180.v:2738.5-2738.42" + wire $1\builder_comb_rhs_array_muxed19[0:0] + attribute \src "ls180.v:2714.12-2714.49" + wire width 13 $1\builder_comb_rhs_array_muxed1[12:0] + attribute \src "ls180.v:2739.5-2739.42" + wire $1\builder_comb_rhs_array_muxed20[0:0] + attribute \src "ls180.v:2740.12-2740.50" + wire width 22 $1\builder_comb_rhs_array_muxed21[21:0] + attribute \src "ls180.v:2741.5-2741.42" + wire $1\builder_comb_rhs_array_muxed22[0:0] + attribute \src "ls180.v:2742.5-2742.42" + wire $1\builder_comb_rhs_array_muxed23[0:0] + attribute \src "ls180.v:2743.12-2743.50" + wire width 32 $1\builder_comb_rhs_array_muxed24[31:0] + attribute \src "ls180.v:2744.12-2744.50" + wire width 64 $1\builder_comb_rhs_array_muxed25[63:0] + attribute \src "ls180.v:2745.11-2745.48" + wire width 8 $1\builder_comb_rhs_array_muxed26[7:0] + attribute \src "ls180.v:2746.5-2746.42" + wire $1\builder_comb_rhs_array_muxed27[0:0] + attribute \src "ls180.v:2747.5-2747.42" + wire $1\builder_comb_rhs_array_muxed28[0:0] + attribute \src "ls180.v:2748.5-2748.42" + wire $1\builder_comb_rhs_array_muxed29[0:0] + attribute \src "ls180.v:2715.11-2715.47" + wire width 2 $1\builder_comb_rhs_array_muxed2[1:0] + attribute \src "ls180.v:2749.11-2749.48" + wire width 3 $1\builder_comb_rhs_array_muxed30[2:0] + attribute \src "ls180.v:2750.11-2750.48" + wire width 2 $1\builder_comb_rhs_array_muxed31[1:0] + attribute \src "ls180.v:2716.5-2716.41" + wire $1\builder_comb_rhs_array_muxed3[0:0] + attribute \src "ls180.v:2717.5-2717.41" + wire $1\builder_comb_rhs_array_muxed4[0:0] + attribute \src "ls180.v:2718.5-2718.41" + wire $1\builder_comb_rhs_array_muxed5[0:0] + attribute \src "ls180.v:2722.5-2722.41" + wire $1\builder_comb_rhs_array_muxed6[0:0] + attribute \src "ls180.v:2723.12-2723.49" + wire width 13 $1\builder_comb_rhs_array_muxed7[12:0] + attribute \src "ls180.v:2724.11-2724.47" + wire width 2 $1\builder_comb_rhs_array_muxed8[1:0] + attribute \src "ls180.v:2725.5-2725.41" + wire $1\builder_comb_rhs_array_muxed9[0:0] + attribute \src "ls180.v:2719.5-2719.39" + wire $1\builder_comb_t_array_muxed0[0:0] + attribute \src "ls180.v:2720.5-2720.39" + wire $1\builder_comb_t_array_muxed1[0:0] + attribute \src "ls180.v:2721.5-2721.39" + wire $1\builder_comb_t_array_muxed2[0:0] + attribute \src "ls180.v:2728.5-2728.39" + wire $1\builder_comb_t_array_muxed3[0:0] + attribute \src "ls180.v:2729.5-2729.39" + wire $1\builder_comb_t_array_muxed4[0:0] + attribute \src "ls180.v:2730.5-2730.39" + wire $1\builder_comb_t_array_muxed5[0:0] + attribute \src "ls180.v:1840.5-1840.41" + wire $1\builder_converter0_next_state[0:0] + attribute \src "ls180.v:1839.5-1839.36" + wire $1\builder_converter0_state[0:0] + attribute \src "ls180.v:1844.5-1844.41" + wire $1\builder_converter1_next_state[0:0] + attribute \src "ls180.v:1843.5-1843.36" + wire $1\builder_converter1_state[0:0] + attribute \src "ls180.v:1848.5-1848.41" + wire $1\builder_converter2_next_state[0:0] + attribute \src "ls180.v:1847.5-1847.36" + wire $1\builder_converter2_state[0:0] + attribute \src "ls180.v:1885.5-1885.40" + wire $1\builder_converter_next_state[0:0] + attribute \src "ls180.v:1884.5-1884.35" + wire $1\builder_converter_state[0:0] + attribute \src "ls180.v:2013.12-2013.39" + wire width 20 $1\builder_count[19:0] + attribute \src "ls180.v:2010.5-2010.25" + wire $1\builder_error[0:0] + attribute \src "ls180.v:2007.11-2007.31" + wire width 3 $1\builder_grant[2:0] + attribute \src "ls180.v:2017.11-2017.51" + wire width 8 $1\builder_interface0_bank_bus_dat_r[7:0] + attribute \src "ls180.v:2519.11-2519.52" + wire width 8 $1\builder_interface10_bank_bus_dat_r[7:0] + attribute \src "ls180.v:2552.11-2552.52" + wire width 8 $1\builder_interface11_bank_bus_dat_r[7:0] + attribute \src "ls180.v:2593.11-2593.52" + wire width 8 $1\builder_interface12_bank_bus_dat_r[7:0] + attribute \src "ls180.v:2658.11-2658.52" + wire width 8 $1\builder_interface13_bank_bus_dat_r[7:0] + attribute \src "ls180.v:2683.11-2683.52" + wire width 8 $1\builder_interface14_bank_bus_dat_r[7:0] + attribute \src "ls180.v:2058.11-2058.51" + wire width 8 $1\builder_interface1_bank_bus_dat_r[7:0] + attribute \src "ls180.v:2087.11-2087.51" + wire width 8 $1\builder_interface2_bank_bus_dat_r[7:0] + attribute \src "ls180.v:2100.11-2100.51" + wire width 8 $1\builder_interface3_bank_bus_dat_r[7:0] + attribute \src "ls180.v:2141.11-2141.51" + wire width 8 $1\builder_interface4_bank_bus_dat_r[7:0] + attribute \src "ls180.v:2182.11-2182.51" + wire width 8 $1\builder_interface5_bank_bus_dat_r[7:0] + attribute \src "ls180.v:2247.11-2247.51" + wire width 8 $1\builder_interface6_bank_bus_dat_r[7:0] + attribute \src "ls180.v:2380.11-2380.51" + wire width 8 $1\builder_interface7_bank_bus_dat_r[7:0] + attribute \src "ls180.v:2461.11-2461.51" + wire width 8 $1\builder_interface8_bank_bus_dat_r[7:0] + attribute \src "ls180.v:2478.11-2478.51" + wire width 8 $1\builder_interface9_bank_bus_dat_r[7:0] + attribute \src "ls180.v:1972.12-1972.43" + wire width 14 $1\builder_libresocsim_adr[13:0] + attribute \src "ls180.v:2709.12-2709.55" + wire width 14 $1\builder_libresocsim_adr_next_value1[13:0] + attribute \src "ls180.v:2710.5-2710.50" + wire $1\builder_libresocsim_adr_next_value_ce1[0:0] + attribute \src "ls180.v:1974.11-1974.43" + wire width 8 $1\builder_libresocsim_dat_w[7:0] + attribute \src "ls180.v:2707.11-2707.55" + wire width 8 $1\builder_libresocsim_dat_w_next_value0[7:0] + attribute \src "ls180.v:2708.5-2708.52" + wire $1\builder_libresocsim_dat_w_next_value_ce0[0:0] + attribute \src "ls180.v:1973.5-1973.34" + wire $1\builder_libresocsim_we[0:0] + attribute \src "ls180.v:2711.5-2711.46" + wire $1\builder_libresocsim_we_next_value2[0:0] + attribute \src "ls180.v:2712.5-2712.49" + wire $1\builder_libresocsim_we_next_value_ce2[0:0] + attribute \src "ls180.v:1982.5-1982.44" + wire $1\builder_libresocsim_wishbone_ack[0:0] + attribute \src "ls180.v:1978.12-1978.54" + wire width 32 $1\builder_libresocsim_wishbone_dat_r[31:0] + attribute \src "ls180.v:1862.11-1862.48" + wire width 3 $1\builder_multiplexer_next_state[2:0] + attribute \src "ls180.v:1861.11-1861.43" + wire width 3 $1\builder_multiplexer_state[2:0] + attribute \src "ls180.v:2816.32-2816.66" + wire $1\builder_multiregimpl0_regs0[0:0] + attribute \src "ls180.v:2817.32-2817.66" + wire $1\builder_multiregimpl0_regs1[0:0] + attribute \src "ls180.v:2836.32-2836.67" + wire $1\builder_multiregimpl10_regs0[0:0] + attribute \src "ls180.v:2837.32-2837.67" + wire $1\builder_multiregimpl10_regs1[0:0] + attribute \src "ls180.v:2838.32-2838.67" + wire $1\builder_multiregimpl11_regs0[0:0] + attribute \src "ls180.v:2839.32-2839.67" + wire $1\builder_multiregimpl11_regs1[0:0] + attribute \src "ls180.v:2840.32-2840.67" + wire $1\builder_multiregimpl12_regs0[0:0] + attribute \src "ls180.v:2841.32-2841.67" + wire $1\builder_multiregimpl12_regs1[0:0] + attribute \src "ls180.v:2842.32-2842.67" + wire $1\builder_multiregimpl13_regs0[0:0] + attribute \src "ls180.v:2843.32-2843.67" + wire $1\builder_multiregimpl13_regs1[0:0] + attribute \src "ls180.v:2844.32-2844.67" + wire $1\builder_multiregimpl14_regs0[0:0] + attribute \src "ls180.v:2845.32-2845.67" + wire $1\builder_multiregimpl14_regs1[0:0] + attribute \src "ls180.v:2846.32-2846.67" + wire $1\builder_multiregimpl15_regs0[0:0] + attribute \src "ls180.v:2847.32-2847.67" + wire $1\builder_multiregimpl15_regs1[0:0] + attribute \src "ls180.v:2848.32-2848.67" + wire $1\builder_multiregimpl16_regs0[0:0] + attribute \src "ls180.v:2849.32-2849.67" + wire $1\builder_multiregimpl16_regs1[0:0] + attribute \src "ls180.v:2818.32-2818.66" + wire $1\builder_multiregimpl1_regs0[0:0] + attribute \src "ls180.v:2819.32-2819.66" + wire $1\builder_multiregimpl1_regs1[0:0] + attribute \src "ls180.v:2820.32-2820.66" + wire $1\builder_multiregimpl2_regs0[0:0] + attribute \src "ls180.v:2821.32-2821.66" + wire $1\builder_multiregimpl2_regs1[0:0] + attribute \src "ls180.v:2822.32-2822.66" + wire $1\builder_multiregimpl3_regs0[0:0] + attribute \src "ls180.v:2823.32-2823.66" + wire $1\builder_multiregimpl3_regs1[0:0] + attribute \src "ls180.v:2824.32-2824.66" + wire $1\builder_multiregimpl4_regs0[0:0] + attribute \src "ls180.v:2825.32-2825.66" + wire $1\builder_multiregimpl4_regs1[0:0] + attribute \src "ls180.v:2826.32-2826.66" + wire $1\builder_multiregimpl5_regs0[0:0] + attribute \src "ls180.v:2827.32-2827.66" + wire $1\builder_multiregimpl5_regs1[0:0] + attribute \src "ls180.v:2828.32-2828.66" + wire $1\builder_multiregimpl6_regs0[0:0] + attribute \src "ls180.v:2829.32-2829.66" + wire $1\builder_multiregimpl6_regs1[0:0] + attribute \src "ls180.v:2830.32-2830.66" + wire $1\builder_multiregimpl7_regs0[0:0] + attribute \src "ls180.v:2831.32-2831.66" + wire $1\builder_multiregimpl7_regs1[0:0] + attribute \src "ls180.v:2832.32-2832.66" + wire $1\builder_multiregimpl8_regs0[0:0] + attribute \src "ls180.v:2833.32-2833.66" + wire $1\builder_multiregimpl8_regs1[0:0] + attribute \src "ls180.v:2834.32-2834.66" + wire $1\builder_multiregimpl9_regs0[0:0] + attribute \src "ls180.v:2835.32-2835.66" + wire $1\builder_multiregimpl9_regs1[0:0] + attribute \src "ls180.v:1880.5-1880.43" + wire $1\builder_new_master_rdata_valid0[0:0] + attribute \src "ls180.v:1881.5-1881.43" + wire $1\builder_new_master_rdata_valid1[0:0] + attribute \src "ls180.v:1882.5-1882.43" + wire $1\builder_new_master_rdata_valid2[0:0] + attribute \src "ls180.v:1883.5-1883.43" + wire $1\builder_new_master_rdata_valid3[0:0] + attribute \src "ls180.v:1879.5-1879.42" + wire $1\builder_new_master_wdata_ready[0:0] + attribute \src "ls180.v:2706.11-2706.36" + wire width 2 $1\builder_next_state[1:0] + attribute \src "ls180.v:1852.11-1852.46" + wire width 2 $1\builder_refresher_next_state[1:0] + attribute \src "ls180.v:1851.11-1851.41" + wire width 2 $1\builder_refresher_state[1:0] + attribute \src "ls180.v:1961.11-1961.51" + wire width 2 $1\builder_sdblock2memdma_next_state[1:0] + attribute \src "ls180.v:1960.11-1960.46" + wire width 2 $1\builder_sdblock2memdma_state[1:0] + attribute \src "ls180.v:1929.5-1929.57" + wire $1\builder_sdcore_crcupstreaminserter_next_state[0:0] + attribute \src "ls180.v:1928.5-1928.52" + wire $1\builder_sdcore_crcupstreaminserter_state[0:0] + attribute \src "ls180.v:1941.11-1941.47" + wire width 3 $1\builder_sdcore_fsm_next_state[2:0] + attribute \src "ls180.v:1940.11-1940.42" + wire width 3 $1\builder_sdcore_fsm_state[2:0] + attribute \src "ls180.v:1965.5-1965.49" + wire $1\builder_sdmem2blockdma_fsm_next_state[0:0] + attribute \src "ls180.v:1964.5-1964.44" + wire $1\builder_sdmem2blockdma_fsm_state[0:0] + attribute \src "ls180.v:1969.11-1969.65" + wire width 2 $1\builder_sdmem2blockdma_resetinserter_next_state[1:0] + attribute \src "ls180.v:1968.11-1968.60" + wire width 2 $1\builder_sdmem2blockdma_resetinserter_state[1:0] + attribute \src "ls180.v:1917.11-1917.46" + wire width 3 $1\builder_sdphy_fsm_next_state[2:0] + attribute \src "ls180.v:1916.11-1916.41" + wire width 3 $1\builder_sdphy_fsm_state[2:0] + attribute \src "ls180.v:1905.11-1905.52" + wire width 3 $1\builder_sdphy_sdphycmdr_next_state[2:0] + attribute \src "ls180.v:1904.11-1904.47" + wire width 3 $1\builder_sdphy_sdphycmdr_state[2:0] + attribute \src "ls180.v:1901.11-1901.52" + wire width 2 $1\builder_sdphy_sdphycmdw_next_state[1:0] + attribute \src "ls180.v:1900.11-1900.47" + wire width 2 $1\builder_sdphy_sdphycmdw_state[1:0] + attribute \src "ls180.v:1913.5-1913.46" + wire $1\builder_sdphy_sdphycrcr_next_state[0:0] + attribute \src "ls180.v:1912.5-1912.41" + wire $1\builder_sdphy_sdphycrcr_state[0:0] + attribute \src "ls180.v:1921.11-1921.53" + wire width 3 $1\builder_sdphy_sdphydatar_next_state[2:0] + attribute \src "ls180.v:1920.11-1920.48" + wire width 3 $1\builder_sdphy_sdphydatar_state[2:0] + attribute \src "ls180.v:1897.5-1897.46" + wire $1\builder_sdphy_sdphyinit_next_state[0:0] + attribute \src "ls180.v:1896.5-1896.41" + wire $1\builder_sdphy_sdphyinit_state[0:0] + attribute \src "ls180.v:2001.5-2001.30" + wire $1\builder_shared_ack[0:0] + attribute \src "ls180.v:1997.12-1997.40" + wire width 32 $1\builder_shared_dat_r[31:0] + attribute \src "ls180.v:2008.12-2008.37" + wire width 13 $1\builder_slave_sel[12:0] + attribute \src "ls180.v:2009.12-2009.39" + wire width 13 $1\builder_slave_sel_r[12:0] + attribute \src "ls180.v:1889.11-1889.47" + wire width 2 $1\builder_spimaster0_next_state[1:0] + attribute \src "ls180.v:1888.11-1888.42" + wire width 2 $1\builder_spimaster0_state[1:0] + attribute \src "ls180.v:1893.11-1893.47" + wire width 2 $1\builder_spimaster1_next_state[1:0] + attribute \src "ls180.v:1892.11-1892.42" + wire width 2 $1\builder_spimaster1_state[1:0] + attribute \src "ls180.v:2705.11-2705.31" + wire width 2 $1\builder_state[1:0] + attribute \src "ls180.v:2758.5-2758.39" + wire $1\builder_sync_f_array_muxed0[0:0] + attribute \src "ls180.v:2759.5-2759.39" + wire $1\builder_sync_f_array_muxed1[0:0] + attribute \src "ls180.v:2751.11-2751.47" + wire width 2 $1\builder_sync_rhs_array_muxed0[1:0] + attribute \src "ls180.v:2752.12-2752.49" + wire width 13 $1\builder_sync_rhs_array_muxed1[12:0] + attribute \src "ls180.v:2753.5-2753.41" + wire $1\builder_sync_rhs_array_muxed2[0:0] + attribute \src "ls180.v:2754.5-2754.41" + wire $1\builder_sync_rhs_array_muxed3[0:0] + attribute \src "ls180.v:2755.5-2755.41" + wire $1\builder_sync_rhs_array_muxed4[0:0] + attribute \src "ls180.v:2756.5-2756.41" + wire $1\builder_sync_rhs_array_muxed5[0:0] + attribute \src "ls180.v:2757.5-2757.41" + wire $1\builder_sync_rhs_array_muxed6[0:0] + attribute \src "ls180.v:935.5-935.29" + wire $1\main_cmd_consumed[0:0] + attribute \src "ls180.v:318.5-318.35" + wire $1\main_converter0_counter[0:0] + attribute \src "ls180.v:1841.5-1841.57" + wire $1\main_converter0_counter_converter0_next_value[0:0] + attribute \src "ls180.v:1842.5-1842.60" + wire $1\main_converter0_counter_converter0_next_value_ce[0:0] + attribute \src "ls180.v:320.12-320.41" + wire width 64 $1\main_converter0_dat_r[63:0] + attribute \src "ls180.v:317.5-317.32" + wire $1\main_converter0_skip[0:0] + attribute \src "ls180.v:333.5-333.35" + wire $1\main_converter1_counter[0:0] + attribute \src "ls180.v:1845.5-1845.57" + wire $1\main_converter1_counter_converter1_next_value[0:0] + attribute \src "ls180.v:1846.5-1846.60" + wire $1\main_converter1_counter_converter1_next_value_ce[0:0] + attribute \src "ls180.v:335.12-335.41" + wire width 64 $1\main_converter1_dat_r[63:0] + attribute \src "ls180.v:332.5-332.32" + wire $1\main_converter1_skip[0:0] + attribute \src "ls180.v:932.5-932.34" + wire $1\main_converter_counter[0:0] + attribute \src "ls180.v:1886.5-1886.55" + wire $1\main_converter_counter_converter_next_value[0:0] + attribute \src "ls180.v:1887.5-1887.58" + wire $1\main_converter_counter_converter_next_value_ce[0:0] + attribute \src "ls180.v:934.12-934.40" + wire width 32 $1\main_converter_dat_r[31:0] + attribute \src "ls180.v:931.5-931.31" + wire $1\main_converter_skip[0:0] + attribute \src "ls180.v:354.12-354.38" + wire width 16 $1\main_dfi_p0_rddata[15:0] + attribute \src "ls180.v:355.5-355.36" + wire $1\main_dfi_p0_rddata_valid[0:0] + attribute \src "ls180.v:1172.12-1172.30" + wire width 24 $1\main_dummy[23:0] + attribute \src "ls180.v:1083.12-1083.49" + wire width 16 $1\main_gpiotristateasic0_status[15:0] + attribute \src "ls180.v:1089.5-1089.40" + wire $1\main_gpiotristateasic1_oe_re[0:0] + attribute \src "ls180.v:1088.12-1088.53" + wire width 16 $1\main_gpiotristateasic1_oe_storage[15:0] + attribute \src "ls180.v:1093.5-1093.41" + wire $1\main_gpiotristateasic1_out_re[0:0] + attribute \src "ls180.v:1092.12-1092.54" + wire width 16 $1\main_gpiotristateasic1_out_storage[15:0] + attribute \src "ls180.v:1090.12-1090.49" + wire width 16 $1\main_gpiotristateasic1_status[15:0] + attribute \src "ls180.v:1197.5-1197.23" + wire $1\main_i2c_re[0:0] + attribute \src "ls180.v:1196.11-1196.34" + wire width 3 $1\main_i2c_storage[2:0] + attribute \src "ls180.v:339.5-339.24" + wire $1\main_int_rst[0:0] + attribute \src "ls180.v:312.5-312.51" + wire $1\main_interface0_converted_interface_ack[0:0] + attribute \src "ls180.v:252.5-252.39" + wire $1\main_interface0_ram_bus_ack[0:0] + attribute \src "ls180.v:1745.12-1745.43" + wire width 32 $1\main_interface1_bus_adr[31:0] + attribute \src "ls180.v:1749.5-1749.35" + wire $1\main_interface1_bus_cyc[0:0] + attribute \src "ls180.v:1748.11-1748.41" + wire width 8 $1\main_interface1_bus_sel[7:0] + attribute \src "ls180.v:1750.5-1750.35" + wire $1\main_interface1_bus_stb[0:0] + attribute \src "ls180.v:1752.5-1752.34" + wire $1\main_interface1_bus_we[0:0] + attribute \src "ls180.v:327.5-327.51" + wire $1\main_interface1_converted_interface_ack[0:0] + attribute \src "ls180.v:267.5-267.39" + wire $1\main_interface1_ram_bus_ack[0:0] + attribute \src "ls180.v:282.5-282.39" + wire $1\main_interface2_ram_bus_ack[0:0] + attribute \src "ls180.v:297.5-297.39" + wire $1\main_interface3_ram_bus_ack[0:0] + attribute \src "ls180.v:63.12-63.47" + wire width 32 $1\main_libresocsim_bus_errors[31:0] + attribute \src "ls180.v:224.5-224.34" + wire $1\main_libresocsim_en_re[0:0] + attribute \src "ls180.v:223.5-223.39" + wire $1\main_libresocsim_en_storage[0:0] + attribute \src "ls180.v:244.5-244.44" + wire $1\main_libresocsim_eventmanager_re[0:0] + attribute \src "ls180.v:243.5-243.49" + wire $1\main_libresocsim_eventmanager_storage[0:0] + attribute \src "ls180.v:65.12-65.55" + wire width 16 $1\main_libresocsim_libresoc_interrupt[15:0] + attribute \src "ls180.v:88.12-88.58" + wire width 30 $1\main_libresocsim_libresoc_xics_icp_adr[29:0] + attribute \src "ls180.v:92.5-92.50" + wire $1\main_libresocsim_libresoc_xics_icp_cyc[0:0] + attribute \src "ls180.v:89.12-89.60" + wire width 32 $1\main_libresocsim_libresoc_xics_icp_dat_w[31:0] + attribute \src "ls180.v:91.11-91.56" + wire width 4 $1\main_libresocsim_libresoc_xics_icp_sel[3:0] + attribute \src "ls180.v:93.5-93.50" + wire $1\main_libresocsim_libresoc_xics_icp_stb[0:0] + attribute \src "ls180.v:95.5-95.49" + wire $1\main_libresocsim_libresoc_xics_icp_we[0:0] + attribute \src "ls180.v:97.12-97.58" + wire width 30 $1\main_libresocsim_libresoc_xics_ics_adr[29:0] + attribute \src "ls180.v:101.5-101.50" + wire $1\main_libresocsim_libresoc_xics_ics_cyc[0:0] + attribute \src "ls180.v:98.12-98.60" + wire width 32 $1\main_libresocsim_libresoc_xics_ics_dat_w[31:0] + attribute \src "ls180.v:100.11-100.56" + wire width 4 $1\main_libresocsim_libresoc_xics_ics_sel[3:0] + attribute \src "ls180.v:102.5-102.50" + wire $1\main_libresocsim_libresoc_xics_ics_stb[0:0] + attribute \src "ls180.v:104.5-104.49" + wire $1\main_libresocsim_libresoc_xics_ics_we[0:0] + attribute \src "ls180.v:220.5-220.36" + wire $1\main_libresocsim_load_re[0:0] + attribute \src "ls180.v:219.12-219.49" + wire width 32 $1\main_libresocsim_load_storage[31:0] + attribute \src "ls180.v:210.5-210.40" + wire $1\main_libresocsim_ram_bus_ack[0:0] + attribute \src "ls180.v:222.5-222.38" + wire $1\main_libresocsim_reload_re[0:0] + attribute \src "ls180.v:221.12-221.51" + wire width 32 $1\main_libresocsim_reload_storage[31:0] + attribute \src "ls180.v:56.5-56.37" + wire $1\main_libresocsim_reset_re[0:0] + attribute \src "ls180.v:55.5-55.42" + wire $1\main_libresocsim_reset_storage[0:0] + attribute \src "ls180.v:58.5-58.39" + wire $1\main_libresocsim_scratch_re[0:0] + attribute \src "ls180.v:57.12-57.60" + wire width 32 $1\main_libresocsim_scratch_storage[31:0] + attribute \src "ls180.v:226.5-226.44" + wire $1\main_libresocsim_update_value_re[0:0] + attribute \src "ls180.v:225.5-225.49" + wire $1\main_libresocsim_update_value_storage[0:0] + attribute \src "ls180.v:245.12-245.42" + wire width 32 $1\main_libresocsim_value[31:0] + attribute \src "ls180.v:227.12-227.49" + wire width 32 $1\main_libresocsim_value_status[31:0] + attribute \src "ls180.v:217.11-217.37" + wire width 8 $1\main_libresocsim_we[7:0] + attribute \src "ls180.v:233.5-233.39" + wire $1\main_libresocsim_zero_clear[0:0] + attribute \src "ls180.v:234.5-234.45" + wire $1\main_libresocsim_zero_old_trigger[0:0] + attribute \src "ls180.v:231.5-231.41" + wire $1\main_libresocsim_zero_pending[0:0] + attribute \src "ls180.v:923.12-923.40" + wire width 30 $1\main_litedram_wb_adr[29:0] + attribute \src "ls180.v:927.5-927.32" + wire $1\main_litedram_wb_cyc[0:0] + attribute \src "ls180.v:924.12-924.42" + wire width 16 $1\main_litedram_wb_dat_w[15:0] + attribute \src "ls180.v:926.11-926.38" + wire width 2 $1\main_litedram_wb_sel[1:0] + attribute \src "ls180.v:928.5-928.32" + wire $1\main_litedram_wb_stb[0:0] + attribute \src "ls180.v:930.5-930.31" + wire $1\main_litedram_wb_we[0:0] + attribute \src "ls180.v:1176.12-1176.37" + wire width 32 $1\main_pwm0_counter[31:0] + attribute \src "ls180.v:1178.5-1178.31" + wire $1\main_pwm0_enable_re[0:0] + attribute \src "ls180.v:1177.5-1177.36" + wire $1\main_pwm0_enable_storage[0:0] + attribute \src "ls180.v:1182.5-1182.31" + wire $1\main_pwm0_period_re[0:0] + attribute \src "ls180.v:1181.12-1181.44" + wire width 32 $1\main_pwm0_period_storage[31:0] + attribute \src "ls180.v:1180.5-1180.30" + wire $1\main_pwm0_width_re[0:0] + attribute \src "ls180.v:1179.12-1179.43" + wire width 32 $1\main_pwm0_width_storage[31:0] + attribute \src "ls180.v:1186.12-1186.37" + wire width 32 $1\main_pwm1_counter[31:0] + attribute \src "ls180.v:1188.5-1188.31" + wire $1\main_pwm1_enable_re[0:0] + attribute \src "ls180.v:1187.5-1187.36" + wire $1\main_pwm1_enable_storage[0:0] + attribute \src "ls180.v:1192.5-1192.31" + wire $1\main_pwm1_period_re[0:0] + attribute \src "ls180.v:1191.12-1191.44" + wire width 32 $1\main_pwm1_period_storage[31:0] + attribute \src "ls180.v:1190.5-1190.30" + wire $1\main_pwm1_width_re[0:0] + attribute \src "ls180.v:1189.12-1189.43" + wire width 32 $1\main_pwm1_width_storage[31:0] + attribute \src "ls180.v:356.11-356.32" + wire width 3 $1\main_rddata_en[2:0] + attribute \src "ls180.v:1714.11-1714.50" + wire width 3 $1\main_sdblock2mem_converter_demux[2:0] + attribute \src "ls180.v:1710.5-1710.51" + wire $1\main_sdblock2mem_converter_source_first[0:0] + attribute \src "ls180.v:1711.5-1711.50" + wire $1\main_sdblock2mem_converter_source_last[0:0] + attribute \src "ls180.v:1712.12-1712.66" + wire width 64 $1\main_sdblock2mem_converter_source_payload_data[63:0] + attribute \src "ls180.v:1713.11-1713.77" + wire width 4 $1\main_sdblock2mem_converter_source_payload_valid_token_count[3:0] + attribute \src "ls180.v:1716.5-1716.49" + wire $1\main_sdblock2mem_converter_strobe_all[0:0] + attribute \src "ls180.v:1689.11-1689.47" + wire width 5 $1\main_sdblock2mem_fifo_consume[4:0] + attribute \src "ls180.v:1686.11-1686.45" + wire width 6 $1\main_sdblock2mem_fifo_level[5:0] + attribute \src "ls180.v:1688.11-1688.47" + wire width 5 $1\main_sdblock2mem_fifo_produce[4:0] + attribute \src "ls180.v:1690.11-1690.50" + wire width 5 $1\main_sdblock2mem_fifo_wrport_adr[4:0] + attribute \src "ls180.v:1724.12-1724.62" + wire width 32 $1\main_sdblock2mem_sink_sink_payload_address[31:0] + attribute \src "ls180.v:1725.12-1725.60" + wire width 64 $1\main_sdblock2mem_sink_sink_payload_data1[63:0] + attribute \src "ls180.v:1722.5-1722.45" + wire $1\main_sdblock2mem_sink_sink_valid1[0:0] + attribute \src "ls180.v:1732.5-1732.54" + wire $1\main_sdblock2mem_wishbonedmawriter_base_re[0:0] + attribute \src "ls180.v:1731.12-1731.67" + wire width 64 $1\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] + attribute \src "ls180.v:1736.5-1736.56" + wire $1\main_sdblock2mem_wishbonedmawriter_enable_re[0:0] + attribute \src "ls180.v:1735.5-1735.61" + wire $1\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] + attribute \src "ls180.v:1734.5-1734.56" + wire $1\main_sdblock2mem_wishbonedmawriter_length_re[0:0] + attribute \src "ls180.v:1733.12-1733.69" + wire width 32 $1\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] + attribute \src "ls180.v:1740.5-1740.54" + wire $1\main_sdblock2mem_wishbonedmawriter_loop_re[0:0] + attribute \src "ls180.v:1739.5-1739.59" + wire $1\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] + attribute \src "ls180.v:1742.12-1742.61" + wire width 32 $1\main_sdblock2mem_wishbonedmawriter_offset[31:0] + attribute \src "ls180.v:1962.12-1962.87" + wire width 32 $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] + attribute \src "ls180.v:1963.5-1963.82" + wire $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] + attribute \src "ls180.v:1727.5-1727.57" + wire $1\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] + attribute \src "ls180.v:1737.5-1737.53" + wire $1\main_sdblock2mem_wishbonedmawriter_status[0:0] + attribute \src "ls180.v:1506.5-1506.38" + wire $1\main_sdcore_block_count_re[0:0] + attribute \src "ls180.v:1505.12-1505.51" + wire width 32 $1\main_sdcore_block_count_storage[31:0] + attribute \src "ls180.v:1504.5-1504.39" + wire $1\main_sdcore_block_length_re[0:0] + attribute \src "ls180.v:1503.11-1503.51" + wire width 10 $1\main_sdcore_block_length_storage[9:0] + attribute \src "ls180.v:1490.5-1490.39" + wire $1\main_sdcore_cmd_argument_re[0:0] + attribute \src "ls180.v:1489.12-1489.52" + wire width 32 $1\main_sdcore_cmd_argument_storage[31:0] + attribute \src "ls180.v:1492.5-1492.38" + wire $1\main_sdcore_cmd_command_re[0:0] + attribute \src "ls180.v:1491.12-1491.51" + wire width 32 $1\main_sdcore_cmd_command_storage[31:0] + attribute \src "ls180.v:1645.11-1645.39" + wire width 3 $1\main_sdcore_cmd_count[2:0] + attribute \src "ls180.v:1946.11-1946.62" + wire width 3 $1\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] + attribute \src "ls180.v:1947.5-1947.59" + wire $1\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] + attribute \src "ls180.v:1646.5-1646.32" + wire $1\main_sdcore_cmd_done[0:0] + attribute \src "ls180.v:1942.5-1942.55" + wire $1\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] + attribute \src "ls180.v:1943.5-1943.58" + wire $1\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] + attribute \src "ls180.v:1647.5-1647.33" + wire $1\main_sdcore_cmd_error[0:0] + attribute \src "ls180.v:1950.5-1950.56" + wire $1\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] + attribute \src "ls180.v:1951.5-1951.59" + wire $1\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] + attribute \src "ls180.v:1497.13-1497.53" + wire width 128 $1\main_sdcore_cmd_response_status[127:0] + attribute \src "ls180.v:1958.13-1958.76" + wire width 128 $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] + attribute \src "ls180.v:1959.5-1959.69" + wire $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] + attribute \src "ls180.v:1648.5-1648.35" + wire $1\main_sdcore_cmd_timeout[0:0] + attribute \src "ls180.v:1952.5-1952.58" + wire $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] + attribute \src "ls180.v:1953.5-1953.61" + wire $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] + attribute \src "ls180.v:1606.11-1606.47" + wire width 4 $1\main_sdcore_crc16_checker_cnt[3:0] + attribute \src "ls180.v:1612.5-1612.46" + wire $1\main_sdcore_crc16_checker_crc0_clr[0:0] + attribute \src "ls180.v:1611.12-1611.54" + wire width 16 $1\main_sdcore_crc16_checker_crc0_crc[15:0] + attribute \src "ls180.v:1607.12-1607.58" + wire width 16 $1\main_sdcore_crc16_checker_crc0_crcreg0[15:0] + attribute \src "ls180.v:1619.5-1619.46" + wire $1\main_sdcore_crc16_checker_crc1_clr[0:0] + attribute \src "ls180.v:1618.12-1618.54" + wire width 16 $1\main_sdcore_crc16_checker_crc1_crc[15:0] + attribute \src "ls180.v:1614.12-1614.58" + wire width 16 $1\main_sdcore_crc16_checker_crc1_crcreg0[15:0] + attribute \src "ls180.v:1626.5-1626.46" + wire $1\main_sdcore_crc16_checker_crc2_clr[0:0] + attribute \src "ls180.v:1625.12-1625.54" + wire width 16 $1\main_sdcore_crc16_checker_crc2_crc[15:0] + attribute \src "ls180.v:1621.12-1621.58" + wire width 16 $1\main_sdcore_crc16_checker_crc2_crcreg0[15:0] + attribute \src "ls180.v:1633.5-1633.46" + wire $1\main_sdcore_crc16_checker_crc3_clr[0:0] + attribute \src "ls180.v:1632.12-1632.54" + wire width 16 $1\main_sdcore_crc16_checker_crc3_crc[15:0] + attribute \src "ls180.v:1628.12-1628.58" + wire width 16 $1\main_sdcore_crc16_checker_crc3_crcreg0[15:0] + attribute \src "ls180.v:1635.12-1635.53" + wire width 16 $1\main_sdcore_crc16_checker_crctmp0[15:0] + attribute \src "ls180.v:1636.12-1636.53" + wire width 16 $1\main_sdcore_crc16_checker_crctmp1[15:0] + attribute \src "ls180.v:1637.12-1637.53" + wire width 16 $1\main_sdcore_crc16_checker_crctmp2[15:0] + attribute \src "ls180.v:1638.12-1638.53" + wire width 16 $1\main_sdcore_crc16_checker_crctmp3[15:0] + attribute \src "ls180.v:1640.12-1640.51" + wire width 16 $1\main_sdcore_crc16_checker_fifo0[15:0] + attribute \src "ls180.v:1641.12-1641.51" + wire width 16 $1\main_sdcore_crc16_checker_fifo1[15:0] + attribute \src "ls180.v:1642.12-1642.51" + wire width 16 $1\main_sdcore_crc16_checker_fifo2[15:0] + attribute \src "ls180.v:1643.12-1643.51" + wire width 16 $1\main_sdcore_crc16_checker_fifo3[15:0] + attribute \src "ls180.v:1597.5-1597.48" + wire $1\main_sdcore_crc16_checker_sink_first[0:0] + attribute \src "ls180.v:1598.5-1598.47" + wire $1\main_sdcore_crc16_checker_sink_last[0:0] + attribute \src "ls180.v:1599.11-1599.61" + wire width 8 $1\main_sdcore_crc16_checker_sink_payload_data[7:0] + attribute \src "ls180.v:1596.5-1596.48" + wire $1\main_sdcore_crc16_checker_sink_ready[0:0] + attribute \src "ls180.v:1595.5-1595.48" + wire $1\main_sdcore_crc16_checker_sink_valid[0:0] + attribute \src "ls180.v:1600.5-1600.50" + wire $1\main_sdcore_crc16_checker_source_valid[0:0] + attribute \src "ls180.v:1605.11-1605.47" + wire width 8 $1\main_sdcore_crc16_checker_val[7:0] + attribute \src "ls180.v:1639.5-1639.43" + wire $1\main_sdcore_crc16_checker_valid[0:0] + attribute \src "ls180.v:1562.11-1562.48" + wire width 3 $1\main_sdcore_crc16_inserter_cnt[2:0] + attribute \src "ls180.v:1938.11-1938.87" + wire width 3 $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] + attribute \src "ls180.v:1939.5-1939.84" + wire $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] + attribute \src "ls180.v:1567.12-1567.55" + wire width 16 $1\main_sdcore_crc16_inserter_crc0_crc[15:0] + attribute \src "ls180.v:1563.12-1563.59" + wire width 16 $1\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] + attribute \src "ls180.v:1574.12-1574.55" + wire width 16 $1\main_sdcore_crc16_inserter_crc1_crc[15:0] + attribute \src "ls180.v:1570.12-1570.59" + wire width 16 $1\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] + attribute \src "ls180.v:1581.12-1581.55" + wire width 16 $1\main_sdcore_crc16_inserter_crc2_crc[15:0] + attribute \src "ls180.v:1577.12-1577.59" + wire width 16 $1\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] + attribute \src "ls180.v:1588.12-1588.55" + wire width 16 $1\main_sdcore_crc16_inserter_crc3_crc[15:0] + attribute \src "ls180.v:1584.12-1584.59" + wire width 16 $1\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] + attribute \src "ls180.v:1591.12-1591.54" + wire width 16 $1\main_sdcore_crc16_inserter_crctmp0[15:0] + attribute \src "ls180.v:1930.12-1930.93" + wire width 16 $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] + attribute \src "ls180.v:1931.5-1931.88" + wire $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] + attribute \src "ls180.v:1592.12-1592.54" + wire width 16 $1\main_sdcore_crc16_inserter_crctmp1[15:0] + attribute \src "ls180.v:1932.12-1932.93" + wire width 16 $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] + attribute \src "ls180.v:1933.5-1933.88" + wire $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] + attribute \src "ls180.v:1593.12-1593.54" + wire width 16 $1\main_sdcore_crc16_inserter_crctmp2[15:0] + attribute \src "ls180.v:1934.12-1934.93" + wire width 16 $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] + attribute \src "ls180.v:1935.5-1935.88" + wire $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] + attribute \src "ls180.v:1594.12-1594.54" + wire width 16 $1\main_sdcore_crc16_inserter_crctmp3[15:0] + attribute \src "ls180.v:1936.12-1936.93" + wire width 16 $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] + attribute \src "ls180.v:1937.5-1937.88" + wire $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] + attribute \src "ls180.v:1553.5-1553.49" + wire $1\main_sdcore_crc16_inserter_sink_ready[0:0] + attribute \src "ls180.v:1560.5-1560.50" + wire $1\main_sdcore_crc16_inserter_source_last[0:0] + attribute \src "ls180.v:1561.11-1561.64" + wire width 8 $1\main_sdcore_crc16_inserter_source_payload_data[7:0] + attribute \src "ls180.v:1558.5-1558.51" + wire $1\main_sdcore_crc16_inserter_source_ready[0:0] + attribute \src "ls180.v:1557.5-1557.51" + wire $1\main_sdcore_crc16_inserter_source_valid[0:0] + attribute \src "ls180.v:1549.11-1549.47" + wire width 7 $1\main_sdcore_crc7_inserter_crc[6:0] + attribute \src "ls180.v:1507.11-1507.51" + wire width 7 $1\main_sdcore_crc7_inserter_crcreg0[6:0] + attribute \src "ls180.v:1650.12-1650.42" + wire width 32 $1\main_sdcore_data_count[31:0] + attribute \src "ls180.v:1948.12-1948.65" + wire width 32 $1\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] + attribute \src "ls180.v:1949.5-1949.60" + wire $1\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] + attribute \src "ls180.v:1651.5-1651.33" + wire $1\main_sdcore_data_done[0:0] + attribute \src "ls180.v:1944.5-1944.56" + wire $1\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] + attribute \src "ls180.v:1945.5-1945.59" + wire $1\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] + attribute \src "ls180.v:1652.5-1652.34" + wire $1\main_sdcore_data_error[0:0] + attribute \src "ls180.v:1954.5-1954.57" + wire $1\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] + attribute \src "ls180.v:1955.5-1955.60" + wire $1\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] + attribute \src "ls180.v:1653.5-1653.36" + wire $1\main_sdcore_data_timeout[0:0] + attribute \src "ls180.v:1956.5-1956.59" + wire $1\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] + attribute \src "ls180.v:1957.5-1957.62" + wire $1\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] + attribute \src "ls180.v:1798.11-1798.48" + wire width 3 $1\main_sdmem2block_converter_mux[2:0] + attribute \src "ls180.v:1796.11-1796.64" + wire width 8 $1\main_sdmem2block_converter_source_payload_data[7:0] + attribute \src "ls180.v:1772.5-1772.40" + wire $1\main_sdmem2block_dma_base_re[0:0] + attribute \src "ls180.v:1771.12-1771.53" + wire width 64 $1\main_sdmem2block_dma_base_storage[63:0] + attribute \src "ls180.v:1770.12-1770.45" + wire width 64 $1\main_sdmem2block_dma_data[63:0] + attribute \src "ls180.v:1966.12-1966.75" + wire width 64 $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[63:0] + attribute \src "ls180.v:1967.5-1967.70" + wire $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] + attribute \src "ls180.v:1777.5-1777.44" + wire $1\main_sdmem2block_dma_done_status[0:0] + attribute \src "ls180.v:1776.5-1776.42" + wire $1\main_sdmem2block_dma_enable_re[0:0] + attribute \src "ls180.v:1775.5-1775.47" + wire $1\main_sdmem2block_dma_enable_storage[0:0] + attribute \src "ls180.v:1774.5-1774.42" + wire $1\main_sdmem2block_dma_length_re[0:0] + attribute \src "ls180.v:1773.12-1773.55" + wire width 32 $1\main_sdmem2block_dma_length_storage[31:0] + attribute \src "ls180.v:1780.5-1780.40" + wire $1\main_sdmem2block_dma_loop_re[0:0] + attribute \src "ls180.v:1779.5-1779.45" + wire $1\main_sdmem2block_dma_loop_storage[0:0] + attribute \src "ls180.v:1784.12-1784.47" + wire width 32 $1\main_sdmem2block_dma_offset[31:0] + attribute \src "ls180.v:1970.12-1970.87" + wire width 32 $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] + attribute \src "ls180.v:1971.5-1971.82" + wire $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] + attribute \src "ls180.v:1763.5-1763.42" + wire $1\main_sdmem2block_dma_sink_last[0:0] + attribute \src "ls180.v:1764.12-1764.61" + wire width 32 $1\main_sdmem2block_dma_sink_payload_address[31:0] + attribute \src "ls180.v:1762.5-1762.43" + wire $1\main_sdmem2block_dma_sink_ready[0:0] + attribute \src "ls180.v:1761.5-1761.43" + wire $1\main_sdmem2block_dma_sink_valid[0:0] + attribute \src "ls180.v:1768.5-1768.44" + wire $1\main_sdmem2block_dma_source_last[0:0] + attribute \src "ls180.v:1769.12-1769.60" + wire width 64 $1\main_sdmem2block_dma_source_payload_data[63:0] + attribute \src "ls180.v:1765.5-1765.45" + wire $1\main_sdmem2block_dma_source_valid[0:0] + attribute \src "ls180.v:1825.11-1825.47" + wire width 5 $1\main_sdmem2block_fifo_consume[4:0] + attribute \src "ls180.v:1822.11-1822.45" + wire width 6 $1\main_sdmem2block_fifo_level[5:0] + attribute \src "ls180.v:1824.11-1824.47" + wire width 5 $1\main_sdmem2block_fifo_produce[4:0] + attribute \src "ls180.v:1826.11-1826.50" + wire width 5 $1\main_sdmem2block_fifo_wrport_adr[4:0] + attribute \src "ls180.v:1206.5-1206.35" + wire $1\main_sdphy_clocker_clk0[0:0] + attribute \src "ls180.v:1209.5-1209.35" + wire $1\main_sdphy_clocker_clk1[0:0] + attribute \src "ls180.v:1210.5-1210.36" + wire $1\main_sdphy_clocker_clk_d[0:0] + attribute \src "ls180.v:1208.11-1208.41" + wire width 9 $1\main_sdphy_clocker_clks[8:0] + attribute \src "ls180.v:1204.5-1204.33" + wire $1\main_sdphy_clocker_re[0:0] + attribute \src "ls180.v:1203.11-1203.46" + wire width 9 $1\main_sdphy_clocker_storage[8:0] + attribute \src "ls180.v:1312.5-1312.49" + wire $1\main_sdphy_cmdr_cmdr_buf_source_first[0:0] + attribute \src "ls180.v:1313.5-1313.48" + wire $1\main_sdphy_cmdr_cmdr_buf_source_last[0:0] + attribute \src "ls180.v:1314.11-1314.62" + wire width 8 $1\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0] + attribute \src "ls180.v:1310.5-1310.49" + wire $1\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] + attribute \src "ls180.v:1297.11-1297.54" + wire width 3 $1\main_sdphy_cmdr_cmdr_converter_demux[2:0] + attribute \src "ls180.v:1293.5-1293.55" + wire $1\main_sdphy_cmdr_cmdr_converter_source_first[0:0] + attribute \src "ls180.v:1294.5-1294.54" + wire $1\main_sdphy_cmdr_cmdr_converter_source_last[0:0] + attribute \src "ls180.v:1295.11-1295.68" + wire width 8 $1\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] + attribute \src "ls180.v:1296.11-1296.81" + wire width 4 $1\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] + attribute \src "ls180.v:1299.5-1299.53" + wire $1\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] + attribute \src "ls180.v:1315.5-1315.38" + wire $1\main_sdphy_cmdr_cmdr_reset[0:0] + attribute \src "ls180.v:1910.5-1910.66" + wire $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] + attribute \src "ls180.v:1911.5-1911.69" + wire $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] + attribute \src "ls180.v:1285.5-1285.36" + wire $1\main_sdphy_cmdr_cmdr_run[0:0] + attribute \src "ls180.v:1280.5-1280.53" + wire $1\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] + attribute \src "ls180.v:1267.11-1267.39" + wire width 8 $1\main_sdphy_cmdr_count[7:0] + attribute \src "ls180.v:1906.11-1906.67" + wire width 8 $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] + attribute \src "ls180.v:1907.5-1907.64" + wire $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] + attribute \src "ls180.v:1252.5-1252.48" + wire $1\main_sdphy_cmdr_pads_out_payload_clk[0:0] + attribute \src "ls180.v:1253.5-1253.50" + wire $1\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] + attribute \src "ls180.v:1254.5-1254.51" + wire $1\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] + attribute \src "ls180.v:1259.5-1259.37" + wire $1\main_sdphy_cmdr_sink_last[0:0] + attribute \src "ls180.v:1260.11-1260.53" + wire width 8 $1\main_sdphy_cmdr_sink_payload_length[7:0] + attribute \src "ls180.v:1258.5-1258.38" + wire $1\main_sdphy_cmdr_sink_ready[0:0] + attribute \src "ls180.v:1257.5-1257.38" + wire $1\main_sdphy_cmdr_sink_valid[0:0] + attribute \src "ls180.v:1263.5-1263.39" + wire $1\main_sdphy_cmdr_source_last[0:0] + attribute \src "ls180.v:1264.11-1264.53" + wire width 8 $1\main_sdphy_cmdr_source_payload_data[7:0] + attribute \src "ls180.v:1265.11-1265.55" + wire width 3 $1\main_sdphy_cmdr_source_payload_status[2:0] + attribute \src "ls180.v:1262.5-1262.40" + wire $1\main_sdphy_cmdr_source_ready[0:0] + attribute \src "ls180.v:1261.5-1261.40" + wire $1\main_sdphy_cmdr_source_valid[0:0] + attribute \src "ls180.v:1266.12-1266.48" + wire width 32 $1\main_sdphy_cmdr_timeout[31:0] + attribute \src "ls180.v:1908.12-1908.71" + wire width 32 $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] + attribute \src "ls180.v:1909.5-1909.66" + wire $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] + attribute \src "ls180.v:1239.11-1239.39" + wire width 8 $1\main_sdphy_cmdw_count[7:0] + attribute \src "ls180.v:1902.11-1902.66" + wire width 8 $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] + attribute \src "ls180.v:1903.5-1903.63" + wire $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] + attribute \src "ls180.v:1238.5-1238.32" + wire $1\main_sdphy_cmdw_done[0:0] + attribute \src "ls180.v:1229.5-1229.48" + wire $1\main_sdphy_cmdw_pads_out_payload_clk[0:0] + attribute \src "ls180.v:1230.5-1230.50" + wire $1\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] + attribute \src "ls180.v:1231.5-1231.51" + wire $1\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] + attribute \src "ls180.v:1236.5-1236.37" + wire $1\main_sdphy_cmdw_sink_last[0:0] + attribute \src "ls180.v:1237.11-1237.51" + wire width 8 $1\main_sdphy_cmdw_sink_payload_data[7:0] + attribute \src "ls180.v:1235.5-1235.38" + wire $1\main_sdphy_cmdw_sink_ready[0:0] + attribute \src "ls180.v:1234.5-1234.38" + wire $1\main_sdphy_cmdw_sink_valid[0:0] + attribute \src "ls180.v:1423.11-1423.41" + wire width 10 $1\main_sdphy_datar_count[9:0] + attribute \src "ls180.v:1922.11-1922.70" + wire width 10 $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] + attribute \src "ls180.v:1923.5-1923.66" + wire $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] + attribute \src "ls180.v:1468.5-1468.51" + wire $1\main_sdphy_datar_datar_buf_source_first[0:0] + attribute \src "ls180.v:1469.5-1469.50" + wire $1\main_sdphy_datar_datar_buf_source_last[0:0] + attribute \src "ls180.v:1470.11-1470.64" + wire width 8 $1\main_sdphy_datar_datar_buf_source_payload_data[7:0] + attribute \src "ls180.v:1466.5-1466.51" + wire $1\main_sdphy_datar_datar_buf_source_valid[0:0] + attribute \src "ls180.v:1453.5-1453.50" + wire $1\main_sdphy_datar_datar_converter_demux[0:0] + attribute \src "ls180.v:1449.5-1449.57" + wire $1\main_sdphy_datar_datar_converter_source_first[0:0] + attribute \src "ls180.v:1450.5-1450.56" + wire $1\main_sdphy_datar_datar_converter_source_last[0:0] + attribute \src "ls180.v:1451.11-1451.70" + wire width 8 $1\main_sdphy_datar_datar_converter_source_payload_data[7:0] + attribute \src "ls180.v:1452.11-1452.83" + wire width 2 $1\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] + attribute \src "ls180.v:1455.5-1455.55" + wire $1\main_sdphy_datar_datar_converter_strobe_all[0:0] + attribute \src "ls180.v:1471.5-1471.40" + wire $1\main_sdphy_datar_datar_reset[0:0] + attribute \src "ls180.v:1926.5-1926.69" + wire $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] + attribute \src "ls180.v:1927.5-1927.72" + wire $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] + attribute \src "ls180.v:1441.5-1441.38" + wire $1\main_sdphy_datar_datar_run[0:0] + attribute \src "ls180.v:1436.5-1436.55" + wire $1\main_sdphy_datar_datar_source_source_ready0[0:0] + attribute \src "ls180.v:1406.5-1406.49" + wire $1\main_sdphy_datar_pads_out_payload_clk[0:0] + attribute \src "ls180.v:1413.5-1413.38" + wire $1\main_sdphy_datar_sink_last[0:0] + attribute \src "ls180.v:1414.11-1414.61" + wire width 10 $1\main_sdphy_datar_sink_payload_block_length[9:0] + attribute \src "ls180.v:1412.5-1412.39" + wire $1\main_sdphy_datar_sink_ready[0:0] + attribute \src "ls180.v:1411.5-1411.39" + wire $1\main_sdphy_datar_sink_valid[0:0] + attribute \src "ls180.v:1418.5-1418.40" + wire $1\main_sdphy_datar_source_last[0:0] + attribute \src "ls180.v:1419.11-1419.54" + wire width 8 $1\main_sdphy_datar_source_payload_data[7:0] + attribute \src "ls180.v:1420.11-1420.56" + wire width 3 $1\main_sdphy_datar_source_payload_status[2:0] + attribute \src "ls180.v:1416.5-1416.41" + wire $1\main_sdphy_datar_source_ready[0:0] + attribute \src "ls180.v:1415.5-1415.41" + wire $1\main_sdphy_datar_source_valid[0:0] + attribute \src "ls180.v:1421.5-1421.33" + wire $1\main_sdphy_datar_stop[0:0] + attribute \src "ls180.v:1422.12-1422.49" + wire width 32 $1\main_sdphy_datar_timeout[31:0] + attribute \src "ls180.v:1924.12-1924.73" + wire width 32 $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] + attribute \src "ls180.v:1925.5-1925.68" + wire $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] + attribute \src "ls180.v:1331.11-1331.40" + wire width 8 $1\main_sdphy_dataw_count[7:0] + attribute \src "ls180.v:1918.11-1918.61" + wire width 8 $1\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] + attribute \src "ls180.v:1919.5-1919.58" + wire $1\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] + attribute \src "ls180.v:1390.5-1390.50" + wire $1\main_sdphy_dataw_crcr_buf_source_first[0:0] + attribute \src "ls180.v:1391.5-1391.49" + wire $1\main_sdphy_dataw_crcr_buf_source_last[0:0] + attribute \src "ls180.v:1392.11-1392.63" + wire width 8 $1\main_sdphy_dataw_crcr_buf_source_payload_data[7:0] + attribute \src "ls180.v:1388.5-1388.50" + wire $1\main_sdphy_dataw_crcr_buf_source_valid[0:0] + attribute \src "ls180.v:1375.11-1375.55" + wire width 3 $1\main_sdphy_dataw_crcr_converter_demux[2:0] + attribute \src "ls180.v:1371.5-1371.56" + wire $1\main_sdphy_dataw_crcr_converter_source_first[0:0] + attribute \src "ls180.v:1372.5-1372.55" + wire $1\main_sdphy_dataw_crcr_converter_source_last[0:0] + attribute \src "ls180.v:1373.11-1373.69" + wire width 8 $1\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] + attribute \src "ls180.v:1374.11-1374.82" + wire width 4 $1\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] + attribute \src "ls180.v:1377.5-1377.54" + wire $1\main_sdphy_dataw_crcr_converter_strobe_all[0:0] + attribute \src "ls180.v:1393.5-1393.39" + wire $1\main_sdphy_dataw_crcr_reset[0:0] + attribute \src "ls180.v:1914.5-1914.66" + wire $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] + attribute \src "ls180.v:1915.5-1915.69" + wire $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] + attribute \src "ls180.v:1363.5-1363.37" + wire $1\main_sdphy_dataw_crcr_run[0:0] + attribute \src "ls180.v:1358.5-1358.54" + wire $1\main_sdphy_dataw_crcr_source_source_ready0[0:0] + attribute \src "ls180.v:1345.5-1345.34" + wire $1\main_sdphy_dataw_error[0:0] + attribute \src "ls180.v:1320.5-1320.49" + wire $1\main_sdphy_dataw_pads_out_payload_clk[0:0] + attribute \src "ls180.v:1323.11-1323.58" + wire width 4 $1\main_sdphy_dataw_pads_out_payload_data_o[3:0] + attribute \src "ls180.v:1324.5-1324.53" + wire $1\main_sdphy_dataw_pads_out_payload_data_oe[0:0] + attribute \src "ls180.v:1327.5-1327.39" + wire $1\main_sdphy_dataw_sink_first[0:0] + attribute \src "ls180.v:1328.5-1328.38" + wire $1\main_sdphy_dataw_sink_last[0:0] + attribute \src "ls180.v:1329.11-1329.52" + wire width 8 $1\main_sdphy_dataw_sink_payload_data[7:0] + attribute \src "ls180.v:1326.5-1326.39" + wire $1\main_sdphy_dataw_sink_ready[0:0] + attribute \src "ls180.v:1325.5-1325.39" + wire $1\main_sdphy_dataw_sink_valid[0:0] + attribute \src "ls180.v:1343.5-1343.34" + wire $1\main_sdphy_dataw_start[0:0] + attribute \src "ls180.v:1330.5-1330.33" + wire $1\main_sdphy_dataw_stop[0:0] + attribute \src "ls180.v:1344.5-1344.34" + wire $1\main_sdphy_dataw_valid[0:0] + attribute \src "ls180.v:1224.11-1224.39" + wire width 8 $1\main_sdphy_init_count[7:0] + attribute \src "ls180.v:1898.11-1898.66" + wire width 8 $1\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] + attribute \src "ls180.v:1899.5-1899.63" + wire $1\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] + attribute \src "ls180.v:1219.5-1219.48" + wire $1\main_sdphy_init_pads_out_payload_clk[0:0] + attribute \src "ls180.v:1220.5-1220.50" + wire $1\main_sdphy_init_pads_out_payload_cmd_o[0:0] + attribute \src "ls180.v:1221.5-1221.51" + wire $1\main_sdphy_init_pads_out_payload_cmd_oe[0:0] + attribute \src "ls180.v:1222.11-1222.57" + wire width 4 $1\main_sdphy_init_pads_out_payload_data_o[3:0] + attribute \src "ls180.v:1223.5-1223.52" + wire $1\main_sdphy_init_pads_out_payload_data_oe[0:0] + attribute \src "ls180.v:1473.5-1473.35" + wire $1\main_sdphy_sdpads_cmd_i[0:0] + attribute \src "ls180.v:1476.11-1476.42" + wire width 4 $1\main_sdphy_sdpads_data_i[3:0] + attribute \src "ls180.v:418.5-418.33" + wire $1\main_sdram_address_re[0:0] + attribute \src "ls180.v:417.12-417.46" + wire width 13 $1\main_sdram_address_storage[12:0] + attribute \src "ls180.v:420.5-420.34" + wire $1\main_sdram_baddress_re[0:0] + attribute \src "ls180.v:419.11-419.45" + wire width 2 $1\main_sdram_baddress_storage[1:0] + attribute \src "ls180.v:516.5-516.50" + wire $1\main_sdram_bankmachine0_auto_precharge[0:0] + attribute \src "ls180.v:538.11-538.70" + wire width 3 $1\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] + attribute \src "ls180.v:535.11-535.68" + wire width 4 $1\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] + attribute \src "ls180.v:537.11-537.70" + wire width 3 $1\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] + attribute \src "ls180.v:539.11-539.73" + wire width 3 $1\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] + attribute \src "ls180.v:562.5-562.59" + wire $1\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] + attribute \src "ls180.v:563.5-563.58" + wire $1\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] + attribute \src "ls180.v:565.12-565.74" + wire width 22 $1\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] + attribute \src "ls180.v:564.5-564.64" + wire $1\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] + attribute \src "ls180.v:560.5-560.59" + wire $1\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] + attribute \src "ls180.v:508.12-508.57" + wire width 13 $1\main_sdram_bankmachine0_cmd_payload_a[12:0] + attribute \src "ls180.v:510.5-510.51" + wire $1\main_sdram_bankmachine0_cmd_payload_cas[0:0] + attribute \src "ls180.v:513.5-513.54" + wire $1\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] + attribute \src "ls180.v:514.5-514.55" + wire $1\main_sdram_bankmachine0_cmd_payload_is_read[0:0] + attribute \src "ls180.v:515.5-515.56" + wire $1\main_sdram_bankmachine0_cmd_payload_is_write[0:0] + attribute \src "ls180.v:511.5-511.51" + wire $1\main_sdram_bankmachine0_cmd_payload_ras[0:0] + attribute \src "ls180.v:512.5-512.50" + wire $1\main_sdram_bankmachine0_cmd_payload_we[0:0] + attribute \src "ls180.v:507.5-507.45" + wire $1\main_sdram_bankmachine0_cmd_ready[0:0] + attribute \src "ls180.v:506.5-506.45" + wire $1\main_sdram_bankmachine0_cmd_valid[0:0] + attribute \src "ls180.v:505.5-505.47" + wire $1\main_sdram_bankmachine0_refresh_gnt[0:0] + attribute \src "ls180.v:503.5-503.51" + wire $1\main_sdram_bankmachine0_req_rdata_valid[0:0] + attribute \src "ls180.v:502.5-502.51" + wire $1\main_sdram_bankmachine0_req_wdata_ready[0:0] + attribute \src "ls180.v:566.12-566.47" + wire width 13 $1\main_sdram_bankmachine0_row[12:0] + attribute \src "ls180.v:570.5-570.45" + wire $1\main_sdram_bankmachine0_row_close[0:0] + attribute \src "ls180.v:571.5-571.54" + wire $1\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] + attribute \src "ls180.v:569.5-569.44" + wire $1\main_sdram_bankmachine0_row_open[0:0] + attribute \src "ls180.v:567.5-567.46" + wire $1\main_sdram_bankmachine0_row_opened[0:0] + attribute \src "ls180.v:574.11-574.55" + wire width 3 $1\main_sdram_bankmachine0_twtpcon_count[2:0] + attribute \src "ls180.v:573.32-573.76" + wire $1\main_sdram_bankmachine0_twtpcon_ready[0:0] + attribute \src "ls180.v:598.5-598.50" + wire $1\main_sdram_bankmachine1_auto_precharge[0:0] + attribute \src "ls180.v:620.11-620.70" + wire width 3 $1\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] + attribute \src "ls180.v:617.11-617.68" + wire width 4 $1\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] + attribute \src "ls180.v:619.11-619.70" + wire width 3 $1\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] + attribute \src "ls180.v:621.11-621.73" + wire width 3 $1\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] + attribute \src "ls180.v:644.5-644.59" + wire $1\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] + attribute \src "ls180.v:645.5-645.58" + wire $1\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] + attribute \src "ls180.v:647.12-647.74" + wire width 22 $1\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] + attribute \src "ls180.v:646.5-646.64" + wire $1\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] + attribute \src "ls180.v:642.5-642.59" + wire $1\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] + attribute \src "ls180.v:590.12-590.57" + wire width 13 $1\main_sdram_bankmachine1_cmd_payload_a[12:0] + attribute \src "ls180.v:592.5-592.51" + wire $1\main_sdram_bankmachine1_cmd_payload_cas[0:0] + attribute \src "ls180.v:595.5-595.54" + wire $1\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] + attribute \src "ls180.v:596.5-596.55" + wire $1\main_sdram_bankmachine1_cmd_payload_is_read[0:0] + attribute \src "ls180.v:597.5-597.56" + wire $1\main_sdram_bankmachine1_cmd_payload_is_write[0:0] + attribute \src "ls180.v:593.5-593.51" + wire $1\main_sdram_bankmachine1_cmd_payload_ras[0:0] + attribute \src "ls180.v:594.5-594.50" + wire $1\main_sdram_bankmachine1_cmd_payload_we[0:0] + attribute \src "ls180.v:589.5-589.45" + wire $1\main_sdram_bankmachine1_cmd_ready[0:0] + attribute \src "ls180.v:588.5-588.45" + wire $1\main_sdram_bankmachine1_cmd_valid[0:0] + attribute \src "ls180.v:587.5-587.47" + wire $1\main_sdram_bankmachine1_refresh_gnt[0:0] + attribute \src "ls180.v:585.5-585.51" + wire $1\main_sdram_bankmachine1_req_rdata_valid[0:0] + attribute \src "ls180.v:584.5-584.51" + wire $1\main_sdram_bankmachine1_req_wdata_ready[0:0] + attribute \src "ls180.v:648.12-648.47" + wire width 13 $1\main_sdram_bankmachine1_row[12:0] + attribute \src "ls180.v:652.5-652.45" + wire $1\main_sdram_bankmachine1_row_close[0:0] + attribute \src "ls180.v:653.5-653.54" + wire $1\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] + attribute \src "ls180.v:651.5-651.44" + wire $1\main_sdram_bankmachine1_row_open[0:0] + attribute \src "ls180.v:649.5-649.46" + wire $1\main_sdram_bankmachine1_row_opened[0:0] + attribute \src "ls180.v:656.11-656.55" + wire width 3 $1\main_sdram_bankmachine1_twtpcon_count[2:0] + attribute \src "ls180.v:655.32-655.76" + wire $1\main_sdram_bankmachine1_twtpcon_ready[0:0] + attribute \src "ls180.v:680.5-680.50" + wire $1\main_sdram_bankmachine2_auto_precharge[0:0] + attribute \src "ls180.v:702.11-702.70" + wire width 3 $1\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] + attribute \src "ls180.v:699.11-699.68" + wire width 4 $1\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] + attribute \src "ls180.v:701.11-701.70" + wire width 3 $1\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] + attribute \src "ls180.v:703.11-703.73" + wire width 3 $1\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] + attribute \src "ls180.v:726.5-726.59" + wire $1\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] + attribute \src "ls180.v:727.5-727.58" + wire $1\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] + attribute \src "ls180.v:729.12-729.74" + wire width 22 $1\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] + attribute \src "ls180.v:728.5-728.64" + wire $1\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] + attribute \src "ls180.v:724.5-724.59" + wire $1\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] + attribute \src "ls180.v:672.12-672.57" + wire width 13 $1\main_sdram_bankmachine2_cmd_payload_a[12:0] + attribute \src "ls180.v:674.5-674.51" + wire $1\main_sdram_bankmachine2_cmd_payload_cas[0:0] + attribute \src "ls180.v:677.5-677.54" + wire $1\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] + attribute \src "ls180.v:678.5-678.55" + wire $1\main_sdram_bankmachine2_cmd_payload_is_read[0:0] + attribute \src "ls180.v:679.5-679.56" + wire $1\main_sdram_bankmachine2_cmd_payload_is_write[0:0] + attribute \src "ls180.v:675.5-675.51" + wire $1\main_sdram_bankmachine2_cmd_payload_ras[0:0] + attribute \src "ls180.v:676.5-676.50" + wire $1\main_sdram_bankmachine2_cmd_payload_we[0:0] + attribute \src "ls180.v:671.5-671.45" + wire $1\main_sdram_bankmachine2_cmd_ready[0:0] + attribute \src "ls180.v:670.5-670.45" + wire $1\main_sdram_bankmachine2_cmd_valid[0:0] + attribute \src "ls180.v:669.5-669.47" + wire $1\main_sdram_bankmachine2_refresh_gnt[0:0] + attribute \src "ls180.v:667.5-667.51" + wire $1\main_sdram_bankmachine2_req_rdata_valid[0:0] + attribute \src "ls180.v:666.5-666.51" + wire $1\main_sdram_bankmachine2_req_wdata_ready[0:0] + attribute \src "ls180.v:730.12-730.47" + wire width 13 $1\main_sdram_bankmachine2_row[12:0] + attribute \src "ls180.v:734.5-734.45" + wire $1\main_sdram_bankmachine2_row_close[0:0] + attribute \src "ls180.v:735.5-735.54" + wire $1\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] + attribute \src "ls180.v:733.5-733.44" + wire $1\main_sdram_bankmachine2_row_open[0:0] + attribute \src "ls180.v:731.5-731.46" + wire $1\main_sdram_bankmachine2_row_opened[0:0] + attribute \src "ls180.v:738.11-738.55" + wire width 3 $1\main_sdram_bankmachine2_twtpcon_count[2:0] + attribute \src "ls180.v:737.32-737.76" + wire $1\main_sdram_bankmachine2_twtpcon_ready[0:0] + attribute \src "ls180.v:762.5-762.50" + wire $1\main_sdram_bankmachine3_auto_precharge[0:0] + attribute \src "ls180.v:784.11-784.70" + wire width 3 $1\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] + attribute \src "ls180.v:781.11-781.68" + wire width 4 $1\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] + attribute \src "ls180.v:783.11-783.70" + wire width 3 $1\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] + attribute \src "ls180.v:785.11-785.73" + wire width 3 $1\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] + attribute \src "ls180.v:808.5-808.59" + wire $1\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] + attribute \src "ls180.v:809.5-809.58" + wire $1\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] + attribute \src "ls180.v:811.12-811.74" + wire width 22 $1\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] + attribute \src "ls180.v:810.5-810.64" + wire $1\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] + attribute \src "ls180.v:806.5-806.59" + wire $1\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] + attribute \src "ls180.v:754.12-754.57" + wire width 13 $1\main_sdram_bankmachine3_cmd_payload_a[12:0] + attribute \src "ls180.v:756.5-756.51" + wire $1\main_sdram_bankmachine3_cmd_payload_cas[0:0] + attribute \src "ls180.v:759.5-759.54" + wire $1\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] + attribute \src "ls180.v:760.5-760.55" + wire $1\main_sdram_bankmachine3_cmd_payload_is_read[0:0] + attribute \src "ls180.v:761.5-761.56" + wire $1\main_sdram_bankmachine3_cmd_payload_is_write[0:0] + attribute \src "ls180.v:757.5-757.51" + wire $1\main_sdram_bankmachine3_cmd_payload_ras[0:0] + attribute \src "ls180.v:758.5-758.50" + wire $1\main_sdram_bankmachine3_cmd_payload_we[0:0] + attribute \src "ls180.v:753.5-753.45" + wire $1\main_sdram_bankmachine3_cmd_ready[0:0] + attribute \src "ls180.v:752.5-752.45" + wire $1\main_sdram_bankmachine3_cmd_valid[0:0] + attribute \src "ls180.v:751.5-751.47" + wire $1\main_sdram_bankmachine3_refresh_gnt[0:0] + attribute \src "ls180.v:749.5-749.51" + wire $1\main_sdram_bankmachine3_req_rdata_valid[0:0] + attribute \src "ls180.v:748.5-748.51" + wire $1\main_sdram_bankmachine3_req_wdata_ready[0:0] + attribute \src "ls180.v:812.12-812.47" + wire width 13 $1\main_sdram_bankmachine3_row[12:0] + attribute \src "ls180.v:816.5-816.45" + wire $1\main_sdram_bankmachine3_row_close[0:0] + attribute \src "ls180.v:817.5-817.54" + wire $1\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] + attribute \src "ls180.v:815.5-815.44" + wire $1\main_sdram_bankmachine3_row_open[0:0] + attribute \src "ls180.v:813.5-813.46" + wire $1\main_sdram_bankmachine3_row_opened[0:0] + attribute \src "ls180.v:820.11-820.55" + wire width 3 $1\main_sdram_bankmachine3_twtpcon_count[2:0] + attribute \src "ls180.v:819.32-819.76" + wire $1\main_sdram_bankmachine3_twtpcon_ready[0:0] + attribute \src "ls180.v:835.5-835.49" + wire $1\main_sdram_choose_cmd_cmd_payload_cas[0:0] + attribute \src "ls180.v:836.5-836.49" + wire $1\main_sdram_choose_cmd_cmd_payload_ras[0:0] + attribute \src "ls180.v:837.5-837.48" + wire $1\main_sdram_choose_cmd_cmd_payload_we[0:0] + attribute \src "ls180.v:843.11-843.45" + wire width 2 $1\main_sdram_choose_cmd_grant[1:0] + attribute \src "ls180.v:841.11-841.46" + wire width 4 $1\main_sdram_choose_cmd_valids[3:0] + attribute \src "ls180.v:853.5-853.49" + wire $1\main_sdram_choose_req_cmd_payload_cas[0:0] + attribute \src "ls180.v:854.5-854.49" + wire $1\main_sdram_choose_req_cmd_payload_ras[0:0] + attribute \src "ls180.v:855.5-855.48" + wire $1\main_sdram_choose_req_cmd_payload_we[0:0] + attribute \src "ls180.v:850.5-850.43" + wire $1\main_sdram_choose_req_cmd_ready[0:0] + attribute \src "ls180.v:861.11-861.45" + wire width 2 $1\main_sdram_choose_req_grant[1:0] + attribute \src "ls180.v:859.11-859.46" + wire width 4 $1\main_sdram_choose_req_valids[3:0] + attribute \src "ls180.v:848.5-848.48" + wire $1\main_sdram_choose_req_want_activates[0:0] + attribute \src "ls180.v:845.5-845.44" + wire $1\main_sdram_choose_req_want_reads[0:0] + attribute \src "ls180.v:846.5-846.45" + wire $1\main_sdram_choose_req_want_writes[0:0] + attribute \src "ls180.v:474.5-474.31" + wire $1\main_sdram_cmd_last[0:0] + attribute \src "ls180.v:475.12-475.44" + wire width 13 $1\main_sdram_cmd_payload_a[12:0] + attribute \src "ls180.v:476.11-476.43" + wire width 2 $1\main_sdram_cmd_payload_ba[1:0] + attribute \src "ls180.v:477.5-477.38" + wire $1\main_sdram_cmd_payload_cas[0:0] + attribute \src "ls180.v:478.5-478.38" + wire $1\main_sdram_cmd_payload_ras[0:0] + attribute \src "ls180.v:479.5-479.37" + wire $1\main_sdram_cmd_payload_we[0:0] + attribute \src "ls180.v:473.5-473.32" + wire $1\main_sdram_cmd_ready[0:0] + attribute \src "ls180.v:472.5-472.32" + wire $1\main_sdram_cmd_valid[0:0] + attribute \src "ls180.v:412.5-412.33" + wire $1\main_sdram_command_re[0:0] + attribute \src "ls180.v:411.11-411.44" + wire width 6 $1\main_sdram_command_storage[5:0] + attribute \src "ls180.v:456.12-456.45" + wire width 13 $1\main_sdram_dfi_p0_address[12:0] + attribute \src "ls180.v:457.11-457.40" + wire width 2 $1\main_sdram_dfi_p0_bank[1:0] + attribute \src "ls180.v:458.5-458.35" + wire $1\main_sdram_dfi_p0_cas_n[0:0] + attribute \src "ls180.v:459.5-459.34" + wire $1\main_sdram_dfi_p0_cs_n[0:0] + attribute \src "ls180.v:460.5-460.35" + wire $1\main_sdram_dfi_p0_ras_n[0:0] + attribute \src "ls180.v:469.5-469.39" + wire $1\main_sdram_dfi_p0_rddata_en[0:0] + attribute \src "ls180.v:461.5-461.34" + wire $1\main_sdram_dfi_p0_we_n[0:0] + attribute \src "ls180.v:467.5-467.39" + wire $1\main_sdram_dfi_p0_wrdata_en[0:0] + attribute \src "ls180.v:880.5-880.26" + wire $1\main_sdram_en0[0:0] + attribute \src "ls180.v:883.5-883.26" + wire $1\main_sdram_en1[0:0] + attribute \src "ls180.v:453.12-453.46" + wire width 16 $1\main_sdram_interface_wdata[15:0] + attribute \src "ls180.v:454.11-454.47" + wire width 2 $1\main_sdram_interface_wdata_we[1:0] + attribute \src "ls180.v:359.5-359.36" + wire $1\main_sdram_inti_p0_cas_n[0:0] + attribute \src "ls180.v:360.5-360.35" + wire $1\main_sdram_inti_p0_cs_n[0:0] + attribute \src "ls180.v:361.5-361.36" + wire $1\main_sdram_inti_p0_ras_n[0:0] + attribute \src "ls180.v:371.12-371.45" + wire width 16 $1\main_sdram_inti_p0_rddata[15:0] + attribute \src "ls180.v:372.5-372.43" + wire $1\main_sdram_inti_p0_rddata_valid[0:0] + attribute \src "ls180.v:362.5-362.35" + wire $1\main_sdram_inti_p0_we_n[0:0] + attribute \src "ls180.v:398.5-398.38" + wire $1\main_sdram_master_p0_act_n[0:0] + attribute \src "ls180.v:389.12-389.48" + wire width 13 $1\main_sdram_master_p0_address[12:0] + attribute \src "ls180.v:390.11-390.43" + wire width 2 $1\main_sdram_master_p0_bank[1:0] + attribute \src "ls180.v:391.5-391.38" + wire $1\main_sdram_master_p0_cas_n[0:0] + attribute \src "ls180.v:395.5-395.36" + wire $1\main_sdram_master_p0_cke[0:0] + attribute \src "ls180.v:392.5-392.37" + wire $1\main_sdram_master_p0_cs_n[0:0] + attribute \src "ls180.v:396.5-396.36" + wire $1\main_sdram_master_p0_odt[0:0] + attribute \src "ls180.v:393.5-393.38" + wire $1\main_sdram_master_p0_ras_n[0:0] + attribute \src "ls180.v:402.5-402.42" + wire $1\main_sdram_master_p0_rddata_en[0:0] + attribute \src "ls180.v:397.5-397.40" + wire $1\main_sdram_master_p0_reset_n[0:0] + attribute \src "ls180.v:394.5-394.37" + wire $1\main_sdram_master_p0_we_n[0:0] + attribute \src "ls180.v:399.12-399.47" + wire width 16 $1\main_sdram_master_p0_wrdata[15:0] + attribute \src "ls180.v:400.5-400.42" + wire $1\main_sdram_master_p0_wrdata_en[0:0] + attribute \src "ls180.v:401.11-401.50" + wire width 2 $1\main_sdram_master_p0_wrdata_mask[1:0] + attribute \src "ls180.v:490.5-490.38" + wire $1\main_sdram_postponer_count[0:0] + attribute \src "ls180.v:489.5-489.38" + wire $1\main_sdram_postponer_req_o[0:0] + attribute \src "ls180.v:410.5-410.25" + wire $1\main_sdram_re[0:0] + attribute \src "ls180.v:496.5-496.38" + wire $1\main_sdram_sequencer_count[0:0] + attribute \src "ls180.v:495.11-495.46" + wire width 4 $1\main_sdram_sequencer_counter[3:0] + attribute \src "ls180.v:494.5-494.38" + wire $1\main_sdram_sequencer_done1[0:0] + attribute \src "ls180.v:491.5-491.39" + wire $1\main_sdram_sequencer_start0[0:0] + attribute \src "ls180.v:387.12-387.46" + wire width 16 $1\main_sdram_slave_p0_rddata[15:0] + attribute \src "ls180.v:388.5-388.44" + wire $1\main_sdram_slave_p0_rddata_valid[0:0] + attribute \src "ls180.v:423.12-423.37" + wire width 16 $1\main_sdram_status[15:0] + attribute \src "ls180.v:865.11-865.40" + wire width 2 $1\main_sdram_steerer_sel[1:0] + attribute \src "ls180.v:409.11-409.36" + wire width 4 $1\main_sdram_storage[3:0] + attribute \src "ls180.v:874.5-874.36" + wire $1\main_sdram_tccdcon_count[0:0] + attribute \src "ls180.v:873.32-873.63" + wire $1\main_sdram_tccdcon_ready[0:0] + attribute \src "ls180.v:882.11-882.34" + wire width 5 $1\main_sdram_time0[4:0] + attribute \src "ls180.v:885.11-885.34" + wire width 4 $1\main_sdram_time1[3:0] + attribute \src "ls180.v:487.11-487.44" + wire width 10 $1\main_sdram_timer_count1[9:0] + attribute \src "ls180.v:877.11-877.42" + wire width 3 $1\main_sdram_twtrcon_count[2:0] + attribute \src "ls180.v:876.32-876.63" + wire $1\main_sdram_twtrcon_ready[0:0] + attribute \src "ls180.v:422.5-422.32" + wire $1\main_sdram_wrdata_re[0:0] + attribute \src "ls180.v:421.12-421.45" + wire width 16 $1\main_sdram_wrdata_storage[15:0] + attribute \src "ls180.v:914.5-914.54" + wire $1\main_socbushandler_converted_interface_ack[0:0] + attribute \src "ls180.v:920.5-920.38" + wire $1\main_socbushandler_counter[0:0] + attribute \src "ls180.v:1849.5-1849.60" + wire $1\main_socbushandler_counter_converter2_next_value[0:0] + attribute \src "ls180.v:1850.5-1850.63" + wire $1\main_socbushandler_counter_converter2_next_value_ce[0:0] + attribute \src "ls180.v:922.12-922.44" + wire width 64 $1\main_socbushandler_dat_r[63:0] + attribute \src "ls180.v:919.5-919.35" + wire $1\main_socbushandler_skip[0:0] + attribute \src "ls180.v:1108.12-1108.44" + wire width 16 $1\main_spimaster11_storage[15:0] + attribute \src "ls180.v:1109.5-1109.31" + wire $1\main_spimaster12_re[0:0] + attribute \src "ls180.v:1113.11-1113.42" + wire width 8 $1\main_spimaster16_storage[7:0] + attribute \src "ls180.v:1114.5-1114.31" + wire $1\main_spimaster17_re[0:0] + attribute \src "ls180.v:1170.5-1170.30" + wire $1\main_spimaster1_re[0:0] + attribute \src "ls180.v:1169.12-1169.45" + wire width 16 $1\main_spimaster1_storage[15:0] + attribute \src "ls180.v:1118.5-1118.36" + wire $1\main_spimaster21_storage[0:0] + attribute \src "ls180.v:1119.5-1119.31" + wire $1\main_spimaster22_re[0:0] + attribute \src "ls180.v:1120.5-1120.36" + wire $1\main_spimaster23_storage[0:0] + attribute \src "ls180.v:1121.5-1121.31" + wire $1\main_spimaster24_re[0:0] + attribute \src "ls180.v:1122.5-1122.39" + wire $1\main_spimaster25_clk_enable[0:0] + attribute \src "ls180.v:1123.5-1123.38" + wire $1\main_spimaster26_cs_enable[0:0] + attribute \src "ls180.v:1124.11-1124.40" + wire width 3 $1\main_spimaster27_count[2:0] + attribute \src "ls180.v:1890.11-1890.62" + wire width 3 $1\main_spimaster27_count_spimaster0_next_value[2:0] + attribute \src "ls180.v:1891.5-1891.59" + wire $1\main_spimaster27_count_spimaster0_next_value_ce[0:0] + attribute \src "ls180.v:1125.5-1125.39" + wire $1\main_spimaster28_mosi_latch[0:0] + attribute \src "ls180.v:1126.5-1126.39" + wire $1\main_spimaster29_miso_latch[0:0] + attribute \src "ls180.v:1099.5-1099.32" + wire $1\main_spimaster2_done[0:0] + attribute \src "ls180.v:1127.12-1127.48" + wire width 16 $1\main_spimaster30_clk_divider[15:0] + attribute \src "ls180.v:1130.11-1130.44" + wire width 8 $1\main_spimaster33_mosi_data[7:0] + attribute \src "ls180.v:1131.11-1131.43" + wire width 3 $1\main_spimaster34_mosi_sel[2:0] + attribute \src "ls180.v:1132.11-1132.44" + wire width 8 $1\main_spimaster35_miso_data[7:0] + attribute \src "ls180.v:1100.5-1100.31" + wire $1\main_spimaster3_irq[0:0] + attribute \src "ls180.v:1102.11-1102.38" + wire width 8 $1\main_spimaster5_miso[7:0] + attribute \src "ls180.v:1106.5-1106.33" + wire $1\main_spimaster9_start[0:0] + attribute \src "ls180.v:1163.12-1163.47" + wire width 16 $1\main_spisdcard_clk_divider1[15:0] + attribute \src "ls180.v:1158.5-1158.37" + wire $1\main_spisdcard_clk_enable[0:0] + attribute \src "ls180.v:1145.5-1145.37" + wire $1\main_spisdcard_control_re[0:0] + attribute \src "ls180.v:1144.12-1144.50" + wire width 16 $1\main_spisdcard_control_storage[15:0] + attribute \src "ls180.v:1160.11-1160.38" + wire width 3 $1\main_spisdcard_count[2:0] + attribute \src "ls180.v:1894.11-1894.60" + wire width 3 $1\main_spisdcard_count_spimaster1_next_value[2:0] + attribute \src "ls180.v:1895.5-1895.57" + wire $1\main_spisdcard_count_spimaster1_next_value_ce[0:0] + attribute \src "ls180.v:1159.5-1159.36" + wire $1\main_spisdcard_cs_enable[0:0] + attribute \src "ls180.v:1155.5-1155.32" + wire $1\main_spisdcard_cs_re[0:0] + attribute \src "ls180.v:1154.5-1154.37" + wire $1\main_spisdcard_cs_storage[0:0] + attribute \src "ls180.v:1135.5-1135.32" + wire $1\main_spisdcard_done0[0:0] + attribute \src "ls180.v:1136.5-1136.30" + wire $1\main_spisdcard_irq[0:0] + attribute \src "ls180.v:1157.5-1157.38" + wire $1\main_spisdcard_loopback_re[0:0] + attribute \src "ls180.v:1156.5-1156.43" + wire $1\main_spisdcard_loopback_storage[0:0] + attribute \src "ls180.v:1138.11-1138.37" + wire width 8 $1\main_spisdcard_miso[7:0] + attribute \src "ls180.v:1168.11-1168.42" + wire width 8 $1\main_spisdcard_miso_data[7:0] + attribute \src "ls180.v:1162.5-1162.37" + wire $1\main_spisdcard_miso_latch[0:0] + attribute \src "ls180.v:1166.11-1166.42" + wire width 8 $1\main_spisdcard_mosi_data[7:0] + attribute \src "ls180.v:1161.5-1161.37" + wire $1\main_spisdcard_mosi_latch[0:0] + attribute \src "ls180.v:1150.5-1150.34" + wire $1\main_spisdcard_mosi_re[0:0] + attribute \src "ls180.v:1167.11-1167.41" + wire width 3 $1\main_spisdcard_mosi_sel[2:0] + attribute \src "ls180.v:1149.11-1149.45" + wire width 8 $1\main_spisdcard_mosi_storage[7:0] + attribute \src "ls180.v:1142.5-1142.33" + wire $1\main_spisdcard_start1[0:0] + attribute \src "ls180.v:259.11-259.31" + wire width 8 $1\main_sram0_we[7:0] + attribute \src "ls180.v:274.11-274.31" + wire width 8 $1\main_sram1_we[7:0] + attribute \src "ls180.v:289.11-289.31" + wire width 8 $1\main_sram2_we[7:0] + attribute \src "ls180.v:304.11-304.31" + wire width 8 $1\main_sram3_we[7:0] + attribute \src "ls180.v:990.11-990.50" + wire width 2 $1\main_uart_eventmanager_pending_w[1:0] + attribute \src "ls180.v:992.5-992.37" + wire $1\main_uart_eventmanager_re[0:0] + attribute \src "ls180.v:986.11-986.49" + wire width 2 $1\main_uart_eventmanager_status_w[1:0] + attribute \src "ls180.v:991.11-991.48" + wire width 2 $1\main_uart_eventmanager_storage[1:0] + attribute \src "ls180.v:958.12-958.54" + wire width 32 $1\main_uart_phy_phase_accumulator_rx[31:0] + attribute \src "ls180.v:948.12-948.54" + wire width 32 $1\main_uart_phy_phase_accumulator_tx[31:0] + attribute \src "ls180.v:941.5-941.28" + wire $1\main_uart_phy_re[0:0] + attribute \src "ls180.v:962.11-962.43" + wire width 4 $1\main_uart_phy_rx_bitcount[3:0] + attribute \src "ls180.v:963.5-963.33" + wire $1\main_uart_phy_rx_busy[0:0] + attribute \src "ls180.v:960.5-960.30" + wire $1\main_uart_phy_rx_r[0:0] + attribute \src "ls180.v:961.11-961.38" + wire width 8 $1\main_uart_phy_rx_reg[7:0] + attribute \src "ls180.v:943.5-943.36" + wire $1\main_uart_phy_sink_ready[0:0] + attribute \src "ls180.v:956.11-956.51" + wire width 8 $1\main_uart_phy_source_payload_data[7:0] + attribute \src "ls180.v:952.5-952.38" + wire $1\main_uart_phy_source_valid[0:0] + attribute \src "ls180.v:940.12-940.47" + wire width 32 $1\main_uart_phy_storage[31:0] + attribute \src "ls180.v:950.11-950.43" + wire width 4 $1\main_uart_phy_tx_bitcount[3:0] + attribute \src "ls180.v:951.5-951.33" + wire $1\main_uart_phy_tx_busy[0:0] + attribute \src "ls180.v:949.11-949.38" + wire width 8 $1\main_uart_phy_tx_reg[7:0] + attribute \src "ls180.v:957.5-957.39" + wire $1\main_uart_phy_uart_clk_rxen[0:0] + attribute \src "ls180.v:947.5-947.39" + wire $1\main_uart_phy_uart_clk_txen[0:0] + attribute \src "ls180.v:981.5-981.30" + wire $1\main_uart_rx_clear[0:0] + attribute \src "ls180.v:1065.11-1065.43" + wire width 4 $1\main_uart_rx_fifo_consume[3:0] + attribute \src "ls180.v:1062.11-1062.42" + wire width 5 $1\main_uart_rx_fifo_level0[4:0] + attribute \src "ls180.v:1064.11-1064.43" + wire width 4 $1\main_uart_rx_fifo_produce[3:0] + attribute \src "ls180.v:1055.5-1055.38" + wire $1\main_uart_rx_fifo_readable[0:0] + attribute \src "ls180.v:1066.11-1066.46" + wire width 4 $1\main_uart_rx_fifo_wrport_adr[3:0] + attribute \src "ls180.v:982.5-982.36" + wire $1\main_uart_rx_old_trigger[0:0] + attribute \src "ls180.v:979.5-979.32" + wire $1\main_uart_rx_pending[0:0] + attribute \src "ls180.v:976.5-976.30" + wire $1\main_uart_tx_clear[0:0] + attribute \src "ls180.v:1028.11-1028.43" + wire width 4 $1\main_uart_tx_fifo_consume[3:0] + attribute \src "ls180.v:1025.11-1025.42" + wire width 5 $1\main_uart_tx_fifo_level0[4:0] + attribute \src "ls180.v:1027.11-1027.43" + wire width 4 $1\main_uart_tx_fifo_produce[3:0] + attribute \src "ls180.v:1018.5-1018.38" + wire $1\main_uart_tx_fifo_readable[0:0] + attribute \src "ls180.v:1029.11-1029.46" + wire width 4 $1\main_uart_tx_fifo_wrport_adr[3:0] + attribute \src "ls180.v:977.5-977.36" + wire $1\main_uart_tx_old_trigger[0:0] + attribute \src "ls180.v:974.5-974.32" + wire $1\main_uart_tx_pending[0:0] + attribute \src "ls180.v:906.5-906.29" + wire $1\main_wb_sdram_ack[0:0] + attribute \src "ls180.v:900.12-900.37" + wire width 30 $1\main_wb_sdram_adr[29:0] + attribute \src "ls180.v:904.5-904.29" + wire $1\main_wb_sdram_cyc[0:0] + attribute \src "ls180.v:901.12-901.39" + wire width 32 $1\main_wb_sdram_dat_w[31:0] + attribute \src "ls180.v:903.11-903.35" + wire width 4 $1\main_wb_sdram_sel[3:0] + attribute \src "ls180.v:905.5-905.29" + wire $1\main_wb_sdram_stb[0:0] + attribute \src "ls180.v:907.5-907.28" + wire $1\main_wb_sdram_we[0:0] + attribute \src "ls180.v:936.5-936.31" + wire $1\main_wdata_consumed[0:0] + attribute \src "ls180.v:2932.56-2932.86" + wire $add$ls180.v:2932$58_Y + attribute \src "ls180.v:2992.56-2992.86" + wire $add$ls180.v:2992$69_Y + attribute \src "ls180.v:3052.59-3052.92" + wire $add$ls180.v:3052$80_Y + attribute \src "ls180.v:4245.54-4245.83" + wire $add$ls180.v:4245$685_Y + attribute \src "ls180.v:4345.36-4345.89" + wire width 5 $add$ls180.v:4345$731_Y + attribute \src "ls180.v:4375.36-4375.89" + wire width 5 $add$ls180.v:4375$742_Y + attribute \src "ls180.v:4441.54-4441.83" + wire width 3 $add$ls180.v:4441$757_Y + attribute \src "ls180.v:4500.52-4500.79" + wire width 3 $add$ls180.v:4500$765_Y + attribute \src "ls180.v:4604.58-4604.86" + wire width 8 $add$ls180.v:4604$793_Y + attribute \src "ls180.v:4661.58-4661.86" + wire width 8 $add$ls180.v:4661$796_Y + attribute \src "ls180.v:4678.58-4678.86" + wire width 8 $add$ls180.v:4678$798_Y + attribute \src "ls180.v:4771.59-4771.87" + wire width 8 $add$ls180.v:4771$815_Y + attribute \src "ls180.v:4796.59-4796.87" + wire width 8 $add$ls180.v:4796$818_Y + attribute \src "ls180.v:4918.53-4918.82" + wire width 8 $add$ls180.v:4918$835_Y + attribute \src "ls180.v:5029.65-5029.114" + wire width 10 $add$ls180.v:5029$849_Y + attribute \src "ls180.v:5034.62-5034.91" + wire width 10 $add$ls180.v:5034$852_Y + attribute \src "ls180.v:5060.61-5060.90" + wire width 10 $add$ls180.v:5060$855_Y + attribute \src "ls180.v:5264.80-5264.117" + wire width 3 $add$ls180.v:5264$1040_Y + attribute \src "ls180.v:5458.54-5458.82" + wire width 3 $add$ls180.v:5458$1115_Y + attribute \src "ls180.v:5510.55-5510.84" + wire width 32 $add$ls180.v:5510$1125_Y + attribute \src "ls180.v:5536.57-5536.86" + wire width 32 $add$ls180.v:5536$1133_Y + attribute \src "ls180.v:5657.51-5657.134" + wire width 32 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$eq$ls180.v:4416$755_Y + attribute \src "ls180.v:4443.10-4443.67" + wire $eq$ls180.v:4443$759_Y + attribute \src "ls180.v:4473.35-4473.108" + wire $eq$ls180.v:4473$761_Y + attribute \src "ls180.v:4474.35-4474.102" + wire $eq$ls180.v:4474$763_Y + attribute \src "ls180.v:4502.10-4502.65" + wire $eq$ls180.v:4502$767_Y + attribute \src "ls180.v:4606.10-4606.40" + wire $eq$ls180.v:4606$794_Y + attribute \src "ls180.v:4663.10-4663.39" + wire $eq$ls180.v:4663$797_Y + attribute \src "ls180.v:4680.10-4680.39" + wire $eq$ls180.v:4680$799_Y + attribute \src "ls180.v:4708.38-4708.88" + wire $eq$ls180.v:4708$801_Y + attribute \src "ls180.v:4758.9-4758.40" + wire $eq$ls180.v:4758$811_Y + attribute \src "ls180.v:4767.36-4767.105" + wire $eq$ls180.v:4767$813_Y + attribute \src "ls180.v:4786.9-4786.40" + wire $eq$ls180.v:4786$817_Y + attribute \src "ls180.v:4798.10-4798.39" + wire $eq$ls180.v:4798$819_Y + attribute \src "ls180.v:4835.39-4835.94" + wire $eq$ls180.v:4835$823_Y + attribute \src "ls180.v:4872.32-4872.89" + wire $eq$ls180.v:4872$832_Y + attribute \src "ls180.v:4920.10-4920.40" + wire $eq$ls180.v:4920$836_Y + attribute \src "ls180.v:4969.40-4969.98" + wire $eq$ls180.v:4969$838_Y + attribute \src "ls180.v:5020.9-5020.41" + wire $eq$ls180.v:5020$848_Y + attribute \src "ls180.v:5029.37-5029.123" + wire $eq$ls180.v:5029$851_Y + attribute \src "ls180.v:5052.9-5052.41" + wire $eq$ls180.v:5052$854_Y + attribute \src "ls180.v:5062.10-5062.41" + wire $eq$ls180.v:5062$856_Y + attribute \src "ls180.v:5231.9-5231.47" + wire $eq$ls180.v:5231$1038_Y + attribute \src "ls180.v:5261.10-5261.48" + wire $eq$ls180.v:5261$1039_Y + attribute \src "ls180.v:5292.10-5292.78" + wire $eq$ls180.v:5292$1044_Y + attribute \src "ls180.v:5292.83-5292.151" + wire $eq$ls180.v:5292$1045_Y + attribute \src "ls180.v:5292.157-5292.225" + wire $eq$ls180.v:5292$1047_Y + attribute \src "ls180.v:5292.231-5292.299" + wire $eq$ls180.v:5292$1049_Y + attribute \src "ls180.v:5300.7-5300.44" + wire $eq$ls180.v:5300$1053_Y + attribute \src "ls180.v:5310.7-5310.44" + wire $eq$ls180.v:5310$1056_Y + attribute \src "ls180.v:5320.7-5320.44" + wire $eq$ls180.v:5320$1059_Y + attribute \src "ls180.v:5330.7-5330.44" + wire $eq$ls180.v:5330$1062_Y + attribute \src "ls180.v:5454.36-5454.64" + wire $eq$ls180.v:5454$1113_Y + attribute \src "ls180.v:5460.10-5460.39" + wire $eq$ls180.v:5460$1116_Y + attribute \src "ls180.v:5461.11-5461.39" + wire $eq$ls180.v:5461$1117_Y + attribute \src "ls180.v:5473.34-5473.63" + wire $eq$ls180.v:5473$1118_Y + attribute \src "ls180.v:5474.9-5474.37" + wire $eq$ls180.v:5474$1119_Y + attribute \src "ls180.v:5481.10-5481.55" + wire $eq$ls180.v:5481$1120_Y + attribute \src "ls180.v:5487.12-5487.41" + wire $eq$ls180.v:5487$1121_Y + attribute \src "ls180.v:5490.13-5490.42" + wire $eq$ls180.v:5490$1122_Y + attribute \src "ls180.v:5512.10-5512.76" + wire $eq$ls180.v:5512$1127_Y + attribute \src "ls180.v:5527.35-5527.101" + wire $eq$ls180.v:5527$1130_Y + attribute \src "ls180.v:5529.10-5529.56" + wire $eq$ls180.v:5529$1131_Y + attribute \src "ls180.v:5538.12-5538.78" + wire $eq$ls180.v:5538$1135_Y + attribute \src "ls180.v:5545.11-5545.57" + wire $eq$ls180.v:5545$1136_Y + attribute \src "ls180.v:5662.10-5662.105" + wire $eq$ls180.v:5662$1153_Y + attribute \src "ls180.v:5752.39-5752.106" + wire $eq$ls180.v:5752$1159_Y + attribute \src "ls180.v:5782.44-5782.82" + wire $eq$ls180.v:5782$1162_Y + attribute \src "ls180.v:5783.43-5783.81" + wire $eq$ls180.v:5783$1163_Y + attribute \src "ls180.v:5895.68-5895.89" + wire $eq$ls180.v:5895$1179_Y + attribute \src "ls180.v:5896.68-5896.89" + wire $eq$ls180.v:5896$1181_Y + attribute \src "ls180.v:5897.71-5897.92" + wire $eq$ls180.v:5897$1183_Y + attribute \src "ls180.v:5898.57-5898.78" + wire $eq$ls180.v:5898$1185_Y + attribute \src "ls180.v:5899.57-5899.78" + wire $eq$ls180.v:5899$1187_Y + attribute \src "ls180.v:5900.68-5900.89" + wire $eq$ls180.v:5900$1189_Y + attribute \src "ls180.v:5901.68-5901.89" + wire $eq$ls180.v:5901$1191_Y + attribute \src "ls180.v:5902.71-5902.92" + wire $eq$ls180.v:5902$1193_Y + attribute \src "ls180.v:5903.57-5903.78" + wire $eq$ls180.v:5903$1195_Y + attribute \src "ls180.v:5904.57-5904.78" + wire $eq$ls180.v:5904$1197_Y + attribute \src "ls180.v:5908.27-5908.59" + wire $eq$ls180.v:5908$1200_Y + attribute \src "ls180.v:5909.27-5909.59" + wire $eq$ls180.v:5909$1201_Y + attribute \src "ls180.v:5910.27-5910.59" + wire $eq$ls180.v:5910$1202_Y + attribute \src "ls180.v:5911.27-5911.59" + wire $eq$ls180.v:5911$1203_Y + attribute \src "ls180.v:5912.27-5912.59" + wire $eq$ls180.v:5912$1204_Y + attribute \src "ls180.v:5913.27-5913.68" + wire $eq$ls180.v:5913$1205_Y + attribute \src "ls180.v:5914.27-5914.65" + wire $eq$ls180.v:5914$1206_Y + attribute \src "ls180.v:5915.27-5915.59" + wire $eq$ls180.v:5915$1207_Y + attribute \src "ls180.v:5916.27-5916.59" + wire $eq$ls180.v:5916$1208_Y + attribute \src "ls180.v:5917.27-5917.59" + wire $eq$ls180.v:5917$1209_Y + attribute \src "ls180.v:5918.28-5918.60" + wire $eq$ls180.v:5918$1210_Y + attribute \src "ls180.v:5919.28-5919.62" + wire $eq$ls180.v:5919$1211_Y + attribute \src "ls180.v:5920.28-5920.66" + wire $eq$ls180.v:5920$1212_Y + attribute \src "ls180.v:6040.24-6040.45" + wire $eq$ls180.v:6040$1279_Y + attribute \src "ls180.v:6041.32-6041.77" + wire $eq$ls180.v:6041$1280_Y + attribute \src "ls180.v:6043.97-6043.141" + wire $eq$ls180.v:6043$1282_Y + attribute \src "ls180.v:6044.100-6044.144" + wire $eq$ls180.v:6044$1286_Y + attribute \src "ls180.v:6046.99-6046.143" + wire $eq$ls180.v:6046$1289_Y + attribute \src "ls180.v:6047.102-6047.146" + wire $eq$ls180.v:6047$1293_Y + attribute \src "ls180.v:6049.99-6049.143" + wire $eq$ls180.v:6049$1296_Y + attribute \src "ls180.v:6050.102-6050.146" + wire $eq$ls180.v:6050$1300_Y + attribute \src "ls180.v:6052.99-6052.143" + wire $eq$ls180.v:6052$1303_Y + attribute \src "ls180.v:6053.102-6053.146" + wire $eq$ls180.v:6053$1307_Y + attribute \src "ls180.v:6055.99-6055.143" + wire $eq$ls180.v:6055$1310_Y + attribute \src "ls180.v:6056.102-6056.146" + wire $eq$ls180.v:6056$1314_Y + attribute \src "ls180.v:6058.102-6058.146" + wire $eq$ls180.v:6058$1317_Y + attribute \src "ls180.v:6059.105-6059.149" + wire $eq$ls180.v:6059$1321_Y + attribute \src "ls180.v:6061.102-6061.146" + wire $eq$ls180.v:6061$1324_Y + attribute \src "ls180.v:6062.105-6062.149" + wire $eq$ls180.v:6062$1328_Y + attribute \src "ls180.v:6064.102-6064.146" + wire $eq$ls180.v:6064$1331_Y + attribute \src "ls180.v:6065.105-6065.149" + wire $eq$ls180.v:6065$1335_Y + attribute \src "ls180.v:6067.102-6067.146" + wire $eq$ls180.v:6067$1338_Y + attribute \src "ls180.v:6068.105-6068.149" + wire $eq$ls180.v:6068$1342_Y + attribute \src "ls180.v:6079.32-6079.77" + wire $eq$ls180.v:6079$1344_Y + attribute \src "ls180.v:6081.94-6081.138" + wire $eq$ls180.v:6081$1346_Y + attribute \src "ls180.v:6082.97-6082.141" + wire $eq$ls180.v:6082$1350_Y + attribute \src "ls180.v:6084.94-6084.138" + wire $eq$ls180.v:6084$1353_Y + attribute \src "ls180.v:6085.97-6085.141" + wire $eq$ls180.v:6085$1357_Y + attribute \src "ls180.v:6087.94-6087.138" + wire $eq$ls180.v:6087$1360_Y + attribute \src "ls180.v:6088.97-6088.141" + wire $eq$ls180.v:6088$1364_Y + attribute \src "ls180.v:6090.94-6090.138" + wire $eq$ls180.v:6090$1367_Y + attribute \src "ls180.v:6091.97-6091.141" + wire $eq$ls180.v:6091$1371_Y + attribute \src "ls180.v:6093.95-6093.139" + wire $eq$ls180.v:6093$1374_Y + attribute \src "ls180.v:6094.98-6094.142" + wire $eq$ls180.v:6094$1378_Y + attribute \src "ls180.v:6096.95-6096.139" + wire $eq$ls180.v:6096$1381_Y + attribute \src "ls180.v:6097.98-6097.142" + wire $eq$ls180.v:6097$1385_Y + attribute \src "ls180.v:6105.32-6105.78" + wire $eq$ls180.v:6105$1387_Y + attribute \src "ls180.v:6107.93-6107.135" + wire $eq$ls180.v:6107$1389_Y + attribute \src "ls180.v:6108.96-6108.138" + wire $eq$ls180.v:6108$1393_Y + attribute \src "ls180.v:6110.92-6110.134" + wire $eq$ls180.v:6110$1396_Y + attribute \src "ls180.v:6111.95-6111.137" + wire $eq$ls180.v:6111$1400_Y + attribute \src "ls180.v:6119.32-6119.78" + wire $eq$ls180.v:6119$1402_Y + attribute \src "ls180.v:6121.98-6121.142" + wire $eq$ls180.v:6121$1404_Y + attribute \src "ls180.v:6122.101-6122.145" + wire $eq$ls180.v:6122$1408_Y + attribute \src "ls180.v:6124.97-6124.141" + wire $eq$ls180.v:6124$1411_Y + attribute \src "ls180.v:6125.100-6125.144" + wire $eq$ls180.v:6125$1415_Y + attribute \src "ls180.v:6127.97-6127.141" + wire $eq$ls180.v:6127$1418_Y + attribute \src "ls180.v:6128.100-6128.144" + wire $eq$ls180.v:6128$1422_Y + attribute \src "ls180.v:6130.97-6130.141" + wire $eq$ls180.v:6130$1425_Y + attribute \src "ls180.v:6131.100-6131.144" + wire $eq$ls180.v:6131$1429_Y + attribute \src "ls180.v:6133.97-6133.141" + wire $eq$ls180.v:6133$1432_Y + attribute \src "ls180.v:6134.100-6134.144" + wire $eq$ls180.v:6134$1436_Y + attribute \src "ls180.v:6136.98-6136.142" + wire $eq$ls180.v:6136$1439_Y + attribute \src "ls180.v:6137.101-6137.145" + wire $eq$ls180.v:6137$1443_Y + attribute \src "ls180.v:6139.98-6139.142" + wire $eq$ls180.v:6139$1446_Y + attribute \src "ls180.v:6140.101-6140.145" + wire $eq$ls180.v:6140$1450_Y + attribute \src "ls180.v:6142.98-6142.142" + wire $eq$ls180.v:6142$1453_Y + attribute \src "ls180.v:6143.101-6143.145" + wire $eq$ls180.v:6143$1457_Y + attribute \src "ls180.v:6145.98-6145.142" + wire $eq$ls180.v:6145$1460_Y + attribute \src "ls180.v:6146.101-6146.145" + wire $eq$ls180.v:6146$1464_Y + attribute \src "ls180.v:6156.32-6156.78" + wire $eq$ls180.v:6156$1466_Y + attribute \src "ls180.v:6158.98-6158.142" + wire $eq$ls180.v:6158$1468_Y + attribute \src "ls180.v:6159.101-6159.145" + wire $eq$ls180.v:6159$1472_Y + attribute \src "ls180.v:6161.97-6161.141" + wire $eq$ls180.v:6161$1475_Y + attribute \src "ls180.v:6162.100-6162.144" + wire $eq$ls180.v:6162$1479_Y + attribute \src "ls180.v:6164.97-6164.141" + wire $eq$ls180.v:6164$1482_Y + attribute \src "ls180.v:6165.100-6165.144" + wire $eq$ls180.v:6165$1486_Y + attribute \src "ls180.v:6167.97-6167.141" + wire $eq$ls180.v:6167$1489_Y + attribute \src "ls180.v:6168.100-6168.144" + wire $eq$ls180.v:6168$1493_Y + attribute \src "ls180.v:6170.97-6170.141" + wire $eq$ls180.v:6170$1496_Y + attribute \src "ls180.v:6171.100-6171.144" + wire $eq$ls180.v:6171$1500_Y + attribute \src "ls180.v:6173.98-6173.142" + wire $eq$ls180.v:6173$1503_Y + attribute \src "ls180.v:6174.101-6174.145" + wire $eq$ls180.v:6174$1507_Y + attribute \src "ls180.v:6176.98-6176.142" + wire $eq$ls180.v:6176$1510_Y + attribute \src "ls180.v:6177.101-6177.145" + wire $eq$ls180.v:6177$1514_Y + attribute \src "ls180.v:6179.98-6179.142" + wire $eq$ls180.v:6179$1517_Y + attribute \src "ls180.v:6180.101-6180.145" + wire $eq$ls180.v:6180$1521_Y + attribute \src "ls180.v:6182.98-6182.142" + wire $eq$ls180.v:6182$1524_Y + attribute \src "ls180.v:6183.101-6183.145" + wire $eq$ls180.v:6183$1528_Y + attribute \src "ls180.v:6193.32-6193.78" + wire $eq$ls180.v:6193$1530_Y + attribute \src "ls180.v:6195.100-6195.144" + wire $eq$ls180.v:6195$1532_Y + attribute \src "ls180.v:6196.103-6196.147" + wire $eq$ls180.v:6196$1536_Y + attribute \src "ls180.v:6198.100-6198.144" + wire $eq$ls180.v:6198$1539_Y + attribute \src "ls180.v:6199.103-6199.147" + wire $eq$ls180.v:6199$1543_Y + attribute \src "ls180.v:6201.100-6201.144" + wire $eq$ls180.v:6201$1546_Y + attribute \src "ls180.v:6202.103-6202.147" + wire $eq$ls180.v:6202$1550_Y + attribute \src "ls180.v:6204.100-6204.144" + wire $eq$ls180.v:6204$1553_Y + attribute \src "ls180.v:6205.103-6205.147" + wire $eq$ls180.v:6205$1557_Y + attribute \src "ls180.v:6207.100-6207.144" + wire $eq$ls180.v:6207$1560_Y + attribute \src "ls180.v:6208.103-6208.147" + wire $eq$ls180.v:6208$1564_Y + attribute \src "ls180.v:6210.100-6210.144" + wire $eq$ls180.v:6210$1567_Y + attribute \src "ls180.v:6211.103-6211.147" + wire $eq$ls180.v:6211$1571_Y + attribute \src "ls180.v:6213.100-6213.144" + wire $eq$ls180.v:6213$1574_Y + attribute \src "ls180.v:6214.103-6214.147" + wire $eq$ls180.v:6214$1578_Y + attribute \src "ls180.v:6216.100-6216.144" + wire $eq$ls180.v:6216$1581_Y + attribute \src "ls180.v:6217.103-6217.147" + wire $eq$ls180.v:6217$1585_Y + attribute \src "ls180.v:6219.102-6219.146" + wire $eq$ls180.v:6219$1588_Y + attribute \src "ls180.v:6220.105-6220.149" + wire $eq$ls180.v:6220$1592_Y + attribute \src "ls180.v:6222.102-6222.146" + wire $eq$ls180.v:6222$1595_Y + attribute \src "ls180.v:6223.105-6223.149" + wire $eq$ls180.v:6223$1599_Y + attribute \src "ls180.v:6225.102-6225.147" + wire $eq$ls180.v:6225$1602_Y + attribute \src "ls180.v:6226.105-6226.150" + wire $eq$ls180.v:6226$1606_Y + attribute \src "ls180.v:6228.102-6228.147" + wire $eq$ls180.v:6228$1609_Y + attribute \src "ls180.v:6229.105-6229.150" + wire $eq$ls180.v:6229$1613_Y + attribute \src "ls180.v:6231.102-6231.147" + wire $eq$ls180.v:6231$1616_Y + attribute \src "ls180.v:6232.105-6232.150" + wire $eq$ls180.v:6232$1620_Y + attribute \src "ls180.v:6234.99-6234.144" + wire $eq$ls180.v:6234$1623_Y + attribute \src "ls180.v:6235.102-6235.147" + wire $eq$ls180.v:6235$1627_Y + attribute \src "ls180.v:6237.100-6237.145" + wire $eq$ls180.v:6237$1630_Y + attribute \src "ls180.v:6238.103-6238.148" + wire $eq$ls180.v:6238$1634_Y + attribute \src "ls180.v:6255.32-6255.78" + wire $eq$ls180.v:6255$1636_Y + attribute \src "ls180.v:6257.104-6257.148" + wire $eq$ls180.v:6257$1638_Y + attribute \src "ls180.v:6258.107-6258.151" + wire $eq$ls180.v:6258$1642_Y + attribute \src "ls180.v:6260.104-6260.148" + wire $eq$ls180.v:6260$1645_Y + attribute \src "ls180.v:6261.107-6261.151" + wire $eq$ls180.v:6261$1649_Y + attribute \src "ls180.v:6263.104-6263.148" + wire $eq$ls180.v:6263$1652_Y + attribute \src "ls180.v:6264.107-6264.151" + wire $eq$ls180.v:6264$1656_Y + attribute \src "ls180.v:6266.104-6266.148" + wire $eq$ls180.v:6266$1659_Y + attribute \src "ls180.v:6267.107-6267.151" + wire $eq$ls180.v:6267$1663_Y + attribute \src "ls180.v:6269.103-6269.147" + wire $eq$ls180.v:6269$1666_Y + attribute \src "ls180.v:6270.106-6270.150" + wire $eq$ls180.v:6270$1670_Y + attribute \src "ls180.v:6272.103-6272.147" + wire $eq$ls180.v:6272$1673_Y + attribute \src "ls180.v:6273.106-6273.150" + wire $eq$ls180.v:6273$1677_Y + attribute \src "ls180.v:6275.103-6275.147" + wire $eq$ls180.v:6275$1680_Y + attribute \src "ls180.v:6276.106-6276.150" + wire $eq$ls180.v:6276$1684_Y + attribute \src "ls180.v:6278.103-6278.147" + wire $eq$ls180.v:6278$1687_Y + attribute \src "ls180.v:6279.106-6279.150" + wire $eq$ls180.v:6279$1691_Y + attribute \src "ls180.v:6281.94-6281.138" + wire $eq$ls180.v:6281$1694_Y + attribute \src "ls180.v:6282.97-6282.141" + wire $eq$ls180.v:6282$1698_Y + attribute \src "ls180.v:6284.105-6284.149" + wire $eq$ls180.v:6284$1701_Y + attribute \src "ls180.v:6285.108-6285.152" + wire $eq$ls180.v:6285$1705_Y + attribute \src "ls180.v:6287.105-6287.150" + wire $eq$ls180.v:6287$1708_Y + attribute \src "ls180.v:6288.108-6288.153" + wire $eq$ls180.v:6288$1712_Y + attribute \src "ls180.v:6290.105-6290.150" + wire $eq$ls180.v:6290$1715_Y + attribute \src "ls180.v:6291.108-6291.153" + wire $eq$ls180.v:6291$1719_Y + attribute \src "ls180.v:6293.105-6293.150" + wire $eq$ls180.v:6293$1722_Y + attribute \src "ls180.v:6294.108-6294.153" + wire $eq$ls180.v:6294$1726_Y + attribute \src "ls180.v:6296.105-6296.150" + wire $eq$ls180.v:6296$1729_Y + attribute \src "ls180.v:6297.108-6297.153" + wire $eq$ls180.v:6297$1733_Y + attribute \src "ls180.v:6299.105-6299.150" + wire $eq$ls180.v:6299$1736_Y + attribute \src "ls180.v:6300.108-6300.153" + wire $eq$ls180.v:6300$1740_Y + attribute \src "ls180.v:6302.104-6302.149" + wire $eq$ls180.v:6302$1743_Y + attribute \src "ls180.v:6303.107-6303.152" + wire $eq$ls180.v:6303$1747_Y + attribute \src "ls180.v:6305.104-6305.149" + wire $eq$ls180.v:6305$1750_Y + attribute \src "ls180.v:6306.107-6306.152" + wire $eq$ls180.v:6306$1754_Y + attribute \src "ls180.v:6308.104-6308.149" + wire $eq$ls180.v:6308$1757_Y + attribute \src "ls180.v:6309.107-6309.152" + wire $eq$ls180.v:6309$1761_Y + attribute \src "ls180.v:6311.104-6311.149" + wire $eq$ls180.v:6311$1764_Y + attribute \src "ls180.v:6312.107-6312.152" + wire $eq$ls180.v:6312$1768_Y + attribute \src "ls180.v:6314.104-6314.149" + wire $eq$ls180.v:6314$1771_Y + attribute \src "ls180.v:6315.107-6315.152" + wire $eq$ls180.v:6315$1775_Y + attribute \src "ls180.v:6317.104-6317.149" + wire $eq$ls180.v:6317$1778_Y + attribute \src "ls180.v:6318.107-6318.152" + wire $eq$ls180.v:6318$1782_Y + attribute \src "ls180.v:6320.104-6320.149" + wire $eq$ls180.v:6320$1785_Y + attribute \src "ls180.v:6321.107-6321.152" + wire $eq$ls180.v:6321$1789_Y + attribute \src "ls180.v:6323.104-6323.149" + wire $eq$ls180.v:6323$1792_Y + attribute \src "ls180.v:6324.107-6324.152" + wire $eq$ls180.v:6324$1796_Y + attribute \src "ls180.v:6326.104-6326.149" + wire $eq$ls180.v:6326$1799_Y + attribute \src "ls180.v:6327.107-6327.152" + wire $eq$ls180.v:6327$1803_Y + attribute \src "ls180.v:6329.104-6329.149" + wire $eq$ls180.v:6329$1806_Y + attribute \src "ls180.v:6330.107-6330.152" + wire $eq$ls180.v:6330$1810_Y + attribute \src "ls180.v:6332.100-6332.145" + wire $eq$ls180.v:6332$1813_Y + attribute \src "ls180.v:6333.103-6333.148" + wire $eq$ls180.v:6333$1817_Y + attribute \src "ls180.v:6335.101-6335.146" + wire $eq$ls180.v:6335$1820_Y + attribute \src "ls180.v:6336.104-6336.149" + wire $eq$ls180.v:6336$1824_Y + attribute \src "ls180.v:6338.104-6338.149" + wire $eq$ls180.v:6338$1827_Y + attribute \src "ls180.v:6339.107-6339.152" + wire $eq$ls180.v:6339$1831_Y + attribute \src "ls180.v:6341.104-6341.149" + wire $eq$ls180.v:6341$1834_Y + attribute \src "ls180.v:6342.107-6342.152" + wire $eq$ls180.v:6342$1838_Y + attribute \src "ls180.v:6344.103-6344.148" + wire $eq$ls180.v:6344$1841_Y + attribute \src "ls180.v:6345.106-6345.151" + wire $eq$ls180.v:6345$1845_Y + attribute \src "ls180.v:6347.103-6347.148" + wire $eq$ls180.v:6347$1848_Y + attribute \src "ls180.v:6348.106-6348.151" + wire $eq$ls180.v:6348$1852_Y + attribute \src "ls180.v:6350.103-6350.148" + wire $eq$ls180.v:6350$1855_Y + attribute \src "ls180.v:6351.106-6351.151" + wire $eq$ls180.v:6351$1859_Y + attribute \src "ls180.v:6353.103-6353.148" + wire $eq$ls180.v:6353$1862_Y + attribute \src "ls180.v:6354.106-6354.151" + wire $eq$ls180.v:6354$1866_Y + attribute \src "ls180.v:6390.32-6390.78" + wire $eq$ls180.v:6390$1868_Y + attribute \src "ls180.v:6392.100-6392.144" + wire $eq$ls180.v:6392$1870_Y + attribute \src "ls180.v:6393.103-6393.147" + wire $eq$ls180.v:6393$1874_Y + attribute \src "ls180.v:6395.100-6395.144" + wire $eq$ls180.v:6395$1877_Y + attribute \src "ls180.v:6396.103-6396.147" + wire $eq$ls180.v:6396$1881_Y + attribute \src "ls180.v:6398.100-6398.144" + wire $eq$ls180.v:6398$1884_Y + attribute \src "ls180.v:6399.103-6399.147" + wire $eq$ls180.v:6399$1888_Y + attribute \src "ls180.v:6401.100-6401.144" + wire $eq$ls180.v:6401$1891_Y + attribute \src "ls180.v:6402.103-6402.147" + wire $eq$ls180.v:6402$1895_Y + attribute \src "ls180.v:6404.100-6404.144" + wire $eq$ls180.v:6404$1898_Y + attribute \src "ls180.v:6405.103-6405.147" + wire $eq$ls180.v:6405$1902_Y + attribute \src "ls180.v:6407.100-6407.144" + wire $eq$ls180.v:6407$1905_Y + attribute \src "ls180.v:6408.103-6408.147" + wire $eq$ls180.v:6408$1909_Y + attribute \src "ls180.v:6410.100-6410.144" + wire $eq$ls180.v:6410$1912_Y + attribute \src "ls180.v:6411.103-6411.147" + wire $eq$ls180.v:6411$1916_Y + attribute \src "ls180.v:6413.100-6413.144" + wire $eq$ls180.v:6413$1919_Y + attribute \src "ls180.v:6414.103-6414.147" + wire $eq$ls180.v:6414$1923_Y + attribute \src "ls180.v:6416.102-6416.146" + wire $eq$ls180.v:6416$1926_Y + attribute \src "ls180.v:6417.105-6417.149" + wire $eq$ls180.v:6417$1930_Y + attribute \src "ls180.v:6419.102-6419.146" + wire $eq$ls180.v:6419$1933_Y + attribute \src "ls180.v:6420.105-6420.149" + wire $eq$ls180.v:6420$1937_Y + attribute \src "ls180.v:6422.102-6422.147" + wire $eq$ls180.v:6422$1940_Y + attribute \src "ls180.v:6423.105-6423.150" + wire $eq$ls180.v:6423$1944_Y + attribute \src "ls180.v:6425.102-6425.147" + wire $eq$ls180.v:6425$1947_Y + attribute \src "ls180.v:6426.105-6426.150" + wire $eq$ls180.v:6426$1951_Y + attribute \src "ls180.v:6428.102-6428.147" + wire $eq$ls180.v:6428$1954_Y + attribute \src "ls180.v:6429.105-6429.150" + wire $eq$ls180.v:6429$1958_Y + attribute \src "ls180.v:6431.99-6431.144" + wire $eq$ls180.v:6431$1961_Y + attribute \src "ls180.v:6432.102-6432.147" + wire $eq$ls180.v:6432$1965_Y + attribute \src "ls180.v:6434.100-6434.145" + wire $eq$ls180.v:6434$1968_Y + attribute \src "ls180.v:6435.103-6435.148" + wire $eq$ls180.v:6435$1972_Y + attribute \src "ls180.v:6437.102-6437.147" + wire $eq$ls180.v:6437$1975_Y + attribute \src "ls180.v:6438.105-6438.150" + wire $eq$ls180.v:6438$1979_Y + attribute \src "ls180.v:6440.102-6440.147" + wire $eq$ls180.v:6440$1982_Y + attribute \src "ls180.v:6441.105-6441.150" + wire $eq$ls180.v:6441$1986_Y + attribute \src "ls180.v:6443.102-6443.147" + wire $eq$ls180.v:6443$1989_Y + attribute \src "ls180.v:6444.105-6444.150" + wire $eq$ls180.v:6444$1993_Y + attribute \src "ls180.v:6446.102-6446.147" + wire $eq$ls180.v:6446$1996_Y + attribute \src "ls180.v:6447.105-6447.150" + wire $eq$ls180.v:6447$2000_Y + attribute \src "ls180.v:6469.32-6469.78" + wire $eq$ls180.v:6469$2002_Y + attribute \src "ls180.v:6471.102-6471.146" + wire $eq$ls180.v:6471$2004_Y + attribute \src "ls180.v:6472.105-6472.149" + wire $eq$ls180.v:6472$2008_Y + attribute \src "ls180.v:6474.107-6474.151" + wire $eq$ls180.v:6474$2011_Y + attribute \src "ls180.v:6475.110-6475.154" + wire $eq$ls180.v:6475$2015_Y + attribute \src "ls180.v:6477.107-6477.151" + wire $eq$ls180.v:6477$2018_Y + attribute \src "ls180.v:6478.110-6478.154" + wire $eq$ls180.v:6478$2022_Y + attribute \src "ls180.v:6480.100-6480.144" + wire $eq$ls180.v:6480$2025_Y + attribute \src "ls180.v:6481.103-6481.147" + wire $eq$ls180.v:6481$2029_Y + attribute \src "ls180.v:6486.32-6486.77" + wire $eq$ls180.v:6486$2031_Y + attribute \src "ls180.v:6488.104-6488.148" + wire $eq$ls180.v:6488$2033_Y + attribute \src "ls180.v:6489.107-6489.151" + wire $eq$ls180.v:6489$2037_Y + attribute \src "ls180.v:6491.108-6491.152" + wire $eq$ls180.v:6491$2040_Y + attribute \src "ls180.v:6492.111-6492.155" + wire $eq$ls180.v:6492$2044_Y + attribute \src "ls180.v:6494.98-6494.142" + wire $eq$ls180.v:6494$2047_Y + attribute \src "ls180.v:6495.101-6495.145" + wire $eq$ls180.v:6495$2051_Y + attribute \src "ls180.v:6497.108-6497.152" + wire $eq$ls180.v:6497$2054_Y + attribute \src "ls180.v:6498.111-6498.155" + wire $eq$ls180.v:6498$2058_Y + attribute \src "ls180.v:6500.108-6500.152" + wire $eq$ls180.v:6500$2061_Y + attribute \src "ls180.v:6501.111-6501.155" + wire $eq$ls180.v:6501$2065_Y + attribute \src "ls180.v:6503.109-6503.153" + wire $eq$ls180.v:6503$2068_Y + attribute \src "ls180.v:6504.112-6504.156" + wire $eq$ls180.v:6504$2072_Y + attribute \src "ls180.v:6506.107-6506.151" + wire $eq$ls180.v:6506$2075_Y + attribute \src "ls180.v:6507.110-6507.154" + wire $eq$ls180.v:6507$2079_Y + attribute \src "ls180.v:6509.107-6509.151" + wire $eq$ls180.v:6509$2082_Y + attribute \src "ls180.v:6510.110-6510.154" + wire $eq$ls180.v:6510$2086_Y + attribute \src "ls180.v:6512.107-6512.151" + wire $eq$ls180.v:6512$2089_Y + attribute \src "ls180.v:6513.110-6513.154" + wire $eq$ls180.v:6513$2093_Y + attribute \src "ls180.v:6515.107-6515.151" + wire $eq$ls180.v:6515$2096_Y + attribute \src "ls180.v:6516.110-6516.154" + wire $eq$ls180.v:6516$2100_Y + attribute \src "ls180.v:6531.33-6531.79" + wire $eq$ls180.v:6531$2102_Y + attribute \src "ls180.v:6533.102-6533.147" + wire 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$eq$ls180.v:6628$2238_Y + attribute \src "ls180.v:6630.99-6630.144" + wire $eq$ls180.v:6630$2241_Y + attribute \src "ls180.v:6631.102-6631.147" + wire $eq$ls180.v:6631$2245_Y + attribute \src "ls180.v:6633.101-6633.146" + wire $eq$ls180.v:6633$2248_Y + attribute \src "ls180.v:6634.104-6634.149" + wire $eq$ls180.v:6634$2252_Y + attribute \src "ls180.v:6636.101-6636.146" + wire $eq$ls180.v:6636$2255_Y + attribute \src "ls180.v:6637.104-6637.149" + wire $eq$ls180.v:6637$2259_Y + attribute \src "ls180.v:6639.101-6639.146" + wire $eq$ls180.v:6639$2262_Y + attribute \src "ls180.v:6640.104-6640.149" + wire $eq$ls180.v:6640$2266_Y + attribute \src "ls180.v:6642.101-6642.146" + wire $eq$ls180.v:6642$2269_Y + attribute \src "ls180.v:6643.104-6643.149" + wire $eq$ls180.v:6643$2273_Y + attribute \src "ls180.v:6645.97-6645.142" + wire $eq$ls180.v:6645$2276_Y + attribute \src "ls180.v:6646.100-6646.145" + wire $eq$ls180.v:6646$2280_Y + attribute \src "ls180.v:6648.107-6648.152" + wire $eq$ls180.v:6648$2283_Y + attribute \src "ls180.v:6649.110-6649.155" + wire $eq$ls180.v:6649$2287_Y + attribute \src "ls180.v:6651.100-6651.146" + wire $eq$ls180.v:6651$2290_Y + attribute \src "ls180.v:6652.103-6652.149" + wire $eq$ls180.v:6652$2294_Y + attribute \src "ls180.v:6654.100-6654.146" + wire $eq$ls180.v:6654$2297_Y + attribute \src "ls180.v:6655.103-6655.149" + wire $eq$ls180.v:6655$2301_Y + attribute \src "ls180.v:6657.100-6657.146" + wire $eq$ls180.v:6657$2304_Y + attribute \src "ls180.v:6658.103-6658.149" + wire $eq$ls180.v:6658$2308_Y + attribute \src "ls180.v:6660.100-6660.146" + wire $eq$ls180.v:6660$2311_Y + attribute \src "ls180.v:6661.103-6661.149" + wire $eq$ls180.v:6661$2315_Y + attribute \src "ls180.v:6663.112-6663.158" + wire $eq$ls180.v:6663$2318_Y + attribute \src "ls180.v:6664.115-6664.161" + wire $eq$ls180.v:6664$2322_Y + attribute \src "ls180.v:6666.113-6666.159" + wire $eq$ls180.v:6666$2325_Y + attribute \src "ls180.v:6667.116-6667.162" + wire $eq$ls180.v:6667$2329_Y + attribute \src "ls180.v:6669.104-6669.150" + wire $eq$ls180.v:6669$2332_Y + attribute \src "ls180.v:6670.107-6670.153" + wire $eq$ls180.v:6670$2336_Y + attribute \src "ls180.v:6687.33-6687.79" + wire $eq$ls180.v:6687$2338_Y + attribute \src "ls180.v:6689.90-6689.135" + wire $eq$ls180.v:6689$2340_Y + attribute \src "ls180.v:6690.93-6690.138" + wire $eq$ls180.v:6690$2344_Y + attribute \src "ls180.v:6692.100-6692.145" + wire $eq$ls180.v:6692$2347_Y + attribute \src "ls180.v:6693.103-6693.148" + wire $eq$ls180.v:6693$2351_Y + attribute \src "ls180.v:6695.101-6695.146" + wire $eq$ls180.v:6695$2354_Y + attribute \src "ls180.v:6696.104-6696.149" + wire $eq$ls180.v:6696$2358_Y + attribute \src "ls180.v:6698.105-6698.150" + wire $eq$ls180.v:6698$2361_Y + attribute \src "ls180.v:6699.108-6699.153" + wire $eq$ls180.v:6699$2365_Y + attribute \src "ls180.v:6701.106-6701.151" + wire $eq$ls180.v:6701$2368_Y + attribute \src "ls180.v:6702.109-6702.154" + wire $eq$ls180.v:6702$2372_Y + attribute \src "ls180.v:6704.104-6704.149" + wire $eq$ls180.v:6704$2375_Y + attribute \src "ls180.v:6705.107-6705.152" + wire $eq$ls180.v:6705$2379_Y + attribute \src "ls180.v:6707.101-6707.146" + wire $eq$ls180.v:6707$2382_Y + attribute \src "ls180.v:6708.104-6708.149" + wire $eq$ls180.v:6708$2386_Y + attribute \src "ls180.v:6710.100-6710.145" + wire $eq$ls180.v:6710$2389_Y + attribute \src "ls180.v:6711.103-6711.148" + wire $eq$ls180.v:6711$2393_Y + attribute \src "ls180.v:6721.33-6721.79" + wire $eq$ls180.v:6721$2395_Y + attribute \src "ls180.v:6723.106-6723.151" + wire $eq$ls180.v:6723$2397_Y + attribute \src "ls180.v:6724.109-6724.154" + wire $eq$ls180.v:6724$2401_Y + attribute \src "ls180.v:6726.106-6726.151" + wire $eq$ls180.v:6726$2404_Y + attribute \src "ls180.v:6727.109-6727.154" + wire $eq$ls180.v:6727$2408_Y + attribute \src "ls180.v:6729.106-6729.151" + wire $eq$ls180.v:6729$2411_Y + attribute \src "ls180.v:6730.109-6730.154" + wire $eq$ls180.v:6730$2415_Y + attribute \src "ls180.v:6732.106-6732.151" + wire $eq$ls180.v:6732$2418_Y + attribute \src "ls180.v:6733.109-6733.154" + wire $eq$ls180.v:6733$2422_Y + attribute \src "ls180.v:7114.41-7114.81" + wire $eq$ls180.v:7114$2459_Y + attribute \src "ls180.v:7114.144-7114.177" + wire $eq$ls180.v:7114$2460_Y + attribute \src "ls180.v:7114.219-7114.252" + wire $eq$ls180.v:7114$2463_Y + attribute \src "ls180.v:7114.294-7114.327" + wire $eq$ls180.v:7114$2466_Y + attribute \src "ls180.v:7138.41-7138.81" + wire $eq$ls180.v:7138$2475_Y + attribute \src "ls180.v:7138.144-7138.177" + wire $eq$ls180.v:7138$2476_Y + attribute \src "ls180.v:7138.219-7138.252" + wire $eq$ls180.v:7138$2479_Y + attribute \src "ls180.v:7138.294-7138.327" + wire $eq$ls180.v:7138$2482_Y + attribute \src "ls180.v:7162.41-7162.81" + wire $eq$ls180.v:7162$2491_Y + attribute \src "ls180.v:7162.144-7162.177" + wire $eq$ls180.v:7162$2492_Y + attribute \src "ls180.v:7162.219-7162.252" + wire $eq$ls180.v:7162$2495_Y + attribute \src "ls180.v:7162.294-7162.327" + wire $eq$ls180.v:7162$2498_Y + attribute \src "ls180.v:7186.41-7186.81" + wire $eq$ls180.v:7186$2507_Y + attribute \src "ls180.v:7186.144-7186.177" + wire $eq$ls180.v:7186$2508_Y + attribute \src "ls180.v:7186.219-7186.252" + wire $eq$ls180.v:7186$2511_Y + attribute \src "ls180.v:7186.294-7186.327" + wire $eq$ls180.v:7186$2514_Y + attribute \src "ls180.v:7770.8-7770.38" + wire $eq$ls180.v:7770$2606_Y + attribute \src "ls180.v:7817.8-7817.42" + wire $eq$ls180.v:7817$2626_Y + attribute \src "ls180.v:7837.38-7837.74" + wire $eq$ls180.v:7837$2629_Y + attribute \src "ls180.v:7844.7-7844.43" + wire $eq$ls180.v:7844$2631_Y + attribute \src "ls180.v:7851.7-7851.43" + wire $eq$ls180.v:7851$2632_Y + attribute \src "ls180.v:7859.7-7859.43" + wire $eq$ls180.v:7859$2633_Y + attribute \src "ls180.v:7911.9-7911.54" + wire $eq$ls180.v:7911$2651_Y + attribute \src "ls180.v:7957.9-7957.54" + wire $eq$ls180.v:7957$2667_Y + attribute \src "ls180.v:8003.9-8003.54" + wire $eq$ls180.v:8003$2683_Y + attribute \src "ls180.v:8049.9-8049.54" + wire $eq$ls180.v:8049$2699_Y + attribute \src "ls180.v:8199.9-8199.41" + wire $eq$ls180.v:8199$2711_Y + attribute \src "ls180.v:8214.9-8214.41" + wire $eq$ls180.v:8214$2714_Y + attribute \src "ls180.v:8220.49-8220.82" + wire $eq$ls180.v:8220$2715_Y + attribute \src "ls180.v:8220.131-8220.164" + wire $eq$ls180.v:8220$2718_Y + attribute \src "ls180.v:8220.213-8220.246" + wire $eq$ls180.v:8220$2721_Y + attribute \src "ls180.v:8220.295-8220.328" + wire $eq$ls180.v:8220$2724_Y + attribute \src "ls180.v:8221.50-8221.83" + wire $eq$ls180.v:8221$2727_Y + attribute \src "ls180.v:8221.132-8221.165" + wire $eq$ls180.v:8221$2730_Y + attribute \src "ls180.v:8221.214-8221.247" + wire $eq$ls180.v:8221$2733_Y + attribute \src "ls180.v:8221.296-8221.329" + wire $eq$ls180.v:8221$2736_Y + attribute \src "ls180.v:8256.9-8256.42" + wire $eq$ls180.v:8256$2748_Y + attribute \src "ls180.v:8259.10-8259.43" + wire $eq$ls180.v:8259$2749_Y + attribute \src "ls180.v:8285.9-8285.42" + wire $eq$ls180.v:8285$2755_Y + attribute \src "ls180.v:8290.10-8290.43" + wire $eq$ls180.v:8290$2756_Y + attribute \src "ls180.v:8497.9-8497.53" + wire $eq$ls180.v:8497$2805_Y + attribute \src "ls180.v:8578.9-8578.54" + wire $eq$ls180.v:8578$2817_Y + attribute \src "ls180.v:8657.9-8657.55" + wire $eq$ls180.v:8657$2829_Y + attribute \src "ls180.v:8880.9-8880.49" + wire $eq$ls180.v:8880$2862_Y + attribute \src "ls180.v:8456.8-8456.54" + wire $ge$ls180.v:8456$2797_Y + attribute \src "ls180.v:8470.8-8470.54" + wire $ge$ls180.v:8470$2801_Y + attribute \src "ls180.v:5339.47-5339.83" + wire $gt$ls180.v:5339$1064_Y + attribute \src "ls180.v:5345.7-5345.43" + wire $lt$ls180.v:5345$1067_Y + attribute \src "ls180.v:8451.8-8451.43" + wire $lt$ls180.v:8451$2795_Y + attribute \src "ls180.v:8465.8-8465.43" + wire $lt$ls180.v:8465$2799_Y + attribute \src "ls180.v:10370.33-10370.36" + wire width 64 $memrd$\mem$ls180.v:10370$2916_DATA + attribute \src "ls180.v:10398.27-10398.32" + wire width 64 $memrd$\mem_1$ls180.v:10398$2942_DATA + attribute \src "ls180.v:10426.27-10426.32" + wire width 64 $memrd$\mem_2$ls180.v:10426$2968_DATA + attribute \src "ls180.v:10454.27-10454.32" + wire width 64 $memrd$\mem_3$ls180.v:10454$2994_DATA + attribute \src "ls180.v:10482.27-10482.32" + wire width 64 $memrd$\mem_4$ls180.v:10482$3020_DATA + attribute \src "ls180.v:10493.12-10493.19" + wire width 25 $memrd$\storage$ls180.v:10493$3025_DATA + attribute \src "ls180.v:10500.68-10500.75" + wire width 25 $memrd$\storage$ls180.v:10500$3027_DATA + attribute \src "ls180.v:10507.14-10507.23" + wire width 25 $memrd$\storage_1$ls180.v:10507$3032_DATA + attribute \src "ls180.v:10514.68-10514.77" + wire width 25 $memrd$\storage_1$ls180.v:10514$3034_DATA + attribute \src "ls180.v:10521.14-10521.23" + wire width 25 $memrd$\storage_2$ls180.v:10521$3039_DATA + attribute \src "ls180.v:10528.68-10528.77" + wire width 25 $memrd$\storage_2$ls180.v:10528$3041_DATA + attribute \src "ls180.v:10535.14-10535.23" + wire width 25 $memrd$\storage_3$ls180.v:10535$3046_DATA + attribute \src "ls180.v:10542.68-10542.77" + wire width 25 $memrd$\storage_3$ls180.v:10542$3048_DATA + attribute \src "ls180.v:10550.14-10550.23" + wire width 10 $memrd$\storage_4$ls180.v:10550$3053_DATA + attribute \src "ls180.v:10555.15-10555.24" + wire width 10 $memrd$\storage_4$ls180.v:10555$3055_DATA + attribute \src "ls180.v:10567.14-10567.23" + wire width 10 $memrd$\storage_5$ls180.v:10567$3060_DATA + attribute \src "ls180.v:10572.15-10572.24" + wire width 10 $memrd$\storage_5$ls180.v:10572$3062_DATA + attribute \src "ls180.v:10583.14-10583.23" + wire width 10 $memrd$\storage_6$ls180.v:10583$3067_DATA + attribute \src "ls180.v:10590.45-10590.54" + wire width 10 $memrd$\storage_6$ls180.v:10590$3069_DATA + attribute \src "ls180.v:10597.14-10597.23" + wire width 10 $memrd$\storage_7$ls180.v:10597$3074_DATA + attribute \src "ls180.v:10604.45-10604.54" + wire width 10 $memrd$\storage_7$ls180.v:10604$3076_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 6 $memwr$\mem$ls180.v:10352$1_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem$ls180.v:10352$1_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem$ls180.v:10352$1_EN + attribute \src "ls180.v:0.0-0.0" + wire width 6 $memwr$\mem$ls180.v:10354$2_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem$ls180.v:10354$2_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem$ls180.v:10354$2_EN + attribute \src "ls180.v:0.0-0.0" + wire width 6 $memwr$\mem$ls180.v:10356$3_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem$ls180.v:10356$3_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem$ls180.v:10356$3_EN + attribute \src "ls180.v:0.0-0.0" + wire width 6 $memwr$\mem$ls180.v:10358$4_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem$ls180.v:10358$4_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem$ls180.v:10358$4_EN + attribute \src "ls180.v:0.0-0.0" + wire width 6 $memwr$\mem$ls180.v:10360$5_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem$ls180.v:10360$5_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem$ls180.v:10360$5_EN + attribute \src "ls180.v:0.0-0.0" + wire width 6 $memwr$\mem$ls180.v:10362$6_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem$ls180.v:10362$6_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem$ls180.v:10362$6_EN + attribute \src "ls180.v:0.0-0.0" + wire width 6 $memwr$\mem$ls180.v:10364$7_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem$ls180.v:10364$7_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem$ls180.v:10364$7_EN + attribute \src "ls180.v:0.0-0.0" + wire width 6 $memwr$\mem$ls180.v:10366$8_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem$ls180.v:10366$8_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem$ls180.v:10366$8_EN + attribute \src "ls180.v:0.0-0.0" + wire width 6 $memwr$\mem_1$ls180.v:10380$9_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_1$ls180.v:10380$9_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_1$ls180.v:10380$9_EN + attribute \src "ls180.v:0.0-0.0" + wire width 6 $memwr$\mem_1$ls180.v:10382$10_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_1$ls180.v:10382$10_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_1$ls180.v:10382$10_EN + attribute \src "ls180.v:0.0-0.0" + wire width 6 $memwr$\mem_1$ls180.v:10384$11_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_1$ls180.v:10384$11_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_1$ls180.v:10384$11_EN + attribute \src "ls180.v:0.0-0.0" + wire width 6 $memwr$\mem_1$ls180.v:10386$12_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_1$ls180.v:10386$12_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_1$ls180.v:10386$12_EN + attribute \src "ls180.v:0.0-0.0" + wire width 6 $memwr$\mem_1$ls180.v:10388$13_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_1$ls180.v:10388$13_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_1$ls180.v:10388$13_EN + attribute \src "ls180.v:0.0-0.0" + wire width 6 $memwr$\mem_1$ls180.v:10390$14_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_1$ls180.v:10390$14_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_1$ls180.v:10390$14_EN + attribute \src "ls180.v:0.0-0.0" + wire width 6 $memwr$\mem_1$ls180.v:10392$15_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_1$ls180.v:10392$15_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_1$ls180.v:10392$15_EN + attribute \src "ls180.v:0.0-0.0" + wire width 6 $memwr$\mem_1$ls180.v:10394$16_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_1$ls180.v:10394$16_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_1$ls180.v:10394$16_EN + attribute \src "ls180.v:0.0-0.0" + wire width 6 $memwr$\mem_2$ls180.v:10408$17_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_2$ls180.v:10408$17_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_2$ls180.v:10408$17_EN + attribute \src "ls180.v:0.0-0.0" + wire width 6 $memwr$\mem_2$ls180.v:10410$18_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_2$ls180.v:10410$18_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_2$ls180.v:10410$18_EN + attribute \src "ls180.v:0.0-0.0" + wire width 6 $memwr$\mem_2$ls180.v:10412$19_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_2$ls180.v:10412$19_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_2$ls180.v:10412$19_EN + attribute \src "ls180.v:0.0-0.0" + wire width 6 $memwr$\mem_2$ls180.v:10414$20_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_2$ls180.v:10414$20_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_2$ls180.v:10414$20_EN + attribute \src "ls180.v:0.0-0.0" + wire width 6 $memwr$\mem_2$ls180.v:10416$21_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_2$ls180.v:10416$21_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_2$ls180.v:10416$21_EN + attribute \src "ls180.v:0.0-0.0" + wire width 6 $memwr$\mem_2$ls180.v:10418$22_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_2$ls180.v:10418$22_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_2$ls180.v:10418$22_EN + attribute \src "ls180.v:0.0-0.0" + wire width 6 $memwr$\mem_2$ls180.v:10420$23_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_2$ls180.v:10420$23_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_2$ls180.v:10420$23_EN + attribute \src "ls180.v:0.0-0.0" + wire width 6 $memwr$\mem_2$ls180.v:10422$24_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_2$ls180.v:10422$24_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_2$ls180.v:10422$24_EN + attribute \src "ls180.v:0.0-0.0" + wire width 6 $memwr$\mem_3$ls180.v:10436$25_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_3$ls180.v:10436$25_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_3$ls180.v:10436$25_EN + attribute \src "ls180.v:0.0-0.0" + wire width 6 $memwr$\mem_3$ls180.v:10438$26_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_3$ls180.v:10438$26_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_3$ls180.v:10438$26_EN + attribute \src "ls180.v:0.0-0.0" + wire width 6 $memwr$\mem_3$ls180.v:10440$27_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_3$ls180.v:10440$27_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_3$ls180.v:10440$27_EN + attribute \src "ls180.v:0.0-0.0" + wire width 6 $memwr$\mem_3$ls180.v:10442$28_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_3$ls180.v:10442$28_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_3$ls180.v:10442$28_EN + attribute \src "ls180.v:0.0-0.0" + wire width 6 $memwr$\mem_3$ls180.v:10444$29_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_3$ls180.v:10444$29_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_3$ls180.v:10444$29_EN + attribute \src "ls180.v:0.0-0.0" + wire width 6 $memwr$\mem_3$ls180.v:10446$30_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_3$ls180.v:10446$30_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_3$ls180.v:10446$30_EN + attribute \src "ls180.v:0.0-0.0" + wire width 6 $memwr$\mem_3$ls180.v:10448$31_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_3$ls180.v:10448$31_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_3$ls180.v:10448$31_EN + attribute \src "ls180.v:0.0-0.0" + wire width 6 $memwr$\mem_3$ls180.v:10450$32_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_3$ls180.v:10450$32_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_3$ls180.v:10450$32_EN + attribute \src "ls180.v:0.0-0.0" + wire width 6 $memwr$\mem_4$ls180.v:10464$33_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_4$ls180.v:10464$33_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_4$ls180.v:10464$33_EN + attribute \src "ls180.v:0.0-0.0" + wire width 6 $memwr$\mem_4$ls180.v:10466$34_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_4$ls180.v:10466$34_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_4$ls180.v:10466$34_EN + attribute \src "ls180.v:0.0-0.0" + wire width 6 $memwr$\mem_4$ls180.v:10468$35_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_4$ls180.v:10468$35_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_4$ls180.v:10468$35_EN + attribute \src "ls180.v:0.0-0.0" + wire width 6 $memwr$\mem_4$ls180.v:10470$36_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_4$ls180.v:10470$36_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_4$ls180.v:10470$36_EN + attribute \src "ls180.v:0.0-0.0" + wire width 6 $memwr$\mem_4$ls180.v:10472$37_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_4$ls180.v:10472$37_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_4$ls180.v:10472$37_EN + attribute \src "ls180.v:0.0-0.0" + wire width 6 $memwr$\mem_4$ls180.v:10474$38_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_4$ls180.v:10474$38_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_4$ls180.v:10474$38_EN + attribute \src "ls180.v:0.0-0.0" + wire width 6 $memwr$\mem_4$ls180.v:10476$39_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_4$ls180.v:10476$39_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_4$ls180.v:10476$39_EN + attribute \src "ls180.v:0.0-0.0" + wire width 6 $memwr$\mem_4$ls180.v:10478$40_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_4$ls180.v:10478$40_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 64 $memwr$\mem_4$ls180.v:10478$40_EN + attribute \src "ls180.v:0.0-0.0" + wire width 3 $memwr$\storage$ls180.v:10492$41_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 25 $memwr$\storage$ls180.v:10492$41_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 25 $memwr$\storage$ls180.v:10492$41_EN + attribute \src "ls180.v:0.0-0.0" + wire width 3 $memwr$\storage_1$ls180.v:10506$42_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 25 $memwr$\storage_1$ls180.v:10506$42_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 25 $memwr$\storage_1$ls180.v:10506$42_EN + attribute \src "ls180.v:0.0-0.0" + wire width 3 $memwr$\storage_2$ls180.v:10520$43_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 25 $memwr$\storage_2$ls180.v:10520$43_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 25 $memwr$\storage_2$ls180.v:10520$43_EN + attribute \src "ls180.v:0.0-0.0" + wire width 3 $memwr$\storage_3$ls180.v:10534$44_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 25 $memwr$\storage_3$ls180.v:10534$44_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 25 $memwr$\storage_3$ls180.v:10534$44_EN + attribute \src "ls180.v:0.0-0.0" + wire width 4 $memwr$\storage_4$ls180.v:10549$45_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 10 $memwr$\storage_4$ls180.v:10549$45_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 10 $memwr$\storage_4$ls180.v:10549$45_EN + attribute \src "ls180.v:0.0-0.0" + wire width 4 $memwr$\storage_5$ls180.v:10566$46_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 10 $memwr$\storage_5$ls180.v:10566$46_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 10 $memwr$\storage_5$ls180.v:10566$46_EN + attribute \src "ls180.v:0.0-0.0" + wire width 5 $memwr$\storage_6$ls180.v:10582$47_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 10 $memwr$\storage_6$ls180.v:10582$47_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 10 $memwr$\storage_6$ls180.v:10582$47_EN + attribute \src "ls180.v:0.0-0.0" + wire width 5 $memwr$\storage_7$ls180.v:10596$48_ADDR + attribute \src "ls180.v:0.0-0.0" + wire width 10 $memwr$\storage_7$ls180.v:10596$48_DATA + attribute \src "ls180.v:0.0-0.0" + wire width 10 $memwr$\storage_7$ls180.v:10596$48_EN + attribute \src "ls180.v:3086.41-3086.71" + wire $ne$ls180.v:3086$108_Y + attribute \src "ls180.v:3303.70-3303.104" + wire $ne$ls180.v:3303$222_Y + attribute \src "ls180.v:3364.8-3364.142" + wire $ne$ls180.v:3364$241_Y + attribute \src "ls180.v:3396.75-3396.133" + wire $ne$ls180.v:3396$248_Y + attribute \src "ls180.v:3397.75-3397.133" + wire $ne$ls180.v:3397$249_Y + attribute \src "ls180.v:3521.8-3521.142" + wire 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"ls180.v:5518.10-5518.56" + wire $ne$ls180.v:5518$1128_Y + attribute \src "ls180.v:5623.51-5623.87" + wire $ne$ls180.v:5623$1142_Y + attribute \src "ls180.v:5624.51-5624.86" + wire $ne$ls180.v:5624$1143_Y + attribute \src "ls180.v:5843.51-5843.87" + wire $ne$ls180.v:5843$1173_Y + attribute \src "ls180.v:5844.51-5844.86" + wire $ne$ls180.v:5844$1174_Y + attribute \src "ls180.v:5875.79-5875.119" + wire $ne$ls180.v:5875$1177_Y + attribute \src "ls180.v:7760.7-7760.52" + wire $ne$ls180.v:7760$2601_Y + attribute \src "ls180.v:7826.9-7826.43" + wire $ne$ls180.v:7826$2627_Y + attribute \src "ls180.v:7862.8-7862.44" + wire $ne$ls180.v:7862$2634_Y + attribute \src "ls180.v:8800.9-8800.47" + wire $ne$ls180.v:8800$2849_Y + attribute \src "ls180.v:2890.33-2890.73" + wire $not$ls180.v:2890$50_Y + attribute \src "ls180.v:2929.48-2929.69" + wire $not$ls180.v:2929$55_Y + attribute \src "ls180.v:2930.48-2930.69" + wire $not$ls180.v:2930$56_Y + attribute \src "ls180.v:2950.33-2950.73" + wire $not$ls180.v:2950$61_Y + attribute \src "ls180.v:2989.48-2989.69" + wire $not$ls180.v:2989$66_Y + attribute \src "ls180.v:2990.48-2990.69" + wire $not$ls180.v:2990$67_Y + attribute \src "ls180.v:3010.36-3010.79" + wire $not$ls180.v:3010$72_Y + attribute \src "ls180.v:3049.27-3049.51" + wire $not$ls180.v:3049$77_Y + attribute \src "ls180.v:3050.27-3050.51" + wire $not$ls180.v:3050$78_Y + attribute \src "ls180.v:3252.34-3252.64" + wire $not$ls180.v:3252$214_Y + attribute \src "ls180.v:3253.31-3253.61" + wire $not$ls180.v:3253$215_Y + attribute \src "ls180.v:3254.32-3254.62" + wire $not$ls180.v:3254$216_Y + attribute \src "ls180.v:3255.32-3255.62" + wire $not$ls180.v:3255$217_Y + attribute \src "ls180.v:3297.33-3297.56" + wire $not$ls180.v:3297$220_Y + attribute \src "ls180.v:3398.58-3398.106" + wire $not$ls180.v:3398$250_Y + attribute \src "ls180.v:3452.9-3452.45" + wire $not$ls180.v:3452$255_Y + attribute \src "ls180.v:3555.58-3555.106" + wire $not$ls180.v:3555$280_Y + attribute \src "ls180.v:3609.9-3609.45" + wire $not$ls180.v:3609$285_Y + attribute \src "ls180.v:3712.58-3712.106" + wire $not$ls180.v:3712$310_Y + attribute \src "ls180.v:3766.9-3766.45" + wire $not$ls180.v:3766$315_Y + attribute \src "ls180.v:3869.58-3869.106" + wire $not$ls180.v:3869$340_Y + attribute \src "ls180.v:3923.9-3923.45" + wire $not$ls180.v:3923$345_Y + attribute \src "ls180.v:3965.149-3965.187" + wire $not$ls180.v:3965$348_Y + attribute \src "ls180.v:3965.193-3965.230" + wire $not$ls180.v:3965$350_Y + attribute \src "ls180.v:3966.149-3966.187" + wire $not$ls180.v:3966$354_Y + attribute \src "ls180.v:3966.193-3966.230" + wire $not$ls180.v:3966$356_Y + attribute \src "ls180.v:3982.43-3982.73" + wire width 2 $not$ls180.v:3982$384_Y + attribute \src "ls180.v:3985.205-3985.245" + wire $not$ls180.v:3985$387_Y + attribute \src "ls180.v:3985.251-3985.290" + wire $not$ls180.v:3985$389_Y + attribute \src "ls180.v:3985.159-3985.292" + wire $not$ls180.v:3985$391_Y + attribute \src "ls180.v:3986.205-3986.245" + wire $not$ls180.v:3986$400_Y + attribute \src "ls180.v:3986.251-3986.290" + wire $not$ls180.v:3986$402_Y + attribute \src "ls180.v:3986.159-3986.292" + wire $not$ls180.v:3986$404_Y + attribute \src "ls180.v:3987.205-3987.245" + wire $not$ls180.v:3987$413_Y + attribute \src "ls180.v:3987.251-3987.290" + wire $not$ls180.v:3987$415_Y + attribute \src "ls180.v:3987.159-3987.292" + wire $not$ls180.v:3987$417_Y + attribute \src "ls180.v:3988.205-3988.245" + wire $not$ls180.v:3988$426_Y + attribute \src "ls180.v:3988.251-3988.290" + wire $not$ls180.v:3988$428_Y + attribute \src "ls180.v:3988.159-3988.292" + wire $not$ls180.v:3988$430_Y + attribute \src "ls180.v:4015.71-4015.103" + wire $not$ls180.v:4015$441_Y + attribute \src "ls180.v:4018.205-4018.245" + wire $not$ls180.v:4018$445_Y + attribute \src "ls180.v:4018.251-4018.290" + wire $not$ls180.v:4018$447_Y + attribute \src "ls180.v:4018.159-4018.292" + wire $not$ls180.v:4018$449_Y + attribute \src "ls180.v:4019.205-4019.245" + wire $not$ls180.v:4019$458_Y + attribute \src "ls180.v:4019.251-4019.290" + wire $not$ls180.v:4019$460_Y + attribute \src "ls180.v:4019.159-4019.292" + wire $not$ls180.v:4019$462_Y + attribute \src "ls180.v:4020.205-4020.245" + wire $not$ls180.v:4020$471_Y + attribute \src "ls180.v:4020.251-4020.290" + wire $not$ls180.v:4020$473_Y + attribute \src "ls180.v:4020.159-4020.292" + wire $not$ls180.v:4020$475_Y + attribute \src "ls180.v:4021.205-4021.245" + wire $not$ls180.v:4021$484_Y + attribute \src "ls180.v:4021.251-4021.290" + wire $not$ls180.v:4021$486_Y + attribute \src "ls180.v:4021.159-4021.292" + wire $not$ls180.v:4021$488_Y + attribute \src "ls180.v:4084.71-4084.103" + wire $not$ls180.v:4084$527_Y + attribute \src "ls180.v:4105.112-4105.150" + wire $not$ls180.v:4105$530_Y + attribute \src "ls180.v:4105.156-4105.193" + wire $not$ls180.v:4105$532_Y + attribute \src "ls180.v:4105.68-4105.195" + wire $not$ls180.v:4105$534_Y + attribute \src "ls180.v:4113.11-4113.38" + wire $not$ls180.v:4113$537_Y + attribute \src "ls180.v:4143.112-4143.150" + wire $not$ls180.v:4143$539_Y + attribute \src "ls180.v:4143.156-4143.193" + wire $not$ls180.v:4143$541_Y + attribute \src "ls180.v:4143.68-4143.195" + wire $not$ls180.v:4143$543_Y + attribute \src "ls180.v:4151.11-4151.37" + wire $not$ls180.v:4151$546_Y + attribute \src "ls180.v:4161.87-4161.331" + wire $not$ls180.v:4161$558_Y + attribute \src "ls180.v:4162.35-4162.68" + wire $not$ls180.v:4162$561_Y + attribute \src "ls180.v:4162.73-4162.105" + wire $not$ls180.v:4162$562_Y + attribute \src "ls180.v:4166.87-4166.331" + wire $not$ls180.v:4166$574_Y + attribute \src "ls180.v:4167.35-4167.68" + wire $not$ls180.v:4167$577_Y + attribute \src "ls180.v:4167.73-4167.105" + wire $not$ls180.v:4167$578_Y + attribute \src "ls180.v:4171.87-4171.331" + wire $not$ls180.v:4171$590_Y + attribute \src "ls180.v:4172.35-4172.68" + wire $not$ls180.v:4172$593_Y + attribute \src "ls180.v:4172.73-4172.105" + wire $not$ls180.v:4172$594_Y + attribute \src "ls180.v:4176.87-4176.331" + wire $not$ls180.v:4176$606_Y + attribute \src "ls180.v:4177.35-4177.68" + wire $not$ls180.v:4177$609_Y + attribute \src "ls180.v:4177.73-4177.105" + wire $not$ls180.v:4177$610_Y + attribute \src "ls180.v:4181.128-4181.372" + wire $not$ls180.v:4181$623_Y + attribute \src "ls180.v:4181.502-4181.746" + wire $not$ls180.v:4181$639_Y + attribute \src "ls180.v:4181.876-4181.1120" + wire $not$ls180.v:4181$655_Y + attribute \src "ls180.v:4181.1250-4181.1494" + wire $not$ls180.v:4181$671_Y + attribute \src "ls180.v:4203.32-4203.50" + wire $not$ls180.v:4203$677_Y + attribute \src "ls180.v:4242.30-4242.50" + wire $not$ls180.v:4242$682_Y + attribute \src "ls180.v:4243.30-4243.50" + wire $not$ls180.v:4243$683_Y + attribute \src "ls180.v:4268.27-4268.48" + wire $not$ls180.v:4268$689_Y + attribute \src "ls180.v:4269.30-4269.50" + wire $not$ls180.v:4269$690_Y + attribute \src "ls180.v:4270.80-4270.98" + wire $not$ls180.v:4270$692_Y + attribute \src "ls180.v:4271.107-4271.127" + wire $not$ls180.v:4271$696_Y + attribute \src "ls180.v:4272.78-4272.103" + wire $not$ls180.v:4272$699_Y + attribute \src "ls180.v:4273.91-4273.111" + wire $not$ls180.v:4273$702_Y + attribute \src "ls180.v:4289.35-4289.64" + wire $not$ls180.v:4289$711_Y + attribute \src "ls180.v:4290.36-4290.67" + wire $not$ls180.v:4290$712_Y + attribute \src "ls180.v:4296.32-4296.61" + wire $not$ls180.v:4296$713_Y + attribute \src "ls180.v:4302.36-4302.67" + wire $not$ls180.v:4302$714_Y + attribute \src "ls180.v:4303.35-4303.64" + wire $not$ls180.v:4303$715_Y + attribute \src "ls180.v:4306.32-4306.63" + wire $not$ls180.v:4306$718_Y + attribute \src "ls180.v:4344.81-4344.108" + wire $not$ls180.v:4344$728_Y + attribute \src "ls180.v:4374.81-4374.108" + wire $not$ls180.v:4374$739_Y + attribute \src "ls180.v:4585.60-4585.85" + wire $not$ls180.v:4585$790_Y + attribute \src "ls180.v:4726.54-4726.96" + wire $not$ls180.v:4726$804_Y + attribute \src "ls180.v:4729.48-4729.86" + wire $not$ls180.v:4729$807_Y + attribute \src "ls180.v:4853.55-4853.98" + wire $not$ls180.v:4853$825_Y + attribute \src "ls180.v:4856.49-4856.88" + wire $not$ls180.v:4856$828_Y + attribute \src "ls180.v:4906.30-4906.58" + wire $not$ls180.v:4906$834_Y + attribute \src "ls180.v:4987.56-4987.100" + wire $not$ls180.v:4987$840_Y + attribute \src "ls180.v:4990.50-4990.90" + wire $not$ls180.v:4990$843_Y + attribute \src "ls180.v:5106.42-5106.74" + wire $not$ls180.v:5106$859_Y + attribute \src "ls180.v:5630.50-5630.88" + wire $not$ls180.v:5630$1144_Y + attribute \src "ls180.v:5642.52-5642.102" + wire $not$ls180.v:5642$1147_Y + attribute \src "ls180.v:5701.38-5701.74" + wire $not$ls180.v:5701$1154_Y + attribute \src "ls180.v:6027.69-6027.88" + wire $not$ls180.v:6027$1239_Y + attribute \src "ls180.v:6044.63-6044.94" + wire $not$ls180.v:6044$1284_Y + attribute \src "ls180.v:6047.65-6047.96" + wire $not$ls180.v:6047$1291_Y + attribute \src "ls180.v:6050.65-6050.96" + wire $not$ls180.v:6050$1298_Y + attribute \src "ls180.v:6053.65-6053.96" + wire $not$ls180.v:6053$1305_Y + attribute \src "ls180.v:6056.65-6056.96" + wire $not$ls180.v:6056$1312_Y + attribute \src "ls180.v:6059.68-6059.99" + wire $not$ls180.v:6059$1319_Y + attribute \src "ls180.v:6062.68-6062.99" + wire $not$ls180.v:6062$1326_Y + attribute \src "ls180.v:6065.68-6065.99" + wire $not$ls180.v:6065$1333_Y + attribute \src "ls180.v:6068.68-6068.99" + wire $not$ls180.v:6068$1340_Y + attribute \src "ls180.v:6082.60-6082.91" + wire $not$ls180.v:6082$1348_Y + attribute \src "ls180.v:6085.60-6085.91" + wire $not$ls180.v:6085$1355_Y + attribute \src "ls180.v:6088.60-6088.91" + wire $not$ls180.v:6088$1362_Y + attribute \src "ls180.v:6091.60-6091.91" + wire $not$ls180.v:6091$1369_Y + attribute \src "ls180.v:6094.61-6094.92" + wire $not$ls180.v:6094$1376_Y + attribute \src "ls180.v:6097.61-6097.92" + wire $not$ls180.v:6097$1383_Y + attribute \src "ls180.v:6108.59-6108.90" + wire $not$ls180.v:6108$1391_Y + attribute \src "ls180.v:6111.58-6111.89" + wire $not$ls180.v:6111$1398_Y + attribute \src "ls180.v:6122.64-6122.95" + wire $not$ls180.v:6122$1406_Y + attribute \src "ls180.v:6125.63-6125.94" + wire $not$ls180.v:6125$1413_Y + attribute \src "ls180.v:6128.63-6128.94" + wire $not$ls180.v:6128$1420_Y + attribute \src "ls180.v:6131.63-6131.94" + wire $not$ls180.v:6131$1427_Y + attribute \src "ls180.v:6134.63-6134.94" + wire $not$ls180.v:6134$1434_Y + attribute \src "ls180.v:6137.64-6137.95" + wire $not$ls180.v:6137$1441_Y + attribute \src "ls180.v:6140.64-6140.95" + wire $not$ls180.v:6140$1448_Y + attribute \src "ls180.v:6143.64-6143.95" + wire $not$ls180.v:6143$1455_Y + attribute \src "ls180.v:6146.64-6146.95" + wire $not$ls180.v:6146$1462_Y + attribute \src "ls180.v:6159.64-6159.95" + wire $not$ls180.v:6159$1470_Y + attribute \src "ls180.v:6162.63-6162.94" + wire $not$ls180.v:6162$1477_Y + attribute \src "ls180.v:6165.63-6165.94" + wire $not$ls180.v:6165$1484_Y + attribute \src "ls180.v:6168.63-6168.94" + wire $not$ls180.v:6168$1491_Y + attribute \src "ls180.v:6171.63-6171.94" + wire $not$ls180.v:6171$1498_Y + attribute \src "ls180.v:6174.64-6174.95" + wire $not$ls180.v:6174$1505_Y + attribute \src "ls180.v:6177.64-6177.95" + wire $not$ls180.v:6177$1512_Y + attribute \src "ls180.v:6180.64-6180.95" + wire $not$ls180.v:6180$1519_Y + attribute \src "ls180.v:6183.64-6183.95" + wire $not$ls180.v:6183$1526_Y + attribute \src "ls180.v:6196.66-6196.97" + wire $not$ls180.v:6196$1534_Y + attribute \src "ls180.v:6199.66-6199.97" + wire $not$ls180.v:6199$1541_Y + attribute \src "ls180.v:6202.66-6202.97" + wire $not$ls180.v:6202$1548_Y + attribute \src "ls180.v:6205.66-6205.97" + wire $not$ls180.v:6205$1555_Y + attribute \src "ls180.v:6208.66-6208.97" + wire $not$ls180.v:6208$1562_Y + attribute \src "ls180.v:6211.66-6211.97" + wire $not$ls180.v:6211$1569_Y + attribute \src "ls180.v:6214.66-6214.97" + wire $not$ls180.v:6214$1576_Y + attribute \src "ls180.v:6217.66-6217.97" + wire $not$ls180.v:6217$1583_Y + attribute \src "ls180.v:6220.68-6220.99" + wire $not$ls180.v:6220$1590_Y + attribute \src "ls180.v:6223.68-6223.99" + wire $not$ls180.v:6223$1597_Y + attribute \src "ls180.v:6226.68-6226.99" + wire $not$ls180.v:6226$1604_Y + attribute \src "ls180.v:6229.68-6229.99" + wire $not$ls180.v:6229$1611_Y + attribute \src "ls180.v:6232.68-6232.99" + wire $not$ls180.v:6232$1618_Y + attribute \src "ls180.v:6235.65-6235.96" + wire $not$ls180.v:6235$1625_Y + attribute \src "ls180.v:6238.66-6238.97" + wire $not$ls180.v:6238$1632_Y + attribute \src "ls180.v:6258.70-6258.101" + wire $not$ls180.v:6258$1640_Y + attribute \src "ls180.v:6261.70-6261.101" + wire $not$ls180.v:6261$1647_Y + attribute \src "ls180.v:6264.70-6264.101" + wire $not$ls180.v:6264$1654_Y + attribute \src "ls180.v:6267.70-6267.101" + wire $not$ls180.v:6267$1661_Y + attribute \src "ls180.v:6270.69-6270.100" + wire $not$ls180.v:6270$1668_Y + attribute \src "ls180.v:6273.69-6273.100" + wire $not$ls180.v:6273$1675_Y + attribute \src "ls180.v:6276.69-6276.100" + wire $not$ls180.v:6276$1682_Y + attribute \src "ls180.v:6279.69-6279.100" + wire $not$ls180.v:6279$1689_Y + attribute \src "ls180.v:6282.60-6282.91" + wire $not$ls180.v:6282$1696_Y + attribute \src "ls180.v:6285.71-6285.102" + wire $not$ls180.v:6285$1703_Y + attribute \src "ls180.v:6288.71-6288.102" + wire $not$ls180.v:6288$1710_Y + attribute \src "ls180.v:6291.71-6291.102" + wire $not$ls180.v:6291$1717_Y + attribute \src "ls180.v:6294.71-6294.102" + wire $not$ls180.v:6294$1724_Y + attribute \src "ls180.v:6297.71-6297.102" + wire $not$ls180.v:6297$1731_Y + attribute \src "ls180.v:6300.71-6300.102" + wire $not$ls180.v:6300$1738_Y + attribute \src "ls180.v:6303.70-6303.101" + wire $not$ls180.v:6303$1745_Y + attribute \src "ls180.v:6306.70-6306.101" + wire $not$ls180.v:6306$1752_Y + attribute \src "ls180.v:6309.70-6309.101" + wire $not$ls180.v:6309$1759_Y + attribute \src "ls180.v:6312.70-6312.101" + wire $not$ls180.v:6312$1766_Y + attribute \src "ls180.v:6315.70-6315.101" + wire $not$ls180.v:6315$1773_Y + attribute \src "ls180.v:6318.70-6318.101" + wire $not$ls180.v:6318$1780_Y + attribute \src "ls180.v:6321.70-6321.101" + wire $not$ls180.v:6321$1787_Y + attribute \src "ls180.v:6324.70-6324.101" + wire $not$ls180.v:6324$1794_Y + attribute \src "ls180.v:6327.70-6327.101" + wire $not$ls180.v:6327$1801_Y + attribute \src "ls180.v:6330.70-6330.101" + wire $not$ls180.v:6330$1808_Y + attribute \src "ls180.v:6333.66-6333.97" + wire $not$ls180.v:6333$1815_Y + attribute \src "ls180.v:6336.67-6336.98" + wire $not$ls180.v:6336$1822_Y + attribute \src "ls180.v:6339.70-6339.101" + wire $not$ls180.v:6339$1829_Y + attribute \src "ls180.v:6342.70-6342.101" + wire $not$ls180.v:6342$1836_Y + attribute \src "ls180.v:6345.69-6345.100" + wire $not$ls180.v:6345$1843_Y + attribute \src "ls180.v:6348.69-6348.100" + wire $not$ls180.v:6348$1850_Y + attribute \src "ls180.v:6351.69-6351.100" + wire $not$ls180.v:6351$1857_Y + attribute \src "ls180.v:6354.69-6354.100" + wire $not$ls180.v:6354$1864_Y + attribute \src "ls180.v:6393.66-6393.97" + wire $not$ls180.v:6393$1872_Y + attribute \src "ls180.v:6396.66-6396.97" + wire $not$ls180.v:6396$1879_Y + attribute \src "ls180.v:6399.66-6399.97" + wire $not$ls180.v:6399$1886_Y + attribute \src "ls180.v:6402.66-6402.97" + wire $not$ls180.v:6402$1893_Y + attribute \src "ls180.v:6405.66-6405.97" + wire $not$ls180.v:6405$1900_Y + attribute \src "ls180.v:6408.66-6408.97" + wire $not$ls180.v:6408$1907_Y + attribute \src "ls180.v:6411.66-6411.97" + wire $not$ls180.v:6411$1914_Y + attribute \src "ls180.v:6414.66-6414.97" + wire $not$ls180.v:6414$1921_Y + attribute \src "ls180.v:6417.68-6417.99" + wire $not$ls180.v:6417$1928_Y + attribute \src "ls180.v:6420.68-6420.99" + wire $not$ls180.v:6420$1935_Y + attribute \src "ls180.v:6423.68-6423.99" + wire $not$ls180.v:6423$1942_Y + attribute \src "ls180.v:6426.68-6426.99" + wire $not$ls180.v:6426$1949_Y + attribute \src "ls180.v:6429.68-6429.99" + wire $not$ls180.v:6429$1956_Y + attribute \src "ls180.v:6432.65-6432.96" + wire $not$ls180.v:6432$1963_Y + attribute \src "ls180.v:6435.66-6435.97" + wire $not$ls180.v:6435$1970_Y + attribute \src "ls180.v:6438.68-6438.99" + wire $not$ls180.v:6438$1977_Y + attribute \src "ls180.v:6441.68-6441.99" + wire $not$ls180.v:6441$1984_Y + attribute \src "ls180.v:6444.68-6444.99" + wire $not$ls180.v:6444$1991_Y + attribute \src "ls180.v:6447.68-6447.99" + wire $not$ls180.v:6447$1998_Y + attribute \src "ls180.v:6472.68-6472.99" + wire $not$ls180.v:6472$2006_Y + attribute \src "ls180.v:6475.73-6475.104" + wire $not$ls180.v:6475$2013_Y + attribute \src "ls180.v:6478.73-6478.104" + wire $not$ls180.v:6478$2020_Y + attribute \src "ls180.v:6481.66-6481.97" + wire $not$ls180.v:6481$2027_Y + attribute \src "ls180.v:6489.70-6489.101" + wire $not$ls180.v:6489$2035_Y + attribute \src "ls180.v:6492.74-6492.105" + wire $not$ls180.v:6492$2042_Y + attribute \src "ls180.v:6495.64-6495.95" + wire $not$ls180.v:6495$2049_Y + attribute \src "ls180.v:6498.74-6498.105" + wire $not$ls180.v:6498$2056_Y + attribute \src "ls180.v:6501.74-6501.105" + wire $not$ls180.v:6501$2063_Y + attribute \src "ls180.v:6504.75-6504.106" + wire $not$ls180.v:6504$2070_Y + attribute \src "ls180.v:6507.73-6507.104" + wire $not$ls180.v:6507$2077_Y + attribute \src "ls180.v:6510.73-6510.104" + wire $not$ls180.v:6510$2084_Y + attribute \src "ls180.v:6513.73-6513.104" + wire $not$ls180.v:6513$2091_Y + attribute \src "ls180.v:6516.73-6516.104" + wire $not$ls180.v:6516$2098_Y + attribute \src "ls180.v:6534.67-6534.99" + wire $not$ls180.v:6534$2106_Y + attribute \src "ls180.v:6537.67-6537.99" + wire $not$ls180.v:6537$2113_Y + attribute \src "ls180.v:6540.65-6540.97" + wire $not$ls180.v:6540$2120_Y + attribute \src "ls180.v:6543.64-6543.96" + wire $not$ls180.v:6543$2127_Y + attribute \src "ls180.v:6546.63-6546.95" + wire $not$ls180.v:6546$2134_Y + attribute \src "ls180.v:6549.62-6549.94" + wire $not$ls180.v:6549$2141_Y + attribute \src "ls180.v:6552.68-6552.100" + wire $not$ls180.v:6552$2148_Y + attribute \src "ls180.v:6574.67-6574.99" + wire $not$ls180.v:6574$2157_Y + attribute \src "ls180.v:6577.67-6577.99" + wire $not$ls180.v:6577$2164_Y + attribute \src "ls180.v:6580.65-6580.97" + wire $not$ls180.v:6580$2171_Y + attribute \src "ls180.v:6583.64-6583.96" + wire $not$ls180.v:6583$2178_Y + attribute \src "ls180.v:6586.63-6586.95" + wire $not$ls180.v:6586$2185_Y + attribute \src "ls180.v:6589.62-6589.94" + wire $not$ls180.v:6589$2192_Y + attribute \src "ls180.v:6592.68-6592.100" + wire $not$ls180.v:6592$2199_Y + attribute \src "ls180.v:6595.71-6595.103" + wire $not$ls180.v:6595$2206_Y + attribute \src "ls180.v:6598.71-6598.103" + wire $not$ls180.v:6598$2213_Y + attribute \src "ls180.v:6622.64-6622.96" + wire $not$ls180.v:6622$2222_Y + attribute \src "ls180.v:6625.64-6625.96" + wire $not$ls180.v:6625$2229_Y + attribute \src "ls180.v:6628.64-6628.96" + wire $not$ls180.v:6628$2236_Y + attribute \src "ls180.v:6631.64-6631.96" + wire $not$ls180.v:6631$2243_Y + attribute \src "ls180.v:6634.66-6634.98" + wire $not$ls180.v:6634$2250_Y + attribute \src "ls180.v:6637.66-6637.98" + wire $not$ls180.v:6637$2257_Y + attribute \src "ls180.v:6640.66-6640.98" + wire $not$ls180.v:6640$2264_Y + attribute \src "ls180.v:6643.66-6643.98" + wire $not$ls180.v:6643$2271_Y + attribute \src "ls180.v:6646.62-6646.94" + wire $not$ls180.v:6646$2278_Y + attribute \src "ls180.v:6649.72-6649.104" + wire $not$ls180.v:6649$2285_Y + attribute \src "ls180.v:6652.65-6652.97" + wire $not$ls180.v:6652$2292_Y + attribute \src "ls180.v:6655.65-6655.97" + wire $not$ls180.v:6655$2299_Y + attribute \src "ls180.v:6658.65-6658.97" + wire $not$ls180.v:6658$2306_Y + attribute \src "ls180.v:6661.65-6661.97" + wire $not$ls180.v:6661$2313_Y + attribute \src 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$xor$ls180.v:5113$871_Y + attribute \src "ls180.v:5114.353-5114.425" + wire $xor$ls180.v:5114$872_Y + attribute \src "ls180.v:5114.200-5114.272" + wire $xor$ls180.v:5114$873_Y + attribute \src "ls180.v:5114.160-5114.273" + wire $xor$ls180.v:5114$874_Y + attribute \src "ls180.v:5115.353-5115.425" + wire $xor$ls180.v:5115$875_Y + attribute \src "ls180.v:5115.200-5115.272" + wire $xor$ls180.v:5115$876_Y + attribute \src "ls180.v:5115.160-5115.273" + wire $xor$ls180.v:5115$877_Y + attribute \src "ls180.v:5116.353-5116.425" + wire $xor$ls180.v:5116$878_Y + attribute \src "ls180.v:5116.200-5116.272" + wire $xor$ls180.v:5116$879_Y + attribute \src "ls180.v:5116.160-5116.273" + wire $xor$ls180.v:5116$880_Y + attribute \src "ls180.v:5117.353-5117.425" + wire $xor$ls180.v:5117$881_Y + attribute \src "ls180.v:5117.200-5117.272" + wire $xor$ls180.v:5117$882_Y + attribute \src "ls180.v:5117.160-5117.273" + wire $xor$ls180.v:5117$883_Y + attribute \src "ls180.v:5118.353-5118.425" + wire $xor$ls180.v:5118$884_Y + attribute \src "ls180.v:5118.200-5118.272" + wire $xor$ls180.v:5118$885_Y + attribute \src "ls180.v:5118.160-5118.273" + wire $xor$ls180.v:5118$886_Y + attribute \src "ls180.v:5119.354-5119.426" + wire $xor$ls180.v:5119$887_Y + attribute \src "ls180.v:5119.201-5119.273" + wire $xor$ls180.v:5119$888_Y + attribute \src "ls180.v:5119.161-5119.274" + wire $xor$ls180.v:5119$889_Y + attribute \src "ls180.v:5120.361-5120.434" + wire $xor$ls180.v:5120$890_Y + attribute \src "ls180.v:5120.205-5120.278" + wire $xor$ls180.v:5120$891_Y + attribute \src "ls180.v:5120.164-5120.279" + wire $xor$ls180.v:5120$892_Y + attribute \src "ls180.v:5121.361-5121.434" + wire $xor$ls180.v:5121$893_Y + attribute \src "ls180.v:5121.205-5121.278" + wire $xor$ls180.v:5121$894_Y + attribute \src "ls180.v:5121.164-5121.279" + wire $xor$ls180.v:5121$895_Y + attribute \src "ls180.v:5122.361-5122.434" + wire $xor$ls180.v:5122$896_Y + attribute \src "ls180.v:5122.205-5122.278" + wire $xor$ls180.v:5122$897_Y + attribute \src "ls180.v:5122.164-5122.279" + wire $xor$ls180.v:5122$898_Y + attribute \src "ls180.v:5123.361-5123.434" + wire $xor$ls180.v:5123$899_Y + attribute \src "ls180.v:5123.205-5123.278" + wire $xor$ls180.v:5123$900_Y + attribute \src "ls180.v:5123.164-5123.279" + wire $xor$ls180.v:5123$901_Y + attribute \src "ls180.v:5124.361-5124.434" + wire $xor$ls180.v:5124$902_Y + attribute \src "ls180.v:5124.205-5124.278" + wire $xor$ls180.v:5124$903_Y + attribute \src "ls180.v:5124.164-5124.279" + wire $xor$ls180.v:5124$904_Y + attribute \src "ls180.v:5125.361-5125.434" + wire $xor$ls180.v:5125$905_Y + attribute \src "ls180.v:5125.205-5125.278" + wire $xor$ls180.v:5125$906_Y + attribute \src "ls180.v:5125.164-5125.279" + wire $xor$ls180.v:5125$907_Y + attribute \src "ls180.v:5126.361-5126.434" + wire $xor$ls180.v:5126$908_Y + attribute \src "ls180.v:5126.205-5126.278" + wire $xor$ls180.v:5126$909_Y + attribute \src "ls180.v:5126.164-5126.279" + wire $xor$ls180.v:5126$910_Y + attribute \src "ls180.v:5127.361-5127.434" + wire $xor$ls180.v:5127$911_Y + attribute \src "ls180.v:5127.205-5127.278" + wire $xor$ls180.v:5127$912_Y + attribute \src "ls180.v:5127.164-5127.279" + wire $xor$ls180.v:5127$913_Y + attribute \src "ls180.v:5128.361-5128.434" + wire $xor$ls180.v:5128$914_Y + attribute \src "ls180.v:5128.205-5128.278" + wire $xor$ls180.v:5128$915_Y + attribute \src "ls180.v:5128.164-5128.279" + wire $xor$ls180.v:5128$916_Y + attribute \src "ls180.v:5129.361-5129.434" + wire $xor$ls180.v:5129$917_Y + attribute \src "ls180.v:5129.205-5129.278" + wire $xor$ls180.v:5129$918_Y + attribute \src "ls180.v:5129.164-5129.279" + wire $xor$ls180.v:5129$919_Y + attribute \src "ls180.v:5130.361-5130.434" + wire $xor$ls180.v:5130$920_Y + attribute \src "ls180.v:5130.205-5130.278" + wire $xor$ls180.v:5130$921_Y + attribute \src "ls180.v:5130.164-5130.279" + wire $xor$ls180.v:5130$922_Y + attribute \src "ls180.v:5131.361-5131.434" + wire $xor$ls180.v:5131$923_Y + attribute \src "ls180.v:5131.205-5131.278" + wire $xor$ls180.v:5131$924_Y + attribute \src "ls180.v:5131.164-5131.279" + wire $xor$ls180.v:5131$925_Y + attribute \src "ls180.v:5132.361-5132.434" + wire $xor$ls180.v:5132$926_Y + attribute \src "ls180.v:5132.205-5132.278" + wire $xor$ls180.v:5132$927_Y + attribute \src "ls180.v:5132.164-5132.279" + wire $xor$ls180.v:5132$928_Y + attribute \src "ls180.v:5133.361-5133.434" + wire $xor$ls180.v:5133$929_Y + attribute \src "ls180.v:5133.205-5133.278" + wire $xor$ls180.v:5133$930_Y + attribute \src "ls180.v:5133.164-5133.279" + wire $xor$ls180.v:5133$931_Y + attribute \src "ls180.v:5134.361-5134.434" + wire $xor$ls180.v:5134$932_Y + attribute \src "ls180.v:5134.205-5134.278" + wire $xor$ls180.v:5134$933_Y + attribute \src "ls180.v:5134.164-5134.279" + wire $xor$ls180.v:5134$934_Y + attribute \src "ls180.v:5135.361-5135.434" + wire $xor$ls180.v:5135$935_Y + attribute \src "ls180.v:5135.205-5135.278" + wire $xor$ls180.v:5135$936_Y + attribute \src "ls180.v:5135.164-5135.279" + wire $xor$ls180.v:5135$937_Y + attribute \src "ls180.v:5136.361-5136.434" + wire $xor$ls180.v:5136$938_Y + attribute \src "ls180.v:5136.205-5136.278" + wire $xor$ls180.v:5136$939_Y + attribute \src "ls180.v:5136.164-5136.279" + wire $xor$ls180.v:5136$940_Y + attribute \src "ls180.v:5137.361-5137.434" + wire $xor$ls180.v:5137$941_Y + attribute \src "ls180.v:5137.205-5137.278" + wire $xor$ls180.v:5137$942_Y + attribute \src "ls180.v:5137.164-5137.279" + wire $xor$ls180.v:5137$943_Y + attribute \src "ls180.v:5138.361-5138.434" + wire $xor$ls180.v:5138$944_Y + attribute \src "ls180.v:5138.205-5138.278" + wire $xor$ls180.v:5138$945_Y + attribute \src "ls180.v:5138.164-5138.279" + wire $xor$ls180.v:5138$946_Y + attribute \src "ls180.v:5139.361-5139.434" + wire $xor$ls180.v:5139$947_Y + attribute \src "ls180.v:5139.205-5139.278" + wire $xor$ls180.v:5139$948_Y + attribute \src "ls180.v:5139.164-5139.279" + wire $xor$ls180.v:5139$949_Y + attribute \src "ls180.v:5140.360-5140.432" + wire $xor$ls180.v:5140$950_Y + attribute \src "ls180.v:5140.205-5140.277" + wire $xor$ls180.v:5140$951_Y + attribute \src "ls180.v:5140.164-5140.278" + wire $xor$ls180.v:5140$952_Y + attribute \src "ls180.v:5141.360-5141.432" + wire $xor$ls180.v:5141$953_Y + attribute \src "ls180.v:5141.205-5141.277" + wire $xor$ls180.v:5141$954_Y + attribute \src "ls180.v:5141.164-5141.278" + wire $xor$ls180.v:5141$955_Y + attribute \src "ls180.v:5142.360-5142.432" + wire $xor$ls180.v:5142$956_Y + attribute \src "ls180.v:5142.205-5142.277" + wire $xor$ls180.v:5142$957_Y + attribute \src "ls180.v:5142.164-5142.278" + wire $xor$ls180.v:5142$958_Y + attribute \src "ls180.v:5143.360-5143.432" + wire $xor$ls180.v:5143$959_Y + attribute \src "ls180.v:5143.205-5143.277" + wire $xor$ls180.v:5143$960_Y + attribute \src "ls180.v:5143.164-5143.278" + wire $xor$ls180.v:5143$961_Y + attribute \src "ls180.v:5144.360-5144.432" + wire $xor$ls180.v:5144$962_Y + attribute \src "ls180.v:5144.205-5144.277" + wire $xor$ls180.v:5144$963_Y + attribute \src "ls180.v:5144.164-5144.278" + wire $xor$ls180.v:5144$964_Y + attribute \src "ls180.v:5145.360-5145.432" + wire $xor$ls180.v:5145$965_Y + attribute \src "ls180.v:5145.205-5145.277" + wire $xor$ls180.v:5145$966_Y + attribute \src "ls180.v:5145.164-5145.278" + wire $xor$ls180.v:5145$967_Y + attribute \src "ls180.v:5146.360-5146.432" + wire $xor$ls180.v:5146$968_Y + attribute \src "ls180.v:5146.205-5146.277" + wire $xor$ls180.v:5146$969_Y + attribute \src "ls180.v:5146.164-5146.278" + wire $xor$ls180.v:5146$970_Y + attribute \src "ls180.v:5147.360-5147.432" + wire $xor$ls180.v:5147$971_Y + attribute \src "ls180.v:5147.205-5147.277" + wire $xor$ls180.v:5147$972_Y + attribute \src "ls180.v:5147.164-5147.278" + wire $xor$ls180.v:5147$973_Y + attribute \src "ls180.v:5148.360-5148.432" + wire $xor$ls180.v:5148$974_Y + attribute \src "ls180.v:5148.205-5148.277" + wire $xor$ls180.v:5148$975_Y + attribute \src "ls180.v:5148.164-5148.278" + wire $xor$ls180.v:5148$976_Y + attribute \src "ls180.v:5149.360-5149.432" + wire $xor$ls180.v:5149$977_Y + attribute \src "ls180.v:5149.205-5149.277" + wire $xor$ls180.v:5149$978_Y + attribute \src "ls180.v:5149.164-5149.278" + wire $xor$ls180.v:5149$979_Y + attribute \src "ls180.v:5170.899-5170.983" + wire $xor$ls180.v:5170$993_Y + attribute \src "ls180.v:5170.634-5170.718" + wire $xor$ls180.v:5170$994_Y + attribute \src "ls180.v:5170.588-5170.719" + wire $xor$ls180.v:5170$995_Y + attribute \src "ls180.v:5170.234-5170.318" + wire $xor$ls180.v:5170$996_Y + attribute \src "ls180.v:5170.187-5170.319" + wire $xor$ls180.v:5170$997_Y + attribute \src "ls180.v:5171.588-5171.719" + wire $xor$ls180.v:5171$1000_Y + attribute \src "ls180.v:5171.234-5171.318" + wire $xor$ls180.v:5171$1001_Y + attribute \src "ls180.v:5171.187-5171.319" + wire $xor$ls180.v:5171$1002_Y + attribute \src "ls180.v:5171.899-5171.983" + wire $xor$ls180.v:5171$998_Y + attribute \src "ls180.v:5171.634-5171.718" + wire $xor$ls180.v:5171$999_Y + attribute \src "ls180.v:5180.899-5180.983" + wire $xor$ls180.v:5180$1004_Y + attribute \src "ls180.v:5180.634-5180.718" + wire $xor$ls180.v:5180$1005_Y + attribute \src "ls180.v:5180.588-5180.719" + wire $xor$ls180.v:5180$1006_Y + attribute \src "ls180.v:5180.234-5180.318" + wire $xor$ls180.v:5180$1007_Y + attribute \src "ls180.v:5180.187-5180.319" + wire $xor$ls180.v:5180$1008_Y + attribute \src "ls180.v:5181.899-5181.983" + wire $xor$ls180.v:5181$1009_Y + attribute \src "ls180.v:5181.634-5181.718" + wire $xor$ls180.v:5181$1010_Y + attribute \src "ls180.v:5181.588-5181.719" + wire $xor$ls180.v:5181$1011_Y + attribute \src "ls180.v:5181.234-5181.318" + wire $xor$ls180.v:5181$1012_Y + attribute \src "ls180.v:5181.187-5181.319" + wire $xor$ls180.v:5181$1013_Y + attribute \src "ls180.v:5190.899-5190.983" + wire $xor$ls180.v:5190$1015_Y + attribute \src "ls180.v:5190.634-5190.718" + wire $xor$ls180.v:5190$1016_Y + attribute \src "ls180.v:5190.588-5190.719" + wire $xor$ls180.v:5190$1017_Y + attribute \src "ls180.v:5190.234-5190.318" + wire $xor$ls180.v:5190$1018_Y + attribute \src "ls180.v:5190.187-5190.319" + wire $xor$ls180.v:5190$1019_Y + attribute \src "ls180.v:5191.899-5191.983" + wire $xor$ls180.v:5191$1020_Y + attribute \src "ls180.v:5191.634-5191.718" + wire $xor$ls180.v:5191$1021_Y + attribute \src "ls180.v:5191.588-5191.719" + wire $xor$ls180.v:5191$1022_Y + attribute \src "ls180.v:5191.234-5191.318" + wire $xor$ls180.v:5191$1023_Y + attribute \src "ls180.v:5191.187-5191.319" + wire $xor$ls180.v:5191$1024_Y + attribute \src "ls180.v:5200.899-5200.983" + wire $xor$ls180.v:5200$1026_Y + attribute \src "ls180.v:5200.634-5200.718" + wire $xor$ls180.v:5200$1027_Y + attribute \src "ls180.v:5200.588-5200.719" + wire $xor$ls180.v:5200$1028_Y + attribute \src "ls180.v:5200.234-5200.318" + wire $xor$ls180.v:5200$1029_Y + attribute \src "ls180.v:5200.187-5200.319" + wire $xor$ls180.v:5200$1030_Y + attribute \src "ls180.v:5201.899-5201.983" + wire $xor$ls180.v:5201$1031_Y + attribute \src "ls180.v:5201.634-5201.718" + wire $xor$ls180.v:5201$1032_Y + attribute \src "ls180.v:5201.588-5201.719" + wire $xor$ls180.v:5201$1033_Y + attribute \src "ls180.v:5201.234-5201.318" + wire $xor$ls180.v:5201$1034_Y + attribute \src "ls180.v:5201.187-5201.319" + wire $xor$ls180.v:5201$1035_Y + attribute \src "ls180.v:5352.879-5352.961" + wire $xor$ls180.v:5352$1068_Y + attribute \src "ls180.v:5352.620-5352.702" + wire $xor$ls180.v:5352$1069_Y + attribute \src "ls180.v:5352.575-5352.703" + wire $xor$ls180.v:5352$1070_Y + attribute \src "ls180.v:5352.229-5352.311" + wire $xor$ls180.v:5352$1071_Y + attribute \src "ls180.v:5352.183-5352.312" + wire $xor$ls180.v:5352$1072_Y + attribute \src "ls180.v:5353.879-5353.961" + wire $xor$ls180.v:5353$1073_Y + attribute \src "ls180.v:5353.620-5353.702" + wire $xor$ls180.v:5353$1074_Y + attribute \src "ls180.v:5353.575-5353.703" + wire $xor$ls180.v:5353$1075_Y + attribute \src "ls180.v:5353.229-5353.311" + wire $xor$ls180.v:5353$1076_Y + attribute \src "ls180.v:5353.183-5353.312" + wire $xor$ls180.v:5353$1077_Y + attribute \src "ls180.v:5362.879-5362.961" + wire $xor$ls180.v:5362$1079_Y + attribute \src "ls180.v:5362.620-5362.702" + wire $xor$ls180.v:5362$1080_Y + attribute \src "ls180.v:5362.575-5362.703" + wire $xor$ls180.v:5362$1081_Y + attribute \src "ls180.v:5362.229-5362.311" + wire $xor$ls180.v:5362$1082_Y + attribute \src "ls180.v:5362.183-5362.312" + wire $xor$ls180.v:5362$1083_Y + attribute \src "ls180.v:5363.879-5363.961" + wire $xor$ls180.v:5363$1084_Y + attribute \src "ls180.v:5363.620-5363.702" + wire $xor$ls180.v:5363$1085_Y + attribute \src "ls180.v:5363.575-5363.703" + wire $xor$ls180.v:5363$1086_Y + attribute \src "ls180.v:5363.229-5363.311" + wire $xor$ls180.v:5363$1087_Y + attribute \src "ls180.v:5363.183-5363.312" + wire $xor$ls180.v:5363$1088_Y + attribute \src "ls180.v:5372.879-5372.961" + wire $xor$ls180.v:5372$1090_Y + attribute \src "ls180.v:5372.620-5372.702" + wire $xor$ls180.v:5372$1091_Y + attribute \src "ls180.v:5372.575-5372.703" + wire $xor$ls180.v:5372$1092_Y + attribute \src "ls180.v:5372.229-5372.311" + wire $xor$ls180.v:5372$1093_Y + attribute \src "ls180.v:5372.183-5372.312" + wire $xor$ls180.v:5372$1094_Y + attribute \src "ls180.v:5373.879-5373.961" + wire $xor$ls180.v:5373$1095_Y + attribute \src "ls180.v:5373.620-5373.702" + wire $xor$ls180.v:5373$1096_Y + attribute \src "ls180.v:5373.575-5373.703" + wire $xor$ls180.v:5373$1097_Y + attribute \src "ls180.v:5373.229-5373.311" + wire $xor$ls180.v:5373$1098_Y + attribute \src "ls180.v:5373.183-5373.312" + wire $xor$ls180.v:5373$1099_Y + attribute \src "ls180.v:5382.879-5382.961" + wire $xor$ls180.v:5382$1101_Y + attribute \src "ls180.v:5382.620-5382.702" + wire $xor$ls180.v:5382$1102_Y + attribute \src "ls180.v:5382.575-5382.703" + wire $xor$ls180.v:5382$1103_Y + attribute \src "ls180.v:5382.229-5382.311" + wire $xor$ls180.v:5382$1104_Y + attribute \src "ls180.v:5382.183-5382.312" + wire $xor$ls180.v:5382$1105_Y + attribute \src "ls180.v:5383.879-5383.961" + wire $xor$ls180.v:5383$1106_Y + attribute \src "ls180.v:5383.620-5383.702" + wire $xor$ls180.v:5383$1107_Y + attribute \src "ls180.v:5383.575-5383.703" + wire $xor$ls180.v:5383$1108_Y + attribute \src "ls180.v:5383.229-5383.311" + wire $xor$ls180.v:5383$1109_Y + attribute \src "ls180.v:5383.183-5383.312" + wire $xor$ls180.v:5383$1110_Y + attribute \src "ls180.v:1854.11-1854.42" + wire width 3 \builder_bankmachine0_next_state + attribute \src "ls180.v:1853.11-1853.37" + wire width 3 \builder_bankmachine0_state + attribute \src "ls180.v:1856.11-1856.42" + wire width 3 \builder_bankmachine1_next_state + attribute \src "ls180.v:1855.11-1855.37" + wire width 3 \builder_bankmachine1_state + attribute \src "ls180.v:1858.11-1858.42" + wire width 3 \builder_bankmachine2_next_state + attribute \src "ls180.v:1857.11-1857.37" + wire width 3 \builder_bankmachine2_state + attribute \src "ls180.v:1860.11-1860.42" + wire width 3 \builder_bankmachine3_next_state + attribute \src "ls180.v:1859.11-1859.37" + wire width 3 \builder_bankmachine3_state + attribute \src "ls180.v:2713.5-2713.34" + wire \builder_comb_rhs_array_muxed0 + attribute \src "ls180.v:2714.12-2714.41" + wire width 13 \builder_comb_rhs_array_muxed1 + attribute \src "ls180.v:2726.5-2726.35" + wire \builder_comb_rhs_array_muxed10 + attribute \src "ls180.v:2727.5-2727.35" + wire \builder_comb_rhs_array_muxed11 + attribute \src "ls180.v:2731.12-2731.42" + wire width 22 \builder_comb_rhs_array_muxed12 + attribute \src "ls180.v:2732.5-2732.35" + wire \builder_comb_rhs_array_muxed13 + attribute \src "ls180.v:2733.5-2733.35" + wire \builder_comb_rhs_array_muxed14 + attribute \src "ls180.v:2734.12-2734.42" + wire width 22 \builder_comb_rhs_array_muxed15 + attribute \src "ls180.v:2735.5-2735.35" + wire \builder_comb_rhs_array_muxed16 + attribute \src "ls180.v:2736.5-2736.35" + wire \builder_comb_rhs_array_muxed17 + attribute \src "ls180.v:2737.12-2737.42" + wire width 22 \builder_comb_rhs_array_muxed18 + attribute \src "ls180.v:2738.5-2738.35" + wire \builder_comb_rhs_array_muxed19 + attribute \src "ls180.v:2715.11-2715.40" + wire width 2 \builder_comb_rhs_array_muxed2 + attribute \src "ls180.v:2739.5-2739.35" + wire \builder_comb_rhs_array_muxed20 + attribute \src "ls180.v:2740.12-2740.42" + wire width 22 \builder_comb_rhs_array_muxed21 + attribute \src "ls180.v:2741.5-2741.35" + wire \builder_comb_rhs_array_muxed22 + attribute \src "ls180.v:2742.5-2742.35" + wire \builder_comb_rhs_array_muxed23 + attribute \src "ls180.v:2743.12-2743.42" + wire width 32 \builder_comb_rhs_array_muxed24 + attribute \src "ls180.v:2744.12-2744.42" + wire width 64 \builder_comb_rhs_array_muxed25 + attribute \src "ls180.v:2745.11-2745.41" + wire width 8 \builder_comb_rhs_array_muxed26 + attribute \src "ls180.v:2746.5-2746.35" + wire \builder_comb_rhs_array_muxed27 + attribute \src "ls180.v:2747.5-2747.35" + wire \builder_comb_rhs_array_muxed28 + attribute \src "ls180.v:2748.5-2748.35" + wire \builder_comb_rhs_array_muxed29 + attribute \src "ls180.v:2716.5-2716.34" + wire \builder_comb_rhs_array_muxed3 + attribute \src "ls180.v:2749.11-2749.41" + wire width 3 \builder_comb_rhs_array_muxed30 + attribute \src "ls180.v:2750.11-2750.41" + wire width 2 \builder_comb_rhs_array_muxed31 + attribute \src "ls180.v:2717.5-2717.34" + wire \builder_comb_rhs_array_muxed4 + attribute \src "ls180.v:2718.5-2718.34" + wire \builder_comb_rhs_array_muxed5 + attribute \src "ls180.v:2722.5-2722.34" + wire \builder_comb_rhs_array_muxed6 + attribute \src "ls180.v:2723.12-2723.41" + wire width 13 \builder_comb_rhs_array_muxed7 + attribute \src "ls180.v:2724.11-2724.40" + wire width 2 \builder_comb_rhs_array_muxed8 + attribute \src "ls180.v:2725.5-2725.34" + wire \builder_comb_rhs_array_muxed9 + attribute \src "ls180.v:2719.5-2719.32" + wire \builder_comb_t_array_muxed0 + attribute \src "ls180.v:2720.5-2720.32" + wire \builder_comb_t_array_muxed1 + attribute \src "ls180.v:2721.5-2721.32" + wire \builder_comb_t_array_muxed2 + attribute \src "ls180.v:2728.5-2728.32" + wire \builder_comb_t_array_muxed3 + attribute \src "ls180.v:2729.5-2729.32" + wire \builder_comb_t_array_muxed4 + attribute \src "ls180.v:2730.5-2730.32" + wire \builder_comb_t_array_muxed5 + attribute \src "ls180.v:1840.5-1840.34" + wire \builder_converter0_next_state + attribute \src "ls180.v:1839.5-1839.29" + wire \builder_converter0_state + attribute \src "ls180.v:1844.5-1844.34" + wire \builder_converter1_next_state + attribute \src "ls180.v:1843.5-1843.29" + wire \builder_converter1_state + attribute \src "ls180.v:1848.5-1848.34" + wire \builder_converter2_next_state + attribute \src "ls180.v:1847.5-1847.29" + wire \builder_converter2_state + attribute \src "ls180.v:1885.5-1885.33" + wire \builder_converter_next_state + attribute \src "ls180.v:1884.5-1884.28" + wire \builder_converter_state + attribute \src "ls180.v:2013.12-2013.25" + wire width 20 \builder_count + attribute \src "ls180.v:2701.13-2701.41" + wire width 14 \builder_csr_interconnect_adr + attribute \src "ls180.v:2704.12-2704.42" + wire width 8 \builder_csr_interconnect_dat_r + attribute \src "ls180.v:2703.12-2703.42" + wire width 8 \builder_csr_interconnect_dat_w + attribute \src "ls180.v:2702.6-2702.33" + wire \builder_csr_interconnect_we + attribute \src "ls180.v:2051.12-2051.42" + wire width 8 \builder_csrbank0_bus_errors0_r + attribute \src "ls180.v:2050.6-2050.37" + wire \builder_csrbank0_bus_errors0_re + attribute \src "ls180.v:2053.12-2053.42" + wire width 8 \builder_csrbank0_bus_errors0_w + attribute \src "ls180.v:2052.6-2052.37" + wire \builder_csrbank0_bus_errors0_we + attribute \src "ls180.v:2047.12-2047.42" + wire width 8 \builder_csrbank0_bus_errors1_r + attribute \src "ls180.v:2046.6-2046.37" + wire \builder_csrbank0_bus_errors1_re + attribute \src "ls180.v:2049.12-2049.42" + wire width 8 \builder_csrbank0_bus_errors1_w + attribute \src "ls180.v:2048.6-2048.37" + wire \builder_csrbank0_bus_errors1_we + attribute \src "ls180.v:2043.12-2043.42" + wire width 8 \builder_csrbank0_bus_errors2_r + attribute \src "ls180.v:2042.6-2042.37" + wire \builder_csrbank0_bus_errors2_re + attribute \src "ls180.v:2045.12-2045.42" + wire width 8 \builder_csrbank0_bus_errors2_w + attribute \src "ls180.v:2044.6-2044.37" + wire \builder_csrbank0_bus_errors2_we + attribute \src "ls180.v:2039.12-2039.42" + wire width 8 \builder_csrbank0_bus_errors3_r + attribute \src "ls180.v:2038.6-2038.37" + wire \builder_csrbank0_bus_errors3_re + attribute \src "ls180.v:2041.12-2041.42" + wire width 8 \builder_csrbank0_bus_errors3_w + attribute \src "ls180.v:2040.6-2040.37" + wire \builder_csrbank0_bus_errors3_we + attribute \src "ls180.v:2019.6-2019.31" + wire \builder_csrbank0_reset0_r + attribute \src "ls180.v:2018.6-2018.32" + wire \builder_csrbank0_reset0_re + attribute \src "ls180.v:2021.6-2021.31" + wire \builder_csrbank0_reset0_w + attribute \src "ls180.v:2020.6-2020.32" + wire \builder_csrbank0_reset0_we + attribute \src "ls180.v:2035.12-2035.39" + wire width 8 \builder_csrbank0_scratch0_r + attribute \src "ls180.v:2034.6-2034.34" + wire \builder_csrbank0_scratch0_re + attribute \src "ls180.v:2037.12-2037.39" + wire width 8 \builder_csrbank0_scratch0_w + attribute \src "ls180.v:2036.6-2036.34" + wire \builder_csrbank0_scratch0_we + attribute \src "ls180.v:2031.12-2031.39" + wire width 8 \builder_csrbank0_scratch1_r + attribute \src "ls180.v:2030.6-2030.34" + wire \builder_csrbank0_scratch1_re + attribute \src "ls180.v:2033.12-2033.39" + wire width 8 \builder_csrbank0_scratch1_w + attribute \src "ls180.v:2032.6-2032.34" + wire \builder_csrbank0_scratch1_we + attribute \src "ls180.v:2027.12-2027.39" + wire width 8 \builder_csrbank0_scratch2_r + attribute \src "ls180.v:2026.6-2026.34" + wire \builder_csrbank0_scratch2_re + attribute \src "ls180.v:2029.12-2029.39" + wire width 8 \builder_csrbank0_scratch2_w + attribute \src "ls180.v:2028.6-2028.34" + wire \builder_csrbank0_scratch2_we + attribute \src "ls180.v:2023.12-2023.39" + wire width 8 \builder_csrbank0_scratch3_r + attribute \src "ls180.v:2022.6-2022.34" + wire \builder_csrbank0_scratch3_re + attribute \src "ls180.v:2025.12-2025.39" + wire width 8 \builder_csrbank0_scratch3_w + attribute \src "ls180.v:2024.6-2024.34" + wire \builder_csrbank0_scratch3_we + attribute \src "ls180.v:2054.6-2054.26" + wire \builder_csrbank0_sel + attribute \src "ls180.v:2525.12-2525.40" + wire width 8 \builder_csrbank10_control0_r + attribute \src "ls180.v:2524.6-2524.35" + wire \builder_csrbank10_control0_re + attribute \src "ls180.v:2527.12-2527.40" + wire width 8 \builder_csrbank10_control0_w + attribute \src "ls180.v:2526.6-2526.35" + wire \builder_csrbank10_control0_we + attribute \src "ls180.v:2521.12-2521.40" + wire width 8 \builder_csrbank10_control1_r + attribute \src "ls180.v:2520.6-2520.35" + wire \builder_csrbank10_control1_re + attribute \src "ls180.v:2523.12-2523.40" + wire width 8 \builder_csrbank10_control1_w + attribute \src "ls180.v:2522.6-2522.35" + wire \builder_csrbank10_control1_we + attribute \src "ls180.v:2541.6-2541.29" + wire \builder_csrbank10_cs0_r + attribute \src "ls180.v:2540.6-2540.30" + wire \builder_csrbank10_cs0_re + attribute \src "ls180.v:2543.6-2543.29" + wire \builder_csrbank10_cs0_w + attribute \src "ls180.v:2542.6-2542.30" + wire \builder_csrbank10_cs0_we + attribute \src "ls180.v:2545.6-2545.35" + wire \builder_csrbank10_loopback0_r + attribute \src "ls180.v:2544.6-2544.36" + wire \builder_csrbank10_loopback0_re + attribute \src "ls180.v:2547.6-2547.35" + wire \builder_csrbank10_loopback0_w + attribute \src "ls180.v:2546.6-2546.36" + wire \builder_csrbank10_loopback0_we + attribute \src "ls180.v:2537.12-2537.36" + wire width 8 \builder_csrbank10_miso_r + attribute \src "ls180.v:2536.6-2536.31" + wire \builder_csrbank10_miso_re + attribute \src "ls180.v:2539.12-2539.36" + wire width 8 \builder_csrbank10_miso_w + attribute \src "ls180.v:2538.6-2538.31" + wire \builder_csrbank10_miso_we + attribute \src "ls180.v:2533.12-2533.37" + wire width 8 \builder_csrbank10_mosi0_r + attribute \src "ls180.v:2532.6-2532.32" + wire \builder_csrbank10_mosi0_re + attribute \src "ls180.v:2535.12-2535.37" + wire width 8 \builder_csrbank10_mosi0_w + attribute \src "ls180.v:2534.6-2534.32" + wire \builder_csrbank10_mosi0_we + attribute \src "ls180.v:2548.6-2548.27" + wire \builder_csrbank10_sel + attribute \src "ls180.v:2529.6-2529.32" + wire \builder_csrbank10_status_r + attribute \src "ls180.v:2528.6-2528.33" + wire \builder_csrbank10_status_re + attribute \src "ls180.v:2531.6-2531.32" + wire \builder_csrbank10_status_w + attribute \src "ls180.v:2530.6-2530.33" + wire \builder_csrbank10_status_we + attribute \src "ls180.v:2586.12-2586.44" + wire width 8 \builder_csrbank11_clk_divider0_r + attribute \src "ls180.v:2585.6-2585.39" + wire \builder_csrbank11_clk_divider0_re + attribute \src "ls180.v:2588.12-2588.44" + wire width 8 \builder_csrbank11_clk_divider0_w + attribute \src "ls180.v:2587.6-2587.39" + wire \builder_csrbank11_clk_divider0_we + attribute \src "ls180.v:2582.12-2582.44" + wire width 8 \builder_csrbank11_clk_divider1_r + attribute \src "ls180.v:2581.6-2581.39" + wire \builder_csrbank11_clk_divider1_re + attribute \src "ls180.v:2584.12-2584.44" + wire width 8 \builder_csrbank11_clk_divider1_w + attribute \src "ls180.v:2583.6-2583.39" + wire \builder_csrbank11_clk_divider1_we + attribute \src "ls180.v:2558.12-2558.40" + wire width 8 \builder_csrbank11_control0_r + attribute \src "ls180.v:2557.6-2557.35" + wire \builder_csrbank11_control0_re + attribute \src "ls180.v:2560.12-2560.40" + wire width 8 \builder_csrbank11_control0_w + attribute \src "ls180.v:2559.6-2559.35" + wire \builder_csrbank11_control0_we + attribute \src "ls180.v:2554.12-2554.40" + wire width 8 \builder_csrbank11_control1_r + attribute \src "ls180.v:2553.6-2553.35" + wire \builder_csrbank11_control1_re + attribute \src "ls180.v:2556.12-2556.40" + wire width 8 \builder_csrbank11_control1_w + attribute \src "ls180.v:2555.6-2555.35" + wire \builder_csrbank11_control1_we + attribute \src "ls180.v:2574.6-2574.29" + wire \builder_csrbank11_cs0_r + attribute \src "ls180.v:2573.6-2573.30" + wire \builder_csrbank11_cs0_re + attribute \src "ls180.v:2576.6-2576.29" + wire \builder_csrbank11_cs0_w + attribute \src "ls180.v:2575.6-2575.30" + wire \builder_csrbank11_cs0_we + attribute \src "ls180.v:2578.6-2578.35" + wire \builder_csrbank11_loopback0_r + attribute \src "ls180.v:2577.6-2577.36" + wire \builder_csrbank11_loopback0_re + attribute \src "ls180.v:2580.6-2580.35" + wire \builder_csrbank11_loopback0_w + attribute \src "ls180.v:2579.6-2579.36" + wire \builder_csrbank11_loopback0_we + attribute \src "ls180.v:2570.12-2570.36" + wire width 8 \builder_csrbank11_miso_r + attribute \src "ls180.v:2569.6-2569.31" + wire \builder_csrbank11_miso_re + attribute \src "ls180.v:2572.12-2572.36" + wire width 8 \builder_csrbank11_miso_w + attribute \src "ls180.v:2571.6-2571.31" + wire \builder_csrbank11_miso_we + attribute \src "ls180.v:2566.12-2566.37" + wire width 8 \builder_csrbank11_mosi0_r + attribute \src "ls180.v:2565.6-2565.32" + wire \builder_csrbank11_mosi0_re + attribute \src "ls180.v:2568.12-2568.37" + wire width 8 \builder_csrbank11_mosi0_w + attribute \src "ls180.v:2567.6-2567.32" + wire \builder_csrbank11_mosi0_we + attribute \src "ls180.v:2589.6-2589.27" + wire \builder_csrbank11_sel + attribute \src "ls180.v:2562.6-2562.32" + wire \builder_csrbank11_status_r + attribute \src "ls180.v:2561.6-2561.33" + wire \builder_csrbank11_status_re + attribute \src "ls180.v:2564.6-2564.32" + wire \builder_csrbank11_status_w + attribute \src "ls180.v:2563.6-2563.33" + wire \builder_csrbank11_status_we + attribute \src "ls180.v:2627.6-2627.29" + wire \builder_csrbank12_en0_r + attribute \src "ls180.v:2626.6-2626.30" + wire \builder_csrbank12_en0_re + attribute \src "ls180.v:2629.6-2629.29" + wire \builder_csrbank12_en0_w + attribute \src "ls180.v:2628.6-2628.30" + wire \builder_csrbank12_en0_we + attribute \src "ls180.v:2651.6-2651.36" + wire \builder_csrbank12_ev_enable0_r + attribute \src "ls180.v:2650.6-2650.37" + wire \builder_csrbank12_ev_enable0_re + attribute \src "ls180.v:2653.6-2653.36" + wire \builder_csrbank12_ev_enable0_w + attribute \src "ls180.v:2652.6-2652.37" + wire \builder_csrbank12_ev_enable0_we + attribute \src "ls180.v:2607.12-2607.37" + wire width 8 \builder_csrbank12_load0_r + attribute \src "ls180.v:2606.6-2606.32" + wire \builder_csrbank12_load0_re + attribute \src "ls180.v:2609.12-2609.37" + wire width 8 \builder_csrbank12_load0_w + attribute \src "ls180.v:2608.6-2608.32" + wire \builder_csrbank12_load0_we + attribute \src "ls180.v:2603.12-2603.37" + wire width 8 \builder_csrbank12_load1_r + attribute \src "ls180.v:2602.6-2602.32" + wire \builder_csrbank12_load1_re + attribute \src "ls180.v:2605.12-2605.37" + wire width 8 \builder_csrbank12_load1_w + attribute \src "ls180.v:2604.6-2604.32" + wire \builder_csrbank12_load1_we + attribute \src "ls180.v:2599.12-2599.37" + wire width 8 \builder_csrbank12_load2_r + attribute \src "ls180.v:2598.6-2598.32" + wire \builder_csrbank12_load2_re + attribute \src "ls180.v:2601.12-2601.37" + wire width 8 \builder_csrbank12_load2_w + attribute \src "ls180.v:2600.6-2600.32" + wire \builder_csrbank12_load2_we + attribute \src "ls180.v:2595.12-2595.37" + wire width 8 \builder_csrbank12_load3_r + attribute \src "ls180.v:2594.6-2594.32" + wire \builder_csrbank12_load3_re + attribute \src "ls180.v:2597.12-2597.37" + wire width 8 \builder_csrbank12_load3_w + attribute \src "ls180.v:2596.6-2596.32" + wire \builder_csrbank12_load3_we + attribute \src "ls180.v:2623.12-2623.39" + wire width 8 \builder_csrbank12_reload0_r + attribute \src "ls180.v:2622.6-2622.34" + wire \builder_csrbank12_reload0_re + attribute \src "ls180.v:2625.12-2625.39" + wire width 8 \builder_csrbank12_reload0_w + attribute \src "ls180.v:2624.6-2624.34" + wire \builder_csrbank12_reload0_we + attribute \src "ls180.v:2619.12-2619.39" + wire width 8 \builder_csrbank12_reload1_r + attribute \src "ls180.v:2618.6-2618.34" + wire \builder_csrbank12_reload1_re + attribute \src "ls180.v:2621.12-2621.39" + wire width 8 \builder_csrbank12_reload1_w + attribute \src "ls180.v:2620.6-2620.34" + wire \builder_csrbank12_reload1_we + attribute \src "ls180.v:2615.12-2615.39" + wire width 8 \builder_csrbank12_reload2_r + attribute \src "ls180.v:2614.6-2614.34" + wire \builder_csrbank12_reload2_re + attribute \src "ls180.v:2617.12-2617.39" + wire width 8 \builder_csrbank12_reload2_w + attribute \src "ls180.v:2616.6-2616.34" + wire \builder_csrbank12_reload2_we + attribute \src "ls180.v:2611.12-2611.39" + wire width 8 \builder_csrbank12_reload3_r + attribute \src "ls180.v:2610.6-2610.34" + wire \builder_csrbank12_reload3_re + attribute \src "ls180.v:2613.12-2613.39" + wire width 8 \builder_csrbank12_reload3_w + attribute \src "ls180.v:2612.6-2612.34" + wire \builder_csrbank12_reload3_we + attribute \src "ls180.v:2654.6-2654.27" + wire \builder_csrbank12_sel + attribute \src "ls180.v:2631.6-2631.39" + wire \builder_csrbank12_update_value0_r + attribute \src "ls180.v:2630.6-2630.40" + wire \builder_csrbank12_update_value0_re + attribute \src "ls180.v:2633.6-2633.39" + wire \builder_csrbank12_update_value0_w + attribute \src "ls180.v:2632.6-2632.40" + wire \builder_csrbank12_update_value0_we + attribute \src "ls180.v:2647.12-2647.38" + wire width 8 \builder_csrbank12_value0_r + attribute \src "ls180.v:2646.6-2646.33" + wire \builder_csrbank12_value0_re + attribute \src "ls180.v:2649.12-2649.38" + wire width 8 \builder_csrbank12_value0_w + attribute \src "ls180.v:2648.6-2648.33" + wire \builder_csrbank12_value0_we + attribute \src "ls180.v:2643.12-2643.38" + wire width 8 \builder_csrbank12_value1_r + attribute \src "ls180.v:2642.6-2642.33" + wire \builder_csrbank12_value1_re + attribute \src "ls180.v:2645.12-2645.38" + wire width 8 \builder_csrbank12_value1_w + attribute \src "ls180.v:2644.6-2644.33" + wire \builder_csrbank12_value1_we + attribute \src "ls180.v:2639.12-2639.38" + wire width 8 \builder_csrbank12_value2_r + attribute \src "ls180.v:2638.6-2638.33" + wire \builder_csrbank12_value2_re + attribute \src "ls180.v:2641.12-2641.38" + wire width 8 \builder_csrbank12_value2_w + attribute \src "ls180.v:2640.6-2640.33" + wire \builder_csrbank12_value2_we + attribute \src "ls180.v:2635.12-2635.38" + wire width 8 \builder_csrbank12_value3_r + attribute \src "ls180.v:2634.6-2634.33" + wire \builder_csrbank12_value3_re + attribute \src "ls180.v:2637.12-2637.38" + wire width 8 \builder_csrbank12_value3_w + attribute \src "ls180.v:2636.6-2636.33" + wire \builder_csrbank12_value3_we + attribute \src "ls180.v:2668.12-2668.42" + wire width 2 \builder_csrbank13_ev_enable0_r + attribute \src "ls180.v:2667.6-2667.37" + wire \builder_csrbank13_ev_enable0_re + attribute \src "ls180.v:2670.12-2670.42" + wire width 2 \builder_csrbank13_ev_enable0_w + attribute \src "ls180.v:2669.6-2669.37" + wire \builder_csrbank13_ev_enable0_we + attribute \src "ls180.v:2664.6-2664.33" + wire \builder_csrbank13_rxempty_r + attribute \src "ls180.v:2663.6-2663.34" + wire \builder_csrbank13_rxempty_re + attribute \src "ls180.v:2666.6-2666.33" + wire \builder_csrbank13_rxempty_w + attribute \src "ls180.v:2665.6-2665.34" + wire \builder_csrbank13_rxempty_we + attribute \src "ls180.v:2676.6-2676.32" + wire \builder_csrbank13_rxfull_r + attribute \src "ls180.v:2675.6-2675.33" + wire \builder_csrbank13_rxfull_re + attribute \src "ls180.v:2678.6-2678.32" + wire \builder_csrbank13_rxfull_w + attribute \src "ls180.v:2677.6-2677.33" + wire \builder_csrbank13_rxfull_we + attribute \src "ls180.v:2679.6-2679.27" + wire \builder_csrbank13_sel + attribute \src "ls180.v:2672.6-2672.33" + wire \builder_csrbank13_txempty_r + attribute \src "ls180.v:2671.6-2671.34" + wire \builder_csrbank13_txempty_re + attribute \src "ls180.v:2674.6-2674.33" + wire \builder_csrbank13_txempty_w + attribute \src "ls180.v:2673.6-2673.34" + wire \builder_csrbank13_txempty_we + attribute \src "ls180.v:2660.6-2660.32" + wire \builder_csrbank13_txfull_r + attribute \src "ls180.v:2659.6-2659.33" + wire \builder_csrbank13_txfull_re + attribute \src "ls180.v:2662.6-2662.32" + wire \builder_csrbank13_txfull_w + attribute \src "ls180.v:2661.6-2661.33" + wire \builder_csrbank13_txfull_we + attribute \src "ls180.v:2700.6-2700.27" + wire \builder_csrbank14_sel + attribute \src "ls180.v:2697.12-2697.44" + wire width 8 \builder_csrbank14_tuning_word0_r + attribute \src "ls180.v:2696.6-2696.39" + wire \builder_csrbank14_tuning_word0_re + attribute \src "ls180.v:2699.12-2699.44" + wire width 8 \builder_csrbank14_tuning_word0_w + attribute \src "ls180.v:2698.6-2698.39" + wire \builder_csrbank14_tuning_word0_we + attribute \src "ls180.v:2693.12-2693.44" + wire width 8 \builder_csrbank14_tuning_word1_r + attribute \src "ls180.v:2692.6-2692.39" + wire \builder_csrbank14_tuning_word1_re + attribute \src "ls180.v:2695.12-2695.44" + wire width 8 \builder_csrbank14_tuning_word1_w + attribute \src "ls180.v:2694.6-2694.39" + wire \builder_csrbank14_tuning_word1_we + attribute \src "ls180.v:2689.12-2689.44" + wire width 8 \builder_csrbank14_tuning_word2_r + attribute \src "ls180.v:2688.6-2688.39" + wire \builder_csrbank14_tuning_word2_re + attribute \src "ls180.v:2691.12-2691.44" + wire width 8 \builder_csrbank14_tuning_word2_w + attribute \src "ls180.v:2690.6-2690.39" + wire \builder_csrbank14_tuning_word2_we + attribute \src "ls180.v:2685.12-2685.44" + wire width 8 \builder_csrbank14_tuning_word3_r + attribute \src "ls180.v:2684.6-2684.39" + wire \builder_csrbank14_tuning_word3_re + attribute \src "ls180.v:2687.12-2687.44" + wire width 8 \builder_csrbank14_tuning_word3_w + attribute \src "ls180.v:2686.6-2686.39" + wire \builder_csrbank14_tuning_word3_we + attribute \src "ls180.v:2072.12-2072.34" + wire width 8 \builder_csrbank1_in0_r + attribute \src "ls180.v:2071.6-2071.29" + wire \builder_csrbank1_in0_re + attribute \src "ls180.v:2074.12-2074.34" + wire width 8 \builder_csrbank1_in0_w + attribute \src "ls180.v:2073.6-2073.29" + wire \builder_csrbank1_in0_we + attribute \src "ls180.v:2068.12-2068.34" + wire width 8 \builder_csrbank1_in1_r + attribute \src "ls180.v:2067.6-2067.29" + wire \builder_csrbank1_in1_re + attribute \src "ls180.v:2070.12-2070.34" + wire width 8 \builder_csrbank1_in1_w + attribute \src "ls180.v:2069.6-2069.29" + wire \builder_csrbank1_in1_we + attribute \src "ls180.v:2064.12-2064.34" + wire width 8 \builder_csrbank1_oe0_r + attribute \src "ls180.v:2063.6-2063.29" + wire \builder_csrbank1_oe0_re + attribute \src "ls180.v:2066.12-2066.34" + wire width 8 \builder_csrbank1_oe0_w + attribute \src "ls180.v:2065.6-2065.29" + wire \builder_csrbank1_oe0_we + attribute \src "ls180.v:2060.12-2060.34" + wire width 8 \builder_csrbank1_oe1_r + attribute \src "ls180.v:2059.6-2059.29" + wire \builder_csrbank1_oe1_re + attribute \src "ls180.v:2062.12-2062.34" + wire width 8 \builder_csrbank1_oe1_w + attribute \src "ls180.v:2061.6-2061.29" + wire \builder_csrbank1_oe1_we + attribute \src "ls180.v:2080.12-2080.35" + wire width 8 \builder_csrbank1_out0_r + attribute \src "ls180.v:2079.6-2079.30" + wire \builder_csrbank1_out0_re + attribute \src "ls180.v:2082.12-2082.35" + wire width 8 \builder_csrbank1_out0_w + attribute \src "ls180.v:2081.6-2081.30" + wire \builder_csrbank1_out0_we + attribute \src "ls180.v:2076.12-2076.35" + wire width 8 \builder_csrbank1_out1_r + attribute \src "ls180.v:2075.6-2075.30" + wire \builder_csrbank1_out1_re + attribute \src "ls180.v:2078.12-2078.35" + wire width 8 \builder_csrbank1_out1_w + attribute \src "ls180.v:2077.6-2077.30" + wire \builder_csrbank1_out1_we + attribute \src "ls180.v:2083.6-2083.26" + wire \builder_csrbank1_sel + attribute \src "ls180.v:2093.6-2093.26" + wire \builder_csrbank2_r_r + attribute \src "ls180.v:2092.6-2092.27" + wire \builder_csrbank2_r_re + attribute \src "ls180.v:2095.6-2095.26" + wire \builder_csrbank2_r_w + attribute \src "ls180.v:2094.6-2094.27" + wire \builder_csrbank2_r_we + attribute \src "ls180.v:2096.6-2096.26" + wire \builder_csrbank2_sel + attribute \src "ls180.v:2089.12-2089.33" + wire width 3 \builder_csrbank2_w0_r + attribute \src "ls180.v:2088.6-2088.28" + wire \builder_csrbank2_w0_re + attribute \src "ls180.v:2091.12-2091.33" + wire width 3 \builder_csrbank2_w0_w + attribute \src "ls180.v:2090.6-2090.28" + wire \builder_csrbank2_w0_we + attribute \src "ls180.v:2102.6-2102.32" + wire \builder_csrbank3_enable0_r + attribute \src "ls180.v:2101.6-2101.33" + wire \builder_csrbank3_enable0_re + attribute \src "ls180.v:2104.6-2104.32" + wire \builder_csrbank3_enable0_w + attribute \src "ls180.v:2103.6-2103.33" + wire \builder_csrbank3_enable0_we + attribute \src "ls180.v:2134.12-2134.38" + wire width 8 \builder_csrbank3_period0_r + attribute \src "ls180.v:2133.6-2133.33" + wire \builder_csrbank3_period0_re + attribute \src "ls180.v:2136.12-2136.38" + wire width 8 \builder_csrbank3_period0_w + attribute \src "ls180.v:2135.6-2135.33" + wire \builder_csrbank3_period0_we + attribute \src "ls180.v:2130.12-2130.38" + wire width 8 \builder_csrbank3_period1_r + attribute \src "ls180.v:2129.6-2129.33" + wire \builder_csrbank3_period1_re + attribute \src "ls180.v:2132.12-2132.38" + wire width 8 \builder_csrbank3_period1_w + attribute \src "ls180.v:2131.6-2131.33" + wire \builder_csrbank3_period1_we + attribute \src "ls180.v:2126.12-2126.38" + wire width 8 \builder_csrbank3_period2_r + attribute \src "ls180.v:2125.6-2125.33" + wire \builder_csrbank3_period2_re + attribute \src "ls180.v:2128.12-2128.38" + wire width 8 \builder_csrbank3_period2_w + attribute \src "ls180.v:2127.6-2127.33" + wire \builder_csrbank3_period2_we + attribute \src "ls180.v:2122.12-2122.38" + wire width 8 \builder_csrbank3_period3_r + attribute \src "ls180.v:2121.6-2121.33" + wire \builder_csrbank3_period3_re + attribute \src "ls180.v:2124.12-2124.38" + wire width 8 \builder_csrbank3_period3_w + attribute \src "ls180.v:2123.6-2123.33" + wire \builder_csrbank3_period3_we + attribute \src "ls180.v:2137.6-2137.26" + wire \builder_csrbank3_sel + attribute \src "ls180.v:2118.12-2118.37" + wire width 8 \builder_csrbank3_width0_r + attribute \src "ls180.v:2117.6-2117.32" + wire \builder_csrbank3_width0_re + attribute \src "ls180.v:2120.12-2120.37" + wire width 8 \builder_csrbank3_width0_w + attribute \src "ls180.v:2119.6-2119.32" + wire \builder_csrbank3_width0_we + attribute \src "ls180.v:2114.12-2114.37" + wire width 8 \builder_csrbank3_width1_r + attribute \src "ls180.v:2113.6-2113.32" + wire \builder_csrbank3_width1_re + attribute \src "ls180.v:2116.12-2116.37" + wire width 8 \builder_csrbank3_width1_w + attribute \src "ls180.v:2115.6-2115.32" + wire \builder_csrbank3_width1_we + attribute \src "ls180.v:2110.12-2110.37" + wire width 8 \builder_csrbank3_width2_r + attribute \src "ls180.v:2109.6-2109.32" + wire \builder_csrbank3_width2_re + attribute \src "ls180.v:2112.12-2112.37" + wire width 8 \builder_csrbank3_width2_w + attribute \src "ls180.v:2111.6-2111.32" + wire \builder_csrbank3_width2_we + attribute \src "ls180.v:2106.12-2106.37" + wire width 8 \builder_csrbank3_width3_r + attribute \src "ls180.v:2105.6-2105.32" + wire \builder_csrbank3_width3_re + attribute \src "ls180.v:2108.12-2108.37" + wire width 8 \builder_csrbank3_width3_w + attribute \src "ls180.v:2107.6-2107.32" + wire \builder_csrbank3_width3_we + attribute \src "ls180.v:2143.6-2143.32" + wire \builder_csrbank4_enable0_r + attribute \src "ls180.v:2142.6-2142.33" + wire \builder_csrbank4_enable0_re + attribute \src "ls180.v:2145.6-2145.32" + wire \builder_csrbank4_enable0_w + attribute \src "ls180.v:2144.6-2144.33" + wire \builder_csrbank4_enable0_we + attribute \src "ls180.v:2175.12-2175.38" + wire width 8 \builder_csrbank4_period0_r + attribute \src "ls180.v:2174.6-2174.33" + wire \builder_csrbank4_period0_re + attribute \src "ls180.v:2177.12-2177.38" + wire width 8 \builder_csrbank4_period0_w + attribute \src "ls180.v:2176.6-2176.33" + wire \builder_csrbank4_period0_we + attribute \src "ls180.v:2171.12-2171.38" + wire width 8 \builder_csrbank4_period1_r + attribute \src "ls180.v:2170.6-2170.33" + wire \builder_csrbank4_period1_re + attribute \src "ls180.v:2173.12-2173.38" + wire width 8 \builder_csrbank4_period1_w + attribute \src "ls180.v:2172.6-2172.33" + wire \builder_csrbank4_period1_we + attribute \src "ls180.v:2167.12-2167.38" + wire width 8 \builder_csrbank4_period2_r + attribute \src "ls180.v:2166.6-2166.33" + wire \builder_csrbank4_period2_re + attribute \src "ls180.v:2169.12-2169.38" + wire width 8 \builder_csrbank4_period2_w + attribute \src "ls180.v:2168.6-2168.33" + wire \builder_csrbank4_period2_we + attribute \src "ls180.v:2163.12-2163.38" + wire width 8 \builder_csrbank4_period3_r + attribute \src "ls180.v:2162.6-2162.33" + wire \builder_csrbank4_period3_re + attribute \src "ls180.v:2165.12-2165.38" + wire width 8 \builder_csrbank4_period3_w + attribute \src "ls180.v:2164.6-2164.33" + wire \builder_csrbank4_period3_we + attribute \src "ls180.v:2178.6-2178.26" + wire \builder_csrbank4_sel + attribute \src "ls180.v:2159.12-2159.37" + wire width 8 \builder_csrbank4_width0_r + attribute \src "ls180.v:2158.6-2158.32" + wire \builder_csrbank4_width0_re + attribute \src "ls180.v:2161.12-2161.37" + wire width 8 \builder_csrbank4_width0_w + attribute \src "ls180.v:2160.6-2160.32" + wire \builder_csrbank4_width0_we + attribute \src "ls180.v:2155.12-2155.37" + wire width 8 \builder_csrbank4_width1_r + attribute \src "ls180.v:2154.6-2154.32" + wire \builder_csrbank4_width1_re + attribute \src "ls180.v:2157.12-2157.37" + wire width 8 \builder_csrbank4_width1_w + attribute \src "ls180.v:2156.6-2156.32" + wire \builder_csrbank4_width1_we + attribute \src "ls180.v:2151.12-2151.37" + wire width 8 \builder_csrbank4_width2_r + attribute \src "ls180.v:2150.6-2150.32" + wire \builder_csrbank4_width2_re + attribute \src "ls180.v:2153.12-2153.37" + wire width 8 \builder_csrbank4_width2_w + attribute \src "ls180.v:2152.6-2152.32" + wire \builder_csrbank4_width2_we + attribute \src "ls180.v:2147.12-2147.37" + wire width 8 \builder_csrbank4_width3_r + attribute \src "ls180.v:2146.6-2146.32" + wire \builder_csrbank4_width3_re + attribute \src "ls180.v:2149.12-2149.37" + wire width 8 \builder_csrbank4_width3_w + attribute \src "ls180.v:2148.6-2148.32" + wire \builder_csrbank4_width3_we + attribute \src "ls180.v:2212.12-2212.40" + wire width 8 \builder_csrbank5_dma_base0_r + attribute \src "ls180.v:2211.6-2211.35" + wire \builder_csrbank5_dma_base0_re + attribute \src "ls180.v:2214.12-2214.40" + wire width 8 \builder_csrbank5_dma_base0_w + attribute \src "ls180.v:2213.6-2213.35" + wire \builder_csrbank5_dma_base0_we + attribute \src "ls180.v:2208.12-2208.40" + wire width 8 \builder_csrbank5_dma_base1_r + attribute \src "ls180.v:2207.6-2207.35" + wire \builder_csrbank5_dma_base1_re + attribute \src "ls180.v:2210.12-2210.40" + wire width 8 \builder_csrbank5_dma_base1_w + attribute \src "ls180.v:2209.6-2209.35" + wire \builder_csrbank5_dma_base1_we + attribute \src "ls180.v:2204.12-2204.40" + wire width 8 \builder_csrbank5_dma_base2_r + attribute \src "ls180.v:2203.6-2203.35" + wire \builder_csrbank5_dma_base2_re + attribute \src "ls180.v:2206.12-2206.40" + wire width 8 \builder_csrbank5_dma_base2_w + attribute \src "ls180.v:2205.6-2205.35" + wire \builder_csrbank5_dma_base2_we + attribute \src "ls180.v:2200.12-2200.40" + wire width 8 \builder_csrbank5_dma_base3_r + attribute \src "ls180.v:2199.6-2199.35" + wire \builder_csrbank5_dma_base3_re + attribute \src "ls180.v:2202.12-2202.40" + wire width 8 \builder_csrbank5_dma_base3_w + attribute \src "ls180.v:2201.6-2201.35" + wire \builder_csrbank5_dma_base3_we + attribute \src "ls180.v:2196.12-2196.40" + wire width 8 \builder_csrbank5_dma_base4_r + attribute \src "ls180.v:2195.6-2195.35" + wire \builder_csrbank5_dma_base4_re + attribute \src "ls180.v:2198.12-2198.40" + wire width 8 \builder_csrbank5_dma_base4_w + attribute \src "ls180.v:2197.6-2197.35" + wire \builder_csrbank5_dma_base4_we + attribute \src "ls180.v:2192.12-2192.40" + wire width 8 \builder_csrbank5_dma_base5_r + attribute \src "ls180.v:2191.6-2191.35" + wire \builder_csrbank5_dma_base5_re + attribute \src "ls180.v:2194.12-2194.40" + wire width 8 \builder_csrbank5_dma_base5_w + attribute \src "ls180.v:2193.6-2193.35" + wire \builder_csrbank5_dma_base5_we + attribute \src "ls180.v:2188.12-2188.40" + wire width 8 \builder_csrbank5_dma_base6_r + attribute \src "ls180.v:2187.6-2187.35" + wire \builder_csrbank5_dma_base6_re + attribute \src "ls180.v:2190.12-2190.40" + wire width 8 \builder_csrbank5_dma_base6_w + attribute \src "ls180.v:2189.6-2189.35" + wire \builder_csrbank5_dma_base6_we + attribute \src "ls180.v:2184.12-2184.40" + wire width 8 \builder_csrbank5_dma_base7_r + attribute \src "ls180.v:2183.6-2183.35" + wire \builder_csrbank5_dma_base7_re + attribute \src "ls180.v:2186.12-2186.40" + wire width 8 \builder_csrbank5_dma_base7_w + attribute \src "ls180.v:2185.6-2185.35" + wire \builder_csrbank5_dma_base7_we + attribute \src "ls180.v:2236.6-2236.33" + wire \builder_csrbank5_dma_done_r + attribute \src "ls180.v:2235.6-2235.34" + wire \builder_csrbank5_dma_done_re + attribute \src "ls180.v:2238.6-2238.33" + wire \builder_csrbank5_dma_done_w + attribute \src "ls180.v:2237.6-2237.34" + wire \builder_csrbank5_dma_done_we + attribute \src "ls180.v:2232.6-2232.36" + wire \builder_csrbank5_dma_enable0_r + attribute \src "ls180.v:2231.6-2231.37" + wire \builder_csrbank5_dma_enable0_re + attribute \src "ls180.v:2234.6-2234.36" + wire \builder_csrbank5_dma_enable0_w + attribute \src "ls180.v:2233.6-2233.37" + wire \builder_csrbank5_dma_enable0_we + attribute \src "ls180.v:2228.12-2228.42" + wire width 8 \builder_csrbank5_dma_length0_r + attribute \src "ls180.v:2227.6-2227.37" + wire \builder_csrbank5_dma_length0_re + attribute \src "ls180.v:2230.12-2230.42" + wire width 8 \builder_csrbank5_dma_length0_w + attribute \src "ls180.v:2229.6-2229.37" + wire \builder_csrbank5_dma_length0_we + attribute \src "ls180.v:2224.12-2224.42" + wire width 8 \builder_csrbank5_dma_length1_r + attribute \src "ls180.v:2223.6-2223.37" + wire \builder_csrbank5_dma_length1_re + attribute \src "ls180.v:2226.12-2226.42" + wire width 8 \builder_csrbank5_dma_length1_w + attribute \src "ls180.v:2225.6-2225.37" + wire \builder_csrbank5_dma_length1_we + attribute \src "ls180.v:2220.12-2220.42" + wire width 8 \builder_csrbank5_dma_length2_r + attribute \src "ls180.v:2219.6-2219.37" + wire \builder_csrbank5_dma_length2_re + attribute \src "ls180.v:2222.12-2222.42" + wire width 8 \builder_csrbank5_dma_length2_w + attribute \src "ls180.v:2221.6-2221.37" + wire \builder_csrbank5_dma_length2_we + attribute \src "ls180.v:2216.12-2216.42" + wire width 8 \builder_csrbank5_dma_length3_r + attribute \src "ls180.v:2215.6-2215.37" + wire \builder_csrbank5_dma_length3_re + attribute \src "ls180.v:2218.12-2218.42" + wire width 8 \builder_csrbank5_dma_length3_w + attribute \src "ls180.v:2217.6-2217.37" + wire \builder_csrbank5_dma_length3_we + attribute \src "ls180.v:2240.6-2240.34" + wire \builder_csrbank5_dma_loop0_r + attribute \src "ls180.v:2239.6-2239.35" + wire \builder_csrbank5_dma_loop0_re + attribute \src "ls180.v:2242.6-2242.34" + wire \builder_csrbank5_dma_loop0_w + attribute \src "ls180.v:2241.6-2241.35" + wire \builder_csrbank5_dma_loop0_we + attribute \src "ls180.v:2243.6-2243.26" + wire \builder_csrbank5_sel + attribute \src "ls180.v:2373.12-2373.43" + wire width 8 \builder_csrbank6_block_count0_r + attribute \src "ls180.v:2372.6-2372.38" + wire \builder_csrbank6_block_count0_re + attribute \src "ls180.v:2375.12-2375.43" + wire width 8 \builder_csrbank6_block_count0_w + attribute \src "ls180.v:2374.6-2374.38" + wire \builder_csrbank6_block_count0_we + attribute \src "ls180.v:2369.12-2369.43" + wire width 8 \builder_csrbank6_block_count1_r + attribute \src "ls180.v:2368.6-2368.38" + wire \builder_csrbank6_block_count1_re + attribute \src "ls180.v:2371.12-2371.43" + wire width 8 \builder_csrbank6_block_count1_w + attribute \src "ls180.v:2370.6-2370.38" + wire \builder_csrbank6_block_count1_we + attribute \src "ls180.v:2365.12-2365.43" + wire width 8 \builder_csrbank6_block_count2_r + attribute \src "ls180.v:2364.6-2364.38" + wire \builder_csrbank6_block_count2_re + attribute \src "ls180.v:2367.12-2367.43" + wire width 8 \builder_csrbank6_block_count2_w + attribute \src "ls180.v:2366.6-2366.38" + wire \builder_csrbank6_block_count2_we + attribute \src "ls180.v:2361.12-2361.43" + wire width 8 \builder_csrbank6_block_count3_r + attribute \src "ls180.v:2360.6-2360.38" + wire \builder_csrbank6_block_count3_re + attribute \src "ls180.v:2363.12-2363.43" + wire width 8 \builder_csrbank6_block_count3_w + attribute \src "ls180.v:2362.6-2362.38" + wire \builder_csrbank6_block_count3_we + attribute \src "ls180.v:2357.12-2357.44" + wire width 8 \builder_csrbank6_block_length0_r + attribute \src "ls180.v:2356.6-2356.39" + wire \builder_csrbank6_block_length0_re + attribute \src "ls180.v:2359.12-2359.44" + wire width 8 \builder_csrbank6_block_length0_w + attribute \src "ls180.v:2358.6-2358.39" + wire \builder_csrbank6_block_length0_we + attribute \src "ls180.v:2353.12-2353.44" + wire width 2 \builder_csrbank6_block_length1_r + attribute \src "ls180.v:2352.6-2352.39" + wire \builder_csrbank6_block_length1_re + attribute \src "ls180.v:2355.12-2355.44" + wire width 2 \builder_csrbank6_block_length1_w + attribute \src "ls180.v:2354.6-2354.39" + wire \builder_csrbank6_block_length1_we + attribute \src "ls180.v:2261.12-2261.44" + wire width 8 \builder_csrbank6_cmd_argument0_r + attribute \src "ls180.v:2260.6-2260.39" + wire \builder_csrbank6_cmd_argument0_re + attribute \src "ls180.v:2263.12-2263.44" + wire width 8 \builder_csrbank6_cmd_argument0_w + attribute \src "ls180.v:2262.6-2262.39" + wire \builder_csrbank6_cmd_argument0_we + attribute \src "ls180.v:2257.12-2257.44" + wire width 8 \builder_csrbank6_cmd_argument1_r + attribute \src "ls180.v:2256.6-2256.39" + wire \builder_csrbank6_cmd_argument1_re + attribute \src "ls180.v:2259.12-2259.44" + wire width 8 \builder_csrbank6_cmd_argument1_w + attribute \src "ls180.v:2258.6-2258.39" + wire \builder_csrbank6_cmd_argument1_we + attribute \src "ls180.v:2253.12-2253.44" + wire width 8 \builder_csrbank6_cmd_argument2_r + attribute \src "ls180.v:2252.6-2252.39" + wire \builder_csrbank6_cmd_argument2_re + attribute \src "ls180.v:2255.12-2255.44" + wire width 8 \builder_csrbank6_cmd_argument2_w + attribute \src "ls180.v:2254.6-2254.39" + wire \builder_csrbank6_cmd_argument2_we + attribute \src "ls180.v:2249.12-2249.44" + wire width 8 \builder_csrbank6_cmd_argument3_r + attribute \src "ls180.v:2248.6-2248.39" + wire \builder_csrbank6_cmd_argument3_re + attribute \src "ls180.v:2251.12-2251.44" + wire width 8 \builder_csrbank6_cmd_argument3_w + attribute \src "ls180.v:2250.6-2250.39" + wire \builder_csrbank6_cmd_argument3_we + attribute \src "ls180.v:2277.12-2277.43" + wire width 8 \builder_csrbank6_cmd_command0_r + attribute \src "ls180.v:2276.6-2276.38" + wire \builder_csrbank6_cmd_command0_re + attribute \src "ls180.v:2279.12-2279.43" + wire width 8 \builder_csrbank6_cmd_command0_w + attribute \src "ls180.v:2278.6-2278.38" + wire \builder_csrbank6_cmd_command0_we + attribute \src "ls180.v:2273.12-2273.43" + wire width 8 \builder_csrbank6_cmd_command1_r + attribute \src "ls180.v:2272.6-2272.38" + wire \builder_csrbank6_cmd_command1_re + attribute \src "ls180.v:2275.12-2275.43" + wire width 8 \builder_csrbank6_cmd_command1_w + attribute \src "ls180.v:2274.6-2274.38" + wire \builder_csrbank6_cmd_command1_we + attribute \src "ls180.v:2269.12-2269.43" + wire width 8 \builder_csrbank6_cmd_command2_r + attribute \src "ls180.v:2268.6-2268.38" + wire \builder_csrbank6_cmd_command2_re + attribute \src "ls180.v:2271.12-2271.43" + wire width 8 \builder_csrbank6_cmd_command2_w + attribute \src "ls180.v:2270.6-2270.38" + wire \builder_csrbank6_cmd_command2_we + attribute \src "ls180.v:2265.12-2265.43" + wire width 8 \builder_csrbank6_cmd_command3_r + attribute \src "ls180.v:2264.6-2264.38" + wire \builder_csrbank6_cmd_command3_re + attribute \src "ls180.v:2267.12-2267.43" + wire width 8 \builder_csrbank6_cmd_command3_w + attribute \src "ls180.v:2266.6-2266.38" + wire \builder_csrbank6_cmd_command3_we + attribute \src "ls180.v:2345.12-2345.40" + wire width 4 \builder_csrbank6_cmd_event_r + attribute \src "ls180.v:2344.6-2344.35" + wire \builder_csrbank6_cmd_event_re + attribute \src "ls180.v:2347.12-2347.40" + wire width 4 \builder_csrbank6_cmd_event_w + attribute \src "ls180.v:2346.6-2346.35" + wire \builder_csrbank6_cmd_event_we + attribute \src "ls180.v:2341.12-2341.44" + wire width 8 \builder_csrbank6_cmd_response0_r + attribute \src "ls180.v:2340.6-2340.39" + wire \builder_csrbank6_cmd_response0_re + attribute \src "ls180.v:2343.12-2343.44" + wire width 8 \builder_csrbank6_cmd_response0_w + attribute \src "ls180.v:2342.6-2342.39" + wire \builder_csrbank6_cmd_response0_we + attribute \src "ls180.v:2301.12-2301.45" + wire width 8 \builder_csrbank6_cmd_response10_r + attribute \src "ls180.v:2300.6-2300.40" + wire \builder_csrbank6_cmd_response10_re + attribute \src "ls180.v:2303.12-2303.45" + wire width 8 \builder_csrbank6_cmd_response10_w + attribute \src "ls180.v:2302.6-2302.40" + wire \builder_csrbank6_cmd_response10_we + attribute \src "ls180.v:2297.12-2297.45" + wire width 8 \builder_csrbank6_cmd_response11_r + attribute \src "ls180.v:2296.6-2296.40" + wire \builder_csrbank6_cmd_response11_re + attribute \src "ls180.v:2299.12-2299.45" + wire width 8 \builder_csrbank6_cmd_response11_w + attribute \src "ls180.v:2298.6-2298.40" + wire \builder_csrbank6_cmd_response11_we + attribute \src "ls180.v:2293.12-2293.45" + wire width 8 \builder_csrbank6_cmd_response12_r + attribute \src "ls180.v:2292.6-2292.40" + wire \builder_csrbank6_cmd_response12_re + attribute \src "ls180.v:2295.12-2295.45" + wire width 8 \builder_csrbank6_cmd_response12_w + attribute \src "ls180.v:2294.6-2294.40" + wire \builder_csrbank6_cmd_response12_we + attribute \src "ls180.v:2289.12-2289.45" + wire width 8 \builder_csrbank6_cmd_response13_r + attribute \src "ls180.v:2288.6-2288.40" + wire \builder_csrbank6_cmd_response13_re + attribute \src "ls180.v:2291.12-2291.45" + wire width 8 \builder_csrbank6_cmd_response13_w + attribute \src "ls180.v:2290.6-2290.40" + wire \builder_csrbank6_cmd_response13_we + attribute \src "ls180.v:2285.12-2285.45" + wire width 8 \builder_csrbank6_cmd_response14_r + attribute \src "ls180.v:2284.6-2284.40" + wire \builder_csrbank6_cmd_response14_re + attribute \src "ls180.v:2287.12-2287.45" + wire width 8 \builder_csrbank6_cmd_response14_w + attribute \src "ls180.v:2286.6-2286.40" + wire \builder_csrbank6_cmd_response14_we + attribute \src "ls180.v:2281.12-2281.45" + wire width 8 \builder_csrbank6_cmd_response15_r + attribute \src "ls180.v:2280.6-2280.40" + wire \builder_csrbank6_cmd_response15_re + attribute \src "ls180.v:2283.12-2283.45" + wire width 8 \builder_csrbank6_cmd_response15_w + attribute \src "ls180.v:2282.6-2282.40" + wire \builder_csrbank6_cmd_response15_we + attribute \src "ls180.v:2337.12-2337.44" + wire width 8 \builder_csrbank6_cmd_response1_r + attribute \src "ls180.v:2336.6-2336.39" + wire \builder_csrbank6_cmd_response1_re + attribute \src "ls180.v:2339.12-2339.44" + wire width 8 \builder_csrbank6_cmd_response1_w + attribute \src "ls180.v:2338.6-2338.39" + wire \builder_csrbank6_cmd_response1_we + attribute \src "ls180.v:2333.12-2333.44" + wire width 8 \builder_csrbank6_cmd_response2_r + attribute \src "ls180.v:2332.6-2332.39" + wire \builder_csrbank6_cmd_response2_re + attribute \src "ls180.v:2335.12-2335.44" + wire width 8 \builder_csrbank6_cmd_response2_w + attribute \src "ls180.v:2334.6-2334.39" + wire \builder_csrbank6_cmd_response2_we + attribute \src "ls180.v:2329.12-2329.44" + wire width 8 \builder_csrbank6_cmd_response3_r + attribute \src "ls180.v:2328.6-2328.39" + wire \builder_csrbank6_cmd_response3_re + attribute \src "ls180.v:2331.12-2331.44" + wire width 8 \builder_csrbank6_cmd_response3_w + attribute \src "ls180.v:2330.6-2330.39" + wire \builder_csrbank6_cmd_response3_we + attribute \src "ls180.v:2325.12-2325.44" + wire width 8 \builder_csrbank6_cmd_response4_r + attribute \src "ls180.v:2324.6-2324.39" + wire \builder_csrbank6_cmd_response4_re + attribute \src "ls180.v:2327.12-2327.44" + wire width 8 \builder_csrbank6_cmd_response4_w + attribute \src "ls180.v:2326.6-2326.39" + wire \builder_csrbank6_cmd_response4_we + attribute \src "ls180.v:2321.12-2321.44" + wire width 8 \builder_csrbank6_cmd_response5_r + attribute \src "ls180.v:2320.6-2320.39" + wire \builder_csrbank6_cmd_response5_re + attribute \src "ls180.v:2323.12-2323.44" + wire width 8 \builder_csrbank6_cmd_response5_w + attribute \src "ls180.v:2322.6-2322.39" + wire \builder_csrbank6_cmd_response5_we + attribute \src "ls180.v:2317.12-2317.44" + wire width 8 \builder_csrbank6_cmd_response6_r + attribute \src "ls180.v:2316.6-2316.39" + wire \builder_csrbank6_cmd_response6_re + attribute \src "ls180.v:2319.12-2319.44" + wire width 8 \builder_csrbank6_cmd_response6_w + attribute \src "ls180.v:2318.6-2318.39" + wire \builder_csrbank6_cmd_response6_we + attribute \src "ls180.v:2313.12-2313.44" + wire width 8 \builder_csrbank6_cmd_response7_r + attribute \src "ls180.v:2312.6-2312.39" + wire \builder_csrbank6_cmd_response7_re + attribute \src "ls180.v:2315.12-2315.44" + wire width 8 \builder_csrbank6_cmd_response7_w + attribute \src "ls180.v:2314.6-2314.39" + wire \builder_csrbank6_cmd_response7_we + attribute \src "ls180.v:2309.12-2309.44" + wire width 8 \builder_csrbank6_cmd_response8_r + attribute \src "ls180.v:2308.6-2308.39" + wire \builder_csrbank6_cmd_response8_re + attribute \src "ls180.v:2311.12-2311.44" + wire width 8 \builder_csrbank6_cmd_response8_w + attribute \src "ls180.v:2310.6-2310.39" + wire \builder_csrbank6_cmd_response8_we + attribute \src "ls180.v:2305.12-2305.44" + wire width 8 \builder_csrbank6_cmd_response9_r + attribute \src "ls180.v:2304.6-2304.39" + wire \builder_csrbank6_cmd_response9_re + attribute \src "ls180.v:2307.12-2307.44" + wire width 8 \builder_csrbank6_cmd_response9_w + attribute \src "ls180.v:2306.6-2306.39" + wire \builder_csrbank6_cmd_response9_we + attribute \src "ls180.v:2349.12-2349.41" + wire width 4 \builder_csrbank6_data_event_r + attribute \src "ls180.v:2348.6-2348.36" + wire \builder_csrbank6_data_event_re + attribute \src "ls180.v:2351.12-2351.41" + wire width 4 \builder_csrbank6_data_event_w + attribute \src "ls180.v:2350.6-2350.36" + wire \builder_csrbank6_data_event_we + attribute \src "ls180.v:2376.6-2376.26" + wire \builder_csrbank6_sel + attribute \src "ls180.v:2410.12-2410.40" + wire width 8 \builder_csrbank7_dma_base0_r + attribute \src "ls180.v:2409.6-2409.35" + wire \builder_csrbank7_dma_base0_re + attribute \src "ls180.v:2412.12-2412.40" + wire width 8 \builder_csrbank7_dma_base0_w + attribute \src "ls180.v:2411.6-2411.35" + wire \builder_csrbank7_dma_base0_we + attribute \src "ls180.v:2406.12-2406.40" + wire width 8 \builder_csrbank7_dma_base1_r + attribute \src "ls180.v:2405.6-2405.35" + wire \builder_csrbank7_dma_base1_re + attribute \src "ls180.v:2408.12-2408.40" + wire width 8 \builder_csrbank7_dma_base1_w + attribute \src "ls180.v:2407.6-2407.35" + wire \builder_csrbank7_dma_base1_we + attribute \src "ls180.v:2402.12-2402.40" + wire width 8 \builder_csrbank7_dma_base2_r + attribute \src "ls180.v:2401.6-2401.35" + wire \builder_csrbank7_dma_base2_re + attribute \src "ls180.v:2404.12-2404.40" + wire width 8 \builder_csrbank7_dma_base2_w + attribute \src "ls180.v:2403.6-2403.35" + wire \builder_csrbank7_dma_base2_we + attribute \src "ls180.v:2398.12-2398.40" + wire width 8 \builder_csrbank7_dma_base3_r + attribute \src "ls180.v:2397.6-2397.35" + wire \builder_csrbank7_dma_base3_re + attribute \src "ls180.v:2400.12-2400.40" + wire width 8 \builder_csrbank7_dma_base3_w + attribute \src "ls180.v:2399.6-2399.35" + wire \builder_csrbank7_dma_base3_we + attribute \src "ls180.v:2394.12-2394.40" + wire width 8 \builder_csrbank7_dma_base4_r + attribute \src "ls180.v:2393.6-2393.35" + wire \builder_csrbank7_dma_base4_re + attribute \src "ls180.v:2396.12-2396.40" + wire width 8 \builder_csrbank7_dma_base4_w + attribute \src "ls180.v:2395.6-2395.35" + wire \builder_csrbank7_dma_base4_we + attribute \src "ls180.v:2390.12-2390.40" + wire width 8 \builder_csrbank7_dma_base5_r + attribute \src "ls180.v:2389.6-2389.35" + wire \builder_csrbank7_dma_base5_re + attribute \src "ls180.v:2392.12-2392.40" + wire width 8 \builder_csrbank7_dma_base5_w + attribute \src "ls180.v:2391.6-2391.35" + wire \builder_csrbank7_dma_base5_we + attribute \src "ls180.v:2386.12-2386.40" + wire width 8 \builder_csrbank7_dma_base6_r + attribute \src "ls180.v:2385.6-2385.35" + wire \builder_csrbank7_dma_base6_re + attribute \src "ls180.v:2388.12-2388.40" + wire width 8 \builder_csrbank7_dma_base6_w + attribute \src "ls180.v:2387.6-2387.35" + wire \builder_csrbank7_dma_base6_we + attribute \src "ls180.v:2382.12-2382.40" + wire width 8 \builder_csrbank7_dma_base7_r + attribute \src "ls180.v:2381.6-2381.35" + wire \builder_csrbank7_dma_base7_re + attribute \src "ls180.v:2384.12-2384.40" + wire width 8 \builder_csrbank7_dma_base7_w + attribute \src "ls180.v:2383.6-2383.35" + wire \builder_csrbank7_dma_base7_we + attribute \src "ls180.v:2434.6-2434.33" + wire \builder_csrbank7_dma_done_r + attribute \src "ls180.v:2433.6-2433.34" + wire \builder_csrbank7_dma_done_re + attribute \src "ls180.v:2436.6-2436.33" + wire \builder_csrbank7_dma_done_w + attribute \src "ls180.v:2435.6-2435.34" + wire \builder_csrbank7_dma_done_we + attribute \src "ls180.v:2430.6-2430.36" + wire \builder_csrbank7_dma_enable0_r + attribute \src "ls180.v:2429.6-2429.37" + wire \builder_csrbank7_dma_enable0_re + attribute \src "ls180.v:2432.6-2432.36" + wire \builder_csrbank7_dma_enable0_w + attribute \src "ls180.v:2431.6-2431.37" + wire \builder_csrbank7_dma_enable0_we + attribute \src "ls180.v:2426.12-2426.42" + wire width 8 \builder_csrbank7_dma_length0_r + attribute \src "ls180.v:2425.6-2425.37" + wire \builder_csrbank7_dma_length0_re + attribute \src "ls180.v:2428.12-2428.42" + wire width 8 \builder_csrbank7_dma_length0_w + attribute \src "ls180.v:2427.6-2427.37" + wire \builder_csrbank7_dma_length0_we + attribute \src "ls180.v:2422.12-2422.42" + wire width 8 \builder_csrbank7_dma_length1_r + attribute \src "ls180.v:2421.6-2421.37" + wire \builder_csrbank7_dma_length1_re + attribute \src "ls180.v:2424.12-2424.42" + wire width 8 \builder_csrbank7_dma_length1_w + attribute \src "ls180.v:2423.6-2423.37" + wire \builder_csrbank7_dma_length1_we + attribute \src "ls180.v:2418.12-2418.42" + wire width 8 \builder_csrbank7_dma_length2_r + attribute \src "ls180.v:2417.6-2417.37" + wire \builder_csrbank7_dma_length2_re + attribute \src "ls180.v:2420.12-2420.42" + wire width 8 \builder_csrbank7_dma_length2_w + attribute \src "ls180.v:2419.6-2419.37" + wire \builder_csrbank7_dma_length2_we + attribute \src "ls180.v:2414.12-2414.42" + wire width 8 \builder_csrbank7_dma_length3_r + attribute \src "ls180.v:2413.6-2413.37" + wire \builder_csrbank7_dma_length3_re + attribute \src "ls180.v:2416.12-2416.42" + wire width 8 \builder_csrbank7_dma_length3_w + attribute \src "ls180.v:2415.6-2415.37" + wire \builder_csrbank7_dma_length3_we + attribute \src "ls180.v:2438.6-2438.34" + wire \builder_csrbank7_dma_loop0_r + attribute \src "ls180.v:2437.6-2437.35" + wire \builder_csrbank7_dma_loop0_re + attribute \src "ls180.v:2440.6-2440.34" + wire \builder_csrbank7_dma_loop0_w + attribute \src "ls180.v:2439.6-2439.35" + wire \builder_csrbank7_dma_loop0_we + attribute \src "ls180.v:2454.12-2454.42" + wire width 8 \builder_csrbank7_dma_offset0_r + attribute \src "ls180.v:2453.6-2453.37" + wire \builder_csrbank7_dma_offset0_re + attribute \src "ls180.v:2456.12-2456.42" + wire width 8 \builder_csrbank7_dma_offset0_w + attribute \src "ls180.v:2455.6-2455.37" + wire \builder_csrbank7_dma_offset0_we + attribute \src "ls180.v:2450.12-2450.42" + wire width 8 \builder_csrbank7_dma_offset1_r + attribute \src "ls180.v:2449.6-2449.37" + wire \builder_csrbank7_dma_offset1_re + attribute \src "ls180.v:2452.12-2452.42" + wire width 8 \builder_csrbank7_dma_offset1_w + attribute \src "ls180.v:2451.6-2451.37" + wire \builder_csrbank7_dma_offset1_we + attribute \src "ls180.v:2446.12-2446.42" + wire width 8 \builder_csrbank7_dma_offset2_r + attribute \src "ls180.v:2445.6-2445.37" + wire \builder_csrbank7_dma_offset2_re + attribute \src "ls180.v:2448.12-2448.42" + wire width 8 \builder_csrbank7_dma_offset2_w + attribute \src "ls180.v:2447.6-2447.37" + wire \builder_csrbank7_dma_offset2_we + attribute \src "ls180.v:2442.12-2442.42" + wire width 8 \builder_csrbank7_dma_offset3_r + attribute \src "ls180.v:2441.6-2441.37" + wire \builder_csrbank7_dma_offset3_re + attribute \src "ls180.v:2444.12-2444.42" + wire width 8 \builder_csrbank7_dma_offset3_w + attribute \src "ls180.v:2443.6-2443.37" + wire \builder_csrbank7_dma_offset3_we + attribute \src "ls180.v:2457.6-2457.26" + wire \builder_csrbank7_sel + attribute \src "ls180.v:2463.6-2463.36" + wire \builder_csrbank8_card_detect_r + attribute \src "ls180.v:2462.6-2462.37" + wire \builder_csrbank8_card_detect_re + attribute \src "ls180.v:2465.6-2465.36" + wire \builder_csrbank8_card_detect_w + attribute \src "ls180.v:2464.6-2464.37" + wire \builder_csrbank8_card_detect_we + attribute \src "ls180.v:2471.12-2471.47" + wire width 8 \builder_csrbank8_clocker_divider0_r + attribute \src "ls180.v:2470.6-2470.42" + wire \builder_csrbank8_clocker_divider0_re + attribute \src "ls180.v:2473.12-2473.47" + wire width 8 \builder_csrbank8_clocker_divider0_w + attribute \src "ls180.v:2472.6-2472.42" + wire \builder_csrbank8_clocker_divider0_we + attribute \src "ls180.v:2467.6-2467.41" + wire \builder_csrbank8_clocker_divider1_r + attribute \src "ls180.v:2466.6-2466.42" + wire \builder_csrbank8_clocker_divider1_re + attribute \src "ls180.v:2469.6-2469.41" + wire \builder_csrbank8_clocker_divider1_w + attribute \src "ls180.v:2468.6-2468.42" + wire \builder_csrbank8_clocker_divider1_we + attribute \src "ls180.v:2474.6-2474.26" + wire \builder_csrbank8_sel + attribute \src "ls180.v:2480.12-2480.44" + wire width 4 \builder_csrbank9_dfii_control0_r + attribute \src "ls180.v:2479.6-2479.39" + wire \builder_csrbank9_dfii_control0_re + attribute \src "ls180.v:2482.12-2482.44" + wire width 4 \builder_csrbank9_dfii_control0_w + attribute \src "ls180.v:2481.6-2481.39" + wire \builder_csrbank9_dfii_control0_we + attribute \src "ls180.v:2492.12-2492.48" + wire width 8 \builder_csrbank9_dfii_pi0_address0_r + attribute \src "ls180.v:2491.6-2491.43" + wire \builder_csrbank9_dfii_pi0_address0_re + attribute \src "ls180.v:2494.12-2494.48" + wire width 8 \builder_csrbank9_dfii_pi0_address0_w + attribute \src "ls180.v:2493.6-2493.43" + wire \builder_csrbank9_dfii_pi0_address0_we + attribute \src "ls180.v:2488.12-2488.48" + wire width 5 \builder_csrbank9_dfii_pi0_address1_r + attribute \src "ls180.v:2487.6-2487.43" + wire \builder_csrbank9_dfii_pi0_address1_re + attribute \src "ls180.v:2490.12-2490.48" + wire width 5 \builder_csrbank9_dfii_pi0_address1_w + attribute \src "ls180.v:2489.6-2489.43" + wire \builder_csrbank9_dfii_pi0_address1_we + attribute \src "ls180.v:2496.12-2496.49" + wire width 2 \builder_csrbank9_dfii_pi0_baddress0_r + attribute \src "ls180.v:2495.6-2495.44" + wire \builder_csrbank9_dfii_pi0_baddress0_re + attribute \src "ls180.v:2498.12-2498.49" + wire width 2 \builder_csrbank9_dfii_pi0_baddress0_w + attribute \src "ls180.v:2497.6-2497.44" + wire \builder_csrbank9_dfii_pi0_baddress0_we + attribute \src "ls180.v:2484.12-2484.48" + wire width 6 \builder_csrbank9_dfii_pi0_command0_r + attribute \src "ls180.v:2483.6-2483.43" + wire \builder_csrbank9_dfii_pi0_command0_re + attribute \src "ls180.v:2486.12-2486.48" + wire width 6 \builder_csrbank9_dfii_pi0_command0_w + attribute \src "ls180.v:2485.6-2485.43" + wire \builder_csrbank9_dfii_pi0_command0_we + attribute \src "ls180.v:2512.12-2512.47" + wire width 8 \builder_csrbank9_dfii_pi0_rddata0_r + attribute \src "ls180.v:2511.6-2511.42" + wire \builder_csrbank9_dfii_pi0_rddata0_re + attribute \src "ls180.v:2514.12-2514.47" + wire width 8 \builder_csrbank9_dfii_pi0_rddata0_w + attribute \src "ls180.v:2513.6-2513.42" + wire \builder_csrbank9_dfii_pi0_rddata0_we + attribute \src "ls180.v:2508.12-2508.47" + wire width 8 \builder_csrbank9_dfii_pi0_rddata1_r + attribute \src "ls180.v:2507.6-2507.42" + wire \builder_csrbank9_dfii_pi0_rddata1_re + attribute \src "ls180.v:2510.12-2510.47" + wire width 8 \builder_csrbank9_dfii_pi0_rddata1_w + attribute \src "ls180.v:2509.6-2509.42" + wire \builder_csrbank9_dfii_pi0_rddata1_we + attribute \src "ls180.v:2504.12-2504.47" + wire width 8 \builder_csrbank9_dfii_pi0_wrdata0_r + attribute \src "ls180.v:2503.6-2503.42" + wire \builder_csrbank9_dfii_pi0_wrdata0_re + attribute \src "ls180.v:2506.12-2506.47" + wire width 8 \builder_csrbank9_dfii_pi0_wrdata0_w + attribute \src "ls180.v:2505.6-2505.42" + wire \builder_csrbank9_dfii_pi0_wrdata0_we + attribute \src "ls180.v:2500.12-2500.47" + wire width 8 \builder_csrbank9_dfii_pi0_wrdata1_r + attribute \src "ls180.v:2499.6-2499.42" + wire \builder_csrbank9_dfii_pi0_wrdata1_re + attribute \src "ls180.v:2502.12-2502.47" + wire width 8 \builder_csrbank9_dfii_pi0_wrdata1_w + attribute \src "ls180.v:2501.6-2501.42" + wire \builder_csrbank9_dfii_pi0_wrdata1_we + attribute \src "ls180.v:2515.6-2515.26" + wire \builder_csrbank9_sel + attribute \src "ls180.v:2012.6-2012.18" + wire \builder_done + attribute \src "ls180.v:2010.5-2010.18" + wire \builder_error + attribute \src "ls180.v:2007.11-2007.24" + wire width 3 \builder_grant + attribute \src "ls180.v:2014.13-2014.44" + wire width 14 \builder_interface0_bank_bus_adr + attribute \src "ls180.v:2017.11-2017.44" + wire width 8 \builder_interface0_bank_bus_dat_r + attribute \src "ls180.v:2016.12-2016.45" + wire width 8 \builder_interface0_bank_bus_dat_w + attribute \src "ls180.v:2015.6-2015.36" + wire \builder_interface0_bank_bus_we + attribute \src "ls180.v:2516.13-2516.45" + wire width 14 \builder_interface10_bank_bus_adr + attribute \src "ls180.v:2519.11-2519.45" + wire width 8 \builder_interface10_bank_bus_dat_r + attribute \src "ls180.v:2518.12-2518.46" + wire width 8 \builder_interface10_bank_bus_dat_w + attribute \src "ls180.v:2517.6-2517.37" + wire \builder_interface10_bank_bus_we + attribute \src "ls180.v:2549.13-2549.45" + wire width 14 \builder_interface11_bank_bus_adr + attribute \src "ls180.v:2552.11-2552.45" + wire width 8 \builder_interface11_bank_bus_dat_r + attribute \src "ls180.v:2551.12-2551.46" + wire width 8 \builder_interface11_bank_bus_dat_w + attribute \src "ls180.v:2550.6-2550.37" + wire \builder_interface11_bank_bus_we + attribute \src "ls180.v:2590.13-2590.45" + wire width 14 \builder_interface12_bank_bus_adr + attribute \src "ls180.v:2593.11-2593.45" + wire width 8 \builder_interface12_bank_bus_dat_r + attribute \src "ls180.v:2592.12-2592.46" + wire width 8 \builder_interface12_bank_bus_dat_w + attribute \src "ls180.v:2591.6-2591.37" + wire \builder_interface12_bank_bus_we + attribute \src "ls180.v:2655.13-2655.45" + wire width 14 \builder_interface13_bank_bus_adr + attribute \src "ls180.v:2658.11-2658.45" + wire width 8 \builder_interface13_bank_bus_dat_r + attribute \src "ls180.v:2657.12-2657.46" + wire width 8 \builder_interface13_bank_bus_dat_w + attribute \src "ls180.v:2656.6-2656.37" + wire \builder_interface13_bank_bus_we + attribute \src "ls180.v:2680.13-2680.45" + wire width 14 \builder_interface14_bank_bus_adr + attribute \src "ls180.v:2683.11-2683.45" + wire width 8 \builder_interface14_bank_bus_dat_r + attribute \src "ls180.v:2682.12-2682.46" + wire width 8 \builder_interface14_bank_bus_dat_w + attribute \src "ls180.v:2681.6-2681.37" + wire \builder_interface14_bank_bus_we + attribute \src "ls180.v:2055.13-2055.44" + wire width 14 \builder_interface1_bank_bus_adr + attribute \src "ls180.v:2058.11-2058.44" + wire width 8 \builder_interface1_bank_bus_dat_r + attribute \src "ls180.v:2057.12-2057.45" + wire width 8 \builder_interface1_bank_bus_dat_w + attribute \src "ls180.v:2056.6-2056.36" + wire \builder_interface1_bank_bus_we + attribute \src "ls180.v:2084.13-2084.44" + wire width 14 \builder_interface2_bank_bus_adr + attribute \src "ls180.v:2087.11-2087.44" + wire width 8 \builder_interface2_bank_bus_dat_r + attribute \src "ls180.v:2086.12-2086.45" + wire width 8 \builder_interface2_bank_bus_dat_w + attribute \src "ls180.v:2085.6-2085.36" + wire \builder_interface2_bank_bus_we + attribute \src "ls180.v:2097.13-2097.44" + wire width 14 \builder_interface3_bank_bus_adr + attribute \src "ls180.v:2100.11-2100.44" + wire width 8 \builder_interface3_bank_bus_dat_r + attribute \src "ls180.v:2099.12-2099.45" + wire width 8 \builder_interface3_bank_bus_dat_w + attribute \src "ls180.v:2098.6-2098.36" + wire \builder_interface3_bank_bus_we + attribute \src "ls180.v:2138.13-2138.44" + wire width 14 \builder_interface4_bank_bus_adr + attribute \src "ls180.v:2141.11-2141.44" + wire width 8 \builder_interface4_bank_bus_dat_r + attribute \src "ls180.v:2140.12-2140.45" + wire width 8 \builder_interface4_bank_bus_dat_w + attribute \src "ls180.v:2139.6-2139.36" + wire \builder_interface4_bank_bus_we + attribute \src "ls180.v:2179.13-2179.44" + wire width 14 \builder_interface5_bank_bus_adr + attribute \src "ls180.v:2182.11-2182.44" + wire width 8 \builder_interface5_bank_bus_dat_r + attribute \src "ls180.v:2181.12-2181.45" + wire width 8 \builder_interface5_bank_bus_dat_w + attribute \src "ls180.v:2180.6-2180.36" + wire \builder_interface5_bank_bus_we + attribute \src "ls180.v:2244.13-2244.44" + wire width 14 \builder_interface6_bank_bus_adr + attribute \src "ls180.v:2247.11-2247.44" + wire width 8 \builder_interface6_bank_bus_dat_r + attribute \src "ls180.v:2246.12-2246.45" + wire width 8 \builder_interface6_bank_bus_dat_w + attribute \src "ls180.v:2245.6-2245.36" + wire \builder_interface6_bank_bus_we + attribute \src "ls180.v:2377.13-2377.44" + wire width 14 \builder_interface7_bank_bus_adr + attribute \src "ls180.v:2380.11-2380.44" + wire width 8 \builder_interface7_bank_bus_dat_r + attribute \src "ls180.v:2379.12-2379.45" + wire width 8 \builder_interface7_bank_bus_dat_w + attribute \src "ls180.v:2378.6-2378.36" + wire \builder_interface7_bank_bus_we + attribute \src "ls180.v:2458.13-2458.44" + wire width 14 \builder_interface8_bank_bus_adr + attribute \src "ls180.v:2461.11-2461.44" + wire width 8 \builder_interface8_bank_bus_dat_r + attribute \src "ls180.v:2460.12-2460.45" + wire width 8 \builder_interface8_bank_bus_dat_w + attribute \src "ls180.v:2459.6-2459.36" + wire \builder_interface8_bank_bus_we + attribute \src "ls180.v:2475.13-2475.44" + wire width 14 \builder_interface9_bank_bus_adr + attribute \src "ls180.v:2478.11-2478.44" + wire width 8 \builder_interface9_bank_bus_dat_r + attribute \src "ls180.v:2477.12-2477.45" + wire width 8 \builder_interface9_bank_bus_dat_w + attribute \src "ls180.v:2476.6-2476.36" + wire \builder_interface9_bank_bus_we + attribute \src "ls180.v:1972.12-1972.35" + wire width 14 \builder_libresocsim_adr + attribute \src "ls180.v:2709.12-2709.47" + wire width 14 \builder_libresocsim_adr_next_value1 + attribute \src "ls180.v:2710.5-2710.43" + wire \builder_libresocsim_adr_next_value_ce1 + attribute \src "ls180.v:1990.5-1990.48" + wire \builder_libresocsim_converted_interface_ack + attribute \src "ls180.v:1984.13-1984.56" + wire width 30 \builder_libresocsim_converted_interface_adr + attribute \src "ls180.v:1993.12-1993.55" + wire width 2 \builder_libresocsim_converted_interface_bte + attribute \src "ls180.v:1992.12-1992.55" + wire width 3 \builder_libresocsim_converted_interface_cti + attribute \src "ls180.v:1988.6-1988.49" + wire \builder_libresocsim_converted_interface_cyc + attribute \src "ls180.v:1986.12-1986.57" + wire width 64 \builder_libresocsim_converted_interface_dat_r + attribute \src "ls180.v:1985.13-1985.58" + wire width 64 \builder_libresocsim_converted_interface_dat_w + attribute \src "ls180.v:1994.5-1994.48" + wire \builder_libresocsim_converted_interface_err + attribute \src "ls180.v:1987.12-1987.55" + wire width 8 \builder_libresocsim_converted_interface_sel + attribute \src "ls180.v:1989.6-1989.49" + wire \builder_libresocsim_converted_interface_stb + attribute \src "ls180.v:1991.6-1991.48" + wire \builder_libresocsim_converted_interface_we + attribute \src "ls180.v:1975.12-1975.37" + wire width 8 \builder_libresocsim_dat_r + attribute \src "ls180.v:1974.11-1974.36" + wire width 8 \builder_libresocsim_dat_w + attribute \src "ls180.v:2707.11-2707.48" + wire width 8 \builder_libresocsim_dat_w_next_value0 + attribute \src "ls180.v:2708.5-2708.45" + wire \builder_libresocsim_dat_w_next_value_ce0 + attribute \src "ls180.v:1973.5-1973.27" + wire \builder_libresocsim_we + attribute \src "ls180.v:2711.5-2711.39" + wire \builder_libresocsim_we_next_value2 + attribute \src "ls180.v:2712.5-2712.42" + wire \builder_libresocsim_we_next_value_ce2 + attribute \src "ls180.v:1982.5-1982.37" + wire \builder_libresocsim_wishbone_ack + attribute \src "ls180.v:1976.12-1976.44" + wire width 30 \builder_libresocsim_wishbone_adr + attribute \src "ls180.v:1980.5-1980.37" + wire \builder_libresocsim_wishbone_cyc + attribute \src "ls180.v:1978.12-1978.46" + wire width 32 \builder_libresocsim_wishbone_dat_r + attribute \src "ls180.v:1977.12-1977.46" + wire width 32 \builder_libresocsim_wishbone_dat_w + attribute \src "ls180.v:1979.11-1979.43" + wire width 4 \builder_libresocsim_wishbone_sel + attribute \src "ls180.v:1981.5-1981.37" + wire \builder_libresocsim_wishbone_stb + attribute \src "ls180.v:1983.5-1983.36" + wire \builder_libresocsim_wishbone_we + attribute \src "ls180.v:1875.5-1875.20" + wire \builder_locked0 + attribute \src "ls180.v:1876.5-1876.20" + wire \builder_locked1 + attribute \src "ls180.v:1877.5-1877.20" + wire \builder_locked2 + attribute \src "ls180.v:1878.5-1878.20" + wire \builder_locked3 + attribute \src "ls180.v:1862.11-1862.41" + wire width 3 \builder_multiplexer_next_state + attribute \src "ls180.v:1861.11-1861.36" + wire width 3 \builder_multiplexer_state + attribute \no_retiming "true" + attribute \src "ls180.v:2816.32-2816.59" + wire \builder_multiregimpl0_regs0 + attribute \no_retiming "true" + attribute \src "ls180.v:2817.32-2817.59" + wire \builder_multiregimpl0_regs1 + attribute \no_retiming "true" + attribute \src "ls180.v:2836.32-2836.60" + wire \builder_multiregimpl10_regs0 + attribute \no_retiming "true" + attribute \src "ls180.v:2837.32-2837.60" + wire \builder_multiregimpl10_regs1 + attribute \no_retiming "true" + attribute \src "ls180.v:2838.32-2838.60" + wire \builder_multiregimpl11_regs0 + attribute \no_retiming "true" + attribute \src "ls180.v:2839.32-2839.60" + wire \builder_multiregimpl11_regs1 + attribute \no_retiming "true" + attribute \src "ls180.v:2840.32-2840.60" + wire \builder_multiregimpl12_regs0 + attribute \no_retiming "true" + attribute \src "ls180.v:2841.32-2841.60" + wire \builder_multiregimpl12_regs1 + attribute \no_retiming "true" + attribute \src "ls180.v:2842.32-2842.60" + wire \builder_multiregimpl13_regs0 + attribute \no_retiming "true" + attribute \src "ls180.v:2843.32-2843.60" + wire \builder_multiregimpl13_regs1 + attribute \no_retiming "true" + attribute \src "ls180.v:2844.32-2844.60" + wire \builder_multiregimpl14_regs0 + attribute \no_retiming "true" + attribute \src "ls180.v:2845.32-2845.60" + wire \builder_multiregimpl14_regs1 + attribute \no_retiming "true" + attribute \src "ls180.v:2846.32-2846.60" + wire \builder_multiregimpl15_regs0 + attribute \no_retiming "true" + attribute \src "ls180.v:2847.32-2847.60" + wire \builder_multiregimpl15_regs1 + attribute \no_retiming "true" + attribute \src "ls180.v:2848.32-2848.60" + wire \builder_multiregimpl16_regs0 + attribute \no_retiming "true" + attribute \src "ls180.v:2849.32-2849.60" + wire \builder_multiregimpl16_regs1 + attribute \no_retiming "true" + attribute \src "ls180.v:2818.32-2818.59" + wire \builder_multiregimpl1_regs0 + attribute \no_retiming "true" + attribute \src "ls180.v:2819.32-2819.59" + wire \builder_multiregimpl1_regs1 + attribute \no_retiming "true" + attribute \src "ls180.v:2820.32-2820.59" + wire \builder_multiregimpl2_regs0 + attribute \no_retiming "true" + attribute \src "ls180.v:2821.32-2821.59" + wire \builder_multiregimpl2_regs1 + attribute \no_retiming "true" + attribute \src "ls180.v:2822.32-2822.59" + wire \builder_multiregimpl3_regs0 + attribute \no_retiming "true" + attribute \src "ls180.v:2823.32-2823.59" + wire \builder_multiregimpl3_regs1 + attribute \no_retiming "true" + attribute \src "ls180.v:2824.32-2824.59" + wire \builder_multiregimpl4_regs0 + attribute \no_retiming "true" + attribute \src "ls180.v:2825.32-2825.59" + wire \builder_multiregimpl4_regs1 + attribute \no_retiming "true" + attribute \src "ls180.v:2826.32-2826.59" + wire \builder_multiregimpl5_regs0 + attribute \no_retiming "true" + attribute \src "ls180.v:2827.32-2827.59" + wire \builder_multiregimpl5_regs1 + attribute \no_retiming "true" + attribute \src "ls180.v:2828.32-2828.59" + wire \builder_multiregimpl6_regs0 + attribute \no_retiming "true" + attribute \src "ls180.v:2829.32-2829.59" + wire \builder_multiregimpl6_regs1 + attribute \no_retiming "true" + attribute \src "ls180.v:2830.32-2830.59" + wire \builder_multiregimpl7_regs0 + attribute \no_retiming "true" + attribute \src "ls180.v:2831.32-2831.59" + wire \builder_multiregimpl7_regs1 + attribute \no_retiming "true" + attribute \src "ls180.v:2832.32-2832.59" + wire \builder_multiregimpl8_regs0 + attribute \no_retiming "true" + attribute \src "ls180.v:2833.32-2833.59" + wire \builder_multiregimpl8_regs1 + attribute \no_retiming "true" + attribute \src "ls180.v:2834.32-2834.59" + wire \builder_multiregimpl9_regs0 + attribute \no_retiming "true" + attribute \src "ls180.v:2835.32-2835.59" + wire \builder_multiregimpl9_regs1 + attribute \src "ls180.v:1880.5-1880.36" + wire \builder_new_master_rdata_valid0 + attribute \src "ls180.v:1881.5-1881.36" + wire \builder_new_master_rdata_valid1 + attribute \src "ls180.v:1882.5-1882.36" + wire \builder_new_master_rdata_valid2 + attribute \src "ls180.v:1883.5-1883.36" + wire \builder_new_master_rdata_valid3 + attribute \src "ls180.v:1879.5-1879.35" + wire \builder_new_master_wdata_ready + attribute \src "ls180.v:2706.11-2706.29" + wire width 2 \builder_next_state + attribute \src "ls180.v:1852.11-1852.39" + wire width 2 \builder_refresher_next_state + attribute \src "ls180.v:1851.11-1851.34" + wire width 2 \builder_refresher_state + attribute \src "ls180.v:2006.12-2006.27" + wire width 5 \builder_request + attribute \src "ls180.v:1865.6-1865.28" + wire \builder_roundrobin0_ce + attribute \src "ls180.v:1864.6-1864.31" + wire \builder_roundrobin0_grant + attribute \src "ls180.v:1863.6-1863.33" + wire \builder_roundrobin0_request + attribute \src "ls180.v:1868.6-1868.28" + wire \builder_roundrobin1_ce + attribute \src "ls180.v:1867.6-1867.31" + wire \builder_roundrobin1_grant + attribute \src "ls180.v:1866.6-1866.33" + wire \builder_roundrobin1_request + attribute \src "ls180.v:1871.6-1871.28" + wire \builder_roundrobin2_ce + attribute \src "ls180.v:1870.6-1870.31" + wire \builder_roundrobin2_grant + attribute \src "ls180.v:1869.6-1869.33" + wire \builder_roundrobin2_request + attribute \src "ls180.v:1874.6-1874.28" + wire \builder_roundrobin3_ce + attribute \src "ls180.v:1873.6-1873.31" + wire \builder_roundrobin3_grant + attribute \src "ls180.v:1872.6-1872.33" + wire \builder_roundrobin3_request + attribute \src "ls180.v:1961.11-1961.44" + wire width 2 \builder_sdblock2memdma_next_state + attribute \src "ls180.v:1960.11-1960.39" + wire width 2 \builder_sdblock2memdma_state + attribute \src "ls180.v:1929.5-1929.50" + wire \builder_sdcore_crcupstreaminserter_next_state + attribute \src "ls180.v:1928.5-1928.45" + wire \builder_sdcore_crcupstreaminserter_state + attribute \src "ls180.v:1941.11-1941.40" + wire width 3 \builder_sdcore_fsm_next_state + attribute \src "ls180.v:1940.11-1940.35" + wire width 3 \builder_sdcore_fsm_state + attribute \src "ls180.v:1965.5-1965.42" + wire \builder_sdmem2blockdma_fsm_next_state + attribute \src "ls180.v:1964.5-1964.37" + wire \builder_sdmem2blockdma_fsm_state + attribute \src "ls180.v:1969.11-1969.58" + wire width 2 \builder_sdmem2blockdma_resetinserter_next_state + attribute \src "ls180.v:1968.11-1968.53" + wire width 2 \builder_sdmem2blockdma_resetinserter_state + attribute \src "ls180.v:1917.11-1917.39" + wire width 3 \builder_sdphy_fsm_next_state + attribute \src "ls180.v:1916.11-1916.34" + wire width 3 \builder_sdphy_fsm_state + attribute \src "ls180.v:1905.11-1905.45" + wire width 3 \builder_sdphy_sdphycmdr_next_state + attribute \src "ls180.v:1904.11-1904.40" + wire width 3 \builder_sdphy_sdphycmdr_state + attribute \src "ls180.v:1901.11-1901.45" + wire width 2 \builder_sdphy_sdphycmdw_next_state + attribute \src "ls180.v:1900.11-1900.40" + wire width 2 \builder_sdphy_sdphycmdw_state + attribute \src "ls180.v:1913.5-1913.39" + wire \builder_sdphy_sdphycrcr_next_state + attribute \src "ls180.v:1912.5-1912.34" + wire \builder_sdphy_sdphycrcr_state + attribute \src "ls180.v:1921.11-1921.46" + wire width 3 \builder_sdphy_sdphydatar_next_state + attribute \src "ls180.v:1920.11-1920.41" + wire width 3 \builder_sdphy_sdphydatar_state + attribute \src "ls180.v:1897.5-1897.39" + wire \builder_sdphy_sdphyinit_next_state + attribute \src "ls180.v:1896.5-1896.34" + wire \builder_sdphy_sdphyinit_state + attribute \src "ls180.v:2001.5-2001.23" + wire \builder_shared_ack + attribute \src "ls180.v:1995.13-1995.31" + wire width 30 \builder_shared_adr + attribute \src "ls180.v:2004.12-2004.30" + wire width 2 \builder_shared_bte + attribute \src "ls180.v:2003.12-2003.30" + wire width 3 \builder_shared_cti + attribute \src "ls180.v:1999.6-1999.24" + wire \builder_shared_cyc + attribute \src "ls180.v:1997.12-1997.32" + wire width 32 \builder_shared_dat_r + attribute \src "ls180.v:1996.13-1996.33" + wire width 32 \builder_shared_dat_w + attribute \src "ls180.v:2005.6-2005.24" + wire \builder_shared_err + attribute \src "ls180.v:1998.12-1998.30" + wire width 4 \builder_shared_sel + attribute \src "ls180.v:2000.6-2000.24" + wire \builder_shared_stb + attribute \src "ls180.v:2002.6-2002.23" + wire \builder_shared_we + attribute \src "ls180.v:2008.12-2008.29" + wire width 13 \builder_slave_sel + attribute \src "ls180.v:2009.12-2009.31" + wire width 13 \builder_slave_sel_r + attribute \src "ls180.v:1889.11-1889.40" + wire width 2 \builder_spimaster0_next_state + attribute \src "ls180.v:1888.11-1888.35" + wire width 2 \builder_spimaster0_state + attribute \src "ls180.v:1893.11-1893.40" + wire width 2 \builder_spimaster1_next_state + attribute \src "ls180.v:1892.11-1892.35" + wire width 2 \builder_spimaster1_state + attribute \src "ls180.v:2705.11-2705.24" + wire width 2 \builder_state + attribute \src "ls180.v:2758.5-2758.32" + wire \builder_sync_f_array_muxed0 + attribute \src "ls180.v:2759.5-2759.32" + wire \builder_sync_f_array_muxed1 + attribute \src "ls180.v:2751.11-2751.40" + wire width 2 \builder_sync_rhs_array_muxed0 + attribute \src "ls180.v:2752.12-2752.41" + wire width 13 \builder_sync_rhs_array_muxed1 + attribute \src "ls180.v:2753.5-2753.34" + wire \builder_sync_rhs_array_muxed2 + attribute \src "ls180.v:2754.5-2754.34" + wire \builder_sync_rhs_array_muxed3 + attribute \src "ls180.v:2755.5-2755.34" + wire \builder_sync_rhs_array_muxed4 + attribute \src "ls180.v:2756.5-2756.34" + wire \builder_sync_rhs_array_muxed5 + attribute \src "ls180.v:2757.5-2757.34" + wire \builder_sync_rhs_array_muxed6 + attribute \src "ls180.v:2011.6-2011.18" + wire \builder_wait + attribute \src "ls180.v:5.19-5.23" + wire width 3 input 1 \eint + attribute \src "ls180.v:171.12-171.18" + wire width 3 \eint_1 + attribute \src "ls180.v:34.20-34.26" + wire width 16 input 30 \gpio_i + attribute \src "ls180.v:35.20-35.26" + wire width 16 output 31 \gpio_o + attribute \src "ls180.v:36.20-36.27" + wire width 16 output 32 \gpio_oe + attribute \src "ls180.v:30.14-30.21" + wire output 26 \i2c_scl + attribute \src "ls180.v:31.13-31.22" + wire input 27 \i2c_sda_i + attribute \src "ls180.v:32.14-32.23" + wire output 28 \i2c_sda_o + attribute \src "ls180.v:33.14-33.24" + wire output 29 \i2c_sda_oe + attribute \src "ls180.v:49.13-49.21" + wire input 45 \jtag_tck + attribute \src "ls180.v:50.13-50.21" + wire input 46 \jtag_tdi + attribute \src "ls180.v:51.14-51.22" + wire output 47 \jtag_tdo + attribute \src "ls180.v:48.13-48.21" + wire input 44 \jtag_tms + attribute \src "ls180.v:937.6-937.18" + wire \main_ack_cmd + attribute \src "ls180.v:939.6-939.20" + wire \main_ack_rdata + attribute \src "ls180.v:938.6-938.20" + wire \main_ack_wdata + attribute \src "ls180.v:935.5-935.22" + wire \main_cmd_consumed + attribute \src "ls180.v:318.5-318.28" + wire \main_converter0_counter + attribute \src "ls180.v:1841.5-1841.50" + wire \main_converter0_counter_converter0_next_value + attribute \src "ls180.v:1842.5-1842.53" + wire \main_converter0_counter_converter0_next_value_ce + attribute \src "ls180.v:320.12-320.33" + wire width 64 \main_converter0_dat_r + attribute \src "ls180.v:319.6-319.27" + wire \main_converter0_reset + attribute \src "ls180.v:317.5-317.25" + wire \main_converter0_skip + attribute \src "ls180.v:333.5-333.28" + wire \main_converter1_counter + attribute \src "ls180.v:1845.5-1845.50" + wire \main_converter1_counter_converter1_next_value + attribute \src "ls180.v:1846.5-1846.53" + wire \main_converter1_counter_converter1_next_value_ce + attribute \src "ls180.v:335.12-335.33" + wire width 64 \main_converter1_dat_r + attribute \src "ls180.v:334.6-334.27" + wire \main_converter1_reset + attribute \src "ls180.v:332.5-332.25" + wire \main_converter1_skip + attribute \src "ls180.v:932.5-932.27" + wire \main_converter_counter + attribute \src "ls180.v:1886.5-1886.48" + wire \main_converter_counter_converter_next_value + attribute \src "ls180.v:1887.5-1887.51" + wire \main_converter_counter_converter_next_value_ce + attribute \src "ls180.v:934.12-934.32" + wire width 32 \main_converter_dat_r + attribute \src "ls180.v:933.6-933.26" + wire \main_converter_reset + attribute \src "ls180.v:931.5-931.24" + wire \main_converter_skip + attribute \src "ls180.v:349.6-349.23" + wire \main_dfi_p0_act_n + attribute \src "ls180.v:340.13-340.32" + wire width 13 \main_dfi_p0_address + attribute \src "ls180.v:341.12-341.28" + wire width 2 \main_dfi_p0_bank + attribute \src "ls180.v:342.6-342.23" + wire \main_dfi_p0_cas_n + attribute \src "ls180.v:346.6-346.21" + wire \main_dfi_p0_cke + attribute \src "ls180.v:343.6-343.22" + wire \main_dfi_p0_cs_n + attribute \src "ls180.v:347.6-347.21" + wire \main_dfi_p0_odt + attribute \src "ls180.v:344.6-344.23" + wire \main_dfi_p0_ras_n + attribute \src "ls180.v:354.12-354.30" + wire width 16 \main_dfi_p0_rddata + attribute \src "ls180.v:353.6-353.27" + wire \main_dfi_p0_rddata_en + attribute \src "ls180.v:355.5-355.29" + wire \main_dfi_p0_rddata_valid + attribute \src "ls180.v:348.6-348.25" + wire \main_dfi_p0_reset_n + attribute \src "ls180.v:345.6-345.22" + wire \main_dfi_p0_we_n + attribute \src "ls180.v:350.13-350.31" + wire width 16 \main_dfi_p0_wrdata + attribute \src "ls180.v:351.6-351.27" + wire \main_dfi_p0_wrdata_en + attribute \src "ls180.v:352.12-352.35" + wire width 2 \main_dfi_p0_wrdata_mask + attribute \src "ls180.v:1172.12-1172.22" + wire width 24 \main_dummy + attribute \src "ls180.v:1082.12-1082.45" + wire width 16 \main_gpiotristateasic0_oe_storage + attribute \src "ls180.v:1084.12-1084.46" + wire width 16 \main_gpiotristateasic0_out_storage + attribute \src "ls180.v:1085.13-1085.42" + wire width 16 \main_gpiotristateasic0_pads_i + attribute \src "ls180.v:1086.13-1086.42" + wire width 16 \main_gpiotristateasic0_pads_o + attribute \src "ls180.v:1087.13-1087.43" + wire width 16 \main_gpiotristateasic0_pads_oe + attribute \src "ls180.v:1083.12-1083.41" + wire width 16 \main_gpiotristateasic0_status + attribute \src "ls180.v:1089.5-1089.33" + wire \main_gpiotristateasic1_oe_re + attribute \src "ls180.v:1088.12-1088.45" + wire width 16 \main_gpiotristateasic1_oe_storage + attribute \src "ls180.v:1093.5-1093.34" + wire \main_gpiotristateasic1_out_re + attribute \src "ls180.v:1092.12-1092.46" + wire width 16 \main_gpiotristateasic1_out_storage + attribute \src "ls180.v:1094.13-1094.42" + wire width 16 \main_gpiotristateasic1_pads_i + attribute \src "ls180.v:1095.13-1095.42" + wire width 16 \main_gpiotristateasic1_pads_o + attribute \src "ls180.v:1096.13-1096.43" + wire width 16 \main_gpiotristateasic1_pads_oe + attribute \src "ls180.v:1090.12-1090.41" + wire width 16 \main_gpiotristateasic1_status + attribute \src "ls180.v:1091.6-1091.31" + wire \main_gpiotristateasic1_we + attribute \src "ls180.v:1194.6-1194.17" + wire \main_i2c_oe + attribute \src "ls180.v:1197.5-1197.16" + wire \main_i2c_re + attribute \src "ls180.v:1193.6-1193.18" + wire \main_i2c_scl + attribute \src "ls180.v:1195.6-1195.19" + wire \main_i2c_sda0 + attribute \src "ls180.v:1198.6-1198.19" + wire \main_i2c_sda1 + attribute \src "ls180.v:1199.6-1199.21" + wire \main_i2c_status + attribute \src "ls180.v:1196.11-1196.27" + wire width 3 \main_i2c_storage + attribute \src "ls180.v:1200.6-1200.17" + wire \main_i2c_we + attribute \src "ls180.v:339.5-339.17" + wire \main_int_rst + attribute \src "ls180.v:1660.6-1660.29" + wire \main_interface0_bus_ack + attribute \src "ls180.v:1654.13-1654.36" + wire width 32 \main_interface0_bus_adr + attribute \src "ls180.v:1663.11-1663.34" + wire width 2 \main_interface0_bus_bte + attribute \src "ls180.v:1662.11-1662.34" + wire width 3 \main_interface0_bus_cti + attribute \src "ls180.v:1658.6-1658.29" + wire \main_interface0_bus_cyc + attribute \src "ls180.v:1656.13-1656.38" + wire width 64 \main_interface0_bus_dat_r + attribute \src "ls180.v:1655.13-1655.38" + wire width 64 \main_interface0_bus_dat_w + attribute \src "ls180.v:1664.6-1664.29" + wire \main_interface0_bus_err + attribute \src "ls180.v:1657.12-1657.35" + wire width 8 \main_interface0_bus_sel + attribute \src "ls180.v:1659.6-1659.29" + wire \main_interface0_bus_stb + attribute \src "ls180.v:1661.6-1661.28" + wire \main_interface0_bus_we + attribute \src "ls180.v:312.5-312.44" + wire \main_interface0_converted_interface_ack + attribute \src "ls180.v:306.13-306.52" + wire width 30 \main_interface0_converted_interface_adr + attribute \src "ls180.v:315.12-315.51" + wire width 2 \main_interface0_converted_interface_bte + attribute \src "ls180.v:314.12-314.51" + wire width 3 \main_interface0_converted_interface_cti + attribute \src "ls180.v:310.6-310.45" + wire \main_interface0_converted_interface_cyc + attribute \src "ls180.v:308.13-308.54" + wire width 64 \main_interface0_converted_interface_dat_r + attribute \src "ls180.v:307.13-307.54" + wire width 64 \main_interface0_converted_interface_dat_w + attribute \src "ls180.v:316.5-316.44" + wire \main_interface0_converted_interface_err + attribute \src "ls180.v:309.12-309.51" + wire width 8 \main_interface0_converted_interface_sel + attribute \src "ls180.v:311.6-311.45" + wire \main_interface0_converted_interface_stb + attribute \src "ls180.v:313.6-313.44" + wire \main_interface0_converted_interface_we + attribute \src "ls180.v:252.5-252.32" + wire \main_interface0_ram_bus_ack + attribute \src "ls180.v:246.13-246.40" + wire width 30 \main_interface0_ram_bus_adr + attribute \src "ls180.v:255.12-255.39" + wire width 2 \main_interface0_ram_bus_bte + attribute \src "ls180.v:254.12-254.39" + wire width 3 \main_interface0_ram_bus_cti + attribute \src "ls180.v:250.6-250.33" + wire \main_interface0_ram_bus_cyc + attribute \src "ls180.v:248.13-248.42" + wire width 64 \main_interface0_ram_bus_dat_r + attribute \src "ls180.v:247.13-247.42" + wire width 64 \main_interface0_ram_bus_dat_w + attribute \src "ls180.v:256.5-256.32" + wire \main_interface0_ram_bus_err + attribute \src "ls180.v:249.12-249.39" + wire width 8 \main_interface0_ram_bus_sel + attribute \src "ls180.v:251.6-251.33" + wire \main_interface0_ram_bus_stb + attribute \src "ls180.v:253.6-253.32" + wire \main_interface0_ram_bus_we + attribute \src "ls180.v:1751.6-1751.29" + wire \main_interface1_bus_ack + attribute \src "ls180.v:1745.12-1745.35" + wire width 32 \main_interface1_bus_adr + attribute \src "ls180.v:1754.11-1754.34" + wire width 2 \main_interface1_bus_bte + attribute \src "ls180.v:1753.11-1753.34" + wire width 3 \main_interface1_bus_cti + attribute \src "ls180.v:1749.5-1749.28" + wire \main_interface1_bus_cyc + attribute \src "ls180.v:1747.13-1747.38" + wire width 64 \main_interface1_bus_dat_r + attribute \src "ls180.v:1746.12-1746.37" + wire width 64 \main_interface1_bus_dat_w + attribute \src "ls180.v:1755.6-1755.29" + wire \main_interface1_bus_err + attribute \src "ls180.v:1748.11-1748.34" + wire width 8 \main_interface1_bus_sel + attribute \src "ls180.v:1750.5-1750.28" + wire \main_interface1_bus_stb + attribute \src "ls180.v:1752.5-1752.27" + wire \main_interface1_bus_we + attribute \src "ls180.v:327.5-327.44" + wire \main_interface1_converted_interface_ack + attribute \src "ls180.v:321.13-321.52" + wire width 30 \main_interface1_converted_interface_adr + attribute \src "ls180.v:330.12-330.51" + wire width 2 \main_interface1_converted_interface_bte + attribute \src "ls180.v:329.12-329.51" + wire width 3 \main_interface1_converted_interface_cti + attribute \src "ls180.v:325.6-325.45" + wire \main_interface1_converted_interface_cyc + attribute \src "ls180.v:323.13-323.54" + wire width 64 \main_interface1_converted_interface_dat_r + attribute \src "ls180.v:322.13-322.54" + wire width 64 \main_interface1_converted_interface_dat_w + attribute \src "ls180.v:331.5-331.44" + wire \main_interface1_converted_interface_err + attribute \src "ls180.v:324.12-324.51" + wire width 8 \main_interface1_converted_interface_sel + attribute \src "ls180.v:326.6-326.45" + wire \main_interface1_converted_interface_stb + attribute \src "ls180.v:328.6-328.44" + wire \main_interface1_converted_interface_we + attribute \src "ls180.v:267.5-267.32" + wire \main_interface1_ram_bus_ack + attribute \src "ls180.v:261.13-261.40" + wire width 30 \main_interface1_ram_bus_adr + attribute \src "ls180.v:270.12-270.39" + wire width 2 \main_interface1_ram_bus_bte + attribute \src "ls180.v:269.12-269.39" + wire width 3 \main_interface1_ram_bus_cti + attribute \src "ls180.v:265.6-265.33" + wire \main_interface1_ram_bus_cyc + attribute \src "ls180.v:263.13-263.42" + wire width 64 \main_interface1_ram_bus_dat_r + attribute \src "ls180.v:262.13-262.42" + wire width 64 \main_interface1_ram_bus_dat_w + attribute \src "ls180.v:271.5-271.32" + wire \main_interface1_ram_bus_err + attribute \src "ls180.v:264.12-264.39" + wire width 8 \main_interface1_ram_bus_sel + attribute \src "ls180.v:266.6-266.33" + wire \main_interface1_ram_bus_stb + attribute \src "ls180.v:268.6-268.32" + wire \main_interface1_ram_bus_we + attribute \src "ls180.v:282.5-282.32" + wire \main_interface2_ram_bus_ack + attribute \src "ls180.v:276.13-276.40" + wire width 30 \main_interface2_ram_bus_adr + attribute \src "ls180.v:285.12-285.39" + wire width 2 \main_interface2_ram_bus_bte + attribute \src "ls180.v:284.12-284.39" + wire width 3 \main_interface2_ram_bus_cti + attribute \src "ls180.v:280.6-280.33" + wire \main_interface2_ram_bus_cyc + attribute \src "ls180.v:278.13-278.42" + wire width 64 \main_interface2_ram_bus_dat_r + attribute \src "ls180.v:277.13-277.42" + wire width 64 \main_interface2_ram_bus_dat_w + attribute \src "ls180.v:286.5-286.32" + wire \main_interface2_ram_bus_err + attribute \src "ls180.v:279.12-279.39" + wire width 8 \main_interface2_ram_bus_sel + attribute \src "ls180.v:281.6-281.33" + wire \main_interface2_ram_bus_stb + attribute \src "ls180.v:283.6-283.32" + wire \main_interface2_ram_bus_we + attribute \src "ls180.v:297.5-297.32" + wire \main_interface3_ram_bus_ack + attribute \src "ls180.v:291.13-291.40" + wire width 30 \main_interface3_ram_bus_adr + attribute \src "ls180.v:300.12-300.39" + wire width 2 \main_interface3_ram_bus_bte + attribute \src "ls180.v:299.12-299.39" + wire width 3 \main_interface3_ram_bus_cti + attribute \src "ls180.v:295.6-295.33" + wire \main_interface3_ram_bus_cyc + attribute \src "ls180.v:293.13-293.42" + wire width 64 \main_interface3_ram_bus_dat_r + attribute \src "ls180.v:292.13-292.42" + wire width 64 \main_interface3_ram_bus_dat_w + attribute \src "ls180.v:301.5-301.32" + wire \main_interface3_ram_bus_err + attribute \src "ls180.v:294.12-294.39" + wire width 8 \main_interface3_ram_bus_sel + attribute \src "ls180.v:296.6-296.33" + wire \main_interface3_ram_bus_stb + attribute \src "ls180.v:298.6-298.32" + wire \main_interface3_ram_bus_we + attribute \src "ls180.v:215.12-215.32" + wire width 6 \main_libresocsim_adr + attribute \src "ls180.v:62.6-62.32" + wire \main_libresocsim_bus_error + attribute \src "ls180.v:63.12-63.39" + wire width 32 \main_libresocsim_bus_errors + attribute \src "ls180.v:59.13-59.47" + wire width 32 \main_libresocsim_bus_errors_status + attribute \src "ls180.v:60.6-60.36" + wire \main_libresocsim_bus_errors_we + attribute \src "ls180.v:216.13-216.35" + wire width 64 \main_libresocsim_dat_r + attribute \src "ls180.v:218.13-218.35" + wire width 64 \main_libresocsim_dat_w + attribute \src "ls180.v:224.5-224.27" + wire \main_libresocsim_en_re + attribute \src "ls180.v:223.5-223.32" + wire \main_libresocsim_en_storage + attribute \src "ls180.v:240.6-240.45" + wire \main_libresocsim_eventmanager_pending_r + attribute \src "ls180.v:239.6-239.46" + wire \main_libresocsim_eventmanager_pending_re + attribute \src "ls180.v:242.6-242.45" + wire \main_libresocsim_eventmanager_pending_w + attribute \src "ls180.v:241.6-241.46" + wire \main_libresocsim_eventmanager_pending_we + attribute \src "ls180.v:244.5-244.37" + wire \main_libresocsim_eventmanager_re + attribute \src "ls180.v:236.6-236.44" + wire \main_libresocsim_eventmanager_status_r + attribute \src "ls180.v:235.6-235.45" + wire \main_libresocsim_eventmanager_status_re + attribute \src "ls180.v:238.6-238.44" + wire \main_libresocsim_eventmanager_status_w + attribute \src "ls180.v:237.6-237.45" + wire \main_libresocsim_eventmanager_status_we + attribute \src "ls180.v:243.5-243.42" + wire \main_libresocsim_eventmanager_storage + attribute \src "ls180.v:229.6-229.26" + wire \main_libresocsim_irq + attribute \src "ls180.v:165.6-165.32" + wire \main_libresocsim_libresoc0 + attribute \src "ls180.v:166.6-166.32" + wire \main_libresocsim_libresoc1 + attribute \src "ls180.v:167.13-167.39" + wire width 64 \main_libresocsim_libresoc2 + attribute \src "ls180.v:169.12-169.45" + wire width 2 \main_libresocsim_libresoc_clk_sel + attribute \src "ls180.v:197.13-197.67" + wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_gpio_i + attribute \src "ls180.v:198.13-198.67" + wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_gpio_o + attribute \src "ls180.v:199.13-199.68" + wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe + attribute \src "ls180.v:193.6-193.61" + wire \main_libresocsim_libresoc_constraintmanager_obj_i2c_scl + attribute \src "ls180.v:194.6-194.63" + wire \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i + attribute \src "ls180.v:195.6-195.63" + wire \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_o + attribute \src "ls180.v:196.6-196.64" + wire \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_oe + attribute \src "ls180.v:189.6-189.64" + wire \main_libresocsim_libresoc_constraintmanager_obj_sdcard_clk + attribute \src "ls180.v:190.6-190.66" + wire \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i + attribute \src "ls180.v:191.6-191.66" + wire \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_o + attribute \src "ls180.v:192.6-192.67" + wire \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_oe + attribute \src "ls180.v:172.13-172.68" + wire width 13 \main_libresocsim_libresoc_constraintmanager_obj_sdram_a + attribute \src "ls180.v:181.12-181.68" + wire width 2 \main_libresocsim_libresoc_constraintmanager_obj_sdram_ba + attribute \src "ls180.v:178.6-178.65" + wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_cas_n + attribute \src "ls180.v:180.6-180.63" + wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_cke + attribute \src "ls180.v:179.6-179.64" + wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_cs_n + attribute \src "ls180.v:182.12-182.68" + wire width 2 \main_libresocsim_libresoc_constraintmanager_obj_sdram_dm + attribute \src "ls180.v:173.13-173.71" + wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i + attribute \src "ls180.v:174.13-174.71" + wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o + attribute \src "ls180.v:175.6-175.65" + wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe + attribute \src "ls180.v:177.6-177.65" + wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_ras_n + attribute \src "ls180.v:176.6-176.64" + wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_we_n + attribute \src "ls180.v:200.6-200.67" + wire \main_libresocsim_libresoc_constraintmanager_obj_spimaster_clk + attribute \src "ls180.v:202.6-202.68" + wire \main_libresocsim_libresoc_constraintmanager_obj_spimaster_cs_n + attribute \src "ls180.v:203.6-203.68" + wire \main_libresocsim_libresoc_constraintmanager_obj_spimaster_miso + attribute \src "ls180.v:201.6-201.68" + wire \main_libresocsim_libresoc_constraintmanager_obj_spimaster_mosi + attribute \src "ls180.v:185.6-185.67" + wire \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_clk + attribute \src "ls180.v:187.6-187.68" + wire \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_cs_n + attribute \src "ls180.v:188.6-188.68" + wire \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_miso + attribute \src "ls180.v:186.6-186.68" + wire \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_mosi + attribute \src "ls180.v:72.6-72.40" + wire \main_libresocsim_libresoc_dbus_ack + attribute \src "ls180.v:66.13-66.47" + wire width 29 \main_libresocsim_libresoc_dbus_adr + attribute \src "ls180.v:75.11-75.45" + wire width 2 \main_libresocsim_libresoc_dbus_bte + attribute \src "ls180.v:74.11-74.45" + wire width 3 \main_libresocsim_libresoc_dbus_cti + attribute \src "ls180.v:70.6-70.40" + wire \main_libresocsim_libresoc_dbus_cyc + attribute \src "ls180.v:68.13-68.49" + wire width 64 \main_libresocsim_libresoc_dbus_dat_r + attribute \src "ls180.v:67.13-67.49" + wire width 64 \main_libresocsim_libresoc_dbus_dat_w + attribute \src "ls180.v:76.6-76.40" + wire \main_libresocsim_libresoc_dbus_err + attribute \src "ls180.v:69.12-69.46" + wire width 8 \main_libresocsim_libresoc_dbus_sel + attribute \src "ls180.v:71.6-71.40" + wire \main_libresocsim_libresoc_dbus_stb + attribute \src "ls180.v:73.6-73.39" + wire \main_libresocsim_libresoc_dbus_we + attribute \src "ls180.v:83.6-83.40" + wire \main_libresocsim_libresoc_ibus_ack + attribute \src "ls180.v:77.13-77.47" + wire width 29 \main_libresocsim_libresoc_ibus_adr + attribute \src "ls180.v:86.11-86.45" + wire width 2 \main_libresocsim_libresoc_ibus_bte + attribute \src "ls180.v:85.11-85.45" + wire width 3 \main_libresocsim_libresoc_ibus_cti + attribute \src "ls180.v:81.6-81.40" + wire \main_libresocsim_libresoc_ibus_cyc + attribute \src "ls180.v:79.13-79.49" + wire width 64 \main_libresocsim_libresoc_ibus_dat_r + attribute \src "ls180.v:78.13-78.49" + wire width 64 \main_libresocsim_libresoc_ibus_dat_w + attribute \src "ls180.v:87.6-87.40" + wire \main_libresocsim_libresoc_ibus_err + attribute \src "ls180.v:80.12-80.46" + wire width 8 \main_libresocsim_libresoc_ibus_sel + attribute \src "ls180.v:82.6-82.40" + wire \main_libresocsim_libresoc_ibus_stb + attribute \src "ls180.v:84.6-84.39" + wire \main_libresocsim_libresoc_ibus_we + attribute \src "ls180.v:123.6-123.46" + wire \main_libresocsim_libresoc_interface0_ack + attribute \src "ls180.v:117.13-117.53" + wire width 29 \main_libresocsim_libresoc_interface0_adr + attribute \src "ls180.v:126.12-126.52" + wire width 2 \main_libresocsim_libresoc_interface0_bte + attribute \src "ls180.v:125.12-125.52" + wire width 3 \main_libresocsim_libresoc_interface0_cti + attribute \src "ls180.v:121.6-121.46" + wire \main_libresocsim_libresoc_interface0_cyc + attribute \src "ls180.v:119.13-119.55" + wire width 64 \main_libresocsim_libresoc_interface0_dat_r + attribute \src "ls180.v:118.13-118.55" + wire width 64 \main_libresocsim_libresoc_interface0_dat_w + attribute \src "ls180.v:127.6-127.46" + wire \main_libresocsim_libresoc_interface0_err + attribute \src "ls180.v:120.12-120.52" + wire width 8 \main_libresocsim_libresoc_interface0_sel + attribute \src "ls180.v:122.6-122.46" + wire \main_libresocsim_libresoc_interface0_stb + attribute \src "ls180.v:124.6-124.45" + wire \main_libresocsim_libresoc_interface0_we + attribute \src "ls180.v:134.6-134.46" + wire \main_libresocsim_libresoc_interface1_ack + attribute \src "ls180.v:128.13-128.53" + wire width 29 \main_libresocsim_libresoc_interface1_adr + attribute \src "ls180.v:137.12-137.52" + wire width 2 \main_libresocsim_libresoc_interface1_bte + attribute \src "ls180.v:136.12-136.52" + wire width 3 \main_libresocsim_libresoc_interface1_cti + attribute \src "ls180.v:132.6-132.46" + wire \main_libresocsim_libresoc_interface1_cyc + attribute \src "ls180.v:130.13-130.55" + wire width 64 \main_libresocsim_libresoc_interface1_dat_r + attribute \src "ls180.v:129.13-129.55" + wire width 64 \main_libresocsim_libresoc_interface1_dat_w + attribute \src "ls180.v:138.6-138.46" + wire \main_libresocsim_libresoc_interface1_err + attribute \src "ls180.v:131.12-131.52" + wire width 8 \main_libresocsim_libresoc_interface1_sel + attribute \src "ls180.v:133.6-133.46" + wire \main_libresocsim_libresoc_interface1_stb + attribute \src "ls180.v:135.6-135.45" + wire \main_libresocsim_libresoc_interface1_we + attribute \src "ls180.v:145.6-145.46" + wire \main_libresocsim_libresoc_interface2_ack + attribute \src "ls180.v:139.13-139.53" + wire width 29 \main_libresocsim_libresoc_interface2_adr + attribute \src "ls180.v:148.12-148.52" + wire width 2 \main_libresocsim_libresoc_interface2_bte + attribute \src "ls180.v:147.12-147.52" + wire width 3 \main_libresocsim_libresoc_interface2_cti + attribute \src "ls180.v:143.6-143.46" + wire \main_libresocsim_libresoc_interface2_cyc + attribute \src "ls180.v:141.13-141.55" + wire width 64 \main_libresocsim_libresoc_interface2_dat_r + attribute \src "ls180.v:140.13-140.55" + wire width 64 \main_libresocsim_libresoc_interface2_dat_w + attribute \src "ls180.v:149.6-149.46" + wire \main_libresocsim_libresoc_interface2_err + attribute \src "ls180.v:142.12-142.52" + wire width 8 \main_libresocsim_libresoc_interface2_sel + attribute \src "ls180.v:144.6-144.46" + wire \main_libresocsim_libresoc_interface2_stb + attribute \src "ls180.v:146.6-146.45" + wire \main_libresocsim_libresoc_interface2_we + attribute \src "ls180.v:156.6-156.46" + wire \main_libresocsim_libresoc_interface3_ack + attribute \src "ls180.v:150.13-150.53" + wire width 29 \main_libresocsim_libresoc_interface3_adr + attribute \src "ls180.v:159.12-159.52" + wire width 2 \main_libresocsim_libresoc_interface3_bte + attribute \src "ls180.v:158.12-158.52" + wire width 3 \main_libresocsim_libresoc_interface3_cti + attribute \src "ls180.v:154.6-154.46" + wire \main_libresocsim_libresoc_interface3_cyc + attribute \src "ls180.v:152.13-152.55" + wire width 64 \main_libresocsim_libresoc_interface3_dat_r + attribute \src "ls180.v:151.13-151.55" + wire width 64 \main_libresocsim_libresoc_interface3_dat_w + attribute \src "ls180.v:160.6-160.46" + wire \main_libresocsim_libresoc_interface3_err + attribute \src "ls180.v:153.12-153.52" + wire width 8 \main_libresocsim_libresoc_interface3_sel + attribute \src "ls180.v:155.6-155.46" + wire \main_libresocsim_libresoc_interface3_stb + attribute \src "ls180.v:157.6-157.45" + wire \main_libresocsim_libresoc_interface3_we + attribute \src "ls180.v:65.12-65.47" + wire width 16 \main_libresocsim_libresoc_interrupt + attribute \src "ls180.v:161.6-161.40" + wire \main_libresocsim_libresoc_jtag_tck + attribute \src "ls180.v:163.6-163.40" + wire \main_libresocsim_libresoc_jtag_tdi + attribute \src "ls180.v:164.6-164.40" + wire \main_libresocsim_libresoc_jtag_tdo + attribute \src "ls180.v:162.6-162.40" + wire \main_libresocsim_libresoc_jtag_tms + attribute \src "ls180.v:112.6-112.43" + wire \main_libresocsim_libresoc_jtag_wb_ack + attribute \src "ls180.v:106.13-106.50" + wire width 29 \main_libresocsim_libresoc_jtag_wb_adr + attribute \src "ls180.v:115.11-115.48" + wire width 2 \main_libresocsim_libresoc_jtag_wb_bte + attribute \src "ls180.v:114.11-114.48" + wire width 3 \main_libresocsim_libresoc_jtag_wb_cti + attribute \src "ls180.v:110.6-110.43" + wire \main_libresocsim_libresoc_jtag_wb_cyc + attribute \src "ls180.v:108.13-108.52" + wire width 64 \main_libresocsim_libresoc_jtag_wb_dat_r + attribute \src "ls180.v:107.13-107.52" + wire width 64 \main_libresocsim_libresoc_jtag_wb_dat_w + attribute \src "ls180.v:116.6-116.43" + wire \main_libresocsim_libresoc_jtag_wb_err + attribute \src "ls180.v:109.12-109.49" + wire width 8 \main_libresocsim_libresoc_jtag_wb_sel + attribute \src "ls180.v:111.6-111.43" + wire \main_libresocsim_libresoc_jtag_wb_stb + attribute \src "ls180.v:113.6-113.42" + wire \main_libresocsim_libresoc_jtag_wb_we + attribute \src "ls180.v:168.6-168.40" + wire \main_libresocsim_libresoc_pll_18_o + attribute \src "ls180.v:170.6-170.41" + wire \main_libresocsim_libresoc_pll_lck_o + attribute \src "ls180.v:64.6-64.37" + wire \main_libresocsim_libresoc_reset + attribute \src "ls180.v:94.6-94.44" + wire \main_libresocsim_libresoc_xics_icp_ack + attribute \src "ls180.v:88.12-88.50" + wire width 30 \main_libresocsim_libresoc_xics_icp_adr + attribute \src "ls180.v:92.5-92.43" + wire \main_libresocsim_libresoc_xics_icp_cyc + attribute \src "ls180.v:90.13-90.53" + wire width 32 \main_libresocsim_libresoc_xics_icp_dat_r + attribute \src "ls180.v:89.12-89.52" + wire width 32 \main_libresocsim_libresoc_xics_icp_dat_w + attribute \src "ls180.v:96.6-96.44" + wire \main_libresocsim_libresoc_xics_icp_err + attribute \src "ls180.v:91.11-91.49" + wire width 4 \main_libresocsim_libresoc_xics_icp_sel + attribute \src "ls180.v:93.5-93.43" + wire \main_libresocsim_libresoc_xics_icp_stb + attribute \src "ls180.v:95.5-95.42" + wire \main_libresocsim_libresoc_xics_icp_we + attribute \src "ls180.v:103.6-103.44" + wire \main_libresocsim_libresoc_xics_ics_ack + attribute \src "ls180.v:97.12-97.50" + wire width 30 \main_libresocsim_libresoc_xics_ics_adr + attribute \src "ls180.v:101.5-101.43" + wire \main_libresocsim_libresoc_xics_ics_cyc + attribute \src "ls180.v:99.13-99.53" + wire width 32 \main_libresocsim_libresoc_xics_ics_dat_r + attribute \src "ls180.v:98.12-98.52" + wire width 32 \main_libresocsim_libresoc_xics_ics_dat_w + attribute \src "ls180.v:105.6-105.44" + wire \main_libresocsim_libresoc_xics_ics_err + attribute \src "ls180.v:100.11-100.49" + wire width 4 \main_libresocsim_libresoc_xics_ics_sel + attribute \src "ls180.v:102.5-102.43" + wire \main_libresocsim_libresoc_xics_ics_stb + attribute \src "ls180.v:104.5-104.42" + wire \main_libresocsim_libresoc_xics_ics_we + attribute \src "ls180.v:220.5-220.29" + wire \main_libresocsim_load_re + attribute \src "ls180.v:219.12-219.41" + wire width 32 \main_libresocsim_load_storage + attribute \src "ls180.v:210.5-210.33" + wire \main_libresocsim_ram_bus_ack + attribute \src "ls180.v:204.13-204.41" + wire width 30 \main_libresocsim_ram_bus_adr + attribute \src "ls180.v:213.12-213.40" + wire width 2 \main_libresocsim_ram_bus_bte + attribute \src "ls180.v:212.12-212.40" + wire width 3 \main_libresocsim_ram_bus_cti + attribute \src "ls180.v:208.6-208.34" + wire \main_libresocsim_ram_bus_cyc + attribute \src "ls180.v:206.13-206.43" + wire width 64 \main_libresocsim_ram_bus_dat_r + attribute \src "ls180.v:205.13-205.43" + wire width 64 \main_libresocsim_ram_bus_dat_w + attribute \src "ls180.v:214.5-214.33" + wire \main_libresocsim_ram_bus_err + attribute \src "ls180.v:207.12-207.40" + wire width 8 \main_libresocsim_ram_bus_sel + attribute \src "ls180.v:209.6-209.34" + wire \main_libresocsim_ram_bus_stb + attribute \src "ls180.v:211.6-211.33" + wire \main_libresocsim_ram_bus_we + attribute \src "ls180.v:222.5-222.31" + wire \main_libresocsim_reload_re + attribute \src "ls180.v:221.12-221.43" + wire width 32 \main_libresocsim_reload_storage + attribute \src "ls180.v:61.6-61.28" + wire \main_libresocsim_reset + attribute \src "ls180.v:56.5-56.30" + wire \main_libresocsim_reset_re + attribute \src "ls180.v:55.5-55.35" + wire \main_libresocsim_reset_storage + attribute \src "ls180.v:58.5-58.32" + wire \main_libresocsim_scratch_re + attribute \src "ls180.v:57.12-57.44" + wire width 32 \main_libresocsim_scratch_storage + attribute \src "ls180.v:226.5-226.37" + wire \main_libresocsim_update_value_re + attribute \src "ls180.v:225.5-225.42" + wire \main_libresocsim_update_value_storage + attribute \src "ls180.v:245.12-245.34" + wire width 32 \main_libresocsim_value + attribute \src "ls180.v:227.12-227.41" + wire width 32 \main_libresocsim_value_status + attribute \src "ls180.v:228.6-228.31" + wire \main_libresocsim_value_we + attribute \src "ls180.v:217.11-217.30" + wire width 8 \main_libresocsim_we + attribute \src "ls180.v:233.5-233.32" + wire \main_libresocsim_zero_clear + attribute \src "ls180.v:234.5-234.38" + wire \main_libresocsim_zero_old_trigger + attribute \src "ls180.v:231.5-231.34" + wire \main_libresocsim_zero_pending + attribute \src "ls180.v:230.6-230.34" + wire \main_libresocsim_zero_status + attribute \src "ls180.v:232.6-232.35" + wire \main_libresocsim_zero_trigger + attribute \src "ls180.v:929.6-929.26" + wire \main_litedram_wb_ack + attribute \src "ls180.v:923.12-923.32" + wire width 30 \main_litedram_wb_adr + attribute \src "ls180.v:927.5-927.25" + wire \main_litedram_wb_cyc + attribute \src "ls180.v:925.13-925.35" + wire width 16 \main_litedram_wb_dat_r + attribute \src "ls180.v:924.12-924.34" + wire width 16 \main_litedram_wb_dat_w + attribute \src "ls180.v:926.11-926.31" + wire width 2 \main_litedram_wb_sel + attribute \src "ls180.v:928.5-928.25" + wire \main_litedram_wb_stb + attribute \src "ls180.v:930.5-930.24" + wire \main_litedram_wb_we + attribute \src "ls180.v:1171.13-1171.20" + wire width 24 \main_nc + attribute \src "ls180.v:890.6-890.24" + wire \main_port_cmd_last + attribute \src "ls180.v:892.13-892.39" + wire width 24 \main_port_cmd_payload_addr + attribute \src "ls180.v:891.6-891.30" + wire \main_port_cmd_payload_we + attribute \src "ls180.v:889.6-889.25" + wire \main_port_cmd_ready + attribute \src "ls180.v:888.6-888.25" + wire \main_port_cmd_valid + attribute \src "ls180.v:887.6-887.21" + wire \main_port_flush + attribute \src "ls180.v:899.13-899.41" + wire width 16 \main_port_rdata_payload_data + attribute \src "ls180.v:898.6-898.27" + wire \main_port_rdata_ready + attribute \src "ls180.v:897.6-897.27" + wire \main_port_rdata_valid + attribute \src "ls180.v:895.13-895.41" + wire width 16 \main_port_wdata_payload_data + attribute \src "ls180.v:896.12-896.38" + wire width 2 \main_port_wdata_payload_we + attribute \src "ls180.v:894.6-894.27" + wire \main_port_wdata_ready + attribute \src "ls180.v:893.6-893.27" + wire \main_port_wdata_valid + attribute \src "ls180.v:1176.12-1176.29" + wire width 32 \main_pwm0_counter + attribute \src "ls180.v:1173.6-1173.22" + wire \main_pwm0_enable + attribute \src "ls180.v:1178.5-1178.24" + wire \main_pwm0_enable_re + attribute \src "ls180.v:1177.5-1177.29" + wire \main_pwm0_enable_storage + attribute \src "ls180.v:1175.13-1175.29" + wire width 32 \main_pwm0_period + attribute \src "ls180.v:1182.5-1182.24" + wire \main_pwm0_period_re + attribute \src "ls180.v:1181.12-1181.36" + wire width 32 \main_pwm0_period_storage + attribute \src "ls180.v:1174.13-1174.28" + wire width 32 \main_pwm0_width + attribute \src "ls180.v:1180.5-1180.23" + wire \main_pwm0_width_re + attribute \src "ls180.v:1179.12-1179.35" + wire width 32 \main_pwm0_width_storage + attribute \src "ls180.v:1186.12-1186.29" + wire width 32 \main_pwm1_counter + attribute \src "ls180.v:1183.6-1183.22" + wire \main_pwm1_enable + attribute \src "ls180.v:1188.5-1188.24" + wire \main_pwm1_enable_re + attribute \src "ls180.v:1187.5-1187.29" + wire \main_pwm1_enable_storage + attribute \src "ls180.v:1185.13-1185.29" + wire width 32 \main_pwm1_period + attribute \src "ls180.v:1192.5-1192.24" + wire \main_pwm1_period_re + attribute \src "ls180.v:1191.12-1191.36" + wire width 32 \main_pwm1_period_storage + attribute \src "ls180.v:1184.13-1184.28" + wire width 32 \main_pwm1_width + attribute \src "ls180.v:1190.5-1190.23" + wire \main_pwm1_width_re + attribute \src "ls180.v:1189.12-1189.35" + wire width 32 \main_pwm1_width_storage + attribute \src "ls180.v:356.11-356.25" + wire width 3 \main_rddata_en + attribute \src "ls180.v:1714.11-1714.43" + wire width 3 \main_sdblock2mem_converter_demux + attribute \src "ls180.v:1715.6-1715.42" + wire \main_sdblock2mem_converter_load_part + attribute \src "ls180.v:1705.6-1705.43" + wire \main_sdblock2mem_converter_sink_first + attribute \src "ls180.v:1706.6-1706.42" + wire \main_sdblock2mem_converter_sink_last + attribute \src "ls180.v:1707.12-1707.56" + wire width 8 \main_sdblock2mem_converter_sink_payload_data + attribute \src "ls180.v:1704.6-1704.43" + wire \main_sdblock2mem_converter_sink_ready + attribute \src "ls180.v:1703.6-1703.43" + wire \main_sdblock2mem_converter_sink_valid + attribute \src "ls180.v:1710.5-1710.44" + wire \main_sdblock2mem_converter_source_first + attribute \src "ls180.v:1711.5-1711.43" + wire \main_sdblock2mem_converter_source_last + attribute \src "ls180.v:1712.12-1712.58" + wire width 64 \main_sdblock2mem_converter_source_payload_data + attribute \src "ls180.v:1713.11-1713.70" + wire width 4 \main_sdblock2mem_converter_source_payload_valid_token_count + attribute \src "ls180.v:1709.6-1709.45" + wire \main_sdblock2mem_converter_source_ready + attribute \src "ls180.v:1708.6-1708.45" + wire \main_sdblock2mem_converter_source_valid + attribute \src "ls180.v:1716.5-1716.42" + wire \main_sdblock2mem_converter_strobe_all + attribute \src "ls180.v:1689.11-1689.40" + wire width 5 \main_sdblock2mem_fifo_consume + attribute \src "ls180.v:1694.6-1694.35" + wire \main_sdblock2mem_fifo_do_read + attribute \src "ls180.v:1698.6-1698.41" + wire \main_sdblock2mem_fifo_fifo_in_first + attribute \src "ls180.v:1699.6-1699.40" + wire \main_sdblock2mem_fifo_fifo_in_last + attribute \src "ls180.v:1697.12-1697.54" + wire width 8 \main_sdblock2mem_fifo_fifo_in_payload_data + attribute \src "ls180.v:1701.6-1701.42" + wire \main_sdblock2mem_fifo_fifo_out_first + attribute \src "ls180.v:1702.6-1702.41" + wire \main_sdblock2mem_fifo_fifo_out_last + attribute \src "ls180.v:1700.12-1700.55" + wire width 8 \main_sdblock2mem_fifo_fifo_out_payload_data + attribute \src "ls180.v:1686.11-1686.38" + wire width 6 \main_sdblock2mem_fifo_level + attribute \src "ls180.v:1688.11-1688.40" + wire width 5 \main_sdblock2mem_fifo_produce + attribute \src "ls180.v:1695.12-1695.44" + wire width 5 \main_sdblock2mem_fifo_rdport_adr + attribute \src "ls180.v:1696.12-1696.46" + wire width 10 \main_sdblock2mem_fifo_rdport_dat_r + attribute \src "ls180.v:1687.5-1687.34" + wire \main_sdblock2mem_fifo_replace + attribute \src "ls180.v:1672.6-1672.38" + wire \main_sdblock2mem_fifo_sink_first + attribute \src "ls180.v:1673.6-1673.37" + wire \main_sdblock2mem_fifo_sink_last + attribute \src "ls180.v:1674.12-1674.51" + wire width 8 \main_sdblock2mem_fifo_sink_payload_data + attribute \src "ls180.v:1671.6-1671.38" + wire \main_sdblock2mem_fifo_sink_ready + attribute \src "ls180.v:1670.6-1670.38" + wire \main_sdblock2mem_fifo_sink_valid + attribute \src "ls180.v:1677.6-1677.40" + wire \main_sdblock2mem_fifo_source_first + attribute \src "ls180.v:1678.6-1678.39" + wire \main_sdblock2mem_fifo_source_last + attribute \src "ls180.v:1679.12-1679.53" + wire width 8 \main_sdblock2mem_fifo_source_payload_data + attribute \src "ls180.v:1676.6-1676.40" + wire \main_sdblock2mem_fifo_source_ready + attribute \src "ls180.v:1675.6-1675.40" + wire \main_sdblock2mem_fifo_source_valid + attribute \src "ls180.v:1684.12-1684.46" + wire width 10 \main_sdblock2mem_fifo_syncfifo_din + attribute \src "ls180.v:1685.12-1685.47" + wire width 10 \main_sdblock2mem_fifo_syncfifo_dout + attribute \src "ls180.v:1682.6-1682.39" + wire \main_sdblock2mem_fifo_syncfifo_re + attribute \src "ls180.v:1683.6-1683.45" + wire \main_sdblock2mem_fifo_syncfifo_readable + attribute \src "ls180.v:1680.6-1680.39" + wire \main_sdblock2mem_fifo_syncfifo_we + attribute \src "ls180.v:1681.6-1681.45" + wire \main_sdblock2mem_fifo_syncfifo_writable + attribute \src "ls180.v:1690.11-1690.43" + wire width 5 \main_sdblock2mem_fifo_wrport_adr + attribute \src "ls180.v:1691.12-1691.46" + wire width 10 \main_sdblock2mem_fifo_wrport_dat_r + attribute \src "ls180.v:1693.12-1693.46" + wire width 10 \main_sdblock2mem_fifo_wrport_dat_w + attribute \src "ls180.v:1692.6-1692.37" + wire \main_sdblock2mem_fifo_wrport_we + attribute \src "ls180.v:1667.6-1667.38" + wire \main_sdblock2mem_sink_sink_first + attribute \src "ls180.v:1668.6-1668.37" + wire \main_sdblock2mem_sink_sink_last + attribute \src "ls180.v:1724.12-1724.54" + wire width 32 \main_sdblock2mem_sink_sink_payload_address + attribute \src "ls180.v:1669.12-1669.52" + wire width 8 \main_sdblock2mem_sink_sink_payload_data0 + attribute \src "ls180.v:1725.12-1725.52" + wire width 64 \main_sdblock2mem_sink_sink_payload_data1 + attribute \src "ls180.v:1666.6-1666.39" + wire \main_sdblock2mem_sink_sink_ready0 + attribute \src "ls180.v:1723.6-1723.39" + wire \main_sdblock2mem_sink_sink_ready1 + attribute \src "ls180.v:1665.6-1665.39" + wire \main_sdblock2mem_sink_sink_valid0 + attribute \src "ls180.v:1722.5-1722.38" + wire \main_sdblock2mem_sink_sink_valid1 + attribute \src "ls180.v:1719.6-1719.42" + wire \main_sdblock2mem_source_source_first + attribute \src "ls180.v:1720.6-1720.41" + wire \main_sdblock2mem_source_source_last + attribute \src "ls180.v:1721.13-1721.56" + wire width 64 \main_sdblock2mem_source_source_payload_data + attribute \src "ls180.v:1718.6-1718.42" + wire \main_sdblock2mem_source_source_ready + attribute \src "ls180.v:1717.6-1717.42" + wire \main_sdblock2mem_source_source_valid + attribute \src "ls180.v:1741.13-1741.52" + wire width 32 \main_sdblock2mem_wishbonedmawriter_base + attribute \src "ls180.v:1732.5-1732.47" + wire \main_sdblock2mem_wishbonedmawriter_base_re + attribute \src "ls180.v:1731.12-1731.59" + wire width 64 \main_sdblock2mem_wishbonedmawriter_base_storage + attribute \src "ls180.v:1736.5-1736.49" + wire \main_sdblock2mem_wishbonedmawriter_enable_re + attribute \src "ls180.v:1735.5-1735.54" + wire \main_sdblock2mem_wishbonedmawriter_enable_storage + attribute \src "ls180.v:1743.13-1743.54" + wire width 32 \main_sdblock2mem_wishbonedmawriter_length + attribute \src "ls180.v:1734.5-1734.49" + wire \main_sdblock2mem_wishbonedmawriter_length_re + attribute \src "ls180.v:1733.12-1733.61" + wire width 32 \main_sdblock2mem_wishbonedmawriter_length_storage + attribute \src "ls180.v:1740.5-1740.47" + wire \main_sdblock2mem_wishbonedmawriter_loop_re + attribute \src "ls180.v:1739.5-1739.52" + wire \main_sdblock2mem_wishbonedmawriter_loop_storage + attribute \src "ls180.v:1742.12-1742.53" + wire width 32 \main_sdblock2mem_wishbonedmawriter_offset + attribute \src "ls180.v:1962.12-1962.79" + wire width 32 \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value + attribute \src "ls180.v:1963.5-1963.75" + wire \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce + attribute \src "ls180.v:1744.6-1744.46" + wire \main_sdblock2mem_wishbonedmawriter_reset + attribute \src "ls180.v:1728.6-1728.51" + wire \main_sdblock2mem_wishbonedmawriter_sink_first + attribute \src "ls180.v:1729.6-1729.50" + wire \main_sdblock2mem_wishbonedmawriter_sink_last + attribute \src "ls180.v:1730.13-1730.65" + wire width 64 \main_sdblock2mem_wishbonedmawriter_sink_payload_data + attribute \src "ls180.v:1727.5-1727.50" + wire \main_sdblock2mem_wishbonedmawriter_sink_ready + attribute \src "ls180.v:1726.6-1726.51" + wire \main_sdblock2mem_wishbonedmawriter_sink_valid + attribute \src "ls180.v:1737.5-1737.46" + wire \main_sdblock2mem_wishbonedmawriter_status + attribute \src "ls180.v:1738.6-1738.43" + wire \main_sdblock2mem_wishbonedmawriter_we + attribute \src "ls180.v:1506.5-1506.31" + wire \main_sdcore_block_count_re + attribute \src "ls180.v:1505.12-1505.43" + wire width 32 \main_sdcore_block_count_storage + attribute \src "ls180.v:1504.5-1504.32" + wire \main_sdcore_block_length_re + attribute \src "ls180.v:1503.11-1503.43" + wire width 10 \main_sdcore_block_length_storage + attribute \src "ls180.v:1490.5-1490.32" + wire \main_sdcore_cmd_argument_re + attribute \src "ls180.v:1489.12-1489.44" + wire width 32 \main_sdcore_cmd_argument_storage + attribute \src "ls180.v:1492.5-1492.31" + wire \main_sdcore_cmd_command_re + attribute \src "ls180.v:1491.12-1491.43" + wire width 32 \main_sdcore_cmd_command_storage + attribute \src "ls180.v:1645.11-1645.32" + wire width 3 \main_sdcore_cmd_count + attribute \src "ls180.v:1946.11-1946.55" + wire width 3 \main_sdcore_cmd_count_sdcore_fsm_next_value2 + attribute \src "ls180.v:1947.5-1947.52" + wire \main_sdcore_cmd_count_sdcore_fsm_next_value_ce2 + attribute \src "ls180.v:1646.5-1646.25" + wire \main_sdcore_cmd_done + attribute \src "ls180.v:1942.5-1942.48" + wire \main_sdcore_cmd_done_sdcore_fsm_next_value0 + attribute \src "ls180.v:1943.5-1943.51" + wire \main_sdcore_cmd_done_sdcore_fsm_next_value_ce0 + attribute \src "ls180.v:1647.5-1647.26" + wire \main_sdcore_cmd_error + attribute \src "ls180.v:1950.5-1950.49" + wire \main_sdcore_cmd_error_sdcore_fsm_next_value4 + attribute \src "ls180.v:1951.5-1951.52" + wire \main_sdcore_cmd_error_sdcore_fsm_next_value_ce4 + attribute \src "ls180.v:1499.12-1499.40" + wire width 4 \main_sdcore_cmd_event_status + attribute \src "ls180.v:1500.6-1500.30" + wire \main_sdcore_cmd_event_we + attribute \src "ls180.v:1497.13-1497.44" + wire width 128 \main_sdcore_cmd_response_status + attribute \src "ls180.v:1958.13-1958.67" + wire width 128 \main_sdcore_cmd_response_status_sdcore_fsm_next_value8 + attribute \src "ls180.v:1959.5-1959.62" + wire \main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8 + attribute \src "ls180.v:1498.6-1498.33" + wire \main_sdcore_cmd_response_we + attribute \src "ls180.v:1494.6-1494.28" + wire \main_sdcore_cmd_send_r + attribute \src "ls180.v:1493.6-1493.29" + wire \main_sdcore_cmd_send_re + attribute \src "ls180.v:1496.5-1496.27" + wire \main_sdcore_cmd_send_w + attribute \src "ls180.v:1495.6-1495.29" + wire \main_sdcore_cmd_send_we + attribute \src "ls180.v:1648.5-1648.28" + wire \main_sdcore_cmd_timeout + attribute \src "ls180.v:1952.5-1952.51" + wire \main_sdcore_cmd_timeout_sdcore_fsm_next_value5 + attribute \src "ls180.v:1953.5-1953.54" + wire \main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5 + attribute \src "ls180.v:1644.12-1644.32" + wire width 2 \main_sdcore_cmd_type + attribute \src "ls180.v:1606.11-1606.40" + wire width 4 \main_sdcore_crc16_checker_cnt + attribute \src "ls180.v:1612.5-1612.39" + wire \main_sdcore_crc16_checker_crc0_clr + attribute \src "ls180.v:1611.12-1611.46" + wire width 16 \main_sdcore_crc16_checker_crc0_crc + attribute \src "ls180.v:1607.12-1607.50" + wire width 16 \main_sdcore_crc16_checker_crc0_crcreg0 + attribute \src "ls180.v:1608.13-1608.51" + wire width 16 \main_sdcore_crc16_checker_crc0_crcreg1 + attribute \src "ls180.v:1609.13-1609.51" + wire width 16 \main_sdcore_crc16_checker_crc0_crcreg2 + attribute \src "ls180.v:1613.6-1613.43" + wire \main_sdcore_crc16_checker_crc0_enable + attribute \src "ls180.v:1610.12-1610.46" + wire width 2 \main_sdcore_crc16_checker_crc0_val + attribute \src "ls180.v:1619.5-1619.39" + wire \main_sdcore_crc16_checker_crc1_clr + attribute \src "ls180.v:1618.12-1618.46" + wire width 16 \main_sdcore_crc16_checker_crc1_crc + attribute \src "ls180.v:1614.12-1614.50" + wire width 16 \main_sdcore_crc16_checker_crc1_crcreg0 + attribute \src "ls180.v:1615.13-1615.51" + wire width 16 \main_sdcore_crc16_checker_crc1_crcreg1 + attribute \src "ls180.v:1616.13-1616.51" + wire width 16 \main_sdcore_crc16_checker_crc1_crcreg2 + attribute \src "ls180.v:1620.6-1620.43" + wire \main_sdcore_crc16_checker_crc1_enable + attribute \src "ls180.v:1617.12-1617.46" + wire width 2 \main_sdcore_crc16_checker_crc1_val + attribute \src "ls180.v:1626.5-1626.39" + wire \main_sdcore_crc16_checker_crc2_clr + attribute \src "ls180.v:1625.12-1625.46" + wire width 16 \main_sdcore_crc16_checker_crc2_crc + attribute \src "ls180.v:1621.12-1621.50" + wire width 16 \main_sdcore_crc16_checker_crc2_crcreg0 + attribute \src "ls180.v:1622.13-1622.51" + wire width 16 \main_sdcore_crc16_checker_crc2_crcreg1 + attribute \src "ls180.v:1623.13-1623.51" + wire width 16 \main_sdcore_crc16_checker_crc2_crcreg2 + attribute \src "ls180.v:1627.6-1627.43" + wire \main_sdcore_crc16_checker_crc2_enable + attribute \src "ls180.v:1624.12-1624.46" + wire width 2 \main_sdcore_crc16_checker_crc2_val + attribute \src "ls180.v:1633.5-1633.39" + wire \main_sdcore_crc16_checker_crc3_clr + attribute \src "ls180.v:1632.12-1632.46" + wire width 16 \main_sdcore_crc16_checker_crc3_crc + attribute \src "ls180.v:1628.12-1628.50" + wire width 16 \main_sdcore_crc16_checker_crc3_crcreg0 + attribute \src "ls180.v:1629.13-1629.51" + wire width 16 \main_sdcore_crc16_checker_crc3_crcreg1 + attribute \src "ls180.v:1630.13-1630.51" + wire width 16 \main_sdcore_crc16_checker_crc3_crcreg2 + attribute \src "ls180.v:1634.6-1634.43" + wire \main_sdcore_crc16_checker_crc3_enable + attribute \src "ls180.v:1631.12-1631.46" + wire width 2 \main_sdcore_crc16_checker_crc3_val + attribute \src "ls180.v:1635.12-1635.45" + wire width 16 \main_sdcore_crc16_checker_crctmp0 + attribute \src "ls180.v:1636.12-1636.45" + wire width 16 \main_sdcore_crc16_checker_crctmp1 + attribute \src "ls180.v:1637.12-1637.45" + wire width 16 \main_sdcore_crc16_checker_crctmp2 + attribute \src "ls180.v:1638.12-1638.45" + wire width 16 \main_sdcore_crc16_checker_crctmp3 + attribute \src "ls180.v:1640.12-1640.43" + wire width 16 \main_sdcore_crc16_checker_fifo0 + attribute \src "ls180.v:1641.12-1641.43" + wire width 16 \main_sdcore_crc16_checker_fifo1 + attribute \src "ls180.v:1642.12-1642.43" + wire width 16 \main_sdcore_crc16_checker_fifo2 + attribute \src "ls180.v:1643.12-1643.43" + wire width 16 \main_sdcore_crc16_checker_fifo3 + attribute \src "ls180.v:1597.5-1597.41" + wire \main_sdcore_crc16_checker_sink_first + attribute \src "ls180.v:1598.5-1598.40" + wire \main_sdcore_crc16_checker_sink_last + attribute \src "ls180.v:1599.11-1599.54" + wire width 8 \main_sdcore_crc16_checker_sink_payload_data + attribute \src "ls180.v:1596.5-1596.41" + wire \main_sdcore_crc16_checker_sink_ready + attribute \src "ls180.v:1595.5-1595.41" + wire \main_sdcore_crc16_checker_sink_valid + attribute \src "ls180.v:1602.5-1602.43" + wire \main_sdcore_crc16_checker_source_first + attribute \src "ls180.v:1603.6-1603.43" + wire \main_sdcore_crc16_checker_source_last + attribute \src "ls180.v:1604.12-1604.57" + wire width 8 \main_sdcore_crc16_checker_source_payload_data + attribute \src "ls180.v:1601.6-1601.44" + wire \main_sdcore_crc16_checker_source_ready + attribute \src "ls180.v:1600.5-1600.43" + wire \main_sdcore_crc16_checker_source_valid + attribute \src "ls180.v:1605.11-1605.40" + wire width 8 \main_sdcore_crc16_checker_val + attribute \src "ls180.v:1639.5-1639.36" + wire \main_sdcore_crc16_checker_valid + attribute \src "ls180.v:1562.11-1562.41" + wire width 3 \main_sdcore_crc16_inserter_cnt + attribute \src "ls180.v:1938.11-1938.80" + wire width 3 \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4 + attribute \src "ls180.v:1939.5-1939.77" + wire \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4 + attribute \src "ls180.v:1568.6-1568.41" + wire \main_sdcore_crc16_inserter_crc0_clr + attribute \src "ls180.v:1567.12-1567.47" + wire width 16 \main_sdcore_crc16_inserter_crc0_crc + attribute \src "ls180.v:1563.12-1563.51" + wire width 16 \main_sdcore_crc16_inserter_crc0_crcreg0 + attribute \src "ls180.v:1564.13-1564.52" + wire width 16 \main_sdcore_crc16_inserter_crc0_crcreg1 + attribute \src "ls180.v:1565.13-1565.52" + wire width 16 \main_sdcore_crc16_inserter_crc0_crcreg2 + attribute \src "ls180.v:1569.6-1569.44" + wire \main_sdcore_crc16_inserter_crc0_enable + attribute \src "ls180.v:1566.12-1566.47" + wire width 2 \main_sdcore_crc16_inserter_crc0_val + attribute \src "ls180.v:1575.6-1575.41" + wire \main_sdcore_crc16_inserter_crc1_clr + attribute \src "ls180.v:1574.12-1574.47" + wire width 16 \main_sdcore_crc16_inserter_crc1_crc + attribute \src "ls180.v:1570.12-1570.51" + wire width 16 \main_sdcore_crc16_inserter_crc1_crcreg0 + attribute \src "ls180.v:1571.13-1571.52" + wire width 16 \main_sdcore_crc16_inserter_crc1_crcreg1 + attribute \src "ls180.v:1572.13-1572.52" + wire width 16 \main_sdcore_crc16_inserter_crc1_crcreg2 + attribute \src "ls180.v:1576.6-1576.44" + wire \main_sdcore_crc16_inserter_crc1_enable + attribute \src "ls180.v:1573.12-1573.47" + wire width 2 \main_sdcore_crc16_inserter_crc1_val + attribute \src "ls180.v:1582.6-1582.41" + wire \main_sdcore_crc16_inserter_crc2_clr + attribute \src "ls180.v:1581.12-1581.47" + wire width 16 \main_sdcore_crc16_inserter_crc2_crc + attribute \src "ls180.v:1577.12-1577.51" + wire width 16 \main_sdcore_crc16_inserter_crc2_crcreg0 + attribute \src "ls180.v:1578.13-1578.52" + wire width 16 \main_sdcore_crc16_inserter_crc2_crcreg1 + attribute \src "ls180.v:1579.13-1579.52" + wire width 16 \main_sdcore_crc16_inserter_crc2_crcreg2 + attribute \src "ls180.v:1583.6-1583.44" + wire \main_sdcore_crc16_inserter_crc2_enable + attribute \src "ls180.v:1580.12-1580.47" + wire width 2 \main_sdcore_crc16_inserter_crc2_val + attribute \src "ls180.v:1589.6-1589.41" + wire \main_sdcore_crc16_inserter_crc3_clr + attribute \src "ls180.v:1588.12-1588.47" + wire width 16 \main_sdcore_crc16_inserter_crc3_crc + attribute \src "ls180.v:1584.12-1584.51" + wire width 16 \main_sdcore_crc16_inserter_crc3_crcreg0 + attribute \src "ls180.v:1585.13-1585.52" + wire width 16 \main_sdcore_crc16_inserter_crc3_crcreg1 + attribute \src "ls180.v:1586.13-1586.52" + wire width 16 \main_sdcore_crc16_inserter_crc3_crcreg2 + attribute \src "ls180.v:1590.6-1590.44" + wire \main_sdcore_crc16_inserter_crc3_enable + attribute \src "ls180.v:1587.12-1587.47" + wire width 2 \main_sdcore_crc16_inserter_crc3_val + attribute \src "ls180.v:1591.12-1591.46" + wire width 16 \main_sdcore_crc16_inserter_crctmp0 + attribute \src "ls180.v:1930.12-1930.85" + wire width 16 \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0 + attribute \src "ls180.v:1931.5-1931.81" + wire \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0 + attribute \src "ls180.v:1592.12-1592.46" + wire width 16 \main_sdcore_crc16_inserter_crctmp1 + attribute \src "ls180.v:1932.12-1932.85" + wire width 16 \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1 + attribute \src "ls180.v:1933.5-1933.81" + wire \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1 + attribute \src "ls180.v:1593.12-1593.46" + wire width 16 \main_sdcore_crc16_inserter_crctmp2 + attribute \src "ls180.v:1934.12-1934.85" + wire width 16 \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2 + attribute \src "ls180.v:1935.5-1935.81" + wire \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2 + attribute \src "ls180.v:1594.12-1594.46" + wire width 16 \main_sdcore_crc16_inserter_crctmp3 + attribute \src "ls180.v:1936.12-1936.85" + wire width 16 \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3 + attribute \src "ls180.v:1937.5-1937.81" + wire \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3 + attribute \src "ls180.v:1554.6-1554.43" + wire \main_sdcore_crc16_inserter_sink_first + attribute \src "ls180.v:1555.6-1555.42" + wire \main_sdcore_crc16_inserter_sink_last + attribute \src "ls180.v:1556.12-1556.56" + wire width 8 \main_sdcore_crc16_inserter_sink_payload_data + attribute \src "ls180.v:1553.5-1553.42" + wire \main_sdcore_crc16_inserter_sink_ready + attribute \src "ls180.v:1552.6-1552.43" + wire \main_sdcore_crc16_inserter_sink_valid + attribute \src "ls180.v:1559.5-1559.44" + wire \main_sdcore_crc16_inserter_source_first + attribute \src "ls180.v:1560.5-1560.43" + wire \main_sdcore_crc16_inserter_source_last + attribute \src "ls180.v:1561.11-1561.57" + wire width 8 \main_sdcore_crc16_inserter_source_payload_data + attribute \src "ls180.v:1558.5-1558.44" + wire \main_sdcore_crc16_inserter_source_ready + attribute \src "ls180.v:1557.5-1557.44" + wire \main_sdcore_crc16_inserter_source_valid + attribute \src "ls180.v:1550.6-1550.35" + wire \main_sdcore_crc7_inserter_clr + attribute \src "ls180.v:1549.11-1549.40" + wire width 7 \main_sdcore_crc7_inserter_crc + attribute \src "ls180.v:1507.11-1507.44" + wire width 7 \main_sdcore_crc7_inserter_crcreg0 + attribute \src "ls180.v:1508.12-1508.45" + wire width 7 \main_sdcore_crc7_inserter_crcreg1 + attribute \src "ls180.v:1517.12-1517.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg10 + attribute \src "ls180.v:1518.12-1518.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg11 + attribute \src "ls180.v:1519.12-1519.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg12 + attribute \src "ls180.v:1520.12-1520.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg13 + attribute \src "ls180.v:1521.12-1521.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg14 + attribute \src "ls180.v:1522.12-1522.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg15 + attribute \src "ls180.v:1523.12-1523.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg16 + attribute \src "ls180.v:1524.12-1524.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg17 + attribute \src "ls180.v:1525.12-1525.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg18 + attribute \src "ls180.v:1526.12-1526.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg19 + attribute \src "ls180.v:1509.12-1509.45" + wire width 7 \main_sdcore_crc7_inserter_crcreg2 + attribute \src "ls180.v:1527.12-1527.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg20 + attribute \src "ls180.v:1528.12-1528.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg21 + attribute \src "ls180.v:1529.12-1529.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg22 + attribute \src "ls180.v:1530.12-1530.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg23 + attribute \src "ls180.v:1531.12-1531.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg24 + attribute \src "ls180.v:1532.12-1532.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg25 + attribute \src "ls180.v:1533.12-1533.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg26 + attribute \src "ls180.v:1534.12-1534.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg27 + attribute \src "ls180.v:1535.12-1535.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg28 + attribute \src "ls180.v:1536.12-1536.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg29 + attribute \src "ls180.v:1510.12-1510.45" + wire width 7 \main_sdcore_crc7_inserter_crcreg3 + attribute \src "ls180.v:1537.12-1537.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg30 + attribute \src "ls180.v:1538.12-1538.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg31 + attribute \src "ls180.v:1539.12-1539.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg32 + attribute \src "ls180.v:1540.12-1540.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg33 + attribute \src "ls180.v:1541.12-1541.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg34 + attribute \src "ls180.v:1542.12-1542.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg35 + attribute \src "ls180.v:1543.12-1543.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg36 + attribute \src "ls180.v:1544.12-1544.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg37 + attribute \src "ls180.v:1545.12-1545.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg38 + attribute \src "ls180.v:1546.12-1546.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg39 + attribute \src "ls180.v:1511.12-1511.45" + wire width 7 \main_sdcore_crc7_inserter_crcreg4 + attribute \src "ls180.v:1547.12-1547.46" + wire width 7 \main_sdcore_crc7_inserter_crcreg40 + attribute \src "ls180.v:1512.12-1512.45" + wire width 7 \main_sdcore_crc7_inserter_crcreg5 + attribute \src "ls180.v:1513.12-1513.45" + wire width 7 \main_sdcore_crc7_inserter_crcreg6 + attribute \src "ls180.v:1514.12-1514.45" + wire width 7 \main_sdcore_crc7_inserter_crcreg7 + attribute \src "ls180.v:1515.12-1515.45" + wire width 7 \main_sdcore_crc7_inserter_crcreg8 + attribute \src "ls180.v:1516.12-1516.45" + wire width 7 \main_sdcore_crc7_inserter_crcreg9 + attribute \src "ls180.v:1551.6-1551.38" + wire \main_sdcore_crc7_inserter_enable + attribute \src "ls180.v:1548.13-1548.42" + wire width 40 \main_sdcore_crc7_inserter_val + attribute \src "ls180.v:1650.12-1650.34" + wire width 32 \main_sdcore_data_count + attribute \src "ls180.v:1948.12-1948.57" + wire width 32 \main_sdcore_data_count_sdcore_fsm_next_value3 + attribute \src "ls180.v:1949.5-1949.53" + wire \main_sdcore_data_count_sdcore_fsm_next_value_ce3 + attribute \src "ls180.v:1651.5-1651.26" + wire \main_sdcore_data_done + attribute \src "ls180.v:1944.5-1944.49" + wire \main_sdcore_data_done_sdcore_fsm_next_value1 + attribute \src "ls180.v:1945.5-1945.52" + wire \main_sdcore_data_done_sdcore_fsm_next_value_ce1 + attribute \src "ls180.v:1652.5-1652.27" + wire \main_sdcore_data_error + attribute \src "ls180.v:1954.5-1954.50" + wire \main_sdcore_data_error_sdcore_fsm_next_value6 + attribute \src "ls180.v:1955.5-1955.53" + wire \main_sdcore_data_error_sdcore_fsm_next_value_ce6 + attribute \src "ls180.v:1501.12-1501.41" + wire width 4 \main_sdcore_data_event_status + attribute \src "ls180.v:1502.6-1502.31" + wire \main_sdcore_data_event_we + attribute \src "ls180.v:1653.5-1653.29" + wire \main_sdcore_data_timeout + attribute \src "ls180.v:1956.5-1956.52" + wire \main_sdcore_data_timeout_sdcore_fsm_next_value7 + attribute \src "ls180.v:1957.5-1957.55" + wire \main_sdcore_data_timeout_sdcore_fsm_next_value_ce7 + attribute \src "ls180.v:1649.12-1649.33" + wire width 2 \main_sdcore_data_type + attribute \src "ls180.v:1481.6-1481.33" + wire \main_sdcore_sink_sink_first + attribute \src "ls180.v:1482.6-1482.32" + wire \main_sdcore_sink_sink_last + attribute \src "ls180.v:1483.12-1483.46" + wire width 8 \main_sdcore_sink_sink_payload_data + attribute \src "ls180.v:1480.6-1480.33" + wire \main_sdcore_sink_sink_ready + attribute \src "ls180.v:1479.6-1479.33" + wire \main_sdcore_sink_sink_valid + attribute \src "ls180.v:1486.6-1486.37" + wire \main_sdcore_source_source_first + attribute \src "ls180.v:1487.6-1487.36" + wire \main_sdcore_source_source_last + attribute \src "ls180.v:1488.12-1488.50" + wire width 8 \main_sdcore_source_source_payload_data + attribute \src "ls180.v:1485.6-1485.37" + wire \main_sdcore_source_source_ready + attribute \src "ls180.v:1484.6-1484.37" + wire \main_sdcore_source_source_valid + attribute \src "ls180.v:1799.6-1799.38" + wire \main_sdmem2block_converter_first + attribute \src "ls180.v:1800.6-1800.37" + wire \main_sdmem2block_converter_last + attribute \src "ls180.v:1798.11-1798.41" + wire width 3 \main_sdmem2block_converter_mux + attribute \src "ls180.v:1789.6-1789.43" + wire \main_sdmem2block_converter_sink_first + attribute \src "ls180.v:1790.6-1790.42" + wire \main_sdmem2block_converter_sink_last + attribute \src "ls180.v:1791.13-1791.57" + wire width 64 \main_sdmem2block_converter_sink_payload_data + attribute \src "ls180.v:1788.6-1788.43" + wire \main_sdmem2block_converter_sink_ready + attribute \src "ls180.v:1787.6-1787.43" + wire \main_sdmem2block_converter_sink_valid + attribute \src "ls180.v:1794.6-1794.45" + wire \main_sdmem2block_converter_source_first + attribute \src "ls180.v:1795.6-1795.44" + wire \main_sdmem2block_converter_source_last + attribute \src "ls180.v:1796.11-1796.57" + wire width 8 \main_sdmem2block_converter_source_payload_data + attribute \src "ls180.v:1797.6-1797.65" + wire \main_sdmem2block_converter_source_payload_valid_token_count + attribute \src "ls180.v:1793.6-1793.45" + wire \main_sdmem2block_converter_source_ready + attribute \src "ls180.v:1792.6-1792.45" + wire \main_sdmem2block_converter_source_valid + attribute \src "ls180.v:1783.13-1783.38" + wire width 32 \main_sdmem2block_dma_base + attribute \src "ls180.v:1772.5-1772.33" + wire \main_sdmem2block_dma_base_re + attribute \src "ls180.v:1771.12-1771.45" + wire width 64 \main_sdmem2block_dma_base_storage + attribute \src "ls180.v:1770.12-1770.37" + wire width 64 \main_sdmem2block_dma_data + attribute \src "ls180.v:1966.12-1966.67" + wire width 64 \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value + attribute \src "ls180.v:1967.5-1967.63" + wire \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce + attribute \src "ls180.v:1777.5-1777.37" + wire \main_sdmem2block_dma_done_status + attribute \src "ls180.v:1778.6-1778.34" + wire \main_sdmem2block_dma_done_we + attribute \src "ls180.v:1776.5-1776.35" + wire \main_sdmem2block_dma_enable_re + attribute \src "ls180.v:1775.5-1775.40" + wire \main_sdmem2block_dma_enable_storage + attribute \src "ls180.v:1785.13-1785.40" + wire width 32 \main_sdmem2block_dma_length + attribute \src "ls180.v:1774.5-1774.35" + wire \main_sdmem2block_dma_length_re + attribute \src "ls180.v:1773.12-1773.47" + wire width 32 \main_sdmem2block_dma_length_storage + attribute \src "ls180.v:1780.5-1780.33" + wire \main_sdmem2block_dma_loop_re + attribute \src "ls180.v:1779.5-1779.38" + wire \main_sdmem2block_dma_loop_storage + attribute \src "ls180.v:1784.12-1784.39" + wire width 32 \main_sdmem2block_dma_offset + attribute \src "ls180.v:1970.12-1970.79" + wire width 32 \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value + attribute \src "ls180.v:1971.5-1971.75" + wire \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce + attribute \src "ls180.v:1781.13-1781.47" + wire width 32 \main_sdmem2block_dma_offset_status + attribute \src "ls180.v:1782.6-1782.36" + wire \main_sdmem2block_dma_offset_we + attribute \src "ls180.v:1786.6-1786.32" + wire \main_sdmem2block_dma_reset + attribute \src "ls180.v:1763.5-1763.35" + wire \main_sdmem2block_dma_sink_last + attribute \src "ls180.v:1764.12-1764.53" + wire width 32 \main_sdmem2block_dma_sink_payload_address + attribute \src "ls180.v:1762.5-1762.36" + wire \main_sdmem2block_dma_sink_ready + attribute \src "ls180.v:1761.5-1761.36" + wire \main_sdmem2block_dma_sink_valid + attribute \src "ls180.v:1767.5-1767.38" + wire \main_sdmem2block_dma_source_first + attribute \src "ls180.v:1768.5-1768.37" + wire \main_sdmem2block_dma_source_last + attribute \src "ls180.v:1769.12-1769.52" + wire width 64 \main_sdmem2block_dma_source_payload_data + attribute \src "ls180.v:1766.6-1766.39" + wire \main_sdmem2block_dma_source_ready + attribute \src "ls180.v:1765.5-1765.38" + wire \main_sdmem2block_dma_source_valid + attribute \src "ls180.v:1825.11-1825.40" + wire width 5 \main_sdmem2block_fifo_consume + attribute \src "ls180.v:1830.6-1830.35" + wire \main_sdmem2block_fifo_do_read + attribute \src "ls180.v:1834.6-1834.41" + wire \main_sdmem2block_fifo_fifo_in_first + attribute \src "ls180.v:1835.6-1835.40" + wire \main_sdmem2block_fifo_fifo_in_last + attribute \src "ls180.v:1833.12-1833.54" + wire width 8 \main_sdmem2block_fifo_fifo_in_payload_data + attribute \src "ls180.v:1837.6-1837.42" + wire \main_sdmem2block_fifo_fifo_out_first + attribute \src "ls180.v:1838.6-1838.41" + wire \main_sdmem2block_fifo_fifo_out_last + attribute \src "ls180.v:1836.12-1836.55" + wire width 8 \main_sdmem2block_fifo_fifo_out_payload_data + attribute \src "ls180.v:1822.11-1822.38" + wire width 6 \main_sdmem2block_fifo_level + attribute \src "ls180.v:1824.11-1824.40" + wire width 5 \main_sdmem2block_fifo_produce + attribute \src "ls180.v:1831.12-1831.44" + wire width 5 \main_sdmem2block_fifo_rdport_adr + attribute \src "ls180.v:1832.12-1832.46" + wire width 10 \main_sdmem2block_fifo_rdport_dat_r + attribute \src "ls180.v:1823.5-1823.34" + wire \main_sdmem2block_fifo_replace + attribute \src "ls180.v:1808.6-1808.38" + wire \main_sdmem2block_fifo_sink_first + attribute \src "ls180.v:1809.6-1809.37" + wire \main_sdmem2block_fifo_sink_last + attribute \src "ls180.v:1810.12-1810.51" + wire width 8 \main_sdmem2block_fifo_sink_payload_data + attribute \src "ls180.v:1807.6-1807.38" + wire \main_sdmem2block_fifo_sink_ready + attribute \src "ls180.v:1806.6-1806.38" + wire \main_sdmem2block_fifo_sink_valid + attribute \src "ls180.v:1813.6-1813.40" + wire \main_sdmem2block_fifo_source_first + attribute \src "ls180.v:1814.6-1814.39" + wire \main_sdmem2block_fifo_source_last + attribute \src "ls180.v:1815.12-1815.53" + wire width 8 \main_sdmem2block_fifo_source_payload_data + attribute \src "ls180.v:1812.6-1812.40" + wire \main_sdmem2block_fifo_source_ready + attribute \src "ls180.v:1811.6-1811.40" + wire \main_sdmem2block_fifo_source_valid + attribute \src "ls180.v:1820.12-1820.46" + wire width 10 \main_sdmem2block_fifo_syncfifo_din + attribute \src "ls180.v:1821.12-1821.47" + wire width 10 \main_sdmem2block_fifo_syncfifo_dout + attribute \src "ls180.v:1818.6-1818.39" + wire \main_sdmem2block_fifo_syncfifo_re + attribute \src "ls180.v:1819.6-1819.45" + wire \main_sdmem2block_fifo_syncfifo_readable + attribute \src "ls180.v:1816.6-1816.39" + wire \main_sdmem2block_fifo_syncfifo_we + attribute \src "ls180.v:1817.6-1817.45" + wire \main_sdmem2block_fifo_syncfifo_writable + attribute \src "ls180.v:1826.11-1826.43" + wire width 5 \main_sdmem2block_fifo_wrport_adr + attribute \src "ls180.v:1827.12-1827.46" + wire width 10 \main_sdmem2block_fifo_wrport_dat_r + attribute \src "ls180.v:1829.12-1829.46" + wire width 10 \main_sdmem2block_fifo_wrport_dat_w + attribute \src "ls180.v:1828.6-1828.37" + wire \main_sdmem2block_fifo_wrport_we + attribute \src "ls180.v:1758.6-1758.43" + wire \main_sdmem2block_source_source_first0 + attribute \src "ls180.v:1803.6-1803.43" + wire \main_sdmem2block_source_source_first1 + attribute \src "ls180.v:1759.6-1759.42" + wire \main_sdmem2block_source_source_last0 + attribute \src "ls180.v:1804.6-1804.42" + wire \main_sdmem2block_source_source_last1 + attribute \src "ls180.v:1760.12-1760.56" + wire width 8 \main_sdmem2block_source_source_payload_data0 + attribute \src "ls180.v:1805.12-1805.56" + wire width 8 \main_sdmem2block_source_source_payload_data1 + attribute \src "ls180.v:1757.6-1757.43" + wire \main_sdmem2block_source_source_ready0 + attribute \src "ls180.v:1802.6-1802.43" + wire \main_sdmem2block_source_source_ready1 + attribute \src "ls180.v:1756.6-1756.43" + wire \main_sdmem2block_source_source_valid0 + attribute \src "ls180.v:1801.6-1801.43" + wire \main_sdmem2block_source_source_valid1 + attribute \src "ls180.v:1207.6-1207.27" + wire \main_sdphy_clocker_ce + attribute \src "ls180.v:1206.5-1206.28" + wire \main_sdphy_clocker_clk0 + attribute \src "ls180.v:1209.5-1209.28" + wire \main_sdphy_clocker_clk1 + attribute \src "ls180.v:1210.5-1210.29" + wire \main_sdphy_clocker_clk_d + attribute \src "ls180.v:1208.11-1208.34" + wire width 9 \main_sdphy_clocker_clks + attribute \src "ls180.v:1204.5-1204.26" + wire \main_sdphy_clocker_re + attribute \src "ls180.v:1205.6-1205.29" + wire \main_sdphy_clocker_stop + attribute \src "ls180.v:1203.11-1203.37" + wire width 9 \main_sdphy_clocker_storage + attribute \src "ls180.v:1307.6-1307.41" + wire \main_sdphy_cmdr_cmdr_buf_sink_first + attribute \src "ls180.v:1308.6-1308.40" + wire \main_sdphy_cmdr_cmdr_buf_sink_last + attribute \src "ls180.v:1309.12-1309.54" + wire width 8 \main_sdphy_cmdr_cmdr_buf_sink_payload_data + attribute \src "ls180.v:1306.6-1306.41" + wire \main_sdphy_cmdr_cmdr_buf_sink_ready + attribute \src "ls180.v:1305.6-1305.41" + wire \main_sdphy_cmdr_cmdr_buf_sink_valid + attribute \src "ls180.v:1312.5-1312.42" + wire \main_sdphy_cmdr_cmdr_buf_source_first + attribute \src "ls180.v:1313.5-1313.41" + wire \main_sdphy_cmdr_cmdr_buf_source_last + attribute \src "ls180.v:1314.11-1314.55" + wire width 8 \main_sdphy_cmdr_cmdr_buf_source_payload_data + attribute \src "ls180.v:1311.6-1311.43" + wire \main_sdphy_cmdr_cmdr_buf_source_ready + attribute \src "ls180.v:1310.5-1310.42" + wire \main_sdphy_cmdr_cmdr_buf_source_valid + attribute \src "ls180.v:1297.11-1297.47" + wire width 3 \main_sdphy_cmdr_cmdr_converter_demux + attribute \src "ls180.v:1298.6-1298.46" + wire \main_sdphy_cmdr_cmdr_converter_load_part + attribute \src "ls180.v:1288.5-1288.46" + wire \main_sdphy_cmdr_cmdr_converter_sink_first + attribute \src "ls180.v:1289.5-1289.45" + wire \main_sdphy_cmdr_cmdr_converter_sink_last + attribute \src "ls180.v:1290.6-1290.54" + wire \main_sdphy_cmdr_cmdr_converter_sink_payload_data + attribute \src "ls180.v:1287.6-1287.47" + wire \main_sdphy_cmdr_cmdr_converter_sink_ready + attribute \src "ls180.v:1286.6-1286.47" + wire \main_sdphy_cmdr_cmdr_converter_sink_valid + attribute \src "ls180.v:1293.5-1293.48" + wire \main_sdphy_cmdr_cmdr_converter_source_first + attribute \src "ls180.v:1294.5-1294.47" + wire \main_sdphy_cmdr_cmdr_converter_source_last + attribute \src "ls180.v:1295.11-1295.61" + wire width 8 \main_sdphy_cmdr_cmdr_converter_source_payload_data + attribute \src "ls180.v:1296.11-1296.74" + wire width 4 \main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count + attribute \src "ls180.v:1292.6-1292.49" + wire \main_sdphy_cmdr_cmdr_converter_source_ready + attribute \src "ls180.v:1291.6-1291.49" + wire \main_sdphy_cmdr_cmdr_converter_source_valid + attribute \src "ls180.v:1299.5-1299.46" + wire \main_sdphy_cmdr_cmdr_converter_strobe_all + attribute \src "ls180.v:1270.6-1270.40" + wire \main_sdphy_cmdr_cmdr_pads_in_first + attribute \src "ls180.v:1271.6-1271.39" + wire \main_sdphy_cmdr_cmdr_pads_in_last + attribute \src "ls180.v:1272.6-1272.46" + wire \main_sdphy_cmdr_cmdr_pads_in_payload_clk + attribute \src "ls180.v:1273.6-1273.48" + wire \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_i + attribute \src "ls180.v:1274.6-1274.48" + wire \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_o + attribute \src "ls180.v:1275.6-1275.49" + wire \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_oe + attribute \src "ls180.v:1276.12-1276.55" + wire width 4 \main_sdphy_cmdr_cmdr_pads_in_payload_data_i + attribute \src "ls180.v:1277.12-1277.55" + wire width 4 \main_sdphy_cmdr_cmdr_pads_in_payload_data_o + attribute \src "ls180.v:1278.6-1278.50" + wire \main_sdphy_cmdr_cmdr_pads_in_payload_data_oe + attribute \src "ls180.v:1269.5-1269.39" + wire \main_sdphy_cmdr_cmdr_pads_in_ready + attribute \src "ls180.v:1268.6-1268.40" + wire \main_sdphy_cmdr_cmdr_pads_in_valid + attribute \src "ls180.v:1315.5-1315.31" + wire \main_sdphy_cmdr_cmdr_reset + attribute \src "ls180.v:1910.5-1910.59" + wire \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2 + attribute \src "ls180.v:1911.5-1911.62" + wire \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2 + attribute \src "ls180.v:1285.5-1285.29" + wire \main_sdphy_cmdr_cmdr_run + attribute \src "ls180.v:1281.6-1281.47" + wire \main_sdphy_cmdr_cmdr_source_source_first0 + attribute \src "ls180.v:1302.6-1302.47" + wire \main_sdphy_cmdr_cmdr_source_source_first1 + attribute \src "ls180.v:1282.6-1282.46" + wire \main_sdphy_cmdr_cmdr_source_source_last0 + attribute \src "ls180.v:1303.6-1303.46" + wire \main_sdphy_cmdr_cmdr_source_source_last1 + attribute \src "ls180.v:1283.12-1283.60" + wire width 8 \main_sdphy_cmdr_cmdr_source_source_payload_data0 + attribute \src "ls180.v:1304.12-1304.60" + wire width 8 \main_sdphy_cmdr_cmdr_source_source_payload_data1 + attribute \src "ls180.v:1280.5-1280.46" + wire \main_sdphy_cmdr_cmdr_source_source_ready0 + attribute \src "ls180.v:1301.6-1301.47" + wire \main_sdphy_cmdr_cmdr_source_source_ready1 + attribute \src "ls180.v:1279.6-1279.47" + wire \main_sdphy_cmdr_cmdr_source_source_valid0 + attribute \src "ls180.v:1300.6-1300.47" + wire \main_sdphy_cmdr_cmdr_source_source_valid1 + attribute \src "ls180.v:1284.6-1284.32" + wire \main_sdphy_cmdr_cmdr_start + attribute \src "ls180.v:1267.11-1267.32" + wire width 8 \main_sdphy_cmdr_count + attribute \src "ls180.v:1906.11-1906.60" + wire width 8 \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0 + attribute \src "ls180.v:1907.5-1907.57" + wire \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0 + attribute \src "ls180.v:1242.5-1242.42" + wire \main_sdphy_cmdr_pads_in_pads_in_first + attribute \src "ls180.v:1243.5-1243.41" + wire \main_sdphy_cmdr_pads_in_pads_in_last + attribute \src "ls180.v:1244.5-1244.48" + wire \main_sdphy_cmdr_pads_in_pads_in_payload_clk + attribute \src "ls180.v:1245.6-1245.51" + wire \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_i + attribute \src "ls180.v:1246.5-1246.50" + wire \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_o + attribute \src "ls180.v:1247.5-1247.51" + wire \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_oe + attribute \src "ls180.v:1248.12-1248.58" + wire width 4 \main_sdphy_cmdr_pads_in_pads_in_payload_data_i + attribute \src "ls180.v:1249.11-1249.57" + wire width 4 \main_sdphy_cmdr_pads_in_pads_in_payload_data_o + attribute \src "ls180.v:1250.5-1250.52" + wire \main_sdphy_cmdr_pads_in_pads_in_payload_data_oe + attribute \src "ls180.v:1241.6-1241.43" + wire \main_sdphy_cmdr_pads_in_pads_in_ready + attribute \src "ls180.v:1240.6-1240.43" + wire \main_sdphy_cmdr_pads_in_pads_in_valid + attribute \src "ls180.v:1252.5-1252.41" + wire \main_sdphy_cmdr_pads_out_payload_clk + attribute \src "ls180.v:1253.5-1253.43" + wire \main_sdphy_cmdr_pads_out_payload_cmd_o + attribute \src "ls180.v:1254.5-1254.44" + wire \main_sdphy_cmdr_pads_out_payload_cmd_oe + attribute \src "ls180.v:1255.11-1255.50" + wire width 4 \main_sdphy_cmdr_pads_out_payload_data_o + attribute \src "ls180.v:1256.5-1256.45" + wire \main_sdphy_cmdr_pads_out_payload_data_oe + attribute \src "ls180.v:1251.6-1251.36" + wire \main_sdphy_cmdr_pads_out_ready + attribute \src "ls180.v:1259.5-1259.30" + wire \main_sdphy_cmdr_sink_last + attribute \src "ls180.v:1260.11-1260.46" + wire width 8 \main_sdphy_cmdr_sink_payload_length + attribute \src "ls180.v:1258.5-1258.31" + wire \main_sdphy_cmdr_sink_ready + attribute \src "ls180.v:1257.5-1257.31" + wire \main_sdphy_cmdr_sink_valid + attribute \src "ls180.v:1263.5-1263.32" + wire \main_sdphy_cmdr_source_last + attribute \src "ls180.v:1264.11-1264.46" + wire width 8 \main_sdphy_cmdr_source_payload_data + attribute \src "ls180.v:1265.11-1265.48" + wire width 3 \main_sdphy_cmdr_source_payload_status + attribute \src "ls180.v:1262.5-1262.33" + wire \main_sdphy_cmdr_source_ready + attribute \src "ls180.v:1261.5-1261.33" + wire \main_sdphy_cmdr_source_valid + attribute \src "ls180.v:1266.12-1266.35" + wire width 32 \main_sdphy_cmdr_timeout + attribute \src "ls180.v:1908.12-1908.63" + wire width 32 \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1 + attribute \src "ls180.v:1909.5-1909.59" + wire \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1 + attribute \src "ls180.v:1239.11-1239.32" + wire width 8 \main_sdphy_cmdw_count + attribute \src "ls180.v:1902.11-1902.59" + wire width 8 \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value + attribute \src "ls180.v:1903.5-1903.56" + wire \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce + attribute \src "ls180.v:1238.5-1238.25" + wire \main_sdphy_cmdw_done + attribute \src "ls180.v:1226.6-1226.43" + wire \main_sdphy_cmdw_pads_in_payload_cmd_i + attribute \src "ls180.v:1227.12-1227.50" + wire width 4 \main_sdphy_cmdw_pads_in_payload_data_i + attribute \src "ls180.v:1225.6-1225.35" + wire \main_sdphy_cmdw_pads_in_valid + attribute \src "ls180.v:1229.5-1229.41" + wire \main_sdphy_cmdw_pads_out_payload_clk + attribute \src "ls180.v:1230.5-1230.43" + wire \main_sdphy_cmdw_pads_out_payload_cmd_o + attribute \src "ls180.v:1231.5-1231.44" + wire \main_sdphy_cmdw_pads_out_payload_cmd_oe + attribute \src "ls180.v:1232.11-1232.50" + wire width 4 \main_sdphy_cmdw_pads_out_payload_data_o + attribute \src "ls180.v:1233.5-1233.45" + wire \main_sdphy_cmdw_pads_out_payload_data_oe + attribute \src "ls180.v:1228.6-1228.36" + wire \main_sdphy_cmdw_pads_out_ready + attribute \src "ls180.v:1236.5-1236.30" + wire \main_sdphy_cmdw_sink_last + attribute \src "ls180.v:1237.11-1237.44" + wire width 8 \main_sdphy_cmdw_sink_payload_data + attribute \src "ls180.v:1235.5-1235.31" + wire \main_sdphy_cmdw_sink_ready + attribute \src "ls180.v:1234.5-1234.31" + wire \main_sdphy_cmdw_sink_valid + attribute \src "ls180.v:1423.11-1423.33" + wire width 10 \main_sdphy_datar_count + attribute \src "ls180.v:1922.11-1922.62" + wire width 10 \main_sdphy_datar_count_sdphy_sdphydatar_next_value0 + attribute \src "ls180.v:1923.5-1923.59" + wire \main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0 + attribute \src "ls180.v:1463.6-1463.43" + wire \main_sdphy_datar_datar_buf_sink_first + attribute \src "ls180.v:1464.6-1464.42" + wire \main_sdphy_datar_datar_buf_sink_last + attribute \src "ls180.v:1465.12-1465.56" + wire width 8 \main_sdphy_datar_datar_buf_sink_payload_data + attribute \src "ls180.v:1462.6-1462.43" + wire \main_sdphy_datar_datar_buf_sink_ready + attribute \src "ls180.v:1461.6-1461.43" + wire \main_sdphy_datar_datar_buf_sink_valid + attribute \src "ls180.v:1468.5-1468.44" + wire \main_sdphy_datar_datar_buf_source_first + attribute \src "ls180.v:1469.5-1469.43" + wire \main_sdphy_datar_datar_buf_source_last + attribute \src "ls180.v:1470.11-1470.57" + wire width 8 \main_sdphy_datar_datar_buf_source_payload_data + attribute \src "ls180.v:1467.6-1467.45" + wire \main_sdphy_datar_datar_buf_source_ready + attribute \src "ls180.v:1466.5-1466.44" + wire \main_sdphy_datar_datar_buf_source_valid + attribute \src "ls180.v:1453.5-1453.43" + wire \main_sdphy_datar_datar_converter_demux + attribute \src "ls180.v:1454.6-1454.48" + wire \main_sdphy_datar_datar_converter_load_part + attribute \src "ls180.v:1444.5-1444.48" + wire \main_sdphy_datar_datar_converter_sink_first + attribute \src "ls180.v:1445.5-1445.47" + wire \main_sdphy_datar_datar_converter_sink_last + attribute \src "ls180.v:1446.12-1446.62" + wire width 4 \main_sdphy_datar_datar_converter_sink_payload_data + attribute \src "ls180.v:1443.6-1443.49" + wire \main_sdphy_datar_datar_converter_sink_ready + attribute \src "ls180.v:1442.6-1442.49" + wire \main_sdphy_datar_datar_converter_sink_valid + attribute \src "ls180.v:1449.5-1449.50" + wire \main_sdphy_datar_datar_converter_source_first + attribute \src "ls180.v:1450.5-1450.49" + wire \main_sdphy_datar_datar_converter_source_last + attribute \src "ls180.v:1451.11-1451.63" + wire width 8 \main_sdphy_datar_datar_converter_source_payload_data + attribute \src "ls180.v:1452.11-1452.76" + wire width 2 \main_sdphy_datar_datar_converter_source_payload_valid_token_count + attribute \src "ls180.v:1448.6-1448.51" + wire \main_sdphy_datar_datar_converter_source_ready + attribute \src "ls180.v:1447.6-1447.51" + wire \main_sdphy_datar_datar_converter_source_valid + attribute \src "ls180.v:1455.5-1455.48" + wire \main_sdphy_datar_datar_converter_strobe_all + attribute \src "ls180.v:1426.6-1426.42" + wire \main_sdphy_datar_datar_pads_in_first + attribute \src "ls180.v:1427.6-1427.41" + wire \main_sdphy_datar_datar_pads_in_last + attribute \src "ls180.v:1428.6-1428.48" + wire \main_sdphy_datar_datar_pads_in_payload_clk + attribute \src "ls180.v:1429.6-1429.50" + wire \main_sdphy_datar_datar_pads_in_payload_cmd_i + attribute \src "ls180.v:1430.6-1430.50" + wire \main_sdphy_datar_datar_pads_in_payload_cmd_o + attribute \src "ls180.v:1431.6-1431.51" + wire \main_sdphy_datar_datar_pads_in_payload_cmd_oe + attribute \src "ls180.v:1432.12-1432.57" + wire width 4 \main_sdphy_datar_datar_pads_in_payload_data_i + attribute \src "ls180.v:1433.12-1433.57" + wire width 4 \main_sdphy_datar_datar_pads_in_payload_data_o + attribute \src "ls180.v:1434.6-1434.52" + wire \main_sdphy_datar_datar_pads_in_payload_data_oe + attribute \src "ls180.v:1425.5-1425.41" + wire \main_sdphy_datar_datar_pads_in_ready + attribute \src "ls180.v:1424.6-1424.42" + wire \main_sdphy_datar_datar_pads_in_valid + attribute \src "ls180.v:1471.5-1471.33" + wire \main_sdphy_datar_datar_reset + attribute \src "ls180.v:1926.5-1926.62" + wire \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2 + attribute \src "ls180.v:1927.5-1927.65" + wire \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2 + attribute \src "ls180.v:1441.5-1441.31" + wire \main_sdphy_datar_datar_run + attribute \src "ls180.v:1437.6-1437.49" + wire \main_sdphy_datar_datar_source_source_first0 + attribute \src "ls180.v:1458.6-1458.49" + wire \main_sdphy_datar_datar_source_source_first1 + attribute \src "ls180.v:1438.6-1438.48" + wire \main_sdphy_datar_datar_source_source_last0 + attribute \src "ls180.v:1459.6-1459.48" + wire \main_sdphy_datar_datar_source_source_last1 + attribute \src "ls180.v:1439.12-1439.62" + wire width 8 \main_sdphy_datar_datar_source_source_payload_data0 + attribute \src "ls180.v:1460.12-1460.62" + wire width 8 \main_sdphy_datar_datar_source_source_payload_data1 + attribute \src "ls180.v:1436.5-1436.48" + wire \main_sdphy_datar_datar_source_source_ready0 + attribute \src "ls180.v:1457.6-1457.49" + wire \main_sdphy_datar_datar_source_source_ready1 + attribute \src "ls180.v:1435.6-1435.49" + wire \main_sdphy_datar_datar_source_source_valid0 + attribute \src "ls180.v:1456.6-1456.49" + wire \main_sdphy_datar_datar_source_source_valid1 + attribute \src "ls180.v:1440.6-1440.34" + wire \main_sdphy_datar_datar_start + attribute \src "ls180.v:1396.5-1396.43" + wire \main_sdphy_datar_pads_in_pads_in_first + attribute \src "ls180.v:1397.5-1397.42" + wire \main_sdphy_datar_pads_in_pads_in_last + attribute \src "ls180.v:1398.5-1398.49" + wire \main_sdphy_datar_pads_in_pads_in_payload_clk + attribute \src "ls180.v:1399.6-1399.52" + wire \main_sdphy_datar_pads_in_pads_in_payload_cmd_i + attribute \src "ls180.v:1400.5-1400.51" + wire \main_sdphy_datar_pads_in_pads_in_payload_cmd_o + attribute \src "ls180.v:1401.5-1401.52" + wire \main_sdphy_datar_pads_in_pads_in_payload_cmd_oe + attribute \src "ls180.v:1402.12-1402.59" + wire width 4 \main_sdphy_datar_pads_in_pads_in_payload_data_i + attribute \src "ls180.v:1403.11-1403.58" + wire width 4 \main_sdphy_datar_pads_in_pads_in_payload_data_o + attribute \src "ls180.v:1404.5-1404.53" + wire \main_sdphy_datar_pads_in_pads_in_payload_data_oe + attribute \src "ls180.v:1395.6-1395.44" + wire \main_sdphy_datar_pads_in_pads_in_ready + attribute \src "ls180.v:1394.6-1394.44" + wire \main_sdphy_datar_pads_in_pads_in_valid + attribute \src "ls180.v:1406.5-1406.42" + wire \main_sdphy_datar_pads_out_payload_clk + attribute \src "ls180.v:1407.5-1407.44" + wire \main_sdphy_datar_pads_out_payload_cmd_o + attribute \src "ls180.v:1408.5-1408.45" + wire \main_sdphy_datar_pads_out_payload_cmd_oe + attribute \src "ls180.v:1409.11-1409.51" + wire width 4 \main_sdphy_datar_pads_out_payload_data_o + attribute \src "ls180.v:1410.5-1410.46" + wire \main_sdphy_datar_pads_out_payload_data_oe + attribute \src "ls180.v:1405.6-1405.37" + wire \main_sdphy_datar_pads_out_ready + attribute \src "ls180.v:1413.5-1413.31" + wire \main_sdphy_datar_sink_last + attribute \src "ls180.v:1414.11-1414.53" + wire width 10 \main_sdphy_datar_sink_payload_block_length + attribute \src "ls180.v:1412.5-1412.32" + wire \main_sdphy_datar_sink_ready + attribute \src "ls180.v:1411.5-1411.32" + wire \main_sdphy_datar_sink_valid + attribute \src "ls180.v:1417.5-1417.34" + wire \main_sdphy_datar_source_first + attribute \src "ls180.v:1418.5-1418.33" + wire \main_sdphy_datar_source_last + attribute \src "ls180.v:1419.11-1419.47" + wire width 8 \main_sdphy_datar_source_payload_data + attribute \src "ls180.v:1420.11-1420.49" + wire width 3 \main_sdphy_datar_source_payload_status + attribute \src "ls180.v:1416.5-1416.34" + wire \main_sdphy_datar_source_ready + attribute \src "ls180.v:1415.5-1415.34" + wire \main_sdphy_datar_source_valid + attribute \src "ls180.v:1421.5-1421.26" + wire \main_sdphy_datar_stop + attribute \src "ls180.v:1422.12-1422.36" + wire width 32 \main_sdphy_datar_timeout + attribute \src "ls180.v:1924.12-1924.65" + wire width 32 \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1 + attribute \src "ls180.v:1925.5-1925.61" + wire \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1 + attribute \src "ls180.v:1331.11-1331.33" + wire width 8 \main_sdphy_dataw_count + attribute \src "ls180.v:1918.11-1918.54" + wire width 8 \main_sdphy_dataw_count_sdphy_fsm_next_value + attribute \src "ls180.v:1919.5-1919.51" + wire \main_sdphy_dataw_count_sdphy_fsm_next_value_ce + attribute \src "ls180.v:1385.6-1385.42" + wire \main_sdphy_dataw_crcr_buf_sink_first + attribute \src "ls180.v:1386.6-1386.41" + wire \main_sdphy_dataw_crcr_buf_sink_last + attribute \src "ls180.v:1387.12-1387.55" + wire width 8 \main_sdphy_dataw_crcr_buf_sink_payload_data + attribute \src "ls180.v:1384.6-1384.42" + wire \main_sdphy_dataw_crcr_buf_sink_ready + attribute \src "ls180.v:1383.6-1383.42" + wire \main_sdphy_dataw_crcr_buf_sink_valid + attribute \src "ls180.v:1390.5-1390.43" + wire \main_sdphy_dataw_crcr_buf_source_first + attribute \src "ls180.v:1391.5-1391.42" + wire \main_sdphy_dataw_crcr_buf_source_last + attribute \src "ls180.v:1392.11-1392.56" + wire width 8 \main_sdphy_dataw_crcr_buf_source_payload_data + attribute \src "ls180.v:1389.6-1389.44" + wire \main_sdphy_dataw_crcr_buf_source_ready + attribute \src "ls180.v:1388.5-1388.43" + wire \main_sdphy_dataw_crcr_buf_source_valid + attribute \src "ls180.v:1375.11-1375.48" + wire width 3 \main_sdphy_dataw_crcr_converter_demux + attribute \src "ls180.v:1376.6-1376.47" + wire \main_sdphy_dataw_crcr_converter_load_part + attribute \src "ls180.v:1366.5-1366.47" + wire \main_sdphy_dataw_crcr_converter_sink_first + attribute \src "ls180.v:1367.5-1367.46" + wire \main_sdphy_dataw_crcr_converter_sink_last + attribute \src "ls180.v:1368.6-1368.55" + wire \main_sdphy_dataw_crcr_converter_sink_payload_data + attribute \src "ls180.v:1365.6-1365.48" + wire \main_sdphy_dataw_crcr_converter_sink_ready + attribute \src "ls180.v:1364.6-1364.48" + wire \main_sdphy_dataw_crcr_converter_sink_valid + attribute \src "ls180.v:1371.5-1371.49" + wire \main_sdphy_dataw_crcr_converter_source_first + attribute \src "ls180.v:1372.5-1372.48" + wire \main_sdphy_dataw_crcr_converter_source_last + attribute \src "ls180.v:1373.11-1373.62" + wire width 8 \main_sdphy_dataw_crcr_converter_source_payload_data + attribute \src "ls180.v:1374.11-1374.75" + wire width 4 \main_sdphy_dataw_crcr_converter_source_payload_valid_token_count + attribute \src "ls180.v:1370.6-1370.50" + wire \main_sdphy_dataw_crcr_converter_source_ready + attribute \src "ls180.v:1369.6-1369.50" + wire \main_sdphy_dataw_crcr_converter_source_valid + attribute \src "ls180.v:1377.5-1377.47" + wire \main_sdphy_dataw_crcr_converter_strobe_all + attribute \src "ls180.v:1348.6-1348.41" + wire \main_sdphy_dataw_crcr_pads_in_first + attribute \src "ls180.v:1349.6-1349.40" + wire \main_sdphy_dataw_crcr_pads_in_last + attribute \src "ls180.v:1350.6-1350.47" + wire \main_sdphy_dataw_crcr_pads_in_payload_clk + attribute \src "ls180.v:1351.6-1351.49" + wire \main_sdphy_dataw_crcr_pads_in_payload_cmd_i + attribute \src "ls180.v:1352.6-1352.49" + wire \main_sdphy_dataw_crcr_pads_in_payload_cmd_o + attribute \src "ls180.v:1353.6-1353.50" + wire \main_sdphy_dataw_crcr_pads_in_payload_cmd_oe + attribute \src "ls180.v:1354.12-1354.56" + wire width 4 \main_sdphy_dataw_crcr_pads_in_payload_data_i + attribute \src "ls180.v:1355.12-1355.56" + wire width 4 \main_sdphy_dataw_crcr_pads_in_payload_data_o + attribute \src "ls180.v:1356.6-1356.51" + wire \main_sdphy_dataw_crcr_pads_in_payload_data_oe + attribute \src "ls180.v:1347.5-1347.40" + wire \main_sdphy_dataw_crcr_pads_in_ready + attribute \src "ls180.v:1346.6-1346.41" + wire \main_sdphy_dataw_crcr_pads_in_valid + attribute \src "ls180.v:1393.5-1393.32" + wire \main_sdphy_dataw_crcr_reset + attribute \src "ls180.v:1914.5-1914.59" + wire \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value + attribute \src "ls180.v:1915.5-1915.62" + wire \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce + attribute \src "ls180.v:1363.5-1363.30" + wire \main_sdphy_dataw_crcr_run + attribute \src "ls180.v:1359.6-1359.48" + wire \main_sdphy_dataw_crcr_source_source_first0 + attribute \src "ls180.v:1380.6-1380.48" + wire \main_sdphy_dataw_crcr_source_source_first1 + attribute \src "ls180.v:1360.6-1360.47" + wire \main_sdphy_dataw_crcr_source_source_last0 + attribute \src "ls180.v:1381.6-1381.47" + wire \main_sdphy_dataw_crcr_source_source_last1 + attribute \src "ls180.v:1361.12-1361.61" + wire width 8 \main_sdphy_dataw_crcr_source_source_payload_data0 + attribute \src "ls180.v:1382.12-1382.61" + wire width 8 \main_sdphy_dataw_crcr_source_source_payload_data1 + attribute \src "ls180.v:1358.5-1358.47" + wire \main_sdphy_dataw_crcr_source_source_ready0 + attribute \src "ls180.v:1379.6-1379.48" + wire \main_sdphy_dataw_crcr_source_source_ready1 + attribute \src "ls180.v:1357.6-1357.48" + wire \main_sdphy_dataw_crcr_source_source_valid0 + attribute \src "ls180.v:1378.6-1378.48" + wire \main_sdphy_dataw_crcr_source_source_valid1 + attribute \src "ls180.v:1362.6-1362.33" + wire \main_sdphy_dataw_crcr_start + attribute \src "ls180.v:1345.5-1345.27" + wire \main_sdphy_dataw_error + attribute \src "ls180.v:1334.5-1334.43" + wire \main_sdphy_dataw_pads_in_pads_in_first + attribute \src "ls180.v:1335.5-1335.42" + wire \main_sdphy_dataw_pads_in_pads_in_last + attribute \src "ls180.v:1336.5-1336.49" + wire \main_sdphy_dataw_pads_in_pads_in_payload_clk + attribute \src "ls180.v:1337.5-1337.51" + wire \main_sdphy_dataw_pads_in_pads_in_payload_cmd_i + attribute \src "ls180.v:1338.5-1338.51" + wire \main_sdphy_dataw_pads_in_pads_in_payload_cmd_o + attribute \src "ls180.v:1339.5-1339.52" + wire \main_sdphy_dataw_pads_in_pads_in_payload_cmd_oe + attribute \src "ls180.v:1340.11-1340.58" + wire width 4 \main_sdphy_dataw_pads_in_pads_in_payload_data_i + attribute \src "ls180.v:1341.11-1341.58" + wire width 4 \main_sdphy_dataw_pads_in_pads_in_payload_data_o + attribute \src "ls180.v:1342.5-1342.53" + wire \main_sdphy_dataw_pads_in_pads_in_payload_data_oe + attribute \src "ls180.v:1333.6-1333.44" + wire \main_sdphy_dataw_pads_in_pads_in_ready + attribute \src "ls180.v:1332.5-1332.43" + wire \main_sdphy_dataw_pads_in_pads_in_valid + attribute \src "ls180.v:1317.6-1317.44" + wire \main_sdphy_dataw_pads_in_payload_cmd_i + attribute \src "ls180.v:1318.12-1318.51" + wire width 4 \main_sdphy_dataw_pads_in_payload_data_i + attribute \src "ls180.v:1316.6-1316.36" + wire \main_sdphy_dataw_pads_in_valid + attribute \src "ls180.v:1320.5-1320.42" + wire \main_sdphy_dataw_pads_out_payload_clk + attribute \src "ls180.v:1321.5-1321.44" + wire \main_sdphy_dataw_pads_out_payload_cmd_o + attribute \src "ls180.v:1322.5-1322.45" + wire \main_sdphy_dataw_pads_out_payload_cmd_oe + attribute \src "ls180.v:1323.11-1323.51" + wire width 4 \main_sdphy_dataw_pads_out_payload_data_o + attribute \src "ls180.v:1324.5-1324.46" + wire \main_sdphy_dataw_pads_out_payload_data_oe + attribute \src "ls180.v:1319.6-1319.37" + wire \main_sdphy_dataw_pads_out_ready + attribute \src "ls180.v:1327.5-1327.32" + wire \main_sdphy_dataw_sink_first + attribute \src "ls180.v:1328.5-1328.31" + wire \main_sdphy_dataw_sink_last + attribute \src "ls180.v:1329.11-1329.45" + wire width 8 \main_sdphy_dataw_sink_payload_data + attribute \src "ls180.v:1326.5-1326.32" + wire \main_sdphy_dataw_sink_ready + attribute \src "ls180.v:1325.5-1325.32" + wire \main_sdphy_dataw_sink_valid + attribute \src "ls180.v:1343.5-1343.27" + wire \main_sdphy_dataw_start + attribute \src "ls180.v:1330.5-1330.26" + wire \main_sdphy_dataw_stop + attribute \src "ls180.v:1344.5-1344.27" + wire \main_sdphy_dataw_valid + attribute \src "ls180.v:1224.11-1224.32" + wire width 8 \main_sdphy_init_count + attribute \src "ls180.v:1898.11-1898.59" + wire width 8 \main_sdphy_init_count_sdphy_sdphyinit_next_value + attribute \src "ls180.v:1899.5-1899.56" + wire \main_sdphy_init_count_sdphy_sdphyinit_next_value_ce + attribute \src "ls180.v:1212.6-1212.34" + wire \main_sdphy_init_initialize_r + attribute \src "ls180.v:1211.6-1211.35" + wire \main_sdphy_init_initialize_re + attribute \src "ls180.v:1214.5-1214.33" + wire \main_sdphy_init_initialize_w + attribute \src "ls180.v:1213.6-1213.35" + wire \main_sdphy_init_initialize_we + attribute \src "ls180.v:1216.6-1216.43" + wire \main_sdphy_init_pads_in_payload_cmd_i + attribute \src "ls180.v:1217.12-1217.50" + wire width 4 \main_sdphy_init_pads_in_payload_data_i + attribute \src "ls180.v:1215.6-1215.35" + wire \main_sdphy_init_pads_in_valid + attribute \src "ls180.v:1219.5-1219.41" + wire \main_sdphy_init_pads_out_payload_clk + attribute \src "ls180.v:1220.5-1220.43" + wire \main_sdphy_init_pads_out_payload_cmd_o + attribute \src "ls180.v:1221.5-1221.44" + wire \main_sdphy_init_pads_out_payload_cmd_oe + attribute \src "ls180.v:1222.11-1222.50" + wire width 4 \main_sdphy_init_pads_out_payload_data_o + attribute \src "ls180.v:1223.5-1223.45" + wire \main_sdphy_init_pads_out_payload_data_oe + attribute \src "ls180.v:1218.6-1218.36" + wire \main_sdphy_init_pads_out_ready + attribute \src "ls180.v:1472.6-1472.27" + wire \main_sdphy_sdpads_clk + attribute \src "ls180.v:1473.5-1473.28" + wire \main_sdphy_sdpads_cmd_i + attribute \src "ls180.v:1474.6-1474.29" + wire \main_sdphy_sdpads_cmd_o + attribute \src "ls180.v:1475.6-1475.30" + wire \main_sdphy_sdpads_cmd_oe + attribute \src "ls180.v:1476.11-1476.35" + wire width 4 \main_sdphy_sdpads_data_i + attribute \src "ls180.v:1477.12-1477.36" + wire width 4 \main_sdphy_sdpads_data_o + attribute \src "ls180.v:1478.6-1478.31" + wire \main_sdphy_sdpads_data_oe + attribute \src "ls180.v:1201.6-1201.23" + wire \main_sdphy_status + attribute \src "ls180.v:1202.6-1202.19" + wire \main_sdphy_we + attribute \src "ls180.v:418.5-418.26" + wire \main_sdram_address_re + attribute \src "ls180.v:417.12-417.38" + wire width 13 \main_sdram_address_storage + attribute \src "ls180.v:420.5-420.27" + wire \main_sdram_baddress_re + attribute \src "ls180.v:419.11-419.38" + wire width 2 \main_sdram_baddress_storage + attribute \src "ls180.v:516.5-516.43" + wire \main_sdram_bankmachine0_auto_precharge + attribute \src "ls180.v:538.11-538.63" + wire width 3 \main_sdram_bankmachine0_cmd_buffer_lookahead_consume + attribute \src "ls180.v:543.6-543.58" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read + attribute \src "ls180.v:548.6-548.64" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first + attribute \src "ls180.v:549.6-549.63" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last + attribute \src "ls180.v:547.13-547.78" + wire width 22 \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr + attribute \src "ls180.v:546.6-546.69" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we + attribute \src "ls180.v:552.6-552.65" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first + attribute \src "ls180.v:553.6-553.64" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last + attribute \src "ls180.v:551.13-551.79" + wire width 22 \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr + attribute \src "ls180.v:550.6-550.70" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we + attribute \src "ls180.v:535.11-535.61" + wire width 4 \main_sdram_bankmachine0_cmd_buffer_lookahead_level + attribute \src "ls180.v:537.11-537.63" + wire width 3 \main_sdram_bankmachine0_cmd_buffer_lookahead_produce + attribute \src "ls180.v:544.12-544.67" + wire width 3 \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr + attribute \src "ls180.v:545.13-545.70" + wire width 25 \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r + attribute \src "ls180.v:536.5-536.57" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_replace + attribute \src "ls180.v:519.5-519.60" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first + attribute \src "ls180.v:520.5-520.59" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last + attribute \src "ls180.v:522.13-522.75" + wire width 22 \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_addr + attribute \src "ls180.v:521.6-521.66" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we + attribute \src "ls180.v:518.6-518.61" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_ready + attribute \src "ls180.v:517.6-517.61" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_valid + attribute \src "ls180.v:525.6-525.63" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_source_first + attribute \src "ls180.v:526.6-526.62" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_source_last + attribute \src "ls180.v:528.13-528.77" + wire width 22 \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr + attribute \src "ls180.v:527.6-527.68" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we + attribute \src "ls180.v:524.6-524.63" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_source_ready + attribute \src "ls180.v:523.6-523.63" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_source_valid + attribute \src "ls180.v:533.13-533.71" + wire width 25 \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din + attribute \src "ls180.v:534.13-534.72" + wire width 25 \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout + attribute \src "ls180.v:531.6-531.63" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re + attribute \src "ls180.v:532.6-532.69" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable + attribute \src "ls180.v:529.6-529.63" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we + attribute \src "ls180.v:530.6-530.69" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable + attribute \src "ls180.v:539.11-539.66" + wire width 3 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr + attribute \src "ls180.v:540.13-540.70" + wire width 25 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_r + attribute \src "ls180.v:542.13-542.70" + wire width 25 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w + attribute \src "ls180.v:541.6-541.60" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_we + attribute \src "ls180.v:556.6-556.51" + wire \main_sdram_bankmachine0_cmd_buffer_sink_first + attribute \src "ls180.v:557.6-557.50" + wire \main_sdram_bankmachine0_cmd_buffer_sink_last + attribute \src "ls180.v:559.13-559.65" + wire width 22 \main_sdram_bankmachine0_cmd_buffer_sink_payload_addr + attribute \src "ls180.v:558.6-558.56" + wire \main_sdram_bankmachine0_cmd_buffer_sink_payload_we + attribute \src "ls180.v:555.6-555.51" + wire \main_sdram_bankmachine0_cmd_buffer_sink_ready + attribute \src "ls180.v:554.6-554.51" + wire \main_sdram_bankmachine0_cmd_buffer_sink_valid + attribute \src "ls180.v:562.5-562.52" + wire \main_sdram_bankmachine0_cmd_buffer_source_first + attribute \src "ls180.v:563.5-563.51" + wire \main_sdram_bankmachine0_cmd_buffer_source_last + attribute \src "ls180.v:565.12-565.66" + wire width 22 \main_sdram_bankmachine0_cmd_buffer_source_payload_addr + attribute \src "ls180.v:564.5-564.57" + wire \main_sdram_bankmachine0_cmd_buffer_source_payload_we + attribute \src "ls180.v:561.6-561.53" + wire \main_sdram_bankmachine0_cmd_buffer_source_ready + attribute \src "ls180.v:560.5-560.52" + wire \main_sdram_bankmachine0_cmd_buffer_source_valid + attribute \src "ls180.v:508.12-508.49" + wire width 13 \main_sdram_bankmachine0_cmd_payload_a + attribute \src "ls180.v:509.12-509.50" + wire width 2 \main_sdram_bankmachine0_cmd_payload_ba + attribute \src "ls180.v:510.5-510.44" + wire \main_sdram_bankmachine0_cmd_payload_cas + attribute \src "ls180.v:513.5-513.47" + wire \main_sdram_bankmachine0_cmd_payload_is_cmd + attribute \src "ls180.v:514.5-514.48" + wire \main_sdram_bankmachine0_cmd_payload_is_read + attribute \src "ls180.v:515.5-515.49" + wire \main_sdram_bankmachine0_cmd_payload_is_write + attribute \src "ls180.v:511.5-511.44" + wire \main_sdram_bankmachine0_cmd_payload_ras + attribute \src "ls180.v:512.5-512.43" + wire \main_sdram_bankmachine0_cmd_payload_we + attribute \src "ls180.v:507.5-507.38" + wire \main_sdram_bankmachine0_cmd_ready + attribute \src "ls180.v:506.5-506.38" + wire \main_sdram_bankmachine0_cmd_valid + attribute \src "ls180.v:505.5-505.40" + wire \main_sdram_bankmachine0_refresh_gnt + attribute \src "ls180.v:504.6-504.41" + wire \main_sdram_bankmachine0_refresh_req + attribute \src "ls180.v:500.13-500.45" + wire width 22 \main_sdram_bankmachine0_req_addr + attribute \src "ls180.v:501.6-501.38" + wire \main_sdram_bankmachine0_req_lock + attribute \src "ls180.v:503.5-503.44" + wire \main_sdram_bankmachine0_req_rdata_valid + attribute \src "ls180.v:498.6-498.39" + wire \main_sdram_bankmachine0_req_ready + attribute \src "ls180.v:497.6-497.39" + wire \main_sdram_bankmachine0_req_valid + attribute \src "ls180.v:502.5-502.44" + wire \main_sdram_bankmachine0_req_wdata_ready + attribute \src "ls180.v:499.6-499.36" + wire \main_sdram_bankmachine0_req_we + attribute \src "ls180.v:566.12-566.39" + wire width 13 \main_sdram_bankmachine0_row + attribute \src "ls180.v:570.5-570.38" + wire \main_sdram_bankmachine0_row_close + attribute \src "ls180.v:571.5-571.47" + wire \main_sdram_bankmachine0_row_col_n_addr_sel + attribute \src "ls180.v:568.6-568.37" + wire \main_sdram_bankmachine0_row_hit + attribute \src "ls180.v:569.5-569.37" + wire \main_sdram_bankmachine0_row_open + attribute \src "ls180.v:567.5-567.39" + wire \main_sdram_bankmachine0_row_opened + attribute \no_retiming "true" + attribute \src "ls180.v:578.32-578.69" + wire \main_sdram_bankmachine0_trascon_ready + attribute \src "ls180.v:577.6-577.43" + wire \main_sdram_bankmachine0_trascon_valid + attribute \no_retiming "true" + attribute \src "ls180.v:576.32-576.68" + wire \main_sdram_bankmachine0_trccon_ready + attribute \src "ls180.v:575.6-575.42" + wire \main_sdram_bankmachine0_trccon_valid + attribute \src "ls180.v:574.11-574.48" + wire width 3 \main_sdram_bankmachine0_twtpcon_count + attribute \no_retiming "true" + attribute \src "ls180.v:573.32-573.69" + wire \main_sdram_bankmachine0_twtpcon_ready + attribute \src "ls180.v:572.6-572.43" + wire \main_sdram_bankmachine0_twtpcon_valid + attribute \src "ls180.v:598.5-598.43" + wire \main_sdram_bankmachine1_auto_precharge + attribute \src "ls180.v:620.11-620.63" + wire width 3 \main_sdram_bankmachine1_cmd_buffer_lookahead_consume + attribute \src "ls180.v:625.6-625.58" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read + attribute \src "ls180.v:630.6-630.64" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first + attribute \src "ls180.v:631.6-631.63" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last + attribute \src "ls180.v:629.13-629.78" + wire width 22 \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr + attribute \src "ls180.v:628.6-628.69" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we + attribute \src "ls180.v:634.6-634.65" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first + attribute \src "ls180.v:635.6-635.64" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last + attribute \src "ls180.v:633.13-633.79" + wire width 22 \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr + attribute \src "ls180.v:632.6-632.70" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we + attribute \src "ls180.v:617.11-617.61" + wire width 4 \main_sdram_bankmachine1_cmd_buffer_lookahead_level + attribute \src "ls180.v:619.11-619.63" + wire width 3 \main_sdram_bankmachine1_cmd_buffer_lookahead_produce + attribute \src "ls180.v:626.12-626.67" + wire width 3 \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr + attribute \src "ls180.v:627.13-627.70" + wire width 25 \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r + attribute \src "ls180.v:618.5-618.57" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_replace + attribute \src "ls180.v:601.5-601.60" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first + attribute \src "ls180.v:602.5-602.59" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last + attribute \src "ls180.v:604.13-604.75" + wire width 22 \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_addr + attribute \src "ls180.v:603.6-603.66" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we + attribute \src "ls180.v:600.6-600.61" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_ready + attribute \src "ls180.v:599.6-599.61" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_valid + attribute \src "ls180.v:607.6-607.63" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_source_first + attribute \src "ls180.v:608.6-608.62" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_source_last + attribute \src "ls180.v:610.13-610.77" + wire width 22 \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr + attribute \src "ls180.v:609.6-609.68" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we + attribute \src "ls180.v:606.6-606.63" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_source_ready + attribute \src "ls180.v:605.6-605.63" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_source_valid + attribute \src "ls180.v:615.13-615.71" + wire width 25 \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din + attribute \src "ls180.v:616.13-616.72" + wire width 25 \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout + attribute \src "ls180.v:613.6-613.63" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re + attribute \src "ls180.v:614.6-614.69" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable + attribute \src "ls180.v:611.6-611.63" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we + attribute \src "ls180.v:612.6-612.69" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable + attribute \src "ls180.v:621.11-621.66" + wire width 3 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr + attribute \src "ls180.v:622.13-622.70" + wire width 25 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_r + attribute \src "ls180.v:624.13-624.70" + wire width 25 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w + attribute \src "ls180.v:623.6-623.60" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_we + attribute \src "ls180.v:638.6-638.51" + wire \main_sdram_bankmachine1_cmd_buffer_sink_first + attribute \src "ls180.v:639.6-639.50" + wire \main_sdram_bankmachine1_cmd_buffer_sink_last + attribute \src "ls180.v:641.13-641.65" + wire width 22 \main_sdram_bankmachine1_cmd_buffer_sink_payload_addr + attribute \src "ls180.v:640.6-640.56" + wire \main_sdram_bankmachine1_cmd_buffer_sink_payload_we + attribute \src "ls180.v:637.6-637.51" + wire \main_sdram_bankmachine1_cmd_buffer_sink_ready + attribute \src "ls180.v:636.6-636.51" + wire \main_sdram_bankmachine1_cmd_buffer_sink_valid + attribute \src "ls180.v:644.5-644.52" + wire \main_sdram_bankmachine1_cmd_buffer_source_first + attribute \src "ls180.v:645.5-645.51" + wire \main_sdram_bankmachine1_cmd_buffer_source_last + attribute \src "ls180.v:647.12-647.66" + wire width 22 \main_sdram_bankmachine1_cmd_buffer_source_payload_addr + attribute \src "ls180.v:646.5-646.57" + wire \main_sdram_bankmachine1_cmd_buffer_source_payload_we + attribute \src "ls180.v:643.6-643.53" + wire \main_sdram_bankmachine1_cmd_buffer_source_ready + attribute \src "ls180.v:642.5-642.52" + wire \main_sdram_bankmachine1_cmd_buffer_source_valid + attribute \src "ls180.v:590.12-590.49" + wire width 13 \main_sdram_bankmachine1_cmd_payload_a + attribute \src "ls180.v:591.12-591.50" + wire width 2 \main_sdram_bankmachine1_cmd_payload_ba + attribute \src "ls180.v:592.5-592.44" + wire \main_sdram_bankmachine1_cmd_payload_cas + attribute \src "ls180.v:595.5-595.47" + wire \main_sdram_bankmachine1_cmd_payload_is_cmd + attribute \src "ls180.v:596.5-596.48" + wire \main_sdram_bankmachine1_cmd_payload_is_read + attribute \src "ls180.v:597.5-597.49" + wire \main_sdram_bankmachine1_cmd_payload_is_write + attribute \src "ls180.v:593.5-593.44" + wire \main_sdram_bankmachine1_cmd_payload_ras + attribute \src "ls180.v:594.5-594.43" + wire \main_sdram_bankmachine1_cmd_payload_we + attribute \src "ls180.v:589.5-589.38" + wire \main_sdram_bankmachine1_cmd_ready + attribute \src "ls180.v:588.5-588.38" + wire \main_sdram_bankmachine1_cmd_valid + attribute \src "ls180.v:587.5-587.40" + wire \main_sdram_bankmachine1_refresh_gnt + attribute \src "ls180.v:586.6-586.41" + wire \main_sdram_bankmachine1_refresh_req + attribute \src "ls180.v:582.13-582.45" + wire width 22 \main_sdram_bankmachine1_req_addr + attribute \src "ls180.v:583.6-583.38" + wire \main_sdram_bankmachine1_req_lock + attribute \src "ls180.v:585.5-585.44" + wire \main_sdram_bankmachine1_req_rdata_valid + attribute \src "ls180.v:580.6-580.39" + wire \main_sdram_bankmachine1_req_ready + attribute \src "ls180.v:579.6-579.39" + wire \main_sdram_bankmachine1_req_valid + attribute \src "ls180.v:584.5-584.44" + wire \main_sdram_bankmachine1_req_wdata_ready + attribute \src "ls180.v:581.6-581.36" + wire \main_sdram_bankmachine1_req_we + attribute \src "ls180.v:648.12-648.39" + wire width 13 \main_sdram_bankmachine1_row + attribute \src "ls180.v:652.5-652.38" + wire \main_sdram_bankmachine1_row_close + attribute \src "ls180.v:653.5-653.47" + wire \main_sdram_bankmachine1_row_col_n_addr_sel + attribute \src "ls180.v:650.6-650.37" + wire \main_sdram_bankmachine1_row_hit + attribute \src "ls180.v:651.5-651.37" + wire \main_sdram_bankmachine1_row_open + attribute \src "ls180.v:649.5-649.39" + wire \main_sdram_bankmachine1_row_opened + attribute \no_retiming "true" + attribute \src "ls180.v:660.32-660.69" + wire \main_sdram_bankmachine1_trascon_ready + attribute \src "ls180.v:659.6-659.43" + wire \main_sdram_bankmachine1_trascon_valid + attribute \no_retiming "true" + attribute \src "ls180.v:658.32-658.68" + wire \main_sdram_bankmachine1_trccon_ready + attribute \src "ls180.v:657.6-657.42" + wire \main_sdram_bankmachine1_trccon_valid + attribute \src "ls180.v:656.11-656.48" + wire width 3 \main_sdram_bankmachine1_twtpcon_count + attribute \no_retiming "true" + attribute \src "ls180.v:655.32-655.69" + wire \main_sdram_bankmachine1_twtpcon_ready + attribute \src "ls180.v:654.6-654.43" + wire \main_sdram_bankmachine1_twtpcon_valid + attribute \src "ls180.v:680.5-680.43" + wire \main_sdram_bankmachine2_auto_precharge + attribute \src "ls180.v:702.11-702.63" + wire width 3 \main_sdram_bankmachine2_cmd_buffer_lookahead_consume + attribute \src "ls180.v:707.6-707.58" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read + attribute \src "ls180.v:712.6-712.64" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first + attribute \src "ls180.v:713.6-713.63" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last + attribute \src "ls180.v:711.13-711.78" + wire width 22 \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr + attribute \src "ls180.v:710.6-710.69" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we + attribute \src "ls180.v:716.6-716.65" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first + attribute \src "ls180.v:717.6-717.64" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last + attribute \src "ls180.v:715.13-715.79" + wire width 22 \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr + attribute \src "ls180.v:714.6-714.70" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we + attribute \src "ls180.v:699.11-699.61" + wire width 4 \main_sdram_bankmachine2_cmd_buffer_lookahead_level + attribute \src "ls180.v:701.11-701.63" + wire width 3 \main_sdram_bankmachine2_cmd_buffer_lookahead_produce + attribute \src "ls180.v:708.12-708.67" + wire width 3 \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr + attribute \src "ls180.v:709.13-709.70" + wire width 25 \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r + attribute \src "ls180.v:700.5-700.57" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_replace + attribute \src "ls180.v:683.5-683.60" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first + attribute \src "ls180.v:684.5-684.59" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last + attribute \src "ls180.v:686.13-686.75" + wire width 22 \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_addr + attribute \src "ls180.v:685.6-685.66" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we + attribute \src "ls180.v:682.6-682.61" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_ready + attribute \src "ls180.v:681.6-681.61" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_valid + attribute \src "ls180.v:689.6-689.63" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_source_first + attribute \src "ls180.v:690.6-690.62" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_source_last + attribute \src "ls180.v:692.13-692.77" + wire width 22 \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr + attribute \src "ls180.v:691.6-691.68" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we + attribute \src "ls180.v:688.6-688.63" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_source_ready + attribute \src "ls180.v:687.6-687.63" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_source_valid + attribute \src "ls180.v:697.13-697.71" + wire width 25 \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din + attribute \src "ls180.v:698.13-698.72" + wire width 25 \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout + attribute \src "ls180.v:695.6-695.63" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re + attribute \src "ls180.v:696.6-696.69" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable + attribute \src "ls180.v:693.6-693.63" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we + attribute \src "ls180.v:694.6-694.69" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable + attribute \src "ls180.v:703.11-703.66" + wire width 3 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr + attribute \src "ls180.v:704.13-704.70" + wire width 25 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_r + attribute \src "ls180.v:706.13-706.70" + wire width 25 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w + attribute \src "ls180.v:705.6-705.60" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_we + attribute \src "ls180.v:720.6-720.51" + wire \main_sdram_bankmachine2_cmd_buffer_sink_first + attribute \src "ls180.v:721.6-721.50" + wire \main_sdram_bankmachine2_cmd_buffer_sink_last + attribute \src "ls180.v:723.13-723.65" + wire width 22 \main_sdram_bankmachine2_cmd_buffer_sink_payload_addr + attribute \src "ls180.v:722.6-722.56" + wire \main_sdram_bankmachine2_cmd_buffer_sink_payload_we + attribute \src "ls180.v:719.6-719.51" + wire \main_sdram_bankmachine2_cmd_buffer_sink_ready + attribute \src "ls180.v:718.6-718.51" + wire \main_sdram_bankmachine2_cmd_buffer_sink_valid + attribute \src "ls180.v:726.5-726.52" + wire \main_sdram_bankmachine2_cmd_buffer_source_first + attribute \src "ls180.v:727.5-727.51" + wire \main_sdram_bankmachine2_cmd_buffer_source_last + attribute \src "ls180.v:729.12-729.66" + wire width 22 \main_sdram_bankmachine2_cmd_buffer_source_payload_addr + attribute \src "ls180.v:728.5-728.57" + wire \main_sdram_bankmachine2_cmd_buffer_source_payload_we + attribute \src "ls180.v:725.6-725.53" + wire \main_sdram_bankmachine2_cmd_buffer_source_ready + attribute \src "ls180.v:724.5-724.52" + wire \main_sdram_bankmachine2_cmd_buffer_source_valid + attribute \src "ls180.v:672.12-672.49" + wire width 13 \main_sdram_bankmachine2_cmd_payload_a + attribute \src "ls180.v:673.12-673.50" + wire width 2 \main_sdram_bankmachine2_cmd_payload_ba + attribute \src "ls180.v:674.5-674.44" + wire \main_sdram_bankmachine2_cmd_payload_cas + attribute \src "ls180.v:677.5-677.47" + wire \main_sdram_bankmachine2_cmd_payload_is_cmd + attribute \src "ls180.v:678.5-678.48" + wire \main_sdram_bankmachine2_cmd_payload_is_read + attribute \src "ls180.v:679.5-679.49" + wire \main_sdram_bankmachine2_cmd_payload_is_write + attribute \src "ls180.v:675.5-675.44" + wire \main_sdram_bankmachine2_cmd_payload_ras + attribute \src "ls180.v:676.5-676.43" + wire \main_sdram_bankmachine2_cmd_payload_we + attribute \src "ls180.v:671.5-671.38" + wire \main_sdram_bankmachine2_cmd_ready + attribute \src "ls180.v:670.5-670.38" + wire \main_sdram_bankmachine2_cmd_valid + attribute \src "ls180.v:669.5-669.40" + wire \main_sdram_bankmachine2_refresh_gnt + attribute \src "ls180.v:668.6-668.41" + wire \main_sdram_bankmachine2_refresh_req + attribute \src "ls180.v:664.13-664.45" + wire width 22 \main_sdram_bankmachine2_req_addr + attribute \src "ls180.v:665.6-665.38" + wire \main_sdram_bankmachine2_req_lock + attribute \src "ls180.v:667.5-667.44" + wire \main_sdram_bankmachine2_req_rdata_valid + attribute \src "ls180.v:662.6-662.39" + wire \main_sdram_bankmachine2_req_ready + attribute \src "ls180.v:661.6-661.39" + wire \main_sdram_bankmachine2_req_valid + attribute \src "ls180.v:666.5-666.44" + wire \main_sdram_bankmachine2_req_wdata_ready + attribute \src "ls180.v:663.6-663.36" + wire \main_sdram_bankmachine2_req_we + attribute \src "ls180.v:730.12-730.39" + wire width 13 \main_sdram_bankmachine2_row + attribute \src "ls180.v:734.5-734.38" + wire \main_sdram_bankmachine2_row_close + attribute \src "ls180.v:735.5-735.47" + wire \main_sdram_bankmachine2_row_col_n_addr_sel + attribute \src "ls180.v:732.6-732.37" + wire \main_sdram_bankmachine2_row_hit + attribute \src "ls180.v:733.5-733.37" + wire \main_sdram_bankmachine2_row_open + attribute \src "ls180.v:731.5-731.39" + wire \main_sdram_bankmachine2_row_opened + attribute \no_retiming "true" + attribute \src "ls180.v:742.32-742.69" + wire \main_sdram_bankmachine2_trascon_ready + attribute \src "ls180.v:741.6-741.43" + wire \main_sdram_bankmachine2_trascon_valid + attribute \no_retiming "true" + attribute \src "ls180.v:740.32-740.68" + wire \main_sdram_bankmachine2_trccon_ready + attribute \src "ls180.v:739.6-739.42" + wire \main_sdram_bankmachine2_trccon_valid + attribute \src "ls180.v:738.11-738.48" + wire width 3 \main_sdram_bankmachine2_twtpcon_count + attribute \no_retiming "true" + attribute \src "ls180.v:737.32-737.69" + wire \main_sdram_bankmachine2_twtpcon_ready + attribute \src "ls180.v:736.6-736.43" + wire \main_sdram_bankmachine2_twtpcon_valid + attribute \src "ls180.v:762.5-762.43" + wire \main_sdram_bankmachine3_auto_precharge + attribute \src "ls180.v:784.11-784.63" + wire width 3 \main_sdram_bankmachine3_cmd_buffer_lookahead_consume + attribute \src "ls180.v:789.6-789.58" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read + attribute \src "ls180.v:794.6-794.64" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first + attribute \src "ls180.v:795.6-795.63" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last + attribute \src "ls180.v:793.13-793.78" + wire width 22 \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr + attribute \src "ls180.v:792.6-792.69" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we + attribute \src "ls180.v:798.6-798.65" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first + attribute \src "ls180.v:799.6-799.64" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last + attribute \src "ls180.v:797.13-797.79" + wire width 22 \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr + attribute \src "ls180.v:796.6-796.70" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we + attribute \src "ls180.v:781.11-781.61" + wire width 4 \main_sdram_bankmachine3_cmd_buffer_lookahead_level + attribute \src "ls180.v:783.11-783.63" + wire width 3 \main_sdram_bankmachine3_cmd_buffer_lookahead_produce + attribute \src "ls180.v:790.12-790.67" + wire width 3 \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr + attribute \src "ls180.v:791.13-791.70" + wire width 25 \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r + attribute \src "ls180.v:782.5-782.57" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_replace + attribute \src "ls180.v:765.5-765.60" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first + attribute \src "ls180.v:766.5-766.59" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last + attribute \src "ls180.v:768.13-768.75" + wire width 22 \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_addr + attribute \src "ls180.v:767.6-767.66" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we + attribute \src "ls180.v:764.6-764.61" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_ready + attribute \src "ls180.v:763.6-763.61" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_valid + attribute \src "ls180.v:771.6-771.63" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_source_first + attribute \src "ls180.v:772.6-772.62" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_source_last + attribute \src "ls180.v:774.13-774.77" + wire width 22 \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr + attribute \src "ls180.v:773.6-773.68" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we + attribute \src "ls180.v:770.6-770.63" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_source_ready + attribute \src "ls180.v:769.6-769.63" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_source_valid + attribute \src "ls180.v:779.13-779.71" + wire width 25 \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din + attribute \src "ls180.v:780.13-780.72" + wire width 25 \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout + attribute \src "ls180.v:777.6-777.63" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re + attribute \src "ls180.v:778.6-778.69" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable + attribute \src "ls180.v:775.6-775.63" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we + attribute \src "ls180.v:776.6-776.69" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable + attribute \src "ls180.v:785.11-785.66" + wire width 3 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr + attribute \src "ls180.v:786.13-786.70" + wire width 25 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_r + attribute \src "ls180.v:788.13-788.70" + wire width 25 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w + attribute \src "ls180.v:787.6-787.60" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_we + attribute \src "ls180.v:802.6-802.51" + wire \main_sdram_bankmachine3_cmd_buffer_sink_first + attribute \src "ls180.v:803.6-803.50" + wire \main_sdram_bankmachine3_cmd_buffer_sink_last + attribute \src "ls180.v:805.13-805.65" + wire width 22 \main_sdram_bankmachine3_cmd_buffer_sink_payload_addr + attribute \src "ls180.v:804.6-804.56" + wire \main_sdram_bankmachine3_cmd_buffer_sink_payload_we + attribute \src "ls180.v:801.6-801.51" + wire \main_sdram_bankmachine3_cmd_buffer_sink_ready + attribute \src "ls180.v:800.6-800.51" + wire \main_sdram_bankmachine3_cmd_buffer_sink_valid + attribute \src "ls180.v:808.5-808.52" + wire \main_sdram_bankmachine3_cmd_buffer_source_first + attribute \src "ls180.v:809.5-809.51" + wire \main_sdram_bankmachine3_cmd_buffer_source_last + attribute \src "ls180.v:811.12-811.66" + wire width 22 \main_sdram_bankmachine3_cmd_buffer_source_payload_addr + attribute \src "ls180.v:810.5-810.57" + wire \main_sdram_bankmachine3_cmd_buffer_source_payload_we + attribute \src "ls180.v:807.6-807.53" + wire \main_sdram_bankmachine3_cmd_buffer_source_ready + attribute \src "ls180.v:806.5-806.52" + wire \main_sdram_bankmachine3_cmd_buffer_source_valid + attribute \src "ls180.v:754.12-754.49" + wire width 13 \main_sdram_bankmachine3_cmd_payload_a + attribute \src "ls180.v:755.12-755.50" + wire width 2 \main_sdram_bankmachine3_cmd_payload_ba + attribute \src "ls180.v:756.5-756.44" + wire \main_sdram_bankmachine3_cmd_payload_cas + attribute \src "ls180.v:759.5-759.47" + wire \main_sdram_bankmachine3_cmd_payload_is_cmd + attribute \src "ls180.v:760.5-760.48" + wire \main_sdram_bankmachine3_cmd_payload_is_read + attribute \src "ls180.v:761.5-761.49" + wire \main_sdram_bankmachine3_cmd_payload_is_write + attribute \src "ls180.v:757.5-757.44" + wire \main_sdram_bankmachine3_cmd_payload_ras + attribute \src "ls180.v:758.5-758.43" + wire \main_sdram_bankmachine3_cmd_payload_we + attribute \src "ls180.v:753.5-753.38" + wire \main_sdram_bankmachine3_cmd_ready + attribute \src "ls180.v:752.5-752.38" + wire \main_sdram_bankmachine3_cmd_valid + attribute \src "ls180.v:751.5-751.40" + wire \main_sdram_bankmachine3_refresh_gnt + attribute \src "ls180.v:750.6-750.41" + wire \main_sdram_bankmachine3_refresh_req + attribute \src "ls180.v:746.13-746.45" + wire width 22 \main_sdram_bankmachine3_req_addr + attribute \src "ls180.v:747.6-747.38" + wire \main_sdram_bankmachine3_req_lock + attribute \src "ls180.v:749.5-749.44" + wire \main_sdram_bankmachine3_req_rdata_valid + attribute \src "ls180.v:744.6-744.39" + wire \main_sdram_bankmachine3_req_ready + attribute \src "ls180.v:743.6-743.39" + wire \main_sdram_bankmachine3_req_valid + attribute \src "ls180.v:748.5-748.44" + wire \main_sdram_bankmachine3_req_wdata_ready + attribute \src "ls180.v:745.6-745.36" + wire \main_sdram_bankmachine3_req_we + attribute \src "ls180.v:812.12-812.39" + wire width 13 \main_sdram_bankmachine3_row + attribute \src "ls180.v:816.5-816.38" + wire \main_sdram_bankmachine3_row_close + attribute \src "ls180.v:817.5-817.47" + wire \main_sdram_bankmachine3_row_col_n_addr_sel + attribute \src "ls180.v:814.6-814.37" + wire \main_sdram_bankmachine3_row_hit + attribute \src "ls180.v:815.5-815.37" + wire \main_sdram_bankmachine3_row_open + attribute \src "ls180.v:813.5-813.39" + wire \main_sdram_bankmachine3_row_opened + attribute \no_retiming "true" + attribute \src "ls180.v:824.32-824.69" + wire \main_sdram_bankmachine3_trascon_ready + attribute \src "ls180.v:823.6-823.43" + wire \main_sdram_bankmachine3_trascon_valid + attribute \no_retiming "true" + attribute \src "ls180.v:822.32-822.68" + wire \main_sdram_bankmachine3_trccon_ready + attribute \src "ls180.v:821.6-821.42" + wire \main_sdram_bankmachine3_trccon_valid + attribute \src "ls180.v:820.11-820.48" + wire width 3 \main_sdram_bankmachine3_twtpcon_count + attribute \no_retiming "true" + attribute \src "ls180.v:819.32-819.69" + wire \main_sdram_bankmachine3_twtpcon_ready + attribute \src "ls180.v:818.6-818.43" + wire \main_sdram_bankmachine3_twtpcon_valid + attribute \src "ls180.v:826.6-826.28" + wire \main_sdram_cas_allowed + attribute \src "ls180.v:844.6-844.30" + wire \main_sdram_choose_cmd_ce + attribute \src "ls180.v:833.13-833.48" + wire width 13 \main_sdram_choose_cmd_cmd_payload_a + attribute \src "ls180.v:834.12-834.48" + wire width 2 \main_sdram_choose_cmd_cmd_payload_ba + attribute \src "ls180.v:835.5-835.42" + wire \main_sdram_choose_cmd_cmd_payload_cas + attribute \src "ls180.v:838.6-838.46" + wire \main_sdram_choose_cmd_cmd_payload_is_cmd + attribute \src "ls180.v:839.6-839.47" + wire \main_sdram_choose_cmd_cmd_payload_is_read + attribute \src "ls180.v:840.6-840.48" + wire \main_sdram_choose_cmd_cmd_payload_is_write + attribute \src "ls180.v:836.5-836.42" + wire \main_sdram_choose_cmd_cmd_payload_ras + attribute \src "ls180.v:837.5-837.41" + wire \main_sdram_choose_cmd_cmd_payload_we + attribute \src "ls180.v:832.5-832.36" + wire \main_sdram_choose_cmd_cmd_ready + attribute \src "ls180.v:831.6-831.37" + wire \main_sdram_choose_cmd_cmd_valid + attribute \src "ls180.v:843.11-843.38" + wire width 2 \main_sdram_choose_cmd_grant + attribute \src "ls180.v:842.12-842.41" + wire width 4 \main_sdram_choose_cmd_request + attribute \src "ls180.v:841.11-841.39" + wire width 4 \main_sdram_choose_cmd_valids + attribute \src "ls180.v:830.5-830.41" + wire \main_sdram_choose_cmd_want_activates + attribute \src "ls180.v:829.5-829.36" + wire \main_sdram_choose_cmd_want_cmds + attribute \src "ls180.v:827.5-827.37" + wire \main_sdram_choose_cmd_want_reads + attribute \src "ls180.v:828.5-828.38" + wire \main_sdram_choose_cmd_want_writes + attribute \src "ls180.v:862.6-862.30" + wire \main_sdram_choose_req_ce + attribute \src "ls180.v:851.13-851.48" + wire width 13 \main_sdram_choose_req_cmd_payload_a + attribute \src "ls180.v:852.12-852.48" + wire width 2 \main_sdram_choose_req_cmd_payload_ba + attribute \src "ls180.v:853.5-853.42" + wire \main_sdram_choose_req_cmd_payload_cas + attribute \src "ls180.v:856.6-856.46" + wire \main_sdram_choose_req_cmd_payload_is_cmd + attribute \src "ls180.v:857.6-857.47" + wire \main_sdram_choose_req_cmd_payload_is_read + attribute \src "ls180.v:858.6-858.48" + wire \main_sdram_choose_req_cmd_payload_is_write + attribute \src "ls180.v:854.5-854.42" + wire \main_sdram_choose_req_cmd_payload_ras + attribute \src "ls180.v:855.5-855.41" + wire \main_sdram_choose_req_cmd_payload_we + attribute \src "ls180.v:850.5-850.36" + wire \main_sdram_choose_req_cmd_ready + attribute \src "ls180.v:849.6-849.37" + wire \main_sdram_choose_req_cmd_valid + attribute \src "ls180.v:861.11-861.38" + wire width 2 \main_sdram_choose_req_grant + attribute \src "ls180.v:860.12-860.41" + wire width 4 \main_sdram_choose_req_request + attribute \src "ls180.v:859.11-859.39" + wire width 4 \main_sdram_choose_req_valids + attribute \src "ls180.v:848.5-848.41" + wire \main_sdram_choose_req_want_activates + attribute \src "ls180.v:847.6-847.37" + wire \main_sdram_choose_req_want_cmds + attribute \src "ls180.v:845.5-845.37" + wire \main_sdram_choose_req_want_reads + attribute \src "ls180.v:846.5-846.38" + wire \main_sdram_choose_req_want_writes + attribute \src "ls180.v:406.6-406.20" + wire \main_sdram_cke + attribute \src "ls180.v:474.5-474.24" + wire \main_sdram_cmd_last + attribute \src "ls180.v:475.12-475.36" + wire width 13 \main_sdram_cmd_payload_a + attribute \src "ls180.v:476.11-476.36" + wire width 2 \main_sdram_cmd_payload_ba + attribute \src "ls180.v:477.5-477.31" + wire \main_sdram_cmd_payload_cas + attribute \src "ls180.v:480.5-480.35" + wire \main_sdram_cmd_payload_is_read + attribute \src "ls180.v:481.5-481.36" + wire \main_sdram_cmd_payload_is_write + attribute \src "ls180.v:478.5-478.31" + wire \main_sdram_cmd_payload_ras + attribute \src "ls180.v:479.5-479.30" + wire \main_sdram_cmd_payload_we + attribute \src "ls180.v:473.5-473.25" + wire \main_sdram_cmd_ready + attribute \src "ls180.v:472.5-472.25" + wire \main_sdram_cmd_valid + attribute \src "ls180.v:414.6-414.32" + wire \main_sdram_command_issue_r + attribute \src "ls180.v:413.6-413.33" + wire \main_sdram_command_issue_re + attribute \src "ls180.v:416.5-416.31" + wire \main_sdram_command_issue_w + attribute \src "ls180.v:415.6-415.33" + wire \main_sdram_command_issue_we + attribute \src "ls180.v:412.5-412.26" + wire \main_sdram_command_re + attribute \src "ls180.v:411.11-411.37" + wire width 6 \main_sdram_command_storage + attribute \src "ls180.v:465.5-465.28" + wire \main_sdram_dfi_p0_act_n + attribute \src "ls180.v:456.12-456.37" + wire width 13 \main_sdram_dfi_p0_address + attribute \src "ls180.v:457.11-457.33" + wire width 2 \main_sdram_dfi_p0_bank + attribute \src "ls180.v:458.5-458.28" + wire \main_sdram_dfi_p0_cas_n + attribute \src "ls180.v:462.6-462.27" + wire \main_sdram_dfi_p0_cke + attribute \src "ls180.v:459.5-459.27" + wire \main_sdram_dfi_p0_cs_n + attribute \src "ls180.v:463.6-463.27" + wire \main_sdram_dfi_p0_odt + attribute \src "ls180.v:460.5-460.28" + wire \main_sdram_dfi_p0_ras_n + attribute \src "ls180.v:470.13-470.37" + wire width 16 \main_sdram_dfi_p0_rddata + attribute \src "ls180.v:469.5-469.32" + wire \main_sdram_dfi_p0_rddata_en + attribute \src "ls180.v:471.6-471.36" + wire \main_sdram_dfi_p0_rddata_valid + attribute \src "ls180.v:464.6-464.31" + wire \main_sdram_dfi_p0_reset_n + attribute \src "ls180.v:461.5-461.27" + wire \main_sdram_dfi_p0_we_n + attribute \src "ls180.v:466.13-466.37" + wire width 16 \main_sdram_dfi_p0_wrdata + attribute \src "ls180.v:467.5-467.32" + wire \main_sdram_dfi_p0_wrdata_en + attribute \src "ls180.v:468.12-468.41" + wire width 2 \main_sdram_dfi_p0_wrdata_mask + attribute \src "ls180.v:880.5-880.19" + wire \main_sdram_en0 + attribute \src "ls180.v:883.5-883.19" + wire \main_sdram_en1 + attribute \src "ls180.v:886.6-886.30" + wire \main_sdram_go_to_refresh + attribute \src "ls180.v:428.13-428.44" + wire width 22 \main_sdram_interface_bank0_addr + attribute \src "ls180.v:429.6-429.37" + wire \main_sdram_interface_bank0_lock + attribute \src "ls180.v:431.6-431.44" + wire \main_sdram_interface_bank0_rdata_valid + attribute \src "ls180.v:426.6-426.38" + wire \main_sdram_interface_bank0_ready + attribute \src "ls180.v:425.6-425.38" + wire \main_sdram_interface_bank0_valid + attribute \src "ls180.v:430.6-430.44" + wire \main_sdram_interface_bank0_wdata_ready + attribute \src "ls180.v:427.6-427.35" + wire \main_sdram_interface_bank0_we + attribute \src "ls180.v:435.13-435.44" + wire width 22 \main_sdram_interface_bank1_addr + attribute \src "ls180.v:436.6-436.37" + wire \main_sdram_interface_bank1_lock + attribute \src "ls180.v:438.6-438.44" + wire \main_sdram_interface_bank1_rdata_valid + attribute \src "ls180.v:433.6-433.38" + wire \main_sdram_interface_bank1_ready + attribute \src "ls180.v:432.6-432.38" + wire \main_sdram_interface_bank1_valid + attribute \src "ls180.v:437.6-437.44" + wire \main_sdram_interface_bank1_wdata_ready + attribute \src "ls180.v:434.6-434.35" + wire \main_sdram_interface_bank1_we + attribute \src "ls180.v:442.13-442.44" + wire width 22 \main_sdram_interface_bank2_addr + attribute \src "ls180.v:443.6-443.37" + wire \main_sdram_interface_bank2_lock + attribute \src "ls180.v:445.6-445.44" + wire \main_sdram_interface_bank2_rdata_valid + attribute \src "ls180.v:440.6-440.38" + wire \main_sdram_interface_bank2_ready + attribute \src "ls180.v:439.6-439.38" + wire \main_sdram_interface_bank2_valid + attribute \src "ls180.v:444.6-444.44" + wire \main_sdram_interface_bank2_wdata_ready + attribute \src "ls180.v:441.6-441.35" + wire \main_sdram_interface_bank2_we + attribute \src "ls180.v:449.13-449.44" + wire width 22 \main_sdram_interface_bank3_addr + attribute \src "ls180.v:450.6-450.37" + wire \main_sdram_interface_bank3_lock + attribute \src "ls180.v:452.6-452.44" + wire \main_sdram_interface_bank3_rdata_valid + attribute \src "ls180.v:447.6-447.38" + wire \main_sdram_interface_bank3_ready + attribute \src "ls180.v:446.6-446.38" + wire \main_sdram_interface_bank3_valid + attribute \src "ls180.v:451.6-451.44" + wire \main_sdram_interface_bank3_wdata_ready + attribute \src "ls180.v:448.6-448.35" + wire \main_sdram_interface_bank3_we + attribute \src "ls180.v:455.13-455.39" + wire width 16 \main_sdram_interface_rdata + attribute \src "ls180.v:453.12-453.38" + wire width 16 \main_sdram_interface_wdata + attribute \src "ls180.v:454.11-454.40" + wire width 2 \main_sdram_interface_wdata_we + attribute \src "ls180.v:366.5-366.29" + wire \main_sdram_inti_p0_act_n + attribute \src "ls180.v:357.13-357.39" + wire width 13 \main_sdram_inti_p0_address + attribute \src "ls180.v:358.12-358.35" + wire width 2 \main_sdram_inti_p0_bank + attribute \src "ls180.v:359.5-359.29" + wire \main_sdram_inti_p0_cas_n + attribute \src "ls180.v:363.6-363.28" + wire \main_sdram_inti_p0_cke + attribute \src "ls180.v:360.5-360.28" + wire \main_sdram_inti_p0_cs_n + attribute \src "ls180.v:364.6-364.28" + wire \main_sdram_inti_p0_odt + attribute \src "ls180.v:361.5-361.29" + wire \main_sdram_inti_p0_ras_n + attribute \src "ls180.v:371.12-371.37" + wire width 16 \main_sdram_inti_p0_rddata + attribute \src "ls180.v:370.6-370.34" + wire \main_sdram_inti_p0_rddata_en + attribute \src "ls180.v:372.5-372.36" + wire \main_sdram_inti_p0_rddata_valid + attribute \src "ls180.v:365.6-365.32" + wire \main_sdram_inti_p0_reset_n + attribute \src "ls180.v:362.5-362.28" + wire \main_sdram_inti_p0_we_n + attribute \src "ls180.v:367.13-367.38" + wire width 16 \main_sdram_inti_p0_wrdata + attribute \src "ls180.v:368.6-368.34" + wire \main_sdram_inti_p0_wrdata_en + attribute \src "ls180.v:369.12-369.42" + wire width 2 \main_sdram_inti_p0_wrdata_mask + attribute \src "ls180.v:398.5-398.31" + wire \main_sdram_master_p0_act_n + attribute \src "ls180.v:389.12-389.40" + wire width 13 \main_sdram_master_p0_address + attribute \src "ls180.v:390.11-390.36" + wire width 2 \main_sdram_master_p0_bank + attribute \src "ls180.v:391.5-391.31" + wire \main_sdram_master_p0_cas_n + attribute \src "ls180.v:395.5-395.29" + wire \main_sdram_master_p0_cke + attribute \src "ls180.v:392.5-392.30" + wire \main_sdram_master_p0_cs_n + attribute \src "ls180.v:396.5-396.29" + wire \main_sdram_master_p0_odt + attribute \src "ls180.v:393.5-393.31" + wire \main_sdram_master_p0_ras_n + attribute \src "ls180.v:403.13-403.40" + wire width 16 \main_sdram_master_p0_rddata + attribute \src "ls180.v:402.5-402.35" + wire \main_sdram_master_p0_rddata_en + attribute \src "ls180.v:404.6-404.39" + wire \main_sdram_master_p0_rddata_valid + attribute \src "ls180.v:397.5-397.33" + wire \main_sdram_master_p0_reset_n + attribute \src "ls180.v:394.5-394.30" + wire \main_sdram_master_p0_we_n + attribute \src "ls180.v:399.12-399.39" + wire width 16 \main_sdram_master_p0_wrdata + attribute \src "ls180.v:400.5-400.35" + wire \main_sdram_master_p0_wrdata_en + attribute \src "ls180.v:401.11-401.43" + wire width 2 \main_sdram_master_p0_wrdata_mask + attribute \src "ls180.v:881.6-881.26" + wire \main_sdram_max_time0 + attribute \src "ls180.v:884.6-884.26" + wire \main_sdram_max_time1 + attribute \src "ls180.v:863.12-863.28" + wire width 13 \main_sdram_nop_a + attribute \src "ls180.v:864.11-864.28" + wire width 2 \main_sdram_nop_ba + attribute \src "ls180.v:407.6-407.20" + wire \main_sdram_odt + attribute \src "ls180.v:490.5-490.31" + wire \main_sdram_postponer_count + attribute \src "ls180.v:488.6-488.32" + wire \main_sdram_postponer_req_i + attribute \src "ls180.v:489.5-489.31" + wire \main_sdram_postponer_req_o + attribute \src "ls180.v:825.6-825.28" + wire \main_sdram_ras_allowed + attribute \src "ls180.v:410.5-410.18" + wire \main_sdram_re + attribute \src "ls180.v:878.6-878.31" + wire \main_sdram_read_available + attribute \src "ls180.v:408.6-408.24" + wire \main_sdram_reset_n + attribute \src "ls180.v:405.6-405.20" + wire \main_sdram_sel + attribute \src "ls180.v:496.5-496.31" + wire \main_sdram_sequencer_count + attribute \src "ls180.v:495.11-495.39" + wire width 4 \main_sdram_sequencer_counter + attribute \src "ls180.v:492.6-492.32" + wire \main_sdram_sequencer_done0 + attribute \src "ls180.v:494.5-494.31" + wire \main_sdram_sequencer_done1 + attribute \src "ls180.v:491.5-491.32" + wire \main_sdram_sequencer_start0 + attribute \src "ls180.v:493.6-493.33" + wire \main_sdram_sequencer_start1 + attribute \src "ls180.v:382.6-382.31" + wire \main_sdram_slave_p0_act_n + attribute \src "ls180.v:373.13-373.40" + wire width 13 \main_sdram_slave_p0_address + attribute \src "ls180.v:374.12-374.36" + wire width 2 \main_sdram_slave_p0_bank + attribute \src "ls180.v:375.6-375.31" + wire \main_sdram_slave_p0_cas_n + attribute \src "ls180.v:379.6-379.29" + wire \main_sdram_slave_p0_cke + attribute \src "ls180.v:376.6-376.30" + wire \main_sdram_slave_p0_cs_n + attribute \src "ls180.v:380.6-380.29" + wire \main_sdram_slave_p0_odt + attribute \src "ls180.v:377.6-377.31" + wire \main_sdram_slave_p0_ras_n + attribute \src "ls180.v:387.12-387.38" + wire width 16 \main_sdram_slave_p0_rddata + attribute \src "ls180.v:386.6-386.35" + wire \main_sdram_slave_p0_rddata_en + attribute \src "ls180.v:388.5-388.37" + wire \main_sdram_slave_p0_rddata_valid + attribute \src "ls180.v:381.6-381.33" + wire \main_sdram_slave_p0_reset_n + attribute \src "ls180.v:378.6-378.30" + wire \main_sdram_slave_p0_we_n + attribute \src "ls180.v:383.13-383.39" + wire width 16 \main_sdram_slave_p0_wrdata + attribute \src "ls180.v:384.6-384.35" + wire \main_sdram_slave_p0_wrdata_en + attribute \src "ls180.v:385.12-385.43" + wire width 2 \main_sdram_slave_p0_wrdata_mask + attribute \src "ls180.v:423.12-423.29" + wire width 16 \main_sdram_status + attribute \src "ls180.v:866.5-866.24" + wire \main_sdram_steerer0 + attribute \src "ls180.v:867.5-867.24" + wire \main_sdram_steerer1 + attribute \src "ls180.v:865.11-865.33" + wire width 2 \main_sdram_steerer_sel + attribute \src "ls180.v:409.11-409.29" + wire width 4 \main_sdram_storage + attribute \src "ls180.v:874.5-874.29" + wire \main_sdram_tccdcon_count + attribute \no_retiming "true" + attribute \src "ls180.v:873.32-873.56" + wire \main_sdram_tccdcon_ready + attribute \src "ls180.v:872.6-872.30" + wire \main_sdram_tccdcon_valid + attribute \no_retiming "true" + attribute \src "ls180.v:871.32-871.56" + wire \main_sdram_tfawcon_ready + attribute \src "ls180.v:870.6-870.30" + wire \main_sdram_tfawcon_valid + attribute \src "ls180.v:882.11-882.27" + wire width 5 \main_sdram_time0 + attribute \src "ls180.v:885.11-885.27" + wire width 4 \main_sdram_time1 + attribute \src "ls180.v:485.12-485.35" + wire width 10 \main_sdram_timer_count0 + attribute \src "ls180.v:487.11-487.34" + wire width 10 \main_sdram_timer_count1 + attribute \src "ls180.v:484.6-484.28" + wire \main_sdram_timer_done0 + attribute \src "ls180.v:486.6-486.28" + wire \main_sdram_timer_done1 + attribute \src "ls180.v:483.6-483.27" + wire \main_sdram_timer_wait + attribute \no_retiming "true" + attribute \src "ls180.v:869.32-869.56" + wire \main_sdram_trrdcon_ready + attribute \src "ls180.v:868.6-868.30" + wire \main_sdram_trrdcon_valid + attribute \src "ls180.v:877.11-877.35" + wire width 3 \main_sdram_twtrcon_count + attribute \no_retiming "true" + attribute \src "ls180.v:876.32-876.56" + wire \main_sdram_twtrcon_ready + attribute \src "ls180.v:875.6-875.30" + wire \main_sdram_twtrcon_valid + attribute \src "ls180.v:482.6-482.30" + wire \main_sdram_wants_refresh + attribute \src "ls180.v:424.6-424.19" + wire \main_sdram_we + attribute \src "ls180.v:422.5-422.25" + wire \main_sdram_wrdata_re + attribute \src "ls180.v:421.12-421.37" + wire width 16 \main_sdram_wrdata_storage + attribute \src "ls180.v:879.6-879.32" + wire \main_sdram_write_available + attribute \src "ls180.v:914.5-914.47" + wire \main_socbushandler_converted_interface_ack + attribute \src "ls180.v:908.13-908.55" + wire width 30 \main_socbushandler_converted_interface_adr + attribute \src "ls180.v:917.12-917.54" + wire width 2 \main_socbushandler_converted_interface_bte + attribute \src "ls180.v:916.12-916.54" + wire width 3 \main_socbushandler_converted_interface_cti + attribute \src "ls180.v:912.6-912.48" + wire \main_socbushandler_converted_interface_cyc + attribute \src "ls180.v:910.13-910.57" + wire width 64 \main_socbushandler_converted_interface_dat_r + attribute \src "ls180.v:909.13-909.57" + wire width 64 \main_socbushandler_converted_interface_dat_w + attribute \src "ls180.v:918.5-918.47" + wire \main_socbushandler_converted_interface_err + attribute \src "ls180.v:911.12-911.54" + wire width 8 \main_socbushandler_converted_interface_sel + attribute \src "ls180.v:913.6-913.48" + wire \main_socbushandler_converted_interface_stb + attribute \src "ls180.v:915.6-915.47" + wire \main_socbushandler_converted_interface_we + attribute \src "ls180.v:920.5-920.31" + wire \main_socbushandler_counter + attribute \src "ls180.v:1849.5-1849.53" + wire \main_socbushandler_counter_converter2_next_value + attribute \src "ls180.v:1850.5-1850.56" + wire \main_socbushandler_counter_converter2_next_value_ce + attribute \src "ls180.v:922.12-922.36" + wire width 64 \main_socbushandler_dat_r + attribute \src "ls180.v:921.6-921.30" + wire \main_socbushandler_reset + attribute \src "ls180.v:919.5-919.28" + wire \main_socbushandler_skip + attribute \src "ls180.v:1097.6-1097.27" + wire \main_spimaster0_start + attribute \src "ls180.v:1107.12-1107.35" + wire width 8 \main_spimaster10_length + attribute \src "ls180.v:1108.12-1108.36" + wire width 16 \main_spimaster11_storage + attribute \src "ls180.v:1109.5-1109.24" + wire \main_spimaster12_re + attribute \src "ls180.v:1110.6-1110.27" + wire \main_spimaster13_done + attribute \src "ls180.v:1111.6-1111.29" + wire \main_spimaster14_status + attribute \src "ls180.v:1112.6-1112.25" + wire \main_spimaster15_we + attribute \src "ls180.v:1113.11-1113.35" + wire width 8 \main_spimaster16_storage + attribute \src "ls180.v:1114.5-1114.24" + wire \main_spimaster17_re + attribute \src "ls180.v:1115.12-1115.35" + wire width 8 \main_spimaster18_status + attribute \src "ls180.v:1116.6-1116.25" + wire \main_spimaster19_we + attribute \src "ls180.v:1098.12-1098.34" + wire width 8 \main_spimaster1_length + attribute \src "ls180.v:1170.5-1170.23" + wire \main_spimaster1_re + attribute \src "ls180.v:1169.12-1169.35" + wire width 16 \main_spimaster1_storage + attribute \src "ls180.v:1117.6-1117.26" + wire \main_spimaster20_sel + attribute \src "ls180.v:1118.5-1118.29" + wire \main_spimaster21_storage + attribute \src "ls180.v:1119.5-1119.24" + wire \main_spimaster22_re + attribute \src "ls180.v:1120.5-1120.29" + wire \main_spimaster23_storage + attribute \src "ls180.v:1121.5-1121.24" + wire \main_spimaster24_re + attribute \src "ls180.v:1122.5-1122.32" + wire \main_spimaster25_clk_enable + attribute \src "ls180.v:1123.5-1123.31" + wire \main_spimaster26_cs_enable + attribute \src "ls180.v:1124.11-1124.33" + wire width 3 \main_spimaster27_count + attribute \src "ls180.v:1890.11-1890.55" + wire width 3 \main_spimaster27_count_spimaster0_next_value + attribute \src "ls180.v:1891.5-1891.52" + wire \main_spimaster27_count_spimaster0_next_value_ce + attribute \src "ls180.v:1125.5-1125.32" + wire \main_spimaster28_mosi_latch + attribute \src "ls180.v:1126.5-1126.32" + wire \main_spimaster29_miso_latch + attribute \src "ls180.v:1099.5-1099.25" + wire \main_spimaster2_done + attribute \src "ls180.v:1127.12-1127.40" + wire width 16 \main_spimaster30_clk_divider + attribute \src "ls180.v:1128.6-1128.31" + wire \main_spimaster31_clk_rise + attribute \src "ls180.v:1129.6-1129.31" + wire \main_spimaster32_clk_fall + attribute \src "ls180.v:1130.11-1130.37" + wire width 8 \main_spimaster33_mosi_data + attribute \src "ls180.v:1131.11-1131.36" + wire width 3 \main_spimaster34_mosi_sel + attribute \src "ls180.v:1132.11-1132.37" + wire width 8 \main_spimaster35_miso_data + attribute \src "ls180.v:1100.5-1100.24" + wire \main_spimaster3_irq + attribute \src "ls180.v:1101.12-1101.32" + wire width 8 \main_spimaster4_mosi + attribute \src "ls180.v:1102.11-1102.31" + wire width 8 \main_spimaster5_miso + attribute \src "ls180.v:1103.6-1103.24" + wire \main_spimaster6_cs + attribute \src "ls180.v:1104.6-1104.30" + wire \main_spimaster7_loopback + attribute \src "ls180.v:1105.12-1105.39" + wire width 16 \main_spimaster8_clk_divider + attribute \src "ls180.v:1106.5-1106.26" + wire \main_spimaster9_start + attribute \src "ls180.v:1141.13-1141.40" + wire width 16 \main_spisdcard_clk_divider0 + attribute \src "ls180.v:1163.12-1163.39" + wire width 16 \main_spisdcard_clk_divider1 + attribute \src "ls180.v:1158.5-1158.30" + wire \main_spisdcard_clk_enable + attribute \src "ls180.v:1165.6-1165.29" + wire \main_spisdcard_clk_fall + attribute \src "ls180.v:1164.6-1164.29" + wire \main_spisdcard_clk_rise + attribute \src "ls180.v:1145.5-1145.30" + wire \main_spisdcard_control_re + attribute \src "ls180.v:1144.12-1144.42" + wire width 16 \main_spisdcard_control_storage + attribute \src "ls180.v:1160.11-1160.31" + wire width 3 \main_spisdcard_count + attribute \src "ls180.v:1894.11-1894.53" + wire width 3 \main_spisdcard_count_spimaster1_next_value + attribute \src "ls180.v:1895.5-1895.50" + wire \main_spisdcard_count_spimaster1_next_value_ce + attribute \src "ls180.v:1139.6-1139.23" + wire \main_spisdcard_cs + attribute \src "ls180.v:1159.5-1159.29" + wire \main_spisdcard_cs_enable + attribute \src "ls180.v:1155.5-1155.25" + wire \main_spisdcard_cs_re + attribute \src "ls180.v:1154.5-1154.30" + wire \main_spisdcard_cs_storage + attribute \src "ls180.v:1135.5-1135.25" + wire \main_spisdcard_done0 + attribute \src "ls180.v:1146.6-1146.26" + wire \main_spisdcard_done1 + attribute \src "ls180.v:1136.5-1136.23" + wire \main_spisdcard_irq + attribute \src "ls180.v:1134.12-1134.34" + wire width 8 \main_spisdcard_length0 + attribute \src "ls180.v:1143.12-1143.34" + wire width 8 \main_spisdcard_length1 + attribute \src "ls180.v:1140.6-1140.29" + wire \main_spisdcard_loopback + attribute \src "ls180.v:1157.5-1157.31" + wire \main_spisdcard_loopback_re + attribute \src "ls180.v:1156.5-1156.36" + wire \main_spisdcard_loopback_storage + attribute \src "ls180.v:1138.11-1138.30" + wire width 8 \main_spisdcard_miso + attribute \src "ls180.v:1168.11-1168.35" + wire width 8 \main_spisdcard_miso_data + attribute \src "ls180.v:1162.5-1162.30" + wire \main_spisdcard_miso_latch + attribute \src "ls180.v:1151.12-1151.38" + wire width 8 \main_spisdcard_miso_status + attribute \src "ls180.v:1152.6-1152.28" + wire \main_spisdcard_miso_we + attribute \src "ls180.v:1137.12-1137.31" + wire width 8 \main_spisdcard_mosi + attribute \src "ls180.v:1166.11-1166.35" + wire width 8 \main_spisdcard_mosi_data + attribute \src "ls180.v:1161.5-1161.30" + wire \main_spisdcard_mosi_latch + attribute \src "ls180.v:1150.5-1150.27" + wire \main_spisdcard_mosi_re + attribute \src "ls180.v:1167.11-1167.34" + wire width 3 \main_spisdcard_mosi_sel + attribute \src "ls180.v:1149.11-1149.38" + wire width 8 \main_spisdcard_mosi_storage + attribute \src "ls180.v:1153.6-1153.24" + wire \main_spisdcard_sel + attribute \src "ls180.v:1133.6-1133.27" + wire \main_spisdcard_start0 + attribute \src "ls180.v:1142.5-1142.26" + wire \main_spisdcard_start1 + attribute \src "ls180.v:1147.6-1147.34" + wire \main_spisdcard_status_status + attribute \src "ls180.v:1148.6-1148.30" + wire \main_spisdcard_status_we + attribute \src "ls180.v:257.12-257.26" + wire width 6 \main_sram0_adr + attribute \src "ls180.v:258.13-258.29" + wire width 64 \main_sram0_dat_r + attribute \src "ls180.v:260.13-260.29" + wire width 64 \main_sram0_dat_w + attribute \src "ls180.v:259.11-259.24" + wire width 8 \main_sram0_we + attribute \src "ls180.v:272.12-272.26" + wire width 6 \main_sram1_adr + attribute \src "ls180.v:273.13-273.29" + wire width 64 \main_sram1_dat_r + attribute \src "ls180.v:275.13-275.29" + wire width 64 \main_sram1_dat_w + attribute \src "ls180.v:274.11-274.24" + wire width 8 \main_sram1_we + attribute \src "ls180.v:287.12-287.26" + wire width 6 \main_sram2_adr + attribute \src "ls180.v:288.13-288.29" + wire width 64 \main_sram2_dat_r + attribute \src "ls180.v:290.13-290.29" + wire width 64 \main_sram2_dat_w + attribute \src "ls180.v:289.11-289.24" + wire width 8 \main_sram2_we + attribute \src "ls180.v:302.12-302.26" + wire width 6 \main_sram3_adr + attribute \src "ls180.v:303.13-303.29" + wire width 64 \main_sram3_dat_r + attribute \src "ls180.v:305.13-305.29" + wire width 64 \main_sram3_dat_w + attribute \src "ls180.v:304.11-304.24" + wire width 8 \main_sram3_we + attribute \src "ls180.v:988.12-988.44" + wire width 2 \main_uart_eventmanager_pending_r + attribute \src "ls180.v:987.6-987.39" + wire \main_uart_eventmanager_pending_re + attribute \src "ls180.v:990.11-990.43" + wire width 2 \main_uart_eventmanager_pending_w + attribute \src "ls180.v:989.6-989.39" + wire \main_uart_eventmanager_pending_we + attribute \src "ls180.v:992.5-992.30" + wire \main_uart_eventmanager_re + attribute \src "ls180.v:984.12-984.43" + wire width 2 \main_uart_eventmanager_status_r + attribute \src "ls180.v:983.6-983.38" + wire \main_uart_eventmanager_status_re + attribute \src "ls180.v:986.11-986.42" + wire width 2 \main_uart_eventmanager_status_w + attribute \src "ls180.v:985.6-985.38" + wire \main_uart_eventmanager_status_we + attribute \src "ls180.v:991.11-991.41" + wire width 2 \main_uart_eventmanager_storage + attribute \src "ls180.v:972.6-972.19" + wire \main_uart_irq + attribute \src "ls180.v:958.12-958.46" + wire width 32 \main_uart_phy_phase_accumulator_rx + attribute \src "ls180.v:948.12-948.46" + wire width 32 \main_uart_phy_phase_accumulator_tx + attribute \src "ls180.v:941.5-941.21" + wire \main_uart_phy_re + attribute \src "ls180.v:959.6-959.22" + wire \main_uart_phy_rx + attribute \src "ls180.v:962.11-962.36" + wire width 4 \main_uart_phy_rx_bitcount + attribute \src "ls180.v:963.5-963.26" + wire \main_uart_phy_rx_busy + attribute \src "ls180.v:960.5-960.23" + wire \main_uart_phy_rx_r + attribute \src "ls180.v:961.11-961.31" + wire width 8 \main_uart_phy_rx_reg + attribute \src "ls180.v:944.6-944.30" + wire \main_uart_phy_sink_first + attribute \src "ls180.v:945.6-945.29" + wire \main_uart_phy_sink_last + attribute \src "ls180.v:946.12-946.43" + wire width 8 \main_uart_phy_sink_payload_data + attribute \src "ls180.v:943.5-943.29" + wire \main_uart_phy_sink_ready + attribute \src "ls180.v:942.6-942.30" + wire \main_uart_phy_sink_valid + attribute \src "ls180.v:954.5-954.31" + wire \main_uart_phy_source_first + attribute \src "ls180.v:955.5-955.30" + wire \main_uart_phy_source_last + attribute \src "ls180.v:956.11-956.44" + wire width 8 \main_uart_phy_source_payload_data + attribute \src "ls180.v:953.6-953.32" + wire \main_uart_phy_source_ready + attribute \src "ls180.v:952.5-952.31" + wire \main_uart_phy_source_valid + attribute \src "ls180.v:940.12-940.33" + wire width 32 \main_uart_phy_storage + attribute \src "ls180.v:950.11-950.36" + wire width 4 \main_uart_phy_tx_bitcount + attribute \src "ls180.v:951.5-951.26" + wire \main_uart_phy_tx_busy + attribute \src "ls180.v:949.11-949.31" + wire width 8 \main_uart_phy_tx_reg + attribute \src "ls180.v:957.5-957.32" + wire \main_uart_phy_uart_clk_rxen + attribute \src "ls180.v:947.5-947.32" + wire \main_uart_phy_uart_clk_txen + attribute \src "ls180.v:1081.5-1081.20" + wire \main_uart_reset + attribute \src "ls180.v:981.5-981.23" + wire \main_uart_rx_clear + attribute \src "ls180.v:1065.11-1065.36" + wire width 4 \main_uart_rx_fifo_consume + attribute \src "ls180.v:1070.6-1070.31" + wire \main_uart_rx_fifo_do_read + attribute \src "ls180.v:1076.6-1076.37" + wire \main_uart_rx_fifo_fifo_in_first + attribute \src "ls180.v:1077.6-1077.36" + wire \main_uart_rx_fifo_fifo_in_last + attribute \src "ls180.v:1075.12-1075.50" + wire width 8 \main_uart_rx_fifo_fifo_in_payload_data + attribute \src "ls180.v:1079.6-1079.38" + wire \main_uart_rx_fifo_fifo_out_first + attribute \src "ls180.v:1080.6-1080.37" + wire \main_uart_rx_fifo_fifo_out_last + attribute \src "ls180.v:1078.12-1078.51" + wire width 8 \main_uart_rx_fifo_fifo_out_payload_data + attribute \src "ls180.v:1062.11-1062.35" + wire width 5 \main_uart_rx_fifo_level0 + attribute \src "ls180.v:1074.12-1074.36" + wire width 5 \main_uart_rx_fifo_level1 + attribute \src "ls180.v:1064.11-1064.36" + wire width 4 \main_uart_rx_fifo_produce + attribute \src "ls180.v:1071.12-1071.40" + wire width 4 \main_uart_rx_fifo_rdport_adr + attribute \src "ls180.v:1072.12-1072.42" + wire width 10 \main_uart_rx_fifo_rdport_dat_r + attribute \src "ls180.v:1073.6-1073.33" + wire \main_uart_rx_fifo_rdport_re + attribute \src "ls180.v:1054.6-1054.26" + wire \main_uart_rx_fifo_re + attribute \src "ls180.v:1055.5-1055.31" + wire \main_uart_rx_fifo_readable + attribute \src "ls180.v:1063.5-1063.30" + wire \main_uart_rx_fifo_replace + attribute \src "ls180.v:1046.6-1046.34" + wire \main_uart_rx_fifo_sink_first + attribute \src "ls180.v:1047.6-1047.33" + wire \main_uart_rx_fifo_sink_last + attribute \src "ls180.v:1048.12-1048.47" + wire width 8 \main_uart_rx_fifo_sink_payload_data + attribute \src "ls180.v:1045.6-1045.34" + wire \main_uart_rx_fifo_sink_ready + attribute \src "ls180.v:1044.6-1044.34" + wire \main_uart_rx_fifo_sink_valid + attribute \src "ls180.v:1051.6-1051.36" + wire \main_uart_rx_fifo_source_first + attribute \src "ls180.v:1052.6-1052.35" + wire \main_uart_rx_fifo_source_last + attribute \src "ls180.v:1053.12-1053.49" + wire width 8 \main_uart_rx_fifo_source_payload_data + attribute \src "ls180.v:1050.6-1050.36" + wire \main_uart_rx_fifo_source_ready + attribute \src "ls180.v:1049.6-1049.36" + wire \main_uart_rx_fifo_source_valid + attribute \src "ls180.v:1060.12-1060.42" + wire width 10 \main_uart_rx_fifo_syncfifo_din + attribute \src "ls180.v:1061.12-1061.43" + wire width 10 \main_uart_rx_fifo_syncfifo_dout + attribute \src "ls180.v:1058.6-1058.35" + wire \main_uart_rx_fifo_syncfifo_re + attribute \src "ls180.v:1059.6-1059.41" + wire \main_uart_rx_fifo_syncfifo_readable + attribute \src "ls180.v:1056.6-1056.35" + wire \main_uart_rx_fifo_syncfifo_we + attribute \src "ls180.v:1057.6-1057.41" + wire \main_uart_rx_fifo_syncfifo_writable + attribute \src "ls180.v:1066.11-1066.39" + wire width 4 \main_uart_rx_fifo_wrport_adr + attribute \src "ls180.v:1067.12-1067.42" + wire width 10 \main_uart_rx_fifo_wrport_dat_r + attribute \src "ls180.v:1069.12-1069.42" + wire width 10 \main_uart_rx_fifo_wrport_dat_w + attribute \src "ls180.v:1068.6-1068.33" + wire \main_uart_rx_fifo_wrport_we + attribute \src "ls180.v:982.5-982.29" + wire \main_uart_rx_old_trigger + attribute \src "ls180.v:979.5-979.25" + wire \main_uart_rx_pending + attribute \src "ls180.v:978.6-978.25" + wire \main_uart_rx_status + attribute \src "ls180.v:980.6-980.26" + wire \main_uart_rx_trigger + attribute \src "ls180.v:970.6-970.30" + wire \main_uart_rxempty_status + attribute \src "ls180.v:971.6-971.26" + wire \main_uart_rxempty_we + attribute \src "ls180.v:995.6-995.29" + wire \main_uart_rxfull_status + attribute \src "ls180.v:996.6-996.25" + wire \main_uart_rxfull_we + attribute \src "ls180.v:965.12-965.28" + wire width 8 \main_uart_rxtx_r + attribute \src "ls180.v:964.6-964.23" + wire \main_uart_rxtx_re + attribute \src "ls180.v:967.12-967.28" + wire width 8 \main_uart_rxtx_w + attribute \src "ls180.v:966.6-966.23" + wire \main_uart_rxtx_we + attribute \src "ls180.v:976.5-976.23" + wire \main_uart_tx_clear + attribute \src "ls180.v:1028.11-1028.36" + wire width 4 \main_uart_tx_fifo_consume + attribute \src "ls180.v:1033.6-1033.31" + wire \main_uart_tx_fifo_do_read + attribute \src "ls180.v:1039.6-1039.37" + wire \main_uart_tx_fifo_fifo_in_first + attribute \src "ls180.v:1040.6-1040.36" + wire \main_uart_tx_fifo_fifo_in_last + attribute \src "ls180.v:1038.12-1038.50" + wire width 8 \main_uart_tx_fifo_fifo_in_payload_data + attribute \src "ls180.v:1042.6-1042.38" + wire \main_uart_tx_fifo_fifo_out_first + attribute \src "ls180.v:1043.6-1043.37" + wire \main_uart_tx_fifo_fifo_out_last + attribute \src "ls180.v:1041.12-1041.51" + wire width 8 \main_uart_tx_fifo_fifo_out_payload_data + attribute \src "ls180.v:1025.11-1025.35" + wire width 5 \main_uart_tx_fifo_level0 + attribute \src "ls180.v:1037.12-1037.36" + wire width 5 \main_uart_tx_fifo_level1 + attribute \src "ls180.v:1027.11-1027.36" + wire width 4 \main_uart_tx_fifo_produce + attribute \src "ls180.v:1034.12-1034.40" + wire width 4 \main_uart_tx_fifo_rdport_adr + attribute \src "ls180.v:1035.12-1035.42" + wire width 10 \main_uart_tx_fifo_rdport_dat_r + attribute \src "ls180.v:1036.6-1036.33" + wire \main_uart_tx_fifo_rdport_re + attribute \src "ls180.v:1017.6-1017.26" + wire \main_uart_tx_fifo_re + attribute \src "ls180.v:1018.5-1018.31" + wire \main_uart_tx_fifo_readable + attribute \src "ls180.v:1026.5-1026.30" + wire \main_uart_tx_fifo_replace + attribute \src "ls180.v:1009.5-1009.33" + wire \main_uart_tx_fifo_sink_first + attribute \src "ls180.v:1010.5-1010.32" + wire \main_uart_tx_fifo_sink_last + attribute \src "ls180.v:1011.12-1011.47" + wire width 8 \main_uart_tx_fifo_sink_payload_data + attribute \src "ls180.v:1008.6-1008.34" + wire \main_uart_tx_fifo_sink_ready + attribute \src "ls180.v:1007.6-1007.34" + wire \main_uart_tx_fifo_sink_valid + attribute \src "ls180.v:1014.6-1014.36" + wire \main_uart_tx_fifo_source_first + attribute \src "ls180.v:1015.6-1015.35" + wire \main_uart_tx_fifo_source_last + attribute \src "ls180.v:1016.12-1016.49" + wire width 8 \main_uart_tx_fifo_source_payload_data + attribute \src "ls180.v:1013.6-1013.36" + wire \main_uart_tx_fifo_source_ready + attribute \src "ls180.v:1012.6-1012.36" + wire \main_uart_tx_fifo_source_valid + attribute \src "ls180.v:1023.12-1023.42" + wire width 10 \main_uart_tx_fifo_syncfifo_din + attribute \src "ls180.v:1024.12-1024.43" + wire width 10 \main_uart_tx_fifo_syncfifo_dout + attribute \src "ls180.v:1021.6-1021.35" + wire \main_uart_tx_fifo_syncfifo_re + attribute \src "ls180.v:1022.6-1022.41" + wire \main_uart_tx_fifo_syncfifo_readable + attribute \src "ls180.v:1019.6-1019.35" + wire \main_uart_tx_fifo_syncfifo_we + attribute \src "ls180.v:1020.6-1020.41" + wire \main_uart_tx_fifo_syncfifo_writable + attribute \src "ls180.v:1029.11-1029.39" + wire width 4 \main_uart_tx_fifo_wrport_adr + attribute \src "ls180.v:1030.12-1030.42" + wire width 10 \main_uart_tx_fifo_wrport_dat_r + attribute \src "ls180.v:1032.12-1032.42" + wire width 10 \main_uart_tx_fifo_wrport_dat_w + attribute \src "ls180.v:1031.6-1031.33" + wire \main_uart_tx_fifo_wrport_we + attribute \src "ls180.v:977.5-977.29" + wire \main_uart_tx_old_trigger + attribute \src "ls180.v:974.5-974.25" + wire \main_uart_tx_pending + attribute \src "ls180.v:973.6-973.25" + wire \main_uart_tx_status + attribute \src "ls180.v:975.6-975.26" + wire \main_uart_tx_trigger + attribute \src "ls180.v:993.6-993.30" + wire \main_uart_txempty_status + attribute \src "ls180.v:994.6-994.26" + wire \main_uart_txempty_we + attribute \src "ls180.v:968.6-968.29" + wire \main_uart_txfull_status + attribute \src "ls180.v:969.6-969.25" + wire \main_uart_txfull_we + attribute \src "ls180.v:999.6-999.31" + wire \main_uart_uart_sink_first + attribute \src "ls180.v:1000.6-1000.30" + wire \main_uart_uart_sink_last + attribute \src "ls180.v:1001.12-1001.44" + wire width 8 \main_uart_uart_sink_payload_data + attribute \src "ls180.v:998.6-998.31" + wire \main_uart_uart_sink_ready + attribute \src "ls180.v:997.6-997.31" + wire \main_uart_uart_sink_valid + attribute \src "ls180.v:1004.6-1004.33" + wire \main_uart_uart_source_first + attribute \src "ls180.v:1005.6-1005.32" + wire \main_uart_uart_source_last + attribute \src "ls180.v:1006.12-1006.46" + wire width 8 \main_uart_uart_source_payload_data + attribute \src "ls180.v:1003.6-1003.33" + wire \main_uart_uart_source_ready + attribute \src "ls180.v:1002.6-1002.33" + wire \main_uart_uart_source_valid + attribute \src "ls180.v:906.5-906.22" + wire \main_wb_sdram_ack + attribute \src "ls180.v:900.12-900.29" + wire width 30 \main_wb_sdram_adr + attribute \src "ls180.v:904.5-904.22" + wire \main_wb_sdram_cyc + attribute \src "ls180.v:902.13-902.32" + wire width 32 \main_wb_sdram_dat_r + attribute \src "ls180.v:901.12-901.31" + wire width 32 \main_wb_sdram_dat_w + attribute \src "ls180.v:903.11-903.28" + wire width 4 \main_wb_sdram_sel + attribute \src "ls180.v:905.5-905.22" + wire \main_wb_sdram_stb + attribute \src "ls180.v:907.5-907.21" + wire \main_wb_sdram_we + attribute \src "ls180.v:936.5-936.24" + wire \main_wdata_consumed + attribute \src "ls180.v:10349.11-10349.17" + wire width 6 \memadr + attribute \src "ls180.v:10377.11-10377.19" + wire width 6 \memadr_1 + attribute \src "ls180.v:10405.11-10405.19" + wire width 6 \memadr_2 + attribute \src "ls180.v:10433.11-10433.19" + wire width 6 \memadr_3 + attribute \src "ls180.v:10461.11-10461.19" + wire width 6 \memadr_4 + attribute \src "ls180.v:10489.12-10489.18" + wire width 25 \memdat + attribute \src "ls180.v:10503.12-10503.20" + wire width 25 \memdat_1 + attribute \src "ls180.v:10517.12-10517.20" + wire width 25 \memdat_2 + attribute \src "ls180.v:10531.12-10531.20" + wire width 25 \memdat_3 + attribute \src "ls180.v:10545.11-10545.19" + wire width 10 \memdat_4 + attribute \src "ls180.v:10546.11-10546.19" + wire width 10 \memdat_5 + attribute \src "ls180.v:10562.11-10562.19" + wire width 10 \memdat_6 + attribute \src "ls180.v:10563.11-10563.19" + wire width 10 \memdat_7 + attribute \src "ls180.v:10579.11-10579.19" + wire width 10 \memdat_8 + attribute \src "ls180.v:10593.11-10593.19" + wire width 10 \memdat_9 + attribute \src "ls180.v:52.20-52.22" + wire width 24 input 48 \nc + attribute \src "ls180.v:338.6-338.13" + wire \por_clk + attribute \src "ls180.v:18.19-18.22" + wire width 2 output 14 \pwm + attribute \src "ls180.v:184.12-184.17" + wire width 2 \pwm_1 + attribute \src "ls180.v:23.13-23.23" + wire output 19 \sdcard_clk + attribute \src "ls180.v:24.13-24.25" + wire input 20 \sdcard_cmd_i + attribute \src "ls180.v:25.13-25.25" + wire output 21 \sdcard_cmd_o + attribute \src "ls180.v:26.13-26.26" + wire output 22 \sdcard_cmd_oe + attribute \src "ls180.v:27.19-27.32" + wire width 4 input 23 \sdcard_data_i + attribute \src "ls180.v:28.19-28.32" + wire width 4 output 24 \sdcard_data_o + attribute \src "ls180.v:29.13-29.27" + wire output 25 \sdcard_data_oe + attribute \src "ls180.v:6.20-6.27" + wire width 13 output 2 \sdram_a + attribute \src "ls180.v:15.19-15.27" + wire width 2 output 11 \sdram_ba + attribute \src "ls180.v:12.13-12.24" + wire output 8 \sdram_cas_n + attribute \src "ls180.v:14.13-14.22" + wire output 10 \sdram_cke + attribute \src "ls180.v:17.13-17.24" + wire output 13 \sdram_clock + attribute \src "ls180.v:183.6-183.19" + wire \sdram_clock_1 + attribute \src "ls180.v:13.13-13.23" + wire output 9 \sdram_cs_n + attribute \src "ls180.v:16.19-16.27" + wire width 2 output 12 \sdram_dm + attribute \src "ls180.v:7.20-7.30" + wire width 16 input 3 \sdram_dq_i + attribute \src "ls180.v:8.20-8.30" + wire width 16 output 4 \sdram_dq_o + attribute \src "ls180.v:9.13-9.24" + wire output 5 \sdram_dq_oe + attribute \src "ls180.v:11.13-11.24" + wire output 7 \sdram_ras_n + attribute \src "ls180.v:10.13-10.23" + wire output 6 \sdram_we_n + attribute \src "ls180.v:2760.6-2760.15" + wire \sdrio_clk + attribute \src "ls180.v:2761.6-2761.17" + wire \sdrio_clk_1 + attribute \src "ls180.v:2770.6-2770.18" + wire \sdrio_clk_10 + attribute \src "ls180.v:2771.6-2771.18" + wire \sdrio_clk_11 + attribute \src "ls180.v:2772.6-2772.18" + wire \sdrio_clk_12 + attribute \src "ls180.v:2773.6-2773.18" + wire \sdrio_clk_13 + attribute \src "ls180.v:2774.6-2774.18" + wire \sdrio_clk_14 + attribute \src "ls180.v:2775.6-2775.18" + wire \sdrio_clk_15 + attribute \src "ls180.v:2776.6-2776.18" + wire \sdrio_clk_16 + attribute \src "ls180.v:2777.6-2777.18" + wire \sdrio_clk_17 + attribute \src "ls180.v:2778.6-2778.18" + wire \sdrio_clk_18 + attribute \src "ls180.v:2779.6-2779.18" + wire \sdrio_clk_19 + attribute \src "ls180.v:2762.6-2762.17" + wire \sdrio_clk_2 + attribute \src "ls180.v:2780.6-2780.18" + wire \sdrio_clk_20 + attribute \src "ls180.v:2781.6-2781.18" + wire \sdrio_clk_21 + attribute \src "ls180.v:2782.6-2782.18" + wire \sdrio_clk_22 + attribute \src "ls180.v:2783.6-2783.18" + wire \sdrio_clk_23 + attribute \src "ls180.v:2784.6-2784.18" + wire \sdrio_clk_24 + attribute \src "ls180.v:2785.6-2785.18" + wire \sdrio_clk_25 + attribute \src "ls180.v:2786.6-2786.18" + wire \sdrio_clk_26 + attribute \src "ls180.v:2787.6-2787.18" + wire \sdrio_clk_27 + attribute \src "ls180.v:2788.6-2788.18" + wire \sdrio_clk_28 + attribute \src "ls180.v:2789.6-2789.18" + wire \sdrio_clk_29 + attribute \src "ls180.v:2763.6-2763.17" + wire \sdrio_clk_3 + attribute \src "ls180.v:2790.6-2790.18" + wire \sdrio_clk_30 + attribute \src "ls180.v:2791.6-2791.18" + wire \sdrio_clk_31 + attribute \src "ls180.v:2792.6-2792.18" + wire \sdrio_clk_32 + attribute \src "ls180.v:2793.6-2793.18" + wire \sdrio_clk_33 + attribute \src "ls180.v:2794.6-2794.18" + wire \sdrio_clk_34 + attribute \src "ls180.v:2795.6-2795.18" + wire \sdrio_clk_35 + attribute \src "ls180.v:2796.6-2796.18" + wire \sdrio_clk_36 + attribute \src "ls180.v:2797.6-2797.18" + wire \sdrio_clk_37 + attribute \src "ls180.v:2798.6-2798.18" + wire \sdrio_clk_38 + attribute \src "ls180.v:2799.6-2799.18" + wire \sdrio_clk_39 + attribute \src "ls180.v:2764.6-2764.17" + wire \sdrio_clk_4 + attribute \src "ls180.v:2800.6-2800.18" + wire \sdrio_clk_40 + attribute \src "ls180.v:2801.6-2801.18" + wire \sdrio_clk_41 + attribute \src "ls180.v:2802.6-2802.18" + wire \sdrio_clk_42 + attribute \src "ls180.v:2803.6-2803.18" + wire \sdrio_clk_43 + attribute \src "ls180.v:2804.6-2804.18" + wire \sdrio_clk_44 + attribute \src "ls180.v:2805.6-2805.18" + wire \sdrio_clk_45 + attribute \src "ls180.v:2806.6-2806.18" + wire \sdrio_clk_46 + attribute \src "ls180.v:2807.6-2807.18" + wire \sdrio_clk_47 + attribute \src "ls180.v:2808.6-2808.18" + wire \sdrio_clk_48 + attribute \src "ls180.v:2809.6-2809.18" + wire \sdrio_clk_49 + attribute \src "ls180.v:2765.6-2765.17" + wire \sdrio_clk_5 + attribute \src "ls180.v:2810.6-2810.18" + wire \sdrio_clk_50 + attribute \src "ls180.v:2811.6-2811.18" + wire \sdrio_clk_51 + attribute \src "ls180.v:2812.6-2812.18" + wire \sdrio_clk_52 + attribute \src "ls180.v:2813.6-2813.18" + wire \sdrio_clk_53 + attribute \src "ls180.v:2814.6-2814.18" + wire \sdrio_clk_54 + attribute \src "ls180.v:2815.6-2815.18" + wire \sdrio_clk_55 + attribute \src "ls180.v:2850.6-2850.18" + wire \sdrio_clk_56 + attribute \src "ls180.v:2851.6-2851.18" + wire \sdrio_clk_57 + attribute \src "ls180.v:2852.6-2852.18" + wire \sdrio_clk_58 + attribute \src "ls180.v:2853.6-2853.18" + wire \sdrio_clk_59 + attribute \src "ls180.v:2766.6-2766.17" + wire \sdrio_clk_6 + attribute \src "ls180.v:2854.6-2854.18" + wire \sdrio_clk_60 + attribute \src "ls180.v:2855.6-2855.18" + wire \sdrio_clk_61 + attribute \src "ls180.v:2856.6-2856.18" + wire \sdrio_clk_62 + attribute \src "ls180.v:2857.6-2857.18" + wire \sdrio_clk_63 + attribute \src "ls180.v:2858.6-2858.18" + wire \sdrio_clk_64 + attribute \src "ls180.v:2859.6-2859.18" + wire \sdrio_clk_65 + attribute \src "ls180.v:2860.6-2860.18" + wire \sdrio_clk_66 + attribute \src "ls180.v:2861.6-2861.18" + wire \sdrio_clk_67 + attribute \src "ls180.v:2862.6-2862.18" + wire \sdrio_clk_68 + attribute \src "ls180.v:2767.6-2767.17" + wire \sdrio_clk_7 + attribute \src "ls180.v:2768.6-2768.17" + wire \sdrio_clk_8 + attribute \src "ls180.v:2769.6-2769.17" + wire \sdrio_clk_9 + attribute \src "ls180.v:39.13-39.26" + wire output 35 \spimaster_clk + attribute \src "ls180.v:41.13-41.27" + wire output 37 \spimaster_cs_n + attribute \src "ls180.v:42.13-42.27" + wire input 38 \spimaster_miso + attribute \src "ls180.v:40.13-40.27" + wire output 36 \spimaster_mosi + attribute \src "ls180.v:19.13-19.26" + wire output 15 \spisdcard_clk + attribute \src "ls180.v:21.13-21.27" + wire output 17 \spisdcard_cs_n + attribute \src "ls180.v:22.13-22.27" + wire input 18 \spisdcard_miso + attribute \src "ls180.v:20.13-20.27" + wire output 16 \spisdcard_mosi + attribute \src "ls180.v:43.13-43.20" + wire input 39 \sys_clk + attribute \src "ls180.v:336.6-336.15" + wire \sys_clk_1 + attribute \src "ls180.v:45.19-45.31" + wire width 2 input 41 \sys_clksel_i + attribute \src "ls180.v:46.14-46.26" + wire output 42 \sys_pll_18_o + attribute \src "ls180.v:47.14-47.27" + wire output 43 \sys_pll_lck_o + attribute \src "ls180.v:44.13-44.20" + wire input 40 \sys_rst + attribute \src "ls180.v:337.6-337.15" + wire \sys_rst_1 + attribute \src "ls180.v:38.13-38.20" + wire input 34 \uart_rx + attribute \src "ls180.v:37.13-37.20" + wire output 33 \uart_tx + attribute \src "ls180.v:10348.12-10348.15" + memory width 64 size 64 \mem + attribute \src "ls180.v:10376.12-10376.17" + memory width 64 size 64 \mem_1 + attribute \src "ls180.v:10404.12-10404.17" + memory width 64 size 64 \mem_2 + attribute \src "ls180.v:10432.12-10432.17" + memory width 64 size 64 \mem_3 + attribute \src "ls180.v:10460.12-10460.17" + memory width 64 size 64 \mem_4 + attribute \src "ls180.v:10488.12-10488.19" + memory width 25 size 8 \storage + attribute \src "ls180.v:10502.12-10502.21" + memory width 25 size 8 \storage_1 + attribute \src "ls180.v:10516.12-10516.21" + memory width 25 size 8 \storage_2 + attribute \src "ls180.v:10530.12-10530.21" + memory width 25 size 8 \storage_3 + attribute \src "ls180.v:10544.11-10544.20" + memory width 10 size 16 \storage_4 + attribute \src "ls180.v:10561.11-10561.20" + memory width 10 size 16 \storage_5 + attribute \src "ls180.v:10578.11-10578.20" + memory width 10 size 32 \storage_6 + attribute \src "ls180.v:10592.11-10592.20" + memory width 10 size 32 \storage_7 + attribute \src "ls180.v:2932.56-2932.86" + cell $add $add$ls180.v:2932$58 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_converter0_counter + connect \B 1'1 + connect \Y $add$ls180.v:2932$58_Y + end + attribute \src "ls180.v:2992.56-2992.86" + cell $add $add$ls180.v:2992$69 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_converter1_counter + connect \B 1'1 + connect \Y $add$ls180.v:2992$69_Y + end + attribute \src "ls180.v:3052.59-3052.92" + cell $add $add$ls180.v:3052$80 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_socbushandler_counter + connect \B 1'1 + connect \Y $add$ls180.v:3052$80_Y + end + attribute \src "ls180.v:4245.54-4245.83" + cell $add $add$ls180.v:4245$685 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_converter_counter + connect \B 1'1 + connect \Y $add$ls180.v:4245$685_Y + end + attribute \src "ls180.v:4345.36-4345.89" + cell $add $add$ls180.v:4345$731 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 5 + connect \A \main_uart_tx_fifo_level0 + connect \B \main_uart_tx_fifo_readable + connect \Y $add$ls180.v:4345$731_Y + end + attribute \src "ls180.v:4375.36-4375.89" + cell $add $add$ls180.v:4375$742 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 5 + connect \A \main_uart_rx_fifo_level0 + connect \B \main_uart_rx_fifo_readable + connect \Y $add$ls180.v:4375$742_Y + end + attribute \src "ls180.v:4441.54-4441.83" + cell $add $add$ls180.v:4441$757 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_spimaster27_count + connect \B 1'1 + connect \Y $add$ls180.v:4441$757_Y + end + attribute \src "ls180.v:4500.52-4500.79" + cell $add $add$ls180.v:4500$765 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_spisdcard_count + connect \B 1'1 + connect \Y $add$ls180.v:4500$765_Y + end + attribute \src "ls180.v:4604.58-4604.86" + cell $add $add$ls180.v:4604$793 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 8 + connect \A \main_sdphy_init_count + connect \B 1'1 + connect \Y $add$ls180.v:4604$793_Y + end + attribute \src "ls180.v:4661.58-4661.86" + cell $add $add$ls180.v:4661$796 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 8 + connect \A \main_sdphy_cmdw_count + connect \B 1'1 + connect \Y $add$ls180.v:4661$796_Y + end + attribute \src "ls180.v:4678.58-4678.86" + cell $add $add$ls180.v:4678$798 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 8 + connect \A \main_sdphy_cmdw_count + connect \B 1'1 + connect \Y $add$ls180.v:4678$798_Y + end + attribute \src "ls180.v:4771.59-4771.87" + cell $add $add$ls180.v:4771$815 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 8 + connect \A \main_sdphy_cmdr_count + connect \B 1'1 + connect \Y $add$ls180.v:4771$815_Y + end + attribute \src "ls180.v:4796.59-4796.87" + cell $add $add$ls180.v:4796$818 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 8 + connect \A \main_sdphy_cmdr_count + connect \B 1'1 + connect \Y $add$ls180.v:4796$818_Y + end + attribute \src "ls180.v:4918.53-4918.82" + cell $add $add$ls180.v:4918$835 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 8 + connect \A \main_sdphy_dataw_count + connect \B 1'1 + connect \Y $add$ls180.v:4918$835_Y + end + attribute \src "ls180.v:5029.65-5029.114" + cell $add $add$ls180.v:5029$849 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 10 + connect \A \main_sdphy_datar_sink_payload_block_length + connect \B 4'1000 + connect \Y $add$ls180.v:5029$849_Y + end + attribute \src "ls180.v:5034.62-5034.91" + cell $add $add$ls180.v:5034$852 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 10 + connect \A \main_sdphy_datar_count + connect \B 1'1 + connect \Y $add$ls180.v:5034$852_Y + end + attribute \src "ls180.v:5060.61-5060.90" + cell $add $add$ls180.v:5060$855 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 10 + connect \A \main_sdphy_datar_count + connect \B 1'1 + connect \Y $add$ls180.v:5060$855_Y + end + attribute \src "ls180.v:5264.80-5264.117" + cell $add $add$ls180.v:5264$1040 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdcore_crc16_inserter_cnt + connect \B 1'1 + connect \Y $add$ls180.v:5264$1040_Y + end + attribute \src "ls180.v:5458.54-5458.82" + cell $add $add$ls180.v:5458$1115 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdcore_cmd_count + connect \B 1'1 + connect \Y $add$ls180.v:5458$1115_Y + end + attribute \src "ls180.v:5510.55-5510.84" + cell $add $add$ls180.v:5510$1125 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_sdcore_data_count + connect \B 1'1 + connect \Y $add$ls180.v:5510$1125_Y + end + attribute \src "ls180.v:5536.57-5536.86" + cell $add $add$ls180.v:5536$1133 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_sdcore_data_count + connect \B 1'1 + connect \Y $add$ls180.v:5536$1133_Y + end + attribute \src "ls180.v:5657.51-5657.134" + cell $add $add$ls180.v:5657$1149 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 32 + connect \A \main_sdblock2mem_wishbonedmawriter_base + connect \B \main_sdblock2mem_wishbonedmawriter_offset + connect \Y $add$ls180.v:5657$1149_Y + end + attribute \src "ls180.v:5660.77-5660.125" + cell $add $add$ls180.v:5660$1151 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_sdblock2mem_wishbonedmawriter_offset + connect \B 1'1 + connect \Y $add$ls180.v:5660$1151_Y + end + attribute \src "ls180.v:5753.50-5753.105" + cell $add $add$ls180.v:5753$1160 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 32 + connect \A \main_sdmem2block_dma_base + connect \B \main_sdmem2block_dma_offset + connect \Y $add$ls180.v:5753$1160_Y + end + attribute \src "ls180.v:5755.77-5755.111" + cell $add $add$ls180.v:5755$1161 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_sdmem2block_dma_offset + connect \B 1'1 + connect \Y $add$ls180.v:5755$1161_Y + end + attribute \src "ls180.v:7762.36-7762.70" + cell $add $add$ls180.v:7762$2602 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_libresocsim_bus_errors + connect \B 1'1 + connect \Y $add$ls180.v:7762$2602_Y + end + attribute \src "ls180.v:7863.37-7863.72" + cell $add $add$ls180.v:7863$2635 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_sdram_sequencer_counter + connect \B 1'1 + connect \Y $add$ls180.v:7863$2635_Y + end + attribute \src "ls180.v:7880.60-7880.119" + cell $add $add$ls180.v:7880$2639 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_produce + connect \B 1'1 + connect \Y $add$ls180.v:7880$2639_Y + end + attribute \src "ls180.v:7883.60-7883.119" + cell $add $add$ls180.v:7883$2640 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_consume + connect \B 1'1 + connect \Y $add$ls180.v:7883$2640_Y + end + attribute \src "ls180.v:7887.59-7887.116" + cell $add $add$ls180.v:7887$2645 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_level + connect \B 1'1 + connect \Y $add$ls180.v:7887$2645_Y + end + attribute \src "ls180.v:7926.60-7926.119" + cell $add $add$ls180.v:7926$2655 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_produce + connect \B 1'1 + connect \Y $add$ls180.v:7926$2655_Y + end + attribute \src "ls180.v:7929.60-7929.119" + cell $add $add$ls180.v:7929$2656 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_consume + connect \B 1'1 + connect \Y $add$ls180.v:7929$2656_Y + end + attribute \src "ls180.v:7933.59-7933.116" + cell $add $add$ls180.v:7933$2661 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_level + connect \B 1'1 + connect \Y $add$ls180.v:7933$2661_Y + end + attribute \src "ls180.v:7972.60-7972.119" + cell $add $add$ls180.v:7972$2671 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_produce + connect \B 1'1 + connect \Y $add$ls180.v:7972$2671_Y + end + attribute \src "ls180.v:7975.60-7975.119" + cell $add $add$ls180.v:7975$2672 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_consume + connect \B 1'1 + connect \Y $add$ls180.v:7975$2672_Y + end + attribute \src "ls180.v:7979.59-7979.116" + cell $add $add$ls180.v:7979$2677 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_level + connect \B 1'1 + connect \Y $add$ls180.v:7979$2677_Y + end + attribute \src "ls180.v:8018.60-8018.119" + cell $add $add$ls180.v:8018$2687 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_produce + connect \B 1'1 + connect \Y $add$ls180.v:8018$2687_Y + end + attribute \src "ls180.v:8021.60-8021.119" + cell $add $add$ls180.v:8021$2688 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_consume + connect \B 1'1 + connect \Y $add$ls180.v:8021$2688_Y + end + attribute \src "ls180.v:8025.59-8025.116" + cell $add $add$ls180.v:8025$2693 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_level + connect \B 1'1 + connect \Y $add$ls180.v:8025$2693_Y + end + attribute \src "ls180.v:8255.34-8255.66" + cell $add $add$ls180.v:8255$2747 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_uart_phy_tx_bitcount + connect \B 1'1 + connect \Y $add$ls180.v:8255$2747_Y + end + attribute \src "ls180.v:8271.73-8271.131" + cell $add $add$ls180.v:8271$2750 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 33 + connect \A \main_uart_phy_phase_accumulator_tx + connect \B \main_uart_phy_storage + connect \Y $add$ls180.v:8271$2750_Y + end + attribute \src "ls180.v:8284.34-8284.66" + cell $add $add$ls180.v:8284$2754 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_uart_phy_rx_bitcount + connect \B 1'1 + connect \Y $add$ls180.v:8284$2754_Y + end + attribute \src "ls180.v:8303.73-8303.131" + cell $add $add$ls180.v:8303$2757 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 33 + connect \A \main_uart_phy_phase_accumulator_rx + connect \B \main_uart_phy_storage + connect \Y $add$ls180.v:8303$2757_Y + end + attribute \src "ls180.v:8329.33-8329.65" + cell $add $add$ls180.v:8329$2765 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_uart_tx_fifo_produce + connect \B 1'1 + connect \Y $add$ls180.v:8329$2765_Y + end + attribute \src "ls180.v:8332.33-8332.65" + cell $add $add$ls180.v:8332$2766 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_uart_tx_fifo_consume + connect \B 1'1 + connect \Y $add$ls180.v:8332$2766_Y + end + attribute \src "ls180.v:8336.33-8336.64" + cell $add $add$ls180.v:8336$2771 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 5 + connect \A \main_uart_tx_fifo_level0 + connect \B 1'1 + connect \Y $add$ls180.v:8336$2771_Y + end + attribute \src "ls180.v:8351.33-8351.65" + cell $add $add$ls180.v:8351$2776 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_uart_rx_fifo_produce + connect \B 1'1 + connect \Y $add$ls180.v:8351$2776_Y + end + attribute \src "ls180.v:8354.33-8354.65" + cell $add $add$ls180.v:8354$2777 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_uart_rx_fifo_consume + connect \B 1'1 + connect \Y $add$ls180.v:8354$2777_Y + end + attribute \src "ls180.v:8358.33-8358.64" + cell $add $add$ls180.v:8358$2782 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 5 + connect \A \main_uart_rx_fifo_level0 + connect \B 1'1 + connect \Y $add$ls180.v:8358$2782_Y + end + attribute \src "ls180.v:8379.35-8379.70" + cell $add $add$ls180.v:8379$2784 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 16 + connect \A \main_spimaster30_clk_divider + connect \B 1'1 + connect \Y $add$ls180.v:8379$2784_Y + end + attribute \src "ls180.v:8414.34-8414.68" + cell $add $add$ls180.v:8414$2789 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 16 + connect \A \main_spisdcard_clk_divider1 + connect \B 1'1 + connect \Y $add$ls180.v:8414$2789_Y + end + attribute \src "ls180.v:8450.25-8450.49" + cell $add $add$ls180.v:8450$2794 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_pwm0_counter + connect \B 1'1 + connect \Y $add$ls180.v:8450$2794_Y + end + attribute \src "ls180.v:8464.25-8464.49" + cell $add $add$ls180.v:8464$2798 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_pwm1_counter + connect \B 1'1 + connect \Y $add$ls180.v:8464$2798_Y + end + attribute \src "ls180.v:8478.31-8478.61" + cell $add $add$ls180.v:8478$2803 + parameter \A_SIGNED 0 + parameter \A_WIDTH 9 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 9 + connect \A \main_sdphy_clocker_clks + connect \B 1'1 + connect \Y $add$ls180.v:8478$2803_Y + end + attribute \src "ls180.v:8501.45-8501.88" + cell $add $add$ls180.v:8501$2807 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdphy_cmdr_cmdr_converter_demux + connect \B 1'1 + connect \Y $add$ls180.v:8501$2807_Y + end + attribute \src "ls180.v:8547.71-8547.114" + cell $add $add$ls180.v:8547$2813 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_sdphy_cmdr_cmdr_converter_demux + connect \B 1'1 + connect \Y $add$ls180.v:8547$2813_Y + end + attribute \src "ls180.v:8582.46-8582.90" + cell $add $add$ls180.v:8582$2819 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdphy_dataw_crcr_converter_demux + connect \B 1'1 + connect \Y $add$ls180.v:8582$2819_Y + end + attribute \src "ls180.v:8628.72-8628.116" + cell $add $add$ls180.v:8628$2825 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_sdphy_dataw_crcr_converter_demux + connect \B 1'1 + connect \Y $add$ls180.v:8628$2825_Y + end + attribute \src "ls180.v:8661.47-8661.92" + cell $add $add$ls180.v:8661$2831 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_datar_converter_demux + connect \B 1'1 + connect \Y $add$ls180.v:8661$2831_Y + end + attribute \src "ls180.v:8689.73-8689.118" + cell $add $add$ls180.v:8689$2837 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 2 + connect \A \main_sdphy_datar_datar_converter_demux + connect \B 1'1 + connect \Y $add$ls180.v:8689$2837_Y + end + attribute \src "ls180.v:8801.39-8801.75" + cell $add $add$ls180.v:8801$2850 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_sdcore_crc16_checker_cnt + connect \B 1'1 + connect \Y $add$ls180.v:8801$2850_Y + end + attribute \src "ls180.v:8862.37-8862.73" + cell $add $add$ls180.v:8862$2854 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 5 + connect \A \main_sdblock2mem_fifo_produce + connect \B 1'1 + connect \Y $add$ls180.v:8862$2854_Y + end + attribute \src "ls180.v:8865.37-8865.73" + cell $add $add$ls180.v:8865$2855 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 5 + connect \A \main_sdblock2mem_fifo_consume + connect \B 1'1 + connect \Y $add$ls180.v:8865$2855_Y + end + attribute \src "ls180.v:8869.36-8869.70" + cell $add $add$ls180.v:8869$2860 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 6 + connect \A \main_sdblock2mem_fifo_level + connect \B 1'1 + connect \Y $add$ls180.v:8869$2860_Y + end + attribute \src "ls180.v:8884.41-8884.80" + cell $add $add$ls180.v:8884$2864 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdblock2mem_converter_demux + connect \B 1'1 + connect \Y $add$ls180.v:8884$2864_Y + end + attribute \src "ls180.v:8930.67-8930.106" + cell $add $add$ls180.v:8930$2870 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_sdblock2mem_converter_demux + connect \B 1'1 + connect \Y $add$ls180.v:8930$2870_Y + end + attribute \src "ls180.v:8956.39-8956.76" + cell $add $add$ls180.v:8956$2872 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdmem2block_converter_mux + connect \B 1'1 + connect \Y $add$ls180.v:8956$2872_Y + end + attribute \src "ls180.v:8960.37-8960.73" + cell $add $add$ls180.v:8960$2876 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 5 + connect \A \main_sdmem2block_fifo_produce + connect \B 1'1 + connect \Y $add$ls180.v:8960$2876_Y + end + attribute \src "ls180.v:8963.37-8963.73" + cell $add $add$ls180.v:8963$2877 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 5 + connect \A \main_sdmem2block_fifo_consume + connect \B 1'1 + connect \Y $add$ls180.v:8963$2877_Y + end + attribute \src "ls180.v:8967.36-8967.70" + cell $add $add$ls180.v:8967$2882 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 6 + connect \A \main_sdmem2block_fifo_level + connect \B 1'1 + connect \Y $add$ls180.v:8967$2882_Y + end + attribute \src "ls180.v:2926.9-2926.90" + cell $and $and$ls180.v:2926$53 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface0_converted_interface_stb + connect \B \main_interface0_converted_interface_cyc + connect \Y $and$ls180.v:2926$53_Y + end + attribute \src "ls180.v:2944.9-2944.90" + cell $and $and$ls180.v:2944$60 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface0_converted_interface_stb + connect \B \main_interface0_converted_interface_cyc + connect \Y $and$ls180.v:2944$60_Y + end + attribute \src "ls180.v:2986.9-2986.90" + cell $and $and$ls180.v:2986$64 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface1_converted_interface_stb + connect \B \main_interface1_converted_interface_cyc + connect \Y $and$ls180.v:2986$64_Y + end + attribute \src "ls180.v:3004.9-3004.90" + cell $and $and$ls180.v:3004$71 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface1_converted_interface_stb + connect \B \main_interface1_converted_interface_cyc + connect \Y $and$ls180.v:3004$71_Y + end + attribute \src "ls180.v:3046.9-3046.96" + cell $and $and$ls180.v:3046$75 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_socbushandler_converted_interface_stb + connect \B \main_socbushandler_converted_interface_cyc + connect \Y $and$ls180.v:3046$75_Y + end + attribute \src "ls180.v:3064.9-3064.96" + cell $and $and$ls180.v:3064$82 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_socbushandler_converted_interface_stb + connect \B \main_socbushandler_converted_interface_cyc + connect \Y $and$ls180.v:3064$82_Y + end + attribute \src "ls180.v:3074.31-3074.90" + cell $and $and$ls180.v:3074$84 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_ram_bus_cyc + connect \B \main_libresocsim_ram_bus_stb + connect \Y $and$ls180.v:3074$84_Y + end + attribute \src "ls180.v:3074.30-3074.121" + cell $and $and$ls180.v:3074$85 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3074$84_Y + connect \B \main_libresocsim_ram_bus_we + connect \Y $and$ls180.v:3074$85_Y + end + attribute \src "ls180.v:3074.29-3074.156" + cell $and $and$ls180.v:3074$86 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3074$85_Y + connect \B \main_libresocsim_ram_bus_sel [0] + connect \Y $and$ls180.v:3074$86_Y + end + attribute \src "ls180.v:3075.31-3075.90" + cell $and $and$ls180.v:3075$87 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_ram_bus_cyc + connect \B \main_libresocsim_ram_bus_stb + connect \Y $and$ls180.v:3075$87_Y + end + attribute \src "ls180.v:3075.30-3075.121" + cell $and $and$ls180.v:3075$88 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3075$87_Y + connect \B \main_libresocsim_ram_bus_we + connect \Y $and$ls180.v:3075$88_Y + end + attribute \src "ls180.v:3075.29-3075.156" + cell $and $and$ls180.v:3075$89 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3075$88_Y + connect \B \main_libresocsim_ram_bus_sel [1] + connect \Y $and$ls180.v:3075$89_Y + end + attribute \src "ls180.v:3076.31-3076.90" + cell $and $and$ls180.v:3076$90 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_ram_bus_cyc + connect \B \main_libresocsim_ram_bus_stb + connect \Y $and$ls180.v:3076$90_Y + end + attribute \src "ls180.v:3076.30-3076.121" + cell $and $and$ls180.v:3076$91 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3076$90_Y + connect \B \main_libresocsim_ram_bus_we + connect \Y $and$ls180.v:3076$91_Y + end + attribute \src "ls180.v:3076.29-3076.156" + cell $and $and$ls180.v:3076$92 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3076$91_Y + connect \B \main_libresocsim_ram_bus_sel [2] + connect \Y $and$ls180.v:3076$92_Y + end + attribute \src "ls180.v:3077.31-3077.90" + cell $and $and$ls180.v:3077$93 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_ram_bus_cyc + connect \B \main_libresocsim_ram_bus_stb + connect \Y $and$ls180.v:3077$93_Y + end + attribute \src "ls180.v:3077.30-3077.121" + cell $and $and$ls180.v:3077$94 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3077$93_Y + connect \B \main_libresocsim_ram_bus_we + connect \Y $and$ls180.v:3077$94_Y + end + attribute \src "ls180.v:3077.29-3077.156" + cell $and $and$ls180.v:3077$95 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3077$94_Y + connect \B \main_libresocsim_ram_bus_sel [3] + connect \Y $and$ls180.v:3077$95_Y + end + attribute \src "ls180.v:3078.31-3078.90" + cell $and $and$ls180.v:3078$96 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_ram_bus_cyc + connect \B \main_libresocsim_ram_bus_stb + connect \Y $and$ls180.v:3078$96_Y + end + attribute \src "ls180.v:3078.30-3078.121" + cell $and $and$ls180.v:3078$97 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3078$96_Y + connect \B \main_libresocsim_ram_bus_we + connect \Y $and$ls180.v:3078$97_Y + end + attribute \src "ls180.v:3078.29-3078.156" + cell $and $and$ls180.v:3078$98 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3078$97_Y + connect \B \main_libresocsim_ram_bus_sel [4] + connect \Y $and$ls180.v:3078$98_Y + end + attribute \src "ls180.v:3079.30-3079.121" + cell $and $and$ls180.v:3079$100 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3079$99_Y + connect \B \main_libresocsim_ram_bus_we + connect \Y $and$ls180.v:3079$100_Y + end + attribute \src "ls180.v:3079.29-3079.156" + cell $and $and$ls180.v:3079$101 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3079$100_Y + connect \B \main_libresocsim_ram_bus_sel [5] + connect \Y $and$ls180.v:3079$101_Y + end + attribute \src "ls180.v:3079.31-3079.90" + cell $and $and$ls180.v:3079$99 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_ram_bus_cyc + connect \B \main_libresocsim_ram_bus_stb + connect \Y $and$ls180.v:3079$99_Y + end + attribute \src "ls180.v:3080.31-3080.90" + cell $and $and$ls180.v:3080$102 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_ram_bus_cyc + connect \B \main_libresocsim_ram_bus_stb + connect \Y $and$ls180.v:3080$102_Y + end + attribute \src "ls180.v:3080.30-3080.121" + cell $and $and$ls180.v:3080$103 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3080$102_Y + connect \B \main_libresocsim_ram_bus_we + connect \Y $and$ls180.v:3080$103_Y + end + attribute \src "ls180.v:3080.29-3080.156" + cell $and $and$ls180.v:3080$104 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3080$103_Y + connect \B \main_libresocsim_ram_bus_sel [6] + connect \Y $and$ls180.v:3080$104_Y + end + attribute \src "ls180.v:3081.31-3081.90" + cell $and $and$ls180.v:3081$105 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_ram_bus_cyc + connect \B \main_libresocsim_ram_bus_stb + connect \Y $and$ls180.v:3081$105_Y + end + attribute \src "ls180.v:3081.30-3081.121" + cell $and $and$ls180.v:3081$106 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3081$105_Y + connect \B \main_libresocsim_ram_bus_we + connect \Y $and$ls180.v:3081$106_Y + end + attribute \src "ls180.v:3081.29-3081.156" + cell $and $and$ls180.v:3081$107 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3081$106_Y + connect \B \main_libresocsim_ram_bus_sel [7] + connect \Y $and$ls180.v:3081$107_Y + end + attribute \src "ls180.v:3090.7-3090.89" + cell $and $and$ls180.v:3090$110 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_eventmanager_pending_re + connect \B \main_libresocsim_eventmanager_pending_r + connect \Y $and$ls180.v:3090$110_Y + end + attribute \src "ls180.v:3095.32-3095.111" + cell $and $and$ls180.v:3095$111 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_eventmanager_pending_w + connect \B \main_libresocsim_eventmanager_storage + connect \Y $and$ls180.v:3095$111_Y + end + attribute \src "ls180.v:3099.25-3099.82" + cell $and $and$ls180.v:3099$113 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface0_ram_bus_cyc + connect \B \main_interface0_ram_bus_stb + connect \Y $and$ls180.v:3099$113_Y + end + attribute \src "ls180.v:3099.24-3099.112" + cell $and $and$ls180.v:3099$114 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3099$113_Y + connect \B \main_interface0_ram_bus_we + connect \Y $and$ls180.v:3099$114_Y + end + attribute \src "ls180.v:3099.23-3099.146" + cell $and $and$ls180.v:3099$115 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3099$114_Y + connect \B \main_interface0_ram_bus_sel [0] + connect \Y $and$ls180.v:3099$115_Y + end + attribute \src "ls180.v:3100.25-3100.82" + cell $and $and$ls180.v:3100$116 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface0_ram_bus_cyc + connect \B \main_interface0_ram_bus_stb + connect \Y $and$ls180.v:3100$116_Y + end + attribute \src "ls180.v:3100.24-3100.112" + cell $and $and$ls180.v:3100$117 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3100$116_Y + connect \B \main_interface0_ram_bus_we + connect \Y $and$ls180.v:3100$117_Y + end + attribute \src "ls180.v:3100.23-3100.146" + cell $and $and$ls180.v:3100$118 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3100$117_Y + connect \B \main_interface0_ram_bus_sel [1] + connect \Y $and$ls180.v:3100$118_Y + end + attribute \src "ls180.v:3101.25-3101.82" + cell $and $and$ls180.v:3101$119 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface0_ram_bus_cyc + connect \B \main_interface0_ram_bus_stb + connect \Y $and$ls180.v:3101$119_Y + end + attribute \src "ls180.v:3101.24-3101.112" + cell $and $and$ls180.v:3101$120 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3101$119_Y + connect \B \main_interface0_ram_bus_we + connect \Y $and$ls180.v:3101$120_Y + end + attribute \src "ls180.v:3101.23-3101.146" + cell $and $and$ls180.v:3101$121 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3101$120_Y + connect \B \main_interface0_ram_bus_sel [2] + connect \Y $and$ls180.v:3101$121_Y + end + attribute \src "ls180.v:3102.25-3102.82" + cell $and $and$ls180.v:3102$122 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface0_ram_bus_cyc + connect \B \main_interface0_ram_bus_stb + connect \Y $and$ls180.v:3102$122_Y + end + attribute \src "ls180.v:3102.24-3102.112" + cell $and $and$ls180.v:3102$123 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3102$122_Y + connect \B \main_interface0_ram_bus_we + connect \Y $and$ls180.v:3102$123_Y + end + attribute \src "ls180.v:3102.23-3102.146" + cell $and $and$ls180.v:3102$124 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3102$123_Y + connect \B \main_interface0_ram_bus_sel [3] + connect \Y $and$ls180.v:3102$124_Y + end + attribute \src "ls180.v:3103.25-3103.82" + cell $and $and$ls180.v:3103$125 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface0_ram_bus_cyc + connect \B \main_interface0_ram_bus_stb + connect \Y $and$ls180.v:3103$125_Y + end + attribute \src "ls180.v:3103.24-3103.112" + cell $and $and$ls180.v:3103$126 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3103$125_Y + connect \B \main_interface0_ram_bus_we + connect \Y $and$ls180.v:3103$126_Y + end + attribute \src "ls180.v:3103.23-3103.146" + cell $and $and$ls180.v:3103$127 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3103$126_Y + connect \B \main_interface0_ram_bus_sel [4] + connect \Y $and$ls180.v:3103$127_Y + end + attribute \src "ls180.v:3104.25-3104.82" + cell $and $and$ls180.v:3104$128 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface0_ram_bus_cyc + connect \B \main_interface0_ram_bus_stb + connect \Y $and$ls180.v:3104$128_Y + end + attribute \src "ls180.v:3104.24-3104.112" + cell $and $and$ls180.v:3104$129 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3104$128_Y + connect \B \main_interface0_ram_bus_we + connect \Y $and$ls180.v:3104$129_Y + end + attribute \src "ls180.v:3104.23-3104.146" + cell $and $and$ls180.v:3104$130 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3104$129_Y + connect \B \main_interface0_ram_bus_sel [5] + connect \Y $and$ls180.v:3104$130_Y + end + attribute \src "ls180.v:3105.25-3105.82" + cell $and $and$ls180.v:3105$131 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface0_ram_bus_cyc + connect \B \main_interface0_ram_bus_stb + connect \Y $and$ls180.v:3105$131_Y + end + attribute \src "ls180.v:3105.24-3105.112" + cell $and $and$ls180.v:3105$132 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3105$131_Y + connect \B \main_interface0_ram_bus_we + connect \Y $and$ls180.v:3105$132_Y + end + attribute \src "ls180.v:3105.23-3105.146" + cell $and $and$ls180.v:3105$133 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3105$132_Y + connect \B \main_interface0_ram_bus_sel [6] + connect \Y $and$ls180.v:3105$133_Y + end + attribute \src "ls180.v:3106.25-3106.82" + cell $and $and$ls180.v:3106$134 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface0_ram_bus_cyc + connect \B \main_interface0_ram_bus_stb + connect \Y $and$ls180.v:3106$134_Y + end + attribute \src "ls180.v:3106.24-3106.112" + cell $and $and$ls180.v:3106$135 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3106$134_Y + connect \B \main_interface0_ram_bus_we + connect \Y $and$ls180.v:3106$135_Y + end + attribute \src "ls180.v:3106.23-3106.146" + cell $and $and$ls180.v:3106$136 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3106$135_Y + connect \B \main_interface0_ram_bus_sel [7] + connect \Y $and$ls180.v:3106$136_Y + end + attribute \src "ls180.v:3113.25-3113.82" + cell $and $and$ls180.v:3113$138 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface1_ram_bus_cyc + connect \B \main_interface1_ram_bus_stb + connect \Y $and$ls180.v:3113$138_Y + end + attribute \src "ls180.v:3113.24-3113.112" + cell $and $and$ls180.v:3113$139 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3113$138_Y + connect \B \main_interface1_ram_bus_we + connect \Y $and$ls180.v:3113$139_Y + end + attribute \src "ls180.v:3113.23-3113.146" + cell $and $and$ls180.v:3113$140 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3113$139_Y + connect \B \main_interface1_ram_bus_sel [0] + connect \Y $and$ls180.v:3113$140_Y + end + attribute \src "ls180.v:3114.25-3114.82" + cell $and $and$ls180.v:3114$141 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface1_ram_bus_cyc + connect \B \main_interface1_ram_bus_stb + connect \Y $and$ls180.v:3114$141_Y + end + attribute \src "ls180.v:3114.24-3114.112" + cell $and $and$ls180.v:3114$142 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3114$141_Y + connect \B \main_interface1_ram_bus_we + connect \Y $and$ls180.v:3114$142_Y + end + attribute \src "ls180.v:3114.23-3114.146" + cell $and $and$ls180.v:3114$143 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3114$142_Y + connect \B \main_interface1_ram_bus_sel [1] + connect \Y $and$ls180.v:3114$143_Y + end + attribute \src "ls180.v:3115.25-3115.82" + cell $and $and$ls180.v:3115$144 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface1_ram_bus_cyc + connect \B \main_interface1_ram_bus_stb + connect \Y $and$ls180.v:3115$144_Y + end + attribute \src "ls180.v:3115.24-3115.112" + cell $and $and$ls180.v:3115$145 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3115$144_Y + connect \B \main_interface1_ram_bus_we + connect \Y $and$ls180.v:3115$145_Y + end + attribute \src "ls180.v:3115.23-3115.146" + cell $and $and$ls180.v:3115$146 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3115$145_Y + connect \B \main_interface1_ram_bus_sel [2] + connect \Y $and$ls180.v:3115$146_Y + end + attribute \src "ls180.v:3116.25-3116.82" + cell $and $and$ls180.v:3116$147 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface1_ram_bus_cyc + connect \B \main_interface1_ram_bus_stb + connect \Y $and$ls180.v:3116$147_Y + end + attribute \src "ls180.v:3116.24-3116.112" + cell $and $and$ls180.v:3116$148 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3116$147_Y + connect \B \main_interface1_ram_bus_we + connect \Y $and$ls180.v:3116$148_Y + end + attribute \src "ls180.v:3116.23-3116.146" + cell $and $and$ls180.v:3116$149 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3116$148_Y + connect \B \main_interface1_ram_bus_sel [3] + connect \Y $and$ls180.v:3116$149_Y + end + attribute \src "ls180.v:3117.25-3117.82" + cell $and $and$ls180.v:3117$150 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface1_ram_bus_cyc + connect \B \main_interface1_ram_bus_stb + connect \Y $and$ls180.v:3117$150_Y + end + attribute \src "ls180.v:3117.24-3117.112" + cell $and $and$ls180.v:3117$151 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3117$150_Y + connect \B \main_interface1_ram_bus_we + connect \Y $and$ls180.v:3117$151_Y + end + attribute \src "ls180.v:3117.23-3117.146" + cell $and $and$ls180.v:3117$152 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3117$151_Y + connect \B \main_interface1_ram_bus_sel [4] + connect \Y $and$ls180.v:3117$152_Y + end + attribute \src "ls180.v:3118.25-3118.82" + cell $and $and$ls180.v:3118$153 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface1_ram_bus_cyc + connect \B \main_interface1_ram_bus_stb + connect \Y $and$ls180.v:3118$153_Y + end + attribute \src "ls180.v:3118.24-3118.112" + cell $and $and$ls180.v:3118$154 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3118$153_Y + connect \B \main_interface1_ram_bus_we + connect \Y $and$ls180.v:3118$154_Y + end + attribute \src "ls180.v:3118.23-3118.146" + cell $and $and$ls180.v:3118$155 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3118$154_Y + connect \B \main_interface1_ram_bus_sel [5] + connect \Y $and$ls180.v:3118$155_Y + end + attribute \src "ls180.v:3119.25-3119.82" + cell $and $and$ls180.v:3119$156 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface1_ram_bus_cyc + connect \B \main_interface1_ram_bus_stb + connect \Y $and$ls180.v:3119$156_Y + end + attribute \src "ls180.v:3119.24-3119.112" + cell $and $and$ls180.v:3119$157 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3119$156_Y + connect \B \main_interface1_ram_bus_we + connect \Y $and$ls180.v:3119$157_Y + end + attribute \src "ls180.v:3119.23-3119.146" + cell $and $and$ls180.v:3119$158 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3119$157_Y + connect \B \main_interface1_ram_bus_sel [6] + connect \Y $and$ls180.v:3119$158_Y + end + attribute \src "ls180.v:3120.25-3120.82" + cell $and $and$ls180.v:3120$159 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface1_ram_bus_cyc + connect \B \main_interface1_ram_bus_stb + connect \Y $and$ls180.v:3120$159_Y + end + attribute \src "ls180.v:3120.24-3120.112" + cell $and $and$ls180.v:3120$160 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3120$159_Y + connect \B \main_interface1_ram_bus_we + connect \Y $and$ls180.v:3120$160_Y + end + attribute \src "ls180.v:3120.23-3120.146" + cell $and $and$ls180.v:3120$161 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3120$160_Y + connect \B \main_interface1_ram_bus_sel [7] + connect \Y $and$ls180.v:3120$161_Y + end + attribute \src "ls180.v:3127.25-3127.82" + cell $and $and$ls180.v:3127$163 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface2_ram_bus_cyc + connect \B \main_interface2_ram_bus_stb + connect \Y $and$ls180.v:3127$163_Y + end + attribute \src "ls180.v:3127.24-3127.112" + cell $and $and$ls180.v:3127$164 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3127$163_Y + connect \B \main_interface2_ram_bus_we + connect \Y $and$ls180.v:3127$164_Y + end + attribute \src "ls180.v:3127.23-3127.146" + cell $and $and$ls180.v:3127$165 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3127$164_Y + connect \B \main_interface2_ram_bus_sel [0] + connect \Y $and$ls180.v:3127$165_Y + end + attribute \src "ls180.v:3128.25-3128.82" + cell $and $and$ls180.v:3128$166 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface2_ram_bus_cyc + connect \B \main_interface2_ram_bus_stb + connect \Y $and$ls180.v:3128$166_Y + end + attribute \src "ls180.v:3128.24-3128.112" + cell $and $and$ls180.v:3128$167 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3128$166_Y + connect \B \main_interface2_ram_bus_we + connect \Y $and$ls180.v:3128$167_Y + end + attribute \src "ls180.v:3128.23-3128.146" + cell $and $and$ls180.v:3128$168 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3128$167_Y + connect \B \main_interface2_ram_bus_sel [1] + connect \Y $and$ls180.v:3128$168_Y + end + attribute \src "ls180.v:3129.25-3129.82" + cell $and $and$ls180.v:3129$169 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface2_ram_bus_cyc + connect \B \main_interface2_ram_bus_stb + connect \Y $and$ls180.v:3129$169_Y + end + attribute \src "ls180.v:3129.24-3129.112" + cell $and $and$ls180.v:3129$170 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3129$169_Y + connect \B \main_interface2_ram_bus_we + connect \Y $and$ls180.v:3129$170_Y + end + attribute \src "ls180.v:3129.23-3129.146" + cell $and $and$ls180.v:3129$171 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3129$170_Y + connect \B \main_interface2_ram_bus_sel [2] + connect \Y $and$ls180.v:3129$171_Y + end + attribute \src "ls180.v:3130.25-3130.82" + cell $and $and$ls180.v:3130$172 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface2_ram_bus_cyc + connect \B \main_interface2_ram_bus_stb + connect \Y $and$ls180.v:3130$172_Y + end + attribute \src "ls180.v:3130.24-3130.112" + cell $and $and$ls180.v:3130$173 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3130$172_Y + connect \B \main_interface2_ram_bus_we + connect \Y $and$ls180.v:3130$173_Y + end + attribute \src "ls180.v:3130.23-3130.146" + cell $and $and$ls180.v:3130$174 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3130$173_Y + connect \B \main_interface2_ram_bus_sel [3] + connect \Y $and$ls180.v:3130$174_Y + end + attribute \src "ls180.v:3131.25-3131.82" + cell $and $and$ls180.v:3131$175 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface2_ram_bus_cyc + connect \B \main_interface2_ram_bus_stb + connect \Y $and$ls180.v:3131$175_Y + end + attribute \src "ls180.v:3131.24-3131.112" + cell $and $and$ls180.v:3131$176 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3131$175_Y + connect \B \main_interface2_ram_bus_we + connect \Y $and$ls180.v:3131$176_Y + end + attribute \src "ls180.v:3131.23-3131.146" + cell $and $and$ls180.v:3131$177 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3131$176_Y + connect \B \main_interface2_ram_bus_sel [4] + connect \Y $and$ls180.v:3131$177_Y + end + attribute \src "ls180.v:3132.25-3132.82" + cell $and $and$ls180.v:3132$178 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface2_ram_bus_cyc + connect \B \main_interface2_ram_bus_stb + connect \Y $and$ls180.v:3132$178_Y + end + attribute \src "ls180.v:3132.24-3132.112" + cell $and $and$ls180.v:3132$179 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3132$178_Y + connect \B \main_interface2_ram_bus_we + connect \Y $and$ls180.v:3132$179_Y + end + attribute \src "ls180.v:3132.23-3132.146" + cell $and $and$ls180.v:3132$180 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3132$179_Y + connect \B \main_interface2_ram_bus_sel [5] + connect \Y $and$ls180.v:3132$180_Y + end + attribute \src "ls180.v:3133.25-3133.82" + cell $and $and$ls180.v:3133$181 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface2_ram_bus_cyc + connect \B \main_interface2_ram_bus_stb + connect \Y $and$ls180.v:3133$181_Y + end + attribute \src "ls180.v:3133.24-3133.112" + cell $and $and$ls180.v:3133$182 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3133$181_Y + connect \B \main_interface2_ram_bus_we + connect \Y $and$ls180.v:3133$182_Y + end + attribute \src "ls180.v:3133.23-3133.146" + cell $and $and$ls180.v:3133$183 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3133$182_Y + connect \B \main_interface2_ram_bus_sel [6] + connect \Y $and$ls180.v:3133$183_Y + end + attribute \src "ls180.v:3134.25-3134.82" + cell $and $and$ls180.v:3134$184 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface2_ram_bus_cyc + connect \B \main_interface2_ram_bus_stb + connect \Y $and$ls180.v:3134$184_Y + end + attribute \src "ls180.v:3134.24-3134.112" + cell $and $and$ls180.v:3134$185 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3134$184_Y + connect \B \main_interface2_ram_bus_we + connect \Y $and$ls180.v:3134$185_Y + end + attribute \src "ls180.v:3134.23-3134.146" + cell $and $and$ls180.v:3134$186 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3134$185_Y + connect \B \main_interface2_ram_bus_sel [7] + connect \Y $and$ls180.v:3134$186_Y + end + attribute \src "ls180.v:3141.25-3141.82" + cell $and $and$ls180.v:3141$188 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface3_ram_bus_cyc + connect \B \main_interface3_ram_bus_stb + connect \Y $and$ls180.v:3141$188_Y + end + attribute \src "ls180.v:3141.24-3141.112" + cell $and $and$ls180.v:3141$189 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3141$188_Y + connect \B \main_interface3_ram_bus_we + connect \Y $and$ls180.v:3141$189_Y + end + attribute \src "ls180.v:3141.23-3141.146" + cell $and $and$ls180.v:3141$190 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3141$189_Y + connect \B \main_interface3_ram_bus_sel [0] + connect \Y $and$ls180.v:3141$190_Y + end + attribute \src "ls180.v:3142.25-3142.82" + cell $and $and$ls180.v:3142$191 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface3_ram_bus_cyc + connect \B \main_interface3_ram_bus_stb + connect \Y $and$ls180.v:3142$191_Y + end + attribute \src "ls180.v:3142.24-3142.112" + cell $and $and$ls180.v:3142$192 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3142$191_Y + connect \B \main_interface3_ram_bus_we + connect \Y $and$ls180.v:3142$192_Y + end + attribute \src "ls180.v:3142.23-3142.146" + cell $and $and$ls180.v:3142$193 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3142$192_Y + connect \B \main_interface3_ram_bus_sel [1] + connect \Y $and$ls180.v:3142$193_Y + end + attribute \src "ls180.v:3143.25-3143.82" + cell $and $and$ls180.v:3143$194 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface3_ram_bus_cyc + connect \B \main_interface3_ram_bus_stb + connect \Y $and$ls180.v:3143$194_Y + end + attribute \src "ls180.v:3143.24-3143.112" + cell $and $and$ls180.v:3143$195 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3143$194_Y + connect \B \main_interface3_ram_bus_we + connect \Y $and$ls180.v:3143$195_Y + end + attribute \src "ls180.v:3143.23-3143.146" + cell $and $and$ls180.v:3143$196 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3143$195_Y + connect \B \main_interface3_ram_bus_sel [2] + connect \Y $and$ls180.v:3143$196_Y + end + attribute \src "ls180.v:3144.25-3144.82" + cell $and $and$ls180.v:3144$197 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface3_ram_bus_cyc + connect \B \main_interface3_ram_bus_stb + connect \Y $and$ls180.v:3144$197_Y + end + attribute \src "ls180.v:3144.24-3144.112" + cell $and $and$ls180.v:3144$198 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3144$197_Y + connect \B \main_interface3_ram_bus_we + connect \Y $and$ls180.v:3144$198_Y + end + attribute \src "ls180.v:3144.23-3144.146" + cell $and $and$ls180.v:3144$199 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3144$198_Y + connect \B \main_interface3_ram_bus_sel [3] + connect \Y $and$ls180.v:3144$199_Y + end + attribute \src "ls180.v:3145.25-3145.82" + cell $and $and$ls180.v:3145$200 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface3_ram_bus_cyc + connect \B \main_interface3_ram_bus_stb + connect \Y $and$ls180.v:3145$200_Y + end + attribute \src "ls180.v:3145.24-3145.112" + cell $and $and$ls180.v:3145$201 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3145$200_Y + connect \B \main_interface3_ram_bus_we + connect \Y $and$ls180.v:3145$201_Y + end + attribute \src "ls180.v:3145.23-3145.146" + cell $and $and$ls180.v:3145$202 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3145$201_Y + connect \B \main_interface3_ram_bus_sel [4] + connect \Y $and$ls180.v:3145$202_Y + end + attribute \src "ls180.v:3146.25-3146.82" + cell $and $and$ls180.v:3146$203 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface3_ram_bus_cyc + connect \B \main_interface3_ram_bus_stb + connect \Y $and$ls180.v:3146$203_Y + end + attribute \src "ls180.v:3146.24-3146.112" + cell $and $and$ls180.v:3146$204 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3146$203_Y + connect \B \main_interface3_ram_bus_we + connect \Y $and$ls180.v:3146$204_Y + end + attribute \src "ls180.v:3146.23-3146.146" + cell $and $and$ls180.v:3146$205 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3146$204_Y + connect \B \main_interface3_ram_bus_sel [5] + connect \Y $and$ls180.v:3146$205_Y + end + attribute \src "ls180.v:3147.25-3147.82" + cell $and $and$ls180.v:3147$206 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface3_ram_bus_cyc + connect \B \main_interface3_ram_bus_stb + connect \Y $and$ls180.v:3147$206_Y + end + attribute \src "ls180.v:3147.24-3147.112" + cell $and $and$ls180.v:3147$207 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3147$206_Y + connect \B \main_interface3_ram_bus_we + connect \Y $and$ls180.v:3147$207_Y + end + attribute \src "ls180.v:3147.23-3147.146" + cell $and $and$ls180.v:3147$208 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3147$207_Y + connect \B \main_interface3_ram_bus_sel [6] + connect \Y $and$ls180.v:3147$208_Y + end + attribute \src "ls180.v:3148.25-3148.82" + cell $and $and$ls180.v:3148$209 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface3_ram_bus_cyc + connect \B \main_interface3_ram_bus_stb + connect \Y $and$ls180.v:3148$209_Y + end + attribute \src "ls180.v:3148.24-3148.112" + cell $and $and$ls180.v:3148$210 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3148$209_Y + connect \B \main_interface3_ram_bus_we + connect \Y $and$ls180.v:3148$210_Y + end + attribute \src "ls180.v:3148.23-3148.146" + cell $and $and$ls180.v:3148$211 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3148$210_Y + connect \B \main_interface3_ram_bus_sel [7] + connect \Y $and$ls180.v:3148$211_Y + end + attribute \src "ls180.v:3265.40-3265.99" + cell $and $and$ls180.v:3265$218 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_command_issue_re + connect \B \main_sdram_command_storage [4] + connect \Y $and$ls180.v:3265$218_Y + end + attribute \src "ls180.v:3266.40-3266.99" + cell $and $and$ls180.v:3266$219 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_command_issue_re + connect \B \main_sdram_command_storage [5] + connect \Y $and$ls180.v:3266$219_Y + end + attribute \src "ls180.v:3304.38-3304.103" + cell $and $and$ls180.v:3304$225 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_sequencer_done1 + connect \B $eq$ls180.v:3304$224_Y + connect \Y $and$ls180.v:3304$225_Y + end + attribute \src "ls180.v:3358.50-3358.119" + cell $and $and$ls180.v:3358$233 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_valid + connect \B \main_sdram_bankmachine0_cmd_ready + connect \Y $and$ls180.v:3358$233_Y + end + attribute \src "ls180.v:3358.49-3358.167" + cell $and $and$ls180.v:3358$234 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3358$233_Y + connect \B \main_sdram_bankmachine0_cmd_payload_is_write + connect \Y $and$ls180.v:3358$234_Y + end + attribute \src "ls180.v:3359.49-3359.118" + cell $and $and$ls180.v:3359$235 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_valid + connect \B \main_sdram_bankmachine0_cmd_ready + connect \Y $and$ls180.v:3359$235_Y + end + attribute \src "ls180.v:3359.48-3359.154" + cell $and $and$ls180.v:3359$236 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3359$235_Y + connect \B \main_sdram_bankmachine0_row_open + connect \Y $and$ls180.v:3359$236_Y + end + attribute \src "ls180.v:3360.50-3360.119" + cell $and $and$ls180.v:3360$237 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_valid + connect \B \main_sdram_bankmachine0_cmd_ready + connect \Y $and$ls180.v:3360$237_Y + end + attribute \src "ls180.v:3360.49-3360.155" + cell $and $and$ls180.v:3360$238 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3360$237_Y + connect \B \main_sdram_bankmachine0_row_open + connect \Y $and$ls180.v:3360$238_Y + end + attribute \src "ls180.v:3363.7-3363.114" + cell $and $and$ls180.v:3363$240 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_source_valid + connect \B \main_sdram_bankmachine0_cmd_buffer_source_valid + connect \Y $and$ls180.v:3363$240_Y + end + attribute \src "ls180.v:3392.66-3392.246" + cell $and $and$ls180.v:3392$246 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we + connect \B $or$ls180.v:3392$245_Y + connect \Y $and$ls180.v:3392$246_Y + end + attribute \src "ls180.v:3393.64-3393.187" + cell $and $and$ls180.v:3393$247 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable + connect \B \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re + connect \Y $and$ls180.v:3393$247_Y + end + attribute \src "ls180.v:3417.9-3417.86" + cell $and $and$ls180.v:3417$253 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_twtpcon_ready + connect \B \main_sdram_bankmachine0_trascon_ready + connect \Y $and$ls180.v:3417$253_Y + end + attribute \src "ls180.v:3429.9-3429.86" + cell $and $and$ls180.v:3429$254 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_twtpcon_ready + connect \B \main_sdram_bankmachine0_trascon_ready + connect \Y $and$ls180.v:3429$254_Y + end + attribute \src "ls180.v:3479.13-3479.87" + cell $and $and$ls180.v:3479$256 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_ready + connect \B \main_sdram_bankmachine0_auto_precharge + connect \Y $and$ls180.v:3479$256_Y + end + attribute \src "ls180.v:3515.50-3515.119" + cell $and $and$ls180.v:3515$263 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_valid + connect \B \main_sdram_bankmachine1_cmd_ready + connect \Y $and$ls180.v:3515$263_Y + end + attribute \src "ls180.v:3515.49-3515.167" + cell $and $and$ls180.v:3515$264 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3515$263_Y + connect \B \main_sdram_bankmachine1_cmd_payload_is_write + connect \Y $and$ls180.v:3515$264_Y + end + attribute \src "ls180.v:3516.49-3516.118" + cell $and $and$ls180.v:3516$265 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_valid + connect \B \main_sdram_bankmachine1_cmd_ready + connect \Y $and$ls180.v:3516$265_Y + end + attribute \src "ls180.v:3516.48-3516.154" + cell $and $and$ls180.v:3516$266 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3516$265_Y + connect \B \main_sdram_bankmachine1_row_open + connect \Y $and$ls180.v:3516$266_Y + end + attribute \src "ls180.v:3517.50-3517.119" + cell $and $and$ls180.v:3517$267 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_valid + connect \B \main_sdram_bankmachine1_cmd_ready + connect \Y $and$ls180.v:3517$267_Y + end + attribute \src "ls180.v:3517.49-3517.155" + cell $and $and$ls180.v:3517$268 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3517$267_Y + connect \B \main_sdram_bankmachine1_row_open + connect \Y $and$ls180.v:3517$268_Y + end + attribute \src "ls180.v:3520.7-3520.114" + cell $and $and$ls180.v:3520$270 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_source_valid + connect \B \main_sdram_bankmachine1_cmd_buffer_source_valid + connect \Y $and$ls180.v:3520$270_Y + end + attribute \src "ls180.v:3549.66-3549.246" + cell $and $and$ls180.v:3549$276 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we + connect \B $or$ls180.v:3549$275_Y + connect \Y $and$ls180.v:3549$276_Y + end + attribute \src "ls180.v:3550.64-3550.187" + cell $and $and$ls180.v:3550$277 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable + connect \B \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re + connect \Y $and$ls180.v:3550$277_Y + end + attribute \src "ls180.v:3574.9-3574.86" + cell $and $and$ls180.v:3574$283 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_twtpcon_ready + connect \B \main_sdram_bankmachine1_trascon_ready + connect \Y $and$ls180.v:3574$283_Y + end + attribute \src "ls180.v:3586.9-3586.86" + cell $and $and$ls180.v:3586$284 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_twtpcon_ready + connect \B \main_sdram_bankmachine1_trascon_ready + connect \Y $and$ls180.v:3586$284_Y + end + attribute \src "ls180.v:3636.13-3636.87" + cell $and $and$ls180.v:3636$286 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_ready + connect \B \main_sdram_bankmachine1_auto_precharge + connect \Y $and$ls180.v:3636$286_Y + end + attribute \src "ls180.v:3672.50-3672.119" + cell $and $and$ls180.v:3672$293 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_valid + connect \B \main_sdram_bankmachine2_cmd_ready + connect \Y $and$ls180.v:3672$293_Y + end + attribute \src "ls180.v:3672.49-3672.167" + cell $and $and$ls180.v:3672$294 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3672$293_Y + connect \B \main_sdram_bankmachine2_cmd_payload_is_write + connect \Y $and$ls180.v:3672$294_Y + end + attribute \src "ls180.v:3673.49-3673.118" + cell $and $and$ls180.v:3673$295 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_valid + connect \B \main_sdram_bankmachine2_cmd_ready + connect \Y $and$ls180.v:3673$295_Y + end + attribute \src "ls180.v:3673.48-3673.154" + cell $and $and$ls180.v:3673$296 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3673$295_Y + connect \B \main_sdram_bankmachine2_row_open + connect \Y $and$ls180.v:3673$296_Y + end + attribute \src "ls180.v:3674.50-3674.119" + cell $and $and$ls180.v:3674$297 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_valid + connect \B \main_sdram_bankmachine2_cmd_ready + connect \Y $and$ls180.v:3674$297_Y + end + attribute \src "ls180.v:3674.49-3674.155" + cell $and $and$ls180.v:3674$298 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3674$297_Y + connect \B \main_sdram_bankmachine2_row_open + connect \Y $and$ls180.v:3674$298_Y + end + attribute \src "ls180.v:3677.7-3677.114" + cell $and $and$ls180.v:3677$300 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_source_valid + connect \B \main_sdram_bankmachine2_cmd_buffer_source_valid + connect \Y $and$ls180.v:3677$300_Y + end + attribute \src "ls180.v:3706.66-3706.246" + cell $and $and$ls180.v:3706$306 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we + connect \B $or$ls180.v:3706$305_Y + connect \Y $and$ls180.v:3706$306_Y + end + attribute \src "ls180.v:3707.64-3707.187" + cell $and $and$ls180.v:3707$307 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable + connect \B \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re + connect \Y $and$ls180.v:3707$307_Y + end + attribute \src "ls180.v:3731.9-3731.86" + cell $and $and$ls180.v:3731$313 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_twtpcon_ready + connect \B \main_sdram_bankmachine2_trascon_ready + connect \Y $and$ls180.v:3731$313_Y + end + attribute \src "ls180.v:3743.9-3743.86" + cell $and $and$ls180.v:3743$314 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_twtpcon_ready + connect \B \main_sdram_bankmachine2_trascon_ready + connect \Y $and$ls180.v:3743$314_Y + end + attribute \src "ls180.v:3793.13-3793.87" + cell $and $and$ls180.v:3793$316 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_ready + connect \B \main_sdram_bankmachine2_auto_precharge + connect \Y $and$ls180.v:3793$316_Y + end + attribute \src "ls180.v:3829.50-3829.119" + cell $and $and$ls180.v:3829$323 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_valid + connect \B \main_sdram_bankmachine3_cmd_ready + connect \Y $and$ls180.v:3829$323_Y + end + attribute \src "ls180.v:3829.49-3829.167" + cell $and $and$ls180.v:3829$324 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3829$323_Y + connect \B \main_sdram_bankmachine3_cmd_payload_is_write + connect \Y $and$ls180.v:3829$324_Y + end + attribute \src "ls180.v:3830.49-3830.118" + cell $and $and$ls180.v:3830$325 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_valid + connect \B \main_sdram_bankmachine3_cmd_ready + connect \Y $and$ls180.v:3830$325_Y + end + attribute \src "ls180.v:3830.48-3830.154" + cell $and $and$ls180.v:3830$326 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3830$325_Y + connect \B \main_sdram_bankmachine3_row_open + connect \Y $and$ls180.v:3830$326_Y + end + attribute \src "ls180.v:3831.50-3831.119" + cell $and $and$ls180.v:3831$327 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_valid + connect \B \main_sdram_bankmachine3_cmd_ready + connect \Y $and$ls180.v:3831$327_Y + end + attribute \src "ls180.v:3831.49-3831.155" + cell $and $and$ls180.v:3831$328 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3831$327_Y + connect \B \main_sdram_bankmachine3_row_open + connect \Y $and$ls180.v:3831$328_Y + end + attribute \src "ls180.v:3834.7-3834.114" + cell $and $and$ls180.v:3834$330 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_source_valid + connect \B \main_sdram_bankmachine3_cmd_buffer_source_valid + connect \Y $and$ls180.v:3834$330_Y + end + attribute \src "ls180.v:3863.66-3863.246" + cell $and $and$ls180.v:3863$336 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we + connect \B $or$ls180.v:3863$335_Y + connect \Y $and$ls180.v:3863$336_Y + end + attribute \src "ls180.v:3864.64-3864.187" + cell $and $and$ls180.v:3864$337 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable + connect \B \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re + connect \Y $and$ls180.v:3864$337_Y + end + attribute \src "ls180.v:3888.9-3888.86" + cell $and $and$ls180.v:3888$343 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_twtpcon_ready + connect \B \main_sdram_bankmachine3_trascon_ready + connect \Y $and$ls180.v:3888$343_Y + end + attribute \src "ls180.v:3900.9-3900.86" + cell $and $and$ls180.v:3900$344 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_twtpcon_ready + connect \B \main_sdram_bankmachine3_trascon_ready + connect \Y $and$ls180.v:3900$344_Y + end + attribute \src "ls180.v:3950.13-3950.87" + cell $and $and$ls180.v:3950$346 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_ready + connect \B \main_sdram_bankmachine3_auto_precharge + connect \Y $and$ls180.v:3950$346_Y + end + attribute \src "ls180.v:3965.37-3965.102" + cell $and $and$ls180.v:3965$347 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:3965$347_Y + end + attribute \src "ls180.v:3965.108-3965.188" + cell $and $and$ls180.v:3965$349 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_payload_ras + connect \B $not$ls180.v:3965$348_Y + connect \Y $and$ls180.v:3965$349_Y + end + attribute \src "ls180.v:3965.107-3965.231" + cell $and $and$ls180.v:3965$351 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3965$349_Y + connect \B $not$ls180.v:3965$350_Y + connect \Y $and$ls180.v:3965$351_Y + end + attribute \src "ls180.v:3965.36-3965.232" + cell $and $and$ls180.v:3965$352 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3965$347_Y + connect \B $and$ls180.v:3965$351_Y + connect \Y $and$ls180.v:3965$352_Y + end + attribute \src "ls180.v:3966.37-3966.102" + cell $and $and$ls180.v:3966$353 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:3966$353_Y + end + attribute \src "ls180.v:3966.108-3966.188" + cell $and $and$ls180.v:3966$355 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_payload_ras + connect \B $not$ls180.v:3966$354_Y + connect \Y $and$ls180.v:3966$355_Y + end + attribute \src "ls180.v:3966.107-3966.231" + cell $and $and$ls180.v:3966$357 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3966$355_Y + connect \B $not$ls180.v:3966$356_Y + connect \Y $and$ls180.v:3966$357_Y + end + attribute \src "ls180.v:3966.36-3966.232" + cell $and $and$ls180.v:3966$358 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3966$353_Y + connect \B $and$ls180.v:3966$357_Y + connect \Y $and$ls180.v:3966$358_Y + end + attribute \src "ls180.v:3967.34-3967.85" + cell $and $and$ls180.v:3967$359 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_trrdcon_ready + connect \B \main_sdram_tfawcon_ready + connect \Y $and$ls180.v:3967$359_Y + end + attribute \src "ls180.v:3968.37-3968.102" + cell $and $and$ls180.v:3968$360 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:3968$360_Y + end + attribute \src "ls180.v:3968.36-3968.194" + cell $and $and$ls180.v:3968$362 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3968$360_Y + connect \B $or$ls180.v:3968$361_Y + connect \Y $and$ls180.v:3968$362_Y + end + attribute \src "ls180.v:3970.37-3970.102" + cell $and $and$ls180.v:3970$363 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:3970$363_Y + end + attribute \src "ls180.v:3970.36-3970.148" + cell $and $and$ls180.v:3970$364 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3970$363_Y + connect \B \main_sdram_choose_req_cmd_payload_is_write + connect \Y $and$ls180.v:3970$364_Y + end + attribute \src "ls180.v:3971.40-3971.119" + cell $and $and$ls180.v:3971$365 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_valid + connect \B \main_sdram_bankmachine0_cmd_payload_is_read + connect \Y $and$ls180.v:3971$365_Y + end + attribute \src "ls180.v:3971.124-3971.203" + cell $and $and$ls180.v:3971$366 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_valid + connect \B \main_sdram_bankmachine1_cmd_payload_is_read + connect \Y $and$ls180.v:3971$366_Y + end + attribute \src "ls180.v:3971.209-3971.288" + cell $and $and$ls180.v:3971$368 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_valid + connect \B \main_sdram_bankmachine2_cmd_payload_is_read + connect \Y $and$ls180.v:3971$368_Y + end + attribute \src "ls180.v:3971.294-3971.373" + cell $and $and$ls180.v:3971$370 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_valid + connect \B \main_sdram_bankmachine3_cmd_payload_is_read + connect \Y $and$ls180.v:3971$370_Y + end + attribute \src "ls180.v:3972.41-3972.121" + cell $and $and$ls180.v:3972$372 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_valid + connect \B \main_sdram_bankmachine0_cmd_payload_is_write + connect \Y $and$ls180.v:3972$372_Y + end + attribute \src "ls180.v:3972.126-3972.206" + cell $and $and$ls180.v:3972$373 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_valid + connect \B \main_sdram_bankmachine1_cmd_payload_is_write + connect \Y $and$ls180.v:3972$373_Y + end + attribute \src "ls180.v:3972.212-3972.292" + cell $and $and$ls180.v:3972$375 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_valid + connect \B \main_sdram_bankmachine2_cmd_payload_is_write + connect \Y $and$ls180.v:3972$375_Y + end + attribute \src "ls180.v:3972.298-3972.378" + cell $and $and$ls180.v:3972$377 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_valid + connect \B \main_sdram_bankmachine3_cmd_payload_is_write + connect \Y $and$ls180.v:3972$377_Y + end + attribute \src "ls180.v:3979.38-3979.111" + cell $and $and$ls180.v:3979$381 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_refresh_gnt + connect \B \main_sdram_bankmachine1_refresh_gnt + connect \Y $and$ls180.v:3979$381_Y + end + attribute \src "ls180.v:3979.37-3979.150" + cell $and $and$ls180.v:3979$382 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3979$381_Y + connect \B \main_sdram_bankmachine2_refresh_gnt + connect \Y $and$ls180.v:3979$382_Y + end + attribute \src "ls180.v:3979.36-3979.189" + cell $and $and$ls180.v:3979$383 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3979$382_Y + connect \B \main_sdram_bankmachine3_refresh_gnt + connect \Y $and$ls180.v:3979$383_Y + end + attribute \src "ls180.v:3985.77-3985.153" + cell $and $and$ls180.v:3985$386 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_payload_is_cmd + connect \B \main_sdram_choose_cmd_want_cmds + connect \Y $and$ls180.v:3985$386_Y + end + attribute \src "ls180.v:3985.162-3985.246" + cell $and $and$ls180.v:3985$388 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_payload_ras + connect \B $not$ls180.v:3985$387_Y + connect \Y $and$ls180.v:3985$388_Y + end + attribute \src "ls180.v:3985.161-3985.291" + cell $and $and$ls180.v:3985$390 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3985$388_Y + connect \B $not$ls180.v:3985$389_Y + connect \Y $and$ls180.v:3985$390_Y + end + attribute \src "ls180.v:3985.76-3985.333" + cell $and $and$ls180.v:3985$393 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3985$386_Y + connect \B $or$ls180.v:3985$392_Y + connect \Y $and$ls180.v:3985$393_Y + end + attribute \src "ls180.v:3985.338-3985.505" + cell $and $and$ls180.v:3985$396 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:3985$394_Y + connect \B $eq$ls180.v:3985$395_Y + connect \Y $and$ls180.v:3985$396_Y + end + attribute \src "ls180.v:3985.38-3985.507" + cell $and $and$ls180.v:3985$398 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_valid + connect \B $or$ls180.v:3985$397_Y + connect \Y $and$ls180.v:3985$398_Y + end + attribute \src "ls180.v:3986.77-3986.153" + cell $and $and$ls180.v:3986$399 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_payload_is_cmd + connect \B \main_sdram_choose_cmd_want_cmds + connect \Y $and$ls180.v:3986$399_Y + end + attribute \src "ls180.v:3986.162-3986.246" + cell $and $and$ls180.v:3986$401 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_payload_ras + connect \B $not$ls180.v:3986$400_Y + connect \Y $and$ls180.v:3986$401_Y + end + attribute \src "ls180.v:3986.161-3986.291" + cell $and $and$ls180.v:3986$403 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3986$401_Y + connect \B $not$ls180.v:3986$402_Y + connect \Y $and$ls180.v:3986$403_Y + end + attribute \src "ls180.v:3986.76-3986.333" + cell $and $and$ls180.v:3986$406 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3986$399_Y + connect \B $or$ls180.v:3986$405_Y + connect \Y $and$ls180.v:3986$406_Y + end + attribute \src "ls180.v:3986.338-3986.505" + cell $and $and$ls180.v:3986$409 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:3986$407_Y + connect \B $eq$ls180.v:3986$408_Y + connect \Y $and$ls180.v:3986$409_Y + end + attribute \src "ls180.v:3986.38-3986.507" + cell $and $and$ls180.v:3986$411 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_valid + connect \B $or$ls180.v:3986$410_Y + connect \Y $and$ls180.v:3986$411_Y + end + attribute \src "ls180.v:3987.77-3987.153" + cell $and $and$ls180.v:3987$412 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_payload_is_cmd + connect \B \main_sdram_choose_cmd_want_cmds + connect \Y $and$ls180.v:3987$412_Y + end + attribute \src "ls180.v:3987.162-3987.246" + cell $and $and$ls180.v:3987$414 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_payload_ras + connect \B $not$ls180.v:3987$413_Y + connect \Y $and$ls180.v:3987$414_Y + end + attribute \src "ls180.v:3987.161-3987.291" + cell $and $and$ls180.v:3987$416 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3987$414_Y + connect \B $not$ls180.v:3987$415_Y + connect \Y $and$ls180.v:3987$416_Y + end + attribute \src "ls180.v:3987.76-3987.333" + cell $and $and$ls180.v:3987$419 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3987$412_Y + connect \B $or$ls180.v:3987$418_Y + connect \Y $and$ls180.v:3987$419_Y + end + attribute \src "ls180.v:3987.338-3987.505" + cell $and $and$ls180.v:3987$422 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:3987$420_Y + connect \B $eq$ls180.v:3987$421_Y + connect \Y $and$ls180.v:3987$422_Y + end + attribute \src "ls180.v:3987.38-3987.507" + cell $and $and$ls180.v:3987$424 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_valid + connect \B $or$ls180.v:3987$423_Y + connect \Y $and$ls180.v:3987$424_Y + end + attribute \src "ls180.v:3988.77-3988.153" + cell $and $and$ls180.v:3988$425 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_payload_is_cmd + connect \B \main_sdram_choose_cmd_want_cmds + connect \Y $and$ls180.v:3988$425_Y + end + attribute \src "ls180.v:3988.162-3988.246" + cell $and $and$ls180.v:3988$427 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_payload_ras + connect \B $not$ls180.v:3988$426_Y + connect \Y $and$ls180.v:3988$427_Y + end + attribute \src "ls180.v:3988.161-3988.291" + cell $and $and$ls180.v:3988$429 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3988$427_Y + connect \B $not$ls180.v:3988$428_Y + connect \Y $and$ls180.v:3988$429_Y + end + attribute \src "ls180.v:3988.76-3988.333" + cell $and $and$ls180.v:3988$432 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3988$425_Y + connect \B $or$ls180.v:3988$431_Y + connect \Y $and$ls180.v:3988$432_Y + end + attribute \src "ls180.v:3988.338-3988.505" + cell $and $and$ls180.v:3988$435 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:3988$433_Y + connect \B $eq$ls180.v:3988$434_Y + connect \Y $and$ls180.v:3988$435_Y + end + attribute \src "ls180.v:3988.38-3988.507" + cell $and $and$ls180.v:3988$437 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_valid + connect \B $or$ls180.v:3988$436_Y + connect \Y $and$ls180.v:3988$437_Y + end + attribute \src "ls180.v:4018.77-4018.153" + cell $and $and$ls180.v:4018$444 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_payload_is_cmd + connect \B \main_sdram_choose_req_want_cmds + connect \Y $and$ls180.v:4018$444_Y + end + attribute \src "ls180.v:4018.162-4018.246" + cell $and $and$ls180.v:4018$446 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_payload_ras + connect \B $not$ls180.v:4018$445_Y + connect \Y $and$ls180.v:4018$446_Y + end + attribute \src "ls180.v:4018.161-4018.291" + cell $and $and$ls180.v:4018$448 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4018$446_Y + connect \B $not$ls180.v:4018$447_Y + connect \Y $and$ls180.v:4018$448_Y + end + attribute \src "ls180.v:4018.76-4018.333" + cell $and $and$ls180.v:4018$451 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4018$444_Y + connect \B $or$ls180.v:4018$450_Y + connect \Y $and$ls180.v:4018$451_Y + end + attribute \src "ls180.v:4018.338-4018.505" + cell $and $and$ls180.v:4018$454 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:4018$452_Y + connect \B $eq$ls180.v:4018$453_Y + connect \Y $and$ls180.v:4018$454_Y + end + attribute \src "ls180.v:4018.38-4018.507" + cell $and $and$ls180.v:4018$456 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_valid + connect \B $or$ls180.v:4018$455_Y + connect \Y $and$ls180.v:4018$456_Y + end + attribute \src "ls180.v:4019.77-4019.153" + cell $and $and$ls180.v:4019$457 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_payload_is_cmd + connect \B \main_sdram_choose_req_want_cmds + connect \Y $and$ls180.v:4019$457_Y + end + attribute \src "ls180.v:4019.162-4019.246" + cell $and $and$ls180.v:4019$459 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_payload_ras + connect \B $not$ls180.v:4019$458_Y + connect \Y $and$ls180.v:4019$459_Y + end + attribute \src "ls180.v:4019.161-4019.291" + cell $and $and$ls180.v:4019$461 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4019$459_Y + connect \B $not$ls180.v:4019$460_Y + connect \Y $and$ls180.v:4019$461_Y + end + attribute \src "ls180.v:4019.76-4019.333" + cell $and $and$ls180.v:4019$464 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4019$457_Y + connect \B $or$ls180.v:4019$463_Y + connect \Y $and$ls180.v:4019$464_Y + end + attribute \src "ls180.v:4019.338-4019.505" + cell $and $and$ls180.v:4019$467 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:4019$465_Y + connect \B $eq$ls180.v:4019$466_Y + connect \Y $and$ls180.v:4019$467_Y + end + attribute \src "ls180.v:4019.38-4019.507" + cell $and $and$ls180.v:4019$469 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_valid + connect \B $or$ls180.v:4019$468_Y + connect \Y $and$ls180.v:4019$469_Y + end + attribute \src "ls180.v:4020.77-4020.153" + cell $and $and$ls180.v:4020$470 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_payload_is_cmd + connect \B \main_sdram_choose_req_want_cmds + connect \Y $and$ls180.v:4020$470_Y + end + attribute \src "ls180.v:4020.162-4020.246" + cell $and $and$ls180.v:4020$472 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_payload_ras + connect \B $not$ls180.v:4020$471_Y + connect \Y $and$ls180.v:4020$472_Y + end + attribute \src "ls180.v:4020.161-4020.291" + cell $and $and$ls180.v:4020$474 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4020$472_Y + connect \B $not$ls180.v:4020$473_Y + connect \Y $and$ls180.v:4020$474_Y + end + attribute \src "ls180.v:4020.76-4020.333" + cell $and $and$ls180.v:4020$477 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4020$470_Y + connect \B $or$ls180.v:4020$476_Y + connect \Y $and$ls180.v:4020$477_Y + end + attribute \src "ls180.v:4020.338-4020.505" + cell $and $and$ls180.v:4020$480 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:4020$478_Y + connect \B $eq$ls180.v:4020$479_Y + connect \Y $and$ls180.v:4020$480_Y + end + attribute \src "ls180.v:4020.38-4020.507" + cell $and $and$ls180.v:4020$482 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_valid + connect \B $or$ls180.v:4020$481_Y + connect \Y $and$ls180.v:4020$482_Y + end + attribute \src "ls180.v:4021.77-4021.153" + cell $and $and$ls180.v:4021$483 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_payload_is_cmd + connect \B \main_sdram_choose_req_want_cmds + connect \Y $and$ls180.v:4021$483_Y + end + attribute \src "ls180.v:4021.162-4021.246" + cell $and $and$ls180.v:4021$485 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_payload_ras + connect \B $not$ls180.v:4021$484_Y + connect \Y $and$ls180.v:4021$485_Y + end + attribute \src "ls180.v:4021.161-4021.291" + cell $and $and$ls180.v:4021$487 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4021$485_Y + connect \B $not$ls180.v:4021$486_Y + connect \Y $and$ls180.v:4021$487_Y + end + attribute \src "ls180.v:4021.76-4021.333" + cell $and $and$ls180.v:4021$490 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4021$483_Y + connect \B $or$ls180.v:4021$489_Y + connect \Y $and$ls180.v:4021$490_Y + end + attribute \src "ls180.v:4021.338-4021.505" + cell $and $and$ls180.v:4021$493 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:4021$491_Y + connect \B $eq$ls180.v:4021$492_Y + connect \Y $and$ls180.v:4021$493_Y + end + attribute \src "ls180.v:4021.38-4021.507" + cell $and $and$ls180.v:4021$495 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_valid + connect \B $or$ls180.v:4021$494_Y + connect \Y $and$ls180.v:4021$495_Y + end + attribute \src "ls180.v:4050.8-4050.73" + cell $and $and$ls180.v:4050$500 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_cmd_cmd_valid + connect \B \main_sdram_choose_cmd_cmd_ready + connect \Y $and$ls180.v:4050$500_Y + end + attribute \src "ls180.v:4050.7-4050.114" + cell $and $and$ls180.v:4050$502 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4050$500_Y + connect \B $eq$ls180.v:4050$501_Y + connect \Y $and$ls180.v:4050$502_Y + end + attribute \src "ls180.v:4053.8-4053.73" + cell $and $and$ls180.v:4053$503 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:4053$503_Y + end + attribute \src "ls180.v:4053.7-4053.114" + cell $and $and$ls180.v:4053$505 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4053$503_Y + connect \B $eq$ls180.v:4053$504_Y + connect \Y $and$ls180.v:4053$505_Y + end + attribute \src "ls180.v:4059.8-4059.73" + cell $and $and$ls180.v:4059$507 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_cmd_cmd_valid + connect \B \main_sdram_choose_cmd_cmd_ready + connect \Y $and$ls180.v:4059$507_Y + end + attribute \src "ls180.v:4059.7-4059.114" + cell $and $and$ls180.v:4059$509 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4059$507_Y + connect \B $eq$ls180.v:4059$508_Y + connect \Y $and$ls180.v:4059$509_Y + end + attribute \src "ls180.v:4062.8-4062.73" + cell $and $and$ls180.v:4062$510 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:4062$510_Y + end + attribute \src "ls180.v:4062.7-4062.114" + cell $and $and$ls180.v:4062$512 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4062$510_Y + connect \B $eq$ls180.v:4062$511_Y + connect \Y $and$ls180.v:4062$512_Y + end + attribute \src "ls180.v:4068.8-4068.73" + cell $and $and$ls180.v:4068$514 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_cmd_cmd_valid + connect \B \main_sdram_choose_cmd_cmd_ready + connect \Y $and$ls180.v:4068$514_Y + end + attribute \src "ls180.v:4068.7-4068.114" + cell $and $and$ls180.v:4068$516 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4068$514_Y + connect \B $eq$ls180.v:4068$515_Y + connect \Y $and$ls180.v:4068$516_Y + end + attribute \src "ls180.v:4071.8-4071.73" + cell $and $and$ls180.v:4071$517 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:4071$517_Y + end + attribute \src "ls180.v:4071.7-4071.114" + cell $and $and$ls180.v:4071$519 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4071$517_Y + connect \B $eq$ls180.v:4071$518_Y + connect \Y $and$ls180.v:4071$519_Y + end + attribute \src "ls180.v:4077.8-4077.73" + cell $and $and$ls180.v:4077$521 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_cmd_cmd_valid + connect \B \main_sdram_choose_cmd_cmd_ready + connect \Y $and$ls180.v:4077$521_Y + end + attribute \src "ls180.v:4077.7-4077.114" + cell $and $and$ls180.v:4077$523 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4077$521_Y + connect \B $eq$ls180.v:4077$522_Y + connect \Y $and$ls180.v:4077$523_Y + end + attribute \src "ls180.v:4080.8-4080.73" + cell $and $and$ls180.v:4080$524 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:4080$524_Y + end + attribute \src "ls180.v:4080.7-4080.114" + cell $and $and$ls180.v:4080$526 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4080$524_Y + connect \B $eq$ls180.v:4080$525_Y + connect \Y $and$ls180.v:4080$526_Y + end + attribute \src "ls180.v:4105.71-4105.151" + cell $and $and$ls180.v:4105$531 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_payload_ras + connect \B $not$ls180.v:4105$530_Y + connect \Y $and$ls180.v:4105$531_Y + end + attribute \src "ls180.v:4105.70-4105.194" + cell $and $and$ls180.v:4105$533 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4105$531_Y + connect \B $not$ls180.v:4105$532_Y + connect \Y $and$ls180.v:4105$533_Y + end + attribute \src "ls180.v:4105.41-4105.222" + cell $and $and$ls180.v:4105$536 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_cas_allowed + connect \B $or$ls180.v:4105$535_Y + connect \Y $and$ls180.v:4105$536_Y + end + attribute \src "ls180.v:4143.71-4143.151" + cell $and $and$ls180.v:4143$540 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_payload_ras + connect \B $not$ls180.v:4143$539_Y + connect \Y $and$ls180.v:4143$540_Y + end + attribute \src "ls180.v:4143.70-4143.194" + cell $and $and$ls180.v:4143$542 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4143$540_Y + connect \B $not$ls180.v:4143$541_Y + connect \Y $and$ls180.v:4143$542_Y + end + attribute \src "ls180.v:4143.41-4143.222" + cell $and $and$ls180.v:4143$545 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_cas_allowed + connect \B $or$ls180.v:4143$544_Y + connect \Y $and$ls180.v:4143$545_Y + end + attribute \src "ls180.v:4161.110-4161.179" + cell $and $and$ls180.v:4161$550 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank1_lock + connect \B $eq$ls180.v:4161$549_Y + connect \Y $and$ls180.v:4161$550_Y + end + attribute \src "ls180.v:4161.185-4161.254" + cell $and $and$ls180.v:4161$553 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank2_lock + connect \B $eq$ls180.v:4161$552_Y + connect \Y $and$ls180.v:4161$553_Y + end + attribute \src "ls180.v:4161.260-4161.329" + cell $and $and$ls180.v:4161$556 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank3_lock + connect \B $eq$ls180.v:4161$555_Y + connect \Y $and$ls180.v:4161$556_Y + end + attribute \src "ls180.v:4161.41-4161.332" + cell $and $and$ls180.v:4161$559 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:4161$548_Y + connect \B $not$ls180.v:4161$558_Y + connect \Y $and$ls180.v:4161$559_Y + end + attribute \src "ls180.v:4161.40-4161.355" + cell $and $and$ls180.v:4161$560 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4161$559_Y + connect \B \main_port_cmd_valid + connect \Y $and$ls180.v:4161$560_Y + end + attribute \src "ls180.v:4162.34-4162.106" + cell $and $and$ls180.v:4162$563 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:4162$561_Y + connect \B $not$ls180.v:4162$562_Y + connect \Y $and$ls180.v:4162$563_Y + end + attribute \src "ls180.v:4166.110-4166.179" + cell $and $and$ls180.v:4166$566 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank0_lock + connect \B $eq$ls180.v:4166$565_Y + connect \Y $and$ls180.v:4166$566_Y + end + attribute \src "ls180.v:4166.185-4166.254" + cell $and $and$ls180.v:4166$569 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank2_lock + connect \B $eq$ls180.v:4166$568_Y + connect \Y $and$ls180.v:4166$569_Y + end + attribute \src "ls180.v:4166.260-4166.329" + cell $and $and$ls180.v:4166$572 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank3_lock + connect \B $eq$ls180.v:4166$571_Y + connect \Y $and$ls180.v:4166$572_Y + end + attribute \src "ls180.v:4166.41-4166.332" + cell $and $and$ls180.v:4166$575 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:4166$564_Y + connect \B $not$ls180.v:4166$574_Y + connect \Y $and$ls180.v:4166$575_Y + end + attribute \src "ls180.v:4166.40-4166.355" + cell $and $and$ls180.v:4166$576 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4166$575_Y + connect \B \main_port_cmd_valid + connect \Y $and$ls180.v:4166$576_Y + end + attribute \src "ls180.v:4167.34-4167.106" + cell $and $and$ls180.v:4167$579 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:4167$577_Y + connect \B $not$ls180.v:4167$578_Y + connect \Y $and$ls180.v:4167$579_Y + end + attribute \src "ls180.v:4171.110-4171.179" + cell $and $and$ls180.v:4171$582 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank0_lock + connect \B $eq$ls180.v:4171$581_Y + connect \Y $and$ls180.v:4171$582_Y + end + attribute \src "ls180.v:4171.185-4171.254" + cell $and $and$ls180.v:4171$585 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank1_lock + connect \B $eq$ls180.v:4171$584_Y + connect \Y $and$ls180.v:4171$585_Y + end + attribute \src "ls180.v:4171.260-4171.329" + cell $and $and$ls180.v:4171$588 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank3_lock + connect \B $eq$ls180.v:4171$587_Y + connect \Y $and$ls180.v:4171$588_Y + end + attribute \src "ls180.v:4171.41-4171.332" + cell $and $and$ls180.v:4171$591 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:4171$580_Y + connect \B $not$ls180.v:4171$590_Y + connect \Y $and$ls180.v:4171$591_Y + end + attribute \src "ls180.v:4171.40-4171.355" + cell $and $and$ls180.v:4171$592 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4171$591_Y + connect \B \main_port_cmd_valid + connect \Y $and$ls180.v:4171$592_Y + end + attribute \src "ls180.v:4172.34-4172.106" + cell $and $and$ls180.v:4172$595 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:4172$593_Y + connect \B $not$ls180.v:4172$594_Y + connect \Y $and$ls180.v:4172$595_Y + end + attribute \src "ls180.v:4176.110-4176.179" + cell $and $and$ls180.v:4176$598 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank0_lock + connect \B $eq$ls180.v:4176$597_Y + connect \Y $and$ls180.v:4176$598_Y + end + attribute \src "ls180.v:4176.185-4176.254" + cell $and $and$ls180.v:4176$601 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank1_lock + connect \B $eq$ls180.v:4176$600_Y + connect \Y $and$ls180.v:4176$601_Y + end + attribute \src "ls180.v:4176.260-4176.329" + cell $and $and$ls180.v:4176$604 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank2_lock + connect \B $eq$ls180.v:4176$603_Y + connect \Y $and$ls180.v:4176$604_Y + end + attribute \src "ls180.v:4176.41-4176.332" + cell $and $and$ls180.v:4176$607 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:4176$596_Y + connect \B $not$ls180.v:4176$606_Y + connect \Y $and$ls180.v:4176$607_Y + end + attribute \src "ls180.v:4176.40-4176.355" + cell $and $and$ls180.v:4176$608 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4176$607_Y + connect \B \main_port_cmd_valid + connect \Y $and$ls180.v:4176$608_Y + end + attribute \src "ls180.v:4177.34-4177.106" + cell $and $and$ls180.v:4177$611 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:4177$609_Y + connect \B $not$ls180.v:4177$610_Y + connect \Y $and$ls180.v:4177$611_Y + end + attribute \src "ls180.v:4181.151-4181.220" + cell $and $and$ls180.v:4181$615 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank1_lock + connect \B $eq$ls180.v:4181$614_Y + connect \Y $and$ls180.v:4181$615_Y + end + attribute \src "ls180.v:4181.226-4181.295" + cell $and $and$ls180.v:4181$618 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank2_lock + connect \B $eq$ls180.v:4181$617_Y + connect \Y $and$ls180.v:4181$618_Y + end + attribute \src "ls180.v:4181.301-4181.370" + cell $and $and$ls180.v:4181$621 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank3_lock + connect \B $eq$ls180.v:4181$620_Y + connect \Y $and$ls180.v:4181$621_Y + end + attribute \src "ls180.v:4181.82-4181.373" + cell $and $and$ls180.v:4181$624 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:4181$613_Y + connect \B $not$ls180.v:4181$623_Y + connect \Y $and$ls180.v:4181$624_Y + end + attribute \src "ls180.v:4181.43-4181.374" + cell $and $and$ls180.v:4181$625 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:4181$612_Y + connect \B $and$ls180.v:4181$624_Y + connect \Y $and$ls180.v:4181$625_Y + end + attribute \src "ls180.v:4181.42-4181.410" + cell $and $and$ls180.v:4181$626 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4181$625_Y + connect \B \main_sdram_interface_bank0_ready + connect \Y $and$ls180.v:4181$626_Y + end + attribute \src "ls180.v:4181.525-4181.594" + cell $and $and$ls180.v:4181$631 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank0_lock + connect \B $eq$ls180.v:4181$630_Y + connect \Y $and$ls180.v:4181$631_Y + end + attribute \src "ls180.v:4181.600-4181.669" + cell $and $and$ls180.v:4181$634 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank2_lock + connect \B $eq$ls180.v:4181$633_Y + connect \Y $and$ls180.v:4181$634_Y + end + attribute \src "ls180.v:4181.675-4181.744" + cell $and $and$ls180.v:4181$637 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank3_lock + connect \B $eq$ls180.v:4181$636_Y + connect \Y $and$ls180.v:4181$637_Y + end + attribute \src "ls180.v:4181.456-4181.747" + cell $and $and$ls180.v:4181$640 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:4181$629_Y + connect \B $not$ls180.v:4181$639_Y + connect \Y $and$ls180.v:4181$640_Y + end + attribute \src "ls180.v:4181.417-4181.748" + cell $and $and$ls180.v:4181$641 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:4181$628_Y + connect \B $and$ls180.v:4181$640_Y + connect \Y $and$ls180.v:4181$641_Y + end + attribute \src "ls180.v:4181.416-4181.784" + cell $and $and$ls180.v:4181$642 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4181$641_Y + connect \B \main_sdram_interface_bank1_ready + connect \Y $and$ls180.v:4181$642_Y + end + attribute \src "ls180.v:4181.899-4181.968" + cell $and $and$ls180.v:4181$647 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank0_lock + connect \B $eq$ls180.v:4181$646_Y + connect \Y $and$ls180.v:4181$647_Y + end + attribute \src "ls180.v:4181.974-4181.1043" + cell $and $and$ls180.v:4181$650 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank1_lock + connect \B $eq$ls180.v:4181$649_Y + connect \Y $and$ls180.v:4181$650_Y + end + attribute \src "ls180.v:4181.1049-4181.1118" + cell $and $and$ls180.v:4181$653 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank3_lock + connect \B $eq$ls180.v:4181$652_Y + connect \Y $and$ls180.v:4181$653_Y + end + attribute \src "ls180.v:4181.830-4181.1121" + cell $and $and$ls180.v:4181$656 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:4181$645_Y + connect \B $not$ls180.v:4181$655_Y + connect \Y $and$ls180.v:4181$656_Y + end + attribute \src "ls180.v:4181.791-4181.1122" + cell $and $and$ls180.v:4181$657 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:4181$644_Y + connect \B $and$ls180.v:4181$656_Y + connect \Y $and$ls180.v:4181$657_Y + end + attribute \src "ls180.v:4181.790-4181.1158" + cell $and $and$ls180.v:4181$658 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4181$657_Y + connect \B \main_sdram_interface_bank2_ready + connect \Y $and$ls180.v:4181$658_Y + end + attribute \src "ls180.v:4181.1273-4181.1342" + cell $and $and$ls180.v:4181$663 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank0_lock + connect \B $eq$ls180.v:4181$662_Y + connect \Y $and$ls180.v:4181$663_Y + end + attribute \src "ls180.v:4181.1348-4181.1417" + cell $and $and$ls180.v:4181$666 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank1_lock + connect \B $eq$ls180.v:4181$665_Y + connect \Y $and$ls180.v:4181$666_Y + end + attribute \src "ls180.v:4181.1423-4181.1492" + cell $and $and$ls180.v:4181$669 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank2_lock + connect \B $eq$ls180.v:4181$668_Y + connect \Y $and$ls180.v:4181$669_Y + end + attribute \src "ls180.v:4181.1204-4181.1495" + cell $and $and$ls180.v:4181$672 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:4181$661_Y + connect \B $not$ls180.v:4181$671_Y + connect \Y $and$ls180.v:4181$672_Y + end + attribute \src "ls180.v:4181.1165-4181.1496" + cell $and $and$ls180.v:4181$673 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:4181$660_Y + connect \B $and$ls180.v:4181$672_Y + connect \Y $and$ls180.v:4181$673_Y + end + attribute \src "ls180.v:4181.1164-4181.1532" + cell $and $and$ls180.v:4181$674 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4181$673_Y + connect \B \main_sdram_interface_bank3_ready + connect \Y $and$ls180.v:4181$674_Y + end + attribute \src "ls180.v:4239.9-4239.46" + cell $and $and$ls180.v:4239$680 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_wb_sdram_stb + connect \B \main_wb_sdram_cyc + connect \Y $and$ls180.v:4239$680_Y + end + attribute \src "ls180.v:4257.9-4257.46" + cell $and $and$ls180.v:4257$687 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_wb_sdram_stb + connect \B \main_wb_sdram_cyc + connect \Y $and$ls180.v:4257$687_Y + end + attribute \src "ls180.v:4270.32-4270.75" + cell $and $and$ls180.v:4270$691 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_litedram_wb_cyc + connect \B \main_litedram_wb_stb + connect \Y $and$ls180.v:4270$691_Y + end + attribute \src "ls180.v:4270.31-4270.99" + cell $and $and$ls180.v:4270$693 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4270$691_Y + connect \B $not$ls180.v:4270$692_Y + connect \Y $and$ls180.v:4270$693_Y + end + attribute \src "ls180.v:4271.34-4271.102" + cell $and $and$ls180.v:4271$695 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4271$694_Y + connect \B \main_port_cmd_payload_we + connect \Y $and$ls180.v:4271$695_Y + end + attribute \src "ls180.v:4271.33-4271.128" + cell $and $and$ls180.v:4271$697 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4271$695_Y + connect \B $not$ls180.v:4271$696_Y + connect \Y $and$ls180.v:4271$697_Y + end + attribute \src "ls180.v:4272.33-4272.104" + cell $and $and$ls180.v:4272$700 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4272$698_Y + connect \B $not$ls180.v:4272$699_Y + connect \Y $and$ls180.v:4272$700_Y + end + attribute \src "ls180.v:4273.49-4273.85" + cell $and $and$ls180.v:4273$701 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_litedram_wb_we + connect \B \main_ack_wdata + connect \Y $and$ls180.v:4273$701_Y + end + attribute \src "ls180.v:4273.90-4273.129" + cell $and $and$ls180.v:4273$703 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:4273$702_Y + connect \B \main_ack_rdata + connect \Y $and$ls180.v:4273$703_Y + end + attribute \src "ls180.v:4273.32-4273.131" + cell $and $and$ls180.v:4273$705 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_ack_cmd + connect \B $or$ls180.v:4273$704_Y + connect \Y $and$ls180.v:4273$705_Y + end + attribute \src "ls180.v:4274.25-4274.66" + cell $and $and$ls180.v:4274$706 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_valid + connect \B \main_port_cmd_ready + connect \Y $and$ls180.v:4274$706_Y + end + attribute \src "ls180.v:4275.27-4275.72" + cell $and $and$ls180.v:4275$708 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_port_wdata_valid + connect \B \main_port_wdata_ready + connect \Y $and$ls180.v:4275$708_Y + end + attribute \src "ls180.v:4276.26-4276.71" + cell $and $and$ls180.v:4276$710 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_port_rdata_valid + connect \B \main_port_rdata_ready + connect \Y $and$ls180.v:4276$710_Y + end + attribute \src "ls180.v:4305.64-4305.88" + cell $and $and$ls180.v:4305$716 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A 1'0 + connect \B \main_uart_rxtx_we + connect \Y $and$ls180.v:4305$716_Y + end + attribute \src "ls180.v:4309.7-4309.78" + cell $and $and$ls180.v:4309$720 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_eventmanager_pending_re + connect \B \main_uart_eventmanager_pending_r [0] + connect \Y $and$ls180.v:4309$720_Y + end + attribute \src "ls180.v:4320.7-4320.78" + cell $and $and$ls180.v:4320$723 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_eventmanager_pending_re + connect \B \main_uart_eventmanager_pending_r [1] + connect \Y $and$ls180.v:4320$723_Y + end + attribute \src "ls180.v:4329.26-4329.97" + cell $and $and$ls180.v:4329$725 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_eventmanager_pending_w [0] + connect \B \main_uart_eventmanager_storage [0] + connect \Y $and$ls180.v:4329$725_Y + end + attribute \src "ls180.v:4329.102-4329.173" + cell $and $and$ls180.v:4329$726 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_eventmanager_pending_w [1] + connect \B \main_uart_eventmanager_storage [1] + connect \Y $and$ls180.v:4329$726_Y + end + attribute \src "ls180.v:4344.41-4344.133" + cell $and $and$ls180.v:4344$730 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_tx_fifo_syncfifo_readable + connect \B $or$ls180.v:4344$729_Y + connect \Y $and$ls180.v:4344$730_Y + end + attribute \src "ls180.v:4355.39-4355.136" + cell $and $and$ls180.v:4355$735 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_tx_fifo_syncfifo_we + connect \B $or$ls180.v:4355$734_Y + connect \Y $and$ls180.v:4355$735_Y + end + attribute \src "ls180.v:4356.37-4356.104" + cell $and $and$ls180.v:4356$736 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_tx_fifo_syncfifo_readable + connect \B \main_uart_tx_fifo_syncfifo_re + connect \Y $and$ls180.v:4356$736_Y + end + attribute \src "ls180.v:4374.41-4374.133" + cell $and $and$ls180.v:4374$741 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_rx_fifo_syncfifo_readable + connect \B $or$ls180.v:4374$740_Y + connect \Y $and$ls180.v:4374$741_Y + end + attribute \src "ls180.v:4385.39-4385.136" + cell $and $and$ls180.v:4385$746 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_rx_fifo_syncfifo_we + connect \B $or$ls180.v:4385$745_Y + connect \Y $and$ls180.v:4385$746_Y + end + attribute \src "ls180.v:4386.37-4386.104" + cell $and $and$ls180.v:4386$747 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_rx_fifo_syncfifo_readable + connect \B \main_uart_rx_fifo_syncfifo_re + connect \Y $and$ls180.v:4386$747_Y + end + attribute \src "ls180.v:4585.33-4585.86" + cell $and $and$ls180.v:4585$791 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_clocker_clk1 + connect \B $not$ls180.v:4585$790_Y + connect \Y $and$ls180.v:4585$791_Y + end + attribute \src "ls180.v:4689.9-4689.68" + cell $and $and$ls180.v:4689$800 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdw_sink_valid + connect \B \main_sdphy_cmdw_pads_out_ready + connect \Y $and$ls180.v:4689$800_Y + end + attribute \src "ls180.v:4709.53-4709.145" + cell $and $and$ls180.v:4709$803 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_cmdr_pads_in_valid + connect \B $or$ls180.v:4709$802_Y + connect \Y $and$ls180.v:4709$803_Y + end + attribute \src "ls180.v:4728.52-4728.137" + cell $and $and$ls180.v:4728$806 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_cmdr_converter_sink_valid + connect \B \main_sdphy_cmdr_cmdr_converter_sink_ready + connect \Y $and$ls180.v:4728$806_Y + end + attribute \src "ls180.v:4769.9-4769.68" + cell $and $and$ls180.v:4769$814 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_source_valid + connect \B \main_sdphy_cmdr_source_ready + connect \Y $and$ls180.v:4769$814_Y + end + attribute \src "ls180.v:4807.9-4807.68" + cell $and $and$ls180.v:4807$820 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_source_valid + connect \B \main_sdphy_cmdr_source_ready + connect \Y $and$ls180.v:4807$820_Y + end + attribute \src "ls180.v:4816.10-4816.69" + cell $and $and$ls180.v:4816$821 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_sink_valid + connect \B \main_sdphy_cmdr_pads_out_ready + connect \Y $and$ls180.v:4816$821_Y + end + attribute \src "ls180.v:4816.9-4816.93" + cell $and $and$ls180.v:4816$822 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4816$821_Y + connect \B \main_sdphy_cmdw_done + connect \Y $and$ls180.v:4816$822_Y + end + attribute \src "ls180.v:4836.54-4836.117" + cell $and $and$ls180.v:4836$824 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_crcr_pads_in_valid + connect \B \main_sdphy_dataw_crcr_run + connect \Y $and$ls180.v:4836$824_Y + end + attribute \src "ls180.v:4855.53-4855.140" + cell $and $and$ls180.v:4855$827 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_crcr_converter_sink_valid + connect \B \main_sdphy_dataw_crcr_converter_sink_ready + connect \Y $and$ls180.v:4855$827_Y + end + attribute \src "ls180.v:4952.9-4952.70" + cell $and $and$ls180.v:4952$837 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_sink_valid + connect \B \main_sdphy_dataw_pads_out_ready + connect \Y $and$ls180.v:4952$837_Y + end + attribute \src "ls180.v:4970.55-4970.120" + cell $and $and$ls180.v:4970$839 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_datar_pads_in_valid + connect \B \main_sdphy_datar_datar_run + connect \Y $and$ls180.v:4970$839_Y + end + attribute \src "ls180.v:4989.54-4989.143" + cell $and $and$ls180.v:4989$842 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_datar_converter_sink_valid + connect \B \main_sdphy_datar_datar_converter_sink_ready + connect \Y $and$ls180.v:4989$842_Y + end + attribute \src "ls180.v:5071.9-5071.70" + cell $and $and$ls180.v:5071$857 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_source_valid + connect \B \main_sdphy_datar_source_ready + connect \Y $and$ls180.v:5071$857_Y + end + attribute \src "ls180.v:5078.9-5078.70" + cell $and $and$ls180.v:5078$858 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_sink_valid + connect \B \main_sdphy_datar_pads_out_ready + connect \Y $and$ls180.v:5078$858_Y + end + attribute \src "ls180.v:5159.48-5159.124" + cell $and $and$ls180.v:5159$981 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_sink_last + connect \B \main_sdcore_crc16_inserter_sink_valid + connect \Y $and$ls180.v:5159$981_Y + end + attribute \src "ls180.v:5159.47-5159.165" + cell $and $and$ls180.v:5159$982 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5159$981_Y + connect \B \main_sdcore_crc16_inserter_sink_ready + connect \Y $and$ls180.v:5159$982_Y + end + attribute \src "ls180.v:5160.50-5160.127" + cell $and $and$ls180.v:5160$983 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_sink_valid + connect \B \main_sdcore_crc16_inserter_sink_ready + connect \Y $and$ls180.v:5160$983_Y + end + attribute \src "ls180.v:5162.48-5162.124" + cell $and $and$ls180.v:5162$984 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_sink_last + connect \B \main_sdcore_crc16_inserter_sink_valid + connect \Y $and$ls180.v:5162$984_Y + end + attribute \src "ls180.v:5162.47-5162.165" + cell $and $and$ls180.v:5162$985 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5162$984_Y + connect \B \main_sdcore_crc16_inserter_sink_ready + connect \Y $and$ls180.v:5162$985_Y + end + attribute \src "ls180.v:5163.50-5163.127" + cell $and $and$ls180.v:5163$986 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_sink_valid + connect \B \main_sdcore_crc16_inserter_sink_ready + connect \Y $and$ls180.v:5163$986_Y + end + attribute \src "ls180.v:5165.48-5165.124" + cell $and $and$ls180.v:5165$987 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_sink_last + connect \B \main_sdcore_crc16_inserter_sink_valid + connect \Y $and$ls180.v:5165$987_Y + end + attribute \src "ls180.v:5165.47-5165.165" + cell $and $and$ls180.v:5165$988 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5165$987_Y + connect \B \main_sdcore_crc16_inserter_sink_ready + connect \Y $and$ls180.v:5165$988_Y + end + attribute \src "ls180.v:5166.50-5166.127" + cell $and $and$ls180.v:5166$989 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_sink_valid + connect \B \main_sdcore_crc16_inserter_sink_ready + connect \Y $and$ls180.v:5166$989_Y + end + attribute \src "ls180.v:5168.48-5168.124" + cell $and $and$ls180.v:5168$990 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_sink_last + connect \B \main_sdcore_crc16_inserter_sink_valid + connect \Y $and$ls180.v:5168$990_Y + end + attribute \src "ls180.v:5168.47-5168.165" + cell $and $and$ls180.v:5168$991 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5168$990_Y + connect \B \main_sdcore_crc16_inserter_sink_ready + connect \Y $and$ls180.v:5168$991_Y + end + attribute \src "ls180.v:5169.50-5169.127" + cell $and $and$ls180.v:5169$992 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_sink_valid + connect \B \main_sdcore_crc16_inserter_sink_ready + connect \Y $and$ls180.v:5169$992_Y + end + attribute \src "ls180.v:5282.10-5282.86" + cell $and $and$ls180.v:5282$1041 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_sink_valid + connect \B \main_sdcore_crc16_inserter_sink_last + connect \Y $and$ls180.v:5282$1041_Y + end + attribute \src "ls180.v:5282.9-5282.127" + cell $and $and$ls180.v:5282$1042 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5282$1041_Y + connect \B \main_sdcore_crc16_inserter_sink_ready + connect \Y $and$ls180.v:5282$1042_Y + end + attribute \src "ls180.v:5292.9-5292.152" + cell $and $and$ls180.v:5292$1046 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:5292$1044_Y + connect \B $eq$ls180.v:5292$1045_Y + connect \Y $and$ls180.v:5292$1046_Y + end + attribute \src "ls180.v:5292.8-5292.226" + cell $and $and$ls180.v:5292$1048 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5292$1046_Y + connect \B $eq$ls180.v:5292$1047_Y + connect \Y $and$ls180.v:5292$1048_Y + end + attribute \src "ls180.v:5292.7-5292.300" + cell $and $and$ls180.v:5292$1050 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5292$1048_Y + connect \B $eq$ls180.v:5292$1049_Y + connect \Y $and$ls180.v:5292$1050_Y + end + attribute \src "ls180.v:5297.49-5297.124" + cell $and $and$ls180.v:5297$1051 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_sink_valid + connect \B \main_sdcore_crc16_checker_sink_ready + connect \Y $and$ls180.v:5297$1051_Y + end + attribute \src "ls180.v:5307.49-5307.124" + cell $and $and$ls180.v:5307$1054 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_sink_valid + connect \B \main_sdcore_crc16_checker_sink_ready + connect \Y $and$ls180.v:5307$1054_Y + end + attribute \src "ls180.v:5317.49-5317.124" + cell $and $and$ls180.v:5317$1057 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_sink_valid + connect \B \main_sdcore_crc16_checker_sink_ready + connect \Y $and$ls180.v:5317$1057_Y + end + attribute \src "ls180.v:5327.49-5327.124" + cell $and $and$ls180.v:5327$1060 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_sink_valid + connect \B \main_sdcore_crc16_checker_sink_ready + connect \Y $and$ls180.v:5327$1060_Y + end + attribute \src "ls180.v:5339.7-5339.84" + cell $and $and$ls180.v:5339$1065 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_sink_valid + connect \B $gt$ls180.v:5339$1064_Y + connect \Y $and$ls180.v:5339$1065_Y + end + attribute \src "ls180.v:5457.9-5457.64" + cell $and $and$ls180.v:5457$1114 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdw_sink_valid + connect \B \main_sdphy_cmdw_sink_ready + connect \Y $and$ls180.v:5457$1114_Y + end + attribute \src "ls180.v:5509.10-5509.66" + cell $and $and$ls180.v:5509$1123 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_sink_valid + connect \B \main_sdphy_dataw_sink_last + connect \Y $and$ls180.v:5509$1123_Y + end + attribute \src "ls180.v:5509.9-5509.97" + cell $and $and$ls180.v:5509$1124 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:5509$1123_Y + connect \B \main_sdphy_dataw_sink_ready + connect \Y $and$ls180.v:5509$1124_Y + end + attribute \src "ls180.v:5535.11-5535.71" + cell $and $and$ls180.v:5535$1132 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_source_last + connect \B \main_sdphy_datar_source_ready + connect \Y $and$ls180.v:5535$1132_Y + end + attribute \src "ls180.v:5619.43-5619.152" + cell $and $and$ls180.v:5619$1140 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_fifo_syncfifo_we + connect \B $or$ls180.v:5619$1139_Y + connect \Y $and$ls180.v:5619$1140_Y + end + attribute \src "ls180.v:5620.41-5620.116" + cell $and $and$ls180.v:5620$1141 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_fifo_syncfifo_readable + connect \B \main_sdblock2mem_fifo_syncfifo_re + connect \Y $and$ls180.v:5620$1141_Y + end + attribute \src "ls180.v:5632.48-5632.125" + cell $and $and$ls180.v:5632$1146 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_converter_sink_valid + connect \B \main_sdblock2mem_converter_sink_ready + connect \Y $and$ls180.v:5632$1146_Y + end + attribute \src "ls180.v:5659.9-5659.102" + cell $and $and$ls180.v:5659$1150 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_wishbonedmawriter_sink_valid + connect \B \main_sdblock2mem_wishbonedmawriter_sink_ready + connect \Y $and$ls180.v:5659$1150_Y + end + attribute \src "ls180.v:5732.9-5732.58" + cell $and $and$ls180.v:5732$1156 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface1_bus_stb + connect \B \main_interface1_bus_ack + connect \Y $and$ls180.v:5732$1156_Y + end + attribute \src "ls180.v:5785.51-5785.123" + cell $and $and$ls180.v:5785$1164 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdmem2block_converter_sink_first + connect \B \main_sdmem2block_converter_first + connect \Y $and$ls180.v:5785$1164_Y + end + attribute \src "ls180.v:5786.50-5786.120" + cell $and $and$ls180.v:5786$1165 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdmem2block_converter_sink_last + connect \B \main_sdmem2block_converter_last + connect \Y $and$ls180.v:5786$1165_Y + end + attribute \src "ls180.v:5787.49-5787.122" + cell $and $and$ls180.v:5787$1166 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdmem2block_converter_last + connect \B \main_sdmem2block_converter_source_ready + connect \Y $and$ls180.v:5787$1166_Y + end + attribute \src "ls180.v:5839.43-5839.152" + cell $and $and$ls180.v:5839$1171 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdmem2block_fifo_syncfifo_we + connect \B $or$ls180.v:5839$1170_Y + connect \Y $and$ls180.v:5839$1171_Y + end + attribute \src "ls180.v:5840.41-5840.116" + cell $and $and$ls180.v:5840$1172 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdmem2block_fifo_syncfifo_readable + connect \B \main_sdmem2block_fifo_syncfifo_re + connect \Y $and$ls180.v:5840$1172_Y + end + attribute \src "ls180.v:5872.9-5872.76" + cell $and $and$ls180.v:5872$1176 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_libresocsim_wishbone_cyc + connect \B \builder_libresocsim_wishbone_stb + connect \Y $and$ls180.v:5872$1176_Y + end + attribute \src "ls180.v:5875.44-5875.120" + cell $and $and$ls180.v:5875$1178 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_libresocsim_wishbone_we + connect \B $ne$ls180.v:5875$1177_Y + connect \Y $and$ls180.v:5875$1178_Y + end + attribute \src "ls180.v:5895.46-5895.90" + cell $and $and$ls180.v:5895$1180 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_ack + connect \B $eq$ls180.v:5895$1179_Y + connect \Y $and$ls180.v:5895$1180_Y + end + attribute \src "ls180.v:5896.46-5896.90" + cell $and $and$ls180.v:5896$1182 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_ack + connect \B $eq$ls180.v:5896$1181_Y + connect \Y $and$ls180.v:5896$1182_Y + end + attribute \src "ls180.v:5897.49-5897.93" + cell $and $and$ls180.v:5897$1184 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_ack + connect \B $eq$ls180.v:5897$1183_Y + connect \Y $and$ls180.v:5897$1184_Y + end + attribute \src "ls180.v:5898.35-5898.79" + cell $and $and$ls180.v:5898$1186 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_ack + connect \B $eq$ls180.v:5898$1185_Y + connect \Y $and$ls180.v:5898$1186_Y + end + attribute \src "ls180.v:5899.35-5899.79" + cell $and $and$ls180.v:5899$1188 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_ack + connect \B $eq$ls180.v:5899$1187_Y + connect \Y $and$ls180.v:5899$1188_Y + end + attribute \src "ls180.v:5900.46-5900.90" + cell $and $and$ls180.v:5900$1190 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_err + connect \B $eq$ls180.v:5900$1189_Y + connect \Y $and$ls180.v:5900$1190_Y + end + attribute \src "ls180.v:5901.46-5901.90" + cell $and $and$ls180.v:5901$1192 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_err + connect \B $eq$ls180.v:5901$1191_Y + connect \Y $and$ls180.v:5901$1192_Y + end + attribute \src "ls180.v:5902.49-5902.93" + cell $and $and$ls180.v:5902$1194 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_err + connect \B $eq$ls180.v:5902$1193_Y + connect \Y $and$ls180.v:5902$1194_Y + end + attribute \src "ls180.v:5903.35-5903.79" + cell $and $and$ls180.v:5903$1196 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_err + connect \B $eq$ls180.v:5903$1195_Y + connect \Y $and$ls180.v:5903$1196_Y + end + attribute \src "ls180.v:5904.35-5904.79" + cell $and $and$ls180.v:5904$1198 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_err + connect \B $eq$ls180.v:5904$1197_Y + connect \Y $and$ls180.v:5904$1198_Y + end + attribute \src "ls180.v:6013.40-6013.81" + cell $and $and$ls180.v:6013$1213 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_cyc + connect \B \builder_slave_sel [0] + connect \Y $and$ls180.v:6013$1213_Y + end + attribute \src "ls180.v:6014.39-6014.80" + cell $and $and$ls180.v:6014$1214 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_cyc + connect \B \builder_slave_sel [1] + connect \Y $and$ls180.v:6014$1214_Y + end + attribute \src "ls180.v:6015.39-6015.80" + cell $and $and$ls180.v:6015$1215 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_cyc + connect \B \builder_slave_sel [2] + connect \Y $and$ls180.v:6015$1215_Y + end + attribute \src "ls180.v:6016.39-6016.80" + cell $and $and$ls180.v:6016$1216 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_cyc + connect \B \builder_slave_sel [3] + connect \Y $and$ls180.v:6016$1216_Y + end + attribute \src "ls180.v:6017.39-6017.80" + cell $and $and$ls180.v:6017$1217 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_cyc + connect \B \builder_slave_sel [4] + connect \Y $and$ls180.v:6017$1217_Y + end + attribute \src "ls180.v:6018.51-6018.92" + cell $and $and$ls180.v:6018$1218 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_cyc + connect \B \builder_slave_sel [5] + connect \Y $and$ls180.v:6018$1218_Y + end + attribute \src "ls180.v:6019.51-6019.92" + cell $and $and$ls180.v:6019$1219 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_cyc + connect \B \builder_slave_sel [6] + connect \Y $and$ls180.v:6019$1219_Y + end + attribute \src "ls180.v:6020.52-6020.93" + cell $and $and$ls180.v:6020$1220 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_cyc + connect \B \builder_slave_sel [7] + connect \Y $and$ls180.v:6020$1220_Y + end + attribute \src "ls180.v:6021.52-6021.93" + cell $and $and$ls180.v:6021$1221 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_cyc + connect \B \builder_slave_sel [8] + connect \Y $and$ls180.v:6021$1221_Y + end + attribute \src "ls180.v:6022.52-6022.93" + cell $and $and$ls180.v:6022$1222 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_cyc + connect \B \builder_slave_sel [9] + connect \Y $and$ls180.v:6022$1222_Y + end + attribute \src "ls180.v:6023.52-6023.94" + cell $and $and$ls180.v:6023$1223 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_cyc + connect \B \builder_slave_sel [10] + connect \Y $and$ls180.v:6023$1223_Y + end + attribute \src "ls180.v:6024.54-6024.96" + cell $and $and$ls180.v:6024$1224 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_cyc + connect \B \builder_slave_sel [11] + connect \Y $and$ls180.v:6024$1224_Y + end + attribute \src "ls180.v:6025.55-6025.97" + cell $and $and$ls180.v:6025$1225 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_cyc + connect \B \builder_slave_sel [12] + connect \Y $and$ls180.v:6025$1225_Y + end + attribute \src "ls180.v:6027.25-6027.64" + cell $and $and$ls180.v:6027$1238 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_stb + connect \B \builder_shared_cyc + connect \Y $and$ls180.v:6027$1238_Y + end + attribute \src "ls180.v:6027.24-6027.89" + cell $and $and$ls180.v:6027$1240 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6027$1238_Y + connect \B $not$ls180.v:6027$1239_Y + connect \Y $and$ls180.v:6027$1240_Y + end + attribute \src "ls180.v:6033.39-6033.100" + cell $and $and$ls180.v:6033$1254 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A { 32'00000000000000000000000000000000 \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] } + connect \B \main_libresocsim_ram_bus_dat_r + connect \Y $and$ls180.v:6033$1254_Y + end + attribute \src "ls180.v:6033.105-6033.165" + cell $and $and$ls180.v:6033$1255 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A { 32'00000000000000000000000000000000 \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] } + connect \B \main_interface0_ram_bus_dat_r + connect \Y $and$ls180.v:6033$1255_Y + end + attribute \src "ls180.v:6033.171-6033.231" + cell $and $and$ls180.v:6033$1257 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A { 32'00000000000000000000000000000000 \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] } + connect \B \main_interface1_ram_bus_dat_r + connect \Y $and$ls180.v:6033$1257_Y + end + attribute \src "ls180.v:6033.237-6033.297" + cell $and $and$ls180.v:6033$1259 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A { 32'00000000000000000000000000000000 \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] } + connect \B \main_interface2_ram_bus_dat_r + connect \Y $and$ls180.v:6033$1259_Y + end + attribute \src "ls180.v:6033.303-6033.363" + cell $and $and$ls180.v:6033$1261 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A { 32'00000000000000000000000000000000 \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] } + connect \B \main_interface3_ram_bus_dat_r + connect \Y $and$ls180.v:6033$1261_Y + end + attribute \src "ls180.v:6033.369-6033.441" + cell $and $and$ls180.v:6033$1263 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A { 32'00000000000000000000000000000000 \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] } + connect \B \main_interface0_converted_interface_dat_r + connect \Y $and$ls180.v:6033$1263_Y + end + attribute \src "ls180.v:6033.447-6033.519" + cell $and $and$ls180.v:6033$1265 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A { 32'00000000000000000000000000000000 \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] \builder_slave_sel_r [6] } + connect \B \main_interface1_converted_interface_dat_r + connect \Y $and$ls180.v:6033$1265_Y + end + attribute \src "ls180.v:6033.525-6033.598" + cell $and $and$ls180.v:6033$1267 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A { 32'00000000000000000000000000000000 \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] \builder_slave_sel_r [7] } + connect \B \main_libresocsim_libresoc_interface0_dat_r + connect \Y $and$ls180.v:6033$1267_Y + end + attribute \src "ls180.v:6033.604-6033.677" + cell $and $and$ls180.v:6033$1269 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A { 32'00000000000000000000000000000000 \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] \builder_slave_sel_r [8] } + connect \B \main_libresocsim_libresoc_interface1_dat_r + connect \Y $and$ls180.v:6033$1269_Y + end + attribute \src "ls180.v:6033.683-6033.756" + cell $and $and$ls180.v:6033$1271 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A { 32'00000000000000000000000000000000 \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] \builder_slave_sel_r [9] } + connect \B \main_libresocsim_libresoc_interface2_dat_r + connect \Y $and$ls180.v:6033$1271_Y + end + attribute \src "ls180.v:6033.762-6033.836" + cell $and $and$ls180.v:6033$1273 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A { 32'00000000000000000000000000000000 \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] \builder_slave_sel_r [10] } + connect \B \main_libresocsim_libresoc_interface3_dat_r + connect \Y $and$ls180.v:6033$1273_Y + end + attribute \src "ls180.v:6033.842-6033.918" + cell $and $and$ls180.v:6033$1275 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A { 32'00000000000000000000000000000000 \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] \builder_slave_sel_r [11] } + connect \B \main_socbushandler_converted_interface_dat_r + connect \Y $and$ls180.v:6033$1275_Y + end + attribute \src "ls180.v:6033.924-6033.1001" + cell $and $and$ls180.v:6033$1277 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A { 32'00000000000000000000000000000000 \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] \builder_slave_sel_r [12] } + connect \B \builder_libresocsim_converted_interface_dat_r + connect \Y $and$ls180.v:6033$1277_Y + end + attribute \src "ls180.v:6043.39-6043.92" + cell $and $and$ls180.v:6043$1281 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B \builder_interface0_bank_bus_we + connect \Y $and$ls180.v:6043$1281_Y + end + attribute \src "ls180.v:6043.38-6043.142" + cell $and $and$ls180.v:6043$1283 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6043$1281_Y + connect \B $eq$ls180.v:6043$1282_Y + connect \Y $and$ls180.v:6043$1283_Y + end + attribute \src "ls180.v:6044.39-6044.95" + cell $and $and$ls180.v:6044$1285 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B $not$ls180.v:6044$1284_Y + connect \Y $and$ls180.v:6044$1285_Y + end + attribute \src "ls180.v:6044.38-6044.145" + cell $and $and$ls180.v:6044$1287 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6044$1285_Y + connect \B $eq$ls180.v:6044$1286_Y + connect \Y $and$ls180.v:6044$1287_Y + end + attribute \src "ls180.v:6046.41-6046.94" + cell $and $and$ls180.v:6046$1288 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B \builder_interface0_bank_bus_we + connect \Y $and$ls180.v:6046$1288_Y + end + attribute \src "ls180.v:6046.40-6046.144" + cell $and $and$ls180.v:6046$1290 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6046$1288_Y + connect \B $eq$ls180.v:6046$1289_Y + connect \Y $and$ls180.v:6046$1290_Y + end + attribute \src "ls180.v:6047.41-6047.97" + cell $and $and$ls180.v:6047$1292 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B $not$ls180.v:6047$1291_Y + connect \Y $and$ls180.v:6047$1292_Y + end + attribute \src "ls180.v:6047.40-6047.147" + cell $and $and$ls180.v:6047$1294 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6047$1292_Y + connect \B $eq$ls180.v:6047$1293_Y + connect \Y $and$ls180.v:6047$1294_Y + end + attribute \src "ls180.v:6049.41-6049.94" + cell $and $and$ls180.v:6049$1295 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B \builder_interface0_bank_bus_we + connect \Y $and$ls180.v:6049$1295_Y + end + attribute \src "ls180.v:6049.40-6049.144" + cell $and $and$ls180.v:6049$1297 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6049$1295_Y + connect \B $eq$ls180.v:6049$1296_Y + connect \Y $and$ls180.v:6049$1297_Y + end + attribute \src "ls180.v:6050.41-6050.97" + cell $and $and$ls180.v:6050$1299 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B $not$ls180.v:6050$1298_Y + connect \Y $and$ls180.v:6050$1299_Y + end + attribute \src "ls180.v:6050.40-6050.147" + cell $and $and$ls180.v:6050$1301 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6050$1299_Y + connect \B $eq$ls180.v:6050$1300_Y + connect \Y $and$ls180.v:6050$1301_Y + end + attribute \src "ls180.v:6052.41-6052.94" + cell $and $and$ls180.v:6052$1302 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B \builder_interface0_bank_bus_we + connect \Y $and$ls180.v:6052$1302_Y + end + attribute \src "ls180.v:6052.40-6052.144" + cell $and $and$ls180.v:6052$1304 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6052$1302_Y + connect \B $eq$ls180.v:6052$1303_Y + connect \Y $and$ls180.v:6052$1304_Y + end + attribute \src "ls180.v:6053.41-6053.97" + cell $and $and$ls180.v:6053$1306 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B $not$ls180.v:6053$1305_Y + connect \Y $and$ls180.v:6053$1306_Y + end + attribute \src "ls180.v:6053.40-6053.147" + cell $and $and$ls180.v:6053$1308 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6053$1306_Y + connect \B $eq$ls180.v:6053$1307_Y + connect \Y $and$ls180.v:6053$1308_Y + end + attribute \src "ls180.v:6055.41-6055.94" + cell $and $and$ls180.v:6055$1309 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B \builder_interface0_bank_bus_we + connect \Y $and$ls180.v:6055$1309_Y + end + attribute \src "ls180.v:6055.40-6055.144" + cell $and $and$ls180.v:6055$1311 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6055$1309_Y + connect \B $eq$ls180.v:6055$1310_Y + connect \Y $and$ls180.v:6055$1311_Y + end + attribute \src "ls180.v:6056.41-6056.97" + cell $and $and$ls180.v:6056$1313 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B $not$ls180.v:6056$1312_Y + connect \Y $and$ls180.v:6056$1313_Y + end + attribute \src "ls180.v:6056.40-6056.147" + cell $and $and$ls180.v:6056$1315 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6056$1313_Y + connect \B $eq$ls180.v:6056$1314_Y + connect \Y $and$ls180.v:6056$1315_Y + end + attribute \src "ls180.v:6058.44-6058.97" + cell $and $and$ls180.v:6058$1316 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B \builder_interface0_bank_bus_we + connect \Y $and$ls180.v:6058$1316_Y + end + attribute \src "ls180.v:6058.43-6058.147" + cell $and $and$ls180.v:6058$1318 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6058$1316_Y + connect \B $eq$ls180.v:6058$1317_Y + connect \Y $and$ls180.v:6058$1318_Y + end + attribute \src "ls180.v:6059.44-6059.100" + cell $and $and$ls180.v:6059$1320 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B $not$ls180.v:6059$1319_Y + connect \Y $and$ls180.v:6059$1320_Y + end + attribute \src "ls180.v:6059.43-6059.150" + cell $and $and$ls180.v:6059$1322 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6059$1320_Y + connect \B $eq$ls180.v:6059$1321_Y + connect \Y $and$ls180.v:6059$1322_Y + end + attribute \src "ls180.v:6061.44-6061.97" + cell $and $and$ls180.v:6061$1323 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B \builder_interface0_bank_bus_we + connect \Y $and$ls180.v:6061$1323_Y + end + attribute \src "ls180.v:6061.43-6061.147" + cell $and $and$ls180.v:6061$1325 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6061$1323_Y + connect \B $eq$ls180.v:6061$1324_Y + connect \Y $and$ls180.v:6061$1325_Y + end + attribute \src "ls180.v:6062.44-6062.100" + cell $and $and$ls180.v:6062$1327 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B $not$ls180.v:6062$1326_Y + connect \Y $and$ls180.v:6062$1327_Y + end + attribute \src "ls180.v:6062.43-6062.150" + cell $and $and$ls180.v:6062$1329 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6062$1327_Y + connect \B $eq$ls180.v:6062$1328_Y + connect \Y $and$ls180.v:6062$1329_Y + end + attribute \src "ls180.v:6064.44-6064.97" + cell $and $and$ls180.v:6064$1330 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B \builder_interface0_bank_bus_we + connect \Y $and$ls180.v:6064$1330_Y + end + attribute \src "ls180.v:6064.43-6064.147" + cell $and $and$ls180.v:6064$1332 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6064$1330_Y + connect \B $eq$ls180.v:6064$1331_Y + connect \Y $and$ls180.v:6064$1332_Y + end + attribute \src "ls180.v:6065.44-6065.100" + cell $and $and$ls180.v:6065$1334 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B $not$ls180.v:6065$1333_Y + connect \Y $and$ls180.v:6065$1334_Y + end + attribute \src "ls180.v:6065.43-6065.150" + cell $and $and$ls180.v:6065$1336 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6065$1334_Y + connect \B $eq$ls180.v:6065$1335_Y + connect \Y $and$ls180.v:6065$1336_Y + end + attribute \src "ls180.v:6067.44-6067.97" + cell $and $and$ls180.v:6067$1337 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B \builder_interface0_bank_bus_we + connect \Y $and$ls180.v:6067$1337_Y + end + attribute \src "ls180.v:6067.43-6067.147" + cell $and $and$ls180.v:6067$1339 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6067$1337_Y + connect \B $eq$ls180.v:6067$1338_Y + connect \Y $and$ls180.v:6067$1339_Y + end + attribute \src "ls180.v:6068.44-6068.100" + cell $and $and$ls180.v:6068$1341 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B $not$ls180.v:6068$1340_Y + connect \Y $and$ls180.v:6068$1341_Y + end + attribute \src "ls180.v:6068.43-6068.150" + cell $and $and$ls180.v:6068$1343 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6068$1341_Y + connect \B $eq$ls180.v:6068$1342_Y + connect \Y $and$ls180.v:6068$1343_Y + end + attribute \src "ls180.v:6081.36-6081.89" + cell $and $and$ls180.v:6081$1345 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank1_sel + connect \B \builder_interface1_bank_bus_we + connect \Y $and$ls180.v:6081$1345_Y + end + attribute \src "ls180.v:6081.35-6081.139" + cell $and $and$ls180.v:6081$1347 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6081$1345_Y + connect \B $eq$ls180.v:6081$1346_Y + connect \Y $and$ls180.v:6081$1347_Y + end + attribute \src "ls180.v:6082.36-6082.92" + cell $and $and$ls180.v:6082$1349 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank1_sel + connect \B $not$ls180.v:6082$1348_Y + connect \Y $and$ls180.v:6082$1349_Y + end + attribute \src "ls180.v:6082.35-6082.142" + cell $and $and$ls180.v:6082$1351 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6082$1349_Y + connect \B $eq$ls180.v:6082$1350_Y + connect \Y $and$ls180.v:6082$1351_Y + end + attribute \src "ls180.v:6084.36-6084.89" + cell $and $and$ls180.v:6084$1352 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank1_sel + connect \B \builder_interface1_bank_bus_we + connect \Y $and$ls180.v:6084$1352_Y + end + attribute \src "ls180.v:6084.35-6084.139" + cell $and $and$ls180.v:6084$1354 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6084$1352_Y + connect \B $eq$ls180.v:6084$1353_Y + connect \Y $and$ls180.v:6084$1354_Y + end + attribute \src "ls180.v:6085.36-6085.92" + cell $and $and$ls180.v:6085$1356 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank1_sel + connect \B $not$ls180.v:6085$1355_Y + connect \Y $and$ls180.v:6085$1356_Y + end + attribute \src "ls180.v:6085.35-6085.142" + cell $and $and$ls180.v:6085$1358 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6085$1356_Y + connect \B $eq$ls180.v:6085$1357_Y + connect \Y $and$ls180.v:6085$1358_Y + end + attribute \src "ls180.v:6087.36-6087.89" + cell $and $and$ls180.v:6087$1359 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank1_sel + connect \B \builder_interface1_bank_bus_we + connect \Y $and$ls180.v:6087$1359_Y + end + attribute \src "ls180.v:6087.35-6087.139" + cell $and $and$ls180.v:6087$1361 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6087$1359_Y + connect \B $eq$ls180.v:6087$1360_Y + connect \Y $and$ls180.v:6087$1361_Y + end + attribute \src "ls180.v:6088.36-6088.92" + cell $and $and$ls180.v:6088$1363 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank1_sel + connect \B $not$ls180.v:6088$1362_Y + connect \Y $and$ls180.v:6088$1363_Y + end + attribute \src "ls180.v:6088.35-6088.142" + cell $and $and$ls180.v:6088$1365 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6088$1363_Y + connect \B $eq$ls180.v:6088$1364_Y + connect \Y $and$ls180.v:6088$1365_Y + end + attribute \src "ls180.v:6090.36-6090.89" + cell $and $and$ls180.v:6090$1366 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank1_sel + connect \B \builder_interface1_bank_bus_we + connect \Y $and$ls180.v:6090$1366_Y + end + attribute \src "ls180.v:6090.35-6090.139" + cell $and $and$ls180.v:6090$1368 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6090$1366_Y + connect \B $eq$ls180.v:6090$1367_Y + connect \Y $and$ls180.v:6090$1368_Y + end + attribute \src "ls180.v:6091.36-6091.92" + cell $and $and$ls180.v:6091$1370 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank1_sel + connect \B $not$ls180.v:6091$1369_Y + connect \Y $and$ls180.v:6091$1370_Y + end + attribute \src "ls180.v:6091.35-6091.142" + cell $and $and$ls180.v:6091$1372 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6091$1370_Y + connect \B $eq$ls180.v:6091$1371_Y + connect \Y $and$ls180.v:6091$1372_Y + end + attribute \src "ls180.v:6093.37-6093.90" + cell $and $and$ls180.v:6093$1373 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank1_sel + connect \B \builder_interface1_bank_bus_we + connect \Y $and$ls180.v:6093$1373_Y + end + attribute \src "ls180.v:6093.36-6093.140" + cell $and $and$ls180.v:6093$1375 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6093$1373_Y + connect \B $eq$ls180.v:6093$1374_Y + connect \Y $and$ls180.v:6093$1375_Y + end + attribute \src "ls180.v:6094.37-6094.93" + cell $and $and$ls180.v:6094$1377 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank1_sel + connect \B $not$ls180.v:6094$1376_Y + connect \Y $and$ls180.v:6094$1377_Y + end + attribute \src "ls180.v:6094.36-6094.143" + cell $and $and$ls180.v:6094$1379 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6094$1377_Y + connect \B $eq$ls180.v:6094$1378_Y + connect \Y $and$ls180.v:6094$1379_Y + end + attribute \src "ls180.v:6096.37-6096.90" + cell $and $and$ls180.v:6096$1380 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank1_sel + connect \B \builder_interface1_bank_bus_we + connect \Y $and$ls180.v:6096$1380_Y + end + attribute \src "ls180.v:6096.36-6096.140" + cell $and $and$ls180.v:6096$1382 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6096$1380_Y + connect \B $eq$ls180.v:6096$1381_Y + connect \Y $and$ls180.v:6096$1382_Y + end + attribute \src "ls180.v:6097.37-6097.93" + cell $and $and$ls180.v:6097$1384 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank1_sel + connect \B $not$ls180.v:6097$1383_Y + connect \Y $and$ls180.v:6097$1384_Y + end + attribute \src "ls180.v:6097.36-6097.143" + cell $and $and$ls180.v:6097$1386 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6097$1384_Y + connect \B $eq$ls180.v:6097$1385_Y + connect \Y $and$ls180.v:6097$1386_Y + end + attribute \src "ls180.v:6107.35-6107.88" + cell $and $and$ls180.v:6107$1388 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank2_sel + connect \B \builder_interface2_bank_bus_we + connect \Y $and$ls180.v:6107$1388_Y + end + attribute \src "ls180.v:6107.34-6107.136" + cell $and $and$ls180.v:6107$1390 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6107$1388_Y + connect \B $eq$ls180.v:6107$1389_Y + connect \Y $and$ls180.v:6107$1390_Y + end + attribute \src "ls180.v:6108.35-6108.91" + cell $and $and$ls180.v:6108$1392 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank2_sel + connect \B $not$ls180.v:6108$1391_Y + connect \Y $and$ls180.v:6108$1392_Y + end + attribute \src "ls180.v:6108.34-6108.139" + cell $and $and$ls180.v:6108$1394 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6108$1392_Y + connect \B $eq$ls180.v:6108$1393_Y + connect \Y $and$ls180.v:6108$1394_Y + end + attribute \src "ls180.v:6110.34-6110.87" + cell $and $and$ls180.v:6110$1395 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank2_sel + connect \B \builder_interface2_bank_bus_we + connect \Y $and$ls180.v:6110$1395_Y + end + attribute \src "ls180.v:6110.33-6110.135" + cell $and $and$ls180.v:6110$1397 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6110$1395_Y + connect \B $eq$ls180.v:6110$1396_Y + connect \Y $and$ls180.v:6110$1397_Y + end + attribute \src "ls180.v:6111.34-6111.90" + cell $and $and$ls180.v:6111$1399 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank2_sel + connect \B $not$ls180.v:6111$1398_Y + connect \Y $and$ls180.v:6111$1399_Y + end + attribute \src "ls180.v:6111.33-6111.138" + cell $and $and$ls180.v:6111$1401 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6111$1399_Y + connect \B $eq$ls180.v:6111$1400_Y + connect \Y $and$ls180.v:6111$1401_Y + end + attribute \src "ls180.v:6121.40-6121.93" + cell $and $and$ls180.v:6121$1403 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank3_sel + connect \B \builder_interface3_bank_bus_we + connect \Y $and$ls180.v:6121$1403_Y + end + attribute \src "ls180.v:6121.39-6121.143" + cell $and $and$ls180.v:6121$1405 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6121$1403_Y + connect \B $eq$ls180.v:6121$1404_Y + connect \Y $and$ls180.v:6121$1405_Y + end + attribute \src "ls180.v:6122.40-6122.96" + cell $and $and$ls180.v:6122$1407 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank3_sel + connect \B $not$ls180.v:6122$1406_Y + connect \Y $and$ls180.v:6122$1407_Y + end + attribute \src "ls180.v:6122.39-6122.146" + cell $and $and$ls180.v:6122$1409 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6122$1407_Y + connect \B $eq$ls180.v:6122$1408_Y + connect \Y $and$ls180.v:6122$1409_Y + end + attribute \src "ls180.v:6124.39-6124.92" + cell $and $and$ls180.v:6124$1410 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank3_sel + connect \B \builder_interface3_bank_bus_we + connect \Y $and$ls180.v:6124$1410_Y + end + attribute \src "ls180.v:6124.38-6124.142" + cell $and $and$ls180.v:6124$1412 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6124$1410_Y + connect \B $eq$ls180.v:6124$1411_Y + connect \Y $and$ls180.v:6124$1412_Y + end + attribute \src "ls180.v:6125.39-6125.95" + cell $and $and$ls180.v:6125$1414 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank3_sel + connect \B $not$ls180.v:6125$1413_Y + connect \Y $and$ls180.v:6125$1414_Y + end + attribute \src "ls180.v:6125.38-6125.145" + cell $and $and$ls180.v:6125$1416 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6125$1414_Y + connect \B $eq$ls180.v:6125$1415_Y + connect \Y $and$ls180.v:6125$1416_Y + end + attribute \src "ls180.v:6127.39-6127.92" + cell $and $and$ls180.v:6127$1417 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank3_sel + connect \B \builder_interface3_bank_bus_we + connect \Y $and$ls180.v:6127$1417_Y + end + attribute \src "ls180.v:6127.38-6127.142" + cell $and $and$ls180.v:6127$1419 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6127$1417_Y + connect \B $eq$ls180.v:6127$1418_Y + connect \Y $and$ls180.v:6127$1419_Y + end + attribute \src "ls180.v:6128.39-6128.95" + cell $and $and$ls180.v:6128$1421 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank3_sel + connect \B $not$ls180.v:6128$1420_Y + connect \Y $and$ls180.v:6128$1421_Y + end + attribute \src "ls180.v:6128.38-6128.145" + cell $and $and$ls180.v:6128$1423 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6128$1421_Y + connect \B $eq$ls180.v:6128$1422_Y + connect \Y $and$ls180.v:6128$1423_Y + end + attribute \src "ls180.v:6130.39-6130.92" + cell $and $and$ls180.v:6130$1424 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank3_sel + connect \B \builder_interface3_bank_bus_we + connect \Y $and$ls180.v:6130$1424_Y + end + attribute \src "ls180.v:6130.38-6130.142" + cell $and $and$ls180.v:6130$1426 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6130$1424_Y + connect \B $eq$ls180.v:6130$1425_Y + connect \Y $and$ls180.v:6130$1426_Y + end + attribute \src "ls180.v:6131.39-6131.95" + cell $and $and$ls180.v:6131$1428 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank3_sel + connect \B $not$ls180.v:6131$1427_Y + connect \Y $and$ls180.v:6131$1428_Y + end + attribute \src "ls180.v:6131.38-6131.145" + cell $and $and$ls180.v:6131$1430 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6131$1428_Y + connect \B $eq$ls180.v:6131$1429_Y + connect \Y $and$ls180.v:6131$1430_Y + end + attribute \src "ls180.v:6133.39-6133.92" + cell $and $and$ls180.v:6133$1431 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank3_sel + connect \B \builder_interface3_bank_bus_we + connect \Y $and$ls180.v:6133$1431_Y + end + attribute \src "ls180.v:6133.38-6133.142" + cell $and $and$ls180.v:6133$1433 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6133$1431_Y + connect \B $eq$ls180.v:6133$1432_Y + connect \Y $and$ls180.v:6133$1433_Y + end + attribute \src "ls180.v:6134.39-6134.95" + cell $and $and$ls180.v:6134$1435 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank3_sel + connect \B $not$ls180.v:6134$1434_Y + connect \Y $and$ls180.v:6134$1435_Y + end + attribute \src "ls180.v:6134.38-6134.145" + cell $and $and$ls180.v:6134$1437 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6134$1435_Y + connect \B $eq$ls180.v:6134$1436_Y + connect \Y $and$ls180.v:6134$1437_Y + end + attribute \src "ls180.v:6136.40-6136.93" + cell $and $and$ls180.v:6136$1438 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank3_sel + connect \B \builder_interface3_bank_bus_we + connect \Y $and$ls180.v:6136$1438_Y + end + attribute \src "ls180.v:6136.39-6136.143" + cell $and $and$ls180.v:6136$1440 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6136$1438_Y + connect \B $eq$ls180.v:6136$1439_Y + connect \Y $and$ls180.v:6136$1440_Y + end + attribute \src "ls180.v:6137.40-6137.96" + cell $and $and$ls180.v:6137$1442 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank3_sel + connect \B $not$ls180.v:6137$1441_Y + connect \Y $and$ls180.v:6137$1442_Y + end + attribute \src "ls180.v:6137.39-6137.146" + cell $and $and$ls180.v:6137$1444 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6137$1442_Y + connect \B $eq$ls180.v:6137$1443_Y + connect \Y $and$ls180.v:6137$1444_Y + end + attribute \src "ls180.v:6139.40-6139.93" + cell $and $and$ls180.v:6139$1445 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank3_sel + connect \B \builder_interface3_bank_bus_we + connect \Y $and$ls180.v:6139$1445_Y + end + attribute \src "ls180.v:6139.39-6139.143" + cell $and $and$ls180.v:6139$1447 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6139$1445_Y + connect \B $eq$ls180.v:6139$1446_Y + connect \Y $and$ls180.v:6139$1447_Y + end + attribute \src "ls180.v:6140.40-6140.96" + cell $and $and$ls180.v:6140$1449 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank3_sel + connect \B $not$ls180.v:6140$1448_Y + connect \Y $and$ls180.v:6140$1449_Y + end + attribute \src "ls180.v:6140.39-6140.146" + cell $and $and$ls180.v:6140$1451 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6140$1449_Y + connect \B $eq$ls180.v:6140$1450_Y + connect \Y $and$ls180.v:6140$1451_Y + end + attribute \src "ls180.v:6142.40-6142.93" + cell $and $and$ls180.v:6142$1452 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank3_sel + connect \B \builder_interface3_bank_bus_we + connect \Y $and$ls180.v:6142$1452_Y + end + attribute \src "ls180.v:6142.39-6142.143" + cell $and $and$ls180.v:6142$1454 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6142$1452_Y + connect \B $eq$ls180.v:6142$1453_Y + connect \Y $and$ls180.v:6142$1454_Y + end + attribute \src "ls180.v:6143.40-6143.96" + cell $and $and$ls180.v:6143$1456 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank3_sel + connect \B $not$ls180.v:6143$1455_Y + connect \Y $and$ls180.v:6143$1456_Y + end + attribute \src "ls180.v:6143.39-6143.146" + cell $and $and$ls180.v:6143$1458 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6143$1456_Y + connect \B $eq$ls180.v:6143$1457_Y + connect \Y $and$ls180.v:6143$1458_Y + end + attribute \src "ls180.v:6145.40-6145.93" + cell $and $and$ls180.v:6145$1459 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank3_sel + connect \B \builder_interface3_bank_bus_we + connect \Y $and$ls180.v:6145$1459_Y + end + attribute \src "ls180.v:6145.39-6145.143" + cell $and $and$ls180.v:6145$1461 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6145$1459_Y + connect \B $eq$ls180.v:6145$1460_Y + connect \Y $and$ls180.v:6145$1461_Y + end + attribute \src "ls180.v:6146.40-6146.96" + cell $and $and$ls180.v:6146$1463 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank3_sel + connect \B $not$ls180.v:6146$1462_Y + connect \Y $and$ls180.v:6146$1463_Y + end + attribute \src "ls180.v:6146.39-6146.146" + cell $and $and$ls180.v:6146$1465 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6146$1463_Y + connect \B $eq$ls180.v:6146$1464_Y + connect \Y $and$ls180.v:6146$1465_Y + end + attribute \src "ls180.v:6158.40-6158.93" + cell $and $and$ls180.v:6158$1467 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B \builder_interface4_bank_bus_we + connect \Y $and$ls180.v:6158$1467_Y + end + attribute \src "ls180.v:6158.39-6158.143" + cell $and $and$ls180.v:6158$1469 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6158$1467_Y + connect \B $eq$ls180.v:6158$1468_Y + connect \Y $and$ls180.v:6158$1469_Y + end + attribute \src "ls180.v:6159.40-6159.96" + cell $and $and$ls180.v:6159$1471 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B $not$ls180.v:6159$1470_Y + connect \Y $and$ls180.v:6159$1471_Y + end + attribute \src "ls180.v:6159.39-6159.146" + cell $and $and$ls180.v:6159$1473 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6159$1471_Y + connect \B $eq$ls180.v:6159$1472_Y + connect \Y $and$ls180.v:6159$1473_Y + end + attribute \src "ls180.v:6161.39-6161.92" + cell $and $and$ls180.v:6161$1474 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B \builder_interface4_bank_bus_we + connect \Y $and$ls180.v:6161$1474_Y + end + attribute \src "ls180.v:6161.38-6161.142" + cell $and $and$ls180.v:6161$1476 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6161$1474_Y + connect \B $eq$ls180.v:6161$1475_Y + connect \Y $and$ls180.v:6161$1476_Y + end + attribute \src "ls180.v:6162.39-6162.95" + cell $and $and$ls180.v:6162$1478 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B $not$ls180.v:6162$1477_Y + connect \Y $and$ls180.v:6162$1478_Y + end + attribute \src "ls180.v:6162.38-6162.145" + cell $and $and$ls180.v:6162$1480 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6162$1478_Y + connect \B $eq$ls180.v:6162$1479_Y + connect \Y $and$ls180.v:6162$1480_Y + end + attribute \src "ls180.v:6164.39-6164.92" + cell $and $and$ls180.v:6164$1481 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B \builder_interface4_bank_bus_we + connect \Y $and$ls180.v:6164$1481_Y + end + attribute \src "ls180.v:6164.38-6164.142" + cell $and $and$ls180.v:6164$1483 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6164$1481_Y + connect \B $eq$ls180.v:6164$1482_Y + connect \Y $and$ls180.v:6164$1483_Y + end + attribute \src "ls180.v:6165.39-6165.95" + cell $and $and$ls180.v:6165$1485 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B $not$ls180.v:6165$1484_Y + connect \Y $and$ls180.v:6165$1485_Y + end + attribute \src "ls180.v:6165.38-6165.145" + cell $and $and$ls180.v:6165$1487 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6165$1485_Y + connect \B $eq$ls180.v:6165$1486_Y + connect \Y $and$ls180.v:6165$1487_Y + end + attribute \src "ls180.v:6167.39-6167.92" + cell $and $and$ls180.v:6167$1488 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B \builder_interface4_bank_bus_we + connect \Y $and$ls180.v:6167$1488_Y + end + attribute \src "ls180.v:6167.38-6167.142" + cell $and $and$ls180.v:6167$1490 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6167$1488_Y + connect \B $eq$ls180.v:6167$1489_Y + connect \Y $and$ls180.v:6167$1490_Y + end + attribute \src "ls180.v:6168.39-6168.95" + cell $and $and$ls180.v:6168$1492 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B $not$ls180.v:6168$1491_Y + connect \Y $and$ls180.v:6168$1492_Y + end + attribute \src "ls180.v:6168.38-6168.145" + cell $and $and$ls180.v:6168$1494 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6168$1492_Y + connect \B $eq$ls180.v:6168$1493_Y + connect \Y $and$ls180.v:6168$1494_Y + end + attribute \src "ls180.v:6170.39-6170.92" + cell $and $and$ls180.v:6170$1495 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B \builder_interface4_bank_bus_we + connect \Y $and$ls180.v:6170$1495_Y + end + attribute \src "ls180.v:6170.38-6170.142" + cell $and $and$ls180.v:6170$1497 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6170$1495_Y + connect \B $eq$ls180.v:6170$1496_Y + connect \Y $and$ls180.v:6170$1497_Y + end + attribute \src "ls180.v:6171.39-6171.95" + cell $and $and$ls180.v:6171$1499 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B $not$ls180.v:6171$1498_Y + connect \Y $and$ls180.v:6171$1499_Y + end + attribute \src "ls180.v:6171.38-6171.145" + cell $and $and$ls180.v:6171$1501 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6171$1499_Y + connect \B $eq$ls180.v:6171$1500_Y + connect \Y $and$ls180.v:6171$1501_Y + end + attribute \src "ls180.v:6173.40-6173.93" + cell $and $and$ls180.v:6173$1502 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B \builder_interface4_bank_bus_we + connect \Y $and$ls180.v:6173$1502_Y + end + attribute \src "ls180.v:6173.39-6173.143" + cell $and $and$ls180.v:6173$1504 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6173$1502_Y + connect \B $eq$ls180.v:6173$1503_Y + connect \Y $and$ls180.v:6173$1504_Y + end + attribute \src "ls180.v:6174.40-6174.96" + cell $and $and$ls180.v:6174$1506 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B $not$ls180.v:6174$1505_Y + connect \Y $and$ls180.v:6174$1506_Y + end + attribute \src "ls180.v:6174.39-6174.146" + cell $and $and$ls180.v:6174$1508 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6174$1506_Y + connect \B $eq$ls180.v:6174$1507_Y + connect \Y $and$ls180.v:6174$1508_Y + end + attribute \src "ls180.v:6176.40-6176.93" + cell $and $and$ls180.v:6176$1509 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B \builder_interface4_bank_bus_we + connect \Y $and$ls180.v:6176$1509_Y + end + attribute \src "ls180.v:6176.39-6176.143" + cell $and $and$ls180.v:6176$1511 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6176$1509_Y + connect \B $eq$ls180.v:6176$1510_Y + connect \Y $and$ls180.v:6176$1511_Y + end + attribute \src "ls180.v:6177.40-6177.96" + cell $and $and$ls180.v:6177$1513 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B $not$ls180.v:6177$1512_Y + connect \Y $and$ls180.v:6177$1513_Y + end + attribute \src "ls180.v:6177.39-6177.146" + cell $and $and$ls180.v:6177$1515 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6177$1513_Y + connect \B $eq$ls180.v:6177$1514_Y + connect \Y $and$ls180.v:6177$1515_Y + end + attribute \src "ls180.v:6179.40-6179.93" + cell $and $and$ls180.v:6179$1516 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B \builder_interface4_bank_bus_we + connect \Y $and$ls180.v:6179$1516_Y + end + attribute \src "ls180.v:6179.39-6179.143" + cell $and $and$ls180.v:6179$1518 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6179$1516_Y + connect \B $eq$ls180.v:6179$1517_Y + connect \Y $and$ls180.v:6179$1518_Y + end + attribute \src "ls180.v:6180.40-6180.96" + cell $and $and$ls180.v:6180$1520 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B $not$ls180.v:6180$1519_Y + connect \Y $and$ls180.v:6180$1520_Y + end + attribute \src "ls180.v:6180.39-6180.146" + cell $and $and$ls180.v:6180$1522 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6180$1520_Y + connect \B $eq$ls180.v:6180$1521_Y + connect \Y $and$ls180.v:6180$1522_Y + end + attribute \src "ls180.v:6182.40-6182.93" + cell $and $and$ls180.v:6182$1523 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B \builder_interface4_bank_bus_we + connect \Y $and$ls180.v:6182$1523_Y + end + attribute \src "ls180.v:6182.39-6182.143" + cell $and $and$ls180.v:6182$1525 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6182$1523_Y + connect \B $eq$ls180.v:6182$1524_Y + connect \Y $and$ls180.v:6182$1525_Y + end + attribute \src "ls180.v:6183.40-6183.96" + cell $and $and$ls180.v:6183$1527 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank4_sel + connect \B $not$ls180.v:6183$1526_Y + connect \Y $and$ls180.v:6183$1527_Y + end + attribute \src "ls180.v:6183.39-6183.146" + cell $and $and$ls180.v:6183$1529 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6183$1527_Y + connect \B $eq$ls180.v:6183$1528_Y + connect \Y $and$ls180.v:6183$1529_Y + end + attribute \src "ls180.v:6195.42-6195.95" + cell $and $and$ls180.v:6195$1531 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:6195$1531_Y + end + attribute \src "ls180.v:6195.41-6195.145" + cell $and $and$ls180.v:6195$1533 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6195$1531_Y + connect \B $eq$ls180.v:6195$1532_Y + connect \Y $and$ls180.v:6195$1533_Y + end + attribute \src "ls180.v:6196.42-6196.98" + cell $and $and$ls180.v:6196$1535 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:6196$1534_Y + connect \Y $and$ls180.v:6196$1535_Y + end + attribute \src "ls180.v:6196.41-6196.148" + cell $and $and$ls180.v:6196$1537 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6196$1535_Y + connect \B $eq$ls180.v:6196$1536_Y + connect \Y $and$ls180.v:6196$1537_Y + end + attribute \src "ls180.v:6198.42-6198.95" + cell $and $and$ls180.v:6198$1538 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:6198$1538_Y + end + attribute \src "ls180.v:6198.41-6198.145" + cell $and $and$ls180.v:6198$1540 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6198$1538_Y + connect \B $eq$ls180.v:6198$1539_Y + connect \Y $and$ls180.v:6198$1540_Y + end + attribute \src "ls180.v:6199.42-6199.98" + cell $and $and$ls180.v:6199$1542 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:6199$1541_Y + connect \Y $and$ls180.v:6199$1542_Y + end + attribute \src "ls180.v:6199.41-6199.148" + cell $and $and$ls180.v:6199$1544 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6199$1542_Y + connect \B $eq$ls180.v:6199$1543_Y + connect \Y $and$ls180.v:6199$1544_Y + end + attribute \src "ls180.v:6201.42-6201.95" + cell $and $and$ls180.v:6201$1545 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:6201$1545_Y + end + attribute \src "ls180.v:6201.41-6201.145" + cell $and $and$ls180.v:6201$1547 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6201$1545_Y + connect \B $eq$ls180.v:6201$1546_Y + connect \Y $and$ls180.v:6201$1547_Y + end + attribute \src "ls180.v:6202.42-6202.98" + cell $and $and$ls180.v:6202$1549 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:6202$1548_Y + connect \Y $and$ls180.v:6202$1549_Y + end + attribute \src "ls180.v:6202.41-6202.148" + cell $and $and$ls180.v:6202$1551 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6202$1549_Y + connect \B $eq$ls180.v:6202$1550_Y + connect \Y $and$ls180.v:6202$1551_Y + end + attribute \src "ls180.v:6204.42-6204.95" + cell $and $and$ls180.v:6204$1552 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:6204$1552_Y + end + attribute \src "ls180.v:6204.41-6204.145" + cell $and $and$ls180.v:6204$1554 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6204$1552_Y + connect \B $eq$ls180.v:6204$1553_Y + connect \Y $and$ls180.v:6204$1554_Y + end + attribute \src "ls180.v:6205.42-6205.98" + cell $and $and$ls180.v:6205$1556 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:6205$1555_Y + connect \Y $and$ls180.v:6205$1556_Y + end + attribute \src "ls180.v:6205.41-6205.148" + cell $and $and$ls180.v:6205$1558 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6205$1556_Y + connect \B $eq$ls180.v:6205$1557_Y + connect \Y $and$ls180.v:6205$1558_Y + end + attribute \src "ls180.v:6207.42-6207.95" + cell $and $and$ls180.v:6207$1559 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:6207$1559_Y + end + attribute \src "ls180.v:6207.41-6207.145" + cell $and $and$ls180.v:6207$1561 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6207$1559_Y + connect \B $eq$ls180.v:6207$1560_Y + connect \Y $and$ls180.v:6207$1561_Y + end + attribute \src "ls180.v:6208.42-6208.98" + cell $and $and$ls180.v:6208$1563 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:6208$1562_Y + connect \Y $and$ls180.v:6208$1563_Y + end + attribute \src "ls180.v:6208.41-6208.148" + cell $and $and$ls180.v:6208$1565 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6208$1563_Y + connect \B $eq$ls180.v:6208$1564_Y + connect \Y $and$ls180.v:6208$1565_Y + end + attribute \src "ls180.v:6210.42-6210.95" + cell $and $and$ls180.v:6210$1566 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:6210$1566_Y + end + attribute \src "ls180.v:6210.41-6210.145" + cell $and $and$ls180.v:6210$1568 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6210$1566_Y + connect \B $eq$ls180.v:6210$1567_Y + connect \Y $and$ls180.v:6210$1568_Y + end + attribute \src "ls180.v:6211.42-6211.98" + cell $and $and$ls180.v:6211$1570 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:6211$1569_Y + connect \Y $and$ls180.v:6211$1570_Y + end + attribute \src "ls180.v:6211.41-6211.148" + cell $and $and$ls180.v:6211$1572 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6211$1570_Y + connect \B $eq$ls180.v:6211$1571_Y + connect \Y $and$ls180.v:6211$1572_Y + end + attribute \src "ls180.v:6213.42-6213.95" + cell $and $and$ls180.v:6213$1573 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:6213$1573_Y + end + attribute \src "ls180.v:6213.41-6213.145" + cell $and $and$ls180.v:6213$1575 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6213$1573_Y + connect \B $eq$ls180.v:6213$1574_Y + connect \Y $and$ls180.v:6213$1575_Y + end + attribute \src "ls180.v:6214.42-6214.98" + cell $and $and$ls180.v:6214$1577 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:6214$1576_Y + connect \Y $and$ls180.v:6214$1577_Y + end + attribute \src "ls180.v:6214.41-6214.148" + cell $and $and$ls180.v:6214$1579 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6214$1577_Y + connect \B $eq$ls180.v:6214$1578_Y + connect \Y $and$ls180.v:6214$1579_Y + end + attribute \src "ls180.v:6216.42-6216.95" + cell $and $and$ls180.v:6216$1580 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:6216$1580_Y + end + attribute \src "ls180.v:6216.41-6216.145" + cell $and $and$ls180.v:6216$1582 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6216$1580_Y + connect \B $eq$ls180.v:6216$1581_Y + connect \Y $and$ls180.v:6216$1582_Y + end + attribute \src "ls180.v:6217.42-6217.98" + cell $and $and$ls180.v:6217$1584 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:6217$1583_Y + connect \Y $and$ls180.v:6217$1584_Y + end + attribute \src "ls180.v:6217.41-6217.148" + cell $and $and$ls180.v:6217$1586 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6217$1584_Y + connect \B $eq$ls180.v:6217$1585_Y + connect \Y $and$ls180.v:6217$1586_Y + end + attribute \src "ls180.v:6219.44-6219.97" + cell $and $and$ls180.v:6219$1587 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:6219$1587_Y + end + attribute \src "ls180.v:6219.43-6219.147" + cell $and $and$ls180.v:6219$1589 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6219$1587_Y + connect \B $eq$ls180.v:6219$1588_Y + connect \Y $and$ls180.v:6219$1589_Y + end + attribute \src "ls180.v:6220.44-6220.100" + cell $and $and$ls180.v:6220$1591 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:6220$1590_Y + connect \Y $and$ls180.v:6220$1591_Y + end + attribute \src "ls180.v:6220.43-6220.150" + cell $and $and$ls180.v:6220$1593 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6220$1591_Y + connect \B $eq$ls180.v:6220$1592_Y + connect \Y $and$ls180.v:6220$1593_Y + end + attribute \src "ls180.v:6222.44-6222.97" + cell $and $and$ls180.v:6222$1594 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:6222$1594_Y + end + attribute \src "ls180.v:6222.43-6222.147" + cell $and $and$ls180.v:6222$1596 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6222$1594_Y + connect \B $eq$ls180.v:6222$1595_Y + connect \Y $and$ls180.v:6222$1596_Y + end + attribute \src "ls180.v:6223.44-6223.100" + cell $and $and$ls180.v:6223$1598 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:6223$1597_Y + connect \Y $and$ls180.v:6223$1598_Y + end + attribute \src "ls180.v:6223.43-6223.150" + cell $and $and$ls180.v:6223$1600 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6223$1598_Y + connect \B $eq$ls180.v:6223$1599_Y + connect \Y $and$ls180.v:6223$1600_Y + end + attribute \src "ls180.v:6225.44-6225.97" + cell $and $and$ls180.v:6225$1601 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:6225$1601_Y + end + attribute \src "ls180.v:6225.43-6225.148" + cell $and $and$ls180.v:6225$1603 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6225$1601_Y + connect \B $eq$ls180.v:6225$1602_Y + connect \Y $and$ls180.v:6225$1603_Y + end + attribute \src "ls180.v:6226.44-6226.100" + cell $and $and$ls180.v:6226$1605 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:6226$1604_Y + connect \Y $and$ls180.v:6226$1605_Y + end + attribute \src "ls180.v:6226.43-6226.151" + cell $and $and$ls180.v:6226$1607 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6226$1605_Y + connect \B $eq$ls180.v:6226$1606_Y + connect \Y $and$ls180.v:6226$1607_Y + end + attribute \src "ls180.v:6228.44-6228.97" + cell $and $and$ls180.v:6228$1608 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:6228$1608_Y + end + attribute \src "ls180.v:6228.43-6228.148" + cell $and $and$ls180.v:6228$1610 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6228$1608_Y + connect \B $eq$ls180.v:6228$1609_Y + connect \Y $and$ls180.v:6228$1610_Y + end + attribute \src "ls180.v:6229.44-6229.100" + cell $and $and$ls180.v:6229$1612 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:6229$1611_Y + connect \Y $and$ls180.v:6229$1612_Y + end + attribute \src "ls180.v:6229.43-6229.151" + cell $and $and$ls180.v:6229$1614 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6229$1612_Y + connect \B $eq$ls180.v:6229$1613_Y + connect \Y $and$ls180.v:6229$1614_Y + end + attribute \src "ls180.v:6231.44-6231.97" + cell $and $and$ls180.v:6231$1615 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:6231$1615_Y + end + attribute \src "ls180.v:6231.43-6231.148" + cell $and $and$ls180.v:6231$1617 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6231$1615_Y + connect \B $eq$ls180.v:6231$1616_Y + connect \Y $and$ls180.v:6231$1617_Y + end + attribute \src "ls180.v:6232.44-6232.100" + cell $and $and$ls180.v:6232$1619 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:6232$1618_Y + connect \Y $and$ls180.v:6232$1619_Y + end + attribute \src "ls180.v:6232.43-6232.151" + cell $and $and$ls180.v:6232$1621 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6232$1619_Y + connect \B $eq$ls180.v:6232$1620_Y + connect \Y $and$ls180.v:6232$1621_Y + end + attribute \src "ls180.v:6234.41-6234.94" + cell $and $and$ls180.v:6234$1622 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:6234$1622_Y + end + attribute \src "ls180.v:6234.40-6234.145" + cell $and $and$ls180.v:6234$1624 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6234$1622_Y + connect \B $eq$ls180.v:6234$1623_Y + connect \Y $and$ls180.v:6234$1624_Y + end + attribute \src "ls180.v:6235.41-6235.97" + cell $and $and$ls180.v:6235$1626 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:6235$1625_Y + connect \Y $and$ls180.v:6235$1626_Y + end + attribute \src "ls180.v:6235.40-6235.148" + cell $and $and$ls180.v:6235$1628 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6235$1626_Y + connect \B $eq$ls180.v:6235$1627_Y + connect \Y $and$ls180.v:6235$1628_Y + end + attribute \src "ls180.v:6237.42-6237.95" + cell $and $and$ls180.v:6237$1629 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B \builder_interface5_bank_bus_we + connect \Y $and$ls180.v:6237$1629_Y + end + attribute \src "ls180.v:6237.41-6237.146" + cell $and $and$ls180.v:6237$1631 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6237$1629_Y + connect \B $eq$ls180.v:6237$1630_Y + connect \Y $and$ls180.v:6237$1631_Y + end + attribute \src "ls180.v:6238.42-6238.98" + cell $and $and$ls180.v:6238$1633 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank5_sel + connect \B $not$ls180.v:6238$1632_Y + connect \Y $and$ls180.v:6238$1633_Y + end + attribute \src "ls180.v:6238.41-6238.149" + cell $and $and$ls180.v:6238$1635 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6238$1633_Y + connect \B $eq$ls180.v:6238$1634_Y + connect \Y $and$ls180.v:6238$1635_Y + end + attribute \src "ls180.v:6257.46-6257.99" + cell $and $and$ls180.v:6257$1637 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6257$1637_Y + end + attribute \src "ls180.v:6257.45-6257.149" + cell $and $and$ls180.v:6257$1639 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6257$1637_Y + connect \B $eq$ls180.v:6257$1638_Y + connect \Y $and$ls180.v:6257$1639_Y + end + attribute \src "ls180.v:6258.46-6258.102" + cell $and $and$ls180.v:6258$1641 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6258$1640_Y + connect \Y $and$ls180.v:6258$1641_Y + end + attribute \src "ls180.v:6258.45-6258.152" + cell $and $and$ls180.v:6258$1643 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6258$1641_Y + connect \B $eq$ls180.v:6258$1642_Y + connect \Y $and$ls180.v:6258$1643_Y + end + attribute \src "ls180.v:6260.46-6260.99" + cell $and $and$ls180.v:6260$1644 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6260$1644_Y + end + attribute \src "ls180.v:6260.45-6260.149" + cell $and $and$ls180.v:6260$1646 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6260$1644_Y + connect \B $eq$ls180.v:6260$1645_Y + connect \Y $and$ls180.v:6260$1646_Y + end + attribute \src "ls180.v:6261.46-6261.102" + cell $and $and$ls180.v:6261$1648 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6261$1647_Y + connect \Y $and$ls180.v:6261$1648_Y + end + attribute \src "ls180.v:6261.45-6261.152" + cell $and $and$ls180.v:6261$1650 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6261$1648_Y + connect \B $eq$ls180.v:6261$1649_Y + connect \Y $and$ls180.v:6261$1650_Y + end + attribute \src "ls180.v:6263.46-6263.99" + cell $and $and$ls180.v:6263$1651 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6263$1651_Y + end + attribute \src "ls180.v:6263.45-6263.149" + cell $and $and$ls180.v:6263$1653 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6263$1651_Y + connect \B $eq$ls180.v:6263$1652_Y + connect \Y $and$ls180.v:6263$1653_Y + end + attribute \src "ls180.v:6264.46-6264.102" + cell $and $and$ls180.v:6264$1655 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6264$1654_Y + connect \Y $and$ls180.v:6264$1655_Y + end + attribute \src "ls180.v:6264.45-6264.152" + cell $and $and$ls180.v:6264$1657 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6264$1655_Y + connect \B $eq$ls180.v:6264$1656_Y + connect \Y $and$ls180.v:6264$1657_Y + end + attribute \src "ls180.v:6266.46-6266.99" + cell $and $and$ls180.v:6266$1658 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6266$1658_Y + end + attribute \src "ls180.v:6266.45-6266.149" + cell $and $and$ls180.v:6266$1660 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6266$1658_Y + connect \B $eq$ls180.v:6266$1659_Y + connect \Y $and$ls180.v:6266$1660_Y + end + attribute \src "ls180.v:6267.46-6267.102" + cell $and $and$ls180.v:6267$1662 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6267$1661_Y + connect \Y $and$ls180.v:6267$1662_Y + end + attribute \src "ls180.v:6267.45-6267.152" + cell $and $and$ls180.v:6267$1664 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6267$1662_Y + connect \B $eq$ls180.v:6267$1663_Y + connect \Y $and$ls180.v:6267$1664_Y + end + attribute \src "ls180.v:6269.45-6269.98" + cell $and $and$ls180.v:6269$1665 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6269$1665_Y + end + attribute \src "ls180.v:6269.44-6269.148" + cell $and $and$ls180.v:6269$1667 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6269$1665_Y + connect \B $eq$ls180.v:6269$1666_Y + connect \Y $and$ls180.v:6269$1667_Y + end + attribute \src "ls180.v:6270.45-6270.101" + cell $and $and$ls180.v:6270$1669 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6270$1668_Y + connect \Y $and$ls180.v:6270$1669_Y + end + attribute \src "ls180.v:6270.44-6270.151" + cell $and $and$ls180.v:6270$1671 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6270$1669_Y + connect \B $eq$ls180.v:6270$1670_Y + connect \Y $and$ls180.v:6270$1671_Y + end + attribute \src "ls180.v:6272.45-6272.98" + cell $and $and$ls180.v:6272$1672 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6272$1672_Y + end + attribute \src "ls180.v:6272.44-6272.148" + cell $and $and$ls180.v:6272$1674 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6272$1672_Y + connect \B $eq$ls180.v:6272$1673_Y + connect \Y $and$ls180.v:6272$1674_Y + end + attribute \src "ls180.v:6273.45-6273.101" + cell $and $and$ls180.v:6273$1676 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6273$1675_Y + connect \Y $and$ls180.v:6273$1676_Y + end + attribute \src "ls180.v:6273.44-6273.151" + cell $and $and$ls180.v:6273$1678 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6273$1676_Y + connect \B $eq$ls180.v:6273$1677_Y + connect \Y $and$ls180.v:6273$1678_Y + end + attribute \src "ls180.v:6275.45-6275.98" + cell $and $and$ls180.v:6275$1679 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6275$1679_Y + end + attribute \src "ls180.v:6275.44-6275.148" + cell $and $and$ls180.v:6275$1681 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6275$1679_Y + connect \B $eq$ls180.v:6275$1680_Y + connect \Y $and$ls180.v:6275$1681_Y + end + attribute \src "ls180.v:6276.45-6276.101" + cell $and $and$ls180.v:6276$1683 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6276$1682_Y + connect \Y $and$ls180.v:6276$1683_Y + end + attribute \src "ls180.v:6276.44-6276.151" + cell $and $and$ls180.v:6276$1685 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6276$1683_Y + connect \B $eq$ls180.v:6276$1684_Y + connect \Y $and$ls180.v:6276$1685_Y + end + attribute \src "ls180.v:6278.45-6278.98" + cell $and $and$ls180.v:6278$1686 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6278$1686_Y + end + attribute \src "ls180.v:6278.44-6278.148" + cell $and $and$ls180.v:6278$1688 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6278$1686_Y + connect \B $eq$ls180.v:6278$1687_Y + connect \Y $and$ls180.v:6278$1688_Y + end + attribute \src "ls180.v:6279.45-6279.101" + cell $and $and$ls180.v:6279$1690 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6279$1689_Y + connect \Y $and$ls180.v:6279$1690_Y + end + attribute \src "ls180.v:6279.44-6279.151" + cell $and $and$ls180.v:6279$1692 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6279$1690_Y + connect \B $eq$ls180.v:6279$1691_Y + connect \Y $and$ls180.v:6279$1692_Y + end + attribute \src "ls180.v:6281.36-6281.89" + cell $and $and$ls180.v:6281$1693 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6281$1693_Y + end + attribute \src "ls180.v:6281.35-6281.139" + cell $and $and$ls180.v:6281$1695 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6281$1693_Y + connect \B $eq$ls180.v:6281$1694_Y + connect \Y $and$ls180.v:6281$1695_Y + end + attribute \src "ls180.v:6282.36-6282.92" + cell $and $and$ls180.v:6282$1697 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6282$1696_Y + connect \Y $and$ls180.v:6282$1697_Y + end + attribute \src "ls180.v:6282.35-6282.142" + cell $and $and$ls180.v:6282$1699 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6282$1697_Y + connect \B $eq$ls180.v:6282$1698_Y + connect \Y $and$ls180.v:6282$1699_Y + end + attribute \src "ls180.v:6284.47-6284.100" + cell $and $and$ls180.v:6284$1700 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6284$1700_Y + end + attribute \src "ls180.v:6284.46-6284.150" + cell $and $and$ls180.v:6284$1702 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6284$1700_Y + connect \B $eq$ls180.v:6284$1701_Y + connect \Y $and$ls180.v:6284$1702_Y + end + attribute \src "ls180.v:6285.47-6285.103" + cell $and $and$ls180.v:6285$1704 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6285$1703_Y + connect \Y $and$ls180.v:6285$1704_Y + end + attribute \src "ls180.v:6285.46-6285.153" + cell $and $and$ls180.v:6285$1706 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6285$1704_Y + connect \B $eq$ls180.v:6285$1705_Y + connect \Y $and$ls180.v:6285$1706_Y + end + attribute \src "ls180.v:6287.47-6287.100" + cell $and $and$ls180.v:6287$1707 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6287$1707_Y + end + attribute \src "ls180.v:6287.46-6287.151" + cell $and $and$ls180.v:6287$1709 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6287$1707_Y + connect \B $eq$ls180.v:6287$1708_Y + connect \Y $and$ls180.v:6287$1709_Y + end + attribute \src "ls180.v:6288.47-6288.103" + cell $and $and$ls180.v:6288$1711 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6288$1710_Y + connect \Y $and$ls180.v:6288$1711_Y + end + attribute \src "ls180.v:6288.46-6288.154" + cell $and $and$ls180.v:6288$1713 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6288$1711_Y + connect \B $eq$ls180.v:6288$1712_Y + connect \Y $and$ls180.v:6288$1713_Y + end + attribute \src "ls180.v:6290.47-6290.100" + cell $and $and$ls180.v:6290$1714 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6290$1714_Y + end + attribute \src "ls180.v:6290.46-6290.151" + cell $and $and$ls180.v:6290$1716 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6290$1714_Y + connect \B $eq$ls180.v:6290$1715_Y + connect \Y $and$ls180.v:6290$1716_Y + end + attribute \src "ls180.v:6291.47-6291.103" + cell $and $and$ls180.v:6291$1718 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6291$1717_Y + connect \Y $and$ls180.v:6291$1718_Y + end + attribute \src "ls180.v:6291.46-6291.154" + cell $and $and$ls180.v:6291$1720 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6291$1718_Y + connect \B $eq$ls180.v:6291$1719_Y + connect \Y $and$ls180.v:6291$1720_Y + end + attribute \src "ls180.v:6293.47-6293.100" + cell $and $and$ls180.v:6293$1721 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6293$1721_Y + end + attribute \src "ls180.v:6293.46-6293.151" + cell $and $and$ls180.v:6293$1723 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6293$1721_Y + connect \B $eq$ls180.v:6293$1722_Y + connect \Y $and$ls180.v:6293$1723_Y + end + attribute \src "ls180.v:6294.47-6294.103" + cell $and $and$ls180.v:6294$1725 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6294$1724_Y + connect \Y $and$ls180.v:6294$1725_Y + end + attribute \src "ls180.v:6294.46-6294.154" + cell $and $and$ls180.v:6294$1727 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6294$1725_Y + connect \B $eq$ls180.v:6294$1726_Y + connect \Y $and$ls180.v:6294$1727_Y + end + attribute \src "ls180.v:6296.47-6296.100" + cell $and $and$ls180.v:6296$1728 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6296$1728_Y + end + attribute \src "ls180.v:6296.46-6296.151" + cell $and $and$ls180.v:6296$1730 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6296$1728_Y + connect \B $eq$ls180.v:6296$1729_Y + connect \Y $and$ls180.v:6296$1730_Y + end + attribute \src "ls180.v:6297.47-6297.103" + cell $and $and$ls180.v:6297$1732 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6297$1731_Y + connect \Y $and$ls180.v:6297$1732_Y + end + attribute \src "ls180.v:6297.46-6297.154" + cell $and $and$ls180.v:6297$1734 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6297$1732_Y + connect \B $eq$ls180.v:6297$1733_Y + connect \Y $and$ls180.v:6297$1734_Y + end + attribute \src "ls180.v:6299.47-6299.100" + cell $and $and$ls180.v:6299$1735 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6299$1735_Y + end + attribute \src "ls180.v:6299.46-6299.151" + cell $and $and$ls180.v:6299$1737 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6299$1735_Y + connect \B $eq$ls180.v:6299$1736_Y + connect \Y $and$ls180.v:6299$1737_Y + end + attribute \src "ls180.v:6300.47-6300.103" + cell $and $and$ls180.v:6300$1739 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6300$1738_Y + connect \Y $and$ls180.v:6300$1739_Y + end + attribute \src "ls180.v:6300.46-6300.154" + cell $and $and$ls180.v:6300$1741 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6300$1739_Y + connect \B $eq$ls180.v:6300$1740_Y + connect \Y $and$ls180.v:6300$1741_Y + end + attribute \src "ls180.v:6302.46-6302.99" + cell $and $and$ls180.v:6302$1742 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6302$1742_Y + end + attribute \src "ls180.v:6302.45-6302.150" + cell $and $and$ls180.v:6302$1744 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6302$1742_Y + connect \B $eq$ls180.v:6302$1743_Y + connect \Y $and$ls180.v:6302$1744_Y + end + attribute \src "ls180.v:6303.46-6303.102" + cell $and $and$ls180.v:6303$1746 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6303$1745_Y + connect \Y $and$ls180.v:6303$1746_Y + end + attribute \src "ls180.v:6303.45-6303.153" + cell $and $and$ls180.v:6303$1748 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6303$1746_Y + connect \B $eq$ls180.v:6303$1747_Y + connect \Y $and$ls180.v:6303$1748_Y + end + attribute \src "ls180.v:6305.46-6305.99" + cell $and $and$ls180.v:6305$1749 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6305$1749_Y + end + attribute \src "ls180.v:6305.45-6305.150" + cell $and $and$ls180.v:6305$1751 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6305$1749_Y + connect \B $eq$ls180.v:6305$1750_Y + connect \Y $and$ls180.v:6305$1751_Y + end + attribute \src "ls180.v:6306.46-6306.102" + cell $and $and$ls180.v:6306$1753 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6306$1752_Y + connect \Y $and$ls180.v:6306$1753_Y + end + attribute \src "ls180.v:6306.45-6306.153" + cell $and $and$ls180.v:6306$1755 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6306$1753_Y + connect \B $eq$ls180.v:6306$1754_Y + connect \Y $and$ls180.v:6306$1755_Y + end + attribute \src "ls180.v:6308.46-6308.99" + cell $and $and$ls180.v:6308$1756 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6308$1756_Y + end + attribute \src "ls180.v:6308.45-6308.150" + cell $and $and$ls180.v:6308$1758 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6308$1756_Y + connect \B $eq$ls180.v:6308$1757_Y + connect \Y $and$ls180.v:6308$1758_Y + end + attribute \src "ls180.v:6309.46-6309.102" + cell $and $and$ls180.v:6309$1760 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6309$1759_Y + connect \Y $and$ls180.v:6309$1760_Y + end + attribute \src "ls180.v:6309.45-6309.153" + cell $and $and$ls180.v:6309$1762 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6309$1760_Y + connect \B $eq$ls180.v:6309$1761_Y + connect \Y $and$ls180.v:6309$1762_Y + end + attribute \src "ls180.v:6311.46-6311.99" + cell $and $and$ls180.v:6311$1763 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6311$1763_Y + end + attribute \src "ls180.v:6311.45-6311.150" + cell $and $and$ls180.v:6311$1765 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6311$1763_Y + connect \B $eq$ls180.v:6311$1764_Y + connect \Y $and$ls180.v:6311$1765_Y + end + attribute \src "ls180.v:6312.46-6312.102" + cell $and $and$ls180.v:6312$1767 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6312$1766_Y + connect \Y $and$ls180.v:6312$1767_Y + end + attribute \src "ls180.v:6312.45-6312.153" + cell $and $and$ls180.v:6312$1769 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6312$1767_Y + connect \B $eq$ls180.v:6312$1768_Y + connect \Y $and$ls180.v:6312$1769_Y + end + attribute \src "ls180.v:6314.46-6314.99" + cell $and $and$ls180.v:6314$1770 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6314$1770_Y + end + attribute \src "ls180.v:6314.45-6314.150" + cell $and $and$ls180.v:6314$1772 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6314$1770_Y + connect \B $eq$ls180.v:6314$1771_Y + connect \Y $and$ls180.v:6314$1772_Y + end + attribute \src "ls180.v:6315.46-6315.102" + cell $and $and$ls180.v:6315$1774 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6315$1773_Y + connect \Y $and$ls180.v:6315$1774_Y + end + attribute \src "ls180.v:6315.45-6315.153" + cell $and $and$ls180.v:6315$1776 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6315$1774_Y + connect \B $eq$ls180.v:6315$1775_Y + connect \Y $and$ls180.v:6315$1776_Y + end + attribute \src "ls180.v:6317.46-6317.99" + cell $and $and$ls180.v:6317$1777 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6317$1777_Y + end + attribute \src "ls180.v:6317.45-6317.150" + cell $and $and$ls180.v:6317$1779 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6317$1777_Y + connect \B $eq$ls180.v:6317$1778_Y + connect \Y $and$ls180.v:6317$1779_Y + end + attribute \src "ls180.v:6318.46-6318.102" + cell $and $and$ls180.v:6318$1781 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6318$1780_Y + connect \Y $and$ls180.v:6318$1781_Y + end + attribute \src "ls180.v:6318.45-6318.153" + cell $and $and$ls180.v:6318$1783 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6318$1781_Y + connect \B $eq$ls180.v:6318$1782_Y + connect \Y $and$ls180.v:6318$1783_Y + end + attribute \src "ls180.v:6320.46-6320.99" + cell $and $and$ls180.v:6320$1784 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6320$1784_Y + end + attribute \src "ls180.v:6320.45-6320.150" + cell $and $and$ls180.v:6320$1786 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6320$1784_Y + connect \B $eq$ls180.v:6320$1785_Y + connect \Y $and$ls180.v:6320$1786_Y + end + attribute \src "ls180.v:6321.46-6321.102" + cell $and $and$ls180.v:6321$1788 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6321$1787_Y + connect \Y $and$ls180.v:6321$1788_Y + end + attribute \src "ls180.v:6321.45-6321.153" + cell $and $and$ls180.v:6321$1790 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6321$1788_Y + connect \B $eq$ls180.v:6321$1789_Y + connect \Y $and$ls180.v:6321$1790_Y + end + attribute \src "ls180.v:6323.46-6323.99" + cell $and $and$ls180.v:6323$1791 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6323$1791_Y + end + attribute \src "ls180.v:6323.45-6323.150" + cell $and $and$ls180.v:6323$1793 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6323$1791_Y + connect \B $eq$ls180.v:6323$1792_Y + connect \Y $and$ls180.v:6323$1793_Y + end + attribute \src "ls180.v:6324.46-6324.102" + cell $and $and$ls180.v:6324$1795 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6324$1794_Y + connect \Y $and$ls180.v:6324$1795_Y + end + attribute \src "ls180.v:6324.45-6324.153" + cell $and $and$ls180.v:6324$1797 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6324$1795_Y + connect \B $eq$ls180.v:6324$1796_Y + connect \Y $and$ls180.v:6324$1797_Y + end + attribute \src "ls180.v:6326.46-6326.99" + cell $and $and$ls180.v:6326$1798 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6326$1798_Y + end + attribute \src "ls180.v:6326.45-6326.150" + cell $and $and$ls180.v:6326$1800 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6326$1798_Y + connect \B $eq$ls180.v:6326$1799_Y + connect \Y $and$ls180.v:6326$1800_Y + end + attribute \src "ls180.v:6327.46-6327.102" + cell $and $and$ls180.v:6327$1802 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6327$1801_Y + connect \Y $and$ls180.v:6327$1802_Y + end + attribute \src "ls180.v:6327.45-6327.153" + cell $and $and$ls180.v:6327$1804 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6327$1802_Y + connect \B $eq$ls180.v:6327$1803_Y + connect \Y $and$ls180.v:6327$1804_Y + end + attribute \src "ls180.v:6329.46-6329.99" + cell $and $and$ls180.v:6329$1805 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6329$1805_Y + end + attribute \src "ls180.v:6329.45-6329.150" + cell $and $and$ls180.v:6329$1807 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6329$1805_Y + connect \B $eq$ls180.v:6329$1806_Y + connect \Y $and$ls180.v:6329$1807_Y + end + attribute \src "ls180.v:6330.46-6330.102" + cell $and $and$ls180.v:6330$1809 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6330$1808_Y + connect \Y $and$ls180.v:6330$1809_Y + end + attribute \src "ls180.v:6330.45-6330.153" + cell $and $and$ls180.v:6330$1811 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6330$1809_Y + connect \B $eq$ls180.v:6330$1810_Y + connect \Y $and$ls180.v:6330$1811_Y + end + attribute \src "ls180.v:6332.42-6332.95" + cell $and $and$ls180.v:6332$1812 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6332$1812_Y + end + attribute \src "ls180.v:6332.41-6332.146" + cell $and $and$ls180.v:6332$1814 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6332$1812_Y + connect \B $eq$ls180.v:6332$1813_Y + connect \Y $and$ls180.v:6332$1814_Y + end + attribute \src "ls180.v:6333.42-6333.98" + cell $and $and$ls180.v:6333$1816 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6333$1815_Y + connect \Y $and$ls180.v:6333$1816_Y + end + attribute \src "ls180.v:6333.41-6333.149" + cell $and $and$ls180.v:6333$1818 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6333$1816_Y + connect \B $eq$ls180.v:6333$1817_Y + connect \Y $and$ls180.v:6333$1818_Y + end + attribute \src "ls180.v:6335.43-6335.96" + cell $and $and$ls180.v:6335$1819 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6335$1819_Y + end + attribute \src "ls180.v:6335.42-6335.147" + cell $and $and$ls180.v:6335$1821 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6335$1819_Y + connect \B $eq$ls180.v:6335$1820_Y + connect \Y $and$ls180.v:6335$1821_Y + end + attribute \src "ls180.v:6336.43-6336.99" + cell $and $and$ls180.v:6336$1823 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6336$1822_Y + connect \Y $and$ls180.v:6336$1823_Y + end + attribute \src "ls180.v:6336.42-6336.150" + cell $and $and$ls180.v:6336$1825 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6336$1823_Y + connect \B $eq$ls180.v:6336$1824_Y + connect \Y $and$ls180.v:6336$1825_Y + end + attribute \src "ls180.v:6338.46-6338.99" + cell $and $and$ls180.v:6338$1826 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6338$1826_Y + end + attribute \src "ls180.v:6338.45-6338.150" + cell $and $and$ls180.v:6338$1828 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6338$1826_Y + connect \B $eq$ls180.v:6338$1827_Y + connect \Y $and$ls180.v:6338$1828_Y + end + attribute \src "ls180.v:6339.46-6339.102" + cell $and $and$ls180.v:6339$1830 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6339$1829_Y + connect \Y $and$ls180.v:6339$1830_Y + end + attribute \src "ls180.v:6339.45-6339.153" + cell $and $and$ls180.v:6339$1832 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6339$1830_Y + connect \B $eq$ls180.v:6339$1831_Y + connect \Y $and$ls180.v:6339$1832_Y + end + attribute \src "ls180.v:6341.46-6341.99" + cell $and $and$ls180.v:6341$1833 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6341$1833_Y + end + attribute \src "ls180.v:6341.45-6341.150" + cell $and $and$ls180.v:6341$1835 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6341$1833_Y + connect \B $eq$ls180.v:6341$1834_Y + connect \Y $and$ls180.v:6341$1835_Y + end + attribute \src "ls180.v:6342.46-6342.102" + cell $and $and$ls180.v:6342$1837 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6342$1836_Y + connect \Y $and$ls180.v:6342$1837_Y + end + attribute \src "ls180.v:6342.45-6342.153" + cell $and $and$ls180.v:6342$1839 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6342$1837_Y + connect \B $eq$ls180.v:6342$1838_Y + connect \Y $and$ls180.v:6342$1839_Y + end + attribute \src "ls180.v:6344.45-6344.98" + cell $and $and$ls180.v:6344$1840 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6344$1840_Y + end + attribute \src "ls180.v:6344.44-6344.149" + cell $and $and$ls180.v:6344$1842 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6344$1840_Y + connect \B $eq$ls180.v:6344$1841_Y + connect \Y $and$ls180.v:6344$1842_Y + end + attribute \src "ls180.v:6345.45-6345.101" + cell $and $and$ls180.v:6345$1844 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6345$1843_Y + connect \Y $and$ls180.v:6345$1844_Y + end + attribute \src "ls180.v:6345.44-6345.152" + cell $and $and$ls180.v:6345$1846 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6345$1844_Y + connect \B $eq$ls180.v:6345$1845_Y + connect \Y $and$ls180.v:6345$1846_Y + end + attribute \src "ls180.v:6347.45-6347.98" + cell $and $and$ls180.v:6347$1847 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6347$1847_Y + end + attribute \src "ls180.v:6347.44-6347.149" + cell $and $and$ls180.v:6347$1849 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6347$1847_Y + connect \B $eq$ls180.v:6347$1848_Y + connect \Y $and$ls180.v:6347$1849_Y + end + attribute \src "ls180.v:6348.45-6348.101" + cell $and $and$ls180.v:6348$1851 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6348$1850_Y + connect \Y $and$ls180.v:6348$1851_Y + end + attribute \src "ls180.v:6348.44-6348.152" + cell $and $and$ls180.v:6348$1853 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6348$1851_Y + connect \B $eq$ls180.v:6348$1852_Y + connect \Y $and$ls180.v:6348$1853_Y + end + attribute \src "ls180.v:6350.45-6350.98" + cell $and $and$ls180.v:6350$1854 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6350$1854_Y + end + attribute \src "ls180.v:6350.44-6350.149" + cell $and $and$ls180.v:6350$1856 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6350$1854_Y + connect \B $eq$ls180.v:6350$1855_Y + connect \Y $and$ls180.v:6350$1856_Y + end + attribute \src "ls180.v:6351.45-6351.101" + cell $and $and$ls180.v:6351$1858 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6351$1857_Y + connect \Y $and$ls180.v:6351$1858_Y + end + attribute \src "ls180.v:6351.44-6351.152" + cell $and $and$ls180.v:6351$1860 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6351$1858_Y + connect \B $eq$ls180.v:6351$1859_Y + connect \Y $and$ls180.v:6351$1860_Y + end + attribute \src "ls180.v:6353.45-6353.98" + cell $and $and$ls180.v:6353$1861 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B \builder_interface6_bank_bus_we + connect \Y $and$ls180.v:6353$1861_Y + end + attribute \src "ls180.v:6353.44-6353.149" + cell $and $and$ls180.v:6353$1863 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6353$1861_Y + connect \B $eq$ls180.v:6353$1862_Y + connect \Y $and$ls180.v:6353$1863_Y + end + attribute \src "ls180.v:6354.45-6354.101" + cell $and $and$ls180.v:6354$1865 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank6_sel + connect \B $not$ls180.v:6354$1864_Y + connect \Y $and$ls180.v:6354$1865_Y + end + attribute \src "ls180.v:6354.44-6354.152" + cell $and $and$ls180.v:6354$1867 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6354$1865_Y + connect \B $eq$ls180.v:6354$1866_Y + connect \Y $and$ls180.v:6354$1867_Y + end + attribute \src "ls180.v:6392.42-6392.95" + cell $and $and$ls180.v:6392$1869 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B \builder_interface7_bank_bus_we + connect \Y $and$ls180.v:6392$1869_Y + end + attribute \src "ls180.v:6392.41-6392.145" + cell $and $and$ls180.v:6392$1871 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6392$1869_Y + connect \B $eq$ls180.v:6392$1870_Y + connect \Y $and$ls180.v:6392$1871_Y + end + attribute \src "ls180.v:6393.42-6393.98" + cell $and $and$ls180.v:6393$1873 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B $not$ls180.v:6393$1872_Y + connect \Y $and$ls180.v:6393$1873_Y + end + attribute \src "ls180.v:6393.41-6393.148" + cell $and $and$ls180.v:6393$1875 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6393$1873_Y + connect \B $eq$ls180.v:6393$1874_Y + connect \Y $and$ls180.v:6393$1875_Y + end + attribute \src "ls180.v:6395.42-6395.95" + cell $and $and$ls180.v:6395$1876 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B \builder_interface7_bank_bus_we + connect \Y $and$ls180.v:6395$1876_Y + end + attribute \src "ls180.v:6395.41-6395.145" + cell $and $and$ls180.v:6395$1878 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6395$1876_Y + connect \B $eq$ls180.v:6395$1877_Y + connect \Y $and$ls180.v:6395$1878_Y + end + attribute \src "ls180.v:6396.42-6396.98" + cell $and $and$ls180.v:6396$1880 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B $not$ls180.v:6396$1879_Y + connect \Y $and$ls180.v:6396$1880_Y + end + attribute \src "ls180.v:6396.41-6396.148" + cell $and $and$ls180.v:6396$1882 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6396$1880_Y + connect \B $eq$ls180.v:6396$1881_Y + connect \Y $and$ls180.v:6396$1882_Y + end + attribute \src "ls180.v:6398.42-6398.95" + cell $and $and$ls180.v:6398$1883 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B \builder_interface7_bank_bus_we + connect \Y $and$ls180.v:6398$1883_Y + end + attribute \src "ls180.v:6398.41-6398.145" + cell $and $and$ls180.v:6398$1885 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6398$1883_Y + connect \B $eq$ls180.v:6398$1884_Y + connect \Y $and$ls180.v:6398$1885_Y + end + attribute \src "ls180.v:6399.42-6399.98" + cell $and $and$ls180.v:6399$1887 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B $not$ls180.v:6399$1886_Y + connect \Y $and$ls180.v:6399$1887_Y + end + attribute \src "ls180.v:6399.41-6399.148" + cell $and $and$ls180.v:6399$1889 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6399$1887_Y + connect \B $eq$ls180.v:6399$1888_Y + connect \Y $and$ls180.v:6399$1889_Y + end + attribute \src "ls180.v:6401.42-6401.95" + cell $and $and$ls180.v:6401$1890 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B \builder_interface7_bank_bus_we + connect \Y $and$ls180.v:6401$1890_Y + end + attribute \src "ls180.v:6401.41-6401.145" + cell $and $and$ls180.v:6401$1892 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6401$1890_Y + connect \B $eq$ls180.v:6401$1891_Y + connect \Y $and$ls180.v:6401$1892_Y + end + attribute \src "ls180.v:6402.42-6402.98" + cell $and $and$ls180.v:6402$1894 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B $not$ls180.v:6402$1893_Y + connect \Y $and$ls180.v:6402$1894_Y + end + attribute \src "ls180.v:6402.41-6402.148" + cell $and $and$ls180.v:6402$1896 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6402$1894_Y + connect \B $eq$ls180.v:6402$1895_Y + connect \Y $and$ls180.v:6402$1896_Y + end + attribute \src "ls180.v:6404.42-6404.95" + cell $and $and$ls180.v:6404$1897 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B \builder_interface7_bank_bus_we + connect \Y $and$ls180.v:6404$1897_Y + end + attribute \src "ls180.v:6404.41-6404.145" + cell $and $and$ls180.v:6404$1899 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6404$1897_Y + connect \B $eq$ls180.v:6404$1898_Y + connect \Y $and$ls180.v:6404$1899_Y + end + attribute \src "ls180.v:6405.42-6405.98" + cell $and $and$ls180.v:6405$1901 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B $not$ls180.v:6405$1900_Y + connect \Y $and$ls180.v:6405$1901_Y + end + attribute \src "ls180.v:6405.41-6405.148" + cell $and $and$ls180.v:6405$1903 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6405$1901_Y + connect \B $eq$ls180.v:6405$1902_Y + connect \Y $and$ls180.v:6405$1903_Y + end + attribute \src "ls180.v:6407.42-6407.95" + cell $and $and$ls180.v:6407$1904 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B \builder_interface7_bank_bus_we + connect \Y $and$ls180.v:6407$1904_Y + end + attribute \src "ls180.v:6407.41-6407.145" + cell $and $and$ls180.v:6407$1906 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6407$1904_Y + connect \B $eq$ls180.v:6407$1905_Y + connect \Y $and$ls180.v:6407$1906_Y + end + attribute \src "ls180.v:6408.42-6408.98" + cell $and $and$ls180.v:6408$1908 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B $not$ls180.v:6408$1907_Y + connect \Y $and$ls180.v:6408$1908_Y + end + attribute \src "ls180.v:6408.41-6408.148" + cell $and $and$ls180.v:6408$1910 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6408$1908_Y + connect \B $eq$ls180.v:6408$1909_Y + connect \Y $and$ls180.v:6408$1910_Y + end + attribute \src "ls180.v:6410.42-6410.95" + cell $and $and$ls180.v:6410$1911 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B \builder_interface7_bank_bus_we + connect \Y $and$ls180.v:6410$1911_Y + end + attribute \src "ls180.v:6410.41-6410.145" + cell $and $and$ls180.v:6410$1913 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6410$1911_Y + connect \B $eq$ls180.v:6410$1912_Y + connect \Y $and$ls180.v:6410$1913_Y + end + attribute \src "ls180.v:6411.42-6411.98" + cell $and $and$ls180.v:6411$1915 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B $not$ls180.v:6411$1914_Y + connect \Y $and$ls180.v:6411$1915_Y + end + attribute \src "ls180.v:6411.41-6411.148" + cell $and $and$ls180.v:6411$1917 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6411$1915_Y + connect \B $eq$ls180.v:6411$1916_Y + connect \Y $and$ls180.v:6411$1917_Y + end + attribute \src "ls180.v:6413.42-6413.95" + cell $and $and$ls180.v:6413$1918 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B \builder_interface7_bank_bus_we + connect \Y $and$ls180.v:6413$1918_Y + end + attribute \src "ls180.v:6413.41-6413.145" + cell $and $and$ls180.v:6413$1920 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6413$1918_Y + connect \B $eq$ls180.v:6413$1919_Y + connect \Y $and$ls180.v:6413$1920_Y + end + attribute \src "ls180.v:6414.42-6414.98" + cell $and $and$ls180.v:6414$1922 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B $not$ls180.v:6414$1921_Y + connect \Y $and$ls180.v:6414$1922_Y + end + attribute \src "ls180.v:6414.41-6414.148" + cell $and $and$ls180.v:6414$1924 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6414$1922_Y + connect \B $eq$ls180.v:6414$1923_Y + connect \Y $and$ls180.v:6414$1924_Y + end + attribute \src "ls180.v:6416.44-6416.97" + cell $and $and$ls180.v:6416$1925 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B \builder_interface7_bank_bus_we + connect \Y $and$ls180.v:6416$1925_Y + end + attribute \src "ls180.v:6416.43-6416.147" + cell $and $and$ls180.v:6416$1927 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6416$1925_Y + connect \B $eq$ls180.v:6416$1926_Y + connect \Y $and$ls180.v:6416$1927_Y + end + attribute \src "ls180.v:6417.44-6417.100" + cell $and $and$ls180.v:6417$1929 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B $not$ls180.v:6417$1928_Y + connect \Y $and$ls180.v:6417$1929_Y + end + attribute \src "ls180.v:6417.43-6417.150" + cell $and $and$ls180.v:6417$1931 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6417$1929_Y + connect \B $eq$ls180.v:6417$1930_Y + connect \Y $and$ls180.v:6417$1931_Y + end + attribute \src "ls180.v:6419.44-6419.97" + cell $and $and$ls180.v:6419$1932 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B \builder_interface7_bank_bus_we + connect \Y $and$ls180.v:6419$1932_Y + end + attribute \src "ls180.v:6419.43-6419.147" + cell $and $and$ls180.v:6419$1934 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6419$1932_Y + connect \B $eq$ls180.v:6419$1933_Y + connect \Y $and$ls180.v:6419$1934_Y + end + attribute \src "ls180.v:6420.44-6420.100" + cell $and $and$ls180.v:6420$1936 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B $not$ls180.v:6420$1935_Y + connect \Y $and$ls180.v:6420$1936_Y + end + attribute \src "ls180.v:6420.43-6420.150" + cell $and $and$ls180.v:6420$1938 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6420$1936_Y + connect \B $eq$ls180.v:6420$1937_Y + connect \Y $and$ls180.v:6420$1938_Y + end + attribute \src "ls180.v:6422.44-6422.97" + cell $and $and$ls180.v:6422$1939 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B \builder_interface7_bank_bus_we + connect \Y $and$ls180.v:6422$1939_Y + end + attribute \src "ls180.v:6422.43-6422.148" + cell $and $and$ls180.v:6422$1941 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6422$1939_Y + connect \B $eq$ls180.v:6422$1940_Y + connect \Y $and$ls180.v:6422$1941_Y + end + attribute \src "ls180.v:6423.44-6423.100" + cell $and $and$ls180.v:6423$1943 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B $not$ls180.v:6423$1942_Y + connect \Y $and$ls180.v:6423$1943_Y + end + attribute \src "ls180.v:6423.43-6423.151" + cell $and $and$ls180.v:6423$1945 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6423$1943_Y + connect \B $eq$ls180.v:6423$1944_Y + connect \Y $and$ls180.v:6423$1945_Y + end + attribute \src "ls180.v:6425.44-6425.97" + cell $and $and$ls180.v:6425$1946 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B \builder_interface7_bank_bus_we + connect \Y $and$ls180.v:6425$1946_Y + end + attribute \src "ls180.v:6425.43-6425.148" + cell $and $and$ls180.v:6425$1948 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6425$1946_Y + connect \B $eq$ls180.v:6425$1947_Y + connect \Y $and$ls180.v:6425$1948_Y + end + attribute \src "ls180.v:6426.44-6426.100" + cell $and $and$ls180.v:6426$1950 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B $not$ls180.v:6426$1949_Y + connect \Y $and$ls180.v:6426$1950_Y + end + attribute \src "ls180.v:6426.43-6426.151" + cell $and $and$ls180.v:6426$1952 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6426$1950_Y + connect \B $eq$ls180.v:6426$1951_Y + connect \Y $and$ls180.v:6426$1952_Y + end + attribute \src "ls180.v:6428.44-6428.97" + cell $and $and$ls180.v:6428$1953 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B \builder_interface7_bank_bus_we + connect \Y $and$ls180.v:6428$1953_Y + end + attribute \src "ls180.v:6428.43-6428.148" + cell $and $and$ls180.v:6428$1955 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6428$1953_Y + connect \B $eq$ls180.v:6428$1954_Y + connect \Y $and$ls180.v:6428$1955_Y + end + attribute \src "ls180.v:6429.44-6429.100" + cell $and $and$ls180.v:6429$1957 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B $not$ls180.v:6429$1956_Y + connect \Y $and$ls180.v:6429$1957_Y + end + attribute \src "ls180.v:6429.43-6429.151" + cell $and $and$ls180.v:6429$1959 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6429$1957_Y + connect \B $eq$ls180.v:6429$1958_Y + connect \Y $and$ls180.v:6429$1959_Y + end + attribute \src "ls180.v:6431.41-6431.94" + cell $and $and$ls180.v:6431$1960 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B \builder_interface7_bank_bus_we + connect \Y $and$ls180.v:6431$1960_Y + end + attribute \src "ls180.v:6431.40-6431.145" + cell $and $and$ls180.v:6431$1962 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6431$1960_Y + connect \B $eq$ls180.v:6431$1961_Y + connect \Y $and$ls180.v:6431$1962_Y + end + attribute \src "ls180.v:6432.41-6432.97" + cell $and $and$ls180.v:6432$1964 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B $not$ls180.v:6432$1963_Y + connect \Y $and$ls180.v:6432$1964_Y + end + attribute \src "ls180.v:6432.40-6432.148" + cell $and $and$ls180.v:6432$1966 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6432$1964_Y + connect \B $eq$ls180.v:6432$1965_Y + connect \Y $and$ls180.v:6432$1966_Y + end + attribute \src "ls180.v:6434.42-6434.95" + cell $and $and$ls180.v:6434$1967 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B \builder_interface7_bank_bus_we + connect \Y $and$ls180.v:6434$1967_Y + end + attribute \src "ls180.v:6434.41-6434.146" + cell $and $and$ls180.v:6434$1969 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6434$1967_Y + connect \B $eq$ls180.v:6434$1968_Y + connect \Y $and$ls180.v:6434$1969_Y + end + attribute \src "ls180.v:6435.42-6435.98" + cell $and $and$ls180.v:6435$1971 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B $not$ls180.v:6435$1970_Y + connect \Y $and$ls180.v:6435$1971_Y + end + attribute \src "ls180.v:6435.41-6435.149" + cell $and $and$ls180.v:6435$1973 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6435$1971_Y + connect \B $eq$ls180.v:6435$1972_Y + connect \Y $and$ls180.v:6435$1973_Y + end + attribute \src "ls180.v:6437.44-6437.97" + cell $and $and$ls180.v:6437$1974 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B \builder_interface7_bank_bus_we + connect \Y $and$ls180.v:6437$1974_Y + end + attribute \src "ls180.v:6437.43-6437.148" + cell $and $and$ls180.v:6437$1976 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6437$1974_Y + connect \B $eq$ls180.v:6437$1975_Y + connect \Y $and$ls180.v:6437$1976_Y + end + attribute \src "ls180.v:6438.44-6438.100" + cell $and $and$ls180.v:6438$1978 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B $not$ls180.v:6438$1977_Y + connect \Y $and$ls180.v:6438$1978_Y + end + attribute \src "ls180.v:6438.43-6438.151" + cell $and $and$ls180.v:6438$1980 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6438$1978_Y + connect \B $eq$ls180.v:6438$1979_Y + connect \Y $and$ls180.v:6438$1980_Y + end + attribute \src "ls180.v:6440.44-6440.97" + cell $and $and$ls180.v:6440$1981 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B \builder_interface7_bank_bus_we + connect \Y $and$ls180.v:6440$1981_Y + end + attribute \src "ls180.v:6440.43-6440.148" + cell $and $and$ls180.v:6440$1983 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6440$1981_Y + connect \B $eq$ls180.v:6440$1982_Y + connect \Y $and$ls180.v:6440$1983_Y + end + attribute \src "ls180.v:6441.44-6441.100" + cell $and $and$ls180.v:6441$1985 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B $not$ls180.v:6441$1984_Y + connect \Y $and$ls180.v:6441$1985_Y + end + attribute \src "ls180.v:6441.43-6441.151" + cell $and $and$ls180.v:6441$1987 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6441$1985_Y + connect \B $eq$ls180.v:6441$1986_Y + connect \Y $and$ls180.v:6441$1987_Y + end + attribute \src "ls180.v:6443.44-6443.97" + cell $and $and$ls180.v:6443$1988 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B \builder_interface7_bank_bus_we + connect \Y $and$ls180.v:6443$1988_Y + end + attribute \src "ls180.v:6443.43-6443.148" + cell $and $and$ls180.v:6443$1990 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6443$1988_Y + connect \B $eq$ls180.v:6443$1989_Y + connect \Y $and$ls180.v:6443$1990_Y + end + attribute \src "ls180.v:6444.44-6444.100" + cell $and $and$ls180.v:6444$1992 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B $not$ls180.v:6444$1991_Y + connect \Y $and$ls180.v:6444$1992_Y + end + attribute \src "ls180.v:6444.43-6444.151" + cell $and $and$ls180.v:6444$1994 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6444$1992_Y + connect \B $eq$ls180.v:6444$1993_Y + connect \Y $and$ls180.v:6444$1994_Y + end + attribute \src "ls180.v:6446.44-6446.97" + cell $and $and$ls180.v:6446$1995 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B \builder_interface7_bank_bus_we + connect \Y $and$ls180.v:6446$1995_Y + end + attribute \src "ls180.v:6446.43-6446.148" + cell $and $and$ls180.v:6446$1997 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6446$1995_Y + connect \B $eq$ls180.v:6446$1996_Y + connect \Y $and$ls180.v:6446$1997_Y + end + attribute \src "ls180.v:6447.44-6447.100" + cell $and $and$ls180.v:6447$1999 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank7_sel + connect \B $not$ls180.v:6447$1998_Y + connect \Y $and$ls180.v:6447$1999_Y + end + attribute \src "ls180.v:6447.43-6447.151" + cell $and $and$ls180.v:6447$2001 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6447$1999_Y + connect \B $eq$ls180.v:6447$2000_Y + connect \Y $and$ls180.v:6447$2001_Y + end + attribute \src "ls180.v:6471.44-6471.97" + cell $and $and$ls180.v:6471$2003 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank8_sel + connect \B \builder_interface8_bank_bus_we + connect \Y $and$ls180.v:6471$2003_Y + end + attribute \src "ls180.v:6471.43-6471.147" + cell $and $and$ls180.v:6471$2005 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6471$2003_Y + connect \B $eq$ls180.v:6471$2004_Y + connect \Y $and$ls180.v:6471$2005_Y + end + attribute \src "ls180.v:6472.44-6472.100" + cell $and $and$ls180.v:6472$2007 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank8_sel + connect \B $not$ls180.v:6472$2006_Y + connect \Y $and$ls180.v:6472$2007_Y + end + attribute \src "ls180.v:6472.43-6472.150" + cell $and $and$ls180.v:6472$2009 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6472$2007_Y + connect \B $eq$ls180.v:6472$2008_Y + connect \Y $and$ls180.v:6472$2009_Y + end + attribute \src "ls180.v:6474.49-6474.102" + cell $and $and$ls180.v:6474$2010 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank8_sel + connect \B \builder_interface8_bank_bus_we + connect \Y $and$ls180.v:6474$2010_Y + end + attribute \src "ls180.v:6474.48-6474.152" + cell $and $and$ls180.v:6474$2012 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6474$2010_Y + connect \B $eq$ls180.v:6474$2011_Y + connect \Y $and$ls180.v:6474$2012_Y + end + attribute \src "ls180.v:6475.49-6475.105" + cell $and $and$ls180.v:6475$2014 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank8_sel + connect \B $not$ls180.v:6475$2013_Y + connect \Y $and$ls180.v:6475$2014_Y + end + attribute \src "ls180.v:6475.48-6475.155" + cell $and $and$ls180.v:6475$2016 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6475$2014_Y + connect \B $eq$ls180.v:6475$2015_Y + connect \Y $and$ls180.v:6475$2016_Y + end + attribute \src "ls180.v:6477.49-6477.102" + cell $and $and$ls180.v:6477$2017 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank8_sel + connect \B \builder_interface8_bank_bus_we + connect \Y $and$ls180.v:6477$2017_Y + end + attribute \src "ls180.v:6477.48-6477.152" + cell $and $and$ls180.v:6477$2019 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6477$2017_Y + connect \B $eq$ls180.v:6477$2018_Y + connect \Y $and$ls180.v:6477$2019_Y + end + attribute \src "ls180.v:6478.49-6478.105" + cell $and $and$ls180.v:6478$2021 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank8_sel + connect \B $not$ls180.v:6478$2020_Y + connect \Y $and$ls180.v:6478$2021_Y + end + attribute \src "ls180.v:6478.48-6478.155" + cell $and $and$ls180.v:6478$2023 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6478$2021_Y + connect \B $eq$ls180.v:6478$2022_Y + connect \Y $and$ls180.v:6478$2023_Y + end + attribute \src "ls180.v:6480.42-6480.95" + cell $and $and$ls180.v:6480$2024 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank8_sel + connect \B \builder_interface8_bank_bus_we + connect \Y $and$ls180.v:6480$2024_Y + end + attribute \src "ls180.v:6480.41-6480.145" + cell $and $and$ls180.v:6480$2026 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6480$2024_Y + connect \B $eq$ls180.v:6480$2025_Y + connect \Y $and$ls180.v:6480$2026_Y + end + attribute \src "ls180.v:6481.42-6481.98" + cell $and $and$ls180.v:6481$2028 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank8_sel + connect \B $not$ls180.v:6481$2027_Y + connect \Y $and$ls180.v:6481$2028_Y + end + attribute \src "ls180.v:6481.41-6481.148" + cell $and $and$ls180.v:6481$2030 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6481$2028_Y + connect \B $eq$ls180.v:6481$2029_Y + connect \Y $and$ls180.v:6481$2030_Y + end + attribute \src "ls180.v:6488.46-6488.99" + cell $and $and$ls180.v:6488$2032 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B \builder_interface9_bank_bus_we + connect \Y $and$ls180.v:6488$2032_Y + end + attribute \src "ls180.v:6488.45-6488.149" + cell $and $and$ls180.v:6488$2034 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6488$2032_Y + connect \B $eq$ls180.v:6488$2033_Y + connect \Y $and$ls180.v:6488$2034_Y + end + attribute \src "ls180.v:6489.46-6489.102" + cell $and $and$ls180.v:6489$2036 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B $not$ls180.v:6489$2035_Y + connect \Y $and$ls180.v:6489$2036_Y + end + attribute \src "ls180.v:6489.45-6489.152" + cell $and $and$ls180.v:6489$2038 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6489$2036_Y + connect \B $eq$ls180.v:6489$2037_Y + connect \Y $and$ls180.v:6489$2038_Y + end + attribute \src "ls180.v:6491.50-6491.103" + cell $and $and$ls180.v:6491$2039 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B \builder_interface9_bank_bus_we + connect \Y $and$ls180.v:6491$2039_Y + end + attribute \src "ls180.v:6491.49-6491.153" + cell $and $and$ls180.v:6491$2041 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6491$2039_Y + connect \B $eq$ls180.v:6491$2040_Y + connect \Y $and$ls180.v:6491$2041_Y + end + attribute \src "ls180.v:6492.50-6492.106" + cell $and $and$ls180.v:6492$2043 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B $not$ls180.v:6492$2042_Y + connect \Y $and$ls180.v:6492$2043_Y + end + attribute \src "ls180.v:6492.49-6492.156" + cell $and $and$ls180.v:6492$2045 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6492$2043_Y + connect \B $eq$ls180.v:6492$2044_Y + connect \Y $and$ls180.v:6492$2045_Y + end + attribute \src "ls180.v:6494.40-6494.93" + cell $and $and$ls180.v:6494$2046 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B \builder_interface9_bank_bus_we + connect \Y $and$ls180.v:6494$2046_Y + end + attribute \src "ls180.v:6494.39-6494.143" + cell $and $and$ls180.v:6494$2048 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6494$2046_Y + connect \B $eq$ls180.v:6494$2047_Y + connect \Y $and$ls180.v:6494$2048_Y + end + attribute \src "ls180.v:6495.40-6495.96" + cell $and $and$ls180.v:6495$2050 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B $not$ls180.v:6495$2049_Y + connect \Y $and$ls180.v:6495$2050_Y + end + attribute \src "ls180.v:6495.39-6495.146" + cell $and $and$ls180.v:6495$2052 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6495$2050_Y + connect \B $eq$ls180.v:6495$2051_Y + connect \Y $and$ls180.v:6495$2052_Y + end + attribute \src "ls180.v:6497.50-6497.103" + cell $and $and$ls180.v:6497$2053 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B \builder_interface9_bank_bus_we + connect \Y $and$ls180.v:6497$2053_Y + end + attribute \src "ls180.v:6497.49-6497.153" + cell $and $and$ls180.v:6497$2055 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6497$2053_Y + connect \B $eq$ls180.v:6497$2054_Y + connect \Y $and$ls180.v:6497$2055_Y + end + attribute \src "ls180.v:6498.50-6498.106" + cell $and $and$ls180.v:6498$2057 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B $not$ls180.v:6498$2056_Y + connect \Y $and$ls180.v:6498$2057_Y + end + attribute \src "ls180.v:6498.49-6498.156" + cell $and $and$ls180.v:6498$2059 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6498$2057_Y + connect \B $eq$ls180.v:6498$2058_Y + connect \Y $and$ls180.v:6498$2059_Y + end + attribute \src "ls180.v:6500.50-6500.103" + cell $and $and$ls180.v:6500$2060 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B \builder_interface9_bank_bus_we + connect \Y $and$ls180.v:6500$2060_Y + end + attribute \src "ls180.v:6500.49-6500.153" + cell $and $and$ls180.v:6500$2062 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6500$2060_Y + connect \B $eq$ls180.v:6500$2061_Y + connect \Y $and$ls180.v:6500$2062_Y + end + attribute \src "ls180.v:6501.50-6501.106" + cell $and $and$ls180.v:6501$2064 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B $not$ls180.v:6501$2063_Y + connect \Y $and$ls180.v:6501$2064_Y + end + attribute \src "ls180.v:6501.49-6501.156" + cell $and $and$ls180.v:6501$2066 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6501$2064_Y + connect \B $eq$ls180.v:6501$2065_Y + connect \Y $and$ls180.v:6501$2066_Y + end + attribute \src "ls180.v:6503.51-6503.104" + cell $and $and$ls180.v:6503$2067 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B \builder_interface9_bank_bus_we + connect \Y $and$ls180.v:6503$2067_Y + end + attribute \src "ls180.v:6503.50-6503.154" + cell $and $and$ls180.v:6503$2069 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6503$2067_Y + connect \B $eq$ls180.v:6503$2068_Y + connect \Y $and$ls180.v:6503$2069_Y + end + attribute \src "ls180.v:6504.51-6504.107" + cell $and $and$ls180.v:6504$2071 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B $not$ls180.v:6504$2070_Y + connect \Y $and$ls180.v:6504$2071_Y + end + attribute \src "ls180.v:6504.50-6504.157" + cell $and $and$ls180.v:6504$2073 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6504$2071_Y + connect \B $eq$ls180.v:6504$2072_Y + connect \Y $and$ls180.v:6504$2073_Y + end + attribute \src "ls180.v:6506.49-6506.102" + cell $and $and$ls180.v:6506$2074 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B \builder_interface9_bank_bus_we + connect \Y $and$ls180.v:6506$2074_Y + end + attribute \src "ls180.v:6506.48-6506.152" + cell $and $and$ls180.v:6506$2076 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6506$2074_Y + connect \B $eq$ls180.v:6506$2075_Y + connect \Y $and$ls180.v:6506$2076_Y + end + attribute \src "ls180.v:6507.49-6507.105" + cell $and $and$ls180.v:6507$2078 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B $not$ls180.v:6507$2077_Y + connect \Y $and$ls180.v:6507$2078_Y + end + attribute \src "ls180.v:6507.48-6507.155" + cell $and $and$ls180.v:6507$2080 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6507$2078_Y + connect \B $eq$ls180.v:6507$2079_Y + connect \Y $and$ls180.v:6507$2080_Y + end + attribute \src "ls180.v:6509.49-6509.102" + cell $and $and$ls180.v:6509$2081 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B \builder_interface9_bank_bus_we + connect \Y $and$ls180.v:6509$2081_Y + end + attribute \src "ls180.v:6509.48-6509.152" + cell $and $and$ls180.v:6509$2083 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6509$2081_Y + connect \B $eq$ls180.v:6509$2082_Y + connect \Y $and$ls180.v:6509$2083_Y + end + attribute \src "ls180.v:6510.49-6510.105" + cell $and $and$ls180.v:6510$2085 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B $not$ls180.v:6510$2084_Y + connect \Y $and$ls180.v:6510$2085_Y + end + attribute \src "ls180.v:6510.48-6510.155" + cell $and $and$ls180.v:6510$2087 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6510$2085_Y + connect \B $eq$ls180.v:6510$2086_Y + connect \Y $and$ls180.v:6510$2087_Y + end + attribute \src "ls180.v:6512.49-6512.102" + cell $and $and$ls180.v:6512$2088 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B \builder_interface9_bank_bus_we + connect \Y $and$ls180.v:6512$2088_Y + end + attribute \src "ls180.v:6512.48-6512.152" + cell $and $and$ls180.v:6512$2090 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6512$2088_Y + connect \B $eq$ls180.v:6512$2089_Y + connect \Y $and$ls180.v:6512$2090_Y + end + attribute \src "ls180.v:6513.49-6513.105" + cell $and $and$ls180.v:6513$2092 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B $not$ls180.v:6513$2091_Y + connect \Y $and$ls180.v:6513$2092_Y + end + attribute \src "ls180.v:6513.48-6513.155" + cell $and $and$ls180.v:6513$2094 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6513$2092_Y + connect \B $eq$ls180.v:6513$2093_Y + connect \Y $and$ls180.v:6513$2094_Y + end + attribute \src "ls180.v:6515.49-6515.102" + cell $and $and$ls180.v:6515$2095 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B \builder_interface9_bank_bus_we + connect \Y $and$ls180.v:6515$2095_Y + end + attribute \src "ls180.v:6515.48-6515.152" + cell $and $and$ls180.v:6515$2097 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6515$2095_Y + connect \B $eq$ls180.v:6515$2096_Y + connect \Y $and$ls180.v:6515$2097_Y + end + attribute \src "ls180.v:6516.49-6516.105" + cell $and $and$ls180.v:6516$2099 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank9_sel + connect \B $not$ls180.v:6516$2098_Y + connect \Y $and$ls180.v:6516$2099_Y + end + attribute \src "ls180.v:6516.48-6516.155" + cell $and $and$ls180.v:6516$2101 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6516$2099_Y + connect \B $eq$ls180.v:6516$2100_Y + connect \Y $and$ls180.v:6516$2101_Y + end + attribute \src "ls180.v:6533.42-6533.97" + cell $and $and$ls180.v:6533$2103 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank10_sel + connect \B \builder_interface10_bank_bus_we + connect \Y $and$ls180.v:6533$2103_Y + end + attribute \src "ls180.v:6533.41-6533.148" + cell $and $and$ls180.v:6533$2105 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6533$2103_Y + connect \B $eq$ls180.v:6533$2104_Y + connect \Y $and$ls180.v:6533$2105_Y + end + attribute \src "ls180.v:6534.42-6534.100" + cell $and $and$ls180.v:6534$2107 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank10_sel + connect \B $not$ls180.v:6534$2106_Y + connect \Y $and$ls180.v:6534$2107_Y + end + attribute \src "ls180.v:6534.41-6534.151" + cell $and $and$ls180.v:6534$2109 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6534$2107_Y + connect \B $eq$ls180.v:6534$2108_Y + connect \Y $and$ls180.v:6534$2109_Y + end + attribute \src "ls180.v:6536.42-6536.97" + cell $and $and$ls180.v:6536$2110 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank10_sel + connect \B \builder_interface10_bank_bus_we + connect \Y $and$ls180.v:6536$2110_Y + end + attribute \src "ls180.v:6536.41-6536.148" + cell $and $and$ls180.v:6536$2112 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6536$2110_Y + connect \B $eq$ls180.v:6536$2111_Y + connect \Y $and$ls180.v:6536$2112_Y + end + attribute \src "ls180.v:6537.42-6537.100" + cell $and $and$ls180.v:6537$2114 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank10_sel + connect \B $not$ls180.v:6537$2113_Y + connect \Y $and$ls180.v:6537$2114_Y + end + attribute \src "ls180.v:6537.41-6537.151" + cell $and $and$ls180.v:6537$2116 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6537$2114_Y + connect \B $eq$ls180.v:6537$2115_Y + connect \Y $and$ls180.v:6537$2116_Y + end + attribute \src "ls180.v:6539.40-6539.95" + cell $and $and$ls180.v:6539$2117 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank10_sel + connect \B \builder_interface10_bank_bus_we + connect \Y $and$ls180.v:6539$2117_Y + end + attribute \src "ls180.v:6539.39-6539.146" + cell $and $and$ls180.v:6539$2119 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6539$2117_Y + connect \B $eq$ls180.v:6539$2118_Y + connect \Y $and$ls180.v:6539$2119_Y + end + attribute \src "ls180.v:6540.40-6540.98" + cell $and $and$ls180.v:6540$2121 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank10_sel + connect \B $not$ls180.v:6540$2120_Y + connect \Y $and$ls180.v:6540$2121_Y + end + attribute \src "ls180.v:6540.39-6540.149" + cell $and $and$ls180.v:6540$2123 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6540$2121_Y + connect \B $eq$ls180.v:6540$2122_Y + connect \Y $and$ls180.v:6540$2123_Y + end + attribute \src "ls180.v:6542.39-6542.94" + cell $and $and$ls180.v:6542$2124 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank10_sel + connect \B \builder_interface10_bank_bus_we + connect \Y $and$ls180.v:6542$2124_Y + end + attribute \src "ls180.v:6542.38-6542.145" + cell $and $and$ls180.v:6542$2126 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6542$2124_Y + connect \B $eq$ls180.v:6542$2125_Y + connect \Y $and$ls180.v:6542$2126_Y + end + attribute \src "ls180.v:6543.39-6543.97" + cell $and $and$ls180.v:6543$2128 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank10_sel + connect \B $not$ls180.v:6543$2127_Y + connect \Y $and$ls180.v:6543$2128_Y + end + attribute \src "ls180.v:6543.38-6543.148" + cell $and $and$ls180.v:6543$2130 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6543$2128_Y + connect \B $eq$ls180.v:6543$2129_Y + connect \Y $and$ls180.v:6543$2130_Y + end + attribute \src "ls180.v:6545.38-6545.93" + cell $and $and$ls180.v:6545$2131 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank10_sel + connect \B \builder_interface10_bank_bus_we + connect \Y $and$ls180.v:6545$2131_Y + end + attribute \src "ls180.v:6545.37-6545.144" + cell $and $and$ls180.v:6545$2133 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6545$2131_Y + connect \B $eq$ls180.v:6545$2132_Y + connect \Y $and$ls180.v:6545$2133_Y + end + attribute \src "ls180.v:6546.38-6546.96" + cell $and $and$ls180.v:6546$2135 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank10_sel + connect \B $not$ls180.v:6546$2134_Y + connect \Y $and$ls180.v:6546$2135_Y + end + attribute \src "ls180.v:6546.37-6546.147" + cell $and $and$ls180.v:6546$2137 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6546$2135_Y + connect \B $eq$ls180.v:6546$2136_Y + connect \Y $and$ls180.v:6546$2137_Y + end + attribute \src "ls180.v:6548.37-6548.92" + cell $and $and$ls180.v:6548$2138 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank10_sel + connect \B \builder_interface10_bank_bus_we + connect \Y $and$ls180.v:6548$2138_Y + end + attribute \src "ls180.v:6548.36-6548.143" + cell $and $and$ls180.v:6548$2140 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6548$2138_Y + connect \B $eq$ls180.v:6548$2139_Y + connect \Y $and$ls180.v:6548$2140_Y + end + attribute \src "ls180.v:6549.37-6549.95" + cell $and $and$ls180.v:6549$2142 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank10_sel + connect \B $not$ls180.v:6549$2141_Y + connect \Y $and$ls180.v:6549$2142_Y + end + attribute \src "ls180.v:6549.36-6549.146" + cell $and $and$ls180.v:6549$2144 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6549$2142_Y + connect \B $eq$ls180.v:6549$2143_Y + connect \Y $and$ls180.v:6549$2144_Y + end + attribute \src "ls180.v:6551.43-6551.98" + cell $and $and$ls180.v:6551$2145 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank10_sel + connect \B \builder_interface10_bank_bus_we + connect \Y $and$ls180.v:6551$2145_Y + end + attribute \src "ls180.v:6551.42-6551.149" + cell $and $and$ls180.v:6551$2147 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6551$2145_Y + connect \B $eq$ls180.v:6551$2146_Y + connect \Y $and$ls180.v:6551$2147_Y + end + attribute \src "ls180.v:6552.43-6552.101" + cell $and $and$ls180.v:6552$2149 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank10_sel + connect \B $not$ls180.v:6552$2148_Y + connect \Y $and$ls180.v:6552$2149_Y + end + attribute \src "ls180.v:6552.42-6552.152" + cell $and $and$ls180.v:6552$2151 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6552$2149_Y + connect \B $eq$ls180.v:6552$2150_Y + connect \Y $and$ls180.v:6552$2151_Y + end + attribute \src "ls180.v:6573.42-6573.97" + cell $and $and$ls180.v:6573$2154 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B \builder_interface11_bank_bus_we + connect \Y $and$ls180.v:6573$2154_Y + end + attribute \src "ls180.v:6573.41-6573.148" + cell $and $and$ls180.v:6573$2156 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6573$2154_Y + connect \B $eq$ls180.v:6573$2155_Y + connect \Y $and$ls180.v:6573$2156_Y + end + attribute \src "ls180.v:6574.42-6574.100" + cell $and $and$ls180.v:6574$2158 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B $not$ls180.v:6574$2157_Y + connect \Y $and$ls180.v:6574$2158_Y + end + attribute \src "ls180.v:6574.41-6574.151" + cell $and $and$ls180.v:6574$2160 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6574$2158_Y + connect \B $eq$ls180.v:6574$2159_Y + connect \Y $and$ls180.v:6574$2160_Y + end + attribute \src "ls180.v:6576.42-6576.97" + cell $and $and$ls180.v:6576$2161 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B \builder_interface11_bank_bus_we + connect \Y $and$ls180.v:6576$2161_Y + end + attribute \src "ls180.v:6576.41-6576.148" + cell $and $and$ls180.v:6576$2163 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6576$2161_Y + connect \B $eq$ls180.v:6576$2162_Y + connect \Y $and$ls180.v:6576$2163_Y + end + attribute \src "ls180.v:6577.42-6577.100" + cell $and $and$ls180.v:6577$2165 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B $not$ls180.v:6577$2164_Y + connect \Y $and$ls180.v:6577$2165_Y + end + attribute \src "ls180.v:6577.41-6577.151" + cell $and $and$ls180.v:6577$2167 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6577$2165_Y + connect \B $eq$ls180.v:6577$2166_Y + connect \Y $and$ls180.v:6577$2167_Y + end + attribute \src "ls180.v:6579.40-6579.95" + cell $and $and$ls180.v:6579$2168 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B \builder_interface11_bank_bus_we + connect \Y $and$ls180.v:6579$2168_Y + end + attribute \src "ls180.v:6579.39-6579.146" + cell $and $and$ls180.v:6579$2170 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6579$2168_Y + connect \B $eq$ls180.v:6579$2169_Y + connect \Y $and$ls180.v:6579$2170_Y + end + attribute \src "ls180.v:6580.40-6580.98" + cell $and $and$ls180.v:6580$2172 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B $not$ls180.v:6580$2171_Y + connect \Y $and$ls180.v:6580$2172_Y + end + attribute \src "ls180.v:6580.39-6580.149" + cell $and $and$ls180.v:6580$2174 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6580$2172_Y + connect \B $eq$ls180.v:6580$2173_Y + connect \Y $and$ls180.v:6580$2174_Y + end + attribute \src "ls180.v:6582.39-6582.94" + cell $and $and$ls180.v:6582$2175 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B \builder_interface11_bank_bus_we + connect \Y $and$ls180.v:6582$2175_Y + end + attribute \src "ls180.v:6582.38-6582.145" + cell $and $and$ls180.v:6582$2177 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6582$2175_Y + connect \B $eq$ls180.v:6582$2176_Y + connect \Y $and$ls180.v:6582$2177_Y + end + attribute \src "ls180.v:6583.39-6583.97" + cell $and $and$ls180.v:6583$2179 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B $not$ls180.v:6583$2178_Y + connect \Y $and$ls180.v:6583$2179_Y + end + attribute \src "ls180.v:6583.38-6583.148" + cell $and $and$ls180.v:6583$2181 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6583$2179_Y + connect \B $eq$ls180.v:6583$2180_Y + connect \Y $and$ls180.v:6583$2181_Y + end + attribute \src "ls180.v:6585.38-6585.93" + cell $and $and$ls180.v:6585$2182 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B \builder_interface11_bank_bus_we + connect \Y $and$ls180.v:6585$2182_Y + end + attribute \src "ls180.v:6585.37-6585.144" + cell $and $and$ls180.v:6585$2184 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6585$2182_Y + connect \B $eq$ls180.v:6585$2183_Y + connect \Y $and$ls180.v:6585$2184_Y + end + attribute \src "ls180.v:6586.38-6586.96" + cell $and $and$ls180.v:6586$2186 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B $not$ls180.v:6586$2185_Y + connect \Y $and$ls180.v:6586$2186_Y + end + attribute \src "ls180.v:6586.37-6586.147" + cell $and $and$ls180.v:6586$2188 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6586$2186_Y + connect \B $eq$ls180.v:6586$2187_Y + connect \Y $and$ls180.v:6586$2188_Y + end + attribute \src "ls180.v:6588.37-6588.92" + cell $and $and$ls180.v:6588$2189 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B \builder_interface11_bank_bus_we + connect \Y $and$ls180.v:6588$2189_Y + end + attribute \src "ls180.v:6588.36-6588.143" + cell $and $and$ls180.v:6588$2191 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6588$2189_Y + connect \B $eq$ls180.v:6588$2190_Y + connect \Y $and$ls180.v:6588$2191_Y + end + attribute \src "ls180.v:6589.37-6589.95" + cell $and $and$ls180.v:6589$2193 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B $not$ls180.v:6589$2192_Y + connect \Y $and$ls180.v:6589$2193_Y + end + attribute \src "ls180.v:6589.36-6589.146" + cell $and $and$ls180.v:6589$2195 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6589$2193_Y + connect \B $eq$ls180.v:6589$2194_Y + connect \Y $and$ls180.v:6589$2195_Y + end + attribute \src "ls180.v:6591.43-6591.98" + cell $and $and$ls180.v:6591$2196 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B \builder_interface11_bank_bus_we + connect \Y $and$ls180.v:6591$2196_Y + end + attribute \src "ls180.v:6591.42-6591.149" + cell $and $and$ls180.v:6591$2198 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6591$2196_Y + connect \B $eq$ls180.v:6591$2197_Y + connect \Y $and$ls180.v:6591$2198_Y + end + attribute \src "ls180.v:6592.43-6592.101" + cell $and $and$ls180.v:6592$2200 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B $not$ls180.v:6592$2199_Y + connect \Y $and$ls180.v:6592$2200_Y + end + attribute \src "ls180.v:6592.42-6592.152" + cell $and $and$ls180.v:6592$2202 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6592$2200_Y + connect \B $eq$ls180.v:6592$2201_Y + connect \Y $and$ls180.v:6592$2202_Y + end + attribute \src "ls180.v:6594.46-6594.101" + cell $and $and$ls180.v:6594$2203 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B \builder_interface11_bank_bus_we + connect \Y $and$ls180.v:6594$2203_Y + end + attribute \src "ls180.v:6594.45-6594.152" + cell $and $and$ls180.v:6594$2205 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6594$2203_Y + connect \B $eq$ls180.v:6594$2204_Y + connect \Y $and$ls180.v:6594$2205_Y + end + attribute \src "ls180.v:6595.46-6595.104" + cell $and $and$ls180.v:6595$2207 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B $not$ls180.v:6595$2206_Y + connect \Y $and$ls180.v:6595$2207_Y + end + attribute \src "ls180.v:6595.45-6595.155" + cell $and $and$ls180.v:6595$2209 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6595$2207_Y + connect \B $eq$ls180.v:6595$2208_Y + connect \Y $and$ls180.v:6595$2209_Y + end + attribute \src "ls180.v:6597.46-6597.101" + cell $and $and$ls180.v:6597$2210 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B \builder_interface11_bank_bus_we + connect \Y $and$ls180.v:6597$2210_Y + end + attribute \src "ls180.v:6597.45-6597.152" + cell $and $and$ls180.v:6597$2212 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6597$2210_Y + connect \B $eq$ls180.v:6597$2211_Y + connect \Y $and$ls180.v:6597$2212_Y + end + attribute \src "ls180.v:6598.46-6598.104" + cell $and $and$ls180.v:6598$2214 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B $not$ls180.v:6598$2213_Y + connect \Y $and$ls180.v:6598$2214_Y + end + attribute \src "ls180.v:6598.45-6598.155" + cell $and $and$ls180.v:6598$2216 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6598$2214_Y + connect \B $eq$ls180.v:6598$2215_Y + connect \Y $and$ls180.v:6598$2216_Y + end + attribute \src "ls180.v:6621.39-6621.94" + cell $and $and$ls180.v:6621$2219 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B \builder_interface12_bank_bus_we + connect \Y $and$ls180.v:6621$2219_Y + end + attribute \src "ls180.v:6621.38-6621.145" + cell $and $and$ls180.v:6621$2221 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6621$2219_Y + connect \B $eq$ls180.v:6621$2220_Y + connect \Y $and$ls180.v:6621$2221_Y + end + attribute \src "ls180.v:6622.39-6622.97" + cell $and $and$ls180.v:6622$2223 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B $not$ls180.v:6622$2222_Y + connect \Y $and$ls180.v:6622$2223_Y + end + attribute \src "ls180.v:6622.38-6622.148" + cell $and $and$ls180.v:6622$2225 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6622$2223_Y + connect \B $eq$ls180.v:6622$2224_Y + connect \Y $and$ls180.v:6622$2225_Y + end + attribute \src "ls180.v:6624.39-6624.94" + cell $and $and$ls180.v:6624$2226 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B \builder_interface12_bank_bus_we + connect \Y $and$ls180.v:6624$2226_Y + end + attribute \src "ls180.v:6624.38-6624.145" + cell $and $and$ls180.v:6624$2228 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6624$2226_Y + connect \B $eq$ls180.v:6624$2227_Y + connect \Y $and$ls180.v:6624$2228_Y + end + attribute \src "ls180.v:6625.39-6625.97" + cell $and $and$ls180.v:6625$2230 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B $not$ls180.v:6625$2229_Y + connect \Y $and$ls180.v:6625$2230_Y + end + attribute \src "ls180.v:6625.38-6625.148" + cell $and $and$ls180.v:6625$2232 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6625$2230_Y + connect \B $eq$ls180.v:6625$2231_Y + connect \Y $and$ls180.v:6625$2232_Y + end + attribute \src "ls180.v:6627.39-6627.94" + cell $and $and$ls180.v:6627$2233 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B \builder_interface12_bank_bus_we + connect \Y $and$ls180.v:6627$2233_Y + end + attribute \src "ls180.v:6627.38-6627.145" + cell $and $and$ls180.v:6627$2235 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6627$2233_Y + connect \B $eq$ls180.v:6627$2234_Y + connect \Y $and$ls180.v:6627$2235_Y + end + attribute \src "ls180.v:6628.39-6628.97" + cell $and $and$ls180.v:6628$2237 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B $not$ls180.v:6628$2236_Y + connect \Y $and$ls180.v:6628$2237_Y + end + attribute \src "ls180.v:6628.38-6628.148" + cell $and $and$ls180.v:6628$2239 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6628$2237_Y + connect \B $eq$ls180.v:6628$2238_Y + connect \Y $and$ls180.v:6628$2239_Y + end + attribute \src "ls180.v:6630.39-6630.94" + cell $and $and$ls180.v:6630$2240 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B \builder_interface12_bank_bus_we + connect \Y $and$ls180.v:6630$2240_Y + end + attribute \src "ls180.v:6630.38-6630.145" + cell $and $and$ls180.v:6630$2242 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6630$2240_Y + connect \B $eq$ls180.v:6630$2241_Y + connect \Y $and$ls180.v:6630$2242_Y + end + attribute \src "ls180.v:6631.39-6631.97" + cell $and $and$ls180.v:6631$2244 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B $not$ls180.v:6631$2243_Y + connect \Y $and$ls180.v:6631$2244_Y + end + attribute \src "ls180.v:6631.38-6631.148" + cell $and $and$ls180.v:6631$2246 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6631$2244_Y + connect \B $eq$ls180.v:6631$2245_Y + connect \Y $and$ls180.v:6631$2246_Y + end + attribute \src "ls180.v:6633.41-6633.96" + cell $and $and$ls180.v:6633$2247 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B \builder_interface12_bank_bus_we + connect \Y $and$ls180.v:6633$2247_Y + end + attribute \src "ls180.v:6633.40-6633.147" + cell $and $and$ls180.v:6633$2249 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6633$2247_Y + connect \B $eq$ls180.v:6633$2248_Y + connect \Y $and$ls180.v:6633$2249_Y + end + attribute \src "ls180.v:6634.41-6634.99" + cell $and $and$ls180.v:6634$2251 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B $not$ls180.v:6634$2250_Y + connect \Y $and$ls180.v:6634$2251_Y + end + attribute \src "ls180.v:6634.40-6634.150" + cell $and $and$ls180.v:6634$2253 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6634$2251_Y + connect \B $eq$ls180.v:6634$2252_Y + connect \Y $and$ls180.v:6634$2253_Y + end + attribute \src "ls180.v:6636.41-6636.96" + cell $and $and$ls180.v:6636$2254 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B \builder_interface12_bank_bus_we + connect \Y $and$ls180.v:6636$2254_Y + end + attribute \src "ls180.v:6636.40-6636.147" + cell $and $and$ls180.v:6636$2256 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6636$2254_Y + connect \B $eq$ls180.v:6636$2255_Y + connect \Y $and$ls180.v:6636$2256_Y + end + attribute \src "ls180.v:6637.41-6637.99" + cell $and $and$ls180.v:6637$2258 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B $not$ls180.v:6637$2257_Y + connect \Y $and$ls180.v:6637$2258_Y + end + attribute \src "ls180.v:6637.40-6637.150" + cell $and $and$ls180.v:6637$2260 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6637$2258_Y + connect \B $eq$ls180.v:6637$2259_Y + connect \Y $and$ls180.v:6637$2260_Y + end + attribute \src "ls180.v:6639.41-6639.96" + cell $and $and$ls180.v:6639$2261 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B \builder_interface12_bank_bus_we + connect \Y $and$ls180.v:6639$2261_Y + end + attribute \src "ls180.v:6639.40-6639.147" + cell $and $and$ls180.v:6639$2263 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6639$2261_Y + connect \B $eq$ls180.v:6639$2262_Y + connect \Y $and$ls180.v:6639$2263_Y + end + attribute \src "ls180.v:6640.41-6640.99" + cell $and $and$ls180.v:6640$2265 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B $not$ls180.v:6640$2264_Y + connect \Y $and$ls180.v:6640$2265_Y + end + attribute \src "ls180.v:6640.40-6640.150" + cell $and $and$ls180.v:6640$2267 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6640$2265_Y + connect \B $eq$ls180.v:6640$2266_Y + connect \Y $and$ls180.v:6640$2267_Y + end + attribute \src "ls180.v:6642.41-6642.96" + cell $and $and$ls180.v:6642$2268 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B \builder_interface12_bank_bus_we + connect \Y $and$ls180.v:6642$2268_Y + end + attribute \src "ls180.v:6642.40-6642.147" + cell $and $and$ls180.v:6642$2270 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6642$2268_Y + connect \B $eq$ls180.v:6642$2269_Y + connect \Y $and$ls180.v:6642$2270_Y + end + attribute \src "ls180.v:6643.41-6643.99" + cell $and $and$ls180.v:6643$2272 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B $not$ls180.v:6643$2271_Y + connect \Y $and$ls180.v:6643$2272_Y + end + attribute \src "ls180.v:6643.40-6643.150" + cell $and $and$ls180.v:6643$2274 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6643$2272_Y + connect \B $eq$ls180.v:6643$2273_Y + connect \Y $and$ls180.v:6643$2274_Y + end + attribute \src "ls180.v:6645.37-6645.92" + cell $and $and$ls180.v:6645$2275 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B \builder_interface12_bank_bus_we + connect \Y $and$ls180.v:6645$2275_Y + end + attribute \src "ls180.v:6645.36-6645.143" + cell $and $and$ls180.v:6645$2277 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6645$2275_Y + connect \B $eq$ls180.v:6645$2276_Y + connect \Y $and$ls180.v:6645$2277_Y + end + attribute \src "ls180.v:6646.37-6646.95" + cell $and $and$ls180.v:6646$2279 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B $not$ls180.v:6646$2278_Y + connect \Y $and$ls180.v:6646$2279_Y + end + attribute \src "ls180.v:6646.36-6646.146" + cell $and $and$ls180.v:6646$2281 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6646$2279_Y + connect \B $eq$ls180.v:6646$2280_Y + connect \Y $and$ls180.v:6646$2281_Y + end + attribute \src "ls180.v:6648.47-6648.102" + cell $and $and$ls180.v:6648$2282 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B \builder_interface12_bank_bus_we + connect \Y $and$ls180.v:6648$2282_Y + end + attribute \src "ls180.v:6648.46-6648.153" + cell $and $and$ls180.v:6648$2284 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6648$2282_Y + connect \B $eq$ls180.v:6648$2283_Y + connect \Y $and$ls180.v:6648$2284_Y + end + attribute \src "ls180.v:6649.47-6649.105" + cell $and $and$ls180.v:6649$2286 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B $not$ls180.v:6649$2285_Y + connect \Y $and$ls180.v:6649$2286_Y + end + attribute \src "ls180.v:6649.46-6649.156" + cell $and $and$ls180.v:6649$2288 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6649$2286_Y + connect \B $eq$ls180.v:6649$2287_Y + connect \Y $and$ls180.v:6649$2288_Y + end + attribute \src "ls180.v:6651.40-6651.95" + cell $and $and$ls180.v:6651$2289 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B \builder_interface12_bank_bus_we + connect \Y $and$ls180.v:6651$2289_Y + end + attribute \src "ls180.v:6651.39-6651.147" + cell $and $and$ls180.v:6651$2291 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6651$2289_Y + connect \B $eq$ls180.v:6651$2290_Y + connect \Y $and$ls180.v:6651$2291_Y + end + attribute \src "ls180.v:6652.40-6652.98" + cell $and $and$ls180.v:6652$2293 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B $not$ls180.v:6652$2292_Y + connect \Y $and$ls180.v:6652$2293_Y + end + attribute \src "ls180.v:6652.39-6652.150" + cell $and $and$ls180.v:6652$2295 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6652$2293_Y + connect \B $eq$ls180.v:6652$2294_Y + connect \Y $and$ls180.v:6652$2295_Y + end + attribute \src "ls180.v:6654.40-6654.95" + cell $and $and$ls180.v:6654$2296 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B \builder_interface12_bank_bus_we + connect \Y $and$ls180.v:6654$2296_Y + end + attribute \src "ls180.v:6654.39-6654.147" + cell $and $and$ls180.v:6654$2298 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6654$2296_Y + connect \B $eq$ls180.v:6654$2297_Y + connect \Y $and$ls180.v:6654$2298_Y + end + attribute \src "ls180.v:6655.40-6655.98" + cell $and $and$ls180.v:6655$2300 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B $not$ls180.v:6655$2299_Y + connect \Y $and$ls180.v:6655$2300_Y + end + attribute \src "ls180.v:6655.39-6655.150" + cell $and $and$ls180.v:6655$2302 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6655$2300_Y + connect \B $eq$ls180.v:6655$2301_Y + connect \Y $and$ls180.v:6655$2302_Y + end + attribute \src "ls180.v:6657.40-6657.95" + cell $and $and$ls180.v:6657$2303 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B \builder_interface12_bank_bus_we + connect \Y $and$ls180.v:6657$2303_Y + end + attribute \src "ls180.v:6657.39-6657.147" + cell $and $and$ls180.v:6657$2305 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6657$2303_Y + connect \B $eq$ls180.v:6657$2304_Y + connect \Y $and$ls180.v:6657$2305_Y + end + attribute \src "ls180.v:6658.40-6658.98" + cell $and $and$ls180.v:6658$2307 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B $not$ls180.v:6658$2306_Y + connect \Y $and$ls180.v:6658$2307_Y + end + attribute \src "ls180.v:6658.39-6658.150" + cell $and $and$ls180.v:6658$2309 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6658$2307_Y + connect \B $eq$ls180.v:6658$2308_Y + connect \Y $and$ls180.v:6658$2309_Y + end + attribute \src "ls180.v:6660.40-6660.95" + cell $and $and$ls180.v:6660$2310 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B \builder_interface12_bank_bus_we + connect \Y $and$ls180.v:6660$2310_Y + end + attribute \src "ls180.v:6660.39-6660.147" + cell $and $and$ls180.v:6660$2312 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6660$2310_Y + connect \B $eq$ls180.v:6660$2311_Y + connect \Y $and$ls180.v:6660$2312_Y + end + attribute \src "ls180.v:6661.40-6661.98" + cell $and $and$ls180.v:6661$2314 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B $not$ls180.v:6661$2313_Y + connect \Y $and$ls180.v:6661$2314_Y + end + attribute \src "ls180.v:6661.39-6661.150" + cell $and $and$ls180.v:6661$2316 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6661$2314_Y + connect \B $eq$ls180.v:6661$2315_Y + connect \Y $and$ls180.v:6661$2316_Y + end + attribute \src "ls180.v:6663.52-6663.107" + cell $and $and$ls180.v:6663$2317 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B \builder_interface12_bank_bus_we + connect \Y $and$ls180.v:6663$2317_Y + end + attribute \src "ls180.v:6663.51-6663.159" + cell $and $and$ls180.v:6663$2319 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6663$2317_Y + connect \B $eq$ls180.v:6663$2318_Y + connect \Y $and$ls180.v:6663$2319_Y + end + attribute \src "ls180.v:6664.52-6664.110" + cell $and $and$ls180.v:6664$2321 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B $not$ls180.v:6664$2320_Y + connect \Y $and$ls180.v:6664$2321_Y + end + attribute \src "ls180.v:6664.51-6664.162" + cell $and $and$ls180.v:6664$2323 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6664$2321_Y + connect \B $eq$ls180.v:6664$2322_Y + connect \Y $and$ls180.v:6664$2323_Y + end + attribute \src "ls180.v:6666.53-6666.108" + cell $and $and$ls180.v:6666$2324 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B \builder_interface12_bank_bus_we + connect \Y $and$ls180.v:6666$2324_Y + end + attribute \src "ls180.v:6666.52-6666.160" + cell $and $and$ls180.v:6666$2326 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6666$2324_Y + connect \B $eq$ls180.v:6666$2325_Y + connect \Y $and$ls180.v:6666$2326_Y + end + attribute \src "ls180.v:6667.53-6667.111" + cell $and $and$ls180.v:6667$2328 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B $not$ls180.v:6667$2327_Y + connect \Y $and$ls180.v:6667$2328_Y + end + attribute \src "ls180.v:6667.52-6667.163" + cell $and $and$ls180.v:6667$2330 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6667$2328_Y + connect \B $eq$ls180.v:6667$2329_Y + connect \Y $and$ls180.v:6667$2330_Y + end + attribute \src "ls180.v:6669.44-6669.99" + cell $and $and$ls180.v:6669$2331 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B \builder_interface12_bank_bus_we + connect \Y $and$ls180.v:6669$2331_Y + end + attribute \src "ls180.v:6669.43-6669.151" + cell $and $and$ls180.v:6669$2333 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6669$2331_Y + connect \B $eq$ls180.v:6669$2332_Y + connect \Y $and$ls180.v:6669$2333_Y + end + attribute \src "ls180.v:6670.44-6670.102" + cell $and $and$ls180.v:6670$2335 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B $not$ls180.v:6670$2334_Y + connect \Y $and$ls180.v:6670$2335_Y + end + attribute \src "ls180.v:6670.43-6670.154" + cell $and $and$ls180.v:6670$2337 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6670$2335_Y + connect \B $eq$ls180.v:6670$2336_Y + connect \Y $and$ls180.v:6670$2337_Y + end + attribute \src "ls180.v:6689.30-6689.85" + cell $and $and$ls180.v:6689$2339 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank13_sel + connect \B \builder_interface13_bank_bus_we + connect \Y $and$ls180.v:6689$2339_Y + end + attribute \src "ls180.v:6689.29-6689.136" + cell $and $and$ls180.v:6689$2341 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6689$2339_Y + connect \B $eq$ls180.v:6689$2340_Y + connect \Y $and$ls180.v:6689$2341_Y + end + attribute \src "ls180.v:6690.30-6690.88" + cell $and $and$ls180.v:6690$2343 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank13_sel + connect \B $not$ls180.v:6690$2342_Y + connect \Y $and$ls180.v:6690$2343_Y + end + attribute \src "ls180.v:6690.29-6690.139" + cell $and $and$ls180.v:6690$2345 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6690$2343_Y + connect \B $eq$ls180.v:6690$2344_Y + connect \Y $and$ls180.v:6690$2345_Y + end + attribute \src "ls180.v:6692.40-6692.95" + cell $and $and$ls180.v:6692$2346 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank13_sel + connect \B \builder_interface13_bank_bus_we + connect \Y $and$ls180.v:6692$2346_Y + end + attribute \src "ls180.v:6692.39-6692.146" + cell $and $and$ls180.v:6692$2348 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6692$2346_Y + connect \B $eq$ls180.v:6692$2347_Y + connect \Y $and$ls180.v:6692$2348_Y + end + attribute \src "ls180.v:6693.40-6693.98" + cell $and $and$ls180.v:6693$2350 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank13_sel + connect \B $not$ls180.v:6693$2349_Y + connect \Y $and$ls180.v:6693$2350_Y + end + attribute \src "ls180.v:6693.39-6693.149" + cell $and $and$ls180.v:6693$2352 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6693$2350_Y + connect \B $eq$ls180.v:6693$2351_Y + connect \Y $and$ls180.v:6693$2352_Y + end + attribute \src "ls180.v:6695.41-6695.96" + cell $and $and$ls180.v:6695$2353 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank13_sel + connect \B \builder_interface13_bank_bus_we + connect \Y $and$ls180.v:6695$2353_Y + end + attribute \src "ls180.v:6695.40-6695.147" + cell $and $and$ls180.v:6695$2355 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6695$2353_Y + connect \B $eq$ls180.v:6695$2354_Y + connect \Y $and$ls180.v:6695$2355_Y + end + attribute \src "ls180.v:6696.41-6696.99" + cell $and $and$ls180.v:6696$2357 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank13_sel + connect \B $not$ls180.v:6696$2356_Y + connect \Y $and$ls180.v:6696$2357_Y + end + attribute \src "ls180.v:6696.40-6696.150" + cell $and $and$ls180.v:6696$2359 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6696$2357_Y + connect \B $eq$ls180.v:6696$2358_Y + connect \Y $and$ls180.v:6696$2359_Y + end + attribute \src "ls180.v:6698.45-6698.100" + cell $and $and$ls180.v:6698$2360 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank13_sel + connect \B \builder_interface13_bank_bus_we + connect \Y $and$ls180.v:6698$2360_Y + end + attribute \src "ls180.v:6698.44-6698.151" + cell $and $and$ls180.v:6698$2362 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6698$2360_Y + connect \B $eq$ls180.v:6698$2361_Y + connect \Y $and$ls180.v:6698$2362_Y + end + attribute \src "ls180.v:6699.45-6699.103" + cell $and $and$ls180.v:6699$2364 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank13_sel + connect \B $not$ls180.v:6699$2363_Y + connect \Y $and$ls180.v:6699$2364_Y + end + attribute \src "ls180.v:6699.44-6699.154" + cell $and $and$ls180.v:6699$2366 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6699$2364_Y + connect \B $eq$ls180.v:6699$2365_Y + connect \Y $and$ls180.v:6699$2366_Y + end + attribute \src "ls180.v:6701.46-6701.101" + cell $and $and$ls180.v:6701$2367 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank13_sel + connect \B \builder_interface13_bank_bus_we + connect \Y $and$ls180.v:6701$2367_Y + end + attribute \src "ls180.v:6701.45-6701.152" + cell $and $and$ls180.v:6701$2369 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6701$2367_Y + connect \B $eq$ls180.v:6701$2368_Y + connect \Y $and$ls180.v:6701$2369_Y + end + attribute \src "ls180.v:6702.46-6702.104" + cell $and $and$ls180.v:6702$2371 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank13_sel + connect \B $not$ls180.v:6702$2370_Y + connect \Y $and$ls180.v:6702$2371_Y + end + attribute \src "ls180.v:6702.45-6702.155" + cell $and $and$ls180.v:6702$2373 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6702$2371_Y + connect \B $eq$ls180.v:6702$2372_Y + connect \Y $and$ls180.v:6702$2373_Y + end + attribute \src "ls180.v:6704.44-6704.99" + cell $and $and$ls180.v:6704$2374 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank13_sel + connect \B \builder_interface13_bank_bus_we + connect \Y $and$ls180.v:6704$2374_Y + end + attribute \src "ls180.v:6704.43-6704.150" + cell $and $and$ls180.v:6704$2376 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6704$2374_Y + connect \B $eq$ls180.v:6704$2375_Y + connect \Y $and$ls180.v:6704$2376_Y + end + attribute \src "ls180.v:6705.44-6705.102" + cell $and $and$ls180.v:6705$2378 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank13_sel + connect \B $not$ls180.v:6705$2377_Y + connect \Y $and$ls180.v:6705$2378_Y + end + attribute \src "ls180.v:6705.43-6705.153" + cell $and $and$ls180.v:6705$2380 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6705$2378_Y + connect \B $eq$ls180.v:6705$2379_Y + connect \Y $and$ls180.v:6705$2380_Y + end + attribute \src "ls180.v:6707.41-6707.96" + cell $and $and$ls180.v:6707$2381 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank13_sel + connect \B \builder_interface13_bank_bus_we + connect \Y $and$ls180.v:6707$2381_Y + end + attribute \src "ls180.v:6707.40-6707.147" + cell $and $and$ls180.v:6707$2383 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6707$2381_Y + connect \B $eq$ls180.v:6707$2382_Y + connect \Y $and$ls180.v:6707$2383_Y + end + attribute \src "ls180.v:6708.41-6708.99" + cell $and $and$ls180.v:6708$2385 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank13_sel + connect \B $not$ls180.v:6708$2384_Y + connect \Y $and$ls180.v:6708$2385_Y + end + attribute \src "ls180.v:6708.40-6708.150" + cell $and $and$ls180.v:6708$2387 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6708$2385_Y + connect \B $eq$ls180.v:6708$2386_Y + connect \Y $and$ls180.v:6708$2387_Y + end + attribute \src "ls180.v:6710.40-6710.95" + cell $and $and$ls180.v:6710$2388 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank13_sel + connect \B \builder_interface13_bank_bus_we + connect \Y $and$ls180.v:6710$2388_Y + end + attribute \src "ls180.v:6710.39-6710.146" + cell $and $and$ls180.v:6710$2390 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6710$2388_Y + connect \B $eq$ls180.v:6710$2389_Y + connect \Y $and$ls180.v:6710$2390_Y + end + attribute \src "ls180.v:6711.40-6711.98" + cell $and $and$ls180.v:6711$2392 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank13_sel + connect \B $not$ls180.v:6711$2391_Y + connect \Y $and$ls180.v:6711$2392_Y + end + attribute \src "ls180.v:6711.39-6711.149" + cell $and $and$ls180.v:6711$2394 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6711$2392_Y + connect \B $eq$ls180.v:6711$2393_Y + connect \Y $and$ls180.v:6711$2394_Y + end + attribute \src "ls180.v:6723.46-6723.101" + cell $and $and$ls180.v:6723$2396 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank14_sel + connect \B \builder_interface14_bank_bus_we + connect \Y $and$ls180.v:6723$2396_Y + end + attribute \src "ls180.v:6723.45-6723.152" + cell $and $and$ls180.v:6723$2398 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6723$2396_Y + connect \B $eq$ls180.v:6723$2397_Y + connect \Y $and$ls180.v:6723$2398_Y + end + attribute \src "ls180.v:6724.46-6724.104" + cell $and $and$ls180.v:6724$2400 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank14_sel + connect \B $not$ls180.v:6724$2399_Y + connect \Y $and$ls180.v:6724$2400_Y + end + attribute \src "ls180.v:6724.45-6724.155" + cell $and $and$ls180.v:6724$2402 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6724$2400_Y + connect \B $eq$ls180.v:6724$2401_Y + connect \Y $and$ls180.v:6724$2402_Y + end + attribute \src "ls180.v:6726.46-6726.101" + cell $and $and$ls180.v:6726$2403 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank14_sel + connect \B \builder_interface14_bank_bus_we + connect \Y $and$ls180.v:6726$2403_Y + end + attribute \src "ls180.v:6726.45-6726.152" + cell $and $and$ls180.v:6726$2405 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6726$2403_Y + connect \B $eq$ls180.v:6726$2404_Y + connect \Y $and$ls180.v:6726$2405_Y + end + attribute \src "ls180.v:6727.46-6727.104" + cell $and $and$ls180.v:6727$2407 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank14_sel + connect \B $not$ls180.v:6727$2406_Y + connect \Y $and$ls180.v:6727$2407_Y + end + attribute \src "ls180.v:6727.45-6727.155" + cell $and $and$ls180.v:6727$2409 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6727$2407_Y + connect \B $eq$ls180.v:6727$2408_Y + connect \Y $and$ls180.v:6727$2409_Y + end + attribute \src "ls180.v:6729.46-6729.101" + cell $and $and$ls180.v:6729$2410 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank14_sel + connect \B \builder_interface14_bank_bus_we + connect \Y $and$ls180.v:6729$2410_Y + end + attribute \src "ls180.v:6729.45-6729.152" + cell $and $and$ls180.v:6729$2412 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6729$2410_Y + connect \B $eq$ls180.v:6729$2411_Y + connect \Y $and$ls180.v:6729$2412_Y + end + attribute \src "ls180.v:6730.46-6730.104" + cell $and $and$ls180.v:6730$2414 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank14_sel + connect \B $not$ls180.v:6730$2413_Y + connect \Y $and$ls180.v:6730$2414_Y + end + attribute \src "ls180.v:6730.45-6730.155" + cell $and $and$ls180.v:6730$2416 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6730$2414_Y + connect \B $eq$ls180.v:6730$2415_Y + connect \Y $and$ls180.v:6730$2416_Y + end + attribute \src "ls180.v:6732.46-6732.101" + cell $and $and$ls180.v:6732$2417 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank14_sel + connect \B \builder_interface14_bank_bus_we + connect \Y $and$ls180.v:6732$2417_Y + end + attribute \src "ls180.v:6732.45-6732.152" + cell $and $and$ls180.v:6732$2419 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6732$2417_Y + connect \B $eq$ls180.v:6732$2418_Y + connect \Y $and$ls180.v:6732$2419_Y + end + attribute \src "ls180.v:6733.46-6733.104" + cell $and $and$ls180.v:6733$2421 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank14_sel + connect \B $not$ls180.v:6733$2420_Y + connect \Y $and$ls180.v:6733$2421_Y + end + attribute \src "ls180.v:6733.45-6733.155" + cell $and $and$ls180.v:6733$2423 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:6733$2421_Y + connect \B $eq$ls180.v:6733$2422_Y + connect \Y $and$ls180.v:6733$2423_Y + end + attribute \src "ls180.v:7114.109-7114.178" + cell $and $and$ls180.v:7114$2461 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank1_lock + connect \B $eq$ls180.v:7114$2460_Y + connect \Y $and$ls180.v:7114$2461_Y + end + attribute \src "ls180.v:7114.184-7114.253" + cell $and $and$ls180.v:7114$2464 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank2_lock + connect \B $eq$ls180.v:7114$2463_Y + connect \Y $and$ls180.v:7114$2464_Y + end + attribute \src "ls180.v:7114.259-7114.328" + cell $and $and$ls180.v:7114$2467 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank3_lock + connect \B $eq$ls180.v:7114$2466_Y + connect \Y $and$ls180.v:7114$2467_Y + end + attribute \src "ls180.v:7114.40-7114.331" + cell $and $and$ls180.v:7114$2470 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:7114$2459_Y + connect \B $not$ls180.v:7114$2469_Y + connect \Y $and$ls180.v:7114$2470_Y + end + attribute \src "ls180.v:7114.39-7114.354" + cell $and $and$ls180.v:7114$2471 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7114$2470_Y + connect \B \main_port_cmd_valid + connect \Y $and$ls180.v:7114$2471_Y + end + attribute \src "ls180.v:7138.109-7138.178" + cell $and $and$ls180.v:7138$2477 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank0_lock + connect \B $eq$ls180.v:7138$2476_Y + connect \Y $and$ls180.v:7138$2477_Y + end + attribute \src "ls180.v:7138.184-7138.253" + cell $and $and$ls180.v:7138$2480 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank2_lock + connect \B $eq$ls180.v:7138$2479_Y + connect \Y $and$ls180.v:7138$2480_Y + end + attribute \src "ls180.v:7138.259-7138.328" + cell $and $and$ls180.v:7138$2483 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank3_lock + connect \B $eq$ls180.v:7138$2482_Y + connect \Y $and$ls180.v:7138$2483_Y + end + attribute \src "ls180.v:7138.40-7138.331" + cell $and $and$ls180.v:7138$2486 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:7138$2475_Y + connect \B $not$ls180.v:7138$2485_Y + connect \Y $and$ls180.v:7138$2486_Y + end + attribute \src "ls180.v:7138.39-7138.354" + cell $and $and$ls180.v:7138$2487 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7138$2486_Y + connect \B \main_port_cmd_valid + connect \Y $and$ls180.v:7138$2487_Y + end + attribute \src "ls180.v:7162.109-7162.178" + cell $and $and$ls180.v:7162$2493 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank0_lock + connect \B $eq$ls180.v:7162$2492_Y + connect \Y $and$ls180.v:7162$2493_Y + end + attribute \src "ls180.v:7162.184-7162.253" + cell $and $and$ls180.v:7162$2496 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank1_lock + connect \B $eq$ls180.v:7162$2495_Y + connect \Y $and$ls180.v:7162$2496_Y + end + attribute \src "ls180.v:7162.259-7162.328" + cell $and $and$ls180.v:7162$2499 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank3_lock + connect \B $eq$ls180.v:7162$2498_Y + connect \Y $and$ls180.v:7162$2499_Y + end + attribute \src "ls180.v:7162.40-7162.331" + cell $and $and$ls180.v:7162$2502 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:7162$2491_Y + connect \B $not$ls180.v:7162$2501_Y + connect \Y $and$ls180.v:7162$2502_Y + end + attribute \src "ls180.v:7162.39-7162.354" + cell $and $and$ls180.v:7162$2503 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7162$2502_Y + connect \B \main_port_cmd_valid + connect \Y $and$ls180.v:7162$2503_Y + end + attribute \src "ls180.v:7186.109-7186.178" + cell $and $and$ls180.v:7186$2509 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank0_lock + connect \B $eq$ls180.v:7186$2508_Y + connect \Y $and$ls180.v:7186$2509_Y + end + attribute \src "ls180.v:7186.184-7186.253" + cell $and $and$ls180.v:7186$2512 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank1_lock + connect \B $eq$ls180.v:7186$2511_Y + connect \Y $and$ls180.v:7186$2512_Y + end + attribute \src "ls180.v:7186.259-7186.328" + cell $and $and$ls180.v:7186$2515 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank2_lock + connect \B $eq$ls180.v:7186$2514_Y + connect \Y $and$ls180.v:7186$2515_Y + end + attribute \src "ls180.v:7186.40-7186.331" + cell $and $and$ls180.v:7186$2518 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:7186$2507_Y + connect \B $not$ls180.v:7186$2517_Y + connect \Y $and$ls180.v:7186$2518_Y + end + attribute \src "ls180.v:7186.39-7186.354" + cell $and $and$ls180.v:7186$2519 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7186$2518_Y + connect \B \main_port_cmd_valid + connect \Y $and$ls180.v:7186$2519_Y + end + attribute \src "ls180.v:7391.39-7391.104" + cell $and $and$ls180.v:7391$2531 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:7391$2531_Y + end + attribute \src "ls180.v:7391.38-7391.145" + cell $and $and$ls180.v:7391$2532 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7391$2531_Y + connect \B \main_sdram_choose_req_cmd_payload_cas + connect \Y $and$ls180.v:7391$2532_Y + end + attribute \src "ls180.v:7394.39-7394.104" + cell $and $and$ls180.v:7394$2533 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:7394$2533_Y + end + attribute \src "ls180.v:7394.38-7394.145" + cell $and $and$ls180.v:7394$2534 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7394$2533_Y + connect \B \main_sdram_choose_req_cmd_payload_cas + connect \Y $and$ls180.v:7394$2534_Y + end + attribute \src "ls180.v:7397.39-7397.82" + cell $and $and$ls180.v:7397$2535 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_cmd_valid + connect \B \main_sdram_cmd_ready + connect \Y $and$ls180.v:7397$2535_Y + end + attribute \src "ls180.v:7397.38-7397.112" + cell $and $and$ls180.v:7397$2536 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7397$2535_Y + connect \B \main_sdram_cmd_payload_cas + connect \Y $and$ls180.v:7397$2536_Y + end + attribute \src "ls180.v:7408.39-7408.104" + cell $and $and$ls180.v:7408$2538 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:7408$2538_Y + end + attribute \src "ls180.v:7408.38-7408.145" + cell $and $and$ls180.v:7408$2539 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7408$2538_Y + connect \B \main_sdram_choose_req_cmd_payload_ras + connect \Y $and$ls180.v:7408$2539_Y + end + attribute \src "ls180.v:7411.39-7411.104" + cell $and $and$ls180.v:7411$2540 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:7411$2540_Y + end + attribute \src "ls180.v:7411.38-7411.145" + cell $and $and$ls180.v:7411$2541 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7411$2540_Y + connect \B \main_sdram_choose_req_cmd_payload_ras + connect \Y $and$ls180.v:7411$2541_Y + end + attribute \src "ls180.v:7414.39-7414.82" + cell $and $and$ls180.v:7414$2542 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_cmd_valid + connect \B \main_sdram_cmd_ready + connect \Y $and$ls180.v:7414$2542_Y + end + attribute \src "ls180.v:7414.38-7414.112" + cell $and $and$ls180.v:7414$2543 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7414$2542_Y + connect \B \main_sdram_cmd_payload_ras + connect \Y $and$ls180.v:7414$2543_Y + end + attribute \src "ls180.v:7425.39-7425.104" + cell $and $and$ls180.v:7425$2545 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:7425$2545_Y + end + attribute \src "ls180.v:7425.38-7425.144" + cell $and $and$ls180.v:7425$2546 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7425$2545_Y + connect \B \main_sdram_choose_req_cmd_payload_we + connect \Y $and$ls180.v:7425$2546_Y + end + attribute \src "ls180.v:7428.39-7428.104" + cell $and $and$ls180.v:7428$2547 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:7428$2547_Y + end + attribute \src "ls180.v:7428.38-7428.144" + cell $and $and$ls180.v:7428$2548 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7428$2547_Y + connect \B \main_sdram_choose_req_cmd_payload_we + connect \Y $and$ls180.v:7428$2548_Y + end + attribute \src "ls180.v:7431.39-7431.82" + cell $and $and$ls180.v:7431$2549 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_cmd_valid + connect \B \main_sdram_cmd_ready + connect \Y $and$ls180.v:7431$2549_Y + end + attribute \src "ls180.v:7431.38-7431.111" + cell $and $and$ls180.v:7431$2550 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7431$2549_Y + connect \B \main_sdram_cmd_payload_we + connect \Y $and$ls180.v:7431$2550_Y + end + attribute \src "ls180.v:7442.39-7442.104" + cell $and $and$ls180.v:7442$2552 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:7442$2552_Y + end + attribute \src "ls180.v:7442.38-7442.149" + cell $and $and$ls180.v:7442$2553 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7442$2552_Y + connect \B \main_sdram_choose_req_cmd_payload_is_read + connect \Y $and$ls180.v:7442$2553_Y + end + attribute \src "ls180.v:7445.39-7445.104" + cell $and $and$ls180.v:7445$2554 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:7445$2554_Y + end + attribute \src "ls180.v:7445.38-7445.149" + cell $and $and$ls180.v:7445$2555 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7445$2554_Y + connect \B \main_sdram_choose_req_cmd_payload_is_read + connect \Y $and$ls180.v:7445$2555_Y + end + attribute \src "ls180.v:7448.39-7448.82" + cell $and $and$ls180.v:7448$2556 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_cmd_valid + connect \B \main_sdram_cmd_ready + connect \Y $and$ls180.v:7448$2556_Y + end + attribute \src "ls180.v:7448.38-7448.116" + cell $and $and$ls180.v:7448$2557 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7448$2556_Y + connect \B \main_sdram_cmd_payload_is_read + connect \Y $and$ls180.v:7448$2557_Y + end + attribute \src "ls180.v:7459.39-7459.104" + cell $and $and$ls180.v:7459$2559 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:7459$2559_Y + end + attribute \src "ls180.v:7459.38-7459.150" + cell $and $and$ls180.v:7459$2560 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7459$2559_Y + connect \B \main_sdram_choose_req_cmd_payload_is_write + connect \Y $and$ls180.v:7459$2560_Y + end + attribute \src "ls180.v:7462.39-7462.104" + cell $and $and$ls180.v:7462$2561 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:7462$2561_Y + end + attribute \src "ls180.v:7462.38-7462.150" + cell $and $and$ls180.v:7462$2562 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7462$2561_Y + connect \B \main_sdram_choose_req_cmd_payload_is_write + connect \Y $and$ls180.v:7462$2562_Y + end + attribute \src "ls180.v:7465.39-7465.82" + cell $and $and$ls180.v:7465$2563 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_cmd_valid + connect \B \main_sdram_cmd_ready + connect \Y $and$ls180.v:7465$2563_Y + end + attribute \src "ls180.v:7465.38-7465.117" + cell $and $and$ls180.v:7465$2564 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7465$2563_Y + connect \B \main_sdram_cmd_payload_is_write + connect \Y $and$ls180.v:7465$2564_Y + end + attribute \src "ls180.v:7687.17-7687.67" + cell $and $and$ls180.v:7687$2572 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:7687$2571_Y + connect \B \main_sdphy_sdpads_clk + connect \Y $and$ls180.v:7687$2572_Y + end + attribute \src "ls180.v:7766.8-7766.67" + cell $and $and$ls180.v:7766$2603 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_ram_bus_cyc + connect \B \main_libresocsim_ram_bus_stb + connect \Y $and$ls180.v:7766$2603_Y + end + attribute \src "ls180.v:7766.7-7766.102" + cell $and $and$ls180.v:7766$2605 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7766$2603_Y + connect \B $not$ls180.v:7766$2604_Y + connect \Y $and$ls180.v:7766$2605_Y + end + attribute \src "ls180.v:7785.7-7785.75" + cell $and $and$ls180.v:7785$2609 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:7785$2608_Y + connect \B \main_libresocsim_zero_old_trigger + connect \Y $and$ls180.v:7785$2609_Y + end + attribute \src "ls180.v:7789.8-7789.65" + cell $and $and$ls180.v:7789$2610 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface0_ram_bus_cyc + connect \B \main_interface0_ram_bus_stb + connect \Y $and$ls180.v:7789$2610_Y + end + attribute \src "ls180.v:7789.7-7789.99" + cell $and $and$ls180.v:7789$2612 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7789$2610_Y + connect \B $not$ls180.v:7789$2611_Y + connect \Y $and$ls180.v:7789$2612_Y + end + attribute \src "ls180.v:7793.8-7793.65" + cell $and $and$ls180.v:7793$2613 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface1_ram_bus_cyc + connect \B \main_interface1_ram_bus_stb + connect \Y $and$ls180.v:7793$2613_Y + end + attribute \src "ls180.v:7793.7-7793.99" + cell $and $and$ls180.v:7793$2615 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7793$2613_Y + connect \B $not$ls180.v:7793$2614_Y + connect \Y $and$ls180.v:7793$2615_Y + end + attribute \src "ls180.v:7797.8-7797.65" + cell $and $and$ls180.v:7797$2616 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface2_ram_bus_cyc + connect \B \main_interface2_ram_bus_stb + connect \Y $and$ls180.v:7797$2616_Y + end + attribute \src "ls180.v:7797.7-7797.99" + cell $and $and$ls180.v:7797$2618 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7797$2616_Y + connect \B $not$ls180.v:7797$2617_Y + connect \Y $and$ls180.v:7797$2618_Y + end + attribute \src "ls180.v:7801.8-7801.65" + cell $and $and$ls180.v:7801$2619 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface3_ram_bus_cyc + connect \B \main_interface3_ram_bus_stb + connect \Y $and$ls180.v:7801$2619_Y + end + attribute \src "ls180.v:7801.7-7801.99" + cell $and $and$ls180.v:7801$2621 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7801$2619_Y + connect \B $not$ls180.v:7801$2620_Y + connect \Y $and$ls180.v:7801$2621_Y + end + attribute \src "ls180.v:7809.7-7809.56" + cell $and $and$ls180.v:7809$2623 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_timer_wait + connect \B $not$ls180.v:7809$2622_Y + connect \Y $and$ls180.v:7809$2623_Y + end + attribute \src "ls180.v:7837.7-7837.75" + cell $and $and$ls180.v:7837$2630 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_sequencer_start1 + connect \B $eq$ls180.v:7837$2629_Y + connect \Y $and$ls180.v:7837$2630_Y + end + attribute \src "ls180.v:7879.8-7879.131" + cell $and $and$ls180.v:7879$2636 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we + connect \B \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable + connect \Y $and$ls180.v:7879$2636_Y + end + attribute \src "ls180.v:7879.7-7879.190" + cell $and $and$ls180.v:7879$2638 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7879$2636_Y + connect \B $not$ls180.v:7879$2637_Y + connect \Y $and$ls180.v:7879$2638_Y + end + attribute \src "ls180.v:7885.8-7885.131" + cell $and $and$ls180.v:7885$2641 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we + connect \B \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable + connect \Y $and$ls180.v:7885$2641_Y + end + attribute \src "ls180.v:7885.7-7885.190" + cell $and $and$ls180.v:7885$2643 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7885$2641_Y + connect \B $not$ls180.v:7885$2642_Y + connect \Y $and$ls180.v:7885$2643_Y + end + attribute \src "ls180.v:7925.8-7925.131" + cell $and $and$ls180.v:7925$2652 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we + connect \B \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable + connect \Y $and$ls180.v:7925$2652_Y + end + attribute \src "ls180.v:7925.7-7925.190" + cell $and $and$ls180.v:7925$2654 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7925$2652_Y + connect \B $not$ls180.v:7925$2653_Y + connect \Y $and$ls180.v:7925$2654_Y + end + attribute \src "ls180.v:7931.8-7931.131" + cell $and $and$ls180.v:7931$2657 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we + connect \B \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable + connect \Y $and$ls180.v:7931$2657_Y + end + attribute \src "ls180.v:7931.7-7931.190" + cell $and $and$ls180.v:7931$2659 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7931$2657_Y + connect \B $not$ls180.v:7931$2658_Y + connect \Y $and$ls180.v:7931$2659_Y + end + attribute \src "ls180.v:7971.8-7971.131" + cell $and $and$ls180.v:7971$2668 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we + connect \B \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable + connect \Y $and$ls180.v:7971$2668_Y + end + attribute \src "ls180.v:7971.7-7971.190" + cell $and $and$ls180.v:7971$2670 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7971$2668_Y + connect \B $not$ls180.v:7971$2669_Y + connect \Y $and$ls180.v:7971$2670_Y + end + attribute \src "ls180.v:7977.8-7977.131" + cell $and $and$ls180.v:7977$2673 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we + connect \B \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable + connect \Y $and$ls180.v:7977$2673_Y + end + attribute \src "ls180.v:7977.7-7977.190" + cell $and $and$ls180.v:7977$2675 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:7977$2673_Y + connect \B $not$ls180.v:7977$2674_Y + connect \Y $and$ls180.v:7977$2675_Y + end + attribute \src "ls180.v:8017.8-8017.131" + cell $and $and$ls180.v:8017$2684 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we + connect \B \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable + connect \Y $and$ls180.v:8017$2684_Y + end + attribute \src "ls180.v:8017.7-8017.190" + cell $and $and$ls180.v:8017$2686 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:8017$2684_Y + connect \B $not$ls180.v:8017$2685_Y + connect \Y $and$ls180.v:8017$2686_Y + end + attribute \src "ls180.v:8023.8-8023.131" + cell $and $and$ls180.v:8023$2689 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we + connect \B \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable + connect \Y $and$ls180.v:8023$2689_Y + end + attribute \src "ls180.v:8023.7-8023.190" + cell $and $and$ls180.v:8023$2691 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:8023$2689_Y + connect \B $not$ls180.v:8023$2690_Y + connect \Y $and$ls180.v:8023$2691_Y + end + attribute \src "ls180.v:8220.48-8220.124" + cell $and $and$ls180.v:8220$2716 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:8220$2715_Y + connect \B \main_sdram_interface_bank0_wdata_ready + connect \Y $and$ls180.v:8220$2716_Y + end + attribute \src "ls180.v:8220.130-8220.206" + cell $and $and$ls180.v:8220$2719 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:8220$2718_Y + connect \B \main_sdram_interface_bank1_wdata_ready + connect \Y $and$ls180.v:8220$2719_Y + end + attribute \src "ls180.v:8220.212-8220.288" + cell $and $and$ls180.v:8220$2722 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:8220$2721_Y + connect \B \main_sdram_interface_bank2_wdata_ready + connect \Y $and$ls180.v:8220$2722_Y + end + attribute \src "ls180.v:8220.294-8220.370" + cell $and $and$ls180.v:8220$2725 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:8220$2724_Y + connect \B \main_sdram_interface_bank3_wdata_ready + connect \Y $and$ls180.v:8220$2725_Y + end + attribute \src "ls180.v:8221.49-8221.125" + cell $and $and$ls180.v:8221$2728 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:8221$2727_Y + connect \B \main_sdram_interface_bank0_rdata_valid + connect \Y $and$ls180.v:8221$2728_Y + end + attribute \src "ls180.v:8221.131-8221.207" + cell $and $and$ls180.v:8221$2731 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:8221$2730_Y + connect \B \main_sdram_interface_bank1_rdata_valid + connect \Y $and$ls180.v:8221$2731_Y + end + attribute \src "ls180.v:8221.213-8221.289" + cell $and $and$ls180.v:8221$2734 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:8221$2733_Y + connect \B \main_sdram_interface_bank2_rdata_valid + connect \Y $and$ls180.v:8221$2734_Y + end + attribute \src "ls180.v:8221.295-8221.371" + cell $and $and$ls180.v:8221$2737 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:8221$2736_Y + connect \B \main_sdram_interface_bank3_rdata_valid + connect \Y $and$ls180.v:8221$2737_Y + end + attribute \src "ls180.v:8240.8-8240.49" + cell $and $and$ls180.v:8240$2740 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_valid + connect \B \main_port_cmd_ready + connect \Y $and$ls180.v:8240$2740_Y + end + attribute \src "ls180.v:8243.8-8243.53" + cell $and $and$ls180.v:8243$2741 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_port_wdata_valid + connect \B \main_port_wdata_ready + connect \Y $and$ls180.v:8243$2741_Y + end + attribute \src "ls180.v:8248.8-8248.59" + cell $and $and$ls180.v:8248$2743 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_phy_sink_valid + connect \B $not$ls180.v:8248$2742_Y + connect \Y $and$ls180.v:8248$2743_Y + end + attribute \src "ls180.v:8248.7-8248.90" + cell $and $and$ls180.v:8248$2745 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:8248$2743_Y + connect \B $not$ls180.v:8248$2744_Y + connect \Y $and$ls180.v:8248$2745_Y + end + attribute \src "ls180.v:8254.8-8254.59" + cell $and $and$ls180.v:8254$2746 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_phy_uart_clk_txen + connect \B \main_uart_phy_tx_busy + connect \Y $and$ls180.v:8254$2746_Y + end + attribute \src "ls180.v:8278.8-8278.48" + cell $and $and$ls180.v:8278$2753 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:8278$2752_Y + connect \B \main_uart_phy_rx_r + connect \Y $and$ls180.v:8278$2753_Y + end + attribute \src "ls180.v:8311.7-8311.57" + cell $and $and$ls180.v:8311$2759 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:8311$2758_Y + connect \B \main_uart_tx_old_trigger + connect \Y $and$ls180.v:8311$2759_Y + end + attribute \src "ls180.v:8318.7-8318.57" + cell $and $and$ls180.v:8318$2761 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:8318$2760_Y + connect \B \main_uart_rx_old_trigger + connect \Y $and$ls180.v:8318$2761_Y + end + attribute \src "ls180.v:8328.8-8328.75" + cell $and $and$ls180.v:8328$2762 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_tx_fifo_syncfifo_we + connect \B \main_uart_tx_fifo_syncfifo_writable + connect \Y $and$ls180.v:8328$2762_Y + end + attribute \src "ls180.v:8328.7-8328.107" + cell $and $and$ls180.v:8328$2764 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:8328$2762_Y + connect \B $not$ls180.v:8328$2763_Y + connect \Y $and$ls180.v:8328$2764_Y + end + attribute \src "ls180.v:8334.8-8334.75" + cell $and $and$ls180.v:8334$2767 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_tx_fifo_syncfifo_we + connect \B \main_uart_tx_fifo_syncfifo_writable + connect \Y $and$ls180.v:8334$2767_Y + end + attribute \src "ls180.v:8334.7-8334.107" + cell $and $and$ls180.v:8334$2769 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:8334$2767_Y + connect \B $not$ls180.v:8334$2768_Y + connect \Y $and$ls180.v:8334$2769_Y + end + attribute \src "ls180.v:8350.8-8350.75" + cell $and $and$ls180.v:8350$2773 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_rx_fifo_syncfifo_we + connect \B \main_uart_rx_fifo_syncfifo_writable + connect \Y $and$ls180.v:8350$2773_Y + end + attribute \src "ls180.v:8350.7-8350.107" + cell $and $and$ls180.v:8350$2775 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:8350$2773_Y + connect \B $not$ls180.v:8350$2774_Y + connect \Y $and$ls180.v:8350$2775_Y + end + attribute \src "ls180.v:8356.8-8356.75" + cell $and $and$ls180.v:8356$2778 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_rx_fifo_syncfifo_we + connect \B \main_uart_rx_fifo_syncfifo_writable + connect \Y $and$ls180.v:8356$2778_Y + end + attribute \src "ls180.v:8356.7-8356.107" + cell $and $and$ls180.v:8356$2780 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:8356$2778_Y + connect \B $not$ls180.v:8356$2779_Y + connect \Y $and$ls180.v:8356$2780_Y + end + attribute \src "ls180.v:8504.7-8504.96" + cell $and $and$ls180.v:8504$2808 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_cmdr_converter_source_valid + connect \B \main_sdphy_cmdr_cmdr_converter_source_ready + connect \Y $and$ls180.v:8504$2808_Y + end + attribute \src "ls180.v:8505.8-8505.93" + cell $and $and$ls180.v:8505$2809 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_cmdr_converter_sink_valid + connect \B \main_sdphy_cmdr_cmdr_converter_sink_ready + connect \Y $and$ls180.v:8505$2809_Y + end + attribute \src "ls180.v:8513.8-8513.93" + cell $and $and$ls180.v:8513$2810 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_cmdr_converter_sink_valid + connect \B \main_sdphy_cmdr_cmdr_converter_sink_ready + connect \Y $and$ls180.v:8513$2810_Y + end + attribute \src "ls180.v:8585.7-8585.98" + cell $and $and$ls180.v:8585$2820 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_crcr_converter_source_valid + connect \B \main_sdphy_dataw_crcr_converter_source_ready + connect \Y $and$ls180.v:8585$2820_Y + end + attribute \src "ls180.v:8586.8-8586.95" + cell $and $and$ls180.v:8586$2821 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_crcr_converter_sink_valid + connect \B \main_sdphy_dataw_crcr_converter_sink_ready + connect \Y $and$ls180.v:8586$2821_Y + end + attribute \src "ls180.v:8594.8-8594.95" + cell $and $and$ls180.v:8594$2822 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_crcr_converter_sink_valid + connect \B \main_sdphy_dataw_crcr_converter_sink_ready + connect \Y $and$ls180.v:8594$2822_Y + end + attribute \src "ls180.v:8664.7-8664.100" + cell $and $and$ls180.v:8664$2832 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_datar_converter_source_valid + connect \B \main_sdphy_datar_datar_converter_source_ready + connect \Y $and$ls180.v:8664$2832_Y + end + attribute \src "ls180.v:8665.8-8665.97" + cell $and $and$ls180.v:8665$2833 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_datar_converter_sink_valid + connect \B \main_sdphy_datar_datar_converter_sink_ready + connect \Y $and$ls180.v:8665$2833_Y + end + attribute \src "ls180.v:8673.8-8673.97" + cell $and $and$ls180.v:8673$2834 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_datar_converter_sink_valid + connect \B \main_sdphy_datar_datar_converter_sink_ready + connect \Y $and$ls180.v:8673$2834_Y + end + attribute \src "ls180.v:8764.7-8764.82" + cell $and $and$ls180.v:8764$2840 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_sink_ready + connect \B \main_sdcore_crc16_checker_sink_valid + connect \Y $and$ls180.v:8764$2840_Y + end + attribute \src "ls180.v:8767.7-8767.82" + cell $and $and$ls180.v:8767$2841 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_sink_ready + connect \B \main_sdcore_crc16_checker_sink_valid + connect \Y $and$ls180.v:8767$2841_Y + end + attribute \src "ls180.v:8770.7-8770.82" + cell $and $and$ls180.v:8770$2842 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_sink_ready + connect \B \main_sdcore_crc16_checker_sink_valid + connect \Y $and$ls180.v:8770$2842_Y + end + attribute \src "ls180.v:8773.7-8773.82" + cell $and $and$ls180.v:8773$2843 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_sink_ready + connect \B \main_sdcore_crc16_checker_sink_valid + connect \Y $and$ls180.v:8773$2843_Y + end + attribute \src "ls180.v:8776.7-8776.82" + cell $and $and$ls180.v:8776$2844 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_sink_valid + connect \B \main_sdcore_crc16_checker_sink_ready + connect \Y $and$ls180.v:8776$2844_Y + end + attribute \src "ls180.v:8781.7-8781.82" + cell $and $and$ls180.v:8781$2845 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_sink_valid + connect \B \main_sdcore_crc16_checker_sink_ready + connect \Y $and$ls180.v:8781$2845_Y + end + attribute \src "ls180.v:8786.7-8786.82" + cell $and $and$ls180.v:8786$2846 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_sink_valid + connect \B \main_sdcore_crc16_checker_sink_ready + connect \Y $and$ls180.v:8786$2846_Y + end + attribute \src "ls180.v:8791.7-8791.82" + cell $and $and$ls180.v:8791$2847 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_sink_valid + connect \B \main_sdcore_crc16_checker_sink_ready + connect \Y $and$ls180.v:8791$2847_Y + end + attribute \src "ls180.v:8796.7-8796.82" + cell $and $and$ls180.v:8796$2848 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_sink_valid + connect \B \main_sdcore_crc16_checker_sink_ready + connect \Y $and$ls180.v:8796$2848_Y + end + attribute \src "ls180.v:8861.8-8861.83" + cell $and $and$ls180.v:8861$2851 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_fifo_syncfifo_we + connect \B \main_sdblock2mem_fifo_syncfifo_writable + connect \Y $and$ls180.v:8861$2851_Y + end + attribute \src "ls180.v:8861.7-8861.119" + cell $and $and$ls180.v:8861$2853 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:8861$2851_Y + connect \B $not$ls180.v:8861$2852_Y + connect \Y $and$ls180.v:8861$2853_Y + end + attribute \src "ls180.v:8867.8-8867.83" + cell $and $and$ls180.v:8867$2856 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_fifo_syncfifo_we + connect \B \main_sdblock2mem_fifo_syncfifo_writable + connect \Y $and$ls180.v:8867$2856_Y + end + attribute \src "ls180.v:8867.7-8867.119" + cell $and $and$ls180.v:8867$2858 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:8867$2856_Y + connect \B $not$ls180.v:8867$2857_Y + connect \Y $and$ls180.v:8867$2858_Y + end + attribute \src "ls180.v:8887.7-8887.88" + cell $and $and$ls180.v:8887$2865 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_converter_source_valid + connect \B \main_sdblock2mem_converter_source_ready + connect \Y $and$ls180.v:8887$2865_Y + end + attribute \src "ls180.v:8888.8-8888.85" + cell $and $and$ls180.v:8888$2866 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_converter_sink_valid + connect \B \main_sdblock2mem_converter_sink_ready + connect \Y $and$ls180.v:8888$2866_Y + end + attribute \src "ls180.v:8896.8-8896.85" + cell $and $and$ls180.v:8896$2867 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_converter_sink_valid + connect \B \main_sdblock2mem_converter_sink_ready + connect \Y $and$ls180.v:8896$2867_Y + end + attribute \src "ls180.v:8952.7-8952.88" + cell $and $and$ls180.v:8952$2871 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdmem2block_converter_source_valid + connect \B \main_sdmem2block_converter_source_ready + connect \Y $and$ls180.v:8952$2871_Y + end + attribute \src "ls180.v:8959.8-8959.83" + cell $and $and$ls180.v:8959$2873 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdmem2block_fifo_syncfifo_we + connect \B \main_sdmem2block_fifo_syncfifo_writable + connect \Y $and$ls180.v:8959$2873_Y + end + attribute \src "ls180.v:8959.7-8959.119" + cell $and $and$ls180.v:8959$2875 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:8959$2873_Y + connect \B $not$ls180.v:8959$2874_Y + connect \Y $and$ls180.v:8959$2875_Y + end + attribute \src "ls180.v:8965.8-8965.83" + cell $and $and$ls180.v:8965$2878 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdmem2block_fifo_syncfifo_we + connect \B \main_sdmem2block_fifo_syncfifo_writable + connect \Y $and$ls180.v:8965$2878_Y + end + attribute \src "ls180.v:8965.7-8965.119" + cell $and $and$ls180.v:8965$2880 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:8965$2878_Y + connect \B $not$ls180.v:8965$2879_Y + connect \Y $and$ls180.v:8965$2880_Y + end + attribute \src "ls180.v:2927.30-2927.76" + cell $eq $eq$ls180.v:2927$54 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_libresoc_xics_icp_sel + connect \B 1'0 + connect \Y $eq$ls180.v:2927$54_Y + end + attribute \src "ls180.v:2934.11-2934.42" + cell $eq $eq$ls180.v:2934$59 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_converter0_counter + connect \B 1'1 + connect \Y $eq$ls180.v:2934$59_Y + end + attribute \src "ls180.v:2987.30-2987.76" + cell $eq $eq$ls180.v:2987$65 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_libresoc_xics_ics_sel + connect \B 1'0 + connect \Y $eq$ls180.v:2987$65_Y + end + attribute \src "ls180.v:2994.11-2994.42" + cell $eq $eq$ls180.v:2994$70 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_converter1_counter + connect \B 1'1 + connect \Y $eq$ls180.v:2994$70_Y + end + attribute \src "ls180.v:3047.33-3047.58" + cell $eq $eq$ls180.v:3047$76 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_wb_sdram_sel + connect \B 1'0 + connect \Y $eq$ls180.v:3047$76_Y + end + attribute \src "ls180.v:3054.11-3054.45" + cell $eq $eq$ls180.v:3054$81 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_socbushandler_counter + connect \B 1'1 + connect \Y $eq$ls180.v:3054$81_Y + end + attribute \src "ls180.v:3300.34-3300.65" + cell $eq $eq$ls180.v:3300$221 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_timer_count1 + connect \B 1'0 + connect \Y $eq$ls180.v:3300$221_Y + end + attribute \src "ls180.v:3304.68-3304.102" + cell $eq $eq$ls180.v:3304$224 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_sequencer_count + connect \B 1'0 + connect \Y $eq$ls180.v:3304$224_Y + end + attribute \src "ls180.v:3348.43-3348.134" + cell $eq $eq$ls180.v:3348$229 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_row + connect \B \main_sdram_bankmachine0_cmd_buffer_source_payload_addr [21:9] + connect \Y $eq$ls180.v:3348$229_Y + end + attribute \src "ls180.v:3365.47-3365.88" + cell $eq $eq$ls180.v:3365$242 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_row_close + connect \B 1'0 + connect \Y $eq$ls180.v:3365$242_Y + end + attribute \src "ls180.v:3505.43-3505.134" + cell $eq $eq$ls180.v:3505$259 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_row + connect \B \main_sdram_bankmachine1_cmd_buffer_source_payload_addr [21:9] + connect \Y $eq$ls180.v:3505$259_Y + end + attribute \src "ls180.v:3522.47-3522.88" + cell $eq $eq$ls180.v:3522$272 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_row_close + connect \B 1'0 + connect \Y $eq$ls180.v:3522$272_Y + end + attribute \src "ls180.v:3662.43-3662.134" + cell $eq $eq$ls180.v:3662$289 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_row + connect \B \main_sdram_bankmachine2_cmd_buffer_source_payload_addr [21:9] + connect \Y $eq$ls180.v:3662$289_Y + end + attribute \src "ls180.v:3679.47-3679.88" + cell $eq $eq$ls180.v:3679$302 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_row_close + connect \B 1'0 + connect \Y $eq$ls180.v:3679$302_Y + end + attribute \src "ls180.v:3819.43-3819.134" + cell $eq $eq$ls180.v:3819$319 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_row + connect \B \main_sdram_bankmachine3_cmd_buffer_source_payload_addr [21:9] + connect \Y $eq$ls180.v:3819$319_Y + end + attribute \src "ls180.v:3836.47-3836.88" + cell $eq $eq$ls180.v:3836$332 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_row_close + connect \B 1'0 + connect \Y $eq$ls180.v:3836$332_Y + end + attribute \src "ls180.v:3973.32-3973.56" + cell $eq $eq$ls180.v:3973$379 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_time0 + connect \B 1'0 + connect \Y $eq$ls180.v:3973$379_Y + end + attribute \src "ls180.v:3974.32-3974.56" + cell $eq $eq$ls180.v:3974$380 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_time1 + connect \B 1'0 + connect \Y $eq$ls180.v:3974$380_Y + end + attribute \src "ls180.v:3985.339-3985.418" + cell $eq $eq$ls180.v:3985$394 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_payload_is_read + connect \B \main_sdram_choose_cmd_want_reads + connect \Y $eq$ls180.v:3985$394_Y + end + attribute \src "ls180.v:3985.423-3985.504" + cell $eq $eq$ls180.v:3985$395 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_payload_is_write + connect \B \main_sdram_choose_cmd_want_writes + connect \Y $eq$ls180.v:3985$395_Y + end + attribute \src "ls180.v:3986.339-3986.418" + cell $eq $eq$ls180.v:3986$407 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_payload_is_read + connect \B \main_sdram_choose_cmd_want_reads + connect \Y $eq$ls180.v:3986$407_Y + end + attribute \src "ls180.v:3986.423-3986.504" + cell $eq $eq$ls180.v:3986$408 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_payload_is_write + connect \B \main_sdram_choose_cmd_want_writes + connect \Y $eq$ls180.v:3986$408_Y + end + attribute \src "ls180.v:3987.339-3987.418" + cell $eq $eq$ls180.v:3987$420 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_payload_is_read + connect \B \main_sdram_choose_cmd_want_reads + connect \Y $eq$ls180.v:3987$420_Y + end + attribute \src "ls180.v:3987.423-3987.504" + cell $eq $eq$ls180.v:3987$421 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_payload_is_write + connect \B \main_sdram_choose_cmd_want_writes + connect \Y $eq$ls180.v:3987$421_Y + end + attribute \src "ls180.v:3988.339-3988.418" + cell $eq $eq$ls180.v:3988$433 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_payload_is_read + connect \B \main_sdram_choose_cmd_want_reads + connect \Y $eq$ls180.v:3988$433_Y + end + attribute \src "ls180.v:3988.423-3988.504" + cell $eq $eq$ls180.v:3988$434 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_payload_is_write + connect \B \main_sdram_choose_cmd_want_writes + connect \Y $eq$ls180.v:3988$434_Y + end + attribute \src "ls180.v:4018.339-4018.418" + cell $eq $eq$ls180.v:4018$452 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_payload_is_read + connect \B \main_sdram_choose_req_want_reads + connect \Y $eq$ls180.v:4018$452_Y + end + attribute \src "ls180.v:4018.423-4018.504" + cell $eq $eq$ls180.v:4018$453 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_payload_is_write + connect \B \main_sdram_choose_req_want_writes + connect \Y $eq$ls180.v:4018$453_Y + end + attribute \src "ls180.v:4019.339-4019.418" + cell $eq $eq$ls180.v:4019$465 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_payload_is_read + connect \B \main_sdram_choose_req_want_reads + connect \Y $eq$ls180.v:4019$465_Y + end + attribute \src "ls180.v:4019.423-4019.504" + cell $eq $eq$ls180.v:4019$466 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_payload_is_write + connect \B \main_sdram_choose_req_want_writes + connect \Y $eq$ls180.v:4019$466_Y + end + attribute \src "ls180.v:4020.339-4020.418" + cell $eq $eq$ls180.v:4020$478 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_payload_is_read + connect \B \main_sdram_choose_req_want_reads + connect \Y $eq$ls180.v:4020$478_Y + end + attribute \src "ls180.v:4020.423-4020.504" + cell $eq $eq$ls180.v:4020$479 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_payload_is_write + connect \B \main_sdram_choose_req_want_writes + connect \Y $eq$ls180.v:4020$479_Y + end + attribute \src "ls180.v:4021.339-4021.418" + cell $eq $eq$ls180.v:4021$491 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_payload_is_read + connect \B \main_sdram_choose_req_want_reads + connect \Y $eq$ls180.v:4021$491_Y + end + attribute \src "ls180.v:4021.423-4021.504" + cell $eq $eq$ls180.v:4021$492 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_payload_is_write + connect \B \main_sdram_choose_req_want_writes + connect \Y $eq$ls180.v:4021$492_Y + end + attribute \src "ls180.v:4050.78-4050.113" + cell $eq $eq$ls180.v:4050$501 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_cmd_grant + connect \B 1'0 + connect \Y $eq$ls180.v:4050$501_Y + end + attribute \src "ls180.v:4053.78-4053.113" + cell $eq $eq$ls180.v:4053$504 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_grant + connect \B 1'0 + connect \Y $eq$ls180.v:4053$504_Y + end + attribute \src "ls180.v:4059.78-4059.113" + cell $eq $eq$ls180.v:4059$508 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_cmd_grant + connect \B 1'1 + connect \Y $eq$ls180.v:4059$508_Y + end + attribute \src "ls180.v:4062.78-4062.113" + cell $eq $eq$ls180.v:4062$511 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_grant + connect \B 1'1 + connect \Y $eq$ls180.v:4062$511_Y + end + attribute \src "ls180.v:4068.78-4068.113" + cell $eq $eq$ls180.v:4068$515 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_cmd_grant + connect \B 2'10 + connect \Y $eq$ls180.v:4068$515_Y + end + attribute \src "ls180.v:4071.78-4071.113" + cell $eq $eq$ls180.v:4071$518 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_grant + connect \B 2'10 + connect \Y $eq$ls180.v:4071$518_Y + end + attribute \src "ls180.v:4077.78-4077.113" + cell $eq $eq$ls180.v:4077$522 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_cmd_grant + connect \B 2'11 + connect \Y $eq$ls180.v:4077$522_Y + end + attribute \src "ls180.v:4080.78-4080.113" + cell $eq $eq$ls180.v:4080$525 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_grant + connect \B 2'11 + connect \Y $eq$ls180.v:4080$525_Y + end + attribute \src "ls180.v:4161.42-4161.82" + cell $eq $eq$ls180.v:4161$548 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_payload_addr [10:9] + connect \B 1'0 + connect \Y $eq$ls180.v:4161$548_Y + end + attribute \src "ls180.v:4161.145-4161.178" + cell $eq $eq$ls180.v:4161$549 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin1_grant + connect \B 1'0 + connect \Y $eq$ls180.v:4161$549_Y + end + attribute \src "ls180.v:4161.220-4161.253" + cell $eq $eq$ls180.v:4161$552 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin2_grant + connect \B 1'0 + connect \Y $eq$ls180.v:4161$552_Y + end + attribute \src "ls180.v:4161.295-4161.328" + cell $eq $eq$ls180.v:4161$555 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin3_grant + connect \B 1'0 + connect \Y $eq$ls180.v:4161$555_Y + end + attribute \src "ls180.v:4166.42-4166.82" + cell $eq $eq$ls180.v:4166$564 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_payload_addr [10:9] + connect \B 1'1 + connect \Y $eq$ls180.v:4166$564_Y + end + attribute \src "ls180.v:4166.145-4166.178" + cell $eq $eq$ls180.v:4166$565 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin0_grant + connect \B 1'0 + connect \Y $eq$ls180.v:4166$565_Y + end + attribute \src "ls180.v:4166.220-4166.253" + cell $eq $eq$ls180.v:4166$568 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin2_grant + connect \B 1'0 + connect \Y $eq$ls180.v:4166$568_Y + end + attribute \src "ls180.v:4166.295-4166.328" + cell $eq $eq$ls180.v:4166$571 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin3_grant + connect \B 1'0 + connect \Y $eq$ls180.v:4166$571_Y + end + attribute \src "ls180.v:4171.42-4171.82" + cell $eq $eq$ls180.v:4171$580 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_payload_addr [10:9] + connect \B 2'10 + connect \Y $eq$ls180.v:4171$580_Y + end + attribute \src "ls180.v:4171.145-4171.178" + cell $eq $eq$ls180.v:4171$581 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin0_grant + connect \B 1'0 + connect \Y $eq$ls180.v:4171$581_Y + end + attribute \src "ls180.v:4171.220-4171.253" + cell $eq $eq$ls180.v:4171$584 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin1_grant + connect \B 1'0 + connect \Y $eq$ls180.v:4171$584_Y + end + attribute \src "ls180.v:4171.295-4171.328" + cell $eq $eq$ls180.v:4171$587 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin3_grant + connect \B 1'0 + connect \Y $eq$ls180.v:4171$587_Y + end + attribute \src "ls180.v:4176.42-4176.82" + cell $eq $eq$ls180.v:4176$596 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_payload_addr [10:9] + connect \B 2'11 + connect \Y $eq$ls180.v:4176$596_Y + end + attribute \src "ls180.v:4176.145-4176.178" + cell $eq $eq$ls180.v:4176$597 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin0_grant + connect \B 1'0 + connect \Y $eq$ls180.v:4176$597_Y + end + attribute \src "ls180.v:4176.220-4176.253" + cell $eq $eq$ls180.v:4176$600 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin1_grant + connect \B 1'0 + connect \Y $eq$ls180.v:4176$600_Y + end + attribute \src "ls180.v:4176.295-4176.328" + cell $eq $eq$ls180.v:4176$603 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin2_grant + connect \B 1'0 + connect \Y $eq$ls180.v:4176$603_Y + end + attribute \src "ls180.v:4181.44-4181.77" + cell $eq $eq$ls180.v:4181$612 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin0_grant + connect \B 1'0 + connect \Y $eq$ls180.v:4181$612_Y + end + attribute \src "ls180.v:4181.83-4181.123" + cell $eq $eq$ls180.v:4181$613 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_payload_addr [10:9] + connect \B 1'0 + connect \Y $eq$ls180.v:4181$613_Y + end + attribute \src "ls180.v:4181.186-4181.219" + cell $eq $eq$ls180.v:4181$614 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin1_grant + connect \B 1'0 + connect \Y $eq$ls180.v:4181$614_Y + end + attribute \src "ls180.v:4181.261-4181.294" + cell $eq $eq$ls180.v:4181$617 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin2_grant + connect \B 1'0 + connect \Y $eq$ls180.v:4181$617_Y + end + attribute \src "ls180.v:4181.336-4181.369" + cell $eq $eq$ls180.v:4181$620 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin3_grant + connect \B 1'0 + connect \Y $eq$ls180.v:4181$620_Y + end + attribute \src "ls180.v:4181.418-4181.451" + cell $eq $eq$ls180.v:4181$628 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin1_grant + connect \B 1'0 + connect \Y $eq$ls180.v:4181$628_Y + end + attribute \src "ls180.v:4181.457-4181.497" + cell $eq $eq$ls180.v:4181$629 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_payload_addr [10:9] + connect \B 1'1 + connect \Y $eq$ls180.v:4181$629_Y + end + attribute \src "ls180.v:4181.560-4181.593" + cell $eq $eq$ls180.v:4181$630 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin0_grant + connect \B 1'0 + connect \Y $eq$ls180.v:4181$630_Y + end + attribute \src "ls180.v:4181.635-4181.668" + cell $eq $eq$ls180.v:4181$633 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin2_grant + connect \B 1'0 + connect \Y $eq$ls180.v:4181$633_Y + end + attribute \src "ls180.v:4181.710-4181.743" + cell $eq $eq$ls180.v:4181$636 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin3_grant + connect \B 1'0 + connect \Y $eq$ls180.v:4181$636_Y + end + attribute \src "ls180.v:4181.792-4181.825" + cell $eq $eq$ls180.v:4181$644 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin2_grant + connect \B 1'0 + connect \Y $eq$ls180.v:4181$644_Y + end + attribute \src "ls180.v:4181.831-4181.871" + cell $eq $eq$ls180.v:4181$645 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_payload_addr [10:9] + connect \B 2'10 + connect \Y $eq$ls180.v:4181$645_Y + end + attribute \src "ls180.v:4181.934-4181.967" + cell $eq $eq$ls180.v:4181$646 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin0_grant + connect \B 1'0 + connect \Y $eq$ls180.v:4181$646_Y + end + attribute \src "ls180.v:4181.1009-4181.1042" + cell $eq $eq$ls180.v:4181$649 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin1_grant + connect \B 1'0 + connect \Y $eq$ls180.v:4181$649_Y + end + attribute \src "ls180.v:4181.1084-4181.1117" + cell $eq $eq$ls180.v:4181$652 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin3_grant + connect \B 1'0 + connect \Y $eq$ls180.v:4181$652_Y + end + attribute \src "ls180.v:4181.1166-4181.1199" + cell $eq $eq$ls180.v:4181$660 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin3_grant + connect \B 1'0 + connect \Y $eq$ls180.v:4181$660_Y + end + attribute \src "ls180.v:4181.1205-4181.1245" + cell $eq $eq$ls180.v:4181$661 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_payload_addr [10:9] + connect \B 2'11 + connect \Y $eq$ls180.v:4181$661_Y + end + attribute \src "ls180.v:4181.1308-4181.1341" + cell $eq $eq$ls180.v:4181$662 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin0_grant + connect \B 1'0 + connect \Y $eq$ls180.v:4181$662_Y + end + attribute \src "ls180.v:4181.1383-4181.1416" + cell $eq $eq$ls180.v:4181$665 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin1_grant + connect \B 1'0 + connect \Y $eq$ls180.v:4181$665_Y + end + attribute \src "ls180.v:4181.1458-4181.1491" + cell $eq $eq$ls180.v:4181$668 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin2_grant + connect \B 1'0 + connect \Y $eq$ls180.v:4181$668_Y + end + attribute \src "ls180.v:4240.29-4240.57" + cell $eq $eq$ls180.v:4240$681 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_litedram_wb_sel + connect \B 1'0 + connect \Y $eq$ls180.v:4240$681_Y + end + attribute \src "ls180.v:4247.11-4247.41" + cell $eq $eq$ls180.v:4247$686 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_converter_counter + connect \B 1'1 + connect \Y $eq$ls180.v:4247$686_Y + end + attribute \src "ls180.v:4415.37-4415.111" + cell $eq $eq$ls180.v:4415$753 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 16 + parameter \Y_WIDTH 1 + connect \A \main_spimaster30_clk_divider + connect \B $sub$ls180.v:4415$752_Y + connect \Y $eq$ls180.v:4415$753_Y + end + attribute \src "ls180.v:4416.37-4416.105" + cell $eq $eq$ls180.v:4416$755 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 16 + parameter \Y_WIDTH 1 + connect \A \main_spimaster30_clk_divider + connect \B $sub$ls180.v:4416$754_Y + connect \Y $eq$ls180.v:4416$755_Y + end + attribute \src "ls180.v:4443.10-4443.67" + cell $eq $eq$ls180.v:4443$759 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \main_spimaster27_count + connect \B $sub$ls180.v:4443$758_Y + connect \Y $eq$ls180.v:4443$759_Y + end + attribute \src "ls180.v:4473.35-4473.108" + cell $eq $eq$ls180.v:4473$761 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 16 + parameter \Y_WIDTH 1 + connect \A \main_spisdcard_clk_divider1 + connect \B $sub$ls180.v:4473$760_Y + connect \Y $eq$ls180.v:4473$761_Y + end + attribute \src "ls180.v:4474.35-4474.102" + cell $eq $eq$ls180.v:4474$763 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 16 + parameter \Y_WIDTH 1 + connect \A \main_spisdcard_clk_divider1 + connect \B $sub$ls180.v:4474$762_Y + connect \Y $eq$ls180.v:4474$763_Y + end + attribute \src "ls180.v:4502.10-4502.65" + cell $eq $eq$ls180.v:4502$767 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \main_spisdcard_count + connect \B $sub$ls180.v:4502$766_Y + connect \Y $eq$ls180.v:4502$767_Y + end + attribute \src "ls180.v:4606.10-4606.40" + cell $eq $eq$ls180.v:4606$794 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_init_count + connect \B 7'1001111 + connect \Y $eq$ls180.v:4606$794_Y + end + attribute \src "ls180.v:4663.10-4663.39" + cell $eq $eq$ls180.v:4663$797 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdw_count + connect \B 3'111 + connect \Y $eq$ls180.v:4663$797_Y + end + attribute \src "ls180.v:4680.10-4680.39" + cell $eq $eq$ls180.v:4680$799 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdw_count + connect \B 3'111 + connect \Y $eq$ls180.v:4680$799_Y + end + attribute \src "ls180.v:4708.38-4708.88" + cell $eq $eq$ls180.v:4708$801 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_i + connect \B 1'0 + connect \Y $eq$ls180.v:4708$801_Y + end + attribute \src "ls180.v:4758.9-4758.40" + cell $eq $eq$ls180.v:4758$811 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_timeout + connect \B 1'0 + connect \Y $eq$ls180.v:4758$811_Y + end + attribute \src "ls180.v:4767.36-4767.105" + cell $eq $eq$ls180.v:4767$813 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_count + connect \B $sub$ls180.v:4767$812_Y + connect \Y $eq$ls180.v:4767$813_Y + end + attribute \src "ls180.v:4786.9-4786.40" + cell $eq $eq$ls180.v:4786$817 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_timeout + connect \B 1'0 + connect \Y $eq$ls180.v:4786$817_Y + end + attribute \src "ls180.v:4798.10-4798.39" + cell $eq $eq$ls180.v:4798$819 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_count + connect \B 3'111 + connect \Y $eq$ls180.v:4798$819_Y + end + attribute \src "ls180.v:4835.39-4835.94" + cell $eq $eq$ls180.v:4835$823 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_crcr_pads_in_payload_data_i [0] + connect \B 1'0 + connect \Y $eq$ls180.v:4835$823_Y + end + attribute \src "ls180.v:4872.32-4872.89" + cell $eq $eq$ls180.v:4872$832 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_crcr_source_source_payload_data0 + connect \B 3'101 + connect \Y $eq$ls180.v:4872$832_Y + end + attribute \src "ls180.v:4920.10-4920.40" + cell $eq $eq$ls180.v:4920$836 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_count + connect \B 1'1 + connect \Y $eq$ls180.v:4920$836_Y + end + attribute \src "ls180.v:4969.40-4969.98" + cell $eq $eq$ls180.v:4969$838 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_datar_pads_in_payload_data_i + connect \B 1'0 + connect \Y $eq$ls180.v:4969$838_Y + end + attribute \src "ls180.v:5020.9-5020.41" + cell $eq $eq$ls180.v:5020$848 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_timeout + connect \B 1'0 + connect \Y $eq$ls180.v:5020$848_Y + end + attribute \src "ls180.v:5029.37-5029.123" + cell $eq $eq$ls180.v:5029$851 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 10 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_count + connect \B $sub$ls180.v:5029$850_Y + connect \Y $eq$ls180.v:5029$851_Y + end + attribute \src "ls180.v:5052.9-5052.41" + cell $eq $eq$ls180.v:5052$854 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_timeout + connect \B 1'0 + connect \Y $eq$ls180.v:5052$854_Y + end + attribute \src "ls180.v:5062.10-5062.41" + cell $eq $eq$ls180.v:5062$856 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_count + connect \B 6'100111 + connect \Y $eq$ls180.v:5062$856_Y + end + attribute \src "ls180.v:5231.9-5231.47" + cell $eq $eq$ls180.v:5231$1038 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_cnt + connect \B 3'111 + connect \Y $eq$ls180.v:5231$1038_Y + end + attribute \src "ls180.v:5261.10-5261.48" + cell $eq $eq$ls180.v:5261$1039 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_cnt + connect \B 3'111 + connect \Y $eq$ls180.v:5261$1039_Y + end + attribute \src "ls180.v:5292.10-5292.78" + cell $eq $eq$ls180.v:5292$1044 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 16 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_fifo0 + connect \B \main_sdcore_crc16_checker_crctmp0 + connect \Y $eq$ls180.v:5292$1044_Y + end + attribute \src "ls180.v:5292.83-5292.151" + cell $eq $eq$ls180.v:5292$1045 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 16 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_fifo1 + connect \B \main_sdcore_crc16_checker_crctmp1 + connect \Y $eq$ls180.v:5292$1045_Y + end + attribute \src "ls180.v:5292.157-5292.225" + cell $eq $eq$ls180.v:5292$1047 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 16 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_fifo2 + connect \B \main_sdcore_crc16_checker_crctmp2 + connect \Y $eq$ls180.v:5292$1047_Y + end + attribute \src "ls180.v:5292.231-5292.299" + cell $eq $eq$ls180.v:5292$1049 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 16 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_fifo3 + connect \B \main_sdcore_crc16_checker_crctmp3 + connect \Y $eq$ls180.v:5292$1049_Y + end + attribute \src "ls180.v:5300.7-5300.44" + cell $eq $eq$ls180.v:5300$1053 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_cnt + connect \B 3'111 + connect \Y $eq$ls180.v:5300$1053_Y + end + attribute \src "ls180.v:5310.7-5310.44" + cell $eq $eq$ls180.v:5310$1056 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_cnt + connect \B 3'111 + connect \Y $eq$ls180.v:5310$1056_Y + end + attribute \src "ls180.v:5320.7-5320.44" + cell $eq $eq$ls180.v:5320$1059 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_cnt + connect \B 3'111 + connect \Y $eq$ls180.v:5320$1059_Y + end + attribute \src "ls180.v:5330.7-5330.44" + cell $eq $eq$ls180.v:5330$1062 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_cnt + connect \B 3'111 + connect \Y $eq$ls180.v:5330$1062_Y + end + attribute \src "ls180.v:5454.36-5454.64" + cell $eq $eq$ls180.v:5454$1113 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_cmd_type + connect \B 1'0 + connect \Y $eq$ls180.v:5454$1113_Y + end + attribute \src "ls180.v:5460.10-5460.39" + cell $eq $eq$ls180.v:5460$1116 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_cmd_count + connect \B 3'101 + connect \Y $eq$ls180.v:5460$1116_Y + end + attribute \src "ls180.v:5461.11-5461.39" + cell $eq $eq$ls180.v:5461$1117 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_cmd_type + connect \B 1'0 + connect \Y $eq$ls180.v:5461$1117_Y + end + attribute \src "ls180.v:5473.34-5473.63" + cell $eq $eq$ls180.v:5473$1118 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_data_type + connect \B 1'0 + connect \Y $eq$ls180.v:5473$1118_Y + end + attribute \src "ls180.v:5474.9-5474.37" + cell $eq $eq$ls180.v:5474$1119 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_cmd_type + connect \B 2'10 + connect \Y $eq$ls180.v:5474$1119_Y + end + attribute \src "ls180.v:5481.10-5481.55" + cell $eq $eq$ls180.v:5481$1120 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_source_payload_status + connect \B 1'1 + connect \Y $eq$ls180.v:5481$1120_Y + end + attribute \src "ls180.v:5487.12-5487.41" + cell $eq $eq$ls180.v:5487$1121 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_data_type + connect \B 2'10 + connect \Y $eq$ls180.v:5487$1121_Y + end + attribute \src "ls180.v:5490.13-5490.42" + cell $eq $eq$ls180.v:5490$1122 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_data_type + connect \B 1'1 + connect \Y $eq$ls180.v:5490$1122_Y + end + attribute \src "ls180.v:5512.10-5512.76" + cell $eq $eq$ls180.v:5512$1127 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_data_count + connect \B $sub$ls180.v:5512$1126_Y + connect \Y $eq$ls180.v:5512$1127_Y + end + attribute \src "ls180.v:5527.35-5527.101" + cell $eq $eq$ls180.v:5527$1130 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_data_count + connect \B $sub$ls180.v:5527$1129_Y + connect \Y $eq$ls180.v:5527$1130_Y + end + attribute \src "ls180.v:5529.10-5529.56" + cell $eq $eq$ls180.v:5529$1131 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_source_payload_status + connect \B 1'0 + connect \Y $eq$ls180.v:5529$1131_Y + end + attribute \src "ls180.v:5538.12-5538.78" + cell $eq $eq$ls180.v:5538$1135 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_data_count + connect \B $sub$ls180.v:5538$1134_Y + connect \Y $eq$ls180.v:5538$1135_Y + end + attribute \src "ls180.v:5545.11-5545.57" + cell $eq $eq$ls180.v:5545$1136 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_source_payload_status + connect \B 1'1 + connect \Y $eq$ls180.v:5545$1136_Y + end + attribute \src "ls180.v:5662.10-5662.105" + cell $eq $eq$ls180.v:5662$1153 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_wishbonedmawriter_offset + connect \B $sub$ls180.v:5662$1152_Y + connect \Y $eq$ls180.v:5662$1153_Y + end + attribute \src "ls180.v:5752.39-5752.106" + cell $eq $eq$ls180.v:5752$1159 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 1 + connect \A \main_sdmem2block_dma_offset + connect \B $sub$ls180.v:5752$1158_Y + connect \Y $eq$ls180.v:5752$1159_Y + end + attribute \src "ls180.v:5782.44-5782.82" + cell $eq $eq$ls180.v:5782$1162 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdmem2block_converter_mux + connect \B 1'0 + connect \Y $eq$ls180.v:5782$1162_Y + end + attribute \src "ls180.v:5783.43-5783.81" + cell $eq $eq$ls180.v:5783$1163 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \main_sdmem2block_converter_mux + connect \B 3'111 + connect \Y $eq$ls180.v:5783$1163_Y + end + attribute \src "ls180.v:5895.68-5895.89" + cell $eq $eq$ls180.v:5895$1179 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_grant + connect \B 1'0 + connect \Y $eq$ls180.v:5895$1179_Y + end + attribute \src "ls180.v:5896.68-5896.89" + cell $eq $eq$ls180.v:5896$1181 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_grant + connect \B 1'1 + connect \Y $eq$ls180.v:5896$1181_Y + end + attribute \src "ls180.v:5897.71-5897.92" + cell $eq $eq$ls180.v:5897$1183 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_grant + connect \B 2'10 + connect \Y $eq$ls180.v:5897$1183_Y + end + attribute \src "ls180.v:5898.57-5898.78" + cell $eq $eq$ls180.v:5898$1185 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_grant + connect \B 2'11 + connect \Y $eq$ls180.v:5898$1185_Y + end + attribute \src "ls180.v:5899.57-5899.78" + cell $eq $eq$ls180.v:5899$1187 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_grant + connect \B 3'100 + connect \Y $eq$ls180.v:5899$1187_Y + end + attribute \src "ls180.v:5900.68-5900.89" + cell $eq $eq$ls180.v:5900$1189 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_grant + connect \B 1'0 + connect \Y $eq$ls180.v:5900$1189_Y + end + attribute \src "ls180.v:5901.68-5901.89" + cell $eq $eq$ls180.v:5901$1191 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_grant + connect \B 1'1 + connect \Y $eq$ls180.v:5901$1191_Y + end + attribute \src "ls180.v:5902.71-5902.92" + cell $eq $eq$ls180.v:5902$1193 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_grant + connect \B 2'10 + connect \Y $eq$ls180.v:5902$1193_Y + end + attribute \src "ls180.v:5903.57-5903.78" + cell $eq $eq$ls180.v:5903$1195 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_grant + connect \B 2'11 + connect \Y $eq$ls180.v:5903$1195_Y + end + attribute \src "ls180.v:5904.57-5904.78" + cell $eq $eq$ls180.v:5904$1197 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_grant + connect \B 3'100 + connect \Y $eq$ls180.v:5904$1197_Y + end + attribute \src "ls180.v:5908.27-5908.59" + cell $eq $eq$ls180.v:5908$1200 + parameter \A_SIGNED 0 + parameter \A_WIDTH 24 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_adr [29:6] + connect \B 1'0 + connect \Y $eq$ls180.v:5908$1200_Y + end + attribute \src "ls180.v:5909.27-5909.59" + cell $eq $eq$ls180.v:5909$1201 + parameter \A_SIGNED 0 + parameter \A_WIDTH 24 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_adr [29:6] + connect \B 1'1 + connect \Y $eq$ls180.v:5909$1201_Y + end + attribute \src "ls180.v:5910.27-5910.59" + cell $eq $eq$ls180.v:5910$1202 + parameter \A_SIGNED 0 + parameter \A_WIDTH 24 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_shared_adr [29:6] + connect \B 2'10 + connect \Y $eq$ls180.v:5910$1202_Y + end + attribute \src "ls180.v:5911.27-5911.59" + cell $eq $eq$ls180.v:5911$1203 + parameter \A_SIGNED 0 + parameter \A_WIDTH 24 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_shared_adr [29:6] + connect \B 2'11 + connect \Y $eq$ls180.v:5911$1203_Y + end + attribute \src "ls180.v:5912.27-5912.59" + cell $eq $eq$ls180.v:5912$1204 + parameter \A_SIGNED 0 + parameter \A_WIDTH 24 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_shared_adr [29:6] + connect \B 3'100 + connect \Y $eq$ls180.v:5912$1204_Y + end + attribute \src "ls180.v:5913.27-5913.68" + cell $eq $eq$ls180.v:5913$1205 + parameter \A_SIGNED 0 + parameter \A_WIDTH 28 + parameter \B_SIGNED 0 + parameter \B_WIDTH 27 + parameter \Y_WIDTH 1 + connect \A \builder_shared_adr [29:2] + connect \B 27'110000000000000100000000000 + connect \Y $eq$ls180.v:5913$1205_Y + end + attribute \src "ls180.v:5914.27-5914.65" + cell $eq $eq$ls180.v:5914$1206 + parameter \A_SIGNED 0 + parameter \A_WIDTH 21 + parameter \B_SIGNED 0 + parameter \B_WIDTH 20 + parameter \Y_WIDTH 1 + connect \A \builder_shared_adr [29:9] + connect \B 20'11000000000000010001 + connect \Y $eq$ls180.v:5914$1206_Y + end + attribute \src "ls180.v:5915.27-5915.59" + cell $eq $eq$ls180.v:5915$1207 + parameter \A_SIGNED 0 + parameter \A_WIDTH 21 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_adr [29:9] + connect \B 1'1 + connect \Y $eq$ls180.v:5915$1207_Y + end + attribute \src "ls180.v:5916.27-5916.59" + cell $eq $eq$ls180.v:5916$1208 + parameter \A_SIGNED 0 + parameter \A_WIDTH 21 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_shared_adr [29:9] + connect \B 2'10 + connect \Y $eq$ls180.v:5916$1208_Y + end + attribute \src "ls180.v:5917.27-5917.59" + cell $eq $eq$ls180.v:5917$1209 + parameter \A_SIGNED 0 + parameter \A_WIDTH 21 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_shared_adr [29:9] + connect \B 2'11 + connect \Y $eq$ls180.v:5917$1209_Y + end + attribute \src "ls180.v:5918.28-5918.60" + cell $eq $eq$ls180.v:5918$1210 + parameter \A_SIGNED 0 + parameter \A_WIDTH 21 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_shared_adr [29:9] + connect \B 3'100 + connect \Y $eq$ls180.v:5918$1210_Y + end + attribute \src "ls180.v:5919.28-5919.62" + cell $eq $eq$ls180.v:5919$1211 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \builder_shared_adr [29:22] + connect \B 7'1001000 + connect \Y $eq$ls180.v:5919$1211_Y + end + attribute \src "ls180.v:5920.28-5920.66" + cell $eq $eq$ls180.v:5920$1212 + parameter \A_SIGNED 0 + parameter \A_WIDTH 17 + parameter \B_SIGNED 0 + parameter \B_WIDTH 16 + parameter \Y_WIDTH 1 + connect \A \builder_shared_adr [29:13] + connect \B 16'1100000000000000 + connect \Y $eq$ls180.v:5920$1212_Y + end + attribute \src "ls180.v:6040.24-6040.45" + cell $eq $eq$ls180.v:6040$1279 + parameter \A_SIGNED 0 + parameter \A_WIDTH 20 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_count + connect \B 1'0 + connect \Y $eq$ls180.v:6040$1279_Y + end + attribute \src "ls180.v:6041.32-6041.77" + cell $eq $eq$ls180.v:6041$1280 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [13:8] + connect \B 1'0 + connect \Y $eq$ls180.v:6041$1280_Y + end + attribute \src "ls180.v:6043.97-6043.141" + cell $eq $eq$ls180.v:6043$1282 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6043$1282_Y + end + attribute \src "ls180.v:6044.100-6044.144" + cell $eq $eq$ls180.v:6044$1286 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6044$1286_Y + end + attribute \src "ls180.v:6046.99-6046.143" + cell $eq $eq$ls180.v:6046$1289 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6046$1289_Y + end + attribute \src "ls180.v:6047.102-6047.146" + cell $eq $eq$ls180.v:6047$1293 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6047$1293_Y + end + attribute \src "ls180.v:6049.99-6049.143" + cell $eq $eq$ls180.v:6049$1296 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6049$1296_Y + end + attribute \src "ls180.v:6050.102-6050.146" + cell $eq $eq$ls180.v:6050$1300 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6050$1300_Y + end + attribute \src "ls180.v:6052.99-6052.143" + cell $eq $eq$ls180.v:6052$1303 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6052$1303_Y + end + attribute \src "ls180.v:6053.102-6053.146" + cell $eq $eq$ls180.v:6053$1307 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6053$1307_Y + end + attribute \src "ls180.v:6055.99-6055.143" + cell $eq $eq$ls180.v:6055$1310 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 3'100 + connect \Y $eq$ls180.v:6055$1310_Y + end + attribute \src "ls180.v:6056.102-6056.146" + cell $eq $eq$ls180.v:6056$1314 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 3'100 + connect \Y $eq$ls180.v:6056$1314_Y + end + attribute \src "ls180.v:6058.102-6058.146" + cell $eq $eq$ls180.v:6058$1317 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 3'101 + connect \Y $eq$ls180.v:6058$1317_Y + end + attribute \src "ls180.v:6059.105-6059.149" + cell $eq $eq$ls180.v:6059$1321 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 3'101 + connect \Y $eq$ls180.v:6059$1321_Y + end + attribute \src "ls180.v:6061.102-6061.146" + cell $eq $eq$ls180.v:6061$1324 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 3'110 + connect \Y $eq$ls180.v:6061$1324_Y + end + attribute \src "ls180.v:6062.105-6062.149" + cell $eq $eq$ls180.v:6062$1328 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 3'110 + connect \Y $eq$ls180.v:6062$1328_Y + end + attribute \src "ls180.v:6064.102-6064.146" + cell $eq $eq$ls180.v:6064$1331 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 3'111 + connect \Y $eq$ls180.v:6064$1331_Y + end + attribute \src "ls180.v:6065.105-6065.149" + cell $eq $eq$ls180.v:6065$1335 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 3'111 + connect \Y $eq$ls180.v:6065$1335_Y + end + attribute \src "ls180.v:6067.102-6067.146" + cell $eq $eq$ls180.v:6067$1338 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:6067$1338_Y + end + attribute \src "ls180.v:6068.105-6068.149" + cell $eq $eq$ls180.v:6068$1342 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:6068$1342_Y + end + attribute \src "ls180.v:6079.32-6079.77" + cell $eq $eq$ls180.v:6079$1344 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_adr [13:8] + connect \B 3'110 + connect \Y $eq$ls180.v:6079$1344_Y + end + attribute \src "ls180.v:6081.94-6081.138" + cell $eq $eq$ls180.v:6081$1346 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_adr [2:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6081$1346_Y + end + attribute \src "ls180.v:6082.97-6082.141" + cell $eq $eq$ls180.v:6082$1350 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_adr [2:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6082$1350_Y + end + attribute \src "ls180.v:6084.94-6084.138" + cell $eq $eq$ls180.v:6084$1353 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_adr [2:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6084$1353_Y + end + attribute \src "ls180.v:6085.97-6085.141" + cell $eq $eq$ls180.v:6085$1357 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_adr [2:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6085$1357_Y + end + attribute \src "ls180.v:6087.94-6087.138" + cell $eq $eq$ls180.v:6087$1360 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_adr [2:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6087$1360_Y + end + attribute \src "ls180.v:6088.97-6088.141" + cell $eq $eq$ls180.v:6088$1364 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_adr [2:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6088$1364_Y + end + attribute \src "ls180.v:6090.94-6090.138" + cell $eq $eq$ls180.v:6090$1367 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_adr [2:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6090$1367_Y + end + attribute \src "ls180.v:6091.97-6091.141" + cell $eq $eq$ls180.v:6091$1371 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_adr [2:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6091$1371_Y + end + attribute \src "ls180.v:6093.95-6093.139" + cell $eq $eq$ls180.v:6093$1374 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_adr [2:0] + connect \B 3'100 + connect \Y $eq$ls180.v:6093$1374_Y + end + attribute \src "ls180.v:6094.98-6094.142" + cell $eq $eq$ls180.v:6094$1378 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_adr [2:0] + connect \B 3'100 + connect \Y $eq$ls180.v:6094$1378_Y + end + attribute \src "ls180.v:6096.95-6096.139" + cell $eq $eq$ls180.v:6096$1381 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_adr [2:0] + connect \B 3'101 + connect \Y $eq$ls180.v:6096$1381_Y + end + attribute \src "ls180.v:6097.98-6097.142" + cell $eq $eq$ls180.v:6097$1385 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_adr [2:0] + connect \B 3'101 + connect \Y $eq$ls180.v:6097$1385_Y + end + attribute \src "ls180.v:6105.32-6105.78" + cell $eq $eq$ls180.v:6105$1387 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface2_bank_bus_adr [13:8] + connect \B 4'1100 + connect \Y $eq$ls180.v:6105$1387_Y + end + attribute \src "ls180.v:6107.93-6107.135" + cell $eq $eq$ls180.v:6107$1389 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface2_bank_bus_adr [0] + connect \B 1'0 + connect \Y $eq$ls180.v:6107$1389_Y + end + attribute \src "ls180.v:6108.96-6108.138" + cell $eq $eq$ls180.v:6108$1393 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface2_bank_bus_adr [0] + connect \B 1'0 + connect \Y $eq$ls180.v:6108$1393_Y + end + attribute \src "ls180.v:6110.92-6110.134" + cell $eq $eq$ls180.v:6110$1396 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface2_bank_bus_adr [0] + connect \B 1'1 + connect \Y $eq$ls180.v:6110$1396_Y + end + attribute \src "ls180.v:6111.95-6111.137" + cell $eq $eq$ls180.v:6111$1400 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface2_bank_bus_adr [0] + connect \B 1'1 + connect \Y $eq$ls180.v:6111$1400_Y + end + attribute \src "ls180.v:6119.32-6119.78" + cell $eq $eq$ls180.v:6119$1402 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [13:8] + connect \B 4'1010 + connect \Y $eq$ls180.v:6119$1402_Y + end + attribute \src "ls180.v:6121.98-6121.142" + cell $eq $eq$ls180.v:6121$1404 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6121$1404_Y + end + attribute \src "ls180.v:6122.101-6122.145" + cell $eq $eq$ls180.v:6122$1408 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6122$1408_Y + end + attribute \src "ls180.v:6124.97-6124.141" + cell $eq $eq$ls180.v:6124$1411 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6124$1411_Y + end + attribute \src "ls180.v:6125.100-6125.144" + cell $eq $eq$ls180.v:6125$1415 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6125$1415_Y + end + attribute \src "ls180.v:6127.97-6127.141" + cell $eq $eq$ls180.v:6127$1418 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6127$1418_Y + end + attribute \src "ls180.v:6128.100-6128.144" + cell $eq $eq$ls180.v:6128$1422 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6128$1422_Y + end + attribute \src "ls180.v:6130.97-6130.141" + cell $eq $eq$ls180.v:6130$1425 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6130$1425_Y + end + attribute \src "ls180.v:6131.100-6131.144" + cell $eq $eq$ls180.v:6131$1429 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6131$1429_Y + end + attribute \src "ls180.v:6133.97-6133.141" + cell $eq $eq$ls180.v:6133$1432 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 3'100 + connect \Y $eq$ls180.v:6133$1432_Y + end + attribute \src "ls180.v:6134.100-6134.144" + cell $eq $eq$ls180.v:6134$1436 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 3'100 + connect \Y $eq$ls180.v:6134$1436_Y + end + attribute \src "ls180.v:6136.98-6136.142" + cell $eq $eq$ls180.v:6136$1439 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 3'101 + connect \Y $eq$ls180.v:6136$1439_Y + end + attribute \src "ls180.v:6137.101-6137.145" + cell $eq $eq$ls180.v:6137$1443 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 3'101 + connect \Y $eq$ls180.v:6137$1443_Y + end + attribute \src "ls180.v:6139.98-6139.142" + cell $eq $eq$ls180.v:6139$1446 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 3'110 + connect \Y $eq$ls180.v:6139$1446_Y + end + attribute \src "ls180.v:6140.101-6140.145" + cell $eq $eq$ls180.v:6140$1450 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 3'110 + connect \Y $eq$ls180.v:6140$1450_Y + end + attribute \src "ls180.v:6142.98-6142.142" + cell $eq $eq$ls180.v:6142$1453 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 3'111 + connect \Y $eq$ls180.v:6142$1453_Y + end + attribute \src "ls180.v:6143.101-6143.145" + cell $eq $eq$ls180.v:6143$1457 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 3'111 + connect \Y $eq$ls180.v:6143$1457_Y + end + attribute \src "ls180.v:6145.98-6145.142" + cell $eq $eq$ls180.v:6145$1460 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:6145$1460_Y + end + attribute \src "ls180.v:6146.101-6146.145" + cell $eq $eq$ls180.v:6146$1464 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:6146$1464_Y + end + attribute \src "ls180.v:6156.32-6156.78" + cell $eq $eq$ls180.v:6156$1466 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [13:8] + connect \B 4'1011 + connect \Y $eq$ls180.v:6156$1466_Y + end + attribute \src "ls180.v:6158.98-6158.142" + cell $eq $eq$ls180.v:6158$1468 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6158$1468_Y + end + attribute \src "ls180.v:6159.101-6159.145" + cell $eq $eq$ls180.v:6159$1472 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6159$1472_Y + end + attribute \src "ls180.v:6161.97-6161.141" + cell $eq $eq$ls180.v:6161$1475 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6161$1475_Y + end + attribute \src "ls180.v:6162.100-6162.144" + cell $eq $eq$ls180.v:6162$1479 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6162$1479_Y + end + attribute \src "ls180.v:6164.97-6164.141" + cell $eq $eq$ls180.v:6164$1482 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6164$1482_Y + end + attribute \src "ls180.v:6165.100-6165.144" + cell $eq $eq$ls180.v:6165$1486 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6165$1486_Y + end + attribute \src "ls180.v:6167.97-6167.141" + cell $eq $eq$ls180.v:6167$1489 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6167$1489_Y + end + attribute \src "ls180.v:6168.100-6168.144" + cell $eq $eq$ls180.v:6168$1493 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6168$1493_Y + end + attribute \src "ls180.v:6170.97-6170.141" + cell $eq $eq$ls180.v:6170$1496 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 3'100 + connect \Y $eq$ls180.v:6170$1496_Y + end + attribute \src "ls180.v:6171.100-6171.144" + cell $eq $eq$ls180.v:6171$1500 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 3'100 + connect \Y $eq$ls180.v:6171$1500_Y + end + attribute \src "ls180.v:6173.98-6173.142" + cell $eq $eq$ls180.v:6173$1503 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 3'101 + connect \Y $eq$ls180.v:6173$1503_Y + end + attribute \src "ls180.v:6174.101-6174.145" + cell $eq $eq$ls180.v:6174$1507 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 3'101 + connect \Y $eq$ls180.v:6174$1507_Y + end + attribute \src "ls180.v:6176.98-6176.142" + cell $eq $eq$ls180.v:6176$1510 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 3'110 + connect \Y $eq$ls180.v:6176$1510_Y + end + attribute \src "ls180.v:6177.101-6177.145" + cell $eq $eq$ls180.v:6177$1514 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 3'110 + connect \Y $eq$ls180.v:6177$1514_Y + end + attribute \src "ls180.v:6179.98-6179.142" + cell $eq $eq$ls180.v:6179$1517 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 3'111 + connect \Y $eq$ls180.v:6179$1517_Y + end + attribute \src "ls180.v:6180.101-6180.145" + cell $eq $eq$ls180.v:6180$1521 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 3'111 + connect \Y $eq$ls180.v:6180$1521_Y + end + attribute \src "ls180.v:6182.98-6182.142" + cell $eq $eq$ls180.v:6182$1524 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:6182$1524_Y + end + attribute \src "ls180.v:6183.101-6183.145" + cell $eq $eq$ls180.v:6183$1528 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [3:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:6183$1528_Y + end + attribute \src "ls180.v:6193.32-6193.78" + cell $eq $eq$ls180.v:6193$1530 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [13:8] + connect \B 4'1111 + connect \Y $eq$ls180.v:6193$1530_Y + end + attribute \src "ls180.v:6195.100-6195.144" + cell $eq $eq$ls180.v:6195$1532 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6195$1532_Y + end + attribute \src "ls180.v:6196.103-6196.147" + cell $eq $eq$ls180.v:6196$1536 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6196$1536_Y + end + attribute \src "ls180.v:6198.100-6198.144" + cell $eq $eq$ls180.v:6198$1539 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6198$1539_Y + end + attribute \src "ls180.v:6199.103-6199.147" + cell $eq $eq$ls180.v:6199$1543 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6199$1543_Y + end + attribute \src "ls180.v:6201.100-6201.144" + cell $eq $eq$ls180.v:6201$1546 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6201$1546_Y + end + attribute \src "ls180.v:6202.103-6202.147" + cell $eq $eq$ls180.v:6202$1550 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6202$1550_Y + end + attribute \src "ls180.v:6204.100-6204.144" + cell $eq $eq$ls180.v:6204$1553 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6204$1553_Y + end + attribute \src "ls180.v:6205.103-6205.147" + cell $eq $eq$ls180.v:6205$1557 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6205$1557_Y + end + attribute \src "ls180.v:6207.100-6207.144" + cell $eq $eq$ls180.v:6207$1560 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 3'100 + connect \Y $eq$ls180.v:6207$1560_Y + end + attribute \src "ls180.v:6208.103-6208.147" + cell $eq $eq$ls180.v:6208$1564 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 3'100 + connect \Y $eq$ls180.v:6208$1564_Y + end + attribute \src "ls180.v:6210.100-6210.144" + cell $eq $eq$ls180.v:6210$1567 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 3'101 + connect \Y $eq$ls180.v:6210$1567_Y + end + attribute \src "ls180.v:6211.103-6211.147" + cell $eq $eq$ls180.v:6211$1571 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 3'101 + connect \Y $eq$ls180.v:6211$1571_Y + end + attribute \src "ls180.v:6213.100-6213.144" + cell $eq $eq$ls180.v:6213$1574 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 3'110 + connect \Y $eq$ls180.v:6213$1574_Y + end + attribute \src "ls180.v:6214.103-6214.147" + cell $eq $eq$ls180.v:6214$1578 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 3'110 + connect \Y $eq$ls180.v:6214$1578_Y + end + attribute \src "ls180.v:6216.100-6216.144" + cell $eq $eq$ls180.v:6216$1581 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 3'111 + connect \Y $eq$ls180.v:6216$1581_Y + end + attribute \src "ls180.v:6217.103-6217.147" + cell $eq $eq$ls180.v:6217$1585 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 3'111 + connect \Y $eq$ls180.v:6217$1585_Y + end + attribute \src "ls180.v:6219.102-6219.146" + cell $eq $eq$ls180.v:6219$1588 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:6219$1588_Y + end + attribute \src "ls180.v:6220.105-6220.149" + cell $eq $eq$ls180.v:6220$1592 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:6220$1592_Y + end + attribute \src "ls180.v:6222.102-6222.146" + cell $eq $eq$ls180.v:6222$1595 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 4'1001 + connect \Y $eq$ls180.v:6222$1595_Y + end + attribute \src "ls180.v:6223.105-6223.149" + cell $eq $eq$ls180.v:6223$1599 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 4'1001 + connect \Y $eq$ls180.v:6223$1599_Y + end + attribute \src "ls180.v:6225.102-6225.147" + cell $eq $eq$ls180.v:6225$1602 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 4'1010 + connect \Y $eq$ls180.v:6225$1602_Y + end + attribute \src "ls180.v:6226.105-6226.150" + cell $eq $eq$ls180.v:6226$1606 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 4'1010 + connect \Y $eq$ls180.v:6226$1606_Y + end + attribute \src "ls180.v:6228.102-6228.147" + cell $eq $eq$ls180.v:6228$1609 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 4'1011 + connect \Y $eq$ls180.v:6228$1609_Y + end + attribute \src "ls180.v:6229.105-6229.150" + cell $eq $eq$ls180.v:6229$1613 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 4'1011 + connect \Y $eq$ls180.v:6229$1613_Y + end + attribute \src "ls180.v:6231.102-6231.147" + cell $eq $eq$ls180.v:6231$1616 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 4'1100 + connect \Y $eq$ls180.v:6231$1616_Y + end + attribute \src "ls180.v:6232.105-6232.150" + cell $eq $eq$ls180.v:6232$1620 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 4'1100 + connect \Y $eq$ls180.v:6232$1620_Y + end + attribute \src "ls180.v:6234.99-6234.144" + cell $eq $eq$ls180.v:6234$1623 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 4'1101 + connect \Y $eq$ls180.v:6234$1623_Y + end + attribute \src "ls180.v:6235.102-6235.147" + cell $eq $eq$ls180.v:6235$1627 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 4'1101 + connect \Y $eq$ls180.v:6235$1627_Y + end + attribute \src "ls180.v:6237.100-6237.145" + cell $eq $eq$ls180.v:6237$1630 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 4'1110 + connect \Y $eq$ls180.v:6237$1630_Y + end + attribute \src "ls180.v:6238.103-6238.148" + cell $eq $eq$ls180.v:6238$1634 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [3:0] + connect \B 4'1110 + connect \Y $eq$ls180.v:6238$1634_Y + end + attribute \src "ls180.v:6255.32-6255.78" + cell $eq $eq$ls180.v:6255$1636 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [13:8] + connect \B 4'1110 + connect \Y $eq$ls180.v:6255$1636_Y + end + attribute \src "ls180.v:6257.104-6257.148" + cell $eq $eq$ls180.v:6257$1638 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6257$1638_Y + end + attribute \src "ls180.v:6258.107-6258.151" + cell $eq $eq$ls180.v:6258$1642 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6258$1642_Y + end + attribute \src "ls180.v:6260.104-6260.148" + cell $eq $eq$ls180.v:6260$1645 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6260$1645_Y + end + attribute \src "ls180.v:6261.107-6261.151" + cell $eq $eq$ls180.v:6261$1649 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6261$1649_Y + end + attribute \src "ls180.v:6263.104-6263.148" + cell $eq $eq$ls180.v:6263$1652 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6263$1652_Y + end + attribute \src "ls180.v:6264.107-6264.151" + cell $eq $eq$ls180.v:6264$1656 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6264$1656_Y + end + attribute \src "ls180.v:6266.104-6266.148" + cell $eq $eq$ls180.v:6266$1659 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6266$1659_Y + end + attribute \src "ls180.v:6267.107-6267.151" + cell $eq $eq$ls180.v:6267$1663 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6267$1663_Y + end + attribute \src "ls180.v:6269.103-6269.147" + cell $eq $eq$ls180.v:6269$1666 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 3'100 + connect \Y $eq$ls180.v:6269$1666_Y + end + attribute \src "ls180.v:6270.106-6270.150" + cell $eq $eq$ls180.v:6270$1670 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 3'100 + connect \Y $eq$ls180.v:6270$1670_Y + end + attribute \src "ls180.v:6272.103-6272.147" + cell $eq $eq$ls180.v:6272$1673 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 3'101 + connect \Y $eq$ls180.v:6272$1673_Y + end + attribute \src "ls180.v:6273.106-6273.150" + cell $eq $eq$ls180.v:6273$1677 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 3'101 + connect \Y $eq$ls180.v:6273$1677_Y + end + attribute \src "ls180.v:6275.103-6275.147" + cell $eq $eq$ls180.v:6275$1680 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 3'110 + connect \Y $eq$ls180.v:6275$1680_Y + end + attribute \src "ls180.v:6276.106-6276.150" + cell $eq $eq$ls180.v:6276$1684 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 3'110 + connect \Y $eq$ls180.v:6276$1684_Y + end + attribute \src "ls180.v:6278.103-6278.147" + cell $eq $eq$ls180.v:6278$1687 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 3'111 + connect \Y $eq$ls180.v:6278$1687_Y + end + attribute \src "ls180.v:6279.106-6279.150" + cell $eq $eq$ls180.v:6279$1691 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 3'111 + connect \Y $eq$ls180.v:6279$1691_Y + end + attribute \src "ls180.v:6281.94-6281.138" + cell $eq $eq$ls180.v:6281$1694 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:6281$1694_Y + end + attribute \src "ls180.v:6282.97-6282.141" + cell $eq $eq$ls180.v:6282$1698 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:6282$1698_Y + end + attribute \src "ls180.v:6284.105-6284.149" + cell $eq $eq$ls180.v:6284$1701 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 4'1001 + connect \Y $eq$ls180.v:6284$1701_Y + end + attribute \src "ls180.v:6285.108-6285.152" + cell $eq $eq$ls180.v:6285$1705 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 4'1001 + connect \Y $eq$ls180.v:6285$1705_Y + end + attribute \src "ls180.v:6287.105-6287.150" + cell $eq $eq$ls180.v:6287$1708 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 4'1010 + connect \Y $eq$ls180.v:6287$1708_Y + end + attribute \src "ls180.v:6288.108-6288.153" + cell $eq $eq$ls180.v:6288$1712 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 4'1010 + connect \Y $eq$ls180.v:6288$1712_Y + end + attribute \src "ls180.v:6290.105-6290.150" + cell $eq $eq$ls180.v:6290$1715 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 4'1011 + connect \Y $eq$ls180.v:6290$1715_Y + end + attribute \src "ls180.v:6291.108-6291.153" + cell $eq $eq$ls180.v:6291$1719 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 4'1011 + connect \Y $eq$ls180.v:6291$1719_Y + end + attribute \src "ls180.v:6293.105-6293.150" + cell $eq $eq$ls180.v:6293$1722 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 4'1100 + connect \Y $eq$ls180.v:6293$1722_Y + end + attribute \src "ls180.v:6294.108-6294.153" + cell $eq $eq$ls180.v:6294$1726 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 4'1100 + connect \Y $eq$ls180.v:6294$1726_Y + end + attribute \src "ls180.v:6296.105-6296.150" + cell $eq $eq$ls180.v:6296$1729 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 4'1101 + connect \Y $eq$ls180.v:6296$1729_Y + end + attribute \src "ls180.v:6297.108-6297.153" + cell $eq $eq$ls180.v:6297$1733 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 4'1101 + connect \Y $eq$ls180.v:6297$1733_Y + end + attribute \src "ls180.v:6299.105-6299.150" + cell $eq $eq$ls180.v:6299$1736 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 4'1110 + connect \Y $eq$ls180.v:6299$1736_Y + end + attribute \src "ls180.v:6300.108-6300.153" + cell $eq $eq$ls180.v:6300$1740 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 4'1110 + connect \Y $eq$ls180.v:6300$1740_Y + end + attribute \src "ls180.v:6302.104-6302.149" + cell $eq $eq$ls180.v:6302$1743 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 4'1111 + connect \Y $eq$ls180.v:6302$1743_Y + end + attribute \src "ls180.v:6303.107-6303.152" + cell $eq $eq$ls180.v:6303$1747 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 4'1111 + connect \Y $eq$ls180.v:6303$1747_Y + end + attribute \src "ls180.v:6305.104-6305.149" + cell $eq $eq$ls180.v:6305$1750 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'10000 + connect \Y $eq$ls180.v:6305$1750_Y + end + attribute \src "ls180.v:6306.107-6306.152" + cell $eq $eq$ls180.v:6306$1754 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'10000 + connect \Y $eq$ls180.v:6306$1754_Y + end + attribute \src "ls180.v:6308.104-6308.149" + cell $eq $eq$ls180.v:6308$1757 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'10001 + connect \Y $eq$ls180.v:6308$1757_Y + end + attribute \src "ls180.v:6309.107-6309.152" + cell $eq $eq$ls180.v:6309$1761 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'10001 + connect \Y $eq$ls180.v:6309$1761_Y + end + attribute \src "ls180.v:6311.104-6311.149" + cell $eq $eq$ls180.v:6311$1764 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'10010 + connect \Y $eq$ls180.v:6311$1764_Y + end + attribute \src "ls180.v:6312.107-6312.152" + cell $eq $eq$ls180.v:6312$1768 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'10010 + connect \Y $eq$ls180.v:6312$1768_Y + end + attribute \src "ls180.v:6314.104-6314.149" + cell $eq $eq$ls180.v:6314$1771 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'10011 + connect \Y $eq$ls180.v:6314$1771_Y + end + attribute \src "ls180.v:6315.107-6315.152" + cell $eq $eq$ls180.v:6315$1775 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'10011 + connect \Y $eq$ls180.v:6315$1775_Y + end + attribute \src "ls180.v:6317.104-6317.149" + cell $eq $eq$ls180.v:6317$1778 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'10100 + connect \Y $eq$ls180.v:6317$1778_Y + end + attribute \src "ls180.v:6318.107-6318.152" + cell $eq $eq$ls180.v:6318$1782 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'10100 + connect \Y $eq$ls180.v:6318$1782_Y + end + attribute \src "ls180.v:6320.104-6320.149" + cell $eq $eq$ls180.v:6320$1785 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'10101 + connect \Y $eq$ls180.v:6320$1785_Y + end + attribute \src "ls180.v:6321.107-6321.152" + cell $eq $eq$ls180.v:6321$1789 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'10101 + connect \Y $eq$ls180.v:6321$1789_Y + end + attribute \src "ls180.v:6323.104-6323.149" + cell $eq $eq$ls180.v:6323$1792 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'10110 + connect \Y $eq$ls180.v:6323$1792_Y + end + attribute \src "ls180.v:6324.107-6324.152" + cell $eq $eq$ls180.v:6324$1796 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'10110 + connect \Y $eq$ls180.v:6324$1796_Y + end + attribute \src "ls180.v:6326.104-6326.149" + cell $eq $eq$ls180.v:6326$1799 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'10111 + connect \Y $eq$ls180.v:6326$1799_Y + end + attribute \src "ls180.v:6327.107-6327.152" + cell $eq $eq$ls180.v:6327$1803 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'10111 + connect \Y $eq$ls180.v:6327$1803_Y + end + attribute \src "ls180.v:6329.104-6329.149" + cell $eq $eq$ls180.v:6329$1806 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'11000 + connect \Y $eq$ls180.v:6329$1806_Y + end + attribute \src "ls180.v:6330.107-6330.152" + cell $eq $eq$ls180.v:6330$1810 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'11000 + connect \Y $eq$ls180.v:6330$1810_Y + end + attribute \src "ls180.v:6332.100-6332.145" + cell $eq $eq$ls180.v:6332$1813 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'11001 + connect \Y $eq$ls180.v:6332$1813_Y + end + attribute \src "ls180.v:6333.103-6333.148" + cell $eq $eq$ls180.v:6333$1817 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'11001 + connect \Y $eq$ls180.v:6333$1817_Y + end + attribute \src "ls180.v:6335.101-6335.146" + cell $eq $eq$ls180.v:6335$1820 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'11010 + connect \Y $eq$ls180.v:6335$1820_Y + end + attribute \src "ls180.v:6336.104-6336.149" + cell $eq $eq$ls180.v:6336$1824 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'11010 + connect \Y $eq$ls180.v:6336$1824_Y + end + attribute \src "ls180.v:6338.104-6338.149" + cell $eq $eq$ls180.v:6338$1827 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'11011 + connect \Y $eq$ls180.v:6338$1827_Y + end + attribute \src "ls180.v:6339.107-6339.152" + cell $eq $eq$ls180.v:6339$1831 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'11011 + connect \Y $eq$ls180.v:6339$1831_Y + end + attribute \src "ls180.v:6341.104-6341.149" + cell $eq $eq$ls180.v:6341$1834 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'11100 + connect \Y $eq$ls180.v:6341$1834_Y + end + attribute \src "ls180.v:6342.107-6342.152" + cell $eq $eq$ls180.v:6342$1838 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'11100 + connect \Y $eq$ls180.v:6342$1838_Y + end + attribute \src "ls180.v:6344.103-6344.148" + cell $eq $eq$ls180.v:6344$1841 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'11101 + connect \Y $eq$ls180.v:6344$1841_Y + end + attribute \src "ls180.v:6345.106-6345.151" + cell $eq $eq$ls180.v:6345$1845 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'11101 + connect \Y $eq$ls180.v:6345$1845_Y + end + attribute \src "ls180.v:6347.103-6347.148" + cell $eq $eq$ls180.v:6347$1848 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'11110 + connect \Y $eq$ls180.v:6347$1848_Y + end + attribute \src "ls180.v:6348.106-6348.151" + cell $eq $eq$ls180.v:6348$1852 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'11110 + connect \Y $eq$ls180.v:6348$1852_Y + end + attribute \src "ls180.v:6350.103-6350.148" + cell $eq $eq$ls180.v:6350$1855 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'11111 + connect \Y $eq$ls180.v:6350$1855_Y + end + attribute \src "ls180.v:6351.106-6351.151" + cell $eq $eq$ls180.v:6351$1859 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 5'11111 + connect \Y $eq$ls180.v:6351$1859_Y + end + attribute \src "ls180.v:6353.103-6353.148" + cell $eq $eq$ls180.v:6353$1862 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 6'100000 + connect \Y $eq$ls180.v:6353$1862_Y + end + attribute \src "ls180.v:6354.106-6354.151" + cell $eq $eq$ls180.v:6354$1866 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [5:0] + connect \B 6'100000 + connect \Y $eq$ls180.v:6354$1866_Y + end + attribute \src "ls180.v:6390.32-6390.78" + cell $eq $eq$ls180.v:6390$1868 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [13:8] + connect \B 5'10000 + connect \Y $eq$ls180.v:6390$1868_Y + end + attribute \src "ls180.v:6392.100-6392.144" + cell $eq $eq$ls180.v:6392$1870 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6392$1870_Y + end + attribute \src "ls180.v:6393.103-6393.147" + cell $eq $eq$ls180.v:6393$1874 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6393$1874_Y + end + attribute \src "ls180.v:6395.100-6395.144" + cell $eq $eq$ls180.v:6395$1877 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6395$1877_Y + end + attribute \src "ls180.v:6396.103-6396.147" + cell $eq $eq$ls180.v:6396$1881 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6396$1881_Y + end + attribute \src "ls180.v:6398.100-6398.144" + cell $eq $eq$ls180.v:6398$1884 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6398$1884_Y + end + attribute \src "ls180.v:6399.103-6399.147" + cell $eq $eq$ls180.v:6399$1888 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6399$1888_Y + end + attribute \src "ls180.v:6401.100-6401.144" + cell $eq $eq$ls180.v:6401$1891 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6401$1891_Y + end + attribute \src "ls180.v:6402.103-6402.147" + cell $eq $eq$ls180.v:6402$1895 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6402$1895_Y + end + attribute \src "ls180.v:6404.100-6404.144" + cell $eq $eq$ls180.v:6404$1898 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 3'100 + connect \Y $eq$ls180.v:6404$1898_Y + end + attribute \src "ls180.v:6405.103-6405.147" + cell $eq $eq$ls180.v:6405$1902 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 3'100 + connect \Y $eq$ls180.v:6405$1902_Y + end + attribute \src "ls180.v:6407.100-6407.144" + cell $eq $eq$ls180.v:6407$1905 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 3'101 + connect \Y $eq$ls180.v:6407$1905_Y + end + attribute \src "ls180.v:6408.103-6408.147" + cell $eq $eq$ls180.v:6408$1909 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 3'101 + connect \Y $eq$ls180.v:6408$1909_Y + end + attribute \src "ls180.v:6410.100-6410.144" + cell $eq $eq$ls180.v:6410$1912 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 3'110 + connect \Y $eq$ls180.v:6410$1912_Y + end + attribute \src "ls180.v:6411.103-6411.147" + cell $eq $eq$ls180.v:6411$1916 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 3'110 + connect \Y $eq$ls180.v:6411$1916_Y + end + attribute \src "ls180.v:6413.100-6413.144" + cell $eq $eq$ls180.v:6413$1919 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 3'111 + connect \Y $eq$ls180.v:6413$1919_Y + end + attribute \src "ls180.v:6414.103-6414.147" + cell $eq $eq$ls180.v:6414$1923 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 3'111 + connect \Y $eq$ls180.v:6414$1923_Y + end + attribute \src "ls180.v:6416.102-6416.146" + cell $eq $eq$ls180.v:6416$1926 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:6416$1926_Y + end + attribute \src "ls180.v:6417.105-6417.149" + cell $eq $eq$ls180.v:6417$1930 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:6417$1930_Y + end + attribute \src "ls180.v:6419.102-6419.146" + cell $eq $eq$ls180.v:6419$1933 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 4'1001 + connect \Y $eq$ls180.v:6419$1933_Y + end + attribute \src "ls180.v:6420.105-6420.149" + cell $eq $eq$ls180.v:6420$1937 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 4'1001 + connect \Y $eq$ls180.v:6420$1937_Y + end + attribute \src "ls180.v:6422.102-6422.147" + cell $eq $eq$ls180.v:6422$1940 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 4'1010 + connect \Y $eq$ls180.v:6422$1940_Y + end + attribute \src "ls180.v:6423.105-6423.150" + cell $eq $eq$ls180.v:6423$1944 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 4'1010 + connect \Y $eq$ls180.v:6423$1944_Y + end + attribute \src "ls180.v:6425.102-6425.147" + cell $eq $eq$ls180.v:6425$1947 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 4'1011 + connect \Y $eq$ls180.v:6425$1947_Y + end + attribute \src "ls180.v:6426.105-6426.150" + cell $eq $eq$ls180.v:6426$1951 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 4'1011 + connect \Y $eq$ls180.v:6426$1951_Y + end + attribute \src "ls180.v:6428.102-6428.147" + cell $eq $eq$ls180.v:6428$1954 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 4'1100 + connect \Y $eq$ls180.v:6428$1954_Y + end + attribute \src "ls180.v:6429.105-6429.150" + cell $eq $eq$ls180.v:6429$1958 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 4'1100 + connect \Y $eq$ls180.v:6429$1958_Y + end + attribute \src "ls180.v:6431.99-6431.144" + cell $eq $eq$ls180.v:6431$1961 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 4'1101 + connect \Y $eq$ls180.v:6431$1961_Y + end + attribute \src "ls180.v:6432.102-6432.147" + cell $eq $eq$ls180.v:6432$1965 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 4'1101 + connect \Y $eq$ls180.v:6432$1965_Y + end + attribute \src "ls180.v:6434.100-6434.145" + cell $eq $eq$ls180.v:6434$1968 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 4'1110 + connect \Y $eq$ls180.v:6434$1968_Y + end + attribute \src "ls180.v:6435.103-6435.148" + cell $eq $eq$ls180.v:6435$1972 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 4'1110 + connect \Y $eq$ls180.v:6435$1972_Y + end + attribute \src "ls180.v:6437.102-6437.147" + cell $eq $eq$ls180.v:6437$1975 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 4'1111 + connect \Y $eq$ls180.v:6437$1975_Y + end + attribute \src "ls180.v:6438.105-6438.150" + cell $eq $eq$ls180.v:6438$1979 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 4'1111 + connect \Y $eq$ls180.v:6438$1979_Y + end + attribute \src "ls180.v:6440.102-6440.147" + cell $eq $eq$ls180.v:6440$1982 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 5'10000 + connect \Y $eq$ls180.v:6440$1982_Y + end + attribute \src "ls180.v:6441.105-6441.150" + cell $eq $eq$ls180.v:6441$1986 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 5'10000 + connect \Y $eq$ls180.v:6441$1986_Y + end + attribute \src "ls180.v:6443.102-6443.147" + cell $eq $eq$ls180.v:6443$1989 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 5'10001 + connect \Y $eq$ls180.v:6443$1989_Y + end + attribute \src "ls180.v:6444.105-6444.150" + cell $eq $eq$ls180.v:6444$1993 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 5'10001 + connect \Y $eq$ls180.v:6444$1993_Y + end + attribute \src "ls180.v:6446.102-6446.147" + cell $eq $eq$ls180.v:6446$1996 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 5'10010 + connect \Y $eq$ls180.v:6446$1996_Y + end + attribute \src "ls180.v:6447.105-6447.150" + cell $eq $eq$ls180.v:6447$2000 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [4:0] + connect \B 5'10010 + connect \Y $eq$ls180.v:6447$2000_Y + end + attribute \src "ls180.v:6469.32-6469.78" + cell $eq $eq$ls180.v:6469$2002 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_adr [13:8] + connect \B 4'1101 + connect \Y $eq$ls180.v:6469$2002_Y + end + attribute \src "ls180.v:6471.102-6471.146" + cell $eq $eq$ls180.v:6471$2004 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_adr [1:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6471$2004_Y + end + attribute \src "ls180.v:6472.105-6472.149" + cell $eq $eq$ls180.v:6472$2008 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_adr [1:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6472$2008_Y + end + attribute \src "ls180.v:6474.107-6474.151" + cell $eq $eq$ls180.v:6474$2011 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_adr [1:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6474$2011_Y + end + attribute \src "ls180.v:6475.110-6475.154" + cell $eq $eq$ls180.v:6475$2015 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_adr [1:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6475$2015_Y + end + attribute \src "ls180.v:6477.107-6477.151" + cell $eq $eq$ls180.v:6477$2018 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_adr [1:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6477$2018_Y + end + attribute \src "ls180.v:6478.110-6478.154" + cell $eq $eq$ls180.v:6478$2022 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_adr [1:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6478$2022_Y + end + attribute \src "ls180.v:6480.100-6480.144" + cell $eq $eq$ls180.v:6480$2025 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_adr [1:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6480$2025_Y + end + attribute \src "ls180.v:6481.103-6481.147" + cell $eq $eq$ls180.v:6481$2029 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_adr [1:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6481$2029_Y + end + attribute \src "ls180.v:6486.32-6486.77" + cell $eq $eq$ls180.v:6486$2031 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [13:8] + connect \B 2'11 + connect \Y $eq$ls180.v:6486$2031_Y + end + attribute \src "ls180.v:6488.104-6488.148" + cell $eq $eq$ls180.v:6488$2033 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [3:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6488$2033_Y + end + attribute \src "ls180.v:6489.107-6489.151" + cell $eq $eq$ls180.v:6489$2037 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [3:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6489$2037_Y + end + attribute \src "ls180.v:6491.108-6491.152" + cell $eq $eq$ls180.v:6491$2040 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [3:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6491$2040_Y + end + attribute \src "ls180.v:6492.111-6492.155" + cell $eq $eq$ls180.v:6492$2044 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [3:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6492$2044_Y + end + attribute \src "ls180.v:6494.98-6494.142" + cell $eq $eq$ls180.v:6494$2047 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [3:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6494$2047_Y + end + attribute \src "ls180.v:6495.101-6495.145" + cell $eq $eq$ls180.v:6495$2051 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [3:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6495$2051_Y + end + attribute \src "ls180.v:6497.108-6497.152" + cell $eq $eq$ls180.v:6497$2054 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [3:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6497$2054_Y + end + attribute \src "ls180.v:6498.111-6498.155" + cell $eq $eq$ls180.v:6498$2058 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [3:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6498$2058_Y + end + attribute \src "ls180.v:6500.108-6500.152" + cell $eq $eq$ls180.v:6500$2061 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [3:0] + connect \B 3'100 + connect \Y $eq$ls180.v:6500$2061_Y + end + attribute \src "ls180.v:6501.111-6501.155" + cell $eq $eq$ls180.v:6501$2065 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [3:0] + connect \B 3'100 + connect \Y $eq$ls180.v:6501$2065_Y + end + attribute \src "ls180.v:6503.109-6503.153" + cell $eq $eq$ls180.v:6503$2068 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [3:0] + connect \B 3'101 + connect \Y $eq$ls180.v:6503$2068_Y + end + attribute \src "ls180.v:6504.112-6504.156" + cell $eq $eq$ls180.v:6504$2072 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [3:0] + connect \B 3'101 + connect \Y $eq$ls180.v:6504$2072_Y + end + attribute \src "ls180.v:6506.107-6506.151" + cell $eq $eq$ls180.v:6506$2075 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [3:0] + connect \B 3'110 + connect \Y $eq$ls180.v:6506$2075_Y + end + attribute \src "ls180.v:6507.110-6507.154" + cell $eq $eq$ls180.v:6507$2079 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [3:0] + connect \B 3'110 + connect \Y $eq$ls180.v:6507$2079_Y + end + attribute \src "ls180.v:6509.107-6509.151" + cell $eq $eq$ls180.v:6509$2082 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [3:0] + connect \B 3'111 + connect \Y $eq$ls180.v:6509$2082_Y + end + attribute \src "ls180.v:6510.110-6510.154" + cell $eq $eq$ls180.v:6510$2086 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [3:0] + connect \B 3'111 + connect \Y $eq$ls180.v:6510$2086_Y + end + attribute \src "ls180.v:6512.107-6512.151" + cell $eq $eq$ls180.v:6512$2089 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [3:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:6512$2089_Y + end + attribute \src "ls180.v:6513.110-6513.154" + cell $eq $eq$ls180.v:6513$2093 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [3:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:6513$2093_Y + end + attribute \src "ls180.v:6515.107-6515.151" + cell $eq $eq$ls180.v:6515$2096 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [3:0] + connect \B 4'1001 + connect \Y $eq$ls180.v:6515$2096_Y + end + attribute \src "ls180.v:6516.110-6516.154" + cell $eq $eq$ls180.v:6516$2100 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [3:0] + connect \B 4'1001 + connect \Y $eq$ls180.v:6516$2100_Y + end + attribute \src "ls180.v:6531.33-6531.79" + cell $eq $eq$ls180.v:6531$2102 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [13:8] + connect \B 4'1000 + connect \Y $eq$ls180.v:6531$2102_Y + end + attribute \src "ls180.v:6533.102-6533.147" + cell $eq $eq$ls180.v:6533$2104 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [2:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6533$2104_Y + end + attribute \src "ls180.v:6534.105-6534.150" + cell $eq $eq$ls180.v:6534$2108 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [2:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6534$2108_Y + end + attribute \src "ls180.v:6536.102-6536.147" + cell $eq $eq$ls180.v:6536$2111 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [2:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6536$2111_Y + end + attribute \src "ls180.v:6537.105-6537.150" + cell $eq $eq$ls180.v:6537$2115 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [2:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6537$2115_Y + end + attribute \src "ls180.v:6539.100-6539.145" + cell $eq $eq$ls180.v:6539$2118 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [2:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6539$2118_Y + end + attribute \src "ls180.v:6540.103-6540.148" + cell $eq $eq$ls180.v:6540$2122 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [2:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6540$2122_Y + end + attribute \src "ls180.v:6542.99-6542.144" + cell $eq $eq$ls180.v:6542$2125 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [2:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6542$2125_Y + end + attribute \src "ls180.v:6543.102-6543.147" + cell $eq $eq$ls180.v:6543$2129 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [2:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6543$2129_Y + end + attribute \src "ls180.v:6545.98-6545.143" + cell $eq $eq$ls180.v:6545$2132 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [2:0] + connect \B 3'100 + connect \Y $eq$ls180.v:6545$2132_Y + end + attribute \src "ls180.v:6546.101-6546.146" + cell $eq $eq$ls180.v:6546$2136 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [2:0] + connect \B 3'100 + connect \Y $eq$ls180.v:6546$2136_Y + end + attribute \src "ls180.v:6548.97-6548.142" + cell $eq $eq$ls180.v:6548$2139 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [2:0] + connect \B 3'101 + connect \Y $eq$ls180.v:6548$2139_Y + end + attribute \src "ls180.v:6549.100-6549.145" + cell $eq $eq$ls180.v:6549$2143 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [2:0] + connect \B 3'101 + connect \Y $eq$ls180.v:6549$2143_Y + end + attribute \src "ls180.v:6551.103-6551.148" + cell $eq $eq$ls180.v:6551$2146 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [2:0] + connect \B 3'110 + connect \Y $eq$ls180.v:6551$2146_Y + end + attribute \src "ls180.v:6552.106-6552.151" + cell $eq $eq$ls180.v:6552$2150 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [2:0] + connect \B 3'110 + connect \Y $eq$ls180.v:6552$2150_Y + end + attribute \src "ls180.v:6571.33-6571.79" + cell $eq $eq$ls180.v:6571$2153 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [13:8] + connect \B 4'1001 + connect \Y $eq$ls180.v:6571$2153_Y + end + attribute \src "ls180.v:6573.102-6573.147" + cell $eq $eq$ls180.v:6573$2155 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [3:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6573$2155_Y + end + attribute \src "ls180.v:6574.105-6574.150" + cell $eq $eq$ls180.v:6574$2159 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [3:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6574$2159_Y + end + attribute \src "ls180.v:6576.102-6576.147" + cell $eq $eq$ls180.v:6576$2162 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [3:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6576$2162_Y + end + attribute \src "ls180.v:6577.105-6577.150" + cell $eq $eq$ls180.v:6577$2166 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [3:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6577$2166_Y + end + attribute \src "ls180.v:6579.100-6579.145" + cell $eq $eq$ls180.v:6579$2169 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [3:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6579$2169_Y + end + attribute \src "ls180.v:6580.103-6580.148" + cell $eq $eq$ls180.v:6580$2173 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [3:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6580$2173_Y + end + attribute \src "ls180.v:6582.99-6582.144" + cell $eq $eq$ls180.v:6582$2176 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [3:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6582$2176_Y + end + attribute \src "ls180.v:6583.102-6583.147" + cell $eq $eq$ls180.v:6583$2180 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [3:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6583$2180_Y + end + attribute \src "ls180.v:6585.98-6585.143" + cell $eq $eq$ls180.v:6585$2183 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [3:0] + connect \B 3'100 + connect \Y $eq$ls180.v:6585$2183_Y + end + attribute \src "ls180.v:6586.101-6586.146" + cell $eq $eq$ls180.v:6586$2187 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [3:0] + connect \B 3'100 + connect \Y $eq$ls180.v:6586$2187_Y + end + attribute \src "ls180.v:6588.97-6588.142" + cell $eq $eq$ls180.v:6588$2190 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [3:0] + connect \B 3'101 + connect \Y $eq$ls180.v:6588$2190_Y + end + attribute \src "ls180.v:6589.100-6589.145" + cell $eq $eq$ls180.v:6589$2194 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [3:0] + connect \B 3'101 + connect \Y $eq$ls180.v:6589$2194_Y + end + attribute \src "ls180.v:6591.103-6591.148" + cell $eq $eq$ls180.v:6591$2197 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [3:0] + connect \B 3'110 + connect \Y $eq$ls180.v:6591$2197_Y + end + attribute \src "ls180.v:6592.106-6592.151" + cell $eq $eq$ls180.v:6592$2201 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [3:0] + connect \B 3'110 + connect \Y $eq$ls180.v:6592$2201_Y + end + attribute \src "ls180.v:6594.106-6594.151" + cell $eq $eq$ls180.v:6594$2204 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [3:0] + connect \B 3'111 + connect \Y $eq$ls180.v:6594$2204_Y + end + attribute \src "ls180.v:6595.109-6595.154" + cell $eq $eq$ls180.v:6595$2208 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [3:0] + connect \B 3'111 + connect \Y $eq$ls180.v:6595$2208_Y + end + attribute \src "ls180.v:6597.106-6597.151" + cell $eq $eq$ls180.v:6597$2211 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [3:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:6597$2211_Y + end + attribute \src "ls180.v:6598.109-6598.154" + cell $eq $eq$ls180.v:6598$2215 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [3:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:6598$2215_Y + end + attribute \src "ls180.v:6619.33-6619.79" + cell $eq $eq$ls180.v:6619$2218 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [13:8] + connect \B 2'10 + connect \Y $eq$ls180.v:6619$2218_Y + end + attribute \src "ls180.v:6621.99-6621.144" + cell $eq $eq$ls180.v:6621$2220 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6621$2220_Y + end + attribute \src "ls180.v:6622.102-6622.147" + cell $eq $eq$ls180.v:6622$2224 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6622$2224_Y + end + attribute \src "ls180.v:6624.99-6624.144" + cell $eq $eq$ls180.v:6624$2227 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6624$2227_Y + end + attribute \src "ls180.v:6625.102-6625.147" + cell $eq $eq$ls180.v:6625$2231 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6625$2231_Y + end + attribute \src "ls180.v:6627.99-6627.144" + cell $eq $eq$ls180.v:6627$2234 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6627$2234_Y + end + attribute \src "ls180.v:6628.102-6628.147" + cell $eq $eq$ls180.v:6628$2238 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6628$2238_Y + end + attribute \src "ls180.v:6630.99-6630.144" + cell $eq $eq$ls180.v:6630$2241 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6630$2241_Y + end + attribute \src "ls180.v:6631.102-6631.147" + cell $eq $eq$ls180.v:6631$2245 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6631$2245_Y + end + attribute \src "ls180.v:6633.101-6633.146" + cell $eq $eq$ls180.v:6633$2248 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 3'100 + connect \Y $eq$ls180.v:6633$2248_Y + end + attribute \src "ls180.v:6634.104-6634.149" + cell $eq $eq$ls180.v:6634$2252 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 3'100 + connect \Y $eq$ls180.v:6634$2252_Y + end + attribute \src "ls180.v:6636.101-6636.146" + cell $eq $eq$ls180.v:6636$2255 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 3'101 + connect \Y $eq$ls180.v:6636$2255_Y + end + attribute \src "ls180.v:6637.104-6637.149" + cell $eq $eq$ls180.v:6637$2259 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 3'101 + connect \Y $eq$ls180.v:6637$2259_Y + end + attribute \src "ls180.v:6639.101-6639.146" + cell $eq $eq$ls180.v:6639$2262 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 3'110 + connect \Y $eq$ls180.v:6639$2262_Y + end + attribute \src "ls180.v:6640.104-6640.149" + cell $eq $eq$ls180.v:6640$2266 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 3'110 + connect \Y $eq$ls180.v:6640$2266_Y + end + attribute \src "ls180.v:6642.101-6642.146" + cell $eq $eq$ls180.v:6642$2269 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 3'111 + connect \Y $eq$ls180.v:6642$2269_Y + end + attribute \src "ls180.v:6643.104-6643.149" + cell $eq $eq$ls180.v:6643$2273 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 3'111 + connect \Y $eq$ls180.v:6643$2273_Y + end + attribute \src "ls180.v:6645.97-6645.142" + cell $eq $eq$ls180.v:6645$2276 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:6645$2276_Y + end + attribute \src "ls180.v:6646.100-6646.145" + cell $eq $eq$ls180.v:6646$2280 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:6646$2280_Y + end + attribute \src "ls180.v:6648.107-6648.152" + cell $eq $eq$ls180.v:6648$2283 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 4'1001 + connect \Y $eq$ls180.v:6648$2283_Y + end + attribute \src "ls180.v:6649.110-6649.155" + cell $eq $eq$ls180.v:6649$2287 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 4'1001 + connect \Y $eq$ls180.v:6649$2287_Y + end + attribute \src "ls180.v:6651.100-6651.146" + cell $eq $eq$ls180.v:6651$2290 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 4'1010 + connect \Y $eq$ls180.v:6651$2290_Y + end + attribute \src "ls180.v:6652.103-6652.149" + cell $eq $eq$ls180.v:6652$2294 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 4'1010 + connect \Y $eq$ls180.v:6652$2294_Y + end + attribute \src "ls180.v:6654.100-6654.146" + cell $eq $eq$ls180.v:6654$2297 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 4'1011 + connect \Y $eq$ls180.v:6654$2297_Y + end + attribute \src "ls180.v:6655.103-6655.149" + cell $eq $eq$ls180.v:6655$2301 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 4'1011 + connect \Y $eq$ls180.v:6655$2301_Y + end + attribute \src "ls180.v:6657.100-6657.146" + cell $eq $eq$ls180.v:6657$2304 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 4'1100 + connect \Y $eq$ls180.v:6657$2304_Y + end + attribute \src "ls180.v:6658.103-6658.149" + cell $eq $eq$ls180.v:6658$2308 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 4'1100 + connect \Y $eq$ls180.v:6658$2308_Y + end + attribute \src "ls180.v:6660.100-6660.146" + cell $eq $eq$ls180.v:6660$2311 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 4'1101 + connect \Y $eq$ls180.v:6660$2311_Y + end + attribute \src "ls180.v:6661.103-6661.149" + cell $eq $eq$ls180.v:6661$2315 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 4'1101 + connect \Y $eq$ls180.v:6661$2315_Y + end + attribute \src "ls180.v:6663.112-6663.158" + cell $eq $eq$ls180.v:6663$2318 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 4'1110 + connect \Y $eq$ls180.v:6663$2318_Y + end + attribute \src "ls180.v:6664.115-6664.161" + cell $eq $eq$ls180.v:6664$2322 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 4'1110 + connect \Y $eq$ls180.v:6664$2322_Y + end + attribute \src "ls180.v:6666.113-6666.159" + cell $eq $eq$ls180.v:6666$2325 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 4'1111 + connect \Y $eq$ls180.v:6666$2325_Y + end + attribute \src "ls180.v:6667.116-6667.162" + cell $eq $eq$ls180.v:6667$2329 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 4'1111 + connect \Y $eq$ls180.v:6667$2329_Y + end + attribute \src "ls180.v:6669.104-6669.150" + cell $eq $eq$ls180.v:6669$2332 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 5'10000 + connect \Y $eq$ls180.v:6669$2332_Y + end + attribute \src "ls180.v:6670.107-6670.153" + cell $eq $eq$ls180.v:6670$2336 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [4:0] + connect \B 5'10000 + connect \Y $eq$ls180.v:6670$2336_Y + end + attribute \src "ls180.v:6687.33-6687.79" + cell $eq $eq$ls180.v:6687$2338 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_adr [13:8] + connect \B 3'101 + connect \Y $eq$ls180.v:6687$2338_Y + end + attribute \src "ls180.v:6689.90-6689.135" + cell $eq $eq$ls180.v:6689$2340 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_adr [2:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6689$2340_Y + end + attribute \src "ls180.v:6690.93-6690.138" + cell $eq $eq$ls180.v:6690$2344 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_adr [2:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6690$2344_Y + end + attribute \src "ls180.v:6692.100-6692.145" + cell $eq $eq$ls180.v:6692$2347 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_adr [2:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6692$2347_Y + end + attribute \src "ls180.v:6693.103-6693.148" + cell $eq $eq$ls180.v:6693$2351 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_adr [2:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6693$2351_Y + end + attribute \src "ls180.v:6695.101-6695.146" + cell $eq $eq$ls180.v:6695$2354 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_adr [2:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6695$2354_Y + end + attribute \src "ls180.v:6696.104-6696.149" + cell $eq $eq$ls180.v:6696$2358 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_adr [2:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6696$2358_Y + end + attribute \src "ls180.v:6698.105-6698.150" + cell $eq $eq$ls180.v:6698$2361 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_adr [2:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6698$2361_Y + end + attribute \src "ls180.v:6699.108-6699.153" + cell $eq $eq$ls180.v:6699$2365 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_adr [2:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6699$2365_Y + end + attribute \src "ls180.v:6701.106-6701.151" + cell $eq $eq$ls180.v:6701$2368 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_adr [2:0] + connect \B 3'100 + connect \Y $eq$ls180.v:6701$2368_Y + end + attribute \src "ls180.v:6702.109-6702.154" + cell $eq $eq$ls180.v:6702$2372 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_adr [2:0] + connect \B 3'100 + connect \Y $eq$ls180.v:6702$2372_Y + end + attribute \src "ls180.v:6704.104-6704.149" + cell $eq $eq$ls180.v:6704$2375 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_adr [2:0] + connect \B 3'101 + connect \Y $eq$ls180.v:6704$2375_Y + end + attribute \src "ls180.v:6705.107-6705.152" + cell $eq $eq$ls180.v:6705$2379 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_adr [2:0] + connect \B 3'101 + connect \Y $eq$ls180.v:6705$2379_Y + end + attribute \src "ls180.v:6707.101-6707.146" + cell $eq $eq$ls180.v:6707$2382 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_adr [2:0] + connect \B 3'110 + connect \Y $eq$ls180.v:6707$2382_Y + end + attribute \src "ls180.v:6708.104-6708.149" + cell $eq $eq$ls180.v:6708$2386 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_adr [2:0] + connect \B 3'110 + connect \Y $eq$ls180.v:6708$2386_Y + end + attribute \src "ls180.v:6710.100-6710.145" + cell $eq $eq$ls180.v:6710$2389 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_adr [2:0] + connect \B 3'111 + connect \Y $eq$ls180.v:6710$2389_Y + end + attribute \src "ls180.v:6711.103-6711.148" + cell $eq $eq$ls180.v:6711$2393 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_adr [2:0] + connect \B 3'111 + connect \Y $eq$ls180.v:6711$2393_Y + end + attribute \src "ls180.v:6721.33-6721.79" + cell $eq $eq$ls180.v:6721$2395 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface14_bank_bus_adr [13:8] + connect \B 3'100 + connect \Y $eq$ls180.v:6721$2395_Y + end + attribute \src "ls180.v:6723.106-6723.151" + cell $eq $eq$ls180.v:6723$2397 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface14_bank_bus_adr [1:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6723$2397_Y + end + attribute \src "ls180.v:6724.109-6724.154" + cell $eq $eq$ls180.v:6724$2401 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface14_bank_bus_adr [1:0] + connect \B 1'0 + connect \Y $eq$ls180.v:6724$2401_Y + end + attribute \src "ls180.v:6726.106-6726.151" + cell $eq $eq$ls180.v:6726$2404 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface14_bank_bus_adr [1:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6726$2404_Y + end + attribute \src "ls180.v:6727.109-6727.154" + cell $eq $eq$ls180.v:6727$2408 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface14_bank_bus_adr [1:0] + connect \B 1'1 + connect \Y $eq$ls180.v:6727$2408_Y + end + attribute \src "ls180.v:6729.106-6729.151" + cell $eq $eq$ls180.v:6729$2411 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface14_bank_bus_adr [1:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6729$2411_Y + end + attribute \src "ls180.v:6730.109-6730.154" + cell $eq $eq$ls180.v:6730$2415 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface14_bank_bus_adr [1:0] + connect \B 2'10 + connect \Y $eq$ls180.v:6730$2415_Y + end + attribute \src "ls180.v:6732.106-6732.151" + cell $eq $eq$ls180.v:6732$2418 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface14_bank_bus_adr [1:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6732$2418_Y + end + attribute \src "ls180.v:6733.109-6733.154" + cell $eq $eq$ls180.v:6733$2422 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface14_bank_bus_adr [1:0] + connect \B 2'11 + connect \Y $eq$ls180.v:6733$2422_Y + end + attribute \src "ls180.v:7114.41-7114.81" + cell $eq $eq$ls180.v:7114$2459 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_payload_addr [10:9] + connect \B 1'0 + connect \Y $eq$ls180.v:7114$2459_Y + end + attribute \src "ls180.v:7114.144-7114.177" + cell $eq $eq$ls180.v:7114$2460 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin1_grant + connect \B 1'0 + connect \Y $eq$ls180.v:7114$2460_Y + end + attribute \src "ls180.v:7114.219-7114.252" + cell $eq $eq$ls180.v:7114$2463 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin2_grant + connect \B 1'0 + connect \Y $eq$ls180.v:7114$2463_Y + end + attribute \src "ls180.v:7114.294-7114.327" + cell $eq $eq$ls180.v:7114$2466 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin3_grant + connect \B 1'0 + connect \Y $eq$ls180.v:7114$2466_Y + end + attribute \src "ls180.v:7138.41-7138.81" + cell $eq $eq$ls180.v:7138$2475 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_payload_addr [10:9] + connect \B 1'1 + connect \Y $eq$ls180.v:7138$2475_Y + end + attribute \src "ls180.v:7138.144-7138.177" + cell $eq $eq$ls180.v:7138$2476 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin0_grant + connect \B 1'0 + connect \Y $eq$ls180.v:7138$2476_Y + end + attribute \src "ls180.v:7138.219-7138.252" + cell $eq $eq$ls180.v:7138$2479 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin2_grant + connect \B 1'0 + connect \Y $eq$ls180.v:7138$2479_Y + end + attribute \src "ls180.v:7138.294-7138.327" + cell $eq $eq$ls180.v:7138$2482 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin3_grant + connect \B 1'0 + connect \Y $eq$ls180.v:7138$2482_Y + end + attribute \src "ls180.v:7162.41-7162.81" + cell $eq $eq$ls180.v:7162$2491 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_payload_addr [10:9] + connect \B 2'10 + connect \Y $eq$ls180.v:7162$2491_Y + end + attribute \src "ls180.v:7162.144-7162.177" + cell $eq $eq$ls180.v:7162$2492 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin0_grant + connect \B 1'0 + connect \Y $eq$ls180.v:7162$2492_Y + end + attribute \src "ls180.v:7162.219-7162.252" + cell $eq $eq$ls180.v:7162$2495 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin1_grant + connect \B 1'0 + connect \Y $eq$ls180.v:7162$2495_Y + end + attribute \src "ls180.v:7162.294-7162.327" + cell $eq $eq$ls180.v:7162$2498 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin3_grant + connect \B 1'0 + connect \Y $eq$ls180.v:7162$2498_Y + end + attribute \src "ls180.v:7186.41-7186.81" + cell $eq $eq$ls180.v:7186$2507 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_payload_addr [10:9] + connect \B 2'11 + connect \Y $eq$ls180.v:7186$2507_Y + end + attribute \src "ls180.v:7186.144-7186.177" + cell $eq $eq$ls180.v:7186$2508 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin0_grant + connect \B 1'0 + connect \Y $eq$ls180.v:7186$2508_Y + end + attribute \src "ls180.v:7186.219-7186.252" + cell $eq $eq$ls180.v:7186$2511 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin1_grant + connect \B 1'0 + connect \Y $eq$ls180.v:7186$2511_Y + end + attribute \src "ls180.v:7186.294-7186.327" + cell $eq $eq$ls180.v:7186$2514 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin2_grant + connect \B 1'0 + connect \Y $eq$ls180.v:7186$2514_Y + end + attribute \src "ls180.v:7770.8-7770.38" + cell $eq $eq$ls180.v:7770$2606 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_value + connect \B 1'0 + connect \Y $eq$ls180.v:7770$2606_Y + end + attribute \src "ls180.v:7817.8-7817.42" + cell $eq $eq$ls180.v:7817$2626 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_postponer_count + connect \B 1'0 + connect \Y $eq$ls180.v:7817$2626_Y + end + attribute \src "ls180.v:7837.38-7837.74" + cell $eq $eq$ls180.v:7837$2629 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_sequencer_counter + connect \B 1'0 + connect \Y $eq$ls180.v:7837$2629_Y + end + attribute \src "ls180.v:7844.7-7844.43" + cell $eq $eq$ls180.v:7844$2631 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \main_sdram_sequencer_counter + connect \B 2'10 + connect \Y $eq$ls180.v:7844$2631_Y + end + attribute \src "ls180.v:7851.7-7851.43" + cell $eq $eq$ls180.v:7851$2632 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \main_sdram_sequencer_counter + connect \B 4'1000 + connect \Y $eq$ls180.v:7851$2632_Y + end + attribute \src "ls180.v:7859.7-7859.43" + cell $eq $eq$ls180.v:7859$2633 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \main_sdram_sequencer_counter + connect \B 4'1000 + connect \Y $eq$ls180.v:7859$2633_Y + end + attribute \src "ls180.v:7911.9-7911.54" + cell $eq $eq$ls180.v:7911$2651 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_twtpcon_count + connect \B 1'1 + connect \Y $eq$ls180.v:7911$2651_Y + end + attribute \src "ls180.v:7957.9-7957.54" + cell $eq $eq$ls180.v:7957$2667 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_twtpcon_count + connect \B 1'1 + connect \Y $eq$ls180.v:7957$2667_Y + end + attribute \src "ls180.v:8003.9-8003.54" + cell $eq $eq$ls180.v:8003$2683 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_twtpcon_count + connect \B 1'1 + connect \Y $eq$ls180.v:8003$2683_Y + end + attribute \src "ls180.v:8049.9-8049.54" + cell $eq $eq$ls180.v:8049$2699 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_twtpcon_count + connect \B 1'1 + connect \Y $eq$ls180.v:8049$2699_Y + end + attribute \src "ls180.v:8199.9-8199.41" + cell $eq $eq$ls180.v:8199$2711 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_tccdcon_count + connect \B 1'1 + connect \Y $eq$ls180.v:8199$2711_Y + end + attribute \src "ls180.v:8214.9-8214.41" + cell $eq $eq$ls180.v:8214$2714 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_twtrcon_count + connect \B 1'1 + connect \Y $eq$ls180.v:8214$2714_Y + end + attribute \src "ls180.v:8220.49-8220.82" + cell $eq $eq$ls180.v:8220$2715 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin0_grant + connect \B 1'0 + connect \Y $eq$ls180.v:8220$2715_Y + end + attribute \src "ls180.v:8220.131-8220.164" + cell $eq $eq$ls180.v:8220$2718 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin1_grant + connect \B 1'0 + connect \Y $eq$ls180.v:8220$2718_Y + end + attribute \src "ls180.v:8220.213-8220.246" + cell $eq $eq$ls180.v:8220$2721 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin2_grant + connect \B 1'0 + connect \Y $eq$ls180.v:8220$2721_Y + end + attribute \src "ls180.v:8220.295-8220.328" + cell $eq $eq$ls180.v:8220$2724 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin3_grant + connect \B 1'0 + connect \Y $eq$ls180.v:8220$2724_Y + end + attribute \src "ls180.v:8221.50-8221.83" + cell $eq $eq$ls180.v:8221$2727 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin0_grant + connect \B 1'0 + connect \Y $eq$ls180.v:8221$2727_Y + end + attribute \src "ls180.v:8221.132-8221.165" + cell $eq $eq$ls180.v:8221$2730 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin1_grant + connect \B 1'0 + connect \Y $eq$ls180.v:8221$2730_Y + end + attribute \src "ls180.v:8221.214-8221.247" + cell $eq $eq$ls180.v:8221$2733 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin2_grant + connect \B 1'0 + connect \Y $eq$ls180.v:8221$2733_Y + end + attribute \src "ls180.v:8221.296-8221.329" + cell $eq $eq$ls180.v:8221$2736 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin3_grant + connect \B 1'0 + connect \Y $eq$ls180.v:8221$2736_Y + end + attribute \src "ls180.v:8256.9-8256.42" + cell $eq $eq$ls180.v:8256$2748 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \main_uart_phy_tx_bitcount + connect \B 4'1000 + connect \Y $eq$ls180.v:8256$2748_Y + end + attribute \src "ls180.v:8259.10-8259.43" + cell $eq $eq$ls180.v:8259$2749 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \main_uart_phy_tx_bitcount + connect \B 4'1001 + connect \Y $eq$ls180.v:8259$2749_Y + end + attribute \src "ls180.v:8285.9-8285.42" + cell $eq $eq$ls180.v:8285$2755 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_phy_rx_bitcount + connect \B 1'0 + connect \Y $eq$ls180.v:8285$2755_Y + end + attribute \src "ls180.v:8290.10-8290.43" + cell $eq $eq$ls180.v:8290$2756 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \main_uart_phy_rx_bitcount + connect \B 4'1001 + connect \Y $eq$ls180.v:8290$2756_Y + end + attribute \src "ls180.v:8497.9-8497.53" + cell $eq $eq$ls180.v:8497$2805 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_cmdr_converter_demux + connect \B 3'111 + connect \Y $eq$ls180.v:8497$2805_Y + end + attribute \src "ls180.v:8578.9-8578.54" + cell $eq $eq$ls180.v:8578$2817 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_crcr_converter_demux + connect \B 3'111 + connect \Y $eq$ls180.v:8578$2817_Y + end + attribute \src "ls180.v:8657.9-8657.55" + cell $eq $eq$ls180.v:8657$2829 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_datar_converter_demux + connect \B 1'1 + connect \Y $eq$ls180.v:8657$2829_Y + end + attribute \src "ls180.v:8880.9-8880.49" + cell $eq $eq$ls180.v:8880$2862 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_converter_demux + connect \B 3'111 + connect \Y $eq$ls180.v:8880$2862_Y + end + attribute \src "ls180.v:8456.8-8456.54" + cell $ge $ge$ls180.v:8456$2797 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 1 + connect \A \main_pwm0_counter + connect \B $sub$ls180.v:8456$2796_Y + connect \Y $ge$ls180.v:8456$2797_Y + end + attribute \src "ls180.v:8470.8-8470.54" + cell $ge $ge$ls180.v:8470$2801 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 1 + connect \A \main_pwm1_counter + connect \B $sub$ls180.v:8470$2800_Y + connect \Y $ge$ls180.v:8470$2801_Y + end + attribute \src "ls180.v:5339.47-5339.83" + cell $gt $gt$ls180.v:5339$1064 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_cnt + connect \B 3'111 + connect \Y $gt$ls180.v:5339$1064_Y + end + attribute \src "ls180.v:5345.7-5345.43" + cell $lt $lt$ls180.v:5345$1067 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_cnt + connect \B 4'1000 + connect \Y $lt$ls180.v:5345$1067_Y + end + attribute \src "ls180.v:8451.8-8451.43" + cell $lt $lt$ls180.v:8451$2795 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 1 + connect \A \main_pwm0_counter + connect \B \main_pwm0_width + connect \Y $lt$ls180.v:8451$2795_Y + end + attribute \src "ls180.v:8465.8-8465.43" + cell $lt $lt$ls180.v:8465$2799 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 1 + connect \A \main_pwm1_counter + connect \B \main_pwm1_width + connect \Y $lt$ls180.v:8465$2799_Y + end + attribute \src "ls180.v:10370.33-10370.36" + cell $memrd $memrd$\mem$ls180.v:10370$2916 + parameter \ABITS 6 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem" + parameter \TRANSPARENT 0 + parameter \WIDTH 64 + connect \ADDR \memadr + connect \CLK 1'x + connect \DATA $memrd$\mem$ls180.v:10370$2916_DATA + connect \EN 1'x + end + attribute \src "ls180.v:10398.27-10398.32" + cell $memrd $memrd$\mem_1$ls180.v:10398$2942 + parameter \ABITS 6 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem_1" + parameter \TRANSPARENT 0 + parameter \WIDTH 64 + connect \ADDR \memadr_1 + connect \CLK 1'x + connect \DATA $memrd$\mem_1$ls180.v:10398$2942_DATA + connect \EN 1'x + end + attribute \src "ls180.v:10426.27-10426.32" + cell $memrd $memrd$\mem_2$ls180.v:10426$2968 + parameter \ABITS 6 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem_2" + parameter \TRANSPARENT 0 + parameter \WIDTH 64 + connect \ADDR \memadr_2 + connect \CLK 1'x + connect \DATA $memrd$\mem_2$ls180.v:10426$2968_DATA + connect \EN 1'x + end + attribute \src "ls180.v:10454.27-10454.32" + cell $memrd $memrd$\mem_3$ls180.v:10454$2994 + parameter \ABITS 6 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem_3" + parameter \TRANSPARENT 0 + parameter \WIDTH 64 + connect \ADDR \memadr_3 + connect \CLK 1'x + connect \DATA $memrd$\mem_3$ls180.v:10454$2994_DATA + connect \EN 1'x + end + attribute \src "ls180.v:10482.27-10482.32" + cell $memrd $memrd$\mem_4$ls180.v:10482$3020 + parameter \ABITS 6 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem_4" + parameter \TRANSPARENT 0 + parameter \WIDTH 64 + connect \ADDR \memadr_4 + connect \CLK 1'x + connect \DATA $memrd$\mem_4$ls180.v:10482$3020_DATA + connect \EN 1'x + end + attribute \src "ls180.v:10493.12-10493.19" + cell $memrd $memrd$\storage$ls180.v:10493$3025 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage" + parameter \TRANSPARENT 0 + parameter \WIDTH 25 + connect \ADDR \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage$ls180.v:10493$3025_DATA + connect \EN 1'x + end + attribute \src "ls180.v:10500.68-10500.75" + cell $memrd $memrd$\storage$ls180.v:10500$3027 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage" + parameter \TRANSPARENT 0 + parameter \WIDTH 25 + connect \ADDR \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage$ls180.v:10500$3027_DATA + connect \EN 1'x + end + attribute \src "ls180.v:10507.14-10507.23" + cell $memrd $memrd$\storage_1$ls180.v:10507$3032 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_1" + parameter \TRANSPARENT 0 + parameter \WIDTH 25 + connect \ADDR \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage_1$ls180.v:10507$3032_DATA + connect \EN 1'x + end + attribute \src "ls180.v:10514.68-10514.77" + cell $memrd $memrd$\storage_1$ls180.v:10514$3034 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_1" + parameter \TRANSPARENT 0 + parameter \WIDTH 25 + connect \ADDR \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage_1$ls180.v:10514$3034_DATA + connect \EN 1'x + end + attribute \src "ls180.v:10521.14-10521.23" + cell $memrd $memrd$\storage_2$ls180.v:10521$3039 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_2" + parameter \TRANSPARENT 0 + parameter \WIDTH 25 + connect \ADDR \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage_2$ls180.v:10521$3039_DATA + connect \EN 1'x + end + attribute \src "ls180.v:10528.68-10528.77" + cell $memrd $memrd$\storage_2$ls180.v:10528$3041 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_2" + parameter \TRANSPARENT 0 + parameter \WIDTH 25 + connect \ADDR \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage_2$ls180.v:10528$3041_DATA + connect \EN 1'x + end + attribute \src "ls180.v:10535.14-10535.23" + cell $memrd $memrd$\storage_3$ls180.v:10535$3046 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_3" + parameter \TRANSPARENT 0 + parameter \WIDTH 25 + connect \ADDR \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage_3$ls180.v:10535$3046_DATA + connect \EN 1'x + end + attribute \src "ls180.v:10542.68-10542.77" + cell $memrd $memrd$\storage_3$ls180.v:10542$3048 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_3" + parameter \TRANSPARENT 0 + parameter \WIDTH 25 + connect \ADDR \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage_3$ls180.v:10542$3048_DATA + connect \EN 1'x + end + attribute \src "ls180.v:10550.14-10550.23" + cell $memrd $memrd$\storage_4$ls180.v:10550$3053 + parameter \ABITS 4 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_4" + parameter \TRANSPARENT 0 + parameter \WIDTH 10 + connect \ADDR \main_uart_tx_fifo_wrport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage_4$ls180.v:10550$3053_DATA + connect \EN 1'x + end + attribute \src "ls180.v:10555.15-10555.24" + cell $memrd $memrd$\storage_4$ls180.v:10555$3055 + parameter \ABITS 4 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_4" + parameter \TRANSPARENT 0 + parameter \WIDTH 10 + connect \ADDR \main_uart_tx_fifo_rdport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage_4$ls180.v:10555$3055_DATA + connect \EN 1'x + end + attribute \src "ls180.v:10567.14-10567.23" + cell $memrd $memrd$\storage_5$ls180.v:10567$3060 + parameter \ABITS 4 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_5" + parameter \TRANSPARENT 0 + parameter \WIDTH 10 + connect \ADDR \main_uart_rx_fifo_wrport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage_5$ls180.v:10567$3060_DATA + connect \EN 1'x + end + attribute \src "ls180.v:10572.15-10572.24" + cell $memrd $memrd$\storage_5$ls180.v:10572$3062 + parameter \ABITS 4 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_5" + parameter \TRANSPARENT 0 + parameter \WIDTH 10 + connect \ADDR \main_uart_rx_fifo_rdport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage_5$ls180.v:10572$3062_DATA + connect \EN 1'x + end + attribute \src "ls180.v:10583.14-10583.23" + cell $memrd $memrd$\storage_6$ls180.v:10583$3067 + parameter \ABITS 5 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_6" + parameter \TRANSPARENT 0 + parameter \WIDTH 10 + connect \ADDR \main_sdblock2mem_fifo_wrport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage_6$ls180.v:10583$3067_DATA + connect \EN 1'x + end + attribute \src "ls180.v:10590.45-10590.54" + cell $memrd $memrd$\storage_6$ls180.v:10590$3069 + parameter \ABITS 5 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_6" + parameter \TRANSPARENT 0 + parameter \WIDTH 10 + connect \ADDR \main_sdblock2mem_fifo_rdport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage_6$ls180.v:10590$3069_DATA + connect \EN 1'x + end + attribute \src "ls180.v:10597.14-10597.23" + cell $memrd $memrd$\storage_7$ls180.v:10597$3074 + parameter \ABITS 5 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_7" + parameter \TRANSPARENT 0 + parameter \WIDTH 10 + connect \ADDR \main_sdmem2block_fifo_wrport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage_7$ls180.v:10597$3074_DATA + connect \EN 1'x + end + attribute \src "ls180.v:10604.45-10604.54" + cell $memrd $memrd$\storage_7$ls180.v:10604$3076 + parameter \ABITS 5 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_7" + parameter \TRANSPARENT 0 + parameter \WIDTH 10 + connect \ADDR \main_sdmem2block_fifo_rdport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage_7$ls180.v:10604$3076_DATA + connect \EN 1'x + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem$ls180.v:0$3078 + parameter \ABITS 6 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem" + parameter \PRIORITY 3078 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem$ls180.v:10352$1_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem$ls180.v:10352$1_DATA + connect \EN $memwr$\mem$ls180.v:10352$1_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem$ls180.v:0$3079 + parameter \ABITS 6 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem" + parameter \PRIORITY 3079 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem$ls180.v:10354$2_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem$ls180.v:10354$2_DATA + connect \EN $memwr$\mem$ls180.v:10354$2_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem$ls180.v:0$3080 + parameter \ABITS 6 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem" + parameter \PRIORITY 3080 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem$ls180.v:10356$3_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem$ls180.v:10356$3_DATA + connect \EN $memwr$\mem$ls180.v:10356$3_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem$ls180.v:0$3081 + parameter \ABITS 6 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem" + parameter \PRIORITY 3081 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem$ls180.v:10358$4_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem$ls180.v:10358$4_DATA + connect \EN $memwr$\mem$ls180.v:10358$4_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem$ls180.v:0$3082 + parameter \ABITS 6 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem" + parameter \PRIORITY 3082 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem$ls180.v:10360$5_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem$ls180.v:10360$5_DATA + connect \EN $memwr$\mem$ls180.v:10360$5_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem$ls180.v:0$3083 + parameter \ABITS 6 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem" + parameter \PRIORITY 3083 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem$ls180.v:10362$6_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem$ls180.v:10362$6_DATA + connect \EN $memwr$\mem$ls180.v:10362$6_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem$ls180.v:0$3084 + parameter \ABITS 6 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem" + parameter \PRIORITY 3084 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem$ls180.v:10364$7_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem$ls180.v:10364$7_DATA + connect \EN $memwr$\mem$ls180.v:10364$7_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem$ls180.v:0$3085 + parameter \ABITS 6 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem" + parameter \PRIORITY 3085 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem$ls180.v:10366$8_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem$ls180.v:10366$8_DATA + connect \EN $memwr$\mem$ls180.v:10366$8_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem_1$ls180.v:0$3086 + parameter \ABITS 6 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem_1" + parameter \PRIORITY 3086 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_1$ls180.v:10380$9_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem_1$ls180.v:10380$9_DATA + connect \EN $memwr$\mem_1$ls180.v:10380$9_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem_1$ls180.v:0$3087 + parameter \ABITS 6 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem_1" + parameter \PRIORITY 3087 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_1$ls180.v:10382$10_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem_1$ls180.v:10382$10_DATA + connect \EN $memwr$\mem_1$ls180.v:10382$10_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem_1$ls180.v:0$3088 + parameter \ABITS 6 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem_1" + parameter \PRIORITY 3088 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_1$ls180.v:10384$11_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem_1$ls180.v:10384$11_DATA + connect \EN $memwr$\mem_1$ls180.v:10384$11_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem_1$ls180.v:0$3089 + parameter \ABITS 6 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem_1" + parameter \PRIORITY 3089 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_1$ls180.v:10386$12_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem_1$ls180.v:10386$12_DATA + connect \EN $memwr$\mem_1$ls180.v:10386$12_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem_1$ls180.v:0$3090 + parameter \ABITS 6 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem_1" + parameter \PRIORITY 3090 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_1$ls180.v:10388$13_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem_1$ls180.v:10388$13_DATA + connect \EN $memwr$\mem_1$ls180.v:10388$13_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem_1$ls180.v:0$3091 + parameter \ABITS 6 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem_1" + parameter \PRIORITY 3091 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_1$ls180.v:10390$14_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem_1$ls180.v:10390$14_DATA + connect \EN $memwr$\mem_1$ls180.v:10390$14_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem_1$ls180.v:0$3092 + parameter \ABITS 6 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem_1" + parameter \PRIORITY 3092 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_1$ls180.v:10392$15_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem_1$ls180.v:10392$15_DATA + connect \EN $memwr$\mem_1$ls180.v:10392$15_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem_1$ls180.v:0$3093 + parameter \ABITS 6 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem_1" + parameter \PRIORITY 3093 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_1$ls180.v:10394$16_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem_1$ls180.v:10394$16_DATA + connect \EN $memwr$\mem_1$ls180.v:10394$16_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem_2$ls180.v:0$3094 + parameter \ABITS 6 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem_2" + parameter \PRIORITY 3094 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_2$ls180.v:10408$17_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem_2$ls180.v:10408$17_DATA + connect \EN $memwr$\mem_2$ls180.v:10408$17_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem_2$ls180.v:0$3095 + parameter \ABITS 6 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem_2" + parameter \PRIORITY 3095 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_2$ls180.v:10410$18_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem_2$ls180.v:10410$18_DATA + connect \EN $memwr$\mem_2$ls180.v:10410$18_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem_2$ls180.v:0$3096 + parameter \ABITS 6 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem_2" + parameter \PRIORITY 3096 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_2$ls180.v:10412$19_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem_2$ls180.v:10412$19_DATA + connect \EN $memwr$\mem_2$ls180.v:10412$19_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem_2$ls180.v:0$3097 + parameter \ABITS 6 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem_2" + parameter \PRIORITY 3097 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_2$ls180.v:10414$20_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem_2$ls180.v:10414$20_DATA + connect \EN $memwr$\mem_2$ls180.v:10414$20_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem_2$ls180.v:0$3098 + parameter \ABITS 6 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem_2" + parameter \PRIORITY 3098 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_2$ls180.v:10416$21_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem_2$ls180.v:10416$21_DATA + connect \EN $memwr$\mem_2$ls180.v:10416$21_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem_2$ls180.v:0$3099 + parameter \ABITS 6 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem_2" + parameter \PRIORITY 3099 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_2$ls180.v:10418$22_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem_2$ls180.v:10418$22_DATA + connect \EN $memwr$\mem_2$ls180.v:10418$22_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem_2$ls180.v:0$3100 + parameter \ABITS 6 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem_2" + parameter \PRIORITY 3100 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_2$ls180.v:10420$23_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem_2$ls180.v:10420$23_DATA + connect \EN $memwr$\mem_2$ls180.v:10420$23_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem_2$ls180.v:0$3101 + parameter \ABITS 6 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem_2" + parameter \PRIORITY 3101 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_2$ls180.v:10422$24_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem_2$ls180.v:10422$24_DATA + connect \EN $memwr$\mem_2$ls180.v:10422$24_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem_3$ls180.v:0$3102 + parameter \ABITS 6 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem_3" + parameter \PRIORITY 3102 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_3$ls180.v:10436$25_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem_3$ls180.v:10436$25_DATA + connect \EN $memwr$\mem_3$ls180.v:10436$25_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem_3$ls180.v:0$3103 + parameter \ABITS 6 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem_3" + parameter \PRIORITY 3103 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_3$ls180.v:10438$26_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem_3$ls180.v:10438$26_DATA + connect \EN $memwr$\mem_3$ls180.v:10438$26_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem_3$ls180.v:0$3104 + parameter \ABITS 6 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem_3" + parameter \PRIORITY 3104 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_3$ls180.v:10440$27_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem_3$ls180.v:10440$27_DATA + connect \EN $memwr$\mem_3$ls180.v:10440$27_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem_3$ls180.v:0$3105 + parameter \ABITS 6 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem_3" + parameter \PRIORITY 3105 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_3$ls180.v:10442$28_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem_3$ls180.v:10442$28_DATA + connect \EN $memwr$\mem_3$ls180.v:10442$28_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem_3$ls180.v:0$3106 + parameter \ABITS 6 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem_3" + parameter \PRIORITY 3106 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_3$ls180.v:10444$29_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem_3$ls180.v:10444$29_DATA + connect \EN $memwr$\mem_3$ls180.v:10444$29_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem_3$ls180.v:0$3107 + parameter \ABITS 6 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem_3" + parameter \PRIORITY 3107 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_3$ls180.v:10446$30_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem_3$ls180.v:10446$30_DATA + connect \EN $memwr$\mem_3$ls180.v:10446$30_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem_3$ls180.v:0$3108 + parameter \ABITS 6 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem_3" + parameter \PRIORITY 3108 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_3$ls180.v:10448$31_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem_3$ls180.v:10448$31_DATA + connect \EN $memwr$\mem_3$ls180.v:10448$31_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem_3$ls180.v:0$3109 + parameter \ABITS 6 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem_3" + parameter \PRIORITY 3109 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_3$ls180.v:10450$32_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem_3$ls180.v:10450$32_DATA + connect \EN $memwr$\mem_3$ls180.v:10450$32_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem_4$ls180.v:0$3110 + parameter \ABITS 6 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem_4" + parameter \PRIORITY 3110 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_4$ls180.v:10464$33_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem_4$ls180.v:10464$33_DATA + connect \EN $memwr$\mem_4$ls180.v:10464$33_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem_4$ls180.v:0$3111 + parameter \ABITS 6 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem_4" + parameter \PRIORITY 3111 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_4$ls180.v:10466$34_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem_4$ls180.v:10466$34_DATA + connect \EN $memwr$\mem_4$ls180.v:10466$34_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem_4$ls180.v:0$3112 + parameter \ABITS 6 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem_4" + parameter \PRIORITY 3112 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_4$ls180.v:10468$35_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem_4$ls180.v:10468$35_DATA + connect \EN $memwr$\mem_4$ls180.v:10468$35_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem_4$ls180.v:0$3113 + parameter \ABITS 6 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem_4" + parameter \PRIORITY 3113 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_4$ls180.v:10470$36_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem_4$ls180.v:10470$36_DATA + connect \EN $memwr$\mem_4$ls180.v:10470$36_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem_4$ls180.v:0$3114 + parameter \ABITS 6 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem_4" + parameter \PRIORITY 3114 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_4$ls180.v:10472$37_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem_4$ls180.v:10472$37_DATA + connect \EN $memwr$\mem_4$ls180.v:10472$37_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem_4$ls180.v:0$3115 + parameter \ABITS 6 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem_4" + parameter \PRIORITY 3115 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_4$ls180.v:10474$38_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem_4$ls180.v:10474$38_DATA + connect \EN $memwr$\mem_4$ls180.v:10474$38_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem_4$ls180.v:0$3116 + parameter \ABITS 6 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem_4" + parameter \PRIORITY 3116 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_4$ls180.v:10476$39_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem_4$ls180.v:10476$39_DATA + connect \EN $memwr$\mem_4$ls180.v:10476$39_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\mem_4$ls180.v:0$3117 + parameter \ABITS 6 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem_4" + parameter \PRIORITY 3117 + parameter \WIDTH 64 + connect \ADDR $memwr$\mem_4$ls180.v:10478$40_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem_4$ls180.v:10478$40_DATA + connect \EN $memwr$\mem_4$ls180.v:10478$40_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\storage$ls180.v:0$3118 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage" + parameter \PRIORITY 3118 + parameter \WIDTH 25 + connect \ADDR $memwr$\storage$ls180.v:10492$41_ADDR + connect \CLK 1'x + connect \DATA $memwr$\storage$ls180.v:10492$41_DATA + connect \EN $memwr$\storage$ls180.v:10492$41_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\storage_1$ls180.v:0$3119 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_1" + parameter \PRIORITY 3119 + parameter \WIDTH 25 + connect \ADDR $memwr$\storage_1$ls180.v:10506$42_ADDR + connect \CLK 1'x + connect \DATA $memwr$\storage_1$ls180.v:10506$42_DATA + connect \EN $memwr$\storage_1$ls180.v:10506$42_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\storage_2$ls180.v:0$3120 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_2" + parameter \PRIORITY 3120 + parameter \WIDTH 25 + connect \ADDR $memwr$\storage_2$ls180.v:10520$43_ADDR + connect \CLK 1'x + connect \DATA $memwr$\storage_2$ls180.v:10520$43_DATA + connect \EN $memwr$\storage_2$ls180.v:10520$43_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\storage_3$ls180.v:0$3121 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_3" + parameter \PRIORITY 3121 + parameter \WIDTH 25 + connect \ADDR $memwr$\storage_3$ls180.v:10534$44_ADDR + connect \CLK 1'x + connect \DATA $memwr$\storage_3$ls180.v:10534$44_DATA + connect \EN $memwr$\storage_3$ls180.v:10534$44_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\storage_4$ls180.v:0$3122 + parameter \ABITS 4 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_4" + parameter \PRIORITY 3122 + parameter \WIDTH 10 + connect \ADDR $memwr$\storage_4$ls180.v:10549$45_ADDR + connect \CLK 1'x + connect \DATA $memwr$\storage_4$ls180.v:10549$45_DATA + connect \EN $memwr$\storage_4$ls180.v:10549$45_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\storage_5$ls180.v:0$3123 + parameter \ABITS 4 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_5" + parameter \PRIORITY 3123 + parameter \WIDTH 10 + connect \ADDR $memwr$\storage_5$ls180.v:10566$46_ADDR + connect \CLK 1'x + connect \DATA $memwr$\storage_5$ls180.v:10566$46_DATA + connect \EN $memwr$\storage_5$ls180.v:10566$46_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\storage_6$ls180.v:0$3124 + parameter \ABITS 5 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_6" + parameter \PRIORITY 3124 + parameter \WIDTH 10 + connect \ADDR $memwr$\storage_6$ls180.v:10582$47_ADDR + connect \CLK 1'x + connect \DATA $memwr$\storage_6$ls180.v:10582$47_DATA + connect \EN $memwr$\storage_6$ls180.v:10582$47_EN + end + attribute \src "ls180.v:0.0-0.0" + cell $memwr $memwr$\storage_7$ls180.v:0$3125 + parameter \ABITS 5 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_7" + parameter \PRIORITY 3125 + parameter \WIDTH 10 + connect \ADDR $memwr$\storage_7$ls180.v:10596$48_ADDR + connect \CLK 1'x + connect \DATA $memwr$\storage_7$ls180.v:10596$48_DATA + connect \EN $memwr$\storage_7$ls180.v:10596$48_EN + end + attribute \src "ls180.v:3086.41-3086.71" + cell $ne $ne$ls180.v:3086$108 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_value + connect \B 1'0 + connect \Y $ne$ls180.v:3086$108_Y + end + attribute \src "ls180.v:3303.70-3303.104" + cell $ne $ne$ls180.v:3303$222 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_sequencer_count + connect \B 1'0 + connect \Y $ne$ls180.v:3303$222_Y + end + attribute \src "ls180.v:3364.8-3364.142" + cell $ne $ne$ls180.v:3364$241 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr [21:9] + connect \B \main_sdram_bankmachine0_cmd_buffer_source_payload_addr [21:9] + connect \Y $ne$ls180.v:3364$241_Y + end + attribute \src "ls180.v:3396.75-3396.133" + cell $ne $ne$ls180.v:3396$248 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_level + connect \B 4'1000 + connect \Y $ne$ls180.v:3396$248_Y + end + attribute \src "ls180.v:3397.75-3397.133" + cell $ne $ne$ls180.v:3397$249 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_level + connect \B 1'0 + connect \Y $ne$ls180.v:3397$249_Y + end + attribute \src "ls180.v:3521.8-3521.142" + cell $ne $ne$ls180.v:3521$271 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr [21:9] + connect \B \main_sdram_bankmachine1_cmd_buffer_source_payload_addr [21:9] + connect \Y $ne$ls180.v:3521$271_Y + end + attribute \src "ls180.v:3553.75-3553.133" + cell $ne $ne$ls180.v:3553$278 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_level + connect \B 4'1000 + connect \Y $ne$ls180.v:3553$278_Y + end + attribute \src "ls180.v:3554.75-3554.133" + cell $ne $ne$ls180.v:3554$279 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_level + connect \B 1'0 + connect \Y $ne$ls180.v:3554$279_Y + end + attribute \src "ls180.v:3678.8-3678.142" + cell $ne $ne$ls180.v:3678$301 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr [21:9] + connect \B \main_sdram_bankmachine2_cmd_buffer_source_payload_addr [21:9] + connect \Y $ne$ls180.v:3678$301_Y + end + attribute \src "ls180.v:3710.75-3710.133" + cell $ne $ne$ls180.v:3710$308 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_level + connect \B 4'1000 + connect \Y $ne$ls180.v:3710$308_Y + end + attribute \src "ls180.v:3711.75-3711.133" + cell $ne $ne$ls180.v:3711$309 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_level + connect \B 1'0 + connect \Y $ne$ls180.v:3711$309_Y + end + attribute \src "ls180.v:3835.8-3835.142" + cell $ne $ne$ls180.v:3835$331 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr [21:9] + connect \B \main_sdram_bankmachine3_cmd_buffer_source_payload_addr [21:9] + connect \Y $ne$ls180.v:3835$331_Y + end + attribute \src "ls180.v:3867.75-3867.133" + cell $ne $ne$ls180.v:3867$338 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_level + connect \B 4'1000 + connect \Y $ne$ls180.v:3867$338_Y + end + attribute \src "ls180.v:3868.75-3868.133" + cell $ne $ne$ls180.v:3868$339 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_level + connect \B 1'0 + connect \Y $ne$ls180.v:3868$339_Y + end + attribute \src "ls180.v:4360.47-4360.80" + cell $ne $ne$ls180.v:4360$737 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \main_uart_tx_fifo_level0 + connect \B 5'10000 + connect \Y $ne$ls180.v:4360$737_Y + end + attribute \src "ls180.v:4361.47-4361.79" + cell $ne $ne$ls180.v:4361$738 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_tx_fifo_level0 + connect \B 1'0 + connect \Y $ne$ls180.v:4361$738_Y + end + attribute \src "ls180.v:4390.47-4390.80" + cell $ne $ne$ls180.v:4390$748 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \main_uart_rx_fifo_level0 + connect \B 5'10000 + connect \Y $ne$ls180.v:4390$748_Y + end + attribute \src "ls180.v:4391.47-4391.79" + cell $ne $ne$ls180.v:4391$749 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_rx_fifo_level0 + connect \B 1'0 + connect \Y $ne$ls180.v:4391$749_Y + end + attribute \src "ls180.v:4871.32-4871.89" + cell $ne $ne$ls180.v:4871$831 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_crcr_source_source_payload_data0 + connect \B 3'101 + connect \Y $ne$ls180.v:4871$831_Y + end + attribute \src "ls180.v:5518.10-5518.56" + cell $ne $ne$ls180.v:5518$1128 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_source_payload_status + connect \B 2'10 + connect \Y $ne$ls180.v:5518$1128_Y + end + attribute \src "ls180.v:5623.51-5623.87" + cell $ne $ne$ls180.v:5623$1142 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_fifo_level + connect \B 6'100000 + connect \Y $ne$ls180.v:5623$1142_Y + end + attribute \src "ls180.v:5624.51-5624.86" + cell $ne $ne$ls180.v:5624$1143 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_fifo_level + connect \B 1'0 + connect \Y $ne$ls180.v:5624$1143_Y + end + attribute \src "ls180.v:5843.51-5843.87" + cell $ne $ne$ls180.v:5843$1173 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \main_sdmem2block_fifo_level + connect \B 6'100000 + connect \Y $ne$ls180.v:5843$1173_Y + end + attribute \src "ls180.v:5844.51-5844.86" + cell $ne $ne$ls180.v:5844$1174 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdmem2block_fifo_level + connect \B 1'0 + connect \Y $ne$ls180.v:5844$1174_Y + end + attribute \src "ls180.v:5875.79-5875.119" + cell $ne $ne$ls180.v:5875$1177 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_libresocsim_wishbone_sel + connect \B 1'0 + connect \Y $ne$ls180.v:5875$1177_Y + end + attribute \src "ls180.v:7760.7-7760.52" + cell $ne $ne$ls180.v:7760$2601 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_bus_errors + connect \B 32'11111111111111111111111111111111 + connect \Y $ne$ls180.v:7760$2601_Y + end + attribute \src "ls180.v:7826.9-7826.43" + cell $ne $ne$ls180.v:7826$2627 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_sequencer_count + connect \B 1'0 + connect \Y $ne$ls180.v:7826$2627_Y + end + attribute \src "ls180.v:7862.8-7862.44" + cell $ne $ne$ls180.v:7862$2634 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_sequencer_counter + connect \B 1'0 + connect \Y $ne$ls180.v:7862$2634_Y + end + attribute \src "ls180.v:8800.9-8800.47" + cell $ne $ne$ls180.v:8800$2849 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_cnt + connect \B 4'1010 + connect \Y $ne$ls180.v:8800$2849_Y + end + attribute \src "ls180.v:2890.33-2890.73" + cell $not $not$ls180.v:2890$50 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface0_converted_interface_cyc + connect \Y $not$ls180.v:2890$50_Y + end + attribute \src "ls180.v:2929.48-2929.69" + cell $not $not$ls180.v:2929$55 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_converter0_skip + connect \Y $not$ls180.v:2929$55_Y + end + attribute \src "ls180.v:2930.48-2930.69" + cell $not $not$ls180.v:2930$56 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_converter0_skip + connect \Y $not$ls180.v:2930$56_Y + end + attribute \src "ls180.v:2950.33-2950.73" + cell $not $not$ls180.v:2950$61 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface1_converted_interface_cyc + connect \Y $not$ls180.v:2950$61_Y + end + attribute \src "ls180.v:2989.48-2989.69" + cell $not $not$ls180.v:2989$66 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_converter1_skip + connect \Y $not$ls180.v:2989$66_Y + end + attribute \src "ls180.v:2990.48-2990.69" + cell $not $not$ls180.v:2990$67 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_converter1_skip + connect \Y $not$ls180.v:2990$67_Y + end + attribute \src "ls180.v:3010.36-3010.79" + cell $not $not$ls180.v:3010$72 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_socbushandler_converted_interface_cyc + connect \Y $not$ls180.v:3010$72_Y + end + attribute \src "ls180.v:3049.27-3049.51" + cell $not $not$ls180.v:3049$77 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_socbushandler_skip + connect \Y $not$ls180.v:3049$77_Y + end + attribute \src "ls180.v:3050.27-3050.51" + cell $not $not$ls180.v:3050$78 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_socbushandler_skip + connect \Y $not$ls180.v:3050$78_Y + end + attribute \src "ls180.v:3252.34-3252.64" + cell $not $not$ls180.v:3252$214 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_command_storage [0] + connect \Y $not$ls180.v:3252$214_Y + end + attribute \src "ls180.v:3253.31-3253.61" + cell $not $not$ls180.v:3253$215 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_command_storage [1] + connect \Y $not$ls180.v:3253$215_Y + end + attribute \src "ls180.v:3254.32-3254.62" + cell $not $not$ls180.v:3254$216 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_command_storage [2] + connect \Y $not$ls180.v:3254$216_Y + end + attribute \src "ls180.v:3255.32-3255.62" + cell $not $not$ls180.v:3255$217 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_command_storage [3] + connect \Y $not$ls180.v:3255$217_Y + end + attribute \src "ls180.v:3297.33-3297.56" + cell $not $not$ls180.v:3297$220 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_timer_done0 + connect \Y $not$ls180.v:3297$220_Y + end + attribute \src "ls180.v:3398.58-3398.106" + cell $not $not$ls180.v:3398$250 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_buffer_source_valid + connect \Y $not$ls180.v:3398$250_Y + end + attribute \src "ls180.v:3452.9-3452.45" + cell $not $not$ls180.v:3452$255 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_refresh_req + connect \Y $not$ls180.v:3452$255_Y + end + attribute \src "ls180.v:3555.58-3555.106" + cell $not $not$ls180.v:3555$280 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_buffer_source_valid + connect \Y $not$ls180.v:3555$280_Y + end + attribute \src "ls180.v:3609.9-3609.45" + cell $not $not$ls180.v:3609$285 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_refresh_req + connect \Y $not$ls180.v:3609$285_Y + end + attribute \src "ls180.v:3712.58-3712.106" + cell $not $not$ls180.v:3712$310 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_buffer_source_valid + connect \Y $not$ls180.v:3712$310_Y + end + attribute \src "ls180.v:3766.9-3766.45" + cell $not $not$ls180.v:3766$315 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_refresh_req + connect \Y $not$ls180.v:3766$315_Y + end + attribute \src "ls180.v:3869.58-3869.106" + cell $not $not$ls180.v:3869$340 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_buffer_source_valid + connect \Y $not$ls180.v:3869$340_Y + end + attribute \src "ls180.v:3923.9-3923.45" + cell $not $not$ls180.v:3923$345 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_refresh_req + connect \Y $not$ls180.v:3923$345_Y + end + attribute \src "ls180.v:3965.149-3965.187" + cell $not $not$ls180.v:3965$348 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_payload_cas + connect \Y $not$ls180.v:3965$348_Y + end + attribute \src "ls180.v:3965.193-3965.230" + cell $not $not$ls180.v:3965$350 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_payload_we + connect \Y $not$ls180.v:3965$350_Y + end + attribute \src "ls180.v:3966.149-3966.187" + cell $not $not$ls180.v:3966$354 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_payload_cas + connect \Y $not$ls180.v:3966$354_Y + end + attribute \src "ls180.v:3966.193-3966.230" + cell $not $not$ls180.v:3966$356 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_payload_we + connect \Y $not$ls180.v:3966$356_Y + end + attribute \src "ls180.v:3982.43-3982.73" + cell $not $not$ls180.v:3982$384 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \main_sdram_interface_wdata_we + connect \Y $not$ls180.v:3982$384_Y + end + attribute \src "ls180.v:3985.205-3985.245" + cell $not $not$ls180.v:3985$387 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_payload_cas + connect \Y $not$ls180.v:3985$387_Y + end + attribute \src "ls180.v:3985.251-3985.290" + cell $not $not$ls180.v:3985$389 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_payload_we + connect \Y $not$ls180.v:3985$389_Y + end + attribute \src "ls180.v:3985.159-3985.292" + cell $not $not$ls180.v:3985$391 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3985$390_Y + connect \Y $not$ls180.v:3985$391_Y + end + attribute \src "ls180.v:3986.205-3986.245" + cell $not $not$ls180.v:3986$400 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_payload_cas + connect \Y $not$ls180.v:3986$400_Y + end + attribute \src "ls180.v:3986.251-3986.290" + cell $not $not$ls180.v:3986$402 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_payload_we + connect \Y $not$ls180.v:3986$402_Y + end + attribute \src "ls180.v:3986.159-3986.292" + cell $not $not$ls180.v:3986$404 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3986$403_Y + connect \Y $not$ls180.v:3986$404_Y + end + attribute \src "ls180.v:3987.205-3987.245" + cell $not $not$ls180.v:3987$413 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_payload_cas + connect \Y $not$ls180.v:3987$413_Y + end + attribute \src "ls180.v:3987.251-3987.290" + cell $not $not$ls180.v:3987$415 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_payload_we + connect \Y $not$ls180.v:3987$415_Y + end + attribute \src "ls180.v:3987.159-3987.292" + cell $not $not$ls180.v:3987$417 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3987$416_Y + connect \Y $not$ls180.v:3987$417_Y + end + attribute \src "ls180.v:3988.205-3988.245" + cell $not $not$ls180.v:3988$426 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_payload_cas + connect \Y $not$ls180.v:3988$426_Y + end + attribute \src "ls180.v:3988.251-3988.290" + cell $not $not$ls180.v:3988$428 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_payload_we + connect \Y $not$ls180.v:3988$428_Y + end + attribute \src "ls180.v:3988.159-3988.292" + cell $not $not$ls180.v:3988$430 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3988$429_Y + connect \Y $not$ls180.v:3988$430_Y + end + attribute \src "ls180.v:4015.71-4015.103" + cell $not $not$ls180.v:4015$441 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_cmd_cmd_valid + connect \Y $not$ls180.v:4015$441_Y + end + attribute \src "ls180.v:4018.205-4018.245" + cell $not $not$ls180.v:4018$445 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_payload_cas + connect \Y $not$ls180.v:4018$445_Y + end + attribute \src "ls180.v:4018.251-4018.290" + cell $not $not$ls180.v:4018$447 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_payload_we + connect \Y $not$ls180.v:4018$447_Y + end + attribute \src "ls180.v:4018.159-4018.292" + cell $not $not$ls180.v:4018$449 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4018$448_Y + connect \Y $not$ls180.v:4018$449_Y + end + attribute \src "ls180.v:4019.205-4019.245" + cell $not $not$ls180.v:4019$458 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_payload_cas + connect \Y $not$ls180.v:4019$458_Y + end + attribute \src "ls180.v:4019.251-4019.290" + cell $not $not$ls180.v:4019$460 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_payload_we + connect \Y $not$ls180.v:4019$460_Y + end + attribute \src "ls180.v:4019.159-4019.292" + cell $not $not$ls180.v:4019$462 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4019$461_Y + connect \Y $not$ls180.v:4019$462_Y + end + attribute \src "ls180.v:4020.205-4020.245" + cell $not $not$ls180.v:4020$471 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_payload_cas + connect \Y $not$ls180.v:4020$471_Y + end + attribute \src "ls180.v:4020.251-4020.290" + cell $not $not$ls180.v:4020$473 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_payload_we + connect \Y $not$ls180.v:4020$473_Y + end + attribute \src "ls180.v:4020.159-4020.292" + cell $not $not$ls180.v:4020$475 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4020$474_Y + connect \Y $not$ls180.v:4020$475_Y + end + attribute \src "ls180.v:4021.205-4021.245" + cell $not $not$ls180.v:4021$484 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_payload_cas + connect \Y $not$ls180.v:4021$484_Y + end + attribute \src "ls180.v:4021.251-4021.290" + cell $not $not$ls180.v:4021$486 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_payload_we + connect \Y $not$ls180.v:4021$486_Y + end + attribute \src "ls180.v:4021.159-4021.292" + cell $not $not$ls180.v:4021$488 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4021$487_Y + connect \Y $not$ls180.v:4021$488_Y + end + attribute \src "ls180.v:4084.71-4084.103" + cell $not $not$ls180.v:4084$527 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \Y $not$ls180.v:4084$527_Y + end + attribute \src "ls180.v:4105.112-4105.150" + cell $not $not$ls180.v:4105$530 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_payload_cas + connect \Y $not$ls180.v:4105$530_Y + end + attribute \src "ls180.v:4105.156-4105.193" + cell $not $not$ls180.v:4105$532 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_payload_we + connect \Y $not$ls180.v:4105$532_Y + end + attribute \src "ls180.v:4105.68-4105.195" + cell $not $not$ls180.v:4105$534 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4105$533_Y + connect \Y $not$ls180.v:4105$534_Y + end + attribute \src "ls180.v:4113.11-4113.38" + cell $not $not$ls180.v:4113$537 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_write_available + connect \Y $not$ls180.v:4113$537_Y + end + attribute \src "ls180.v:4143.112-4143.150" + cell $not $not$ls180.v:4143$539 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_payload_cas + connect \Y $not$ls180.v:4143$539_Y + end + attribute \src "ls180.v:4143.156-4143.193" + cell $not $not$ls180.v:4143$541 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_payload_we + connect \Y $not$ls180.v:4143$541_Y + end + attribute \src "ls180.v:4143.68-4143.195" + cell $not $not$ls180.v:4143$543 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4143$542_Y + connect \Y $not$ls180.v:4143$543_Y + end + attribute \src "ls180.v:4151.11-4151.37" + cell $not $not$ls180.v:4151$546 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_read_available + connect \Y $not$ls180.v:4151$546_Y + end + attribute \src "ls180.v:4161.87-4161.331" + cell $not $not$ls180.v:4161$558 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4161$557_Y + connect \Y $not$ls180.v:4161$558_Y + end + attribute \src "ls180.v:4162.35-4162.68" + cell $not $not$ls180.v:4162$561 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank0_valid + connect \Y $not$ls180.v:4162$561_Y + end + attribute \src "ls180.v:4162.73-4162.105" + cell $not $not$ls180.v:4162$562 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank0_lock + connect \Y $not$ls180.v:4162$562_Y + end + attribute \src "ls180.v:4166.87-4166.331" + cell $not $not$ls180.v:4166$574 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4166$573_Y + connect \Y $not$ls180.v:4166$574_Y + end + attribute \src "ls180.v:4167.35-4167.68" + cell $not $not$ls180.v:4167$577 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank1_valid + connect \Y $not$ls180.v:4167$577_Y + end + attribute \src "ls180.v:4167.73-4167.105" + cell $not $not$ls180.v:4167$578 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank1_lock + connect \Y $not$ls180.v:4167$578_Y + end + attribute \src "ls180.v:4171.87-4171.331" + cell $not $not$ls180.v:4171$590 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4171$589_Y + connect \Y $not$ls180.v:4171$590_Y + end + attribute \src "ls180.v:4172.35-4172.68" + cell $not $not$ls180.v:4172$593 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank2_valid + connect \Y $not$ls180.v:4172$593_Y + end + attribute \src "ls180.v:4172.73-4172.105" + cell $not $not$ls180.v:4172$594 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank2_lock + connect \Y $not$ls180.v:4172$594_Y + end + attribute \src "ls180.v:4176.87-4176.331" + cell $not $not$ls180.v:4176$606 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4176$605_Y + connect \Y $not$ls180.v:4176$606_Y + end + attribute \src "ls180.v:4177.35-4177.68" + cell $not $not$ls180.v:4177$609 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank3_valid + connect \Y $not$ls180.v:4177$609_Y + end + attribute \src "ls180.v:4177.73-4177.105" + cell $not $not$ls180.v:4177$610 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank3_lock + connect \Y $not$ls180.v:4177$610_Y + end + attribute \src "ls180.v:4181.128-4181.372" + cell $not $not$ls180.v:4181$623 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4181$622_Y + connect \Y $not$ls180.v:4181$623_Y + end + attribute \src "ls180.v:4181.502-4181.746" + cell $not $not$ls180.v:4181$639 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4181$638_Y + connect \Y $not$ls180.v:4181$639_Y + end + attribute \src "ls180.v:4181.876-4181.1120" + cell $not $not$ls180.v:4181$655 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4181$654_Y + connect \Y $not$ls180.v:4181$655_Y + end + attribute \src "ls180.v:4181.1250-4181.1494" + cell $not $not$ls180.v:4181$671 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4181$670_Y + connect \Y $not$ls180.v:4181$671_Y + end + attribute \src "ls180.v:4203.32-4203.50" + cell $not $not$ls180.v:4203$677 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_wb_sdram_cyc + connect \Y $not$ls180.v:4203$677_Y + end + attribute \src "ls180.v:4242.30-4242.50" + cell $not $not$ls180.v:4242$682 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_converter_skip + connect \Y $not$ls180.v:4242$682_Y + end + attribute \src "ls180.v:4243.30-4243.50" + cell $not $not$ls180.v:4243$683 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_converter_skip + connect \Y $not$ls180.v:4243$683_Y + end + attribute \src "ls180.v:4268.27-4268.48" + cell $not $not$ls180.v:4268$689 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_litedram_wb_cyc + connect \Y $not$ls180.v:4268$689_Y + end + attribute \src "ls180.v:4269.30-4269.50" + cell $not $not$ls180.v:4269$690 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_litedram_wb_we + connect \Y $not$ls180.v:4269$690_Y + end + attribute \src "ls180.v:4270.80-4270.98" + cell $not $not$ls180.v:4270$692 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_cmd_consumed + connect \Y $not$ls180.v:4270$692_Y + end + attribute \src "ls180.v:4271.107-4271.127" + cell $not $not$ls180.v:4271$696 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_wdata_consumed + connect \Y $not$ls180.v:4271$696_Y + end + attribute \src "ls180.v:4272.78-4272.103" + cell $not $not$ls180.v:4272$699 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_payload_we + connect \Y $not$ls180.v:4272$699_Y + end + attribute \src "ls180.v:4273.91-4273.111" + cell $not $not$ls180.v:4273$702 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_litedram_wb_we + connect \Y $not$ls180.v:4273$702_Y + end + attribute \src "ls180.v:4289.35-4289.64" + cell $not $not$ls180.v:4289$711 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_tx_fifo_sink_ready + connect \Y $not$ls180.v:4289$711_Y + end + attribute \src "ls180.v:4290.36-4290.67" + cell $not $not$ls180.v:4290$712 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_tx_fifo_source_valid + connect \Y $not$ls180.v:4290$712_Y + end + attribute \src "ls180.v:4296.32-4296.61" + cell $not $not$ls180.v:4296$713 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_tx_fifo_sink_ready + connect \Y $not$ls180.v:4296$713_Y + end + attribute \src "ls180.v:4302.36-4302.67" + cell $not $not$ls180.v:4302$714 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_rx_fifo_source_valid + connect \Y $not$ls180.v:4302$714_Y + end + attribute \src "ls180.v:4303.35-4303.64" + cell $not $not$ls180.v:4303$715 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_rx_fifo_sink_ready + connect \Y $not$ls180.v:4303$715_Y + end + attribute \src "ls180.v:4306.32-4306.63" + cell $not $not$ls180.v:4306$718 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_rx_fifo_source_valid + connect \Y $not$ls180.v:4306$718_Y + end + attribute \src "ls180.v:4344.81-4344.108" + cell $not $not$ls180.v:4344$728 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_tx_fifo_readable + connect \Y $not$ls180.v:4344$728_Y + end + attribute \src "ls180.v:4374.81-4374.108" + cell $not $not$ls180.v:4374$739 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_rx_fifo_readable + connect \Y $not$ls180.v:4374$739_Y + end + attribute \src "ls180.v:4585.60-4585.85" + cell $not $not$ls180.v:4585$790 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_clocker_clk_d + connect \Y $not$ls180.v:4585$790_Y + end + attribute \src "ls180.v:4726.54-4726.96" + cell $not $not$ls180.v:4726$804 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_cmdr_converter_strobe_all + connect \Y $not$ls180.v:4726$804_Y + end + attribute \src "ls180.v:4729.48-4729.86" + cell $not $not$ls180.v:4729$807 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_cmdr_buf_source_valid + connect \Y $not$ls180.v:4729$807_Y + end + attribute \src "ls180.v:4853.55-4853.98" + cell $not $not$ls180.v:4853$825 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_crcr_converter_strobe_all + connect \Y $not$ls180.v:4853$825_Y + end + attribute \src "ls180.v:4856.49-4856.88" + cell $not $not$ls180.v:4856$828 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_crcr_buf_source_valid + connect \Y $not$ls180.v:4856$828_Y + end + attribute \src "ls180.v:4906.30-4906.58" + cell $not $not$ls180.v:4906$834 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_sink_valid + connect \Y $not$ls180.v:4906$834_Y + end + attribute \src "ls180.v:4987.56-4987.100" + cell $not $not$ls180.v:4987$840 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_datar_converter_strobe_all + connect \Y $not$ls180.v:4987$840_Y + end + attribute \src "ls180.v:4990.50-4990.90" + cell $not $not$ls180.v:4990$843 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_datar_buf_source_valid + connect \Y $not$ls180.v:4990$843_Y + end + attribute \src "ls180.v:5106.42-5106.74" + cell $not $not$ls180.v:5106$859 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_valid + connect \Y $not$ls180.v:5106$859_Y + end + attribute \src "ls180.v:5630.50-5630.88" + cell $not $not$ls180.v:5630$1144 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_converter_strobe_all + connect \Y $not$ls180.v:5630$1144_Y + end + attribute \src "ls180.v:5642.52-5642.102" + cell $not $not$ls180.v:5642$1147 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_wishbonedmawriter_enable_storage + connect \Y $not$ls180.v:5642$1147_Y + end + attribute \src "ls180.v:5701.38-5701.74" + cell $not $not$ls180.v:5701$1154 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdmem2block_dma_enable_storage + connect \Y $not$ls180.v:5701$1154_Y + end + attribute \src "ls180.v:6027.69-6027.88" + cell $not $not$ls180.v:6027$1239 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_ack + connect \Y $not$ls180.v:6027$1239_Y + end + attribute \src "ls180.v:6044.63-6044.94" + cell $not $not$ls180.v:6044$1284 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_we + connect \Y $not$ls180.v:6044$1284_Y + end + attribute \src "ls180.v:6047.65-6047.96" + cell $not $not$ls180.v:6047$1291 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_we + connect \Y $not$ls180.v:6047$1291_Y + end + attribute \src "ls180.v:6050.65-6050.96" + cell $not $not$ls180.v:6050$1298 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_we + connect \Y $not$ls180.v:6050$1298_Y + end + attribute \src "ls180.v:6053.65-6053.96" + cell $not $not$ls180.v:6053$1305 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_we + connect \Y $not$ls180.v:6053$1305_Y + end + attribute \src "ls180.v:6056.65-6056.96" + cell $not $not$ls180.v:6056$1312 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_we + connect \Y $not$ls180.v:6056$1312_Y + end + attribute \src "ls180.v:6059.68-6059.99" + cell $not $not$ls180.v:6059$1319 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_we + connect \Y $not$ls180.v:6059$1319_Y + end + attribute \src "ls180.v:6062.68-6062.99" + cell $not $not$ls180.v:6062$1326 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_we + connect \Y $not$ls180.v:6062$1326_Y + end + attribute \src "ls180.v:6065.68-6065.99" + cell $not $not$ls180.v:6065$1333 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_we + connect \Y $not$ls180.v:6065$1333_Y + end + attribute \src "ls180.v:6068.68-6068.99" + cell $not $not$ls180.v:6068$1340 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_we + connect \Y $not$ls180.v:6068$1340_Y + end + attribute \src "ls180.v:6082.60-6082.91" + cell $not $not$ls180.v:6082$1348 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_we + connect \Y $not$ls180.v:6082$1348_Y + end + attribute \src "ls180.v:6085.60-6085.91" + cell $not $not$ls180.v:6085$1355 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_we + connect \Y $not$ls180.v:6085$1355_Y + end + attribute \src "ls180.v:6088.60-6088.91" + cell $not $not$ls180.v:6088$1362 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_we + connect \Y $not$ls180.v:6088$1362_Y + end + attribute \src "ls180.v:6091.60-6091.91" + cell $not $not$ls180.v:6091$1369 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_we + connect \Y $not$ls180.v:6091$1369_Y + end + attribute \src "ls180.v:6094.61-6094.92" + cell $not $not$ls180.v:6094$1376 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_we + connect \Y $not$ls180.v:6094$1376_Y + end + attribute \src "ls180.v:6097.61-6097.92" + cell $not $not$ls180.v:6097$1383 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_we + connect \Y $not$ls180.v:6097$1383_Y + end + attribute \src "ls180.v:6108.59-6108.90" + cell $not $not$ls180.v:6108$1391 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface2_bank_bus_we + connect \Y $not$ls180.v:6108$1391_Y + end + attribute \src "ls180.v:6111.58-6111.89" + cell $not $not$ls180.v:6111$1398 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface2_bank_bus_we + connect \Y $not$ls180.v:6111$1398_Y + end + attribute \src "ls180.v:6122.64-6122.95" + cell $not $not$ls180.v:6122$1406 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_we + connect \Y $not$ls180.v:6122$1406_Y + end + attribute \src "ls180.v:6125.63-6125.94" + cell $not $not$ls180.v:6125$1413 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_we + connect \Y $not$ls180.v:6125$1413_Y + end + attribute \src "ls180.v:6128.63-6128.94" + cell $not $not$ls180.v:6128$1420 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_we + connect \Y $not$ls180.v:6128$1420_Y + end + attribute \src "ls180.v:6131.63-6131.94" + cell $not $not$ls180.v:6131$1427 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_we + connect \Y $not$ls180.v:6131$1427_Y + end + attribute \src "ls180.v:6134.63-6134.94" + cell $not $not$ls180.v:6134$1434 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_we + connect \Y $not$ls180.v:6134$1434_Y + end + attribute \src "ls180.v:6137.64-6137.95" + cell $not $not$ls180.v:6137$1441 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_we + connect \Y $not$ls180.v:6137$1441_Y + end + attribute \src "ls180.v:6140.64-6140.95" + cell $not $not$ls180.v:6140$1448 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_we + connect \Y $not$ls180.v:6140$1448_Y + end + attribute \src "ls180.v:6143.64-6143.95" + cell $not $not$ls180.v:6143$1455 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_we + connect \Y $not$ls180.v:6143$1455_Y + end + attribute \src "ls180.v:6146.64-6146.95" + cell $not $not$ls180.v:6146$1462 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_we + connect \Y $not$ls180.v:6146$1462_Y + end + attribute \src "ls180.v:6159.64-6159.95" + cell $not $not$ls180.v:6159$1470 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_we + connect \Y $not$ls180.v:6159$1470_Y + end + attribute \src "ls180.v:6162.63-6162.94" + cell $not $not$ls180.v:6162$1477 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_we + connect \Y $not$ls180.v:6162$1477_Y + end + attribute \src "ls180.v:6165.63-6165.94" + cell $not $not$ls180.v:6165$1484 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_we + connect \Y $not$ls180.v:6165$1484_Y + end + attribute \src "ls180.v:6168.63-6168.94" + cell $not $not$ls180.v:6168$1491 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_we + connect \Y $not$ls180.v:6168$1491_Y + end + attribute \src "ls180.v:6171.63-6171.94" + cell $not $not$ls180.v:6171$1498 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_we + connect \Y $not$ls180.v:6171$1498_Y + end + attribute \src "ls180.v:6174.64-6174.95" + cell $not $not$ls180.v:6174$1505 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_we + connect \Y $not$ls180.v:6174$1505_Y + end + attribute \src "ls180.v:6177.64-6177.95" + cell $not $not$ls180.v:6177$1512 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_we + connect \Y $not$ls180.v:6177$1512_Y + end + attribute \src "ls180.v:6180.64-6180.95" + cell $not $not$ls180.v:6180$1519 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_we + connect \Y $not$ls180.v:6180$1519_Y + end + attribute \src "ls180.v:6183.64-6183.95" + cell $not $not$ls180.v:6183$1526 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_we + connect \Y $not$ls180.v:6183$1526_Y + end + attribute \src "ls180.v:6196.66-6196.97" + cell $not $not$ls180.v:6196$1534 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:6196$1534_Y + end + attribute \src "ls180.v:6199.66-6199.97" + cell $not $not$ls180.v:6199$1541 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:6199$1541_Y + end + attribute \src "ls180.v:6202.66-6202.97" + cell $not $not$ls180.v:6202$1548 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:6202$1548_Y + end + attribute \src "ls180.v:6205.66-6205.97" + cell $not $not$ls180.v:6205$1555 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:6205$1555_Y + end + attribute \src "ls180.v:6208.66-6208.97" + cell $not $not$ls180.v:6208$1562 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:6208$1562_Y + end + attribute \src "ls180.v:6211.66-6211.97" + cell $not $not$ls180.v:6211$1569 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:6211$1569_Y + end + attribute \src "ls180.v:6214.66-6214.97" + cell $not $not$ls180.v:6214$1576 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:6214$1576_Y + end + attribute \src "ls180.v:6217.66-6217.97" + cell $not $not$ls180.v:6217$1583 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:6217$1583_Y + end + attribute \src "ls180.v:6220.68-6220.99" + cell $not $not$ls180.v:6220$1590 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:6220$1590_Y + end + attribute \src "ls180.v:6223.68-6223.99" + cell $not $not$ls180.v:6223$1597 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:6223$1597_Y + end + attribute \src "ls180.v:6226.68-6226.99" + cell $not $not$ls180.v:6226$1604 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:6226$1604_Y + end + attribute \src "ls180.v:6229.68-6229.99" + cell $not $not$ls180.v:6229$1611 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:6229$1611_Y + end + attribute \src "ls180.v:6232.68-6232.99" + cell $not $not$ls180.v:6232$1618 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:6232$1618_Y + end + attribute \src "ls180.v:6235.65-6235.96" + cell $not $not$ls180.v:6235$1625 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:6235$1625_Y + end + attribute \src "ls180.v:6238.66-6238.97" + cell $not $not$ls180.v:6238$1632 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$ls180.v:6238$1632_Y + end + attribute \src "ls180.v:6258.70-6258.101" + cell $not $not$ls180.v:6258$1640 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6258$1640_Y + end + attribute \src "ls180.v:6261.70-6261.101" + cell $not $not$ls180.v:6261$1647 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6261$1647_Y + end + attribute \src "ls180.v:6264.70-6264.101" + cell $not $not$ls180.v:6264$1654 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6264$1654_Y + end + attribute \src "ls180.v:6267.70-6267.101" + cell $not $not$ls180.v:6267$1661 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6267$1661_Y + end + attribute \src "ls180.v:6270.69-6270.100" + cell $not $not$ls180.v:6270$1668 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6270$1668_Y + end + attribute \src "ls180.v:6273.69-6273.100" + cell $not $not$ls180.v:6273$1675 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6273$1675_Y + end + attribute \src "ls180.v:6276.69-6276.100" + cell $not $not$ls180.v:6276$1682 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6276$1682_Y + end + attribute \src "ls180.v:6279.69-6279.100" + cell $not $not$ls180.v:6279$1689 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6279$1689_Y + end + attribute \src "ls180.v:6282.60-6282.91" + cell $not $not$ls180.v:6282$1696 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6282$1696_Y + end + attribute \src "ls180.v:6285.71-6285.102" + cell $not $not$ls180.v:6285$1703 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6285$1703_Y + end + attribute \src "ls180.v:6288.71-6288.102" + cell $not $not$ls180.v:6288$1710 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6288$1710_Y + end + attribute \src "ls180.v:6291.71-6291.102" + cell $not $not$ls180.v:6291$1717 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6291$1717_Y + end + attribute \src "ls180.v:6294.71-6294.102" + cell $not $not$ls180.v:6294$1724 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6294$1724_Y + end + attribute \src "ls180.v:6297.71-6297.102" + cell $not $not$ls180.v:6297$1731 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6297$1731_Y + end + attribute \src "ls180.v:6300.71-6300.102" + cell $not $not$ls180.v:6300$1738 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6300$1738_Y + end + attribute \src "ls180.v:6303.70-6303.101" + cell $not $not$ls180.v:6303$1745 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6303$1745_Y + end + attribute \src "ls180.v:6306.70-6306.101" + cell $not $not$ls180.v:6306$1752 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6306$1752_Y + end + attribute \src "ls180.v:6309.70-6309.101" + cell $not $not$ls180.v:6309$1759 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6309$1759_Y + end + attribute \src "ls180.v:6312.70-6312.101" + cell $not $not$ls180.v:6312$1766 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6312$1766_Y + end + attribute \src "ls180.v:6315.70-6315.101" + cell $not $not$ls180.v:6315$1773 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6315$1773_Y + end + attribute \src "ls180.v:6318.70-6318.101" + cell $not $not$ls180.v:6318$1780 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6318$1780_Y + end + attribute \src "ls180.v:6321.70-6321.101" + cell $not $not$ls180.v:6321$1787 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6321$1787_Y + end + attribute \src "ls180.v:6324.70-6324.101" + cell $not $not$ls180.v:6324$1794 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6324$1794_Y + end + attribute \src "ls180.v:6327.70-6327.101" + cell $not $not$ls180.v:6327$1801 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6327$1801_Y + end + attribute \src "ls180.v:6330.70-6330.101" + cell $not $not$ls180.v:6330$1808 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6330$1808_Y + end + attribute \src "ls180.v:6333.66-6333.97" + cell $not $not$ls180.v:6333$1815 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6333$1815_Y + end + attribute \src "ls180.v:6336.67-6336.98" + cell $not $not$ls180.v:6336$1822 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6336$1822_Y + end + attribute \src "ls180.v:6339.70-6339.101" + cell $not $not$ls180.v:6339$1829 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6339$1829_Y + end + attribute \src "ls180.v:6342.70-6342.101" + cell $not $not$ls180.v:6342$1836 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6342$1836_Y + end + attribute \src "ls180.v:6345.69-6345.100" + cell $not $not$ls180.v:6345$1843 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6345$1843_Y + end + attribute \src "ls180.v:6348.69-6348.100" + cell $not $not$ls180.v:6348$1850 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6348$1850_Y + end + attribute \src "ls180.v:6351.69-6351.100" + cell $not $not$ls180.v:6351$1857 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6351$1857_Y + end + attribute \src "ls180.v:6354.69-6354.100" + cell $not $not$ls180.v:6354$1864 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$ls180.v:6354$1864_Y + end + attribute \src "ls180.v:6393.66-6393.97" + cell $not $not$ls180.v:6393$1872 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_we + connect \Y $not$ls180.v:6393$1872_Y + end + attribute \src "ls180.v:6396.66-6396.97" + cell $not $not$ls180.v:6396$1879 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_we + connect \Y $not$ls180.v:6396$1879_Y + end + attribute \src "ls180.v:6399.66-6399.97" + cell $not $not$ls180.v:6399$1886 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_we + connect \Y $not$ls180.v:6399$1886_Y + end + attribute \src "ls180.v:6402.66-6402.97" + cell $not $not$ls180.v:6402$1893 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_we + connect \Y $not$ls180.v:6402$1893_Y + end + attribute \src "ls180.v:6405.66-6405.97" + cell $not $not$ls180.v:6405$1900 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_we + connect \Y $not$ls180.v:6405$1900_Y + end + attribute \src "ls180.v:6408.66-6408.97" + cell $not $not$ls180.v:6408$1907 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_we + connect \Y $not$ls180.v:6408$1907_Y + end + attribute \src "ls180.v:6411.66-6411.97" + cell $not $not$ls180.v:6411$1914 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_we + connect \Y $not$ls180.v:6411$1914_Y + end + attribute \src "ls180.v:6414.66-6414.97" + cell $not $not$ls180.v:6414$1921 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_we + connect \Y $not$ls180.v:6414$1921_Y + end + attribute \src "ls180.v:6417.68-6417.99" + cell $not $not$ls180.v:6417$1928 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_we + connect \Y $not$ls180.v:6417$1928_Y + end + attribute \src "ls180.v:6420.68-6420.99" + cell $not $not$ls180.v:6420$1935 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_we + connect \Y $not$ls180.v:6420$1935_Y + end + attribute \src "ls180.v:6423.68-6423.99" + cell $not $not$ls180.v:6423$1942 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_we + connect \Y $not$ls180.v:6423$1942_Y + end + attribute \src "ls180.v:6426.68-6426.99" + cell $not $not$ls180.v:6426$1949 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_we + connect \Y $not$ls180.v:6426$1949_Y + end + attribute \src "ls180.v:6429.68-6429.99" + cell $not $not$ls180.v:6429$1956 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_we + connect \Y $not$ls180.v:6429$1956_Y + end + attribute \src "ls180.v:6432.65-6432.96" + cell $not $not$ls180.v:6432$1963 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_we + connect \Y $not$ls180.v:6432$1963_Y + end + attribute \src "ls180.v:6435.66-6435.97" + cell $not $not$ls180.v:6435$1970 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_we + connect \Y $not$ls180.v:6435$1970_Y + end + attribute \src "ls180.v:6438.68-6438.99" + cell $not $not$ls180.v:6438$1977 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_we + connect \Y $not$ls180.v:6438$1977_Y + end + attribute \src "ls180.v:6441.68-6441.99" + cell $not $not$ls180.v:6441$1984 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_we + connect \Y $not$ls180.v:6441$1984_Y + end + attribute \src "ls180.v:6444.68-6444.99" + cell $not $not$ls180.v:6444$1991 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_we + connect \Y $not$ls180.v:6444$1991_Y + end + attribute \src "ls180.v:6447.68-6447.99" + cell $not $not$ls180.v:6447$1998 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_we + connect \Y $not$ls180.v:6447$1998_Y + end + attribute \src "ls180.v:6472.68-6472.99" + cell $not $not$ls180.v:6472$2006 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_we + connect \Y $not$ls180.v:6472$2006_Y + end + attribute \src "ls180.v:6475.73-6475.104" + cell $not $not$ls180.v:6475$2013 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_we + connect \Y $not$ls180.v:6475$2013_Y + end + attribute \src "ls180.v:6478.73-6478.104" + cell $not $not$ls180.v:6478$2020 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_we + connect \Y $not$ls180.v:6478$2020_Y + end + attribute \src "ls180.v:6481.66-6481.97" + cell $not $not$ls180.v:6481$2027 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_we + connect \Y $not$ls180.v:6481$2027_Y + end + attribute \src "ls180.v:6489.70-6489.101" + cell $not $not$ls180.v:6489$2035 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_we + connect \Y $not$ls180.v:6489$2035_Y + end + attribute \src "ls180.v:6492.74-6492.105" + cell $not $not$ls180.v:6492$2042 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_we + connect \Y $not$ls180.v:6492$2042_Y + end + attribute \src "ls180.v:6495.64-6495.95" + cell $not $not$ls180.v:6495$2049 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_we + connect \Y $not$ls180.v:6495$2049_Y + end + attribute \src "ls180.v:6498.74-6498.105" + cell $not $not$ls180.v:6498$2056 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_we + connect \Y $not$ls180.v:6498$2056_Y + end + attribute \src "ls180.v:6501.74-6501.105" + cell $not $not$ls180.v:6501$2063 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_we + connect \Y $not$ls180.v:6501$2063_Y + end + attribute \src "ls180.v:6504.75-6504.106" + cell $not $not$ls180.v:6504$2070 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_we + connect \Y $not$ls180.v:6504$2070_Y + end + attribute \src "ls180.v:6507.73-6507.104" + cell $not $not$ls180.v:6507$2077 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_we + connect \Y $not$ls180.v:6507$2077_Y + end + attribute \src "ls180.v:6510.73-6510.104" + cell $not $not$ls180.v:6510$2084 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_we + connect \Y $not$ls180.v:6510$2084_Y + end + attribute \src "ls180.v:6513.73-6513.104" + cell $not $not$ls180.v:6513$2091 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_we + connect \Y $not$ls180.v:6513$2091_Y + end + attribute \src "ls180.v:6516.73-6516.104" + cell $not $not$ls180.v:6516$2098 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_we + connect \Y $not$ls180.v:6516$2098_Y + end + attribute \src "ls180.v:6534.67-6534.99" + cell $not $not$ls180.v:6534$2106 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_we + connect \Y $not$ls180.v:6534$2106_Y + end + attribute \src "ls180.v:6537.67-6537.99" + cell $not $not$ls180.v:6537$2113 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_we + connect \Y $not$ls180.v:6537$2113_Y + end + attribute \src "ls180.v:6540.65-6540.97" + cell $not $not$ls180.v:6540$2120 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_we + connect \Y $not$ls180.v:6540$2120_Y + end + attribute \src "ls180.v:6543.64-6543.96" + cell $not $not$ls180.v:6543$2127 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_we + connect \Y $not$ls180.v:6543$2127_Y + end + attribute \src "ls180.v:6546.63-6546.95" + cell $not $not$ls180.v:6546$2134 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_we + connect \Y $not$ls180.v:6546$2134_Y + end + attribute \src "ls180.v:6549.62-6549.94" + cell $not $not$ls180.v:6549$2141 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_we + connect \Y $not$ls180.v:6549$2141_Y + end + attribute \src "ls180.v:6552.68-6552.100" + cell $not $not$ls180.v:6552$2148 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_we + connect \Y $not$ls180.v:6552$2148_Y + end + attribute \src "ls180.v:6574.67-6574.99" + cell $not $not$ls180.v:6574$2157 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_we + connect \Y $not$ls180.v:6574$2157_Y + end + attribute \src "ls180.v:6577.67-6577.99" + cell $not $not$ls180.v:6577$2164 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_we + connect \Y $not$ls180.v:6577$2164_Y + end + attribute \src "ls180.v:6580.65-6580.97" + cell $not $not$ls180.v:6580$2171 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_we + connect \Y $not$ls180.v:6580$2171_Y + end + attribute \src "ls180.v:6583.64-6583.96" + cell $not $not$ls180.v:6583$2178 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_we + connect \Y $not$ls180.v:6583$2178_Y + end + attribute \src "ls180.v:6586.63-6586.95" + cell $not $not$ls180.v:6586$2185 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_we + connect \Y $not$ls180.v:6586$2185_Y + end + attribute \src "ls180.v:6589.62-6589.94" + cell $not $not$ls180.v:6589$2192 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_we + connect \Y $not$ls180.v:6589$2192_Y + end + attribute \src "ls180.v:6592.68-6592.100" + cell $not $not$ls180.v:6592$2199 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_we + connect \Y $not$ls180.v:6592$2199_Y + end + attribute \src "ls180.v:6595.71-6595.103" + cell $not $not$ls180.v:6595$2206 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_we + connect \Y $not$ls180.v:6595$2206_Y + end + attribute \src "ls180.v:6598.71-6598.103" + cell $not $not$ls180.v:6598$2213 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_we + connect \Y $not$ls180.v:6598$2213_Y + end + attribute \src "ls180.v:6622.64-6622.96" + cell $not $not$ls180.v:6622$2222 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_we + connect \Y $not$ls180.v:6622$2222_Y + end + attribute \src "ls180.v:6625.64-6625.96" + cell $not $not$ls180.v:6625$2229 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_we + connect \Y $not$ls180.v:6625$2229_Y + end + attribute \src "ls180.v:6628.64-6628.96" + cell $not $not$ls180.v:6628$2236 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_we + connect \Y $not$ls180.v:6628$2236_Y + end + attribute \src "ls180.v:6631.64-6631.96" + cell $not $not$ls180.v:6631$2243 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_we + connect \Y $not$ls180.v:6631$2243_Y + end + attribute \src "ls180.v:6634.66-6634.98" + cell $not $not$ls180.v:6634$2250 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_we + connect \Y $not$ls180.v:6634$2250_Y + end + attribute \src "ls180.v:6637.66-6637.98" + cell $not $not$ls180.v:6637$2257 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_we + connect \Y $not$ls180.v:6637$2257_Y + end + attribute \src "ls180.v:6640.66-6640.98" + cell $not $not$ls180.v:6640$2264 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_we + connect \Y $not$ls180.v:6640$2264_Y + end + attribute \src "ls180.v:6643.66-6643.98" + cell $not $not$ls180.v:6643$2271 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_we + connect \Y $not$ls180.v:6643$2271_Y + end + attribute \src "ls180.v:6646.62-6646.94" + cell $not $not$ls180.v:6646$2278 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_we + connect \Y $not$ls180.v:6646$2278_Y + end + attribute \src "ls180.v:6649.72-6649.104" + cell $not $not$ls180.v:6649$2285 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_we + connect \Y $not$ls180.v:6649$2285_Y + end + attribute \src "ls180.v:6652.65-6652.97" + cell $not $not$ls180.v:6652$2292 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_we + connect \Y $not$ls180.v:6652$2292_Y + end + attribute \src "ls180.v:6655.65-6655.97" + cell $not $not$ls180.v:6655$2299 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_we + connect \Y $not$ls180.v:6655$2299_Y + end + attribute \src "ls180.v:6658.65-6658.97" + cell $not $not$ls180.v:6658$2306 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_we + connect \Y $not$ls180.v:6658$2306_Y + end + attribute \src "ls180.v:6661.65-6661.97" + cell $not $not$ls180.v:6661$2313 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_we + connect \Y $not$ls180.v:6661$2313_Y + end + attribute \src "ls180.v:6664.77-6664.109" + cell $not $not$ls180.v:6664$2320 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_we + connect \Y $not$ls180.v:6664$2320_Y + end + attribute \src "ls180.v:6667.78-6667.110" + cell $not $not$ls180.v:6667$2327 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_we + connect \Y $not$ls180.v:6667$2327_Y + end + attribute \src "ls180.v:6670.69-6670.101" + cell $not $not$ls180.v:6670$2334 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_we + connect \Y $not$ls180.v:6670$2334_Y + end + attribute \src "ls180.v:6690.55-6690.87" + cell $not $not$ls180.v:6690$2342 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_we + connect \Y $not$ls180.v:6690$2342_Y + end + attribute \src "ls180.v:6693.65-6693.97" + cell $not $not$ls180.v:6693$2349 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_we + connect \Y $not$ls180.v:6693$2349_Y + end + attribute \src "ls180.v:6696.66-6696.98" + cell $not $not$ls180.v:6696$2356 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_we + connect \Y $not$ls180.v:6696$2356_Y + end + attribute \src "ls180.v:6699.70-6699.102" + cell $not $not$ls180.v:6699$2363 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_we + connect \Y $not$ls180.v:6699$2363_Y + end + attribute \src "ls180.v:6702.71-6702.103" + cell $not $not$ls180.v:6702$2370 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_we + connect \Y $not$ls180.v:6702$2370_Y + end + attribute \src "ls180.v:6705.69-6705.101" + cell $not $not$ls180.v:6705$2377 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_we + connect \Y $not$ls180.v:6705$2377_Y + end + attribute \src "ls180.v:6708.66-6708.98" + cell $not $not$ls180.v:6708$2384 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_we + connect \Y $not$ls180.v:6708$2384_Y + end + attribute \src "ls180.v:6711.65-6711.97" + cell $not $not$ls180.v:6711$2391 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface13_bank_bus_we + connect \Y $not$ls180.v:6711$2391_Y + end + attribute \src "ls180.v:6724.71-6724.103" + cell $not $not$ls180.v:6724$2399 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface14_bank_bus_we + connect \Y $not$ls180.v:6724$2399_Y + end + attribute \src "ls180.v:6727.71-6727.103" + cell $not $not$ls180.v:6727$2406 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface14_bank_bus_we + connect \Y $not$ls180.v:6727$2406_Y + end + attribute \src "ls180.v:6730.71-6730.103" + cell $not $not$ls180.v:6730$2413 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface14_bank_bus_we + connect \Y $not$ls180.v:6730$2413_Y + end + attribute \src "ls180.v:6733.71-6733.103" + cell $not $not$ls180.v:6733$2420 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface14_bank_bus_we + connect \Y $not$ls180.v:6733$2420_Y + end + attribute \src "ls180.v:7114.86-7114.330" + cell $not $not$ls180.v:7114$2469 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:7114$2468_Y + connect \Y $not$ls180.v:7114$2469_Y + end + attribute \src "ls180.v:7138.86-7138.330" + cell $not $not$ls180.v:7138$2485 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:7138$2484_Y + connect \Y $not$ls180.v:7138$2485_Y + end + attribute \src "ls180.v:7162.86-7162.330" + cell $not $not$ls180.v:7162$2501 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:7162$2500_Y + connect \Y $not$ls180.v:7162$2501_Y + end + attribute \src "ls180.v:7186.86-7186.330" + cell $not $not$ls180.v:7186$2517 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:7186$2516_Y + connect \Y $not$ls180.v:7186$2517_Y + end + attribute \src "ls180.v:7687.18-7687.42" + cell $not $not$ls180.v:7687$2571 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_clocker_clk0 + connect \Y $not$ls180.v:7687$2571_Y + end + attribute \src "ls180.v:7766.72-7766.101" + cell $not $not$ls180.v:7766$2604 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_ram_bus_ack + connect \Y $not$ls180.v:7766$2604_Y + end + attribute \src "ls180.v:7785.8-7785.38" + cell $not $not$ls180.v:7785$2608 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_zero_trigger + connect \Y $not$ls180.v:7785$2608_Y + end + attribute \src "ls180.v:7789.70-7789.98" + cell $not $not$ls180.v:7789$2611 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface0_ram_bus_ack + connect \Y $not$ls180.v:7789$2611_Y + end + attribute \src "ls180.v:7793.70-7793.98" + cell $not $not$ls180.v:7793$2614 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface1_ram_bus_ack + connect \Y $not$ls180.v:7793$2614_Y + end + attribute \src "ls180.v:7797.70-7797.98" + cell $not $not$ls180.v:7797$2617 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface2_ram_bus_ack + connect \Y $not$ls180.v:7797$2617_Y + end + attribute \src "ls180.v:7801.70-7801.98" + cell $not $not$ls180.v:7801$2620 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_interface3_ram_bus_ack + connect \Y $not$ls180.v:7801$2620_Y + end + attribute \src "ls180.v:7809.32-7809.55" + cell $not $not$ls180.v:7809$2622 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_timer_done0 + connect \Y $not$ls180.v:7809$2622_Y + end + attribute \src "ls180.v:7879.136-7879.189" + cell $not $not$ls180.v:7879$2637 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_replace + connect \Y $not$ls180.v:7879$2637_Y + end + attribute \src "ls180.v:7885.136-7885.189" + cell $not $not$ls180.v:7885$2642 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_replace + connect \Y $not$ls180.v:7885$2642_Y + end + attribute \src "ls180.v:7886.8-7886.61" + cell $not $not$ls180.v:7886$2644 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read + connect \Y $not$ls180.v:7886$2644_Y + end + attribute \src "ls180.v:7894.8-7894.56" + cell $not $not$ls180.v:7894$2647 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_buffer_source_valid + connect \Y $not$ls180.v:7894$2647_Y + end + attribute \src "ls180.v:7909.8-7909.46" + cell $not $not$ls180.v:7909$2649 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_twtpcon_ready + connect \Y $not$ls180.v:7909$2649_Y + end + attribute \src "ls180.v:7925.136-7925.189" + cell $not $not$ls180.v:7925$2653 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_replace + connect \Y $not$ls180.v:7925$2653_Y + end + attribute \src "ls180.v:7931.136-7931.189" + cell $not $not$ls180.v:7931$2658 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_replace + connect \Y $not$ls180.v:7931$2658_Y + end + attribute \src "ls180.v:7932.8-7932.61" + cell $not $not$ls180.v:7932$2660 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read + connect \Y $not$ls180.v:7932$2660_Y + end + attribute \src "ls180.v:7940.8-7940.56" + cell $not $not$ls180.v:7940$2663 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_buffer_source_valid + connect \Y $not$ls180.v:7940$2663_Y + end + attribute \src "ls180.v:7955.8-7955.46" + cell $not $not$ls180.v:7955$2665 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_twtpcon_ready + connect \Y $not$ls180.v:7955$2665_Y + end + attribute \src "ls180.v:7971.136-7971.189" + cell $not $not$ls180.v:7971$2669 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_replace + connect \Y $not$ls180.v:7971$2669_Y + end + attribute \src "ls180.v:7977.136-7977.189" + cell $not $not$ls180.v:7977$2674 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_replace + connect \Y $not$ls180.v:7977$2674_Y + end + attribute \src "ls180.v:7978.8-7978.61" + cell $not $not$ls180.v:7978$2676 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read + connect \Y $not$ls180.v:7978$2676_Y + end + attribute \src "ls180.v:7986.8-7986.56" + cell $not $not$ls180.v:7986$2679 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_buffer_source_valid + connect \Y $not$ls180.v:7986$2679_Y + end + attribute \src "ls180.v:8001.8-8001.46" + cell $not $not$ls180.v:8001$2681 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_twtpcon_ready + connect \Y $not$ls180.v:8001$2681_Y + end + attribute \src "ls180.v:8017.136-8017.189" + cell $not $not$ls180.v:8017$2685 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_replace + connect \Y $not$ls180.v:8017$2685_Y + end + attribute \src "ls180.v:8023.136-8023.189" + cell $not $not$ls180.v:8023$2690 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_replace + connect \Y $not$ls180.v:8023$2690_Y + end + attribute \src "ls180.v:8024.8-8024.61" + cell $not $not$ls180.v:8024$2692 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read + connect \Y $not$ls180.v:8024$2692_Y + end + attribute \src "ls180.v:8032.8-8032.56" + cell $not $not$ls180.v:8032$2695 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_buffer_source_valid + connect \Y $not$ls180.v:8032$2695_Y + end + attribute \src "ls180.v:8047.8-8047.46" + cell $not $not$ls180.v:8047$2697 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_twtpcon_ready + connect \Y $not$ls180.v:8047$2697_Y + end + attribute \src "ls180.v:8055.7-8055.22" + cell $not $not$ls180.v:8055$2700 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_en0 + connect \Y $not$ls180.v:8055$2700_Y + end + attribute \src "ls180.v:8058.8-8058.29" + cell $not $not$ls180.v:8058$2701 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_max_time0 + connect \Y $not$ls180.v:8058$2701_Y + end + attribute \src "ls180.v:8062.7-8062.22" + cell $not $not$ls180.v:8062$2703 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_en1 + connect \Y $not$ls180.v:8062$2703_Y + end + attribute \src "ls180.v:8065.8-8065.29" + cell $not $not$ls180.v:8065$2704 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_max_time1 + connect \Y $not$ls180.v:8065$2704_Y + end + attribute \src "ls180.v:8184.30-8184.60" + cell $not $not$ls180.v:8184$2706 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_sync_rhs_array_muxed2 + connect \Y $not$ls180.v:8184$2706_Y + end + attribute \src "ls180.v:8185.30-8185.60" + cell $not $not$ls180.v:8185$2707 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_sync_rhs_array_muxed3 + connect \Y $not$ls180.v:8185$2707_Y + end + attribute \src "ls180.v:8186.29-8186.59" + cell $not $not$ls180.v:8186$2708 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_sync_rhs_array_muxed4 + connect \Y $not$ls180.v:8186$2708_Y + end + attribute \src "ls180.v:8197.8-8197.33" + cell $not $not$ls180.v:8197$2709 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_tccdcon_ready + connect \Y $not$ls180.v:8197$2709_Y + end + attribute \src "ls180.v:8212.8-8212.33" + cell $not $not$ls180.v:8212$2712 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_twtrcon_ready + connect \Y $not$ls180.v:8212$2712_Y + end + attribute \src "ls180.v:8248.36-8248.58" + cell $not $not$ls180.v:8248$2742 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_phy_tx_busy + connect \Y $not$ls180.v:8248$2742_Y + end + attribute \src "ls180.v:8248.64-8248.89" + cell $not $not$ls180.v:8248$2744 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_phy_sink_ready + connect \Y $not$ls180.v:8248$2744_Y + end + attribute \src "ls180.v:8277.7-8277.29" + cell $not $not$ls180.v:8277$2751 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_phy_rx_busy + connect \Y $not$ls180.v:8277$2751_Y + end + attribute \src "ls180.v:8278.9-8278.26" + cell $not $not$ls180.v:8278$2752 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_phy_rx + connect \Y $not$ls180.v:8278$2752_Y + end + attribute \src "ls180.v:8311.8-8311.29" + cell $not $not$ls180.v:8311$2758 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_tx_trigger + connect \Y $not$ls180.v:8311$2758_Y + end + attribute \src "ls180.v:8318.8-8318.29" + cell $not $not$ls180.v:8318$2760 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_rx_trigger + connect \Y $not$ls180.v:8318$2760_Y + end + attribute \src "ls180.v:8328.80-8328.106" + cell $not $not$ls180.v:8328$2763 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_tx_fifo_replace + connect \Y $not$ls180.v:8328$2763_Y + end + attribute \src "ls180.v:8334.80-8334.106" + cell $not $not$ls180.v:8334$2768 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_tx_fifo_replace + connect \Y $not$ls180.v:8334$2768_Y + end + attribute \src "ls180.v:8335.8-8335.34" + cell $not $not$ls180.v:8335$2770 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_tx_fifo_do_read + connect \Y $not$ls180.v:8335$2770_Y + end + attribute \src "ls180.v:8350.80-8350.106" + cell $not $not$ls180.v:8350$2774 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_rx_fifo_replace + connect \Y $not$ls180.v:8350$2774_Y + end + attribute \src "ls180.v:8356.80-8356.106" + cell $not $not$ls180.v:8356$2779 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_rx_fifo_replace + connect \Y $not$ls180.v:8356$2779_Y + end + attribute \src "ls180.v:8357.8-8357.34" + cell $not $not$ls180.v:8357$2781 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_rx_fifo_do_read + connect \Y $not$ls180.v:8357$2781_Y + end + attribute \src "ls180.v:8388.22-8388.41" + cell $not $not$ls180.v:8388$2785 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_spimaster6_cs + connect \Y $not$ls180.v:8388$2785_Y + end + attribute \src "ls180.v:8388.46-8388.73" + cell $not $not$ls180.v:8388$2786 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_spimaster26_cs_enable + connect \Y $not$ls180.v:8388$2786_Y + end + attribute \src "ls180.v:8423.22-8423.40" + cell $not $not$ls180.v:8423$2790 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_spisdcard_cs + connect \Y $not$ls180.v:8423$2790_Y + end + attribute \src "ls180.v:8423.45-8423.70" + cell $not $not$ls180.v:8423$2791 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_spisdcard_cs_enable + connect \Y $not$ls180.v:8423$2791_Y + end + attribute \src "ls180.v:8477.7-8477.31" + cell $not $not$ls180.v:8477$2802 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_clocker_stop + connect \Y $not$ls180.v:8477$2802_Y + end + attribute \src "ls180.v:8549.8-8549.46" + cell $not $not$ls180.v:8549$2814 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_cmdr_buf_source_valid + connect \Y $not$ls180.v:8549$2814_Y + end + attribute \src "ls180.v:8630.8-8630.47" + cell $not $not$ls180.v:8630$2826 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_crcr_buf_source_valid + connect \Y $not$ls180.v:8630$2826_Y + end + attribute \src "ls180.v:8691.8-8691.48" + cell $not $not$ls180.v:8691$2838 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_datar_buf_source_valid + connect \Y $not$ls180.v:8691$2838_Y + end + attribute \src "ls180.v:8861.88-8861.118" + cell $not $not$ls180.v:8861$2852 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_fifo_replace + connect \Y $not$ls180.v:8861$2852_Y + end + attribute \src "ls180.v:8867.88-8867.118" + cell $not $not$ls180.v:8867$2857 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_fifo_replace + connect \Y $not$ls180.v:8867$2857_Y + end + attribute \src "ls180.v:8868.8-8868.38" + cell $not $not$ls180.v:8868$2859 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_fifo_do_read + connect \Y $not$ls180.v:8868$2859_Y + end + attribute \src "ls180.v:8959.88-8959.118" + cell $not $not$ls180.v:8959$2874 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdmem2block_fifo_replace + connect \Y $not$ls180.v:8959$2874_Y + end + attribute \src "ls180.v:8965.88-8965.118" + cell $not $not$ls180.v:8965$2879 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdmem2block_fifo_replace + connect \Y $not$ls180.v:8965$2879_Y + end + attribute \src "ls180.v:8966.8-8966.38" + cell $not $not$ls180.v:8966$2881 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdmem2block_fifo_do_read + connect \Y $not$ls180.v:8966$2881_Y + end + attribute \src "ls180.v:8986.9-8986.28" + cell $not $not$ls180.v:8986$2884 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_request [0] + connect \Y $not$ls180.v:8986$2884_Y + end + attribute \src "ls180.v:9005.9-9005.28" + cell $not $not$ls180.v:9005$2885 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_request [1] + connect \Y $not$ls180.v:9005$2885_Y + end + attribute \src "ls180.v:9024.9-9024.28" + cell $not $not$ls180.v:9024$2886 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_request [2] + connect \Y $not$ls180.v:9024$2886_Y + end + attribute \src "ls180.v:9043.9-9043.28" + cell $not $not$ls180.v:9043$2887 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_request [3] + connect \Y $not$ls180.v:9043$2887_Y + end + attribute \src "ls180.v:9062.9-9062.28" + cell $not $not$ls180.v:9062$2888 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_request [4] + connect \Y $not$ls180.v:9062$2888_Y + end + attribute \src "ls180.v:9083.8-9083.21" + cell $not $not$ls180.v:9083$2889 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_done + connect \Y $not$ls180.v:9083$2889_Y + end + attribute \src "ls180.v:10706.8-10706.51" + cell $or $or$ls180.v:10706$3077 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \sys_rst_1 + connect \B \main_libresocsim_libresoc_reset + connect \Y $or$ls180.v:10706$3077_Y + end + attribute \src "ls180.v:2931.10-2931.71" + cell $or $or$ls180.v:2931$57 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_libresoc_xics_icp_ack + connect \B \main_converter0_skip + connect \Y $or$ls180.v:2931$57_Y + end + attribute \src "ls180.v:2991.10-2991.71" + cell $or $or$ls180.v:2991$68 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_libresoc_xics_ics_ack + connect \B \main_converter1_skip + connect \Y $or$ls180.v:2991$68_Y + end + attribute \src "ls180.v:3051.10-3051.53" + cell $or $or$ls180.v:3051$79 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_wb_sdram_ack + connect \B \main_socbushandler_skip + connect \Y $or$ls180.v:3051$79_Y + end + attribute \src "ls180.v:3303.39-3303.105" + cell $or $or$ls180.v:3303$223 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_sequencer_start0 + connect \B $ne$ls180.v:3303$222_Y + connect \Y $or$ls180.v:3303$223_Y + end + attribute \src "ls180.v:3346.59-3346.140" + cell $or $or$ls180.v:3346$227 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_req_wdata_ready + connect \B \main_sdram_bankmachine0_req_rdata_valid + connect \Y $or$ls180.v:3346$227_Y + end + attribute \src "ls180.v:3347.44-3347.151" + cell $or $or$ls180.v:3347$228 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_source_valid + connect \B \main_sdram_bankmachine0_cmd_buffer_source_valid + connect \Y $or$ls180.v:3347$228_Y + end + attribute \src "ls180.v:3355.45-3355.170" + cell $or $or$ls180.v:3355$232 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 13 + connect \A $sshl$ls180.v:3355$231_Y + connect \B { 4'0000 \main_sdram_bankmachine0_cmd_buffer_source_payload_addr [8:0] } + connect \Y $or$ls180.v:3355$232_Y + end + attribute \src "ls180.v:3392.127-3392.245" + cell $or $or$ls180.v:3392$245 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable + connect \B \main_sdram_bankmachine0_cmd_buffer_lookahead_replace + connect \Y $or$ls180.v:3392$245_Y + end + attribute \src "ls180.v:3398.57-3398.157" + cell $or $or$ls180.v:3398$251 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:3398$250_Y + connect \B \main_sdram_bankmachine0_cmd_buffer_source_ready + connect \Y $or$ls180.v:3398$251_Y + end + attribute \src "ls180.v:3503.59-3503.140" + cell $or $or$ls180.v:3503$257 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_req_wdata_ready + connect \B \main_sdram_bankmachine1_req_rdata_valid + connect \Y $or$ls180.v:3503$257_Y + end + attribute \src "ls180.v:3504.44-3504.151" + cell $or $or$ls180.v:3504$258 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_source_valid + connect \B \main_sdram_bankmachine1_cmd_buffer_source_valid + connect \Y $or$ls180.v:3504$258_Y + end + attribute \src "ls180.v:3512.45-3512.170" + cell $or $or$ls180.v:3512$262 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 13 + connect \A $sshl$ls180.v:3512$261_Y + connect \B { 4'0000 \main_sdram_bankmachine1_cmd_buffer_source_payload_addr [8:0] } + connect \Y $or$ls180.v:3512$262_Y + end + attribute \src "ls180.v:3549.127-3549.245" + cell $or $or$ls180.v:3549$275 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable + connect \B \main_sdram_bankmachine1_cmd_buffer_lookahead_replace + connect \Y $or$ls180.v:3549$275_Y + end + attribute \src "ls180.v:3555.57-3555.157" + cell $or $or$ls180.v:3555$281 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:3555$280_Y + connect \B \main_sdram_bankmachine1_cmd_buffer_source_ready + connect \Y $or$ls180.v:3555$281_Y + end + attribute \src "ls180.v:3660.59-3660.140" + cell $or $or$ls180.v:3660$287 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_req_wdata_ready + connect \B \main_sdram_bankmachine2_req_rdata_valid + connect \Y $or$ls180.v:3660$287_Y + end + attribute \src "ls180.v:3661.44-3661.151" + cell $or $or$ls180.v:3661$288 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_source_valid + connect \B \main_sdram_bankmachine2_cmd_buffer_source_valid + connect \Y $or$ls180.v:3661$288_Y + end + attribute \src "ls180.v:3669.45-3669.170" + cell $or $or$ls180.v:3669$292 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 13 + connect \A $sshl$ls180.v:3669$291_Y + connect \B { 4'0000 \main_sdram_bankmachine2_cmd_buffer_source_payload_addr [8:0] } + connect \Y $or$ls180.v:3669$292_Y + end + attribute \src "ls180.v:3706.127-3706.245" + cell $or $or$ls180.v:3706$305 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable + connect \B \main_sdram_bankmachine2_cmd_buffer_lookahead_replace + connect \Y $or$ls180.v:3706$305_Y + end + attribute \src "ls180.v:3712.57-3712.157" + cell $or $or$ls180.v:3712$311 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:3712$310_Y + connect \B \main_sdram_bankmachine2_cmd_buffer_source_ready + connect \Y $or$ls180.v:3712$311_Y + end + attribute \src "ls180.v:3817.59-3817.140" + cell $or $or$ls180.v:3817$317 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_req_wdata_ready + connect \B \main_sdram_bankmachine3_req_rdata_valid + connect \Y $or$ls180.v:3817$317_Y + end + attribute \src "ls180.v:3818.44-3818.151" + cell $or $or$ls180.v:3818$318 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_source_valid + connect \B \main_sdram_bankmachine3_cmd_buffer_source_valid + connect \Y $or$ls180.v:3818$318_Y + end + attribute \src "ls180.v:3826.45-3826.170" + cell $or $or$ls180.v:3826$322 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 13 + connect \A $sshl$ls180.v:3826$321_Y + connect \B { 4'0000 \main_sdram_bankmachine3_cmd_buffer_source_payload_addr [8:0] } + connect \Y $or$ls180.v:3826$322_Y + end + attribute \src "ls180.v:3863.127-3863.245" + cell $or $or$ls180.v:3863$335 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable + connect \B \main_sdram_bankmachine3_cmd_buffer_lookahead_replace + connect \Y $or$ls180.v:3863$335_Y + end + attribute \src "ls180.v:3869.57-3869.157" + cell $or $or$ls180.v:3869$341 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:3869$340_Y + connect \B \main_sdram_bankmachine3_cmd_buffer_source_ready + connect \Y $or$ls180.v:3869$341_Y + end + attribute \src "ls180.v:3968.107-3968.193" + cell $or $or$ls180.v:3968$361 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_payload_is_write + connect \B \main_sdram_choose_req_cmd_payload_is_read + connect \Y $or$ls180.v:3968$361_Y + end + attribute \src "ls180.v:3971.39-3971.204" + cell $or $or$ls180.v:3971$367 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3971$365_Y + connect \B $and$ls180.v:3971$366_Y + connect \Y $or$ls180.v:3971$367_Y + end + attribute \src "ls180.v:3971.38-3971.289" + cell $or $or$ls180.v:3971$369 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:3971$367_Y + connect \B $and$ls180.v:3971$368_Y + connect \Y $or$ls180.v:3971$369_Y + end + attribute \src "ls180.v:3971.37-3971.374" + cell $or $or$ls180.v:3971$371 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:3971$369_Y + connect \B $and$ls180.v:3971$370_Y + connect \Y $or$ls180.v:3971$371_Y + end + attribute \src "ls180.v:3972.40-3972.207" + cell $or $or$ls180.v:3972$374 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3972$372_Y + connect \B $and$ls180.v:3972$373_Y + connect \Y $or$ls180.v:3972$374_Y + end + attribute \src "ls180.v:3972.39-3972.293" + cell $or $or$ls180.v:3972$376 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:3972$374_Y + connect \B $and$ls180.v:3972$375_Y + connect \Y $or$ls180.v:3972$376_Y + end + attribute \src "ls180.v:3972.38-3972.379" + cell $or $or$ls180.v:3972$378 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:3972$376_Y + connect \B $and$ls180.v:3972$377_Y + connect \Y $or$ls180.v:3972$378_Y + end + attribute \src "ls180.v:3985.158-3985.332" + cell $or $or$ls180.v:3985$392 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:3985$391_Y + connect \B \main_sdram_choose_cmd_want_activates + connect \Y $or$ls180.v:3985$392_Y + end + attribute \src "ls180.v:3985.75-3985.506" + cell $or $or$ls180.v:3985$397 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3985$393_Y + connect \B $and$ls180.v:3985$396_Y + connect \Y $or$ls180.v:3985$397_Y + end + attribute \src "ls180.v:3986.158-3986.332" + cell $or $or$ls180.v:3986$405 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:3986$404_Y + connect \B \main_sdram_choose_cmd_want_activates + connect \Y $or$ls180.v:3986$405_Y + end + attribute \src "ls180.v:3986.75-3986.506" + cell $or $or$ls180.v:3986$410 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3986$406_Y + connect \B $and$ls180.v:3986$409_Y + connect \Y $or$ls180.v:3986$410_Y + end + attribute \src "ls180.v:3987.158-3987.332" + cell $or $or$ls180.v:3987$418 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:3987$417_Y + connect \B \main_sdram_choose_cmd_want_activates + connect \Y $or$ls180.v:3987$418_Y + end + attribute \src "ls180.v:3987.75-3987.506" + cell $or $or$ls180.v:3987$423 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3987$419_Y + connect \B $and$ls180.v:3987$422_Y + connect \Y $or$ls180.v:3987$423_Y + end + attribute \src "ls180.v:3988.158-3988.332" + cell $or $or$ls180.v:3988$431 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:3988$430_Y + connect \B \main_sdram_choose_cmd_want_activates + connect \Y $or$ls180.v:3988$431_Y + end + attribute \src "ls180.v:3988.75-3988.506" + cell $or $or$ls180.v:3988$436 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:3988$432_Y + connect \B $and$ls180.v:3988$435_Y + connect \Y $or$ls180.v:3988$436_Y + end + attribute \src "ls180.v:4015.36-4015.104" + cell $or $or$ls180.v:4015$442 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_cmd_cmd_ready + connect \B $not$ls180.v:4015$441_Y + connect \Y $or$ls180.v:4015$442_Y + end + attribute \src "ls180.v:4018.158-4018.332" + cell $or $or$ls180.v:4018$450 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:4018$449_Y + connect \B \main_sdram_choose_req_want_activates + connect \Y $or$ls180.v:4018$450_Y + end + attribute \src "ls180.v:4018.75-4018.506" + cell $or $or$ls180.v:4018$455 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4018$451_Y + connect \B $and$ls180.v:4018$454_Y + connect \Y $or$ls180.v:4018$455_Y + end + attribute \src "ls180.v:4019.158-4019.332" + cell $or $or$ls180.v:4019$463 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:4019$462_Y + connect \B \main_sdram_choose_req_want_activates + connect \Y $or$ls180.v:4019$463_Y + end + attribute \src "ls180.v:4019.75-4019.506" + cell $or $or$ls180.v:4019$468 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4019$464_Y + connect \B $and$ls180.v:4019$467_Y + connect \Y $or$ls180.v:4019$468_Y + end + attribute \src "ls180.v:4020.158-4020.332" + cell $or $or$ls180.v:4020$476 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:4020$475_Y + connect \B \main_sdram_choose_req_want_activates + connect \Y $or$ls180.v:4020$476_Y + end + attribute \src "ls180.v:4020.75-4020.506" + cell $or $or$ls180.v:4020$481 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4020$477_Y + connect \B $and$ls180.v:4020$480_Y + connect \Y $or$ls180.v:4020$481_Y + end + attribute \src "ls180.v:4021.158-4021.332" + cell $or $or$ls180.v:4021$489 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:4021$488_Y + connect \B \main_sdram_choose_req_want_activates + connect \Y $or$ls180.v:4021$489_Y + end + attribute \src "ls180.v:4021.75-4021.506" + cell $or $or$ls180.v:4021$494 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4021$490_Y + connect \B $and$ls180.v:4021$493_Y + connect \Y $or$ls180.v:4021$494_Y + end + attribute \src "ls180.v:4084.36-4084.104" + cell $or $or$ls180.v:4084$528 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_ready + connect \B $not$ls180.v:4084$527_Y + connect \Y $or$ls180.v:4084$528_Y + end + attribute \src "ls180.v:4105.67-4105.221" + cell $or $or$ls180.v:4105$535 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:4105$534_Y + connect \B \main_sdram_ras_allowed + connect \Y $or$ls180.v:4105$535_Y + end + attribute \src "ls180.v:4113.10-4113.62" + cell $or $or$ls180.v:4113$538 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:4113$537_Y + connect \B \main_sdram_max_time1 + connect \Y $or$ls180.v:4113$538_Y + end + attribute \src "ls180.v:4143.67-4143.221" + cell $or $or$ls180.v:4143$544 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:4143$543_Y + connect \B \main_sdram_ras_allowed + connect \Y $or$ls180.v:4143$544_Y + end + attribute \src "ls180.v:4151.10-4151.61" + cell $or $or$ls180.v:4151$547 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:4151$546_Y + connect \B \main_sdram_max_time0 + connect \Y $or$ls180.v:4151$547_Y + end + attribute \src "ls180.v:4161.91-4161.180" + cell $or $or$ls180.v:4161$551 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_locked0 + connect \B $and$ls180.v:4161$550_Y + connect \Y $or$ls180.v:4161$551_Y + end + attribute \src "ls180.v:4161.90-4161.255" + cell $or $or$ls180.v:4161$554 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4161$551_Y + connect \B $and$ls180.v:4161$553_Y + connect \Y $or$ls180.v:4161$554_Y + end + attribute \src "ls180.v:4161.89-4161.330" + cell $or $or$ls180.v:4161$557 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4161$554_Y + connect \B $and$ls180.v:4161$556_Y + connect \Y $or$ls180.v:4161$557_Y + end + attribute \src "ls180.v:4166.91-4166.180" + cell $or $or$ls180.v:4166$567 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_locked1 + connect \B $and$ls180.v:4166$566_Y + connect \Y $or$ls180.v:4166$567_Y + end + attribute \src "ls180.v:4166.90-4166.255" + cell $or $or$ls180.v:4166$570 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4166$567_Y + connect \B $and$ls180.v:4166$569_Y + connect \Y $or$ls180.v:4166$570_Y + end + attribute \src "ls180.v:4166.89-4166.330" + cell $or $or$ls180.v:4166$573 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4166$570_Y + connect \B $and$ls180.v:4166$572_Y + connect \Y $or$ls180.v:4166$573_Y + end + attribute \src "ls180.v:4171.91-4171.180" + cell $or $or$ls180.v:4171$583 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_locked2 + connect \B $and$ls180.v:4171$582_Y + connect \Y $or$ls180.v:4171$583_Y + end + attribute \src "ls180.v:4171.90-4171.255" + cell $or $or$ls180.v:4171$586 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4171$583_Y + connect \B $and$ls180.v:4171$585_Y + connect \Y $or$ls180.v:4171$586_Y + end + attribute \src "ls180.v:4171.89-4171.330" + cell $or $or$ls180.v:4171$589 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4171$586_Y + connect \B $and$ls180.v:4171$588_Y + connect \Y $or$ls180.v:4171$589_Y + end + attribute \src "ls180.v:4176.91-4176.180" + cell $or $or$ls180.v:4176$599 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_locked3 + connect \B $and$ls180.v:4176$598_Y + connect \Y $or$ls180.v:4176$599_Y + end + attribute \src "ls180.v:4176.90-4176.255" + cell $or $or$ls180.v:4176$602 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4176$599_Y + connect \B $and$ls180.v:4176$601_Y + connect \Y $or$ls180.v:4176$602_Y + end + attribute \src "ls180.v:4176.89-4176.330" + cell $or $or$ls180.v:4176$605 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4176$602_Y + connect \B $and$ls180.v:4176$604_Y + connect \Y $or$ls180.v:4176$605_Y + end + attribute \src "ls180.v:4181.132-4181.221" + cell $or $or$ls180.v:4181$616 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_locked0 + connect \B $and$ls180.v:4181$615_Y + connect \Y $or$ls180.v:4181$616_Y + end + attribute \src "ls180.v:4181.131-4181.296" + cell $or $or$ls180.v:4181$619 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4181$616_Y + connect \B $and$ls180.v:4181$618_Y + connect \Y $or$ls180.v:4181$619_Y + end + attribute \src "ls180.v:4181.130-4181.371" + cell $or $or$ls180.v:4181$622 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4181$619_Y + connect \B $and$ls180.v:4181$621_Y + connect \Y $or$ls180.v:4181$622_Y + end + attribute \src "ls180.v:4181.34-4181.411" + cell $or $or$ls180.v:4181$627 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A 1'0 + connect \B $and$ls180.v:4181$626_Y + connect \Y $or$ls180.v:4181$627_Y + end + attribute \src "ls180.v:4181.506-4181.595" + cell $or $or$ls180.v:4181$632 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_locked1 + connect \B $and$ls180.v:4181$631_Y + connect \Y $or$ls180.v:4181$632_Y + end + attribute \src "ls180.v:4181.505-4181.670" + cell $or $or$ls180.v:4181$635 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4181$632_Y + connect \B $and$ls180.v:4181$634_Y + connect \Y $or$ls180.v:4181$635_Y + end + attribute \src "ls180.v:4181.504-4181.745" + cell $or $or$ls180.v:4181$638 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4181$635_Y + connect \B $and$ls180.v:4181$637_Y + connect \Y $or$ls180.v:4181$638_Y + end + attribute \src "ls180.v:4181.33-4181.785" + cell $or $or$ls180.v:4181$643 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4181$627_Y + connect \B $and$ls180.v:4181$642_Y + connect \Y $or$ls180.v:4181$643_Y + end + attribute \src "ls180.v:4181.880-4181.969" + cell $or $or$ls180.v:4181$648 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_locked2 + connect \B $and$ls180.v:4181$647_Y + connect \Y $or$ls180.v:4181$648_Y + end + attribute \src "ls180.v:4181.879-4181.1044" + cell $or $or$ls180.v:4181$651 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4181$648_Y + connect \B $and$ls180.v:4181$650_Y + connect \Y $or$ls180.v:4181$651_Y + end + attribute \src "ls180.v:4181.878-4181.1119" + cell $or $or$ls180.v:4181$654 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4181$651_Y + connect \B $and$ls180.v:4181$653_Y + connect \Y $or$ls180.v:4181$654_Y + end + attribute \src "ls180.v:4181.32-4181.1159" + cell $or $or$ls180.v:4181$659 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4181$643_Y + connect \B $and$ls180.v:4181$658_Y + connect \Y $or$ls180.v:4181$659_Y + end + attribute \src "ls180.v:4181.1254-4181.1343" + cell $or $or$ls180.v:4181$664 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_locked3 + connect \B $and$ls180.v:4181$663_Y + connect \Y $or$ls180.v:4181$664_Y + end + attribute \src "ls180.v:4181.1253-4181.1418" + cell $or $or$ls180.v:4181$667 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4181$664_Y + connect \B $and$ls180.v:4181$666_Y + connect \Y $or$ls180.v:4181$667_Y + end + attribute \src "ls180.v:4181.1252-4181.1493" + cell $or $or$ls180.v:4181$670 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4181$667_Y + connect \B $and$ls180.v:4181$669_Y + connect \Y $or$ls180.v:4181$670_Y + end + attribute \src "ls180.v:4181.31-4181.1533" + cell $or $or$ls180.v:4181$675 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4181$659_Y + connect \B $and$ls180.v:4181$674_Y + connect \Y $or$ls180.v:4181$675_Y + end + attribute \src "ls180.v:4244.10-4244.52" + cell $or $or$ls180.v:4244$684 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_litedram_wb_ack + connect \B \main_converter_skip + connect \Y $or$ls180.v:4244$684_Y + end + attribute \src "ls180.v:4271.35-4271.74" + cell $or $or$ls180.v:4271$694 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_valid + connect \B \main_cmd_consumed + connect \Y $or$ls180.v:4271$694_Y + end + attribute \src "ls180.v:4272.34-4272.73" + cell $or $or$ls180.v:4272$698 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_valid + connect \B \main_cmd_consumed + connect \Y $or$ls180.v:4272$698_Y + end + attribute \src "ls180.v:4273.48-4273.130" + cell $or $or$ls180.v:4273$704 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4273$701_Y + connect \B $and$ls180.v:4273$703_Y + connect \Y $or$ls180.v:4273$704_Y + end + attribute \src "ls180.v:4274.24-4274.87" + cell $or $or$ls180.v:4274$707 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4274$706_Y + connect \B \main_cmd_consumed + connect \Y $or$ls180.v:4274$707_Y + end + attribute \src "ls180.v:4275.26-4275.95" + cell $or $or$ls180.v:4275$709 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4275$708_Y + connect \B \main_wdata_consumed + connect \Y $or$ls180.v:4275$709_Y + end + attribute \src "ls180.v:4305.42-4305.89" + cell $or $or$ls180.v:4305$717 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_rx_clear + connect \B $and$ls180.v:4305$716_Y + connect \Y $or$ls180.v:4305$717_Y + end + attribute \src "ls180.v:4329.25-4329.174" + cell $or $or$ls180.v:4329$727 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$ls180.v:4329$725_Y + connect \B $and$ls180.v:4329$726_Y + connect \Y $or$ls180.v:4329$727_Y + end + attribute \src "ls180.v:4344.80-4344.132" + cell $or $or$ls180.v:4344$729 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:4344$728_Y + connect \B \main_uart_tx_fifo_re + connect \Y $or$ls180.v:4344$729_Y + end + attribute \src "ls180.v:4355.72-4355.135" + cell $or $or$ls180.v:4355$734 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_tx_fifo_syncfifo_writable + connect \B \main_uart_tx_fifo_replace + connect \Y $or$ls180.v:4355$734_Y + end + attribute \src "ls180.v:4374.80-4374.132" + cell $or $or$ls180.v:4374$740 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:4374$739_Y + connect \B \main_uart_rx_fifo_re + connect \Y $or$ls180.v:4374$740_Y + end + attribute \src "ls180.v:4385.72-4385.135" + cell $or $or$ls180.v:4385$745 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_uart_rx_fifo_syncfifo_writable + connect \B \main_uart_rx_fifo_replace + connect \Y $or$ls180.v:4385$745_Y + end + attribute \src "ls180.v:4530.36-4530.111" + cell $or $or$ls180.v:4530$768 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_init_pads_out_payload_clk + connect \B \main_sdphy_cmdw_pads_out_payload_clk + connect \Y $or$ls180.v:4530$768_Y + end + attribute \src "ls180.v:4530.35-4530.151" + cell $or $or$ls180.v:4530$769 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4530$768_Y + connect \B \main_sdphy_cmdr_pads_out_payload_clk + connect \Y $or$ls180.v:4530$769_Y + end + attribute \src "ls180.v:4530.34-4530.192" + cell $or $or$ls180.v:4530$770 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4530$769_Y + connect \B \main_sdphy_dataw_pads_out_payload_clk + connect \Y $or$ls180.v:4530$770_Y + end + attribute \src "ls180.v:4530.33-4530.233" + cell $or $or$ls180.v:4530$771 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4530$770_Y + connect \B \main_sdphy_datar_pads_out_payload_clk + connect \Y $or$ls180.v:4530$771_Y + end + attribute \src "ls180.v:4531.39-4531.120" + cell $or $or$ls180.v:4531$772 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_init_pads_out_payload_cmd_oe + connect \B \main_sdphy_cmdw_pads_out_payload_cmd_oe + connect \Y $or$ls180.v:4531$772_Y + end + attribute \src "ls180.v:4531.38-4531.163" + cell $or $or$ls180.v:4531$773 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4531$772_Y + connect \B \main_sdphy_cmdr_pads_out_payload_cmd_oe + connect \Y $or$ls180.v:4531$773_Y + end + attribute \src "ls180.v:4531.37-4531.207" + cell $or $or$ls180.v:4531$774 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4531$773_Y + connect \B \main_sdphy_dataw_pads_out_payload_cmd_oe + connect \Y $or$ls180.v:4531$774_Y + end + attribute \src "ls180.v:4531.36-4531.251" + cell $or $or$ls180.v:4531$775 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4531$774_Y + connect \B \main_sdphy_datar_pads_out_payload_cmd_oe + connect \Y $or$ls180.v:4531$775_Y + end + attribute \src "ls180.v:4532.38-4532.117" + cell $or $or$ls180.v:4532$776 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_init_pads_out_payload_cmd_o + connect \B \main_sdphy_cmdw_pads_out_payload_cmd_o + connect \Y $or$ls180.v:4532$776_Y + end + attribute \src "ls180.v:4532.37-4532.159" + cell $or $or$ls180.v:4532$777 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4532$776_Y + connect \B \main_sdphy_cmdr_pads_out_payload_cmd_o + connect \Y $or$ls180.v:4532$777_Y + end + attribute \src "ls180.v:4532.36-4532.202" + cell $or $or$ls180.v:4532$778 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4532$777_Y + connect \B \main_sdphy_dataw_pads_out_payload_cmd_o + connect \Y $or$ls180.v:4532$778_Y + end + attribute \src "ls180.v:4532.35-4532.245" + cell $or $or$ls180.v:4532$779 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4532$778_Y + connect \B \main_sdphy_datar_pads_out_payload_cmd_o + connect \Y $or$ls180.v:4532$779_Y + end + attribute \src "ls180.v:4533.40-4533.123" + cell $or $or$ls180.v:4533$780 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_init_pads_out_payload_data_oe + connect \B \main_sdphy_cmdw_pads_out_payload_data_oe + connect \Y $or$ls180.v:4533$780_Y + end + attribute \src "ls180.v:4533.39-4533.167" + cell $or $or$ls180.v:4533$781 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4533$780_Y + connect \B \main_sdphy_cmdr_pads_out_payload_data_oe + connect \Y $or$ls180.v:4533$781_Y + end + attribute \src "ls180.v:4533.38-4533.212" + cell $or $or$ls180.v:4533$782 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4533$781_Y + connect \B \main_sdphy_dataw_pads_out_payload_data_oe + connect \Y $or$ls180.v:4533$782_Y + end + attribute \src "ls180.v:4533.37-4533.257" + cell $or $or$ls180.v:4533$783 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:4533$782_Y + connect \B \main_sdphy_datar_pads_out_payload_data_oe + connect \Y $or$ls180.v:4533$783_Y + end + attribute \src "ls180.v:4534.39-4534.120" + cell $or $or$ls180.v:4534$784 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \main_sdphy_init_pads_out_payload_data_o + connect \B \main_sdphy_cmdw_pads_out_payload_data_o + connect \Y $or$ls180.v:4534$784_Y + end + attribute \src "ls180.v:4534.38-4534.163" + cell $or $or$ls180.v:4534$785 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A $or$ls180.v:4534$784_Y + connect \B \main_sdphy_cmdr_pads_out_payload_data_o + connect \Y $or$ls180.v:4534$785_Y + end + attribute \src "ls180.v:4534.37-4534.207" + cell $or $or$ls180.v:4534$786 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A $or$ls180.v:4534$785_Y + connect \B \main_sdphy_dataw_pads_out_payload_data_o + connect \Y $or$ls180.v:4534$786_Y + end + attribute \src "ls180.v:4534.36-4534.251" + cell $or $or$ls180.v:4534$787 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A $or$ls180.v:4534$786_Y + connect \B \main_sdphy_datar_pads_out_payload_data_o + connect \Y $or$ls180.v:4534$787_Y + end + attribute \src "ls180.v:4555.35-4555.80" + cell $or $or$ls180.v:4555$788 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_stop + connect \B \main_sdphy_datar_stop + connect \Y $or$ls180.v:4555$788_Y + end + attribute \src "ls180.v:4709.91-4709.144" + cell $or $or$ls180.v:4709$802 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_cmdr_start + connect \B \main_sdphy_cmdr_cmdr_run + connect \Y $or$ls180.v:4709$802_Y + end + attribute \src "ls180.v:4726.53-4726.143" + cell $or $or$ls180.v:4726$805 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:4726$804_Y + connect \B \main_sdphy_cmdr_cmdr_converter_source_ready + connect \Y $or$ls180.v:4726$805_Y + end + attribute \src "ls180.v:4729.47-4729.127" + cell $or $or$ls180.v:4729$808 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:4729$807_Y + connect \B \main_sdphy_cmdr_cmdr_buf_source_ready + connect \Y $or$ls180.v:4729$808_Y + end + attribute \src "ls180.v:4853.54-4853.146" + cell $or $or$ls180.v:4853$826 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:4853$825_Y + connect \B \main_sdphy_dataw_crcr_converter_source_ready + connect \Y $or$ls180.v:4853$826_Y + end + attribute \src "ls180.v:4856.48-4856.130" + cell $or $or$ls180.v:4856$829 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:4856$828_Y + connect \B \main_sdphy_dataw_crcr_buf_source_ready + connect \Y $or$ls180.v:4856$829_Y + end + attribute \src "ls180.v:4987.55-4987.149" + cell $or $or$ls180.v:4987$841 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:4987$840_Y + connect \B \main_sdphy_datar_datar_converter_source_ready + connect \Y $or$ls180.v:4987$841_Y + end + attribute \src "ls180.v:4990.49-4990.133" + cell $or $or$ls180.v:4990$844 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:4990$843_Y + connect \B \main_sdphy_datar_datar_buf_source_ready + connect \Y $or$ls180.v:4990$844_Y + end + attribute \src "ls180.v:5619.80-5619.151" + cell $or $or$ls180.v:5619$1139 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_fifo_syncfifo_writable + connect \B \main_sdblock2mem_fifo_replace + connect \Y $or$ls180.v:5619$1139_Y + end + attribute \src "ls180.v:5630.49-5630.131" + cell $or $or$ls180.v:5630$1145 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:5630$1144_Y + connect \B \main_sdblock2mem_converter_source_ready + connect \Y $or$ls180.v:5630$1145_Y + end + attribute \src "ls180.v:5839.80-5839.151" + cell $or $or$ls180.v:5839$1170 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdmem2block_fifo_syncfifo_writable + connect \B \main_sdmem2block_fifo_replace + connect \Y $or$ls180.v:5839$1170_Y + end + attribute \src "ls180.v:6026.41-6026.99" + cell $or $or$ls180.v:6026$1226 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_ram_bus_err + connect \B \main_interface0_ram_bus_err + connect \Y $or$ls180.v:6026$1226_Y + end + attribute \src "ls180.v:6026.40-6026.130" + cell $or $or$ls180.v:6026$1227 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:6026$1226_Y + connect \B \main_interface1_ram_bus_err + connect \Y $or$ls180.v:6026$1227_Y + end + attribute \src "ls180.v:6026.39-6026.161" + cell $or $or$ls180.v:6026$1228 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:6026$1227_Y + connect \B \main_interface2_ram_bus_err + connect \Y $or$ls180.v:6026$1228_Y + end + attribute \src "ls180.v:6026.38-6026.192" + cell $or $or$ls180.v:6026$1229 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:6026$1228_Y + connect \B \main_interface3_ram_bus_err + connect \Y $or$ls180.v:6026$1229_Y + end + attribute \src "ls180.v:6026.37-6026.235" + cell $or $or$ls180.v:6026$1230 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:6026$1229_Y + connect \B \main_interface0_converted_interface_err + connect \Y $or$ls180.v:6026$1230_Y + end + attribute \src "ls180.v:6026.36-6026.278" + cell $or $or$ls180.v:6026$1231 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:6026$1230_Y + connect \B \main_interface1_converted_interface_err + connect \Y $or$ls180.v:6026$1231_Y + end + attribute \src "ls180.v:6026.35-6026.322" + cell $or $or$ls180.v:6026$1232 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:6026$1231_Y + connect \B \main_libresocsim_libresoc_interface0_err + connect \Y $or$ls180.v:6026$1232_Y + end + attribute \src "ls180.v:6026.34-6026.366" + cell $or $or$ls180.v:6026$1233 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:6026$1232_Y + connect \B \main_libresocsim_libresoc_interface1_err + connect \Y $or$ls180.v:6026$1233_Y + end + attribute \src "ls180.v:6026.33-6026.410" + cell $or $or$ls180.v:6026$1234 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:6026$1233_Y + connect \B \main_libresocsim_libresoc_interface2_err + connect \Y $or$ls180.v:6026$1234_Y + end + attribute \src "ls180.v:6026.32-6026.454" + cell $or $or$ls180.v:6026$1235 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:6026$1234_Y + connect \B \main_libresocsim_libresoc_interface3_err + connect \Y $or$ls180.v:6026$1235_Y + end + attribute \src "ls180.v:6026.31-6026.500" + cell $or $or$ls180.v:6026$1236 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:6026$1235_Y + connect \B \main_socbushandler_converted_interface_err + connect \Y $or$ls180.v:6026$1236_Y + end + attribute \src "ls180.v:6026.30-6026.547" + cell $or $or$ls180.v:6026$1237 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:6026$1236_Y + connect \B \builder_libresocsim_converted_interface_err + connect \Y $or$ls180.v:6026$1237_Y + end + attribute \src "ls180.v:6032.36-6032.94" + cell $or $or$ls180.v:6032$1242 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_ram_bus_ack + connect \B \main_interface0_ram_bus_ack + connect \Y $or$ls180.v:6032$1242_Y + end + attribute \src "ls180.v:6032.35-6032.125" + cell $or $or$ls180.v:6032$1243 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:6032$1242_Y + connect \B \main_interface1_ram_bus_ack + connect \Y $or$ls180.v:6032$1243_Y + end + attribute \src "ls180.v:6032.34-6032.156" + cell $or $or$ls180.v:6032$1244 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:6032$1243_Y + connect \B \main_interface2_ram_bus_ack + connect \Y $or$ls180.v:6032$1244_Y + end + attribute \src "ls180.v:6032.33-6032.187" + cell $or $or$ls180.v:6032$1245 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:6032$1244_Y + connect \B \main_interface3_ram_bus_ack + connect \Y $or$ls180.v:6032$1245_Y + end + attribute \src "ls180.v:6032.32-6032.230" + cell $or $or$ls180.v:6032$1246 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:6032$1245_Y + connect \B \main_interface0_converted_interface_ack + connect \Y $or$ls180.v:6032$1246_Y + end + attribute \src "ls180.v:6032.31-6032.273" + cell $or $or$ls180.v:6032$1247 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:6032$1246_Y + connect \B \main_interface1_converted_interface_ack + connect \Y $or$ls180.v:6032$1247_Y + end + attribute \src "ls180.v:6032.30-6032.317" + cell $or $or$ls180.v:6032$1248 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:6032$1247_Y + connect \B \main_libresocsim_libresoc_interface0_ack + connect \Y $or$ls180.v:6032$1248_Y + end + attribute \src "ls180.v:6032.29-6032.361" + cell $or $or$ls180.v:6032$1249 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:6032$1248_Y + connect \B \main_libresocsim_libresoc_interface1_ack + connect \Y $or$ls180.v:6032$1249_Y + end + attribute \src "ls180.v:6032.28-6032.405" + cell $or $or$ls180.v:6032$1250 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:6032$1249_Y + connect \B \main_libresocsim_libresoc_interface2_ack + connect \Y $or$ls180.v:6032$1250_Y + end + attribute \src "ls180.v:6032.27-6032.449" + cell $or $or$ls180.v:6032$1251 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:6032$1250_Y + connect \B \main_libresocsim_libresoc_interface3_ack + connect \Y $or$ls180.v:6032$1251_Y + end + attribute \src "ls180.v:6032.26-6032.495" + cell $or $or$ls180.v:6032$1252 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:6032$1251_Y + connect \B \main_socbushandler_converted_interface_ack + connect \Y $or$ls180.v:6032$1252_Y + end + attribute \src "ls180.v:6032.25-6032.542" + cell $or $or$ls180.v:6032$1253 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:6032$1252_Y + connect \B \builder_libresocsim_converted_interface_ack + connect \Y $or$ls180.v:6032$1253_Y + end + attribute \src "ls180.v:6033.38-6033.166" + cell $or $or$ls180.v:6033$1256 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $and$ls180.v:6033$1254_Y + connect \B $and$ls180.v:6033$1255_Y + connect \Y $or$ls180.v:6033$1256_Y + end + attribute \src "ls180.v:6033.37-6033.232" + cell $or $or$ls180.v:6033$1258 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $or$ls180.v:6033$1256_Y + connect \B $and$ls180.v:6033$1257_Y + connect \Y $or$ls180.v:6033$1258_Y + end + attribute \src "ls180.v:6033.36-6033.298" + cell $or $or$ls180.v:6033$1260 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $or$ls180.v:6033$1258_Y + connect \B $and$ls180.v:6033$1259_Y + connect \Y $or$ls180.v:6033$1260_Y + end + attribute \src "ls180.v:6033.35-6033.364" + cell $or $or$ls180.v:6033$1262 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $or$ls180.v:6033$1260_Y + connect \B $and$ls180.v:6033$1261_Y + connect \Y $or$ls180.v:6033$1262_Y + end + attribute \src "ls180.v:6033.34-6033.442" + cell $or $or$ls180.v:6033$1264 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $or$ls180.v:6033$1262_Y + connect \B $and$ls180.v:6033$1263_Y + connect \Y $or$ls180.v:6033$1264_Y + end + attribute \src "ls180.v:6033.33-6033.520" + cell $or $or$ls180.v:6033$1266 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $or$ls180.v:6033$1264_Y + connect \B $and$ls180.v:6033$1265_Y + connect \Y $or$ls180.v:6033$1266_Y + end + attribute \src "ls180.v:6033.32-6033.599" + cell $or $or$ls180.v:6033$1268 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $or$ls180.v:6033$1266_Y + connect \B $and$ls180.v:6033$1267_Y + connect \Y $or$ls180.v:6033$1268_Y + end + attribute \src "ls180.v:6033.31-6033.678" + cell $or $or$ls180.v:6033$1270 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $or$ls180.v:6033$1268_Y + connect \B $and$ls180.v:6033$1269_Y + connect \Y $or$ls180.v:6033$1270_Y + end + attribute \src "ls180.v:6033.30-6033.757" + cell $or $or$ls180.v:6033$1272 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $or$ls180.v:6033$1270_Y + connect \B $and$ls180.v:6033$1271_Y + connect \Y $or$ls180.v:6033$1272_Y + end + attribute \src "ls180.v:6033.29-6033.837" + cell $or $or$ls180.v:6033$1274 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $or$ls180.v:6033$1272_Y + connect \B $and$ls180.v:6033$1273_Y + connect \Y $or$ls180.v:6033$1274_Y + end + attribute \src "ls180.v:6033.28-6033.919" + cell $or $or$ls180.v:6033$1276 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $or$ls180.v:6033$1274_Y + connect \B $and$ls180.v:6033$1275_Y + connect \Y $or$ls180.v:6033$1276_Y + end + attribute \src "ls180.v:6033.27-6033.1002" + cell $or $or$ls180.v:6033$1278 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $or$ls180.v:6033$1276_Y + connect \B $and$ls180.v:6033$1277_Y + connect \Y $or$ls180.v:6033$1278_Y + end + attribute \src "ls180.v:6787.55-6787.124" + cell $or $or$ls180.v:6787$2424 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A \builder_interface0_bank_bus_dat_r + connect \B \builder_interface1_bank_bus_dat_r + connect \Y $or$ls180.v:6787$2424_Y + end + attribute \src "ls180.v:6787.54-6787.161" + cell $or $or$ls180.v:6787$2425 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $or$ls180.v:6787$2424_Y + connect \B \builder_interface2_bank_bus_dat_r + connect \Y $or$ls180.v:6787$2425_Y + end + attribute \src "ls180.v:6787.53-6787.198" + cell $or $or$ls180.v:6787$2426 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $or$ls180.v:6787$2425_Y + connect \B \builder_interface3_bank_bus_dat_r + connect \Y $or$ls180.v:6787$2426_Y + end + attribute \src "ls180.v:6787.52-6787.235" + cell $or $or$ls180.v:6787$2427 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $or$ls180.v:6787$2426_Y + connect \B \builder_interface4_bank_bus_dat_r + connect \Y $or$ls180.v:6787$2427_Y + end + attribute \src "ls180.v:6787.51-6787.272" + cell $or $or$ls180.v:6787$2428 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $or$ls180.v:6787$2427_Y + connect \B \builder_interface5_bank_bus_dat_r + connect \Y $or$ls180.v:6787$2428_Y + end + attribute \src "ls180.v:6787.50-6787.309" + cell $or $or$ls180.v:6787$2429 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $or$ls180.v:6787$2428_Y + connect \B \builder_interface6_bank_bus_dat_r + connect \Y $or$ls180.v:6787$2429_Y + end + attribute \src "ls180.v:6787.49-6787.346" + cell $or $or$ls180.v:6787$2430 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $or$ls180.v:6787$2429_Y + connect \B \builder_interface7_bank_bus_dat_r + connect \Y $or$ls180.v:6787$2430_Y + end + attribute \src "ls180.v:6787.48-6787.383" + cell $or $or$ls180.v:6787$2431 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $or$ls180.v:6787$2430_Y + connect \B \builder_interface8_bank_bus_dat_r + connect \Y $or$ls180.v:6787$2431_Y + end + attribute \src "ls180.v:6787.47-6787.420" + cell $or $or$ls180.v:6787$2432 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $or$ls180.v:6787$2431_Y + connect \B \builder_interface9_bank_bus_dat_r + connect \Y $or$ls180.v:6787$2432_Y + end + attribute \src "ls180.v:6787.46-6787.458" + cell $or $or$ls180.v:6787$2433 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $or$ls180.v:6787$2432_Y + connect \B \builder_interface10_bank_bus_dat_r + connect \Y $or$ls180.v:6787$2433_Y + end + attribute \src "ls180.v:6787.45-6787.496" + cell $or $or$ls180.v:6787$2434 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $or$ls180.v:6787$2433_Y + connect \B \builder_interface11_bank_bus_dat_r + connect \Y $or$ls180.v:6787$2434_Y + end + attribute \src "ls180.v:6787.44-6787.534" + cell $or $or$ls180.v:6787$2435 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $or$ls180.v:6787$2434_Y + connect \B \builder_interface12_bank_bus_dat_r + connect \Y $or$ls180.v:6787$2435_Y + end + attribute \src "ls180.v:6787.43-6787.572" + cell $or $or$ls180.v:6787$2436 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $or$ls180.v:6787$2435_Y + connect \B \builder_interface13_bank_bus_dat_r + connect \Y $or$ls180.v:6787$2436_Y + end + attribute \src "ls180.v:6787.42-6787.610" + cell $or $or$ls180.v:6787$2437 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $or$ls180.v:6787$2436_Y + connect \B \builder_interface14_bank_bus_dat_r + connect \Y $or$ls180.v:6787$2437_Y + end + attribute \src "ls180.v:7114.90-7114.179" + cell $or $or$ls180.v:7114$2462 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_locked0 + connect \B $and$ls180.v:7114$2461_Y + connect \Y $or$ls180.v:7114$2462_Y + end + attribute \src "ls180.v:7114.89-7114.254" + cell $or $or$ls180.v:7114$2465 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:7114$2462_Y + connect \B $and$ls180.v:7114$2464_Y + connect \Y $or$ls180.v:7114$2465_Y + end + attribute \src "ls180.v:7114.88-7114.329" + cell $or $or$ls180.v:7114$2468 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:7114$2465_Y + connect \B $and$ls180.v:7114$2467_Y + connect \Y $or$ls180.v:7114$2468_Y + end + attribute \src "ls180.v:7138.90-7138.179" + cell $or $or$ls180.v:7138$2478 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_locked1 + connect \B $and$ls180.v:7138$2477_Y + connect \Y $or$ls180.v:7138$2478_Y + end + attribute \src "ls180.v:7138.89-7138.254" + cell $or $or$ls180.v:7138$2481 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:7138$2478_Y + connect \B $and$ls180.v:7138$2480_Y + connect \Y $or$ls180.v:7138$2481_Y + end + attribute \src "ls180.v:7138.88-7138.329" + cell $or $or$ls180.v:7138$2484 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:7138$2481_Y + connect \B $and$ls180.v:7138$2483_Y + connect \Y $or$ls180.v:7138$2484_Y + end + attribute \src "ls180.v:7162.90-7162.179" + cell $or $or$ls180.v:7162$2494 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_locked2 + connect \B $and$ls180.v:7162$2493_Y + connect \Y $or$ls180.v:7162$2494_Y + end + attribute \src "ls180.v:7162.89-7162.254" + cell $or $or$ls180.v:7162$2497 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:7162$2494_Y + connect \B $and$ls180.v:7162$2496_Y + connect \Y $or$ls180.v:7162$2497_Y + end + attribute \src "ls180.v:7162.88-7162.329" + cell $or $or$ls180.v:7162$2500 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:7162$2497_Y + connect \B $and$ls180.v:7162$2499_Y + connect \Y $or$ls180.v:7162$2500_Y + end + attribute \src "ls180.v:7186.90-7186.179" + cell $or $or$ls180.v:7186$2510 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_locked3 + connect \B $and$ls180.v:7186$2509_Y + connect \Y $or$ls180.v:7186$2510_Y + end + attribute \src "ls180.v:7186.89-7186.254" + cell $or $or$ls180.v:7186$2513 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:7186$2510_Y + connect \B $and$ls180.v:7186$2512_Y + connect \Y $or$ls180.v:7186$2513_Y + end + attribute \src "ls180.v:7186.88-7186.329" + cell $or $or$ls180.v:7186$2516 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:7186$2513_Y + connect \B $and$ls180.v:7186$2515_Y + connect \Y $or$ls180.v:7186$2516_Y + end + attribute \src "ls180.v:7703.20-7703.71" + cell $or $or$ls180.v:7703$2574 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [0] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7703$2574_Y + end + attribute \src "ls180.v:7704.20-7704.71" + cell $or $or$ls180.v:7704$2575 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [1] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7704$2575_Y + end + attribute \src "ls180.v:7705.20-7705.71" + cell $or $or$ls180.v:7705$2576 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [2] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7705$2576_Y + end + attribute \src "ls180.v:7706.20-7706.71" + cell $or $or$ls180.v:7706$2577 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [3] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7706$2577_Y + end + attribute \src "ls180.v:7707.20-7707.71" + cell $or $or$ls180.v:7707$2578 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [4] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7707$2578_Y + end + attribute \src "ls180.v:7708.20-7708.71" + cell $or $or$ls180.v:7708$2579 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [5] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7708$2579_Y + end + attribute \src "ls180.v:7709.20-7709.71" + cell $or $or$ls180.v:7709$2580 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [6] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7709$2580_Y + end + attribute \src "ls180.v:7710.20-7710.71" + cell $or $or$ls180.v:7710$2581 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [7] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7710$2581_Y + end + attribute \src "ls180.v:7711.20-7711.71" + cell $or $or$ls180.v:7711$2582 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [8] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7711$2582_Y + end + attribute \src "ls180.v:7712.20-7712.71" + cell $or $or$ls180.v:7712$2583 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [9] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7712$2583_Y + end + attribute \src "ls180.v:7713.21-7713.73" + cell $or $or$ls180.v:7713$2584 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [10] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7713$2584_Y + end + attribute \src "ls180.v:7714.21-7714.73" + cell $or $or$ls180.v:7714$2585 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [11] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7714$2585_Y + end + attribute \src "ls180.v:7715.21-7715.73" + cell $or $or$ls180.v:7715$2586 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [12] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7715$2586_Y + end + attribute \src "ls180.v:7716.21-7716.73" + cell $or $or$ls180.v:7716$2587 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [13] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7716$2587_Y + end + attribute \src "ls180.v:7717.21-7717.73" + cell $or $or$ls180.v:7717$2588 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [14] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7717$2588_Y + end + attribute \src "ls180.v:7718.21-7718.73" + cell $or $or$ls180.v:7718$2589 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [15] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7718$2589_Y + end + attribute \src "ls180.v:7719.21-7719.73" + cell $or $or$ls180.v:7719$2590 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [16] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7719$2590_Y + end + attribute \src "ls180.v:7720.21-7720.73" + cell $or $or$ls180.v:7720$2591 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [17] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7720$2591_Y + end + attribute \src "ls180.v:7721.21-7721.73" + cell $or $or$ls180.v:7721$2592 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [18] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7721$2592_Y + end + attribute \src "ls180.v:7722.21-7722.73" + cell $or $or$ls180.v:7722$2593 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [19] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7722$2593_Y + end + attribute \src "ls180.v:7723.21-7723.73" + cell $or $or$ls180.v:7723$2594 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [20] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7723$2594_Y + end + attribute \src "ls180.v:7724.21-7724.73" + cell $or $or$ls180.v:7724$2595 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [21] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7724$2595_Y + end + attribute \src "ls180.v:7725.21-7725.73" + cell $or $or$ls180.v:7725$2596 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [22] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7725$2596_Y + end + attribute \src "ls180.v:7726.21-7726.73" + cell $or $or$ls180.v:7726$2597 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_nc [23] + connect \B \main_libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:7726$2597_Y + end + attribute \src "ls180.v:7727.7-7727.68" + cell $or $or$ls180.v:7727$2598 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_libresoc_xics_icp_ack + connect \B \main_converter0_skip + connect \Y $or$ls180.v:7727$2598_Y + end + attribute \src "ls180.v:7738.7-7738.68" + cell $or $or$ls180.v:7738$2599 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_libresoc_xics_ics_ack + connect \B \main_converter1_skip + connect \Y $or$ls180.v:7738$2599_Y + end + attribute \src "ls180.v:7749.7-7749.50" + cell $or $or$ls180.v:7749$2600 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_wb_sdram_ack + connect \B \main_socbushandler_skip + connect \Y $or$ls180.v:7749$2600_Y + end + attribute \src "ls180.v:7894.7-7894.107" + cell $or $or$ls180.v:7894$2648 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:7894$2647_Y + connect \B \main_sdram_bankmachine0_cmd_buffer_source_ready + connect \Y $or$ls180.v:7894$2648_Y + end + attribute \src "ls180.v:7940.7-7940.107" + cell $or $or$ls180.v:7940$2664 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:7940$2663_Y + connect \B \main_sdram_bankmachine1_cmd_buffer_source_ready + connect \Y $or$ls180.v:7940$2664_Y + end + attribute \src "ls180.v:7986.7-7986.107" + cell $or $or$ls180.v:7986$2680 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:7986$2679_Y + connect \B \main_sdram_bankmachine2_cmd_buffer_source_ready + connect \Y $or$ls180.v:7986$2680_Y + end + attribute \src "ls180.v:8032.7-8032.107" + cell $or $or$ls180.v:8032$2696 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:8032$2695_Y + connect \B \main_sdram_bankmachine3_cmd_buffer_source_ready + connect \Y $or$ls180.v:8032$2696_Y + end + attribute \src "ls180.v:8220.40-8220.125" + cell $or $or$ls180.v:8220$2717 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A 1'0 + connect \B $and$ls180.v:8220$2716_Y + connect \Y $or$ls180.v:8220$2717_Y + end + attribute \src "ls180.v:8220.39-8220.207" + cell $or $or$ls180.v:8220$2720 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:8220$2717_Y + connect \B $and$ls180.v:8220$2719_Y + connect \Y $or$ls180.v:8220$2720_Y + end + attribute \src "ls180.v:8220.38-8220.289" + cell $or $or$ls180.v:8220$2723 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:8220$2720_Y + connect \B $and$ls180.v:8220$2722_Y + connect \Y $or$ls180.v:8220$2723_Y + end + attribute \src "ls180.v:8220.37-8220.371" + cell $or $or$ls180.v:8220$2726 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:8220$2723_Y + connect \B $and$ls180.v:8220$2725_Y + connect \Y $or$ls180.v:8220$2726_Y + end + attribute \src "ls180.v:8221.41-8221.126" + cell $or $or$ls180.v:8221$2729 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A 1'0 + connect \B $and$ls180.v:8221$2728_Y + connect \Y $or$ls180.v:8221$2729_Y + end + attribute \src "ls180.v:8221.40-8221.208" + cell $or $or$ls180.v:8221$2732 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:8221$2729_Y + connect \B $and$ls180.v:8221$2731_Y + connect \Y $or$ls180.v:8221$2732_Y + end + attribute \src "ls180.v:8221.39-8221.290" + cell $or $or$ls180.v:8221$2735 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:8221$2732_Y + connect \B $and$ls180.v:8221$2734_Y + connect \Y $or$ls180.v:8221$2735_Y + end + attribute \src "ls180.v:8221.38-8221.372" + cell $or $or$ls180.v:8221$2738 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$ls180.v:8221$2735_Y + connect \B $and$ls180.v:8221$2737_Y + connect \Y $or$ls180.v:8221$2738_Y + end + attribute \src "ls180.v:8225.7-8225.49" + cell $or $or$ls180.v:8225$2739 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_litedram_wb_ack + connect \B \main_converter_skip + connect \Y $or$ls180.v:8225$2739_Y + end + attribute \src "ls180.v:8388.21-8388.74" + cell $or $or$ls180.v:8388$2787 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:8388$2785_Y + connect \B $not$ls180.v:8388$2786_Y + connect \Y $or$ls180.v:8388$2787_Y + end + attribute \src "ls180.v:8423.21-8423.71" + cell $or $or$ls180.v:8423$2792 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:8423$2790_Y + connect \B $not$ls180.v:8423$2791_Y + connect \Y $or$ls180.v:8423$2792_Y + end + attribute \src "ls180.v:8491.32-8491.85" + cell $or $or$ls180.v:8491$2804 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_cmdr_start + connect \B \main_sdphy_cmdr_cmdr_run + connect \Y $or$ls180.v:8491$2804_Y + end + attribute \src "ls180.v:8497.8-8497.97" + cell $or $or$ls180.v:8497$2806 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:8497$2805_Y + connect \B \main_sdphy_cmdr_cmdr_converter_sink_last + connect \Y $or$ls180.v:8497$2806_Y + end + attribute \src "ls180.v:8514.52-8514.139" + cell $or $or$ls180.v:8514$2811 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_cmdr_converter_sink_first + connect \B \main_sdphy_cmdr_cmdr_converter_source_first + connect \Y $or$ls180.v:8514$2811_Y + end + attribute \src "ls180.v:8515.51-8515.136" + cell $or $or$ls180.v:8515$2812 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_cmdr_cmdr_converter_sink_last + connect \B \main_sdphy_cmdr_cmdr_converter_source_last + connect \Y $or$ls180.v:8515$2812_Y + end + attribute \src "ls180.v:8549.7-8549.87" + cell $or $or$ls180.v:8549$2815 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:8549$2814_Y + connect \B \main_sdphy_cmdr_cmdr_buf_source_ready + connect \Y $or$ls180.v:8549$2815_Y + end + attribute \src "ls180.v:8572.33-8572.88" + cell $or $or$ls180.v:8572$2816 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_crcr_start + connect \B \main_sdphy_dataw_crcr_run + connect \Y $or$ls180.v:8572$2816_Y + end + attribute \src "ls180.v:8578.8-8578.99" + cell $or $or$ls180.v:8578$2818 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:8578$2817_Y + connect \B \main_sdphy_dataw_crcr_converter_sink_last + connect \Y $or$ls180.v:8578$2818_Y + end + attribute \src "ls180.v:8595.53-8595.142" + cell $or $or$ls180.v:8595$2823 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_crcr_converter_sink_first + connect \B \main_sdphy_dataw_crcr_converter_source_first + connect \Y $or$ls180.v:8595$2823_Y + end + attribute \src "ls180.v:8596.52-8596.139" + cell $or $or$ls180.v:8596$2824 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_dataw_crcr_converter_sink_last + connect \B \main_sdphy_dataw_crcr_converter_source_last + connect \Y $or$ls180.v:8596$2824_Y + end + attribute \src "ls180.v:8630.7-8630.89" + cell $or $or$ls180.v:8630$2827 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:8630$2826_Y + connect \B \main_sdphy_dataw_crcr_buf_source_ready + connect \Y $or$ls180.v:8630$2827_Y + end + attribute \src "ls180.v:8651.34-8651.91" + cell $or $or$ls180.v:8651$2828 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_datar_start + connect \B \main_sdphy_datar_datar_run + connect \Y $or$ls180.v:8651$2828_Y + end + attribute \src "ls180.v:8657.8-8657.101" + cell $or $or$ls180.v:8657$2830 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:8657$2829_Y + connect \B \main_sdphy_datar_datar_converter_sink_last + connect \Y $or$ls180.v:8657$2830_Y + end + attribute \src "ls180.v:8674.54-8674.145" + cell $or $or$ls180.v:8674$2835 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_datar_converter_sink_first + connect \B \main_sdphy_datar_datar_converter_source_first + connect \Y $or$ls180.v:8674$2835_Y + end + attribute \src "ls180.v:8675.53-8675.142" + cell $or $or$ls180.v:8675$2836 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdphy_datar_datar_converter_sink_last + connect \B \main_sdphy_datar_datar_converter_source_last + connect \Y $or$ls180.v:8675$2836_Y + end + attribute \src "ls180.v:8691.7-8691.91" + cell $or $or$ls180.v:8691$2839 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$ls180.v:8691$2838_Y + connect \B \main_sdphy_datar_datar_buf_source_ready + connect \Y $or$ls180.v:8691$2839_Y + end + attribute \src "ls180.v:8880.8-8880.89" + cell $or $or$ls180.v:8880$2863 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$ls180.v:8880$2862_Y + connect \B \main_sdblock2mem_converter_sink_last + connect \Y $or$ls180.v:8880$2863_Y + end + attribute \src "ls180.v:8897.48-8897.127" + cell $or $or$ls180.v:8897$2868 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_converter_sink_first + connect \B \main_sdblock2mem_converter_source_first + connect \Y $or$ls180.v:8897$2868_Y + end + attribute \src "ls180.v:8898.47-8898.124" + cell $or $or$ls180.v:8898$2869 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdblock2mem_converter_sink_last + connect \B \main_sdblock2mem_converter_source_last + connect \Y $or$ls180.v:8898$2869_Y + end + attribute \src "ls180.v:3355.46-3355.94" + cell $sshl $sshl$ls180.v:3355$231 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 13 + connect \A \main_sdram_bankmachine0_auto_precharge + connect \B 4'1010 + connect \Y $sshl$ls180.v:3355$231_Y + end + attribute \src "ls180.v:3512.46-3512.94" + cell $sshl $sshl$ls180.v:3512$261 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 13 + connect \A \main_sdram_bankmachine1_auto_precharge + connect \B 4'1010 + connect \Y $sshl$ls180.v:3512$261_Y + end + attribute \src "ls180.v:3669.46-3669.94" + cell $sshl $sshl$ls180.v:3669$291 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 13 + connect \A \main_sdram_bankmachine2_auto_precharge + connect \B 4'1010 + connect \Y $sshl$ls180.v:3669$291_Y + end + attribute \src "ls180.v:3826.46-3826.94" + cell $sshl $sshl$ls180.v:3826$321 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 13 + connect \A \main_sdram_bankmachine3_auto_precharge + connect \B 4'1010 + connect \Y $sshl$ls180.v:3826$321_Y + end + attribute \src "ls180.v:3386.63-3386.122" + cell $sub $sub$ls180.v:3386$244 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_produce + connect \B 1'1 + connect \Y $sub$ls180.v:3386$244_Y + end + attribute \src "ls180.v:3543.63-3543.122" + cell $sub $sub$ls180.v:3543$274 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_produce + connect \B 1'1 + connect \Y $sub$ls180.v:3543$274_Y + end + attribute \src "ls180.v:3700.63-3700.122" + cell $sub $sub$ls180.v:3700$304 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_produce + connect \B 1'1 + connect \Y $sub$ls180.v:3700$304_Y + end + attribute \src "ls180.v:3857.63-3857.122" + cell $sub $sub$ls180.v:3857$334 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_produce + connect \B 1'1 + connect \Y $sub$ls180.v:3857$334_Y + end + attribute \src "ls180.v:4263.38-4263.75" + cell $sub $sub$ls180.v:4263$688 + parameter \A_SIGNED 0 + parameter \A_WIDTH 30 + parameter \B_SIGNED 0 + parameter \B_WIDTH 31 + parameter \Y_WIDTH 31 + connect \A \main_litedram_wb_adr + connect \B 31'1001000000000000000000000000000 + connect \Y $sub$ls180.v:4263$688_Y + end + attribute \src "ls180.v:4349.36-4349.68" + cell $sub $sub$ls180.v:4349$733 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_uart_tx_fifo_produce + connect \B 1'1 + connect \Y $sub$ls180.v:4349$733_Y + end + attribute \src "ls180.v:4379.36-4379.68" + cell $sub $sub$ls180.v:4379$744 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_uart_rx_fifo_produce + connect \B 1'1 + connect \Y $sub$ls180.v:4379$744_Y + end + attribute \src "ls180.v:4415.70-4415.110" + cell $sub $sub$ls180.v:4415$752 + parameter \A_SIGNED 0 + parameter \A_WIDTH 15 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 16 + connect \A \main_spimaster8_clk_divider [15:1] + connect \B 1'1 + connect \Y $sub$ls180.v:4415$752_Y + end + attribute \src "ls180.v:4416.70-4416.104" + cell $sub $sub$ls180.v:4416$754 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 16 + connect \A \main_spimaster8_clk_divider + connect \B 1'1 + connect \Y $sub$ls180.v:4416$754_Y + end + attribute \src "ls180.v:4443.37-4443.66" + cell $sub $sub$ls180.v:4443$758 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 8 + connect \A \main_spimaster1_length + connect \B 1'1 + connect \Y $sub$ls180.v:4443$758_Y + end + attribute \src "ls180.v:4473.67-4473.107" + cell $sub $sub$ls180.v:4473$760 + parameter \A_SIGNED 0 + parameter \A_WIDTH 15 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 16 + connect \A \main_spisdcard_clk_divider0 [15:1] + connect \B 1'1 + connect \Y $sub$ls180.v:4473$760_Y + end + attribute \src "ls180.v:4474.67-4474.101" + cell $sub $sub$ls180.v:4474$762 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 16 + connect \A \main_spisdcard_clk_divider0 + connect \B 1'1 + connect \Y $sub$ls180.v:4474$762_Y + end + attribute \src "ls180.v:4502.35-4502.64" + cell $sub $sub$ls180.v:4502$766 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 8 + connect \A \main_spisdcard_length0 + connect \B 1'1 + connect \Y $sub$ls180.v:4502$766_Y + end + attribute \src "ls180.v:4756.60-4756.90" + cell $sub $sub$ls180.v:4756$810 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_sdphy_cmdr_timeout + connect \B 1'1 + connect \Y $sub$ls180.v:4756$810_Y + end + attribute \src "ls180.v:4767.62-4767.104" + cell $sub $sub$ls180.v:4767$812 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 8 + connect \A \main_sdphy_cmdr_sink_payload_length + connect \B 1'1 + connect \Y $sub$ls180.v:4767$812_Y + end + attribute \src "ls180.v:4784.60-4784.90" + cell $sub $sub$ls180.v:4784$816 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_sdphy_cmdr_timeout + connect \B 1'1 + connect \Y $sub$ls180.v:4784$816_Y + end + attribute \src "ls180.v:5013.62-5013.93" + cell $sub $sub$ls180.v:5013$846 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_sdphy_datar_timeout + connect \B 1'1 + connect \Y $sub$ls180.v:5013$846_Y + end + attribute \src "ls180.v:5018.62-5018.93" + cell $sub $sub$ls180.v:5018$847 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_sdphy_datar_timeout + connect \B 1'1 + connect \Y $sub$ls180.v:5018$847_Y + end + attribute \src "ls180.v:5029.64-5029.122" + cell $sub $sub$ls180.v:5029$850 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 10 + connect \A $add$ls180.v:5029$849_Y + connect \B 1'1 + connect \Y $sub$ls180.v:5029$850_Y + end + attribute \src "ls180.v:5050.62-5050.93" + cell $sub $sub$ls180.v:5050$853 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_sdphy_datar_timeout + connect \B 1'1 + connect \Y $sub$ls180.v:5050$853_Y + end + attribute \src "ls180.v:5512.37-5512.75" + cell $sub $sub$ls180.v:5512$1126 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_sdcore_block_count_storage + connect \B 1'1 + connect \Y $sub$ls180.v:5512$1126_Y + end + attribute \src "ls180.v:5527.62-5527.100" + cell $sub $sub$ls180.v:5527$1129 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_sdcore_block_count_storage + connect \B 1'1 + connect \Y $sub$ls180.v:5527$1129_Y + end + attribute \src "ls180.v:5538.39-5538.77" + cell $sub $sub$ls180.v:5538$1134 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_sdcore_block_count_storage + connect \B 1'1 + connect \Y $sub$ls180.v:5538$1134_Y + end + attribute \src "ls180.v:5613.40-5613.76" + cell $sub $sub$ls180.v:5613$1138 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 5 + connect \A \main_sdblock2mem_fifo_produce + connect \B 1'1 + connect \Y $sub$ls180.v:5613$1138_Y + end + attribute \src "ls180.v:5662.56-5662.104" + cell $sub $sub$ls180.v:5662$1152 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_sdblock2mem_wishbonedmawriter_length + connect \B 1'1 + connect \Y $sub$ls180.v:5662$1152_Y + end + attribute \src "ls180.v:5752.71-5752.105" + cell $sub $sub$ls180.v:5752$1158 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_sdmem2block_dma_length + connect \B 1'1 + connect \Y $sub$ls180.v:5752$1158_Y + end + attribute \src "ls180.v:5833.40-5833.76" + cell $sub $sub$ls180.v:5833$1169 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 5 + connect \A \main_sdmem2block_fifo_produce + connect \B 1'1 + connect \Y $sub$ls180.v:5833$1169_Y + end + attribute \src "ls180.v:7773.31-7773.60" + cell $sub $sub$ls180.v:7773$2607 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_libresocsim_value + connect \B 1'1 + connect \Y $sub$ls180.v:7773$2607_Y + end + attribute \src "ls180.v:7810.31-7810.61" + cell $sub $sub$ls180.v:7810$2624 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 10 + connect \A \main_sdram_timer_count1 + connect \B 1'1 + connect \Y $sub$ls180.v:7810$2624_Y + end + attribute \src "ls180.v:7816.34-7816.67" + cell $sub $sub$ls180.v:7816$2625 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_postponer_count + connect \B 1'1 + connect \Y $sub$ls180.v:7816$2625_Y + end + attribute \src "ls180.v:7827.36-7827.69" + cell $sub $sub$ls180.v:7827$2628 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_sequencer_count + connect \B 1'1 + connect \Y $sub$ls180.v:7827$2628_Y + end + attribute \src "ls180.v:7891.59-7891.116" + cell $sub $sub$ls180.v:7891$2646 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_level + connect \B 1'1 + connect \Y $sub$ls180.v:7891$2646_Y + end + attribute \src "ls180.v:7910.46-7910.90" + cell $sub $sub$ls180.v:7910$2650 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_bankmachine0_twtpcon_count + connect \B 1'1 + connect \Y $sub$ls180.v:7910$2650_Y + end + attribute \src "ls180.v:7937.59-7937.116" + cell $sub $sub$ls180.v:7937$2662 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_level + connect \B 1'1 + connect \Y $sub$ls180.v:7937$2662_Y + end + attribute \src "ls180.v:7956.46-7956.90" + cell $sub $sub$ls180.v:7956$2666 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_bankmachine1_twtpcon_count + connect \B 1'1 + connect \Y $sub$ls180.v:7956$2666_Y + end + attribute \src "ls180.v:7983.59-7983.116" + cell $sub $sub$ls180.v:7983$2678 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_level + connect \B 1'1 + connect \Y $sub$ls180.v:7983$2678_Y + end + attribute \src "ls180.v:8002.46-8002.90" + cell $sub $sub$ls180.v:8002$2682 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_bankmachine2_twtpcon_count + connect \B 1'1 + connect \Y $sub$ls180.v:8002$2682_Y + end + attribute \src "ls180.v:8029.59-8029.116" + cell $sub $sub$ls180.v:8029$2694 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_level + connect \B 1'1 + connect \Y $sub$ls180.v:8029$2694_Y + end + attribute \src "ls180.v:8048.46-8048.90" + cell $sub $sub$ls180.v:8048$2698 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_bankmachine3_twtpcon_count + connect \B 1'1 + connect \Y $sub$ls180.v:8048$2698_Y + end + attribute \src "ls180.v:8059.25-8059.48" + cell $sub $sub$ls180.v:8059$2702 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 5 + connect \A \main_sdram_time0 + connect \B 1'1 + connect \Y $sub$ls180.v:8059$2702_Y + end + attribute \src "ls180.v:8066.25-8066.48" + cell $sub $sub$ls180.v:8066$2705 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_sdram_time1 + connect \B 1'1 + connect \Y $sub$ls180.v:8066$2705_Y + end + attribute \src "ls180.v:8198.33-8198.64" + cell $sub $sub$ls180.v:8198$2710 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_tccdcon_count + connect \B 1'1 + connect \Y $sub$ls180.v:8198$2710_Y + end + attribute \src "ls180.v:8213.33-8213.64" + cell $sub $sub$ls180.v:8213$2713 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_twtrcon_count + connect \B 1'1 + connect \Y $sub$ls180.v:8213$2713_Y + end + attribute \src "ls180.v:8340.33-8340.64" + cell $sub $sub$ls180.v:8340$2772 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 5 + connect \A \main_uart_tx_fifo_level0 + connect \B 1'1 + connect \Y $sub$ls180.v:8340$2772_Y + end + attribute \src "ls180.v:8362.33-8362.64" + cell $sub $sub$ls180.v:8362$2783 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 5 + connect \A \main_uart_rx_fifo_level0 + connect \B 1'1 + connect \Y $sub$ls180.v:8362$2783_Y + end + attribute \src "ls180.v:8397.34-8397.66" + cell $sub $sub$ls180.v:8397$2788 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_spimaster34_mosi_sel + connect \B 1'1 + connect \Y $sub$ls180.v:8397$2788_Y + end + attribute \src "ls180.v:8432.32-8432.62" + cell $sub $sub$ls180.v:8432$2793 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_spisdcard_mosi_sel + connect \B 1'1 + connect \Y $sub$ls180.v:8432$2793_Y + end + attribute \src "ls180.v:8456.30-8456.53" + cell $sub $sub$ls180.v:8456$2796 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_pwm0_period + connect \B 1'1 + connect \Y $sub$ls180.v:8456$2796_Y + end + attribute \src "ls180.v:8470.30-8470.53" + cell $sub $sub$ls180.v:8470$2800 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_pwm1_period + connect \B 1'1 + connect \Y $sub$ls180.v:8470$2800_Y + end + attribute \src "ls180.v:8873.36-8873.70" + cell $sub $sub$ls180.v:8873$2861 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 6 + connect \A \main_sdblock2mem_fifo_level + connect \B 1'1 + connect \Y $sub$ls180.v:8873$2861_Y + end + attribute \src "ls180.v:8971.36-8971.70" + cell $sub $sub$ls180.v:8971$2883 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 6 + connect \A \main_sdmem2block_fifo_level + connect \B 1'1 + connect \Y $sub$ls180.v:8971$2883_Y + end + attribute \src "ls180.v:9084.22-9084.42" + cell $sub $sub$ls180.v:9084$2890 + parameter \A_SIGNED 0 + parameter \A_WIDTH 20 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 20 + connect \A \builder_count + connect \B 1'1 + connect \Y $sub$ls180.v:9084$2890_Y + end + attribute \src "ls180.v:5110.353-5110.425" + cell $xor $xor$ls180.v:5110$860 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [39] + connect \B \main_sdcore_crc7_inserter_crcreg0 [6] + connect \Y $xor$ls180.v:5110$860_Y + end + attribute \src "ls180.v:5110.200-5110.272" + cell $xor $xor$ls180.v:5110$861 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [39] + connect \B \main_sdcore_crc7_inserter_crcreg0 [6] + connect \Y $xor$ls180.v:5110$861_Y + end + attribute \src "ls180.v:5110.160-5110.273" + cell $xor $xor$ls180.v:5110$862 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg0 [2] + connect \B $xor$ls180.v:5110$861_Y + connect \Y $xor$ls180.v:5110$862_Y + end + attribute \src "ls180.v:5111.353-5111.425" + cell $xor $xor$ls180.v:5111$863 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [38] + connect \B \main_sdcore_crc7_inserter_crcreg1 [6] + connect \Y $xor$ls180.v:5111$863_Y + end + attribute \src "ls180.v:5111.200-5111.272" + cell $xor $xor$ls180.v:5111$864 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [38] + connect \B \main_sdcore_crc7_inserter_crcreg1 [6] + connect \Y $xor$ls180.v:5111$864_Y + end + attribute \src "ls180.v:5111.160-5111.273" + cell $xor $xor$ls180.v:5111$865 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg1 [2] + connect \B $xor$ls180.v:5111$864_Y + connect \Y $xor$ls180.v:5111$865_Y + end + attribute \src "ls180.v:5112.353-5112.425" + cell $xor $xor$ls180.v:5112$866 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [37] + connect \B \main_sdcore_crc7_inserter_crcreg2 [6] + connect \Y $xor$ls180.v:5112$866_Y + end + attribute \src "ls180.v:5112.200-5112.272" + cell $xor $xor$ls180.v:5112$867 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [37] + connect \B \main_sdcore_crc7_inserter_crcreg2 [6] + connect \Y $xor$ls180.v:5112$867_Y + end + attribute \src "ls180.v:5112.160-5112.273" + cell $xor $xor$ls180.v:5112$868 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg2 [2] + connect \B $xor$ls180.v:5112$867_Y + connect \Y $xor$ls180.v:5112$868_Y + end + attribute \src "ls180.v:5113.353-5113.425" + cell $xor $xor$ls180.v:5113$869 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [36] + connect \B \main_sdcore_crc7_inserter_crcreg3 [6] + connect \Y $xor$ls180.v:5113$869_Y + end + attribute \src "ls180.v:5113.200-5113.272" + cell $xor $xor$ls180.v:5113$870 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [36] + connect \B \main_sdcore_crc7_inserter_crcreg3 [6] + connect \Y $xor$ls180.v:5113$870_Y + end + attribute \src "ls180.v:5113.160-5113.273" + cell $xor $xor$ls180.v:5113$871 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg3 [2] + connect \B $xor$ls180.v:5113$870_Y + connect \Y $xor$ls180.v:5113$871_Y + end + attribute \src "ls180.v:5114.353-5114.425" + cell $xor $xor$ls180.v:5114$872 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [35] + connect \B \main_sdcore_crc7_inserter_crcreg4 [6] + connect \Y $xor$ls180.v:5114$872_Y + end + attribute \src "ls180.v:5114.200-5114.272" + cell $xor $xor$ls180.v:5114$873 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [35] + connect \B \main_sdcore_crc7_inserter_crcreg4 [6] + connect \Y $xor$ls180.v:5114$873_Y + end + attribute \src "ls180.v:5114.160-5114.273" + cell $xor $xor$ls180.v:5114$874 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg4 [2] + connect \B $xor$ls180.v:5114$873_Y + connect \Y $xor$ls180.v:5114$874_Y + end + attribute \src "ls180.v:5115.353-5115.425" + cell $xor $xor$ls180.v:5115$875 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [34] + connect \B \main_sdcore_crc7_inserter_crcreg5 [6] + connect \Y $xor$ls180.v:5115$875_Y + end + attribute \src "ls180.v:5115.200-5115.272" + cell $xor $xor$ls180.v:5115$876 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [34] + connect \B \main_sdcore_crc7_inserter_crcreg5 [6] + connect \Y $xor$ls180.v:5115$876_Y + end + attribute \src "ls180.v:5115.160-5115.273" + cell $xor $xor$ls180.v:5115$877 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg5 [2] + connect \B $xor$ls180.v:5115$876_Y + connect \Y $xor$ls180.v:5115$877_Y + end + attribute \src "ls180.v:5116.353-5116.425" + cell $xor $xor$ls180.v:5116$878 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [33] + connect \B \main_sdcore_crc7_inserter_crcreg6 [6] + connect \Y $xor$ls180.v:5116$878_Y + end + attribute \src "ls180.v:5116.200-5116.272" + cell $xor $xor$ls180.v:5116$879 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [33] + connect \B \main_sdcore_crc7_inserter_crcreg6 [6] + connect \Y $xor$ls180.v:5116$879_Y + end + attribute \src "ls180.v:5116.160-5116.273" + cell $xor $xor$ls180.v:5116$880 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg6 [2] + connect \B $xor$ls180.v:5116$879_Y + connect \Y $xor$ls180.v:5116$880_Y + end + attribute \src "ls180.v:5117.353-5117.425" + cell $xor $xor$ls180.v:5117$881 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [32] + connect \B \main_sdcore_crc7_inserter_crcreg7 [6] + connect \Y $xor$ls180.v:5117$881_Y + end + attribute \src "ls180.v:5117.200-5117.272" + cell $xor $xor$ls180.v:5117$882 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [32] + connect \B \main_sdcore_crc7_inserter_crcreg7 [6] + connect \Y $xor$ls180.v:5117$882_Y + end + attribute \src "ls180.v:5117.160-5117.273" + cell $xor $xor$ls180.v:5117$883 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg7 [2] + connect \B $xor$ls180.v:5117$882_Y + connect \Y $xor$ls180.v:5117$883_Y + end + attribute \src "ls180.v:5118.353-5118.425" + cell $xor $xor$ls180.v:5118$884 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [31] + connect \B \main_sdcore_crc7_inserter_crcreg8 [6] + connect \Y $xor$ls180.v:5118$884_Y + end + attribute \src "ls180.v:5118.200-5118.272" + cell $xor $xor$ls180.v:5118$885 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [31] + connect \B \main_sdcore_crc7_inserter_crcreg8 [6] + connect \Y $xor$ls180.v:5118$885_Y + end + attribute \src "ls180.v:5118.160-5118.273" + cell $xor $xor$ls180.v:5118$886 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg8 [2] + connect \B $xor$ls180.v:5118$885_Y + connect \Y $xor$ls180.v:5118$886_Y + end + attribute \src "ls180.v:5119.354-5119.426" + cell $xor $xor$ls180.v:5119$887 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [30] + connect \B \main_sdcore_crc7_inserter_crcreg9 [6] + connect \Y $xor$ls180.v:5119$887_Y + end + attribute \src "ls180.v:5119.201-5119.273" + cell $xor $xor$ls180.v:5119$888 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [30] + connect \B \main_sdcore_crc7_inserter_crcreg9 [6] + connect \Y $xor$ls180.v:5119$888_Y + end + attribute \src "ls180.v:5119.161-5119.274" + cell $xor $xor$ls180.v:5119$889 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg9 [2] + connect \B $xor$ls180.v:5119$888_Y + connect \Y $xor$ls180.v:5119$889_Y + end + attribute \src "ls180.v:5120.361-5120.434" + cell $xor $xor$ls180.v:5120$890 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [29] + connect \B \main_sdcore_crc7_inserter_crcreg10 [6] + connect \Y $xor$ls180.v:5120$890_Y + end + attribute \src "ls180.v:5120.205-5120.278" + cell $xor $xor$ls180.v:5120$891 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [29] + connect \B \main_sdcore_crc7_inserter_crcreg10 [6] + connect \Y $xor$ls180.v:5120$891_Y + end + attribute \src "ls180.v:5120.164-5120.279" + cell $xor $xor$ls180.v:5120$892 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg10 [2] + connect \B $xor$ls180.v:5120$891_Y + connect \Y $xor$ls180.v:5120$892_Y + end + attribute \src "ls180.v:5121.361-5121.434" + cell $xor $xor$ls180.v:5121$893 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [28] + connect \B \main_sdcore_crc7_inserter_crcreg11 [6] + connect \Y $xor$ls180.v:5121$893_Y + end + attribute \src "ls180.v:5121.205-5121.278" + cell $xor $xor$ls180.v:5121$894 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [28] + connect \B \main_sdcore_crc7_inserter_crcreg11 [6] + connect \Y $xor$ls180.v:5121$894_Y + end + attribute \src "ls180.v:5121.164-5121.279" + cell $xor $xor$ls180.v:5121$895 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg11 [2] + connect \B $xor$ls180.v:5121$894_Y + connect \Y $xor$ls180.v:5121$895_Y + end + attribute \src "ls180.v:5122.361-5122.434" + cell $xor $xor$ls180.v:5122$896 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [27] + connect \B \main_sdcore_crc7_inserter_crcreg12 [6] + connect \Y $xor$ls180.v:5122$896_Y + end + attribute \src "ls180.v:5122.205-5122.278" + cell $xor $xor$ls180.v:5122$897 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [27] + connect \B \main_sdcore_crc7_inserter_crcreg12 [6] + connect \Y $xor$ls180.v:5122$897_Y + end + attribute \src "ls180.v:5122.164-5122.279" + cell $xor $xor$ls180.v:5122$898 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg12 [2] + connect \B $xor$ls180.v:5122$897_Y + connect \Y $xor$ls180.v:5122$898_Y + end + attribute \src "ls180.v:5123.361-5123.434" + cell $xor $xor$ls180.v:5123$899 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [26] + connect \B \main_sdcore_crc7_inserter_crcreg13 [6] + connect \Y $xor$ls180.v:5123$899_Y + end + attribute \src "ls180.v:5123.205-5123.278" + cell $xor $xor$ls180.v:5123$900 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [26] + connect \B \main_sdcore_crc7_inserter_crcreg13 [6] + connect \Y $xor$ls180.v:5123$900_Y + end + attribute \src "ls180.v:5123.164-5123.279" + cell $xor $xor$ls180.v:5123$901 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg13 [2] + connect \B $xor$ls180.v:5123$900_Y + connect \Y $xor$ls180.v:5123$901_Y + end + attribute \src "ls180.v:5124.361-5124.434" + cell $xor $xor$ls180.v:5124$902 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [25] + connect \B \main_sdcore_crc7_inserter_crcreg14 [6] + connect \Y $xor$ls180.v:5124$902_Y + end + attribute \src "ls180.v:5124.205-5124.278" + cell $xor $xor$ls180.v:5124$903 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [25] + connect \B \main_sdcore_crc7_inserter_crcreg14 [6] + connect \Y $xor$ls180.v:5124$903_Y + end + attribute \src "ls180.v:5124.164-5124.279" + cell $xor $xor$ls180.v:5124$904 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg14 [2] + connect \B $xor$ls180.v:5124$903_Y + connect \Y $xor$ls180.v:5124$904_Y + end + attribute \src "ls180.v:5125.361-5125.434" + cell $xor $xor$ls180.v:5125$905 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [24] + connect \B \main_sdcore_crc7_inserter_crcreg15 [6] + connect \Y $xor$ls180.v:5125$905_Y + end + attribute \src "ls180.v:5125.205-5125.278" + cell $xor $xor$ls180.v:5125$906 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [24] + connect \B \main_sdcore_crc7_inserter_crcreg15 [6] + connect \Y $xor$ls180.v:5125$906_Y + end + attribute \src "ls180.v:5125.164-5125.279" + cell $xor $xor$ls180.v:5125$907 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg15 [2] + connect \B $xor$ls180.v:5125$906_Y + connect \Y $xor$ls180.v:5125$907_Y + end + attribute \src "ls180.v:5126.361-5126.434" + cell $xor $xor$ls180.v:5126$908 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [23] + connect \B \main_sdcore_crc7_inserter_crcreg16 [6] + connect \Y $xor$ls180.v:5126$908_Y + end + attribute \src "ls180.v:5126.205-5126.278" + cell $xor $xor$ls180.v:5126$909 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [23] + connect \B \main_sdcore_crc7_inserter_crcreg16 [6] + connect \Y $xor$ls180.v:5126$909_Y + end + attribute \src "ls180.v:5126.164-5126.279" + cell $xor $xor$ls180.v:5126$910 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg16 [2] + connect \B $xor$ls180.v:5126$909_Y + connect \Y $xor$ls180.v:5126$910_Y + end + attribute \src "ls180.v:5127.361-5127.434" + cell $xor $xor$ls180.v:5127$911 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [22] + connect \B \main_sdcore_crc7_inserter_crcreg17 [6] + connect \Y $xor$ls180.v:5127$911_Y + end + attribute \src "ls180.v:5127.205-5127.278" + cell $xor $xor$ls180.v:5127$912 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [22] + connect \B \main_sdcore_crc7_inserter_crcreg17 [6] + connect \Y $xor$ls180.v:5127$912_Y + end + attribute \src "ls180.v:5127.164-5127.279" + cell $xor $xor$ls180.v:5127$913 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg17 [2] + connect \B $xor$ls180.v:5127$912_Y + connect \Y $xor$ls180.v:5127$913_Y + end + attribute \src "ls180.v:5128.361-5128.434" + cell $xor $xor$ls180.v:5128$914 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [21] + connect \B \main_sdcore_crc7_inserter_crcreg18 [6] + connect \Y $xor$ls180.v:5128$914_Y + end + attribute \src "ls180.v:5128.205-5128.278" + cell $xor $xor$ls180.v:5128$915 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [21] + connect \B \main_sdcore_crc7_inserter_crcreg18 [6] + connect \Y $xor$ls180.v:5128$915_Y + end + attribute \src "ls180.v:5128.164-5128.279" + cell $xor $xor$ls180.v:5128$916 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg18 [2] + connect \B $xor$ls180.v:5128$915_Y + connect \Y $xor$ls180.v:5128$916_Y + end + attribute \src "ls180.v:5129.361-5129.434" + cell $xor $xor$ls180.v:5129$917 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [20] + connect \B \main_sdcore_crc7_inserter_crcreg19 [6] + connect \Y $xor$ls180.v:5129$917_Y + end + attribute \src "ls180.v:5129.205-5129.278" + cell $xor $xor$ls180.v:5129$918 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [20] + connect \B \main_sdcore_crc7_inserter_crcreg19 [6] + connect \Y $xor$ls180.v:5129$918_Y + end + attribute \src "ls180.v:5129.164-5129.279" + cell $xor $xor$ls180.v:5129$919 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg19 [2] + connect \B $xor$ls180.v:5129$918_Y + connect \Y $xor$ls180.v:5129$919_Y + end + attribute \src "ls180.v:5130.361-5130.434" + cell $xor $xor$ls180.v:5130$920 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [19] + connect \B \main_sdcore_crc7_inserter_crcreg20 [6] + connect \Y $xor$ls180.v:5130$920_Y + end + attribute \src "ls180.v:5130.205-5130.278" + cell $xor $xor$ls180.v:5130$921 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [19] + connect \B \main_sdcore_crc7_inserter_crcreg20 [6] + connect \Y $xor$ls180.v:5130$921_Y + end + attribute \src "ls180.v:5130.164-5130.279" + cell $xor $xor$ls180.v:5130$922 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg20 [2] + connect \B $xor$ls180.v:5130$921_Y + connect \Y $xor$ls180.v:5130$922_Y + end + attribute \src "ls180.v:5131.361-5131.434" + cell $xor $xor$ls180.v:5131$923 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [18] + connect \B \main_sdcore_crc7_inserter_crcreg21 [6] + connect \Y $xor$ls180.v:5131$923_Y + end + attribute \src "ls180.v:5131.205-5131.278" + cell $xor $xor$ls180.v:5131$924 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [18] + connect \B \main_sdcore_crc7_inserter_crcreg21 [6] + connect \Y $xor$ls180.v:5131$924_Y + end + attribute \src "ls180.v:5131.164-5131.279" + cell $xor $xor$ls180.v:5131$925 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg21 [2] + connect \B $xor$ls180.v:5131$924_Y + connect \Y $xor$ls180.v:5131$925_Y + end + attribute \src "ls180.v:5132.361-5132.434" + cell $xor $xor$ls180.v:5132$926 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [17] + connect \B \main_sdcore_crc7_inserter_crcreg22 [6] + connect \Y $xor$ls180.v:5132$926_Y + end + attribute \src "ls180.v:5132.205-5132.278" + cell $xor $xor$ls180.v:5132$927 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [17] + connect \B \main_sdcore_crc7_inserter_crcreg22 [6] + connect \Y $xor$ls180.v:5132$927_Y + end + attribute \src "ls180.v:5132.164-5132.279" + cell $xor $xor$ls180.v:5132$928 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg22 [2] + connect \B $xor$ls180.v:5132$927_Y + connect \Y $xor$ls180.v:5132$928_Y + end + attribute \src "ls180.v:5133.361-5133.434" + cell $xor $xor$ls180.v:5133$929 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [16] + connect \B \main_sdcore_crc7_inserter_crcreg23 [6] + connect \Y $xor$ls180.v:5133$929_Y + end + attribute \src "ls180.v:5133.205-5133.278" + cell $xor $xor$ls180.v:5133$930 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [16] + connect \B \main_sdcore_crc7_inserter_crcreg23 [6] + connect \Y $xor$ls180.v:5133$930_Y + end + attribute \src "ls180.v:5133.164-5133.279" + cell $xor $xor$ls180.v:5133$931 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg23 [2] + connect \B $xor$ls180.v:5133$930_Y + connect \Y $xor$ls180.v:5133$931_Y + end + attribute \src "ls180.v:5134.361-5134.434" + cell $xor $xor$ls180.v:5134$932 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [15] + connect \B \main_sdcore_crc7_inserter_crcreg24 [6] + connect \Y $xor$ls180.v:5134$932_Y + end + attribute \src "ls180.v:5134.205-5134.278" + cell $xor $xor$ls180.v:5134$933 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [15] + connect \B \main_sdcore_crc7_inserter_crcreg24 [6] + connect \Y $xor$ls180.v:5134$933_Y + end + attribute \src "ls180.v:5134.164-5134.279" + cell $xor $xor$ls180.v:5134$934 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg24 [2] + connect \B $xor$ls180.v:5134$933_Y + connect \Y $xor$ls180.v:5134$934_Y + end + attribute \src "ls180.v:5135.361-5135.434" + cell $xor $xor$ls180.v:5135$935 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [14] + connect \B \main_sdcore_crc7_inserter_crcreg25 [6] + connect \Y $xor$ls180.v:5135$935_Y + end + attribute \src "ls180.v:5135.205-5135.278" + cell $xor $xor$ls180.v:5135$936 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [14] + connect \B \main_sdcore_crc7_inserter_crcreg25 [6] + connect \Y $xor$ls180.v:5135$936_Y + end + attribute \src "ls180.v:5135.164-5135.279" + cell $xor $xor$ls180.v:5135$937 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg25 [2] + connect \B $xor$ls180.v:5135$936_Y + connect \Y $xor$ls180.v:5135$937_Y + end + attribute \src "ls180.v:5136.361-5136.434" + cell $xor $xor$ls180.v:5136$938 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [13] + connect \B \main_sdcore_crc7_inserter_crcreg26 [6] + connect \Y $xor$ls180.v:5136$938_Y + end + attribute \src "ls180.v:5136.205-5136.278" + cell $xor $xor$ls180.v:5136$939 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [13] + connect \B \main_sdcore_crc7_inserter_crcreg26 [6] + connect \Y $xor$ls180.v:5136$939_Y + end + attribute \src "ls180.v:5136.164-5136.279" + cell $xor $xor$ls180.v:5136$940 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg26 [2] + connect \B $xor$ls180.v:5136$939_Y + connect \Y $xor$ls180.v:5136$940_Y + end + attribute \src "ls180.v:5137.361-5137.434" + cell $xor $xor$ls180.v:5137$941 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [12] + connect \B \main_sdcore_crc7_inserter_crcreg27 [6] + connect \Y $xor$ls180.v:5137$941_Y + end + attribute \src "ls180.v:5137.205-5137.278" + cell $xor $xor$ls180.v:5137$942 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [12] + connect \B \main_sdcore_crc7_inserter_crcreg27 [6] + connect \Y $xor$ls180.v:5137$942_Y + end + attribute \src "ls180.v:5137.164-5137.279" + cell $xor $xor$ls180.v:5137$943 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg27 [2] + connect \B $xor$ls180.v:5137$942_Y + connect \Y $xor$ls180.v:5137$943_Y + end + attribute \src "ls180.v:5138.361-5138.434" + cell $xor $xor$ls180.v:5138$944 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [11] + connect \B \main_sdcore_crc7_inserter_crcreg28 [6] + connect \Y $xor$ls180.v:5138$944_Y + end + attribute \src "ls180.v:5138.205-5138.278" + cell $xor $xor$ls180.v:5138$945 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [11] + connect \B \main_sdcore_crc7_inserter_crcreg28 [6] + connect \Y $xor$ls180.v:5138$945_Y + end + attribute \src "ls180.v:5138.164-5138.279" + cell $xor $xor$ls180.v:5138$946 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg28 [2] + connect \B $xor$ls180.v:5138$945_Y + connect \Y $xor$ls180.v:5138$946_Y + end + attribute \src "ls180.v:5139.361-5139.434" + cell $xor $xor$ls180.v:5139$947 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [10] + connect \B \main_sdcore_crc7_inserter_crcreg29 [6] + connect \Y $xor$ls180.v:5139$947_Y + end + attribute \src "ls180.v:5139.205-5139.278" + cell $xor $xor$ls180.v:5139$948 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [10] + connect \B \main_sdcore_crc7_inserter_crcreg29 [6] + connect \Y $xor$ls180.v:5139$948_Y + end + attribute \src "ls180.v:5139.164-5139.279" + cell $xor $xor$ls180.v:5139$949 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg29 [2] + connect \B $xor$ls180.v:5139$948_Y + connect \Y $xor$ls180.v:5139$949_Y + end + attribute \src "ls180.v:5140.360-5140.432" + cell $xor $xor$ls180.v:5140$950 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [9] + connect \B \main_sdcore_crc7_inserter_crcreg30 [6] + connect \Y $xor$ls180.v:5140$950_Y + end + attribute \src "ls180.v:5140.205-5140.277" + cell $xor $xor$ls180.v:5140$951 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [9] + connect \B \main_sdcore_crc7_inserter_crcreg30 [6] + connect \Y $xor$ls180.v:5140$951_Y + end + attribute \src "ls180.v:5140.164-5140.278" + cell $xor $xor$ls180.v:5140$952 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg30 [2] + connect \B $xor$ls180.v:5140$951_Y + connect \Y $xor$ls180.v:5140$952_Y + end + attribute \src "ls180.v:5141.360-5141.432" + cell $xor $xor$ls180.v:5141$953 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [8] + connect \B \main_sdcore_crc7_inserter_crcreg31 [6] + connect \Y $xor$ls180.v:5141$953_Y + end + attribute \src "ls180.v:5141.205-5141.277" + cell $xor $xor$ls180.v:5141$954 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [8] + connect \B \main_sdcore_crc7_inserter_crcreg31 [6] + connect \Y $xor$ls180.v:5141$954_Y + end + attribute \src "ls180.v:5141.164-5141.278" + cell $xor $xor$ls180.v:5141$955 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg31 [2] + connect \B $xor$ls180.v:5141$954_Y + connect \Y $xor$ls180.v:5141$955_Y + end + attribute \src "ls180.v:5142.360-5142.432" + cell $xor $xor$ls180.v:5142$956 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [7] + connect \B \main_sdcore_crc7_inserter_crcreg32 [6] + connect \Y $xor$ls180.v:5142$956_Y + end + attribute \src "ls180.v:5142.205-5142.277" + cell $xor $xor$ls180.v:5142$957 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [7] + connect \B \main_sdcore_crc7_inserter_crcreg32 [6] + connect \Y $xor$ls180.v:5142$957_Y + end + attribute \src "ls180.v:5142.164-5142.278" + cell $xor $xor$ls180.v:5142$958 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg32 [2] + connect \B $xor$ls180.v:5142$957_Y + connect \Y $xor$ls180.v:5142$958_Y + end + attribute \src "ls180.v:5143.360-5143.432" + cell $xor $xor$ls180.v:5143$959 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [6] + connect \B \main_sdcore_crc7_inserter_crcreg33 [6] + connect \Y $xor$ls180.v:5143$959_Y + end + attribute \src "ls180.v:5143.205-5143.277" + cell $xor $xor$ls180.v:5143$960 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [6] + connect \B \main_sdcore_crc7_inserter_crcreg33 [6] + connect \Y $xor$ls180.v:5143$960_Y + end + attribute \src "ls180.v:5143.164-5143.278" + cell $xor $xor$ls180.v:5143$961 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg33 [2] + connect \B $xor$ls180.v:5143$960_Y + connect \Y $xor$ls180.v:5143$961_Y + end + attribute \src "ls180.v:5144.360-5144.432" + cell $xor $xor$ls180.v:5144$962 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [5] + connect \B \main_sdcore_crc7_inserter_crcreg34 [6] + connect \Y $xor$ls180.v:5144$962_Y + end + attribute \src "ls180.v:5144.205-5144.277" + cell $xor $xor$ls180.v:5144$963 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [5] + connect \B \main_sdcore_crc7_inserter_crcreg34 [6] + connect \Y $xor$ls180.v:5144$963_Y + end + attribute \src "ls180.v:5144.164-5144.278" + cell $xor $xor$ls180.v:5144$964 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg34 [2] + connect \B $xor$ls180.v:5144$963_Y + connect \Y $xor$ls180.v:5144$964_Y + end + attribute \src "ls180.v:5145.360-5145.432" + cell $xor $xor$ls180.v:5145$965 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [4] + connect \B \main_sdcore_crc7_inserter_crcreg35 [6] + connect \Y $xor$ls180.v:5145$965_Y + end + attribute \src "ls180.v:5145.205-5145.277" + cell $xor $xor$ls180.v:5145$966 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [4] + connect \B \main_sdcore_crc7_inserter_crcreg35 [6] + connect \Y $xor$ls180.v:5145$966_Y + end + attribute \src "ls180.v:5145.164-5145.278" + cell $xor $xor$ls180.v:5145$967 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg35 [2] + connect \B $xor$ls180.v:5145$966_Y + connect \Y $xor$ls180.v:5145$967_Y + end + attribute \src "ls180.v:5146.360-5146.432" + cell $xor $xor$ls180.v:5146$968 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [3] + connect \B \main_sdcore_crc7_inserter_crcreg36 [6] + connect \Y $xor$ls180.v:5146$968_Y + end + attribute \src "ls180.v:5146.205-5146.277" + cell $xor $xor$ls180.v:5146$969 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [3] + connect \B \main_sdcore_crc7_inserter_crcreg36 [6] + connect \Y $xor$ls180.v:5146$969_Y + end + attribute \src "ls180.v:5146.164-5146.278" + cell $xor $xor$ls180.v:5146$970 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg36 [2] + connect \B $xor$ls180.v:5146$969_Y + connect \Y $xor$ls180.v:5146$970_Y + end + attribute \src "ls180.v:5147.360-5147.432" + cell $xor $xor$ls180.v:5147$971 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [2] + connect \B \main_sdcore_crc7_inserter_crcreg37 [6] + connect \Y $xor$ls180.v:5147$971_Y + end + attribute \src "ls180.v:5147.205-5147.277" + cell $xor $xor$ls180.v:5147$972 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [2] + connect \B \main_sdcore_crc7_inserter_crcreg37 [6] + connect \Y $xor$ls180.v:5147$972_Y + end + attribute \src "ls180.v:5147.164-5147.278" + cell $xor $xor$ls180.v:5147$973 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg37 [2] + connect \B $xor$ls180.v:5147$972_Y + connect \Y $xor$ls180.v:5147$973_Y + end + attribute \src "ls180.v:5148.360-5148.432" + cell $xor $xor$ls180.v:5148$974 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [1] + connect \B \main_sdcore_crc7_inserter_crcreg38 [6] + connect \Y $xor$ls180.v:5148$974_Y + end + attribute \src "ls180.v:5148.205-5148.277" + cell $xor $xor$ls180.v:5148$975 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [1] + connect \B \main_sdcore_crc7_inserter_crcreg38 [6] + connect \Y $xor$ls180.v:5148$975_Y + end + attribute \src "ls180.v:5148.164-5148.278" + cell $xor $xor$ls180.v:5148$976 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg38 [2] + connect \B $xor$ls180.v:5148$975_Y + connect \Y $xor$ls180.v:5148$976_Y + end + attribute \src "ls180.v:5149.360-5149.432" + cell $xor $xor$ls180.v:5149$977 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [0] + connect \B \main_sdcore_crc7_inserter_crcreg39 [6] + connect \Y $xor$ls180.v:5149$977_Y + end + attribute \src "ls180.v:5149.205-5149.277" + cell $xor $xor$ls180.v:5149$978 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_val [0] + connect \B \main_sdcore_crc7_inserter_crcreg39 [6] + connect \Y $xor$ls180.v:5149$978_Y + end + attribute \src "ls180.v:5149.164-5149.278" + cell $xor $xor$ls180.v:5149$979 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc7_inserter_crcreg39 [2] + connect \B $xor$ls180.v:5149$978_Y + connect \Y $xor$ls180.v:5149$979_Y + end + attribute \src "ls180.v:5170.899-5170.983" + cell $xor $xor$ls180.v:5170$993 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc0_val [1] + connect \B \main_sdcore_crc16_inserter_crc0_crcreg0 [15] + connect \Y $xor$ls180.v:5170$993_Y + end + attribute \src "ls180.v:5170.634-5170.718" + cell $xor $xor$ls180.v:5170$994 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc0_val [1] + connect \B \main_sdcore_crc16_inserter_crc0_crcreg0 [15] + connect \Y $xor$ls180.v:5170$994_Y + end + attribute \src "ls180.v:5170.588-5170.719" + cell $xor $xor$ls180.v:5170$995 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc0_crcreg0 [4] + connect \B $xor$ls180.v:5170$994_Y + connect \Y $xor$ls180.v:5170$995_Y + end + attribute \src "ls180.v:5170.234-5170.318" + cell $xor $xor$ls180.v:5170$996 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc0_val [1] + connect \B \main_sdcore_crc16_inserter_crc0_crcreg0 [15] + connect \Y $xor$ls180.v:5170$996_Y + end + attribute \src "ls180.v:5170.187-5170.319" + cell $xor $xor$ls180.v:5170$997 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc0_crcreg0 [11] + connect \B $xor$ls180.v:5170$996_Y + connect \Y $xor$ls180.v:5170$997_Y + end + attribute \src "ls180.v:5171.588-5171.719" + cell $xor $xor$ls180.v:5171$1000 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc0_crcreg1 [4] + connect \B $xor$ls180.v:5171$999_Y + connect \Y $xor$ls180.v:5171$1000_Y + end + attribute \src "ls180.v:5171.234-5171.318" + cell $xor $xor$ls180.v:5171$1001 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc0_val [0] + connect \B \main_sdcore_crc16_inserter_crc0_crcreg1 [15] + connect \Y $xor$ls180.v:5171$1001_Y + end + attribute \src "ls180.v:5171.187-5171.319" + cell $xor $xor$ls180.v:5171$1002 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc0_crcreg1 [11] + connect \B $xor$ls180.v:5171$1001_Y + connect \Y $xor$ls180.v:5171$1002_Y + end + attribute \src "ls180.v:5171.899-5171.983" + cell $xor $xor$ls180.v:5171$998 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc0_val [0] + connect \B \main_sdcore_crc16_inserter_crc0_crcreg1 [15] + connect \Y $xor$ls180.v:5171$998_Y + end + attribute \src "ls180.v:5171.634-5171.718" + cell $xor $xor$ls180.v:5171$999 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc0_val [0] + connect \B \main_sdcore_crc16_inserter_crc0_crcreg1 [15] + connect \Y $xor$ls180.v:5171$999_Y + end + attribute \src "ls180.v:5180.899-5180.983" + cell $xor $xor$ls180.v:5180$1004 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc1_val [1] + connect \B \main_sdcore_crc16_inserter_crc1_crcreg0 [15] + connect \Y $xor$ls180.v:5180$1004_Y + end + attribute \src "ls180.v:5180.634-5180.718" + cell $xor $xor$ls180.v:5180$1005 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc1_val [1] + connect \B \main_sdcore_crc16_inserter_crc1_crcreg0 [15] + connect \Y $xor$ls180.v:5180$1005_Y + end + attribute \src "ls180.v:5180.588-5180.719" + cell $xor $xor$ls180.v:5180$1006 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc1_crcreg0 [4] + connect \B $xor$ls180.v:5180$1005_Y + connect \Y $xor$ls180.v:5180$1006_Y + end + attribute \src "ls180.v:5180.234-5180.318" + cell $xor $xor$ls180.v:5180$1007 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc1_val [1] + connect \B \main_sdcore_crc16_inserter_crc1_crcreg0 [15] + connect \Y $xor$ls180.v:5180$1007_Y + end + attribute \src "ls180.v:5180.187-5180.319" + cell $xor $xor$ls180.v:5180$1008 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc1_crcreg0 [11] + connect \B $xor$ls180.v:5180$1007_Y + connect \Y $xor$ls180.v:5180$1008_Y + end + attribute \src "ls180.v:5181.899-5181.983" + cell $xor $xor$ls180.v:5181$1009 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc1_val [0] + connect \B \main_sdcore_crc16_inserter_crc1_crcreg1 [15] + connect \Y $xor$ls180.v:5181$1009_Y + end + attribute \src "ls180.v:5181.634-5181.718" + cell $xor $xor$ls180.v:5181$1010 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc1_val [0] + connect \B \main_sdcore_crc16_inserter_crc1_crcreg1 [15] + connect \Y $xor$ls180.v:5181$1010_Y + end + attribute \src "ls180.v:5181.588-5181.719" + cell $xor $xor$ls180.v:5181$1011 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc1_crcreg1 [4] + connect \B $xor$ls180.v:5181$1010_Y + connect \Y $xor$ls180.v:5181$1011_Y + end + attribute \src "ls180.v:5181.234-5181.318" + cell $xor $xor$ls180.v:5181$1012 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc1_val [0] + connect \B \main_sdcore_crc16_inserter_crc1_crcreg1 [15] + connect \Y $xor$ls180.v:5181$1012_Y + end + attribute \src "ls180.v:5181.187-5181.319" + cell $xor $xor$ls180.v:5181$1013 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc1_crcreg1 [11] + connect \B $xor$ls180.v:5181$1012_Y + connect \Y $xor$ls180.v:5181$1013_Y + end + attribute \src "ls180.v:5190.899-5190.983" + cell $xor $xor$ls180.v:5190$1015 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc2_val [1] + connect \B \main_sdcore_crc16_inserter_crc2_crcreg0 [15] + connect \Y $xor$ls180.v:5190$1015_Y + end + attribute \src "ls180.v:5190.634-5190.718" + cell $xor $xor$ls180.v:5190$1016 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc2_val [1] + connect \B \main_sdcore_crc16_inserter_crc2_crcreg0 [15] + connect \Y $xor$ls180.v:5190$1016_Y + end + attribute \src "ls180.v:5190.588-5190.719" + cell $xor $xor$ls180.v:5190$1017 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc2_crcreg0 [4] + connect \B $xor$ls180.v:5190$1016_Y + connect \Y $xor$ls180.v:5190$1017_Y + end + attribute \src "ls180.v:5190.234-5190.318" + cell $xor $xor$ls180.v:5190$1018 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc2_val [1] + connect \B \main_sdcore_crc16_inserter_crc2_crcreg0 [15] + connect \Y $xor$ls180.v:5190$1018_Y + end + attribute \src "ls180.v:5190.187-5190.319" + cell $xor $xor$ls180.v:5190$1019 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc2_crcreg0 [11] + connect \B $xor$ls180.v:5190$1018_Y + connect \Y $xor$ls180.v:5190$1019_Y + end + attribute \src "ls180.v:5191.899-5191.983" + cell $xor $xor$ls180.v:5191$1020 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc2_val [0] + connect \B \main_sdcore_crc16_inserter_crc2_crcreg1 [15] + connect \Y $xor$ls180.v:5191$1020_Y + end + attribute \src "ls180.v:5191.634-5191.718" + cell $xor $xor$ls180.v:5191$1021 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc2_val [0] + connect \B \main_sdcore_crc16_inserter_crc2_crcreg1 [15] + connect \Y $xor$ls180.v:5191$1021_Y + end + attribute \src "ls180.v:5191.588-5191.719" + cell $xor $xor$ls180.v:5191$1022 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc2_crcreg1 [4] + connect \B $xor$ls180.v:5191$1021_Y + connect \Y $xor$ls180.v:5191$1022_Y + end + attribute \src "ls180.v:5191.234-5191.318" + cell $xor $xor$ls180.v:5191$1023 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc2_val [0] + connect \B \main_sdcore_crc16_inserter_crc2_crcreg1 [15] + connect \Y $xor$ls180.v:5191$1023_Y + end + attribute \src "ls180.v:5191.187-5191.319" + cell $xor $xor$ls180.v:5191$1024 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc2_crcreg1 [11] + connect \B $xor$ls180.v:5191$1023_Y + connect \Y $xor$ls180.v:5191$1024_Y + end + attribute \src "ls180.v:5200.899-5200.983" + cell $xor $xor$ls180.v:5200$1026 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc3_val [1] + connect \B \main_sdcore_crc16_inserter_crc3_crcreg0 [15] + connect \Y $xor$ls180.v:5200$1026_Y + end + attribute \src "ls180.v:5200.634-5200.718" + cell $xor $xor$ls180.v:5200$1027 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc3_val [1] + connect \B \main_sdcore_crc16_inserter_crc3_crcreg0 [15] + connect \Y $xor$ls180.v:5200$1027_Y + end + attribute \src "ls180.v:5200.588-5200.719" + cell $xor $xor$ls180.v:5200$1028 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc3_crcreg0 [4] + connect \B $xor$ls180.v:5200$1027_Y + connect \Y $xor$ls180.v:5200$1028_Y + end + attribute \src "ls180.v:5200.234-5200.318" + cell $xor $xor$ls180.v:5200$1029 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc3_val [1] + connect \B \main_sdcore_crc16_inserter_crc3_crcreg0 [15] + connect \Y $xor$ls180.v:5200$1029_Y + end + attribute \src "ls180.v:5200.187-5200.319" + cell $xor $xor$ls180.v:5200$1030 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc3_crcreg0 [11] + connect \B $xor$ls180.v:5200$1029_Y + connect \Y $xor$ls180.v:5200$1030_Y + end + attribute \src "ls180.v:5201.899-5201.983" + cell $xor $xor$ls180.v:5201$1031 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc3_val [0] + connect \B \main_sdcore_crc16_inserter_crc3_crcreg1 [15] + connect \Y $xor$ls180.v:5201$1031_Y + end + attribute \src "ls180.v:5201.634-5201.718" + cell $xor $xor$ls180.v:5201$1032 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc3_val [0] + connect \B \main_sdcore_crc16_inserter_crc3_crcreg1 [15] + connect \Y $xor$ls180.v:5201$1032_Y + end + attribute \src "ls180.v:5201.588-5201.719" + cell $xor $xor$ls180.v:5201$1033 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc3_crcreg1 [4] + connect \B $xor$ls180.v:5201$1032_Y + connect \Y $xor$ls180.v:5201$1033_Y + end + attribute \src "ls180.v:5201.234-5201.318" + cell $xor $xor$ls180.v:5201$1034 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc3_val [0] + connect \B \main_sdcore_crc16_inserter_crc3_crcreg1 [15] + connect \Y $xor$ls180.v:5201$1034_Y + end + attribute \src "ls180.v:5201.187-5201.319" + cell $xor $xor$ls180.v:5201$1035 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_inserter_crc3_crcreg1 [11] + connect \B $xor$ls180.v:5201$1034_Y + connect \Y $xor$ls180.v:5201$1035_Y + end + attribute \src "ls180.v:5352.879-5352.961" + cell $xor $xor$ls180.v:5352$1068 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc0_val [1] + connect \B \main_sdcore_crc16_checker_crc0_crcreg0 [15] + connect \Y $xor$ls180.v:5352$1068_Y + end + attribute \src "ls180.v:5352.620-5352.702" + cell $xor $xor$ls180.v:5352$1069 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc0_val [1] + connect \B \main_sdcore_crc16_checker_crc0_crcreg0 [15] + connect \Y $xor$ls180.v:5352$1069_Y + end + attribute \src "ls180.v:5352.575-5352.703" + cell $xor $xor$ls180.v:5352$1070 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc0_crcreg0 [4] + connect \B $xor$ls180.v:5352$1069_Y + connect \Y $xor$ls180.v:5352$1070_Y + end + attribute \src "ls180.v:5352.229-5352.311" + cell $xor $xor$ls180.v:5352$1071 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc0_val [1] + connect \B \main_sdcore_crc16_checker_crc0_crcreg0 [15] + connect \Y $xor$ls180.v:5352$1071_Y + end + attribute \src "ls180.v:5352.183-5352.312" + cell $xor $xor$ls180.v:5352$1072 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc0_crcreg0 [11] + connect \B $xor$ls180.v:5352$1071_Y + connect \Y $xor$ls180.v:5352$1072_Y + end + attribute \src "ls180.v:5353.879-5353.961" + cell $xor $xor$ls180.v:5353$1073 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc0_val [0] + connect \B \main_sdcore_crc16_checker_crc0_crcreg1 [15] + connect \Y $xor$ls180.v:5353$1073_Y + end + attribute \src "ls180.v:5353.620-5353.702" + cell $xor $xor$ls180.v:5353$1074 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc0_val [0] + connect \B \main_sdcore_crc16_checker_crc0_crcreg1 [15] + connect \Y $xor$ls180.v:5353$1074_Y + end + attribute \src "ls180.v:5353.575-5353.703" + cell $xor $xor$ls180.v:5353$1075 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc0_crcreg1 [4] + connect \B $xor$ls180.v:5353$1074_Y + connect \Y $xor$ls180.v:5353$1075_Y + end + attribute \src "ls180.v:5353.229-5353.311" + cell $xor $xor$ls180.v:5353$1076 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc0_val [0] + connect \B \main_sdcore_crc16_checker_crc0_crcreg1 [15] + connect \Y $xor$ls180.v:5353$1076_Y + end + attribute \src "ls180.v:5353.183-5353.312" + cell $xor $xor$ls180.v:5353$1077 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc0_crcreg1 [11] + connect \B $xor$ls180.v:5353$1076_Y + connect \Y $xor$ls180.v:5353$1077_Y + end + attribute \src "ls180.v:5362.879-5362.961" + cell $xor $xor$ls180.v:5362$1079 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc1_val [1] + connect \B \main_sdcore_crc16_checker_crc1_crcreg0 [15] + connect \Y $xor$ls180.v:5362$1079_Y + end + attribute \src "ls180.v:5362.620-5362.702" + cell $xor $xor$ls180.v:5362$1080 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc1_val [1] + connect \B \main_sdcore_crc16_checker_crc1_crcreg0 [15] + connect \Y $xor$ls180.v:5362$1080_Y + end + attribute \src "ls180.v:5362.575-5362.703" + cell $xor $xor$ls180.v:5362$1081 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc1_crcreg0 [4] + connect \B $xor$ls180.v:5362$1080_Y + connect \Y $xor$ls180.v:5362$1081_Y + end + attribute \src "ls180.v:5362.229-5362.311" + cell $xor $xor$ls180.v:5362$1082 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc1_val [1] + connect \B \main_sdcore_crc16_checker_crc1_crcreg0 [15] + connect \Y $xor$ls180.v:5362$1082_Y + end + attribute \src "ls180.v:5362.183-5362.312" + cell $xor $xor$ls180.v:5362$1083 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc1_crcreg0 [11] + connect \B $xor$ls180.v:5362$1082_Y + connect \Y $xor$ls180.v:5362$1083_Y + end + attribute \src "ls180.v:5363.879-5363.961" + cell $xor $xor$ls180.v:5363$1084 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc1_val [0] + connect \B \main_sdcore_crc16_checker_crc1_crcreg1 [15] + connect \Y $xor$ls180.v:5363$1084_Y + end + attribute \src "ls180.v:5363.620-5363.702" + cell $xor $xor$ls180.v:5363$1085 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc1_val [0] + connect \B \main_sdcore_crc16_checker_crc1_crcreg1 [15] + connect \Y $xor$ls180.v:5363$1085_Y + end + attribute \src "ls180.v:5363.575-5363.703" + cell $xor $xor$ls180.v:5363$1086 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc1_crcreg1 [4] + connect \B $xor$ls180.v:5363$1085_Y + connect \Y $xor$ls180.v:5363$1086_Y + end + attribute \src "ls180.v:5363.229-5363.311" + cell $xor $xor$ls180.v:5363$1087 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc1_val [0] + connect \B \main_sdcore_crc16_checker_crc1_crcreg1 [15] + connect \Y $xor$ls180.v:5363$1087_Y + end + attribute \src "ls180.v:5363.183-5363.312" + cell $xor $xor$ls180.v:5363$1088 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc1_crcreg1 [11] + connect \B $xor$ls180.v:5363$1087_Y + connect \Y $xor$ls180.v:5363$1088_Y + end + attribute \src "ls180.v:5372.879-5372.961" + cell $xor $xor$ls180.v:5372$1090 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc2_val [1] + connect \B \main_sdcore_crc16_checker_crc2_crcreg0 [15] + connect \Y $xor$ls180.v:5372$1090_Y + end + attribute \src "ls180.v:5372.620-5372.702" + cell $xor $xor$ls180.v:5372$1091 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc2_val [1] + connect \B \main_sdcore_crc16_checker_crc2_crcreg0 [15] + connect \Y $xor$ls180.v:5372$1091_Y + end + attribute \src "ls180.v:5372.575-5372.703" + cell $xor $xor$ls180.v:5372$1092 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc2_crcreg0 [4] + connect \B $xor$ls180.v:5372$1091_Y + connect \Y $xor$ls180.v:5372$1092_Y + end + attribute \src "ls180.v:5372.229-5372.311" + cell $xor $xor$ls180.v:5372$1093 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc2_val [1] + connect \B \main_sdcore_crc16_checker_crc2_crcreg0 [15] + connect \Y $xor$ls180.v:5372$1093_Y + end + attribute \src "ls180.v:5372.183-5372.312" + cell $xor $xor$ls180.v:5372$1094 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc2_crcreg0 [11] + connect \B $xor$ls180.v:5372$1093_Y + connect \Y $xor$ls180.v:5372$1094_Y + end + attribute \src "ls180.v:5373.879-5373.961" + cell $xor $xor$ls180.v:5373$1095 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc2_val [0] + connect \B \main_sdcore_crc16_checker_crc2_crcreg1 [15] + connect \Y $xor$ls180.v:5373$1095_Y + end + attribute \src "ls180.v:5373.620-5373.702" + cell $xor $xor$ls180.v:5373$1096 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc2_val [0] + connect \B \main_sdcore_crc16_checker_crc2_crcreg1 [15] + connect \Y $xor$ls180.v:5373$1096_Y + end + attribute \src "ls180.v:5373.575-5373.703" + cell $xor $xor$ls180.v:5373$1097 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc2_crcreg1 [4] + connect \B $xor$ls180.v:5373$1096_Y + connect \Y $xor$ls180.v:5373$1097_Y + end + attribute \src "ls180.v:5373.229-5373.311" + cell $xor $xor$ls180.v:5373$1098 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc2_val [0] + connect \B \main_sdcore_crc16_checker_crc2_crcreg1 [15] + connect \Y $xor$ls180.v:5373$1098_Y + end + attribute \src "ls180.v:5373.183-5373.312" + cell $xor $xor$ls180.v:5373$1099 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc2_crcreg1 [11] + connect \B $xor$ls180.v:5373$1098_Y + connect \Y $xor$ls180.v:5373$1099_Y + end + attribute \src "ls180.v:5382.879-5382.961" + cell $xor $xor$ls180.v:5382$1101 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc3_val [1] + connect \B \main_sdcore_crc16_checker_crc3_crcreg0 [15] + connect \Y $xor$ls180.v:5382$1101_Y + end + attribute \src "ls180.v:5382.620-5382.702" + cell $xor $xor$ls180.v:5382$1102 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc3_val [1] + connect \B \main_sdcore_crc16_checker_crc3_crcreg0 [15] + connect \Y $xor$ls180.v:5382$1102_Y + end + attribute \src "ls180.v:5382.575-5382.703" + cell $xor $xor$ls180.v:5382$1103 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc3_crcreg0 [4] + connect \B $xor$ls180.v:5382$1102_Y + connect \Y $xor$ls180.v:5382$1103_Y + end + attribute \src "ls180.v:5382.229-5382.311" + cell $xor $xor$ls180.v:5382$1104 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc3_val [1] + connect \B \main_sdcore_crc16_checker_crc3_crcreg0 [15] + connect \Y $xor$ls180.v:5382$1104_Y + end + attribute \src "ls180.v:5382.183-5382.312" + cell $xor $xor$ls180.v:5382$1105 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc3_crcreg0 [11] + connect \B $xor$ls180.v:5382$1104_Y + connect \Y $xor$ls180.v:5382$1105_Y + end + attribute \src "ls180.v:5383.879-5383.961" + cell $xor $xor$ls180.v:5383$1106 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc3_val [0] + connect \B \main_sdcore_crc16_checker_crc3_crcreg1 [15] + connect \Y $xor$ls180.v:5383$1106_Y + end + attribute \src "ls180.v:5383.620-5383.702" + cell $xor $xor$ls180.v:5383$1107 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc3_val [0] + connect \B \main_sdcore_crc16_checker_crc3_crcreg1 [15] + connect \Y $xor$ls180.v:5383$1107_Y + end + attribute \src "ls180.v:5383.575-5383.703" + cell $xor $xor$ls180.v:5383$1108 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc3_crcreg1 [4] + connect \B $xor$ls180.v:5383$1107_Y + connect \Y $xor$ls180.v:5383$1108_Y + end + attribute \src "ls180.v:5383.229-5383.311" + cell $xor $xor$ls180.v:5383$1109 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc3_val [0] + connect \B \main_sdcore_crc16_checker_crc3_crcreg1 [15] + connect \Y $xor$ls180.v:5383$1109_Y + end + attribute \src "ls180.v:5383.183-5383.312" + cell $xor $xor$ls180.v:5383$1110 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdcore_crc16_checker_crc3_crcreg1 [11] + connect \B $xor$ls180.v:5383$1109_Y + connect \Y $xor$ls180.v:5383$1110_Y + end + attribute \module_not_derived 1 + attribute \src "ls180.v:10606.13-11024.2" + cell \test_issuer \test_issuer + connect \TAP_bus__tck \main_libresocsim_libresoc_jtag_tck + connect \TAP_bus__tdi \main_libresocsim_libresoc_jtag_tdi + connect \TAP_bus__tdo \main_libresocsim_libresoc_jtag_tdo + connect \TAP_bus__tms \main_libresocsim_libresoc_jtag_tms + connect \busy_o \main_libresocsim_libresoc0 + connect \clk \sys_clk_1 + connect \clk_sel_i \main_libresocsim_libresoc_clk_sel + connect \core_bigendian_i 1'0 + connect \dbus__ack \main_libresocsim_libresoc_dbus_ack + connect \dbus__adr \main_libresocsim_libresoc_dbus_adr + connect \dbus__bte 1'0 + connect \dbus__cti 1'0 + connect \dbus__cyc \main_libresocsim_libresoc_dbus_cyc + connect \dbus__dat_r \main_libresocsim_libresoc_dbus_dat_r + connect \dbus__dat_w \main_libresocsim_libresoc_dbus_dat_w + connect \dbus__err \main_libresocsim_libresoc_dbus_err + connect \dbus__sel \main_libresocsim_libresoc_dbus_sel + connect \dbus__stb \main_libresocsim_libresoc_dbus_stb + connect \dbus__we \main_libresocsim_libresoc_dbus_we + connect \eint_0__core__i \eint [0] + connect \eint_0__pad__i \eint_1 [0] + connect \eint_1__core__i \eint [1] + connect \eint_1__pad__i \eint_1 [1] + connect \eint_2__core__i \eint [2] + connect \eint_2__pad__i \eint_1 [2] + connect \gpio_e10__core__i \gpio_i [10] + connect \gpio_e10__core__o \gpio_o [10] + connect \gpio_e10__core__oe \gpio_oe [10] + connect \gpio_e10__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [10] + connect \gpio_e10__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [10] + connect \gpio_e10__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [10] + connect \gpio_e11__core__i \gpio_i [11] + connect \gpio_e11__core__o \gpio_o [11] + connect \gpio_e11__core__oe \gpio_oe [11] + connect \gpio_e11__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [11] + connect \gpio_e11__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [11] + connect \gpio_e11__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [11] + connect \gpio_e12__core__i \gpio_i [12] + connect \gpio_e12__core__o \gpio_o [12] + connect \gpio_e12__core__oe \gpio_oe [12] + connect \gpio_e12__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [12] + connect \gpio_e12__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [12] + connect \gpio_e12__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [12] + connect \gpio_e13__core__i \gpio_i [13] + connect \gpio_e13__core__o \gpio_o [13] + connect \gpio_e13__core__oe \gpio_oe [13] + connect \gpio_e13__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [13] + connect \gpio_e13__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [13] + connect \gpio_e13__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [13] + connect \gpio_e14__core__i \gpio_i [14] + connect \gpio_e14__core__o \gpio_o [14] + connect \gpio_e14__core__oe \gpio_oe [14] + connect \gpio_e14__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [14] + connect \gpio_e14__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [14] + connect \gpio_e14__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [14] + connect \gpio_e15__core__i \gpio_i [15] + connect \gpio_e15__core__o \gpio_o [15] + connect \gpio_e15__core__oe \gpio_oe [15] + connect \gpio_e15__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [15] + connect \gpio_e15__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [15] + connect \gpio_e15__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [15] + connect \gpio_e8__core__i \gpio_i [8] + connect \gpio_e8__core__o \gpio_o [8] + connect \gpio_e8__core__oe \gpio_oe [8] + connect \gpio_e8__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [8] + connect \gpio_e8__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [8] + connect \gpio_e8__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [8] + connect \gpio_e9__core__i \gpio_i [9] + connect \gpio_e9__core__o \gpio_o [9] + connect \gpio_e9__core__oe \gpio_oe [9] + connect \gpio_e9__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [9] + connect \gpio_e9__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [9] + connect \gpio_e9__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [9] + connect \gpio_s0__core__i \gpio_i [0] + connect \gpio_s0__core__o \gpio_o [0] + connect \gpio_s0__core__oe \gpio_oe [0] + connect \gpio_s0__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [0] + connect \gpio_s0__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [0] + connect \gpio_s0__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [0] + connect \gpio_s1__core__i \gpio_i [1] + connect \gpio_s1__core__o \gpio_o [1] + connect \gpio_s1__core__oe \gpio_oe [1] + connect \gpio_s1__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [1] + connect \gpio_s1__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [1] + connect \gpio_s1__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [1] + connect \gpio_s2__core__i \gpio_i [2] + connect \gpio_s2__core__o \gpio_o [2] + connect \gpio_s2__core__oe \gpio_oe [2] + connect \gpio_s2__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [2] + connect \gpio_s2__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [2] + connect \gpio_s2__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [2] + connect \gpio_s3__core__i \gpio_i [3] + connect \gpio_s3__core__o \gpio_o [3] + connect \gpio_s3__core__oe \gpio_oe [3] + connect \gpio_s3__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [3] + connect \gpio_s3__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [3] + connect \gpio_s3__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [3] + connect \gpio_s4__core__i \gpio_i [4] + connect \gpio_s4__core__o \gpio_o [4] + connect \gpio_s4__core__oe \gpio_oe [4] + connect \gpio_s4__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [4] + connect \gpio_s4__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [4] + connect \gpio_s4__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [4] + connect \gpio_s5__core__i \gpio_i [5] + connect \gpio_s5__core__o \gpio_o [5] + connect \gpio_s5__core__oe \gpio_oe [5] + connect \gpio_s5__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [5] + connect \gpio_s5__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [5] + connect \gpio_s5__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [5] + connect \gpio_s6__core__i \gpio_i [6] + connect \gpio_s6__core__o \gpio_o [6] + connect \gpio_s6__core__oe \gpio_oe [6] + connect \gpio_s6__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [6] + connect \gpio_s6__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [6] + connect \gpio_s6__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [6] + connect \gpio_s7__core__i \gpio_i [7] + connect \gpio_s7__core__o \gpio_o [7] + connect \gpio_s7__core__oe \gpio_oe [7] + connect \gpio_s7__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [7] + connect \gpio_s7__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [7] + connect \gpio_s7__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [7] + connect \ibus__ack \main_libresocsim_libresoc_ibus_ack + connect \ibus__adr \main_libresocsim_libresoc_ibus_adr + connect \ibus__bte 1'0 + connect \ibus__cti 1'0 + connect \ibus__cyc \main_libresocsim_libresoc_ibus_cyc + connect \ibus__dat_r \main_libresocsim_libresoc_ibus_dat_r + connect \ibus__dat_w \main_libresocsim_libresoc_ibus_dat_w + connect \ibus__err \main_libresocsim_libresoc_ibus_err + connect \ibus__sel \main_libresocsim_libresoc_ibus_sel + connect \ibus__stb \main_libresocsim_libresoc_ibus_stb + connect \ibus__we \main_libresocsim_libresoc_ibus_we + connect \icp_wb__ack \main_libresocsim_libresoc_xics_icp_ack + connect \icp_wb__adr \main_libresocsim_libresoc_xics_icp_adr + connect \icp_wb__cyc \main_libresocsim_libresoc_xics_icp_cyc + connect \icp_wb__dat_r \main_libresocsim_libresoc_xics_icp_dat_r + connect \icp_wb__dat_w \main_libresocsim_libresoc_xics_icp_dat_w + connect \icp_wb__err \main_libresocsim_libresoc_xics_icp_err + connect \icp_wb__sel \main_libresocsim_libresoc_xics_icp_sel + connect \icp_wb__stb \main_libresocsim_libresoc_xics_icp_stb + connect \icp_wb__we \main_libresocsim_libresoc_xics_icp_we + connect \ics_wb__ack \main_libresocsim_libresoc_xics_ics_ack + connect \ics_wb__adr \main_libresocsim_libresoc_xics_ics_adr + connect \ics_wb__cyc \main_libresocsim_libresoc_xics_ics_cyc + connect \ics_wb__dat_r \main_libresocsim_libresoc_xics_ics_dat_r + connect \ics_wb__dat_w \main_libresocsim_libresoc_xics_ics_dat_w + connect \ics_wb__err \main_libresocsim_libresoc_xics_ics_err + connect \ics_wb__sel \main_libresocsim_libresoc_xics_ics_sel + connect \ics_wb__stb \main_libresocsim_libresoc_xics_ics_stb + connect \ics_wb__we \main_libresocsim_libresoc_xics_ics_we + connect \int_level_i \main_libresocsim_libresoc_interrupt + connect \jtag_wb__ack \main_libresocsim_libresoc_jtag_wb_ack + connect \jtag_wb__adr \main_libresocsim_libresoc_jtag_wb_adr + connect \jtag_wb__cyc \main_libresocsim_libresoc_jtag_wb_cyc + connect \jtag_wb__dat_r \main_libresocsim_libresoc_jtag_wb_dat_r + connect \jtag_wb__dat_w \main_libresocsim_libresoc_jtag_wb_dat_w + connect \jtag_wb__err \main_libresocsim_libresoc_jtag_wb_err + connect \jtag_wb__sel \main_libresocsim_libresoc_jtag_wb_sel + connect \jtag_wb__stb \main_libresocsim_libresoc_jtag_wb_stb + connect \jtag_wb__we \main_libresocsim_libresoc_jtag_wb_we + connect \memerr_o \main_libresocsim_libresoc1 + connect \mspi0_clk__core__o \spimaster_clk + connect \mspi0_clk__pad__o \main_libresocsim_libresoc_constraintmanager_obj_spimaster_clk + connect \mspi0_cs_n__core__o \spimaster_cs_n + connect \mspi0_cs_n__pad__o \main_libresocsim_libresoc_constraintmanager_obj_spimaster_cs_n + connect \mspi0_miso__core__i \spimaster_miso + connect \mspi0_miso__pad__i \main_libresocsim_libresoc_constraintmanager_obj_spimaster_miso + connect \mspi0_mosi__core__o \spimaster_mosi + connect \mspi0_mosi__pad__o \main_libresocsim_libresoc_constraintmanager_obj_spimaster_mosi + connect \mspi1_clk__core__o \spisdcard_clk + connect \mspi1_clk__pad__o \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_clk + connect \mspi1_cs_n__core__o \spisdcard_cs_n + connect \mspi1_cs_n__pad__o \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_cs_n + connect \mspi1_miso__core__i \spisdcard_miso + connect \mspi1_miso__pad__i \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_miso + connect \mspi1_mosi__core__o \spisdcard_mosi + connect \mspi1_mosi__pad__o \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_mosi + connect \mtwi_scl__core__o \i2c_scl + connect \mtwi_scl__pad__o \main_libresocsim_libresoc_constraintmanager_obj_i2c_scl + connect \mtwi_sda__core__i \i2c_sda_i + connect \mtwi_sda__core__o \i2c_sda_o + connect \mtwi_sda__core__oe \i2c_sda_oe + connect \mtwi_sda__pad__i \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i + connect \mtwi_sda__pad__o \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_o + connect \mtwi_sda__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_oe + connect \pc_i 1'0 + connect \pc_i_ok 1'0 + connect \pc_o \main_libresocsim_libresoc2 + connect \pll_18_o \main_libresocsim_libresoc_pll_18_o + connect \pll_lck_o \main_libresocsim_libresoc_pll_lck_o + connect \pwm_0__core__o \pwm [0] + connect \pwm_0__pad__o \pwm_1 [0] + connect \pwm_1__core__o \pwm [1] + connect \pwm_1__pad__o \pwm_1 [1] + connect \rst $or$ls180.v:10706$3077_Y + connect \sd0_clk__core__o \sdcard_clk + connect \sd0_clk__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdcard_clk + connect \sd0_cmd__core__i \sdcard_cmd_i + connect \sd0_cmd__core__o \sdcard_cmd_o + connect \sd0_cmd__core__oe \sdcard_cmd_oe + connect \sd0_cmd__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i + connect \sd0_cmd__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_o + connect \sd0_cmd__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_oe + connect \sd0_data0__core__i \sdcard_cmd_i + connect \sd0_data0__core__o \sdcard_cmd_o + connect \sd0_data0__core__oe \sdcard_cmd_oe + connect \sd0_data0__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i + connect \sd0_data0__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_o + connect \sd0_data0__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_oe + connect \sd0_data1__core__i \sdcard_cmd_i + connect \sd0_data1__core__o \sdcard_cmd_o + connect \sd0_data1__core__oe \sdcard_cmd_oe + connect \sd0_data1__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i + connect \sd0_data1__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_o + connect \sd0_data1__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_oe + connect \sd0_data2__core__i \sdcard_cmd_i + connect \sd0_data2__core__o \sdcard_cmd_o + connect \sd0_data2__core__oe \sdcard_cmd_oe + connect \sd0_data2__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i + connect \sd0_data2__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_o + connect \sd0_data2__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_oe + connect \sd0_data3__core__i \sdcard_cmd_i + connect \sd0_data3__core__o \sdcard_cmd_o + connect \sd0_data3__core__oe \sdcard_cmd_oe + connect \sd0_data3__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i + connect \sd0_data3__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_o + connect \sd0_data3__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_oe + connect \sdr_a_0__core__o \sdram_a [0] + connect \sdr_a_0__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_a [0] + connect \sdr_a_10__core__o \sdram_a [10] + connect \sdr_a_10__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_a [10] + connect \sdr_a_11__core__o \sdram_a [11] + connect \sdr_a_11__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_a [11] + connect \sdr_a_12__core__o \sdram_a [12] + connect \sdr_a_12__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_a [12] + connect \sdr_a_1__core__o \sdram_a [1] + connect \sdr_a_1__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_a [1] + connect \sdr_a_2__core__o \sdram_a [2] + connect \sdr_a_2__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_a [2] + connect \sdr_a_3__core__o \sdram_a [3] + connect \sdr_a_3__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_a [3] + connect \sdr_a_4__core__o \sdram_a [4] + connect \sdr_a_4__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_a [4] + connect \sdr_a_5__core__o \sdram_a [5] + connect \sdr_a_5__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_a [5] + connect \sdr_a_6__core__o \sdram_a [6] + connect \sdr_a_6__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_a [6] + connect \sdr_a_7__core__o \sdram_a [7] + connect \sdr_a_7__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_a [7] + connect \sdr_a_8__core__o \sdram_a [8] + connect \sdr_a_8__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_a [8] + connect \sdr_a_9__core__o \sdram_a [9] + connect \sdr_a_9__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_a [9] + connect \sdr_ba_0__core__o \sdram_ba [0] + connect \sdr_ba_0__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_ba [0] + connect \sdr_ba_1__core__o \sdram_ba [1] + connect \sdr_ba_1__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_ba [1] + connect \sdr_cas_n__core__o \sdram_cas_n + connect \sdr_cas_n__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_cas_n + connect \sdr_cke__core__o \sdram_cke + connect \sdr_cke__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_cke + connect \sdr_clock__core__o \sdram_clock + connect \sdr_clock__pad__o \sdram_clock_1 + connect \sdr_cs_n__core__o \sdram_cs_n + connect \sdr_cs_n__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_cs_n + connect \sdr_dm_0__core__o \sdram_dm [0] + connect \sdr_dm_0__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dm [0] + connect \sdr_dm_1__core__i \sdram_dq_i [1] + connect \sdr_dm_1__core__o \sdram_dq_o [1] + connect \sdr_dm_1__core__oe \sdram_dq_oe + connect \sdr_dm_1__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [1] + connect \sdr_dm_1__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [1] + connect \sdr_dm_1__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe + connect \sdr_dq_0__core__i \sdram_dq_i [0] + connect \sdr_dq_0__core__o \sdram_dq_o [0] + connect \sdr_dq_0__core__oe \sdram_dq_oe + connect \sdr_dq_0__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [0] + connect \sdr_dq_0__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [0] + connect \sdr_dq_0__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe + connect \sdr_dq_10__core__i \sdram_dq_i [10] + connect \sdr_dq_10__core__o \sdram_dq_o [10] + connect \sdr_dq_10__core__oe \sdram_dq_oe + connect \sdr_dq_10__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [10] + connect \sdr_dq_10__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [10] + connect \sdr_dq_10__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe + connect \sdr_dq_11__core__i \sdram_dq_i [11] + connect \sdr_dq_11__core__o \sdram_dq_o [11] + connect \sdr_dq_11__core__oe \sdram_dq_oe + connect \sdr_dq_11__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [11] + connect \sdr_dq_11__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [11] + connect \sdr_dq_11__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe + connect \sdr_dq_12__core__i \sdram_dq_i [12] + connect \sdr_dq_12__core__o \sdram_dq_o [12] + connect \sdr_dq_12__core__oe \sdram_dq_oe + connect \sdr_dq_12__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [12] + connect \sdr_dq_12__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [12] + connect \sdr_dq_12__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe + connect \sdr_dq_13__core__i \sdram_dq_i [13] + connect \sdr_dq_13__core__o \sdram_dq_o [13] + connect \sdr_dq_13__core__oe \sdram_dq_oe + connect \sdr_dq_13__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [13] + connect \sdr_dq_13__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [13] + connect \sdr_dq_13__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe + connect \sdr_dq_14__core__i \sdram_dq_i [14] + connect \sdr_dq_14__core__o \sdram_dq_o [14] + connect \sdr_dq_14__core__oe \sdram_dq_oe + connect \sdr_dq_14__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [14] + connect \sdr_dq_14__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [14] + connect \sdr_dq_14__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe + connect \sdr_dq_15__core__i \sdram_dq_i [15] + connect \sdr_dq_15__core__o \sdram_dq_o [15] + connect \sdr_dq_15__core__oe \sdram_dq_oe + connect \sdr_dq_15__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [15] + connect \sdr_dq_15__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [15] + connect \sdr_dq_15__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe + connect \sdr_dq_1__core__i \sdram_dq_i [1] + connect \sdr_dq_1__core__o \sdram_dq_o [1] + connect \sdr_dq_1__core__oe \sdram_dq_oe + connect \sdr_dq_1__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [1] + connect \sdr_dq_1__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [1] + connect \sdr_dq_1__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe + connect \sdr_dq_2__core__i \sdram_dq_i [2] + connect \sdr_dq_2__core__o \sdram_dq_o [2] + connect \sdr_dq_2__core__oe \sdram_dq_oe + connect \sdr_dq_2__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [2] + connect \sdr_dq_2__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [2] + connect \sdr_dq_2__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe + connect \sdr_dq_3__core__i \sdram_dq_i [3] + connect \sdr_dq_3__core__o \sdram_dq_o [3] + connect \sdr_dq_3__core__oe \sdram_dq_oe + connect \sdr_dq_3__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [3] + connect \sdr_dq_3__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [3] + connect \sdr_dq_3__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe + connect \sdr_dq_4__core__i \sdram_dq_i [4] + connect \sdr_dq_4__core__o \sdram_dq_o [4] + connect \sdr_dq_4__core__oe \sdram_dq_oe + connect \sdr_dq_4__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [4] + connect \sdr_dq_4__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [4] + connect \sdr_dq_4__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe + connect \sdr_dq_5__core__i \sdram_dq_i [5] + connect \sdr_dq_5__core__o \sdram_dq_o [5] + connect \sdr_dq_5__core__oe \sdram_dq_oe + connect \sdr_dq_5__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [5] + connect \sdr_dq_5__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [5] + connect \sdr_dq_5__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe + connect \sdr_dq_6__core__i \sdram_dq_i [6] + connect \sdr_dq_6__core__o \sdram_dq_o [6] + connect \sdr_dq_6__core__oe \sdram_dq_oe + connect \sdr_dq_6__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [6] + connect \sdr_dq_6__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [6] + connect \sdr_dq_6__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe + connect \sdr_dq_7__core__i \sdram_dq_i [7] + connect \sdr_dq_7__core__o \sdram_dq_o [7] + connect \sdr_dq_7__core__oe \sdram_dq_oe + connect \sdr_dq_7__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [7] + connect \sdr_dq_7__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [7] + connect \sdr_dq_7__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe + connect \sdr_dq_8__core__i \sdram_dq_i [8] + connect \sdr_dq_8__core__o \sdram_dq_o [8] + connect \sdr_dq_8__core__oe \sdram_dq_oe + connect \sdr_dq_8__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [8] + connect \sdr_dq_8__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [8] + connect \sdr_dq_8__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe + connect \sdr_dq_9__core__i \sdram_dq_i [9] + connect \sdr_dq_9__core__o \sdram_dq_o [9] + connect \sdr_dq_9__core__oe \sdram_dq_oe + connect \sdr_dq_9__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [9] + connect \sdr_dq_9__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [9] + connect \sdr_dq_9__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe + connect \sdr_ras_n__core__o \sdram_ras_n + connect \sdr_ras_n__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_ras_n + connect \sdr_we_n__core__o \sdram_we_n + connect \sdr_we_n__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_we_n + connect \sram4k_0_wb__ack \main_libresocsim_libresoc_interface0_ack + connect \sram4k_0_wb__adr \main_libresocsim_libresoc_interface0_adr + connect \sram4k_0_wb__bte \main_libresocsim_libresoc_interface0_bte + connect \sram4k_0_wb__cti \main_libresocsim_libresoc_interface0_cti + connect \sram4k_0_wb__cyc \main_libresocsim_libresoc_interface0_cyc + connect \sram4k_0_wb__dat_r \main_libresocsim_libresoc_interface0_dat_r + connect \sram4k_0_wb__dat_w \main_libresocsim_libresoc_interface0_dat_w + connect \sram4k_0_wb__err \main_libresocsim_libresoc_interface0_err + connect \sram4k_0_wb__sel \main_libresocsim_libresoc_interface0_sel + connect \sram4k_0_wb__stb \main_libresocsim_libresoc_interface0_stb + connect \sram4k_0_wb__we \main_libresocsim_libresoc_interface0_we + connect \sram4k_1_wb__ack \main_libresocsim_libresoc_interface1_ack + connect \sram4k_1_wb__adr \main_libresocsim_libresoc_interface1_adr + connect \sram4k_1_wb__bte \main_libresocsim_libresoc_interface1_bte + connect \sram4k_1_wb__cti \main_libresocsim_libresoc_interface1_cti + connect \sram4k_1_wb__cyc \main_libresocsim_libresoc_interface1_cyc + connect \sram4k_1_wb__dat_r \main_libresocsim_libresoc_interface1_dat_r + connect \sram4k_1_wb__dat_w \main_libresocsim_libresoc_interface1_dat_w + connect \sram4k_1_wb__err \main_libresocsim_libresoc_interface1_err + connect \sram4k_1_wb__sel \main_libresocsim_libresoc_interface1_sel + connect \sram4k_1_wb__stb \main_libresocsim_libresoc_interface1_stb + connect \sram4k_1_wb__we \main_libresocsim_libresoc_interface1_we + connect \sram4k_2_wb__ack \main_libresocsim_libresoc_interface2_ack + connect \sram4k_2_wb__adr \main_libresocsim_libresoc_interface2_adr + connect \sram4k_2_wb__bte \main_libresocsim_libresoc_interface2_bte + connect \sram4k_2_wb__cti \main_libresocsim_libresoc_interface2_cti + connect \sram4k_2_wb__cyc \main_libresocsim_libresoc_interface2_cyc + connect \sram4k_2_wb__dat_r \main_libresocsim_libresoc_interface2_dat_r + connect \sram4k_2_wb__dat_w \main_libresocsim_libresoc_interface2_dat_w + connect \sram4k_2_wb__err \main_libresocsim_libresoc_interface2_err + connect \sram4k_2_wb__sel \main_libresocsim_libresoc_interface2_sel + connect \sram4k_2_wb__stb \main_libresocsim_libresoc_interface2_stb + connect \sram4k_2_wb__we \main_libresocsim_libresoc_interface2_we + connect \sram4k_3_wb__ack \main_libresocsim_libresoc_interface3_ack + connect \sram4k_3_wb__adr \main_libresocsim_libresoc_interface3_adr + connect \sram4k_3_wb__bte \main_libresocsim_libresoc_interface3_bte + connect \sram4k_3_wb__cti \main_libresocsim_libresoc_interface3_cti + connect \sram4k_3_wb__cyc \main_libresocsim_libresoc_interface3_cyc + connect \sram4k_3_wb__dat_r \main_libresocsim_libresoc_interface3_dat_r + connect \sram4k_3_wb__dat_w \main_libresocsim_libresoc_interface3_dat_w + connect \sram4k_3_wb__err \main_libresocsim_libresoc_interface3_err + connect \sram4k_3_wb__sel \main_libresocsim_libresoc_interface3_sel + connect \sram4k_3_wb__stb \main_libresocsim_libresoc_interface3_stb + connect \sram4k_3_wb__we \main_libresocsim_libresoc_interface3_we + end + attribute \src "ls180.v:0.0-0.0" + process $proc$ls180.v:0$4086 + sync always + sync init + end + attribute \src "ls180.v:0.0-0.0" + process $proc$ls180.v:0$4087 + sync always + sync init + end + attribute \src "ls180.v:0.0-0.0" + process $proc$ls180.v:0$4088 + sync always + sync init + end + attribute \src "ls180.v:0.0-0.0" + process $proc$ls180.v:0$4089 + sync always + sync init + end + attribute \src "ls180.v:0.0-0.0" + process $proc$ls180.v:0$4090 + sync always + sync init + end + attribute \src "ls180.v:100.11-100.56" + process $proc$ls180.v:100$3144 + assign { } { } + assign $1\main_libresocsim_libresoc_xics_ics_sel[3:0] 4'0000 + sync always + sync init + update \main_libresocsim_libresoc_xics_ics_sel $1\main_libresocsim_libresoc_xics_ics_sel[3:0] + end + attribute \src "ls180.v:1009.5-1009.40" + process $proc$ls180.v:1009$3478 + assign { } { } + assign $0\main_uart_tx_fifo_sink_first[0:0] 1'0 + sync always + update \main_uart_tx_fifo_sink_first $0\main_uart_tx_fifo_sink_first[0:0] + sync init + end + attribute \src "ls180.v:101.5-101.50" + process $proc$ls180.v:101$3145 + assign { } { } + assign $1\main_libresocsim_libresoc_xics_ics_cyc[0:0] 1'0 + sync always + sync init + update \main_libresocsim_libresoc_xics_ics_cyc $1\main_libresocsim_libresoc_xics_ics_cyc[0:0] + end + attribute \src "ls180.v:1010.5-1010.39" + process $proc$ls180.v:1010$3479 + assign { } { } + assign $0\main_uart_tx_fifo_sink_last[0:0] 1'0 + sync always + update \main_uart_tx_fifo_sink_last $0\main_uart_tx_fifo_sink_last[0:0] + sync init + end + attribute \src "ls180.v:1018.5-1018.38" + process $proc$ls180.v:1018$3480 + assign { } { } + assign $1\main_uart_tx_fifo_readable[0:0] 1'0 + sync always + sync init + update \main_uart_tx_fifo_readable $1\main_uart_tx_fifo_readable[0:0] + end + attribute \src "ls180.v:102.5-102.50" + process $proc$ls180.v:102$3146 + assign { } { } + assign $1\main_libresocsim_libresoc_xics_ics_stb[0:0] 1'0 + sync always + sync init + update \main_libresocsim_libresoc_xics_ics_stb $1\main_libresocsim_libresoc_xics_ics_stb[0:0] + end + attribute \src "ls180.v:1025.11-1025.42" + process $proc$ls180.v:1025$3481 + assign { } { } + assign $1\main_uart_tx_fifo_level0[4:0] 5'00000 + sync always + sync init + update \main_uart_tx_fifo_level0 $1\main_uart_tx_fifo_level0[4:0] + end + attribute \src "ls180.v:1026.5-1026.37" + process $proc$ls180.v:1026$3482 + assign { } { } + assign $0\main_uart_tx_fifo_replace[0:0] 1'0 + sync always + update \main_uart_tx_fifo_replace $0\main_uart_tx_fifo_replace[0:0] + sync init + end + attribute \src "ls180.v:1027.11-1027.43" + process $proc$ls180.v:1027$3483 + assign { } { } + assign $1\main_uart_tx_fifo_produce[3:0] 4'0000 + sync always + sync init + update \main_uart_tx_fifo_produce $1\main_uart_tx_fifo_produce[3:0] + end + attribute \src "ls180.v:1028.11-1028.43" + process $proc$ls180.v:1028$3484 + assign { } { } + assign $1\main_uart_tx_fifo_consume[3:0] 4'0000 + sync always + sync init + update \main_uart_tx_fifo_consume $1\main_uart_tx_fifo_consume[3:0] + end + attribute \src "ls180.v:1029.11-1029.46" + process $proc$ls180.v:1029$3485 + assign { } { } + assign $1\main_uart_tx_fifo_wrport_adr[3:0] 4'0000 + sync always + sync init + update \main_uart_tx_fifo_wrport_adr $1\main_uart_tx_fifo_wrport_adr[3:0] + end + attribute \src "ls180.v:10350.1-10368.4" + process $proc$ls180.v:10350$2891 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0$memwr$\mem$ls180.v:10366$8_ADDR[5:0]$2913 6'xxxxxx + assign $0$memwr$\mem$ls180.v:10366$8_DATA[63:0]$2914 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem$ls180.v:10366$8_EN[63:0]$2915 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem$ls180.v:10364$7_ADDR[5:0]$2910 6'xxxxxx + assign $0$memwr$\mem$ls180.v:10364$7_DATA[63:0]$2911 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem$ls180.v:10364$7_EN[63:0]$2912 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem$ls180.v:10362$6_ADDR[5:0]$2907 6'xxxxxx + assign $0$memwr$\mem$ls180.v:10362$6_DATA[63:0]$2908 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem$ls180.v:10362$6_EN[63:0]$2909 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem$ls180.v:10360$5_ADDR[5:0]$2904 6'xxxxxx + assign $0$memwr$\mem$ls180.v:10360$5_DATA[63:0]$2905 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem$ls180.v:10360$5_EN[63:0]$2906 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem$ls180.v:10358$4_ADDR[5:0]$2901 6'xxxxxx + assign $0$memwr$\mem$ls180.v:10358$4_DATA[63:0]$2902 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem$ls180.v:10358$4_EN[63:0]$2903 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem$ls180.v:10356$3_ADDR[5:0]$2898 6'xxxxxx + assign $0$memwr$\mem$ls180.v:10356$3_DATA[63:0]$2899 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem$ls180.v:10356$3_EN[63:0]$2900 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem$ls180.v:10354$2_ADDR[5:0]$2895 6'xxxxxx + assign $0$memwr$\mem$ls180.v:10354$2_DATA[63:0]$2896 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem$ls180.v:10354$2_EN[63:0]$2897 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem$ls180.v:10352$1_ADDR[5:0]$2892 6'xxxxxx + assign $0$memwr$\mem$ls180.v:10352$1_DATA[63:0]$2893 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem$ls180.v:10352$1_EN[63:0]$2894 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\memadr[5:0] \main_libresocsim_adr + attribute \src "ls180.v:10351.2-10352.65" + switch \main_libresocsim_we [0] + attribute \src "ls180.v:10351.6-10351.28" + case 1'1 + assign $0$memwr$\mem$ls180.v:10352$1_ADDR[5:0]$2892 \main_libresocsim_adr + assign $0$memwr$\mem$ls180.v:10352$1_DATA[63:0]$2893 { 56'00000000000000000000000000000000000000000000000000000000 \main_libresocsim_dat_w [7:0] } + assign $0$memwr$\mem$ls180.v:10352$1_EN[63:0]$2894 64'0000000000000000000000000000000000000000000000000000000011111111 + case + end + attribute \src "ls180.v:10353.2-10354.67" + switch \main_libresocsim_we [1] + attribute \src "ls180.v:10353.6-10353.28" + case 1'1 + assign $0$memwr$\mem$ls180.v:10354$2_ADDR[5:0]$2895 \main_libresocsim_adr + assign $0$memwr$\mem$ls180.v:10354$2_DATA[63:0]$2896 { 48'000000000000000000000000000000000000000000000000 \main_libresocsim_dat_w [15:8] 8'xxxxxxxx } + assign $0$memwr$\mem$ls180.v:10354$2_EN[63:0]$2897 64'0000000000000000000000000000000000000000000000001111111100000000 + case + end + attribute \src "ls180.v:10355.2-10356.69" + switch \main_libresocsim_we [2] + attribute \src "ls180.v:10355.6-10355.28" + case 1'1 + assign $0$memwr$\mem$ls180.v:10356$3_ADDR[5:0]$2898 \main_libresocsim_adr + assign $0$memwr$\mem$ls180.v:10356$3_DATA[63:0]$2899 { 40'0000000000000000000000000000000000000000 \main_libresocsim_dat_w [23:16] 16'xxxxxxxxxxxxxxxx } + assign $0$memwr$\mem$ls180.v:10356$3_EN[63:0]$2900 64'0000000000000000000000000000000000000000111111110000000000000000 + case + end + attribute \src "ls180.v:10357.2-10358.69" + switch \main_libresocsim_we [3] + attribute \src "ls180.v:10357.6-10357.28" + case 1'1 + assign $0$memwr$\mem$ls180.v:10358$4_ADDR[5:0]$2901 \main_libresocsim_adr + assign $0$memwr$\mem$ls180.v:10358$4_DATA[63:0]$2902 { 32'00000000000000000000000000000000 \main_libresocsim_dat_w [31:24] 24'xxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem$ls180.v:10358$4_EN[63:0]$2903 64'0000000000000000000000000000000011111111000000000000000000000000 + case + end + attribute \src "ls180.v:10359.2-10360.69" + switch \main_libresocsim_we [4] + attribute \src "ls180.v:10359.6-10359.28" + case 1'1 + assign $0$memwr$\mem$ls180.v:10360$5_ADDR[5:0]$2904 \main_libresocsim_adr + assign $0$memwr$\mem$ls180.v:10360$5_DATA[63:0]$2905 { 24'000000000000000000000000 \main_libresocsim_dat_w [39:32] 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem$ls180.v:10360$5_EN[63:0]$2906 64'0000000000000000000000001111111100000000000000000000000000000000 + case + end + attribute \src "ls180.v:10361.2-10362.69" + switch \main_libresocsim_we [5] + attribute \src "ls180.v:10361.6-10361.28" + case 1'1 + assign $0$memwr$\mem$ls180.v:10362$6_ADDR[5:0]$2907 \main_libresocsim_adr + assign $0$memwr$\mem$ls180.v:10362$6_DATA[63:0]$2908 { 16'0000000000000000 \main_libresocsim_dat_w [47:40] 40'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem$ls180.v:10362$6_EN[63:0]$2909 64'0000000000000000111111110000000000000000000000000000000000000000 + case + end + attribute \src "ls180.v:10363.2-10364.69" + switch \main_libresocsim_we [6] + attribute \src "ls180.v:10363.6-10363.28" + case 1'1 + assign $0$memwr$\mem$ls180.v:10364$7_ADDR[5:0]$2910 \main_libresocsim_adr + assign $0$memwr$\mem$ls180.v:10364$7_DATA[63:0]$2911 { 8'00000000 \main_libresocsim_dat_w [55:48] 48'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem$ls180.v:10364$7_EN[63:0]$2912 64'0000000011111111000000000000000000000000000000000000000000000000 + case + end + attribute \src "ls180.v:10365.2-10366.69" + switch \main_libresocsim_we [7] + attribute \src "ls180.v:10365.6-10365.28" + case 1'1 + assign $0$memwr$\mem$ls180.v:10366$8_ADDR[5:0]$2913 \main_libresocsim_adr + assign $0$memwr$\mem$ls180.v:10366$8_DATA[63:0]$2914 { \main_libresocsim_dat_w [63:56] 56'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem$ls180.v:10366$8_EN[63:0]$2915 64'1111111100000000000000000000000000000000000000000000000000000000 + case + end + sync posedge \sys_clk_1 + update \memadr $0\memadr[5:0] + update $memwr$\mem$ls180.v:10352$1_ADDR $0$memwr$\mem$ls180.v:10352$1_ADDR[5:0]$2892 + update $memwr$\mem$ls180.v:10352$1_DATA $0$memwr$\mem$ls180.v:10352$1_DATA[63:0]$2893 + update $memwr$\mem$ls180.v:10352$1_EN $0$memwr$\mem$ls180.v:10352$1_EN[63:0]$2894 + update $memwr$\mem$ls180.v:10354$2_ADDR $0$memwr$\mem$ls180.v:10354$2_ADDR[5:0]$2895 + update $memwr$\mem$ls180.v:10354$2_DATA $0$memwr$\mem$ls180.v:10354$2_DATA[63:0]$2896 + update $memwr$\mem$ls180.v:10354$2_EN $0$memwr$\mem$ls180.v:10354$2_EN[63:0]$2897 + update $memwr$\mem$ls180.v:10356$3_ADDR $0$memwr$\mem$ls180.v:10356$3_ADDR[5:0]$2898 + update $memwr$\mem$ls180.v:10356$3_DATA $0$memwr$\mem$ls180.v:10356$3_DATA[63:0]$2899 + update $memwr$\mem$ls180.v:10356$3_EN $0$memwr$\mem$ls180.v:10356$3_EN[63:0]$2900 + update $memwr$\mem$ls180.v:10358$4_ADDR $0$memwr$\mem$ls180.v:10358$4_ADDR[5:0]$2901 + update $memwr$\mem$ls180.v:10358$4_DATA $0$memwr$\mem$ls180.v:10358$4_DATA[63:0]$2902 + update $memwr$\mem$ls180.v:10358$4_EN $0$memwr$\mem$ls180.v:10358$4_EN[63:0]$2903 + update $memwr$\mem$ls180.v:10360$5_ADDR $0$memwr$\mem$ls180.v:10360$5_ADDR[5:0]$2904 + update $memwr$\mem$ls180.v:10360$5_DATA $0$memwr$\mem$ls180.v:10360$5_DATA[63:0]$2905 + update $memwr$\mem$ls180.v:10360$5_EN $0$memwr$\mem$ls180.v:10360$5_EN[63:0]$2906 + update $memwr$\mem$ls180.v:10362$6_ADDR $0$memwr$\mem$ls180.v:10362$6_ADDR[5:0]$2907 + update $memwr$\mem$ls180.v:10362$6_DATA $0$memwr$\mem$ls180.v:10362$6_DATA[63:0]$2908 + update $memwr$\mem$ls180.v:10362$6_EN $0$memwr$\mem$ls180.v:10362$6_EN[63:0]$2909 + update $memwr$\mem$ls180.v:10364$7_ADDR $0$memwr$\mem$ls180.v:10364$7_ADDR[5:0]$2910 + update $memwr$\mem$ls180.v:10364$7_DATA $0$memwr$\mem$ls180.v:10364$7_DATA[63:0]$2911 + update $memwr$\mem$ls180.v:10364$7_EN $0$memwr$\mem$ls180.v:10364$7_EN[63:0]$2912 + update $memwr$\mem$ls180.v:10366$8_ADDR $0$memwr$\mem$ls180.v:10366$8_ADDR[5:0]$2913 + update $memwr$\mem$ls180.v:10366$8_DATA $0$memwr$\mem$ls180.v:10366$8_DATA[63:0]$2914 + update $memwr$\mem$ls180.v:10366$8_EN $0$memwr$\mem$ls180.v:10366$8_EN[63:0]$2915 + end + attribute \src "ls180.v:10378.1-10396.4" + process $proc$ls180.v:10378$2917 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0$memwr$\mem_1$ls180.v:10394$16_ADDR[5:0]$2939 6'xxxxxx + assign $0$memwr$\mem_1$ls180.v:10394$16_DATA[63:0]$2940 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_1$ls180.v:10394$16_EN[63:0]$2941 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_1$ls180.v:10392$15_ADDR[5:0]$2936 6'xxxxxx + assign $0$memwr$\mem_1$ls180.v:10392$15_DATA[63:0]$2937 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_1$ls180.v:10392$15_EN[63:0]$2938 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_1$ls180.v:10390$14_ADDR[5:0]$2933 6'xxxxxx + assign $0$memwr$\mem_1$ls180.v:10390$14_DATA[63:0]$2934 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_1$ls180.v:10390$14_EN[63:0]$2935 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_1$ls180.v:10388$13_ADDR[5:0]$2930 6'xxxxxx + assign $0$memwr$\mem_1$ls180.v:10388$13_DATA[63:0]$2931 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_1$ls180.v:10388$13_EN[63:0]$2932 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_1$ls180.v:10386$12_ADDR[5:0]$2927 6'xxxxxx + assign $0$memwr$\mem_1$ls180.v:10386$12_DATA[63:0]$2928 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_1$ls180.v:10386$12_EN[63:0]$2929 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_1$ls180.v:10384$11_ADDR[5:0]$2924 6'xxxxxx + assign $0$memwr$\mem_1$ls180.v:10384$11_DATA[63:0]$2925 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_1$ls180.v:10384$11_EN[63:0]$2926 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_1$ls180.v:10382$10_ADDR[5:0]$2921 6'xxxxxx + assign $0$memwr$\mem_1$ls180.v:10382$10_DATA[63:0]$2922 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_1$ls180.v:10382$10_EN[63:0]$2923 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_1$ls180.v:10380$9_ADDR[5:0]$2918 6'xxxxxx + assign $0$memwr$\mem_1$ls180.v:10380$9_DATA[63:0]$2919 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_1$ls180.v:10380$9_EN[63:0]$2920 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\memadr_1[5:0] \main_sram0_adr + attribute \src "ls180.v:10379.2-10380.55" + switch \main_sram0_we [0] + attribute \src "ls180.v:10379.6-10379.22" + case 1'1 + assign $0$memwr$\mem_1$ls180.v:10380$9_ADDR[5:0]$2918 \main_sram0_adr + assign $0$memwr$\mem_1$ls180.v:10380$9_DATA[63:0]$2919 { 56'00000000000000000000000000000000000000000000000000000000 \main_sram0_dat_w [7:0] } + assign $0$memwr$\mem_1$ls180.v:10380$9_EN[63:0]$2920 64'0000000000000000000000000000000000000000000000000000000011111111 + case + end + attribute \src "ls180.v:10381.2-10382.57" + switch \main_sram0_we [1] + attribute \src "ls180.v:10381.6-10381.22" + case 1'1 + assign $0$memwr$\mem_1$ls180.v:10382$10_ADDR[5:0]$2921 \main_sram0_adr + assign $0$memwr$\mem_1$ls180.v:10382$10_DATA[63:0]$2922 { 48'000000000000000000000000000000000000000000000000 \main_sram0_dat_w [15:8] 8'xxxxxxxx } + assign $0$memwr$\mem_1$ls180.v:10382$10_EN[63:0]$2923 64'0000000000000000000000000000000000000000000000001111111100000000 + case + end + attribute \src "ls180.v:10383.2-10384.59" + switch \main_sram0_we [2] + attribute \src "ls180.v:10383.6-10383.22" + case 1'1 + assign $0$memwr$\mem_1$ls180.v:10384$11_ADDR[5:0]$2924 \main_sram0_adr + assign $0$memwr$\mem_1$ls180.v:10384$11_DATA[63:0]$2925 { 40'0000000000000000000000000000000000000000 \main_sram0_dat_w [23:16] 16'xxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_1$ls180.v:10384$11_EN[63:0]$2926 64'0000000000000000000000000000000000000000111111110000000000000000 + case + end + attribute \src "ls180.v:10385.2-10386.59" + switch \main_sram0_we [3] + attribute \src "ls180.v:10385.6-10385.22" + case 1'1 + assign $0$memwr$\mem_1$ls180.v:10386$12_ADDR[5:0]$2927 \main_sram0_adr + assign $0$memwr$\mem_1$ls180.v:10386$12_DATA[63:0]$2928 { 32'00000000000000000000000000000000 \main_sram0_dat_w [31:24] 24'xxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_1$ls180.v:10386$12_EN[63:0]$2929 64'0000000000000000000000000000000011111111000000000000000000000000 + case + end + attribute \src "ls180.v:10387.2-10388.59" + switch \main_sram0_we [4] + attribute \src "ls180.v:10387.6-10387.22" + case 1'1 + assign $0$memwr$\mem_1$ls180.v:10388$13_ADDR[5:0]$2930 \main_sram0_adr + assign $0$memwr$\mem_1$ls180.v:10388$13_DATA[63:0]$2931 { 24'000000000000000000000000 \main_sram0_dat_w [39:32] 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_1$ls180.v:10388$13_EN[63:0]$2932 64'0000000000000000000000001111111100000000000000000000000000000000 + case + end + attribute \src "ls180.v:10389.2-10390.59" + switch \main_sram0_we [5] + attribute \src "ls180.v:10389.6-10389.22" + case 1'1 + assign $0$memwr$\mem_1$ls180.v:10390$14_ADDR[5:0]$2933 \main_sram0_adr + assign $0$memwr$\mem_1$ls180.v:10390$14_DATA[63:0]$2934 { 16'0000000000000000 \main_sram0_dat_w [47:40] 40'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_1$ls180.v:10390$14_EN[63:0]$2935 64'0000000000000000111111110000000000000000000000000000000000000000 + case + end + attribute \src "ls180.v:10391.2-10392.59" + switch \main_sram0_we [6] + attribute \src "ls180.v:10391.6-10391.22" + case 1'1 + assign $0$memwr$\mem_1$ls180.v:10392$15_ADDR[5:0]$2936 \main_sram0_adr + assign $0$memwr$\mem_1$ls180.v:10392$15_DATA[63:0]$2937 { 8'00000000 \main_sram0_dat_w [55:48] 48'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_1$ls180.v:10392$15_EN[63:0]$2938 64'0000000011111111000000000000000000000000000000000000000000000000 + case + end + attribute \src "ls180.v:10393.2-10394.59" + switch \main_sram0_we [7] + attribute \src "ls180.v:10393.6-10393.22" + case 1'1 + assign $0$memwr$\mem_1$ls180.v:10394$16_ADDR[5:0]$2939 \main_sram0_adr + assign $0$memwr$\mem_1$ls180.v:10394$16_DATA[63:0]$2940 { \main_sram0_dat_w [63:56] 56'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_1$ls180.v:10394$16_EN[63:0]$2941 64'1111111100000000000000000000000000000000000000000000000000000000 + case + end + sync posedge \sys_clk_1 + update \memadr_1 $0\memadr_1[5:0] + update $memwr$\mem_1$ls180.v:10380$9_ADDR $0$memwr$\mem_1$ls180.v:10380$9_ADDR[5:0]$2918 + update $memwr$\mem_1$ls180.v:10380$9_DATA $0$memwr$\mem_1$ls180.v:10380$9_DATA[63:0]$2919 + update $memwr$\mem_1$ls180.v:10380$9_EN $0$memwr$\mem_1$ls180.v:10380$9_EN[63:0]$2920 + update $memwr$\mem_1$ls180.v:10382$10_ADDR $0$memwr$\mem_1$ls180.v:10382$10_ADDR[5:0]$2921 + update $memwr$\mem_1$ls180.v:10382$10_DATA $0$memwr$\mem_1$ls180.v:10382$10_DATA[63:0]$2922 + update $memwr$\mem_1$ls180.v:10382$10_EN $0$memwr$\mem_1$ls180.v:10382$10_EN[63:0]$2923 + update $memwr$\mem_1$ls180.v:10384$11_ADDR $0$memwr$\mem_1$ls180.v:10384$11_ADDR[5:0]$2924 + update $memwr$\mem_1$ls180.v:10384$11_DATA $0$memwr$\mem_1$ls180.v:10384$11_DATA[63:0]$2925 + update $memwr$\mem_1$ls180.v:10384$11_EN $0$memwr$\mem_1$ls180.v:10384$11_EN[63:0]$2926 + update $memwr$\mem_1$ls180.v:10386$12_ADDR $0$memwr$\mem_1$ls180.v:10386$12_ADDR[5:0]$2927 + update $memwr$\mem_1$ls180.v:10386$12_DATA $0$memwr$\mem_1$ls180.v:10386$12_DATA[63:0]$2928 + update $memwr$\mem_1$ls180.v:10386$12_EN $0$memwr$\mem_1$ls180.v:10386$12_EN[63:0]$2929 + update $memwr$\mem_1$ls180.v:10388$13_ADDR $0$memwr$\mem_1$ls180.v:10388$13_ADDR[5:0]$2930 + update $memwr$\mem_1$ls180.v:10388$13_DATA $0$memwr$\mem_1$ls180.v:10388$13_DATA[63:0]$2931 + update $memwr$\mem_1$ls180.v:10388$13_EN $0$memwr$\mem_1$ls180.v:10388$13_EN[63:0]$2932 + update $memwr$\mem_1$ls180.v:10390$14_ADDR $0$memwr$\mem_1$ls180.v:10390$14_ADDR[5:0]$2933 + update $memwr$\mem_1$ls180.v:10390$14_DATA $0$memwr$\mem_1$ls180.v:10390$14_DATA[63:0]$2934 + update $memwr$\mem_1$ls180.v:10390$14_EN $0$memwr$\mem_1$ls180.v:10390$14_EN[63:0]$2935 + update $memwr$\mem_1$ls180.v:10392$15_ADDR $0$memwr$\mem_1$ls180.v:10392$15_ADDR[5:0]$2936 + update $memwr$\mem_1$ls180.v:10392$15_DATA $0$memwr$\mem_1$ls180.v:10392$15_DATA[63:0]$2937 + update $memwr$\mem_1$ls180.v:10392$15_EN $0$memwr$\mem_1$ls180.v:10392$15_EN[63:0]$2938 + update $memwr$\mem_1$ls180.v:10394$16_ADDR $0$memwr$\mem_1$ls180.v:10394$16_ADDR[5:0]$2939 + update $memwr$\mem_1$ls180.v:10394$16_DATA $0$memwr$\mem_1$ls180.v:10394$16_DATA[63:0]$2940 + update $memwr$\mem_1$ls180.v:10394$16_EN $0$memwr$\mem_1$ls180.v:10394$16_EN[63:0]$2941 + end + attribute \src "ls180.v:104.5-104.49" + process $proc$ls180.v:104$3147 + assign { } { } + assign $1\main_libresocsim_libresoc_xics_ics_we[0:0] 1'0 + sync always + sync init + update \main_libresocsim_libresoc_xics_ics_we $1\main_libresocsim_libresoc_xics_ics_we[0:0] + end + attribute \src "ls180.v:10406.1-10424.4" + process $proc$ls180.v:10406$2943 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0$memwr$\mem_2$ls180.v:10422$24_ADDR[5:0]$2965 6'xxxxxx + assign $0$memwr$\mem_2$ls180.v:10422$24_DATA[63:0]$2966 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_2$ls180.v:10422$24_EN[63:0]$2967 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_2$ls180.v:10420$23_ADDR[5:0]$2962 6'xxxxxx + assign $0$memwr$\mem_2$ls180.v:10420$23_DATA[63:0]$2963 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_2$ls180.v:10420$23_EN[63:0]$2964 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_2$ls180.v:10418$22_ADDR[5:0]$2959 6'xxxxxx + assign $0$memwr$\mem_2$ls180.v:10418$22_DATA[63:0]$2960 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_2$ls180.v:10418$22_EN[63:0]$2961 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_2$ls180.v:10416$21_ADDR[5:0]$2956 6'xxxxxx + assign $0$memwr$\mem_2$ls180.v:10416$21_DATA[63:0]$2957 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_2$ls180.v:10416$21_EN[63:0]$2958 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_2$ls180.v:10414$20_ADDR[5:0]$2953 6'xxxxxx + assign $0$memwr$\mem_2$ls180.v:10414$20_DATA[63:0]$2954 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_2$ls180.v:10414$20_EN[63:0]$2955 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_2$ls180.v:10412$19_ADDR[5:0]$2950 6'xxxxxx + assign $0$memwr$\mem_2$ls180.v:10412$19_DATA[63:0]$2951 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_2$ls180.v:10412$19_EN[63:0]$2952 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_2$ls180.v:10410$18_ADDR[5:0]$2947 6'xxxxxx + assign $0$memwr$\mem_2$ls180.v:10410$18_DATA[63:0]$2948 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_2$ls180.v:10410$18_EN[63:0]$2949 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_2$ls180.v:10408$17_ADDR[5:0]$2944 6'xxxxxx + assign $0$memwr$\mem_2$ls180.v:10408$17_DATA[63:0]$2945 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_2$ls180.v:10408$17_EN[63:0]$2946 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\memadr_2[5:0] \main_sram1_adr + attribute \src "ls180.v:10407.2-10408.55" + switch \main_sram1_we [0] + attribute \src "ls180.v:10407.6-10407.22" + case 1'1 + assign $0$memwr$\mem_2$ls180.v:10408$17_ADDR[5:0]$2944 \main_sram1_adr + assign $0$memwr$\mem_2$ls180.v:10408$17_DATA[63:0]$2945 { 56'00000000000000000000000000000000000000000000000000000000 \main_sram1_dat_w [7:0] } + assign $0$memwr$\mem_2$ls180.v:10408$17_EN[63:0]$2946 64'0000000000000000000000000000000000000000000000000000000011111111 + case + end + attribute \src "ls180.v:10409.2-10410.57" + switch \main_sram1_we [1] + attribute \src "ls180.v:10409.6-10409.22" + case 1'1 + assign $0$memwr$\mem_2$ls180.v:10410$18_ADDR[5:0]$2947 \main_sram1_adr + assign $0$memwr$\mem_2$ls180.v:10410$18_DATA[63:0]$2948 { 48'000000000000000000000000000000000000000000000000 \main_sram1_dat_w [15:8] 8'xxxxxxxx } + assign $0$memwr$\mem_2$ls180.v:10410$18_EN[63:0]$2949 64'0000000000000000000000000000000000000000000000001111111100000000 + case + end + attribute \src "ls180.v:10411.2-10412.59" + switch \main_sram1_we [2] + attribute \src "ls180.v:10411.6-10411.22" + case 1'1 + assign $0$memwr$\mem_2$ls180.v:10412$19_ADDR[5:0]$2950 \main_sram1_adr + assign $0$memwr$\mem_2$ls180.v:10412$19_DATA[63:0]$2951 { 40'0000000000000000000000000000000000000000 \main_sram1_dat_w [23:16] 16'xxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_2$ls180.v:10412$19_EN[63:0]$2952 64'0000000000000000000000000000000000000000111111110000000000000000 + case + end + attribute \src "ls180.v:10413.2-10414.59" + switch \main_sram1_we [3] + attribute \src "ls180.v:10413.6-10413.22" + case 1'1 + assign $0$memwr$\mem_2$ls180.v:10414$20_ADDR[5:0]$2953 \main_sram1_adr + assign $0$memwr$\mem_2$ls180.v:10414$20_DATA[63:0]$2954 { 32'00000000000000000000000000000000 \main_sram1_dat_w [31:24] 24'xxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_2$ls180.v:10414$20_EN[63:0]$2955 64'0000000000000000000000000000000011111111000000000000000000000000 + case + end + attribute \src "ls180.v:10415.2-10416.59" + switch \main_sram1_we [4] + attribute \src "ls180.v:10415.6-10415.22" + case 1'1 + assign $0$memwr$\mem_2$ls180.v:10416$21_ADDR[5:0]$2956 \main_sram1_adr + assign $0$memwr$\mem_2$ls180.v:10416$21_DATA[63:0]$2957 { 24'000000000000000000000000 \main_sram1_dat_w [39:32] 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_2$ls180.v:10416$21_EN[63:0]$2958 64'0000000000000000000000001111111100000000000000000000000000000000 + case + end + attribute \src "ls180.v:10417.2-10418.59" + switch \main_sram1_we [5] + attribute \src "ls180.v:10417.6-10417.22" + case 1'1 + assign $0$memwr$\mem_2$ls180.v:10418$22_ADDR[5:0]$2959 \main_sram1_adr + assign $0$memwr$\mem_2$ls180.v:10418$22_DATA[63:0]$2960 { 16'0000000000000000 \main_sram1_dat_w [47:40] 40'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_2$ls180.v:10418$22_EN[63:0]$2961 64'0000000000000000111111110000000000000000000000000000000000000000 + case + end + attribute \src "ls180.v:10419.2-10420.59" + switch \main_sram1_we [6] + attribute \src "ls180.v:10419.6-10419.22" + case 1'1 + assign $0$memwr$\mem_2$ls180.v:10420$23_ADDR[5:0]$2962 \main_sram1_adr + assign $0$memwr$\mem_2$ls180.v:10420$23_DATA[63:0]$2963 { 8'00000000 \main_sram1_dat_w [55:48] 48'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_2$ls180.v:10420$23_EN[63:0]$2964 64'0000000011111111000000000000000000000000000000000000000000000000 + case + end + attribute \src "ls180.v:10421.2-10422.59" + switch \main_sram1_we [7] + attribute \src "ls180.v:10421.6-10421.22" + case 1'1 + assign $0$memwr$\mem_2$ls180.v:10422$24_ADDR[5:0]$2965 \main_sram1_adr + assign $0$memwr$\mem_2$ls180.v:10422$24_DATA[63:0]$2966 { \main_sram1_dat_w [63:56] 56'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_2$ls180.v:10422$24_EN[63:0]$2967 64'1111111100000000000000000000000000000000000000000000000000000000 + case + end + sync posedge \sys_clk_1 + update \memadr_2 $0\memadr_2[5:0] + update $memwr$\mem_2$ls180.v:10408$17_ADDR $0$memwr$\mem_2$ls180.v:10408$17_ADDR[5:0]$2944 + update $memwr$\mem_2$ls180.v:10408$17_DATA $0$memwr$\mem_2$ls180.v:10408$17_DATA[63:0]$2945 + update $memwr$\mem_2$ls180.v:10408$17_EN $0$memwr$\mem_2$ls180.v:10408$17_EN[63:0]$2946 + update $memwr$\mem_2$ls180.v:10410$18_ADDR $0$memwr$\mem_2$ls180.v:10410$18_ADDR[5:0]$2947 + update $memwr$\mem_2$ls180.v:10410$18_DATA $0$memwr$\mem_2$ls180.v:10410$18_DATA[63:0]$2948 + update $memwr$\mem_2$ls180.v:10410$18_EN $0$memwr$\mem_2$ls180.v:10410$18_EN[63:0]$2949 + update $memwr$\mem_2$ls180.v:10412$19_ADDR $0$memwr$\mem_2$ls180.v:10412$19_ADDR[5:0]$2950 + update $memwr$\mem_2$ls180.v:10412$19_DATA $0$memwr$\mem_2$ls180.v:10412$19_DATA[63:0]$2951 + update $memwr$\mem_2$ls180.v:10412$19_EN $0$memwr$\mem_2$ls180.v:10412$19_EN[63:0]$2952 + update $memwr$\mem_2$ls180.v:10414$20_ADDR $0$memwr$\mem_2$ls180.v:10414$20_ADDR[5:0]$2953 + update $memwr$\mem_2$ls180.v:10414$20_DATA $0$memwr$\mem_2$ls180.v:10414$20_DATA[63:0]$2954 + update $memwr$\mem_2$ls180.v:10414$20_EN $0$memwr$\mem_2$ls180.v:10414$20_EN[63:0]$2955 + update $memwr$\mem_2$ls180.v:10416$21_ADDR $0$memwr$\mem_2$ls180.v:10416$21_ADDR[5:0]$2956 + update $memwr$\mem_2$ls180.v:10416$21_DATA $0$memwr$\mem_2$ls180.v:10416$21_DATA[63:0]$2957 + update $memwr$\mem_2$ls180.v:10416$21_EN $0$memwr$\mem_2$ls180.v:10416$21_EN[63:0]$2958 + update $memwr$\mem_2$ls180.v:10418$22_ADDR $0$memwr$\mem_2$ls180.v:10418$22_ADDR[5:0]$2959 + update $memwr$\mem_2$ls180.v:10418$22_DATA $0$memwr$\mem_2$ls180.v:10418$22_DATA[63:0]$2960 + update $memwr$\mem_2$ls180.v:10418$22_EN $0$memwr$\mem_2$ls180.v:10418$22_EN[63:0]$2961 + update $memwr$\mem_2$ls180.v:10420$23_ADDR $0$memwr$\mem_2$ls180.v:10420$23_ADDR[5:0]$2962 + update $memwr$\mem_2$ls180.v:10420$23_DATA $0$memwr$\mem_2$ls180.v:10420$23_DATA[63:0]$2963 + update $memwr$\mem_2$ls180.v:10420$23_EN $0$memwr$\mem_2$ls180.v:10420$23_EN[63:0]$2964 + update $memwr$\mem_2$ls180.v:10422$24_ADDR $0$memwr$\mem_2$ls180.v:10422$24_ADDR[5:0]$2965 + update $memwr$\mem_2$ls180.v:10422$24_DATA $0$memwr$\mem_2$ls180.v:10422$24_DATA[63:0]$2966 + update $memwr$\mem_2$ls180.v:10422$24_EN $0$memwr$\mem_2$ls180.v:10422$24_EN[63:0]$2967 + end + attribute \src "ls180.v:10434.1-10452.4" + process $proc$ls180.v:10434$2969 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0$memwr$\mem_3$ls180.v:10450$32_ADDR[5:0]$2991 6'xxxxxx + assign $0$memwr$\mem_3$ls180.v:10450$32_DATA[63:0]$2992 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_3$ls180.v:10450$32_EN[63:0]$2993 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_3$ls180.v:10448$31_ADDR[5:0]$2988 6'xxxxxx + assign $0$memwr$\mem_3$ls180.v:10448$31_DATA[63:0]$2989 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_3$ls180.v:10448$31_EN[63:0]$2990 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_3$ls180.v:10446$30_ADDR[5:0]$2985 6'xxxxxx + assign $0$memwr$\mem_3$ls180.v:10446$30_DATA[63:0]$2986 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_3$ls180.v:10446$30_EN[63:0]$2987 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_3$ls180.v:10444$29_ADDR[5:0]$2982 6'xxxxxx + assign $0$memwr$\mem_3$ls180.v:10444$29_DATA[63:0]$2983 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_3$ls180.v:10444$29_EN[63:0]$2984 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_3$ls180.v:10442$28_ADDR[5:0]$2979 6'xxxxxx + assign $0$memwr$\mem_3$ls180.v:10442$28_DATA[63:0]$2980 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_3$ls180.v:10442$28_EN[63:0]$2981 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_3$ls180.v:10440$27_ADDR[5:0]$2976 6'xxxxxx + assign $0$memwr$\mem_3$ls180.v:10440$27_DATA[63:0]$2977 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_3$ls180.v:10440$27_EN[63:0]$2978 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_3$ls180.v:10438$26_ADDR[5:0]$2973 6'xxxxxx + assign $0$memwr$\mem_3$ls180.v:10438$26_DATA[63:0]$2974 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_3$ls180.v:10438$26_EN[63:0]$2975 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_3$ls180.v:10436$25_ADDR[5:0]$2970 6'xxxxxx + assign $0$memwr$\mem_3$ls180.v:10436$25_DATA[63:0]$2971 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_3$ls180.v:10436$25_EN[63:0]$2972 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\memadr_3[5:0] \main_sram2_adr + attribute \src "ls180.v:10435.2-10436.55" + switch \main_sram2_we [0] + attribute \src "ls180.v:10435.6-10435.22" + case 1'1 + assign $0$memwr$\mem_3$ls180.v:10436$25_ADDR[5:0]$2970 \main_sram2_adr + assign $0$memwr$\mem_3$ls180.v:10436$25_DATA[63:0]$2971 { 56'00000000000000000000000000000000000000000000000000000000 \main_sram2_dat_w [7:0] } + assign $0$memwr$\mem_3$ls180.v:10436$25_EN[63:0]$2972 64'0000000000000000000000000000000000000000000000000000000011111111 + case + end + attribute \src "ls180.v:10437.2-10438.57" + switch \main_sram2_we [1] + attribute \src "ls180.v:10437.6-10437.22" + case 1'1 + assign $0$memwr$\mem_3$ls180.v:10438$26_ADDR[5:0]$2973 \main_sram2_adr + assign $0$memwr$\mem_3$ls180.v:10438$26_DATA[63:0]$2974 { 48'000000000000000000000000000000000000000000000000 \main_sram2_dat_w [15:8] 8'xxxxxxxx } + assign $0$memwr$\mem_3$ls180.v:10438$26_EN[63:0]$2975 64'0000000000000000000000000000000000000000000000001111111100000000 + case + end + attribute \src "ls180.v:10439.2-10440.59" + switch \main_sram2_we [2] + attribute \src "ls180.v:10439.6-10439.22" + case 1'1 + assign $0$memwr$\mem_3$ls180.v:10440$27_ADDR[5:0]$2976 \main_sram2_adr + assign $0$memwr$\mem_3$ls180.v:10440$27_DATA[63:0]$2977 { 40'0000000000000000000000000000000000000000 \main_sram2_dat_w [23:16] 16'xxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_3$ls180.v:10440$27_EN[63:0]$2978 64'0000000000000000000000000000000000000000111111110000000000000000 + case + end + attribute \src "ls180.v:10441.2-10442.59" + switch \main_sram2_we [3] + attribute \src "ls180.v:10441.6-10441.22" + case 1'1 + assign $0$memwr$\mem_3$ls180.v:10442$28_ADDR[5:0]$2979 \main_sram2_adr + assign $0$memwr$\mem_3$ls180.v:10442$28_DATA[63:0]$2980 { 32'00000000000000000000000000000000 \main_sram2_dat_w [31:24] 24'xxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_3$ls180.v:10442$28_EN[63:0]$2981 64'0000000000000000000000000000000011111111000000000000000000000000 + case + end + attribute \src "ls180.v:10443.2-10444.59" + switch \main_sram2_we [4] + attribute \src "ls180.v:10443.6-10443.22" + case 1'1 + assign $0$memwr$\mem_3$ls180.v:10444$29_ADDR[5:0]$2982 \main_sram2_adr + assign $0$memwr$\mem_3$ls180.v:10444$29_DATA[63:0]$2983 { 24'000000000000000000000000 \main_sram2_dat_w [39:32] 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_3$ls180.v:10444$29_EN[63:0]$2984 64'0000000000000000000000001111111100000000000000000000000000000000 + case + end + attribute \src "ls180.v:10445.2-10446.59" + switch \main_sram2_we [5] + attribute \src "ls180.v:10445.6-10445.22" + case 1'1 + assign $0$memwr$\mem_3$ls180.v:10446$30_ADDR[5:0]$2985 \main_sram2_adr + assign $0$memwr$\mem_3$ls180.v:10446$30_DATA[63:0]$2986 { 16'0000000000000000 \main_sram2_dat_w [47:40] 40'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_3$ls180.v:10446$30_EN[63:0]$2987 64'0000000000000000111111110000000000000000000000000000000000000000 + case + end + attribute \src "ls180.v:10447.2-10448.59" + switch \main_sram2_we [6] + attribute \src "ls180.v:10447.6-10447.22" + case 1'1 + assign $0$memwr$\mem_3$ls180.v:10448$31_ADDR[5:0]$2988 \main_sram2_adr + assign $0$memwr$\mem_3$ls180.v:10448$31_DATA[63:0]$2989 { 8'00000000 \main_sram2_dat_w [55:48] 48'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_3$ls180.v:10448$31_EN[63:0]$2990 64'0000000011111111000000000000000000000000000000000000000000000000 + case + end + attribute \src "ls180.v:10449.2-10450.59" + switch \main_sram2_we [7] + attribute \src "ls180.v:10449.6-10449.22" + case 1'1 + assign $0$memwr$\mem_3$ls180.v:10450$32_ADDR[5:0]$2991 \main_sram2_adr + assign $0$memwr$\mem_3$ls180.v:10450$32_DATA[63:0]$2992 { \main_sram2_dat_w [63:56] 56'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_3$ls180.v:10450$32_EN[63:0]$2993 64'1111111100000000000000000000000000000000000000000000000000000000 + case + end + sync posedge \sys_clk_1 + update \memadr_3 $0\memadr_3[5:0] + update $memwr$\mem_3$ls180.v:10436$25_ADDR $0$memwr$\mem_3$ls180.v:10436$25_ADDR[5:0]$2970 + update $memwr$\mem_3$ls180.v:10436$25_DATA $0$memwr$\mem_3$ls180.v:10436$25_DATA[63:0]$2971 + update $memwr$\mem_3$ls180.v:10436$25_EN $0$memwr$\mem_3$ls180.v:10436$25_EN[63:0]$2972 + update $memwr$\mem_3$ls180.v:10438$26_ADDR $0$memwr$\mem_3$ls180.v:10438$26_ADDR[5:0]$2973 + update $memwr$\mem_3$ls180.v:10438$26_DATA $0$memwr$\mem_3$ls180.v:10438$26_DATA[63:0]$2974 + update $memwr$\mem_3$ls180.v:10438$26_EN $0$memwr$\mem_3$ls180.v:10438$26_EN[63:0]$2975 + update $memwr$\mem_3$ls180.v:10440$27_ADDR $0$memwr$\mem_3$ls180.v:10440$27_ADDR[5:0]$2976 + update $memwr$\mem_3$ls180.v:10440$27_DATA $0$memwr$\mem_3$ls180.v:10440$27_DATA[63:0]$2977 + update $memwr$\mem_3$ls180.v:10440$27_EN $0$memwr$\mem_3$ls180.v:10440$27_EN[63:0]$2978 + update $memwr$\mem_3$ls180.v:10442$28_ADDR $0$memwr$\mem_3$ls180.v:10442$28_ADDR[5:0]$2979 + update $memwr$\mem_3$ls180.v:10442$28_DATA $0$memwr$\mem_3$ls180.v:10442$28_DATA[63:0]$2980 + update $memwr$\mem_3$ls180.v:10442$28_EN $0$memwr$\mem_3$ls180.v:10442$28_EN[63:0]$2981 + update $memwr$\mem_3$ls180.v:10444$29_ADDR $0$memwr$\mem_3$ls180.v:10444$29_ADDR[5:0]$2982 + update $memwr$\mem_3$ls180.v:10444$29_DATA $0$memwr$\mem_3$ls180.v:10444$29_DATA[63:0]$2983 + update $memwr$\mem_3$ls180.v:10444$29_EN $0$memwr$\mem_3$ls180.v:10444$29_EN[63:0]$2984 + update $memwr$\mem_3$ls180.v:10446$30_ADDR $0$memwr$\mem_3$ls180.v:10446$30_ADDR[5:0]$2985 + update $memwr$\mem_3$ls180.v:10446$30_DATA $0$memwr$\mem_3$ls180.v:10446$30_DATA[63:0]$2986 + update $memwr$\mem_3$ls180.v:10446$30_EN $0$memwr$\mem_3$ls180.v:10446$30_EN[63:0]$2987 + update $memwr$\mem_3$ls180.v:10448$31_ADDR $0$memwr$\mem_3$ls180.v:10448$31_ADDR[5:0]$2988 + update $memwr$\mem_3$ls180.v:10448$31_DATA $0$memwr$\mem_3$ls180.v:10448$31_DATA[63:0]$2989 + update $memwr$\mem_3$ls180.v:10448$31_EN $0$memwr$\mem_3$ls180.v:10448$31_EN[63:0]$2990 + update $memwr$\mem_3$ls180.v:10450$32_ADDR $0$memwr$\mem_3$ls180.v:10450$32_ADDR[5:0]$2991 + update $memwr$\mem_3$ls180.v:10450$32_DATA $0$memwr$\mem_3$ls180.v:10450$32_DATA[63:0]$2992 + update $memwr$\mem_3$ls180.v:10450$32_EN $0$memwr$\mem_3$ls180.v:10450$32_EN[63:0]$2993 + end + attribute \src "ls180.v:10462.1-10480.4" + process $proc$ls180.v:10462$2995 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0$memwr$\mem_4$ls180.v:10478$40_ADDR[5:0]$3017 6'xxxxxx + assign $0$memwr$\mem_4$ls180.v:10478$40_DATA[63:0]$3018 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_4$ls180.v:10478$40_EN[63:0]$3019 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_4$ls180.v:10476$39_ADDR[5:0]$3014 6'xxxxxx + assign $0$memwr$\mem_4$ls180.v:10476$39_DATA[63:0]$3015 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_4$ls180.v:10476$39_EN[63:0]$3016 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_4$ls180.v:10474$38_ADDR[5:0]$3011 6'xxxxxx + assign $0$memwr$\mem_4$ls180.v:10474$38_DATA[63:0]$3012 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_4$ls180.v:10474$38_EN[63:0]$3013 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_4$ls180.v:10472$37_ADDR[5:0]$3008 6'xxxxxx + assign $0$memwr$\mem_4$ls180.v:10472$37_DATA[63:0]$3009 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_4$ls180.v:10472$37_EN[63:0]$3010 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_4$ls180.v:10470$36_ADDR[5:0]$3005 6'xxxxxx + assign $0$memwr$\mem_4$ls180.v:10470$36_DATA[63:0]$3006 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_4$ls180.v:10470$36_EN[63:0]$3007 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_4$ls180.v:10468$35_ADDR[5:0]$3002 6'xxxxxx + assign $0$memwr$\mem_4$ls180.v:10468$35_DATA[63:0]$3003 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_4$ls180.v:10468$35_EN[63:0]$3004 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_4$ls180.v:10466$34_ADDR[5:0]$2999 6'xxxxxx + assign $0$memwr$\mem_4$ls180.v:10466$34_DATA[63:0]$3000 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_4$ls180.v:10466$34_EN[63:0]$3001 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\mem_4$ls180.v:10464$33_ADDR[5:0]$2996 6'xxxxxx + assign $0$memwr$\mem_4$ls180.v:10464$33_DATA[63:0]$2997 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem_4$ls180.v:10464$33_EN[63:0]$2998 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\memadr_4[5:0] \main_sram3_adr + attribute \src "ls180.v:10463.2-10464.55" + switch \main_sram3_we [0] + attribute \src "ls180.v:10463.6-10463.22" + case 1'1 + assign $0$memwr$\mem_4$ls180.v:10464$33_ADDR[5:0]$2996 \main_sram3_adr + assign $0$memwr$\mem_4$ls180.v:10464$33_DATA[63:0]$2997 { 56'00000000000000000000000000000000000000000000000000000000 \main_sram3_dat_w [7:0] } + assign $0$memwr$\mem_4$ls180.v:10464$33_EN[63:0]$2998 64'0000000000000000000000000000000000000000000000000000000011111111 + case + end + attribute \src "ls180.v:10465.2-10466.57" + switch \main_sram3_we [1] + attribute \src "ls180.v:10465.6-10465.22" + case 1'1 + assign $0$memwr$\mem_4$ls180.v:10466$34_ADDR[5:0]$2999 \main_sram3_adr + assign $0$memwr$\mem_4$ls180.v:10466$34_DATA[63:0]$3000 { 48'000000000000000000000000000000000000000000000000 \main_sram3_dat_w [15:8] 8'xxxxxxxx } + assign $0$memwr$\mem_4$ls180.v:10466$34_EN[63:0]$3001 64'0000000000000000000000000000000000000000000000001111111100000000 + case + end + attribute \src "ls180.v:10467.2-10468.59" + switch \main_sram3_we [2] + attribute \src "ls180.v:10467.6-10467.22" + case 1'1 + assign $0$memwr$\mem_4$ls180.v:10468$35_ADDR[5:0]$3002 \main_sram3_adr + assign $0$memwr$\mem_4$ls180.v:10468$35_DATA[63:0]$3003 { 40'0000000000000000000000000000000000000000 \main_sram3_dat_w [23:16] 16'xxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_4$ls180.v:10468$35_EN[63:0]$3004 64'0000000000000000000000000000000000000000111111110000000000000000 + case + end + attribute \src "ls180.v:10469.2-10470.59" + switch \main_sram3_we [3] + attribute \src "ls180.v:10469.6-10469.22" + case 1'1 + assign $0$memwr$\mem_4$ls180.v:10470$36_ADDR[5:0]$3005 \main_sram3_adr + assign $0$memwr$\mem_4$ls180.v:10470$36_DATA[63:0]$3006 { 32'00000000000000000000000000000000 \main_sram3_dat_w [31:24] 24'xxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_4$ls180.v:10470$36_EN[63:0]$3007 64'0000000000000000000000000000000011111111000000000000000000000000 + case + end + attribute \src "ls180.v:10471.2-10472.59" + switch \main_sram3_we [4] + attribute \src "ls180.v:10471.6-10471.22" + case 1'1 + assign $0$memwr$\mem_4$ls180.v:10472$37_ADDR[5:0]$3008 \main_sram3_adr + assign $0$memwr$\mem_4$ls180.v:10472$37_DATA[63:0]$3009 { 24'000000000000000000000000 \main_sram3_dat_w [39:32] 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_4$ls180.v:10472$37_EN[63:0]$3010 64'0000000000000000000000001111111100000000000000000000000000000000 + case + end + attribute \src "ls180.v:10473.2-10474.59" + switch \main_sram3_we [5] + attribute \src "ls180.v:10473.6-10473.22" + case 1'1 + assign $0$memwr$\mem_4$ls180.v:10474$38_ADDR[5:0]$3011 \main_sram3_adr + assign $0$memwr$\mem_4$ls180.v:10474$38_DATA[63:0]$3012 { 16'0000000000000000 \main_sram3_dat_w [47:40] 40'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_4$ls180.v:10474$38_EN[63:0]$3013 64'0000000000000000111111110000000000000000000000000000000000000000 + case + end + attribute \src "ls180.v:10475.2-10476.59" + switch \main_sram3_we [6] + attribute \src "ls180.v:10475.6-10475.22" + case 1'1 + assign $0$memwr$\mem_4$ls180.v:10476$39_ADDR[5:0]$3014 \main_sram3_adr + assign $0$memwr$\mem_4$ls180.v:10476$39_DATA[63:0]$3015 { 8'00000000 \main_sram3_dat_w [55:48] 48'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_4$ls180.v:10476$39_EN[63:0]$3016 64'0000000011111111000000000000000000000000000000000000000000000000 + case + end + attribute \src "ls180.v:10477.2-10478.59" + switch \main_sram3_we [7] + attribute \src "ls180.v:10477.6-10477.22" + case 1'1 + assign $0$memwr$\mem_4$ls180.v:10478$40_ADDR[5:0]$3017 \main_sram3_adr + assign $0$memwr$\mem_4$ls180.v:10478$40_DATA[63:0]$3018 { \main_sram3_dat_w [63:56] 56'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem_4$ls180.v:10478$40_EN[63:0]$3019 64'1111111100000000000000000000000000000000000000000000000000000000 + case + end + sync posedge \sys_clk_1 + update \memadr_4 $0\memadr_4[5:0] + update $memwr$\mem_4$ls180.v:10464$33_ADDR $0$memwr$\mem_4$ls180.v:10464$33_ADDR[5:0]$2996 + update $memwr$\mem_4$ls180.v:10464$33_DATA $0$memwr$\mem_4$ls180.v:10464$33_DATA[63:0]$2997 + update $memwr$\mem_4$ls180.v:10464$33_EN $0$memwr$\mem_4$ls180.v:10464$33_EN[63:0]$2998 + update $memwr$\mem_4$ls180.v:10466$34_ADDR $0$memwr$\mem_4$ls180.v:10466$34_ADDR[5:0]$2999 + update $memwr$\mem_4$ls180.v:10466$34_DATA $0$memwr$\mem_4$ls180.v:10466$34_DATA[63:0]$3000 + update $memwr$\mem_4$ls180.v:10466$34_EN $0$memwr$\mem_4$ls180.v:10466$34_EN[63:0]$3001 + update $memwr$\mem_4$ls180.v:10468$35_ADDR $0$memwr$\mem_4$ls180.v:10468$35_ADDR[5:0]$3002 + update $memwr$\mem_4$ls180.v:10468$35_DATA $0$memwr$\mem_4$ls180.v:10468$35_DATA[63:0]$3003 + update $memwr$\mem_4$ls180.v:10468$35_EN $0$memwr$\mem_4$ls180.v:10468$35_EN[63:0]$3004 + update $memwr$\mem_4$ls180.v:10470$36_ADDR $0$memwr$\mem_4$ls180.v:10470$36_ADDR[5:0]$3005 + update $memwr$\mem_4$ls180.v:10470$36_DATA $0$memwr$\mem_4$ls180.v:10470$36_DATA[63:0]$3006 + update $memwr$\mem_4$ls180.v:10470$36_EN $0$memwr$\mem_4$ls180.v:10470$36_EN[63:0]$3007 + update $memwr$\mem_4$ls180.v:10472$37_ADDR $0$memwr$\mem_4$ls180.v:10472$37_ADDR[5:0]$3008 + update $memwr$\mem_4$ls180.v:10472$37_DATA $0$memwr$\mem_4$ls180.v:10472$37_DATA[63:0]$3009 + update $memwr$\mem_4$ls180.v:10472$37_EN $0$memwr$\mem_4$ls180.v:10472$37_EN[63:0]$3010 + update $memwr$\mem_4$ls180.v:10474$38_ADDR $0$memwr$\mem_4$ls180.v:10474$38_ADDR[5:0]$3011 + update $memwr$\mem_4$ls180.v:10474$38_DATA $0$memwr$\mem_4$ls180.v:10474$38_DATA[63:0]$3012 + update $memwr$\mem_4$ls180.v:10474$38_EN $0$memwr$\mem_4$ls180.v:10474$38_EN[63:0]$3013 + update $memwr$\mem_4$ls180.v:10476$39_ADDR $0$memwr$\mem_4$ls180.v:10476$39_ADDR[5:0]$3014 + update $memwr$\mem_4$ls180.v:10476$39_DATA $0$memwr$\mem_4$ls180.v:10476$39_DATA[63:0]$3015 + update $memwr$\mem_4$ls180.v:10476$39_EN $0$memwr$\mem_4$ls180.v:10476$39_EN[63:0]$3016 + update $memwr$\mem_4$ls180.v:10478$40_ADDR $0$memwr$\mem_4$ls180.v:10478$40_ADDR[5:0]$3017 + update $memwr$\mem_4$ls180.v:10478$40_DATA $0$memwr$\mem_4$ls180.v:10478$40_DATA[63:0]$3018 + update $memwr$\mem_4$ls180.v:10478$40_EN $0$memwr$\mem_4$ls180.v:10478$40_EN[63:0]$3019 + end + attribute \src "ls180.v:10490.1-10494.4" + process $proc$ls180.v:10490$3021 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0$memwr$\storage$ls180.v:10492$41_ADDR[2:0]$3022 3'xxx + assign $0$memwr$\storage$ls180.v:10492$41_DATA[24:0]$3023 25'xxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\storage$ls180.v:10492$41_EN[24:0]$3024 25'0000000000000000000000000 + assign $0\memdat[24:0] $memrd$\storage$ls180.v:10493$3025_DATA + attribute \src "ls180.v:10491.2-10492.129" + switch \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_we + attribute \src "ls180.v:10491.6-10491.60" + case 1'1 + assign $0$memwr$\storage$ls180.v:10492$41_ADDR[2:0]$3022 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr + assign $0$memwr$\storage$ls180.v:10492$41_DATA[24:0]$3023 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w + assign $0$memwr$\storage$ls180.v:10492$41_EN[24:0]$3024 25'1111111111111111111111111 + case + end + sync posedge \sys_clk_1 + update \memdat $0\memdat[24:0] + update $memwr$\storage$ls180.v:10492$41_ADDR $0$memwr$\storage$ls180.v:10492$41_ADDR[2:0]$3022 + update $memwr$\storage$ls180.v:10492$41_DATA $0$memwr$\storage$ls180.v:10492$41_DATA[24:0]$3023 + update $memwr$\storage$ls180.v:10492$41_EN $0$memwr$\storage$ls180.v:10492$41_EN[24:0]$3024 + end + attribute \src "ls180.v:10496.1-10497.4" + process $proc$ls180.v:10496$3026 + sync posedge \sys_clk_1 + end + attribute \src "ls180.v:10504.1-10508.4" + process $proc$ls180.v:10504$3028 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0$memwr$\storage_1$ls180.v:10506$42_ADDR[2:0]$3029 3'xxx + assign $0$memwr$\storage_1$ls180.v:10506$42_DATA[24:0]$3030 25'xxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\storage_1$ls180.v:10506$42_EN[24:0]$3031 25'0000000000000000000000000 + assign $0\memdat_1[24:0] $memrd$\storage_1$ls180.v:10507$3032_DATA + attribute \src "ls180.v:10505.2-10506.131" + switch \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_we + attribute \src "ls180.v:10505.6-10505.60" + case 1'1 + assign $0$memwr$\storage_1$ls180.v:10506$42_ADDR[2:0]$3029 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr + assign $0$memwr$\storage_1$ls180.v:10506$42_DATA[24:0]$3030 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w + assign $0$memwr$\storage_1$ls180.v:10506$42_EN[24:0]$3031 25'1111111111111111111111111 + case + end + sync posedge \sys_clk_1 + update \memdat_1 $0\memdat_1[24:0] + update $memwr$\storage_1$ls180.v:10506$42_ADDR $0$memwr$\storage_1$ls180.v:10506$42_ADDR[2:0]$3029 + update $memwr$\storage_1$ls180.v:10506$42_DATA $0$memwr$\storage_1$ls180.v:10506$42_DATA[24:0]$3030 + update $memwr$\storage_1$ls180.v:10506$42_EN $0$memwr$\storage_1$ls180.v:10506$42_EN[24:0]$3031 + end + attribute \src "ls180.v:10510.1-10511.4" + process $proc$ls180.v:10510$3033 + sync posedge \sys_clk_1 + end + attribute \src "ls180.v:10518.1-10522.4" + process $proc$ls180.v:10518$3035 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0$memwr$\storage_2$ls180.v:10520$43_ADDR[2:0]$3036 3'xxx + assign $0$memwr$\storage_2$ls180.v:10520$43_DATA[24:0]$3037 25'xxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\storage_2$ls180.v:10520$43_EN[24:0]$3038 25'0000000000000000000000000 + assign $0\memdat_2[24:0] $memrd$\storage_2$ls180.v:10521$3039_DATA + attribute \src "ls180.v:10519.2-10520.131" + switch \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_we + attribute \src "ls180.v:10519.6-10519.60" + case 1'1 + assign $0$memwr$\storage_2$ls180.v:10520$43_ADDR[2:0]$3036 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr + assign $0$memwr$\storage_2$ls180.v:10520$43_DATA[24:0]$3037 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w + assign $0$memwr$\storage_2$ls180.v:10520$43_EN[24:0]$3038 25'1111111111111111111111111 + case + end + sync posedge \sys_clk_1 + update \memdat_2 $0\memdat_2[24:0] + update $memwr$\storage_2$ls180.v:10520$43_ADDR $0$memwr$\storage_2$ls180.v:10520$43_ADDR[2:0]$3036 + update $memwr$\storage_2$ls180.v:10520$43_DATA $0$memwr$\storage_2$ls180.v:10520$43_DATA[24:0]$3037 + update $memwr$\storage_2$ls180.v:10520$43_EN $0$memwr$\storage_2$ls180.v:10520$43_EN[24:0]$3038 + end + attribute \src "ls180.v:10524.1-10525.4" + process $proc$ls180.v:10524$3040 + sync posedge \sys_clk_1 + end + attribute \src "ls180.v:10532.1-10536.4" + process $proc$ls180.v:10532$3042 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0$memwr$\storage_3$ls180.v:10534$44_ADDR[2:0]$3043 3'xxx + assign $0$memwr$\storage_3$ls180.v:10534$44_DATA[24:0]$3044 25'xxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\storage_3$ls180.v:10534$44_EN[24:0]$3045 25'0000000000000000000000000 + assign $0\memdat_3[24:0] $memrd$\storage_3$ls180.v:10535$3046_DATA + attribute \src "ls180.v:10533.2-10534.131" + switch \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_we + attribute \src "ls180.v:10533.6-10533.60" + case 1'1 + assign $0$memwr$\storage_3$ls180.v:10534$44_ADDR[2:0]$3043 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr + assign $0$memwr$\storage_3$ls180.v:10534$44_DATA[24:0]$3044 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w + assign $0$memwr$\storage_3$ls180.v:10534$44_EN[24:0]$3045 25'1111111111111111111111111 + case + end + sync posedge \sys_clk_1 + update \memdat_3 $0\memdat_3[24:0] + update $memwr$\storage_3$ls180.v:10534$44_ADDR $0$memwr$\storage_3$ls180.v:10534$44_ADDR[2:0]$3043 + update $memwr$\storage_3$ls180.v:10534$44_DATA $0$memwr$\storage_3$ls180.v:10534$44_DATA[24:0]$3044 + update $memwr$\storage_3$ls180.v:10534$44_EN $0$memwr$\storage_3$ls180.v:10534$44_EN[24:0]$3045 + end + attribute \src "ls180.v:10538.1-10539.4" + process $proc$ls180.v:10538$3047 + sync posedge \sys_clk_1 + end + attribute \src "ls180.v:10547.1-10551.4" + process $proc$ls180.v:10547$3049 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0$memwr$\storage_4$ls180.v:10549$45_ADDR[3:0]$3050 4'xxxx + assign $0$memwr$\storage_4$ls180.v:10549$45_DATA[9:0]$3051 10'xxxxxxxxxx + assign $0$memwr$\storage_4$ls180.v:10549$45_EN[9:0]$3052 10'0000000000 + assign $0\memdat_4[9:0] $memrd$\storage_4$ls180.v:10550$3053_DATA + attribute \src "ls180.v:10548.2-10549.77" + switch \main_uart_tx_fifo_wrport_we + attribute \src "ls180.v:10548.6-10548.33" + case 1'1 + assign $0$memwr$\storage_4$ls180.v:10549$45_ADDR[3:0]$3050 \main_uart_tx_fifo_wrport_adr + assign $0$memwr$\storage_4$ls180.v:10549$45_DATA[9:0]$3051 \main_uart_tx_fifo_wrport_dat_w + assign $0$memwr$\storage_4$ls180.v:10549$45_EN[9:0]$3052 10'1111111111 + case + end + sync posedge \sys_clk_1 + update \memdat_4 $0\memdat_4[9:0] + update $memwr$\storage_4$ls180.v:10549$45_ADDR $0$memwr$\storage_4$ls180.v:10549$45_ADDR[3:0]$3050 + update $memwr$\storage_4$ls180.v:10549$45_DATA $0$memwr$\storage_4$ls180.v:10549$45_DATA[9:0]$3051 + update $memwr$\storage_4$ls180.v:10549$45_EN $0$memwr$\storage_4$ls180.v:10549$45_EN[9:0]$3052 + end + attribute \src "ls180.v:1055.5-1055.38" + process $proc$ls180.v:1055$3486 + assign { } { } + assign $1\main_uart_rx_fifo_readable[0:0] 1'0 + sync always + sync init + update \main_uart_rx_fifo_readable $1\main_uart_rx_fifo_readable[0:0] + end + attribute \src "ls180.v:10553.1-10556.4" + process $proc$ls180.v:10553$3054 + assign $0\memdat_5[9:0] \memdat_5 + attribute \src "ls180.v:10554.2-10555.55" + switch \main_uart_tx_fifo_rdport_re + attribute \src "ls180.v:10554.6-10554.33" + case 1'1 + assign $0\memdat_5[9:0] $memrd$\storage_4$ls180.v:10555$3055_DATA + case + end + sync posedge \sys_clk_1 + update \memdat_5 $0\memdat_5[9:0] + end + attribute \src "ls180.v:10564.1-10568.4" + process $proc$ls180.v:10564$3056 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0$memwr$\storage_5$ls180.v:10566$46_ADDR[3:0]$3057 4'xxxx + assign $0$memwr$\storage_5$ls180.v:10566$46_DATA[9:0]$3058 10'xxxxxxxxxx + assign $0$memwr$\storage_5$ls180.v:10566$46_EN[9:0]$3059 10'0000000000 + assign $0\memdat_6[9:0] $memrd$\storage_5$ls180.v:10567$3060_DATA + attribute \src "ls180.v:10565.2-10566.77" + switch \main_uart_rx_fifo_wrport_we + attribute \src "ls180.v:10565.6-10565.33" + case 1'1 + assign $0$memwr$\storage_5$ls180.v:10566$46_ADDR[3:0]$3057 \main_uart_rx_fifo_wrport_adr + assign $0$memwr$\storage_5$ls180.v:10566$46_DATA[9:0]$3058 \main_uart_rx_fifo_wrport_dat_w + assign $0$memwr$\storage_5$ls180.v:10566$46_EN[9:0]$3059 10'1111111111 + case + end + sync posedge \sys_clk_1 + update \memdat_6 $0\memdat_6[9:0] + update $memwr$\storage_5$ls180.v:10566$46_ADDR $0$memwr$\storage_5$ls180.v:10566$46_ADDR[3:0]$3057 + update $memwr$\storage_5$ls180.v:10566$46_DATA $0$memwr$\storage_5$ls180.v:10566$46_DATA[9:0]$3058 + update $memwr$\storage_5$ls180.v:10566$46_EN $0$memwr$\storage_5$ls180.v:10566$46_EN[9:0]$3059 + end + attribute \src "ls180.v:10570.1-10573.4" + process $proc$ls180.v:10570$3061 + assign $0\memdat_7[9:0] \memdat_7 + attribute \src "ls180.v:10571.2-10572.55" + switch \main_uart_rx_fifo_rdport_re + attribute \src "ls180.v:10571.6-10571.33" + case 1'1 + assign $0\memdat_7[9:0] $memrd$\storage_5$ls180.v:10572$3062_DATA + case + end + sync posedge \sys_clk_1 + update \memdat_7 $0\memdat_7[9:0] + end + attribute \src "ls180.v:10580.1-10584.4" + process $proc$ls180.v:10580$3063 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0$memwr$\storage_6$ls180.v:10582$47_ADDR[4:0]$3064 5'xxxxx + assign $0$memwr$\storage_6$ls180.v:10582$47_DATA[9:0]$3065 10'xxxxxxxxxx + assign $0$memwr$\storage_6$ls180.v:10582$47_EN[9:0]$3066 10'0000000000 + assign $0\memdat_8[9:0] $memrd$\storage_6$ls180.v:10583$3067_DATA + attribute \src "ls180.v:10581.2-10582.85" + switch \main_sdblock2mem_fifo_wrport_we + attribute \src "ls180.v:10581.6-10581.37" + case 1'1 + assign $0$memwr$\storage_6$ls180.v:10582$47_ADDR[4:0]$3064 \main_sdblock2mem_fifo_wrport_adr + assign $0$memwr$\storage_6$ls180.v:10582$47_DATA[9:0]$3065 \main_sdblock2mem_fifo_wrport_dat_w + assign $0$memwr$\storage_6$ls180.v:10582$47_EN[9:0]$3066 10'1111111111 + case + end + sync posedge \sys_clk_1 + update \memdat_8 $0\memdat_8[9:0] + update $memwr$\storage_6$ls180.v:10582$47_ADDR $0$memwr$\storage_6$ls180.v:10582$47_ADDR[4:0]$3064 + update $memwr$\storage_6$ls180.v:10582$47_DATA $0$memwr$\storage_6$ls180.v:10582$47_DATA[9:0]$3065 + update $memwr$\storage_6$ls180.v:10582$47_EN $0$memwr$\storage_6$ls180.v:10582$47_EN[9:0]$3066 + end + attribute \src "ls180.v:10586.1-10587.4" + process $proc$ls180.v:10586$3068 + sync posedge \sys_clk_1 + end + attribute \src "ls180.v:10594.1-10598.4" + process $proc$ls180.v:10594$3070 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0$memwr$\storage_7$ls180.v:10596$48_ADDR[4:0]$3071 5'xxxxx + assign $0$memwr$\storage_7$ls180.v:10596$48_DATA[9:0]$3072 10'xxxxxxxxxx + assign $0$memwr$\storage_7$ls180.v:10596$48_EN[9:0]$3073 10'0000000000 + assign $0\memdat_9[9:0] $memrd$\storage_7$ls180.v:10597$3074_DATA + attribute \src "ls180.v:10595.2-10596.85" + switch \main_sdmem2block_fifo_wrport_we + attribute \src "ls180.v:10595.6-10595.37" + case 1'1 + assign $0$memwr$\storage_7$ls180.v:10596$48_ADDR[4:0]$3071 \main_sdmem2block_fifo_wrport_adr + assign $0$memwr$\storage_7$ls180.v:10596$48_DATA[9:0]$3072 \main_sdmem2block_fifo_wrport_dat_w + assign $0$memwr$\storage_7$ls180.v:10596$48_EN[9:0]$3073 10'1111111111 + case + end + sync posedge \sys_clk_1 + update \memdat_9 $0\memdat_9[9:0] + update $memwr$\storage_7$ls180.v:10596$48_ADDR $0$memwr$\storage_7$ls180.v:10596$48_ADDR[4:0]$3071 + update $memwr$\storage_7$ls180.v:10596$48_DATA $0$memwr$\storage_7$ls180.v:10596$48_DATA[9:0]$3072 + update $memwr$\storage_7$ls180.v:10596$48_EN $0$memwr$\storage_7$ls180.v:10596$48_EN[9:0]$3073 + end + attribute \src "ls180.v:10600.1-10601.4" + process $proc$ls180.v:10600$3075 + sync posedge \sys_clk_1 + end + attribute \src "ls180.v:1062.11-1062.42" + process $proc$ls180.v:1062$3487 + assign { } { } + assign $1\main_uart_rx_fifo_level0[4:0] 5'00000 + sync always + sync init + update \main_uart_rx_fifo_level0 $1\main_uart_rx_fifo_level0[4:0] + end + attribute \src "ls180.v:1063.5-1063.37" + process $proc$ls180.v:1063$3488 + assign { } { } + assign $0\main_uart_rx_fifo_replace[0:0] 1'0 + sync always + update \main_uart_rx_fifo_replace $0\main_uart_rx_fifo_replace[0:0] + sync init + end + attribute \src "ls180.v:1064.11-1064.43" + process $proc$ls180.v:1064$3489 + assign { } { } + assign $1\main_uart_rx_fifo_produce[3:0] 4'0000 + sync always + sync init + update \main_uart_rx_fifo_produce $1\main_uart_rx_fifo_produce[3:0] + end + attribute \src "ls180.v:1065.11-1065.43" + process $proc$ls180.v:1065$3490 + assign { } { } + assign $1\main_uart_rx_fifo_consume[3:0] 4'0000 + sync always + sync init + update \main_uart_rx_fifo_consume $1\main_uart_rx_fifo_consume[3:0] + end + attribute \src "ls180.v:1066.11-1066.46" + process $proc$ls180.v:1066$3491 + assign { } { } + assign $1\main_uart_rx_fifo_wrport_adr[3:0] 4'0000 + sync always + sync init + update \main_uart_rx_fifo_wrport_adr $1\main_uart_rx_fifo_wrport_adr[3:0] + end + attribute \src "ls180.v:1081.5-1081.27" + process $proc$ls180.v:1081$3492 + assign { } { } + assign $0\main_uart_reset[0:0] 1'0 + sync always + update \main_uart_reset $0\main_uart_reset[0:0] + sync init + end + attribute \src "ls180.v:1082.12-1082.53" + process $proc$ls180.v:1082$3493 + assign { } { } + assign $0\main_gpiotristateasic0_oe_storage[15:0] 16'0000000000000000 + sync always + update \main_gpiotristateasic0_oe_storage $0\main_gpiotristateasic0_oe_storage[15:0] + sync init + end + attribute \src "ls180.v:1083.12-1083.49" + process $proc$ls180.v:1083$3494 + assign { } { } + assign $1\main_gpiotristateasic0_status[15:0] 16'0000000000000000 + sync always + sync init + update \main_gpiotristateasic0_status $1\main_gpiotristateasic0_status[15:0] + end + attribute \src "ls180.v:1084.12-1084.54" + process $proc$ls180.v:1084$3495 + assign { } { } + assign $0\main_gpiotristateasic0_out_storage[15:0] 16'0000000000000000 + sync always + update \main_gpiotristateasic0_out_storage $0\main_gpiotristateasic0_out_storage[15:0] + sync init + end + attribute \src "ls180.v:1088.12-1088.53" + process $proc$ls180.v:1088$3496 + assign { } { } + assign $1\main_gpiotristateasic1_oe_storage[15:0] 16'0000000000000000 + sync always + sync init + update \main_gpiotristateasic1_oe_storage $1\main_gpiotristateasic1_oe_storage[15:0] + end + attribute \src "ls180.v:1089.5-1089.40" + process $proc$ls180.v:1089$3497 + assign { } { } + assign $1\main_gpiotristateasic1_oe_re[0:0] 1'0 + sync always + sync init + update \main_gpiotristateasic1_oe_re $1\main_gpiotristateasic1_oe_re[0:0] + end + attribute \src "ls180.v:1090.12-1090.49" + process $proc$ls180.v:1090$3498 + assign { } { } + assign $1\main_gpiotristateasic1_status[15:0] 16'0000000000000000 + sync always + sync init + update \main_gpiotristateasic1_status $1\main_gpiotristateasic1_status[15:0] + end + attribute \src "ls180.v:1092.12-1092.54" + process $proc$ls180.v:1092$3499 + assign { } { } + assign $1\main_gpiotristateasic1_out_storage[15:0] 16'0000000000000000 + sync always + sync init + update \main_gpiotristateasic1_out_storage $1\main_gpiotristateasic1_out_storage[15:0] + end + attribute \src "ls180.v:1093.5-1093.41" + process $proc$ls180.v:1093$3500 + assign { } { } + assign $1\main_gpiotristateasic1_out_re[0:0] 1'0 + sync always + sync init + update \main_gpiotristateasic1_out_re $1\main_gpiotristateasic1_out_re[0:0] + end + attribute \src "ls180.v:1099.5-1099.32" + process $proc$ls180.v:1099$3501 + assign { } { } + assign $1\main_spimaster2_done[0:0] 1'0 + sync always + sync init + update \main_spimaster2_done $1\main_spimaster2_done[0:0] + end + attribute \src "ls180.v:1100.5-1100.31" + process $proc$ls180.v:1100$3502 + assign { } { } + assign $1\main_spimaster3_irq[0:0] 1'0 + sync always + sync init + update \main_spimaster3_irq $1\main_spimaster3_irq[0:0] + end + attribute \src "ls180.v:1102.11-1102.38" + process $proc$ls180.v:1102$3503 + assign { } { } + assign $1\main_spimaster5_miso[7:0] 8'00000000 + sync always + sync init + update \main_spimaster5_miso $1\main_spimaster5_miso[7:0] + end + attribute \src "ls180.v:1105.12-1105.47" + process $proc$ls180.v:1105$3504 + assign { } { } + assign $0\main_spimaster8_clk_divider[15:0] 16'0000000000000111 + sync always + update \main_spimaster8_clk_divider $0\main_spimaster8_clk_divider[15:0] + sync init + end + attribute \src "ls180.v:1106.5-1106.33" + process $proc$ls180.v:1106$3505 + assign { } { } + assign $1\main_spimaster9_start[0:0] 1'0 + sync always + sync init + update \main_spimaster9_start $1\main_spimaster9_start[0:0] + end + attribute \src "ls180.v:1108.12-1108.44" + process $proc$ls180.v:1108$3506 + assign { } { } + assign $1\main_spimaster11_storage[15:0] 16'0000000000000000 + sync always + sync init + update \main_spimaster11_storage $1\main_spimaster11_storage[15:0] + end + attribute \src "ls180.v:1109.5-1109.31" + process $proc$ls180.v:1109$3507 + assign { } { } + assign $1\main_spimaster12_re[0:0] 1'0 + sync always + sync init + update \main_spimaster12_re $1\main_spimaster12_re[0:0] + end + attribute \src "ls180.v:1113.11-1113.42" + process $proc$ls180.v:1113$3508 + assign { } { } + assign $1\main_spimaster16_storage[7:0] 8'00000000 + sync always + sync init + update \main_spimaster16_storage $1\main_spimaster16_storage[7:0] + end + attribute \src "ls180.v:1114.5-1114.31" + process $proc$ls180.v:1114$3509 + assign { } { } + assign $1\main_spimaster17_re[0:0] 1'0 + sync always + sync init + update \main_spimaster17_re $1\main_spimaster17_re[0:0] + end + attribute \src "ls180.v:1118.5-1118.36" + process $proc$ls180.v:1118$3510 + assign { } { } + assign $1\main_spimaster21_storage[0:0] 1'1 + sync always + sync init + update \main_spimaster21_storage $1\main_spimaster21_storage[0:0] + end + attribute \src "ls180.v:1119.5-1119.31" + process $proc$ls180.v:1119$3511 + assign { } { } + assign $1\main_spimaster22_re[0:0] 1'0 + sync always + sync init + update \main_spimaster22_re $1\main_spimaster22_re[0:0] + end + attribute \src "ls180.v:1120.5-1120.36" + process $proc$ls180.v:1120$3512 + assign { } { } + assign $1\main_spimaster23_storage[0:0] 1'0 + sync always + sync init + update \main_spimaster23_storage $1\main_spimaster23_storage[0:0] + end + attribute \src "ls180.v:1121.5-1121.31" + process $proc$ls180.v:1121$3513 + assign { } { } + assign $1\main_spimaster24_re[0:0] 1'0 + sync always + sync init + update \main_spimaster24_re $1\main_spimaster24_re[0:0] + end + attribute \src "ls180.v:1122.5-1122.39" + process $proc$ls180.v:1122$3514 + assign { } { } + assign $1\main_spimaster25_clk_enable[0:0] 1'0 + sync always + sync init + update \main_spimaster25_clk_enable $1\main_spimaster25_clk_enable[0:0] + end + attribute \src "ls180.v:1123.5-1123.38" + process $proc$ls180.v:1123$3515 + assign { } { } + assign $1\main_spimaster26_cs_enable[0:0] 1'0 + sync always + sync init + update \main_spimaster26_cs_enable $1\main_spimaster26_cs_enable[0:0] + end + attribute \src "ls180.v:1124.11-1124.40" + process $proc$ls180.v:1124$3516 + assign { } { } + assign $1\main_spimaster27_count[2:0] 3'000 + sync always + sync init + update \main_spimaster27_count $1\main_spimaster27_count[2:0] + end + attribute \src "ls180.v:1125.5-1125.39" + process $proc$ls180.v:1125$3517 + assign { } { } + assign $1\main_spimaster28_mosi_latch[0:0] 1'0 + sync always + sync init + update \main_spimaster28_mosi_latch $1\main_spimaster28_mosi_latch[0:0] + end + attribute \src "ls180.v:1126.5-1126.39" + process $proc$ls180.v:1126$3518 + assign { } { } + assign $1\main_spimaster29_miso_latch[0:0] 1'0 + sync always + sync init + update \main_spimaster29_miso_latch $1\main_spimaster29_miso_latch[0:0] + end + attribute \src "ls180.v:1127.12-1127.48" + process $proc$ls180.v:1127$3519 + assign { } { } + assign $1\main_spimaster30_clk_divider[15:0] 16'0000000000000000 + sync always + sync init + update \main_spimaster30_clk_divider $1\main_spimaster30_clk_divider[15:0] + end + attribute \src "ls180.v:1130.11-1130.44" + process $proc$ls180.v:1130$3520 + assign { } { } + assign $1\main_spimaster33_mosi_data[7:0] 8'00000000 + sync always + sync init + update \main_spimaster33_mosi_data $1\main_spimaster33_mosi_data[7:0] + end + attribute \src "ls180.v:1131.11-1131.43" + process $proc$ls180.v:1131$3521 + assign { } { } + assign $1\main_spimaster34_mosi_sel[2:0] 3'000 + sync always + sync init + update \main_spimaster34_mosi_sel $1\main_spimaster34_mosi_sel[2:0] + end + attribute \src "ls180.v:1132.11-1132.44" + process $proc$ls180.v:1132$3522 + assign { } { } + assign $1\main_spimaster35_miso_data[7:0] 8'00000000 + sync always + sync init + update \main_spimaster35_miso_data $1\main_spimaster35_miso_data[7:0] + end + attribute \src "ls180.v:1135.5-1135.32" + process $proc$ls180.v:1135$3523 + assign { } { } + assign $1\main_spisdcard_done0[0:0] 1'0 + sync always + sync init + update \main_spisdcard_done0 $1\main_spisdcard_done0[0:0] + end + attribute \src "ls180.v:1136.5-1136.30" + process $proc$ls180.v:1136$3524 + assign { } { } + assign $1\main_spisdcard_irq[0:0] 1'0 + sync always + sync init + update \main_spisdcard_irq $1\main_spisdcard_irq[0:0] + end + attribute \src "ls180.v:1138.11-1138.37" + process $proc$ls180.v:1138$3525 + assign { } { } + assign $1\main_spisdcard_miso[7:0] 8'00000000 + sync always + sync init + update \main_spisdcard_miso $1\main_spisdcard_miso[7:0] + end + attribute \src "ls180.v:114.11-114.55" + process $proc$ls180.v:114$3148 + assign { } { } + assign $0\main_libresocsim_libresoc_jtag_wb_cti[2:0] 3'000 + sync always + update \main_libresocsim_libresoc_jtag_wb_cti $0\main_libresocsim_libresoc_jtag_wb_cti[2:0] + sync init + end + attribute \src "ls180.v:1142.5-1142.33" + process $proc$ls180.v:1142$3526 + assign { } { } + assign $1\main_spisdcard_start1[0:0] 1'0 + sync always + sync init + update \main_spisdcard_start1 $1\main_spisdcard_start1[0:0] + end + attribute \src "ls180.v:1144.12-1144.50" + process $proc$ls180.v:1144$3527 + assign { } { } + assign $1\main_spisdcard_control_storage[15:0] 16'0000000000000000 + sync always + sync init + update \main_spisdcard_control_storage $1\main_spisdcard_control_storage[15:0] + end + attribute \src "ls180.v:1145.5-1145.37" + process $proc$ls180.v:1145$3528 + assign { } { } + assign $1\main_spisdcard_control_re[0:0] 1'0 + sync always + sync init + update \main_spisdcard_control_re $1\main_spisdcard_control_re[0:0] + end + attribute \src "ls180.v:1149.11-1149.45" + process $proc$ls180.v:1149$3529 + assign { } { } + assign $1\main_spisdcard_mosi_storage[7:0] 8'00000000 + sync always + sync init + update \main_spisdcard_mosi_storage $1\main_spisdcard_mosi_storage[7:0] + end + attribute \src "ls180.v:115.11-115.55" + process $proc$ls180.v:115$3149 + assign { } { } + assign $0\main_libresocsim_libresoc_jtag_wb_bte[1:0] 2'00 + sync always + update \main_libresocsim_libresoc_jtag_wb_bte $0\main_libresocsim_libresoc_jtag_wb_bte[1:0] + sync init + end + attribute \src "ls180.v:1150.5-1150.34" + process $proc$ls180.v:1150$3530 + assign { } { } + assign $1\main_spisdcard_mosi_re[0:0] 1'0 + sync always + sync init + update \main_spisdcard_mosi_re $1\main_spisdcard_mosi_re[0:0] + end + attribute \src "ls180.v:1154.5-1154.37" + process $proc$ls180.v:1154$3531 + assign { } { } + assign $1\main_spisdcard_cs_storage[0:0] 1'1 + sync always + sync init + update \main_spisdcard_cs_storage $1\main_spisdcard_cs_storage[0:0] + end + attribute \src "ls180.v:1155.5-1155.32" + process $proc$ls180.v:1155$3532 + assign { } { } + assign $1\main_spisdcard_cs_re[0:0] 1'0 + sync always + sync init + update \main_spisdcard_cs_re $1\main_spisdcard_cs_re[0:0] + end + attribute \src "ls180.v:1156.5-1156.43" + process $proc$ls180.v:1156$3533 + assign { } { } + assign $1\main_spisdcard_loopback_storage[0:0] 1'0 + sync always + sync init + update \main_spisdcard_loopback_storage $1\main_spisdcard_loopback_storage[0:0] + end + attribute \src "ls180.v:1157.5-1157.38" + process $proc$ls180.v:1157$3534 + assign { } { } + assign $1\main_spisdcard_loopback_re[0:0] 1'0 + sync always + sync init + update \main_spisdcard_loopback_re $1\main_spisdcard_loopback_re[0:0] + end + attribute \src "ls180.v:1158.5-1158.37" + process $proc$ls180.v:1158$3535 + assign { } { } + assign $1\main_spisdcard_clk_enable[0:0] 1'0 + sync always + sync init + update \main_spisdcard_clk_enable $1\main_spisdcard_clk_enable[0:0] + end + attribute \src "ls180.v:1159.5-1159.36" + process $proc$ls180.v:1159$3536 + assign { } { } + assign $1\main_spisdcard_cs_enable[0:0] 1'0 + sync always + sync init + update \main_spisdcard_cs_enable $1\main_spisdcard_cs_enable[0:0] + end + attribute \src "ls180.v:1160.11-1160.38" + process $proc$ls180.v:1160$3537 + assign { } { } + assign $1\main_spisdcard_count[2:0] 3'000 + sync always + sync init + update \main_spisdcard_count $1\main_spisdcard_count[2:0] + end + attribute \src "ls180.v:1161.5-1161.37" + process $proc$ls180.v:1161$3538 + assign { } { } + assign $1\main_spisdcard_mosi_latch[0:0] 1'0 + sync always + sync init + update \main_spisdcard_mosi_latch $1\main_spisdcard_mosi_latch[0:0] + end + attribute \src "ls180.v:1162.5-1162.37" + process $proc$ls180.v:1162$3539 + assign { } { } + assign $1\main_spisdcard_miso_latch[0:0] 1'0 + sync always + sync init + update \main_spisdcard_miso_latch $1\main_spisdcard_miso_latch[0:0] + end + attribute \src "ls180.v:1163.12-1163.47" + process $proc$ls180.v:1163$3540 + assign { } { } + assign $1\main_spisdcard_clk_divider1[15:0] 16'0000000000000000 + sync always + sync init + update \main_spisdcard_clk_divider1 $1\main_spisdcard_clk_divider1[15:0] + end + attribute \src "ls180.v:1166.11-1166.42" + process $proc$ls180.v:1166$3541 + assign { } { } + assign $1\main_spisdcard_mosi_data[7:0] 8'00000000 + sync always + sync init + update \main_spisdcard_mosi_data $1\main_spisdcard_mosi_data[7:0] + end + attribute \src "ls180.v:1167.11-1167.41" + process $proc$ls180.v:1167$3542 + assign { } { } + assign $1\main_spisdcard_mosi_sel[2:0] 3'000 + sync always + sync init + update \main_spisdcard_mosi_sel $1\main_spisdcard_mosi_sel[2:0] + end + attribute \src "ls180.v:1168.11-1168.42" + process $proc$ls180.v:1168$3543 + assign { } { } + assign $1\main_spisdcard_miso_data[7:0] 8'00000000 + sync always + sync init + update \main_spisdcard_miso_data $1\main_spisdcard_miso_data[7:0] + end + attribute \src "ls180.v:1169.12-1169.45" + process $proc$ls180.v:1169$3544 + assign { } { } + assign $1\main_spimaster1_storage[15:0] 16'0000000001111101 + sync always + sync init + update \main_spimaster1_storage $1\main_spimaster1_storage[15:0] + end + attribute \src "ls180.v:1170.5-1170.30" + process $proc$ls180.v:1170$3545 + assign { } { } + assign $1\main_spimaster1_re[0:0] 1'0 + sync always + sync init + update \main_spimaster1_re $1\main_spimaster1_re[0:0] + end + attribute \src "ls180.v:1172.12-1172.30" + process $proc$ls180.v:1172$3546 + assign { } { } + assign $1\main_dummy[23:0] 24'000000000000000000000000 + sync always + sync init + update \main_dummy $1\main_dummy[23:0] + end + attribute \src "ls180.v:1176.12-1176.37" + process $proc$ls180.v:1176$3547 + assign { } { } + assign $1\main_pwm0_counter[31:0] 0 + sync always + sync init + update \main_pwm0_counter $1\main_pwm0_counter[31:0] + end + attribute \src "ls180.v:1177.5-1177.36" + process $proc$ls180.v:1177$3548 + assign { } { } + assign $1\main_pwm0_enable_storage[0:0] 1'0 + sync always + sync init + update \main_pwm0_enable_storage $1\main_pwm0_enable_storage[0:0] + end + attribute \src "ls180.v:1178.5-1178.31" + process $proc$ls180.v:1178$3549 + assign { } { } + assign $1\main_pwm0_enable_re[0:0] 1'0 + sync always + sync init + update \main_pwm0_enable_re $1\main_pwm0_enable_re[0:0] + end + attribute \src "ls180.v:1179.12-1179.43" + process $proc$ls180.v:1179$3550 + assign { } { } + assign $1\main_pwm0_width_storage[31:0] 0 + sync always + sync init + update \main_pwm0_width_storage $1\main_pwm0_width_storage[31:0] + end + attribute \src "ls180.v:1180.5-1180.30" + process $proc$ls180.v:1180$3551 + assign { } { } + assign $1\main_pwm0_width_re[0:0] 1'0 + sync always + sync init + update \main_pwm0_width_re $1\main_pwm0_width_re[0:0] + end + attribute \src "ls180.v:1181.12-1181.44" + process $proc$ls180.v:1181$3552 + assign { } { } + assign $1\main_pwm0_period_storage[31:0] 0 + sync always + sync init + update \main_pwm0_period_storage $1\main_pwm0_period_storage[31:0] + end + attribute \src "ls180.v:1182.5-1182.31" + process $proc$ls180.v:1182$3553 + assign { } { } + assign $1\main_pwm0_period_re[0:0] 1'0 + sync always + sync init + update \main_pwm0_period_re $1\main_pwm0_period_re[0:0] + end + attribute \src "ls180.v:1186.12-1186.37" + process $proc$ls180.v:1186$3554 + assign { } { } + assign $1\main_pwm1_counter[31:0] 0 + sync always + sync init + update \main_pwm1_counter $1\main_pwm1_counter[31:0] + end + attribute \src "ls180.v:1187.5-1187.36" + process $proc$ls180.v:1187$3555 + assign { } { } + assign $1\main_pwm1_enable_storage[0:0] 1'0 + sync always + sync init + update \main_pwm1_enable_storage $1\main_pwm1_enable_storage[0:0] + end + attribute \src "ls180.v:1188.5-1188.31" + process $proc$ls180.v:1188$3556 + assign { } { } + assign $1\main_pwm1_enable_re[0:0] 1'0 + sync always + sync init + update \main_pwm1_enable_re $1\main_pwm1_enable_re[0:0] + end + attribute \src "ls180.v:1189.12-1189.43" + process $proc$ls180.v:1189$3557 + assign { } { } + assign $1\main_pwm1_width_storage[31:0] 0 + sync always + sync init + update \main_pwm1_width_storage $1\main_pwm1_width_storage[31:0] + end + attribute \src "ls180.v:1190.5-1190.30" + process $proc$ls180.v:1190$3558 + assign { } { } + assign $1\main_pwm1_width_re[0:0] 1'0 + sync always + sync init + update \main_pwm1_width_re $1\main_pwm1_width_re[0:0] + end + attribute \src "ls180.v:1191.12-1191.44" + process $proc$ls180.v:1191$3559 + assign { } { } + assign $1\main_pwm1_period_storage[31:0] 0 + sync always + sync init + update \main_pwm1_period_storage $1\main_pwm1_period_storage[31:0] + end + attribute \src "ls180.v:1192.5-1192.31" + process $proc$ls180.v:1192$3560 + assign { } { } + assign $1\main_pwm1_period_re[0:0] 1'0 + sync always + sync init + update \main_pwm1_period_re $1\main_pwm1_period_re[0:0] + end + attribute \src "ls180.v:1196.11-1196.34" + process $proc$ls180.v:1196$3561 + assign { } { } + assign $1\main_i2c_storage[2:0] 3'000 + sync always + sync init + update \main_i2c_storage $1\main_i2c_storage[2:0] + end + attribute \src "ls180.v:1197.5-1197.23" + process $proc$ls180.v:1197$3562 + assign { } { } + assign $1\main_i2c_re[0:0] 1'0 + sync always + sync init + update \main_i2c_re $1\main_i2c_re[0:0] + end + attribute \src "ls180.v:1203.11-1203.46" + process $proc$ls180.v:1203$3563 + assign { } { } + assign $1\main_sdphy_clocker_storage[8:0] 9'100000000 + sync always + sync init + update \main_sdphy_clocker_storage $1\main_sdphy_clocker_storage[8:0] + end + attribute \src "ls180.v:1204.5-1204.33" + process $proc$ls180.v:1204$3564 + assign { } { } + assign $1\main_sdphy_clocker_re[0:0] 1'0 + sync always + sync init + update \main_sdphy_clocker_re $1\main_sdphy_clocker_re[0:0] + end + attribute \src "ls180.v:1206.5-1206.35" + process $proc$ls180.v:1206$3565 + assign { } { } + assign $1\main_sdphy_clocker_clk0[0:0] 1'0 + sync always + sync init + update \main_sdphy_clocker_clk0 $1\main_sdphy_clocker_clk0[0:0] + end + attribute \src "ls180.v:1208.11-1208.41" + process $proc$ls180.v:1208$3566 + assign { } { } + assign $1\main_sdphy_clocker_clks[8:0] 9'000000000 + sync always + sync init + update \main_sdphy_clocker_clks $1\main_sdphy_clocker_clks[8:0] + end + attribute \src "ls180.v:1209.5-1209.35" + process $proc$ls180.v:1209$3567 + assign { } { } + assign $1\main_sdphy_clocker_clk1[0:0] 1'0 + sync always + sync init + update \main_sdphy_clocker_clk1 $1\main_sdphy_clocker_clk1[0:0] + end + attribute \src "ls180.v:1210.5-1210.36" + process $proc$ls180.v:1210$3568 + assign { } { } + assign $1\main_sdphy_clocker_clk_d[0:0] 1'0 + sync always + sync init + update \main_sdphy_clocker_clk_d $1\main_sdphy_clocker_clk_d[0:0] + end + attribute \src "ls180.v:1214.5-1214.40" + process $proc$ls180.v:1214$3569 + assign { } { } + assign $0\main_sdphy_init_initialize_w[0:0] 1'0 + sync always + update \main_sdphy_init_initialize_w $0\main_sdphy_init_initialize_w[0:0] + sync init + end + attribute \src "ls180.v:1219.5-1219.48" + process $proc$ls180.v:1219$3570 + assign { } { } + assign $1\main_sdphy_init_pads_out_payload_clk[0:0] 1'0 + sync always + sync init + update \main_sdphy_init_pads_out_payload_clk $1\main_sdphy_init_pads_out_payload_clk[0:0] + end + attribute \src "ls180.v:1220.5-1220.50" + process $proc$ls180.v:1220$3571 + assign { } { } + assign $1\main_sdphy_init_pads_out_payload_cmd_o[0:0] 1'0 + sync always + sync init + update \main_sdphy_init_pads_out_payload_cmd_o $1\main_sdphy_init_pads_out_payload_cmd_o[0:0] + end + attribute \src "ls180.v:1221.5-1221.51" + process $proc$ls180.v:1221$3572 + assign { } { } + assign $1\main_sdphy_init_pads_out_payload_cmd_oe[0:0] 1'0 + sync always + sync init + update \main_sdphy_init_pads_out_payload_cmd_oe $1\main_sdphy_init_pads_out_payload_cmd_oe[0:0] + end + attribute \src "ls180.v:1222.11-1222.57" + process $proc$ls180.v:1222$3573 + assign { } { } + assign $1\main_sdphy_init_pads_out_payload_data_o[3:0] 4'0000 + sync always + sync init + update \main_sdphy_init_pads_out_payload_data_o $1\main_sdphy_init_pads_out_payload_data_o[3:0] + end + attribute \src "ls180.v:1223.5-1223.52" + process $proc$ls180.v:1223$3574 + assign { } { } + assign $1\main_sdphy_init_pads_out_payload_data_oe[0:0] 1'0 + sync always + sync init + update \main_sdphy_init_pads_out_payload_data_oe $1\main_sdphy_init_pads_out_payload_data_oe[0:0] + end + attribute \src "ls180.v:1224.11-1224.39" + process $proc$ls180.v:1224$3575 + assign { } { } + assign $1\main_sdphy_init_count[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_init_count $1\main_sdphy_init_count[7:0] + end + attribute \src "ls180.v:1229.5-1229.48" + process $proc$ls180.v:1229$3576 + assign { } { } + assign $1\main_sdphy_cmdw_pads_out_payload_clk[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdw_pads_out_payload_clk $1\main_sdphy_cmdw_pads_out_payload_clk[0:0] + end + attribute \src "ls180.v:1230.5-1230.50" + process $proc$ls180.v:1230$3577 + assign { } { } + assign $1\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdw_pads_out_payload_cmd_o $1\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] + end + attribute \src "ls180.v:1231.5-1231.51" + process $proc$ls180.v:1231$3578 + assign { } { } + assign $1\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdw_pads_out_payload_cmd_oe $1\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] + end + attribute \src "ls180.v:1232.11-1232.57" + process $proc$ls180.v:1232$3579 + assign { } { } + assign $0\main_sdphy_cmdw_pads_out_payload_data_o[3:0] 4'0000 + sync always + update \main_sdphy_cmdw_pads_out_payload_data_o $0\main_sdphy_cmdw_pads_out_payload_data_o[3:0] + sync init + end + attribute \src "ls180.v:1233.5-1233.52" + process $proc$ls180.v:1233$3580 + assign { } { } + assign $0\main_sdphy_cmdw_pads_out_payload_data_oe[0:0] 1'0 + sync always + update \main_sdphy_cmdw_pads_out_payload_data_oe $0\main_sdphy_cmdw_pads_out_payload_data_oe[0:0] + sync init + end + attribute \src "ls180.v:1234.5-1234.38" + process $proc$ls180.v:1234$3581 + assign { } { } + assign $1\main_sdphy_cmdw_sink_valid[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdw_sink_valid $1\main_sdphy_cmdw_sink_valid[0:0] + end + attribute \src "ls180.v:1235.5-1235.38" + process $proc$ls180.v:1235$3582 + assign { } { } + assign $1\main_sdphy_cmdw_sink_ready[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdw_sink_ready $1\main_sdphy_cmdw_sink_ready[0:0] + end + attribute \src "ls180.v:1236.5-1236.37" + process $proc$ls180.v:1236$3583 + assign { } { } + assign $1\main_sdphy_cmdw_sink_last[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdw_sink_last $1\main_sdphy_cmdw_sink_last[0:0] + end + attribute \src "ls180.v:1237.11-1237.51" + process $proc$ls180.v:1237$3584 + assign { } { } + assign $1\main_sdphy_cmdw_sink_payload_data[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_cmdw_sink_payload_data $1\main_sdphy_cmdw_sink_payload_data[7:0] + end + attribute \src "ls180.v:1238.5-1238.32" + process $proc$ls180.v:1238$3585 + assign { } { } + assign $1\main_sdphy_cmdw_done[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdw_done $1\main_sdphy_cmdw_done[0:0] + end + attribute \src "ls180.v:1239.11-1239.39" + process $proc$ls180.v:1239$3586 + assign { } { } + assign $1\main_sdphy_cmdw_count[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_cmdw_count $1\main_sdphy_cmdw_count[7:0] + end + attribute \src "ls180.v:1242.5-1242.49" + process $proc$ls180.v:1242$3587 + assign { } { } + assign $0\main_sdphy_cmdr_pads_in_pads_in_first[0:0] 1'0 + sync always + update \main_sdphy_cmdr_pads_in_pads_in_first $0\main_sdphy_cmdr_pads_in_pads_in_first[0:0] + sync init + end + attribute \src "ls180.v:1243.5-1243.48" + process $proc$ls180.v:1243$3588 + assign { } { } + assign $0\main_sdphy_cmdr_pads_in_pads_in_last[0:0] 1'0 + sync always + update \main_sdphy_cmdr_pads_in_pads_in_last $0\main_sdphy_cmdr_pads_in_pads_in_last[0:0] + sync init + end + attribute \src "ls180.v:1244.5-1244.55" + process $proc$ls180.v:1244$3589 + assign { } { } + assign $0\main_sdphy_cmdr_pads_in_pads_in_payload_clk[0:0] 1'0 + sync always + update \main_sdphy_cmdr_pads_in_pads_in_payload_clk $0\main_sdphy_cmdr_pads_in_pads_in_payload_clk[0:0] + sync init + end + attribute \src "ls180.v:1246.5-1246.57" + process $proc$ls180.v:1246$3590 + assign { } { } + assign $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_o[0:0] 1'0 + sync always + update \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_o $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_o[0:0] + sync init + end + attribute \src "ls180.v:1247.5-1247.58" + process $proc$ls180.v:1247$3591 + assign { } { } + assign $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_oe[0:0] 1'0 + sync always + update \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_oe $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_oe[0:0] + sync init + end + attribute \src "ls180.v:1249.11-1249.64" + process $proc$ls180.v:1249$3592 + assign { } { } + assign $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_o[3:0] 4'0000 + sync always + update \main_sdphy_cmdr_pads_in_pads_in_payload_data_o $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_o[3:0] + sync init + end + attribute \src "ls180.v:1250.5-1250.59" + process $proc$ls180.v:1250$3593 + assign { } { } + assign $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_oe[0:0] 1'0 + sync always + update \main_sdphy_cmdr_pads_in_pads_in_payload_data_oe $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_oe[0:0] + sync init + end + attribute \src "ls180.v:1252.5-1252.48" + process $proc$ls180.v:1252$3594 + assign { } { } + assign $1\main_sdphy_cmdr_pads_out_payload_clk[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_pads_out_payload_clk $1\main_sdphy_cmdr_pads_out_payload_clk[0:0] + end + attribute \src "ls180.v:1253.5-1253.50" + process $proc$ls180.v:1253$3595 + assign { } { } + assign $1\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_pads_out_payload_cmd_o $1\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] + end + attribute \src "ls180.v:1254.5-1254.51" + process $proc$ls180.v:1254$3596 + assign { } { } + assign $1\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_pads_out_payload_cmd_oe $1\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] + end + attribute \src "ls180.v:1255.11-1255.57" + process $proc$ls180.v:1255$3597 + assign { } { } + assign $0\main_sdphy_cmdr_pads_out_payload_data_o[3:0] 4'0000 + sync always + update \main_sdphy_cmdr_pads_out_payload_data_o $0\main_sdphy_cmdr_pads_out_payload_data_o[3:0] + sync init + end + attribute \src "ls180.v:1256.5-1256.52" + process $proc$ls180.v:1256$3598 + assign { } { } + assign $0\main_sdphy_cmdr_pads_out_payload_data_oe[0:0] 1'0 + sync always + update \main_sdphy_cmdr_pads_out_payload_data_oe $0\main_sdphy_cmdr_pads_out_payload_data_oe[0:0] + sync init + end + attribute \src "ls180.v:1257.5-1257.38" + process $proc$ls180.v:1257$3599 + assign { } { } + assign $1\main_sdphy_cmdr_sink_valid[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_sink_valid $1\main_sdphy_cmdr_sink_valid[0:0] + end + attribute \src "ls180.v:1258.5-1258.38" + process $proc$ls180.v:1258$3600 + assign { } { } + assign $1\main_sdphy_cmdr_sink_ready[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_sink_ready $1\main_sdphy_cmdr_sink_ready[0:0] + end + attribute \src "ls180.v:1259.5-1259.37" + process $proc$ls180.v:1259$3601 + assign { } { } + assign $1\main_sdphy_cmdr_sink_last[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_sink_last $1\main_sdphy_cmdr_sink_last[0:0] + end + attribute \src "ls180.v:1260.11-1260.53" + process $proc$ls180.v:1260$3602 + assign { } { } + assign $1\main_sdphy_cmdr_sink_payload_length[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_cmdr_sink_payload_length $1\main_sdphy_cmdr_sink_payload_length[7:0] + end + attribute \src "ls180.v:1261.5-1261.40" + process $proc$ls180.v:1261$3603 + assign { } { } + assign $1\main_sdphy_cmdr_source_valid[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_source_valid $1\main_sdphy_cmdr_source_valid[0:0] + end + attribute \src "ls180.v:1262.5-1262.40" + process $proc$ls180.v:1262$3604 + assign { } { } + assign $1\main_sdphy_cmdr_source_ready[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_source_ready $1\main_sdphy_cmdr_source_ready[0:0] + end + attribute \src "ls180.v:1263.5-1263.39" + process $proc$ls180.v:1263$3605 + assign { } { } + assign $1\main_sdphy_cmdr_source_last[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_source_last $1\main_sdphy_cmdr_source_last[0:0] + end + attribute \src "ls180.v:1264.11-1264.53" + process $proc$ls180.v:1264$3606 + assign { } { } + assign $1\main_sdphy_cmdr_source_payload_data[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_cmdr_source_payload_data $1\main_sdphy_cmdr_source_payload_data[7:0] + end + attribute \src "ls180.v:1265.11-1265.55" + process $proc$ls180.v:1265$3607 + assign { } { } + assign $1\main_sdphy_cmdr_source_payload_status[2:0] 3'000 + sync always + sync init + update \main_sdphy_cmdr_source_payload_status $1\main_sdphy_cmdr_source_payload_status[2:0] + end + attribute \src "ls180.v:1266.12-1266.48" + process $proc$ls180.v:1266$3608 + assign { } { } + assign $1\main_sdphy_cmdr_timeout[31:0] 500000 + sync always + sync init + update \main_sdphy_cmdr_timeout $1\main_sdphy_cmdr_timeout[31:0] + end + attribute \src "ls180.v:1267.11-1267.39" + process $proc$ls180.v:1267$3609 + assign { } { } + assign $1\main_sdphy_cmdr_count[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_cmdr_count $1\main_sdphy_cmdr_count[7:0] + end + attribute \src "ls180.v:1269.5-1269.46" + process $proc$ls180.v:1269$3610 + assign { } { } + assign $0\main_sdphy_cmdr_cmdr_pads_in_ready[0:0] 1'0 + sync always + update \main_sdphy_cmdr_cmdr_pads_in_ready $0\main_sdphy_cmdr_cmdr_pads_in_ready[0:0] + sync init + end + attribute \src "ls180.v:1280.5-1280.53" + process $proc$ls180.v:1280$3611 + assign { } { } + assign $1\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_cmdr_source_source_ready0 $1\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] + end + attribute \src "ls180.v:1285.5-1285.36" + process $proc$ls180.v:1285$3612 + assign { } { } + assign $1\main_sdphy_cmdr_cmdr_run[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_cmdr_run $1\main_sdphy_cmdr_cmdr_run[0:0] + end + attribute \src "ls180.v:1288.5-1288.53" + process $proc$ls180.v:1288$3613 + assign { } { } + assign $0\main_sdphy_cmdr_cmdr_converter_sink_first[0:0] 1'0 + sync always + update \main_sdphy_cmdr_cmdr_converter_sink_first $0\main_sdphy_cmdr_cmdr_converter_sink_first[0:0] + sync init + end + attribute \src "ls180.v:1289.5-1289.52" + process $proc$ls180.v:1289$3614 + assign { } { } + assign $0\main_sdphy_cmdr_cmdr_converter_sink_last[0:0] 1'0 + sync always + update \main_sdphy_cmdr_cmdr_converter_sink_last $0\main_sdphy_cmdr_cmdr_converter_sink_last[0:0] + sync init + end + attribute \src "ls180.v:1293.5-1293.55" + process $proc$ls180.v:1293$3615 + assign { } { } + assign $1\main_sdphy_cmdr_cmdr_converter_source_first[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_cmdr_converter_source_first $1\main_sdphy_cmdr_cmdr_converter_source_first[0:0] + end + attribute \src "ls180.v:1294.5-1294.54" + process $proc$ls180.v:1294$3616 + assign { } { } + assign $1\main_sdphy_cmdr_cmdr_converter_source_last[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_cmdr_converter_source_last $1\main_sdphy_cmdr_cmdr_converter_source_last[0:0] + end + attribute \src "ls180.v:1295.11-1295.68" + process $proc$ls180.v:1295$3617 + assign { } { } + assign $1\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_cmdr_cmdr_converter_source_payload_data $1\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] + end + attribute \src "ls180.v:1296.11-1296.81" + process $proc$ls180.v:1296$3618 + assign { } { } + assign $1\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] 4'0000 + sync always + sync init + update \main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count $1\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] + end + attribute \src "ls180.v:1297.11-1297.54" + process $proc$ls180.v:1297$3619 + assign { } { } + assign $1\main_sdphy_cmdr_cmdr_converter_demux[2:0] 3'000 + sync always + sync init + update \main_sdphy_cmdr_cmdr_converter_demux $1\main_sdphy_cmdr_cmdr_converter_demux[2:0] + end + attribute \src "ls180.v:1299.5-1299.53" + process $proc$ls180.v:1299$3620 + assign { } { } + assign $1\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_cmdr_converter_strobe_all $1\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] + end + attribute \src "ls180.v:1310.5-1310.49" + process $proc$ls180.v:1310$3621 + assign { } { } + assign $1\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_cmdr_buf_source_valid $1\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] + end + attribute \src "ls180.v:1312.5-1312.49" + process $proc$ls180.v:1312$3622 + assign { } { } + assign $1\main_sdphy_cmdr_cmdr_buf_source_first[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_cmdr_buf_source_first $1\main_sdphy_cmdr_cmdr_buf_source_first[0:0] + end + attribute \src "ls180.v:1313.5-1313.48" + process $proc$ls180.v:1313$3623 + assign { } { } + assign $1\main_sdphy_cmdr_cmdr_buf_source_last[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_cmdr_buf_source_last $1\main_sdphy_cmdr_cmdr_buf_source_last[0:0] + end + attribute \src "ls180.v:1314.11-1314.62" + process $proc$ls180.v:1314$3624 + assign { } { } + assign $1\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_cmdr_cmdr_buf_source_payload_data $1\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0] + end + attribute \src "ls180.v:1315.5-1315.38" + process $proc$ls180.v:1315$3625 + assign { } { } + assign $1\main_sdphy_cmdr_cmdr_reset[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_cmdr_reset $1\main_sdphy_cmdr_cmdr_reset[0:0] + end + attribute \src "ls180.v:1320.5-1320.49" + process $proc$ls180.v:1320$3626 + assign { } { } + assign $1\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_pads_out_payload_clk $1\main_sdphy_dataw_pads_out_payload_clk[0:0] + end + attribute \src "ls180.v:1321.5-1321.51" + process $proc$ls180.v:1321$3627 + assign { } { } + assign $0\main_sdphy_dataw_pads_out_payload_cmd_o[0:0] 1'0 + sync always + update \main_sdphy_dataw_pads_out_payload_cmd_o $0\main_sdphy_dataw_pads_out_payload_cmd_o[0:0] + sync init + end + attribute \src "ls180.v:1322.5-1322.52" + process $proc$ls180.v:1322$3628 + assign { } { } + assign $0\main_sdphy_dataw_pads_out_payload_cmd_oe[0:0] 1'0 + sync always + update \main_sdphy_dataw_pads_out_payload_cmd_oe $0\main_sdphy_dataw_pads_out_payload_cmd_oe[0:0] + sync init + end + attribute \src "ls180.v:1323.11-1323.58" + process $proc$ls180.v:1323$3629 + assign { } { } + assign $1\main_sdphy_dataw_pads_out_payload_data_o[3:0] 4'0000 + sync always + sync init + update \main_sdphy_dataw_pads_out_payload_data_o $1\main_sdphy_dataw_pads_out_payload_data_o[3:0] + end + attribute \src "ls180.v:1324.5-1324.53" + process $proc$ls180.v:1324$3630 + assign { } { } + assign $1\main_sdphy_dataw_pads_out_payload_data_oe[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_pads_out_payload_data_oe $1\main_sdphy_dataw_pads_out_payload_data_oe[0:0] + end + attribute \src "ls180.v:1325.5-1325.39" + process $proc$ls180.v:1325$3631 + assign { } { } + assign $1\main_sdphy_dataw_sink_valid[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_sink_valid $1\main_sdphy_dataw_sink_valid[0:0] + end + attribute \src "ls180.v:1326.5-1326.39" + process $proc$ls180.v:1326$3632 + assign { } { } + assign $1\main_sdphy_dataw_sink_ready[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_sink_ready $1\main_sdphy_dataw_sink_ready[0:0] + end + attribute \src "ls180.v:1327.5-1327.39" + process $proc$ls180.v:1327$3633 + assign { } { } + assign $1\main_sdphy_dataw_sink_first[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_sink_first $1\main_sdphy_dataw_sink_first[0:0] + end + attribute \src "ls180.v:1328.5-1328.38" + process $proc$ls180.v:1328$3634 + assign { } { } + assign $1\main_sdphy_dataw_sink_last[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_sink_last $1\main_sdphy_dataw_sink_last[0:0] + end + attribute \src "ls180.v:1329.11-1329.52" + process $proc$ls180.v:1329$3635 + assign { } { } + assign $1\main_sdphy_dataw_sink_payload_data[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_dataw_sink_payload_data $1\main_sdphy_dataw_sink_payload_data[7:0] + end + attribute \src "ls180.v:1330.5-1330.33" + process $proc$ls180.v:1330$3636 + assign { } { } + assign $1\main_sdphy_dataw_stop[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_stop $1\main_sdphy_dataw_stop[0:0] + end + attribute \src "ls180.v:1331.11-1331.40" + process $proc$ls180.v:1331$3637 + assign { } { } + assign $1\main_sdphy_dataw_count[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_dataw_count $1\main_sdphy_dataw_count[7:0] + end + attribute \src "ls180.v:1332.5-1332.50" + process $proc$ls180.v:1332$3638 + assign { } { } + assign $0\main_sdphy_dataw_pads_in_pads_in_valid[0:0] 1'0 + sync always + update \main_sdphy_dataw_pads_in_pads_in_valid $0\main_sdphy_dataw_pads_in_pads_in_valid[0:0] + sync init + end + attribute \src "ls180.v:1334.5-1334.50" + process $proc$ls180.v:1334$3639 + assign { } { } + assign $0\main_sdphy_dataw_pads_in_pads_in_first[0:0] 1'0 + sync always + update \main_sdphy_dataw_pads_in_pads_in_first $0\main_sdphy_dataw_pads_in_pads_in_first[0:0] + sync init + end + attribute \src "ls180.v:1335.5-1335.49" + process $proc$ls180.v:1335$3640 + assign { } { } + assign $0\main_sdphy_dataw_pads_in_pads_in_last[0:0] 1'0 + sync always + update \main_sdphy_dataw_pads_in_pads_in_last $0\main_sdphy_dataw_pads_in_pads_in_last[0:0] + sync init + end + attribute \src "ls180.v:1336.5-1336.56" + process $proc$ls180.v:1336$3641 + assign { } { } + assign $0\main_sdphy_dataw_pads_in_pads_in_payload_clk[0:0] 1'0 + sync always + update \main_sdphy_dataw_pads_in_pads_in_payload_clk $0\main_sdphy_dataw_pads_in_pads_in_payload_clk[0:0] + sync init + end + attribute \src "ls180.v:1337.5-1337.58" + process $proc$ls180.v:1337$3642 + assign { } { } + assign $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_i[0:0] 1'0 + sync always + update \main_sdphy_dataw_pads_in_pads_in_payload_cmd_i $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_i[0:0] + sync init + end + attribute \src "ls180.v:1338.5-1338.58" + process $proc$ls180.v:1338$3643 + assign { } { } + assign $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_o[0:0] 1'0 + sync always + update \main_sdphy_dataw_pads_in_pads_in_payload_cmd_o $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_o[0:0] + sync init + end + attribute \src "ls180.v:1339.5-1339.59" + process $proc$ls180.v:1339$3644 + assign { } { } + assign $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_oe[0:0] 1'0 + sync always + update \main_sdphy_dataw_pads_in_pads_in_payload_cmd_oe $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_oe[0:0] + sync init + end + attribute \src "ls180.v:1340.11-1340.65" + process $proc$ls180.v:1340$3645 + assign { } { } + assign $0\main_sdphy_dataw_pads_in_pads_in_payload_data_i[3:0] 4'0000 + sync always + update \main_sdphy_dataw_pads_in_pads_in_payload_data_i $0\main_sdphy_dataw_pads_in_pads_in_payload_data_i[3:0] + sync init + end + attribute \src "ls180.v:1341.11-1341.65" + process $proc$ls180.v:1341$3646 + assign { } { } + assign $0\main_sdphy_dataw_pads_in_pads_in_payload_data_o[3:0] 4'0000 + sync always + update \main_sdphy_dataw_pads_in_pads_in_payload_data_o $0\main_sdphy_dataw_pads_in_pads_in_payload_data_o[3:0] + sync init + end + attribute \src "ls180.v:1342.5-1342.60" + process $proc$ls180.v:1342$3647 + assign { } { } + assign $0\main_sdphy_dataw_pads_in_pads_in_payload_data_oe[0:0] 1'0 + sync always + update \main_sdphy_dataw_pads_in_pads_in_payload_data_oe $0\main_sdphy_dataw_pads_in_pads_in_payload_data_oe[0:0] + sync init + end + attribute \src "ls180.v:1343.5-1343.34" + process $proc$ls180.v:1343$3648 + assign { } { } + assign $1\main_sdphy_dataw_start[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_start $1\main_sdphy_dataw_start[0:0] + end + attribute \src "ls180.v:1344.5-1344.34" + process $proc$ls180.v:1344$3649 + assign { } { } + assign $1\main_sdphy_dataw_valid[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_valid $1\main_sdphy_dataw_valid[0:0] + end + attribute \src "ls180.v:1345.5-1345.34" + process $proc$ls180.v:1345$3650 + assign { } { } + assign $1\main_sdphy_dataw_error[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_error $1\main_sdphy_dataw_error[0:0] + end + attribute \src "ls180.v:1347.5-1347.47" + process $proc$ls180.v:1347$3651 + assign { } { } + assign $0\main_sdphy_dataw_crcr_pads_in_ready[0:0] 1'0 + sync always + update \main_sdphy_dataw_crcr_pads_in_ready $0\main_sdphy_dataw_crcr_pads_in_ready[0:0] + sync init + end + attribute \src "ls180.v:1358.5-1358.54" + process $proc$ls180.v:1358$3652 + assign { } { } + assign $1\main_sdphy_dataw_crcr_source_source_ready0[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_crcr_source_source_ready0 $1\main_sdphy_dataw_crcr_source_source_ready0[0:0] + end + attribute \src "ls180.v:1363.5-1363.37" + process $proc$ls180.v:1363$3653 + assign { } { } + assign $1\main_sdphy_dataw_crcr_run[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_crcr_run $1\main_sdphy_dataw_crcr_run[0:0] + end + attribute \src "ls180.v:1366.5-1366.54" + process $proc$ls180.v:1366$3654 + assign { } { } + assign $0\main_sdphy_dataw_crcr_converter_sink_first[0:0] 1'0 + sync always + update \main_sdphy_dataw_crcr_converter_sink_first $0\main_sdphy_dataw_crcr_converter_sink_first[0:0] + sync init + end + attribute \src "ls180.v:1367.5-1367.53" + process $proc$ls180.v:1367$3655 + assign { } { } + assign $0\main_sdphy_dataw_crcr_converter_sink_last[0:0] 1'0 + sync always + update \main_sdphy_dataw_crcr_converter_sink_last $0\main_sdphy_dataw_crcr_converter_sink_last[0:0] + sync init + end + attribute \src "ls180.v:1371.5-1371.56" + process $proc$ls180.v:1371$3656 + assign { } { } + assign $1\main_sdphy_dataw_crcr_converter_source_first[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_crcr_converter_source_first $1\main_sdphy_dataw_crcr_converter_source_first[0:0] + end + attribute \src "ls180.v:1372.5-1372.55" + process $proc$ls180.v:1372$3657 + assign { } { } + assign $1\main_sdphy_dataw_crcr_converter_source_last[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_crcr_converter_source_last $1\main_sdphy_dataw_crcr_converter_source_last[0:0] + end + attribute \src "ls180.v:1373.11-1373.69" + process $proc$ls180.v:1373$3658 + assign { } { } + assign $1\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_dataw_crcr_converter_source_payload_data $1\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] + end + attribute \src "ls180.v:1374.11-1374.82" + process $proc$ls180.v:1374$3659 + assign { } { } + assign $1\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] 4'0000 + sync always + sync init + update \main_sdphy_dataw_crcr_converter_source_payload_valid_token_count $1\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] + end + attribute \src "ls180.v:1375.11-1375.55" + process $proc$ls180.v:1375$3660 + assign { } { } + assign $1\main_sdphy_dataw_crcr_converter_demux[2:0] 3'000 + sync always + sync init + update \main_sdphy_dataw_crcr_converter_demux $1\main_sdphy_dataw_crcr_converter_demux[2:0] + end + attribute \src "ls180.v:1377.5-1377.54" + process $proc$ls180.v:1377$3661 + assign { } { } + assign $1\main_sdphy_dataw_crcr_converter_strobe_all[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_crcr_converter_strobe_all $1\main_sdphy_dataw_crcr_converter_strobe_all[0:0] + end + attribute \src "ls180.v:1388.5-1388.50" + process $proc$ls180.v:1388$3662 + assign { } { } + assign $1\main_sdphy_dataw_crcr_buf_source_valid[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_crcr_buf_source_valid $1\main_sdphy_dataw_crcr_buf_source_valid[0:0] + end + attribute \src "ls180.v:1390.5-1390.50" + process $proc$ls180.v:1390$3663 + assign { } { } + assign $1\main_sdphy_dataw_crcr_buf_source_first[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_crcr_buf_source_first $1\main_sdphy_dataw_crcr_buf_source_first[0:0] + end + attribute \src "ls180.v:1391.5-1391.49" + process $proc$ls180.v:1391$3664 + assign { } { } + assign $1\main_sdphy_dataw_crcr_buf_source_last[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_crcr_buf_source_last $1\main_sdphy_dataw_crcr_buf_source_last[0:0] + end + attribute \src "ls180.v:1392.11-1392.63" + process $proc$ls180.v:1392$3665 + assign { } { } + assign $1\main_sdphy_dataw_crcr_buf_source_payload_data[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_dataw_crcr_buf_source_payload_data $1\main_sdphy_dataw_crcr_buf_source_payload_data[7:0] + end + attribute \src "ls180.v:1393.5-1393.39" + process $proc$ls180.v:1393$3666 + assign { } { } + assign $1\main_sdphy_dataw_crcr_reset[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_crcr_reset $1\main_sdphy_dataw_crcr_reset[0:0] + end + attribute \src "ls180.v:1396.5-1396.50" + process $proc$ls180.v:1396$3667 + assign { } { } + assign $0\main_sdphy_datar_pads_in_pads_in_first[0:0] 1'0 + sync always + update \main_sdphy_datar_pads_in_pads_in_first $0\main_sdphy_datar_pads_in_pads_in_first[0:0] + sync init + end + attribute \src "ls180.v:1397.5-1397.49" + process $proc$ls180.v:1397$3668 + assign { } { } + assign $0\main_sdphy_datar_pads_in_pads_in_last[0:0] 1'0 + sync always + update \main_sdphy_datar_pads_in_pads_in_last $0\main_sdphy_datar_pads_in_pads_in_last[0:0] + sync init + end + attribute \src "ls180.v:1398.5-1398.56" + process $proc$ls180.v:1398$3669 + assign { } { } + assign $0\main_sdphy_datar_pads_in_pads_in_payload_clk[0:0] 1'0 + sync always + update \main_sdphy_datar_pads_in_pads_in_payload_clk $0\main_sdphy_datar_pads_in_pads_in_payload_clk[0:0] + sync init + end + attribute \src "ls180.v:1400.5-1400.58" + process $proc$ls180.v:1400$3670 + assign { } { } + assign $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_o[0:0] 1'0 + sync always + update \main_sdphy_datar_pads_in_pads_in_payload_cmd_o $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_o[0:0] + sync init + end + attribute \src "ls180.v:1401.5-1401.59" + process $proc$ls180.v:1401$3671 + assign { } { } + assign $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_oe[0:0] 1'0 + sync always + update \main_sdphy_datar_pads_in_pads_in_payload_cmd_oe $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_oe[0:0] + sync init + end + attribute \src "ls180.v:1403.11-1403.65" + process $proc$ls180.v:1403$3672 + assign { } { } + assign $0\main_sdphy_datar_pads_in_pads_in_payload_data_o[3:0] 4'0000 + sync always + update \main_sdphy_datar_pads_in_pads_in_payload_data_o $0\main_sdphy_datar_pads_in_pads_in_payload_data_o[3:0] + sync init + end + attribute \src "ls180.v:1404.5-1404.60" + process $proc$ls180.v:1404$3673 + assign { } { } + assign $0\main_sdphy_datar_pads_in_pads_in_payload_data_oe[0:0] 1'0 + sync always + update \main_sdphy_datar_pads_in_pads_in_payload_data_oe $0\main_sdphy_datar_pads_in_pads_in_payload_data_oe[0:0] + sync init + end + attribute \src "ls180.v:1406.5-1406.49" + process $proc$ls180.v:1406$3674 + assign { } { } + assign $1\main_sdphy_datar_pads_out_payload_clk[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_pads_out_payload_clk $1\main_sdphy_datar_pads_out_payload_clk[0:0] + end + attribute \src "ls180.v:1407.5-1407.51" + process $proc$ls180.v:1407$3675 + assign { } { } + assign $0\main_sdphy_datar_pads_out_payload_cmd_o[0:0] 1'0 + sync always + update \main_sdphy_datar_pads_out_payload_cmd_o $0\main_sdphy_datar_pads_out_payload_cmd_o[0:0] + sync init + end + attribute \src "ls180.v:1408.5-1408.52" + process $proc$ls180.v:1408$3676 + assign { } { } + assign $0\main_sdphy_datar_pads_out_payload_cmd_oe[0:0] 1'0 + sync always + update \main_sdphy_datar_pads_out_payload_cmd_oe $0\main_sdphy_datar_pads_out_payload_cmd_oe[0:0] + sync init + end + attribute \src "ls180.v:1409.11-1409.58" + process $proc$ls180.v:1409$3677 + assign { } { } + assign $0\main_sdphy_datar_pads_out_payload_data_o[3:0] 4'0000 + sync always + update \main_sdphy_datar_pads_out_payload_data_o $0\main_sdphy_datar_pads_out_payload_data_o[3:0] + sync init + end + attribute \src "ls180.v:1410.5-1410.53" + process $proc$ls180.v:1410$3678 + assign { } { } + assign $0\main_sdphy_datar_pads_out_payload_data_oe[0:0] 1'0 + sync always + update \main_sdphy_datar_pads_out_payload_data_oe $0\main_sdphy_datar_pads_out_payload_data_oe[0:0] + sync init + end + attribute \src "ls180.v:1411.5-1411.39" + process $proc$ls180.v:1411$3679 + assign { } { } + assign $1\main_sdphy_datar_sink_valid[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_sink_valid $1\main_sdphy_datar_sink_valid[0:0] + end + attribute \src "ls180.v:1412.5-1412.39" + process $proc$ls180.v:1412$3680 + assign { } { } + assign $1\main_sdphy_datar_sink_ready[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_sink_ready $1\main_sdphy_datar_sink_ready[0:0] + end + attribute \src "ls180.v:1413.5-1413.38" + process $proc$ls180.v:1413$3681 + assign { } { } + assign $1\main_sdphy_datar_sink_last[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_sink_last $1\main_sdphy_datar_sink_last[0:0] + end + attribute \src "ls180.v:1414.11-1414.61" + process $proc$ls180.v:1414$3682 + assign { } { } + assign $1\main_sdphy_datar_sink_payload_block_length[9:0] 10'0000000000 + sync always + sync init + update \main_sdphy_datar_sink_payload_block_length $1\main_sdphy_datar_sink_payload_block_length[9:0] + end + attribute \src "ls180.v:1415.5-1415.41" + process $proc$ls180.v:1415$3683 + assign { } { } + assign $1\main_sdphy_datar_source_valid[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_source_valid $1\main_sdphy_datar_source_valid[0:0] + end + attribute \src "ls180.v:1416.5-1416.41" + process $proc$ls180.v:1416$3684 + assign { } { } + assign $1\main_sdphy_datar_source_ready[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_source_ready $1\main_sdphy_datar_source_ready[0:0] + end + attribute \src "ls180.v:1417.5-1417.41" + process $proc$ls180.v:1417$3685 + assign { } { } + assign $0\main_sdphy_datar_source_first[0:0] 1'0 + sync always + update \main_sdphy_datar_source_first $0\main_sdphy_datar_source_first[0:0] + sync init + end + attribute \src "ls180.v:1418.5-1418.40" + process $proc$ls180.v:1418$3686 + assign { } { } + assign $1\main_sdphy_datar_source_last[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_source_last $1\main_sdphy_datar_source_last[0:0] + end + attribute \src "ls180.v:1419.11-1419.54" + process $proc$ls180.v:1419$3687 + assign { } { } + assign $1\main_sdphy_datar_source_payload_data[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_datar_source_payload_data $1\main_sdphy_datar_source_payload_data[7:0] + end + attribute \src "ls180.v:1420.11-1420.56" + process $proc$ls180.v:1420$3688 + assign { } { } + assign $1\main_sdphy_datar_source_payload_status[2:0] 3'000 + sync always + sync init + update \main_sdphy_datar_source_payload_status $1\main_sdphy_datar_source_payload_status[2:0] + end + attribute \src "ls180.v:1421.5-1421.33" + process $proc$ls180.v:1421$3689 + assign { } { } + assign $1\main_sdphy_datar_stop[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_stop $1\main_sdphy_datar_stop[0:0] + end + attribute \src "ls180.v:1422.12-1422.49" + process $proc$ls180.v:1422$3690 + assign { } { } + assign $1\main_sdphy_datar_timeout[31:0] 500000 + sync always + sync init + update \main_sdphy_datar_timeout $1\main_sdphy_datar_timeout[31:0] + end + attribute \src "ls180.v:1423.11-1423.41" + process $proc$ls180.v:1423$3691 + assign { } { } + assign $1\main_sdphy_datar_count[9:0] 10'0000000000 + sync always + sync init + update \main_sdphy_datar_count $1\main_sdphy_datar_count[9:0] + end + attribute \src "ls180.v:1425.5-1425.48" + process $proc$ls180.v:1425$3692 + assign { } { } + assign $0\main_sdphy_datar_datar_pads_in_ready[0:0] 1'0 + sync always + update \main_sdphy_datar_datar_pads_in_ready $0\main_sdphy_datar_datar_pads_in_ready[0:0] + sync init + end + attribute \src "ls180.v:1436.5-1436.55" + process $proc$ls180.v:1436$3693 + assign { } { } + assign $1\main_sdphy_datar_datar_source_source_ready0[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_datar_source_source_ready0 $1\main_sdphy_datar_datar_source_source_ready0[0:0] + end + attribute \src "ls180.v:1441.5-1441.38" + process $proc$ls180.v:1441$3694 + assign { } { } + assign $1\main_sdphy_datar_datar_run[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_datar_run $1\main_sdphy_datar_datar_run[0:0] + end + attribute \src "ls180.v:1444.5-1444.55" + process $proc$ls180.v:1444$3695 + assign { } { } + assign $0\main_sdphy_datar_datar_converter_sink_first[0:0] 1'0 + sync always + update \main_sdphy_datar_datar_converter_sink_first $0\main_sdphy_datar_datar_converter_sink_first[0:0] + sync init + end + attribute \src "ls180.v:1445.5-1445.54" + process $proc$ls180.v:1445$3696 + assign { } { } + assign $0\main_sdphy_datar_datar_converter_sink_last[0:0] 1'0 + sync always + update \main_sdphy_datar_datar_converter_sink_last $0\main_sdphy_datar_datar_converter_sink_last[0:0] + sync init + end + attribute \src "ls180.v:1449.5-1449.57" + process $proc$ls180.v:1449$3697 + assign { } { } + assign $1\main_sdphy_datar_datar_converter_source_first[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_datar_converter_source_first $1\main_sdphy_datar_datar_converter_source_first[0:0] + end + attribute \src "ls180.v:1450.5-1450.56" + process $proc$ls180.v:1450$3698 + assign { } { } + assign $1\main_sdphy_datar_datar_converter_source_last[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_datar_converter_source_last $1\main_sdphy_datar_datar_converter_source_last[0:0] + end + attribute \src "ls180.v:1451.11-1451.70" + process $proc$ls180.v:1451$3699 + assign { } { } + assign $1\main_sdphy_datar_datar_converter_source_payload_data[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_datar_datar_converter_source_payload_data $1\main_sdphy_datar_datar_converter_source_payload_data[7:0] + end + attribute \src "ls180.v:1452.11-1452.83" + process $proc$ls180.v:1452$3700 + assign { } { } + assign $1\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] 2'00 + sync always + sync init + update \main_sdphy_datar_datar_converter_source_payload_valid_token_count $1\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] + end + attribute \src "ls180.v:1453.5-1453.50" + process $proc$ls180.v:1453$3701 + assign { } { } + assign $1\main_sdphy_datar_datar_converter_demux[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_datar_converter_demux $1\main_sdphy_datar_datar_converter_demux[0:0] + end + attribute \src "ls180.v:1455.5-1455.55" + process $proc$ls180.v:1455$3702 + assign { } { } + assign $1\main_sdphy_datar_datar_converter_strobe_all[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_datar_converter_strobe_all $1\main_sdphy_datar_datar_converter_strobe_all[0:0] + end + attribute \src "ls180.v:1466.5-1466.51" + process $proc$ls180.v:1466$3703 + assign { } { } + assign $1\main_sdphy_datar_datar_buf_source_valid[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_datar_buf_source_valid $1\main_sdphy_datar_datar_buf_source_valid[0:0] + end + attribute \src "ls180.v:1468.5-1468.51" + process $proc$ls180.v:1468$3704 + assign { } { } + assign $1\main_sdphy_datar_datar_buf_source_first[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_datar_buf_source_first $1\main_sdphy_datar_datar_buf_source_first[0:0] + end + attribute \src "ls180.v:1469.5-1469.50" + process $proc$ls180.v:1469$3705 + assign { } { } + assign $1\main_sdphy_datar_datar_buf_source_last[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_datar_buf_source_last $1\main_sdphy_datar_datar_buf_source_last[0:0] + end + attribute \src "ls180.v:1470.11-1470.64" + process $proc$ls180.v:1470$3706 + assign { } { } + assign $1\main_sdphy_datar_datar_buf_source_payload_data[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_datar_datar_buf_source_payload_data $1\main_sdphy_datar_datar_buf_source_payload_data[7:0] + end + attribute \src "ls180.v:1471.5-1471.40" + process $proc$ls180.v:1471$3707 + assign { } { } + assign $1\main_sdphy_datar_datar_reset[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_datar_reset $1\main_sdphy_datar_datar_reset[0:0] + end + attribute \src "ls180.v:1473.5-1473.35" + process $proc$ls180.v:1473$3708 + assign { } { } + assign $1\main_sdphy_sdpads_cmd_i[0:0] 1'0 + sync always + sync init + update \main_sdphy_sdpads_cmd_i $1\main_sdphy_sdpads_cmd_i[0:0] + end + attribute \src "ls180.v:1476.11-1476.42" + process $proc$ls180.v:1476$3709 + assign { } { } + assign $1\main_sdphy_sdpads_data_i[3:0] 4'0000 + sync always + sync init + update \main_sdphy_sdpads_data_i $1\main_sdphy_sdpads_data_i[3:0] + end + attribute \src "ls180.v:1489.12-1489.52" + process $proc$ls180.v:1489$3710 + assign { } { } + assign $1\main_sdcore_cmd_argument_storage[31:0] 0 + sync always + sync init + update \main_sdcore_cmd_argument_storage $1\main_sdcore_cmd_argument_storage[31:0] + end + attribute \src "ls180.v:1490.5-1490.39" + process $proc$ls180.v:1490$3711 + assign { } { } + assign $1\main_sdcore_cmd_argument_re[0:0] 1'0 + sync always + sync init + update \main_sdcore_cmd_argument_re $1\main_sdcore_cmd_argument_re[0:0] + end + attribute \src "ls180.v:1491.12-1491.51" + process $proc$ls180.v:1491$3712 + assign { } { } + assign $1\main_sdcore_cmd_command_storage[31:0] 0 + sync always + sync init + update \main_sdcore_cmd_command_storage $1\main_sdcore_cmd_command_storage[31:0] + end + attribute \src "ls180.v:1492.5-1492.38" + process $proc$ls180.v:1492$3713 + assign { } { } + assign $1\main_sdcore_cmd_command_re[0:0] 1'0 + sync always + sync init + update \main_sdcore_cmd_command_re $1\main_sdcore_cmd_command_re[0:0] + end + attribute \src "ls180.v:1496.5-1496.34" + process $proc$ls180.v:1496$3714 + assign { } { } + assign $0\main_sdcore_cmd_send_w[0:0] 1'0 + sync always + update \main_sdcore_cmd_send_w $0\main_sdcore_cmd_send_w[0:0] + sync init + end + attribute \src "ls180.v:1497.13-1497.53" + process $proc$ls180.v:1497$3715 + assign { } { } + assign $1\main_sdcore_cmd_response_status[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \main_sdcore_cmd_response_status $1\main_sdcore_cmd_response_status[127:0] + end + attribute \src "ls180.v:1503.11-1503.51" + process $proc$ls180.v:1503$3716 + assign { } { } + assign $1\main_sdcore_block_length_storage[9:0] 10'0000000000 + sync always + sync init + update \main_sdcore_block_length_storage $1\main_sdcore_block_length_storage[9:0] + end + attribute \src "ls180.v:1504.5-1504.39" + process $proc$ls180.v:1504$3717 + assign { } { } + assign $1\main_sdcore_block_length_re[0:0] 1'0 + sync always + sync init + update \main_sdcore_block_length_re $1\main_sdcore_block_length_re[0:0] + end + attribute \src "ls180.v:1505.12-1505.51" + process $proc$ls180.v:1505$3718 + assign { } { } + assign $1\main_sdcore_block_count_storage[31:0] 0 + sync always + sync init + update \main_sdcore_block_count_storage $1\main_sdcore_block_count_storage[31:0] + end + attribute \src "ls180.v:1506.5-1506.38" + process $proc$ls180.v:1506$3719 + assign { } { } + assign $1\main_sdcore_block_count_re[0:0] 1'0 + sync always + sync init + update \main_sdcore_block_count_re $1\main_sdcore_block_count_re[0:0] + end + attribute \src "ls180.v:1507.11-1507.51" + process $proc$ls180.v:1507$3720 + assign { } { } + assign $1\main_sdcore_crc7_inserter_crcreg0[6:0] 7'0000000 + sync always + sync init + update \main_sdcore_crc7_inserter_crcreg0 $1\main_sdcore_crc7_inserter_crcreg0[6:0] + end + attribute \src "ls180.v:1549.11-1549.47" + process $proc$ls180.v:1549$3721 + assign { } { } + assign $1\main_sdcore_crc7_inserter_crc[6:0] 7'0000000 + sync always + sync init + update \main_sdcore_crc7_inserter_crc $1\main_sdcore_crc7_inserter_crc[6:0] + end + attribute \src "ls180.v:1553.5-1553.49" + process $proc$ls180.v:1553$3722 + assign { } { } + assign $1\main_sdcore_crc16_inserter_sink_ready[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_inserter_sink_ready $1\main_sdcore_crc16_inserter_sink_ready[0:0] + end + attribute \src "ls180.v:1557.5-1557.51" + process $proc$ls180.v:1557$3723 + assign { } { } + assign $1\main_sdcore_crc16_inserter_source_valid[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_inserter_source_valid $1\main_sdcore_crc16_inserter_source_valid[0:0] + end + attribute \src "ls180.v:1558.5-1558.51" + process $proc$ls180.v:1558$3724 + assign { } { } + assign $1\main_sdcore_crc16_inserter_source_ready[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_inserter_source_ready $1\main_sdcore_crc16_inserter_source_ready[0:0] + end + attribute \src "ls180.v:1559.5-1559.51" + process $proc$ls180.v:1559$3725 + assign { } { } + assign $0\main_sdcore_crc16_inserter_source_first[0:0] 1'0 + sync always + update \main_sdcore_crc16_inserter_source_first $0\main_sdcore_crc16_inserter_source_first[0:0] + sync init + end + attribute \src "ls180.v:1560.5-1560.50" + process $proc$ls180.v:1560$3726 + assign { } { } + assign $1\main_sdcore_crc16_inserter_source_last[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_inserter_source_last $1\main_sdcore_crc16_inserter_source_last[0:0] + end + attribute \src "ls180.v:1561.11-1561.64" + process $proc$ls180.v:1561$3727 + assign { } { } + assign $1\main_sdcore_crc16_inserter_source_payload_data[7:0] 8'00000000 + sync always + sync init + update \main_sdcore_crc16_inserter_source_payload_data $1\main_sdcore_crc16_inserter_source_payload_data[7:0] + end + attribute \src "ls180.v:1562.11-1562.48" + process $proc$ls180.v:1562$3728 + assign { } { } + assign $1\main_sdcore_crc16_inserter_cnt[2:0] 3'000 + sync always + sync init + update \main_sdcore_crc16_inserter_cnt $1\main_sdcore_crc16_inserter_cnt[2:0] + end + attribute \src "ls180.v:1563.12-1563.59" + process $proc$ls180.v:1563$3729 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_inserter_crc0_crcreg0 $1\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] + end + attribute \src "ls180.v:1567.12-1567.55" + process $proc$ls180.v:1567$3730 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crc0_crc[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_inserter_crc0_crc $1\main_sdcore_crc16_inserter_crc0_crc[15:0] + end + attribute \src "ls180.v:1570.12-1570.59" + process $proc$ls180.v:1570$3731 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_inserter_crc1_crcreg0 $1\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] + end + attribute \src "ls180.v:1574.12-1574.55" + process $proc$ls180.v:1574$3732 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crc1_crc[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_inserter_crc1_crc $1\main_sdcore_crc16_inserter_crc1_crc[15:0] + end + attribute \src "ls180.v:1577.12-1577.59" + process $proc$ls180.v:1577$3733 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_inserter_crc2_crcreg0 $1\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] + end + attribute \src "ls180.v:1581.12-1581.55" + process $proc$ls180.v:1581$3734 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crc2_crc[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_inserter_crc2_crc $1\main_sdcore_crc16_inserter_crc2_crc[15:0] + end + attribute \src "ls180.v:1584.12-1584.59" + process $proc$ls180.v:1584$3735 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_inserter_crc3_crcreg0 $1\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] + end + attribute \src "ls180.v:1588.12-1588.55" + process $proc$ls180.v:1588$3736 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crc3_crc[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_inserter_crc3_crc $1\main_sdcore_crc16_inserter_crc3_crc[15:0] + end + attribute \src "ls180.v:1591.12-1591.54" + process $proc$ls180.v:1591$3737 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crctmp0[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_inserter_crctmp0 $1\main_sdcore_crc16_inserter_crctmp0[15:0] + end + attribute \src "ls180.v:1592.12-1592.54" + process $proc$ls180.v:1592$3738 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crctmp1[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_inserter_crctmp1 $1\main_sdcore_crc16_inserter_crctmp1[15:0] + end + attribute \src "ls180.v:1593.12-1593.54" + process $proc$ls180.v:1593$3739 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crctmp2[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_inserter_crctmp2 $1\main_sdcore_crc16_inserter_crctmp2[15:0] + end + attribute \src "ls180.v:1594.12-1594.54" + process $proc$ls180.v:1594$3740 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crctmp3[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_inserter_crctmp3 $1\main_sdcore_crc16_inserter_crctmp3[15:0] + end + attribute \src "ls180.v:1595.5-1595.48" + process $proc$ls180.v:1595$3741 + assign { } { } + assign $1\main_sdcore_crc16_checker_sink_valid[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_checker_sink_valid $1\main_sdcore_crc16_checker_sink_valid[0:0] + end + attribute \src "ls180.v:1596.5-1596.48" + process $proc$ls180.v:1596$3742 + assign { } { } + assign $1\main_sdcore_crc16_checker_sink_ready[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_checker_sink_ready $1\main_sdcore_crc16_checker_sink_ready[0:0] + end + attribute \src "ls180.v:1597.5-1597.48" + process $proc$ls180.v:1597$3743 + assign { } { } + assign $1\main_sdcore_crc16_checker_sink_first[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_checker_sink_first $1\main_sdcore_crc16_checker_sink_first[0:0] + end + attribute \src "ls180.v:1598.5-1598.47" + process $proc$ls180.v:1598$3744 + assign { } { } + assign $1\main_sdcore_crc16_checker_sink_last[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_checker_sink_last $1\main_sdcore_crc16_checker_sink_last[0:0] + end + attribute \src "ls180.v:1599.11-1599.61" + process $proc$ls180.v:1599$3745 + assign { } { } + assign $1\main_sdcore_crc16_checker_sink_payload_data[7:0] 8'00000000 + sync always + sync init + update \main_sdcore_crc16_checker_sink_payload_data $1\main_sdcore_crc16_checker_sink_payload_data[7:0] + end + attribute \src "ls180.v:1600.5-1600.50" + process $proc$ls180.v:1600$3746 + assign { } { } + assign $1\main_sdcore_crc16_checker_source_valid[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_checker_source_valid $1\main_sdcore_crc16_checker_source_valid[0:0] + end + attribute \src "ls180.v:1602.5-1602.50" + process $proc$ls180.v:1602$3747 + assign { } { } + assign $0\main_sdcore_crc16_checker_source_first[0:0] 1'0 + sync always + update \main_sdcore_crc16_checker_source_first $0\main_sdcore_crc16_checker_source_first[0:0] + sync init + end + attribute \src "ls180.v:1605.11-1605.47" + process $proc$ls180.v:1605$3748 + assign { } { } + assign $1\main_sdcore_crc16_checker_val[7:0] 8'00000000 + sync always + sync init + update \main_sdcore_crc16_checker_val $1\main_sdcore_crc16_checker_val[7:0] + end + attribute \src "ls180.v:1606.11-1606.47" + process $proc$ls180.v:1606$3749 + assign { } { } + assign $1\main_sdcore_crc16_checker_cnt[3:0] 4'0000 + sync always + sync init + update \main_sdcore_crc16_checker_cnt $1\main_sdcore_crc16_checker_cnt[3:0] + end + attribute \src "ls180.v:1607.12-1607.58" + process $proc$ls180.v:1607$3750 + assign { } { } + assign $1\main_sdcore_crc16_checker_crc0_crcreg0[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_checker_crc0_crcreg0 $1\main_sdcore_crc16_checker_crc0_crcreg0[15:0] + end + attribute \src "ls180.v:1611.12-1611.54" + process $proc$ls180.v:1611$3751 + assign { } { } + assign $1\main_sdcore_crc16_checker_crc0_crc[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_checker_crc0_crc $1\main_sdcore_crc16_checker_crc0_crc[15:0] + end + attribute \src "ls180.v:1612.5-1612.46" + process $proc$ls180.v:1612$3752 + assign { } { } + assign $1\main_sdcore_crc16_checker_crc0_clr[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_checker_crc0_clr $1\main_sdcore_crc16_checker_crc0_clr[0:0] + end + attribute \src "ls180.v:1614.12-1614.58" + process $proc$ls180.v:1614$3753 + assign { } { } + assign $1\main_sdcore_crc16_checker_crc1_crcreg0[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_checker_crc1_crcreg0 $1\main_sdcore_crc16_checker_crc1_crcreg0[15:0] + end + attribute \src "ls180.v:1618.12-1618.54" + process $proc$ls180.v:1618$3754 + assign { } { } + assign $1\main_sdcore_crc16_checker_crc1_crc[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_checker_crc1_crc $1\main_sdcore_crc16_checker_crc1_crc[15:0] + end + attribute \src "ls180.v:1619.5-1619.46" + process $proc$ls180.v:1619$3755 + assign { } { } + assign $1\main_sdcore_crc16_checker_crc1_clr[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_checker_crc1_clr $1\main_sdcore_crc16_checker_crc1_clr[0:0] + end + attribute \src "ls180.v:1621.12-1621.58" + process $proc$ls180.v:1621$3756 + assign { } { } + assign $1\main_sdcore_crc16_checker_crc2_crcreg0[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_checker_crc2_crcreg0 $1\main_sdcore_crc16_checker_crc2_crcreg0[15:0] + end + attribute \src "ls180.v:1625.12-1625.54" + process $proc$ls180.v:1625$3757 + assign { } { } + assign $1\main_sdcore_crc16_checker_crc2_crc[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_checker_crc2_crc $1\main_sdcore_crc16_checker_crc2_crc[15:0] + end + attribute \src "ls180.v:1626.5-1626.46" + process $proc$ls180.v:1626$3758 + assign { } { } + assign $1\main_sdcore_crc16_checker_crc2_clr[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_checker_crc2_clr $1\main_sdcore_crc16_checker_crc2_clr[0:0] + end + attribute \src "ls180.v:1628.12-1628.58" + process $proc$ls180.v:1628$3759 + assign { } { } + assign $1\main_sdcore_crc16_checker_crc3_crcreg0[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_checker_crc3_crcreg0 $1\main_sdcore_crc16_checker_crc3_crcreg0[15:0] + end + attribute \src "ls180.v:1632.12-1632.54" + process $proc$ls180.v:1632$3760 + assign { } { } + assign $1\main_sdcore_crc16_checker_crc3_crc[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_checker_crc3_crc $1\main_sdcore_crc16_checker_crc3_crc[15:0] + end + attribute \src "ls180.v:1633.5-1633.46" + process $proc$ls180.v:1633$3761 + assign { } { } + assign $1\main_sdcore_crc16_checker_crc3_clr[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_checker_crc3_clr $1\main_sdcore_crc16_checker_crc3_clr[0:0] + end + attribute \src "ls180.v:1635.12-1635.53" + process $proc$ls180.v:1635$3762 + assign { } { } + assign $1\main_sdcore_crc16_checker_crctmp0[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_checker_crctmp0 $1\main_sdcore_crc16_checker_crctmp0[15:0] + end + attribute \src "ls180.v:1636.12-1636.53" + process $proc$ls180.v:1636$3763 + assign { } { } + assign $1\main_sdcore_crc16_checker_crctmp1[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_checker_crctmp1 $1\main_sdcore_crc16_checker_crctmp1[15:0] + end + attribute \src "ls180.v:1637.12-1637.53" + process $proc$ls180.v:1637$3764 + assign { } { } + assign $1\main_sdcore_crc16_checker_crctmp2[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_checker_crctmp2 $1\main_sdcore_crc16_checker_crctmp2[15:0] + end + attribute \src "ls180.v:1638.12-1638.53" + process $proc$ls180.v:1638$3765 + assign { } { } + assign $1\main_sdcore_crc16_checker_crctmp3[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_checker_crctmp3 $1\main_sdcore_crc16_checker_crctmp3[15:0] + end + attribute \src "ls180.v:1639.5-1639.43" + process $proc$ls180.v:1639$3766 + assign { } { } + assign $1\main_sdcore_crc16_checker_valid[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_checker_valid $1\main_sdcore_crc16_checker_valid[0:0] + end + attribute \src "ls180.v:1640.12-1640.51" + process $proc$ls180.v:1640$3767 + assign { } { } + assign $1\main_sdcore_crc16_checker_fifo0[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_checker_fifo0 $1\main_sdcore_crc16_checker_fifo0[15:0] + end + attribute \src "ls180.v:1641.12-1641.51" + process $proc$ls180.v:1641$3768 + assign { } { } + assign $1\main_sdcore_crc16_checker_fifo1[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_checker_fifo1 $1\main_sdcore_crc16_checker_fifo1[15:0] + end + attribute \src "ls180.v:1642.12-1642.51" + process $proc$ls180.v:1642$3769 + assign { } { } + assign $1\main_sdcore_crc16_checker_fifo2[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_checker_fifo2 $1\main_sdcore_crc16_checker_fifo2[15:0] + end + attribute \src "ls180.v:1643.12-1643.51" + process $proc$ls180.v:1643$3770 + assign { } { } + assign $1\main_sdcore_crc16_checker_fifo3[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_checker_fifo3 $1\main_sdcore_crc16_checker_fifo3[15:0] + end + attribute \src "ls180.v:1645.11-1645.39" + process $proc$ls180.v:1645$3771 + assign { } { } + assign $1\main_sdcore_cmd_count[2:0] 3'000 + sync always + sync init + update \main_sdcore_cmd_count $1\main_sdcore_cmd_count[2:0] + end + attribute \src "ls180.v:1646.5-1646.32" + process $proc$ls180.v:1646$3772 + assign { } { } + assign $1\main_sdcore_cmd_done[0:0] 1'0 + sync always + sync init + update \main_sdcore_cmd_done $1\main_sdcore_cmd_done[0:0] + end + attribute \src "ls180.v:1647.5-1647.33" + process $proc$ls180.v:1647$3773 + assign { } { } + assign $1\main_sdcore_cmd_error[0:0] 1'0 + sync always + sync init + update \main_sdcore_cmd_error $1\main_sdcore_cmd_error[0:0] + end + attribute \src "ls180.v:1648.5-1648.35" + process $proc$ls180.v:1648$3774 + assign { } { } + assign $1\main_sdcore_cmd_timeout[0:0] 1'0 + sync always + sync init + update \main_sdcore_cmd_timeout $1\main_sdcore_cmd_timeout[0:0] + end + attribute \src "ls180.v:1650.12-1650.42" + process $proc$ls180.v:1650$3775 + assign { } { } + assign $1\main_sdcore_data_count[31:0] 0 + sync always + sync init + update \main_sdcore_data_count $1\main_sdcore_data_count[31:0] + end + attribute \src "ls180.v:1651.5-1651.33" + process $proc$ls180.v:1651$3776 + assign { } { } + assign $1\main_sdcore_data_done[0:0] 1'0 + sync always + sync init + update \main_sdcore_data_done $1\main_sdcore_data_done[0:0] + end + attribute \src "ls180.v:1652.5-1652.34" + process $proc$ls180.v:1652$3777 + assign { } { } + assign $1\main_sdcore_data_error[0:0] 1'0 + sync always + sync init + update \main_sdcore_data_error $1\main_sdcore_data_error[0:0] + end + attribute \src "ls180.v:1653.5-1653.36" + process $proc$ls180.v:1653$3778 + assign { } { } + assign $1\main_sdcore_data_timeout[0:0] 1'0 + sync always + sync init + update \main_sdcore_data_timeout $1\main_sdcore_data_timeout[0:0] + end + attribute \src "ls180.v:1662.11-1662.41" + process $proc$ls180.v:1662$3779 + assign { } { } + assign $0\main_interface0_bus_cti[2:0] 3'000 + sync always + update \main_interface0_bus_cti $0\main_interface0_bus_cti[2:0] + sync init + end + attribute \src "ls180.v:1663.11-1663.41" + process $proc$ls180.v:1663$3780 + assign { } { } + assign $0\main_interface0_bus_bte[1:0] 2'00 + sync always + update \main_interface0_bus_bte $0\main_interface0_bus_bte[1:0] + sync init + end + attribute \src "ls180.v:1686.11-1686.45" + process $proc$ls180.v:1686$3781 + assign { } { } + assign $1\main_sdblock2mem_fifo_level[5:0] 6'000000 + sync always + sync init + update \main_sdblock2mem_fifo_level $1\main_sdblock2mem_fifo_level[5:0] + end + attribute \src "ls180.v:1687.5-1687.41" + process $proc$ls180.v:1687$3782 + assign { } { } + assign $0\main_sdblock2mem_fifo_replace[0:0] 1'0 + sync always + update \main_sdblock2mem_fifo_replace $0\main_sdblock2mem_fifo_replace[0:0] + sync init + end + attribute \src "ls180.v:1688.11-1688.47" + process $proc$ls180.v:1688$3783 + assign { } { } + assign $1\main_sdblock2mem_fifo_produce[4:0] 5'00000 + sync always + sync init + update \main_sdblock2mem_fifo_produce $1\main_sdblock2mem_fifo_produce[4:0] + end + attribute \src "ls180.v:1689.11-1689.47" + process $proc$ls180.v:1689$3784 + assign { } { } + assign $1\main_sdblock2mem_fifo_consume[4:0] 5'00000 + sync always + sync init + update \main_sdblock2mem_fifo_consume $1\main_sdblock2mem_fifo_consume[4:0] + end + attribute \src "ls180.v:1690.11-1690.50" + process $proc$ls180.v:1690$3785 + assign { } { } + assign $1\main_sdblock2mem_fifo_wrport_adr[4:0] 5'00000 + sync always + sync init + update \main_sdblock2mem_fifo_wrport_adr $1\main_sdblock2mem_fifo_wrport_adr[4:0] + end + attribute \src "ls180.v:1710.5-1710.51" + process $proc$ls180.v:1710$3786 + assign { } { } + assign $1\main_sdblock2mem_converter_source_first[0:0] 1'0 + sync always + sync init + update \main_sdblock2mem_converter_source_first $1\main_sdblock2mem_converter_source_first[0:0] + end + attribute \src "ls180.v:1711.5-1711.50" + process $proc$ls180.v:1711$3787 + assign { } { } + assign $1\main_sdblock2mem_converter_source_last[0:0] 1'0 + sync always + sync init + update \main_sdblock2mem_converter_source_last $1\main_sdblock2mem_converter_source_last[0:0] + end + attribute \src "ls180.v:1712.12-1712.66" + process $proc$ls180.v:1712$3788 + assign { } { } + assign $1\main_sdblock2mem_converter_source_payload_data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \main_sdblock2mem_converter_source_payload_data $1\main_sdblock2mem_converter_source_payload_data[63:0] + end + attribute \src "ls180.v:1713.11-1713.77" + process $proc$ls180.v:1713$3789 + assign { } { } + assign $1\main_sdblock2mem_converter_source_payload_valid_token_count[3:0] 4'0000 + sync always + sync init + update \main_sdblock2mem_converter_source_payload_valid_token_count $1\main_sdblock2mem_converter_source_payload_valid_token_count[3:0] + end + attribute \src "ls180.v:1714.11-1714.50" + process $proc$ls180.v:1714$3790 + assign { } { } + assign $1\main_sdblock2mem_converter_demux[2:0] 3'000 + sync always + sync init + update \main_sdblock2mem_converter_demux $1\main_sdblock2mem_converter_demux[2:0] + end + attribute \src "ls180.v:1716.5-1716.49" + process $proc$ls180.v:1716$3791 + assign { } { } + assign $1\main_sdblock2mem_converter_strobe_all[0:0] 1'0 + sync always + sync init + update \main_sdblock2mem_converter_strobe_all $1\main_sdblock2mem_converter_strobe_all[0:0] + end + attribute \src "ls180.v:1722.5-1722.45" + process $proc$ls180.v:1722$3792 + assign { } { } + assign $1\main_sdblock2mem_sink_sink_valid1[0:0] 1'0 + sync always + sync init + update \main_sdblock2mem_sink_sink_valid1 $1\main_sdblock2mem_sink_sink_valid1[0:0] + end + attribute \src "ls180.v:1724.12-1724.62" + process $proc$ls180.v:1724$3793 + assign { } { } + assign $1\main_sdblock2mem_sink_sink_payload_address[31:0] 0 + sync always + sync init + update \main_sdblock2mem_sink_sink_payload_address $1\main_sdblock2mem_sink_sink_payload_address[31:0] + end + attribute \src "ls180.v:1725.12-1725.60" + process $proc$ls180.v:1725$3794 + assign { } { } + assign $1\main_sdblock2mem_sink_sink_payload_data1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \main_sdblock2mem_sink_sink_payload_data1 $1\main_sdblock2mem_sink_sink_payload_data1[63:0] + end + attribute \src "ls180.v:1727.5-1727.57" + process $proc$ls180.v:1727$3795 + assign { } { } + assign $1\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] 1'0 + sync always + sync init + update \main_sdblock2mem_wishbonedmawriter_sink_ready $1\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] + end + attribute \src "ls180.v:1731.12-1731.67" + process $proc$ls180.v:1731$3796 + assign { } { } + assign $1\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \main_sdblock2mem_wishbonedmawriter_base_storage $1\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] + end + attribute \src "ls180.v:1732.5-1732.54" + process $proc$ls180.v:1732$3797 + assign { } { } + assign $1\main_sdblock2mem_wishbonedmawriter_base_re[0:0] 1'0 + sync always + sync init + update \main_sdblock2mem_wishbonedmawriter_base_re $1\main_sdblock2mem_wishbonedmawriter_base_re[0:0] + end + attribute \src "ls180.v:1733.12-1733.69" + process $proc$ls180.v:1733$3798 + assign { } { } + assign $1\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] 0 + sync always + sync init + update \main_sdblock2mem_wishbonedmawriter_length_storage $1\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] + end + attribute \src "ls180.v:1734.5-1734.56" + process $proc$ls180.v:1734$3799 + assign { } { } + assign $1\main_sdblock2mem_wishbonedmawriter_length_re[0:0] 1'0 + sync always + sync init + update \main_sdblock2mem_wishbonedmawriter_length_re $1\main_sdblock2mem_wishbonedmawriter_length_re[0:0] + end + attribute \src "ls180.v:1735.5-1735.61" + process $proc$ls180.v:1735$3800 + assign { } { } + assign $1\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] 1'0 + sync always + sync init + update \main_sdblock2mem_wishbonedmawriter_enable_storage $1\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] + end + attribute \src "ls180.v:1736.5-1736.56" + process $proc$ls180.v:1736$3801 + assign { } { } + assign $1\main_sdblock2mem_wishbonedmawriter_enable_re[0:0] 1'0 + sync always + sync init + update \main_sdblock2mem_wishbonedmawriter_enable_re $1\main_sdblock2mem_wishbonedmawriter_enable_re[0:0] + end + attribute \src "ls180.v:1737.5-1737.53" + process $proc$ls180.v:1737$3802 + assign { } { } + assign $1\main_sdblock2mem_wishbonedmawriter_status[0:0] 1'0 + sync always + sync init + update \main_sdblock2mem_wishbonedmawriter_status $1\main_sdblock2mem_wishbonedmawriter_status[0:0] + end + attribute \src "ls180.v:1739.5-1739.59" + process $proc$ls180.v:1739$3803 + assign { } { } + assign $1\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] 1'0 + sync always + sync init + update \main_sdblock2mem_wishbonedmawriter_loop_storage $1\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] + end + attribute \src "ls180.v:1740.5-1740.54" + process $proc$ls180.v:1740$3804 + assign { } { } + assign $1\main_sdblock2mem_wishbonedmawriter_loop_re[0:0] 1'0 + sync always + sync init + update \main_sdblock2mem_wishbonedmawriter_loop_re $1\main_sdblock2mem_wishbonedmawriter_loop_re[0:0] + end + attribute \src "ls180.v:1742.12-1742.61" + process $proc$ls180.v:1742$3805 + assign { } { } + assign $1\main_sdblock2mem_wishbonedmawriter_offset[31:0] 0 + sync always + sync init + update \main_sdblock2mem_wishbonedmawriter_offset $1\main_sdblock2mem_wishbonedmawriter_offset[31:0] + end + attribute \src "ls180.v:1745.12-1745.43" + process $proc$ls180.v:1745$3806 + assign { } { } + assign $1\main_interface1_bus_adr[31:0] 0 + sync always + sync init + update \main_interface1_bus_adr $1\main_interface1_bus_adr[31:0] + end + attribute \src "ls180.v:1746.12-1746.45" + process $proc$ls180.v:1746$3807 + assign { } { } + assign $0\main_interface1_bus_dat_w[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + update \main_interface1_bus_dat_w $0\main_interface1_bus_dat_w[63:0] + sync init + end + attribute \src "ls180.v:1748.11-1748.41" + process $proc$ls180.v:1748$3808 + assign { } { } + assign $1\main_interface1_bus_sel[7:0] 8'00000000 + sync always + sync init + update \main_interface1_bus_sel $1\main_interface1_bus_sel[7:0] + end + attribute \src "ls180.v:1749.5-1749.35" + process $proc$ls180.v:1749$3809 + assign { } { } + assign $1\main_interface1_bus_cyc[0:0] 1'0 + sync always + sync init + update \main_interface1_bus_cyc $1\main_interface1_bus_cyc[0:0] + end + attribute \src "ls180.v:1750.5-1750.35" + process $proc$ls180.v:1750$3810 + assign { } { } + assign $1\main_interface1_bus_stb[0:0] 1'0 + sync always + sync init + update \main_interface1_bus_stb $1\main_interface1_bus_stb[0:0] + end + attribute \src "ls180.v:1752.5-1752.34" + process $proc$ls180.v:1752$3811 + assign { } { } + assign $1\main_interface1_bus_we[0:0] 1'0 + sync always + sync init + update \main_interface1_bus_we $1\main_interface1_bus_we[0:0] + end + attribute \src "ls180.v:1753.11-1753.41" + process $proc$ls180.v:1753$3812 + assign { } { } + assign $0\main_interface1_bus_cti[2:0] 3'000 + sync always + update \main_interface1_bus_cti $0\main_interface1_bus_cti[2:0] + sync init + end + attribute \src "ls180.v:1754.11-1754.41" + process $proc$ls180.v:1754$3813 + assign { } { } + assign $0\main_interface1_bus_bte[1:0] 2'00 + sync always + update \main_interface1_bus_bte $0\main_interface1_bus_bte[1:0] + sync init + end + attribute \src "ls180.v:1761.5-1761.43" + process $proc$ls180.v:1761$3814 + assign { } { } + assign $1\main_sdmem2block_dma_sink_valid[0:0] 1'0 + sync always + sync init + update \main_sdmem2block_dma_sink_valid $1\main_sdmem2block_dma_sink_valid[0:0] + end + attribute \src "ls180.v:1762.5-1762.43" + process $proc$ls180.v:1762$3815 + assign { } { } + assign $1\main_sdmem2block_dma_sink_ready[0:0] 1'0 + sync always + sync init + update \main_sdmem2block_dma_sink_ready $1\main_sdmem2block_dma_sink_ready[0:0] + end + attribute \src "ls180.v:1763.5-1763.42" + process $proc$ls180.v:1763$3816 + assign { } { } + assign $1\main_sdmem2block_dma_sink_last[0:0] 1'0 + sync always + sync init + update \main_sdmem2block_dma_sink_last $1\main_sdmem2block_dma_sink_last[0:0] + end + attribute \src "ls180.v:1764.12-1764.61" + process $proc$ls180.v:1764$3817 + assign { } { } + assign $1\main_sdmem2block_dma_sink_payload_address[31:0] 0 + sync always + sync init + update \main_sdmem2block_dma_sink_payload_address $1\main_sdmem2block_dma_sink_payload_address[31:0] + end + attribute \src "ls180.v:1765.5-1765.45" + process $proc$ls180.v:1765$3818 + assign { } { } + assign $1\main_sdmem2block_dma_source_valid[0:0] 1'0 + sync always + sync init + update \main_sdmem2block_dma_source_valid $1\main_sdmem2block_dma_source_valid[0:0] + end + attribute \src "ls180.v:1767.5-1767.45" + process $proc$ls180.v:1767$3819 + assign { } { } + assign $0\main_sdmem2block_dma_source_first[0:0] 1'0 + sync always + update \main_sdmem2block_dma_source_first $0\main_sdmem2block_dma_source_first[0:0] + sync init + end + attribute \src "ls180.v:1768.5-1768.44" + process $proc$ls180.v:1768$3820 + assign { } { } + assign $1\main_sdmem2block_dma_source_last[0:0] 1'0 + sync always + sync init + update \main_sdmem2block_dma_source_last $1\main_sdmem2block_dma_source_last[0:0] + end + attribute \src "ls180.v:1769.12-1769.60" + process $proc$ls180.v:1769$3821 + assign { } { } + assign $1\main_sdmem2block_dma_source_payload_data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \main_sdmem2block_dma_source_payload_data $1\main_sdmem2block_dma_source_payload_data[63:0] + end + attribute \src "ls180.v:1770.12-1770.45" + process $proc$ls180.v:1770$3822 + assign { } { } + assign $1\main_sdmem2block_dma_data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \main_sdmem2block_dma_data $1\main_sdmem2block_dma_data[63:0] + end + attribute \src "ls180.v:1771.12-1771.53" + process $proc$ls180.v:1771$3823 + assign { } { } + assign $1\main_sdmem2block_dma_base_storage[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \main_sdmem2block_dma_base_storage $1\main_sdmem2block_dma_base_storage[63:0] + end + attribute \src "ls180.v:1772.5-1772.40" + process $proc$ls180.v:1772$3824 + assign { } { } + assign $1\main_sdmem2block_dma_base_re[0:0] 1'0 + sync always + sync init + update \main_sdmem2block_dma_base_re $1\main_sdmem2block_dma_base_re[0:0] + end + attribute \src "ls180.v:1773.12-1773.55" + process $proc$ls180.v:1773$3825 + assign { } { } + assign $1\main_sdmem2block_dma_length_storage[31:0] 0 + sync always + sync init + update \main_sdmem2block_dma_length_storage $1\main_sdmem2block_dma_length_storage[31:0] + end + attribute \src "ls180.v:1774.5-1774.42" + process $proc$ls180.v:1774$3826 + assign { } { } + assign $1\main_sdmem2block_dma_length_re[0:0] 1'0 + sync always + sync init + update \main_sdmem2block_dma_length_re $1\main_sdmem2block_dma_length_re[0:0] + end + attribute \src "ls180.v:1775.5-1775.47" + process $proc$ls180.v:1775$3827 + assign { } { } + assign $1\main_sdmem2block_dma_enable_storage[0:0] 1'0 + sync always + sync init + update \main_sdmem2block_dma_enable_storage $1\main_sdmem2block_dma_enable_storage[0:0] + end + attribute \src "ls180.v:1776.5-1776.42" + process $proc$ls180.v:1776$3828 + assign { } { } + assign $1\main_sdmem2block_dma_enable_re[0:0] 1'0 + sync always + sync init + update \main_sdmem2block_dma_enable_re $1\main_sdmem2block_dma_enable_re[0:0] + end + attribute \src "ls180.v:1777.5-1777.44" + process $proc$ls180.v:1777$3829 + assign { } { } + assign $1\main_sdmem2block_dma_done_status[0:0] 1'0 + sync always + sync init + update \main_sdmem2block_dma_done_status $1\main_sdmem2block_dma_done_status[0:0] + end + attribute \src "ls180.v:1779.5-1779.45" + process $proc$ls180.v:1779$3830 + assign { } { } + assign $1\main_sdmem2block_dma_loop_storage[0:0] 1'0 + sync always + sync init + update \main_sdmem2block_dma_loop_storage $1\main_sdmem2block_dma_loop_storage[0:0] + end + attribute \src "ls180.v:1780.5-1780.40" + process $proc$ls180.v:1780$3831 + assign { } { } + assign $1\main_sdmem2block_dma_loop_re[0:0] 1'0 + sync always + sync init + update \main_sdmem2block_dma_loop_re $1\main_sdmem2block_dma_loop_re[0:0] + end + attribute \src "ls180.v:1784.12-1784.47" + process $proc$ls180.v:1784$3832 + assign { } { } + assign $1\main_sdmem2block_dma_offset[31:0] 0 + sync always + sync init + update \main_sdmem2block_dma_offset $1\main_sdmem2block_dma_offset[31:0] + end + attribute \src "ls180.v:1796.11-1796.64" + process $proc$ls180.v:1796$3833 + assign { } { } + assign $1\main_sdmem2block_converter_source_payload_data[7:0] 8'00000000 + sync always + sync init + update \main_sdmem2block_converter_source_payload_data $1\main_sdmem2block_converter_source_payload_data[7:0] + end + attribute \src "ls180.v:1798.11-1798.48" + process $proc$ls180.v:1798$3834 + assign { } { } + assign $1\main_sdmem2block_converter_mux[2:0] 3'000 + sync always + sync init + update \main_sdmem2block_converter_mux $1\main_sdmem2block_converter_mux[2:0] + end + attribute \src "ls180.v:1822.11-1822.45" + process $proc$ls180.v:1822$3835 + assign { } { } + assign $1\main_sdmem2block_fifo_level[5:0] 6'000000 + sync always + sync init + update \main_sdmem2block_fifo_level $1\main_sdmem2block_fifo_level[5:0] + end + attribute \src "ls180.v:1823.5-1823.41" + process $proc$ls180.v:1823$3836 + assign { } { } + assign $0\main_sdmem2block_fifo_replace[0:0] 1'0 + sync always + update \main_sdmem2block_fifo_replace $0\main_sdmem2block_fifo_replace[0:0] + sync init + end + attribute \src "ls180.v:1824.11-1824.47" + process $proc$ls180.v:1824$3837 + assign { } { } + assign $1\main_sdmem2block_fifo_produce[4:0] 5'00000 + sync always + sync init + update \main_sdmem2block_fifo_produce $1\main_sdmem2block_fifo_produce[4:0] + end + attribute \src "ls180.v:1825.11-1825.47" + process $proc$ls180.v:1825$3838 + assign { } { } + assign $1\main_sdmem2block_fifo_consume[4:0] 5'00000 + sync always + sync init + update \main_sdmem2block_fifo_consume $1\main_sdmem2block_fifo_consume[4:0] + end + attribute \src "ls180.v:1826.11-1826.50" + process $proc$ls180.v:1826$3839 + assign { } { } + assign $1\main_sdmem2block_fifo_wrport_adr[4:0] 5'00000 + sync always + sync init + update \main_sdmem2block_fifo_wrport_adr $1\main_sdmem2block_fifo_wrport_adr[4:0] + end + attribute \src "ls180.v:1839.5-1839.36" + process $proc$ls180.v:1839$3840 + assign { } { } + assign $1\builder_converter0_state[0:0] 1'0 + sync always + sync init + update \builder_converter0_state $1\builder_converter0_state[0:0] + end + attribute \src "ls180.v:1840.5-1840.41" + process $proc$ls180.v:1840$3841 + assign { } { } + assign $1\builder_converter0_next_state[0:0] 1'0 + sync always + sync init + update \builder_converter0_next_state $1\builder_converter0_next_state[0:0] + end + attribute \src "ls180.v:1841.5-1841.57" + process $proc$ls180.v:1841$3842 + assign { } { } + assign $1\main_converter0_counter_converter0_next_value[0:0] 1'0 + sync always + sync init + update \main_converter0_counter_converter0_next_value $1\main_converter0_counter_converter0_next_value[0:0] + end + attribute \src "ls180.v:1842.5-1842.60" + process $proc$ls180.v:1842$3843 + assign { } { } + assign $1\main_converter0_counter_converter0_next_value_ce[0:0] 1'0 + sync always + sync init + update \main_converter0_counter_converter0_next_value_ce $1\main_converter0_counter_converter0_next_value_ce[0:0] + end + attribute \src "ls180.v:1843.5-1843.36" + process $proc$ls180.v:1843$3844 + assign { } { } + assign $1\builder_converter1_state[0:0] 1'0 + sync always + sync init + update \builder_converter1_state $1\builder_converter1_state[0:0] + end + attribute \src "ls180.v:1844.5-1844.41" + process $proc$ls180.v:1844$3845 + assign { } { } + assign $1\builder_converter1_next_state[0:0] 1'0 + sync always + sync init + update \builder_converter1_next_state $1\builder_converter1_next_state[0:0] + end + attribute \src "ls180.v:1845.5-1845.57" + process $proc$ls180.v:1845$3846 + assign { } { } + assign $1\main_converter1_counter_converter1_next_value[0:0] 1'0 + sync always + sync init + update \main_converter1_counter_converter1_next_value $1\main_converter1_counter_converter1_next_value[0:0] + end + attribute \src "ls180.v:1846.5-1846.60" + process $proc$ls180.v:1846$3847 + assign { } { } + assign $1\main_converter1_counter_converter1_next_value_ce[0:0] 1'0 + sync always + sync init + update \main_converter1_counter_converter1_next_value_ce $1\main_converter1_counter_converter1_next_value_ce[0:0] + end + attribute \src "ls180.v:1847.5-1847.36" + process $proc$ls180.v:1847$3848 + assign { } { } + assign $1\builder_converter2_state[0:0] 1'0 + sync always + sync init + update \builder_converter2_state $1\builder_converter2_state[0:0] + end + attribute \src "ls180.v:1848.5-1848.41" + process $proc$ls180.v:1848$3849 + assign { } { } + assign $1\builder_converter2_next_state[0:0] 1'0 + sync always + sync init + update \builder_converter2_next_state $1\builder_converter2_next_state[0:0] + end + attribute \src "ls180.v:1849.5-1849.60" + process $proc$ls180.v:1849$3850 + assign { } { } + assign $1\main_socbushandler_counter_converter2_next_value[0:0] 1'0 + sync always + sync init + update \main_socbushandler_counter_converter2_next_value $1\main_socbushandler_counter_converter2_next_value[0:0] + end + attribute \src "ls180.v:1850.5-1850.63" + process $proc$ls180.v:1850$3851 + assign { } { } + assign $1\main_socbushandler_counter_converter2_next_value_ce[0:0] 1'0 + sync always + sync init + update \main_socbushandler_counter_converter2_next_value_ce $1\main_socbushandler_counter_converter2_next_value_ce[0:0] + end + attribute \src "ls180.v:1851.11-1851.41" + process $proc$ls180.v:1851$3852 + assign { } { } + assign $1\builder_refresher_state[1:0] 2'00 + sync always + sync init + update \builder_refresher_state $1\builder_refresher_state[1:0] + end + attribute \src "ls180.v:1852.11-1852.46" + process $proc$ls180.v:1852$3853 + assign { } { } + assign $1\builder_refresher_next_state[1:0] 2'00 + sync always + sync init + update \builder_refresher_next_state $1\builder_refresher_next_state[1:0] + end + attribute \src "ls180.v:1853.11-1853.44" + process $proc$ls180.v:1853$3854 + assign { } { } + assign $1\builder_bankmachine0_state[2:0] 3'000 + sync always + sync init + update \builder_bankmachine0_state $1\builder_bankmachine0_state[2:0] + end + attribute \src "ls180.v:1854.11-1854.49" + process $proc$ls180.v:1854$3855 + assign { } { } + assign $1\builder_bankmachine0_next_state[2:0] 3'000 + sync always + sync init + update \builder_bankmachine0_next_state $1\builder_bankmachine0_next_state[2:0] + end + attribute \src "ls180.v:1855.11-1855.44" + process $proc$ls180.v:1855$3856 + assign { } { } + assign $1\builder_bankmachine1_state[2:0] 3'000 + sync always + sync init + update \builder_bankmachine1_state $1\builder_bankmachine1_state[2:0] + end + attribute \src "ls180.v:1856.11-1856.49" + process $proc$ls180.v:1856$3857 + assign { } { } + assign $1\builder_bankmachine1_next_state[2:0] 3'000 + sync always + sync init + update \builder_bankmachine1_next_state $1\builder_bankmachine1_next_state[2:0] + end + attribute \src "ls180.v:1857.11-1857.44" + process $proc$ls180.v:1857$3858 + assign { } { } + assign $1\builder_bankmachine2_state[2:0] 3'000 + sync always + sync init + update \builder_bankmachine2_state $1\builder_bankmachine2_state[2:0] + end + attribute \src "ls180.v:1858.11-1858.49" + process $proc$ls180.v:1858$3859 + assign { } { } + assign $1\builder_bankmachine2_next_state[2:0] 3'000 + sync always + sync init + update \builder_bankmachine2_next_state $1\builder_bankmachine2_next_state[2:0] + end + attribute \src "ls180.v:1859.11-1859.44" + process $proc$ls180.v:1859$3860 + assign { } { } + assign $1\builder_bankmachine3_state[2:0] 3'000 + sync always + sync init + update \builder_bankmachine3_state $1\builder_bankmachine3_state[2:0] + end + attribute \src "ls180.v:1860.11-1860.49" + process $proc$ls180.v:1860$3861 + assign { } { } + assign $1\builder_bankmachine3_next_state[2:0] 3'000 + sync always + sync init + update \builder_bankmachine3_next_state $1\builder_bankmachine3_next_state[2:0] + end + attribute \src "ls180.v:1861.11-1861.43" + process $proc$ls180.v:1861$3862 + assign { } { } + assign $1\builder_multiplexer_state[2:0] 3'000 + sync always + sync init + update \builder_multiplexer_state $1\builder_multiplexer_state[2:0] + end + attribute \src "ls180.v:1862.11-1862.48" + process $proc$ls180.v:1862$3863 + assign { } { } + assign $1\builder_multiplexer_next_state[2:0] 3'000 + sync always + sync init + update \builder_multiplexer_next_state $1\builder_multiplexer_next_state[2:0] + end + attribute \src "ls180.v:1875.5-1875.27" + process $proc$ls180.v:1875$3864 + assign { } { } + assign $0\builder_locked0[0:0] 1'0 + sync always + update \builder_locked0 $0\builder_locked0[0:0] + sync init + end + attribute \src "ls180.v:1876.5-1876.27" + process $proc$ls180.v:1876$3865 + assign { } { } + assign $0\builder_locked1[0:0] 1'0 + sync always + update \builder_locked1 $0\builder_locked1[0:0] + sync init + end + attribute \src "ls180.v:1877.5-1877.27" + process $proc$ls180.v:1877$3866 + assign { } { } + assign $0\builder_locked2[0:0] 1'0 + sync always + update \builder_locked2 $0\builder_locked2[0:0] + sync init + end + attribute \src "ls180.v:1878.5-1878.27" + process $proc$ls180.v:1878$3867 + assign { } { } + assign $0\builder_locked3[0:0] 1'0 + sync always + update \builder_locked3 $0\builder_locked3[0:0] + sync init + end + attribute \src "ls180.v:1879.5-1879.42" + process $proc$ls180.v:1879$3868 + assign { } { } + assign $1\builder_new_master_wdata_ready[0:0] 1'0 + sync always + sync init + update \builder_new_master_wdata_ready $1\builder_new_master_wdata_ready[0:0] + end + attribute \src "ls180.v:1880.5-1880.43" + process $proc$ls180.v:1880$3869 + assign { } { } + assign $1\builder_new_master_rdata_valid0[0:0] 1'0 + sync always + sync init + update \builder_new_master_rdata_valid0 $1\builder_new_master_rdata_valid0[0:0] + end + attribute \src "ls180.v:1881.5-1881.43" + process $proc$ls180.v:1881$3870 + assign { } { } + assign $1\builder_new_master_rdata_valid1[0:0] 1'0 + sync always + sync init + update \builder_new_master_rdata_valid1 $1\builder_new_master_rdata_valid1[0:0] + end + attribute \src "ls180.v:1882.5-1882.43" + process $proc$ls180.v:1882$3871 + assign { } { } + assign $1\builder_new_master_rdata_valid2[0:0] 1'0 + sync always + sync init + update \builder_new_master_rdata_valid2 $1\builder_new_master_rdata_valid2[0:0] + end + attribute \src "ls180.v:1883.5-1883.43" + process $proc$ls180.v:1883$3872 + assign { } { } + assign $1\builder_new_master_rdata_valid3[0:0] 1'0 + sync always + sync init + update \builder_new_master_rdata_valid3 $1\builder_new_master_rdata_valid3[0:0] + end + attribute \src "ls180.v:1884.5-1884.35" + process $proc$ls180.v:1884$3873 + assign { } { } + assign $1\builder_converter_state[0:0] 1'0 + sync always + sync init + update \builder_converter_state $1\builder_converter_state[0:0] + end + attribute \src "ls180.v:1885.5-1885.40" + process $proc$ls180.v:1885$3874 + assign { } { } + assign $1\builder_converter_next_state[0:0] 1'0 + sync always + sync init + update \builder_converter_next_state $1\builder_converter_next_state[0:0] + end + attribute \src "ls180.v:1886.5-1886.55" + process $proc$ls180.v:1886$3875 + assign { } { } + assign $1\main_converter_counter_converter_next_value[0:0] 1'0 + sync always + sync init + update \main_converter_counter_converter_next_value $1\main_converter_counter_converter_next_value[0:0] + end + attribute \src "ls180.v:1887.5-1887.58" + process $proc$ls180.v:1887$3876 + assign { } { } + assign $1\main_converter_counter_converter_next_value_ce[0:0] 1'0 + sync always + sync init + update \main_converter_counter_converter_next_value_ce $1\main_converter_counter_converter_next_value_ce[0:0] + end + attribute \src "ls180.v:1888.11-1888.42" + process $proc$ls180.v:1888$3877 + assign { } { } + assign $1\builder_spimaster0_state[1:0] 2'00 + sync always + sync init + update \builder_spimaster0_state $1\builder_spimaster0_state[1:0] + end + attribute \src "ls180.v:1889.11-1889.47" + process $proc$ls180.v:1889$3878 + assign { } { } + assign $1\builder_spimaster0_next_state[1:0] 2'00 + sync always + sync init + update \builder_spimaster0_next_state $1\builder_spimaster0_next_state[1:0] + end + attribute \src "ls180.v:1890.11-1890.62" + process $proc$ls180.v:1890$3879 + assign { } { } + assign $1\main_spimaster27_count_spimaster0_next_value[2:0] 3'000 + sync always + sync init + update \main_spimaster27_count_spimaster0_next_value $1\main_spimaster27_count_spimaster0_next_value[2:0] + end + attribute \src "ls180.v:1891.5-1891.59" + process $proc$ls180.v:1891$3880 + assign { } { } + assign $1\main_spimaster27_count_spimaster0_next_value_ce[0:0] 1'0 + sync always + sync init + update \main_spimaster27_count_spimaster0_next_value_ce $1\main_spimaster27_count_spimaster0_next_value_ce[0:0] + end + attribute \src "ls180.v:1892.11-1892.42" + process $proc$ls180.v:1892$3881 + assign { } { } + assign $1\builder_spimaster1_state[1:0] 2'00 + sync always + sync init + update \builder_spimaster1_state $1\builder_spimaster1_state[1:0] + end + attribute \src "ls180.v:1893.11-1893.47" + process $proc$ls180.v:1893$3882 + assign { } { } + assign $1\builder_spimaster1_next_state[1:0] 2'00 + sync always + sync init + update \builder_spimaster1_next_state $1\builder_spimaster1_next_state[1:0] + end + attribute \src "ls180.v:1894.11-1894.60" + process $proc$ls180.v:1894$3883 + assign { } { } + assign $1\main_spisdcard_count_spimaster1_next_value[2:0] 3'000 + sync always + sync init + update \main_spisdcard_count_spimaster1_next_value $1\main_spisdcard_count_spimaster1_next_value[2:0] + end + attribute \src "ls180.v:1895.5-1895.57" + process $proc$ls180.v:1895$3884 + assign { } { } + assign $1\main_spisdcard_count_spimaster1_next_value_ce[0:0] 1'0 + sync always + sync init + update \main_spisdcard_count_spimaster1_next_value_ce $1\main_spisdcard_count_spimaster1_next_value_ce[0:0] + end + attribute \src "ls180.v:1896.5-1896.41" + process $proc$ls180.v:1896$3885 + assign { } { } + assign $1\builder_sdphy_sdphyinit_state[0:0] 1'0 + sync always + sync init + update \builder_sdphy_sdphyinit_state $1\builder_sdphy_sdphyinit_state[0:0] + end + attribute \src "ls180.v:1897.5-1897.46" + process $proc$ls180.v:1897$3886 + assign { } { } + assign $1\builder_sdphy_sdphyinit_next_state[0:0] 1'0 + sync always + sync init + update \builder_sdphy_sdphyinit_next_state $1\builder_sdphy_sdphyinit_next_state[0:0] + end + attribute \src "ls180.v:1898.11-1898.66" + process $proc$ls180.v:1898$3887 + assign { } { } + assign $1\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_init_count_sdphy_sdphyinit_next_value $1\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] + end + attribute \src "ls180.v:1899.5-1899.63" + process $proc$ls180.v:1899$3888 + assign { } { } + assign $1\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] 1'0 + sync always + sync init + update \main_sdphy_init_count_sdphy_sdphyinit_next_value_ce $1\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] + end + attribute \src "ls180.v:1900.11-1900.47" + process $proc$ls180.v:1900$3889 + assign { } { } + assign $1\builder_sdphy_sdphycmdw_state[1:0] 2'00 + sync always + sync init + update \builder_sdphy_sdphycmdw_state $1\builder_sdphy_sdphycmdw_state[1:0] + end + attribute \src "ls180.v:1901.11-1901.52" + process $proc$ls180.v:1901$3890 + assign { } { } + assign $1\builder_sdphy_sdphycmdw_next_state[1:0] 2'00 + sync always + sync init + update \builder_sdphy_sdphycmdw_next_state $1\builder_sdphy_sdphycmdw_next_state[1:0] + end + attribute \src "ls180.v:1902.11-1902.66" + process $proc$ls180.v:1902$3891 + assign { } { } + assign $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] + end + attribute \src "ls180.v:1903.5-1903.63" + process $proc$ls180.v:1903$3892 + assign { } { } + assign $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] + end + attribute \src "ls180.v:1904.11-1904.47" + process $proc$ls180.v:1904$3893 + assign { } { } + assign $1\builder_sdphy_sdphycmdr_state[2:0] 3'000 + sync always + sync init + update \builder_sdphy_sdphycmdr_state $1\builder_sdphy_sdphycmdr_state[2:0] + end + attribute \src "ls180.v:1905.11-1905.52" + process $proc$ls180.v:1905$3894 + assign { } { } + assign $1\builder_sdphy_sdphycmdr_next_state[2:0] 3'000 + sync always + sync init + update \builder_sdphy_sdphycmdr_next_state $1\builder_sdphy_sdphycmdr_next_state[2:0] + end + attribute \src "ls180.v:1906.11-1906.67" + process $proc$ls180.v:1906$3895 + assign { } { } + assign $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0 $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] + end + attribute \src "ls180.v:1907.5-1907.64" + process $proc$ls180.v:1907$3896 + assign { } { } + assign $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0 $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] + end + attribute \src "ls180.v:1908.12-1908.71" + process $proc$ls180.v:1908$3897 + assign { } { } + assign $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] 0 + sync always + sync init + update \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1 $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] + end + attribute \src "ls180.v:1909.5-1909.66" + process $proc$ls180.v:1909$3898 + assign { } { } + assign $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1 $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] + end + attribute \src "ls180.v:1910.5-1910.66" + process $proc$ls180.v:1910$3899 + assign { } { } + assign $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2 $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] + end + attribute \src "ls180.v:1911.5-1911.69" + process $proc$ls180.v:1911$3900 + assign { } { } + assign $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] 1'0 + sync always + sync init + update \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2 $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] + end + attribute \src "ls180.v:1912.5-1912.41" + process $proc$ls180.v:1912$3901 + assign { } { } + assign $1\builder_sdphy_sdphycrcr_state[0:0] 1'0 + sync always + sync init + update \builder_sdphy_sdphycrcr_state $1\builder_sdphy_sdphycrcr_state[0:0] + end + attribute \src "ls180.v:1913.5-1913.46" + process $proc$ls180.v:1913$3902 + assign { } { } + assign $1\builder_sdphy_sdphycrcr_next_state[0:0] 1'0 + sync always + sync init + update \builder_sdphy_sdphycrcr_next_state $1\builder_sdphy_sdphycrcr_next_state[0:0] + end + attribute \src "ls180.v:1914.5-1914.66" + process $proc$ls180.v:1914$3903 + assign { } { } + assign $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] + end + attribute \src "ls180.v:1915.5-1915.69" + process $proc$ls180.v:1915$3904 + assign { } { } + assign $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] + end + attribute \src "ls180.v:1916.11-1916.41" + process $proc$ls180.v:1916$3905 + assign { } { } + assign $1\builder_sdphy_fsm_state[2:0] 3'000 + sync always + sync init + update \builder_sdphy_fsm_state $1\builder_sdphy_fsm_state[2:0] + end + attribute \src "ls180.v:1917.11-1917.46" + process $proc$ls180.v:1917$3906 + assign { } { } + assign $1\builder_sdphy_fsm_next_state[2:0] 3'000 + sync always + sync init + update \builder_sdphy_fsm_next_state $1\builder_sdphy_fsm_next_state[2:0] + end + attribute \src "ls180.v:1918.11-1918.61" + process $proc$ls180.v:1918$3907 + assign { } { } + assign $1\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] 8'00000000 + sync always + sync init + update \main_sdphy_dataw_count_sdphy_fsm_next_value $1\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] + end + attribute \src "ls180.v:1919.5-1919.58" + process $proc$ls180.v:1919$3908 + assign { } { } + assign $1\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] 1'0 + sync always + sync init + update \main_sdphy_dataw_count_sdphy_fsm_next_value_ce $1\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] + end + attribute \src "ls180.v:1920.11-1920.48" + process $proc$ls180.v:1920$3909 + assign { } { } + assign $1\builder_sdphy_sdphydatar_state[2:0] 3'000 + sync always + sync init + update \builder_sdphy_sdphydatar_state $1\builder_sdphy_sdphydatar_state[2:0] + end + attribute \src "ls180.v:1921.11-1921.53" + process $proc$ls180.v:1921$3910 + assign { } { } + assign $1\builder_sdphy_sdphydatar_next_state[2:0] 3'000 + sync always + sync init + update \builder_sdphy_sdphydatar_next_state $1\builder_sdphy_sdphydatar_next_state[2:0] + end + attribute \src "ls180.v:1922.11-1922.70" + process $proc$ls180.v:1922$3911 + assign { } { } + assign $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] 10'0000000000 + sync always + sync init + update \main_sdphy_datar_count_sdphy_sdphydatar_next_value0 $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] + end + attribute \src "ls180.v:1923.5-1923.66" + process $proc$ls180.v:1923$3912 + assign { } { } + assign $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0 $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] + end + attribute \src "ls180.v:1924.12-1924.73" + process $proc$ls180.v:1924$3913 + assign { } { } + assign $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] 0 + sync always + sync init + update \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1 $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] + end + attribute \src "ls180.v:1925.5-1925.68" + process $proc$ls180.v:1925$3914 + assign { } { } + assign $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1 $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] + end + attribute \src "ls180.v:1926.5-1926.69" + process $proc$ls180.v:1926$3915 + assign { } { } + assign $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2 $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] + end + attribute \src "ls180.v:1927.5-1927.72" + process $proc$ls180.v:1927$3916 + assign { } { } + assign $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] 1'0 + sync always + sync init + update \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2 $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] + end + attribute \src "ls180.v:1928.5-1928.52" + process $proc$ls180.v:1928$3917 + assign { } { } + assign $1\builder_sdcore_crcupstreaminserter_state[0:0] 1'0 + sync always + sync init + update \builder_sdcore_crcupstreaminserter_state $1\builder_sdcore_crcupstreaminserter_state[0:0] + end + attribute \src "ls180.v:1929.5-1929.57" + process $proc$ls180.v:1929$3918 + assign { } { } + assign $1\builder_sdcore_crcupstreaminserter_next_state[0:0] 1'0 + sync always + sync init + update \builder_sdcore_crcupstreaminserter_next_state $1\builder_sdcore_crcupstreaminserter_next_state[0:0] + end + attribute \src "ls180.v:1930.12-1930.93" + process $proc$ls180.v:1930$3919 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0 $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] + end + attribute \src "ls180.v:1931.5-1931.88" + process $proc$ls180.v:1931$3920 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0 $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] + end + attribute \src "ls180.v:1932.12-1932.93" + process $proc$ls180.v:1932$3921 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1 $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] + end + attribute \src "ls180.v:1933.5-1933.88" + process $proc$ls180.v:1933$3922 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1 $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] + end + attribute \src "ls180.v:1934.12-1934.93" + process $proc$ls180.v:1934$3923 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2 $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] + end + attribute \src "ls180.v:1935.5-1935.88" + process $proc$ls180.v:1935$3924 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2 $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] + end + attribute \src "ls180.v:1936.12-1936.93" + process $proc$ls180.v:1936$3925 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3 $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] + end + attribute \src "ls180.v:1937.5-1937.88" + process $proc$ls180.v:1937$3926 + assign { } { } + assign $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3 $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] + end + attribute \src "ls180.v:1938.11-1938.87" + process $proc$ls180.v:1938$3927 + assign { } { } + assign $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] 3'000 + sync always + sync init + update \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4 $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] + end + attribute \src "ls180.v:1939.5-1939.84" + process $proc$ls180.v:1939$3928 + assign { } { } + assign $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] 1'0 + sync always + sync init + update \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4 $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] + end + attribute \src "ls180.v:1940.11-1940.42" + process $proc$ls180.v:1940$3929 + assign { } { } + assign $1\builder_sdcore_fsm_state[2:0] 3'000 + sync always + sync init + update \builder_sdcore_fsm_state $1\builder_sdcore_fsm_state[2:0] + end + attribute \src "ls180.v:1941.11-1941.47" + process $proc$ls180.v:1941$3930 + assign { } { } + assign $1\builder_sdcore_fsm_next_state[2:0] 3'000 + sync always + sync init + update \builder_sdcore_fsm_next_state $1\builder_sdcore_fsm_next_state[2:0] + end + attribute \src "ls180.v:1942.5-1942.55" + process $proc$ls180.v:1942$3931 + assign { } { } + assign $1\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] 1'0 + sync always + sync init + update \main_sdcore_cmd_done_sdcore_fsm_next_value0 $1\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] + end + attribute \src "ls180.v:1943.5-1943.58" + process $proc$ls180.v:1943$3932 + assign { } { } + assign $1\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] 1'0 + sync always + sync init + update \main_sdcore_cmd_done_sdcore_fsm_next_value_ce0 $1\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] + end + attribute \src "ls180.v:1944.5-1944.56" + process $proc$ls180.v:1944$3933 + assign { } { } + assign $1\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] 1'0 + sync always + sync init + update \main_sdcore_data_done_sdcore_fsm_next_value1 $1\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] + end + attribute \src "ls180.v:1945.5-1945.59" + process $proc$ls180.v:1945$3934 + assign { } { } + assign $1\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] 1'0 + sync always + sync init + update \main_sdcore_data_done_sdcore_fsm_next_value_ce1 $1\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] + end + attribute \src "ls180.v:1946.11-1946.62" + process $proc$ls180.v:1946$3935 + assign { } { } + assign $1\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] 3'000 + sync always + sync init + update \main_sdcore_cmd_count_sdcore_fsm_next_value2 $1\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] + end + attribute \src "ls180.v:1947.5-1947.59" + process $proc$ls180.v:1947$3936 + assign { } { } + assign $1\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] 1'0 + sync always + sync init + update \main_sdcore_cmd_count_sdcore_fsm_next_value_ce2 $1\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] + end + attribute \src "ls180.v:1948.12-1948.65" + process $proc$ls180.v:1948$3937 + assign { } { } + assign $1\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] 0 + sync always + sync init + update \main_sdcore_data_count_sdcore_fsm_next_value3 $1\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] + end + attribute \src "ls180.v:1949.5-1949.60" + process $proc$ls180.v:1949$3938 + assign { } { } + assign $1\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'0 + sync always + sync init + update \main_sdcore_data_count_sdcore_fsm_next_value_ce3 $1\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] + end + attribute \src "ls180.v:1950.5-1950.56" + process $proc$ls180.v:1950$3939 + assign { } { } + assign $1\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] 1'0 + sync always + sync init + update \main_sdcore_cmd_error_sdcore_fsm_next_value4 $1\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] + end + attribute \src "ls180.v:1951.5-1951.59" + process $proc$ls180.v:1951$3940 + assign { } { } + assign $1\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] 1'0 + sync always + sync init + update \main_sdcore_cmd_error_sdcore_fsm_next_value_ce4 $1\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] + end + attribute \src "ls180.v:1952.5-1952.58" + process $proc$ls180.v:1952$3941 + assign { } { } + assign $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] 1'0 + sync always + sync init + update \main_sdcore_cmd_timeout_sdcore_fsm_next_value5 $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] + end + attribute \src "ls180.v:1953.5-1953.61" + process $proc$ls180.v:1953$3942 + assign { } { } + assign $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] 1'0 + sync always + sync init + update \main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5 $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] + end + attribute \src "ls180.v:1954.5-1954.57" + process $proc$ls180.v:1954$3943 + assign { } { } + assign $1\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] 1'0 + sync always + sync init + update \main_sdcore_data_error_sdcore_fsm_next_value6 $1\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] + end + attribute \src "ls180.v:1955.5-1955.60" + process $proc$ls180.v:1955$3944 + assign { } { } + assign $1\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] 1'0 + sync always + sync init + update \main_sdcore_data_error_sdcore_fsm_next_value_ce6 $1\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] + end + attribute \src "ls180.v:1956.5-1956.59" + process $proc$ls180.v:1956$3945 + assign { } { } + assign $1\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] 1'0 + sync always + sync init + update \main_sdcore_data_timeout_sdcore_fsm_next_value7 $1\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] + end + attribute \src "ls180.v:1957.5-1957.62" + process $proc$ls180.v:1957$3946 + assign { } { } + assign $1\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] 1'0 + sync always + sync init + update \main_sdcore_data_timeout_sdcore_fsm_next_value_ce7 $1\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] + end + attribute \src "ls180.v:1958.13-1958.76" + process $proc$ls180.v:1958$3947 + assign { } { } + assign $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \main_sdcore_cmd_response_status_sdcore_fsm_next_value8 $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] + end + attribute \src "ls180.v:1959.5-1959.69" + process $proc$ls180.v:1959$3948 + assign { } { } + assign $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] 1'0 + sync always + sync init + update \main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8 $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] + end + attribute \src "ls180.v:1960.11-1960.46" + process $proc$ls180.v:1960$3949 + assign { } { } + assign $1\builder_sdblock2memdma_state[1:0] 2'00 + sync always + sync init + update \builder_sdblock2memdma_state $1\builder_sdblock2memdma_state[1:0] + end + attribute \src "ls180.v:1961.11-1961.51" + process $proc$ls180.v:1961$3950 + assign { } { } + assign $1\builder_sdblock2memdma_next_state[1:0] 2'00 + sync always + sync init + update \builder_sdblock2memdma_next_state $1\builder_sdblock2memdma_next_state[1:0] + end + attribute \src "ls180.v:1962.12-1962.87" + process $proc$ls180.v:1962$3951 + assign { } { } + assign $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] 0 + sync always + sync init + update \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] + end + attribute \src "ls180.v:1963.5-1963.82" + process $proc$ls180.v:1963$3952 + assign { } { } + assign $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] 1'0 + sync always + sync init + update \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] + end + attribute \src "ls180.v:1964.5-1964.44" + process $proc$ls180.v:1964$3953 + assign { } { } + assign $1\builder_sdmem2blockdma_fsm_state[0:0] 1'0 + sync always + sync init + update \builder_sdmem2blockdma_fsm_state $1\builder_sdmem2blockdma_fsm_state[0:0] + end + attribute \src "ls180.v:1965.5-1965.49" + process $proc$ls180.v:1965$3954 + assign { } { } + assign $1\builder_sdmem2blockdma_fsm_next_state[0:0] 1'0 + sync always + sync init + update \builder_sdmem2blockdma_fsm_next_state $1\builder_sdmem2blockdma_fsm_next_state[0:0] + end + attribute \src "ls180.v:1966.12-1966.75" + process $proc$ls180.v:1966$3955 + assign { } { } + assign $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[63:0] + end + attribute \src "ls180.v:1967.5-1967.70" + process $proc$ls180.v:1967$3956 + assign { } { } + assign $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] 1'0 + sync always + sync init + update \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] + end + attribute \src "ls180.v:1968.11-1968.60" + process $proc$ls180.v:1968$3957 + assign { } { } + assign $1\builder_sdmem2blockdma_resetinserter_state[1:0] 2'00 + sync always + sync init + update \builder_sdmem2blockdma_resetinserter_state $1\builder_sdmem2blockdma_resetinserter_state[1:0] + end + attribute \src "ls180.v:1969.11-1969.65" + process $proc$ls180.v:1969$3958 + assign { } { } + assign $1\builder_sdmem2blockdma_resetinserter_next_state[1:0] 2'00 + sync always + sync init + update \builder_sdmem2blockdma_resetinserter_next_state $1\builder_sdmem2blockdma_resetinserter_next_state[1:0] + end + attribute \src "ls180.v:1970.12-1970.87" + process $proc$ls180.v:1970$3959 + assign { } { } + assign $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] 0 + sync always + sync init + update \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] + end + attribute \src "ls180.v:1971.5-1971.82" + process $proc$ls180.v:1971$3960 + assign { } { } + assign $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] 1'0 + sync always + sync init + update \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] + end + attribute \src "ls180.v:1972.12-1972.43" + process $proc$ls180.v:1972$3961 + assign { } { } + assign $1\builder_libresocsim_adr[13:0] 14'00000000000000 + sync always + sync init + update \builder_libresocsim_adr $1\builder_libresocsim_adr[13:0] + end + attribute \src "ls180.v:1973.5-1973.34" + process $proc$ls180.v:1973$3962 + assign { } { } + assign $1\builder_libresocsim_we[0:0] 1'0 + sync always + sync init + update \builder_libresocsim_we $1\builder_libresocsim_we[0:0] + end + attribute \src "ls180.v:1974.11-1974.43" + process $proc$ls180.v:1974$3963 + assign { } { } + assign $1\builder_libresocsim_dat_w[7:0] 8'00000000 + sync always + sync init + update \builder_libresocsim_dat_w $1\builder_libresocsim_dat_w[7:0] + end + attribute \src "ls180.v:1976.12-1976.52" + process $proc$ls180.v:1976$3964 + assign { } { } + assign $0\builder_libresocsim_wishbone_adr[29:0] 30'000000000000000000000000000000 + sync always + update \builder_libresocsim_wishbone_adr $0\builder_libresocsim_wishbone_adr[29:0] + sync init + end + attribute \src "ls180.v:1977.12-1977.54" + process $proc$ls180.v:1977$3965 + assign { } { } + assign $0\builder_libresocsim_wishbone_dat_w[31:0] 0 + sync always + update \builder_libresocsim_wishbone_dat_w $0\builder_libresocsim_wishbone_dat_w[31:0] + sync init + end + attribute \src "ls180.v:1978.12-1978.54" + process $proc$ls180.v:1978$3966 + assign { } { } + assign $1\builder_libresocsim_wishbone_dat_r[31:0] 0 + sync always + sync init + update \builder_libresocsim_wishbone_dat_r $1\builder_libresocsim_wishbone_dat_r[31:0] + end + attribute \src "ls180.v:1979.11-1979.50" + process $proc$ls180.v:1979$3967 + assign { } { } + assign $0\builder_libresocsim_wishbone_sel[3:0] 4'0000 + sync always + update \builder_libresocsim_wishbone_sel $0\builder_libresocsim_wishbone_sel[3:0] + sync init + end + attribute \src "ls180.v:1980.5-1980.44" + process $proc$ls180.v:1980$3968 + assign { } { } + assign $0\builder_libresocsim_wishbone_cyc[0:0] 1'0 + sync always + update \builder_libresocsim_wishbone_cyc $0\builder_libresocsim_wishbone_cyc[0:0] + sync init + end + attribute \src "ls180.v:1981.5-1981.44" + process $proc$ls180.v:1981$3969 + assign { } { } + assign $0\builder_libresocsim_wishbone_stb[0:0] 1'0 + sync always + update \builder_libresocsim_wishbone_stb $0\builder_libresocsim_wishbone_stb[0:0] + sync init + end + attribute \src "ls180.v:1982.5-1982.44" + process $proc$ls180.v:1982$3970 + assign { } { } + assign $1\builder_libresocsim_wishbone_ack[0:0] 1'0 + sync always + sync init + update \builder_libresocsim_wishbone_ack $1\builder_libresocsim_wishbone_ack[0:0] + end + attribute \src "ls180.v:1983.5-1983.43" + process $proc$ls180.v:1983$3971 + assign { } { } + assign $0\builder_libresocsim_wishbone_we[0:0] 1'0 + sync always + update \builder_libresocsim_wishbone_we $0\builder_libresocsim_wishbone_we[0:0] + sync init + end + attribute \src "ls180.v:1986.12-1986.65" + process $proc$ls180.v:1986$3972 + assign { } { } + assign $0\builder_libresocsim_converted_interface_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + update \builder_libresocsim_converted_interface_dat_r $0\builder_libresocsim_converted_interface_dat_r[63:0] + sync init + end + attribute \src "ls180.v:1990.5-1990.55" + process $proc$ls180.v:1990$3973 + assign { } { } + assign $0\builder_libresocsim_converted_interface_ack[0:0] 1'0 + sync always + update \builder_libresocsim_converted_interface_ack $0\builder_libresocsim_converted_interface_ack[0:0] + sync init + end + attribute \src "ls180.v:1994.5-1994.55" + process $proc$ls180.v:1994$3974 + assign { } { } + assign $0\builder_libresocsim_converted_interface_err[0:0] 1'0 + sync always + update \builder_libresocsim_converted_interface_err $0\builder_libresocsim_converted_interface_err[0:0] + sync init + end + attribute \src "ls180.v:1997.12-1997.40" + process $proc$ls180.v:1997$3975 + assign { } { } + assign $1\builder_shared_dat_r[31:0] 0 + sync always + sync init + update \builder_shared_dat_r $1\builder_shared_dat_r[31:0] + end + attribute \src "ls180.v:2001.5-2001.30" + process $proc$ls180.v:2001$3976 + assign { } { } + assign $1\builder_shared_ack[0:0] 1'0 + sync always + sync init + update \builder_shared_ack $1\builder_shared_ack[0:0] + end + attribute \src "ls180.v:2007.11-2007.31" + process $proc$ls180.v:2007$3977 + assign { } { } + assign $1\builder_grant[2:0] 3'000 + sync always + sync init + update \builder_grant $1\builder_grant[2:0] + end + attribute \src "ls180.v:2008.12-2008.37" + process $proc$ls180.v:2008$3978 + assign { } { } + assign $1\builder_slave_sel[12:0] 13'0000000000000 + sync always + sync init + update \builder_slave_sel $1\builder_slave_sel[12:0] + end + attribute \src "ls180.v:2009.12-2009.39" + process $proc$ls180.v:2009$3979 + assign { } { } + assign $1\builder_slave_sel_r[12:0] 13'0000000000000 + sync always + sync init + update \builder_slave_sel_r $1\builder_slave_sel_r[12:0] + end + attribute \src "ls180.v:2010.5-2010.25" + process $proc$ls180.v:2010$3980 + assign { } { } + assign $1\builder_error[0:0] 1'0 + sync always + sync init + update \builder_error $1\builder_error[0:0] + end + attribute \src "ls180.v:2013.12-2013.39" + process $proc$ls180.v:2013$3981 + assign { } { } + assign $1\builder_count[19:0] 20'11110100001001000000 + sync always + sync init + update \builder_count $1\builder_count[19:0] + end + attribute \src "ls180.v:2017.11-2017.51" + process $proc$ls180.v:2017$3982 + assign { } { } + assign $1\builder_interface0_bank_bus_dat_r[7:0] 8'00000000 + sync always + sync init + update \builder_interface0_bank_bus_dat_r $1\builder_interface0_bank_bus_dat_r[7:0] + end + attribute \src "ls180.v:2058.11-2058.51" + process $proc$ls180.v:2058$3983 + assign { } { } + assign $1\builder_interface1_bank_bus_dat_r[7:0] 8'00000000 + sync always + sync init + update \builder_interface1_bank_bus_dat_r $1\builder_interface1_bank_bus_dat_r[7:0] + end + attribute \src "ls180.v:2087.11-2087.51" + process $proc$ls180.v:2087$3984 + assign { } { } + assign $1\builder_interface2_bank_bus_dat_r[7:0] 8'00000000 + sync always + sync init + update \builder_interface2_bank_bus_dat_r $1\builder_interface2_bank_bus_dat_r[7:0] + end + attribute \src "ls180.v:210.5-210.40" + process $proc$ls180.v:210$3150 + assign { } { } + assign $1\main_libresocsim_ram_bus_ack[0:0] 1'0 + sync always + sync init + update \main_libresocsim_ram_bus_ack $1\main_libresocsim_ram_bus_ack[0:0] + end + attribute \src "ls180.v:2100.11-2100.51" + process $proc$ls180.v:2100$3985 + assign { } { } + assign $1\builder_interface3_bank_bus_dat_r[7:0] 8'00000000 + sync always + sync init + update \builder_interface3_bank_bus_dat_r $1\builder_interface3_bank_bus_dat_r[7:0] + end + attribute \src "ls180.v:214.5-214.40" + process $proc$ls180.v:214$3151 + assign { } { } + assign $0\main_libresocsim_ram_bus_err[0:0] 1'0 + sync always + update \main_libresocsim_ram_bus_err $0\main_libresocsim_ram_bus_err[0:0] + sync init + end + attribute \src "ls180.v:2141.11-2141.51" + process $proc$ls180.v:2141$3986 + assign { } { } + assign $1\builder_interface4_bank_bus_dat_r[7:0] 8'00000000 + sync always + sync init + update \builder_interface4_bank_bus_dat_r $1\builder_interface4_bank_bus_dat_r[7:0] + end + attribute \src "ls180.v:217.11-217.37" + process $proc$ls180.v:217$3152 + assign { } { } + assign $1\main_libresocsim_we[7:0] 8'00000000 + sync always + sync init + update \main_libresocsim_we $1\main_libresocsim_we[7:0] + end + attribute \src "ls180.v:2182.11-2182.51" + process $proc$ls180.v:2182$3987 + assign { } { } + assign $1\builder_interface5_bank_bus_dat_r[7:0] 8'00000000 + sync always + sync init + update \builder_interface5_bank_bus_dat_r $1\builder_interface5_bank_bus_dat_r[7:0] + end + attribute \src "ls180.v:219.12-219.49" + process $proc$ls180.v:219$3153 + assign { } { } + assign $1\main_libresocsim_load_storage[31:0] 0 + sync always + sync init + update \main_libresocsim_load_storage $1\main_libresocsim_load_storage[31:0] + end + attribute \src "ls180.v:220.5-220.36" + process $proc$ls180.v:220$3154 + assign { } { } + assign $1\main_libresocsim_load_re[0:0] 1'0 + sync always + sync init + update \main_libresocsim_load_re $1\main_libresocsim_load_re[0:0] + end + attribute \src "ls180.v:221.12-221.51" + process $proc$ls180.v:221$3155 + assign { } { } + assign $1\main_libresocsim_reload_storage[31:0] 0 + sync always + sync init + update \main_libresocsim_reload_storage $1\main_libresocsim_reload_storage[31:0] + end + attribute \src "ls180.v:222.5-222.38" + process $proc$ls180.v:222$3156 + assign { } { } + assign $1\main_libresocsim_reload_re[0:0] 1'0 + sync always + sync init + update \main_libresocsim_reload_re $1\main_libresocsim_reload_re[0:0] + end + attribute \src "ls180.v:223.5-223.39" + process $proc$ls180.v:223$3157 + assign { } { } + assign $1\main_libresocsim_en_storage[0:0] 1'0 + sync always + sync init + update \main_libresocsim_en_storage $1\main_libresocsim_en_storage[0:0] + end + attribute \src "ls180.v:224.5-224.34" + process $proc$ls180.v:224$3158 + assign { } { } + assign $1\main_libresocsim_en_re[0:0] 1'0 + sync always + sync init + update \main_libresocsim_en_re $1\main_libresocsim_en_re[0:0] + end + attribute \src "ls180.v:2247.11-2247.51" + process $proc$ls180.v:2247$3988 + assign { } { } + assign $1\builder_interface6_bank_bus_dat_r[7:0] 8'00000000 + sync always + sync init + update \builder_interface6_bank_bus_dat_r $1\builder_interface6_bank_bus_dat_r[7:0] + end + attribute \src "ls180.v:225.5-225.49" + process $proc$ls180.v:225$3159 + assign { } { } + assign $1\main_libresocsim_update_value_storage[0:0] 1'0 + sync always + sync init + update \main_libresocsim_update_value_storage $1\main_libresocsim_update_value_storage[0:0] + end + attribute \src "ls180.v:226.5-226.44" + process $proc$ls180.v:226$3160 + assign { } { } + assign $1\main_libresocsim_update_value_re[0:0] 1'0 + sync always + sync init + update \main_libresocsim_update_value_re $1\main_libresocsim_update_value_re[0:0] + end + attribute \src "ls180.v:227.12-227.49" + process $proc$ls180.v:227$3161 + assign { } { } + assign $1\main_libresocsim_value_status[31:0] 0 + sync always + sync init + update \main_libresocsim_value_status $1\main_libresocsim_value_status[31:0] + end + attribute \src "ls180.v:231.5-231.41" + process $proc$ls180.v:231$3162 + assign { } { } + assign $1\main_libresocsim_zero_pending[0:0] 1'0 + sync always + sync init + update \main_libresocsim_zero_pending $1\main_libresocsim_zero_pending[0:0] + end + attribute \src "ls180.v:233.5-233.39" + process $proc$ls180.v:233$3163 + assign { } { } + assign $1\main_libresocsim_zero_clear[0:0] 1'0 + sync always + sync init + update \main_libresocsim_zero_clear $1\main_libresocsim_zero_clear[0:0] + end + attribute \src "ls180.v:234.5-234.45" + process $proc$ls180.v:234$3164 + assign { } { } + assign $1\main_libresocsim_zero_old_trigger[0:0] 1'0 + sync always + sync init + update \main_libresocsim_zero_old_trigger $1\main_libresocsim_zero_old_trigger[0:0] + end + attribute \src "ls180.v:2380.11-2380.51" + process $proc$ls180.v:2380$3989 + assign { } { } + assign $1\builder_interface7_bank_bus_dat_r[7:0] 8'00000000 + sync always + sync init + update \builder_interface7_bank_bus_dat_r $1\builder_interface7_bank_bus_dat_r[7:0] + end + attribute \src "ls180.v:243.5-243.49" + process $proc$ls180.v:243$3165 + assign { } { } + assign $1\main_libresocsim_eventmanager_storage[0:0] 1'0 + sync always + sync init + update \main_libresocsim_eventmanager_storage $1\main_libresocsim_eventmanager_storage[0:0] + end + attribute \src "ls180.v:244.5-244.44" + process $proc$ls180.v:244$3166 + assign { } { } + assign $1\main_libresocsim_eventmanager_re[0:0] 1'0 + sync always + sync init + update \main_libresocsim_eventmanager_re $1\main_libresocsim_eventmanager_re[0:0] + end + attribute \src "ls180.v:245.12-245.42" + process $proc$ls180.v:245$3167 + assign { } { } + assign $1\main_libresocsim_value[31:0] 0 + sync always + sync init + update \main_libresocsim_value $1\main_libresocsim_value[31:0] + end + attribute \src "ls180.v:2461.11-2461.51" + process $proc$ls180.v:2461$3990 + assign { } { } + assign $1\builder_interface8_bank_bus_dat_r[7:0] 8'00000000 + sync always + sync init + update \builder_interface8_bank_bus_dat_r $1\builder_interface8_bank_bus_dat_r[7:0] + end + attribute \src "ls180.v:2478.11-2478.51" + process $proc$ls180.v:2478$3991 + assign { } { } + assign $1\builder_interface9_bank_bus_dat_r[7:0] 8'00000000 + sync always + sync init + update \builder_interface9_bank_bus_dat_r $1\builder_interface9_bank_bus_dat_r[7:0] + end + attribute \src "ls180.v:2519.11-2519.52" + process $proc$ls180.v:2519$3992 + assign { } { } + assign $1\builder_interface10_bank_bus_dat_r[7:0] 8'00000000 + sync always + sync init + update \builder_interface10_bank_bus_dat_r $1\builder_interface10_bank_bus_dat_r[7:0] + end + attribute \src "ls180.v:252.5-252.39" + process $proc$ls180.v:252$3168 + assign { } { } + assign $1\main_interface0_ram_bus_ack[0:0] 1'0 + sync always + sync init + update \main_interface0_ram_bus_ack $1\main_interface0_ram_bus_ack[0:0] + end + attribute \src "ls180.v:2552.11-2552.52" + process $proc$ls180.v:2552$3993 + assign { } { } + assign $1\builder_interface11_bank_bus_dat_r[7:0] 8'00000000 + sync always + sync init + update \builder_interface11_bank_bus_dat_r $1\builder_interface11_bank_bus_dat_r[7:0] + end + attribute \src "ls180.v:256.5-256.39" + process $proc$ls180.v:256$3169 + assign { } { } + assign $0\main_interface0_ram_bus_err[0:0] 1'0 + sync always + update \main_interface0_ram_bus_err $0\main_interface0_ram_bus_err[0:0] + sync init + end + attribute \src "ls180.v:259.11-259.31" + process $proc$ls180.v:259$3170 + assign { } { } + assign $1\main_sram0_we[7:0] 8'00000000 + sync always + sync init + update \main_sram0_we $1\main_sram0_we[7:0] + end + attribute \src "ls180.v:2593.11-2593.52" + process $proc$ls180.v:2593$3994 + assign { } { } + assign $1\builder_interface12_bank_bus_dat_r[7:0] 8'00000000 + sync always + sync init + update \builder_interface12_bank_bus_dat_r $1\builder_interface12_bank_bus_dat_r[7:0] + end + attribute \src "ls180.v:2658.11-2658.52" + process $proc$ls180.v:2658$3995 + assign { } { } + assign $1\builder_interface13_bank_bus_dat_r[7:0] 8'00000000 + sync always + sync init + update \builder_interface13_bank_bus_dat_r $1\builder_interface13_bank_bus_dat_r[7:0] + end + attribute \src "ls180.v:267.5-267.39" + process $proc$ls180.v:267$3171 + assign { } { } + assign $1\main_interface1_ram_bus_ack[0:0] 1'0 + sync always + sync init + update \main_interface1_ram_bus_ack $1\main_interface1_ram_bus_ack[0:0] + end + attribute \src "ls180.v:2683.11-2683.52" + process $proc$ls180.v:2683$3996 + assign { } { } + assign $1\builder_interface14_bank_bus_dat_r[7:0] 8'00000000 + sync always + sync init + update \builder_interface14_bank_bus_dat_r $1\builder_interface14_bank_bus_dat_r[7:0] + end + attribute \src "ls180.v:2705.11-2705.31" + process $proc$ls180.v:2705$3997 + assign { } { } + assign $1\builder_state[1:0] 2'00 + sync always + sync init + update \builder_state $1\builder_state[1:0] + end + attribute \src "ls180.v:2706.11-2706.36" + process $proc$ls180.v:2706$3998 + assign { } { } + assign $1\builder_next_state[1:0] 2'00 + sync always + sync init + update \builder_next_state $1\builder_next_state[1:0] + end + attribute \src "ls180.v:2707.11-2707.55" + process $proc$ls180.v:2707$3999 + assign { } { } + assign $1\builder_libresocsim_dat_w_next_value0[7:0] 8'00000000 + sync always + sync init + update \builder_libresocsim_dat_w_next_value0 $1\builder_libresocsim_dat_w_next_value0[7:0] + end + attribute \src "ls180.v:2708.5-2708.52" + process $proc$ls180.v:2708$4000 + assign { } { } + assign $1\builder_libresocsim_dat_w_next_value_ce0[0:0] 1'0 + sync always + sync init + update \builder_libresocsim_dat_w_next_value_ce0 $1\builder_libresocsim_dat_w_next_value_ce0[0:0] + end + attribute \src "ls180.v:2709.12-2709.55" + process $proc$ls180.v:2709$4001 + assign { } { } + assign $1\builder_libresocsim_adr_next_value1[13:0] 14'00000000000000 + sync always + sync init + update \builder_libresocsim_adr_next_value1 $1\builder_libresocsim_adr_next_value1[13:0] + end + attribute \src "ls180.v:271.5-271.39" + process $proc$ls180.v:271$3172 + assign { } { } + assign $0\main_interface1_ram_bus_err[0:0] 1'0 + sync always + update \main_interface1_ram_bus_err $0\main_interface1_ram_bus_err[0:0] + sync init + end + attribute \src "ls180.v:2710.5-2710.50" + process $proc$ls180.v:2710$4002 + assign { } { } + assign $1\builder_libresocsim_adr_next_value_ce1[0:0] 1'0 + sync always + sync init + update \builder_libresocsim_adr_next_value_ce1 $1\builder_libresocsim_adr_next_value_ce1[0:0] + end + attribute \src "ls180.v:2711.5-2711.46" + process $proc$ls180.v:2711$4003 + assign { } { } + assign $1\builder_libresocsim_we_next_value2[0:0] 1'0 + sync always + sync init + update \builder_libresocsim_we_next_value2 $1\builder_libresocsim_we_next_value2[0:0] + end + attribute \src "ls180.v:2712.5-2712.49" + process $proc$ls180.v:2712$4004 + assign { } { } + assign $1\builder_libresocsim_we_next_value_ce2[0:0] 1'0 + sync always + sync init + update \builder_libresocsim_we_next_value_ce2 $1\builder_libresocsim_we_next_value_ce2[0:0] + end + attribute \src "ls180.v:2713.5-2713.41" + process $proc$ls180.v:2713$4005 + assign { } { } + assign $1\builder_comb_rhs_array_muxed0[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed0 $1\builder_comb_rhs_array_muxed0[0:0] + end + attribute \src "ls180.v:2714.12-2714.49" + process $proc$ls180.v:2714$4006 + assign { } { } + assign $1\builder_comb_rhs_array_muxed1[12:0] 13'0000000000000 + sync always + sync init + update \builder_comb_rhs_array_muxed1 $1\builder_comb_rhs_array_muxed1[12:0] + end + attribute \src "ls180.v:2715.11-2715.47" + process $proc$ls180.v:2715$4007 + assign { } { } + assign $1\builder_comb_rhs_array_muxed2[1:0] 2'00 + sync always + sync init + update \builder_comb_rhs_array_muxed2 $1\builder_comb_rhs_array_muxed2[1:0] + end + attribute \src "ls180.v:2716.5-2716.41" + process $proc$ls180.v:2716$4008 + assign { } { } + assign $1\builder_comb_rhs_array_muxed3[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed3 $1\builder_comb_rhs_array_muxed3[0:0] + end + attribute \src "ls180.v:2717.5-2717.41" + process $proc$ls180.v:2717$4009 + assign { } { } + assign $1\builder_comb_rhs_array_muxed4[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed4 $1\builder_comb_rhs_array_muxed4[0:0] + end + attribute \src "ls180.v:2718.5-2718.41" + process $proc$ls180.v:2718$4010 + assign { } { } + assign $1\builder_comb_rhs_array_muxed5[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed5 $1\builder_comb_rhs_array_muxed5[0:0] + end + attribute \src "ls180.v:2719.5-2719.39" + process $proc$ls180.v:2719$4011 + assign { } { } + assign $1\builder_comb_t_array_muxed0[0:0] 1'0 + sync always + sync init + update \builder_comb_t_array_muxed0 $1\builder_comb_t_array_muxed0[0:0] + end + attribute \src "ls180.v:2720.5-2720.39" + process $proc$ls180.v:2720$4012 + assign { } { } + assign $1\builder_comb_t_array_muxed1[0:0] 1'0 + sync always + sync init + update \builder_comb_t_array_muxed1 $1\builder_comb_t_array_muxed1[0:0] + end + attribute \src "ls180.v:2721.5-2721.39" + process $proc$ls180.v:2721$4013 + assign { } { } + assign $1\builder_comb_t_array_muxed2[0:0] 1'0 + sync always + sync init + update \builder_comb_t_array_muxed2 $1\builder_comb_t_array_muxed2[0:0] + end + attribute \src "ls180.v:2722.5-2722.41" + process $proc$ls180.v:2722$4014 + assign { } { } + assign $1\builder_comb_rhs_array_muxed6[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed6 $1\builder_comb_rhs_array_muxed6[0:0] + end + attribute \src "ls180.v:2723.12-2723.49" + process $proc$ls180.v:2723$4015 + assign { } { } + assign $1\builder_comb_rhs_array_muxed7[12:0] 13'0000000000000 + sync always + sync init + update \builder_comb_rhs_array_muxed7 $1\builder_comb_rhs_array_muxed7[12:0] + end + attribute \src "ls180.v:2724.11-2724.47" + process $proc$ls180.v:2724$4016 + assign { } { } + assign $1\builder_comb_rhs_array_muxed8[1:0] 2'00 + sync always + sync init + update \builder_comb_rhs_array_muxed8 $1\builder_comb_rhs_array_muxed8[1:0] + end + attribute \src "ls180.v:2725.5-2725.41" + process $proc$ls180.v:2725$4017 + assign { } { } + assign $1\builder_comb_rhs_array_muxed9[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed9 $1\builder_comb_rhs_array_muxed9[0:0] + end + attribute \src "ls180.v:2726.5-2726.42" + process $proc$ls180.v:2726$4018 + assign { } { } + assign $1\builder_comb_rhs_array_muxed10[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed10 $1\builder_comb_rhs_array_muxed10[0:0] + end + attribute \src "ls180.v:2727.5-2727.42" + process $proc$ls180.v:2727$4019 + assign { } { } + assign $1\builder_comb_rhs_array_muxed11[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed11 $1\builder_comb_rhs_array_muxed11[0:0] + end + attribute \src "ls180.v:2728.5-2728.39" + process $proc$ls180.v:2728$4020 + assign { } { } + assign $1\builder_comb_t_array_muxed3[0:0] 1'0 + sync always + sync init + update \builder_comb_t_array_muxed3 $1\builder_comb_t_array_muxed3[0:0] + end + attribute \src "ls180.v:2729.5-2729.39" + process $proc$ls180.v:2729$4021 + assign { } { } + assign $1\builder_comb_t_array_muxed4[0:0] 1'0 + sync always + sync init + update \builder_comb_t_array_muxed4 $1\builder_comb_t_array_muxed4[0:0] + end + attribute \src "ls180.v:2730.5-2730.39" + process $proc$ls180.v:2730$4022 + assign { } { } + assign $1\builder_comb_t_array_muxed5[0:0] 1'0 + sync always + sync init + update \builder_comb_t_array_muxed5 $1\builder_comb_t_array_muxed5[0:0] + end + attribute \src "ls180.v:2731.12-2731.50" + process $proc$ls180.v:2731$4023 + assign { } { } + assign $1\builder_comb_rhs_array_muxed12[21:0] 22'0000000000000000000000 + sync always + sync init + update \builder_comb_rhs_array_muxed12 $1\builder_comb_rhs_array_muxed12[21:0] + end + attribute \src "ls180.v:2732.5-2732.42" + process $proc$ls180.v:2732$4024 + assign { } { } + assign $1\builder_comb_rhs_array_muxed13[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed13 $1\builder_comb_rhs_array_muxed13[0:0] + end + attribute \src "ls180.v:2733.5-2733.42" + process $proc$ls180.v:2733$4025 + assign { } { } + assign $1\builder_comb_rhs_array_muxed14[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed14 $1\builder_comb_rhs_array_muxed14[0:0] + end + attribute \src "ls180.v:2734.12-2734.50" + process $proc$ls180.v:2734$4026 + assign { } { } + assign $1\builder_comb_rhs_array_muxed15[21:0] 22'0000000000000000000000 + sync always + sync init + update \builder_comb_rhs_array_muxed15 $1\builder_comb_rhs_array_muxed15[21:0] + end + attribute \src "ls180.v:2735.5-2735.42" + process $proc$ls180.v:2735$4027 + assign { } { } + assign $1\builder_comb_rhs_array_muxed16[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed16 $1\builder_comb_rhs_array_muxed16[0:0] + end + attribute \src "ls180.v:2736.5-2736.42" + process $proc$ls180.v:2736$4028 + assign { } { } + assign $1\builder_comb_rhs_array_muxed17[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed17 $1\builder_comb_rhs_array_muxed17[0:0] + end + attribute \src "ls180.v:2737.12-2737.50" + process $proc$ls180.v:2737$4029 + assign { } { } + assign $1\builder_comb_rhs_array_muxed18[21:0] 22'0000000000000000000000 + sync always + sync init + update \builder_comb_rhs_array_muxed18 $1\builder_comb_rhs_array_muxed18[21:0] + end + attribute \src "ls180.v:2738.5-2738.42" + process $proc$ls180.v:2738$4030 + assign { } { } + assign $1\builder_comb_rhs_array_muxed19[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed19 $1\builder_comb_rhs_array_muxed19[0:0] + end + attribute \src "ls180.v:2739.5-2739.42" + process $proc$ls180.v:2739$4031 + assign { } { } + assign $1\builder_comb_rhs_array_muxed20[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed20 $1\builder_comb_rhs_array_muxed20[0:0] + end + attribute \src "ls180.v:274.11-274.31" + process $proc$ls180.v:274$3173 + assign { } { } + assign $1\main_sram1_we[7:0] 8'00000000 + sync always + sync init + update \main_sram1_we $1\main_sram1_we[7:0] + end + attribute \src "ls180.v:2740.12-2740.50" + process $proc$ls180.v:2740$4032 + assign { } { } + assign $1\builder_comb_rhs_array_muxed21[21:0] 22'0000000000000000000000 + sync always + sync init + update \builder_comb_rhs_array_muxed21 $1\builder_comb_rhs_array_muxed21[21:0] + end + attribute \src "ls180.v:2741.5-2741.42" + process $proc$ls180.v:2741$4033 + assign { } { } + assign $1\builder_comb_rhs_array_muxed22[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed22 $1\builder_comb_rhs_array_muxed22[0:0] + end + attribute \src "ls180.v:2742.5-2742.42" + process $proc$ls180.v:2742$4034 + assign { } { } + assign $1\builder_comb_rhs_array_muxed23[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed23 $1\builder_comb_rhs_array_muxed23[0:0] + end + attribute \src "ls180.v:2743.12-2743.50" + process $proc$ls180.v:2743$4035 + assign { } { } + assign $1\builder_comb_rhs_array_muxed24[31:0] 0 + sync always + sync init + update \builder_comb_rhs_array_muxed24 $1\builder_comb_rhs_array_muxed24[31:0] + end + attribute \src "ls180.v:2744.12-2744.50" + process $proc$ls180.v:2744$4036 + assign { } { } + assign $1\builder_comb_rhs_array_muxed25[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \builder_comb_rhs_array_muxed25 $1\builder_comb_rhs_array_muxed25[63:0] + end + attribute \src "ls180.v:2745.11-2745.48" + process $proc$ls180.v:2745$4037 + assign { } { } + assign $1\builder_comb_rhs_array_muxed26[7:0] 8'00000000 + sync always + sync init + update \builder_comb_rhs_array_muxed26 $1\builder_comb_rhs_array_muxed26[7:0] + end + attribute \src "ls180.v:2746.5-2746.42" + process $proc$ls180.v:2746$4038 + assign { } { } + assign $1\builder_comb_rhs_array_muxed27[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed27 $1\builder_comb_rhs_array_muxed27[0:0] + end + attribute \src "ls180.v:2747.5-2747.42" + process $proc$ls180.v:2747$4039 + assign { } { } + assign $1\builder_comb_rhs_array_muxed28[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed28 $1\builder_comb_rhs_array_muxed28[0:0] + end + attribute \src "ls180.v:2748.5-2748.42" + process $proc$ls180.v:2748$4040 + assign { } { } + assign $1\builder_comb_rhs_array_muxed29[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed29 $1\builder_comb_rhs_array_muxed29[0:0] + end + attribute \src "ls180.v:2749.11-2749.48" + process $proc$ls180.v:2749$4041 + assign { } { } + assign $1\builder_comb_rhs_array_muxed30[2:0] 3'000 + sync always + sync init + update \builder_comb_rhs_array_muxed30 $1\builder_comb_rhs_array_muxed30[2:0] + end + attribute \src "ls180.v:2750.11-2750.48" + process $proc$ls180.v:2750$4042 + assign { } { } + assign $1\builder_comb_rhs_array_muxed31[1:0] 2'00 + sync always + sync init + update \builder_comb_rhs_array_muxed31 $1\builder_comb_rhs_array_muxed31[1:0] + end + attribute \src "ls180.v:2751.11-2751.47" + process $proc$ls180.v:2751$4043 + assign { } { } + assign $1\builder_sync_rhs_array_muxed0[1:0] 2'00 + sync always + sync init + update \builder_sync_rhs_array_muxed0 $1\builder_sync_rhs_array_muxed0[1:0] + end + attribute \src "ls180.v:2752.12-2752.49" + process $proc$ls180.v:2752$4044 + assign { } { } + assign $1\builder_sync_rhs_array_muxed1[12:0] 13'0000000000000 + sync always + sync init + update \builder_sync_rhs_array_muxed1 $1\builder_sync_rhs_array_muxed1[12:0] + end + attribute \src "ls180.v:2753.5-2753.41" + process $proc$ls180.v:2753$4045 + assign { } { } + assign $1\builder_sync_rhs_array_muxed2[0:0] 1'0 + sync always + sync init + update \builder_sync_rhs_array_muxed2 $1\builder_sync_rhs_array_muxed2[0:0] + end + attribute \src "ls180.v:2754.5-2754.41" + process $proc$ls180.v:2754$4046 + assign { } { } + assign $1\builder_sync_rhs_array_muxed3[0:0] 1'0 + sync always + sync init + update \builder_sync_rhs_array_muxed3 $1\builder_sync_rhs_array_muxed3[0:0] + end + attribute \src "ls180.v:2755.5-2755.41" + process $proc$ls180.v:2755$4047 + assign { } { } + assign $1\builder_sync_rhs_array_muxed4[0:0] 1'0 + sync always + sync init + update \builder_sync_rhs_array_muxed4 $1\builder_sync_rhs_array_muxed4[0:0] + end + attribute \src "ls180.v:2756.5-2756.41" + process $proc$ls180.v:2756$4048 + assign { } { } + assign $1\builder_sync_rhs_array_muxed5[0:0] 1'0 + sync always + sync init + update \builder_sync_rhs_array_muxed5 $1\builder_sync_rhs_array_muxed5[0:0] + end + attribute \src "ls180.v:2757.5-2757.41" + process $proc$ls180.v:2757$4049 + assign { } { } + assign $1\builder_sync_rhs_array_muxed6[0:0] 1'0 + sync always + sync init + update \builder_sync_rhs_array_muxed6 $1\builder_sync_rhs_array_muxed6[0:0] + end + attribute \src "ls180.v:2758.5-2758.39" + process $proc$ls180.v:2758$4050 + assign { } { } + assign $1\builder_sync_f_array_muxed0[0:0] 1'0 + sync always + sync init + update \builder_sync_f_array_muxed0 $1\builder_sync_f_array_muxed0[0:0] + end + attribute \src "ls180.v:2759.5-2759.39" + process $proc$ls180.v:2759$4051 + assign { } { } + assign $1\builder_sync_f_array_muxed1[0:0] 1'0 + sync always + sync init + update \builder_sync_f_array_muxed1 $1\builder_sync_f_array_muxed1[0:0] + end + attribute \src "ls180.v:2816.32-2816.66" + process $proc$ls180.v:2816$4052 + assign { } { } + assign $1\builder_multiregimpl0_regs0[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl0_regs0 $1\builder_multiregimpl0_regs0[0:0] + end + attribute \src "ls180.v:2817.32-2817.66" + process $proc$ls180.v:2817$4053 + assign { } { } + assign $1\builder_multiregimpl0_regs1[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl0_regs1 $1\builder_multiregimpl0_regs1[0:0] + end + attribute \src "ls180.v:2818.32-2818.66" + process $proc$ls180.v:2818$4054 + assign { } { } + assign $1\builder_multiregimpl1_regs0[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl1_regs0 $1\builder_multiregimpl1_regs0[0:0] + end + attribute \src "ls180.v:2819.32-2819.66" + process $proc$ls180.v:2819$4055 + assign { } { } + assign $1\builder_multiregimpl1_regs1[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl1_regs1 $1\builder_multiregimpl1_regs1[0:0] + end + attribute \src "ls180.v:282.5-282.39" + process $proc$ls180.v:282$3174 + assign { } { } + assign $1\main_interface2_ram_bus_ack[0:0] 1'0 + sync always + sync init + update \main_interface2_ram_bus_ack $1\main_interface2_ram_bus_ack[0:0] + end + attribute \src "ls180.v:2820.32-2820.66" + process $proc$ls180.v:2820$4056 + assign { } { } + assign $1\builder_multiregimpl2_regs0[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl2_regs0 $1\builder_multiregimpl2_regs0[0:0] + end + attribute \src "ls180.v:2821.32-2821.66" + process $proc$ls180.v:2821$4057 + assign { } { } + assign $1\builder_multiregimpl2_regs1[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl2_regs1 $1\builder_multiregimpl2_regs1[0:0] + end + attribute \src "ls180.v:2822.32-2822.66" + process $proc$ls180.v:2822$4058 + assign { } { } + assign $1\builder_multiregimpl3_regs0[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl3_regs0 $1\builder_multiregimpl3_regs0[0:0] + end + attribute \src "ls180.v:2823.32-2823.66" + process $proc$ls180.v:2823$4059 + assign { } { } + assign $1\builder_multiregimpl3_regs1[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl3_regs1 $1\builder_multiregimpl3_regs1[0:0] + end + attribute \src "ls180.v:2824.32-2824.66" + process $proc$ls180.v:2824$4060 + assign { } { } + assign $1\builder_multiregimpl4_regs0[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl4_regs0 $1\builder_multiregimpl4_regs0[0:0] + end + attribute \src "ls180.v:2825.32-2825.66" + process $proc$ls180.v:2825$4061 + assign { } { } + assign $1\builder_multiregimpl4_regs1[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl4_regs1 $1\builder_multiregimpl4_regs1[0:0] + end + attribute \src "ls180.v:2826.32-2826.66" + process $proc$ls180.v:2826$4062 + assign { } { } + assign $1\builder_multiregimpl5_regs0[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl5_regs0 $1\builder_multiregimpl5_regs0[0:0] + end + attribute \src "ls180.v:2827.32-2827.66" + process $proc$ls180.v:2827$4063 + assign { } { } + assign $1\builder_multiregimpl5_regs1[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl5_regs1 $1\builder_multiregimpl5_regs1[0:0] + end + attribute \src "ls180.v:2828.32-2828.66" + process $proc$ls180.v:2828$4064 + assign { } { } + assign $1\builder_multiregimpl6_regs0[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl6_regs0 $1\builder_multiregimpl6_regs0[0:0] + end + attribute \src "ls180.v:2829.32-2829.66" + process $proc$ls180.v:2829$4065 + assign { } { } + assign $1\builder_multiregimpl6_regs1[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl6_regs1 $1\builder_multiregimpl6_regs1[0:0] + end + attribute \src "ls180.v:2830.32-2830.66" + process $proc$ls180.v:2830$4066 + assign { } { } + assign $1\builder_multiregimpl7_regs0[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl7_regs0 $1\builder_multiregimpl7_regs0[0:0] + end + attribute \src "ls180.v:2831.32-2831.66" + process $proc$ls180.v:2831$4067 + assign { } { } + assign $1\builder_multiregimpl7_regs1[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl7_regs1 $1\builder_multiregimpl7_regs1[0:0] + end + attribute \src "ls180.v:2832.32-2832.66" + process $proc$ls180.v:2832$4068 + assign { } { } + assign $1\builder_multiregimpl8_regs0[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl8_regs0 $1\builder_multiregimpl8_regs0[0:0] + end + attribute \src "ls180.v:2833.32-2833.66" + process $proc$ls180.v:2833$4069 + assign { } { } + assign $1\builder_multiregimpl8_regs1[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl8_regs1 $1\builder_multiregimpl8_regs1[0:0] + end + attribute \src "ls180.v:2834.32-2834.66" + process $proc$ls180.v:2834$4070 + assign { } { } + assign $1\builder_multiregimpl9_regs0[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl9_regs0 $1\builder_multiregimpl9_regs0[0:0] + end + attribute \src "ls180.v:2835.32-2835.66" + process $proc$ls180.v:2835$4071 + assign { } { } + assign $1\builder_multiregimpl9_regs1[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl9_regs1 $1\builder_multiregimpl9_regs1[0:0] + end + attribute \src "ls180.v:2836.32-2836.67" + process $proc$ls180.v:2836$4072 + assign { } { } + assign $1\builder_multiregimpl10_regs0[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl10_regs0 $1\builder_multiregimpl10_regs0[0:0] + end + attribute \src "ls180.v:2837.32-2837.67" + process $proc$ls180.v:2837$4073 + assign { } { } + assign $1\builder_multiregimpl10_regs1[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl10_regs1 $1\builder_multiregimpl10_regs1[0:0] + end + attribute \src "ls180.v:2838.32-2838.67" + process $proc$ls180.v:2838$4074 + assign { } { } + assign $1\builder_multiregimpl11_regs0[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl11_regs0 $1\builder_multiregimpl11_regs0[0:0] + end + attribute \src "ls180.v:2839.32-2839.67" + process $proc$ls180.v:2839$4075 + assign { } { } + assign $1\builder_multiregimpl11_regs1[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl11_regs1 $1\builder_multiregimpl11_regs1[0:0] + end + attribute \src "ls180.v:2840.32-2840.67" + process $proc$ls180.v:2840$4076 + assign { } { } + assign $1\builder_multiregimpl12_regs0[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl12_regs0 $1\builder_multiregimpl12_regs0[0:0] + end + attribute \src "ls180.v:2841.32-2841.67" + process $proc$ls180.v:2841$4077 + assign { } { } + assign $1\builder_multiregimpl12_regs1[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl12_regs1 $1\builder_multiregimpl12_regs1[0:0] + end + attribute \src "ls180.v:2842.32-2842.67" + process $proc$ls180.v:2842$4078 + assign { } { } + assign $1\builder_multiregimpl13_regs0[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl13_regs0 $1\builder_multiregimpl13_regs0[0:0] + end + attribute \src "ls180.v:2843.32-2843.67" + process $proc$ls180.v:2843$4079 + assign { } { } + assign $1\builder_multiregimpl13_regs1[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl13_regs1 $1\builder_multiregimpl13_regs1[0:0] + end + attribute \src "ls180.v:2844.32-2844.67" + process $proc$ls180.v:2844$4080 + assign { } { } + assign $1\builder_multiregimpl14_regs0[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl14_regs0 $1\builder_multiregimpl14_regs0[0:0] + end + attribute \src "ls180.v:2845.32-2845.67" + process $proc$ls180.v:2845$4081 + assign { } { } + assign $1\builder_multiregimpl14_regs1[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl14_regs1 $1\builder_multiregimpl14_regs1[0:0] + end + attribute \src "ls180.v:2846.32-2846.67" + process $proc$ls180.v:2846$4082 + assign { } { } + assign $1\builder_multiregimpl15_regs0[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl15_regs0 $1\builder_multiregimpl15_regs0[0:0] + end + attribute \src "ls180.v:2847.32-2847.67" + process $proc$ls180.v:2847$4083 + assign { } { } + assign $1\builder_multiregimpl15_regs1[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl15_regs1 $1\builder_multiregimpl15_regs1[0:0] + end + attribute \src "ls180.v:2848.32-2848.67" + process $proc$ls180.v:2848$4084 + assign { } { } + assign $1\builder_multiregimpl16_regs0[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl16_regs0 $1\builder_multiregimpl16_regs0[0:0] + end + attribute \src "ls180.v:2849.32-2849.67" + process $proc$ls180.v:2849$4085 + assign { } { } + assign $1\builder_multiregimpl16_regs1[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl16_regs1 $1\builder_multiregimpl16_regs1[0:0] + end + attribute \src "ls180.v:286.5-286.39" + process $proc$ls180.v:286$3175 + assign { } { } + assign $0\main_interface2_ram_bus_err[0:0] 1'0 + sync always + update \main_interface2_ram_bus_err $0\main_interface2_ram_bus_err[0:0] + sync init + end + attribute \src "ls180.v:2884.1-2889.4" + process $proc$ls180.v:2884$49 + assign { } { } + assign $0\main_libresocsim_libresoc_interrupt[15:0] [11:2] 10'0000000000 + assign $0\main_libresocsim_libresoc_interrupt[15:0] [15:12] { 1'0 \eint } + assign $0\main_libresocsim_libresoc_interrupt[15:0] [0] \main_libresocsim_irq + assign $0\main_libresocsim_libresoc_interrupt[15:0] [1] \main_uart_irq + sync always + update \main_libresocsim_libresoc_interrupt $0\main_libresocsim_libresoc_interrupt[15:0] + end + attribute \src "ls180.v:289.11-289.31" + process $proc$ls180.v:289$3176 + assign { } { } + assign $1\main_sram2_we[7:0] 8'00000000 + sync always + sync init + update \main_sram2_we $1\main_sram2_we[7:0] + end + attribute \src "ls180.v:2891.1-2901.4" + process $proc$ls180.v:2891$51 + assign { } { } + assign $0\main_libresocsim_libresoc_xics_icp_dat_w[31:0] 0 + attribute \src "ls180.v:2893.2-2900.9" + switch \main_converter0_counter + attribute \src "ls180.v:0.0-0.0" + case 1'0 + assign $0\main_libresocsim_libresoc_xics_icp_dat_w[31:0] \main_interface0_converted_interface_dat_w [31:0] + attribute \src "ls180.v:0.0-0.0" + case 1'1 + assign $0\main_libresocsim_libresoc_xics_icp_dat_w[31:0] \main_interface0_converted_interface_dat_w [63:32] + case + end + sync always + update \main_libresocsim_libresoc_xics_icp_dat_w $0\main_libresocsim_libresoc_xics_icp_dat_w[31:0] + end + attribute \src "ls180.v:2903.1-2949.4" + process $proc$ls180.v:2903$52 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_converter0_counter_converter0_next_value[0:0] 1'0 + assign $0\main_converter0_counter_converter0_next_value_ce[0:0] 1'0 + assign $0\main_libresocsim_libresoc_xics_icp_adr[29:0] 30'000000000000000000000000000000 + assign $0\main_interface0_converted_interface_ack[0:0] 1'0 + assign $0\main_libresocsim_libresoc_xics_icp_sel[3:0] 4'0000 + assign $0\main_libresocsim_libresoc_xics_icp_cyc[0:0] 1'0 + assign $0\main_libresocsim_libresoc_xics_icp_stb[0:0] 1'0 + assign $0\main_libresocsim_libresoc_xics_icp_we[0:0] 1'0 + assign $0\main_converter0_skip[0:0] 1'0 + assign $0\builder_converter0_next_state[0:0] \builder_converter0_state + attribute \src "ls180.v:2915.2-2948.9" + switch \builder_converter0_state + attribute \src "ls180.v:0.0-0.0" + case 1'1 + assign $0\main_libresocsim_libresoc_xics_icp_adr[29:0] { \main_interface0_converted_interface_adr [28:0] \main_converter0_counter } + attribute \src "ls180.v:2918.4-2925.11" + switch \main_converter0_counter + attribute \src "ls180.v:0.0-0.0" + case 1'0 + assign $0\main_libresocsim_libresoc_xics_icp_sel[3:0] \main_interface0_converted_interface_sel [3:0] + attribute \src "ls180.v:0.0-0.0" + case 1'1 + assign $0\main_libresocsim_libresoc_xics_icp_sel[3:0] \main_interface0_converted_interface_sel [7:4] + case + end + attribute \src "ls180.v:2926.4-2939.7" + switch $and$ls180.v:2926$53_Y + attribute \src "ls180.v:2926.8-2926.91" + case 1'1 + assign $0\main_converter0_skip[0:0] $eq$ls180.v:2927$54_Y + assign $0\main_libresocsim_libresoc_xics_icp_we[0:0] \main_interface0_converted_interface_we + assign $0\main_libresocsim_libresoc_xics_icp_cyc[0:0] $not$ls180.v:2929$55_Y + assign $0\main_libresocsim_libresoc_xics_icp_stb[0:0] $not$ls180.v:2930$56_Y + attribute \src "ls180.v:2931.5-2938.8" + switch $or$ls180.v:2931$57_Y + attribute \src "ls180.v:2931.9-2931.72" + case 1'1 + assign $0\main_converter0_counter_converter0_next_value[0:0] $add$ls180.v:2932$58_Y + assign $0\main_converter0_counter_converter0_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:2934.6-2937.9" + switch $eq$ls180.v:2934$59_Y + attribute \src "ls180.v:2934.10-2934.43" + case 1'1 + assign $0\main_interface0_converted_interface_ack[0:0] 1'1 + assign $0\builder_converter0_next_state[0:0] 1'0 + case + end + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_converter0_counter_converter0_next_value[0:0] 1'0 + assign $0\main_converter0_counter_converter0_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:2944.4-2946.7" + switch $and$ls180.v:2944$60_Y + attribute \src "ls180.v:2944.8-2944.91" + case 1'1 + assign $0\builder_converter0_next_state[0:0] 1'1 + case + end + end + sync always + update \main_libresocsim_libresoc_xics_icp_adr $0\main_libresocsim_libresoc_xics_icp_adr[29:0] + update \main_libresocsim_libresoc_xics_icp_sel $0\main_libresocsim_libresoc_xics_icp_sel[3:0] + update \main_libresocsim_libresoc_xics_icp_cyc $0\main_libresocsim_libresoc_xics_icp_cyc[0:0] + update \main_libresocsim_libresoc_xics_icp_stb $0\main_libresocsim_libresoc_xics_icp_stb[0:0] + update \main_libresocsim_libresoc_xics_icp_we $0\main_libresocsim_libresoc_xics_icp_we[0:0] + update \main_interface0_converted_interface_ack $0\main_interface0_converted_interface_ack[0:0] + update \main_converter0_skip $0\main_converter0_skip[0:0] + update \builder_converter0_next_state $0\builder_converter0_next_state[0:0] + update \main_converter0_counter_converter0_next_value $0\main_converter0_counter_converter0_next_value[0:0] + update \main_converter0_counter_converter0_next_value_ce $0\main_converter0_counter_converter0_next_value_ce[0:0] + end + attribute \src "ls180.v:2951.1-2961.4" + process $proc$ls180.v:2951$62 + assign { } { } + assign $0\main_libresocsim_libresoc_xics_ics_dat_w[31:0] 0 + attribute \src "ls180.v:2953.2-2960.9" + switch \main_converter1_counter + attribute \src "ls180.v:0.0-0.0" + case 1'0 + assign $0\main_libresocsim_libresoc_xics_ics_dat_w[31:0] \main_interface1_converted_interface_dat_w [31:0] + attribute \src "ls180.v:0.0-0.0" + case 1'1 + assign $0\main_libresocsim_libresoc_xics_ics_dat_w[31:0] \main_interface1_converted_interface_dat_w [63:32] + case + end + sync always + update \main_libresocsim_libresoc_xics_ics_dat_w $0\main_libresocsim_libresoc_xics_ics_dat_w[31:0] + end + attribute \src "ls180.v:2963.1-3009.4" + process $proc$ls180.v:2963$63 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_converter1_counter_converter1_next_value[0:0] 1'0 + assign $0\main_libresocsim_libresoc_xics_ics_adr[29:0] 30'000000000000000000000000000000 + assign $0\main_converter1_counter_converter1_next_value_ce[0:0] 1'0 + assign $0\main_libresocsim_libresoc_xics_ics_sel[3:0] 4'0000 + assign $0\main_interface1_converted_interface_ack[0:0] 1'0 + assign $0\main_libresocsim_libresoc_xics_ics_cyc[0:0] 1'0 + assign $0\main_libresocsim_libresoc_xics_ics_stb[0:0] 1'0 + assign $0\main_libresocsim_libresoc_xics_ics_we[0:0] 1'0 + assign $0\main_converter1_skip[0:0] 1'0 + assign $0\builder_converter1_next_state[0:0] \builder_converter1_state + attribute \src "ls180.v:2975.2-3008.9" + switch \builder_converter1_state + attribute \src "ls180.v:0.0-0.0" + case 1'1 + assign $0\main_libresocsim_libresoc_xics_ics_adr[29:0] { \main_interface1_converted_interface_adr [28:0] \main_converter1_counter } + attribute \src "ls180.v:2978.4-2985.11" + switch \main_converter1_counter + attribute \src "ls180.v:0.0-0.0" + case 1'0 + assign $0\main_libresocsim_libresoc_xics_ics_sel[3:0] \main_interface1_converted_interface_sel [3:0] + attribute \src "ls180.v:0.0-0.0" + case 1'1 + assign $0\main_libresocsim_libresoc_xics_ics_sel[3:0] \main_interface1_converted_interface_sel [7:4] + case + end + attribute \src "ls180.v:2986.4-2999.7" + switch $and$ls180.v:2986$64_Y + attribute \src "ls180.v:2986.8-2986.91" + case 1'1 + assign $0\main_converter1_skip[0:0] $eq$ls180.v:2987$65_Y + assign $0\main_libresocsim_libresoc_xics_ics_we[0:0] \main_interface1_converted_interface_we + assign $0\main_libresocsim_libresoc_xics_ics_cyc[0:0] $not$ls180.v:2989$66_Y + assign $0\main_libresocsim_libresoc_xics_ics_stb[0:0] $not$ls180.v:2990$67_Y + attribute \src "ls180.v:2991.5-2998.8" + switch $or$ls180.v:2991$68_Y + attribute \src "ls180.v:2991.9-2991.72" + case 1'1 + assign $0\main_converter1_counter_converter1_next_value[0:0] $add$ls180.v:2992$69_Y + assign $0\main_converter1_counter_converter1_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:2994.6-2997.9" + switch $eq$ls180.v:2994$70_Y + attribute \src "ls180.v:2994.10-2994.43" + case 1'1 + assign $0\main_interface1_converted_interface_ack[0:0] 1'1 + assign $0\builder_converter1_next_state[0:0] 1'0 + case + end + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_converter1_counter_converter1_next_value[0:0] 1'0 + assign $0\main_converter1_counter_converter1_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:3004.4-3006.7" + switch $and$ls180.v:3004$71_Y + attribute \src "ls180.v:3004.8-3004.91" + case 1'1 + assign $0\builder_converter1_next_state[0:0] 1'1 + case + end + end + sync always + update \main_libresocsim_libresoc_xics_ics_adr $0\main_libresocsim_libresoc_xics_ics_adr[29:0] + update \main_libresocsim_libresoc_xics_ics_sel $0\main_libresocsim_libresoc_xics_ics_sel[3:0] + update \main_libresocsim_libresoc_xics_ics_cyc $0\main_libresocsim_libresoc_xics_ics_cyc[0:0] + update \main_libresocsim_libresoc_xics_ics_stb $0\main_libresocsim_libresoc_xics_ics_stb[0:0] + update \main_libresocsim_libresoc_xics_ics_we $0\main_libresocsim_libresoc_xics_ics_we[0:0] + update \main_interface1_converted_interface_ack $0\main_interface1_converted_interface_ack[0:0] + update \main_converter1_skip $0\main_converter1_skip[0:0] + update \builder_converter1_next_state $0\builder_converter1_next_state[0:0] + update \main_converter1_counter_converter1_next_value $0\main_converter1_counter_converter1_next_value[0:0] + update \main_converter1_counter_converter1_next_value_ce $0\main_converter1_counter_converter1_next_value_ce[0:0] + end + attribute \src "ls180.v:297.5-297.39" + process $proc$ls180.v:297$3177 + assign { } { } + assign $1\main_interface3_ram_bus_ack[0:0] 1'0 + sync always + sync init + update \main_interface3_ram_bus_ack $1\main_interface3_ram_bus_ack[0:0] + end + attribute \src "ls180.v:301.5-301.39" + process $proc$ls180.v:301$3178 + assign { } { } + assign $0\main_interface3_ram_bus_err[0:0] 1'0 + sync always + update \main_interface3_ram_bus_err $0\main_interface3_ram_bus_err[0:0] + sync init + end + attribute \src "ls180.v:3011.1-3021.4" + process $proc$ls180.v:3011$73 + assign { } { } + assign $0\main_wb_sdram_dat_w[31:0] 0 + attribute \src "ls180.v:3013.2-3020.9" + switch \main_socbushandler_counter + attribute \src "ls180.v:0.0-0.0" + case 1'0 + assign $0\main_wb_sdram_dat_w[31:0] \main_socbushandler_converted_interface_dat_w [31:0] + attribute \src "ls180.v:0.0-0.0" + case 1'1 + assign $0\main_wb_sdram_dat_w[31:0] \main_socbushandler_converted_interface_dat_w [63:32] + case + end + sync always + update \main_wb_sdram_dat_w $0\main_wb_sdram_dat_w[31:0] + end + attribute \src "ls180.v:3023.1-3069.4" + process $proc$ls180.v:3023$74 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_wb_sdram_we[0:0] 1'0 + assign $0\main_socbushandler_counter_converter2_next_value_ce[0:0] 1'0 + assign $0\main_wb_sdram_adr[29:0] 30'000000000000000000000000000000 + assign $0\main_socbushandler_converted_interface_ack[0:0] 1'0 + assign $0\main_wb_sdram_sel[3:0] 4'0000 + assign $0\main_wb_sdram_cyc[0:0] 1'0 + assign $0\main_wb_sdram_stb[0:0] 1'0 + assign $0\main_socbushandler_skip[0:0] 1'0 + assign { } { } + assign $0\main_socbushandler_counter_converter2_next_value[0:0] 1'0 + assign $0\builder_converter2_next_state[0:0] \builder_converter2_state + attribute \src "ls180.v:3035.2-3068.9" + switch \builder_converter2_state + attribute \src "ls180.v:0.0-0.0" + case 1'1 + assign $0\main_wb_sdram_adr[29:0] { \main_socbushandler_converted_interface_adr [28:0] \main_socbushandler_counter } + attribute \src "ls180.v:3038.4-3045.11" + switch \main_socbushandler_counter + attribute \src "ls180.v:0.0-0.0" + case 1'0 + assign $0\main_wb_sdram_sel[3:0] \main_socbushandler_converted_interface_sel [3:0] + attribute \src "ls180.v:0.0-0.0" + case 1'1 + assign $0\main_wb_sdram_sel[3:0] \main_socbushandler_converted_interface_sel [7:4] + case + end + attribute \src "ls180.v:3046.4-3059.7" + switch $and$ls180.v:3046$75_Y + attribute \src "ls180.v:3046.8-3046.97" + case 1'1 + assign $0\main_socbushandler_skip[0:0] $eq$ls180.v:3047$76_Y + assign $0\main_wb_sdram_we[0:0] \main_socbushandler_converted_interface_we + assign $0\main_wb_sdram_cyc[0:0] $not$ls180.v:3049$77_Y + assign $0\main_wb_sdram_stb[0:0] $not$ls180.v:3050$78_Y + attribute \src "ls180.v:3051.5-3058.8" + switch $or$ls180.v:3051$79_Y + attribute \src "ls180.v:3051.9-3051.54" + case 1'1 + assign $0\main_socbushandler_counter_converter2_next_value[0:0] $add$ls180.v:3052$80_Y + assign $0\main_socbushandler_counter_converter2_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:3054.6-3057.9" + switch $eq$ls180.v:3054$81_Y + attribute \src "ls180.v:3054.10-3054.46" + case 1'1 + assign $0\main_socbushandler_converted_interface_ack[0:0] 1'1 + assign $0\builder_converter2_next_state[0:0] 1'0 + case + end + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_socbushandler_counter_converter2_next_value[0:0] 1'0 + assign $0\main_socbushandler_counter_converter2_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:3064.4-3066.7" + switch $and$ls180.v:3064$82_Y + attribute \src "ls180.v:3064.8-3064.97" + case 1'1 + assign $0\builder_converter2_next_state[0:0] 1'1 + case + end + end + sync always + update \main_wb_sdram_adr $0\main_wb_sdram_adr[29:0] + update \main_wb_sdram_sel $0\main_wb_sdram_sel[3:0] + update \main_wb_sdram_cyc $0\main_wb_sdram_cyc[0:0] + update \main_wb_sdram_stb $0\main_wb_sdram_stb[0:0] + update \main_wb_sdram_we $0\main_wb_sdram_we[0:0] + update \main_socbushandler_converted_interface_ack $0\main_socbushandler_converted_interface_ack[0:0] + update \main_socbushandler_skip $0\main_socbushandler_skip[0:0] + update \builder_converter2_next_state $0\builder_converter2_next_state[0:0] + update \main_socbushandler_counter_converter2_next_value $0\main_socbushandler_counter_converter2_next_value[0:0] + update \main_socbushandler_counter_converter2_next_value_ce $0\main_socbushandler_counter_converter2_next_value_ce[0:0] + end + attribute \src "ls180.v:304.11-304.31" + process $proc$ls180.v:304$3179 + assign { } { } + assign $1\main_sram3_we[7:0] 8'00000000 + sync always + sync init + update \main_sram3_we $1\main_sram3_we[7:0] + end + attribute \src "ls180.v:3072.1-3082.4" + process $proc$ls180.v:3072$83 + assign { } { } + assign { } { } + assign $0\main_libresocsim_we[7:0] [0] $and$ls180.v:3074$86_Y + assign $0\main_libresocsim_we[7:0] [1] $and$ls180.v:3075$89_Y + assign $0\main_libresocsim_we[7:0] [2] $and$ls180.v:3076$92_Y + assign $0\main_libresocsim_we[7:0] [3] $and$ls180.v:3077$95_Y + assign $0\main_libresocsim_we[7:0] [4] $and$ls180.v:3078$98_Y + assign $0\main_libresocsim_we[7:0] [5] $and$ls180.v:3079$101_Y + assign $0\main_libresocsim_we[7:0] [6] $and$ls180.v:3080$104_Y + assign $0\main_libresocsim_we[7:0] [7] $and$ls180.v:3081$107_Y + sync always + update \main_libresocsim_we $0\main_libresocsim_we[7:0] + end + attribute \src "ls180.v:3088.1-3093.4" + process $proc$ls180.v:3088$109 + assign { } { } + assign $0\main_libresocsim_zero_clear[0:0] 1'0 + attribute \src "ls180.v:3090.2-3092.5" + switch $and$ls180.v:3090$110_Y + attribute \src "ls180.v:3090.6-3090.90" + case 1'1 + assign $0\main_libresocsim_zero_clear[0:0] 1'1 + case + end + sync always + update \main_libresocsim_zero_clear $0\main_libresocsim_zero_clear[0:0] + end + attribute \src "ls180.v:3097.1-3107.4" + process $proc$ls180.v:3097$112 + assign { } { } + assign { } { } + assign $0\main_sram0_we[7:0] [0] $and$ls180.v:3099$115_Y + assign $0\main_sram0_we[7:0] [1] $and$ls180.v:3100$118_Y + assign $0\main_sram0_we[7:0] [2] $and$ls180.v:3101$121_Y + assign $0\main_sram0_we[7:0] [3] $and$ls180.v:3102$124_Y + assign $0\main_sram0_we[7:0] [4] $and$ls180.v:3103$127_Y + assign $0\main_sram0_we[7:0] [5] $and$ls180.v:3104$130_Y + assign $0\main_sram0_we[7:0] [6] $and$ls180.v:3105$133_Y + assign $0\main_sram0_we[7:0] [7] $and$ls180.v:3106$136_Y + sync always + update \main_sram0_we $0\main_sram0_we[7:0] + end + attribute \src "ls180.v:3111.1-3121.4" + process $proc$ls180.v:3111$137 + assign { } { } + assign { } { } + assign $0\main_sram1_we[7:0] [0] $and$ls180.v:3113$140_Y + assign $0\main_sram1_we[7:0] [1] $and$ls180.v:3114$143_Y + assign $0\main_sram1_we[7:0] [2] $and$ls180.v:3115$146_Y + assign $0\main_sram1_we[7:0] [3] $and$ls180.v:3116$149_Y + assign $0\main_sram1_we[7:0] [4] $and$ls180.v:3117$152_Y + assign $0\main_sram1_we[7:0] [5] $and$ls180.v:3118$155_Y + assign $0\main_sram1_we[7:0] [6] $and$ls180.v:3119$158_Y + assign $0\main_sram1_we[7:0] [7] $and$ls180.v:3120$161_Y + sync always + update \main_sram1_we $0\main_sram1_we[7:0] + end + attribute \src "ls180.v:312.5-312.51" + process $proc$ls180.v:312$3180 + assign { } { } + assign $1\main_interface0_converted_interface_ack[0:0] 1'0 + sync always + sync init + update \main_interface0_converted_interface_ack $1\main_interface0_converted_interface_ack[0:0] + end + attribute \src "ls180.v:3125.1-3135.4" + process $proc$ls180.v:3125$162 + assign { } { } + assign { } { } + assign $0\main_sram2_we[7:0] [0] $and$ls180.v:3127$165_Y + assign $0\main_sram2_we[7:0] [1] $and$ls180.v:3128$168_Y + assign $0\main_sram2_we[7:0] [2] $and$ls180.v:3129$171_Y + assign $0\main_sram2_we[7:0] [3] $and$ls180.v:3130$174_Y + assign $0\main_sram2_we[7:0] [4] $and$ls180.v:3131$177_Y + assign $0\main_sram2_we[7:0] [5] $and$ls180.v:3132$180_Y + assign $0\main_sram2_we[7:0] [6] $and$ls180.v:3133$183_Y + assign $0\main_sram2_we[7:0] [7] $and$ls180.v:3134$186_Y + sync always + update \main_sram2_we $0\main_sram2_we[7:0] + end + attribute \src "ls180.v:3139.1-3149.4" + process $proc$ls180.v:3139$187 + assign { } { } + assign { } { } + assign $0\main_sram3_we[7:0] [0] $and$ls180.v:3141$190_Y + assign $0\main_sram3_we[7:0] [1] $and$ls180.v:3142$193_Y + assign $0\main_sram3_we[7:0] [2] $and$ls180.v:3143$196_Y + assign $0\main_sram3_we[7:0] [3] $and$ls180.v:3144$199_Y + assign $0\main_sram3_we[7:0] [4] $and$ls180.v:3145$202_Y + assign $0\main_sram3_we[7:0] [5] $and$ls180.v:3146$205_Y + assign $0\main_sram3_we[7:0] [6] $and$ls180.v:3147$208_Y + assign $0\main_sram3_we[7:0] [7] $and$ls180.v:3148$211_Y + sync always + update \main_sram3_we $0\main_sram3_we[7:0] + end + attribute \src "ls180.v:316.5-316.51" + process $proc$ls180.v:316$3181 + assign { } { } + assign $0\main_interface0_converted_interface_err[0:0] 1'0 + sync always + update \main_interface0_converted_interface_err $0\main_interface0_converted_interface_err[0:0] + sync init + end + attribute \src "ls180.v:317.5-317.32" + process $proc$ls180.v:317$3182 + assign { } { } + assign $1\main_converter0_skip[0:0] 1'0 + sync always + sync init + update \main_converter0_skip $1\main_converter0_skip[0:0] + end + attribute \src "ls180.v:318.5-318.35" + process $proc$ls180.v:318$3183 + assign { } { } + assign $1\main_converter0_counter[0:0] 1'0 + sync always + sync init + update \main_converter0_counter $1\main_converter0_counter[0:0] + end + attribute \src "ls180.v:3188.1-3242.4" + process $proc$ls180.v:3188$212 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdram_slave_p0_rddata[15:0] 16'0000000000000000 + assign $0\main_sdram_slave_p0_rddata_valid[0:0] 1'0 + assign $0\main_sdram_master_p0_address[12:0] 13'0000000000000 + assign $0\main_sdram_master_p0_bank[1:0] 2'00 + assign $0\main_sdram_master_p0_cas_n[0:0] 1'1 + assign $0\main_sdram_master_p0_cs_n[0:0] 1'1 + assign $0\main_sdram_master_p0_ras_n[0:0] 1'1 + assign $0\main_sdram_master_p0_we_n[0:0] 1'1 + assign $0\main_sdram_master_p0_cke[0:0] 1'0 + assign $0\main_sdram_master_p0_odt[0:0] 1'0 + assign $0\main_sdram_master_p0_reset_n[0:0] 1'0 + assign $0\main_sdram_master_p0_act_n[0:0] 1'1 + assign $0\main_sdram_inti_p0_rddata[15:0] 16'0000000000000000 + assign $0\main_sdram_master_p0_wrdata[15:0] 16'0000000000000000 + assign $0\main_sdram_inti_p0_rddata_valid[0:0] 1'0 + assign $0\main_sdram_master_p0_wrdata_en[0:0] 1'0 + assign $0\main_sdram_master_p0_wrdata_mask[1:0] 2'00 + assign $0\main_sdram_master_p0_rddata_en[0:0] 1'0 + attribute \src "ls180.v:3207.2-3241.5" + switch \main_sdram_sel + attribute \src "ls180.v:3207.6-3207.20" + case 1'1 + assign $0\main_sdram_master_p0_address[12:0] \main_sdram_slave_p0_address + assign $0\main_sdram_master_p0_bank[1:0] \main_sdram_slave_p0_bank + assign $0\main_sdram_master_p0_cas_n[0:0] \main_sdram_slave_p0_cas_n + assign $0\main_sdram_master_p0_cs_n[0:0] \main_sdram_slave_p0_cs_n + assign $0\main_sdram_master_p0_ras_n[0:0] \main_sdram_slave_p0_ras_n + assign $0\main_sdram_master_p0_we_n[0:0] \main_sdram_slave_p0_we_n + assign $0\main_sdram_master_p0_cke[0:0] \main_sdram_slave_p0_cke + assign $0\main_sdram_master_p0_odt[0:0] \main_sdram_slave_p0_odt + assign $0\main_sdram_master_p0_reset_n[0:0] \main_sdram_slave_p0_reset_n + assign $0\main_sdram_master_p0_act_n[0:0] \main_sdram_slave_p0_act_n + assign $0\main_sdram_master_p0_wrdata[15:0] \main_sdram_slave_p0_wrdata + assign $0\main_sdram_master_p0_wrdata_en[0:0] \main_sdram_slave_p0_wrdata_en + assign $0\main_sdram_master_p0_wrdata_mask[1:0] \main_sdram_slave_p0_wrdata_mask + assign $0\main_sdram_master_p0_rddata_en[0:0] \main_sdram_slave_p0_rddata_en + assign $0\main_sdram_slave_p0_rddata[15:0] \main_sdram_master_p0_rddata + assign $0\main_sdram_slave_p0_rddata_valid[0:0] \main_sdram_master_p0_rddata_valid + attribute \src "ls180.v:3224.6-3224.10" + case + assign $0\main_sdram_master_p0_address[12:0] \main_sdram_inti_p0_address + assign $0\main_sdram_master_p0_bank[1:0] \main_sdram_inti_p0_bank + assign $0\main_sdram_master_p0_cas_n[0:0] \main_sdram_inti_p0_cas_n + assign $0\main_sdram_master_p0_cs_n[0:0] \main_sdram_inti_p0_cs_n + assign $0\main_sdram_master_p0_ras_n[0:0] \main_sdram_inti_p0_ras_n + assign $0\main_sdram_master_p0_we_n[0:0] \main_sdram_inti_p0_we_n + assign $0\main_sdram_master_p0_cke[0:0] \main_sdram_inti_p0_cke + assign $0\main_sdram_master_p0_odt[0:0] \main_sdram_inti_p0_odt + assign $0\main_sdram_master_p0_reset_n[0:0] \main_sdram_inti_p0_reset_n + assign $0\main_sdram_master_p0_act_n[0:0] \main_sdram_inti_p0_act_n + assign $0\main_sdram_master_p0_wrdata[15:0] \main_sdram_inti_p0_wrdata + assign $0\main_sdram_master_p0_wrdata_en[0:0] \main_sdram_inti_p0_wrdata_en + assign $0\main_sdram_master_p0_wrdata_mask[1:0] \main_sdram_inti_p0_wrdata_mask + assign $0\main_sdram_master_p0_rddata_en[0:0] \main_sdram_inti_p0_rddata_en + assign $0\main_sdram_inti_p0_rddata[15:0] \main_sdram_master_p0_rddata + assign $0\main_sdram_inti_p0_rddata_valid[0:0] \main_sdram_master_p0_rddata_valid + end + sync always + update \main_sdram_inti_p0_rddata $0\main_sdram_inti_p0_rddata[15:0] + update \main_sdram_inti_p0_rddata_valid $0\main_sdram_inti_p0_rddata_valid[0:0] + update \main_sdram_slave_p0_rddata $0\main_sdram_slave_p0_rddata[15:0] + update \main_sdram_slave_p0_rddata_valid $0\main_sdram_slave_p0_rddata_valid[0:0] + update \main_sdram_master_p0_address $0\main_sdram_master_p0_address[12:0] + update \main_sdram_master_p0_bank $0\main_sdram_master_p0_bank[1:0] + update \main_sdram_master_p0_cas_n $0\main_sdram_master_p0_cas_n[0:0] + update \main_sdram_master_p0_cs_n $0\main_sdram_master_p0_cs_n[0:0] + update \main_sdram_master_p0_ras_n $0\main_sdram_master_p0_ras_n[0:0] + update \main_sdram_master_p0_we_n $0\main_sdram_master_p0_we_n[0:0] + update \main_sdram_master_p0_cke $0\main_sdram_master_p0_cke[0:0] + update \main_sdram_master_p0_odt $0\main_sdram_master_p0_odt[0:0] + update \main_sdram_master_p0_reset_n $0\main_sdram_master_p0_reset_n[0:0] + update \main_sdram_master_p0_act_n $0\main_sdram_master_p0_act_n[0:0] + update \main_sdram_master_p0_wrdata $0\main_sdram_master_p0_wrdata[15:0] + update \main_sdram_master_p0_wrdata_en $0\main_sdram_master_p0_wrdata_en[0:0] + update \main_sdram_master_p0_wrdata_mask $0\main_sdram_master_p0_wrdata_mask[1:0] + update \main_sdram_master_p0_rddata_en $0\main_sdram_master_p0_rddata_en[0:0] + end + attribute \src "ls180.v:320.12-320.41" + process $proc$ls180.v:320$3184 + assign { } { } + assign $1\main_converter0_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \main_converter0_dat_r $1\main_converter0_dat_r[63:0] + end + attribute \src "ls180.v:3246.1-3262.4" + process $proc$ls180.v:3246$213 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdram_inti_p0_cas_n[0:0] 1'1 + assign $0\main_sdram_inti_p0_cs_n[0:0] 1'1 + assign $0\main_sdram_inti_p0_ras_n[0:0] 1'1 + assign $0\main_sdram_inti_p0_we_n[0:0] 1'1 + attribute \src "ls180.v:3251.2-3261.5" + switch \main_sdram_command_issue_re + attribute \src "ls180.v:3251.6-3251.33" + case 1'1 + assign $0\main_sdram_inti_p0_cs_n[0:0] $not$ls180.v:3252$214_Y + assign $0\main_sdram_inti_p0_we_n[0:0] $not$ls180.v:3253$215_Y + assign $0\main_sdram_inti_p0_cas_n[0:0] $not$ls180.v:3254$216_Y + assign $0\main_sdram_inti_p0_ras_n[0:0] $not$ls180.v:3255$217_Y + attribute \src "ls180.v:3256.6-3256.10" + case + assign $0\main_sdram_inti_p0_cs_n[0:0] 1'1 + assign $0\main_sdram_inti_p0_we_n[0:0] 1'1 + assign $0\main_sdram_inti_p0_cas_n[0:0] 1'1 + assign $0\main_sdram_inti_p0_ras_n[0:0] 1'1 + end + sync always + update \main_sdram_inti_p0_cas_n $0\main_sdram_inti_p0_cas_n[0:0] + update \main_sdram_inti_p0_cs_n $0\main_sdram_inti_p0_cs_n[0:0] + update \main_sdram_inti_p0_ras_n $0\main_sdram_inti_p0_ras_n[0:0] + update \main_sdram_inti_p0_we_n $0\main_sdram_inti_p0_we_n[0:0] + end + attribute \src "ls180.v:327.5-327.51" + process $proc$ls180.v:327$3185 + assign { } { } + assign $1\main_interface1_converted_interface_ack[0:0] 1'0 + sync always + sync init + update \main_interface1_converted_interface_ack $1\main_interface1_converted_interface_ack[0:0] + end + attribute \src "ls180.v:3305.1-3335.4" + process $proc$ls180.v:3305$226 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdram_cmd_last[0:0] 1'0 + assign $0\main_sdram_sequencer_start0[0:0] 1'0 + assign $0\main_sdram_cmd_valid[0:0] 1'0 + assign $0\builder_refresher_next_state[1:0] \builder_refresher_state + attribute \src "ls180.v:3311.2-3334.9" + switch \builder_refresher_state + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\main_sdram_cmd_valid[0:0] 1'1 + attribute \src "ls180.v:3314.4-3317.7" + switch \main_sdram_cmd_ready + attribute \src "ls180.v:3314.8-3314.28" + case 1'1 + assign $0\main_sdram_sequencer_start0[0:0] 1'1 + assign $0\builder_refresher_next_state[1:0] 2'10 + case + end + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\main_sdram_cmd_valid[0:0] 1'1 + attribute \src "ls180.v:3321.4-3325.7" + switch \main_sdram_sequencer_done0 + attribute \src "ls180.v:3321.8-3321.34" + case 1'1 + assign $0\main_sdram_cmd_valid[0:0] 1'0 + assign $0\main_sdram_cmd_last[0:0] 1'1 + assign $0\builder_refresher_next_state[1:0] 2'00 + case + end + attribute \src "ls180.v:0.0-0.0" + case + attribute \src "ls180.v:3328.4-3332.7" + switch 1'1 + attribute \src "ls180.v:3328.8-3328.12" + case 1'1 + attribute \src "ls180.v:3329.5-3331.8" + switch \main_sdram_wants_refresh + attribute \src "ls180.v:3329.9-3329.33" + case 1'1 + assign $0\builder_refresher_next_state[1:0] 2'01 + case + end + case + end + end + sync always + update \main_sdram_cmd_valid $0\main_sdram_cmd_valid[0:0] + update \main_sdram_cmd_last $0\main_sdram_cmd_last[0:0] + update \main_sdram_sequencer_start0 $0\main_sdram_sequencer_start0[0:0] + update \builder_refresher_next_state $0\builder_refresher_next_state[1:0] + end + attribute \src "ls180.v:331.5-331.51" + process $proc$ls180.v:331$3186 + assign { } { } + assign $0\main_interface1_converted_interface_err[0:0] 1'0 + sync always + update \main_interface1_converted_interface_err $0\main_interface1_converted_interface_err[0:0] + sync init + end + attribute \src "ls180.v:332.5-332.32" + process $proc$ls180.v:332$3187 + assign { } { } + assign $1\main_converter1_skip[0:0] 1'0 + sync always + sync init + update \main_converter1_skip $1\main_converter1_skip[0:0] + end + attribute \src "ls180.v:333.5-333.35" + process $proc$ls180.v:333$3188 + assign { } { } + assign $1\main_converter1_counter[0:0] 1'0 + sync always + sync init + update \main_converter1_counter $1\main_converter1_counter[0:0] + end + attribute \src "ls180.v:335.12-335.41" + process $proc$ls180.v:335$3189 + assign { } { } + assign $1\main_converter1_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \main_converter1_dat_r $1\main_converter1_dat_r[63:0] + end + attribute \src "ls180.v:3350.1-3357.4" + process $proc$ls180.v:3350$230 + assign { } { } + assign $0\main_sdram_bankmachine0_cmd_payload_a[12:0] 13'0000000000000 + attribute \src "ls180.v:3352.2-3356.5" + switch \main_sdram_bankmachine0_row_col_n_addr_sel + attribute \src "ls180.v:3352.6-3352.48" + case 1'1 + assign $0\main_sdram_bankmachine0_cmd_payload_a[12:0] \main_sdram_bankmachine0_cmd_buffer_source_payload_addr [21:9] + attribute \src "ls180.v:3354.6-3354.10" + case + assign $0\main_sdram_bankmachine0_cmd_payload_a[12:0] $or$ls180.v:3355$232_Y + end + sync always + update \main_sdram_bankmachine0_cmd_payload_a $0\main_sdram_bankmachine0_cmd_payload_a[12:0] + end + attribute \src "ls180.v:3361.1-3368.4" + process $proc$ls180.v:3361$239 + assign { } { } + assign $0\main_sdram_bankmachine0_auto_precharge[0:0] 1'0 + attribute \src "ls180.v:3363.2-3367.5" + switch $and$ls180.v:3363$240_Y + attribute \src "ls180.v:3363.6-3363.115" + case 1'1 + attribute \src "ls180.v:3364.3-3366.6" + switch $ne$ls180.v:3364$241_Y + attribute \src "ls180.v:3364.7-3364.143" + case 1'1 + assign $0\main_sdram_bankmachine0_auto_precharge[0:0] $eq$ls180.v:3365$242_Y + case + end + case + end + sync always + update \main_sdram_bankmachine0_auto_precharge $0\main_sdram_bankmachine0_auto_precharge[0:0] + end + attribute \src "ls180.v:3383.1-3390.4" + process $proc$ls180.v:3383$243 + assign { } { } + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 + attribute \src "ls180.v:3385.2-3389.5" + switch \main_sdram_bankmachine0_cmd_buffer_lookahead_replace + attribute \src "ls180.v:3385.6-3385.58" + case 1'1 + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:3386$244_Y + attribute \src "ls180.v:3387.6-3387.10" + case + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] \main_sdram_bankmachine0_cmd_buffer_lookahead_produce + end + sync always + update \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr $0\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] + end + attribute \src "ls180.v:339.5-339.24" + process $proc$ls180.v:339$3190 + assign { } { } + assign $1\main_int_rst[0:0] 1'1 + sync always + sync init + update \main_int_rst $1\main_int_rst[0:0] + end + attribute \src "ls180.v:3399.1-3492.4" + process $proc$ls180.v:3399$252 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdram_bankmachine0_row_open[0:0] 1'0 + assign $0\main_sdram_bankmachine0_row_close[0:0] 1'0 + assign $0\main_sdram_bankmachine0_cmd_payload_cas[0:0] 1'0 + assign $0\main_sdram_bankmachine0_cmd_payload_ras[0:0] 1'0 + assign $0\main_sdram_bankmachine0_cmd_payload_we[0:0] 1'0 + assign $0\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] 1'0 + assign $0\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'0 + assign { } { } + assign $0\main_sdram_bankmachine0_cmd_payload_is_read[0:0] 1'0 + assign $0\main_sdram_bankmachine0_cmd_payload_is_write[0:0] 1'0 + assign $0\main_sdram_bankmachine0_req_wdata_ready[0:0] 1'0 + assign $0\main_sdram_bankmachine0_req_rdata_valid[0:0] 1'0 + assign $0\main_sdram_bankmachine0_refresh_gnt[0:0] 1'0 + assign $0\main_sdram_bankmachine0_cmd_valid[0:0] 1'0 + assign $0\builder_bankmachine0_next_state[2:0] \builder_bankmachine0_state + attribute \src "ls180.v:3415.2-3491.9" + switch \builder_bankmachine0_state + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\main_sdram_bankmachine0_row_close[0:0] 1'1 + attribute \src "ls180.v:3417.4-3425.7" + switch $and$ls180.v:3417$253_Y + attribute \src "ls180.v:3417.8-3417.87" + case 1'1 + assign $0\main_sdram_bankmachine0_cmd_valid[0:0] 1'1 + assign $0\main_sdram_bankmachine0_cmd_payload_ras[0:0] 1'1 + assign $0\main_sdram_bankmachine0_cmd_payload_we[0:0] 1'1 + assign $0\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'1 + attribute \src "ls180.v:3419.5-3421.8" + switch \main_sdram_bankmachine0_cmd_ready + attribute \src "ls180.v:3419.9-3419.42" + case 1'1 + assign $0\builder_bankmachine0_next_state[2:0] 3'101 + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\main_sdram_bankmachine0_row_close[0:0] 1'1 + attribute \src "ls180.v:3429.4-3431.7" + switch $and$ls180.v:3429$254_Y + attribute \src "ls180.v:3429.8-3429.87" + case 1'1 + assign $0\builder_bankmachine0_next_state[2:0] 3'101 + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'011 + attribute \src "ls180.v:3435.4-3444.7" + switch \main_sdram_bankmachine0_trccon_ready + attribute \src "ls180.v:3435.8-3435.44" + case 1'1 + assign $0\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] 1'1 + assign $0\main_sdram_bankmachine0_row_open[0:0] 1'1 + assign $0\main_sdram_bankmachine0_cmd_valid[0:0] 1'1 + assign $0\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'1 + assign $0\main_sdram_bankmachine0_cmd_payload_ras[0:0] 1'1 + attribute \src "ls180.v:3440.5-3442.8" + switch \main_sdram_bankmachine0_cmd_ready + attribute \src "ls180.v:3440.9-3440.42" + case 1'1 + assign $0\builder_bankmachine0_next_state[2:0] 3'110 + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\main_sdram_bankmachine0_row_close[0:0] 1'1 + assign $0\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'1 + attribute \src "ls180.v:3447.4-3449.7" + switch \main_sdram_bankmachine0_twtpcon_ready + attribute \src "ls180.v:3447.8-3447.45" + case 1'1 + assign $0\main_sdram_bankmachine0_refresh_gnt[0:0] 1'1 + case + end + attribute \src "ls180.v:3452.4-3454.7" + switch $not$ls180.v:3452$255_Y + attribute \src "ls180.v:3452.8-3452.46" + case 1'1 + assign $0\builder_bankmachine0_next_state[2:0] 3'000 + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'101 + assign $0\builder_bankmachine0_next_state[2:0] 3'011 + attribute \src "ls180.v:0.0-0.0" + case 3'110 + assign $0\builder_bankmachine0_next_state[2:0] 3'000 + attribute \src "ls180.v:0.0-0.0" + case + attribute \src "ls180.v:3463.4-3489.7" + switch \main_sdram_bankmachine0_refresh_req + attribute \src "ls180.v:3463.8-3463.43" + case 1'1 + assign $0\builder_bankmachine0_next_state[2:0] 3'100 + attribute \src "ls180.v:3465.8-3465.12" + case + attribute \src "ls180.v:3466.5-3488.8" + switch \main_sdram_bankmachine0_cmd_buffer_source_valid + attribute \src "ls180.v:3466.9-3466.56" + case 1'1 + attribute \src "ls180.v:3467.6-3487.9" + switch \main_sdram_bankmachine0_row_opened + attribute \src "ls180.v:3467.10-3467.44" + case 1'1 + attribute \src "ls180.v:3468.7-3484.10" + switch \main_sdram_bankmachine0_row_hit + attribute \src "ls180.v:3468.11-3468.42" + case 1'1 + assign $0\main_sdram_bankmachine0_cmd_valid[0:0] 1'1 + assign $0\main_sdram_bankmachine0_cmd_payload_cas[0:0] 1'1 + attribute \src "ls180.v:3470.8-3477.11" + switch \main_sdram_bankmachine0_cmd_buffer_source_payload_we + attribute \src "ls180.v:3470.12-3470.64" + case 1'1 + assign $0\main_sdram_bankmachine0_req_wdata_ready[0:0] \main_sdram_bankmachine0_cmd_ready + assign $0\main_sdram_bankmachine0_cmd_payload_is_write[0:0] 1'1 + assign $0\main_sdram_bankmachine0_cmd_payload_we[0:0] 1'1 + attribute \src "ls180.v:3474.12-3474.16" + case + assign $0\main_sdram_bankmachine0_req_rdata_valid[0:0] \main_sdram_bankmachine0_cmd_ready + assign $0\main_sdram_bankmachine0_cmd_payload_is_read[0:0] 1'1 + end + attribute \src "ls180.v:3479.8-3481.11" + switch $and$ls180.v:3479$256_Y + attribute \src "ls180.v:3479.12-3479.88" + case 1'1 + assign $0\builder_bankmachine0_next_state[2:0] 3'010 + case + end + attribute \src "ls180.v:3482.11-3482.15" + case + assign $0\builder_bankmachine0_next_state[2:0] 3'001 + end + attribute \src "ls180.v:3485.10-3485.14" + case + assign $0\builder_bankmachine0_next_state[2:0] 3'011 + end + case + end + end + end + sync always + update \main_sdram_bankmachine0_req_wdata_ready $0\main_sdram_bankmachine0_req_wdata_ready[0:0] + update \main_sdram_bankmachine0_req_rdata_valid $0\main_sdram_bankmachine0_req_rdata_valid[0:0] + update \main_sdram_bankmachine0_refresh_gnt $0\main_sdram_bankmachine0_refresh_gnt[0:0] + update \main_sdram_bankmachine0_cmd_valid $0\main_sdram_bankmachine0_cmd_valid[0:0] + update \main_sdram_bankmachine0_cmd_payload_cas $0\main_sdram_bankmachine0_cmd_payload_cas[0:0] + update \main_sdram_bankmachine0_cmd_payload_ras $0\main_sdram_bankmachine0_cmd_payload_ras[0:0] + update \main_sdram_bankmachine0_cmd_payload_we $0\main_sdram_bankmachine0_cmd_payload_we[0:0] + update \main_sdram_bankmachine0_cmd_payload_is_cmd $0\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] + update \main_sdram_bankmachine0_cmd_payload_is_read $0\main_sdram_bankmachine0_cmd_payload_is_read[0:0] + update \main_sdram_bankmachine0_cmd_payload_is_write $0\main_sdram_bankmachine0_cmd_payload_is_write[0:0] + update \main_sdram_bankmachine0_row_open $0\main_sdram_bankmachine0_row_open[0:0] + update \main_sdram_bankmachine0_row_close $0\main_sdram_bankmachine0_row_close[0:0] + update \main_sdram_bankmachine0_row_col_n_addr_sel $0\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] + update \builder_bankmachine0_next_state $0\builder_bankmachine0_next_state[2:0] + end + attribute \src "ls180.v:3507.1-3514.4" + process $proc$ls180.v:3507$260 + assign { } { } + assign $0\main_sdram_bankmachine1_cmd_payload_a[12:0] 13'0000000000000 + attribute \src "ls180.v:3509.2-3513.5" + switch \main_sdram_bankmachine1_row_col_n_addr_sel + attribute \src "ls180.v:3509.6-3509.48" + case 1'1 + assign $0\main_sdram_bankmachine1_cmd_payload_a[12:0] \main_sdram_bankmachine1_cmd_buffer_source_payload_addr [21:9] + attribute \src "ls180.v:3511.6-3511.10" + case + assign $0\main_sdram_bankmachine1_cmd_payload_a[12:0] $or$ls180.v:3512$262_Y + end + sync always + update \main_sdram_bankmachine1_cmd_payload_a $0\main_sdram_bankmachine1_cmd_payload_a[12:0] + end + attribute \src "ls180.v:3518.1-3525.4" + process $proc$ls180.v:3518$269 + assign { } { } + assign $0\main_sdram_bankmachine1_auto_precharge[0:0] 1'0 + attribute \src "ls180.v:3520.2-3524.5" + switch $and$ls180.v:3520$270_Y + attribute \src "ls180.v:3520.6-3520.115" + case 1'1 + attribute \src "ls180.v:3521.3-3523.6" + switch $ne$ls180.v:3521$271_Y + attribute \src "ls180.v:3521.7-3521.143" + case 1'1 + assign $0\main_sdram_bankmachine1_auto_precharge[0:0] $eq$ls180.v:3522$272_Y + case + end + case + end + sync always + update \main_sdram_bankmachine1_auto_precharge $0\main_sdram_bankmachine1_auto_precharge[0:0] + end + attribute \src "ls180.v:354.12-354.38" + process $proc$ls180.v:354$3191 + assign { } { } + assign $1\main_dfi_p0_rddata[15:0] 16'0000000000000000 + sync always + sync init + update \main_dfi_p0_rddata $1\main_dfi_p0_rddata[15:0] + end + attribute \src "ls180.v:3540.1-3547.4" + process $proc$ls180.v:3540$273 + assign { } { } + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 + attribute \src "ls180.v:3542.2-3546.5" + switch \main_sdram_bankmachine1_cmd_buffer_lookahead_replace + attribute \src "ls180.v:3542.6-3542.58" + case 1'1 + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:3543$274_Y + attribute \src "ls180.v:3544.6-3544.10" + case + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] \main_sdram_bankmachine1_cmd_buffer_lookahead_produce + end + sync always + update \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr $0\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] + end + attribute \src "ls180.v:355.5-355.36" + process $proc$ls180.v:355$3192 + assign { } { } + assign $1\main_dfi_p0_rddata_valid[0:0] 1'0 + sync always + sync init + update \main_dfi_p0_rddata_valid $1\main_dfi_p0_rddata_valid[0:0] + end + attribute \src "ls180.v:3556.1-3649.4" + process $proc$ls180.v:3556$282 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdram_bankmachine1_refresh_gnt[0:0] 1'0 + assign $0\main_sdram_bankmachine1_cmd_valid[0:0] 1'0 + assign $0\main_sdram_bankmachine1_row_open[0:0] 1'0 + assign { } { } + assign $0\main_sdram_bankmachine1_row_close[0:0] 1'0 + assign $0\main_sdram_bankmachine1_cmd_payload_cas[0:0] 1'0 + assign $0\main_sdram_bankmachine1_cmd_payload_ras[0:0] 1'0 + assign $0\main_sdram_bankmachine1_cmd_payload_we[0:0] 1'0 + assign $0\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] 1'0 + assign $0\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'0 + assign $0\main_sdram_bankmachine1_cmd_payload_is_read[0:0] 1'0 + assign $0\main_sdram_bankmachine1_cmd_payload_is_write[0:0] 1'0 + assign $0\main_sdram_bankmachine1_req_wdata_ready[0:0] 1'0 + assign $0\main_sdram_bankmachine1_req_rdata_valid[0:0] 1'0 + assign $0\builder_bankmachine1_next_state[2:0] \builder_bankmachine1_state + attribute \src "ls180.v:3572.2-3648.9" + switch \builder_bankmachine1_state + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\main_sdram_bankmachine1_row_close[0:0] 1'1 + attribute \src "ls180.v:3574.4-3582.7" + switch $and$ls180.v:3574$283_Y + attribute \src "ls180.v:3574.8-3574.87" + case 1'1 + assign $0\main_sdram_bankmachine1_cmd_valid[0:0] 1'1 + assign $0\main_sdram_bankmachine1_cmd_payload_ras[0:0] 1'1 + assign $0\main_sdram_bankmachine1_cmd_payload_we[0:0] 1'1 + assign $0\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'1 + attribute \src "ls180.v:3576.5-3578.8" + switch \main_sdram_bankmachine1_cmd_ready + attribute \src "ls180.v:3576.9-3576.42" + case 1'1 + assign $0\builder_bankmachine1_next_state[2:0] 3'101 + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\main_sdram_bankmachine1_row_close[0:0] 1'1 + attribute \src "ls180.v:3586.4-3588.7" + switch $and$ls180.v:3586$284_Y + attribute \src "ls180.v:3586.8-3586.87" + case 1'1 + assign $0\builder_bankmachine1_next_state[2:0] 3'101 + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'011 + attribute \src "ls180.v:3592.4-3601.7" + switch \main_sdram_bankmachine1_trccon_ready + attribute \src "ls180.v:3592.8-3592.44" + case 1'1 + assign $0\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] 1'1 + assign $0\main_sdram_bankmachine1_row_open[0:0] 1'1 + assign $0\main_sdram_bankmachine1_cmd_valid[0:0] 1'1 + assign $0\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'1 + assign $0\main_sdram_bankmachine1_cmd_payload_ras[0:0] 1'1 + attribute \src "ls180.v:3597.5-3599.8" + switch \main_sdram_bankmachine1_cmd_ready + attribute \src "ls180.v:3597.9-3597.42" + case 1'1 + assign $0\builder_bankmachine1_next_state[2:0] 3'110 + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\main_sdram_bankmachine1_row_close[0:0] 1'1 + assign $0\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'1 + attribute \src "ls180.v:3604.4-3606.7" + switch \main_sdram_bankmachine1_twtpcon_ready + attribute \src "ls180.v:3604.8-3604.45" + case 1'1 + assign $0\main_sdram_bankmachine1_refresh_gnt[0:0] 1'1 + case + end + attribute \src "ls180.v:3609.4-3611.7" + switch $not$ls180.v:3609$285_Y + attribute \src "ls180.v:3609.8-3609.46" + case 1'1 + assign $0\builder_bankmachine1_next_state[2:0] 3'000 + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'101 + assign $0\builder_bankmachine1_next_state[2:0] 3'011 + attribute \src "ls180.v:0.0-0.0" + case 3'110 + assign $0\builder_bankmachine1_next_state[2:0] 3'000 + attribute \src "ls180.v:0.0-0.0" + case + attribute \src "ls180.v:3620.4-3646.7" + switch \main_sdram_bankmachine1_refresh_req + attribute \src "ls180.v:3620.8-3620.43" + case 1'1 + assign $0\builder_bankmachine1_next_state[2:0] 3'100 + attribute \src "ls180.v:3622.8-3622.12" + case + attribute \src "ls180.v:3623.5-3645.8" + switch \main_sdram_bankmachine1_cmd_buffer_source_valid + attribute \src "ls180.v:3623.9-3623.56" + case 1'1 + attribute \src "ls180.v:3624.6-3644.9" + switch \main_sdram_bankmachine1_row_opened + attribute \src "ls180.v:3624.10-3624.44" + case 1'1 + attribute \src "ls180.v:3625.7-3641.10" + switch \main_sdram_bankmachine1_row_hit + attribute \src "ls180.v:3625.11-3625.42" + case 1'1 + assign $0\main_sdram_bankmachine1_cmd_valid[0:0] 1'1 + assign $0\main_sdram_bankmachine1_cmd_payload_cas[0:0] 1'1 + attribute \src "ls180.v:3627.8-3634.11" + switch \main_sdram_bankmachine1_cmd_buffer_source_payload_we + attribute \src "ls180.v:3627.12-3627.64" + case 1'1 + assign $0\main_sdram_bankmachine1_req_wdata_ready[0:0] \main_sdram_bankmachine1_cmd_ready + assign $0\main_sdram_bankmachine1_cmd_payload_is_write[0:0] 1'1 + assign $0\main_sdram_bankmachine1_cmd_payload_we[0:0] 1'1 + attribute \src "ls180.v:3631.12-3631.16" + case + assign $0\main_sdram_bankmachine1_req_rdata_valid[0:0] \main_sdram_bankmachine1_cmd_ready + assign $0\main_sdram_bankmachine1_cmd_payload_is_read[0:0] 1'1 + end + attribute \src "ls180.v:3636.8-3638.11" + switch $and$ls180.v:3636$286_Y + attribute \src "ls180.v:3636.12-3636.88" + case 1'1 + assign $0\builder_bankmachine1_next_state[2:0] 3'010 + case + end + attribute \src "ls180.v:3639.11-3639.15" + case + assign $0\builder_bankmachine1_next_state[2:0] 3'001 + end + attribute \src "ls180.v:3642.10-3642.14" + case + assign $0\builder_bankmachine1_next_state[2:0] 3'011 + end + case + end + end + end + sync always + update \main_sdram_bankmachine1_req_wdata_ready $0\main_sdram_bankmachine1_req_wdata_ready[0:0] + update \main_sdram_bankmachine1_req_rdata_valid $0\main_sdram_bankmachine1_req_rdata_valid[0:0] + update \main_sdram_bankmachine1_refresh_gnt $0\main_sdram_bankmachine1_refresh_gnt[0:0] + update \main_sdram_bankmachine1_cmd_valid $0\main_sdram_bankmachine1_cmd_valid[0:0] + update \main_sdram_bankmachine1_cmd_payload_cas $0\main_sdram_bankmachine1_cmd_payload_cas[0:0] + update \main_sdram_bankmachine1_cmd_payload_ras $0\main_sdram_bankmachine1_cmd_payload_ras[0:0] + update \main_sdram_bankmachine1_cmd_payload_we $0\main_sdram_bankmachine1_cmd_payload_we[0:0] + update \main_sdram_bankmachine1_cmd_payload_is_cmd $0\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] + update \main_sdram_bankmachine1_cmd_payload_is_read $0\main_sdram_bankmachine1_cmd_payload_is_read[0:0] + update \main_sdram_bankmachine1_cmd_payload_is_write $0\main_sdram_bankmachine1_cmd_payload_is_write[0:0] + update \main_sdram_bankmachine1_row_open $0\main_sdram_bankmachine1_row_open[0:0] + update \main_sdram_bankmachine1_row_close $0\main_sdram_bankmachine1_row_close[0:0] + update \main_sdram_bankmachine1_row_col_n_addr_sel $0\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] + update \builder_bankmachine1_next_state $0\builder_bankmachine1_next_state[2:0] + end + attribute \src "ls180.v:356.11-356.32" + process $proc$ls180.v:356$3193 + assign { } { } + assign $1\main_rddata_en[2:0] 3'000 + sync always + sync init + update \main_rddata_en $1\main_rddata_en[2:0] + end + attribute \src "ls180.v:359.5-359.36" + process $proc$ls180.v:359$3194 + assign { } { } + assign $1\main_sdram_inti_p0_cas_n[0:0] 1'1 + sync always + sync init + update \main_sdram_inti_p0_cas_n $1\main_sdram_inti_p0_cas_n[0:0] + end + attribute \src "ls180.v:360.5-360.35" + process $proc$ls180.v:360$3195 + assign { } { } + assign $1\main_sdram_inti_p0_cs_n[0:0] 1'1 + sync always + sync init + update \main_sdram_inti_p0_cs_n $1\main_sdram_inti_p0_cs_n[0:0] + end + attribute \src "ls180.v:361.5-361.36" + process $proc$ls180.v:361$3196 + assign { } { } + assign $1\main_sdram_inti_p0_ras_n[0:0] 1'1 + sync always + sync init + update \main_sdram_inti_p0_ras_n $1\main_sdram_inti_p0_ras_n[0:0] + end + attribute \src "ls180.v:362.5-362.35" + process $proc$ls180.v:362$3197 + assign { } { } + assign $1\main_sdram_inti_p0_we_n[0:0] 1'1 + sync always + sync init + update \main_sdram_inti_p0_we_n $1\main_sdram_inti_p0_we_n[0:0] + end + attribute \src "ls180.v:366.5-366.36" + process $proc$ls180.v:366$3198 + assign { } { } + assign $0\main_sdram_inti_p0_act_n[0:0] 1'1 + sync always + update \main_sdram_inti_p0_act_n $0\main_sdram_inti_p0_act_n[0:0] + sync init + end + attribute \src "ls180.v:3664.1-3671.4" + process $proc$ls180.v:3664$290 + assign { } { } + assign $0\main_sdram_bankmachine2_cmd_payload_a[12:0] 13'0000000000000 + attribute \src "ls180.v:3666.2-3670.5" + switch \main_sdram_bankmachine2_row_col_n_addr_sel + attribute \src "ls180.v:3666.6-3666.48" + case 1'1 + assign $0\main_sdram_bankmachine2_cmd_payload_a[12:0] \main_sdram_bankmachine2_cmd_buffer_source_payload_addr [21:9] + attribute \src "ls180.v:3668.6-3668.10" + case + assign $0\main_sdram_bankmachine2_cmd_payload_a[12:0] $or$ls180.v:3669$292_Y + end + sync always + update \main_sdram_bankmachine2_cmd_payload_a $0\main_sdram_bankmachine2_cmd_payload_a[12:0] + end + attribute \src "ls180.v:3675.1-3682.4" + process $proc$ls180.v:3675$299 + assign { } { } + assign $0\main_sdram_bankmachine2_auto_precharge[0:0] 1'0 + attribute \src "ls180.v:3677.2-3681.5" + switch $and$ls180.v:3677$300_Y + attribute \src "ls180.v:3677.6-3677.115" + case 1'1 + attribute \src "ls180.v:3678.3-3680.6" + switch $ne$ls180.v:3678$301_Y + attribute \src "ls180.v:3678.7-3678.143" + case 1'1 + assign $0\main_sdram_bankmachine2_auto_precharge[0:0] $eq$ls180.v:3679$302_Y + case + end + case + end + sync always + update \main_sdram_bankmachine2_auto_precharge $0\main_sdram_bankmachine2_auto_precharge[0:0] + end + attribute \src "ls180.v:3697.1-3704.4" + process $proc$ls180.v:3697$303 + assign { } { } + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 + attribute \src "ls180.v:3699.2-3703.5" + switch \main_sdram_bankmachine2_cmd_buffer_lookahead_replace + attribute \src "ls180.v:3699.6-3699.58" + case 1'1 + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:3700$304_Y + attribute \src "ls180.v:3701.6-3701.10" + case + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] \main_sdram_bankmachine2_cmd_buffer_lookahead_produce + end + sync always + update \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr $0\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] + end + attribute \src "ls180.v:371.12-371.45" + process $proc$ls180.v:371$3199 + assign { } { } + assign $1\main_sdram_inti_p0_rddata[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdram_inti_p0_rddata $1\main_sdram_inti_p0_rddata[15:0] + end + attribute \src "ls180.v:3713.1-3806.4" + process $proc$ls180.v:3713$312 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdram_bankmachine2_cmd_payload_is_write[0:0] 1'0 + assign $0\main_sdram_bankmachine2_req_wdata_ready[0:0] 1'0 + assign $0\main_sdram_bankmachine2_req_rdata_valid[0:0] 1'0 + assign { } { } + assign $0\main_sdram_bankmachine2_refresh_gnt[0:0] 1'0 + assign $0\main_sdram_bankmachine2_cmd_valid[0:0] 1'0 + assign $0\main_sdram_bankmachine2_row_open[0:0] 1'0 + assign $0\main_sdram_bankmachine2_row_close[0:0] 1'0 + assign $0\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] 1'0 + assign $0\main_sdram_bankmachine2_cmd_payload_cas[0:0] 1'0 + assign $0\main_sdram_bankmachine2_cmd_payload_ras[0:0] 1'0 + assign $0\main_sdram_bankmachine2_cmd_payload_we[0:0] 1'0 + assign $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'0 + assign $0\main_sdram_bankmachine2_cmd_payload_is_read[0:0] 1'0 + assign $0\builder_bankmachine2_next_state[2:0] \builder_bankmachine2_state + attribute \src "ls180.v:3729.2-3805.9" + switch \builder_bankmachine2_state + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\main_sdram_bankmachine2_row_close[0:0] 1'1 + attribute \src "ls180.v:3731.4-3739.7" + switch $and$ls180.v:3731$313_Y + attribute \src "ls180.v:3731.8-3731.87" + case 1'1 + assign $0\main_sdram_bankmachine2_cmd_valid[0:0] 1'1 + assign $0\main_sdram_bankmachine2_cmd_payload_ras[0:0] 1'1 + assign $0\main_sdram_bankmachine2_cmd_payload_we[0:0] 1'1 + assign $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'1 + attribute \src "ls180.v:3733.5-3735.8" + switch \main_sdram_bankmachine2_cmd_ready + attribute \src "ls180.v:3733.9-3733.42" + case 1'1 + assign $0\builder_bankmachine2_next_state[2:0] 3'101 + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\main_sdram_bankmachine2_row_close[0:0] 1'1 + attribute \src "ls180.v:3743.4-3745.7" + switch $and$ls180.v:3743$314_Y + attribute \src "ls180.v:3743.8-3743.87" + case 1'1 + assign $0\builder_bankmachine2_next_state[2:0] 3'101 + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'011 + attribute \src "ls180.v:3749.4-3758.7" + switch \main_sdram_bankmachine2_trccon_ready + attribute \src "ls180.v:3749.8-3749.44" + case 1'1 + assign $0\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] 1'1 + assign $0\main_sdram_bankmachine2_row_open[0:0] 1'1 + assign $0\main_sdram_bankmachine2_cmd_valid[0:0] 1'1 + assign $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'1 + assign $0\main_sdram_bankmachine2_cmd_payload_ras[0:0] 1'1 + attribute \src "ls180.v:3754.5-3756.8" + switch \main_sdram_bankmachine2_cmd_ready + attribute \src "ls180.v:3754.9-3754.42" + case 1'1 + assign $0\builder_bankmachine2_next_state[2:0] 3'110 + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\main_sdram_bankmachine2_row_close[0:0] 1'1 + assign $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'1 + attribute \src "ls180.v:3761.4-3763.7" + switch \main_sdram_bankmachine2_twtpcon_ready + attribute \src "ls180.v:3761.8-3761.45" + case 1'1 + assign $0\main_sdram_bankmachine2_refresh_gnt[0:0] 1'1 + case + end + attribute \src "ls180.v:3766.4-3768.7" + switch $not$ls180.v:3766$315_Y + attribute \src "ls180.v:3766.8-3766.46" + case 1'1 + assign $0\builder_bankmachine2_next_state[2:0] 3'000 + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'101 + assign $0\builder_bankmachine2_next_state[2:0] 3'011 + attribute \src "ls180.v:0.0-0.0" + case 3'110 + assign $0\builder_bankmachine2_next_state[2:0] 3'000 + attribute \src "ls180.v:0.0-0.0" + case + attribute \src "ls180.v:3777.4-3803.7" + switch \main_sdram_bankmachine2_refresh_req + attribute \src "ls180.v:3777.8-3777.43" + case 1'1 + assign $0\builder_bankmachine2_next_state[2:0] 3'100 + attribute \src "ls180.v:3779.8-3779.12" + case + attribute \src "ls180.v:3780.5-3802.8" + switch \main_sdram_bankmachine2_cmd_buffer_source_valid + attribute \src "ls180.v:3780.9-3780.56" + case 1'1 + attribute \src "ls180.v:3781.6-3801.9" + switch \main_sdram_bankmachine2_row_opened + attribute \src "ls180.v:3781.10-3781.44" + case 1'1 + attribute \src "ls180.v:3782.7-3798.10" + switch \main_sdram_bankmachine2_row_hit + attribute \src "ls180.v:3782.11-3782.42" + case 1'1 + assign $0\main_sdram_bankmachine2_cmd_valid[0:0] 1'1 + assign $0\main_sdram_bankmachine2_cmd_payload_cas[0:0] 1'1 + attribute \src "ls180.v:3784.8-3791.11" + switch \main_sdram_bankmachine2_cmd_buffer_source_payload_we + attribute \src "ls180.v:3784.12-3784.64" + case 1'1 + assign $0\main_sdram_bankmachine2_req_wdata_ready[0:0] \main_sdram_bankmachine2_cmd_ready + assign $0\main_sdram_bankmachine2_cmd_payload_is_write[0:0] 1'1 + assign $0\main_sdram_bankmachine2_cmd_payload_we[0:0] 1'1 + attribute \src "ls180.v:3788.12-3788.16" + case + assign $0\main_sdram_bankmachine2_req_rdata_valid[0:0] \main_sdram_bankmachine2_cmd_ready + assign $0\main_sdram_bankmachine2_cmd_payload_is_read[0:0] 1'1 + end + attribute \src "ls180.v:3793.8-3795.11" + switch $and$ls180.v:3793$316_Y + attribute \src "ls180.v:3793.12-3793.88" + case 1'1 + assign $0\builder_bankmachine2_next_state[2:0] 3'010 + case + end + attribute \src "ls180.v:3796.11-3796.15" + case + assign $0\builder_bankmachine2_next_state[2:0] 3'001 + end + attribute \src "ls180.v:3799.10-3799.14" + case + assign $0\builder_bankmachine2_next_state[2:0] 3'011 + end + case + end + end + end + sync always + update \main_sdram_bankmachine2_req_wdata_ready $0\main_sdram_bankmachine2_req_wdata_ready[0:0] + update \main_sdram_bankmachine2_req_rdata_valid $0\main_sdram_bankmachine2_req_rdata_valid[0:0] + update \main_sdram_bankmachine2_refresh_gnt $0\main_sdram_bankmachine2_refresh_gnt[0:0] + update \main_sdram_bankmachine2_cmd_valid $0\main_sdram_bankmachine2_cmd_valid[0:0] + update \main_sdram_bankmachine2_cmd_payload_cas $0\main_sdram_bankmachine2_cmd_payload_cas[0:0] + update \main_sdram_bankmachine2_cmd_payload_ras $0\main_sdram_bankmachine2_cmd_payload_ras[0:0] + update \main_sdram_bankmachine2_cmd_payload_we $0\main_sdram_bankmachine2_cmd_payload_we[0:0] + update \main_sdram_bankmachine2_cmd_payload_is_cmd $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] + update \main_sdram_bankmachine2_cmd_payload_is_read $0\main_sdram_bankmachine2_cmd_payload_is_read[0:0] + update \main_sdram_bankmachine2_cmd_payload_is_write $0\main_sdram_bankmachine2_cmd_payload_is_write[0:0] + update \main_sdram_bankmachine2_row_open $0\main_sdram_bankmachine2_row_open[0:0] + update \main_sdram_bankmachine2_row_close $0\main_sdram_bankmachine2_row_close[0:0] + update \main_sdram_bankmachine2_row_col_n_addr_sel $0\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] + update \builder_bankmachine2_next_state $0\builder_bankmachine2_next_state[2:0] + end + attribute \src "ls180.v:372.5-372.43" + process $proc$ls180.v:372$3200 + assign { } { } + assign $1\main_sdram_inti_p0_rddata_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_inti_p0_rddata_valid $1\main_sdram_inti_p0_rddata_valid[0:0] + end + attribute \src "ls180.v:3821.1-3828.4" + process $proc$ls180.v:3821$320 + assign { } { } + assign $0\main_sdram_bankmachine3_cmd_payload_a[12:0] 13'0000000000000 + attribute \src "ls180.v:3823.2-3827.5" + switch \main_sdram_bankmachine3_row_col_n_addr_sel + attribute \src "ls180.v:3823.6-3823.48" + case 1'1 + assign $0\main_sdram_bankmachine3_cmd_payload_a[12:0] \main_sdram_bankmachine3_cmd_buffer_source_payload_addr [21:9] + attribute \src "ls180.v:3825.6-3825.10" + case + assign $0\main_sdram_bankmachine3_cmd_payload_a[12:0] $or$ls180.v:3826$322_Y + end + sync always + update \main_sdram_bankmachine3_cmd_payload_a $0\main_sdram_bankmachine3_cmd_payload_a[12:0] + end + attribute \src "ls180.v:3832.1-3839.4" + process $proc$ls180.v:3832$329 + assign { } { } + assign $0\main_sdram_bankmachine3_auto_precharge[0:0] 1'0 + attribute \src "ls180.v:3834.2-3838.5" + switch $and$ls180.v:3834$330_Y + attribute \src "ls180.v:3834.6-3834.115" + case 1'1 + attribute \src "ls180.v:3835.3-3837.6" + switch $ne$ls180.v:3835$331_Y + attribute \src "ls180.v:3835.7-3835.143" + case 1'1 + assign $0\main_sdram_bankmachine3_auto_precharge[0:0] $eq$ls180.v:3836$332_Y + case + end + case + end + sync always + update \main_sdram_bankmachine3_auto_precharge $0\main_sdram_bankmachine3_auto_precharge[0:0] + end + attribute \src "ls180.v:3854.1-3861.4" + process $proc$ls180.v:3854$333 + assign { } { } + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 + attribute \src "ls180.v:3856.2-3860.5" + switch \main_sdram_bankmachine3_cmd_buffer_lookahead_replace + attribute \src "ls180.v:3856.6-3856.58" + case 1'1 + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:3857$334_Y + attribute \src "ls180.v:3858.6-3858.10" + case + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] \main_sdram_bankmachine3_cmd_buffer_lookahead_produce + end + sync always + update \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr $0\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] + end + attribute \src "ls180.v:387.12-387.46" + process $proc$ls180.v:387$3201 + assign { } { } + assign $1\main_sdram_slave_p0_rddata[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdram_slave_p0_rddata $1\main_sdram_slave_p0_rddata[15:0] + end + attribute \src "ls180.v:3870.1-3963.4" + process $proc$ls180.v:3870$342 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdram_bankmachine3_cmd_payload_ras[0:0] 1'0 + assign { } { } + assign $0\main_sdram_bankmachine3_cmd_payload_we[0:0] 1'0 + assign $0\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'0 + assign $0\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] 1'0 + assign $0\main_sdram_bankmachine3_cmd_payload_is_read[0:0] 1'0 + assign $0\main_sdram_bankmachine3_cmd_payload_is_write[0:0] 1'0 + assign $0\main_sdram_bankmachine3_req_wdata_ready[0:0] 1'0 + assign $0\main_sdram_bankmachine3_req_rdata_valid[0:0] 1'0 + assign $0\main_sdram_bankmachine3_refresh_gnt[0:0] 1'0 + assign $0\main_sdram_bankmachine3_cmd_valid[0:0] 1'0 + assign $0\main_sdram_bankmachine3_row_open[0:0] 1'0 + assign $0\main_sdram_bankmachine3_row_close[0:0] 1'0 + assign $0\main_sdram_bankmachine3_cmd_payload_cas[0:0] 1'0 + assign $0\builder_bankmachine3_next_state[2:0] \builder_bankmachine3_state + attribute \src "ls180.v:3886.2-3962.9" + switch \builder_bankmachine3_state + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\main_sdram_bankmachine3_row_close[0:0] 1'1 + attribute \src "ls180.v:3888.4-3896.7" + switch $and$ls180.v:3888$343_Y + attribute \src "ls180.v:3888.8-3888.87" + case 1'1 + assign $0\main_sdram_bankmachine3_cmd_valid[0:0] 1'1 + assign $0\main_sdram_bankmachine3_cmd_payload_ras[0:0] 1'1 + assign $0\main_sdram_bankmachine3_cmd_payload_we[0:0] 1'1 + assign $0\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'1 + attribute \src "ls180.v:3890.5-3892.8" + switch \main_sdram_bankmachine3_cmd_ready + attribute \src "ls180.v:3890.9-3890.42" + case 1'1 + assign $0\builder_bankmachine3_next_state[2:0] 3'101 + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\main_sdram_bankmachine3_row_close[0:0] 1'1 + attribute \src "ls180.v:3900.4-3902.7" + switch $and$ls180.v:3900$344_Y + attribute \src "ls180.v:3900.8-3900.87" + case 1'1 + assign $0\builder_bankmachine3_next_state[2:0] 3'101 + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'011 + attribute \src "ls180.v:3906.4-3915.7" + switch \main_sdram_bankmachine3_trccon_ready + attribute \src "ls180.v:3906.8-3906.44" + case 1'1 + assign $0\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] 1'1 + assign $0\main_sdram_bankmachine3_row_open[0:0] 1'1 + assign $0\main_sdram_bankmachine3_cmd_valid[0:0] 1'1 + assign $0\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'1 + assign $0\main_sdram_bankmachine3_cmd_payload_ras[0:0] 1'1 + attribute \src "ls180.v:3911.5-3913.8" + switch \main_sdram_bankmachine3_cmd_ready + attribute \src "ls180.v:3911.9-3911.42" + case 1'1 + assign $0\builder_bankmachine3_next_state[2:0] 3'110 + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\main_sdram_bankmachine3_row_close[0:0] 1'1 + assign $0\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'1 + attribute \src "ls180.v:3918.4-3920.7" + switch \main_sdram_bankmachine3_twtpcon_ready + attribute \src "ls180.v:3918.8-3918.45" + case 1'1 + assign $0\main_sdram_bankmachine3_refresh_gnt[0:0] 1'1 + case + end + attribute \src "ls180.v:3923.4-3925.7" + switch $not$ls180.v:3923$345_Y + attribute \src "ls180.v:3923.8-3923.46" + case 1'1 + assign $0\builder_bankmachine3_next_state[2:0] 3'000 + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'101 + assign $0\builder_bankmachine3_next_state[2:0] 3'011 + attribute \src "ls180.v:0.0-0.0" + case 3'110 + assign $0\builder_bankmachine3_next_state[2:0] 3'000 + attribute \src "ls180.v:0.0-0.0" + case + attribute \src "ls180.v:3934.4-3960.7" + switch \main_sdram_bankmachine3_refresh_req + attribute \src "ls180.v:3934.8-3934.43" + case 1'1 + assign $0\builder_bankmachine3_next_state[2:0] 3'100 + attribute \src "ls180.v:3936.8-3936.12" + case + attribute \src "ls180.v:3937.5-3959.8" + switch \main_sdram_bankmachine3_cmd_buffer_source_valid + attribute \src "ls180.v:3937.9-3937.56" + case 1'1 + attribute \src "ls180.v:3938.6-3958.9" + switch \main_sdram_bankmachine3_row_opened + attribute \src "ls180.v:3938.10-3938.44" + case 1'1 + attribute \src "ls180.v:3939.7-3955.10" + switch \main_sdram_bankmachine3_row_hit + attribute \src "ls180.v:3939.11-3939.42" + case 1'1 + assign $0\main_sdram_bankmachine3_cmd_valid[0:0] 1'1 + assign $0\main_sdram_bankmachine3_cmd_payload_cas[0:0] 1'1 + attribute \src "ls180.v:3941.8-3948.11" + switch \main_sdram_bankmachine3_cmd_buffer_source_payload_we + attribute \src "ls180.v:3941.12-3941.64" + case 1'1 + assign $0\main_sdram_bankmachine3_req_wdata_ready[0:0] \main_sdram_bankmachine3_cmd_ready + assign $0\main_sdram_bankmachine3_cmd_payload_is_write[0:0] 1'1 + assign $0\main_sdram_bankmachine3_cmd_payload_we[0:0] 1'1 + attribute \src "ls180.v:3945.12-3945.16" + case + assign $0\main_sdram_bankmachine3_req_rdata_valid[0:0] \main_sdram_bankmachine3_cmd_ready + assign $0\main_sdram_bankmachine3_cmd_payload_is_read[0:0] 1'1 + end + attribute \src "ls180.v:3950.8-3952.11" + switch $and$ls180.v:3950$346_Y + attribute \src "ls180.v:3950.12-3950.88" + case 1'1 + assign $0\builder_bankmachine3_next_state[2:0] 3'010 + case + end + attribute \src "ls180.v:3953.11-3953.15" + case + assign $0\builder_bankmachine3_next_state[2:0] 3'001 + end + attribute \src "ls180.v:3956.10-3956.14" + case + assign $0\builder_bankmachine3_next_state[2:0] 3'011 + end + case + end + end + end + sync always + update \main_sdram_bankmachine3_req_wdata_ready $0\main_sdram_bankmachine3_req_wdata_ready[0:0] + update \main_sdram_bankmachine3_req_rdata_valid $0\main_sdram_bankmachine3_req_rdata_valid[0:0] + update \main_sdram_bankmachine3_refresh_gnt $0\main_sdram_bankmachine3_refresh_gnt[0:0] + update \main_sdram_bankmachine3_cmd_valid $0\main_sdram_bankmachine3_cmd_valid[0:0] + update \main_sdram_bankmachine3_cmd_payload_cas $0\main_sdram_bankmachine3_cmd_payload_cas[0:0] + update \main_sdram_bankmachine3_cmd_payload_ras $0\main_sdram_bankmachine3_cmd_payload_ras[0:0] + update \main_sdram_bankmachine3_cmd_payload_we $0\main_sdram_bankmachine3_cmd_payload_we[0:0] + update \main_sdram_bankmachine3_cmd_payload_is_cmd $0\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] + update \main_sdram_bankmachine3_cmd_payload_is_read $0\main_sdram_bankmachine3_cmd_payload_is_read[0:0] + update \main_sdram_bankmachine3_cmd_payload_is_write $0\main_sdram_bankmachine3_cmd_payload_is_write[0:0] + update \main_sdram_bankmachine3_row_open $0\main_sdram_bankmachine3_row_open[0:0] + update \main_sdram_bankmachine3_row_close $0\main_sdram_bankmachine3_row_close[0:0] + update \main_sdram_bankmachine3_row_col_n_addr_sel $0\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] + update \builder_bankmachine3_next_state $0\builder_bankmachine3_next_state[2:0] + end + attribute \src "ls180.v:388.5-388.44" + process $proc$ls180.v:388$3202 + assign { } { } + assign $1\main_sdram_slave_p0_rddata_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_slave_p0_rddata_valid $1\main_sdram_slave_p0_rddata_valid[0:0] + end + attribute \src "ls180.v:389.12-389.48" + process $proc$ls180.v:389$3203 + assign { } { } + assign $1\main_sdram_master_p0_address[12:0] 13'0000000000000 + sync always + sync init + update \main_sdram_master_p0_address $1\main_sdram_master_p0_address[12:0] + end + attribute \src "ls180.v:390.11-390.43" + process $proc$ls180.v:390$3204 + assign { } { } + assign $1\main_sdram_master_p0_bank[1:0] 2'00 + sync always + sync init + update \main_sdram_master_p0_bank $1\main_sdram_master_p0_bank[1:0] + end + attribute \src "ls180.v:391.5-391.38" + process $proc$ls180.v:391$3205 + assign { } { } + assign $1\main_sdram_master_p0_cas_n[0:0] 1'1 + sync always + sync init + update \main_sdram_master_p0_cas_n $1\main_sdram_master_p0_cas_n[0:0] + end + attribute \src "ls180.v:392.5-392.37" + process $proc$ls180.v:392$3206 + assign { } { } + assign $1\main_sdram_master_p0_cs_n[0:0] 1'1 + sync always + sync init + update \main_sdram_master_p0_cs_n $1\main_sdram_master_p0_cs_n[0:0] + end + attribute \src "ls180.v:393.5-393.38" + process $proc$ls180.v:393$3207 + assign { } { } + assign $1\main_sdram_master_p0_ras_n[0:0] 1'1 + sync always + sync init + update \main_sdram_master_p0_ras_n $1\main_sdram_master_p0_ras_n[0:0] + end + attribute \src "ls180.v:394.5-394.37" + process $proc$ls180.v:394$3208 + assign { } { } + assign $1\main_sdram_master_p0_we_n[0:0] 1'1 + sync always + sync init + update \main_sdram_master_p0_we_n $1\main_sdram_master_p0_we_n[0:0] + end + attribute \src "ls180.v:395.5-395.36" + process $proc$ls180.v:395$3209 + assign { } { } + assign $1\main_sdram_master_p0_cke[0:0] 1'0 + sync always + sync init + update \main_sdram_master_p0_cke $1\main_sdram_master_p0_cke[0:0] + end + attribute \src "ls180.v:396.5-396.36" + process $proc$ls180.v:396$3210 + assign { } { } + assign $1\main_sdram_master_p0_odt[0:0] 1'0 + sync always + sync init + update \main_sdram_master_p0_odt $1\main_sdram_master_p0_odt[0:0] + end + attribute \src "ls180.v:397.5-397.40" + process $proc$ls180.v:397$3211 + assign { } { } + assign $1\main_sdram_master_p0_reset_n[0:0] 1'0 + sync always + sync init + update \main_sdram_master_p0_reset_n $1\main_sdram_master_p0_reset_n[0:0] + end + attribute \src "ls180.v:398.5-398.38" + process $proc$ls180.v:398$3212 + assign { } { } + assign $1\main_sdram_master_p0_act_n[0:0] 1'1 + sync always + sync init + update \main_sdram_master_p0_act_n $1\main_sdram_master_p0_act_n[0:0] + end + attribute \src "ls180.v:3983.1-3989.4" + process $proc$ls180.v:3983$385 + assign { } { } + assign { } { } + assign $0\main_sdram_choose_cmd_valids[3:0] [0] $and$ls180.v:3985$398_Y + assign $0\main_sdram_choose_cmd_valids[3:0] [1] $and$ls180.v:3986$411_Y + assign $0\main_sdram_choose_cmd_valids[3:0] [2] $and$ls180.v:3987$424_Y + assign $0\main_sdram_choose_cmd_valids[3:0] [3] $and$ls180.v:3988$437_Y + sync always + update \main_sdram_choose_cmd_valids $0\main_sdram_choose_cmd_valids[3:0] + end + attribute \src "ls180.v:399.12-399.47" + process $proc$ls180.v:399$3213 + assign { } { } + assign $1\main_sdram_master_p0_wrdata[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdram_master_p0_wrdata $1\main_sdram_master_p0_wrdata[15:0] + end + attribute \src "ls180.v:3997.1-4002.4" + process $proc$ls180.v:3997$438 + assign { } { } + assign $0\main_sdram_choose_cmd_cmd_payload_cas[0:0] 1'0 + attribute \src "ls180.v:3999.2-4001.5" + switch \main_sdram_choose_cmd_cmd_valid + attribute \src "ls180.v:3999.6-3999.37" + case 1'1 + assign $0\main_sdram_choose_cmd_cmd_payload_cas[0:0] \builder_comb_t_array_muxed0 + case + end + sync always + update \main_sdram_choose_cmd_cmd_payload_cas $0\main_sdram_choose_cmd_cmd_payload_cas[0:0] + end + attribute \src "ls180.v:400.5-400.42" + process $proc$ls180.v:400$3214 + assign { } { } + assign $1\main_sdram_master_p0_wrdata_en[0:0] 1'0 + sync always + sync init + update \main_sdram_master_p0_wrdata_en $1\main_sdram_master_p0_wrdata_en[0:0] + end + attribute \src "ls180.v:4003.1-4008.4" + process $proc$ls180.v:4003$439 + assign { } { } + assign $0\main_sdram_choose_cmd_cmd_payload_ras[0:0] 1'0 + attribute \src "ls180.v:4005.2-4007.5" + switch \main_sdram_choose_cmd_cmd_valid + attribute \src "ls180.v:4005.6-4005.37" + case 1'1 + assign $0\main_sdram_choose_cmd_cmd_payload_ras[0:0] \builder_comb_t_array_muxed1 + case + end + sync always + update \main_sdram_choose_cmd_cmd_payload_ras $0\main_sdram_choose_cmd_cmd_payload_ras[0:0] + end + attribute \src "ls180.v:4009.1-4014.4" + process $proc$ls180.v:4009$440 + assign { } { } + assign $0\main_sdram_choose_cmd_cmd_payload_we[0:0] 1'0 + attribute \src "ls180.v:4011.2-4013.5" + switch \main_sdram_choose_cmd_cmd_valid + attribute \src "ls180.v:4011.6-4011.37" + case 1'1 + assign $0\main_sdram_choose_cmd_cmd_payload_we[0:0] \builder_comb_t_array_muxed2 + case + end + sync always + update \main_sdram_choose_cmd_cmd_payload_we $0\main_sdram_choose_cmd_cmd_payload_we[0:0] + end + attribute \src "ls180.v:401.11-401.50" + process $proc$ls180.v:401$3215 + assign { } { } + assign $1\main_sdram_master_p0_wrdata_mask[1:0] 2'00 + sync always + sync init + update \main_sdram_master_p0_wrdata_mask $1\main_sdram_master_p0_wrdata_mask[1:0] + end + attribute \src "ls180.v:4016.1-4022.4" + process $proc$ls180.v:4016$443 + assign { } { } + assign { } { } + assign $0\main_sdram_choose_req_valids[3:0] [0] $and$ls180.v:4018$456_Y + assign $0\main_sdram_choose_req_valids[3:0] [1] $and$ls180.v:4019$469_Y + assign $0\main_sdram_choose_req_valids[3:0] [2] $and$ls180.v:4020$482_Y + assign $0\main_sdram_choose_req_valids[3:0] [3] $and$ls180.v:4021$495_Y + sync always + update \main_sdram_choose_req_valids $0\main_sdram_choose_req_valids[3:0] + end + attribute \src "ls180.v:402.5-402.42" + process $proc$ls180.v:402$3216 + assign { } { } + assign $1\main_sdram_master_p0_rddata_en[0:0] 1'0 + sync always + sync init + update \main_sdram_master_p0_rddata_en $1\main_sdram_master_p0_rddata_en[0:0] + end + attribute \src "ls180.v:4030.1-4035.4" + process $proc$ls180.v:4030$496 + assign { } { } + assign $0\main_sdram_choose_req_cmd_payload_cas[0:0] 1'0 + attribute \src "ls180.v:4032.2-4034.5" + switch \main_sdram_choose_req_cmd_valid + attribute \src "ls180.v:4032.6-4032.37" + case 1'1 + assign $0\main_sdram_choose_req_cmd_payload_cas[0:0] \builder_comb_t_array_muxed3 + case + end + sync always + update \main_sdram_choose_req_cmd_payload_cas $0\main_sdram_choose_req_cmd_payload_cas[0:0] + end + attribute \src "ls180.v:4036.1-4041.4" + process $proc$ls180.v:4036$497 + assign { } { } + assign $0\main_sdram_choose_req_cmd_payload_ras[0:0] 1'0 + attribute \src "ls180.v:4038.2-4040.5" + switch \main_sdram_choose_req_cmd_valid + attribute \src "ls180.v:4038.6-4038.37" + case 1'1 + assign $0\main_sdram_choose_req_cmd_payload_ras[0:0] \builder_comb_t_array_muxed4 + case + end + sync always + update \main_sdram_choose_req_cmd_payload_ras $0\main_sdram_choose_req_cmd_payload_ras[0:0] + end + attribute \src "ls180.v:4042.1-4047.4" + process $proc$ls180.v:4042$498 + assign { } { } + assign $0\main_sdram_choose_req_cmd_payload_we[0:0] 1'0 + attribute \src "ls180.v:4044.2-4046.5" + switch \main_sdram_choose_req_cmd_valid + attribute \src "ls180.v:4044.6-4044.37" + case 1'1 + assign $0\main_sdram_choose_req_cmd_payload_we[0:0] \builder_comb_t_array_muxed5 + case + end + sync always + update \main_sdram_choose_req_cmd_payload_we $0\main_sdram_choose_req_cmd_payload_we[0:0] + end + attribute \src "ls180.v:4048.1-4056.4" + process $proc$ls180.v:4048$499 + assign { } { } + assign $0\main_sdram_bankmachine0_cmd_ready[0:0] 1'0 + attribute \src "ls180.v:4050.2-4052.5" + switch $and$ls180.v:4050$502_Y + attribute \src "ls180.v:4050.6-4050.115" + case 1'1 + assign $0\main_sdram_bankmachine0_cmd_ready[0:0] 1'1 + case + end + attribute \src "ls180.v:4053.2-4055.5" + switch $and$ls180.v:4053$505_Y + attribute \src "ls180.v:4053.6-4053.115" + case 1'1 + assign $0\main_sdram_bankmachine0_cmd_ready[0:0] 1'1 + case + end + sync always + update \main_sdram_bankmachine0_cmd_ready $0\main_sdram_bankmachine0_cmd_ready[0:0] + end + attribute \src "ls180.v:4057.1-4065.4" + process $proc$ls180.v:4057$506 + assign { } { } + assign $0\main_sdram_bankmachine1_cmd_ready[0:0] 1'0 + attribute \src "ls180.v:4059.2-4061.5" + switch $and$ls180.v:4059$509_Y + attribute \src "ls180.v:4059.6-4059.115" + case 1'1 + assign $0\main_sdram_bankmachine1_cmd_ready[0:0] 1'1 + case + end + attribute \src "ls180.v:4062.2-4064.5" + switch $and$ls180.v:4062$512_Y + attribute \src "ls180.v:4062.6-4062.115" + case 1'1 + assign $0\main_sdram_bankmachine1_cmd_ready[0:0] 1'1 + case + end + sync always + update \main_sdram_bankmachine1_cmd_ready $0\main_sdram_bankmachine1_cmd_ready[0:0] + end + attribute \src "ls180.v:4066.1-4074.4" + process $proc$ls180.v:4066$513 + assign { } { } + assign $0\main_sdram_bankmachine2_cmd_ready[0:0] 1'0 + attribute \src "ls180.v:4068.2-4070.5" + switch $and$ls180.v:4068$516_Y + attribute \src "ls180.v:4068.6-4068.115" + case 1'1 + assign $0\main_sdram_bankmachine2_cmd_ready[0:0] 1'1 + case + end + attribute \src "ls180.v:4071.2-4073.5" + switch $and$ls180.v:4071$519_Y + attribute \src "ls180.v:4071.6-4071.115" + case 1'1 + assign $0\main_sdram_bankmachine2_cmd_ready[0:0] 1'1 + case + end + sync always + update \main_sdram_bankmachine2_cmd_ready $0\main_sdram_bankmachine2_cmd_ready[0:0] + end + attribute \src "ls180.v:4075.1-4083.4" + process $proc$ls180.v:4075$520 + assign { } { } + assign $0\main_sdram_bankmachine3_cmd_ready[0:0] 1'0 + attribute \src "ls180.v:4077.2-4079.5" + switch $and$ls180.v:4077$523_Y + attribute \src "ls180.v:4077.6-4077.115" + case 1'1 + assign $0\main_sdram_bankmachine3_cmd_ready[0:0] 1'1 + case + end + attribute \src "ls180.v:4080.2-4082.5" + switch $and$ls180.v:4080$526_Y + attribute \src "ls180.v:4080.6-4080.115" + case 1'1 + assign $0\main_sdram_bankmachine3_cmd_ready[0:0] 1'1 + case + end + sync always + update \main_sdram_bankmachine3_cmd_ready $0\main_sdram_bankmachine3_cmd_ready[0:0] + end + attribute \src "ls180.v:4088.1-4160.4" + process $proc$ls180.v:4088$529 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdram_en1[0:0] 1'0 + assign $0\main_sdram_choose_req_want_reads[0:0] 1'0 + assign $0\main_sdram_choose_req_want_writes[0:0] 1'0 + assign $0\main_sdram_cmd_ready[0:0] 1'0 + assign { } { } + assign $0\main_sdram_steerer_sel[1:0] 2'00 + assign $0\main_sdram_choose_req_cmd_ready[0:0] 1'0 + assign $0\main_sdram_en0[0:0] 1'0 + assign { } { } + assign $0\main_sdram_choose_req_want_activates[0:0] \main_sdram_ras_allowed + assign $0\builder_multiplexer_next_state[2:0] \builder_multiplexer_state + attribute \src "ls180.v:4100.2-4159.9" + switch \builder_multiplexer_state + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\main_sdram_en1[0:0] 1'1 + assign $0\main_sdram_choose_req_want_writes[0:0] 1'1 + assign $0\main_sdram_steerer_sel[1:0] 2'10 + attribute \src "ls180.v:4104.4-4110.7" + switch 1'1 + attribute \src "ls180.v:4104.8-4104.12" + case 1'1 + assign $0\main_sdram_choose_req_cmd_ready[0:0] $and$ls180.v:4105$536_Y + case + end + attribute \src "ls180.v:4112.4-4116.7" + switch \main_sdram_read_available + attribute \src "ls180.v:4112.8-4112.33" + case 1'1 + attribute \src "ls180.v:4113.5-4115.8" + switch $or$ls180.v:4113$538_Y + attribute \src "ls180.v:4113.9-4113.63" + case 1'1 + assign $0\builder_multiplexer_next_state[2:0] 3'011 + case + end + case + end + attribute \src "ls180.v:4117.4-4119.7" + switch \main_sdram_go_to_refresh + attribute \src "ls180.v:4117.8-4117.32" + case 1'1 + assign $0\builder_multiplexer_next_state[2:0] 3'010 + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\main_sdram_steerer_sel[1:0] 2'11 + assign $0\main_sdram_cmd_ready[0:0] 1'1 + attribute \src "ls180.v:4124.4-4126.7" + switch \main_sdram_cmd_last + attribute \src "ls180.v:4124.8-4124.27" + case 1'1 + assign $0\builder_multiplexer_next_state[2:0] 3'000 + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'011 + attribute \src "ls180.v:4129.4-4131.7" + switch \main_sdram_twtrcon_ready + attribute \src "ls180.v:4129.8-4129.32" + case 1'1 + assign $0\builder_multiplexer_next_state[2:0] 3'000 + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\builder_multiplexer_next_state[2:0] 3'101 + attribute \src "ls180.v:0.0-0.0" + case 3'101 + assign $0\builder_multiplexer_next_state[2:0] 3'001 + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_sdram_en0[0:0] 1'1 + assign $0\main_sdram_choose_req_want_reads[0:0] 1'1 + assign $0\main_sdram_steerer_sel[1:0] 2'10 + attribute \src "ls180.v:4142.4-4148.7" + switch 1'1 + attribute \src "ls180.v:4142.8-4142.12" + case 1'1 + assign $0\main_sdram_choose_req_cmd_ready[0:0] $and$ls180.v:4143$545_Y + case + end + attribute \src "ls180.v:4150.4-4154.7" + switch \main_sdram_write_available + attribute \src "ls180.v:4150.8-4150.34" + case 1'1 + attribute \src "ls180.v:4151.5-4153.8" + switch $or$ls180.v:4151$547_Y + attribute \src "ls180.v:4151.9-4151.62" + case 1'1 + assign $0\builder_multiplexer_next_state[2:0] 3'100 + case + end + case + end + attribute \src "ls180.v:4155.4-4157.7" + switch \main_sdram_go_to_refresh + attribute \src "ls180.v:4155.8-4155.32" + case 1'1 + assign $0\builder_multiplexer_next_state[2:0] 3'010 + case + end + end + sync always + update \main_sdram_cmd_ready $0\main_sdram_cmd_ready[0:0] + update \main_sdram_choose_req_want_reads $0\main_sdram_choose_req_want_reads[0:0] + update \main_sdram_choose_req_want_writes $0\main_sdram_choose_req_want_writes[0:0] + update \main_sdram_choose_req_want_activates $0\main_sdram_choose_req_want_activates[0:0] + update \main_sdram_choose_req_cmd_ready $0\main_sdram_choose_req_cmd_ready[0:0] + update \main_sdram_steerer_sel $0\main_sdram_steerer_sel[1:0] + update \main_sdram_en0 $0\main_sdram_en0[0:0] + update \main_sdram_en1 $0\main_sdram_en1[0:0] + update \builder_multiplexer_next_state $0\builder_multiplexer_next_state[2:0] + end + attribute \src "ls180.v:409.11-409.36" + process $proc$ls180.v:409$3217 + assign { } { } + assign $1\main_sdram_storage[3:0] 4'0001 + sync always + sync init + update \main_sdram_storage $1\main_sdram_storage[3:0] + end + attribute \src "ls180.v:410.5-410.25" + process $proc$ls180.v:410$3218 + assign { } { } + assign $1\main_sdram_re[0:0] 1'0 + sync always + sync init + update \main_sdram_re $1\main_sdram_re[0:0] + end + attribute \src "ls180.v:411.11-411.44" + process $proc$ls180.v:411$3219 + assign { } { } + assign $1\main_sdram_command_storage[5:0] 6'000000 + sync always + sync init + update \main_sdram_command_storage $1\main_sdram_command_storage[5:0] + end + attribute \src "ls180.v:412.5-412.33" + process $proc$ls180.v:412$3220 + assign { } { } + assign $1\main_sdram_command_re[0:0] 1'0 + sync always + sync init + update \main_sdram_command_re $1\main_sdram_command_re[0:0] + end + attribute \src "ls180.v:416.5-416.38" + process $proc$ls180.v:416$3221 + assign { } { } + assign $0\main_sdram_command_issue_w[0:0] 1'0 + sync always + update \main_sdram_command_issue_w $0\main_sdram_command_issue_w[0:0] + sync init + end + attribute \src "ls180.v:417.12-417.46" + process $proc$ls180.v:417$3222 + assign { } { } + assign $1\main_sdram_address_storage[12:0] 13'0000000000000 + sync always + sync init + update \main_sdram_address_storage $1\main_sdram_address_storage[12:0] + end + attribute \src "ls180.v:418.5-418.33" + process $proc$ls180.v:418$3223 + assign { } { } + assign $1\main_sdram_address_re[0:0] 1'0 + sync always + sync init + update \main_sdram_address_re $1\main_sdram_address_re[0:0] + end + attribute \src "ls180.v:4184.1-4197.4" + process $proc$ls180.v:4184$676 + assign { } { } + assign { } { } + assign $0\main_sdram_interface_wdata[15:0] 16'0000000000000000 + assign $0\main_sdram_interface_wdata_we[1:0] 2'00 + attribute \src "ls180.v:4187.2-4196.9" + switch \builder_new_master_wdata_ready + attribute \src "ls180.v:0.0-0.0" + case 1'1 + assign $0\main_sdram_interface_wdata[15:0] \main_port_wdata_payload_data + assign $0\main_sdram_interface_wdata_we[1:0] \main_port_wdata_payload_we + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_sdram_interface_wdata[15:0] 16'0000000000000000 + assign $0\main_sdram_interface_wdata_we[1:0] 2'00 + end + sync always + update \main_sdram_interface_wdata $0\main_sdram_interface_wdata[15:0] + update \main_sdram_interface_wdata_we $0\main_sdram_interface_wdata_we[1:0] + end + attribute \src "ls180.v:419.11-419.45" + process $proc$ls180.v:419$3224 + assign { } { } + assign $1\main_sdram_baddress_storage[1:0] 2'00 + sync always + sync init + update \main_sdram_baddress_storage $1\main_sdram_baddress_storage[1:0] + end + attribute \src "ls180.v:420.5-420.34" + process $proc$ls180.v:420$3225 + assign { } { } + assign $1\main_sdram_baddress_re[0:0] 1'0 + sync always + sync init + update \main_sdram_baddress_re $1\main_sdram_baddress_re[0:0] + end + attribute \src "ls180.v:4204.1-4214.4" + process $proc$ls180.v:4204$678 + assign { } { } + assign $0\main_litedram_wb_dat_w[15:0] 16'0000000000000000 + attribute \src "ls180.v:4206.2-4213.9" + switch \main_converter_counter + attribute \src "ls180.v:0.0-0.0" + case 1'0 + assign $0\main_litedram_wb_dat_w[15:0] \main_wb_sdram_dat_w [15:0] + attribute \src "ls180.v:0.0-0.0" + case 1'1 + assign $0\main_litedram_wb_dat_w[15:0] \main_wb_sdram_dat_w [31:16] + case + end + sync always + update \main_litedram_wb_dat_w $0\main_litedram_wb_dat_w[15:0] + end + attribute \src "ls180.v:421.12-421.45" + process $proc$ls180.v:421$3226 + assign { } { } + assign $1\main_sdram_wrdata_storage[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdram_wrdata_storage $1\main_sdram_wrdata_storage[15:0] + end + attribute \src "ls180.v:4216.1-4262.4" + process $proc$ls180.v:4216$679 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_litedram_wb_sel[1:0] 2'00 + assign $0\main_litedram_wb_cyc[0:0] 1'0 + assign { } { } + assign $0\main_litedram_wb_stb[0:0] 1'0 + assign $0\main_converter_counter_converter_next_value[0:0] 1'0 + assign $0\main_converter_counter_converter_next_value_ce[0:0] 1'0 + assign $0\main_litedram_wb_we[0:0] 1'0 + assign $0\main_converter_skip[0:0] 1'0 + assign $0\main_wb_sdram_ack[0:0] 1'0 + assign $0\main_litedram_wb_adr[29:0] 30'000000000000000000000000000000 + assign $0\builder_converter_next_state[0:0] \builder_converter_state + attribute \src "ls180.v:4228.2-4261.9" + switch \builder_converter_state + attribute \src "ls180.v:0.0-0.0" + case 1'1 + assign $0\main_litedram_wb_adr[29:0] { \main_wb_sdram_adr [28:0] \main_converter_counter } + attribute \src "ls180.v:4231.4-4238.11" + switch \main_converter_counter + attribute \src "ls180.v:0.0-0.0" + case 1'0 + assign $0\main_litedram_wb_sel[1:0] \main_wb_sdram_sel [1:0] + attribute \src "ls180.v:0.0-0.0" + case 1'1 + assign $0\main_litedram_wb_sel[1:0] \main_wb_sdram_sel [3:2] + case + end + attribute \src "ls180.v:4239.4-4252.7" + switch $and$ls180.v:4239$680_Y + attribute \src "ls180.v:4239.8-4239.47" + case 1'1 + assign $0\main_converter_skip[0:0] $eq$ls180.v:4240$681_Y + assign $0\main_litedram_wb_we[0:0] \main_wb_sdram_we + assign $0\main_litedram_wb_cyc[0:0] $not$ls180.v:4242$682_Y + assign $0\main_litedram_wb_stb[0:0] $not$ls180.v:4243$683_Y + attribute \src "ls180.v:4244.5-4251.8" + switch $or$ls180.v:4244$684_Y + attribute \src "ls180.v:4244.9-4244.53" + case 1'1 + assign $0\main_converter_counter_converter_next_value[0:0] $add$ls180.v:4245$685_Y + assign $0\main_converter_counter_converter_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:4247.6-4250.9" + switch $eq$ls180.v:4247$686_Y + attribute \src "ls180.v:4247.10-4247.42" + case 1'1 + assign $0\main_wb_sdram_ack[0:0] 1'1 + assign $0\builder_converter_next_state[0:0] 1'0 + case + end + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_converter_counter_converter_next_value[0:0] 1'0 + assign $0\main_converter_counter_converter_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:4257.4-4259.7" + switch $and$ls180.v:4257$687_Y + attribute \src "ls180.v:4257.8-4257.47" + case 1'1 + assign $0\builder_converter_next_state[0:0] 1'1 + case + end + end + sync always + update \main_wb_sdram_ack $0\main_wb_sdram_ack[0:0] + update \main_litedram_wb_adr $0\main_litedram_wb_adr[29:0] + update \main_litedram_wb_sel $0\main_litedram_wb_sel[1:0] + update \main_litedram_wb_cyc $0\main_litedram_wb_cyc[0:0] + update \main_litedram_wb_stb $0\main_litedram_wb_stb[0:0] + update \main_litedram_wb_we $0\main_litedram_wb_we[0:0] + update \main_converter_skip $0\main_converter_skip[0:0] + update \builder_converter_next_state $0\builder_converter_next_state[0:0] + update \main_converter_counter_converter_next_value $0\main_converter_counter_converter_next_value[0:0] + update \main_converter_counter_converter_next_value_ce $0\main_converter_counter_converter_next_value_ce[0:0] + end + attribute \src "ls180.v:422.5-422.32" + process $proc$ls180.v:422$3227 + assign { } { } + assign $1\main_sdram_wrdata_re[0:0] 1'0 + sync always + sync init + update \main_sdram_wrdata_re $1\main_sdram_wrdata_re[0:0] + end + attribute \src "ls180.v:423.12-423.37" + process $proc$ls180.v:423$3228 + assign { } { } + assign $1\main_sdram_status[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdram_status $1\main_sdram_status[15:0] + end + attribute \src "ls180.v:4307.1-4312.4" + process $proc$ls180.v:4307$719 + assign { } { } + assign $0\main_uart_tx_clear[0:0] 1'0 + attribute \src "ls180.v:4309.2-4311.5" + switch $and$ls180.v:4309$720_Y + attribute \src "ls180.v:4309.6-4309.79" + case 1'1 + assign $0\main_uart_tx_clear[0:0] 1'1 + case + end + sync always + update \main_uart_tx_clear $0\main_uart_tx_clear[0:0] + end + attribute \src "ls180.v:4313.1-4317.4" + process $proc$ls180.v:4313$721 + assign { } { } + assign { } { } + assign $0\main_uart_eventmanager_status_w[1:0] [0] \main_uart_tx_status + assign $0\main_uart_eventmanager_status_w[1:0] [1] \main_uart_rx_status + sync always + update \main_uart_eventmanager_status_w $0\main_uart_eventmanager_status_w[1:0] + end + attribute \src "ls180.v:4318.1-4323.4" + process $proc$ls180.v:4318$722 + assign { } { } + assign $0\main_uart_rx_clear[0:0] 1'0 + attribute \src "ls180.v:4320.2-4322.5" + switch $and$ls180.v:4320$723_Y + attribute \src "ls180.v:4320.6-4320.79" + case 1'1 + assign $0\main_uart_rx_clear[0:0] 1'1 + case + end + sync always + update \main_uart_rx_clear $0\main_uart_rx_clear[0:0] + end + attribute \src "ls180.v:4324.1-4328.4" + process $proc$ls180.v:4324$724 + assign { } { } + assign { } { } + assign $0\main_uart_eventmanager_pending_w[1:0] [0] \main_uart_tx_pending + assign $0\main_uart_eventmanager_pending_w[1:0] [1] \main_uart_rx_pending + sync always + update \main_uart_eventmanager_pending_w $0\main_uart_eventmanager_pending_w[1:0] + end + attribute \src "ls180.v:4346.1-4353.4" + process $proc$ls180.v:4346$732 + assign { } { } + assign $0\main_uart_tx_fifo_wrport_adr[3:0] 4'0000 + attribute \src "ls180.v:4348.2-4352.5" + switch \main_uart_tx_fifo_replace + attribute \src "ls180.v:4348.6-4348.31" + case 1'1 + assign $0\main_uart_tx_fifo_wrport_adr[3:0] $sub$ls180.v:4349$733_Y + attribute \src "ls180.v:4350.6-4350.10" + case + assign $0\main_uart_tx_fifo_wrport_adr[3:0] \main_uart_tx_fifo_produce + end + sync always + update \main_uart_tx_fifo_wrport_adr $0\main_uart_tx_fifo_wrport_adr[3:0] + end + attribute \src "ls180.v:4376.1-4383.4" + process $proc$ls180.v:4376$743 + assign { } { } + assign $0\main_uart_rx_fifo_wrport_adr[3:0] 4'0000 + attribute \src "ls180.v:4378.2-4382.5" + switch \main_uart_rx_fifo_replace + attribute \src "ls180.v:4378.6-4378.31" + case 1'1 + assign $0\main_uart_rx_fifo_wrport_adr[3:0] $sub$ls180.v:4379$744_Y + attribute \src "ls180.v:4380.6-4380.10" + case + assign $0\main_uart_rx_fifo_wrport_adr[3:0] \main_uart_rx_fifo_produce + end + sync always + update \main_uart_rx_fifo_wrport_adr $0\main_uart_rx_fifo_wrport_adr[3:0] + end + attribute \src "ls180.v:4396.1-4400.4" + process $proc$ls180.v:4396$750 + assign { } { } + assign { } { } + assign { } { } + assign $0\gpio_o[15:0] \main_gpiotristateasic1_pads_o + sync always + update \gpio_o $0\gpio_o[15:0] + end + attribute \src "ls180.v:4401.1-4405.4" + process $proc$ls180.v:4401$751 + assign { } { } + assign { } { } + assign { } { } + assign $0\gpio_oe[15:0] \main_gpiotristateasic1_pads_oe + sync always + update \gpio_oe $0\gpio_oe[15:0] + end + attribute \src "ls180.v:4417.1-4465.4" + process $proc$ls180.v:4417$756 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_spimaster27_count_spimaster0_next_value[2:0] 3'000 + assign $0\main_spimaster27_count_spimaster0_next_value_ce[0:0] 1'0 + assign $0\main_spimaster25_clk_enable[0:0] 1'0 + assign $0\main_spimaster26_cs_enable[0:0] 1'0 + assign $0\main_spimaster28_mosi_latch[0:0] 1'0 + assign $0\main_spimaster2_done[0:0] 1'0 + assign $0\main_spimaster29_miso_latch[0:0] 1'0 + assign $0\main_spimaster3_irq[0:0] 1'0 + assign $0\builder_spimaster0_next_state[1:0] \builder_spimaster0_state + attribute \src "ls180.v:4428.2-4464.9" + switch \builder_spimaster0_state + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\main_spimaster27_count_spimaster0_next_value[2:0] 3'000 + assign $0\main_spimaster27_count_spimaster0_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:4432.4-4435.7" + switch \main_spimaster32_clk_fall + attribute \src "ls180.v:4432.8-4432.33" + case 1'1 + assign $0\main_spimaster26_cs_enable[0:0] 1'1 + assign $0\builder_spimaster0_next_state[1:0] 2'10 + case + end + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\main_spimaster25_clk_enable[0:0] 1'1 + assign $0\main_spimaster26_cs_enable[0:0] 1'1 + attribute \src "ls180.v:4440.4-4446.7" + switch \main_spimaster32_clk_fall + attribute \src "ls180.v:4440.8-4440.33" + case 1'1 + assign $0\main_spimaster27_count_spimaster0_next_value[2:0] $add$ls180.v:4441$757_Y + assign $0\main_spimaster27_count_spimaster0_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:4443.5-4445.8" + switch $eq$ls180.v:4443$759_Y + attribute \src "ls180.v:4443.9-4443.68" + case 1'1 + assign $0\builder_spimaster0_next_state[1:0] 2'11 + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 2'11 + assign $0\main_spimaster26_cs_enable[0:0] 1'1 + attribute \src "ls180.v:4450.4-4454.7" + switch \main_spimaster31_clk_rise + attribute \src "ls180.v:4450.8-4450.33" + case 1'1 + assign $0\main_spimaster29_miso_latch[0:0] 1'1 + assign $0\main_spimaster3_irq[0:0] 1'1 + assign $0\builder_spimaster0_next_state[1:0] 2'00 + case + end + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_spimaster2_done[0:0] 1'1 + attribute \src "ls180.v:4458.4-4462.7" + switch \main_spimaster0_start + attribute \src "ls180.v:4458.8-4458.29" + case 1'1 + assign $0\main_spimaster2_done[0:0] 1'0 + assign $0\main_spimaster28_mosi_latch[0:0] 1'1 + assign $0\builder_spimaster0_next_state[1:0] 2'01 + case + end + end + sync always + update \main_spimaster2_done $0\main_spimaster2_done[0:0] + update \main_spimaster3_irq $0\main_spimaster3_irq[0:0] + update \main_spimaster25_clk_enable $0\main_spimaster25_clk_enable[0:0] + update \main_spimaster26_cs_enable $0\main_spimaster26_cs_enable[0:0] + update \main_spimaster28_mosi_latch $0\main_spimaster28_mosi_latch[0:0] + update \main_spimaster29_miso_latch $0\main_spimaster29_miso_latch[0:0] + update \builder_spimaster0_next_state $0\builder_spimaster0_next_state[1:0] + update \main_spimaster27_count_spimaster0_next_value $0\main_spimaster27_count_spimaster0_next_value[2:0] + update \main_spimaster27_count_spimaster0_next_value_ce $0\main_spimaster27_count_spimaster0_next_value_ce[0:0] + end + attribute \src "ls180.v:4476.1-4524.4" + process $proc$ls180.v:4476$764 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_spisdcard_clk_enable[0:0] 1'0 + assign $0\main_spisdcard_cs_enable[0:0] 1'0 + assign $0\main_spisdcard_mosi_latch[0:0] 1'0 + assign $0\main_spisdcard_done0[0:0] 1'0 + assign $0\main_spisdcard_miso_latch[0:0] 1'0 + assign $0\main_spisdcard_irq[0:0] 1'0 + assign { } { } + assign $0\main_spisdcard_count_spimaster1_next_value[2:0] 3'000 + assign $0\main_spisdcard_count_spimaster1_next_value_ce[0:0] 1'0 + assign $0\builder_spimaster1_next_state[1:0] \builder_spimaster1_state + attribute \src "ls180.v:4487.2-4523.9" + switch \builder_spimaster1_state + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\main_spisdcard_count_spimaster1_next_value[2:0] 3'000 + assign $0\main_spisdcard_count_spimaster1_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:4491.4-4494.7" + switch \main_spisdcard_clk_fall + attribute \src "ls180.v:4491.8-4491.31" + case 1'1 + assign $0\main_spisdcard_cs_enable[0:0] 1'1 + assign $0\builder_spimaster1_next_state[1:0] 2'10 + case + end + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\main_spisdcard_clk_enable[0:0] 1'1 + assign $0\main_spisdcard_cs_enable[0:0] 1'1 + attribute \src "ls180.v:4499.4-4505.7" + switch \main_spisdcard_clk_fall + attribute \src "ls180.v:4499.8-4499.31" + case 1'1 + assign $0\main_spisdcard_count_spimaster1_next_value[2:0] $add$ls180.v:4500$765_Y + assign $0\main_spisdcard_count_spimaster1_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:4502.5-4504.8" + switch $eq$ls180.v:4502$767_Y + attribute \src "ls180.v:4502.9-4502.66" + case 1'1 + assign $0\builder_spimaster1_next_state[1:0] 2'11 + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 2'11 + assign $0\main_spisdcard_cs_enable[0:0] 1'1 + attribute \src "ls180.v:4509.4-4513.7" + switch \main_spisdcard_clk_rise + attribute \src "ls180.v:4509.8-4509.31" + case 1'1 + assign $0\main_spisdcard_miso_latch[0:0] 1'1 + assign $0\main_spisdcard_irq[0:0] 1'1 + assign $0\builder_spimaster1_next_state[1:0] 2'00 + case + end + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_spisdcard_done0[0:0] 1'1 + attribute \src "ls180.v:4517.4-4521.7" + switch \main_spisdcard_start0 + attribute \src "ls180.v:4517.8-4517.29" + case 1'1 + assign $0\main_spisdcard_done0[0:0] 1'0 + assign $0\main_spisdcard_mosi_latch[0:0] 1'1 + assign $0\builder_spimaster1_next_state[1:0] 2'01 + case + end + end + sync always + update \main_spisdcard_done0 $0\main_spisdcard_done0[0:0] + update \main_spisdcard_irq $0\main_spisdcard_irq[0:0] + update \main_spisdcard_clk_enable $0\main_spisdcard_clk_enable[0:0] + update \main_spisdcard_cs_enable $0\main_spisdcard_cs_enable[0:0] + update \main_spisdcard_mosi_latch $0\main_spisdcard_mosi_latch[0:0] + update \main_spisdcard_miso_latch $0\main_spisdcard_miso_latch[0:0] + update \builder_spimaster1_next_state $0\builder_spimaster1_next_state[1:0] + update \main_spisdcard_count_spimaster1_next_value $0\main_spisdcard_count_spimaster1_next_value[2:0] + update \main_spisdcard_count_spimaster1_next_value_ce $0\main_spisdcard_count_spimaster1_next_value_ce[0:0] + end + attribute \src "ls180.v:453.12-453.46" + process $proc$ls180.v:453$3229 + assign { } { } + assign $1\main_sdram_interface_wdata[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdram_interface_wdata $1\main_sdram_interface_wdata[15:0] + end + attribute \src "ls180.v:454.11-454.47" + process $proc$ls180.v:454$3230 + assign { } { } + assign $1\main_sdram_interface_wdata_we[1:0] 2'00 + sync always + sync init + update \main_sdram_interface_wdata_we $1\main_sdram_interface_wdata_we[1:0] + end + attribute \src "ls180.v:4556.1-4584.4" + process $proc$ls180.v:4556$789 + assign { } { } + assign $0\main_sdphy_clocker_clk1[0:0] 1'0 + attribute \src "ls180.v:4558.2-4583.9" + switch \main_sdphy_clocker_storage + attribute \src "ls180.v:0.0-0.0" + case 9'000000100 + assign $0\main_sdphy_clocker_clk1[0:0] \main_sdphy_clocker_clks [1] + attribute \src "ls180.v:0.0-0.0" + case 9'000001000 + assign $0\main_sdphy_clocker_clk1[0:0] \main_sdphy_clocker_clks [2] + attribute \src "ls180.v:0.0-0.0" + case 9'000010000 + assign $0\main_sdphy_clocker_clk1[0:0] \main_sdphy_clocker_clks [3] + attribute \src "ls180.v:0.0-0.0" + case 9'000100000 + assign $0\main_sdphy_clocker_clk1[0:0] \main_sdphy_clocker_clks [4] + attribute \src "ls180.v:0.0-0.0" + case 9'001000000 + assign $0\main_sdphy_clocker_clk1[0:0] \main_sdphy_clocker_clks [5] + attribute \src "ls180.v:0.0-0.0" + case 9'010000000 + assign $0\main_sdphy_clocker_clk1[0:0] \main_sdphy_clocker_clks [6] + attribute \src "ls180.v:0.0-0.0" + case 9'100000000 + assign $0\main_sdphy_clocker_clk1[0:0] \main_sdphy_clocker_clks [7] + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_sdphy_clocker_clk1[0:0] \main_sdphy_clocker_clks [0] + end + sync always + update \main_sdphy_clocker_clk1 $0\main_sdphy_clocker_clk1[0:0] + end + attribute \src "ls180.v:456.12-456.45" + process $proc$ls180.v:456$3231 + assign { } { } + assign $1\main_sdram_dfi_p0_address[12:0] 13'0000000000000 + sync always + sync init + update \main_sdram_dfi_p0_address $1\main_sdram_dfi_p0_address[12:0] + end + attribute \src "ls180.v:457.11-457.40" + process $proc$ls180.v:457$3232 + assign { } { } + assign $1\main_sdram_dfi_p0_bank[1:0] 2'00 + sync always + sync init + update \main_sdram_dfi_p0_bank $1\main_sdram_dfi_p0_bank[1:0] + end + attribute \src "ls180.v:458.5-458.35" + process $proc$ls180.v:458$3233 + assign { } { } + assign $1\main_sdram_dfi_p0_cas_n[0:0] 1'1 + sync always + sync init + update \main_sdram_dfi_p0_cas_n $1\main_sdram_dfi_p0_cas_n[0:0] + end + attribute \src "ls180.v:4586.1-4619.4" + process $proc$ls180.v:4586$792 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdphy_init_pads_out_payload_data_o[3:0] 4'0000 + assign $0\main_sdphy_init_pads_out_payload_data_oe[0:0] 1'0 + assign { } { } + assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] 8'00000000 + assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] 1'0 + assign $0\main_sdphy_init_pads_out_payload_clk[0:0] 1'0 + assign $0\main_sdphy_init_pads_out_payload_cmd_o[0:0] 1'0 + assign $0\main_sdphy_init_pads_out_payload_cmd_oe[0:0] 1'0 + assign $0\builder_sdphy_sdphyinit_next_state[0:0] \builder_sdphy_sdphyinit_state + attribute \src "ls180.v:4596.2-4618.9" + switch \builder_sdphy_sdphyinit_state + attribute \src "ls180.v:0.0-0.0" + case 1'1 + assign $0\main_sdphy_init_pads_out_payload_clk[0:0] 1'1 + assign $0\main_sdphy_init_pads_out_payload_cmd_oe[0:0] 1'1 + assign $0\main_sdphy_init_pads_out_payload_cmd_o[0:0] 1'1 + assign $0\main_sdphy_init_pads_out_payload_data_oe[0:0] 1'1 + assign $0\main_sdphy_init_pads_out_payload_data_o[3:0] 4'1111 + attribute \src "ls180.v:4603.4-4609.7" + switch \main_sdphy_init_pads_out_ready + attribute \src "ls180.v:4603.8-4603.38" + case 1'1 + assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] $add$ls180.v:4604$793_Y + assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:4606.5-4608.8" + switch $eq$ls180.v:4606$794_Y + attribute \src "ls180.v:4606.9-4606.41" + case 1'1 + assign $0\builder_sdphy_sdphyinit_next_state[0:0] 1'0 + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] 8'00000000 + assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:4614.4-4616.7" + switch \main_sdphy_init_initialize_re + attribute \src "ls180.v:4614.8-4614.37" + case 1'1 + assign $0\builder_sdphy_sdphyinit_next_state[0:0] 1'1 + case + end + end + sync always + update \main_sdphy_init_pads_out_payload_clk $0\main_sdphy_init_pads_out_payload_clk[0:0] + update \main_sdphy_init_pads_out_payload_cmd_o $0\main_sdphy_init_pads_out_payload_cmd_o[0:0] + update \main_sdphy_init_pads_out_payload_cmd_oe $0\main_sdphy_init_pads_out_payload_cmd_oe[0:0] + update \main_sdphy_init_pads_out_payload_data_o $0\main_sdphy_init_pads_out_payload_data_o[3:0] + update \main_sdphy_init_pads_out_payload_data_oe $0\main_sdphy_init_pads_out_payload_data_oe[0:0] + update \builder_sdphy_sdphyinit_next_state $0\builder_sdphy_sdphyinit_next_state[0:0] + update \main_sdphy_init_count_sdphy_sdphyinit_next_value $0\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] + update \main_sdphy_init_count_sdphy_sdphyinit_next_value_ce $0\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] + end + attribute \src "ls180.v:459.5-459.34" + process $proc$ls180.v:459$3234 + assign { } { } + assign $1\main_sdram_dfi_p0_cs_n[0:0] 1'1 + sync always + sync init + update \main_sdram_dfi_p0_cs_n $1\main_sdram_dfi_p0_cs_n[0:0] + end + attribute \src "ls180.v:460.5-460.35" + process $proc$ls180.v:460$3235 + assign { } { } + assign $1\main_sdram_dfi_p0_ras_n[0:0] 1'1 + sync always + sync init + update \main_sdram_dfi_p0_ras_n $1\main_sdram_dfi_p0_ras_n[0:0] + end + attribute \src "ls180.v:461.5-461.34" + process $proc$ls180.v:461$3236 + assign { } { } + assign $1\main_sdram_dfi_p0_we_n[0:0] 1'1 + sync always + sync init + update \main_sdram_dfi_p0_we_n $1\main_sdram_dfi_p0_we_n[0:0] + end + attribute \src "ls180.v:4620.1-4696.4" + process $proc$ls180.v:4620$795 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdphy_cmdw_done[0:0] 1'0 + assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] 8'00000000 + assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] 1'0 + assign $0\main_sdphy_cmdw_pads_out_payload_clk[0:0] 1'0 + assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] 1'0 + assign $0\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] 1'0 + assign $0\main_sdphy_cmdw_sink_ready[0:0] 1'0 + assign $0\builder_sdphy_sdphycmdw_next_state[1:0] \builder_sdphy_sdphycmdw_state + attribute \src "ls180.v:4630.2-4695.9" + switch \builder_sdphy_sdphycmdw_state + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\main_sdphy_cmdw_pads_out_payload_clk[0:0] 1'1 + assign $0\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] 1'1 + attribute \src "ls180.v:4634.4-4659.11" + switch \main_sdphy_cmdw_count + attribute \src "ls180.v:0.0-0.0" + case 8'00000000 + assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] \main_sdphy_cmdw_sink_payload_data [7] + attribute \src "ls180.v:0.0-0.0" + case 8'00000001 + assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] \main_sdphy_cmdw_sink_payload_data [6] + attribute \src "ls180.v:0.0-0.0" + case 8'00000010 + assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] \main_sdphy_cmdw_sink_payload_data [5] + attribute \src "ls180.v:0.0-0.0" + case 8'00000011 + assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] \main_sdphy_cmdw_sink_payload_data [4] + attribute \src "ls180.v:0.0-0.0" + case 8'00000100 + assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] \main_sdphy_cmdw_sink_payload_data [3] + attribute \src "ls180.v:0.0-0.0" + case 8'00000101 + assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] \main_sdphy_cmdw_sink_payload_data [2] + attribute \src "ls180.v:0.0-0.0" + case 8'00000110 + assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] \main_sdphy_cmdw_sink_payload_data [1] + attribute \src "ls180.v:0.0-0.0" + case 8'00000111 + assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] \main_sdphy_cmdw_sink_payload_data [0] + case + end + attribute \src "ls180.v:4660.4-4671.7" + switch \main_sdphy_cmdw_pads_out_ready + attribute \src "ls180.v:4660.8-4660.38" + case 1'1 + assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] $add$ls180.v:4661$796_Y + assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:4663.5-4670.8" + switch $eq$ls180.v:4663$797_Y + attribute \src "ls180.v:4663.9-4663.40" + case 1'1 + attribute \src "ls180.v:4664.6-4669.9" + switch \main_sdphy_cmdw_sink_last + attribute \src "ls180.v:4664.10-4664.35" + case 1'1 + assign $0\builder_sdphy_sdphycmdw_next_state[1:0] 2'10 + attribute \src "ls180.v:4666.10-4666.14" + case + assign $0\main_sdphy_cmdw_sink_ready[0:0] 1'1 + assign $0\builder_sdphy_sdphycmdw_next_state[1:0] 2'00 + end + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\main_sdphy_cmdw_pads_out_payload_clk[0:0] 1'1 + assign $0\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] 1'1 + assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] 1'1 + attribute \src "ls180.v:4677.4-4684.7" + switch \main_sdphy_cmdw_pads_out_ready + attribute \src "ls180.v:4677.8-4677.38" + case 1'1 + assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] $add$ls180.v:4678$798_Y + assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:4680.5-4683.8" + switch $eq$ls180.v:4680$799_Y + attribute \src "ls180.v:4680.9-4680.40" + case 1'1 + assign $0\main_sdphy_cmdw_sink_ready[0:0] 1'1 + assign $0\builder_sdphy_sdphycmdw_next_state[1:0] 2'00 + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] 8'00000000 + assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:4689.4-4693.7" + switch $and$ls180.v:4689$800_Y + attribute \src "ls180.v:4689.8-4689.69" + case 1'1 + assign $0\builder_sdphy_sdphycmdw_next_state[1:0] 2'01 + attribute \src "ls180.v:4691.8-4691.12" + case + assign $0\main_sdphy_cmdw_done[0:0] 1'1 + end + end + sync always + update \main_sdphy_cmdw_pads_out_payload_clk $0\main_sdphy_cmdw_pads_out_payload_clk[0:0] + update \main_sdphy_cmdw_pads_out_payload_cmd_o $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] + update \main_sdphy_cmdw_pads_out_payload_cmd_oe $0\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] + update \main_sdphy_cmdw_sink_ready $0\main_sdphy_cmdw_sink_ready[0:0] + update \main_sdphy_cmdw_done $0\main_sdphy_cmdw_done[0:0] + update \builder_sdphy_sdphycmdw_next_state $0\builder_sdphy_sdphycmdw_next_state[1:0] + update \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] + update \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] + end + attribute \src "ls180.v:465.5-465.35" + process $proc$ls180.v:465$3237 + assign { } { } + assign $0\main_sdram_dfi_p0_act_n[0:0] 1'1 + sync always + update \main_sdram_dfi_p0_act_n $0\main_sdram_dfi_p0_act_n[0:0] + sync init + end + attribute \src "ls180.v:467.5-467.39" + process $proc$ls180.v:467$3238 + assign { } { } + assign $1\main_sdram_dfi_p0_wrdata_en[0:0] 1'0 + sync always + sync init + update \main_sdram_dfi_p0_wrdata_en $1\main_sdram_dfi_p0_wrdata_en[0:0] + end + attribute \src "ls180.v:469.5-469.39" + process $proc$ls180.v:469$3239 + assign { } { } + assign $1\main_sdram_dfi_p0_rddata_en[0:0] 1'0 + sync always + sync init + update \main_sdram_dfi_p0_rddata_en $1\main_sdram_dfi_p0_rddata_en[0:0] + end + attribute \src "ls180.v:472.5-472.32" + process $proc$ls180.v:472$3240 + assign { } { } + assign $1\main_sdram_cmd_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_cmd_valid $1\main_sdram_cmd_valid[0:0] + end + attribute \src "ls180.v:473.5-473.32" + process $proc$ls180.v:473$3241 + assign { } { } + assign $1\main_sdram_cmd_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_cmd_ready $1\main_sdram_cmd_ready[0:0] + end + attribute \src "ls180.v:4730.1-4823.4" + process $proc$ls180.v:4730$809 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdphy_cmdr_source_valid[0:0] 1'0 + assign $0\main_sdphy_cmdr_source_last[0:0] 1'0 + assign $0\main_sdphy_cmdr_source_payload_data[7:0] 8'00000000 + assign $0\main_sdphy_cmdr_source_payload_status[2:0] 3'000 + assign { } { } + assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] 8'00000000 + assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'0 + assign $0\main_sdphy_cmdr_pads_out_payload_clk[0:0] 1'0 + assign $0\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] 1'0 + assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] 0 + assign $0\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] 1'0 + assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] 1'0 + assign $0\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] 1'0 + assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] 1'0 + assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] 1'0 + assign $0\main_sdphy_cmdr_sink_ready[0:0] 1'0 + assign $0\builder_sdphy_sdphycmdr_next_state[2:0] \builder_sdphy_sdphycmdr_state + attribute \src "ls180.v:4748.2-4822.9" + switch \builder_sdphy_sdphycmdr_state + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\main_sdphy_cmdr_pads_out_payload_clk[0:0] 1'1 + assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] 1'0 + assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] 1'1 + assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] $sub$ls180.v:4756$810_Y + assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] 1'1 + attribute \src "ls180.v:4753.4-4755.7" + switch \main_sdphy_cmdr_cmdr_source_source_valid0 + attribute \src "ls180.v:4753.8-4753.49" + case 1'1 + assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'010 + case + end + attribute \src "ls180.v:4758.4-4761.7" + switch $eq$ls180.v:4758$811_Y + attribute \src "ls180.v:4758.8-4758.41" + case 1'1 + assign $0\main_sdphy_cmdr_sink_ready[0:0] 1'1 + assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'100 + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\main_sdphy_cmdr_pads_out_payload_clk[0:0] 1'1 + assign $0\main_sdphy_cmdr_source_valid[0:0] \main_sdphy_cmdr_cmdr_source_source_valid0 + assign $0\main_sdphy_cmdr_source_payload_status[2:0] 3'000 + assign $0\main_sdphy_cmdr_source_last[0:0] $eq$ls180.v:4767$813_Y + assign $0\main_sdphy_cmdr_source_payload_data[7:0] \main_sdphy_cmdr_cmdr_source_source_payload_data0 + assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] $sub$ls180.v:4784$816_Y + assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] 1'1 + attribute \src "ls180.v:4769.4-4783.7" + switch $and$ls180.v:4769$814_Y + attribute \src "ls180.v:4769.8-4769.69" + case 1'1 + assign $0\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] 1'1 + assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] $add$ls180.v:4771$815_Y + assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'1 + attribute \src "ls180.v:4773.5-4782.8" + switch \main_sdphy_cmdr_source_last + attribute \src "ls180.v:4773.9-4773.36" + case 1'1 + assign $0\main_sdphy_cmdr_sink_ready[0:0] 1'1 + attribute \src "ls180.v:4775.6-4781.9" + switch \main_sdphy_cmdr_sink_last + attribute \src "ls180.v:4775.10-4775.35" + case 1'1 + assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] 8'00000000 + assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'1 + assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'011 + attribute \src "ls180.v:4779.10-4779.14" + case + assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'000 + end + case + end + case + end + attribute \src "ls180.v:4786.4-4789.7" + switch $eq$ls180.v:4786$817_Y + attribute \src "ls180.v:4786.8-4786.41" + case 1'1 + assign $0\main_sdphy_cmdr_sink_ready[0:0] 1'1 + assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'100 + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\main_sdphy_cmdr_pads_out_payload_clk[0:0] 1'1 + assign $0\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] 1'1 + assign $0\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] 1'1 + attribute \src "ls180.v:4795.4-4801.7" + switch \main_sdphy_cmdr_pads_out_ready + attribute \src "ls180.v:4795.8-4795.38" + case 1'1 + assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] $add$ls180.v:4796$818_Y + assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'1 + attribute \src "ls180.v:4798.5-4800.8" + switch $eq$ls180.v:4798$819_Y + attribute \src "ls180.v:4798.9-4798.40" + case 1'1 + assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'000 + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\main_sdphy_cmdr_source_valid[0:0] 1'1 + assign $0\main_sdphy_cmdr_source_payload_status[2:0] 3'001 + assign $0\main_sdphy_cmdr_source_last[0:0] 1'1 + attribute \src "ls180.v:4807.4-4809.7" + switch $and$ls180.v:4807$820_Y + attribute \src "ls180.v:4807.8-4807.69" + case 1'1 + assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'000 + case + end + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] 8'00000000 + assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'1 + assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] 500000 + assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] 1'1 + attribute \src "ls180.v:4816.4-4820.7" + switch $and$ls180.v:4816$822_Y + attribute \src "ls180.v:4816.8-4816.94" + case 1'1 + assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] 1'1 + assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] 1'1 + assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'001 + case + end + end + sync always + update \main_sdphy_cmdr_pads_out_payload_clk $0\main_sdphy_cmdr_pads_out_payload_clk[0:0] + update \main_sdphy_cmdr_pads_out_payload_cmd_o $0\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] + update \main_sdphy_cmdr_pads_out_payload_cmd_oe $0\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] + update \main_sdphy_cmdr_sink_ready $0\main_sdphy_cmdr_sink_ready[0:0] + update \main_sdphy_cmdr_source_valid $0\main_sdphy_cmdr_source_valid[0:0] + update \main_sdphy_cmdr_source_last $0\main_sdphy_cmdr_source_last[0:0] + update \main_sdphy_cmdr_source_payload_data $0\main_sdphy_cmdr_source_payload_data[7:0] + update \main_sdphy_cmdr_source_payload_status $0\main_sdphy_cmdr_source_payload_status[2:0] + update \main_sdphy_cmdr_cmdr_source_source_ready0 $0\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] + update \builder_sdphy_sdphycmdr_next_state $0\builder_sdphy_sdphycmdr_next_state[2:0] + update \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0 $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] + update \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0 $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] + update \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1 $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] + update \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1 $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] + update \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2 $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] + update \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2 $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] + end + attribute \src "ls180.v:474.5-474.31" + process $proc$ls180.v:474$3242 + assign { } { } + assign $1\main_sdram_cmd_last[0:0] 1'0 + sync always + sync init + update \main_sdram_cmd_last $1\main_sdram_cmd_last[0:0] + end + attribute \src "ls180.v:475.12-475.44" + process $proc$ls180.v:475$3243 + assign { } { } + assign $1\main_sdram_cmd_payload_a[12:0] 13'0000000000000 + sync always + sync init + update \main_sdram_cmd_payload_a $1\main_sdram_cmd_payload_a[12:0] + end + attribute \src "ls180.v:476.11-476.43" + process $proc$ls180.v:476$3244 + assign { } { } + assign $1\main_sdram_cmd_payload_ba[1:0] 2'00 + sync always + sync init + update \main_sdram_cmd_payload_ba $1\main_sdram_cmd_payload_ba[1:0] + end + attribute \src "ls180.v:477.5-477.38" + process $proc$ls180.v:477$3245 + assign { } { } + assign $1\main_sdram_cmd_payload_cas[0:0] 1'0 + sync always + sync init + update \main_sdram_cmd_payload_cas $1\main_sdram_cmd_payload_cas[0:0] + end + attribute \src "ls180.v:478.5-478.38" + process $proc$ls180.v:478$3246 + assign { } { } + assign $1\main_sdram_cmd_payload_ras[0:0] 1'0 + sync always + sync init + update \main_sdram_cmd_payload_ras $1\main_sdram_cmd_payload_ras[0:0] + end + attribute \src "ls180.v:479.5-479.37" + process $proc$ls180.v:479$3247 + assign { } { } + assign $1\main_sdram_cmd_payload_we[0:0] 1'0 + sync always + sync init + update \main_sdram_cmd_payload_we $1\main_sdram_cmd_payload_we[0:0] + end + attribute \src "ls180.v:480.5-480.42" + process $proc$ls180.v:480$3248 + assign { } { } + assign $0\main_sdram_cmd_payload_is_read[0:0] 1'0 + sync always + update \main_sdram_cmd_payload_is_read $0\main_sdram_cmd_payload_is_read[0:0] + sync init + end + attribute \src "ls180.v:481.5-481.43" + process $proc$ls180.v:481$3249 + assign { } { } + assign $0\main_sdram_cmd_payload_is_write[0:0] 1'0 + sync always + update \main_sdram_cmd_payload_is_write $0\main_sdram_cmd_payload_is_write[0:0] + sync init + end + attribute \src "ls180.v:4857.1-4884.4" + process $proc$ls180.v:4857$830 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] 1'0 + assign $0\main_sdphy_dataw_crcr_source_source_ready0[0:0] 1'0 + assign $0\main_sdphy_dataw_valid[0:0] 1'0 + assign $0\main_sdphy_dataw_error[0:0] 1'0 + assign { } { } + assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] 1'0 + assign $0\builder_sdphy_sdphycrcr_next_state[0:0] \builder_sdphy_sdphycrcr_state + attribute \src "ls180.v:4865.2-4883.9" + switch \builder_sdphy_sdphycrcr_state + attribute \src "ls180.v:0.0-0.0" + case 1'1 + assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] 1'0 + assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] 1'1 + assign $0\main_sdphy_dataw_crcr_source_source_ready0[0:0] 1'1 + attribute \src "ls180.v:4870.4-4874.7" + switch \main_sdphy_dataw_crcr_source_source_valid0 + attribute \src "ls180.v:4870.8-4870.50" + case 1'1 + assign $0\main_sdphy_dataw_valid[0:0] $ne$ls180.v:4871$831_Y + assign $0\main_sdphy_dataw_error[0:0] $eq$ls180.v:4872$832_Y + assign $0\builder_sdphy_sdphycrcr_next_state[0:0] 1'0 + case + end + attribute \src "ls180.v:0.0-0.0" + case + attribute \src "ls180.v:4877.4-4881.7" + switch \main_sdphy_dataw_start + attribute \src "ls180.v:4877.8-4877.30" + case 1'1 + assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] 1'1 + assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] 1'1 + assign $0\builder_sdphy_sdphycrcr_next_state[0:0] 1'1 + case + end + end + sync always + update \main_sdphy_dataw_valid $0\main_sdphy_dataw_valid[0:0] + update \main_sdphy_dataw_error $0\main_sdphy_dataw_error[0:0] + update \main_sdphy_dataw_crcr_source_source_ready0 $0\main_sdphy_dataw_crcr_source_source_ready0[0:0] + update \builder_sdphy_sdphycrcr_next_state $0\builder_sdphy_sdphycrcr_next_state[0:0] + update \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] + update \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] + end + attribute \src "ls180.v:487.11-487.44" + process $proc$ls180.v:487$3250 + assign { } { } + assign $1\main_sdram_timer_count1[9:0] 10'1100001101 + sync always + sync init + update \main_sdram_timer_count1 $1\main_sdram_timer_count1[9:0] + end + attribute \src "ls180.v:4885.1-4957.4" + process $proc$ls180.v:4885$833 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'0 + assign $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] 4'0000 + assign $0\main_sdphy_dataw_pads_out_payload_data_oe[0:0] 1'0 + assign $0\main_sdphy_dataw_sink_ready[0:0] 1'0 + assign { } { } + assign $0\main_sdphy_dataw_start[0:0] 1'0 + assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] 8'00000000 + assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] 1'0 + assign $0\main_sdphy_dataw_stop[0:0] 1'0 + assign $0\builder_sdphy_fsm_next_state[2:0] \builder_sdphy_fsm_state + attribute \src "ls180.v:4896.2-4956.9" + switch \builder_sdphy_fsm_state + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'1 + assign $0\main_sdphy_dataw_pads_out_payload_data_oe[0:0] 1'1 + assign $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] 4'0000 + attribute \src "ls180.v:4901.4-4903.7" + switch \main_sdphy_dataw_pads_out_ready + attribute \src "ls180.v:4901.8-4901.39" + case 1'1 + assign $0\builder_sdphy_fsm_next_state[2:0] 3'010 + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\main_sdphy_dataw_stop[0:0] $not$ls180.v:4906$834_Y + assign $0\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'1 + assign $0\main_sdphy_dataw_pads_out_payload_data_oe[0:0] 1'1 + attribute \src "ls180.v:4909.4-4916.11" + switch \main_sdphy_dataw_count + attribute \src "ls180.v:0.0-0.0" + case 8'00000000 + assign $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] \main_sdphy_dataw_sink_payload_data [7:4] + attribute \src "ls180.v:0.0-0.0" + case 8'00000001 + assign $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] \main_sdphy_dataw_sink_payload_data [3:0] + case + end + attribute \src "ls180.v:4917.4-4929.7" + switch \main_sdphy_dataw_pads_out_ready + attribute \src "ls180.v:4917.8-4917.39" + case 1'1 + assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] $add$ls180.v:4918$835_Y + assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:4920.5-4928.8" + switch $eq$ls180.v:4920$836_Y + attribute \src "ls180.v:4920.9-4920.41" + case 1'1 + assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] 8'00000000 + assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:4923.6-4927.9" + switch \main_sdphy_dataw_sink_last + attribute \src "ls180.v:4923.10-4923.36" + case 1'1 + assign $0\builder_sdphy_fsm_next_state[2:0] 3'011 + attribute \src "ls180.v:4925.10-4925.14" + case + assign $0\main_sdphy_dataw_sink_ready[0:0] 1'1 + end + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'1 + assign $0\main_sdphy_dataw_pads_out_payload_data_oe[0:0] 1'1 + assign $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] 4'1111 + attribute \src "ls180.v:4935.4-4938.7" + switch \main_sdphy_dataw_pads_out_ready + attribute \src "ls180.v:4935.8-4935.39" + case 1'1 + assign $0\main_sdphy_dataw_start[0:0] 1'1 + assign $0\builder_sdphy_fsm_next_state[2:0] 3'100 + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'1 + attribute \src "ls180.v:4942.4-4947.7" + switch \main_sdphy_dataw_pads_out_ready + attribute \src "ls180.v:4942.8-4942.39" + case 1'1 + attribute \src "ls180.v:4943.5-4946.8" + switch \main_sdphy_dataw_pads_in_payload_data_i [0] + attribute \src "ls180.v:4943.9-4943.51" + case 1'1 + assign $0\main_sdphy_dataw_sink_ready[0:0] 1'1 + assign $0\builder_sdphy_fsm_next_state[2:0] 3'000 + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] 8'00000000 + assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:4952.4-4954.7" + switch $and$ls180.v:4952$837_Y + attribute \src "ls180.v:4952.8-4952.71" + case 1'1 + assign $0\builder_sdphy_fsm_next_state[2:0] 3'001 + case + end + end + sync always + update \main_sdphy_dataw_pads_out_payload_clk $0\main_sdphy_dataw_pads_out_payload_clk[0:0] + update \main_sdphy_dataw_pads_out_payload_data_o $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] + update \main_sdphy_dataw_pads_out_payload_data_oe $0\main_sdphy_dataw_pads_out_payload_data_oe[0:0] + update \main_sdphy_dataw_sink_ready $0\main_sdphy_dataw_sink_ready[0:0] + update \main_sdphy_dataw_stop $0\main_sdphy_dataw_stop[0:0] + update \main_sdphy_dataw_start $0\main_sdphy_dataw_start[0:0] + update \builder_sdphy_fsm_next_state $0\builder_sdphy_fsm_next_state[2:0] + update \main_sdphy_dataw_count_sdphy_fsm_next_value $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] + update \main_sdphy_dataw_count_sdphy_fsm_next_value_ce $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] + end + attribute \src "ls180.v:489.5-489.38" + process $proc$ls180.v:489$3251 + assign { } { } + assign $1\main_sdram_postponer_req_o[0:0] 1'0 + sync always + sync init + update \main_sdram_postponer_req_o $1\main_sdram_postponer_req_o[0:0] + end + attribute \src "ls180.v:490.5-490.38" + process $proc$ls180.v:490$3252 + assign { } { } + assign $1\main_sdram_postponer_count[0:0] 1'0 + sync always + sync init + update \main_sdram_postponer_count $1\main_sdram_postponer_count[0:0] + end + attribute \src "ls180.v:491.5-491.39" + process $proc$ls180.v:491$3253 + assign { } { } + assign $1\main_sdram_sequencer_start0[0:0] 1'0 + sync always + sync init + update \main_sdram_sequencer_start0 $1\main_sdram_sequencer_start0[0:0] + end + attribute \src "ls180.v:494.5-494.38" + process $proc$ls180.v:494$3254 + assign { } { } + assign $1\main_sdram_sequencer_done1[0:0] 1'0 + sync always + sync init + update \main_sdram_sequencer_done1 $1\main_sdram_sequencer_done1[0:0] + end + attribute \src "ls180.v:495.11-495.46" + process $proc$ls180.v:495$3255 + assign { } { } + assign $1\main_sdram_sequencer_counter[3:0] 4'0000 + sync always + sync init + update \main_sdram_sequencer_counter $1\main_sdram_sequencer_counter[3:0] + end + attribute \src "ls180.v:496.5-496.38" + process $proc$ls180.v:496$3256 + assign { } { } + assign $1\main_sdram_sequencer_count[0:0] 1'0 + sync always + sync init + update \main_sdram_sequencer_count $1\main_sdram_sequencer_count[0:0] + end + attribute \src "ls180.v:4991.1-5092.4" + process $proc$ls180.v:4991$845 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] 1'0 + assign $0\main_sdphy_datar_source_payload_status[2:0] 3'000 + assign $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] 1'0 + assign $0\main_sdphy_datar_datar_source_source_ready0[0:0] 1'0 + assign $0\main_sdphy_datar_stop[0:0] 1'0 + assign $0\main_sdphy_datar_source_payload_data[7:0] 8'00000000 + assign $0\main_sdphy_datar_sink_ready[0:0] 1'0 + assign { } { } + assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] 10'0000000000 + assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'0 + assign $0\main_sdphy_datar_source_valid[0:0] 1'0 + assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] 0 + assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] 1'0 + assign $0\main_sdphy_datar_source_last[0:0] 1'0 + assign $0\main_sdphy_datar_pads_out_payload_clk[0:0] 1'0 + assign $0\builder_sdphy_sdphydatar_next_state[2:0] \builder_sdphy_sdphydatar_state + attribute \src "ls180.v:5008.2-5091.9" + switch \builder_sdphy_sdphydatar_state + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\main_sdphy_datar_pads_out_payload_clk[0:0] 1'1 + assign $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] 1'0 + assign $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] 1'1 + assign { } { } + assign { } { } + assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] $sub$ls180.v:5018$847_Y + assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] 1'1 + attribute \src "ls180.v:5015.4-5017.7" + switch \main_sdphy_datar_datar_source_source_valid0 + attribute \src "ls180.v:5015.8-5015.51" + case 1'1 + assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'010 + case + end + attribute \src "ls180.v:5020.4-5023.7" + switch $eq$ls180.v:5020$848_Y + attribute \src "ls180.v:5020.8-5020.42" + case 1'1 + assign $0\main_sdphy_datar_sink_ready[0:0] 1'1 + assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'100 + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\main_sdphy_datar_pads_out_payload_clk[0:0] 1'1 + assign $0\main_sdphy_datar_source_valid[0:0] \main_sdphy_datar_datar_source_source_valid0 + assign $0\main_sdphy_datar_source_payload_status[2:0] 3'000 + assign $0\main_sdphy_datar_source_last[0:0] $eq$ls180.v:5029$851_Y + assign $0\main_sdphy_datar_source_payload_data[7:0] \main_sdphy_datar_datar_source_source_payload_data0 + assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] $sub$ls180.v:5050$853_Y + assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] 1'1 + attribute \src "ls180.v:5031.4-5049.7" + switch \main_sdphy_datar_source_valid + attribute \src "ls180.v:5031.8-5031.37" + case 1'1 + attribute \src "ls180.v:5032.5-5048.8" + switch \main_sdphy_datar_source_ready + attribute \src "ls180.v:5032.9-5032.38" + case 1'1 + assign $0\main_sdphy_datar_datar_source_source_ready0[0:0] 1'1 + assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] $add$ls180.v:5034$852_Y + assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'1 + attribute \src "ls180.v:5036.6-5045.9" + switch \main_sdphy_datar_source_last + attribute \src "ls180.v:5036.10-5036.38" + case 1'1 + assign $0\main_sdphy_datar_sink_ready[0:0] 1'1 + attribute \src "ls180.v:5038.7-5044.10" + switch \main_sdphy_datar_sink_last + attribute \src "ls180.v:5038.11-5038.37" + case 1'1 + assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] 10'0000000000 + assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'1 + assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'011 + attribute \src "ls180.v:5042.11-5042.15" + case + assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'000 + end + case + end + attribute \src "ls180.v:5046.9-5046.13" + case + assign $0\main_sdphy_datar_stop[0:0] 1'1 + end + case + end + attribute \src "ls180.v:5052.4-5055.7" + switch $eq$ls180.v:5052$854_Y + attribute \src "ls180.v:5052.8-5052.42" + case 1'1 + assign $0\main_sdphy_datar_sink_ready[0:0] 1'1 + assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'100 + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\main_sdphy_datar_pads_out_payload_clk[0:0] 1'1 + attribute \src "ls180.v:5059.4-5065.7" + switch \main_sdphy_datar_pads_out_ready + attribute \src "ls180.v:5059.8-5059.39" + case 1'1 + assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] $add$ls180.v:5060$855_Y + assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'1 + attribute \src "ls180.v:5062.5-5064.8" + switch $eq$ls180.v:5062$856_Y + attribute \src "ls180.v:5062.9-5062.42" + case 1'1 + assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'000 + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\main_sdphy_datar_source_valid[0:0] 1'1 + assign $0\main_sdphy_datar_source_payload_status[2:0] 3'001 + assign $0\main_sdphy_datar_source_last[0:0] 1'1 + attribute \src "ls180.v:5071.4-5073.7" + switch $and$ls180.v:5071$857_Y + attribute \src "ls180.v:5071.8-5071.71" + case 1'1 + assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'000 + case + end + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] 10'0000000000 + assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'1 + attribute \src "ls180.v:5078.4-5089.7" + switch $and$ls180.v:5078$858_Y + attribute \src "ls180.v:5078.8-5078.71" + case 1'1 + assign $0\main_sdphy_datar_pads_out_payload_clk[0:0] 1'1 + attribute \src "ls180.v:5080.5-5088.8" + switch \main_sdphy_datar_pads_out_ready + attribute \src "ls180.v:5080.9-5080.40" + case 1'1 + assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] 500000 + assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] 1'1 + assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] 10'0000000000 + assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'1 + assign $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] 1'1 + assign $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] 1'1 + assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'001 + case + end + case + end + end + sync always + update \main_sdphy_datar_pads_out_payload_clk $0\main_sdphy_datar_pads_out_payload_clk[0:0] + update \main_sdphy_datar_sink_ready $0\main_sdphy_datar_sink_ready[0:0] + update \main_sdphy_datar_source_valid $0\main_sdphy_datar_source_valid[0:0] + update \main_sdphy_datar_source_last $0\main_sdphy_datar_source_last[0:0] + update \main_sdphy_datar_source_payload_data $0\main_sdphy_datar_source_payload_data[7:0] + update \main_sdphy_datar_source_payload_status $0\main_sdphy_datar_source_payload_status[2:0] + update \main_sdphy_datar_stop $0\main_sdphy_datar_stop[0:0] + update \main_sdphy_datar_datar_source_source_ready0 $0\main_sdphy_datar_datar_source_source_ready0[0:0] + update \builder_sdphy_sdphydatar_next_state $0\builder_sdphy_sdphydatar_next_state[2:0] + update \main_sdphy_datar_count_sdphy_sdphydatar_next_value0 $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] + update \main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0 $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] + update \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1 $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] + update \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1 $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] + update \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2 $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] + update \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2 $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] + end + attribute \src "ls180.v:502.5-502.51" + process $proc$ls180.v:502$3257 + assign { } { } + assign $1\main_sdram_bankmachine0_req_wdata_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_req_wdata_ready $1\main_sdram_bankmachine0_req_wdata_ready[0:0] + end + attribute \src "ls180.v:503.5-503.51" + process $proc$ls180.v:503$3258 + assign { } { } + assign $1\main_sdram_bankmachine0_req_rdata_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_req_rdata_valid $1\main_sdram_bankmachine0_req_rdata_valid[0:0] + end + attribute \src "ls180.v:505.5-505.47" + process $proc$ls180.v:505$3259 + assign { } { } + assign $1\main_sdram_bankmachine0_refresh_gnt[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_refresh_gnt $1\main_sdram_bankmachine0_refresh_gnt[0:0] + end + attribute \src "ls180.v:506.5-506.45" + process $proc$ls180.v:506$3260 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_cmd_valid $1\main_sdram_bankmachine0_cmd_valid[0:0] + end + attribute \src "ls180.v:507.5-507.45" + process $proc$ls180.v:507$3261 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_cmd_ready $1\main_sdram_bankmachine0_cmd_ready[0:0] + end + attribute \src "ls180.v:508.12-508.57" + process $proc$ls180.v:508$3262 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_payload_a[12:0] 13'0000000000000 + sync always + sync init + update \main_sdram_bankmachine0_cmd_payload_a $1\main_sdram_bankmachine0_cmd_payload_a[12:0] + end + attribute \src "ls180.v:510.5-510.51" + process $proc$ls180.v:510$3263 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_payload_cas[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_cmd_payload_cas $1\main_sdram_bankmachine0_cmd_payload_cas[0:0] + end + attribute \src "ls180.v:511.5-511.51" + process $proc$ls180.v:511$3264 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_payload_ras[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_cmd_payload_ras $1\main_sdram_bankmachine0_cmd_payload_ras[0:0] + end + attribute \src "ls180.v:512.5-512.50" + process $proc$ls180.v:512$3265 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_payload_we[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_cmd_payload_we $1\main_sdram_bankmachine0_cmd_payload_we[0:0] + end + attribute \src "ls180.v:513.5-513.54" + process $proc$ls180.v:513$3266 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_cmd_payload_is_cmd $1\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] + end + attribute \src "ls180.v:514.5-514.55" + process $proc$ls180.v:514$3267 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_payload_is_read[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_cmd_payload_is_read $1\main_sdram_bankmachine0_cmd_payload_is_read[0:0] + end + attribute \src "ls180.v:515.5-515.56" + process $proc$ls180.v:515$3268 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_payload_is_write[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_cmd_payload_is_write $1\main_sdram_bankmachine0_cmd_payload_is_write[0:0] + end + attribute \src "ls180.v:5150.1-5157.4" + process $proc$ls180.v:5150$980 + assign { } { } + assign $0\main_sdcore_crc7_inserter_crc[6:0] 7'0000000 + attribute \src "ls180.v:5152.2-5156.5" + switch \main_sdcore_crc7_inserter_enable + attribute \src "ls180.v:5152.6-5152.38" + case 1'1 + assign $0\main_sdcore_crc7_inserter_crc[6:0] \main_sdcore_crc7_inserter_crcreg40 + attribute \src "ls180.v:5154.6-5154.10" + case + assign $0\main_sdcore_crc7_inserter_crc[6:0] \main_sdcore_crc7_inserter_crcreg0 + end + sync always + update \main_sdcore_crc7_inserter_crc $0\main_sdcore_crc7_inserter_crc[6:0] + end + attribute \src "ls180.v:516.5-516.50" + process $proc$ls180.v:516$3269 + assign { } { } + assign $1\main_sdram_bankmachine0_auto_precharge[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_auto_precharge $1\main_sdram_bankmachine0_auto_precharge[0:0] + end + attribute \src "ls180.v:5172.1-5179.4" + process $proc$ls180.v:5172$1003 + assign { } { } + assign $0\main_sdcore_crc16_inserter_crc0_crc[15:0] 16'0000000000000000 + attribute \src "ls180.v:5174.2-5178.5" + switch \main_sdcore_crc16_inserter_crc0_enable + attribute \src "ls180.v:5174.6-5174.44" + case 1'1 + assign $0\main_sdcore_crc16_inserter_crc0_crc[15:0] \main_sdcore_crc16_inserter_crc0_crcreg2 + attribute \src "ls180.v:5176.6-5176.10" + case + assign $0\main_sdcore_crc16_inserter_crc0_crc[15:0] \main_sdcore_crc16_inserter_crc0_crcreg0 + end + sync always + update \main_sdcore_crc16_inserter_crc0_crc $0\main_sdcore_crc16_inserter_crc0_crc[15:0] + end + attribute \src "ls180.v:5182.1-5189.4" + process $proc$ls180.v:5182$1014 + assign { } { } + assign $0\main_sdcore_crc16_inserter_crc1_crc[15:0] 16'0000000000000000 + attribute \src "ls180.v:5184.2-5188.5" + switch \main_sdcore_crc16_inserter_crc1_enable + attribute \src "ls180.v:5184.6-5184.44" + case 1'1 + assign $0\main_sdcore_crc16_inserter_crc1_crc[15:0] \main_sdcore_crc16_inserter_crc1_crcreg2 + attribute \src "ls180.v:5186.6-5186.10" + case + assign $0\main_sdcore_crc16_inserter_crc1_crc[15:0] \main_sdcore_crc16_inserter_crc1_crcreg0 + end + sync always + update \main_sdcore_crc16_inserter_crc1_crc $0\main_sdcore_crc16_inserter_crc1_crc[15:0] + end + attribute \src "ls180.v:519.5-519.67" + process $proc$ls180.v:519$3270 + assign { } { } + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first[0:0] 1'0 + sync always + update \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first[0:0] + sync init + end + attribute \src "ls180.v:5192.1-5199.4" + process $proc$ls180.v:5192$1025 + assign { } { } + assign $0\main_sdcore_crc16_inserter_crc2_crc[15:0] 16'0000000000000000 + attribute \src "ls180.v:5194.2-5198.5" + switch \main_sdcore_crc16_inserter_crc2_enable + attribute \src "ls180.v:5194.6-5194.44" + case 1'1 + assign $0\main_sdcore_crc16_inserter_crc2_crc[15:0] \main_sdcore_crc16_inserter_crc2_crcreg2 + attribute \src "ls180.v:5196.6-5196.10" + case + assign $0\main_sdcore_crc16_inserter_crc2_crc[15:0] \main_sdcore_crc16_inserter_crc2_crcreg0 + end + sync always + update \main_sdcore_crc16_inserter_crc2_crc $0\main_sdcore_crc16_inserter_crc2_crc[15:0] + end + attribute \src "ls180.v:520.5-520.66" + process $proc$ls180.v:520$3271 + assign { } { } + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last[0:0] 1'0 + sync always + update \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last[0:0] + sync init + end + attribute \src "ls180.v:5202.1-5209.4" + process $proc$ls180.v:5202$1036 + assign { } { } + assign $0\main_sdcore_crc16_inserter_crc3_crc[15:0] 16'0000000000000000 + attribute \src "ls180.v:5204.2-5208.5" + switch \main_sdcore_crc16_inserter_crc3_enable + attribute \src "ls180.v:5204.6-5204.44" + case 1'1 + assign $0\main_sdcore_crc16_inserter_crc3_crc[15:0] \main_sdcore_crc16_inserter_crc3_crcreg2 + attribute \src "ls180.v:5206.6-5206.10" + case + assign $0\main_sdcore_crc16_inserter_crc3_crc[15:0] \main_sdcore_crc16_inserter_crc3_crcreg0 + end + sync always + update \main_sdcore_crc16_inserter_crc3_crc $0\main_sdcore_crc16_inserter_crc3_crc[15:0] + end + attribute \src "ls180.v:5210.1-5289.4" + process $proc$ls180.v:5210$1037 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] 3'000 + assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] 1'0 + assign { } { } + assign $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_inserter_sink_ready[0:0] 1'0 + assign $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] 1'0 + assign $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] 1'0 + assign $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] 1'0 + assign $0\main_sdcore_crc16_inserter_source_valid[0:0] 1'0 + assign $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] 1'0 + assign $0\main_sdcore_crc16_inserter_source_last[0:0] 1'0 + assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] 8'00000000 + assign $0\builder_sdcore_crcupstreaminserter_next_state[0:0] \builder_sdcore_crcupstreaminserter_state + attribute \src "ls180.v:5227.2-5288.9" + switch \builder_sdcore_crcupstreaminserter_state + attribute \src "ls180.v:0.0-0.0" + case 1'1 + assign $0\main_sdcore_crc16_inserter_sink_ready[0:0] 1'0 + assign $0\main_sdcore_crc16_inserter_source_valid[0:0] 1'1 + attribute \src "ls180.v:5231.4-5233.7" + switch $eq$ls180.v:5231$1038_Y + attribute \src "ls180.v:5231.8-5231.48" + case 1'1 + assign $0\main_sdcore_crc16_inserter_source_last[0:0] 1'1 + case + end + attribute \src "ls180.v:5234.4-5259.11" + switch \main_sdcore_crc16_inserter_cnt + attribute \src "ls180.v:0.0-0.0" + case 3'000 + assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] { \main_sdcore_crc16_inserter_crctmp3 [15] \main_sdcore_crc16_inserter_crctmp2 [15] \main_sdcore_crc16_inserter_crctmp1 [15] \main_sdcore_crc16_inserter_crctmp0 [15] \main_sdcore_crc16_inserter_crctmp3 [14] \main_sdcore_crc16_inserter_crctmp2 [14] \main_sdcore_crc16_inserter_crctmp1 [14] \main_sdcore_crc16_inserter_crctmp0 [14] } + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] { \main_sdcore_crc16_inserter_crctmp3 [13] \main_sdcore_crc16_inserter_crctmp2 [13] \main_sdcore_crc16_inserter_crctmp1 [13] \main_sdcore_crc16_inserter_crctmp0 [13] \main_sdcore_crc16_inserter_crctmp3 [12] \main_sdcore_crc16_inserter_crctmp2 [12] \main_sdcore_crc16_inserter_crctmp1 [12] \main_sdcore_crc16_inserter_crctmp0 [12] } + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] { \main_sdcore_crc16_inserter_crctmp3 [11] \main_sdcore_crc16_inserter_crctmp2 [11] \main_sdcore_crc16_inserter_crctmp1 [11] \main_sdcore_crc16_inserter_crctmp0 [11] \main_sdcore_crc16_inserter_crctmp3 [10] \main_sdcore_crc16_inserter_crctmp2 [10] \main_sdcore_crc16_inserter_crctmp1 [10] \main_sdcore_crc16_inserter_crctmp0 [10] } + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] { \main_sdcore_crc16_inserter_crctmp3 [9] \main_sdcore_crc16_inserter_crctmp2 [9] \main_sdcore_crc16_inserter_crctmp1 [9] \main_sdcore_crc16_inserter_crctmp0 [9] \main_sdcore_crc16_inserter_crctmp3 [8] \main_sdcore_crc16_inserter_crctmp2 [8] \main_sdcore_crc16_inserter_crctmp1 [8] \main_sdcore_crc16_inserter_crctmp0 [8] } + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] { \main_sdcore_crc16_inserter_crctmp3 [7] \main_sdcore_crc16_inserter_crctmp2 [7] \main_sdcore_crc16_inserter_crctmp1 [7] \main_sdcore_crc16_inserter_crctmp0 [7] \main_sdcore_crc16_inserter_crctmp3 [6] \main_sdcore_crc16_inserter_crctmp2 [6] \main_sdcore_crc16_inserter_crctmp1 [6] \main_sdcore_crc16_inserter_crctmp0 [6] } + attribute \src "ls180.v:0.0-0.0" + case 3'101 + assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] { \main_sdcore_crc16_inserter_crctmp3 [5] \main_sdcore_crc16_inserter_crctmp2 [5] \main_sdcore_crc16_inserter_crctmp1 [5] \main_sdcore_crc16_inserter_crctmp0 [5] \main_sdcore_crc16_inserter_crctmp3 [4] \main_sdcore_crc16_inserter_crctmp2 [4] \main_sdcore_crc16_inserter_crctmp1 [4] \main_sdcore_crc16_inserter_crctmp0 [4] } + attribute \src "ls180.v:0.0-0.0" + case 3'110 + assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] { \main_sdcore_crc16_inserter_crctmp3 [3] \main_sdcore_crc16_inserter_crctmp2 [3] \main_sdcore_crc16_inserter_crctmp1 [3] \main_sdcore_crc16_inserter_crctmp0 [3] \main_sdcore_crc16_inserter_crctmp3 [2] \main_sdcore_crc16_inserter_crctmp2 [2] \main_sdcore_crc16_inserter_crctmp1 [2] \main_sdcore_crc16_inserter_crctmp0 [2] } + attribute \src "ls180.v:0.0-0.0" + case 3'111 + assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] { \main_sdcore_crc16_inserter_crctmp3 [1] \main_sdcore_crc16_inserter_crctmp2 [1] \main_sdcore_crc16_inserter_crctmp1 [1] \main_sdcore_crc16_inserter_crctmp0 [1] \main_sdcore_crc16_inserter_crctmp3 [0] \main_sdcore_crc16_inserter_crctmp2 [0] \main_sdcore_crc16_inserter_crctmp1 [0] \main_sdcore_crc16_inserter_crctmp0 [0] } + case + end + attribute \src "ls180.v:5260.4-5267.7" + switch \main_sdcore_crc16_inserter_source_ready + attribute \src "ls180.v:5260.8-5260.47" + case 1'1 + attribute \src "ls180.v:5261.5-5266.8" + switch $eq$ls180.v:5261$1039_Y + attribute \src "ls180.v:5261.9-5261.49" + case 1'1 + assign $0\builder_sdcore_crcupstreaminserter_next_state[0:0] 1'0 + attribute \src "ls180.v:5263.9-5263.13" + case + assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] $add$ls180.v:5264$1040_Y + assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] 1'1 + end + case + end + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] \main_sdcore_crc16_inserter_sink_payload_data + assign $0\main_sdcore_crc16_inserter_source_valid[0:0] \main_sdcore_crc16_inserter_sink_valid + assign $0\main_sdcore_crc16_inserter_sink_ready[0:0] \main_sdcore_crc16_inserter_source_ready + assign $0\main_sdcore_crc16_inserter_source_last[0:0] 1'0 + assign $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] \main_sdcore_crc16_inserter_crc0_crc + assign $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] 1'1 + assign $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] \main_sdcore_crc16_inserter_crc1_crc + assign $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] 1'1 + assign $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] \main_sdcore_crc16_inserter_crc2_crc + assign $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] 1'1 + assign $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] \main_sdcore_crc16_inserter_crc3_crc + assign $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] 1'1 + attribute \src "ls180.v:5282.4-5286.7" + switch $and$ls180.v:5282$1042_Y + attribute \src "ls180.v:5282.8-5282.128" + case 1'1 + assign $0\builder_sdcore_crcupstreaminserter_next_state[0:0] 1'1 + assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] 3'000 + assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] 1'1 + case + end + end + sync always + update \main_sdcore_crc16_inserter_sink_ready $0\main_sdcore_crc16_inserter_sink_ready[0:0] + update \main_sdcore_crc16_inserter_source_valid $0\main_sdcore_crc16_inserter_source_valid[0:0] + update \main_sdcore_crc16_inserter_source_last $0\main_sdcore_crc16_inserter_source_last[0:0] + update \main_sdcore_crc16_inserter_source_payload_data $0\main_sdcore_crc16_inserter_source_payload_data[7:0] + update \builder_sdcore_crcupstreaminserter_next_state $0\builder_sdcore_crcupstreaminserter_next_state[0:0] + update \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0 $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] + update \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0 $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] + update \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1 $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] + update \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1 $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] + update \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2 $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] + update \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2 $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] + update \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3 $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] + update \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3 $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] + update \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4 $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] + update \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4 $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] + end + attribute \src "ls180.v:5290.1-5295.4" + process $proc$ls180.v:5290$1043 + assign { } { } + assign $0\main_sdcore_crc16_checker_valid[0:0] 1'0 + attribute \src "ls180.v:5292.2-5294.5" + switch $and$ls180.v:5292$1050_Y + attribute \src "ls180.v:5292.6-5292.301" + case 1'1 + assign $0\main_sdcore_crc16_checker_valid[0:0] 1'1 + case + end + sync always + update \main_sdcore_crc16_checker_valid $0\main_sdcore_crc16_checker_valid[0:0] + end + attribute \src "ls180.v:5298.1-5305.4" + process $proc$ls180.v:5298$1052 + assign { } { } + assign $0\main_sdcore_crc16_checker_crc0_clr[0:0] 1'0 + attribute \src "ls180.v:5300.2-5304.5" + switch $eq$ls180.v:5300$1053_Y + attribute \src "ls180.v:5300.6-5300.45" + case 1'1 + assign $0\main_sdcore_crc16_checker_crc0_clr[0:0] 1'1 + attribute \src "ls180.v:5302.6-5302.10" + case + assign $0\main_sdcore_crc16_checker_crc0_clr[0:0] 1'0 + end + sync always + update \main_sdcore_crc16_checker_crc0_clr $0\main_sdcore_crc16_checker_crc0_clr[0:0] + end + attribute \src "ls180.v:5308.1-5315.4" + process $proc$ls180.v:5308$1055 + assign { } { } + assign $0\main_sdcore_crc16_checker_crc1_clr[0:0] 1'0 + attribute \src "ls180.v:5310.2-5314.5" + switch $eq$ls180.v:5310$1056_Y + attribute \src "ls180.v:5310.6-5310.45" + case 1'1 + assign $0\main_sdcore_crc16_checker_crc1_clr[0:0] 1'1 + attribute \src "ls180.v:5312.6-5312.10" + case + assign $0\main_sdcore_crc16_checker_crc1_clr[0:0] 1'0 + end + sync always + update \main_sdcore_crc16_checker_crc1_clr $0\main_sdcore_crc16_checker_crc1_clr[0:0] + end + attribute \src "ls180.v:5318.1-5325.4" + process $proc$ls180.v:5318$1058 + assign { } { } + assign $0\main_sdcore_crc16_checker_crc2_clr[0:0] 1'0 + attribute \src "ls180.v:5320.2-5324.5" + switch $eq$ls180.v:5320$1059_Y + attribute \src "ls180.v:5320.6-5320.45" + case 1'1 + assign $0\main_sdcore_crc16_checker_crc2_clr[0:0] 1'1 + attribute \src "ls180.v:5322.6-5322.10" + case + assign $0\main_sdcore_crc16_checker_crc2_clr[0:0] 1'0 + end + sync always + update \main_sdcore_crc16_checker_crc2_clr $0\main_sdcore_crc16_checker_crc2_clr[0:0] + end + attribute \src "ls180.v:5328.1-5335.4" + process $proc$ls180.v:5328$1061 + assign { } { } + assign $0\main_sdcore_crc16_checker_crc3_clr[0:0] 1'0 + attribute \src "ls180.v:5330.2-5334.5" + switch $eq$ls180.v:5330$1062_Y + attribute \src "ls180.v:5330.6-5330.45" + case 1'1 + assign $0\main_sdcore_crc16_checker_crc3_clr[0:0] 1'1 + attribute \src "ls180.v:5332.6-5332.10" + case + assign $0\main_sdcore_crc16_checker_crc3_clr[0:0] 1'0 + end + sync always + update \main_sdcore_crc16_checker_crc3_clr $0\main_sdcore_crc16_checker_crc3_clr[0:0] + end + attribute \src "ls180.v:5337.1-5342.4" + process $proc$ls180.v:5337$1063 + assign { } { } + assign $0\main_sdcore_crc16_checker_source_valid[0:0] 1'0 + attribute \src "ls180.v:5339.2-5341.5" + switch $and$ls180.v:5339$1065_Y + attribute \src "ls180.v:5339.6-5339.85" + case 1'1 + assign $0\main_sdcore_crc16_checker_source_valid[0:0] 1'1 + case + end + sync always + update \main_sdcore_crc16_checker_source_valid $0\main_sdcore_crc16_checker_source_valid[0:0] + end + attribute \src "ls180.v:5343.1-5350.4" + process $proc$ls180.v:5343$1066 + assign { } { } + assign $0\main_sdcore_crc16_checker_sink_ready[0:0] 1'0 + attribute \src "ls180.v:5345.2-5349.5" + switch $lt$ls180.v:5345$1067_Y + attribute \src "ls180.v:5345.6-5345.44" + case 1'1 + assign $0\main_sdcore_crc16_checker_sink_ready[0:0] 1'1 + attribute \src "ls180.v:5347.6-5347.10" + case + assign $0\main_sdcore_crc16_checker_sink_ready[0:0] \main_sdcore_crc16_checker_source_ready + end + sync always + update \main_sdcore_crc16_checker_sink_ready $0\main_sdcore_crc16_checker_sink_ready[0:0] + end + attribute \src "ls180.v:535.11-535.68" + process $proc$ls180.v:535$3272 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] 4'0000 + sync always + sync init + update \main_sdram_bankmachine0_cmd_buffer_lookahead_level $1\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] + end + attribute \src "ls180.v:5354.1-5361.4" + process $proc$ls180.v:5354$1078 + assign { } { } + assign $0\main_sdcore_crc16_checker_crc0_crc[15:0] 16'0000000000000000 + attribute \src "ls180.v:5356.2-5360.5" + switch \main_sdcore_crc16_checker_crc0_enable + attribute \src "ls180.v:5356.6-5356.43" + case 1'1 + assign $0\main_sdcore_crc16_checker_crc0_crc[15:0] \main_sdcore_crc16_checker_crc0_crcreg2 + attribute \src "ls180.v:5358.6-5358.10" + case + assign $0\main_sdcore_crc16_checker_crc0_crc[15:0] \main_sdcore_crc16_checker_crc0_crcreg0 + end + sync always + update \main_sdcore_crc16_checker_crc0_crc $0\main_sdcore_crc16_checker_crc0_crc[15:0] + end + attribute \src "ls180.v:536.5-536.64" + process $proc$ls180.v:536$3273 + assign { } { } + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_replace[0:0] 1'0 + sync always + update \main_sdram_bankmachine0_cmd_buffer_lookahead_replace $0\main_sdram_bankmachine0_cmd_buffer_lookahead_replace[0:0] + sync init + end + attribute \src "ls180.v:5364.1-5371.4" + process $proc$ls180.v:5364$1089 + assign { } { } + assign $0\main_sdcore_crc16_checker_crc1_crc[15:0] 16'0000000000000000 + attribute \src "ls180.v:5366.2-5370.5" + switch \main_sdcore_crc16_checker_crc1_enable + attribute \src "ls180.v:5366.6-5366.43" + case 1'1 + assign $0\main_sdcore_crc16_checker_crc1_crc[15:0] \main_sdcore_crc16_checker_crc1_crcreg2 + attribute \src "ls180.v:5368.6-5368.10" + case + assign $0\main_sdcore_crc16_checker_crc1_crc[15:0] \main_sdcore_crc16_checker_crc1_crcreg0 + end + sync always + update \main_sdcore_crc16_checker_crc1_crc $0\main_sdcore_crc16_checker_crc1_crc[15:0] + end + attribute \src "ls180.v:537.11-537.70" + process $proc$ls180.v:537$3274 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine0_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] + end + attribute \src "ls180.v:5374.1-5381.4" + process $proc$ls180.v:5374$1100 + assign { } { } + assign $0\main_sdcore_crc16_checker_crc2_crc[15:0] 16'0000000000000000 + attribute \src "ls180.v:5376.2-5380.5" + switch \main_sdcore_crc16_checker_crc2_enable + attribute \src "ls180.v:5376.6-5376.43" + case 1'1 + assign $0\main_sdcore_crc16_checker_crc2_crc[15:0] \main_sdcore_crc16_checker_crc2_crcreg2 + attribute \src "ls180.v:5378.6-5378.10" + case + assign $0\main_sdcore_crc16_checker_crc2_crc[15:0] \main_sdcore_crc16_checker_crc2_crcreg0 + end + sync always + update \main_sdcore_crc16_checker_crc2_crc $0\main_sdcore_crc16_checker_crc2_crc[15:0] + end + attribute \src "ls180.v:538.11-538.70" + process $proc$ls180.v:538$3275 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine0_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] + end + attribute \src "ls180.v:5384.1-5391.4" + process $proc$ls180.v:5384$1111 + assign { } { } + assign $0\main_sdcore_crc16_checker_crc3_crc[15:0] 16'0000000000000000 + attribute \src "ls180.v:5386.2-5390.5" + switch \main_sdcore_crc16_checker_crc3_enable + attribute \src "ls180.v:5386.6-5386.43" + case 1'1 + assign $0\main_sdcore_crc16_checker_crc3_crc[15:0] \main_sdcore_crc16_checker_crc3_crcreg2 + attribute \src "ls180.v:5388.6-5388.10" + case + assign $0\main_sdcore_crc16_checker_crc3_crc[15:0] \main_sdcore_crc16_checker_crc3_crcreg0 + end + sync always + update \main_sdcore_crc16_checker_crc3_crc $0\main_sdcore_crc16_checker_crc3_crc[15:0] + end + attribute \src "ls180.v:539.11-539.73" + process $proc$ls180.v:539$3276 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr $1\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] + end + attribute \src "ls180.v:5392.1-5582.4" + process $proc$ls180.v:5392$1112 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdphy_cmdr_sink_payload_length[7:0] 8'00000000 + assign $0\main_sdphy_cmdr_source_ready[0:0] 1'0 + assign $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] 1'0 + assign $0\main_sdphy_cmdw_sink_valid[0:0] 1'0 + assign $0\main_sdphy_cmdw_sink_last[0:0] 1'0 + assign $0\main_sdphy_cmdw_sink_payload_data[7:0] 8'00000000 + assign { } { } + assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] 1'0 + assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] 1'0 + assign $0\main_sdcore_crc16_checker_sink_valid[0:0] 1'0 + assign $0\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] 1'0 + assign $0\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] 1'0 + assign $0\main_sdcore_crc16_checker_sink_first[0:0] 1'0 + assign $0\main_sdcore_crc16_checker_sink_last[0:0] 1'0 + assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] 3'000 + assign $0\main_sdcore_crc16_checker_sink_payload_data[7:0] 8'00000000 + assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] 1'0 + assign $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] 0 + assign $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'0 + assign $0\main_sdcore_crc16_inserter_source_ready[0:0] 1'0 + assign $0\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] 1'0 + assign $0\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] 1'0 + assign $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] 1'0 + assign $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] 1'0 + assign $0\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] 1'0 + assign $0\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] 1'0 + assign $0\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] 1'0 + assign $0\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] 1'0 + assign $0\main_sdphy_dataw_sink_valid[0:0] 1'0 + assign $0\main_sdphy_datar_sink_valid[0:0] 1'0 + assign $0\main_sdphy_dataw_sink_first[0:0] 1'0 + assign $0\main_sdphy_datar_sink_last[0:0] 1'0 + assign $0\main_sdphy_dataw_sink_last[0:0] 1'0 + assign $0\main_sdphy_datar_sink_payload_block_length[9:0] 10'0000000000 + assign $0\main_sdphy_dataw_sink_payload_data[7:0] 8'00000000 + assign $0\main_sdphy_cmdr_sink_valid[0:0] 1'0 + assign $0\main_sdphy_datar_source_ready[0:0] 1'0 + assign $0\main_sdphy_cmdr_sink_last[0:0] 1'0 + assign $0\builder_sdcore_fsm_next_state[2:0] \builder_sdcore_fsm_state + attribute \src "ls180.v:5433.2-5581.9" + switch \builder_sdcore_fsm_state + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\main_sdphy_cmdw_sink_valid[0:0] 1'1 + attribute \src "ls180.v:5436.4-5456.11" + switch \main_sdcore_cmd_count + attribute \src "ls180.v:0.0-0.0" + case 3'000 + assign $0\main_sdphy_cmdw_sink_payload_data[7:0] { 2'01 \main_sdcore_cmd_command_storage [13:8] } + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\main_sdphy_cmdw_sink_payload_data[7:0] \main_sdcore_cmd_argument_storage [31:24] + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\main_sdphy_cmdw_sink_payload_data[7:0] \main_sdcore_cmd_argument_storage [23:16] + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\main_sdphy_cmdw_sink_payload_data[7:0] \main_sdcore_cmd_argument_storage [15:8] + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\main_sdphy_cmdw_sink_payload_data[7:0] \main_sdcore_cmd_argument_storage [7:0] + attribute \src "ls180.v:0.0-0.0" + case 3'101 + assign $0\main_sdphy_cmdw_sink_payload_data[7:0] { \main_sdcore_crc7_inserter_crc 1'1 } + assign $0\main_sdphy_cmdw_sink_last[0:0] $eq$ls180.v:5454$1113_Y + case + end + attribute \src "ls180.v:5457.4-5469.7" + switch $and$ls180.v:5457$1114_Y + attribute \src "ls180.v:5457.8-5457.65" + case 1'1 + assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] $add$ls180.v:5458$1115_Y + assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] 1'1 + attribute \src "ls180.v:5460.5-5468.8" + switch $eq$ls180.v:5460$1116_Y + attribute \src "ls180.v:5460.9-5460.40" + case 1'1 + attribute \src "ls180.v:5461.6-5467.9" + switch $eq$ls180.v:5461$1117_Y + attribute \src "ls180.v:5461.10-5461.40" + case 1'1 + assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] 1'1 + assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] 1'1 + assign $0\builder_sdcore_fsm_next_state[2:0] 3'000 + attribute \src "ls180.v:5465.10-5465.14" + case + assign $0\builder_sdcore_fsm_next_state[2:0] 3'010 + end + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\main_sdphy_cmdr_sink_valid[0:0] 1'1 + assign $0\main_sdphy_cmdr_sink_last[0:0] $eq$ls180.v:5473$1118_Y + assign $0\main_sdphy_cmdr_source_ready[0:0] 1'1 + attribute \src "ls180.v:5474.4-5478.7" + switch $eq$ls180.v:5474$1119_Y + attribute \src "ls180.v:5474.8-5474.38" + case 1'1 + assign $0\main_sdphy_cmdr_sink_payload_length[7:0] 8'00010001 + attribute \src "ls180.v:5476.8-5476.12" + case + assign $0\main_sdphy_cmdr_sink_payload_length[7:0] 8'00000110 + end + attribute \src "ls180.v:5480.4-5501.7" + switch \main_sdphy_cmdr_source_valid + attribute \src "ls180.v:5480.8-5480.36" + case 1'1 + attribute \src "ls180.v:5481.5-5500.8" + switch $eq$ls180.v:5481$1120_Y + attribute \src "ls180.v:5481.9-5481.56" + case 1'1 + assign $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] 1'1 + assign $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] 1'1 + assign $0\builder_sdcore_fsm_next_state[2:0] 3'000 + attribute \src "ls180.v:5485.9-5485.13" + case + attribute \src "ls180.v:5486.6-5499.9" + switch \main_sdphy_cmdr_source_last + attribute \src "ls180.v:5486.10-5486.37" + case 1'1 + attribute \src "ls180.v:5487.7-5495.10" + switch $eq$ls180.v:5487$1121_Y + attribute \src "ls180.v:5487.11-5487.42" + case 1'1 + assign $0\builder_sdcore_fsm_next_state[2:0] 3'011 + attribute \src "ls180.v:5489.11-5489.15" + case + attribute \src "ls180.v:5490.8-5494.11" + switch $eq$ls180.v:5490$1122_Y + attribute \src "ls180.v:5490.12-5490.43" + case 1'1 + assign $0\builder_sdcore_fsm_next_state[2:0] 3'100 + attribute \src "ls180.v:5492.12-5492.16" + case + assign $0\builder_sdcore_fsm_next_state[2:0] 3'000 + end + end + attribute \src "ls180.v:5496.10-5496.14" + case + assign $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] { \main_sdcore_cmd_response_status [119:0] \main_sdphy_cmdr_source_payload_data } + assign $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] 1'1 + end + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\main_sdphy_dataw_sink_valid[0:0] \main_sdcore_crc16_inserter_source_valid + assign $0\main_sdcore_crc16_inserter_source_ready[0:0] \main_sdphy_dataw_sink_ready + assign $0\main_sdphy_dataw_sink_first[0:0] \main_sdcore_crc16_inserter_source_first + assign $0\main_sdphy_dataw_sink_last[0:0] \main_sdcore_crc16_inserter_source_last + assign $0\main_sdphy_dataw_sink_payload_data[7:0] \main_sdcore_crc16_inserter_source_payload_data + assign $0\main_sdphy_datar_source_ready[0:0] 1'1 + attribute \src "ls180.v:5509.4-5515.7" + switch $and$ls180.v:5509$1124_Y + attribute \src "ls180.v:5509.8-5509.98" + case 1'1 + assign $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] $add$ls180.v:5510$1125_Y + assign $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'1 + attribute \src "ls180.v:5512.5-5514.8" + switch $eq$ls180.v:5512$1127_Y + attribute \src "ls180.v:5512.9-5512.77" + case 1'1 + assign $0\builder_sdcore_fsm_next_state[2:0] 3'000 + case + end + case + end + attribute \src "ls180.v:5517.4-5522.7" + switch \main_sdphy_datar_source_valid + attribute \src "ls180.v:5517.8-5517.37" + case 1'1 + attribute \src "ls180.v:5518.5-5521.8" + switch $ne$ls180.v:5518$1128_Y + attribute \src "ls180.v:5518.9-5518.57" + case 1'1 + assign $0\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] 1'1 + assign $0\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] 1'1 + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\main_sdphy_datar_sink_valid[0:0] 1'1 + assign $0\main_sdphy_datar_sink_payload_block_length[9:0] \main_sdcore_block_length_storage + assign $0\main_sdphy_datar_sink_last[0:0] $eq$ls180.v:5527$1130_Y + attribute \src "ls180.v:5528.4-5554.7" + switch \main_sdphy_datar_source_valid + attribute \src "ls180.v:5528.8-5528.37" + case 1'1 + attribute \src "ls180.v:5529.5-5553.8" + switch $eq$ls180.v:5529$1131_Y + attribute \src "ls180.v:5529.9-5529.57" + case 1'1 + assign $0\main_sdcore_crc16_checker_sink_valid[0:0] \main_sdphy_datar_source_valid + assign $0\main_sdphy_datar_source_ready[0:0] \main_sdcore_crc16_checker_sink_ready + assign $0\main_sdcore_crc16_checker_sink_first[0:0] \main_sdphy_datar_source_first + assign $0\main_sdcore_crc16_checker_sink_last[0:0] \main_sdphy_datar_source_last + assign $0\main_sdcore_crc16_checker_sink_payload_data[7:0] \main_sdphy_datar_source_payload_data + attribute \src "ls180.v:5535.6-5543.9" + switch $and$ls180.v:5535$1132_Y + attribute \src "ls180.v:5535.10-5535.72" + case 1'1 + assign $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] $add$ls180.v:5536$1133_Y + assign $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'1 + attribute \src "ls180.v:5538.7-5542.10" + switch $eq$ls180.v:5538$1135_Y + attribute \src "ls180.v:5538.11-5538.79" + case 1'1 + assign $0\builder_sdcore_fsm_next_state[2:0] 3'000 + attribute \src "ls180.v:5540.11-5540.15" + case + assign $0\builder_sdcore_fsm_next_state[2:0] 3'100 + end + case + end + attribute \src "ls180.v:5544.9-5544.13" + case + attribute \src "ls180.v:5545.6-5552.9" + switch $eq$ls180.v:5545$1136_Y + attribute \src "ls180.v:5545.10-5545.58" + case 1'1 + assign $0\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] 1'1 + assign $0\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] 1'1 + assign $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] 0 + assign $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'1 + assign $0\main_sdphy_datar_source_ready[0:0] 1'1 + assign $0\builder_sdcore_fsm_next_state[2:0] 3'000 + case + end + end + case + end + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] 1'1 + assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] 1'1 + assign $0\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] 1'1 + assign $0\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] 1'1 + assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] 3'000 + assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] 1'1 + assign $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] 0 + assign $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'1 + attribute \src "ls180.v:5565.4-5579.7" + switch \main_sdcore_cmd_send_re + attribute \src "ls180.v:5565.8-5565.31" + case 1'1 + assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] 1'0 + assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] 1'1 + assign $0\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] 1'0 + assign $0\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] 1'1 + assign $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] 1'0 + assign $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] 1'1 + assign $0\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] 1'0 + assign $0\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] 1'1 + assign $0\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] 1'0 + assign $0\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] 1'1 + assign $0\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] 1'0 + assign $0\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] 1'1 + assign $0\builder_sdcore_fsm_next_state[2:0] 3'001 + case + end + end + sync always + update \main_sdphy_cmdw_sink_valid $0\main_sdphy_cmdw_sink_valid[0:0] + update \main_sdphy_cmdw_sink_last $0\main_sdphy_cmdw_sink_last[0:0] + update \main_sdphy_cmdw_sink_payload_data $0\main_sdphy_cmdw_sink_payload_data[7:0] + update \main_sdphy_cmdr_sink_valid $0\main_sdphy_cmdr_sink_valid[0:0] + update \main_sdphy_cmdr_sink_last $0\main_sdphy_cmdr_sink_last[0:0] + update \main_sdphy_cmdr_sink_payload_length $0\main_sdphy_cmdr_sink_payload_length[7:0] + update \main_sdphy_cmdr_source_ready $0\main_sdphy_cmdr_source_ready[0:0] + update \main_sdphy_dataw_sink_valid $0\main_sdphy_dataw_sink_valid[0:0] + update \main_sdphy_dataw_sink_first $0\main_sdphy_dataw_sink_first[0:0] + update \main_sdphy_dataw_sink_last $0\main_sdphy_dataw_sink_last[0:0] + update \main_sdphy_dataw_sink_payload_data $0\main_sdphy_dataw_sink_payload_data[7:0] + update \main_sdphy_datar_sink_valid $0\main_sdphy_datar_sink_valid[0:0] + update \main_sdphy_datar_sink_last $0\main_sdphy_datar_sink_last[0:0] + update \main_sdphy_datar_sink_payload_block_length $0\main_sdphy_datar_sink_payload_block_length[9:0] + update \main_sdphy_datar_source_ready $0\main_sdphy_datar_source_ready[0:0] + update \main_sdcore_crc16_inserter_source_ready $0\main_sdcore_crc16_inserter_source_ready[0:0] + update \main_sdcore_crc16_checker_sink_valid $0\main_sdcore_crc16_checker_sink_valid[0:0] + update \main_sdcore_crc16_checker_sink_first $0\main_sdcore_crc16_checker_sink_first[0:0] + update \main_sdcore_crc16_checker_sink_last $0\main_sdcore_crc16_checker_sink_last[0:0] + update \main_sdcore_crc16_checker_sink_payload_data $0\main_sdcore_crc16_checker_sink_payload_data[7:0] + update \builder_sdcore_fsm_next_state $0\builder_sdcore_fsm_next_state[2:0] + update \main_sdcore_cmd_done_sdcore_fsm_next_value0 $0\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] + update \main_sdcore_cmd_done_sdcore_fsm_next_value_ce0 $0\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] + update \main_sdcore_data_done_sdcore_fsm_next_value1 $0\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] + update \main_sdcore_data_done_sdcore_fsm_next_value_ce1 $0\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] + update \main_sdcore_cmd_count_sdcore_fsm_next_value2 $0\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] + update \main_sdcore_cmd_count_sdcore_fsm_next_value_ce2 $0\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] + update \main_sdcore_data_count_sdcore_fsm_next_value3 $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] + update \main_sdcore_data_count_sdcore_fsm_next_value_ce3 $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] + update \main_sdcore_cmd_error_sdcore_fsm_next_value4 $0\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] + update \main_sdcore_cmd_error_sdcore_fsm_next_value_ce4 $0\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] + update \main_sdcore_cmd_timeout_sdcore_fsm_next_value5 $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] + update \main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5 $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] + update \main_sdcore_data_error_sdcore_fsm_next_value6 $0\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] + update \main_sdcore_data_error_sdcore_fsm_next_value_ce6 $0\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] + update \main_sdcore_data_timeout_sdcore_fsm_next_value7 $0\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] + update \main_sdcore_data_timeout_sdcore_fsm_next_value_ce7 $0\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] + update \main_sdcore_cmd_response_status_sdcore_fsm_next_value8 $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] + update \main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8 $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] + end + attribute \src "ls180.v:55.5-55.42" + process $proc$ls180.v:55$3126 + assign { } { } + assign $1\main_libresocsim_reset_storage[0:0] 1'0 + sync always + sync init + update \main_libresocsim_reset_storage $1\main_libresocsim_reset_storage[0:0] + end + attribute \src "ls180.v:56.5-56.37" + process $proc$ls180.v:56$3127 + assign { } { } + assign $1\main_libresocsim_reset_re[0:0] 1'0 + sync always + sync init + update \main_libresocsim_reset_re $1\main_libresocsim_reset_re[0:0] + end + attribute \src "ls180.v:560.5-560.59" + process $proc$ls180.v:560$3277 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_cmd_buffer_source_valid $1\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] + end + attribute \src "ls180.v:5610.1-5617.4" + process $proc$ls180.v:5610$1137 + assign { } { } + assign $0\main_sdblock2mem_fifo_wrport_adr[4:0] 5'00000 + attribute \src "ls180.v:5612.2-5616.5" + switch \main_sdblock2mem_fifo_replace + attribute \src "ls180.v:5612.6-5612.35" + case 1'1 + assign $0\main_sdblock2mem_fifo_wrport_adr[4:0] $sub$ls180.v:5613$1138_Y + attribute \src "ls180.v:5614.6-5614.10" + case + assign $0\main_sdblock2mem_fifo_wrport_adr[4:0] \main_sdblock2mem_fifo_produce + end + sync always + update \main_sdblock2mem_fifo_wrport_adr $0\main_sdblock2mem_fifo_wrport_adr[4:0] + end + attribute \src "ls180.v:562.5-562.59" + process $proc$ls180.v:562$3278 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_cmd_buffer_source_first $1\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] + end + attribute \src "ls180.v:563.5-563.58" + process $proc$ls180.v:563$3279 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_cmd_buffer_source_last $1\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] + end + attribute \src "ls180.v:564.5-564.64" + process $proc$ls180.v:564$3280 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_cmd_buffer_source_payload_we $1\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] + end + attribute \src "ls180.v:5643.1-5682.4" + process $proc$ls180.v:5643$1148 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdblock2mem_sink_sink_payload_address[31:0] 0 + assign $0\main_sdblock2mem_sink_sink_payload_data1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\main_sdblock2mem_wishbonedmawriter_status[0:0] 1'0 + assign { } { } + assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] 0 + assign $0\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] 1'0 + assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] 1'0 + assign $0\main_sdblock2mem_sink_sink_valid1[0:0] 1'0 + assign $0\builder_sdblock2memdma_next_state[1:0] \builder_sdblock2memdma_state + attribute \src "ls180.v:5653.2-5681.9" + switch \builder_sdblock2memdma_state + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\main_sdblock2mem_sink_sink_valid1[0:0] \main_sdblock2mem_wishbonedmawriter_sink_valid + assign $0\main_sdblock2mem_sink_sink_payload_data1[63:0] \main_sdblock2mem_wishbonedmawriter_sink_payload_data + assign $0\main_sdblock2mem_sink_sink_payload_address[31:0] $add$ls180.v:5657$1149_Y + assign $0\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] \main_sdblock2mem_sink_sink_ready1 + attribute \src "ls180.v:5659.4-5670.7" + switch $and$ls180.v:5659$1150_Y + attribute \src "ls180.v:5659.8-5659.103" + case 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] $add$ls180.v:5660$1151_Y + assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:5662.5-5669.8" + switch $eq$ls180.v:5662$1153_Y + attribute \src "ls180.v:5662.9-5662.106" + case 1'1 + attribute \src "ls180.v:5663.6-5668.9" + switch \main_sdblock2mem_wishbonedmawriter_loop_storage + attribute \src "ls180.v:5663.10-5663.57" + case 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] 0 + assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:5666.10-5666.14" + case + assign $0\builder_sdblock2memdma_next_state[1:0] 2'10 + end + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\main_sdblock2mem_wishbonedmawriter_status[0:0] 1'1 + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] 0 + assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] 1'1 + assign $0\builder_sdblock2memdma_next_state[1:0] 2'01 + end + sync always + update \main_sdblock2mem_sink_sink_valid1 $0\main_sdblock2mem_sink_sink_valid1[0:0] + update \main_sdblock2mem_sink_sink_payload_address $0\main_sdblock2mem_sink_sink_payload_address[31:0] + update \main_sdblock2mem_sink_sink_payload_data1 $0\main_sdblock2mem_sink_sink_payload_data1[63:0] + update \main_sdblock2mem_wishbonedmawriter_sink_ready $0\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] + update \main_sdblock2mem_wishbonedmawriter_status $0\main_sdblock2mem_wishbonedmawriter_status[0:0] + update \builder_sdblock2memdma_next_state $0\builder_sdblock2memdma_next_state[1:0] + update \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] + update \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] + end + attribute \src "ls180.v:565.12-565.74" + process $proc$ls180.v:565$3281 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000 + sync always + sync init + update \main_sdram_bankmachine0_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] + end + attribute \src "ls180.v:566.12-566.47" + process $proc$ls180.v:566$3282 + assign { } { } + assign $1\main_sdram_bankmachine0_row[12:0] 13'0000000000000 + sync always + sync init + update \main_sdram_bankmachine0_row $1\main_sdram_bankmachine0_row[12:0] + end + attribute \src "ls180.v:567.5-567.46" + process $proc$ls180.v:567$3283 + assign { } { } + assign $1\main_sdram_bankmachine0_row_opened[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_row_opened $1\main_sdram_bankmachine0_row_opened[0:0] + end + attribute \src "ls180.v:569.5-569.44" + process $proc$ls180.v:569$3284 + assign { } { } + assign $1\main_sdram_bankmachine0_row_open[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_row_open $1\main_sdram_bankmachine0_row_open[0:0] + end + attribute \src "ls180.v:57.12-57.60" + process $proc$ls180.v:57$3128 + assign { } { } + assign $1\main_libresocsim_scratch_storage[31:0] 305419896 + sync always + sync init + update \main_libresocsim_scratch_storage $1\main_libresocsim_scratch_storage[31:0] + end + attribute \src "ls180.v:570.5-570.45" + process $proc$ls180.v:570$3285 + assign { } { } + assign $1\main_sdram_bankmachine0_row_close[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_row_close $1\main_sdram_bankmachine0_row_close[0:0] + end + attribute \src "ls180.v:5702.1-5739.4" + process $proc$ls180.v:5702$1155 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_interface1_bus_adr[31:0] 0 + assign { } { } + assign $0\main_sdmem2block_dma_sink_ready[0:0] 1'0 + assign $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\main_interface1_bus_sel[7:0] 8'00000000 + assign $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] 1'0 + assign $0\main_interface1_bus_cyc[0:0] 1'0 + assign $0\main_interface1_bus_stb[0:0] 1'0 + assign $0\main_sdmem2block_dma_source_valid[0:0] 1'0 + assign $0\main_interface1_bus_we[0:0] 1'0 + assign $0\main_sdmem2block_dma_source_last[0:0] 1'0 + assign $0\main_sdmem2block_dma_source_payload_data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\builder_sdmem2blockdma_fsm_next_state[0:0] \builder_sdmem2blockdma_fsm_state + attribute \src "ls180.v:5716.2-5738.9" + switch \builder_sdmem2blockdma_fsm_state + attribute \src "ls180.v:0.0-0.0" + case 1'1 + assign $0\main_sdmem2block_dma_source_valid[0:0] 1'1 + assign $0\main_sdmem2block_dma_source_last[0:0] \main_sdmem2block_dma_sink_last + assign $0\main_sdmem2block_dma_source_payload_data[63:0] \main_sdmem2block_dma_data + attribute \src "ls180.v:5721.4-5724.7" + switch \main_sdmem2block_dma_source_ready + attribute \src "ls180.v:5721.8-5721.41" + case 1'1 + assign $0\main_sdmem2block_dma_sink_ready[0:0] 1'1 + assign $0\builder_sdmem2blockdma_fsm_next_state[0:0] 1'0 + case + end + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_interface1_bus_stb[0:0] \main_sdmem2block_dma_sink_valid + assign $0\main_interface1_bus_cyc[0:0] \main_sdmem2block_dma_sink_valid + assign $0\main_interface1_bus_we[0:0] 1'0 + assign $0\main_interface1_bus_sel[7:0] 8'11111111 + assign $0\main_interface1_bus_adr[31:0] \main_sdmem2block_dma_sink_payload_address + attribute \src "ls180.v:5732.4-5736.7" + switch $and$ls180.v:5732$1156_Y + attribute \src "ls180.v:5732.8-5732.59" + case 1'1 + assign $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[63:0] { \main_interface1_bus_dat_r [7:0] \main_interface1_bus_dat_r [15:8] \main_interface1_bus_dat_r [23:16] \main_interface1_bus_dat_r [31:24] \main_interface1_bus_dat_r [39:32] \main_interface1_bus_dat_r [47:40] \main_interface1_bus_dat_r [55:48] \main_interface1_bus_dat_r [63:56] } + assign $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] 1'1 + assign $0\builder_sdmem2blockdma_fsm_next_state[0:0] 1'1 + case + end + end + sync always + update \main_interface1_bus_adr $0\main_interface1_bus_adr[31:0] + update \main_interface1_bus_sel $0\main_interface1_bus_sel[7:0] + update \main_interface1_bus_cyc $0\main_interface1_bus_cyc[0:0] + update \main_interface1_bus_stb $0\main_interface1_bus_stb[0:0] + update \main_interface1_bus_we $0\main_interface1_bus_we[0:0] + update \main_sdmem2block_dma_sink_ready $0\main_sdmem2block_dma_sink_ready[0:0] + update \main_sdmem2block_dma_source_valid $0\main_sdmem2block_dma_source_valid[0:0] + update \main_sdmem2block_dma_source_last $0\main_sdmem2block_dma_source_last[0:0] + update \main_sdmem2block_dma_source_payload_data $0\main_sdmem2block_dma_source_payload_data[63:0] + update \builder_sdmem2blockdma_fsm_next_state $0\builder_sdmem2blockdma_fsm_next_state[0:0] + update \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[63:0] + update \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] + end + attribute \src "ls180.v:571.5-571.54" + process $proc$ls180.v:571$3286 + assign { } { } + assign $1\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_row_col_n_addr_sel $1\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] + end + attribute \src "ls180.v:573.32-573.76" + process $proc$ls180.v:573$3287 + assign { } { } + assign $1\main_sdram_bankmachine0_twtpcon_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_twtpcon_ready $1\main_sdram_bankmachine0_twtpcon_ready[0:0] + end + attribute \src "ls180.v:574.11-574.55" + process $proc$ls180.v:574$3288 + assign { } { } + assign $1\main_sdram_bankmachine0_twtpcon_count[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine0_twtpcon_count $1\main_sdram_bankmachine0_twtpcon_count[2:0] + end + attribute \src "ls180.v:5740.1-5776.4" + process $proc$ls180.v:5740$1157 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] 0 + assign $0\main_sdmem2block_dma_done_status[0:0] 1'0 + assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] 1'0 + assign $0\main_sdmem2block_dma_sink_last[0:0] 1'0 + assign $0\main_sdmem2block_dma_sink_payload_address[31:0] 0 + assign $0\main_sdmem2block_dma_sink_valid[0:0] 1'0 + assign { } { } + assign $0\builder_sdmem2blockdma_resetinserter_next_state[1:0] \builder_sdmem2blockdma_resetinserter_state + attribute \src "ls180.v:5749.2-5775.9" + switch \builder_sdmem2blockdma_resetinserter_state + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\main_sdmem2block_dma_sink_valid[0:0] 1'1 + assign $0\main_sdmem2block_dma_sink_last[0:0] $eq$ls180.v:5752$1159_Y + assign $0\main_sdmem2block_dma_sink_payload_address[31:0] $add$ls180.v:5753$1160_Y + attribute \src "ls180.v:5754.4-5765.7" + switch \main_sdmem2block_dma_sink_ready + attribute \src "ls180.v:5754.8-5754.39" + case 1'1 + assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] $add$ls180.v:5755$1161_Y + assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:5757.5-5764.8" + switch \main_sdmem2block_dma_sink_last + attribute \src "ls180.v:5757.9-5757.39" + case 1'1 + attribute \src "ls180.v:5758.6-5763.9" + switch \main_sdmem2block_dma_loop_storage + attribute \src "ls180.v:5758.10-5758.43" + case 1'1 + assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] 0 + assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:5761.10-5761.14" + case + assign $0\builder_sdmem2blockdma_resetinserter_next_state[1:0] 2'10 + end + case + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\main_sdmem2block_dma_done_status[0:0] 1'1 + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] 0 + assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] 1'1 + assign $0\builder_sdmem2blockdma_resetinserter_next_state[1:0] 2'01 + end + sync always + update \main_sdmem2block_dma_sink_valid $0\main_sdmem2block_dma_sink_valid[0:0] + update \main_sdmem2block_dma_sink_last $0\main_sdmem2block_dma_sink_last[0:0] + update \main_sdmem2block_dma_sink_payload_address $0\main_sdmem2block_dma_sink_payload_address[31:0] + update \main_sdmem2block_dma_done_status $0\main_sdmem2block_dma_done_status[0:0] + update \builder_sdmem2blockdma_resetinserter_next_state $0\builder_sdmem2blockdma_resetinserter_next_state[1:0] + update \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] + update \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] + end + attribute \src "ls180.v:576.32-576.75" + process $proc$ls180.v:576$3289 + assign { } { } + assign $0\main_sdram_bankmachine0_trccon_ready[0:0] 1'1 + sync always + update \main_sdram_bankmachine0_trccon_ready $0\main_sdram_bankmachine0_trccon_ready[0:0] + sync init + end + attribute \src "ls180.v:578.32-578.76" + process $proc$ls180.v:578$3290 + assign { } { } + assign $0\main_sdram_bankmachine0_trascon_ready[0:0] 1'1 + sync always + update \main_sdram_bankmachine0_trascon_ready $0\main_sdram_bankmachine0_trascon_ready[0:0] + sync init + end + attribute \src "ls180.v:5788.1-5816.4" + process $proc$ls180.v:5788$1167 + assign { } { } + assign $0\main_sdmem2block_converter_source_payload_data[7:0] 8'00000000 + attribute \src "ls180.v:5790.2-5815.9" + switch \main_sdmem2block_converter_mux + attribute \src "ls180.v:0.0-0.0" + case 3'000 + assign $0\main_sdmem2block_converter_source_payload_data[7:0] \main_sdmem2block_converter_sink_payload_data [63:56] + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\main_sdmem2block_converter_source_payload_data[7:0] \main_sdmem2block_converter_sink_payload_data [55:48] + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\main_sdmem2block_converter_source_payload_data[7:0] \main_sdmem2block_converter_sink_payload_data [47:40] + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\main_sdmem2block_converter_source_payload_data[7:0] \main_sdmem2block_converter_sink_payload_data [39:32] + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\main_sdmem2block_converter_source_payload_data[7:0] \main_sdmem2block_converter_sink_payload_data [31:24] + attribute \src "ls180.v:0.0-0.0" + case 3'101 + assign $0\main_sdmem2block_converter_source_payload_data[7:0] \main_sdmem2block_converter_sink_payload_data [23:16] + attribute \src "ls180.v:0.0-0.0" + case 3'110 + assign $0\main_sdmem2block_converter_source_payload_data[7:0] \main_sdmem2block_converter_sink_payload_data [15:8] + attribute \src "ls180.v:0.0-0.0" + case + assign $0\main_sdmem2block_converter_source_payload_data[7:0] \main_sdmem2block_converter_sink_payload_data [7:0] + end + sync always + update \main_sdmem2block_converter_source_payload_data $0\main_sdmem2block_converter_source_payload_data[7:0] + end + attribute \src "ls180.v:58.5-58.39" + process $proc$ls180.v:58$3129 + assign { } { } + assign $1\main_libresocsim_scratch_re[0:0] 1'0 + sync always + sync init + update \main_libresocsim_scratch_re $1\main_libresocsim_scratch_re[0:0] + end + attribute \src "ls180.v:5830.1-5837.4" + process $proc$ls180.v:5830$1168 + assign { } { } + assign $0\main_sdmem2block_fifo_wrport_adr[4:0] 5'00000 + attribute \src "ls180.v:5832.2-5836.5" + switch \main_sdmem2block_fifo_replace + attribute \src "ls180.v:5832.6-5832.35" + case 1'1 + assign $0\main_sdmem2block_fifo_wrport_adr[4:0] $sub$ls180.v:5833$1169_Y + attribute \src "ls180.v:5834.6-5834.10" + case + assign $0\main_sdmem2block_fifo_wrport_adr[4:0] \main_sdmem2block_fifo_produce + end + sync always + update \main_sdmem2block_fifo_wrport_adr $0\main_sdmem2block_fifo_wrport_adr[4:0] + end + attribute \src "ls180.v:584.5-584.51" + process $proc$ls180.v:584$3291 + assign { } { } + assign $1\main_sdram_bankmachine1_req_wdata_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_req_wdata_ready $1\main_sdram_bankmachine1_req_wdata_ready[0:0] + end + attribute \src "ls180.v:5845.1-5881.4" + process $proc$ls180.v:5845$1175 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\builder_libresocsim_wishbone_dat_r[31:0] 0 + assign { } { } + assign $0\builder_libresocsim_dat_w_next_value0[7:0] 8'00000000 + assign $0\builder_libresocsim_dat_w_next_value_ce0[0:0] 1'0 + assign $0\builder_libresocsim_wishbone_ack[0:0] 1'0 + assign $0\builder_libresocsim_adr_next_value1[13:0] 14'00000000000000 + assign $0\builder_libresocsim_adr_next_value_ce1[0:0] 1'0 + assign $0\builder_libresocsim_we_next_value2[0:0] 1'0 + assign $0\builder_libresocsim_we_next_value_ce2[0:0] 1'0 + assign $0\builder_next_state[1:0] \builder_state + attribute \src "ls180.v:5856.2-5880.9" + switch \builder_state + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_libresocsim_adr_next_value1[13:0] 14'00000000000000 + assign $0\builder_libresocsim_adr_next_value_ce1[0:0] 1'1 + assign $0\builder_libresocsim_we_next_value2[0:0] 1'0 + assign $0\builder_libresocsim_we_next_value_ce2[0:0] 1'1 + assign $0\builder_next_state[1:0] 2'10 + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_libresocsim_wishbone_ack[0:0] 1'1 + assign $0\builder_libresocsim_wishbone_dat_r[31:0] { 24'000000000000000000000000 \builder_libresocsim_dat_r } + assign $0\builder_next_state[1:0] 2'00 + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_libresocsim_dat_w_next_value0[7:0] \builder_libresocsim_wishbone_dat_w [7:0] + assign $0\builder_libresocsim_dat_w_next_value_ce0[0:0] 1'1 + attribute \src "ls180.v:5872.4-5878.7" + switch $and$ls180.v:5872$1176_Y + attribute \src "ls180.v:5872.8-5872.77" + case 1'1 + assign $0\builder_libresocsim_adr_next_value1[13:0] \builder_libresocsim_wishbone_adr [13:0] + assign $0\builder_libresocsim_adr_next_value_ce1[0:0] 1'1 + assign $0\builder_libresocsim_we_next_value2[0:0] $and$ls180.v:5875$1178_Y + assign $0\builder_libresocsim_we_next_value_ce2[0:0] 1'1 + assign $0\builder_next_state[1:0] 2'01 + case + end + end + sync always + update \builder_libresocsim_wishbone_dat_r $0\builder_libresocsim_wishbone_dat_r[31:0] + update \builder_libresocsim_wishbone_ack $0\builder_libresocsim_wishbone_ack[0:0] + update \builder_next_state $0\builder_next_state[1:0] + update \builder_libresocsim_dat_w_next_value0 $0\builder_libresocsim_dat_w_next_value0[7:0] + update \builder_libresocsim_dat_w_next_value_ce0 $0\builder_libresocsim_dat_w_next_value_ce0[0:0] + update \builder_libresocsim_adr_next_value1 $0\builder_libresocsim_adr_next_value1[13:0] + update \builder_libresocsim_adr_next_value_ce1 $0\builder_libresocsim_adr_next_value_ce1[0:0] + update \builder_libresocsim_we_next_value2 $0\builder_libresocsim_we_next_value2[0:0] + update \builder_libresocsim_we_next_value_ce2 $0\builder_libresocsim_we_next_value_ce2[0:0] + end + attribute \src "ls180.v:585.5-585.51" + process $proc$ls180.v:585$3292 + assign { } { } + assign $1\main_sdram_bankmachine1_req_rdata_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_req_rdata_valid $1\main_sdram_bankmachine1_req_rdata_valid[0:0] + end + attribute \src "ls180.v:587.5-587.47" + process $proc$ls180.v:587$3293 + assign { } { } + assign $1\main_sdram_bankmachine1_refresh_gnt[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_refresh_gnt $1\main_sdram_bankmachine1_refresh_gnt[0:0] + end + attribute \src "ls180.v:588.5-588.45" + process $proc$ls180.v:588$3294 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_cmd_valid $1\main_sdram_bankmachine1_cmd_valid[0:0] + end + attribute \src "ls180.v:589.5-589.45" + process $proc$ls180.v:589$3295 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_cmd_ready $1\main_sdram_bankmachine1_cmd_ready[0:0] + end + attribute \src "ls180.v:590.12-590.57" + process $proc$ls180.v:590$3296 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_payload_a[12:0] 13'0000000000000 + sync always + sync init + update \main_sdram_bankmachine1_cmd_payload_a $1\main_sdram_bankmachine1_cmd_payload_a[12:0] + end + attribute \src "ls180.v:5906.1-5921.4" + process $proc$ls180.v:5906$1199 + assign { } { } + assign { } { } + assign $0\builder_slave_sel[12:0] [0] $eq$ls180.v:5908$1200_Y + assign $0\builder_slave_sel[12:0] [1] $eq$ls180.v:5909$1201_Y + assign $0\builder_slave_sel[12:0] [2] $eq$ls180.v:5910$1202_Y + assign $0\builder_slave_sel[12:0] [3] $eq$ls180.v:5911$1203_Y + assign $0\builder_slave_sel[12:0] [4] $eq$ls180.v:5912$1204_Y + assign $0\builder_slave_sel[12:0] [5] $eq$ls180.v:5913$1205_Y + assign $0\builder_slave_sel[12:0] [6] $eq$ls180.v:5914$1206_Y + assign $0\builder_slave_sel[12:0] [7] $eq$ls180.v:5915$1207_Y + assign $0\builder_slave_sel[12:0] [8] $eq$ls180.v:5916$1208_Y + assign $0\builder_slave_sel[12:0] [9] $eq$ls180.v:5917$1209_Y + assign $0\builder_slave_sel[12:0] [10] $eq$ls180.v:5918$1210_Y + assign $0\builder_slave_sel[12:0] [11] $eq$ls180.v:5919$1211_Y + assign $0\builder_slave_sel[12:0] [12] $eq$ls180.v:5920$1212_Y + sync always + update \builder_slave_sel $0\builder_slave_sel[12:0] + end + attribute \src "ls180.v:592.5-592.51" + process $proc$ls180.v:592$3297 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_payload_cas[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_cmd_payload_cas $1\main_sdram_bankmachine1_cmd_payload_cas[0:0] + end + attribute \src "ls180.v:593.5-593.51" + process $proc$ls180.v:593$3298 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_payload_ras[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_cmd_payload_ras $1\main_sdram_bankmachine1_cmd_payload_ras[0:0] + end + attribute \src "ls180.v:594.5-594.50" + process $proc$ls180.v:594$3299 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_payload_we[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_cmd_payload_we $1\main_sdram_bankmachine1_cmd_payload_we[0:0] + end + attribute \src "ls180.v:595.5-595.54" + process $proc$ls180.v:595$3300 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_cmd_payload_is_cmd $1\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] + end + attribute \src "ls180.v:596.5-596.55" + process $proc$ls180.v:596$3301 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_payload_is_read[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_cmd_payload_is_read $1\main_sdram_bankmachine1_cmd_payload_is_read[0:0] + end + attribute \src "ls180.v:597.5-597.56" + process $proc$ls180.v:597$3302 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_payload_is_write[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_cmd_payload_is_write $1\main_sdram_bankmachine1_cmd_payload_is_write[0:0] + end + attribute \src "ls180.v:598.5-598.50" + process $proc$ls180.v:598$3303 + assign { } { } + assign $1\main_sdram_bankmachine1_auto_precharge[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_auto_precharge $1\main_sdram_bankmachine1_auto_precharge[0:0] + end + attribute \src "ls180.v:601.5-601.67" + process $proc$ls180.v:601$3304 + assign { } { } + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first[0:0] 1'0 + sync always + update \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first[0:0] + sync init + end + attribute \src "ls180.v:602.5-602.66" + process $proc$ls180.v:602$3305 + assign { } { } + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last[0:0] 1'0 + sync always + update \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last[0:0] + sync init + end + attribute \src "ls180.v:6028.1-6039.4" + process $proc$ls180.v:6028$1241 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\builder_error[0:0] 1'0 + assign $0\builder_shared_ack[0:0] $or$ls180.v:6032$1253_Y + assign $0\builder_shared_dat_r[31:0] $or$ls180.v:6033$1278_Y [31:0] + attribute \src "ls180.v:6034.2-6038.5" + switch \builder_done + attribute \src "ls180.v:6034.6-6034.18" + case 1'1 + assign $0\builder_shared_dat_r[31:0] 32'11111111111111111111111111111111 + assign $0\builder_shared_ack[0:0] 1'1 + assign $0\builder_error[0:0] 1'1 + case + end + sync always + update \builder_shared_dat_r $0\builder_shared_dat_r[31:0] + update \builder_shared_ack $0\builder_shared_ack[0:0] + update \builder_error $0\builder_error[0:0] + end + attribute \src "ls180.v:617.11-617.68" + process $proc$ls180.v:617$3306 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] 4'0000 + sync always + sync init + update \main_sdram_bankmachine1_cmd_buffer_lookahead_level $1\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] + end + attribute \src "ls180.v:618.5-618.64" + process $proc$ls180.v:618$3307 + assign { } { } + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_replace[0:0] 1'0 + sync always + update \main_sdram_bankmachine1_cmd_buffer_lookahead_replace $0\main_sdram_bankmachine1_cmd_buffer_lookahead_replace[0:0] + sync init + end + attribute \src "ls180.v:619.11-619.70" + process $proc$ls180.v:619$3308 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine1_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] + end + attribute \src "ls180.v:620.11-620.70" + process $proc$ls180.v:620$3309 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine1_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] + end + attribute \src "ls180.v:621.11-621.73" + process $proc$ls180.v:621$3310 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr $1\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] + end + attribute \src "ls180.v:63.12-63.47" + process $proc$ls180.v:63$3130 + assign { } { } + assign $1\main_libresocsim_bus_errors[31:0] 0 + sync always + sync init + update \main_libresocsim_bus_errors $1\main_libresocsim_bus_errors[31:0] + end + attribute \src "ls180.v:642.5-642.59" + process $proc$ls180.v:642$3311 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_cmd_buffer_source_valid $1\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] + end + attribute \src "ls180.v:644.5-644.59" + process $proc$ls180.v:644$3312 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_cmd_buffer_source_first $1\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] + end + attribute \src "ls180.v:645.5-645.58" + process $proc$ls180.v:645$3313 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_cmd_buffer_source_last $1\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] + end + attribute \src "ls180.v:646.5-646.64" + process $proc$ls180.v:646$3314 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_cmd_buffer_source_payload_we $1\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] + end + attribute \src "ls180.v:647.12-647.74" + process $proc$ls180.v:647$3315 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000 + sync always + sync init + update \main_sdram_bankmachine1_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] + end + attribute \src "ls180.v:648.12-648.47" + process $proc$ls180.v:648$3316 + assign { } { } + assign $1\main_sdram_bankmachine1_row[12:0] 13'0000000000000 + sync always + sync init + update \main_sdram_bankmachine1_row $1\main_sdram_bankmachine1_row[12:0] + end + attribute \src "ls180.v:649.5-649.46" + process $proc$ls180.v:649$3317 + assign { } { } + assign $1\main_sdram_bankmachine1_row_opened[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_row_opened $1\main_sdram_bankmachine1_row_opened[0:0] + end + attribute \src "ls180.v:65.12-65.55" + process $proc$ls180.v:65$3131 + assign { } { } + assign $1\main_libresocsim_libresoc_interrupt[15:0] 16'0000000000000000 + sync always + sync init + update \main_libresocsim_libresoc_interrupt $1\main_libresocsim_libresoc_interrupt[15:0] + end + attribute \src "ls180.v:651.5-651.44" + process $proc$ls180.v:651$3318 + assign { } { } + assign $1\main_sdram_bankmachine1_row_open[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_row_open $1\main_sdram_bankmachine1_row_open[0:0] + end + attribute \src "ls180.v:652.5-652.45" + process $proc$ls180.v:652$3319 + assign { } { } + assign $1\main_sdram_bankmachine1_row_close[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_row_close $1\main_sdram_bankmachine1_row_close[0:0] + end + attribute \src "ls180.v:653.5-653.54" + process $proc$ls180.v:653$3320 + assign { } { } + assign $1\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_row_col_n_addr_sel $1\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] + end + attribute \src "ls180.v:655.32-655.76" + process $proc$ls180.v:655$3321 + assign { } { } + assign $1\main_sdram_bankmachine1_twtpcon_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_twtpcon_ready $1\main_sdram_bankmachine1_twtpcon_ready[0:0] + end + attribute \src "ls180.v:6553.1-6558.4" + process $proc$ls180.v:6553$2152 + assign { } { } + assign $0\main_spimaster9_start[0:0] 1'0 + attribute \src "ls180.v:6555.2-6557.5" + switch \main_spimaster12_re + attribute \src "ls180.v:6555.6-6555.25" + case 1'1 + assign $0\main_spimaster9_start[0:0] \main_spimaster11_storage [0] + case + end + sync always + update \main_spimaster9_start $0\main_spimaster9_start[0:0] + end + attribute \src "ls180.v:656.11-656.55" + process $proc$ls180.v:656$3322 + assign { } { } + assign $1\main_sdram_bankmachine1_twtpcon_count[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine1_twtpcon_count $1\main_sdram_bankmachine1_twtpcon_count[2:0] + end + attribute \src "ls180.v:658.32-658.75" + process $proc$ls180.v:658$3323 + assign { } { } + assign $0\main_sdram_bankmachine1_trccon_ready[0:0] 1'1 + sync always + update \main_sdram_bankmachine1_trccon_ready $0\main_sdram_bankmachine1_trccon_ready[0:0] + sync init + end + attribute \src "ls180.v:6599.1-6604.4" + process $proc$ls180.v:6599$2217 + assign { } { } + assign $0\main_spisdcard_start1[0:0] 1'0 + attribute \src "ls180.v:6601.2-6603.5" + switch \main_spisdcard_control_re + attribute \src "ls180.v:6601.6-6601.31" + case 1'1 + assign $0\main_spisdcard_start1[0:0] \main_spisdcard_control_storage [0] + case + end + sync always + update \main_spisdcard_start1 $0\main_spisdcard_start1[0:0] + end + attribute \src "ls180.v:660.32-660.76" + process $proc$ls180.v:660$3324 + assign { } { } + assign $0\main_sdram_bankmachine1_trascon_ready[0:0] 1'1 + sync always + update \main_sdram_bankmachine1_trascon_ready $0\main_sdram_bankmachine1_trascon_ready[0:0] + sync init + end + attribute \src "ls180.v:666.5-666.51" + process $proc$ls180.v:666$3325 + assign { } { } + assign $1\main_sdram_bankmachine2_req_wdata_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_req_wdata_ready $1\main_sdram_bankmachine2_req_wdata_ready[0:0] + end + attribute \src "ls180.v:667.5-667.51" + process $proc$ls180.v:667$3326 + assign { } { } + assign $1\main_sdram_bankmachine2_req_rdata_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_req_rdata_valid $1\main_sdram_bankmachine2_req_rdata_valid[0:0] + end + attribute \src "ls180.v:669.5-669.47" + process $proc$ls180.v:669$3327 + assign { } { } + assign $1\main_sdram_bankmachine2_refresh_gnt[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_refresh_gnt $1\main_sdram_bankmachine2_refresh_gnt[0:0] + end + attribute \src "ls180.v:670.5-670.45" + process $proc$ls180.v:670$3328 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_cmd_valid $1\main_sdram_bankmachine2_cmd_valid[0:0] + end + attribute \src "ls180.v:671.5-671.45" + process $proc$ls180.v:671$3329 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_cmd_ready $1\main_sdram_bankmachine2_cmd_ready[0:0] + end + attribute \src "ls180.v:672.12-672.57" + process $proc$ls180.v:672$3330 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_payload_a[12:0] 13'0000000000000 + sync always + sync init + update \main_sdram_bankmachine2_cmd_payload_a $1\main_sdram_bankmachine2_cmd_payload_a[12:0] + end + attribute \src "ls180.v:674.5-674.51" + process $proc$ls180.v:674$3331 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_payload_cas[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_cmd_payload_cas $1\main_sdram_bankmachine2_cmd_payload_cas[0:0] + end + attribute \src "ls180.v:675.5-675.51" + process $proc$ls180.v:675$3332 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_payload_ras[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_cmd_payload_ras $1\main_sdram_bankmachine2_cmd_payload_ras[0:0] + end + attribute \src "ls180.v:676.5-676.50" + process $proc$ls180.v:676$3333 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_payload_we[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_cmd_payload_we $1\main_sdram_bankmachine2_cmd_payload_we[0:0] + end + attribute \src "ls180.v:677.5-677.54" + process $proc$ls180.v:677$3334 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_cmd_payload_is_cmd $1\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] + end + attribute \src "ls180.v:678.5-678.55" + process $proc$ls180.v:678$3335 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_payload_is_read[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_cmd_payload_is_read $1\main_sdram_bankmachine2_cmd_payload_is_read[0:0] + end + attribute \src "ls180.v:6788.1-6804.4" + process $proc$ls180.v:6788$2438 + assign { } { } + assign $0\builder_comb_rhs_array_muxed0[0:0] 1'0 + attribute \src "ls180.v:6790.2-6803.9" + switch \main_sdram_choose_cmd_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_rhs_array_muxed0[0:0] \main_sdram_choose_cmd_valids [0] + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_rhs_array_muxed0[0:0] \main_sdram_choose_cmd_valids [1] + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_rhs_array_muxed0[0:0] \main_sdram_choose_cmd_valids [2] + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed0[0:0] \main_sdram_choose_cmd_valids [3] + end + sync always + update \builder_comb_rhs_array_muxed0 $0\builder_comb_rhs_array_muxed0[0:0] + end + attribute \src "ls180.v:679.5-679.56" + process $proc$ls180.v:679$3336 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_payload_is_write[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_cmd_payload_is_write $1\main_sdram_bankmachine2_cmd_payload_is_write[0:0] + end + attribute \src "ls180.v:680.5-680.50" + process $proc$ls180.v:680$3337 + assign { } { } + assign $1\main_sdram_bankmachine2_auto_precharge[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_auto_precharge $1\main_sdram_bankmachine2_auto_precharge[0:0] + end + attribute \src "ls180.v:6805.1-6821.4" + process $proc$ls180.v:6805$2439 + assign { } { } + assign $0\builder_comb_rhs_array_muxed1[12:0] 13'0000000000000 + attribute \src "ls180.v:6807.2-6820.9" + switch \main_sdram_choose_cmd_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_rhs_array_muxed1[12:0] \main_sdram_bankmachine0_cmd_payload_a + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_rhs_array_muxed1[12:0] \main_sdram_bankmachine1_cmd_payload_a + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_rhs_array_muxed1[12:0] \main_sdram_bankmachine2_cmd_payload_a + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed1[12:0] \main_sdram_bankmachine3_cmd_payload_a + end + sync always + update \builder_comb_rhs_array_muxed1 $0\builder_comb_rhs_array_muxed1[12:0] + end + attribute \src "ls180.v:6822.1-6838.4" + process $proc$ls180.v:6822$2440 + assign { } { } + assign $0\builder_comb_rhs_array_muxed2[1:0] 2'00 + attribute \src "ls180.v:6824.2-6837.9" + switch \main_sdram_choose_cmd_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_rhs_array_muxed2[1:0] \main_sdram_bankmachine0_cmd_payload_ba + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_rhs_array_muxed2[1:0] \main_sdram_bankmachine1_cmd_payload_ba + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_rhs_array_muxed2[1:0] \main_sdram_bankmachine2_cmd_payload_ba + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed2[1:0] \main_sdram_bankmachine3_cmd_payload_ba + end + sync always + update \builder_comb_rhs_array_muxed2 $0\builder_comb_rhs_array_muxed2[1:0] + end + attribute \src "ls180.v:683.5-683.67" + process $proc$ls180.v:683$3338 + assign { } { } + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first[0:0] 1'0 + sync always + update \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first[0:0] + sync init + end + attribute \src "ls180.v:6839.1-6855.4" + process $proc$ls180.v:6839$2441 + assign { } { } + assign $0\builder_comb_rhs_array_muxed3[0:0] 1'0 + attribute \src "ls180.v:6841.2-6854.9" + switch \main_sdram_choose_cmd_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_rhs_array_muxed3[0:0] \main_sdram_bankmachine0_cmd_payload_is_read + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_rhs_array_muxed3[0:0] \main_sdram_bankmachine1_cmd_payload_is_read + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_rhs_array_muxed3[0:0] \main_sdram_bankmachine2_cmd_payload_is_read + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed3[0:0] \main_sdram_bankmachine3_cmd_payload_is_read + end + sync always + update \builder_comb_rhs_array_muxed3 $0\builder_comb_rhs_array_muxed3[0:0] + end + attribute \src "ls180.v:684.5-684.66" + process $proc$ls180.v:684$3339 + assign { } { } + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last[0:0] 1'0 + sync always + update \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last[0:0] + sync init + end + attribute \src "ls180.v:6856.1-6872.4" + process $proc$ls180.v:6856$2442 + assign { } { } + assign $0\builder_comb_rhs_array_muxed4[0:0] 1'0 + attribute \src "ls180.v:6858.2-6871.9" + switch \main_sdram_choose_cmd_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_rhs_array_muxed4[0:0] \main_sdram_bankmachine0_cmd_payload_is_write + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_rhs_array_muxed4[0:0] \main_sdram_bankmachine1_cmd_payload_is_write + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_rhs_array_muxed4[0:0] \main_sdram_bankmachine2_cmd_payload_is_write + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed4[0:0] \main_sdram_bankmachine3_cmd_payload_is_write + end + sync always + update \builder_comb_rhs_array_muxed4 $0\builder_comb_rhs_array_muxed4[0:0] + end + attribute \src "ls180.v:6873.1-6889.4" + process $proc$ls180.v:6873$2443 + assign { } { } + assign $0\builder_comb_rhs_array_muxed5[0:0] 1'0 + attribute \src "ls180.v:6875.2-6888.9" + switch \main_sdram_choose_cmd_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_rhs_array_muxed5[0:0] \main_sdram_bankmachine0_cmd_payload_is_cmd + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_rhs_array_muxed5[0:0] \main_sdram_bankmachine1_cmd_payload_is_cmd + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_rhs_array_muxed5[0:0] \main_sdram_bankmachine2_cmd_payload_is_cmd + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed5[0:0] \main_sdram_bankmachine3_cmd_payload_is_cmd + end + sync always + update \builder_comb_rhs_array_muxed5 $0\builder_comb_rhs_array_muxed5[0:0] + end + attribute \src "ls180.v:6890.1-6906.4" + process $proc$ls180.v:6890$2444 + assign { } { } + assign $0\builder_comb_t_array_muxed0[0:0] 1'0 + attribute \src "ls180.v:6892.2-6905.9" + switch \main_sdram_choose_cmd_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_t_array_muxed0[0:0] \main_sdram_bankmachine0_cmd_payload_cas + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_t_array_muxed0[0:0] \main_sdram_bankmachine1_cmd_payload_cas + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_t_array_muxed0[0:0] \main_sdram_bankmachine2_cmd_payload_cas + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_t_array_muxed0[0:0] \main_sdram_bankmachine3_cmd_payload_cas + end + sync always + update \builder_comb_t_array_muxed0 $0\builder_comb_t_array_muxed0[0:0] + end + attribute \src "ls180.v:6907.1-6923.4" + process $proc$ls180.v:6907$2445 + assign { } { } + assign $0\builder_comb_t_array_muxed1[0:0] 1'0 + attribute \src "ls180.v:6909.2-6922.9" + switch \main_sdram_choose_cmd_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_t_array_muxed1[0:0] \main_sdram_bankmachine0_cmd_payload_ras + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_t_array_muxed1[0:0] \main_sdram_bankmachine1_cmd_payload_ras + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_t_array_muxed1[0:0] \main_sdram_bankmachine2_cmd_payload_ras + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_t_array_muxed1[0:0] \main_sdram_bankmachine3_cmd_payload_ras + end + sync always + update \builder_comb_t_array_muxed1 $0\builder_comb_t_array_muxed1[0:0] + end + attribute \src "ls180.v:6924.1-6940.4" + process $proc$ls180.v:6924$2446 + assign { } { } + assign $0\builder_comb_t_array_muxed2[0:0] 1'0 + attribute \src "ls180.v:6926.2-6939.9" + switch \main_sdram_choose_cmd_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_t_array_muxed2[0:0] \main_sdram_bankmachine0_cmd_payload_we + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_t_array_muxed2[0:0] \main_sdram_bankmachine1_cmd_payload_we + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_t_array_muxed2[0:0] \main_sdram_bankmachine2_cmd_payload_we + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_t_array_muxed2[0:0] \main_sdram_bankmachine3_cmd_payload_we + end + sync always + update \builder_comb_t_array_muxed2 $0\builder_comb_t_array_muxed2[0:0] + end + attribute \src "ls180.v:6941.1-6957.4" + process $proc$ls180.v:6941$2447 + assign { } { } + assign $0\builder_comb_rhs_array_muxed6[0:0] 1'0 + attribute \src "ls180.v:6943.2-6956.9" + switch \main_sdram_choose_req_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_rhs_array_muxed6[0:0] \main_sdram_choose_req_valids [0] + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_rhs_array_muxed6[0:0] \main_sdram_choose_req_valids [1] + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_rhs_array_muxed6[0:0] \main_sdram_choose_req_valids [2] + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed6[0:0] \main_sdram_choose_req_valids [3] + end + sync always + update \builder_comb_rhs_array_muxed6 $0\builder_comb_rhs_array_muxed6[0:0] + end + attribute \src "ls180.v:6958.1-6974.4" + process $proc$ls180.v:6958$2448 + assign { } { } + assign $0\builder_comb_rhs_array_muxed7[12:0] 13'0000000000000 + attribute \src "ls180.v:6960.2-6973.9" + switch \main_sdram_choose_req_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_rhs_array_muxed7[12:0] \main_sdram_bankmachine0_cmd_payload_a + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_rhs_array_muxed7[12:0] \main_sdram_bankmachine1_cmd_payload_a + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_rhs_array_muxed7[12:0] \main_sdram_bankmachine2_cmd_payload_a + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed7[12:0] \main_sdram_bankmachine3_cmd_payload_a + end + sync always + update \builder_comb_rhs_array_muxed7 $0\builder_comb_rhs_array_muxed7[12:0] + end + attribute \src "ls180.v:6975.1-6991.4" + process $proc$ls180.v:6975$2449 + assign { } { } + assign $0\builder_comb_rhs_array_muxed8[1:0] 2'00 + attribute \src "ls180.v:6977.2-6990.9" + switch \main_sdram_choose_req_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_rhs_array_muxed8[1:0] \main_sdram_bankmachine0_cmd_payload_ba + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_rhs_array_muxed8[1:0] \main_sdram_bankmachine1_cmd_payload_ba + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_rhs_array_muxed8[1:0] \main_sdram_bankmachine2_cmd_payload_ba + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed8[1:0] \main_sdram_bankmachine3_cmd_payload_ba + end + sync always + update \builder_comb_rhs_array_muxed8 $0\builder_comb_rhs_array_muxed8[1:0] + end + attribute \src "ls180.v:699.11-699.68" + process $proc$ls180.v:699$3340 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] 4'0000 + sync always + sync init + update \main_sdram_bankmachine2_cmd_buffer_lookahead_level $1\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] + end + attribute \src "ls180.v:6992.1-7008.4" + process $proc$ls180.v:6992$2450 + assign { } { } + assign $0\builder_comb_rhs_array_muxed9[0:0] 1'0 + attribute \src "ls180.v:6994.2-7007.9" + switch \main_sdram_choose_req_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_rhs_array_muxed9[0:0] \main_sdram_bankmachine0_cmd_payload_is_read + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_rhs_array_muxed9[0:0] \main_sdram_bankmachine1_cmd_payload_is_read + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_rhs_array_muxed9[0:0] \main_sdram_bankmachine2_cmd_payload_is_read + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed9[0:0] \main_sdram_bankmachine3_cmd_payload_is_read + end + sync always + update \builder_comb_rhs_array_muxed9 $0\builder_comb_rhs_array_muxed9[0:0] + end + attribute \src "ls180.v:700.5-700.64" + process $proc$ls180.v:700$3341 + assign { } { } + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_replace[0:0] 1'0 + sync always + update \main_sdram_bankmachine2_cmd_buffer_lookahead_replace $0\main_sdram_bankmachine2_cmd_buffer_lookahead_replace[0:0] + sync init + end + attribute \src "ls180.v:7009.1-7025.4" + process $proc$ls180.v:7009$2451 + assign { } { } + assign $0\builder_comb_rhs_array_muxed10[0:0] 1'0 + attribute \src "ls180.v:7011.2-7024.9" + switch \main_sdram_choose_req_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_rhs_array_muxed10[0:0] \main_sdram_bankmachine0_cmd_payload_is_write + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_rhs_array_muxed10[0:0] \main_sdram_bankmachine1_cmd_payload_is_write + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_rhs_array_muxed10[0:0] \main_sdram_bankmachine2_cmd_payload_is_write + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed10[0:0] \main_sdram_bankmachine3_cmd_payload_is_write + end + sync always + update \builder_comb_rhs_array_muxed10 $0\builder_comb_rhs_array_muxed10[0:0] + end + attribute \src "ls180.v:701.11-701.70" + process $proc$ls180.v:701$3342 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine2_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] + end + attribute \src "ls180.v:702.11-702.70" + process $proc$ls180.v:702$3343 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine2_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] + end + attribute \src "ls180.v:7026.1-7042.4" + process $proc$ls180.v:7026$2452 + assign { } { } + assign $0\builder_comb_rhs_array_muxed11[0:0] 1'0 + attribute \src "ls180.v:7028.2-7041.9" + switch \main_sdram_choose_req_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_rhs_array_muxed11[0:0] \main_sdram_bankmachine0_cmd_payload_is_cmd + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_rhs_array_muxed11[0:0] \main_sdram_bankmachine1_cmd_payload_is_cmd + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_rhs_array_muxed11[0:0] \main_sdram_bankmachine2_cmd_payload_is_cmd + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed11[0:0] \main_sdram_bankmachine3_cmd_payload_is_cmd + end + sync always + update \builder_comb_rhs_array_muxed11 $0\builder_comb_rhs_array_muxed11[0:0] + end + attribute \src "ls180.v:703.11-703.73" + process $proc$ls180.v:703$3344 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr $1\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] + end + attribute \src "ls180.v:7043.1-7059.4" + process $proc$ls180.v:7043$2453 + assign { } { } + assign $0\builder_comb_t_array_muxed3[0:0] 1'0 + attribute \src "ls180.v:7045.2-7058.9" + switch \main_sdram_choose_req_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_t_array_muxed3[0:0] \main_sdram_bankmachine0_cmd_payload_cas + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_t_array_muxed3[0:0] \main_sdram_bankmachine1_cmd_payload_cas + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_t_array_muxed3[0:0] \main_sdram_bankmachine2_cmd_payload_cas + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_t_array_muxed3[0:0] \main_sdram_bankmachine3_cmd_payload_cas + end + sync always + update \builder_comb_t_array_muxed3 $0\builder_comb_t_array_muxed3[0:0] + end + attribute \src "ls180.v:7060.1-7076.4" + process $proc$ls180.v:7060$2454 + assign { } { } + assign $0\builder_comb_t_array_muxed4[0:0] 1'0 + attribute \src "ls180.v:7062.2-7075.9" + switch \main_sdram_choose_req_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_t_array_muxed4[0:0] \main_sdram_bankmachine0_cmd_payload_ras + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_t_array_muxed4[0:0] \main_sdram_bankmachine1_cmd_payload_ras + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_t_array_muxed4[0:0] \main_sdram_bankmachine2_cmd_payload_ras + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_t_array_muxed4[0:0] \main_sdram_bankmachine3_cmd_payload_ras + end + sync always + update \builder_comb_t_array_muxed4 $0\builder_comb_t_array_muxed4[0:0] + end + attribute \src "ls180.v:7077.1-7093.4" + process $proc$ls180.v:7077$2455 + assign { } { } + assign $0\builder_comb_t_array_muxed5[0:0] 1'0 + attribute \src "ls180.v:7079.2-7092.9" + switch \main_sdram_choose_req_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_t_array_muxed5[0:0] \main_sdram_bankmachine0_cmd_payload_we + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_t_array_muxed5[0:0] \main_sdram_bankmachine1_cmd_payload_we + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_t_array_muxed5[0:0] \main_sdram_bankmachine2_cmd_payload_we + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_t_array_muxed5[0:0] \main_sdram_bankmachine3_cmd_payload_we + end + sync always + update \builder_comb_t_array_muxed5 $0\builder_comb_t_array_muxed5[0:0] + end + attribute \src "ls180.v:7094.1-7101.4" + process $proc$ls180.v:7094$2456 + assign { } { } + assign $0\builder_comb_rhs_array_muxed12[21:0] 22'0000000000000000000000 + attribute \src "ls180.v:7096.2-7100.9" + switch \builder_roundrobin0_grant + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed12[21:0] { \main_port_cmd_payload_addr [23:11] \main_port_cmd_payload_addr [8:0] } + end + sync always + update \builder_comb_rhs_array_muxed12 $0\builder_comb_rhs_array_muxed12[21:0] + end + attribute \src "ls180.v:7102.1-7109.4" + process $proc$ls180.v:7102$2457 + assign { } { } + assign $0\builder_comb_rhs_array_muxed13[0:0] 1'0 + attribute \src "ls180.v:7104.2-7108.9" + switch \builder_roundrobin0_grant + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed13[0:0] \main_port_cmd_payload_we + end + sync always + update \builder_comb_rhs_array_muxed13 $0\builder_comb_rhs_array_muxed13[0:0] + end + attribute \src "ls180.v:7110.1-7117.4" + process $proc$ls180.v:7110$2458 + assign { } { } + assign $0\builder_comb_rhs_array_muxed14[0:0] 1'0 + attribute \src "ls180.v:7112.2-7116.9" + switch \builder_roundrobin0_grant + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed14[0:0] $and$ls180.v:7114$2471_Y + end + sync always + update \builder_comb_rhs_array_muxed14 $0\builder_comb_rhs_array_muxed14[0:0] + end + attribute \src "ls180.v:7118.1-7125.4" + process $proc$ls180.v:7118$2472 + assign { } { } + assign $0\builder_comb_rhs_array_muxed15[21:0] 22'0000000000000000000000 + attribute \src "ls180.v:7120.2-7124.9" + switch \builder_roundrobin1_grant + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed15[21:0] { \main_port_cmd_payload_addr [23:11] \main_port_cmd_payload_addr [8:0] } + end + sync always + update \builder_comb_rhs_array_muxed15 $0\builder_comb_rhs_array_muxed15[21:0] + end + attribute \src "ls180.v:7126.1-7133.4" + process $proc$ls180.v:7126$2473 + assign { } { } + assign $0\builder_comb_rhs_array_muxed16[0:0] 1'0 + attribute \src "ls180.v:7128.2-7132.9" + switch \builder_roundrobin1_grant + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed16[0:0] \main_port_cmd_payload_we + end + sync always + update \builder_comb_rhs_array_muxed16 $0\builder_comb_rhs_array_muxed16[0:0] + end + attribute \src "ls180.v:7134.1-7141.4" + process $proc$ls180.v:7134$2474 + assign { } { } + assign $0\builder_comb_rhs_array_muxed17[0:0] 1'0 + attribute \src "ls180.v:7136.2-7140.9" + switch \builder_roundrobin1_grant + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed17[0:0] $and$ls180.v:7138$2487_Y + end + sync always + update \builder_comb_rhs_array_muxed17 $0\builder_comb_rhs_array_muxed17[0:0] + end + attribute \src "ls180.v:7142.1-7149.4" + process $proc$ls180.v:7142$2488 + assign { } { } + assign $0\builder_comb_rhs_array_muxed18[21:0] 22'0000000000000000000000 + attribute \src "ls180.v:7144.2-7148.9" + switch \builder_roundrobin2_grant + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed18[21:0] { \main_port_cmd_payload_addr [23:11] \main_port_cmd_payload_addr [8:0] } + end + sync always + update \builder_comb_rhs_array_muxed18 $0\builder_comb_rhs_array_muxed18[21:0] + end + attribute \src "ls180.v:7150.1-7157.4" + process $proc$ls180.v:7150$2489 + assign { } { } + assign $0\builder_comb_rhs_array_muxed19[0:0] 1'0 + attribute \src "ls180.v:7152.2-7156.9" + switch \builder_roundrobin2_grant + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed19[0:0] \main_port_cmd_payload_we + end + sync always + update \builder_comb_rhs_array_muxed19 $0\builder_comb_rhs_array_muxed19[0:0] + end + attribute \src "ls180.v:7158.1-7165.4" + process $proc$ls180.v:7158$2490 + assign { } { } + assign $0\builder_comb_rhs_array_muxed20[0:0] 1'0 + attribute \src "ls180.v:7160.2-7164.9" + switch \builder_roundrobin2_grant + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed20[0:0] $and$ls180.v:7162$2503_Y + end + sync always + update \builder_comb_rhs_array_muxed20 $0\builder_comb_rhs_array_muxed20[0:0] + end + attribute \src "ls180.v:7166.1-7173.4" + process $proc$ls180.v:7166$2504 + assign { } { } + assign $0\builder_comb_rhs_array_muxed21[21:0] 22'0000000000000000000000 + attribute \src "ls180.v:7168.2-7172.9" + switch \builder_roundrobin3_grant + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed21[21:0] { \main_port_cmd_payload_addr [23:11] \main_port_cmd_payload_addr [8:0] } + end + sync always + update \builder_comb_rhs_array_muxed21 $0\builder_comb_rhs_array_muxed21[21:0] + end + attribute \src "ls180.v:7174.1-7181.4" + process $proc$ls180.v:7174$2505 + assign { } { } + assign $0\builder_comb_rhs_array_muxed22[0:0] 1'0 + attribute \src "ls180.v:7176.2-7180.9" + switch \builder_roundrobin3_grant + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed22[0:0] \main_port_cmd_payload_we + end + sync always + update \builder_comb_rhs_array_muxed22 $0\builder_comb_rhs_array_muxed22[0:0] + end + attribute \src "ls180.v:7182.1-7189.4" + process $proc$ls180.v:7182$2506 + assign { } { } + assign $0\builder_comb_rhs_array_muxed23[0:0] 1'0 + attribute \src "ls180.v:7184.2-7188.9" + switch \builder_roundrobin3_grant + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed23[0:0] $and$ls180.v:7186$2519_Y + end + sync always + update \builder_comb_rhs_array_muxed23 $0\builder_comb_rhs_array_muxed23[0:0] + end + attribute \src "ls180.v:7190.1-7209.4" + process $proc$ls180.v:7190$2520 + assign { } { } + assign $0\builder_comb_rhs_array_muxed24[31:0] 0 + attribute \src "ls180.v:7192.2-7208.9" + switch \builder_grant + attribute \src "ls180.v:0.0-0.0" + case 3'000 + assign $0\builder_comb_rhs_array_muxed24[31:0] { 3'000 \main_libresocsim_libresoc_ibus_adr } + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\builder_comb_rhs_array_muxed24[31:0] { 3'000 \main_libresocsim_libresoc_dbus_adr } + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\builder_comb_rhs_array_muxed24[31:0] { 3'000 \main_libresocsim_libresoc_jtag_wb_adr } + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\builder_comb_rhs_array_muxed24[31:0] \main_interface0_bus_adr + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed24[31:0] \main_interface1_bus_adr + end + sync always + update \builder_comb_rhs_array_muxed24 $0\builder_comb_rhs_array_muxed24[31:0] + end + attribute \src "ls180.v:7210.1-7229.4" + process $proc$ls180.v:7210$2521 + assign { } { } + assign $0\builder_comb_rhs_array_muxed25[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "ls180.v:7212.2-7228.9" + switch \builder_grant + attribute \src "ls180.v:0.0-0.0" + case 3'000 + assign $0\builder_comb_rhs_array_muxed25[63:0] \main_libresocsim_libresoc_ibus_dat_w + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\builder_comb_rhs_array_muxed25[63:0] \main_libresocsim_libresoc_dbus_dat_w + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\builder_comb_rhs_array_muxed25[63:0] \main_libresocsim_libresoc_jtag_wb_dat_w + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\builder_comb_rhs_array_muxed25[63:0] \main_interface0_bus_dat_w + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed25[63:0] \main_interface1_bus_dat_w + end + sync always + update \builder_comb_rhs_array_muxed25 $0\builder_comb_rhs_array_muxed25[63:0] + end + attribute \src "ls180.v:7230.1-7249.4" + process $proc$ls180.v:7230$2522 + assign { } { } + assign $0\builder_comb_rhs_array_muxed26[7:0] 8'00000000 + attribute \src "ls180.v:7232.2-7248.9" + switch \builder_grant + attribute \src "ls180.v:0.0-0.0" + case 3'000 + assign $0\builder_comb_rhs_array_muxed26[7:0] \main_libresocsim_libresoc_ibus_sel + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\builder_comb_rhs_array_muxed26[7:0] \main_libresocsim_libresoc_dbus_sel + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\builder_comb_rhs_array_muxed26[7:0] \main_libresocsim_libresoc_jtag_wb_sel + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\builder_comb_rhs_array_muxed26[7:0] \main_interface0_bus_sel + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed26[7:0] \main_interface1_bus_sel + end + sync always + update \builder_comb_rhs_array_muxed26 $0\builder_comb_rhs_array_muxed26[7:0] + end + attribute \src "ls180.v:724.5-724.59" + process $proc$ls180.v:724$3345 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_cmd_buffer_source_valid $1\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] + end + attribute \src "ls180.v:7250.1-7269.4" + process $proc$ls180.v:7250$2523 + assign { } { } + assign $0\builder_comb_rhs_array_muxed27[0:0] 1'0 + attribute \src "ls180.v:7252.2-7268.9" + switch \builder_grant + attribute \src "ls180.v:0.0-0.0" + case 3'000 + assign $0\builder_comb_rhs_array_muxed27[0:0] \main_libresocsim_libresoc_ibus_cyc + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\builder_comb_rhs_array_muxed27[0:0] \main_libresocsim_libresoc_dbus_cyc + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\builder_comb_rhs_array_muxed27[0:0] \main_libresocsim_libresoc_jtag_wb_cyc + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\builder_comb_rhs_array_muxed27[0:0] \main_interface0_bus_cyc + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed27[0:0] \main_interface1_bus_cyc + end + sync always + update \builder_comb_rhs_array_muxed27 $0\builder_comb_rhs_array_muxed27[0:0] + end + attribute \src "ls180.v:726.5-726.59" + process $proc$ls180.v:726$3346 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_cmd_buffer_source_first $1\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] + end + attribute \src "ls180.v:727.5-727.58" + process $proc$ls180.v:727$3347 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_cmd_buffer_source_last $1\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] + end + attribute \src "ls180.v:7270.1-7289.4" + process $proc$ls180.v:7270$2524 + assign { } { } + assign $0\builder_comb_rhs_array_muxed28[0:0] 1'0 + attribute \src "ls180.v:7272.2-7288.9" + switch \builder_grant + attribute \src "ls180.v:0.0-0.0" + case 3'000 + assign $0\builder_comb_rhs_array_muxed28[0:0] \main_libresocsim_libresoc_ibus_stb + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\builder_comb_rhs_array_muxed28[0:0] \main_libresocsim_libresoc_dbus_stb + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\builder_comb_rhs_array_muxed28[0:0] \main_libresocsim_libresoc_jtag_wb_stb + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\builder_comb_rhs_array_muxed28[0:0] \main_interface0_bus_stb + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed28[0:0] \main_interface1_bus_stb + end + sync always + update \builder_comb_rhs_array_muxed28 $0\builder_comb_rhs_array_muxed28[0:0] + end + attribute \src "ls180.v:728.5-728.64" + process $proc$ls180.v:728$3348 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_cmd_buffer_source_payload_we $1\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] + end + attribute \src "ls180.v:729.12-729.74" + process $proc$ls180.v:729$3349 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000 + sync always + sync init + update \main_sdram_bankmachine2_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] + end + attribute \src "ls180.v:7290.1-7309.4" + process $proc$ls180.v:7290$2525 + assign { } { } + assign $0\builder_comb_rhs_array_muxed29[0:0] 1'0 + attribute \src "ls180.v:7292.2-7308.9" + switch \builder_grant + attribute \src "ls180.v:0.0-0.0" + case 3'000 + assign $0\builder_comb_rhs_array_muxed29[0:0] \main_libresocsim_libresoc_ibus_we + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\builder_comb_rhs_array_muxed29[0:0] \main_libresocsim_libresoc_dbus_we + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\builder_comb_rhs_array_muxed29[0:0] \main_libresocsim_libresoc_jtag_wb_we + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\builder_comb_rhs_array_muxed29[0:0] \main_interface0_bus_we + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed29[0:0] \main_interface1_bus_we + end + sync always + update \builder_comb_rhs_array_muxed29 $0\builder_comb_rhs_array_muxed29[0:0] + end + attribute \src "ls180.v:730.12-730.47" + process $proc$ls180.v:730$3350 + assign { } { } + assign $1\main_sdram_bankmachine2_row[12:0] 13'0000000000000 + sync always + sync init + update \main_sdram_bankmachine2_row $1\main_sdram_bankmachine2_row[12:0] + end + attribute \src "ls180.v:731.5-731.46" + process $proc$ls180.v:731$3351 + assign { } { } + assign $1\main_sdram_bankmachine2_row_opened[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_row_opened $1\main_sdram_bankmachine2_row_opened[0:0] + end + attribute \src "ls180.v:7310.1-7329.4" + process $proc$ls180.v:7310$2526 + assign { } { } + assign $0\builder_comb_rhs_array_muxed30[2:0] 3'000 + attribute \src "ls180.v:7312.2-7328.9" + switch \builder_grant + attribute \src "ls180.v:0.0-0.0" + case 3'000 + assign $0\builder_comb_rhs_array_muxed30[2:0] \main_libresocsim_libresoc_ibus_cti + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\builder_comb_rhs_array_muxed30[2:0] \main_libresocsim_libresoc_dbus_cti + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\builder_comb_rhs_array_muxed30[2:0] \main_libresocsim_libresoc_jtag_wb_cti + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\builder_comb_rhs_array_muxed30[2:0] \main_interface0_bus_cti + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed30[2:0] \main_interface1_bus_cti + end + sync always + update \builder_comb_rhs_array_muxed30 $0\builder_comb_rhs_array_muxed30[2:0] + end + attribute \src "ls180.v:733.5-733.44" + process $proc$ls180.v:733$3352 + assign { } { } + assign $1\main_sdram_bankmachine2_row_open[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_row_open $1\main_sdram_bankmachine2_row_open[0:0] + end + attribute \src "ls180.v:7330.1-7349.4" + process $proc$ls180.v:7330$2527 + assign { } { } + assign $0\builder_comb_rhs_array_muxed31[1:0] 2'00 + attribute \src "ls180.v:7332.2-7348.9" + switch \builder_grant + attribute \src "ls180.v:0.0-0.0" + case 3'000 + assign $0\builder_comb_rhs_array_muxed31[1:0] \main_libresocsim_libresoc_ibus_bte + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\builder_comb_rhs_array_muxed31[1:0] \main_libresocsim_libresoc_dbus_bte + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\builder_comb_rhs_array_muxed31[1:0] \main_libresocsim_libresoc_jtag_wb_bte + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\builder_comb_rhs_array_muxed31[1:0] \main_interface0_bus_bte + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed31[1:0] \main_interface1_bus_bte + end + sync always + update \builder_comb_rhs_array_muxed31 $0\builder_comb_rhs_array_muxed31[1:0] + end + attribute \src "ls180.v:734.5-734.45" + process $proc$ls180.v:734$3353 + assign { } { } + assign $1\main_sdram_bankmachine2_row_close[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_row_close $1\main_sdram_bankmachine2_row_close[0:0] + end + attribute \src "ls180.v:735.5-735.54" + process $proc$ls180.v:735$3354 + assign { } { } + assign $1\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_row_col_n_addr_sel $1\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] + end + attribute \src "ls180.v:7350.1-7366.4" + process $proc$ls180.v:7350$2528 + assign { } { } + assign $0\builder_sync_rhs_array_muxed0[1:0] 2'00 + attribute \src "ls180.v:7352.2-7365.9" + switch \main_sdram_steerer_sel + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_sync_rhs_array_muxed0[1:0] \main_sdram_nop_ba + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_sync_rhs_array_muxed0[1:0] \main_sdram_choose_req_cmd_payload_ba + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_sync_rhs_array_muxed0[1:0] \main_sdram_choose_req_cmd_payload_ba + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_sync_rhs_array_muxed0[1:0] \main_sdram_cmd_payload_ba + end + sync always + update \builder_sync_rhs_array_muxed0 $0\builder_sync_rhs_array_muxed0[1:0] + end + attribute \src "ls180.v:7367.1-7383.4" + process $proc$ls180.v:7367$2529 + assign { } { } + assign $0\builder_sync_rhs_array_muxed1[12:0] 13'0000000000000 + attribute \src "ls180.v:7369.2-7382.9" + switch \main_sdram_steerer_sel + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_sync_rhs_array_muxed1[12:0] \main_sdram_nop_a + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_sync_rhs_array_muxed1[12:0] \main_sdram_choose_req_cmd_payload_a + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_sync_rhs_array_muxed1[12:0] \main_sdram_choose_req_cmd_payload_a + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_sync_rhs_array_muxed1[12:0] \main_sdram_cmd_payload_a + end + sync always + update \builder_sync_rhs_array_muxed1 $0\builder_sync_rhs_array_muxed1[12:0] + end + attribute \src "ls180.v:737.32-737.76" + process $proc$ls180.v:737$3355 + assign { } { } + assign $1\main_sdram_bankmachine2_twtpcon_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_twtpcon_ready $1\main_sdram_bankmachine2_twtpcon_ready[0:0] + end + attribute \src "ls180.v:738.11-738.55" + process $proc$ls180.v:738$3356 + assign { } { } + assign $1\main_sdram_bankmachine2_twtpcon_count[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine2_twtpcon_count $1\main_sdram_bankmachine2_twtpcon_count[2:0] + end + attribute \src "ls180.v:7384.1-7400.4" + process $proc$ls180.v:7384$2530 + assign { } { } + assign $0\builder_sync_rhs_array_muxed2[0:0] 1'0 + attribute \src "ls180.v:7386.2-7399.9" + switch \main_sdram_steerer_sel + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_sync_rhs_array_muxed2[0:0] 1'0 + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_sync_rhs_array_muxed2[0:0] $and$ls180.v:7391$2532_Y + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_sync_rhs_array_muxed2[0:0] $and$ls180.v:7394$2534_Y + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_sync_rhs_array_muxed2[0:0] $and$ls180.v:7397$2536_Y + end + sync always + update \builder_sync_rhs_array_muxed2 $0\builder_sync_rhs_array_muxed2[0:0] + end + attribute \src "ls180.v:74.11-74.52" + process $proc$ls180.v:74$3132 + assign { } { } + assign $0\main_libresocsim_libresoc_dbus_cti[2:0] 3'000 + sync always + update \main_libresocsim_libresoc_dbus_cti $0\main_libresocsim_libresoc_dbus_cti[2:0] + sync init + end + attribute \src "ls180.v:740.32-740.75" + process $proc$ls180.v:740$3357 + assign { } { } + assign $0\main_sdram_bankmachine2_trccon_ready[0:0] 1'1 + sync always + update \main_sdram_bankmachine2_trccon_ready $0\main_sdram_bankmachine2_trccon_ready[0:0] + sync init + end + attribute \src "ls180.v:7401.1-7417.4" + process $proc$ls180.v:7401$2537 + assign { } { } + assign $0\builder_sync_rhs_array_muxed3[0:0] 1'0 + attribute \src "ls180.v:7403.2-7416.9" + switch \main_sdram_steerer_sel + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_sync_rhs_array_muxed3[0:0] 1'0 + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_sync_rhs_array_muxed3[0:0] $and$ls180.v:7408$2539_Y + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_sync_rhs_array_muxed3[0:0] $and$ls180.v:7411$2541_Y + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_sync_rhs_array_muxed3[0:0] $and$ls180.v:7414$2543_Y + end + sync always + update \builder_sync_rhs_array_muxed3 $0\builder_sync_rhs_array_muxed3[0:0] + end + attribute \src "ls180.v:7418.1-7434.4" + process $proc$ls180.v:7418$2544 + assign { } { } + assign $0\builder_sync_rhs_array_muxed4[0:0] 1'0 + attribute \src "ls180.v:7420.2-7433.9" + switch \main_sdram_steerer_sel + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_sync_rhs_array_muxed4[0:0] 1'0 + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_sync_rhs_array_muxed4[0:0] $and$ls180.v:7425$2546_Y + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_sync_rhs_array_muxed4[0:0] $and$ls180.v:7428$2548_Y + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_sync_rhs_array_muxed4[0:0] $and$ls180.v:7431$2550_Y + end + sync always + update \builder_sync_rhs_array_muxed4 $0\builder_sync_rhs_array_muxed4[0:0] + end + attribute \src "ls180.v:742.32-742.76" + process $proc$ls180.v:742$3358 + assign { } { } + assign $0\main_sdram_bankmachine2_trascon_ready[0:0] 1'1 + sync always + update \main_sdram_bankmachine2_trascon_ready $0\main_sdram_bankmachine2_trascon_ready[0:0] + sync init + end + attribute \src "ls180.v:7435.1-7451.4" + process $proc$ls180.v:7435$2551 + assign { } { } + assign $0\builder_sync_rhs_array_muxed5[0:0] 1'0 + attribute \src "ls180.v:7437.2-7450.9" + switch \main_sdram_steerer_sel + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_sync_rhs_array_muxed5[0:0] 1'0 + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_sync_rhs_array_muxed5[0:0] $and$ls180.v:7442$2553_Y + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_sync_rhs_array_muxed5[0:0] $and$ls180.v:7445$2555_Y + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_sync_rhs_array_muxed5[0:0] $and$ls180.v:7448$2557_Y + end + sync always + update \builder_sync_rhs_array_muxed5 $0\builder_sync_rhs_array_muxed5[0:0] + end + attribute \src "ls180.v:7452.1-7468.4" + process $proc$ls180.v:7452$2558 + assign { } { } + assign $0\builder_sync_rhs_array_muxed6[0:0] 1'0 + attribute \src "ls180.v:7454.2-7467.9" + switch \main_sdram_steerer_sel + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_sync_rhs_array_muxed6[0:0] 1'0 + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_sync_rhs_array_muxed6[0:0] $and$ls180.v:7459$2560_Y + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_sync_rhs_array_muxed6[0:0] $and$ls180.v:7462$2562_Y + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_sync_rhs_array_muxed6[0:0] $and$ls180.v:7465$2564_Y + end + sync always + update \builder_sync_rhs_array_muxed6 $0\builder_sync_rhs_array_muxed6[0:0] + end + attribute \src "ls180.v:7469.1-7497.4" + process $proc$ls180.v:7469$2565 + assign { } { } + assign $0\builder_sync_f_array_muxed0[0:0] 1'0 + attribute \src "ls180.v:7471.2-7496.9" + switch \main_spimaster34_mosi_sel + attribute \src "ls180.v:0.0-0.0" + case 3'000 + assign $0\builder_sync_f_array_muxed0[0:0] \main_spimaster33_mosi_data [0] + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\builder_sync_f_array_muxed0[0:0] \main_spimaster33_mosi_data [1] + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\builder_sync_f_array_muxed0[0:0] \main_spimaster33_mosi_data [2] + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\builder_sync_f_array_muxed0[0:0] \main_spimaster33_mosi_data [3] + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\builder_sync_f_array_muxed0[0:0] \main_spimaster33_mosi_data [4] + attribute \src "ls180.v:0.0-0.0" + case 3'101 + assign $0\builder_sync_f_array_muxed0[0:0] \main_spimaster33_mosi_data [5] + attribute \src "ls180.v:0.0-0.0" + case 3'110 + assign $0\builder_sync_f_array_muxed0[0:0] \main_spimaster33_mosi_data [6] + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_sync_f_array_muxed0[0:0] \main_spimaster33_mosi_data [7] + end + sync always + update \builder_sync_f_array_muxed0 $0\builder_sync_f_array_muxed0[0:0] + end + attribute \src "ls180.v:748.5-748.51" + process $proc$ls180.v:748$3359 + assign { } { } + assign $1\main_sdram_bankmachine3_req_wdata_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_req_wdata_ready $1\main_sdram_bankmachine3_req_wdata_ready[0:0] + end + attribute \src "ls180.v:749.5-749.51" + process $proc$ls180.v:749$3360 + assign { } { } + assign $1\main_sdram_bankmachine3_req_rdata_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_req_rdata_valid $1\main_sdram_bankmachine3_req_rdata_valid[0:0] + end + attribute \src "ls180.v:7498.1-7526.4" + process $proc$ls180.v:7498$2566 + assign { } { } + assign $0\builder_sync_f_array_muxed1[0:0] 1'0 + attribute \src "ls180.v:7500.2-7525.9" + switch \main_spisdcard_mosi_sel + attribute \src "ls180.v:0.0-0.0" + case 3'000 + assign $0\builder_sync_f_array_muxed1[0:0] \main_spisdcard_mosi_data [0] + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\builder_sync_f_array_muxed1[0:0] \main_spisdcard_mosi_data [1] + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\builder_sync_f_array_muxed1[0:0] \main_spisdcard_mosi_data [2] + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\builder_sync_f_array_muxed1[0:0] \main_spisdcard_mosi_data [3] + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\builder_sync_f_array_muxed1[0:0] \main_spisdcard_mosi_data [4] + attribute \src "ls180.v:0.0-0.0" + case 3'101 + assign $0\builder_sync_f_array_muxed1[0:0] \main_spisdcard_mosi_data [5] + attribute \src "ls180.v:0.0-0.0" + case 3'110 + assign $0\builder_sync_f_array_muxed1[0:0] \main_spisdcard_mosi_data [6] + attribute \src "ls180.v:0.0-0.0" + case + assign $0\builder_sync_f_array_muxed1[0:0] \main_spisdcard_mosi_data [7] + end + sync always + update \builder_sync_f_array_muxed1 $0\builder_sync_f_array_muxed1[0:0] + end + attribute \src "ls180.v:75.11-75.52" + process $proc$ls180.v:75$3133 + assign { } { } + assign $0\main_libresocsim_libresoc_dbus_bte[1:0] 2'00 + sync always + update \main_libresocsim_libresoc_dbus_bte $0\main_libresocsim_libresoc_dbus_bte[1:0] + sync init + end + attribute \src "ls180.v:751.5-751.47" + process $proc$ls180.v:751$3361 + assign { } { } + assign $1\main_sdram_bankmachine3_refresh_gnt[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_refresh_gnt $1\main_sdram_bankmachine3_refresh_gnt[0:0] + end + attribute \src "ls180.v:752.5-752.45" + process $proc$ls180.v:752$3362 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_cmd_valid $1\main_sdram_bankmachine3_cmd_valid[0:0] + end + attribute \src "ls180.v:753.5-753.45" + process $proc$ls180.v:753$3363 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_cmd_ready $1\main_sdram_bankmachine3_cmd_ready[0:0] + end + attribute \src "ls180.v:754.12-754.57" + process $proc$ls180.v:754$3364 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_payload_a[12:0] 13'0000000000000 + sync always + sync init + update \main_sdram_bankmachine3_cmd_payload_a $1\main_sdram_bankmachine3_cmd_payload_a[12:0] + end + attribute \src "ls180.v:756.5-756.51" + process $proc$ls180.v:756$3365 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_payload_cas[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_cmd_payload_cas $1\main_sdram_bankmachine3_cmd_payload_cas[0:0] + end + attribute \src "ls180.v:757.5-757.51" + process $proc$ls180.v:757$3366 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_payload_ras[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_cmd_payload_ras $1\main_sdram_bankmachine3_cmd_payload_ras[0:0] + end + attribute \src "ls180.v:758.5-758.50" + process $proc$ls180.v:758$3367 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_payload_we[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_cmd_payload_we $1\main_sdram_bankmachine3_cmd_payload_we[0:0] + end + attribute \src "ls180.v:7584.1-7594.4" + process $proc$ls180.v:7584$2567 + assign { } { } + assign $0\main_gpiotristateasic0_status[15:0] [15:8] 8'00000000 + assign $0\main_gpiotristateasic0_status[15:0] [0] \builder_multiregimpl1_regs1 + assign $0\main_gpiotristateasic0_status[15:0] [1] \builder_multiregimpl2_regs1 + assign $0\main_gpiotristateasic0_status[15:0] [2] \builder_multiregimpl3_regs1 + assign $0\main_gpiotristateasic0_status[15:0] [3] \builder_multiregimpl4_regs1 + assign $0\main_gpiotristateasic0_status[15:0] [4] \builder_multiregimpl5_regs1 + assign $0\main_gpiotristateasic0_status[15:0] [5] \builder_multiregimpl6_regs1 + assign $0\main_gpiotristateasic0_status[15:0] [6] \builder_multiregimpl7_regs1 + assign $0\main_gpiotristateasic0_status[15:0] [7] \builder_multiregimpl8_regs1 + sync always + update \main_gpiotristateasic0_status $0\main_gpiotristateasic0_status[15:0] + end + attribute \src "ls180.v:759.5-759.54" + process $proc$ls180.v:759$3368 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_cmd_payload_is_cmd $1\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] + end + attribute \src "ls180.v:7595.1-7605.4" + process $proc$ls180.v:7595$2568 + assign { } { } + assign $0\main_gpiotristateasic1_status[15:0] [7:0] 8'00000000 + assign $0\main_gpiotristateasic1_status[15:0] [8] \builder_multiregimpl9_regs1 + assign $0\main_gpiotristateasic1_status[15:0] [9] \builder_multiregimpl10_regs1 + assign $0\main_gpiotristateasic1_status[15:0] [10] \builder_multiregimpl11_regs1 + assign $0\main_gpiotristateasic1_status[15:0] [11] \builder_multiregimpl12_regs1 + assign $0\main_gpiotristateasic1_status[15:0] [12] \builder_multiregimpl13_regs1 + assign $0\main_gpiotristateasic1_status[15:0] [13] \builder_multiregimpl14_regs1 + assign $0\main_gpiotristateasic1_status[15:0] [14] \builder_multiregimpl15_regs1 + assign $0\main_gpiotristateasic1_status[15:0] [15] \builder_multiregimpl16_regs1 + sync always + update \main_gpiotristateasic1_status $0\main_gpiotristateasic1_status[15:0] + end + attribute \src "ls180.v:760.5-760.55" + process $proc$ls180.v:760$3369 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_payload_is_read[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_cmd_payload_is_read $1\main_sdram_bankmachine3_cmd_payload_is_read[0:0] + end + attribute \src "ls180.v:761.5-761.56" + process $proc$ls180.v:761$3370 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_payload_is_write[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_cmd_payload_is_write $1\main_sdram_bankmachine3_cmd_payload_is_write[0:0] + end + attribute \src "ls180.v:762.5-762.50" + process $proc$ls180.v:762$3371 + assign { } { } + assign $1\main_sdram_bankmachine3_auto_precharge[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_auto_precharge $1\main_sdram_bankmachine3_auto_precharge[0:0] + end + attribute \src "ls180.v:7626.1-7628.4" + process $proc$ls180.v:7626$2569 + assign { } { } + assign $0\main_int_rst[0:0] \sys_rst + sync posedge \por_clk + update \main_int_rst $0\main_int_rst[0:0] + end + attribute \src "ls180.v:7630.1-7700.4" + process $proc$ls180.v:7630$2570 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\sdram_a[12:0] [0] \main_dfi_p0_address [0] + assign $0\sdram_a[12:0] [1] \main_dfi_p0_address [1] + assign $0\sdram_a[12:0] [2] \main_dfi_p0_address [2] + assign $0\sdram_a[12:0] [3] \main_dfi_p0_address [3] + assign $0\sdram_a[12:0] [4] \main_dfi_p0_address [4] + assign $0\sdram_a[12:0] [5] \main_dfi_p0_address [5] + assign $0\sdram_a[12:0] [6] \main_dfi_p0_address [6] + assign $0\sdram_a[12:0] [7] \main_dfi_p0_address [7] + assign $0\sdram_a[12:0] [8] \main_dfi_p0_address [8] + assign $0\sdram_a[12:0] [9] \main_dfi_p0_address [9] + assign $0\sdram_a[12:0] [10] \main_dfi_p0_address [10] + assign $0\sdram_a[12:0] [11] \main_dfi_p0_address [11] + assign $0\sdram_a[12:0] [12] \main_dfi_p0_address [12] + assign $0\sdram_ba[1:0] [0] \main_dfi_p0_bank [0] + assign $0\sdram_ba[1:0] [1] \main_dfi_p0_bank [1] + assign $0\sdram_cas_n[0:0] \main_dfi_p0_cas_n + assign $0\sdram_ras_n[0:0] \main_dfi_p0_ras_n + assign $0\sdram_we_n[0:0] \main_dfi_p0_we_n + assign $0\sdram_cke[0:0] \main_dfi_p0_cke + assign $0\sdram_cs_n[0:0] \main_dfi_p0_cs_n + assign $0\sdram_dq_oe[0:0] \main_dfi_p0_wrdata_en + assign $0\sdram_dq_o[15:0] [0] \main_dfi_p0_wrdata [0] + assign $0\main_dfi_p0_rddata[15:0] [0] \sdram_dq_i [0] + assign $0\sdram_dq_o[15:0] [1] \main_dfi_p0_wrdata [1] + assign $0\main_dfi_p0_rddata[15:0] [1] \sdram_dq_i [1] + assign $0\sdram_dq_o[15:0] [2] \main_dfi_p0_wrdata [2] + assign $0\main_dfi_p0_rddata[15:0] [2] \sdram_dq_i [2] + assign $0\sdram_dq_o[15:0] [3] \main_dfi_p0_wrdata [3] + assign $0\main_dfi_p0_rddata[15:0] [3] \sdram_dq_i [3] + assign $0\sdram_dq_o[15:0] [4] \main_dfi_p0_wrdata [4] + assign $0\main_dfi_p0_rddata[15:0] [4] \sdram_dq_i [4] + assign $0\sdram_dq_o[15:0] [5] \main_dfi_p0_wrdata [5] + assign $0\main_dfi_p0_rddata[15:0] [5] \sdram_dq_i [5] + assign $0\sdram_dq_o[15:0] [6] \main_dfi_p0_wrdata [6] + assign $0\main_dfi_p0_rddata[15:0] [6] \sdram_dq_i [6] + assign $0\sdram_dq_o[15:0] [7] \main_dfi_p0_wrdata [7] + assign $0\main_dfi_p0_rddata[15:0] [7] \sdram_dq_i [7] + assign $0\sdram_dq_o[15:0] [8] \main_dfi_p0_wrdata [8] + assign $0\main_dfi_p0_rddata[15:0] [8] \sdram_dq_i [8] + assign $0\sdram_dq_o[15:0] [9] \main_dfi_p0_wrdata [9] + assign $0\main_dfi_p0_rddata[15:0] [9] \sdram_dq_i [9] + assign $0\sdram_dq_o[15:0] [10] \main_dfi_p0_wrdata [10] + assign $0\main_dfi_p0_rddata[15:0] [10] \sdram_dq_i [10] + assign $0\sdram_dq_o[15:0] [11] \main_dfi_p0_wrdata [11] + assign $0\main_dfi_p0_rddata[15:0] [11] \sdram_dq_i [11] + assign $0\sdram_dq_o[15:0] [12] \main_dfi_p0_wrdata [12] + assign $0\main_dfi_p0_rddata[15:0] [12] \sdram_dq_i [12] + assign $0\sdram_dq_o[15:0] [13] \main_dfi_p0_wrdata [13] + assign $0\main_dfi_p0_rddata[15:0] [13] \sdram_dq_i [13] + assign $0\sdram_dq_o[15:0] [14] \main_dfi_p0_wrdata [14] + assign $0\main_dfi_p0_rddata[15:0] [14] \sdram_dq_i [14] + assign $0\sdram_dq_o[15:0] [15] \main_dfi_p0_wrdata [15] + assign $0\main_dfi_p0_rddata[15:0] [15] \sdram_dq_i [15] + assign $0\sdram_dm[1:0] [0] \main_dfi_p0_wrdata_mask [0] + assign $0\sdram_dm[1:0] [1] \main_dfi_p0_wrdata_mask [1] + assign $0\sdram_clock[0:0] \sys_clk_1 + assign $0\sdcard_clk[0:0] $and$ls180.v:7687$2572_Y + assign $0\sdcard_cmd_oe[0:0] \main_sdphy_sdpads_cmd_oe + assign $0\sdcard_cmd_o[0:0] \main_sdphy_sdpads_cmd_o + assign $0\main_sdphy_sdpads_cmd_i[0:0] \sdcard_cmd_i + assign $0\sdcard_data_oe[0:0] \main_sdphy_sdpads_data_oe + assign $0\sdcard_data_o[3:0] [0] \main_sdphy_sdpads_data_o [0] + assign $0\main_sdphy_sdpads_data_i[3:0] [0] \sdcard_data_i [0] + assign $0\sdcard_data_o[3:0] [1] \main_sdphy_sdpads_data_o [1] + assign $0\main_sdphy_sdpads_data_i[3:0] [1] \sdcard_data_i [1] + assign $0\sdcard_data_o[3:0] [2] \main_sdphy_sdpads_data_o [2] + assign $0\main_sdphy_sdpads_data_i[3:0] [2] \sdcard_data_i [2] + assign $0\sdcard_data_o[3:0] [3] \main_sdphy_sdpads_data_o [3] + assign $0\main_sdphy_sdpads_data_i[3:0] [3] \sdcard_data_i [3] + sync posedge \sdrio_clk + update \sdram_a $0\sdram_a[12:0] + update \sdram_dq_o $0\sdram_dq_o[15:0] + update \sdram_dq_oe $0\sdram_dq_oe[0:0] + update \sdram_we_n $0\sdram_we_n[0:0] + update \sdram_ras_n $0\sdram_ras_n[0:0] + update \sdram_cas_n $0\sdram_cas_n[0:0] + update \sdram_cs_n $0\sdram_cs_n[0:0] + update \sdram_cke $0\sdram_cke[0:0] + update \sdram_ba $0\sdram_ba[1:0] + update \sdram_dm $0\sdram_dm[1:0] + update \sdram_clock $0\sdram_clock[0:0] + update \sdcard_clk $0\sdcard_clk[0:0] + update \sdcard_cmd_o $0\sdcard_cmd_o[0:0] + update \sdcard_cmd_oe $0\sdcard_cmd_oe[0:0] + update \sdcard_data_o $0\sdcard_data_o[3:0] + update \sdcard_data_oe $0\sdcard_data_oe[0:0] + update \main_dfi_p0_rddata $0\main_dfi_p0_rddata[15:0] + update \main_sdphy_sdpads_cmd_i $0\main_sdphy_sdpads_cmd_i[0:0] + update \main_sdphy_sdpads_data_i $0\main_sdphy_sdpads_data_i[3:0] + end + attribute \src "ls180.v:765.5-765.67" + process $proc$ls180.v:765$3372 + assign { } { } + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first[0:0] 1'0 + sync always + update \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first[0:0] + sync init + end + attribute \src "ls180.v:766.5-766.66" + process $proc$ls180.v:766$3373 + assign { } { } + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last[0:0] 1'0 + sync always + update \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last[0:0] + sync init + end + attribute \src "ls180.v:7702.1-10346.4" + process $proc$ls180.v:7702$2573 + assign $0\pwm[1:0] \pwm + assign $0\spisdcard_clk[0:0] \spisdcard_clk + assign $0\spisdcard_mosi[0:0] \spisdcard_mosi + assign { } { } + assign $0\uart_tx[0:0] \uart_tx + assign $0\spimaster_clk[0:0] \spimaster_clk + assign $0\spimaster_mosi[0:0] \spimaster_mosi + assign { } { } + assign $0\main_libresocsim_reset_storage[0:0] \main_libresocsim_reset_storage + assign { } { } + assign $0\main_libresocsim_scratch_storage[31:0] \main_libresocsim_scratch_storage + assign { } { } + assign $0\main_libresocsim_bus_errors[31:0] \main_libresocsim_bus_errors + assign { } { } + assign $0\main_libresocsim_load_storage[31:0] \main_libresocsim_load_storage + assign { } { } + assign $0\main_libresocsim_reload_storage[31:0] \main_libresocsim_reload_storage + assign { } { } + assign $0\main_libresocsim_en_storage[0:0] \main_libresocsim_en_storage + assign { } { } + assign $0\main_libresocsim_update_value_storage[0:0] \main_libresocsim_update_value_storage + assign { } { } + assign $0\main_libresocsim_value_status[31:0] \main_libresocsim_value_status + assign $0\main_libresocsim_zero_pending[0:0] \main_libresocsim_zero_pending + assign { } { } + assign $0\main_libresocsim_eventmanager_storage[0:0] \main_libresocsim_eventmanager_storage + assign { } { } + assign $0\main_libresocsim_value[31:0] \main_libresocsim_value + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_converter0_counter[0:0] \main_converter0_counter + assign $0\main_converter0_dat_r[63:0] \main_converter0_dat_r + assign $0\main_converter1_counter[0:0] \main_converter1_counter + assign $0\main_converter1_dat_r[63:0] \main_converter1_dat_r + assign { } { } + assign { } { } + assign $0\main_sdram_storage[3:0] \main_sdram_storage + assign { } { } + assign $0\main_sdram_command_storage[5:0] \main_sdram_command_storage + assign { } { } + assign $0\main_sdram_address_storage[12:0] \main_sdram_address_storage + assign { } { } + assign $0\main_sdram_baddress_storage[1:0] \main_sdram_baddress_storage + assign { } { } + assign $0\main_sdram_wrdata_storage[15:0] \main_sdram_wrdata_storage + assign { } { } + assign $0\main_sdram_status[15:0] \main_sdram_status + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdram_timer_count1[9:0] \main_sdram_timer_count1 + assign { } { } + assign $0\main_sdram_postponer_count[0:0] \main_sdram_postponer_count + assign { } { } + assign $0\main_sdram_sequencer_counter[3:0] \main_sdram_sequencer_counter + assign $0\main_sdram_sequencer_count[0:0] \main_sdram_sequencer_count + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] \main_sdram_bankmachine0_cmd_buffer_lookahead_level + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] \main_sdram_bankmachine0_cmd_buffer_lookahead_produce + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] \main_sdram_bankmachine0_cmd_buffer_lookahead_consume + assign $0\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine0_cmd_buffer_source_valid + assign $0\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] \main_sdram_bankmachine0_cmd_buffer_source_first + assign $0\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] \main_sdram_bankmachine0_cmd_buffer_source_last + assign $0\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] \main_sdram_bankmachine0_cmd_buffer_source_payload_we + assign $0\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine0_cmd_buffer_source_payload_addr + assign $0\main_sdram_bankmachine0_row[12:0] \main_sdram_bankmachine0_row + assign $0\main_sdram_bankmachine0_row_opened[0:0] \main_sdram_bankmachine0_row_opened + assign $0\main_sdram_bankmachine0_twtpcon_ready[0:0] \main_sdram_bankmachine0_twtpcon_ready + assign $0\main_sdram_bankmachine0_twtpcon_count[2:0] \main_sdram_bankmachine0_twtpcon_count + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] \main_sdram_bankmachine1_cmd_buffer_lookahead_level + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] \main_sdram_bankmachine1_cmd_buffer_lookahead_produce + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] \main_sdram_bankmachine1_cmd_buffer_lookahead_consume + assign $0\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine1_cmd_buffer_source_valid + assign $0\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] \main_sdram_bankmachine1_cmd_buffer_source_first + assign $0\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] \main_sdram_bankmachine1_cmd_buffer_source_last + assign $0\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] \main_sdram_bankmachine1_cmd_buffer_source_payload_we + assign $0\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine1_cmd_buffer_source_payload_addr + assign $0\main_sdram_bankmachine1_row[12:0] \main_sdram_bankmachine1_row + assign $0\main_sdram_bankmachine1_row_opened[0:0] \main_sdram_bankmachine1_row_opened + assign $0\main_sdram_bankmachine1_twtpcon_ready[0:0] \main_sdram_bankmachine1_twtpcon_ready + assign $0\main_sdram_bankmachine1_twtpcon_count[2:0] \main_sdram_bankmachine1_twtpcon_count + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] \main_sdram_bankmachine2_cmd_buffer_lookahead_level + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] \main_sdram_bankmachine2_cmd_buffer_lookahead_produce + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] \main_sdram_bankmachine2_cmd_buffer_lookahead_consume + assign $0\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine2_cmd_buffer_source_valid + assign $0\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] \main_sdram_bankmachine2_cmd_buffer_source_first + assign $0\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] \main_sdram_bankmachine2_cmd_buffer_source_last + assign $0\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] \main_sdram_bankmachine2_cmd_buffer_source_payload_we + assign $0\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine2_cmd_buffer_source_payload_addr + assign $0\main_sdram_bankmachine2_row[12:0] \main_sdram_bankmachine2_row + assign $0\main_sdram_bankmachine2_row_opened[0:0] \main_sdram_bankmachine2_row_opened + assign $0\main_sdram_bankmachine2_twtpcon_ready[0:0] \main_sdram_bankmachine2_twtpcon_ready + assign $0\main_sdram_bankmachine2_twtpcon_count[2:0] \main_sdram_bankmachine2_twtpcon_count + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] \main_sdram_bankmachine3_cmd_buffer_lookahead_level + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] \main_sdram_bankmachine3_cmd_buffer_lookahead_produce + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] \main_sdram_bankmachine3_cmd_buffer_lookahead_consume + assign $0\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine3_cmd_buffer_source_valid + assign $0\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] \main_sdram_bankmachine3_cmd_buffer_source_first + assign $0\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] \main_sdram_bankmachine3_cmd_buffer_source_last + assign $0\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] \main_sdram_bankmachine3_cmd_buffer_source_payload_we + assign $0\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine3_cmd_buffer_source_payload_addr + assign $0\main_sdram_bankmachine3_row[12:0] \main_sdram_bankmachine3_row + assign $0\main_sdram_bankmachine3_row_opened[0:0] \main_sdram_bankmachine3_row_opened + assign $0\main_sdram_bankmachine3_twtpcon_ready[0:0] \main_sdram_bankmachine3_twtpcon_ready + assign $0\main_sdram_bankmachine3_twtpcon_count[2:0] \main_sdram_bankmachine3_twtpcon_count + assign $0\main_sdram_choose_cmd_grant[1:0] \main_sdram_choose_cmd_grant + assign $0\main_sdram_choose_req_grant[1:0] \main_sdram_choose_req_grant + assign $0\main_sdram_tccdcon_ready[0:0] \main_sdram_tccdcon_ready + assign $0\main_sdram_tccdcon_count[0:0] \main_sdram_tccdcon_count + assign $0\main_sdram_twtrcon_ready[0:0] \main_sdram_twtrcon_ready + assign $0\main_sdram_twtrcon_count[2:0] \main_sdram_twtrcon_count + assign $0\main_sdram_time0[4:0] \main_sdram_time0 + assign $0\main_sdram_time1[3:0] \main_sdram_time1 + assign $0\main_socbushandler_counter[0:0] \main_socbushandler_counter + assign $0\main_socbushandler_dat_r[63:0] \main_socbushandler_dat_r + assign $0\main_converter_counter[0:0] \main_converter_counter + assign $0\main_converter_dat_r[31:0] \main_converter_dat_r + assign $0\main_cmd_consumed[0:0] \main_cmd_consumed + assign $0\main_wdata_consumed[0:0] \main_wdata_consumed + assign $0\main_uart_phy_storage[31:0] \main_uart_phy_storage + assign { } { } + assign { } { } + assign $0\main_uart_phy_uart_clk_txen[0:0] \main_uart_phy_uart_clk_txen + assign $0\main_uart_phy_phase_accumulator_tx[31:0] \main_uart_phy_phase_accumulator_tx + assign $0\main_uart_phy_tx_reg[7:0] \main_uart_phy_tx_reg + assign $0\main_uart_phy_tx_bitcount[3:0] \main_uart_phy_tx_bitcount + assign $0\main_uart_phy_tx_busy[0:0] \main_uart_phy_tx_busy + assign { } { } + assign $0\main_uart_phy_source_payload_data[7:0] \main_uart_phy_source_payload_data + assign $0\main_uart_phy_uart_clk_rxen[0:0] \main_uart_phy_uart_clk_rxen + assign $0\main_uart_phy_phase_accumulator_rx[31:0] \main_uart_phy_phase_accumulator_rx + assign { } { } + assign $0\main_uart_phy_rx_reg[7:0] \main_uart_phy_rx_reg + assign $0\main_uart_phy_rx_bitcount[3:0] \main_uart_phy_rx_bitcount + assign $0\main_uart_phy_rx_busy[0:0] \main_uart_phy_rx_busy + assign $0\main_uart_tx_pending[0:0] \main_uart_tx_pending + assign { } { } + assign $0\main_uart_rx_pending[0:0] \main_uart_rx_pending + assign { } { } + assign $0\main_uart_eventmanager_storage[1:0] \main_uart_eventmanager_storage + assign { } { } + assign $0\main_uart_tx_fifo_readable[0:0] \main_uart_tx_fifo_readable + assign $0\main_uart_tx_fifo_level0[4:0] \main_uart_tx_fifo_level0 + assign $0\main_uart_tx_fifo_produce[3:0] \main_uart_tx_fifo_produce + assign $0\main_uart_tx_fifo_consume[3:0] \main_uart_tx_fifo_consume + assign $0\main_uart_rx_fifo_readable[0:0] \main_uart_rx_fifo_readable + assign $0\main_uart_rx_fifo_level0[4:0] \main_uart_rx_fifo_level0 + assign $0\main_uart_rx_fifo_produce[3:0] \main_uart_rx_fifo_produce + assign $0\main_uart_rx_fifo_consume[3:0] \main_uart_rx_fifo_consume + assign $0\main_gpiotristateasic1_oe_storage[15:0] \main_gpiotristateasic1_oe_storage + assign { } { } + assign $0\main_gpiotristateasic1_out_storage[15:0] \main_gpiotristateasic1_out_storage + assign { } { } + assign $0\main_spimaster5_miso[7:0] \main_spimaster5_miso + assign $0\main_spimaster11_storage[15:0] \main_spimaster11_storage + assign { } { } + assign $0\main_spimaster16_storage[7:0] \main_spimaster16_storage + assign { } { } + assign $0\main_spimaster21_storage[0:0] \main_spimaster21_storage + assign { } { } + assign $0\main_spimaster23_storage[0:0] \main_spimaster23_storage + assign { } { } + assign $0\main_spimaster27_count[2:0] \main_spimaster27_count + assign { } { } + assign $0\main_spimaster33_mosi_data[7:0] \main_spimaster33_mosi_data + assign $0\main_spimaster34_mosi_sel[2:0] \main_spimaster34_mosi_sel + assign $0\main_spimaster35_miso_data[7:0] \main_spimaster35_miso_data + assign $0\main_spisdcard_miso[7:0] \main_spisdcard_miso + assign $0\main_spisdcard_control_storage[15:0] \main_spisdcard_control_storage + assign { } { } + assign $0\main_spisdcard_mosi_storage[7:0] \main_spisdcard_mosi_storage + assign { } { } + assign $0\main_spisdcard_cs_storage[0:0] \main_spisdcard_cs_storage + assign { } { } + assign $0\main_spisdcard_loopback_storage[0:0] \main_spisdcard_loopback_storage + assign { } { } + assign $0\main_spisdcard_count[2:0] \main_spisdcard_count + assign { } { } + assign $0\main_spisdcard_mosi_data[7:0] \main_spisdcard_mosi_data + assign $0\main_spisdcard_mosi_sel[2:0] \main_spisdcard_mosi_sel + assign $0\main_spisdcard_miso_data[7:0] \main_spisdcard_miso_data + assign $0\main_spimaster1_storage[15:0] \main_spimaster1_storage + assign { } { } + assign { } { } + assign $0\main_pwm0_counter[31:0] \main_pwm0_counter + assign $0\main_pwm0_enable_storage[0:0] \main_pwm0_enable_storage + assign { } { } + assign $0\main_pwm0_width_storage[31:0] \main_pwm0_width_storage + assign { } { } + assign $0\main_pwm0_period_storage[31:0] \main_pwm0_period_storage + assign { } { } + assign $0\main_pwm1_counter[31:0] \main_pwm1_counter + assign $0\main_pwm1_enable_storage[0:0] \main_pwm1_enable_storage + assign { } { } + assign $0\main_pwm1_width_storage[31:0] \main_pwm1_width_storage + assign { } { } + assign $0\main_pwm1_period_storage[31:0] \main_pwm1_period_storage + assign { } { } + assign $0\main_i2c_storage[2:0] \main_i2c_storage + assign { } { } + assign $0\main_sdphy_clocker_storage[8:0] \main_sdphy_clocker_storage + assign { } { } + assign { } { } + assign $0\main_sdphy_clocker_clks[8:0] \main_sdphy_clocker_clks + assign { } { } + assign $0\main_sdphy_init_count[7:0] \main_sdphy_init_count + assign $0\main_sdphy_cmdw_count[7:0] \main_sdphy_cmdw_count + assign $0\main_sdphy_cmdr_timeout[31:0] \main_sdphy_cmdr_timeout + assign $0\main_sdphy_cmdr_count[7:0] \main_sdphy_cmdr_count + assign $0\main_sdphy_cmdr_cmdr_run[0:0] \main_sdphy_cmdr_cmdr_run + assign $0\main_sdphy_cmdr_cmdr_converter_source_first[0:0] \main_sdphy_cmdr_cmdr_converter_source_first + assign $0\main_sdphy_cmdr_cmdr_converter_source_last[0:0] \main_sdphy_cmdr_cmdr_converter_source_last + assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] \main_sdphy_cmdr_cmdr_converter_source_payload_data + assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] \main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count + assign $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] \main_sdphy_cmdr_cmdr_converter_demux + assign $0\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] \main_sdphy_cmdr_cmdr_converter_strobe_all + assign $0\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] \main_sdphy_cmdr_cmdr_buf_source_valid + assign $0\main_sdphy_cmdr_cmdr_buf_source_first[0:0] \main_sdphy_cmdr_cmdr_buf_source_first + assign $0\main_sdphy_cmdr_cmdr_buf_source_last[0:0] \main_sdphy_cmdr_cmdr_buf_source_last + assign $0\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0] \main_sdphy_cmdr_cmdr_buf_source_payload_data + assign $0\main_sdphy_cmdr_cmdr_reset[0:0] \main_sdphy_cmdr_cmdr_reset + assign $0\main_sdphy_dataw_count[7:0] \main_sdphy_dataw_count + assign $0\main_sdphy_dataw_crcr_run[0:0] \main_sdphy_dataw_crcr_run + assign $0\main_sdphy_dataw_crcr_converter_source_first[0:0] \main_sdphy_dataw_crcr_converter_source_first + assign $0\main_sdphy_dataw_crcr_converter_source_last[0:0] \main_sdphy_dataw_crcr_converter_source_last + assign $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] \main_sdphy_dataw_crcr_converter_source_payload_data + assign $0\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] \main_sdphy_dataw_crcr_converter_source_payload_valid_token_count + assign $0\main_sdphy_dataw_crcr_converter_demux[2:0] \main_sdphy_dataw_crcr_converter_demux + assign $0\main_sdphy_dataw_crcr_converter_strobe_all[0:0] \main_sdphy_dataw_crcr_converter_strobe_all + assign $0\main_sdphy_dataw_crcr_buf_source_valid[0:0] \main_sdphy_dataw_crcr_buf_source_valid + assign $0\main_sdphy_dataw_crcr_buf_source_first[0:0] \main_sdphy_dataw_crcr_buf_source_first + assign $0\main_sdphy_dataw_crcr_buf_source_last[0:0] \main_sdphy_dataw_crcr_buf_source_last + assign $0\main_sdphy_dataw_crcr_buf_source_payload_data[7:0] \main_sdphy_dataw_crcr_buf_source_payload_data + assign $0\main_sdphy_dataw_crcr_reset[0:0] \main_sdphy_dataw_crcr_reset + assign $0\main_sdphy_datar_timeout[31:0] \main_sdphy_datar_timeout + assign $0\main_sdphy_datar_count[9:0] \main_sdphy_datar_count + assign $0\main_sdphy_datar_datar_run[0:0] \main_sdphy_datar_datar_run + assign $0\main_sdphy_datar_datar_converter_source_first[0:0] \main_sdphy_datar_datar_converter_source_first + assign $0\main_sdphy_datar_datar_converter_source_last[0:0] \main_sdphy_datar_datar_converter_source_last + assign $0\main_sdphy_datar_datar_converter_source_payload_data[7:0] \main_sdphy_datar_datar_converter_source_payload_data + assign $0\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] \main_sdphy_datar_datar_converter_source_payload_valid_token_count + assign $0\main_sdphy_datar_datar_converter_demux[0:0] \main_sdphy_datar_datar_converter_demux + assign $0\main_sdphy_datar_datar_converter_strobe_all[0:0] \main_sdphy_datar_datar_converter_strobe_all + assign $0\main_sdphy_datar_datar_buf_source_valid[0:0] \main_sdphy_datar_datar_buf_source_valid + assign $0\main_sdphy_datar_datar_buf_source_first[0:0] \main_sdphy_datar_datar_buf_source_first + assign $0\main_sdphy_datar_datar_buf_source_last[0:0] \main_sdphy_datar_datar_buf_source_last + assign $0\main_sdphy_datar_datar_buf_source_payload_data[7:0] \main_sdphy_datar_datar_buf_source_payload_data + assign $0\main_sdphy_datar_datar_reset[0:0] \main_sdphy_datar_datar_reset + assign $0\main_sdcore_cmd_argument_storage[31:0] \main_sdcore_cmd_argument_storage + assign { } { } + assign $0\main_sdcore_cmd_command_storage[31:0] \main_sdcore_cmd_command_storage + assign { } { } + assign $0\main_sdcore_cmd_response_status[127:0] \main_sdcore_cmd_response_status + assign $0\main_sdcore_block_length_storage[9:0] \main_sdcore_block_length_storage + assign { } { } + assign $0\main_sdcore_block_count_storage[31:0] \main_sdcore_block_count_storage + assign { } { } + assign $0\main_sdcore_crc7_inserter_crcreg0[6:0] \main_sdcore_crc7_inserter_crcreg0 + assign $0\main_sdcore_crc16_inserter_cnt[2:0] \main_sdcore_crc16_inserter_cnt + assign $0\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] \main_sdcore_crc16_inserter_crc0_crcreg0 + assign $0\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] \main_sdcore_crc16_inserter_crc1_crcreg0 + assign $0\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] \main_sdcore_crc16_inserter_crc2_crcreg0 + assign $0\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] \main_sdcore_crc16_inserter_crc3_crcreg0 + assign $0\main_sdcore_crc16_inserter_crctmp0[15:0] \main_sdcore_crc16_inserter_crctmp0 + assign $0\main_sdcore_crc16_inserter_crctmp1[15:0] \main_sdcore_crc16_inserter_crctmp1 + assign $0\main_sdcore_crc16_inserter_crctmp2[15:0] \main_sdcore_crc16_inserter_crctmp2 + assign $0\main_sdcore_crc16_inserter_crctmp3[15:0] \main_sdcore_crc16_inserter_crctmp3 + assign $0\main_sdcore_crc16_checker_val[7:0] \main_sdcore_crc16_checker_val + assign $0\main_sdcore_crc16_checker_cnt[3:0] \main_sdcore_crc16_checker_cnt + assign $0\main_sdcore_crc16_checker_crc0_crcreg0[15:0] \main_sdcore_crc16_checker_crc0_crcreg0 + assign $0\main_sdcore_crc16_checker_crc1_crcreg0[15:0] \main_sdcore_crc16_checker_crc1_crcreg0 + assign $0\main_sdcore_crc16_checker_crc2_crcreg0[15:0] \main_sdcore_crc16_checker_crc2_crcreg0 + assign $0\main_sdcore_crc16_checker_crc3_crcreg0[15:0] \main_sdcore_crc16_checker_crc3_crcreg0 + assign $0\main_sdcore_crc16_checker_crctmp0[15:0] \main_sdcore_crc16_checker_crctmp0 + assign $0\main_sdcore_crc16_checker_crctmp1[15:0] \main_sdcore_crc16_checker_crctmp1 + assign $0\main_sdcore_crc16_checker_crctmp2[15:0] \main_sdcore_crc16_checker_crctmp2 + assign $0\main_sdcore_crc16_checker_crctmp3[15:0] \main_sdcore_crc16_checker_crctmp3 + assign $0\main_sdcore_crc16_checker_fifo0[15:0] \main_sdcore_crc16_checker_fifo0 + assign $0\main_sdcore_crc16_checker_fifo1[15:0] \main_sdcore_crc16_checker_fifo1 + assign $0\main_sdcore_crc16_checker_fifo2[15:0] \main_sdcore_crc16_checker_fifo2 + assign $0\main_sdcore_crc16_checker_fifo3[15:0] \main_sdcore_crc16_checker_fifo3 + assign $0\main_sdcore_cmd_count[2:0] \main_sdcore_cmd_count + assign $0\main_sdcore_cmd_done[0:0] \main_sdcore_cmd_done + assign $0\main_sdcore_cmd_error[0:0] \main_sdcore_cmd_error + assign $0\main_sdcore_cmd_timeout[0:0] \main_sdcore_cmd_timeout + assign $0\main_sdcore_data_count[31:0] \main_sdcore_data_count + assign $0\main_sdcore_data_done[0:0] \main_sdcore_data_done + assign $0\main_sdcore_data_error[0:0] \main_sdcore_data_error + assign $0\main_sdcore_data_timeout[0:0] \main_sdcore_data_timeout + assign $0\main_sdblock2mem_fifo_level[5:0] \main_sdblock2mem_fifo_level + assign $0\main_sdblock2mem_fifo_produce[4:0] \main_sdblock2mem_fifo_produce + assign $0\main_sdblock2mem_fifo_consume[4:0] \main_sdblock2mem_fifo_consume + assign $0\main_sdblock2mem_converter_source_first[0:0] \main_sdblock2mem_converter_source_first + assign $0\main_sdblock2mem_converter_source_last[0:0] \main_sdblock2mem_converter_source_last + assign $0\main_sdblock2mem_converter_source_payload_data[63:0] \main_sdblock2mem_converter_source_payload_data + assign $0\main_sdblock2mem_converter_source_payload_valid_token_count[3:0] \main_sdblock2mem_converter_source_payload_valid_token_count + assign $0\main_sdblock2mem_converter_demux[2:0] \main_sdblock2mem_converter_demux + assign $0\main_sdblock2mem_converter_strobe_all[0:0] \main_sdblock2mem_converter_strobe_all + assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] \main_sdblock2mem_wishbonedmawriter_base_storage + assign { } { } + assign $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] \main_sdblock2mem_wishbonedmawriter_length_storage + assign { } { } + assign $0\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] \main_sdblock2mem_wishbonedmawriter_enable_storage + assign { } { } + assign $0\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] \main_sdblock2mem_wishbonedmawriter_loop_storage + assign { } { } + assign $0\main_sdblock2mem_wishbonedmawriter_offset[31:0] \main_sdblock2mem_wishbonedmawriter_offset + assign $0\main_sdmem2block_dma_data[63:0] \main_sdmem2block_dma_data + assign $0\main_sdmem2block_dma_base_storage[63:0] \main_sdmem2block_dma_base_storage + assign { } { } + assign $0\main_sdmem2block_dma_length_storage[31:0] \main_sdmem2block_dma_length_storage + assign { } { } + assign $0\main_sdmem2block_dma_enable_storage[0:0] \main_sdmem2block_dma_enable_storage + assign { } { } + assign $0\main_sdmem2block_dma_loop_storage[0:0] \main_sdmem2block_dma_loop_storage + assign { } { } + assign $0\main_sdmem2block_dma_offset[31:0] \main_sdmem2block_dma_offset + assign $0\main_sdmem2block_converter_mux[2:0] \main_sdmem2block_converter_mux + assign $0\main_sdmem2block_fifo_level[5:0] \main_sdmem2block_fifo_level + assign $0\main_sdmem2block_fifo_produce[4:0] \main_sdmem2block_fifo_produce + assign $0\main_sdmem2block_fifo_consume[4:0] \main_sdmem2block_fifo_consume + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\builder_libresocsim_adr[13:0] \builder_libresocsim_adr + assign $0\builder_libresocsim_we[0:0] \builder_libresocsim_we + assign $0\builder_libresocsim_dat_w[7:0] \builder_libresocsim_dat_w + assign $0\builder_grant[2:0] \builder_grant + assign { } { } + assign $0\builder_count[19:0] \builder_count + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_dummy[23:0] [0] $or$ls180.v:7703$2574_Y + assign $0\main_dummy[23:0] [1] $or$ls180.v:7704$2575_Y + assign $0\main_dummy[23:0] [2] $or$ls180.v:7705$2576_Y + assign $0\main_dummy[23:0] [3] $or$ls180.v:7706$2577_Y + assign $0\main_dummy[23:0] [4] $or$ls180.v:7707$2578_Y + assign $0\main_dummy[23:0] [5] $or$ls180.v:7708$2579_Y + assign $0\main_dummy[23:0] [6] $or$ls180.v:7709$2580_Y + assign $0\main_dummy[23:0] [7] $or$ls180.v:7710$2581_Y + assign $0\main_dummy[23:0] [8] $or$ls180.v:7711$2582_Y + assign $0\main_dummy[23:0] [9] $or$ls180.v:7712$2583_Y + assign $0\main_dummy[23:0] [10] $or$ls180.v:7713$2584_Y + assign $0\main_dummy[23:0] [11] $or$ls180.v:7714$2585_Y + assign $0\main_dummy[23:0] [12] $or$ls180.v:7715$2586_Y + assign $0\main_dummy[23:0] [13] $or$ls180.v:7716$2587_Y + assign $0\main_dummy[23:0] [14] $or$ls180.v:7717$2588_Y + assign $0\main_dummy[23:0] [15] $or$ls180.v:7718$2589_Y + assign $0\main_dummy[23:0] [16] $or$ls180.v:7719$2590_Y + assign $0\main_dummy[23:0] [17] $or$ls180.v:7720$2591_Y + assign $0\main_dummy[23:0] [18] $or$ls180.v:7721$2592_Y + assign $0\main_dummy[23:0] [19] $or$ls180.v:7722$2593_Y + assign $0\main_dummy[23:0] [20] $or$ls180.v:7723$2594_Y + assign $0\main_dummy[23:0] [21] $or$ls180.v:7724$2595_Y + assign $0\main_dummy[23:0] [22] $or$ls180.v:7725$2596_Y + assign $0\main_dummy[23:0] [23] $or$ls180.v:7726$2597_Y + assign $0\builder_converter0_state[0:0] \builder_converter0_next_state + assign $0\builder_converter1_state[0:0] \builder_converter1_next_state + assign $0\builder_converter2_state[0:0] \builder_converter2_next_state + assign $0\main_libresocsim_ram_bus_ack[0:0] 1'0 + assign $0\main_libresocsim_zero_old_trigger[0:0] \main_libresocsim_zero_trigger + assign $0\main_interface0_ram_bus_ack[0:0] 1'0 + assign $0\main_interface1_ram_bus_ack[0:0] 1'0 + assign $0\main_interface2_ram_bus_ack[0:0] 1'0 + assign $0\main_interface3_ram_bus_ack[0:0] 1'0 + assign $0\main_rddata_en[2:0] { \main_rddata_en [1:0] \main_dfi_p0_rddata_en } + assign $0\main_dfi_p0_rddata_valid[0:0] \main_rddata_en [2] + assign $0\main_sdram_postponer_req_o[0:0] 1'0 + assign $0\main_sdram_cmd_payload_a[12:0] 13'0000000000000 + assign $0\main_sdram_cmd_payload_ba[1:0] 2'00 + assign $0\main_sdram_cmd_payload_cas[0:0] 1'0 + assign $0\main_sdram_cmd_payload_ras[0:0] 1'0 + assign $0\main_sdram_cmd_payload_we[0:0] 1'0 + assign $0\main_sdram_sequencer_done1[0:0] 1'0 + assign $0\builder_refresher_state[1:0] \builder_refresher_next_state + assign $0\builder_bankmachine0_state[2:0] \builder_bankmachine0_next_state + assign $0\builder_bankmachine1_state[2:0] \builder_bankmachine1_next_state + assign $0\builder_bankmachine2_state[2:0] \builder_bankmachine2_next_state + assign $0\builder_bankmachine3_state[2:0] \builder_bankmachine3_next_state + assign $0\main_sdram_dfi_p0_cs_n[0:0] 1'0 + assign $0\main_sdram_dfi_p0_bank[1:0] \builder_sync_rhs_array_muxed0 + assign $0\main_sdram_dfi_p0_address[12:0] \builder_sync_rhs_array_muxed1 + assign $0\main_sdram_dfi_p0_cas_n[0:0] $not$ls180.v:8184$2706_Y + assign $0\main_sdram_dfi_p0_ras_n[0:0] $not$ls180.v:8185$2707_Y + assign $0\main_sdram_dfi_p0_we_n[0:0] $not$ls180.v:8186$2708_Y + assign $0\main_sdram_dfi_p0_rddata_en[0:0] \builder_sync_rhs_array_muxed5 + assign $0\main_sdram_dfi_p0_wrdata_en[0:0] \builder_sync_rhs_array_muxed6 + assign $0\builder_multiplexer_state[2:0] \builder_multiplexer_next_state + assign $0\builder_new_master_wdata_ready[0:0] $or$ls180.v:8220$2726_Y + assign $0\builder_new_master_rdata_valid0[0:0] $or$ls180.v:8221$2738_Y + assign $0\builder_new_master_rdata_valid1[0:0] \builder_new_master_rdata_valid0 + assign $0\builder_new_master_rdata_valid2[0:0] \builder_new_master_rdata_valid1 + assign $0\builder_new_master_rdata_valid3[0:0] \builder_new_master_rdata_valid2 + assign $0\builder_converter_state[0:0] \builder_converter_next_state + assign $0\main_uart_phy_sink_ready[0:0] 1'0 + assign $0\main_uart_phy_source_valid[0:0] 1'0 + assign $0\main_uart_phy_rx_r[0:0] \main_uart_phy_rx + assign $0\main_uart_tx_old_trigger[0:0] \main_uart_tx_trigger + assign $0\main_uart_rx_old_trigger[0:0] \main_uart_rx_trigger + assign $0\main_spimaster30_clk_divider[15:0] $add$ls180.v:8379$2784_Y + assign $0\spisdcard_cs_n[0:0] $or$ls180.v:8388$2787_Y + assign $0\builder_spimaster0_state[1:0] \builder_spimaster0_next_state + assign $0\main_spisdcard_clk_divider1[15:0] $add$ls180.v:8414$2789_Y + assign $0\spimaster_cs_n[0:0] $or$ls180.v:8423$2792_Y + assign $0\builder_spimaster1_state[1:0] \builder_spimaster1_next_state + assign $0\main_sdphy_clocker_clk_d[0:0] \main_sdphy_clocker_clk1 + assign $0\main_sdphy_clocker_clk0[0:0] \main_sdphy_clocker_clk1 + assign $0\builder_sdphy_sdphyinit_state[0:0] \builder_sdphy_sdphyinit_next_state + assign $0\builder_sdphy_sdphycmdw_state[1:0] \builder_sdphy_sdphycmdw_next_state + assign $0\builder_sdphy_sdphycmdr_state[2:0] \builder_sdphy_sdphycmdr_next_state + assign $0\builder_sdphy_sdphycrcr_state[0:0] \builder_sdphy_sdphycrcr_next_state + assign $0\builder_sdphy_fsm_state[2:0] \builder_sdphy_fsm_next_state + assign $0\builder_sdphy_sdphydatar_state[2:0] \builder_sdphy_sdphydatar_next_state + assign $0\builder_sdcore_crcupstreaminserter_state[0:0] \builder_sdcore_crcupstreaminserter_next_state + assign $0\builder_sdcore_fsm_state[2:0] \builder_sdcore_fsm_next_state + assign $0\builder_sdblock2memdma_state[1:0] \builder_sdblock2memdma_next_state + assign $0\builder_sdmem2blockdma_fsm_state[0:0] \builder_sdmem2blockdma_fsm_next_state + assign $0\builder_sdmem2blockdma_resetinserter_state[1:0] \builder_sdmem2blockdma_resetinserter_next_state + assign $0\builder_state[1:0] \builder_next_state + assign $0\builder_slave_sel_r[12:0] \builder_slave_sel + assign $0\builder_interface0_bank_bus_dat_r[7:0] 8'00000000 + assign $0\main_libresocsim_reset_re[0:0] \builder_csrbank0_reset0_re + assign $0\main_libresocsim_scratch_re[0:0] \builder_csrbank0_scratch0_re + assign $0\builder_interface1_bank_bus_dat_r[7:0] 8'00000000 + assign $0\main_gpiotristateasic1_oe_re[0:0] \builder_csrbank1_oe0_re + assign $0\main_gpiotristateasic1_out_re[0:0] \builder_csrbank1_out0_re + assign $0\builder_interface2_bank_bus_dat_r[7:0] 8'00000000 + assign $0\main_i2c_re[0:0] \builder_csrbank2_w0_re + assign $0\builder_interface3_bank_bus_dat_r[7:0] 8'00000000 + assign $0\main_pwm0_enable_re[0:0] \builder_csrbank3_enable0_re + assign $0\main_pwm0_width_re[0:0] \builder_csrbank3_width0_re + assign $0\main_pwm0_period_re[0:0] \builder_csrbank3_period0_re + assign $0\builder_interface4_bank_bus_dat_r[7:0] 8'00000000 + assign $0\main_pwm1_enable_re[0:0] \builder_csrbank4_enable0_re + assign $0\main_pwm1_width_re[0:0] \builder_csrbank4_width0_re + assign $0\main_pwm1_period_re[0:0] \builder_csrbank4_period0_re + assign $0\builder_interface5_bank_bus_dat_r[7:0] 8'00000000 + assign $0\main_sdblock2mem_wishbonedmawriter_base_re[0:0] \builder_csrbank5_dma_base0_re + assign $0\main_sdblock2mem_wishbonedmawriter_length_re[0:0] \builder_csrbank5_dma_length0_re + assign $0\main_sdblock2mem_wishbonedmawriter_enable_re[0:0] \builder_csrbank5_dma_enable0_re + assign $0\main_sdblock2mem_wishbonedmawriter_loop_re[0:0] \builder_csrbank5_dma_loop0_re + assign $0\builder_interface6_bank_bus_dat_r[7:0] 8'00000000 + assign $0\main_sdcore_cmd_argument_re[0:0] \builder_csrbank6_cmd_argument0_re + assign $0\main_sdcore_cmd_command_re[0:0] \builder_csrbank6_cmd_command0_re + assign $0\main_sdcore_block_length_re[0:0] \builder_csrbank6_block_length0_re + assign $0\main_sdcore_block_count_re[0:0] \builder_csrbank6_block_count0_re + assign $0\builder_interface7_bank_bus_dat_r[7:0] 8'00000000 + assign $0\main_sdmem2block_dma_base_re[0:0] \builder_csrbank7_dma_base0_re + assign $0\main_sdmem2block_dma_length_re[0:0] \builder_csrbank7_dma_length0_re + assign $0\main_sdmem2block_dma_enable_re[0:0] \builder_csrbank7_dma_enable0_re + assign $0\main_sdmem2block_dma_loop_re[0:0] \builder_csrbank7_dma_loop0_re + assign $0\builder_interface8_bank_bus_dat_r[7:0] 8'00000000 + assign $0\main_sdphy_clocker_re[0:0] \builder_csrbank8_clocker_divider0_re + assign $0\builder_interface9_bank_bus_dat_r[7:0] 8'00000000 + assign $0\main_sdram_re[0:0] \builder_csrbank9_dfii_control0_re + assign $0\main_sdram_command_re[0:0] \builder_csrbank9_dfii_pi0_command0_re + assign $0\main_sdram_address_re[0:0] \builder_csrbank9_dfii_pi0_address0_re + assign $0\main_sdram_baddress_re[0:0] \builder_csrbank9_dfii_pi0_baddress0_re + assign $0\main_sdram_wrdata_re[0:0] \builder_csrbank9_dfii_pi0_wrdata0_re + assign $0\builder_interface10_bank_bus_dat_r[7:0] 8'00000000 + assign $0\main_spimaster12_re[0:0] \builder_csrbank10_control0_re + assign $0\main_spimaster17_re[0:0] \builder_csrbank10_mosi0_re + assign $0\main_spimaster22_re[0:0] \builder_csrbank10_cs0_re + assign $0\main_spimaster24_re[0:0] \builder_csrbank10_loopback0_re + assign $0\builder_interface11_bank_bus_dat_r[7:0] 8'00000000 + assign $0\main_spisdcard_control_re[0:0] \builder_csrbank11_control0_re + assign $0\main_spisdcard_mosi_re[0:0] \builder_csrbank11_mosi0_re + assign $0\main_spisdcard_cs_re[0:0] \builder_csrbank11_cs0_re + assign $0\main_spisdcard_loopback_re[0:0] \builder_csrbank11_loopback0_re + assign $0\main_spimaster1_re[0:0] \builder_csrbank11_clk_divider0_re + assign $0\builder_interface12_bank_bus_dat_r[7:0] 8'00000000 + assign $0\main_libresocsim_load_re[0:0] \builder_csrbank12_load0_re + assign $0\main_libresocsim_reload_re[0:0] \builder_csrbank12_reload0_re + assign $0\main_libresocsim_en_re[0:0] \builder_csrbank12_en0_re + assign $0\main_libresocsim_update_value_re[0:0] \builder_csrbank12_update_value0_re + assign $0\main_libresocsim_eventmanager_re[0:0] \builder_csrbank12_ev_enable0_re + assign $0\builder_interface13_bank_bus_dat_r[7:0] 8'00000000 + assign $0\main_uart_eventmanager_re[0:0] \builder_csrbank13_ev_enable0_re + assign $0\builder_interface14_bank_bus_dat_r[7:0] 8'00000000 + assign $0\main_uart_phy_re[0:0] \builder_csrbank14_tuning_word0_re + assign $0\builder_multiregimpl0_regs0[0:0] \uart_rx + assign $0\builder_multiregimpl0_regs1[0:0] \builder_multiregimpl0_regs0 + assign $0\builder_multiregimpl1_regs0[0:0] \main_gpiotristateasic0_pads_i [0] + assign $0\builder_multiregimpl1_regs1[0:0] \builder_multiregimpl1_regs0 + assign $0\builder_multiregimpl2_regs0[0:0] \main_gpiotristateasic0_pads_i [1] + assign $0\builder_multiregimpl2_regs1[0:0] \builder_multiregimpl2_regs0 + assign $0\builder_multiregimpl3_regs0[0:0] \main_gpiotristateasic0_pads_i [2] + assign $0\builder_multiregimpl3_regs1[0:0] \builder_multiregimpl3_regs0 + assign $0\builder_multiregimpl4_regs0[0:0] \main_gpiotristateasic0_pads_i [3] + assign $0\builder_multiregimpl4_regs1[0:0] \builder_multiregimpl4_regs0 + assign $0\builder_multiregimpl5_regs0[0:0] \main_gpiotristateasic0_pads_i [4] + assign $0\builder_multiregimpl5_regs1[0:0] \builder_multiregimpl5_regs0 + assign $0\builder_multiregimpl6_regs0[0:0] \main_gpiotristateasic0_pads_i [5] + assign $0\builder_multiregimpl6_regs1[0:0] \builder_multiregimpl6_regs0 + assign $0\builder_multiregimpl7_regs0[0:0] \main_gpiotristateasic0_pads_i [6] + assign $0\builder_multiregimpl7_regs1[0:0] \builder_multiregimpl7_regs0 + assign $0\builder_multiregimpl8_regs0[0:0] \main_gpiotristateasic0_pads_i [7] + assign $0\builder_multiregimpl8_regs1[0:0] \builder_multiregimpl8_regs0 + assign $0\builder_multiregimpl9_regs0[0:0] \main_gpiotristateasic1_pads_i [8] + assign $0\builder_multiregimpl9_regs1[0:0] \builder_multiregimpl9_regs0 + assign $0\builder_multiregimpl10_regs0[0:0] \main_gpiotristateasic1_pads_i [9] + assign $0\builder_multiregimpl10_regs1[0:0] \builder_multiregimpl10_regs0 + assign $0\builder_multiregimpl11_regs0[0:0] \main_gpiotristateasic1_pads_i [10] + assign $0\builder_multiregimpl11_regs1[0:0] \builder_multiregimpl11_regs0 + assign $0\builder_multiregimpl12_regs0[0:0] \main_gpiotristateasic1_pads_i [11] + assign $0\builder_multiregimpl12_regs1[0:0] \builder_multiregimpl12_regs0 + assign $0\builder_multiregimpl13_regs0[0:0] \main_gpiotristateasic1_pads_i [12] + assign $0\builder_multiregimpl13_regs1[0:0] \builder_multiregimpl13_regs0 + assign $0\builder_multiregimpl14_regs0[0:0] \main_gpiotristateasic1_pads_i [13] + assign $0\builder_multiregimpl14_regs1[0:0] \builder_multiregimpl14_regs0 + assign $0\builder_multiregimpl15_regs0[0:0] \main_gpiotristateasic1_pads_i [14] + assign $0\builder_multiregimpl15_regs1[0:0] \builder_multiregimpl15_regs0 + assign $0\builder_multiregimpl16_regs0[0:0] \main_gpiotristateasic1_pads_i [15] + assign $0\builder_multiregimpl16_regs1[0:0] \builder_multiregimpl16_regs0 + attribute \src "ls180.v:7727.2-7729.5" + switch $or$ls180.v:7727$2598_Y + attribute \src "ls180.v:7727.6-7727.69" + case 1'1 + assign $0\main_converter0_dat_r[63:0] \main_interface0_converted_interface_dat_r + case + end + attribute \src "ls180.v:7731.2-7733.5" + switch \main_converter0_counter_converter0_next_value_ce + attribute \src "ls180.v:7731.6-7731.54" + case 1'1 + assign $0\main_converter0_counter[0:0] \main_converter0_counter_converter0_next_value + case + end + attribute \src "ls180.v:7734.2-7737.5" + switch \main_converter0_reset + attribute \src "ls180.v:7734.6-7734.27" + case 1'1 + assign $0\main_converter0_counter[0:0] 1'0 + assign $0\builder_converter0_state[0:0] 1'0 + case + end + attribute \src "ls180.v:7738.2-7740.5" + switch $or$ls180.v:7738$2599_Y + attribute \src "ls180.v:7738.6-7738.69" + case 1'1 + assign $0\main_converter1_dat_r[63:0] \main_interface1_converted_interface_dat_r + case + end + attribute \src "ls180.v:7742.2-7744.5" + switch \main_converter1_counter_converter1_next_value_ce + attribute \src "ls180.v:7742.6-7742.54" + case 1'1 + assign $0\main_converter1_counter[0:0] \main_converter1_counter_converter1_next_value + case + end + attribute \src "ls180.v:7745.2-7748.5" + switch \main_converter1_reset + attribute \src "ls180.v:7745.6-7745.27" + case 1'1 + assign $0\main_converter1_counter[0:0] 1'0 + assign $0\builder_converter1_state[0:0] 1'0 + case + end + attribute \src "ls180.v:7749.2-7751.5" + switch $or$ls180.v:7749$2600_Y + attribute \src "ls180.v:7749.6-7749.51" + case 1'1 + assign $0\main_socbushandler_dat_r[63:0] \main_socbushandler_converted_interface_dat_r + case + end + attribute \src "ls180.v:7753.2-7755.5" + switch \main_socbushandler_counter_converter2_next_value_ce + attribute \src "ls180.v:7753.6-7753.57" + case 1'1 + assign $0\main_socbushandler_counter[0:0] \main_socbushandler_counter_converter2_next_value + case + end + attribute \src "ls180.v:7756.2-7759.5" + switch \main_socbushandler_reset + attribute \src "ls180.v:7756.6-7756.30" + case 1'1 + assign $0\main_socbushandler_counter[0:0] 1'0 + assign $0\builder_converter2_state[0:0] 1'0 + case + end + attribute \src "ls180.v:7760.2-7764.5" + switch $ne$ls180.v:7760$2601_Y + attribute \src "ls180.v:7760.6-7760.53" + case 1'1 + attribute \src "ls180.v:7761.3-7763.6" + switch \main_libresocsim_bus_error + attribute \src "ls180.v:7761.7-7761.33" + case 1'1 + assign $0\main_libresocsim_bus_errors[31:0] $add$ls180.v:7762$2602_Y + case + end + case + end + attribute \src "ls180.v:7766.2-7768.5" + switch $and$ls180.v:7766$2605_Y + attribute \src "ls180.v:7766.6-7766.103" + case 1'1 + assign $0\main_libresocsim_ram_bus_ack[0:0] 1'1 + case + end + attribute \src "ls180.v:7769.2-7777.5" + switch \main_libresocsim_en_storage + attribute \src "ls180.v:7769.6-7769.33" + case 1'1 + attribute \src "ls180.v:7770.3-7774.6" + switch $eq$ls180.v:7770$2606_Y + attribute \src "ls180.v:7770.7-7770.39" + case 1'1 + assign $0\main_libresocsim_value[31:0] \main_libresocsim_reload_storage + attribute \src "ls180.v:7772.7-7772.11" + case + assign $0\main_libresocsim_value[31:0] $sub$ls180.v:7773$2607_Y + end + attribute \src "ls180.v:7775.6-7775.10" + case + assign $0\main_libresocsim_value[31:0] \main_libresocsim_load_storage + end + attribute \src "ls180.v:7778.2-7780.5" + switch \main_libresocsim_update_value_re + attribute \src "ls180.v:7778.6-7778.38" + case 1'1 + assign $0\main_libresocsim_value_status[31:0] \main_libresocsim_value + case + end + attribute \src "ls180.v:7781.2-7783.5" + switch \main_libresocsim_zero_clear + attribute \src "ls180.v:7781.6-7781.33" + case 1'1 + assign $0\main_libresocsim_zero_pending[0:0] 1'0 + case + end + attribute \src "ls180.v:7785.2-7787.5" + switch $and$ls180.v:7785$2609_Y + attribute \src "ls180.v:7785.6-7785.76" + case 1'1 + assign $0\main_libresocsim_zero_pending[0:0] 1'1 + case + end + attribute \src "ls180.v:7789.2-7791.5" + switch $and$ls180.v:7789$2612_Y + attribute \src "ls180.v:7789.6-7789.100" + case 1'1 + assign $0\main_interface0_ram_bus_ack[0:0] 1'1 + case + end + attribute \src "ls180.v:7793.2-7795.5" + switch $and$ls180.v:7793$2615_Y + attribute \src "ls180.v:7793.6-7793.100" + case 1'1 + assign $0\main_interface1_ram_bus_ack[0:0] 1'1 + case + end + attribute \src "ls180.v:7797.2-7799.5" + switch $and$ls180.v:7797$2618_Y + attribute \src "ls180.v:7797.6-7797.100" + case 1'1 + assign $0\main_interface2_ram_bus_ack[0:0] 1'1 + case + end + attribute \src "ls180.v:7801.2-7803.5" + switch $and$ls180.v:7801$2621_Y + attribute \src "ls180.v:7801.6-7801.100" + case 1'1 + assign $0\main_interface3_ram_bus_ack[0:0] 1'1 + case + end + attribute \src "ls180.v:7806.2-7808.5" + switch \main_sdram_inti_p0_rddata_valid + attribute \src "ls180.v:7806.6-7806.37" + case 1'1 + assign $0\main_sdram_status[15:0] \main_sdram_inti_p0_rddata + case + end + attribute \src "ls180.v:7809.2-7813.5" + switch $and$ls180.v:7809$2623_Y + attribute \src "ls180.v:7809.6-7809.57" + case 1'1 + assign $0\main_sdram_timer_count1[9:0] $sub$ls180.v:7810$2624_Y + attribute \src "ls180.v:7811.6-7811.10" + case + assign $0\main_sdram_timer_count1[9:0] 10'1100001101 + end + attribute \src "ls180.v:7815.2-7821.5" + switch \main_sdram_postponer_req_i + attribute \src "ls180.v:7815.6-7815.32" + case 1'1 + assign $0\main_sdram_postponer_count[0:0] $sub$ls180.v:7816$2625_Y + attribute \src "ls180.v:7817.3-7820.6" + switch $eq$ls180.v:7817$2626_Y + attribute \src "ls180.v:7817.7-7817.43" + case 1'1 + assign $0\main_sdram_postponer_count[0:0] 1'0 + assign $0\main_sdram_postponer_req_o[0:0] 1'1 + case + end + case + end + attribute \src "ls180.v:7822.2-7830.5" + switch \main_sdram_sequencer_start0 + attribute \src "ls180.v:7822.6-7822.33" + case 1'1 + assign $0\main_sdram_sequencer_count[0:0] 1'0 + attribute \src "ls180.v:7824.6-7824.10" + case + attribute \src "ls180.v:7825.3-7829.6" + switch \main_sdram_sequencer_done1 + attribute \src "ls180.v:7825.7-7825.33" + case 1'1 + attribute \src "ls180.v:7826.4-7828.7" + switch $ne$ls180.v:7826$2627_Y + attribute \src "ls180.v:7826.8-7826.44" + case 1'1 + assign $0\main_sdram_sequencer_count[0:0] $sub$ls180.v:7827$2628_Y + case + end + case + end + end + attribute \src "ls180.v:7837.2-7843.5" + switch $and$ls180.v:7837$2630_Y + attribute \src "ls180.v:7837.6-7837.76" + case 1'1 + assign $0\main_sdram_cmd_payload_a[12:0] 13'0010000000000 + assign $0\main_sdram_cmd_payload_ba[1:0] 2'00 + assign $0\main_sdram_cmd_payload_cas[0:0] 1'0 + assign $0\main_sdram_cmd_payload_ras[0:0] 1'1 + assign $0\main_sdram_cmd_payload_we[0:0] 1'1 + case + end + attribute \src "ls180.v:7844.2-7850.5" + switch $eq$ls180.v:7844$2631_Y + attribute \src "ls180.v:7844.6-7844.44" + case 1'1 + assign $0\main_sdram_cmd_payload_a[12:0] 13'0000000000000 + assign $0\main_sdram_cmd_payload_ba[1:0] 2'00 + assign $0\main_sdram_cmd_payload_cas[0:0] 1'1 + assign $0\main_sdram_cmd_payload_ras[0:0] 1'1 + assign $0\main_sdram_cmd_payload_we[0:0] 1'0 + case + end + attribute \src "ls180.v:7851.2-7858.5" + switch $eq$ls180.v:7851$2632_Y + attribute \src "ls180.v:7851.6-7851.44" + case 1'1 + assign $0\main_sdram_cmd_payload_a[12:0] 13'0000000000000 + assign $0\main_sdram_cmd_payload_ba[1:0] 2'00 + assign $0\main_sdram_cmd_payload_cas[0:0] 1'0 + assign $0\main_sdram_cmd_payload_ras[0:0] 1'0 + assign $0\main_sdram_cmd_payload_we[0:0] 1'0 + assign $0\main_sdram_sequencer_done1[0:0] 1'1 + case + end + attribute \src "ls180.v:7859.2-7869.5" + switch $eq$ls180.v:7859$2633_Y + attribute \src "ls180.v:7859.6-7859.44" + case 1'1 + assign $0\main_sdram_sequencer_counter[3:0] 4'0000 + attribute \src "ls180.v:7861.6-7861.10" + case + attribute \src "ls180.v:7862.3-7868.6" + switch $ne$ls180.v:7862$2634_Y + attribute \src "ls180.v:7862.7-7862.45" + case 1'1 + assign $0\main_sdram_sequencer_counter[3:0] $add$ls180.v:7863$2635_Y + attribute \src "ls180.v:7864.7-7864.11" + case + attribute \src "ls180.v:7865.4-7867.7" + switch \main_sdram_sequencer_start1 + attribute \src "ls180.v:7865.8-7865.35" + case 1'1 + assign $0\main_sdram_sequencer_counter[3:0] 4'0001 + case + end + end + end + attribute \src "ls180.v:7871.2-7878.5" + switch \main_sdram_bankmachine0_row_close + attribute \src "ls180.v:7871.6-7871.39" + case 1'1 + assign $0\main_sdram_bankmachine0_row_opened[0:0] 1'0 + attribute \src "ls180.v:7873.6-7873.10" + case + attribute \src "ls180.v:7874.3-7877.6" + switch \main_sdram_bankmachine0_row_open + attribute \src "ls180.v:7874.7-7874.39" + case 1'1 + assign $0\main_sdram_bankmachine0_row_opened[0:0] 1'1 + assign $0\main_sdram_bankmachine0_row[12:0] \main_sdram_bankmachine0_cmd_buffer_source_payload_addr [21:9] + case + end + end + attribute \src "ls180.v:7879.2-7881.5" + switch $and$ls180.v:7879$2638_Y + attribute \src "ls180.v:7879.6-7879.191" + case 1'1 + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7880$2639_Y + case + end + attribute \src "ls180.v:7882.2-7884.5" + switch \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read + attribute \src "ls180.v:7882.6-7882.58" + case 1'1 + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7883$2640_Y + case + end + attribute \src "ls180.v:7885.2-7893.5" + switch $and$ls180.v:7885$2643_Y + attribute \src "ls180.v:7885.6-7885.191" + case 1'1 + attribute \src "ls180.v:7886.3-7888.6" + switch $not$ls180.v:7886$2644_Y + attribute \src "ls180.v:7886.7-7886.62" + case 1'1 + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7887$2645_Y + case + end + attribute \src "ls180.v:7889.6-7889.10" + case + attribute \src "ls180.v:7890.3-7892.6" + switch \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read + attribute \src "ls180.v:7890.7-7890.59" + case 1'1 + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7891$2646_Y + case + end + end + attribute \src "ls180.v:7894.2-7900.5" + switch $or$ls180.v:7894$2648_Y + attribute \src "ls180.v:7894.6-7894.108" + case 1'1 + assign $0\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine0_cmd_buffer_sink_valid + assign $0\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] \main_sdram_bankmachine0_cmd_buffer_sink_first + assign $0\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] \main_sdram_bankmachine0_cmd_buffer_sink_last + assign $0\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] \main_sdram_bankmachine0_cmd_buffer_sink_payload_we + assign $0\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine0_cmd_buffer_sink_payload_addr + case + end + attribute \src "ls180.v:7901.2-7915.5" + switch \main_sdram_bankmachine0_twtpcon_valid + attribute \src "ls180.v:7901.6-7901.43" + case 1'1 + assign $0\main_sdram_bankmachine0_twtpcon_count[2:0] 3'100 + attribute \src "ls180.v:7903.3-7907.6" + switch 1'0 + attribute \src "ls180.v:7905.7-7905.11" + case + assign $0\main_sdram_bankmachine0_twtpcon_ready[0:0] 1'0 + end + attribute \src "ls180.v:7908.6-7908.10" + case + attribute \src "ls180.v:7909.3-7914.6" + switch $not$ls180.v:7909$2649_Y + attribute \src "ls180.v:7909.7-7909.47" + case 1'1 + assign $0\main_sdram_bankmachine0_twtpcon_count[2:0] $sub$ls180.v:7910$2650_Y + attribute \src "ls180.v:7911.4-7913.7" + switch $eq$ls180.v:7911$2651_Y + attribute \src "ls180.v:7911.8-7911.55" + case 1'1 + assign $0\main_sdram_bankmachine0_twtpcon_ready[0:0] 1'1 + case + end + case + end + end + attribute \src "ls180.v:7917.2-7924.5" + switch \main_sdram_bankmachine1_row_close + attribute \src "ls180.v:7917.6-7917.39" + case 1'1 + assign $0\main_sdram_bankmachine1_row_opened[0:0] 1'0 + attribute \src "ls180.v:7919.6-7919.10" + case + attribute \src "ls180.v:7920.3-7923.6" + switch \main_sdram_bankmachine1_row_open + attribute \src "ls180.v:7920.7-7920.39" + case 1'1 + assign $0\main_sdram_bankmachine1_row_opened[0:0] 1'1 + assign $0\main_sdram_bankmachine1_row[12:0] \main_sdram_bankmachine1_cmd_buffer_source_payload_addr [21:9] + case + end + end + attribute \src "ls180.v:7925.2-7927.5" + switch $and$ls180.v:7925$2654_Y + attribute \src "ls180.v:7925.6-7925.191" + case 1'1 + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7926$2655_Y + case + end + attribute \src "ls180.v:7928.2-7930.5" + switch \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read + attribute \src "ls180.v:7928.6-7928.58" + case 1'1 + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7929$2656_Y + case + end + attribute \src "ls180.v:7931.2-7939.5" + switch $and$ls180.v:7931$2659_Y + attribute \src "ls180.v:7931.6-7931.191" + case 1'1 + attribute \src "ls180.v:7932.3-7934.6" + switch $not$ls180.v:7932$2660_Y + attribute \src "ls180.v:7932.7-7932.62" + case 1'1 + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7933$2661_Y + case + end + attribute \src "ls180.v:7935.6-7935.10" + case + attribute \src "ls180.v:7936.3-7938.6" + switch \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read + attribute \src "ls180.v:7936.7-7936.59" + case 1'1 + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7937$2662_Y + case + end + end + attribute \src "ls180.v:7940.2-7946.5" + switch $or$ls180.v:7940$2664_Y + attribute \src "ls180.v:7940.6-7940.108" + case 1'1 + assign $0\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine1_cmd_buffer_sink_valid + assign $0\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] \main_sdram_bankmachine1_cmd_buffer_sink_first + assign $0\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] \main_sdram_bankmachine1_cmd_buffer_sink_last + assign $0\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] \main_sdram_bankmachine1_cmd_buffer_sink_payload_we + assign $0\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine1_cmd_buffer_sink_payload_addr + case + end + attribute \src "ls180.v:7947.2-7961.5" + switch \main_sdram_bankmachine1_twtpcon_valid + attribute \src "ls180.v:7947.6-7947.43" + case 1'1 + assign $0\main_sdram_bankmachine1_twtpcon_count[2:0] 3'100 + attribute \src "ls180.v:7949.3-7953.6" + switch 1'0 + attribute \src "ls180.v:7951.7-7951.11" + case + assign $0\main_sdram_bankmachine1_twtpcon_ready[0:0] 1'0 + end + attribute \src "ls180.v:7954.6-7954.10" + case + attribute \src "ls180.v:7955.3-7960.6" + switch $not$ls180.v:7955$2665_Y + attribute \src "ls180.v:7955.7-7955.47" + case 1'1 + assign $0\main_sdram_bankmachine1_twtpcon_count[2:0] $sub$ls180.v:7956$2666_Y + attribute \src "ls180.v:7957.4-7959.7" + switch $eq$ls180.v:7957$2667_Y + attribute \src "ls180.v:7957.8-7957.55" + case 1'1 + assign $0\main_sdram_bankmachine1_twtpcon_ready[0:0] 1'1 + case + end + case + end + end + attribute \src "ls180.v:7963.2-7970.5" + switch \main_sdram_bankmachine2_row_close + attribute \src "ls180.v:7963.6-7963.39" + case 1'1 + assign $0\main_sdram_bankmachine2_row_opened[0:0] 1'0 + attribute \src "ls180.v:7965.6-7965.10" + case + attribute \src "ls180.v:7966.3-7969.6" + switch \main_sdram_bankmachine2_row_open + attribute \src "ls180.v:7966.7-7966.39" + case 1'1 + assign $0\main_sdram_bankmachine2_row_opened[0:0] 1'1 + assign $0\main_sdram_bankmachine2_row[12:0] \main_sdram_bankmachine2_cmd_buffer_source_payload_addr [21:9] + case + end + end + attribute \src "ls180.v:7971.2-7973.5" + switch $and$ls180.v:7971$2670_Y + attribute \src "ls180.v:7971.6-7971.191" + case 1'1 + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7972$2671_Y + case + end + attribute \src "ls180.v:7974.2-7976.5" + switch \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read + attribute \src "ls180.v:7974.6-7974.58" + case 1'1 + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7975$2672_Y + case + end + attribute \src "ls180.v:7977.2-7985.5" + switch $and$ls180.v:7977$2675_Y + attribute \src "ls180.v:7977.6-7977.191" + case 1'1 + attribute \src "ls180.v:7978.3-7980.6" + switch $not$ls180.v:7978$2676_Y + attribute \src "ls180.v:7978.7-7978.62" + case 1'1 + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7979$2677_Y + case + end + attribute \src "ls180.v:7981.6-7981.10" + case + attribute \src "ls180.v:7982.3-7984.6" + switch \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read + attribute \src "ls180.v:7982.7-7982.59" + case 1'1 + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7983$2678_Y + case + end + end + attribute \src "ls180.v:7986.2-7992.5" + switch $or$ls180.v:7986$2680_Y + attribute \src "ls180.v:7986.6-7986.108" + case 1'1 + assign $0\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine2_cmd_buffer_sink_valid + assign $0\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] \main_sdram_bankmachine2_cmd_buffer_sink_first + assign $0\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] \main_sdram_bankmachine2_cmd_buffer_sink_last + assign $0\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] \main_sdram_bankmachine2_cmd_buffer_sink_payload_we + assign $0\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine2_cmd_buffer_sink_payload_addr + case + end + attribute \src "ls180.v:7993.2-8007.5" + switch \main_sdram_bankmachine2_twtpcon_valid + attribute \src "ls180.v:7993.6-7993.43" + case 1'1 + assign $0\main_sdram_bankmachine2_twtpcon_count[2:0] 3'100 + attribute \src "ls180.v:7995.3-7999.6" + switch 1'0 + attribute \src "ls180.v:7997.7-7997.11" + case + assign $0\main_sdram_bankmachine2_twtpcon_ready[0:0] 1'0 + end + attribute \src "ls180.v:8000.6-8000.10" + case + attribute \src "ls180.v:8001.3-8006.6" + switch $not$ls180.v:8001$2681_Y + attribute \src "ls180.v:8001.7-8001.47" + case 1'1 + assign $0\main_sdram_bankmachine2_twtpcon_count[2:0] $sub$ls180.v:8002$2682_Y + attribute \src "ls180.v:8003.4-8005.7" + switch $eq$ls180.v:8003$2683_Y + attribute \src "ls180.v:8003.8-8003.55" + case 1'1 + assign $0\main_sdram_bankmachine2_twtpcon_ready[0:0] 1'1 + case + end + case + end + end + attribute \src "ls180.v:8009.2-8016.5" + switch \main_sdram_bankmachine3_row_close + attribute \src "ls180.v:8009.6-8009.39" + case 1'1 + assign $0\main_sdram_bankmachine3_row_opened[0:0] 1'0 + attribute \src "ls180.v:8011.6-8011.10" + case + attribute \src "ls180.v:8012.3-8015.6" + switch \main_sdram_bankmachine3_row_open + attribute \src "ls180.v:8012.7-8012.39" + case 1'1 + assign $0\main_sdram_bankmachine3_row_opened[0:0] 1'1 + assign $0\main_sdram_bankmachine3_row[12:0] \main_sdram_bankmachine3_cmd_buffer_source_payload_addr [21:9] + case + end + end + attribute \src "ls180.v:8017.2-8019.5" + switch $and$ls180.v:8017$2686_Y + attribute \src "ls180.v:8017.6-8017.191" + case 1'1 + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:8018$2687_Y + case + end + attribute \src "ls180.v:8020.2-8022.5" + switch \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read + attribute \src "ls180.v:8020.6-8020.58" + case 1'1 + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:8021$2688_Y + case + end + attribute \src "ls180.v:8023.2-8031.5" + switch $and$ls180.v:8023$2691_Y + attribute \src "ls180.v:8023.6-8023.191" + case 1'1 + attribute \src "ls180.v:8024.3-8026.6" + switch $not$ls180.v:8024$2692_Y + attribute \src "ls180.v:8024.7-8024.62" + case 1'1 + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] $add$ls180.v:8025$2693_Y + case + end + attribute \src "ls180.v:8027.6-8027.10" + case + attribute \src "ls180.v:8028.3-8030.6" + switch \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read + attribute \src "ls180.v:8028.7-8028.59" + case 1'1 + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:8029$2694_Y + case + end + end + attribute \src "ls180.v:8032.2-8038.5" + switch $or$ls180.v:8032$2696_Y + attribute \src "ls180.v:8032.6-8032.108" + case 1'1 + assign $0\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine3_cmd_buffer_sink_valid + assign $0\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] \main_sdram_bankmachine3_cmd_buffer_sink_first + assign $0\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] \main_sdram_bankmachine3_cmd_buffer_sink_last + assign $0\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] \main_sdram_bankmachine3_cmd_buffer_sink_payload_we + assign $0\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine3_cmd_buffer_sink_payload_addr + case + end + attribute \src "ls180.v:8039.2-8053.5" + switch \main_sdram_bankmachine3_twtpcon_valid + attribute \src "ls180.v:8039.6-8039.43" + case 1'1 + assign $0\main_sdram_bankmachine3_twtpcon_count[2:0] 3'100 + attribute \src "ls180.v:8041.3-8045.6" + switch 1'0 + attribute \src "ls180.v:8043.7-8043.11" + case + assign $0\main_sdram_bankmachine3_twtpcon_ready[0:0] 1'0 + end + attribute \src "ls180.v:8046.6-8046.10" + case + attribute \src "ls180.v:8047.3-8052.6" + switch $not$ls180.v:8047$2697_Y + attribute \src "ls180.v:8047.7-8047.47" + case 1'1 + assign $0\main_sdram_bankmachine3_twtpcon_count[2:0] $sub$ls180.v:8048$2698_Y + attribute \src "ls180.v:8049.4-8051.7" + switch $eq$ls180.v:8049$2699_Y + attribute \src "ls180.v:8049.8-8049.55" + case 1'1 + assign $0\main_sdram_bankmachine3_twtpcon_ready[0:0] 1'1 + case + end + case + end + end + attribute \src "ls180.v:8055.2-8061.5" + switch $not$ls180.v:8055$2700_Y + attribute \src "ls180.v:8055.6-8055.23" + case 1'1 + assign $0\main_sdram_time0[4:0] 5'11111 + attribute \src "ls180.v:8057.6-8057.10" + case + attribute \src "ls180.v:8058.3-8060.6" + switch $not$ls180.v:8058$2701_Y + attribute \src "ls180.v:8058.7-8058.30" + case 1'1 + assign $0\main_sdram_time0[4:0] $sub$ls180.v:8059$2702_Y + case + end + end + attribute \src "ls180.v:8062.2-8068.5" + switch $not$ls180.v:8062$2703_Y + attribute \src "ls180.v:8062.6-8062.23" + case 1'1 + assign $0\main_sdram_time1[3:0] 4'1111 + attribute \src "ls180.v:8064.6-8064.10" + case + attribute \src "ls180.v:8065.3-8067.6" + switch $not$ls180.v:8065$2704_Y + attribute \src "ls180.v:8065.7-8065.30" + case 1'1 + assign $0\main_sdram_time1[3:0] $sub$ls180.v:8066$2705_Y + case + end + end + attribute \src "ls180.v:8069.2-8124.5" + switch \main_sdram_choose_cmd_ce + attribute \src "ls180.v:8069.6-8069.30" + case 1'1 + attribute \src "ls180.v:8070.3-8123.10" + switch \main_sdram_choose_cmd_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + attribute \src "ls180.v:8072.5-8082.8" + switch \main_sdram_choose_cmd_request [1] + attribute \src "ls180.v:8072.9-8072.41" + case 1'1 + assign $0\main_sdram_choose_cmd_grant[1:0] 2'01 + attribute \src "ls180.v:8074.9-8074.13" + case + attribute \src "ls180.v:8075.6-8081.9" + switch \main_sdram_choose_cmd_request [2] + attribute \src "ls180.v:8075.10-8075.42" + case 1'1 + assign $0\main_sdram_choose_cmd_grant[1:0] 2'10 + attribute \src "ls180.v:8077.10-8077.14" + case + attribute \src "ls180.v:8078.7-8080.10" + switch \main_sdram_choose_cmd_request [3] + attribute \src "ls180.v:8078.11-8078.43" + case 1'1 + assign $0\main_sdram_choose_cmd_grant[1:0] 2'11 + case + end + end + end + attribute \src "ls180.v:0.0-0.0" + case 2'01 + attribute \src "ls180.v:8085.5-8095.8" + switch \main_sdram_choose_cmd_request [2] + attribute \src "ls180.v:8085.9-8085.41" + case 1'1 + assign $0\main_sdram_choose_cmd_grant[1:0] 2'10 + attribute \src "ls180.v:8087.9-8087.13" + case + attribute \src "ls180.v:8088.6-8094.9" + switch \main_sdram_choose_cmd_request [3] + attribute \src "ls180.v:8088.10-8088.42" + case 1'1 + assign $0\main_sdram_choose_cmd_grant[1:0] 2'11 + attribute \src "ls180.v:8090.10-8090.14" + case + attribute \src "ls180.v:8091.7-8093.10" + switch \main_sdram_choose_cmd_request [0] + attribute \src "ls180.v:8091.11-8091.43" + case 1'1 + assign $0\main_sdram_choose_cmd_grant[1:0] 2'00 + case + end + end + end + attribute \src "ls180.v:0.0-0.0" + case 2'10 + attribute \src "ls180.v:8098.5-8108.8" + switch \main_sdram_choose_cmd_request [3] + attribute \src "ls180.v:8098.9-8098.41" + case 1'1 + assign $0\main_sdram_choose_cmd_grant[1:0] 2'11 + attribute \src "ls180.v:8100.9-8100.13" + case + attribute \src "ls180.v:8101.6-8107.9" + switch \main_sdram_choose_cmd_request [0] + attribute \src "ls180.v:8101.10-8101.42" + case 1'1 + assign $0\main_sdram_choose_cmd_grant[1:0] 2'00 + attribute \src "ls180.v:8103.10-8103.14" + case + attribute \src "ls180.v:8104.7-8106.10" + switch \main_sdram_choose_cmd_request [1] + attribute \src "ls180.v:8104.11-8104.43" + case 1'1 + assign $0\main_sdram_choose_cmd_grant[1:0] 2'01 + case + end + end + end + attribute \src "ls180.v:0.0-0.0" + case 2'11 + attribute \src "ls180.v:8111.5-8121.8" + switch \main_sdram_choose_cmd_request [0] + attribute \src "ls180.v:8111.9-8111.41" + case 1'1 + assign $0\main_sdram_choose_cmd_grant[1:0] 2'00 + attribute \src "ls180.v:8113.9-8113.13" + case + attribute \src "ls180.v:8114.6-8120.9" + switch \main_sdram_choose_cmd_request [1] + attribute \src "ls180.v:8114.10-8114.42" + case 1'1 + assign $0\main_sdram_choose_cmd_grant[1:0] 2'01 + attribute \src "ls180.v:8116.10-8116.14" + case + attribute \src "ls180.v:8117.7-8119.10" + switch \main_sdram_choose_cmd_request [2] + attribute \src "ls180.v:8117.11-8117.43" + case 1'1 + assign $0\main_sdram_choose_cmd_grant[1:0] 2'10 + case + end + end + end + case + end + case + end + attribute \src "ls180.v:8125.2-8180.5" + switch \main_sdram_choose_req_ce + attribute \src "ls180.v:8125.6-8125.30" + case 1'1 + attribute \src "ls180.v:8126.3-8179.10" + switch \main_sdram_choose_req_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + attribute \src "ls180.v:8128.5-8138.8" + switch \main_sdram_choose_req_request [1] + attribute \src "ls180.v:8128.9-8128.41" + case 1'1 + assign $0\main_sdram_choose_req_grant[1:0] 2'01 + attribute \src "ls180.v:8130.9-8130.13" + case + attribute \src "ls180.v:8131.6-8137.9" + switch \main_sdram_choose_req_request [2] + attribute \src "ls180.v:8131.10-8131.42" + case 1'1 + assign $0\main_sdram_choose_req_grant[1:0] 2'10 + attribute \src "ls180.v:8133.10-8133.14" + case + attribute \src "ls180.v:8134.7-8136.10" + switch \main_sdram_choose_req_request [3] + attribute \src "ls180.v:8134.11-8134.43" + case 1'1 + assign $0\main_sdram_choose_req_grant[1:0] 2'11 + case + end + end + end + attribute \src "ls180.v:0.0-0.0" + case 2'01 + attribute \src "ls180.v:8141.5-8151.8" + switch \main_sdram_choose_req_request [2] + attribute \src "ls180.v:8141.9-8141.41" + case 1'1 + assign $0\main_sdram_choose_req_grant[1:0] 2'10 + attribute \src "ls180.v:8143.9-8143.13" + case + attribute \src "ls180.v:8144.6-8150.9" + switch \main_sdram_choose_req_request [3] + attribute \src "ls180.v:8144.10-8144.42" + case 1'1 + assign $0\main_sdram_choose_req_grant[1:0] 2'11 + attribute \src "ls180.v:8146.10-8146.14" + case + attribute \src "ls180.v:8147.7-8149.10" + switch \main_sdram_choose_req_request [0] + attribute \src "ls180.v:8147.11-8147.43" + case 1'1 + assign $0\main_sdram_choose_req_grant[1:0] 2'00 + case + end + end + end + attribute \src "ls180.v:0.0-0.0" + case 2'10 + attribute \src "ls180.v:8154.5-8164.8" + switch \main_sdram_choose_req_request [3] + attribute \src "ls180.v:8154.9-8154.41" + case 1'1 + assign $0\main_sdram_choose_req_grant[1:0] 2'11 + attribute \src "ls180.v:8156.9-8156.13" + case + attribute \src "ls180.v:8157.6-8163.9" + switch \main_sdram_choose_req_request [0] + attribute \src "ls180.v:8157.10-8157.42" + case 1'1 + assign $0\main_sdram_choose_req_grant[1:0] 2'00 + attribute \src "ls180.v:8159.10-8159.14" + case + attribute \src "ls180.v:8160.7-8162.10" + switch \main_sdram_choose_req_request [1] + attribute \src "ls180.v:8160.11-8160.43" + case 1'1 + assign $0\main_sdram_choose_req_grant[1:0] 2'01 + case + end + end + end + attribute \src "ls180.v:0.0-0.0" + case 2'11 + attribute \src "ls180.v:8167.5-8177.8" + switch \main_sdram_choose_req_request [0] + attribute \src "ls180.v:8167.9-8167.41" + case 1'1 + assign $0\main_sdram_choose_req_grant[1:0] 2'00 + attribute \src "ls180.v:8169.9-8169.13" + case + attribute \src "ls180.v:8170.6-8176.9" + switch \main_sdram_choose_req_request [1] + attribute \src "ls180.v:8170.10-8170.42" + case 1'1 + assign $0\main_sdram_choose_req_grant[1:0] 2'01 + attribute \src "ls180.v:8172.10-8172.14" + case + attribute \src "ls180.v:8173.7-8175.10" + switch \main_sdram_choose_req_request [2] + attribute \src "ls180.v:8173.11-8173.43" + case 1'1 + assign $0\main_sdram_choose_req_grant[1:0] 2'10 + case + end + end + end + case + end + case + end + attribute \src "ls180.v:8189.2-8203.5" + switch \main_sdram_tccdcon_valid + attribute \src "ls180.v:8189.6-8189.30" + case 1'1 + assign $0\main_sdram_tccdcon_count[0:0] 1'0 + attribute \src "ls180.v:8191.3-8195.6" + switch 1'1 + attribute \src "ls180.v:8191.7-8191.11" + case 1'1 + assign $0\main_sdram_tccdcon_ready[0:0] 1'1 + case + end + attribute \src "ls180.v:8196.6-8196.10" + case + attribute \src "ls180.v:8197.3-8202.6" + switch $not$ls180.v:8197$2709_Y + attribute \src "ls180.v:8197.7-8197.34" + case 1'1 + assign $0\main_sdram_tccdcon_count[0:0] $sub$ls180.v:8198$2710_Y + attribute \src "ls180.v:8199.4-8201.7" + switch $eq$ls180.v:8199$2711_Y + attribute \src "ls180.v:8199.8-8199.42" + case 1'1 + assign $0\main_sdram_tccdcon_ready[0:0] 1'1 + case + end + case + end + end + attribute \src "ls180.v:8204.2-8218.5" + switch \main_sdram_twtrcon_valid + attribute \src "ls180.v:8204.6-8204.30" + case 1'1 + assign $0\main_sdram_twtrcon_count[2:0] 3'100 + attribute \src "ls180.v:8206.3-8210.6" + switch 1'0 + attribute \src "ls180.v:8208.7-8208.11" + case + assign $0\main_sdram_twtrcon_ready[0:0] 1'0 + end + attribute \src "ls180.v:8211.6-8211.10" + case + attribute \src "ls180.v:8212.3-8217.6" + switch $not$ls180.v:8212$2712_Y + attribute \src "ls180.v:8212.7-8212.34" + case 1'1 + assign $0\main_sdram_twtrcon_count[2:0] $sub$ls180.v:8213$2713_Y + attribute \src "ls180.v:8214.4-8216.7" + switch $eq$ls180.v:8214$2714_Y + attribute \src "ls180.v:8214.8-8214.42" + case 1'1 + assign $0\main_sdram_twtrcon_ready[0:0] 1'1 + case + end + case + end + end + attribute \src "ls180.v:8225.2-8227.5" + switch $or$ls180.v:8225$2739_Y + attribute \src "ls180.v:8225.6-8225.50" + case 1'1 + assign $0\main_converter_dat_r[31:0] \main_wb_sdram_dat_r + case + end + attribute \src "ls180.v:8229.2-8231.5" + switch \main_converter_counter_converter_next_value_ce + attribute \src "ls180.v:8229.6-8229.52" + case 1'1 + assign $0\main_converter_counter[0:0] \main_converter_counter_converter_next_value + case + end + attribute \src "ls180.v:8232.2-8235.5" + switch \main_converter_reset + attribute \src "ls180.v:8232.6-8232.26" + case 1'1 + assign $0\main_converter_counter[0:0] 1'0 + assign $0\builder_converter_state[0:0] 1'0 + case + end + attribute \src "ls180.v:8236.2-8246.5" + switch \main_litedram_wb_ack + attribute \src "ls180.v:8236.6-8236.26" + case 1'1 + assign $0\main_cmd_consumed[0:0] 1'0 + assign $0\main_wdata_consumed[0:0] 1'0 + attribute \src "ls180.v:8239.6-8239.10" + case + attribute \src "ls180.v:8240.3-8242.6" + switch $and$ls180.v:8240$2740_Y + attribute \src "ls180.v:8240.7-8240.50" + case 1'1 + assign $0\main_cmd_consumed[0:0] 1'1 + case + end + attribute \src "ls180.v:8243.3-8245.6" + switch $and$ls180.v:8243$2741_Y + attribute \src "ls180.v:8243.7-8243.54" + case 1'1 + assign $0\main_wdata_consumed[0:0] 1'1 + case + end + end + attribute \src "ls180.v:8248.2-8269.5" + switch $and$ls180.v:8248$2745_Y + attribute \src "ls180.v:8248.6-8248.91" + case 1'1 + assign $0\main_uart_phy_tx_reg[7:0] \main_uart_phy_sink_payload_data + assign $0\main_uart_phy_tx_bitcount[3:0] 4'0000 + assign $0\main_uart_phy_tx_busy[0:0] 1'1 + assign $0\uart_tx[0:0] 1'0 + attribute \src "ls180.v:8253.6-8253.10" + case + attribute \src "ls180.v:8254.3-8268.6" + switch $and$ls180.v:8254$2746_Y + attribute \src "ls180.v:8254.7-8254.60" + case 1'1 + assign $0\main_uart_phy_tx_bitcount[3:0] $add$ls180.v:8255$2747_Y + attribute \src "ls180.v:8256.4-8267.7" + switch $eq$ls180.v:8256$2748_Y + attribute \src "ls180.v:8256.8-8256.43" + case 1'1 + assign $0\uart_tx[0:0] 1'1 + attribute \src "ls180.v:8258.8-8258.12" + case + attribute \src "ls180.v:8259.5-8266.8" + switch $eq$ls180.v:8259$2749_Y + attribute \src "ls180.v:8259.9-8259.44" + case 1'1 + assign $0\uart_tx[0:0] 1'1 + assign $0\main_uart_phy_tx_busy[0:0] 1'0 + assign $0\main_uart_phy_sink_ready[0:0] 1'1 + attribute \src "ls180.v:8263.9-8263.13" + case + assign $0\uart_tx[0:0] \main_uart_phy_tx_reg [0] + assign $0\main_uart_phy_tx_reg[7:0] { 1'0 \main_uart_phy_tx_reg [7:1] } + end + end + case + end + end + attribute \src "ls180.v:8270.2-8274.5" + switch \main_uart_phy_tx_busy + attribute \src "ls180.v:8270.6-8270.27" + case 1'1 + assign { $0\main_uart_phy_uart_clk_txen[0:0] $0\main_uart_phy_phase_accumulator_tx[31:0] } $add$ls180.v:8271$2750_Y + attribute \src "ls180.v:8272.6-8272.10" + case + assign { $0\main_uart_phy_uart_clk_txen[0:0] $0\main_uart_phy_phase_accumulator_tx[31:0] } { 1'0 \main_uart_phy_storage } + end + attribute \src "ls180.v:8277.2-8301.5" + switch $not$ls180.v:8277$2751_Y + attribute \src "ls180.v:8277.6-8277.30" + case 1'1 + attribute \src "ls180.v:8278.3-8281.6" + switch $and$ls180.v:8278$2753_Y + attribute \src "ls180.v:8278.7-8278.49" + case 1'1 + assign $0\main_uart_phy_rx_busy[0:0] 1'1 + assign $0\main_uart_phy_rx_bitcount[3:0] 4'0000 + case + end + attribute \src "ls180.v:8282.6-8282.10" + case + attribute \src "ls180.v:8283.3-8300.6" + switch \main_uart_phy_uart_clk_rxen + attribute \src "ls180.v:8283.7-8283.34" + case 1'1 + assign $0\main_uart_phy_rx_bitcount[3:0] $add$ls180.v:8284$2754_Y + attribute \src "ls180.v:8285.4-8299.7" + switch $eq$ls180.v:8285$2755_Y + attribute \src "ls180.v:8285.8-8285.43" + case 1'1 + attribute \src "ls180.v:8286.5-8288.8" + switch \main_uart_phy_rx + attribute \src "ls180.v:8286.9-8286.25" + case 1'1 + assign $0\main_uart_phy_rx_busy[0:0] 1'0 + case + end + attribute \src "ls180.v:8289.8-8289.12" + case + attribute \src "ls180.v:8290.5-8298.8" + switch $eq$ls180.v:8290$2756_Y + attribute \src "ls180.v:8290.9-8290.44" + case 1'1 + assign $0\main_uart_phy_rx_busy[0:0] 1'0 + attribute \src "ls180.v:8292.6-8295.9" + switch \main_uart_phy_rx + attribute \src "ls180.v:8292.10-8292.26" + case 1'1 + assign $0\main_uart_phy_source_payload_data[7:0] \main_uart_phy_rx_reg + assign $0\main_uart_phy_source_valid[0:0] 1'1 + case + end + attribute \src "ls180.v:8296.9-8296.13" + case + assign $0\main_uart_phy_rx_reg[7:0] { \main_uart_phy_rx \main_uart_phy_rx_reg [7:1] } + end + end + case + end + end + attribute \src "ls180.v:8302.2-8306.5" + switch \main_uart_phy_rx_busy + attribute \src "ls180.v:8302.6-8302.27" + case 1'1 + assign { $0\main_uart_phy_uart_clk_rxen[0:0] $0\main_uart_phy_phase_accumulator_rx[31:0] } $add$ls180.v:8303$2757_Y + attribute \src "ls180.v:8304.6-8304.10" + case + assign { $0\main_uart_phy_uart_clk_rxen[0:0] $0\main_uart_phy_phase_accumulator_rx[31:0] } 33'010000000000000000000000000000000 + end + attribute \src "ls180.v:8307.2-8309.5" + switch \main_uart_tx_clear + attribute \src "ls180.v:8307.6-8307.24" + case 1'1 + assign $0\main_uart_tx_pending[0:0] 1'0 + case + end + attribute \src "ls180.v:8311.2-8313.5" + switch $and$ls180.v:8311$2759_Y + attribute \src "ls180.v:8311.6-8311.58" + case 1'1 + assign $0\main_uart_tx_pending[0:0] 1'1 + case + end + attribute \src "ls180.v:8314.2-8316.5" + switch \main_uart_rx_clear + attribute \src "ls180.v:8314.6-8314.24" + case 1'1 + assign $0\main_uart_rx_pending[0:0] 1'0 + case + end + attribute \src "ls180.v:8318.2-8320.5" + switch $and$ls180.v:8318$2761_Y + attribute \src "ls180.v:8318.6-8318.58" + case 1'1 + assign $0\main_uart_rx_pending[0:0] 1'1 + case + end + attribute \src "ls180.v:8321.2-8327.5" + switch \main_uart_tx_fifo_syncfifo_re + attribute \src "ls180.v:8321.6-8321.35" + case 1'1 + assign $0\main_uart_tx_fifo_readable[0:0] 1'1 + attribute \src "ls180.v:8323.6-8323.10" + case + attribute \src "ls180.v:8324.3-8326.6" + switch \main_uart_tx_fifo_re + attribute \src "ls180.v:8324.7-8324.27" + case 1'1 + assign $0\main_uart_tx_fifo_readable[0:0] 1'0 + case + end + end + attribute \src "ls180.v:8328.2-8330.5" + switch $and$ls180.v:8328$2764_Y + attribute \src "ls180.v:8328.6-8328.108" + case 1'1 + assign $0\main_uart_tx_fifo_produce[3:0] $add$ls180.v:8329$2765_Y + case + end + attribute \src "ls180.v:8331.2-8333.5" + switch \main_uart_tx_fifo_do_read + attribute \src "ls180.v:8331.6-8331.31" + case 1'1 + assign $0\main_uart_tx_fifo_consume[3:0] $add$ls180.v:8332$2766_Y + case + end + attribute \src "ls180.v:8334.2-8342.5" + switch $and$ls180.v:8334$2769_Y + attribute \src "ls180.v:8334.6-8334.108" + case 1'1 + attribute \src "ls180.v:8335.3-8337.6" + switch $not$ls180.v:8335$2770_Y + attribute \src "ls180.v:8335.7-8335.35" + case 1'1 + assign $0\main_uart_tx_fifo_level0[4:0] $add$ls180.v:8336$2771_Y + case + end + attribute \src "ls180.v:8338.6-8338.10" + case + attribute \src "ls180.v:8339.3-8341.6" + switch \main_uart_tx_fifo_do_read + attribute \src "ls180.v:8339.7-8339.32" + case 1'1 + assign $0\main_uart_tx_fifo_level0[4:0] $sub$ls180.v:8340$2772_Y + case + end + end + attribute \src "ls180.v:8343.2-8349.5" + switch \main_uart_rx_fifo_syncfifo_re + attribute \src "ls180.v:8343.6-8343.35" + case 1'1 + assign $0\main_uart_rx_fifo_readable[0:0] 1'1 + attribute \src "ls180.v:8345.6-8345.10" + case + attribute \src "ls180.v:8346.3-8348.6" + switch \main_uart_rx_fifo_re + attribute \src "ls180.v:8346.7-8346.27" + case 1'1 + assign $0\main_uart_rx_fifo_readable[0:0] 1'0 + case + end + end + attribute \src "ls180.v:8350.2-8352.5" + switch $and$ls180.v:8350$2775_Y + attribute \src "ls180.v:8350.6-8350.108" + case 1'1 + assign $0\main_uart_rx_fifo_produce[3:0] $add$ls180.v:8351$2776_Y + case + end + attribute \src "ls180.v:8353.2-8355.5" + switch \main_uart_rx_fifo_do_read + attribute \src "ls180.v:8353.6-8353.31" + case 1'1 + assign $0\main_uart_rx_fifo_consume[3:0] $add$ls180.v:8354$2777_Y + case + end + attribute \src "ls180.v:8356.2-8364.5" + switch $and$ls180.v:8356$2780_Y + attribute \src "ls180.v:8356.6-8356.108" + case 1'1 + attribute \src "ls180.v:8357.3-8359.6" + switch $not$ls180.v:8357$2781_Y + attribute \src "ls180.v:8357.7-8357.35" + case 1'1 + assign $0\main_uart_rx_fifo_level0[4:0] $add$ls180.v:8358$2782_Y + case + end + attribute \src "ls180.v:8360.6-8360.10" + case + attribute \src "ls180.v:8361.3-8363.6" + switch \main_uart_rx_fifo_do_read + attribute \src "ls180.v:8361.7-8361.32" + case 1'1 + assign $0\main_uart_rx_fifo_level0[4:0] $sub$ls180.v:8362$2783_Y + case + end + end + attribute \src "ls180.v:8365.2-8378.5" + switch \main_uart_reset + attribute \src "ls180.v:8365.6-8365.21" + case 1'1 + assign $0\main_uart_tx_pending[0:0] 1'0 + assign $0\main_uart_tx_old_trigger[0:0] 1'0 + assign $0\main_uart_rx_pending[0:0] 1'0 + assign $0\main_uart_rx_old_trigger[0:0] 1'0 + assign $0\main_uart_tx_fifo_readable[0:0] 1'0 + assign $0\main_uart_tx_fifo_level0[4:0] 5'00000 + assign $0\main_uart_tx_fifo_produce[3:0] 4'0000 + assign $0\main_uart_tx_fifo_consume[3:0] 4'0000 + assign $0\main_uart_rx_fifo_readable[0:0] 1'0 + assign $0\main_uart_rx_fifo_level0[4:0] 5'00000 + assign $0\main_uart_rx_fifo_produce[3:0] 4'0000 + assign $0\main_uart_rx_fifo_consume[3:0] 4'0000 + case + end + attribute \src "ls180.v:8380.2-8387.5" + switch \main_spimaster31_clk_rise + attribute \src "ls180.v:8380.6-8380.31" + case 1'1 + assign $0\spisdcard_clk[0:0] \main_spimaster25_clk_enable + attribute \src "ls180.v:8382.6-8382.10" + case + attribute \src "ls180.v:8383.3-8386.6" + switch \main_spimaster32_clk_fall + attribute \src "ls180.v:8383.7-8383.32" + case 1'1 + assign $0\main_spimaster30_clk_divider[15:0] 16'0000000000000000 + assign $0\spisdcard_clk[0:0] 1'0 + case + end + end + attribute \src "ls180.v:8389.2-8399.5" + switch \main_spimaster28_mosi_latch + attribute \src "ls180.v:8389.6-8389.33" + case 1'1 + assign $0\main_spimaster33_mosi_data[7:0] \main_spimaster4_mosi + assign $0\main_spimaster34_mosi_sel[2:0] 3'111 + attribute \src "ls180.v:8392.6-8392.10" + case + attribute \src "ls180.v:8393.3-8398.6" + switch \main_spimaster32_clk_fall + attribute \src "ls180.v:8393.7-8393.32" + case 1'1 + assign $0\main_spimaster34_mosi_sel[2:0] $sub$ls180.v:8397$2788_Y + attribute \src "ls180.v:8394.4-8396.7" + switch \main_spimaster26_cs_enable + attribute \src "ls180.v:8394.8-8394.34" + case 1'1 + assign $0\spisdcard_mosi[0:0] \builder_sync_f_array_muxed0 + case + end + case + end + end + attribute \src "ls180.v:8400.2-8406.5" + switch \main_spimaster31_clk_rise + attribute \src "ls180.v:8400.6-8400.31" + case 1'1 + attribute \src "ls180.v:8401.3-8405.6" + switch \main_spimaster7_loopback + attribute \src "ls180.v:8401.7-8401.31" + case 1'1 + assign $0\main_spimaster35_miso_data[7:0] { \main_spimaster35_miso_data [6:0] \spisdcard_mosi } + attribute \src "ls180.v:8403.7-8403.11" + case + assign $0\main_spimaster35_miso_data[7:0] { \main_spimaster35_miso_data [6:0] \spisdcard_miso } + end + case + end + attribute \src "ls180.v:8407.2-8409.5" + switch \main_spimaster29_miso_latch + attribute \src "ls180.v:8407.6-8407.33" + case 1'1 + assign $0\main_spimaster5_miso[7:0] \main_spimaster35_miso_data + case + end + attribute \src "ls180.v:8411.2-8413.5" + switch \main_spimaster27_count_spimaster0_next_value_ce + attribute \src "ls180.v:8411.6-8411.53" + case 1'1 + assign $0\main_spimaster27_count[2:0] \main_spimaster27_count_spimaster0_next_value + case + end + attribute \src "ls180.v:8415.2-8422.5" + switch \main_spisdcard_clk_rise + attribute \src "ls180.v:8415.6-8415.29" + case 1'1 + assign $0\spimaster_clk[0:0] \main_spisdcard_clk_enable + attribute \src "ls180.v:8417.6-8417.10" + case + attribute \src "ls180.v:8418.3-8421.6" + switch \main_spisdcard_clk_fall + attribute \src "ls180.v:8418.7-8418.30" + case 1'1 + assign $0\main_spisdcard_clk_divider1[15:0] 16'0000000000000000 + assign $0\spimaster_clk[0:0] 1'0 + case + end + end + attribute \src "ls180.v:8424.2-8434.5" + switch \main_spisdcard_mosi_latch + attribute \src "ls180.v:8424.6-8424.31" + case 1'1 + assign $0\main_spisdcard_mosi_data[7:0] \main_spisdcard_mosi + assign $0\main_spisdcard_mosi_sel[2:0] 3'111 + attribute \src "ls180.v:8427.6-8427.10" + case + attribute \src "ls180.v:8428.3-8433.6" + switch \main_spisdcard_clk_fall + attribute \src "ls180.v:8428.7-8428.30" + case 1'1 + assign $0\main_spisdcard_mosi_sel[2:0] $sub$ls180.v:8432$2793_Y + attribute \src "ls180.v:8429.4-8431.7" + switch \main_spisdcard_cs_enable + attribute \src "ls180.v:8429.8-8429.32" + case 1'1 + assign $0\spimaster_mosi[0:0] \builder_sync_f_array_muxed1 + case + end + case + end + end + attribute \src "ls180.v:8435.2-8441.5" + switch \main_spisdcard_clk_rise + attribute \src "ls180.v:8435.6-8435.29" + case 1'1 + attribute \src "ls180.v:8436.3-8440.6" + switch \main_spisdcard_loopback + attribute \src "ls180.v:8436.7-8436.30" + case 1'1 + assign $0\main_spisdcard_miso_data[7:0] { \main_spisdcard_miso_data [6:0] \spimaster_mosi } + attribute \src "ls180.v:8438.7-8438.11" + case + assign $0\main_spisdcard_miso_data[7:0] { \main_spisdcard_miso_data [6:0] \spimaster_miso } + end + case + end + attribute \src "ls180.v:8442.2-8444.5" + switch \main_spisdcard_miso_latch + attribute \src "ls180.v:8442.6-8442.31" + case 1'1 + assign $0\main_spisdcard_miso[7:0] \main_spisdcard_miso_data + case + end + attribute \src "ls180.v:8446.2-8448.5" + switch \main_spisdcard_count_spimaster1_next_value_ce + attribute \src "ls180.v:8446.6-8446.51" + case 1'1 + assign $0\main_spisdcard_count[2:0] \main_spisdcard_count_spimaster1_next_value + case + end + attribute \src "ls180.v:8449.2-8462.5" + switch \main_pwm0_enable + attribute \src "ls180.v:8449.6-8449.22" + case 1'1 + assign $0\main_pwm0_counter[31:0] $add$ls180.v:8450$2794_Y + attribute \src "ls180.v:8451.3-8455.6" + switch $lt$ls180.v:8451$2795_Y + attribute \src "ls180.v:8451.7-8451.44" + case 1'1 + assign $0\pwm[1:0] [0] 1'1 + attribute \src "ls180.v:8453.7-8453.11" + case + assign $0\pwm[1:0] [0] 1'0 + end + attribute \src "ls180.v:8456.3-8458.6" + switch $ge$ls180.v:8456$2797_Y + attribute \src "ls180.v:8456.7-8456.55" + case 1'1 + assign $0\main_pwm0_counter[31:0] 0 + case + end + attribute \src "ls180.v:8459.6-8459.10" + case + assign $0\main_pwm0_counter[31:0] 0 + assign $0\pwm[1:0] [0] 1'0 + end + attribute \src "ls180.v:8463.2-8476.5" + switch \main_pwm1_enable + attribute \src "ls180.v:8463.6-8463.22" + case 1'1 + assign $0\main_pwm1_counter[31:0] $add$ls180.v:8464$2798_Y + attribute \src "ls180.v:8465.3-8469.6" + switch $lt$ls180.v:8465$2799_Y + attribute \src "ls180.v:8465.7-8465.44" + case 1'1 + assign $0\pwm[1:0] [1] 1'1 + attribute \src "ls180.v:8467.7-8467.11" + case + assign $0\pwm[1:0] [1] 1'0 + end + attribute \src "ls180.v:8470.3-8472.6" + switch $ge$ls180.v:8470$2801_Y + attribute \src "ls180.v:8470.7-8470.55" + case 1'1 + assign $0\main_pwm1_counter[31:0] 0 + case + end + attribute \src "ls180.v:8473.6-8473.10" + case + assign $0\main_pwm1_counter[31:0] 0 + assign $0\pwm[1:0] [1] 1'0 + end + attribute \src "ls180.v:8477.2-8479.5" + switch $not$ls180.v:8477$2802_Y + attribute \src "ls180.v:8477.6-8477.32" + case 1'1 + assign $0\main_sdphy_clocker_clks[8:0] $add$ls180.v:8478$2803_Y + case + end + attribute \src "ls180.v:8483.2-8485.5" + switch \main_sdphy_init_count_sdphy_sdphyinit_next_value_ce + attribute \src "ls180.v:8483.6-8483.57" + case 1'1 + assign $0\main_sdphy_init_count[7:0] \main_sdphy_init_count_sdphy_sdphyinit_next_value + case + end + attribute \src "ls180.v:8487.2-8489.5" + switch \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce + attribute \src "ls180.v:8487.6-8487.57" + case 1'1 + assign $0\main_sdphy_cmdw_count[7:0] \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value + case + end + attribute \src "ls180.v:8490.2-8492.5" + switch \main_sdphy_cmdr_cmdr_pads_in_valid + attribute \src "ls180.v:8490.6-8490.40" + case 1'1 + assign $0\main_sdphy_cmdr_cmdr_run[0:0] $or$ls180.v:8491$2804_Y + case + end + attribute \src "ls180.v:8493.2-8495.5" + switch \main_sdphy_cmdr_cmdr_converter_source_ready + attribute \src "ls180.v:8493.6-8493.49" + case 1'1 + assign $0\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] 1'0 + case + end + attribute \src "ls180.v:8496.2-8503.5" + switch \main_sdphy_cmdr_cmdr_converter_load_part + attribute \src "ls180.v:8496.6-8496.46" + case 1'1 + attribute \src "ls180.v:8497.3-8502.6" + switch $or$ls180.v:8497$2806_Y + attribute \src "ls180.v:8497.7-8497.98" + case 1'1 + assign $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] 3'000 + assign $0\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] 1'1 + attribute \src "ls180.v:8500.7-8500.11" + case + assign $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] $add$ls180.v:8501$2807_Y + end + case + end + attribute \src "ls180.v:8504.2-8517.5" + switch $and$ls180.v:8504$2808_Y + attribute \src "ls180.v:8504.6-8504.97" + case 1'1 + attribute \src "ls180.v:8505.3-8511.6" + switch $and$ls180.v:8505$2809_Y + attribute \src "ls180.v:8505.7-8505.94" + case 1'1 + assign $0\main_sdphy_cmdr_cmdr_converter_source_first[0:0] \main_sdphy_cmdr_cmdr_converter_sink_first + assign $0\main_sdphy_cmdr_cmdr_converter_source_last[0:0] \main_sdphy_cmdr_cmdr_converter_sink_last + attribute \src "ls180.v:8508.7-8508.11" + case + assign $0\main_sdphy_cmdr_cmdr_converter_source_first[0:0] 1'0 + assign $0\main_sdphy_cmdr_cmdr_converter_source_last[0:0] 1'0 + end + attribute \src "ls180.v:8512.6-8512.10" + case + attribute \src "ls180.v:8513.3-8516.6" + switch $and$ls180.v:8513$2810_Y + attribute \src "ls180.v:8513.7-8513.94" + case 1'1 + assign $0\main_sdphy_cmdr_cmdr_converter_source_first[0:0] $or$ls180.v:8514$2811_Y + assign $0\main_sdphy_cmdr_cmdr_converter_source_last[0:0] $or$ls180.v:8515$2812_Y + case + end + end + attribute \src "ls180.v:8518.2-8545.5" + switch \main_sdphy_cmdr_cmdr_converter_load_part + attribute \src "ls180.v:8518.6-8518.46" + case 1'1 + attribute \src "ls180.v:8519.3-8544.10" + switch \main_sdphy_cmdr_cmdr_converter_demux + attribute \src "ls180.v:0.0-0.0" + case 3'000 + assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] [7] \main_sdphy_cmdr_cmdr_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] [6] \main_sdphy_cmdr_cmdr_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] [5] \main_sdphy_cmdr_cmdr_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] [4] \main_sdphy_cmdr_cmdr_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] [3] \main_sdphy_cmdr_cmdr_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 3'101 + assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] [2] \main_sdphy_cmdr_cmdr_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 3'110 + assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] [1] \main_sdphy_cmdr_cmdr_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 3'111 + assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] [0] \main_sdphy_cmdr_cmdr_converter_sink_payload_data + case + end + case + end + attribute \src "ls180.v:8546.2-8548.5" + switch \main_sdphy_cmdr_cmdr_converter_load_part + attribute \src "ls180.v:8546.6-8546.46" + case 1'1 + assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] $add$ls180.v:8547$2813_Y + case + end + attribute \src "ls180.v:8549.2-8554.5" + switch $or$ls180.v:8549$2815_Y + attribute \src "ls180.v:8549.6-8549.88" + case 1'1 + assign $0\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] \main_sdphy_cmdr_cmdr_buf_sink_valid + assign $0\main_sdphy_cmdr_cmdr_buf_source_first[0:0] \main_sdphy_cmdr_cmdr_buf_sink_first + assign $0\main_sdphy_cmdr_cmdr_buf_source_last[0:0] \main_sdphy_cmdr_cmdr_buf_sink_last + assign $0\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0] \main_sdphy_cmdr_cmdr_buf_sink_payload_data + case + end + attribute \src "ls180.v:8555.2-8560.5" + switch \main_sdphy_cmdr_cmdr_reset + attribute \src "ls180.v:8555.6-8555.32" + case 1'1 + assign $0\main_sdphy_cmdr_cmdr_run[0:0] 1'0 + assign $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] 3'000 + assign $0\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] 1'0 + assign $0\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] 1'0 + case + end + attribute \src "ls180.v:8562.2-8564.5" + switch \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0 + attribute \src "ls180.v:8562.6-8562.58" + case 1'1 + assign $0\main_sdphy_cmdr_count[7:0] \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0 + case + end + attribute \src "ls180.v:8565.2-8567.5" + switch \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1 + attribute \src "ls180.v:8565.6-8565.60" + case 1'1 + assign $0\main_sdphy_cmdr_timeout[31:0] \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1 + case + end + attribute \src "ls180.v:8568.2-8570.5" + switch \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2 + attribute \src "ls180.v:8568.6-8568.63" + case 1'1 + assign $0\main_sdphy_cmdr_cmdr_reset[0:0] \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2 + case + end + attribute \src "ls180.v:8571.2-8573.5" + switch \main_sdphy_dataw_crcr_pads_in_valid + attribute \src "ls180.v:8571.6-8571.41" + case 1'1 + assign $0\main_sdphy_dataw_crcr_run[0:0] $or$ls180.v:8572$2816_Y + case + end + attribute \src "ls180.v:8574.2-8576.5" + switch \main_sdphy_dataw_crcr_converter_source_ready + attribute \src "ls180.v:8574.6-8574.50" + case 1'1 + assign $0\main_sdphy_dataw_crcr_converter_strobe_all[0:0] 1'0 + case + end + attribute \src "ls180.v:8577.2-8584.5" + switch \main_sdphy_dataw_crcr_converter_load_part + attribute \src "ls180.v:8577.6-8577.47" + case 1'1 + attribute \src "ls180.v:8578.3-8583.6" + switch $or$ls180.v:8578$2818_Y + attribute \src "ls180.v:8578.7-8578.100" + case 1'1 + assign $0\main_sdphy_dataw_crcr_converter_demux[2:0] 3'000 + assign $0\main_sdphy_dataw_crcr_converter_strobe_all[0:0] 1'1 + attribute \src "ls180.v:8581.7-8581.11" + case + assign $0\main_sdphy_dataw_crcr_converter_demux[2:0] $add$ls180.v:8582$2819_Y + end + case + end + attribute \src "ls180.v:8585.2-8598.5" + switch $and$ls180.v:8585$2820_Y + attribute \src "ls180.v:8585.6-8585.99" + case 1'1 + attribute \src "ls180.v:8586.3-8592.6" + switch $and$ls180.v:8586$2821_Y + attribute \src "ls180.v:8586.7-8586.96" + case 1'1 + assign $0\main_sdphy_dataw_crcr_converter_source_first[0:0] \main_sdphy_dataw_crcr_converter_sink_first + assign $0\main_sdphy_dataw_crcr_converter_source_last[0:0] \main_sdphy_dataw_crcr_converter_sink_last + attribute \src "ls180.v:8589.7-8589.11" + case + assign $0\main_sdphy_dataw_crcr_converter_source_first[0:0] 1'0 + assign $0\main_sdphy_dataw_crcr_converter_source_last[0:0] 1'0 + end + attribute \src "ls180.v:8593.6-8593.10" + case + attribute \src "ls180.v:8594.3-8597.6" + switch $and$ls180.v:8594$2822_Y + attribute \src "ls180.v:8594.7-8594.96" + case 1'1 + assign $0\main_sdphy_dataw_crcr_converter_source_first[0:0] $or$ls180.v:8595$2823_Y + assign $0\main_sdphy_dataw_crcr_converter_source_last[0:0] $or$ls180.v:8596$2824_Y + case + end + end + attribute \src "ls180.v:8599.2-8626.5" + switch \main_sdphy_dataw_crcr_converter_load_part + attribute \src "ls180.v:8599.6-8599.47" + case 1'1 + attribute \src "ls180.v:8600.3-8625.10" + switch \main_sdphy_dataw_crcr_converter_demux + attribute \src "ls180.v:0.0-0.0" + case 3'000 + assign $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] [7] \main_sdphy_dataw_crcr_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] [6] \main_sdphy_dataw_crcr_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] [5] \main_sdphy_dataw_crcr_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] [4] \main_sdphy_dataw_crcr_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] [3] \main_sdphy_dataw_crcr_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 3'101 + assign $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] [2] \main_sdphy_dataw_crcr_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 3'110 + assign $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] [1] \main_sdphy_dataw_crcr_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 3'111 + assign $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] [0] \main_sdphy_dataw_crcr_converter_sink_payload_data + case + end + case + end + attribute \src "ls180.v:8627.2-8629.5" + switch \main_sdphy_dataw_crcr_converter_load_part + attribute \src "ls180.v:8627.6-8627.47" + case 1'1 + assign $0\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] $add$ls180.v:8628$2825_Y + case + end + attribute \src "ls180.v:8630.2-8635.5" + switch $or$ls180.v:8630$2827_Y + attribute \src "ls180.v:8630.6-8630.90" + case 1'1 + assign $0\main_sdphy_dataw_crcr_buf_source_valid[0:0] \main_sdphy_dataw_crcr_buf_sink_valid + assign $0\main_sdphy_dataw_crcr_buf_source_first[0:0] \main_sdphy_dataw_crcr_buf_sink_first + assign $0\main_sdphy_dataw_crcr_buf_source_last[0:0] \main_sdphy_dataw_crcr_buf_sink_last + assign $0\main_sdphy_dataw_crcr_buf_source_payload_data[7:0] \main_sdphy_dataw_crcr_buf_sink_payload_data + case + end + attribute \src "ls180.v:8636.2-8641.5" + switch \main_sdphy_dataw_crcr_reset + attribute \src "ls180.v:8636.6-8636.33" + case 1'1 + assign $0\main_sdphy_dataw_crcr_run[0:0] 1'0 + assign $0\main_sdphy_dataw_crcr_converter_demux[2:0] 3'000 + assign $0\main_sdphy_dataw_crcr_converter_strobe_all[0:0] 1'0 + assign $0\main_sdphy_dataw_crcr_buf_source_valid[0:0] 1'0 + case + end + attribute \src "ls180.v:8643.2-8645.5" + switch \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce + attribute \src "ls180.v:8643.6-8643.63" + case 1'1 + assign $0\main_sdphy_dataw_crcr_reset[0:0] \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value + case + end + attribute \src "ls180.v:8647.2-8649.5" + switch \main_sdphy_dataw_count_sdphy_fsm_next_value_ce + attribute \src "ls180.v:8647.6-8647.52" + case 1'1 + assign $0\main_sdphy_dataw_count[7:0] \main_sdphy_dataw_count_sdphy_fsm_next_value + case + end + attribute \src "ls180.v:8650.2-8652.5" + switch \main_sdphy_datar_datar_pads_in_valid + attribute \src "ls180.v:8650.6-8650.42" + case 1'1 + assign $0\main_sdphy_datar_datar_run[0:0] $or$ls180.v:8651$2828_Y + case + end + attribute \src "ls180.v:8653.2-8655.5" + switch \main_sdphy_datar_datar_converter_source_ready + attribute \src "ls180.v:8653.6-8653.51" + case 1'1 + assign $0\main_sdphy_datar_datar_converter_strobe_all[0:0] 1'0 + case + end + attribute \src "ls180.v:8656.2-8663.5" + switch \main_sdphy_datar_datar_converter_load_part + attribute \src "ls180.v:8656.6-8656.48" + case 1'1 + attribute \src "ls180.v:8657.3-8662.6" + switch $or$ls180.v:8657$2830_Y + attribute \src "ls180.v:8657.7-8657.102" + case 1'1 + assign $0\main_sdphy_datar_datar_converter_demux[0:0] 1'0 + assign $0\main_sdphy_datar_datar_converter_strobe_all[0:0] 1'1 + attribute \src "ls180.v:8660.7-8660.11" + case + assign $0\main_sdphy_datar_datar_converter_demux[0:0] $add$ls180.v:8661$2831_Y + end + case + end + attribute \src "ls180.v:8664.2-8677.5" + switch $and$ls180.v:8664$2832_Y + attribute \src "ls180.v:8664.6-8664.101" + case 1'1 + attribute \src "ls180.v:8665.3-8671.6" + switch $and$ls180.v:8665$2833_Y + attribute \src "ls180.v:8665.7-8665.98" + case 1'1 + assign $0\main_sdphy_datar_datar_converter_source_first[0:0] \main_sdphy_datar_datar_converter_sink_first + assign $0\main_sdphy_datar_datar_converter_source_last[0:0] \main_sdphy_datar_datar_converter_sink_last + attribute \src "ls180.v:8668.7-8668.11" + case + assign $0\main_sdphy_datar_datar_converter_source_first[0:0] 1'0 + assign $0\main_sdphy_datar_datar_converter_source_last[0:0] 1'0 + end + attribute \src "ls180.v:8672.6-8672.10" + case + attribute \src "ls180.v:8673.3-8676.6" + switch $and$ls180.v:8673$2834_Y + attribute \src "ls180.v:8673.7-8673.98" + case 1'1 + assign $0\main_sdphy_datar_datar_converter_source_first[0:0] $or$ls180.v:8674$2835_Y + assign $0\main_sdphy_datar_datar_converter_source_last[0:0] $or$ls180.v:8675$2836_Y + case + end + end + attribute \src "ls180.v:8678.2-8687.5" + switch \main_sdphy_datar_datar_converter_load_part + attribute \src "ls180.v:8678.6-8678.48" + case 1'1 + attribute \src "ls180.v:8679.3-8686.10" + switch \main_sdphy_datar_datar_converter_demux + attribute \src "ls180.v:0.0-0.0" + case 1'0 + assign $0\main_sdphy_datar_datar_converter_source_payload_data[7:0] [7:4] \main_sdphy_datar_datar_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 1'1 + assign $0\main_sdphy_datar_datar_converter_source_payload_data[7:0] [3:0] \main_sdphy_datar_datar_converter_sink_payload_data + case + end + case + end + attribute \src "ls180.v:8688.2-8690.5" + switch \main_sdphy_datar_datar_converter_load_part + attribute \src "ls180.v:8688.6-8688.48" + case 1'1 + assign $0\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] $add$ls180.v:8689$2837_Y + case + end + attribute \src "ls180.v:8691.2-8696.5" + switch $or$ls180.v:8691$2839_Y + attribute \src "ls180.v:8691.6-8691.92" + case 1'1 + assign $0\main_sdphy_datar_datar_buf_source_valid[0:0] \main_sdphy_datar_datar_buf_sink_valid + assign $0\main_sdphy_datar_datar_buf_source_first[0:0] \main_sdphy_datar_datar_buf_sink_first + assign $0\main_sdphy_datar_datar_buf_source_last[0:0] \main_sdphy_datar_datar_buf_sink_last + assign $0\main_sdphy_datar_datar_buf_source_payload_data[7:0] \main_sdphy_datar_datar_buf_sink_payload_data + case + end + attribute \src "ls180.v:8697.2-8702.5" + switch \main_sdphy_datar_datar_reset + attribute \src "ls180.v:8697.6-8697.34" + case 1'1 + assign $0\main_sdphy_datar_datar_run[0:0] 1'0 + assign $0\main_sdphy_datar_datar_converter_demux[0:0] 1'0 + assign $0\main_sdphy_datar_datar_converter_strobe_all[0:0] 1'0 + assign $0\main_sdphy_datar_datar_buf_source_valid[0:0] 1'0 + case + end + attribute \src "ls180.v:8704.2-8706.5" + switch \main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0 + attribute \src "ls180.v:8704.6-8704.60" + case 1'1 + assign $0\main_sdphy_datar_count[9:0] \main_sdphy_datar_count_sdphy_sdphydatar_next_value0 + case + end + attribute \src "ls180.v:8707.2-8709.5" + switch \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1 + attribute \src "ls180.v:8707.6-8707.62" + case 1'1 + assign $0\main_sdphy_datar_timeout[31:0] \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1 + case + end + attribute \src "ls180.v:8710.2-8712.5" + switch \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2 + attribute \src "ls180.v:8710.6-8710.66" + case 1'1 + assign $0\main_sdphy_datar_datar_reset[0:0] \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2 + case + end + attribute \src "ls180.v:8713.2-8719.5" + switch \main_sdcore_crc7_inserter_clr + attribute \src "ls180.v:8713.6-8713.35" + case 1'1 + assign $0\main_sdcore_crc7_inserter_crcreg0[6:0] 7'0000000 + attribute \src "ls180.v:8715.6-8715.10" + case + attribute \src "ls180.v:8716.3-8718.6" + switch \main_sdcore_crc7_inserter_enable + attribute \src "ls180.v:8716.7-8716.39" + case 1'1 + assign $0\main_sdcore_crc7_inserter_crcreg0[6:0] \main_sdcore_crc7_inserter_crcreg40 + case + end + end + attribute \src "ls180.v:8720.2-8726.5" + switch \main_sdcore_crc16_inserter_crc0_clr + attribute \src "ls180.v:8720.6-8720.41" + case 1'1 + assign $0\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] 16'0000000000000000 + attribute \src "ls180.v:8722.6-8722.10" + case + attribute \src "ls180.v:8723.3-8725.6" + switch \main_sdcore_crc16_inserter_crc0_enable + attribute \src "ls180.v:8723.7-8723.45" + case 1'1 + assign $0\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] \main_sdcore_crc16_inserter_crc0_crcreg2 + case + end + end + attribute \src "ls180.v:8727.2-8733.5" + switch \main_sdcore_crc16_inserter_crc1_clr + attribute \src "ls180.v:8727.6-8727.41" + case 1'1 + assign $0\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] 16'0000000000000000 + attribute \src "ls180.v:8729.6-8729.10" + case + attribute \src "ls180.v:8730.3-8732.6" + switch \main_sdcore_crc16_inserter_crc1_enable + attribute \src "ls180.v:8730.7-8730.45" + case 1'1 + assign $0\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] \main_sdcore_crc16_inserter_crc1_crcreg2 + case + end + end + attribute \src "ls180.v:8734.2-8740.5" + switch \main_sdcore_crc16_inserter_crc2_clr + attribute \src "ls180.v:8734.6-8734.41" + case 1'1 + assign $0\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] 16'0000000000000000 + attribute \src "ls180.v:8736.6-8736.10" + case + attribute \src "ls180.v:8737.3-8739.6" + switch \main_sdcore_crc16_inserter_crc2_enable + attribute \src "ls180.v:8737.7-8737.45" + case 1'1 + assign $0\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] \main_sdcore_crc16_inserter_crc2_crcreg2 + case + end + end + attribute \src "ls180.v:8741.2-8747.5" + switch \main_sdcore_crc16_inserter_crc3_clr + attribute \src "ls180.v:8741.6-8741.41" + case 1'1 + assign $0\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] 16'0000000000000000 + attribute \src "ls180.v:8743.6-8743.10" + case + attribute \src "ls180.v:8744.3-8746.6" + switch \main_sdcore_crc16_inserter_crc3_enable + attribute \src "ls180.v:8744.7-8744.45" + case 1'1 + assign $0\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] \main_sdcore_crc16_inserter_crc3_crcreg2 + case + end + end + attribute \src "ls180.v:8749.2-8751.5" + switch \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0 + attribute \src "ls180.v:8749.6-8749.82" + case 1'1 + assign $0\main_sdcore_crc16_inserter_crctmp0[15:0] \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0 + case + end + attribute \src "ls180.v:8752.2-8754.5" + switch \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1 + attribute \src "ls180.v:8752.6-8752.82" + case 1'1 + assign $0\main_sdcore_crc16_inserter_crctmp1[15:0] \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1 + case + end + attribute \src "ls180.v:8755.2-8757.5" + switch \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2 + attribute \src "ls180.v:8755.6-8755.82" + case 1'1 + assign $0\main_sdcore_crc16_inserter_crctmp2[15:0] \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2 + case + end + attribute \src "ls180.v:8758.2-8760.5" + switch \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3 + attribute \src "ls180.v:8758.6-8758.82" + case 1'1 + assign $0\main_sdcore_crc16_inserter_crctmp3[15:0] \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3 + case + end + attribute \src "ls180.v:8761.2-8763.5" + switch \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4 + attribute \src "ls180.v:8761.6-8761.78" + case 1'1 + assign $0\main_sdcore_crc16_inserter_cnt[2:0] \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4 + case + end + attribute \src "ls180.v:8764.2-8766.5" + switch $and$ls180.v:8764$2840_Y + attribute \src "ls180.v:8764.6-8764.83" + case 1'1 + assign $0\main_sdcore_crc16_checker_crctmp0[15:0] \main_sdcore_crc16_checker_crc0_crc + case + end + attribute \src "ls180.v:8767.2-8769.5" + switch $and$ls180.v:8767$2841_Y + attribute \src "ls180.v:8767.6-8767.83" + case 1'1 + assign $0\main_sdcore_crc16_checker_crctmp1[15:0] \main_sdcore_crc16_checker_crc1_crc + case + end + attribute \src "ls180.v:8770.2-8772.5" + switch $and$ls180.v:8770$2842_Y + attribute \src "ls180.v:8770.6-8770.83" + case 1'1 + assign $0\main_sdcore_crc16_checker_crctmp2[15:0] \main_sdcore_crc16_checker_crc2_crc + case + end + attribute \src "ls180.v:8773.2-8775.5" + switch $and$ls180.v:8773$2843_Y + attribute \src "ls180.v:8773.6-8773.83" + case 1'1 + assign $0\main_sdcore_crc16_checker_crctmp3[15:0] \main_sdcore_crc16_checker_crc3_crc + case + end + attribute \src "ls180.v:8776.2-8780.5" + switch $and$ls180.v:8776$2844_Y + attribute \src "ls180.v:8776.6-8776.83" + case 1'1 + assign $0\main_sdcore_crc16_checker_fifo0[15:0] { \main_sdcore_crc16_checker_fifo0 [13:0] \main_sdcore_crc16_checker_sink_payload_data [7] \main_sdcore_crc16_checker_sink_payload_data [3] } + assign $0\main_sdcore_crc16_checker_val[7:0] [7] \main_sdcore_crc16_checker_fifo0 [13] + assign $0\main_sdcore_crc16_checker_val[7:0] [3] \main_sdcore_crc16_checker_fifo0 [12] + case + end + attribute \src "ls180.v:8781.2-8785.5" + switch $and$ls180.v:8781$2845_Y + attribute \src "ls180.v:8781.6-8781.83" + case 1'1 + assign $0\main_sdcore_crc16_checker_fifo1[15:0] { \main_sdcore_crc16_checker_fifo1 [13:0] \main_sdcore_crc16_checker_sink_payload_data [6] \main_sdcore_crc16_checker_sink_payload_data [2] } + assign $0\main_sdcore_crc16_checker_val[7:0] [6] \main_sdcore_crc16_checker_fifo1 [13] + assign $0\main_sdcore_crc16_checker_val[7:0] [2] \main_sdcore_crc16_checker_fifo1 [12] + case + end + attribute \src "ls180.v:8786.2-8790.5" + switch $and$ls180.v:8786$2846_Y + attribute \src "ls180.v:8786.6-8786.83" + case 1'1 + assign $0\main_sdcore_crc16_checker_fifo2[15:0] { \main_sdcore_crc16_checker_fifo2 [13:0] \main_sdcore_crc16_checker_sink_payload_data [5] \main_sdcore_crc16_checker_sink_payload_data [1] } + assign $0\main_sdcore_crc16_checker_val[7:0] [5] \main_sdcore_crc16_checker_fifo2 [13] + assign $0\main_sdcore_crc16_checker_val[7:0] [1] \main_sdcore_crc16_checker_fifo2 [12] + case + end + attribute \src "ls180.v:8791.2-8795.5" + switch $and$ls180.v:8791$2847_Y + attribute \src "ls180.v:8791.6-8791.83" + case 1'1 + assign $0\main_sdcore_crc16_checker_fifo3[15:0] { \main_sdcore_crc16_checker_fifo3 [13:0] \main_sdcore_crc16_checker_sink_payload_data [4] \main_sdcore_crc16_checker_sink_payload_data [0] } + assign $0\main_sdcore_crc16_checker_val[7:0] [4] \main_sdcore_crc16_checker_fifo3 [13] + assign $0\main_sdcore_crc16_checker_val[7:0] [0] \main_sdcore_crc16_checker_fifo3 [12] + case + end + attribute \src "ls180.v:8796.2-8804.5" + switch $and$ls180.v:8796$2848_Y + attribute \src "ls180.v:8796.6-8796.83" + case 1'1 + attribute \src "ls180.v:8797.3-8803.6" + switch \main_sdcore_crc16_checker_sink_last + attribute \src "ls180.v:8797.7-8797.42" + case 1'1 + assign $0\main_sdcore_crc16_checker_cnt[3:0] 4'0000 + attribute \src "ls180.v:8799.7-8799.11" + case + attribute \src "ls180.v:8800.4-8802.7" + switch $ne$ls180.v:8800$2849_Y + attribute \src "ls180.v:8800.8-8800.48" + case 1'1 + assign $0\main_sdcore_crc16_checker_cnt[3:0] $add$ls180.v:8801$2850_Y + case + end + end + case + end + attribute \src "ls180.v:8805.2-8811.5" + switch \main_sdcore_crc16_checker_crc0_clr + attribute \src "ls180.v:8805.6-8805.40" + case 1'1 + assign $0\main_sdcore_crc16_checker_crc0_crcreg0[15:0] 16'0000000000000000 + attribute \src "ls180.v:8807.6-8807.10" + case + attribute \src "ls180.v:8808.3-8810.6" + switch \main_sdcore_crc16_checker_crc0_enable + attribute \src "ls180.v:8808.7-8808.44" + case 1'1 + assign $0\main_sdcore_crc16_checker_crc0_crcreg0[15:0] \main_sdcore_crc16_checker_crc0_crcreg2 + case + end + end + attribute \src "ls180.v:8812.2-8818.5" + switch \main_sdcore_crc16_checker_crc1_clr + attribute \src "ls180.v:8812.6-8812.40" + case 1'1 + assign $0\main_sdcore_crc16_checker_crc1_crcreg0[15:0] 16'0000000000000000 + attribute \src "ls180.v:8814.6-8814.10" + case + attribute \src "ls180.v:8815.3-8817.6" + switch \main_sdcore_crc16_checker_crc1_enable + attribute \src "ls180.v:8815.7-8815.44" + case 1'1 + assign $0\main_sdcore_crc16_checker_crc1_crcreg0[15:0] \main_sdcore_crc16_checker_crc1_crcreg2 + case + end + end + attribute \src "ls180.v:8819.2-8825.5" + switch \main_sdcore_crc16_checker_crc2_clr + attribute \src "ls180.v:8819.6-8819.40" + case 1'1 + assign $0\main_sdcore_crc16_checker_crc2_crcreg0[15:0] 16'0000000000000000 + attribute \src "ls180.v:8821.6-8821.10" + case + attribute \src "ls180.v:8822.3-8824.6" + switch \main_sdcore_crc16_checker_crc2_enable + attribute \src "ls180.v:8822.7-8822.44" + case 1'1 + assign $0\main_sdcore_crc16_checker_crc2_crcreg0[15:0] \main_sdcore_crc16_checker_crc2_crcreg2 + case + end + end + attribute \src "ls180.v:8826.2-8832.5" + switch \main_sdcore_crc16_checker_crc3_clr + attribute \src "ls180.v:8826.6-8826.40" + case 1'1 + assign $0\main_sdcore_crc16_checker_crc3_crcreg0[15:0] 16'0000000000000000 + attribute \src "ls180.v:8828.6-8828.10" + case + attribute \src "ls180.v:8829.3-8831.6" + switch \main_sdcore_crc16_checker_crc3_enable + attribute \src "ls180.v:8829.7-8829.44" + case 1'1 + assign $0\main_sdcore_crc16_checker_crc3_crcreg0[15:0] \main_sdcore_crc16_checker_crc3_crcreg2 + case + end + end + attribute \src "ls180.v:8834.2-8836.5" + switch \main_sdcore_cmd_done_sdcore_fsm_next_value_ce0 + attribute \src "ls180.v:8834.6-8834.52" + case 1'1 + assign $0\main_sdcore_cmd_done[0:0] \main_sdcore_cmd_done_sdcore_fsm_next_value0 + case + end + attribute \src "ls180.v:8837.2-8839.5" + switch \main_sdcore_data_done_sdcore_fsm_next_value_ce1 + attribute \src "ls180.v:8837.6-8837.53" + case 1'1 + assign $0\main_sdcore_data_done[0:0] \main_sdcore_data_done_sdcore_fsm_next_value1 + case + end + attribute \src "ls180.v:8840.2-8842.5" + switch \main_sdcore_cmd_count_sdcore_fsm_next_value_ce2 + attribute \src "ls180.v:8840.6-8840.53" + case 1'1 + assign $0\main_sdcore_cmd_count[2:0] \main_sdcore_cmd_count_sdcore_fsm_next_value2 + case + end + attribute \src "ls180.v:8843.2-8845.5" + switch \main_sdcore_data_count_sdcore_fsm_next_value_ce3 + attribute \src "ls180.v:8843.6-8843.54" + case 1'1 + assign $0\main_sdcore_data_count[31:0] \main_sdcore_data_count_sdcore_fsm_next_value3 + case + end + attribute \src "ls180.v:8846.2-8848.5" + switch \main_sdcore_cmd_error_sdcore_fsm_next_value_ce4 + attribute \src "ls180.v:8846.6-8846.53" + case 1'1 + assign $0\main_sdcore_cmd_error[0:0] \main_sdcore_cmd_error_sdcore_fsm_next_value4 + case + end + attribute \src "ls180.v:8849.2-8851.5" + switch \main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5 + attribute \src "ls180.v:8849.6-8849.55" + case 1'1 + assign $0\main_sdcore_cmd_timeout[0:0] \main_sdcore_cmd_timeout_sdcore_fsm_next_value5 + case + end + attribute \src "ls180.v:8852.2-8854.5" + switch \main_sdcore_data_error_sdcore_fsm_next_value_ce6 + attribute \src "ls180.v:8852.6-8852.54" + case 1'1 + assign $0\main_sdcore_data_error[0:0] \main_sdcore_data_error_sdcore_fsm_next_value6 + case + end + attribute \src "ls180.v:8855.2-8857.5" + switch \main_sdcore_data_timeout_sdcore_fsm_next_value_ce7 + attribute \src "ls180.v:8855.6-8855.56" + case 1'1 + assign $0\main_sdcore_data_timeout[0:0] \main_sdcore_data_timeout_sdcore_fsm_next_value7 + case + end + attribute \src "ls180.v:8858.2-8860.5" + switch \main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8 + attribute \src "ls180.v:8858.6-8858.63" + case 1'1 + assign $0\main_sdcore_cmd_response_status[127:0] \main_sdcore_cmd_response_status_sdcore_fsm_next_value8 + case + end + attribute \src "ls180.v:8861.2-8863.5" + switch $and$ls180.v:8861$2853_Y + attribute \src "ls180.v:8861.6-8861.120" + case 1'1 + assign $0\main_sdblock2mem_fifo_produce[4:0] $add$ls180.v:8862$2854_Y + case + end + attribute \src "ls180.v:8864.2-8866.5" + switch \main_sdblock2mem_fifo_do_read + attribute \src "ls180.v:8864.6-8864.35" + case 1'1 + assign $0\main_sdblock2mem_fifo_consume[4:0] $add$ls180.v:8865$2855_Y + case + end + attribute \src "ls180.v:8867.2-8875.5" + switch $and$ls180.v:8867$2858_Y + attribute \src "ls180.v:8867.6-8867.120" + case 1'1 + attribute \src "ls180.v:8868.3-8870.6" + switch $not$ls180.v:8868$2859_Y + attribute \src "ls180.v:8868.7-8868.39" + case 1'1 + assign $0\main_sdblock2mem_fifo_level[5:0] $add$ls180.v:8869$2860_Y + case + end + attribute \src "ls180.v:8871.6-8871.10" + case + attribute \src "ls180.v:8872.3-8874.6" + switch \main_sdblock2mem_fifo_do_read + attribute \src "ls180.v:8872.7-8872.36" + case 1'1 + assign $0\main_sdblock2mem_fifo_level[5:0] $sub$ls180.v:8873$2861_Y + case + end + end + attribute \src "ls180.v:8876.2-8878.5" + switch \main_sdblock2mem_converter_source_ready + attribute \src "ls180.v:8876.6-8876.45" + case 1'1 + assign $0\main_sdblock2mem_converter_strobe_all[0:0] 1'0 + case + end + attribute \src "ls180.v:8879.2-8886.5" + switch \main_sdblock2mem_converter_load_part + attribute \src "ls180.v:8879.6-8879.42" + case 1'1 + attribute \src "ls180.v:8880.3-8885.6" + switch $or$ls180.v:8880$2863_Y + attribute \src "ls180.v:8880.7-8880.90" + case 1'1 + assign $0\main_sdblock2mem_converter_demux[2:0] 3'000 + assign $0\main_sdblock2mem_converter_strobe_all[0:0] 1'1 + attribute \src "ls180.v:8883.7-8883.11" + case + assign $0\main_sdblock2mem_converter_demux[2:0] $add$ls180.v:8884$2864_Y + end + case + end + attribute \src "ls180.v:8887.2-8900.5" + switch $and$ls180.v:8887$2865_Y + attribute \src "ls180.v:8887.6-8887.89" + case 1'1 + attribute \src "ls180.v:8888.3-8894.6" + switch $and$ls180.v:8888$2866_Y + attribute \src "ls180.v:8888.7-8888.86" + case 1'1 + assign $0\main_sdblock2mem_converter_source_first[0:0] \main_sdblock2mem_converter_sink_first + assign $0\main_sdblock2mem_converter_source_last[0:0] \main_sdblock2mem_converter_sink_last + attribute \src "ls180.v:8891.7-8891.11" + case + assign $0\main_sdblock2mem_converter_source_first[0:0] 1'0 + assign $0\main_sdblock2mem_converter_source_last[0:0] 1'0 + end + attribute \src "ls180.v:8895.6-8895.10" + case + attribute \src "ls180.v:8896.3-8899.6" + switch $and$ls180.v:8896$2867_Y + attribute \src "ls180.v:8896.7-8896.86" + case 1'1 + assign $0\main_sdblock2mem_converter_source_first[0:0] $or$ls180.v:8897$2868_Y + assign $0\main_sdblock2mem_converter_source_last[0:0] $or$ls180.v:8898$2869_Y + case + end + end + attribute \src "ls180.v:8901.2-8928.5" + switch \main_sdblock2mem_converter_load_part + attribute \src "ls180.v:8901.6-8901.42" + case 1'1 + attribute \src "ls180.v:8902.3-8927.10" + switch \main_sdblock2mem_converter_demux + attribute \src "ls180.v:0.0-0.0" + case 3'000 + assign $0\main_sdblock2mem_converter_source_payload_data[63:0] [63:56] \main_sdblock2mem_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\main_sdblock2mem_converter_source_payload_data[63:0] [55:48] \main_sdblock2mem_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\main_sdblock2mem_converter_source_payload_data[63:0] [47:40] \main_sdblock2mem_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\main_sdblock2mem_converter_source_payload_data[63:0] [39:32] \main_sdblock2mem_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\main_sdblock2mem_converter_source_payload_data[63:0] [31:24] \main_sdblock2mem_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 3'101 + assign $0\main_sdblock2mem_converter_source_payload_data[63:0] [23:16] \main_sdblock2mem_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 3'110 + assign $0\main_sdblock2mem_converter_source_payload_data[63:0] [15:8] \main_sdblock2mem_converter_sink_payload_data + attribute \src "ls180.v:0.0-0.0" + case 3'111 + assign $0\main_sdblock2mem_converter_source_payload_data[63:0] [7:0] \main_sdblock2mem_converter_sink_payload_data + case + end + case + end + attribute \src "ls180.v:8929.2-8931.5" + switch \main_sdblock2mem_converter_load_part + attribute \src "ls180.v:8929.6-8929.42" + case 1'1 + assign $0\main_sdblock2mem_converter_source_payload_valid_token_count[3:0] $add$ls180.v:8930$2870_Y + case + end + attribute \src "ls180.v:8933.2-8935.5" + switch \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce + attribute \src "ls180.v:8933.6-8933.76" + case 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_offset[31:0] \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value + case + end + attribute \src "ls180.v:8936.2-8939.5" + switch \main_sdblock2mem_wishbonedmawriter_reset + attribute \src "ls180.v:8936.6-8936.46" + case 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_offset[31:0] 0 + assign $0\builder_sdblock2memdma_state[1:0] 2'00 + case + end + attribute \src "ls180.v:8941.2-8943.5" + switch \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce + attribute \src "ls180.v:8941.6-8941.64" + case 1'1 + assign $0\main_sdmem2block_dma_data[63:0] \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value + case + end + attribute \src "ls180.v:8945.2-8947.5" + switch \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce + attribute \src "ls180.v:8945.6-8945.76" + case 1'1 + assign $0\main_sdmem2block_dma_offset[31:0] \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value + case + end + attribute \src "ls180.v:8948.2-8951.5" + switch \main_sdmem2block_dma_reset + attribute \src "ls180.v:8948.6-8948.32" + case 1'1 + assign $0\main_sdmem2block_dma_offset[31:0] 0 + assign $0\builder_sdmem2blockdma_resetinserter_state[1:0] 2'00 + case + end + attribute \src "ls180.v:8952.2-8958.5" + switch $and$ls180.v:8952$2871_Y + attribute \src "ls180.v:8952.6-8952.89" + case 1'1 + attribute \src "ls180.v:8953.3-8957.6" + switch \main_sdmem2block_converter_last + attribute \src "ls180.v:8953.7-8953.38" + case 1'1 + assign $0\main_sdmem2block_converter_mux[2:0] 3'000 + attribute \src "ls180.v:8955.7-8955.11" + case + assign $0\main_sdmem2block_converter_mux[2:0] $add$ls180.v:8956$2872_Y + end + case + end + attribute \src "ls180.v:8959.2-8961.5" + switch $and$ls180.v:8959$2875_Y + attribute \src "ls180.v:8959.6-8959.120" + case 1'1 + assign $0\main_sdmem2block_fifo_produce[4:0] $add$ls180.v:8960$2876_Y + case + end + attribute \src "ls180.v:8962.2-8964.5" + switch \main_sdmem2block_fifo_do_read + attribute \src "ls180.v:8962.6-8962.35" + case 1'1 + assign $0\main_sdmem2block_fifo_consume[4:0] $add$ls180.v:8963$2877_Y + case + end + attribute \src "ls180.v:8965.2-8973.5" + switch $and$ls180.v:8965$2880_Y + attribute \src "ls180.v:8965.6-8965.120" + case 1'1 + attribute \src "ls180.v:8966.3-8968.6" + switch $not$ls180.v:8966$2881_Y + attribute \src "ls180.v:8966.7-8966.39" + case 1'1 + assign $0\main_sdmem2block_fifo_level[5:0] $add$ls180.v:8967$2882_Y + case + end + attribute \src "ls180.v:8969.6-8969.10" + case + attribute \src "ls180.v:8970.3-8972.6" + switch \main_sdmem2block_fifo_do_read + attribute \src "ls180.v:8970.7-8970.36" + case 1'1 + assign $0\main_sdmem2block_fifo_level[5:0] $sub$ls180.v:8971$2883_Y + case + end + end + attribute \src "ls180.v:8975.2-8977.5" + switch \builder_libresocsim_dat_w_next_value_ce0 + attribute \src "ls180.v:8975.6-8975.46" + case 1'1 + assign $0\builder_libresocsim_dat_w[7:0] \builder_libresocsim_dat_w_next_value0 + case + end + attribute \src "ls180.v:8978.2-8980.5" + switch \builder_libresocsim_adr_next_value_ce1 + attribute \src "ls180.v:8978.6-8978.44" + case 1'1 + assign $0\builder_libresocsim_adr[13:0] \builder_libresocsim_adr_next_value1 + case + end + attribute \src "ls180.v:8981.2-8983.5" + switch \builder_libresocsim_we_next_value_ce2 + attribute \src "ls180.v:8981.6-8981.43" + case 1'1 + assign $0\builder_libresocsim_we[0:0] \builder_libresocsim_we_next_value2 + case + end + attribute \src "ls180.v:8984.2-9080.9" + switch \builder_grant + attribute \src "ls180.v:0.0-0.0" + case 3'000 + attribute \src "ls180.v:8986.4-9002.7" + switch $not$ls180.v:8986$2884_Y + attribute \src "ls180.v:8986.8-8986.29" + case 1'1 + attribute \src "ls180.v:8987.5-9001.8" + switch \builder_request [1] + attribute \src "ls180.v:8987.9-8987.27" + case 1'1 + assign $0\builder_grant[2:0] 3'001 + attribute \src "ls180.v:8989.9-8989.13" + case + attribute \src "ls180.v:8990.6-9000.9" + switch \builder_request [2] + attribute \src "ls180.v:8990.10-8990.28" + case 1'1 + assign $0\builder_grant[2:0] 3'010 + attribute \src "ls180.v:8992.10-8992.14" + case + attribute \src "ls180.v:8993.7-8999.10" + switch \builder_request [3] + attribute \src "ls180.v:8993.11-8993.29" + case 1'1 + assign $0\builder_grant[2:0] 3'011 + attribute \src "ls180.v:8995.11-8995.15" + case + attribute \src "ls180.v:8996.8-8998.11" + switch \builder_request [4] + attribute \src "ls180.v:8996.12-8996.30" + case 1'1 + assign $0\builder_grant[2:0] 3'100 + case + end + end + end + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'001 + attribute \src "ls180.v:9005.4-9021.7" + switch $not$ls180.v:9005$2885_Y + attribute \src "ls180.v:9005.8-9005.29" + case 1'1 + attribute \src "ls180.v:9006.5-9020.8" + switch \builder_request [2] + attribute \src "ls180.v:9006.9-9006.27" + case 1'1 + assign $0\builder_grant[2:0] 3'010 + attribute \src "ls180.v:9008.9-9008.13" + case + attribute \src "ls180.v:9009.6-9019.9" + switch \builder_request [3] + attribute \src "ls180.v:9009.10-9009.28" + case 1'1 + assign $0\builder_grant[2:0] 3'011 + attribute \src "ls180.v:9011.10-9011.14" + case + attribute \src "ls180.v:9012.7-9018.10" + switch \builder_request [4] + attribute \src "ls180.v:9012.11-9012.29" + case 1'1 + assign $0\builder_grant[2:0] 3'100 + attribute \src "ls180.v:9014.11-9014.15" + case + attribute \src "ls180.v:9015.8-9017.11" + switch \builder_request [0] + attribute \src "ls180.v:9015.12-9015.30" + case 1'1 + assign $0\builder_grant[2:0] 3'000 + case + end + end + end + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'010 + attribute \src "ls180.v:9024.4-9040.7" + switch $not$ls180.v:9024$2886_Y + attribute \src "ls180.v:9024.8-9024.29" + case 1'1 + attribute \src "ls180.v:9025.5-9039.8" + switch \builder_request [3] + attribute \src "ls180.v:9025.9-9025.27" + case 1'1 + assign $0\builder_grant[2:0] 3'011 + attribute \src "ls180.v:9027.9-9027.13" + case + attribute \src "ls180.v:9028.6-9038.9" + switch \builder_request [4] + attribute \src "ls180.v:9028.10-9028.28" + case 1'1 + assign $0\builder_grant[2:0] 3'100 + attribute \src "ls180.v:9030.10-9030.14" + case + attribute \src "ls180.v:9031.7-9037.10" + switch \builder_request [0] + attribute \src "ls180.v:9031.11-9031.29" + case 1'1 + assign $0\builder_grant[2:0] 3'000 + attribute \src "ls180.v:9033.11-9033.15" + case + attribute \src "ls180.v:9034.8-9036.11" + switch \builder_request [1] + attribute \src "ls180.v:9034.12-9034.30" + case 1'1 + assign $0\builder_grant[2:0] 3'001 + case + end + end + end + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'011 + attribute \src "ls180.v:9043.4-9059.7" + switch $not$ls180.v:9043$2887_Y + attribute \src "ls180.v:9043.8-9043.29" + case 1'1 + attribute \src "ls180.v:9044.5-9058.8" + switch \builder_request [4] + attribute \src "ls180.v:9044.9-9044.27" + case 1'1 + assign $0\builder_grant[2:0] 3'100 + attribute \src "ls180.v:9046.9-9046.13" + case + attribute \src "ls180.v:9047.6-9057.9" + switch \builder_request [0] + attribute \src "ls180.v:9047.10-9047.28" + case 1'1 + assign $0\builder_grant[2:0] 3'000 + attribute \src "ls180.v:9049.10-9049.14" + case + attribute \src "ls180.v:9050.7-9056.10" + switch \builder_request [1] + attribute \src "ls180.v:9050.11-9050.29" + case 1'1 + assign $0\builder_grant[2:0] 3'001 + attribute \src "ls180.v:9052.11-9052.15" + case + attribute \src "ls180.v:9053.8-9055.11" + switch \builder_request [2] + attribute \src "ls180.v:9053.12-9053.30" + case 1'1 + assign $0\builder_grant[2:0] 3'010 + case + end + end + end + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'100 + attribute \src "ls180.v:9062.4-9078.7" + switch $not$ls180.v:9062$2888_Y + attribute \src "ls180.v:9062.8-9062.29" + case 1'1 + attribute \src "ls180.v:9063.5-9077.8" + switch \builder_request [0] + attribute \src "ls180.v:9063.9-9063.27" + case 1'1 + assign $0\builder_grant[2:0] 3'000 + attribute \src "ls180.v:9065.9-9065.13" + case + attribute \src "ls180.v:9066.6-9076.9" + switch \builder_request [1] + attribute \src "ls180.v:9066.10-9066.28" + case 1'1 + assign $0\builder_grant[2:0] 3'001 + attribute \src "ls180.v:9068.10-9068.14" + case + attribute \src "ls180.v:9069.7-9075.10" + switch \builder_request [2] + attribute \src "ls180.v:9069.11-9069.29" + case 1'1 + assign $0\builder_grant[2:0] 3'010 + attribute \src "ls180.v:9071.11-9071.15" + case + attribute \src "ls180.v:9072.8-9074.11" + switch \builder_request [3] + attribute \src "ls180.v:9072.12-9072.30" + case 1'1 + assign $0\builder_grant[2:0] 3'011 + case + end + end + end + end + case + end + case + end + attribute \src "ls180.v:9082.2-9088.5" + switch \builder_wait + attribute \src "ls180.v:9082.6-9082.18" + case 1'1 + attribute \src "ls180.v:9083.3-9085.6" + switch $not$ls180.v:9083$2889_Y + attribute \src "ls180.v:9083.7-9083.22" + case 1'1 + assign $0\builder_count[19:0] $sub$ls180.v:9084$2890_Y + case + end + attribute \src "ls180.v:9086.6-9086.10" + case + assign $0\builder_count[19:0] 20'11110100001001000000 + end + attribute \src "ls180.v:9090.2-9120.5" + switch \builder_csrbank0_sel + attribute \src "ls180.v:9090.6-9090.26" + case 1'1 + attribute \src "ls180.v:9091.3-9119.10" + switch \builder_interface0_bank_bus_adr [3:0] + attribute \src "ls180.v:0.0-0.0" + case 4'0000 + assign $0\builder_interface0_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank0_reset0_w } + attribute \src "ls180.v:0.0-0.0" + case 4'0001 + assign $0\builder_interface0_bank_bus_dat_r[7:0] \builder_csrbank0_scratch3_w + attribute \src "ls180.v:0.0-0.0" + case 4'0010 + assign $0\builder_interface0_bank_bus_dat_r[7:0] \builder_csrbank0_scratch2_w + attribute \src "ls180.v:0.0-0.0" + case 4'0011 + assign $0\builder_interface0_bank_bus_dat_r[7:0] \builder_csrbank0_scratch1_w + attribute \src "ls180.v:0.0-0.0" + case 4'0100 + assign $0\builder_interface0_bank_bus_dat_r[7:0] \builder_csrbank0_scratch0_w + attribute \src "ls180.v:0.0-0.0" + case 4'0101 + assign $0\builder_interface0_bank_bus_dat_r[7:0] \builder_csrbank0_bus_errors3_w + attribute \src "ls180.v:0.0-0.0" + case 4'0110 + assign $0\builder_interface0_bank_bus_dat_r[7:0] \builder_csrbank0_bus_errors2_w + attribute \src "ls180.v:0.0-0.0" + case 4'0111 + assign $0\builder_interface0_bank_bus_dat_r[7:0] \builder_csrbank0_bus_errors1_w + attribute \src "ls180.v:0.0-0.0" + case 4'1000 + assign $0\builder_interface0_bank_bus_dat_r[7:0] \builder_csrbank0_bus_errors0_w + case + end + case + end + attribute \src "ls180.v:9121.2-9123.5" + switch \builder_csrbank0_reset0_re + attribute \src "ls180.v:9121.6-9121.32" + case 1'1 + assign $0\main_libresocsim_reset_storage[0:0] \builder_csrbank0_reset0_r + case + end + attribute \src "ls180.v:9125.2-9127.5" + switch \builder_csrbank0_scratch3_re + attribute \src "ls180.v:9125.6-9125.34" + case 1'1 + assign $0\main_libresocsim_scratch_storage[31:0] [31:24] \builder_csrbank0_scratch3_r + case + end + attribute \src "ls180.v:9128.2-9130.5" + switch \builder_csrbank0_scratch2_re + attribute \src "ls180.v:9128.6-9128.34" + case 1'1 + assign $0\main_libresocsim_scratch_storage[31:0] [23:16] \builder_csrbank0_scratch2_r + case + end + attribute \src "ls180.v:9131.2-9133.5" + switch \builder_csrbank0_scratch1_re + attribute \src "ls180.v:9131.6-9131.34" + case 1'1 + assign $0\main_libresocsim_scratch_storage[31:0] [15:8] \builder_csrbank0_scratch1_r + case + end + attribute \src "ls180.v:9134.2-9136.5" + switch \builder_csrbank0_scratch0_re + attribute \src "ls180.v:9134.6-9134.34" + case 1'1 + assign $0\main_libresocsim_scratch_storage[31:0] [7:0] \builder_csrbank0_scratch0_r + case + end + attribute \src "ls180.v:9139.2-9160.5" + switch \builder_csrbank1_sel + attribute \src "ls180.v:9139.6-9139.26" + case 1'1 + attribute \src "ls180.v:9140.3-9159.10" + switch \builder_interface1_bank_bus_adr [2:0] + attribute \src "ls180.v:0.0-0.0" + case 3'000 + assign $0\builder_interface1_bank_bus_dat_r[7:0] \builder_csrbank1_oe1_w + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\builder_interface1_bank_bus_dat_r[7:0] \builder_csrbank1_oe0_w + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\builder_interface1_bank_bus_dat_r[7:0] \builder_csrbank1_in1_w + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\builder_interface1_bank_bus_dat_r[7:0] \builder_csrbank1_in0_w + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\builder_interface1_bank_bus_dat_r[7:0] \builder_csrbank1_out1_w + attribute \src "ls180.v:0.0-0.0" + case 3'101 + assign $0\builder_interface1_bank_bus_dat_r[7:0] \builder_csrbank1_out0_w + case + end + case + end + attribute \src "ls180.v:9161.2-9163.5" + switch \builder_csrbank1_oe1_re + attribute \src "ls180.v:9161.6-9161.29" + case 1'1 + assign $0\main_gpiotristateasic1_oe_storage[15:0] [15:8] \builder_csrbank1_oe1_r + case + end + attribute \src "ls180.v:9164.2-9166.5" + switch \builder_csrbank1_oe0_re + attribute \src "ls180.v:9164.6-9164.29" + case 1'1 + assign $0\main_gpiotristateasic1_oe_storage[15:0] [7:0] \builder_csrbank1_oe0_r + case + end + attribute \src "ls180.v:9168.2-9170.5" + switch \builder_csrbank1_out1_re + attribute \src "ls180.v:9168.6-9168.30" + case 1'1 + assign $0\main_gpiotristateasic1_out_storage[15:0] [15:8] \builder_csrbank1_out1_r + case + end + attribute \src "ls180.v:9171.2-9173.5" + switch \builder_csrbank1_out0_re + attribute \src "ls180.v:9171.6-9171.30" + case 1'1 + assign $0\main_gpiotristateasic1_out_storage[15:0] [7:0] \builder_csrbank1_out0_r + case + end + attribute \src "ls180.v:9176.2-9185.5" + switch \builder_csrbank2_sel + attribute \src "ls180.v:9176.6-9176.26" + case 1'1 + attribute \src "ls180.v:9177.3-9184.10" + switch \builder_interface2_bank_bus_adr [0] + attribute \src "ls180.v:0.0-0.0" + case 1'0 + assign $0\builder_interface2_bank_bus_dat_r[7:0] { 5'00000 \builder_csrbank2_w0_w } + attribute \src "ls180.v:0.0-0.0" + case 1'1 + assign $0\builder_interface2_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank2_r_w } + case + end + case + end + attribute \src "ls180.v:9186.2-9188.5" + switch \builder_csrbank2_w0_re + attribute \src "ls180.v:9186.6-9186.28" + case 1'1 + assign $0\main_i2c_storage[2:0] \builder_csrbank2_w0_r + case + end + attribute \src "ls180.v:9191.2-9221.5" + switch \builder_csrbank3_sel + attribute \src "ls180.v:9191.6-9191.26" + case 1'1 + attribute \src "ls180.v:9192.3-9220.10" + switch \builder_interface3_bank_bus_adr [3:0] + attribute \src "ls180.v:0.0-0.0" + case 4'0000 + assign $0\builder_interface3_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank3_enable0_w } + attribute \src "ls180.v:0.0-0.0" + case 4'0001 + assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_width3_w + attribute \src "ls180.v:0.0-0.0" + case 4'0010 + assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_width2_w + attribute \src "ls180.v:0.0-0.0" + case 4'0011 + assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_width1_w + attribute \src "ls180.v:0.0-0.0" + case 4'0100 + assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_width0_w + attribute \src "ls180.v:0.0-0.0" + case 4'0101 + assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_period3_w + attribute \src "ls180.v:0.0-0.0" + case 4'0110 + assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_period2_w + attribute \src "ls180.v:0.0-0.0" + case 4'0111 + assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_period1_w + attribute \src "ls180.v:0.0-0.0" + case 4'1000 + assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_period0_w + case + end + case + end + attribute \src "ls180.v:9222.2-9224.5" + switch \builder_csrbank3_enable0_re + attribute \src "ls180.v:9222.6-9222.33" + case 1'1 + assign $0\main_pwm0_enable_storage[0:0] \builder_csrbank3_enable0_r + case + end + attribute \src "ls180.v:9226.2-9228.5" + switch \builder_csrbank3_width3_re + attribute \src "ls180.v:9226.6-9226.32" + case 1'1 + assign $0\main_pwm0_width_storage[31:0] [31:24] \builder_csrbank3_width3_r + case + end + attribute \src "ls180.v:9229.2-9231.5" + switch \builder_csrbank3_width2_re + attribute \src "ls180.v:9229.6-9229.32" + case 1'1 + assign $0\main_pwm0_width_storage[31:0] [23:16] \builder_csrbank3_width2_r + case + end + attribute \src "ls180.v:9232.2-9234.5" + switch \builder_csrbank3_width1_re + attribute \src "ls180.v:9232.6-9232.32" + case 1'1 + assign $0\main_pwm0_width_storage[31:0] [15:8] \builder_csrbank3_width1_r + case + end + attribute \src "ls180.v:9235.2-9237.5" + switch \builder_csrbank3_width0_re + attribute \src "ls180.v:9235.6-9235.32" + case 1'1 + assign $0\main_pwm0_width_storage[31:0] [7:0] \builder_csrbank3_width0_r + case + end + attribute \src "ls180.v:9239.2-9241.5" + switch \builder_csrbank3_period3_re + attribute \src "ls180.v:9239.6-9239.33" + case 1'1 + assign $0\main_pwm0_period_storage[31:0] [31:24] \builder_csrbank3_period3_r + case + end + attribute \src "ls180.v:9242.2-9244.5" + switch \builder_csrbank3_period2_re + attribute \src "ls180.v:9242.6-9242.33" + case 1'1 + assign $0\main_pwm0_period_storage[31:0] [23:16] \builder_csrbank3_period2_r + case + end + attribute \src "ls180.v:9245.2-9247.5" + switch \builder_csrbank3_period1_re + attribute \src "ls180.v:9245.6-9245.33" + case 1'1 + assign $0\main_pwm0_period_storage[31:0] [15:8] \builder_csrbank3_period1_r + case + end + attribute \src "ls180.v:9248.2-9250.5" + switch \builder_csrbank3_period0_re + attribute \src "ls180.v:9248.6-9248.33" + case 1'1 + assign $0\main_pwm0_period_storage[31:0] [7:0] \builder_csrbank3_period0_r + case + end + attribute \src "ls180.v:9253.2-9283.5" + switch \builder_csrbank4_sel + attribute \src "ls180.v:9253.6-9253.26" + case 1'1 + attribute \src "ls180.v:9254.3-9282.10" + switch \builder_interface4_bank_bus_adr [3:0] + attribute \src "ls180.v:0.0-0.0" + case 4'0000 + assign $0\builder_interface4_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank4_enable0_w } + attribute \src "ls180.v:0.0-0.0" + case 4'0001 + assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_width3_w + attribute \src "ls180.v:0.0-0.0" + case 4'0010 + assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_width2_w + attribute \src "ls180.v:0.0-0.0" + case 4'0011 + assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_width1_w + attribute \src "ls180.v:0.0-0.0" + case 4'0100 + assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_width0_w + attribute \src "ls180.v:0.0-0.0" + case 4'0101 + assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_period3_w + attribute \src "ls180.v:0.0-0.0" + case 4'0110 + assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_period2_w + attribute \src "ls180.v:0.0-0.0" + case 4'0111 + assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_period1_w + attribute \src "ls180.v:0.0-0.0" + case 4'1000 + assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_period0_w + case + end + case + end + attribute \src "ls180.v:9284.2-9286.5" + switch \builder_csrbank4_enable0_re + attribute \src "ls180.v:9284.6-9284.33" + case 1'1 + assign $0\main_pwm1_enable_storage[0:0] \builder_csrbank4_enable0_r + case + end + attribute \src "ls180.v:9288.2-9290.5" + switch \builder_csrbank4_width3_re + attribute \src "ls180.v:9288.6-9288.32" + case 1'1 + assign $0\main_pwm1_width_storage[31:0] [31:24] \builder_csrbank4_width3_r + case + end + attribute \src "ls180.v:9291.2-9293.5" + switch \builder_csrbank4_width2_re + attribute \src "ls180.v:9291.6-9291.32" + case 1'1 + assign $0\main_pwm1_width_storage[31:0] [23:16] \builder_csrbank4_width2_r + case + end + attribute \src "ls180.v:9294.2-9296.5" + switch \builder_csrbank4_width1_re + attribute \src "ls180.v:9294.6-9294.32" + case 1'1 + assign $0\main_pwm1_width_storage[31:0] [15:8] \builder_csrbank4_width1_r + case + end + attribute \src "ls180.v:9297.2-9299.5" + switch \builder_csrbank4_width0_re + attribute \src "ls180.v:9297.6-9297.32" + case 1'1 + assign $0\main_pwm1_width_storage[31:0] [7:0] \builder_csrbank4_width0_r + case + end + attribute \src "ls180.v:9301.2-9303.5" + switch \builder_csrbank4_period3_re + attribute \src "ls180.v:9301.6-9301.33" + case 1'1 + assign $0\main_pwm1_period_storage[31:0] [31:24] \builder_csrbank4_period3_r + case + end + attribute \src "ls180.v:9304.2-9306.5" + switch \builder_csrbank4_period2_re + attribute \src "ls180.v:9304.6-9304.33" + case 1'1 + assign $0\main_pwm1_period_storage[31:0] [23:16] \builder_csrbank4_period2_r + case + end + attribute \src "ls180.v:9307.2-9309.5" + switch \builder_csrbank4_period1_re + attribute \src "ls180.v:9307.6-9307.33" + case 1'1 + assign $0\main_pwm1_period_storage[31:0] [15:8] \builder_csrbank4_period1_r + case + end + attribute \src "ls180.v:9310.2-9312.5" + switch \builder_csrbank4_period0_re + attribute \src "ls180.v:9310.6-9310.33" + case 1'1 + assign $0\main_pwm1_period_storage[31:0] [7:0] \builder_csrbank4_period0_r + case + end + attribute \src "ls180.v:9315.2-9363.5" + switch \builder_csrbank5_sel + attribute \src "ls180.v:9315.6-9315.26" + case 1'1 + attribute \src "ls180.v:9316.3-9362.10" + switch \builder_interface5_bank_bus_adr [3:0] + attribute \src "ls180.v:0.0-0.0" + case 4'0000 + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_base7_w + attribute \src "ls180.v:0.0-0.0" + case 4'0001 + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_base6_w + attribute \src "ls180.v:0.0-0.0" + case 4'0010 + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_base5_w + attribute \src "ls180.v:0.0-0.0" + case 4'0011 + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_base4_w + attribute \src "ls180.v:0.0-0.0" + case 4'0100 + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_base3_w + attribute \src "ls180.v:0.0-0.0" + case 4'0101 + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_base2_w + attribute \src "ls180.v:0.0-0.0" + case 4'0110 + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_base1_w + attribute \src "ls180.v:0.0-0.0" + case 4'0111 + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_base0_w + attribute \src "ls180.v:0.0-0.0" + case 4'1000 + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_length3_w + attribute \src "ls180.v:0.0-0.0" + case 4'1001 + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_length2_w + attribute \src "ls180.v:0.0-0.0" + case 4'1010 + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_length1_w + attribute \src "ls180.v:0.0-0.0" + case 4'1011 + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_length0_w + attribute \src "ls180.v:0.0-0.0" + case 4'1100 + assign $0\builder_interface5_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank5_dma_enable0_w } + attribute \src "ls180.v:0.0-0.0" + case 4'1101 + assign $0\builder_interface5_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank5_dma_done_w } + attribute \src "ls180.v:0.0-0.0" + case 4'1110 + assign $0\builder_interface5_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank5_dma_loop0_w } + case + end + case + end + attribute \src "ls180.v:9364.2-9366.5" + switch \builder_csrbank5_dma_base7_re + attribute \src "ls180.v:9364.6-9364.35" + case 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [63:56] \builder_csrbank5_dma_base7_r + case + end + attribute \src "ls180.v:9367.2-9369.5" + switch \builder_csrbank5_dma_base6_re + attribute \src "ls180.v:9367.6-9367.35" + case 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [55:48] \builder_csrbank5_dma_base6_r + case + end + attribute \src "ls180.v:9370.2-9372.5" + switch \builder_csrbank5_dma_base5_re + attribute \src "ls180.v:9370.6-9370.35" + case 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [47:40] \builder_csrbank5_dma_base5_r + case + end + attribute \src "ls180.v:9373.2-9375.5" + switch \builder_csrbank5_dma_base4_re + attribute \src "ls180.v:9373.6-9373.35" + case 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [39:32] \builder_csrbank5_dma_base4_r + case + end + attribute \src "ls180.v:9376.2-9378.5" + switch \builder_csrbank5_dma_base3_re + attribute \src "ls180.v:9376.6-9376.35" + case 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [31:24] \builder_csrbank5_dma_base3_r + case + end + attribute \src "ls180.v:9379.2-9381.5" + switch \builder_csrbank5_dma_base2_re + attribute \src "ls180.v:9379.6-9379.35" + case 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [23:16] \builder_csrbank5_dma_base2_r + case + end + attribute \src "ls180.v:9382.2-9384.5" + switch \builder_csrbank5_dma_base1_re + attribute \src "ls180.v:9382.6-9382.35" + case 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [15:8] \builder_csrbank5_dma_base1_r + case + end + attribute \src "ls180.v:9385.2-9387.5" + switch \builder_csrbank5_dma_base0_re + attribute \src "ls180.v:9385.6-9385.35" + case 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [7:0] \builder_csrbank5_dma_base0_r + case + end + attribute \src "ls180.v:9389.2-9391.5" + switch \builder_csrbank5_dma_length3_re + attribute \src "ls180.v:9389.6-9389.37" + case 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] [31:24] \builder_csrbank5_dma_length3_r + case + end + attribute \src "ls180.v:9392.2-9394.5" + switch \builder_csrbank5_dma_length2_re + attribute \src "ls180.v:9392.6-9392.37" + case 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] [23:16] \builder_csrbank5_dma_length2_r + case + end + attribute \src "ls180.v:9395.2-9397.5" + switch \builder_csrbank5_dma_length1_re + attribute \src "ls180.v:9395.6-9395.37" + case 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] [15:8] \builder_csrbank5_dma_length1_r + case + end + attribute \src "ls180.v:9398.2-9400.5" + switch \builder_csrbank5_dma_length0_re + attribute \src "ls180.v:9398.6-9398.37" + case 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] [7:0] \builder_csrbank5_dma_length0_r + case + end + attribute \src "ls180.v:9402.2-9404.5" + switch \builder_csrbank5_dma_enable0_re + attribute \src "ls180.v:9402.6-9402.37" + case 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] \builder_csrbank5_dma_enable0_r + case + end + attribute \src "ls180.v:9406.2-9408.5" + switch \builder_csrbank5_dma_loop0_re + attribute \src "ls180.v:9406.6-9406.35" + case 1'1 + assign $0\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] \builder_csrbank5_dma_loop0_r + case + end + attribute \src "ls180.v:9411.2-9513.5" + switch \builder_csrbank6_sel + attribute \src "ls180.v:9411.6-9411.26" + case 1'1 + attribute \src "ls180.v:9412.3-9512.10" + switch \builder_interface6_bank_bus_adr [5:0] + attribute \src "ls180.v:0.0-0.0" + case 6'000000 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_argument3_w + attribute \src "ls180.v:0.0-0.0" + case 6'000001 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_argument2_w + attribute \src "ls180.v:0.0-0.0" + case 6'000010 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_argument1_w + attribute \src "ls180.v:0.0-0.0" + case 6'000011 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_argument0_w + attribute \src "ls180.v:0.0-0.0" + case 6'000100 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_command3_w + attribute \src "ls180.v:0.0-0.0" + case 6'000101 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_command2_w + attribute \src "ls180.v:0.0-0.0" + case 6'000110 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_command1_w + attribute \src "ls180.v:0.0-0.0" + case 6'000111 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_command0_w + attribute \src "ls180.v:0.0-0.0" + case 6'001000 + assign $0\builder_interface6_bank_bus_dat_r[7:0] { 7'0000000 \main_sdcore_cmd_send_w } + attribute \src "ls180.v:0.0-0.0" + case 6'001001 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response15_w + attribute \src "ls180.v:0.0-0.0" + case 6'001010 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response14_w + attribute \src "ls180.v:0.0-0.0" + case 6'001011 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response13_w + attribute \src "ls180.v:0.0-0.0" + case 6'001100 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response12_w + attribute \src "ls180.v:0.0-0.0" + case 6'001101 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response11_w + attribute \src "ls180.v:0.0-0.0" + case 6'001110 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response10_w + attribute \src "ls180.v:0.0-0.0" + case 6'001111 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response9_w + attribute \src "ls180.v:0.0-0.0" + case 6'010000 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response8_w + attribute \src "ls180.v:0.0-0.0" + case 6'010001 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response7_w + attribute \src "ls180.v:0.0-0.0" + case 6'010010 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response6_w + attribute \src "ls180.v:0.0-0.0" + case 6'010011 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response5_w + attribute \src "ls180.v:0.0-0.0" + case 6'010100 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response4_w + attribute \src "ls180.v:0.0-0.0" + case 6'010101 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response3_w + attribute \src "ls180.v:0.0-0.0" + case 6'010110 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response2_w + attribute \src "ls180.v:0.0-0.0" + case 6'010111 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response1_w + attribute \src "ls180.v:0.0-0.0" + case 6'011000 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response0_w + attribute \src "ls180.v:0.0-0.0" + case 6'011001 + assign $0\builder_interface6_bank_bus_dat_r[7:0] { 4'0000 \builder_csrbank6_cmd_event_w } + attribute \src "ls180.v:0.0-0.0" + case 6'011010 + assign $0\builder_interface6_bank_bus_dat_r[7:0] { 4'0000 \builder_csrbank6_data_event_w } + attribute \src "ls180.v:0.0-0.0" + case 6'011011 + assign $0\builder_interface6_bank_bus_dat_r[7:0] { 6'000000 \builder_csrbank6_block_length1_w } + attribute \src "ls180.v:0.0-0.0" + case 6'011100 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_block_length0_w + attribute \src "ls180.v:0.0-0.0" + case 6'011101 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_block_count3_w + attribute \src "ls180.v:0.0-0.0" + case 6'011110 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_block_count2_w + attribute \src "ls180.v:0.0-0.0" + case 6'011111 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_block_count1_w + attribute \src "ls180.v:0.0-0.0" + case 6'100000 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_block_count0_w + case + end + case + end + attribute \src "ls180.v:9514.2-9516.5" + switch \builder_csrbank6_cmd_argument3_re + attribute \src "ls180.v:9514.6-9514.39" + case 1'1 + assign $0\main_sdcore_cmd_argument_storage[31:0] [31:24] \builder_csrbank6_cmd_argument3_r + case + end + attribute \src "ls180.v:9517.2-9519.5" + switch \builder_csrbank6_cmd_argument2_re + attribute \src "ls180.v:9517.6-9517.39" + case 1'1 + assign $0\main_sdcore_cmd_argument_storage[31:0] [23:16] \builder_csrbank6_cmd_argument2_r + case + end + attribute \src "ls180.v:9520.2-9522.5" + switch \builder_csrbank6_cmd_argument1_re + attribute \src "ls180.v:9520.6-9520.39" + case 1'1 + assign $0\main_sdcore_cmd_argument_storage[31:0] [15:8] \builder_csrbank6_cmd_argument1_r + case + end + attribute \src "ls180.v:9523.2-9525.5" + switch \builder_csrbank6_cmd_argument0_re + attribute \src "ls180.v:9523.6-9523.39" + case 1'1 + assign $0\main_sdcore_cmd_argument_storage[31:0] [7:0] \builder_csrbank6_cmd_argument0_r + case + end + attribute \src "ls180.v:9527.2-9529.5" + switch \builder_csrbank6_cmd_command3_re + attribute \src "ls180.v:9527.6-9527.38" + case 1'1 + assign $0\main_sdcore_cmd_command_storage[31:0] [31:24] \builder_csrbank6_cmd_command3_r + case + end + attribute \src "ls180.v:9530.2-9532.5" + switch \builder_csrbank6_cmd_command2_re + attribute \src "ls180.v:9530.6-9530.38" + case 1'1 + assign $0\main_sdcore_cmd_command_storage[31:0] [23:16] \builder_csrbank6_cmd_command2_r + case + end + attribute \src "ls180.v:9533.2-9535.5" + switch \builder_csrbank6_cmd_command1_re + attribute \src "ls180.v:9533.6-9533.38" + case 1'1 + assign $0\main_sdcore_cmd_command_storage[31:0] [15:8] \builder_csrbank6_cmd_command1_r + case + end + attribute \src "ls180.v:9536.2-9538.5" + switch \builder_csrbank6_cmd_command0_re + attribute \src "ls180.v:9536.6-9536.38" + case 1'1 + assign $0\main_sdcore_cmd_command_storage[31:0] [7:0] \builder_csrbank6_cmd_command0_r + case + end + attribute \src "ls180.v:9540.2-9542.5" + switch \builder_csrbank6_block_length1_re + attribute \src "ls180.v:9540.6-9540.39" + case 1'1 + assign $0\main_sdcore_block_length_storage[9:0] [9:8] \builder_csrbank6_block_length1_r + case + end + attribute \src "ls180.v:9543.2-9545.5" + switch \builder_csrbank6_block_length0_re + attribute \src "ls180.v:9543.6-9543.39" + case 1'1 + assign $0\main_sdcore_block_length_storage[9:0] [7:0] \builder_csrbank6_block_length0_r + case + end + attribute \src "ls180.v:9547.2-9549.5" + switch \builder_csrbank6_block_count3_re + attribute \src "ls180.v:9547.6-9547.38" + case 1'1 + assign $0\main_sdcore_block_count_storage[31:0] [31:24] \builder_csrbank6_block_count3_r + case + end + attribute \src "ls180.v:9550.2-9552.5" + switch \builder_csrbank6_block_count2_re + attribute \src "ls180.v:9550.6-9550.38" + case 1'1 + assign $0\main_sdcore_block_count_storage[31:0] [23:16] \builder_csrbank6_block_count2_r + case + end + attribute \src "ls180.v:9553.2-9555.5" + switch \builder_csrbank6_block_count1_re + attribute \src "ls180.v:9553.6-9553.38" + case 1'1 + assign $0\main_sdcore_block_count_storage[31:0] [15:8] \builder_csrbank6_block_count1_r + case + end + attribute \src "ls180.v:9556.2-9558.5" + switch \builder_csrbank6_block_count0_re + attribute \src "ls180.v:9556.6-9556.38" + case 1'1 + assign $0\main_sdcore_block_count_storage[31:0] [7:0] \builder_csrbank6_block_count0_r + case + end + attribute \src "ls180.v:9561.2-9621.5" + switch \builder_csrbank7_sel + attribute \src "ls180.v:9561.6-9561.26" + case 1'1 + attribute \src "ls180.v:9562.3-9620.10" + switch \builder_interface7_bank_bus_adr [4:0] + attribute \src "ls180.v:0.0-0.0" + case 5'00000 + assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_base7_w + attribute \src "ls180.v:0.0-0.0" + case 5'00001 + assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_base6_w + attribute \src "ls180.v:0.0-0.0" + case 5'00010 + assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_base5_w + attribute \src "ls180.v:0.0-0.0" + case 5'00011 + assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_base4_w + attribute \src "ls180.v:0.0-0.0" + case 5'00100 + assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_base3_w + attribute \src "ls180.v:0.0-0.0" + case 5'00101 + assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_base2_w + attribute \src "ls180.v:0.0-0.0" + case 5'00110 + assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_base1_w + attribute \src "ls180.v:0.0-0.0" + case 5'00111 + assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_base0_w + attribute \src "ls180.v:0.0-0.0" + case 5'01000 + assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_length3_w + attribute \src "ls180.v:0.0-0.0" + case 5'01001 + assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_length2_w + attribute \src "ls180.v:0.0-0.0" + case 5'01010 + assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_length1_w + attribute \src "ls180.v:0.0-0.0" + case 5'01011 + assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_length0_w + attribute \src "ls180.v:0.0-0.0" + case 5'01100 + assign $0\builder_interface7_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank7_dma_enable0_w } + attribute \src "ls180.v:0.0-0.0" + case 5'01101 + assign $0\builder_interface7_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank7_dma_done_w } + attribute \src "ls180.v:0.0-0.0" + case 5'01110 + assign $0\builder_interface7_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank7_dma_loop0_w } + attribute \src "ls180.v:0.0-0.0" + case 5'01111 + assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_offset3_w + attribute \src "ls180.v:0.0-0.0" + case 5'10000 + assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_offset2_w + attribute \src "ls180.v:0.0-0.0" + case 5'10001 + assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_offset1_w + attribute \src "ls180.v:0.0-0.0" + case 5'10010 + assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_offset0_w + case + end + case + end + attribute \src "ls180.v:9622.2-9624.5" + switch \builder_csrbank7_dma_base7_re + attribute \src "ls180.v:9622.6-9622.35" + case 1'1 + assign $0\main_sdmem2block_dma_base_storage[63:0] [63:56] \builder_csrbank7_dma_base7_r + case + end + attribute \src "ls180.v:9625.2-9627.5" + switch \builder_csrbank7_dma_base6_re + attribute \src "ls180.v:9625.6-9625.35" + case 1'1 + assign $0\main_sdmem2block_dma_base_storage[63:0] [55:48] \builder_csrbank7_dma_base6_r + case + end + attribute \src "ls180.v:9628.2-9630.5" + switch \builder_csrbank7_dma_base5_re + attribute \src "ls180.v:9628.6-9628.35" + case 1'1 + assign $0\main_sdmem2block_dma_base_storage[63:0] [47:40] \builder_csrbank7_dma_base5_r + case + end + attribute \src "ls180.v:9631.2-9633.5" + switch \builder_csrbank7_dma_base4_re + attribute \src "ls180.v:9631.6-9631.35" + case 1'1 + assign $0\main_sdmem2block_dma_base_storage[63:0] [39:32] \builder_csrbank7_dma_base4_r + case + end + attribute \src "ls180.v:9634.2-9636.5" + switch \builder_csrbank7_dma_base3_re + attribute \src "ls180.v:9634.6-9634.35" + case 1'1 + assign $0\main_sdmem2block_dma_base_storage[63:0] [31:24] \builder_csrbank7_dma_base3_r + case + end + attribute \src "ls180.v:9637.2-9639.5" + switch \builder_csrbank7_dma_base2_re + attribute \src "ls180.v:9637.6-9637.35" + case 1'1 + assign $0\main_sdmem2block_dma_base_storage[63:0] [23:16] \builder_csrbank7_dma_base2_r + case + end + attribute \src "ls180.v:9640.2-9642.5" + switch \builder_csrbank7_dma_base1_re + attribute \src "ls180.v:9640.6-9640.35" + case 1'1 + assign $0\main_sdmem2block_dma_base_storage[63:0] [15:8] \builder_csrbank7_dma_base1_r + case + end + attribute \src "ls180.v:9643.2-9645.5" + switch \builder_csrbank7_dma_base0_re + attribute \src "ls180.v:9643.6-9643.35" + case 1'1 + assign $0\main_sdmem2block_dma_base_storage[63:0] [7:0] \builder_csrbank7_dma_base0_r + case + end + attribute \src "ls180.v:9647.2-9649.5" + switch \builder_csrbank7_dma_length3_re + attribute \src "ls180.v:9647.6-9647.37" + case 1'1 + assign $0\main_sdmem2block_dma_length_storage[31:0] [31:24] \builder_csrbank7_dma_length3_r + case + end + attribute \src "ls180.v:9650.2-9652.5" + switch \builder_csrbank7_dma_length2_re + attribute \src "ls180.v:9650.6-9650.37" + case 1'1 + assign $0\main_sdmem2block_dma_length_storage[31:0] [23:16] \builder_csrbank7_dma_length2_r + case + end + attribute \src "ls180.v:9653.2-9655.5" + switch \builder_csrbank7_dma_length1_re + attribute \src "ls180.v:9653.6-9653.37" + case 1'1 + assign $0\main_sdmem2block_dma_length_storage[31:0] [15:8] \builder_csrbank7_dma_length1_r + case + end + attribute \src "ls180.v:9656.2-9658.5" + switch \builder_csrbank7_dma_length0_re + attribute \src "ls180.v:9656.6-9656.37" + case 1'1 + assign $0\main_sdmem2block_dma_length_storage[31:0] [7:0] \builder_csrbank7_dma_length0_r + case + end + attribute \src "ls180.v:9660.2-9662.5" + switch \builder_csrbank7_dma_enable0_re + attribute \src "ls180.v:9660.6-9660.37" + case 1'1 + assign $0\main_sdmem2block_dma_enable_storage[0:0] \builder_csrbank7_dma_enable0_r + case + end + attribute \src "ls180.v:9664.2-9666.5" + switch \builder_csrbank7_dma_loop0_re + attribute \src "ls180.v:9664.6-9664.35" + case 1'1 + assign $0\main_sdmem2block_dma_loop_storage[0:0] \builder_csrbank7_dma_loop0_r + case + end + attribute \src "ls180.v:9669.2-9684.5" + switch \builder_csrbank8_sel + attribute \src "ls180.v:9669.6-9669.26" + case 1'1 + attribute \src "ls180.v:9670.3-9683.10" + switch \builder_interface8_bank_bus_adr [1:0] + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_interface8_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank8_card_detect_w } + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_interface8_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank8_clocker_divider1_w } + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_interface8_bank_bus_dat_r[7:0] \builder_csrbank8_clocker_divider0_w + attribute \src "ls180.v:0.0-0.0" + case 2'11 + assign $0\builder_interface8_bank_bus_dat_r[7:0] { 7'0000000 \main_sdphy_init_initialize_w } + case + end + case + end + attribute \src "ls180.v:9685.2-9687.5" + switch \builder_csrbank8_clocker_divider1_re + attribute \src "ls180.v:9685.6-9685.42" + case 1'1 + assign $0\main_sdphy_clocker_storage[8:0] [8] \builder_csrbank8_clocker_divider1_r + case + end + attribute \src "ls180.v:9688.2-9690.5" + switch \builder_csrbank8_clocker_divider0_re + attribute \src "ls180.v:9688.6-9688.42" + case 1'1 + assign $0\main_sdphy_clocker_storage[8:0] [7:0] \builder_csrbank8_clocker_divider0_r + case + end + attribute \src "ls180.v:9693.2-9726.5" + switch \builder_csrbank9_sel + attribute \src "ls180.v:9693.6-9693.26" + case 1'1 + attribute \src "ls180.v:9694.3-9725.10" + switch \builder_interface9_bank_bus_adr [3:0] + attribute \src "ls180.v:0.0-0.0" + case 4'0000 + assign $0\builder_interface9_bank_bus_dat_r[7:0] { 4'0000 \builder_csrbank9_dfii_control0_w } + attribute \src "ls180.v:0.0-0.0" + case 4'0001 + assign $0\builder_interface9_bank_bus_dat_r[7:0] { 2'00 \builder_csrbank9_dfii_pi0_command0_w } + attribute \src "ls180.v:0.0-0.0" + case 4'0010 + assign $0\builder_interface9_bank_bus_dat_r[7:0] { 7'0000000 \main_sdram_command_issue_w } + attribute \src "ls180.v:0.0-0.0" + case 4'0011 + assign $0\builder_interface9_bank_bus_dat_r[7:0] { 3'000 \builder_csrbank9_dfii_pi0_address1_w } + attribute \src "ls180.v:0.0-0.0" + case 4'0100 + assign $0\builder_interface9_bank_bus_dat_r[7:0] \builder_csrbank9_dfii_pi0_address0_w + attribute \src "ls180.v:0.0-0.0" + case 4'0101 + assign $0\builder_interface9_bank_bus_dat_r[7:0] { 6'000000 \builder_csrbank9_dfii_pi0_baddress0_w } + attribute \src "ls180.v:0.0-0.0" + case 4'0110 + assign $0\builder_interface9_bank_bus_dat_r[7:0] \builder_csrbank9_dfii_pi0_wrdata1_w + attribute \src "ls180.v:0.0-0.0" + case 4'0111 + assign $0\builder_interface9_bank_bus_dat_r[7:0] \builder_csrbank9_dfii_pi0_wrdata0_w + attribute \src "ls180.v:0.0-0.0" + case 4'1000 + assign $0\builder_interface9_bank_bus_dat_r[7:0] \builder_csrbank9_dfii_pi0_rddata1_w + attribute \src "ls180.v:0.0-0.0" + case 4'1001 + assign $0\builder_interface9_bank_bus_dat_r[7:0] \builder_csrbank9_dfii_pi0_rddata0_w + case + end + case + end + attribute \src "ls180.v:9727.2-9729.5" + switch \builder_csrbank9_dfii_control0_re + attribute \src "ls180.v:9727.6-9727.39" + case 1'1 + assign $0\main_sdram_storage[3:0] \builder_csrbank9_dfii_control0_r + case + end + attribute \src "ls180.v:9731.2-9733.5" + switch \builder_csrbank9_dfii_pi0_command0_re + attribute \src "ls180.v:9731.6-9731.43" + case 1'1 + assign $0\main_sdram_command_storage[5:0] \builder_csrbank9_dfii_pi0_command0_r + case + end + attribute \src "ls180.v:9735.2-9737.5" + switch \builder_csrbank9_dfii_pi0_address1_re + attribute \src "ls180.v:9735.6-9735.43" + case 1'1 + assign $0\main_sdram_address_storage[12:0] [12:8] \builder_csrbank9_dfii_pi0_address1_r + case + end + attribute \src "ls180.v:9738.2-9740.5" + switch \builder_csrbank9_dfii_pi0_address0_re + attribute \src "ls180.v:9738.6-9738.43" + case 1'1 + assign $0\main_sdram_address_storage[12:0] [7:0] \builder_csrbank9_dfii_pi0_address0_r + case + end + attribute \src "ls180.v:9742.2-9744.5" + switch \builder_csrbank9_dfii_pi0_baddress0_re + attribute \src "ls180.v:9742.6-9742.44" + case 1'1 + assign $0\main_sdram_baddress_storage[1:0] \builder_csrbank9_dfii_pi0_baddress0_r + case + end + attribute \src "ls180.v:9746.2-9748.5" + switch \builder_csrbank9_dfii_pi0_wrdata1_re + attribute \src "ls180.v:9746.6-9746.42" + case 1'1 + assign $0\main_sdram_wrdata_storage[15:0] [15:8] \builder_csrbank9_dfii_pi0_wrdata1_r + case + end + attribute \src "ls180.v:9749.2-9751.5" + switch \builder_csrbank9_dfii_pi0_wrdata0_re + attribute \src "ls180.v:9749.6-9749.42" + case 1'1 + assign $0\main_sdram_wrdata_storage[15:0] [7:0] \builder_csrbank9_dfii_pi0_wrdata0_r + case + end + attribute \src "ls180.v:9754.2-9778.5" + switch \builder_csrbank10_sel + attribute \src "ls180.v:9754.6-9754.27" + case 1'1 + attribute \src "ls180.v:9755.3-9777.10" + switch \builder_interface10_bank_bus_adr [2:0] + attribute \src "ls180.v:0.0-0.0" + case 3'000 + assign $0\builder_interface10_bank_bus_dat_r[7:0] \builder_csrbank10_control1_w + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\builder_interface10_bank_bus_dat_r[7:0] \builder_csrbank10_control0_w + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\builder_interface10_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank10_status_w } + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\builder_interface10_bank_bus_dat_r[7:0] \builder_csrbank10_mosi0_w + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\builder_interface10_bank_bus_dat_r[7:0] \builder_csrbank10_miso_w + attribute \src "ls180.v:0.0-0.0" + case 3'101 + assign $0\builder_interface10_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank10_cs0_w } + attribute \src "ls180.v:0.0-0.0" + case 3'110 + assign $0\builder_interface10_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank10_loopback0_w } + case + end + case + end + attribute \src "ls180.v:9779.2-9781.5" + switch \builder_csrbank10_control1_re + attribute \src "ls180.v:9779.6-9779.35" + case 1'1 + assign $0\main_spimaster11_storage[15:0] [15:8] \builder_csrbank10_control1_r + case + end + attribute \src "ls180.v:9782.2-9784.5" + switch \builder_csrbank10_control0_re + attribute \src "ls180.v:9782.6-9782.35" + case 1'1 + assign $0\main_spimaster11_storage[15:0] [7:0] \builder_csrbank10_control0_r + case + end + attribute \src "ls180.v:9786.2-9788.5" + switch \builder_csrbank10_mosi0_re + attribute \src "ls180.v:9786.6-9786.32" + case 1'1 + assign $0\main_spimaster16_storage[7:0] \builder_csrbank10_mosi0_r + case + end + attribute \src "ls180.v:9790.2-9792.5" + switch \builder_csrbank10_cs0_re + attribute \src "ls180.v:9790.6-9790.30" + case 1'1 + assign $0\main_spimaster21_storage[0:0] \builder_csrbank10_cs0_r + case + end + attribute \src "ls180.v:9794.2-9796.5" + switch \builder_csrbank10_loopback0_re + attribute \src "ls180.v:9794.6-9794.36" + case 1'1 + assign $0\main_spimaster23_storage[0:0] \builder_csrbank10_loopback0_r + case + end + attribute \src "ls180.v:9799.2-9829.5" + switch \builder_csrbank11_sel + attribute \src "ls180.v:9799.6-9799.27" + case 1'1 + attribute \src "ls180.v:9800.3-9828.10" + switch \builder_interface11_bank_bus_adr [3:0] + attribute \src "ls180.v:0.0-0.0" + case 4'0000 + assign $0\builder_interface11_bank_bus_dat_r[7:0] \builder_csrbank11_control1_w + attribute \src "ls180.v:0.0-0.0" + case 4'0001 + assign $0\builder_interface11_bank_bus_dat_r[7:0] \builder_csrbank11_control0_w + attribute \src "ls180.v:0.0-0.0" + case 4'0010 + assign $0\builder_interface11_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank11_status_w } + attribute \src "ls180.v:0.0-0.0" + case 4'0011 + assign $0\builder_interface11_bank_bus_dat_r[7:0] \builder_csrbank11_mosi0_w + attribute \src "ls180.v:0.0-0.0" + case 4'0100 + assign $0\builder_interface11_bank_bus_dat_r[7:0] \builder_csrbank11_miso_w + attribute \src "ls180.v:0.0-0.0" + case 4'0101 + assign $0\builder_interface11_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank11_cs0_w } + attribute \src "ls180.v:0.0-0.0" + case 4'0110 + assign $0\builder_interface11_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank11_loopback0_w } + attribute \src "ls180.v:0.0-0.0" + case 4'0111 + assign $0\builder_interface11_bank_bus_dat_r[7:0] \builder_csrbank11_clk_divider1_w + attribute \src "ls180.v:0.0-0.0" + case 4'1000 + assign $0\builder_interface11_bank_bus_dat_r[7:0] \builder_csrbank11_clk_divider0_w + case + end + case + end + attribute \src "ls180.v:9830.2-9832.5" + switch \builder_csrbank11_control1_re + attribute \src "ls180.v:9830.6-9830.35" + case 1'1 + assign $0\main_spisdcard_control_storage[15:0] [15:8] \builder_csrbank11_control1_r + case + end + attribute \src "ls180.v:9833.2-9835.5" + switch \builder_csrbank11_control0_re + attribute \src "ls180.v:9833.6-9833.35" + case 1'1 + assign $0\main_spisdcard_control_storage[15:0] [7:0] \builder_csrbank11_control0_r + case + end + attribute \src "ls180.v:9837.2-9839.5" + switch \builder_csrbank11_mosi0_re + attribute \src "ls180.v:9837.6-9837.32" + case 1'1 + assign $0\main_spisdcard_mosi_storage[7:0] \builder_csrbank11_mosi0_r + case + end + attribute \src "ls180.v:9841.2-9843.5" + switch \builder_csrbank11_cs0_re + attribute \src "ls180.v:9841.6-9841.30" + case 1'1 + assign $0\main_spisdcard_cs_storage[0:0] \builder_csrbank11_cs0_r + case + end + attribute \src "ls180.v:9845.2-9847.5" + switch \builder_csrbank11_loopback0_re + attribute \src "ls180.v:9845.6-9845.36" + case 1'1 + assign $0\main_spisdcard_loopback_storage[0:0] \builder_csrbank11_loopback0_r + case + end + attribute \src "ls180.v:9849.2-9851.5" + switch \builder_csrbank11_clk_divider1_re + attribute \src "ls180.v:9849.6-9849.39" + case 1'1 + assign $0\main_spimaster1_storage[15:0] [15:8] \builder_csrbank11_clk_divider1_r + case + end + attribute \src "ls180.v:9852.2-9854.5" + switch \builder_csrbank11_clk_divider0_re + attribute \src "ls180.v:9852.6-9852.39" + case 1'1 + assign $0\main_spimaster1_storage[15:0] [7:0] \builder_csrbank11_clk_divider0_r + case + end + attribute \src "ls180.v:9857.2-9911.5" + switch \builder_csrbank12_sel + attribute \src "ls180.v:9857.6-9857.27" + case 1'1 + attribute \src "ls180.v:9858.3-9910.10" + switch \builder_interface12_bank_bus_adr [4:0] + attribute \src "ls180.v:0.0-0.0" + case 5'00000 + assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_load3_w + attribute \src "ls180.v:0.0-0.0" + case 5'00001 + assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_load2_w + attribute \src "ls180.v:0.0-0.0" + case 5'00010 + assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_load1_w + attribute \src "ls180.v:0.0-0.0" + case 5'00011 + assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_load0_w + attribute \src "ls180.v:0.0-0.0" + case 5'00100 + assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_reload3_w + attribute \src "ls180.v:0.0-0.0" + case 5'00101 + assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_reload2_w + attribute \src "ls180.v:0.0-0.0" + case 5'00110 + assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_reload1_w + attribute \src "ls180.v:0.0-0.0" + case 5'00111 + assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_reload0_w + attribute \src "ls180.v:0.0-0.0" + case 5'01000 + assign $0\builder_interface12_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank12_en0_w } + attribute \src "ls180.v:0.0-0.0" + case 5'01001 + assign $0\builder_interface12_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank12_update_value0_w } + attribute \src "ls180.v:0.0-0.0" + case 5'01010 + assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_value3_w + attribute \src "ls180.v:0.0-0.0" + case 5'01011 + assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_value2_w + attribute \src "ls180.v:0.0-0.0" + case 5'01100 + assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_value1_w + attribute \src "ls180.v:0.0-0.0" + case 5'01101 + assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_value0_w + attribute \src "ls180.v:0.0-0.0" + case 5'01110 + assign $0\builder_interface12_bank_bus_dat_r[7:0] { 7'0000000 \main_libresocsim_eventmanager_status_w } + attribute \src "ls180.v:0.0-0.0" + case 5'01111 + assign $0\builder_interface12_bank_bus_dat_r[7:0] { 7'0000000 \main_libresocsim_eventmanager_pending_w } + attribute \src "ls180.v:0.0-0.0" + case 5'10000 + assign $0\builder_interface12_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank12_ev_enable0_w } + case + end + case + end + attribute \src "ls180.v:9912.2-9914.5" + switch \builder_csrbank12_load3_re + attribute \src "ls180.v:9912.6-9912.32" + case 1'1 + assign $0\main_libresocsim_load_storage[31:0] [31:24] \builder_csrbank12_load3_r + case + end + attribute \src "ls180.v:9915.2-9917.5" + switch \builder_csrbank12_load2_re + attribute \src "ls180.v:9915.6-9915.32" + case 1'1 + assign $0\main_libresocsim_load_storage[31:0] [23:16] \builder_csrbank12_load2_r + case + end + attribute \src "ls180.v:9918.2-9920.5" + switch \builder_csrbank12_load1_re + attribute \src "ls180.v:9918.6-9918.32" + case 1'1 + assign $0\main_libresocsim_load_storage[31:0] [15:8] \builder_csrbank12_load1_r + case + end + attribute \src "ls180.v:9921.2-9923.5" + switch \builder_csrbank12_load0_re + attribute \src "ls180.v:9921.6-9921.32" + case 1'1 + assign $0\main_libresocsim_load_storage[31:0] [7:0] \builder_csrbank12_load0_r + case + end + attribute \src "ls180.v:9925.2-9927.5" + switch \builder_csrbank12_reload3_re + attribute \src "ls180.v:9925.6-9925.34" + case 1'1 + assign $0\main_libresocsim_reload_storage[31:0] [31:24] \builder_csrbank12_reload3_r + case + end + attribute \src "ls180.v:9928.2-9930.5" + switch \builder_csrbank12_reload2_re + attribute \src "ls180.v:9928.6-9928.34" + case 1'1 + assign $0\main_libresocsim_reload_storage[31:0] [23:16] \builder_csrbank12_reload2_r + case + end + attribute \src "ls180.v:9931.2-9933.5" + switch \builder_csrbank12_reload1_re + attribute \src "ls180.v:9931.6-9931.34" + case 1'1 + assign $0\main_libresocsim_reload_storage[31:0] [15:8] \builder_csrbank12_reload1_r + case + end + attribute \src "ls180.v:9934.2-9936.5" + switch \builder_csrbank12_reload0_re + attribute \src "ls180.v:9934.6-9934.34" + case 1'1 + assign $0\main_libresocsim_reload_storage[31:0] [7:0] \builder_csrbank12_reload0_r + case + end + attribute \src "ls180.v:9938.2-9940.5" + switch \builder_csrbank12_en0_re + attribute \src "ls180.v:9938.6-9938.30" + case 1'1 + assign $0\main_libresocsim_en_storage[0:0] \builder_csrbank12_en0_r + case + end + attribute \src "ls180.v:9942.2-9944.5" + switch \builder_csrbank12_update_value0_re + attribute \src "ls180.v:9942.6-9942.40" + case 1'1 + assign $0\main_libresocsim_update_value_storage[0:0] \builder_csrbank12_update_value0_r + case + end + attribute \src "ls180.v:9946.2-9948.5" + switch \builder_csrbank12_ev_enable0_re + attribute \src "ls180.v:9946.6-9946.37" + case 1'1 + assign $0\main_libresocsim_eventmanager_storage[0:0] \builder_csrbank12_ev_enable0_r + case + end + attribute \src "ls180.v:9951.2-9978.5" + switch \builder_csrbank13_sel + attribute \src "ls180.v:9951.6-9951.27" + case 1'1 + attribute \src "ls180.v:9952.3-9977.10" + switch \builder_interface13_bank_bus_adr [2:0] + attribute \src "ls180.v:0.0-0.0" + case 3'000 + assign $0\builder_interface13_bank_bus_dat_r[7:0] \main_uart_rxtx_w + attribute \src "ls180.v:0.0-0.0" + case 3'001 + assign $0\builder_interface13_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank13_txfull_w } + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\builder_interface13_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank13_rxempty_w } + attribute \src "ls180.v:0.0-0.0" + case 3'011 + assign $0\builder_interface13_bank_bus_dat_r[7:0] { 6'000000 \main_uart_eventmanager_status_w } + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\builder_interface13_bank_bus_dat_r[7:0] { 6'000000 \main_uart_eventmanager_pending_w } + attribute \src "ls180.v:0.0-0.0" + case 3'101 + assign $0\builder_interface13_bank_bus_dat_r[7:0] { 6'000000 \builder_csrbank13_ev_enable0_w } + attribute \src "ls180.v:0.0-0.0" + case 3'110 + assign $0\builder_interface13_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank13_txempty_w } + attribute \src "ls180.v:0.0-0.0" + case 3'111 + assign $0\builder_interface13_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank13_rxfull_w } + case + end + case + end + attribute \src "ls180.v:9979.2-9981.5" + switch \builder_csrbank13_ev_enable0_re + attribute \src "ls180.v:9979.6-9979.37" + case 1'1 + assign $0\main_uart_eventmanager_storage[1:0] \builder_csrbank13_ev_enable0_r + case + end + attribute \src "ls180.v:9984.2-9999.5" + switch \builder_csrbank14_sel + attribute \src "ls180.v:9984.6-9984.27" + case 1'1 + attribute \src "ls180.v:9985.3-9998.10" + switch \builder_interface14_bank_bus_adr [1:0] + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_interface14_bank_bus_dat_r[7:0] \builder_csrbank14_tuning_word3_w + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_interface14_bank_bus_dat_r[7:0] \builder_csrbank14_tuning_word2_w + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_interface14_bank_bus_dat_r[7:0] \builder_csrbank14_tuning_word1_w + attribute \src "ls180.v:0.0-0.0" + case 2'11 + assign $0\builder_interface14_bank_bus_dat_r[7:0] \builder_csrbank14_tuning_word0_w + case + end + case + end + attribute \src "ls180.v:10000.2-10002.5" + switch \builder_csrbank14_tuning_word3_re + attribute \src "ls180.v:10000.6-10000.39" + case 1'1 + assign $0\main_uart_phy_storage[31:0] [31:24] \builder_csrbank14_tuning_word3_r + case + end + attribute \src "ls180.v:10003.2-10005.5" + switch \builder_csrbank14_tuning_word2_re + attribute \src "ls180.v:10003.6-10003.39" + case 1'1 + assign $0\main_uart_phy_storage[31:0] [23:16] \builder_csrbank14_tuning_word2_r + case + end + attribute \src "ls180.v:10006.2-10008.5" + switch \builder_csrbank14_tuning_word1_re + attribute \src "ls180.v:10006.6-10006.39" + case 1'1 + assign $0\main_uart_phy_storage[31:0] [15:8] \builder_csrbank14_tuning_word1_r + case + end + attribute \src "ls180.v:10009.2-10011.5" + switch \builder_csrbank14_tuning_word0_re + attribute \src "ls180.v:10009.6-10009.39" + case 1'1 + assign $0\main_uart_phy_storage[31:0] [7:0] \builder_csrbank14_tuning_word0_r + case + end + attribute \src "ls180.v:10013.2-10311.5" + switch \sys_rst_1 + attribute \src "ls180.v:10013.6-10013.15" + case 1'1 + assign $0\main_libresocsim_reset_storage[0:0] 1'0 + assign $0\main_libresocsim_reset_re[0:0] 1'0 + assign $0\main_libresocsim_scratch_storage[31:0] 305419896 + assign $0\main_libresocsim_scratch_re[0:0] 1'0 + assign $0\main_libresocsim_bus_errors[31:0] 0 + assign $0\pwm[1:0] 2'00 + assign $0\spisdcard_clk[0:0] 1'0 + assign $0\spisdcard_mosi[0:0] 1'0 + assign $0\spisdcard_cs_n[0:0] 1'0 + assign $0\uart_tx[0:0] 1'1 + assign $0\spimaster_clk[0:0] 1'0 + assign $0\spimaster_mosi[0:0] 1'0 + assign $0\spimaster_cs_n[0:0] 1'0 + assign $0\main_libresocsim_ram_bus_ack[0:0] 1'0 + assign $0\main_libresocsim_load_storage[31:0] 0 + assign $0\main_libresocsim_load_re[0:0] 1'0 + assign $0\main_libresocsim_reload_storage[31:0] 0 + assign $0\main_libresocsim_reload_re[0:0] 1'0 + assign $0\main_libresocsim_en_storage[0:0] 1'0 + assign $0\main_libresocsim_en_re[0:0] 1'0 + assign $0\main_libresocsim_update_value_storage[0:0] 1'0 + assign $0\main_libresocsim_update_value_re[0:0] 1'0 + assign $0\main_libresocsim_value_status[31:0] 0 + assign $0\main_libresocsim_zero_pending[0:0] 1'0 + assign $0\main_libresocsim_zero_old_trigger[0:0] 1'0 + assign $0\main_libresocsim_eventmanager_storage[0:0] 1'0 + assign $0\main_libresocsim_eventmanager_re[0:0] 1'0 + assign $0\main_libresocsim_value[31:0] 0 + assign $0\main_interface0_ram_bus_ack[0:0] 1'0 + assign $0\main_interface1_ram_bus_ack[0:0] 1'0 + assign $0\main_interface2_ram_bus_ack[0:0] 1'0 + assign $0\main_interface3_ram_bus_ack[0:0] 1'0 + assign $0\main_converter0_counter[0:0] 1'0 + assign $0\main_converter1_counter[0:0] 1'0 + assign $0\main_dfi_p0_rddata_valid[0:0] 1'0 + assign $0\main_rddata_en[2:0] 3'000 + assign $0\main_sdram_storage[3:0] 4'0001 + assign $0\main_sdram_re[0:0] 1'0 + assign $0\main_sdram_command_storage[5:0] 6'000000 + assign $0\main_sdram_command_re[0:0] 1'0 + assign $0\main_sdram_address_re[0:0] 1'0 + assign $0\main_sdram_baddress_re[0:0] 1'0 + assign $0\main_sdram_wrdata_re[0:0] 1'0 + assign $0\main_sdram_status[15:0] 16'0000000000000000 + assign $0\main_sdram_dfi_p0_address[12:0] 13'0000000000000 + assign $0\main_sdram_dfi_p0_bank[1:0] 2'00 + assign $0\main_sdram_dfi_p0_cas_n[0:0] 1'1 + assign $0\main_sdram_dfi_p0_cs_n[0:0] 1'1 + assign $0\main_sdram_dfi_p0_ras_n[0:0] 1'1 + assign $0\main_sdram_dfi_p0_we_n[0:0] 1'1 + assign $0\main_sdram_dfi_p0_wrdata_en[0:0] 1'0 + assign $0\main_sdram_dfi_p0_rddata_en[0:0] 1'0 + assign $0\main_sdram_timer_count1[9:0] 10'1100001101 + assign $0\main_sdram_postponer_req_o[0:0] 1'0 + assign $0\main_sdram_postponer_count[0:0] 1'0 + assign $0\main_sdram_sequencer_done1[0:0] 1'0 + assign $0\main_sdram_sequencer_counter[3:0] 4'0000 + assign $0\main_sdram_sequencer_count[0:0] 1'0 + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] 4'0000 + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] 3'000 + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] 3'000 + assign $0\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] 1'0 + assign $0\main_sdram_bankmachine0_row[12:0] 13'0000000000000 + assign $0\main_sdram_bankmachine0_row_opened[0:0] 1'0 + assign $0\main_sdram_bankmachine0_twtpcon_ready[0:0] 1'0 + assign $0\main_sdram_bankmachine0_twtpcon_count[2:0] 3'000 + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] 4'0000 + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] 3'000 + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] 3'000 + assign $0\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] 1'0 + assign $0\main_sdram_bankmachine1_row[12:0] 13'0000000000000 + assign $0\main_sdram_bankmachine1_row_opened[0:0] 1'0 + assign $0\main_sdram_bankmachine1_twtpcon_ready[0:0] 1'0 + assign $0\main_sdram_bankmachine1_twtpcon_count[2:0] 3'000 + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] 4'0000 + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] 3'000 + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] 3'000 + assign $0\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] 1'0 + assign $0\main_sdram_bankmachine2_row[12:0] 13'0000000000000 + assign $0\main_sdram_bankmachine2_row_opened[0:0] 1'0 + assign $0\main_sdram_bankmachine2_twtpcon_ready[0:0] 1'0 + assign $0\main_sdram_bankmachine2_twtpcon_count[2:0] 3'000 + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] 4'0000 + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] 3'000 + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] 3'000 + assign $0\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] 1'0 + assign $0\main_sdram_bankmachine3_row[12:0] 13'0000000000000 + assign $0\main_sdram_bankmachine3_row_opened[0:0] 1'0 + assign $0\main_sdram_bankmachine3_twtpcon_ready[0:0] 1'0 + assign $0\main_sdram_bankmachine3_twtpcon_count[2:0] 3'000 + assign $0\main_sdram_choose_cmd_grant[1:0] 2'00 + assign $0\main_sdram_choose_req_grant[1:0] 2'00 + assign $0\main_sdram_tccdcon_ready[0:0] 1'0 + assign $0\main_sdram_tccdcon_count[0:0] 1'0 + assign $0\main_sdram_twtrcon_ready[0:0] 1'0 + assign $0\main_sdram_twtrcon_count[2:0] 3'000 + assign $0\main_sdram_time0[4:0] 5'00000 + assign $0\main_sdram_time1[3:0] 4'0000 + assign $0\main_socbushandler_counter[0:0] 1'0 + assign $0\main_converter_counter[0:0] 1'0 + assign $0\main_cmd_consumed[0:0] 1'0 + assign $0\main_wdata_consumed[0:0] 1'0 + assign $0\main_uart_phy_storage[31:0] 9895604 + assign $0\main_uart_phy_re[0:0] 1'0 + assign $0\main_uart_phy_sink_ready[0:0] 1'0 + assign $0\main_uart_phy_uart_clk_txen[0:0] 1'0 + assign $0\main_uart_phy_tx_busy[0:0] 1'0 + assign $0\main_uart_phy_source_valid[0:0] 1'0 + assign $0\main_uart_phy_uart_clk_rxen[0:0] 1'0 + assign $0\main_uart_phy_rx_r[0:0] 1'0 + assign $0\main_uart_phy_rx_busy[0:0] 1'0 + assign $0\main_uart_tx_pending[0:0] 1'0 + assign $0\main_uart_tx_old_trigger[0:0] 1'0 + assign $0\main_uart_rx_pending[0:0] 1'0 + assign $0\main_uart_rx_old_trigger[0:0] 1'0 + assign $0\main_uart_eventmanager_storage[1:0] 2'00 + assign $0\main_uart_eventmanager_re[0:0] 1'0 + assign $0\main_uart_tx_fifo_readable[0:0] 1'0 + assign $0\main_uart_tx_fifo_level0[4:0] 5'00000 + assign $0\main_uart_tx_fifo_produce[3:0] 4'0000 + assign $0\main_uart_tx_fifo_consume[3:0] 4'0000 + assign $0\main_uart_rx_fifo_readable[0:0] 1'0 + assign $0\main_uart_rx_fifo_level0[4:0] 5'00000 + assign $0\main_uart_rx_fifo_produce[3:0] 4'0000 + assign $0\main_uart_rx_fifo_consume[3:0] 4'0000 + assign $0\main_gpiotristateasic1_oe_storage[15:0] 16'0000000000000000 + assign $0\main_gpiotristateasic1_oe_re[0:0] 1'0 + assign $0\main_gpiotristateasic1_out_storage[15:0] 16'0000000000000000 + assign $0\main_gpiotristateasic1_out_re[0:0] 1'0 + assign $0\main_spimaster5_miso[7:0] 8'00000000 + assign $0\main_spimaster11_storage[15:0] 16'0000000000000000 + assign $0\main_spimaster12_re[0:0] 1'0 + assign $0\main_spimaster17_re[0:0] 1'0 + assign $0\main_spimaster21_storage[0:0] 1'1 + assign $0\main_spimaster22_re[0:0] 1'0 + assign $0\main_spimaster23_storage[0:0] 1'0 + assign $0\main_spimaster24_re[0:0] 1'0 + assign $0\main_spimaster27_count[2:0] 3'000 + assign $0\main_spimaster30_clk_divider[15:0] 16'0000000000000000 + assign $0\main_spimaster33_mosi_data[7:0] 8'00000000 + assign $0\main_spimaster34_mosi_sel[2:0] 3'000 + assign $0\main_spimaster35_miso_data[7:0] 8'00000000 + assign $0\main_spisdcard_miso[7:0] 8'00000000 + assign $0\main_spisdcard_control_storage[15:0] 16'0000000000000000 + assign $0\main_spisdcard_control_re[0:0] 1'0 + assign $0\main_spisdcard_mosi_re[0:0] 1'0 + assign $0\main_spisdcard_cs_storage[0:0] 1'1 + assign $0\main_spisdcard_cs_re[0:0] 1'0 + assign $0\main_spisdcard_loopback_storage[0:0] 1'0 + assign $0\main_spisdcard_loopback_re[0:0] 1'0 + assign $0\main_spisdcard_count[2:0] 3'000 + assign $0\main_spisdcard_clk_divider1[15:0] 16'0000000000000000 + assign $0\main_spisdcard_mosi_data[7:0] 8'00000000 + assign $0\main_spisdcard_mosi_sel[2:0] 3'000 + assign $0\main_spisdcard_miso_data[7:0] 8'00000000 + assign $0\main_spimaster1_storage[15:0] 16'0000000001111101 + assign $0\main_spimaster1_re[0:0] 1'0 + assign $0\main_dummy[23:0] 24'000000000000000000000000 + assign $0\main_pwm0_enable_storage[0:0] 1'0 + assign $0\main_pwm0_enable_re[0:0] 1'0 + assign $0\main_pwm0_width_re[0:0] 1'0 + assign $0\main_pwm0_period_re[0:0] 1'0 + assign $0\main_pwm1_enable_storage[0:0] 1'0 + assign $0\main_pwm1_enable_re[0:0] 1'0 + assign $0\main_pwm1_width_re[0:0] 1'0 + assign $0\main_pwm1_period_re[0:0] 1'0 + assign $0\main_i2c_storage[2:0] 3'000 + assign $0\main_i2c_re[0:0] 1'0 + assign $0\main_sdphy_clocker_storage[8:0] 9'100000000 + assign $0\main_sdphy_clocker_re[0:0] 1'0 + assign $0\main_sdphy_clocker_clk0[0:0] 1'0 + assign $0\main_sdphy_clocker_clks[8:0] 9'000000000 + assign $0\main_sdphy_clocker_clk_d[0:0] 1'0 + assign $0\main_sdphy_init_count[7:0] 8'00000000 + assign $0\main_sdphy_cmdw_count[7:0] 8'00000000 + assign $0\main_sdphy_cmdr_timeout[31:0] 500000 + assign $0\main_sdphy_cmdr_count[7:0] 8'00000000 + assign $0\main_sdphy_cmdr_cmdr_run[0:0] 1'0 + assign $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] 3'000 + assign $0\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] 1'0 + assign $0\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] 1'0 + assign $0\main_sdphy_cmdr_cmdr_reset[0:0] 1'0 + assign $0\main_sdphy_dataw_count[7:0] 8'00000000 + assign $0\main_sdphy_dataw_crcr_run[0:0] 1'0 + assign $0\main_sdphy_dataw_crcr_converter_demux[2:0] 3'000 + assign $0\main_sdphy_dataw_crcr_converter_strobe_all[0:0] 1'0 + assign $0\main_sdphy_dataw_crcr_buf_source_valid[0:0] 1'0 + assign $0\main_sdphy_dataw_crcr_reset[0:0] 1'0 + assign $0\main_sdphy_datar_timeout[31:0] 500000 + assign $0\main_sdphy_datar_count[9:0] 10'0000000000 + assign $0\main_sdphy_datar_datar_run[0:0] 1'0 + assign $0\main_sdphy_datar_datar_converter_demux[0:0] 1'0 + assign $0\main_sdphy_datar_datar_converter_strobe_all[0:0] 1'0 + assign $0\main_sdphy_datar_datar_buf_source_valid[0:0] 1'0 + assign $0\main_sdphy_datar_datar_reset[0:0] 1'0 + assign $0\main_sdcore_cmd_argument_storage[31:0] 0 + assign $0\main_sdcore_cmd_argument_re[0:0] 1'0 + assign $0\main_sdcore_cmd_command_storage[31:0] 0 + assign $0\main_sdcore_cmd_command_re[0:0] 1'0 + assign $0\main_sdcore_cmd_response_status[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign $0\main_sdcore_block_length_storage[9:0] 10'0000000000 + assign $0\main_sdcore_block_length_re[0:0] 1'0 + assign $0\main_sdcore_block_count_storage[31:0] 0 + assign $0\main_sdcore_block_count_re[0:0] 1'0 + assign $0\main_sdcore_crc7_inserter_crcreg0[6:0] 7'0000000 + assign $0\main_sdcore_crc16_inserter_cnt[2:0] 3'000 + assign $0\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_inserter_crctmp0[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_inserter_crctmp1[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_inserter_crctmp2[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_inserter_crctmp3[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_checker_val[7:0] 8'00000000 + assign $0\main_sdcore_crc16_checker_cnt[3:0] 4'0000 + assign $0\main_sdcore_crc16_checker_crc0_crcreg0[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_checker_crc1_crcreg0[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_checker_crc2_crcreg0[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_checker_crc3_crcreg0[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_checker_crctmp0[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_checker_crctmp1[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_checker_crctmp2[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_checker_crctmp3[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_checker_fifo0[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_checker_fifo1[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_checker_fifo2[15:0] 16'0000000000000000 + assign $0\main_sdcore_crc16_checker_fifo3[15:0] 16'0000000000000000 + assign $0\main_sdcore_cmd_count[2:0] 3'000 + assign $0\main_sdcore_cmd_done[0:0] 1'0 + assign $0\main_sdcore_cmd_error[0:0] 1'0 + assign $0\main_sdcore_cmd_timeout[0:0] 1'0 + assign $0\main_sdcore_data_count[31:0] 0 + assign $0\main_sdcore_data_done[0:0] 1'0 + assign $0\main_sdcore_data_error[0:0] 1'0 + assign $0\main_sdcore_data_timeout[0:0] 1'0 + assign $0\main_sdblock2mem_fifo_level[5:0] 6'000000 + assign $0\main_sdblock2mem_fifo_produce[4:0] 5'00000 + assign $0\main_sdblock2mem_fifo_consume[4:0] 5'00000 + assign $0\main_sdblock2mem_converter_demux[2:0] 3'000 + assign $0\main_sdblock2mem_converter_strobe_all[0:0] 1'0 + assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\main_sdblock2mem_wishbonedmawriter_base_re[0:0] 1'0 + assign $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] 0 + assign $0\main_sdblock2mem_wishbonedmawriter_length_re[0:0] 1'0 + assign $0\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] 1'0 + assign $0\main_sdblock2mem_wishbonedmawriter_enable_re[0:0] 1'0 + assign $0\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] 1'0 + assign $0\main_sdblock2mem_wishbonedmawriter_loop_re[0:0] 1'0 + assign $0\main_sdblock2mem_wishbonedmawriter_offset[31:0] 0 + assign $0\main_sdmem2block_dma_data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\main_sdmem2block_dma_base_storage[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\main_sdmem2block_dma_base_re[0:0] 1'0 + assign $0\main_sdmem2block_dma_length_storage[31:0] 0 + assign $0\main_sdmem2block_dma_length_re[0:0] 1'0 + assign $0\main_sdmem2block_dma_enable_storage[0:0] 1'0 + assign $0\main_sdmem2block_dma_enable_re[0:0] 1'0 + assign $0\main_sdmem2block_dma_loop_storage[0:0] 1'0 + assign $0\main_sdmem2block_dma_loop_re[0:0] 1'0 + assign $0\main_sdmem2block_dma_offset[31:0] 0 + assign $0\main_sdmem2block_converter_mux[2:0] 3'000 + assign $0\main_sdmem2block_fifo_level[5:0] 6'000000 + assign $0\main_sdmem2block_fifo_produce[4:0] 5'00000 + assign $0\main_sdmem2block_fifo_consume[4:0] 5'00000 + assign $0\builder_converter0_state[0:0] 1'0 + assign $0\builder_converter1_state[0:0] 1'0 + assign $0\builder_converter2_state[0:0] 1'0 + assign $0\builder_refresher_state[1:0] 2'00 + assign $0\builder_bankmachine0_state[2:0] 3'000 + assign $0\builder_bankmachine1_state[2:0] 3'000 + assign $0\builder_bankmachine2_state[2:0] 3'000 + assign $0\builder_bankmachine3_state[2:0] 3'000 + assign $0\builder_multiplexer_state[2:0] 3'000 + assign $0\builder_new_master_wdata_ready[0:0] 1'0 + assign $0\builder_new_master_rdata_valid0[0:0] 1'0 + assign $0\builder_new_master_rdata_valid1[0:0] 1'0 + assign $0\builder_new_master_rdata_valid2[0:0] 1'0 + assign $0\builder_new_master_rdata_valid3[0:0] 1'0 + assign $0\builder_converter_state[0:0] 1'0 + assign $0\builder_spimaster0_state[1:0] 2'00 + assign $0\builder_spimaster1_state[1:0] 2'00 + assign $0\builder_sdphy_sdphyinit_state[0:0] 1'0 + assign $0\builder_sdphy_sdphycmdw_state[1:0] 2'00 + assign $0\builder_sdphy_sdphycmdr_state[2:0] 3'000 + assign $0\builder_sdphy_sdphycrcr_state[0:0] 1'0 + assign $0\builder_sdphy_fsm_state[2:0] 3'000 + assign $0\builder_sdphy_sdphydatar_state[2:0] 3'000 + assign $0\builder_sdcore_crcupstreaminserter_state[0:0] 1'0 + assign $0\builder_sdcore_fsm_state[2:0] 3'000 + assign $0\builder_sdblock2memdma_state[1:0] 2'00 + assign $0\builder_sdmem2blockdma_fsm_state[0:0] 1'0 + assign $0\builder_sdmem2blockdma_resetinserter_state[1:0] 2'00 + assign $0\builder_libresocsim_we[0:0] 1'0 + assign $0\builder_grant[2:0] 3'000 + assign $0\builder_slave_sel_r[12:0] 13'0000000000000 + assign $0\builder_count[19:0] 20'11110100001001000000 + assign $0\builder_state[1:0] 2'00 + case + end + sync posedge \sys_clk_1 + update \pwm $0\pwm[1:0] + update \spisdcard_clk $0\spisdcard_clk[0:0] + update \spisdcard_mosi $0\spisdcard_mosi[0:0] + update \spisdcard_cs_n $0\spisdcard_cs_n[0:0] + update \uart_tx $0\uart_tx[0:0] + update \spimaster_clk $0\spimaster_clk[0:0] + update \spimaster_mosi $0\spimaster_mosi[0:0] + update \spimaster_cs_n $0\spimaster_cs_n[0:0] + update \main_libresocsim_reset_storage $0\main_libresocsim_reset_storage[0:0] + update \main_libresocsim_reset_re $0\main_libresocsim_reset_re[0:0] + update \main_libresocsim_scratch_storage $0\main_libresocsim_scratch_storage[31:0] + update \main_libresocsim_scratch_re $0\main_libresocsim_scratch_re[0:0] + update \main_libresocsim_bus_errors $0\main_libresocsim_bus_errors[31:0] + update \main_libresocsim_ram_bus_ack $0\main_libresocsim_ram_bus_ack[0:0] + update \main_libresocsim_load_storage $0\main_libresocsim_load_storage[31:0] + update \main_libresocsim_load_re $0\main_libresocsim_load_re[0:0] + update \main_libresocsim_reload_storage $0\main_libresocsim_reload_storage[31:0] + update \main_libresocsim_reload_re $0\main_libresocsim_reload_re[0:0] + update \main_libresocsim_en_storage $0\main_libresocsim_en_storage[0:0] + update \main_libresocsim_en_re $0\main_libresocsim_en_re[0:0] + update \main_libresocsim_update_value_storage $0\main_libresocsim_update_value_storage[0:0] + update \main_libresocsim_update_value_re $0\main_libresocsim_update_value_re[0:0] + update \main_libresocsim_value_status $0\main_libresocsim_value_status[31:0] + update \main_libresocsim_zero_pending $0\main_libresocsim_zero_pending[0:0] + update \main_libresocsim_zero_old_trigger $0\main_libresocsim_zero_old_trigger[0:0] + update \main_libresocsim_eventmanager_storage $0\main_libresocsim_eventmanager_storage[0:0] + update \main_libresocsim_eventmanager_re $0\main_libresocsim_eventmanager_re[0:0] + update \main_libresocsim_value $0\main_libresocsim_value[31:0] + update \main_interface0_ram_bus_ack $0\main_interface0_ram_bus_ack[0:0] + update \main_interface1_ram_bus_ack $0\main_interface1_ram_bus_ack[0:0] + update \main_interface2_ram_bus_ack $0\main_interface2_ram_bus_ack[0:0] + update \main_interface3_ram_bus_ack $0\main_interface3_ram_bus_ack[0:0] + update \main_converter0_counter $0\main_converter0_counter[0:0] + update \main_converter0_dat_r $0\main_converter0_dat_r[63:0] + update \main_converter1_counter $0\main_converter1_counter[0:0] + update \main_converter1_dat_r $0\main_converter1_dat_r[63:0] + update \main_dfi_p0_rddata_valid $0\main_dfi_p0_rddata_valid[0:0] + update \main_rddata_en $0\main_rddata_en[2:0] + update \main_sdram_storage $0\main_sdram_storage[3:0] + update \main_sdram_re $0\main_sdram_re[0:0] + update \main_sdram_command_storage $0\main_sdram_command_storage[5:0] + update \main_sdram_command_re $0\main_sdram_command_re[0:0] + update \main_sdram_address_storage $0\main_sdram_address_storage[12:0] + update \main_sdram_address_re $0\main_sdram_address_re[0:0] + update \main_sdram_baddress_storage $0\main_sdram_baddress_storage[1:0] + update \main_sdram_baddress_re $0\main_sdram_baddress_re[0:0] + update \main_sdram_wrdata_storage $0\main_sdram_wrdata_storage[15:0] + update \main_sdram_wrdata_re $0\main_sdram_wrdata_re[0:0] + update \main_sdram_status $0\main_sdram_status[15:0] + update \main_sdram_dfi_p0_address $0\main_sdram_dfi_p0_address[12:0] + update \main_sdram_dfi_p0_bank $0\main_sdram_dfi_p0_bank[1:0] + update \main_sdram_dfi_p0_cas_n $0\main_sdram_dfi_p0_cas_n[0:0] + update \main_sdram_dfi_p0_cs_n $0\main_sdram_dfi_p0_cs_n[0:0] + update \main_sdram_dfi_p0_ras_n $0\main_sdram_dfi_p0_ras_n[0:0] + update \main_sdram_dfi_p0_we_n $0\main_sdram_dfi_p0_we_n[0:0] + update \main_sdram_dfi_p0_wrdata_en $0\main_sdram_dfi_p0_wrdata_en[0:0] + update \main_sdram_dfi_p0_rddata_en $0\main_sdram_dfi_p0_rddata_en[0:0] + update \main_sdram_cmd_payload_a $0\main_sdram_cmd_payload_a[12:0] + update \main_sdram_cmd_payload_ba $0\main_sdram_cmd_payload_ba[1:0] + update \main_sdram_cmd_payload_cas $0\main_sdram_cmd_payload_cas[0:0] + update \main_sdram_cmd_payload_ras $0\main_sdram_cmd_payload_ras[0:0] + update \main_sdram_cmd_payload_we $0\main_sdram_cmd_payload_we[0:0] + update \main_sdram_timer_count1 $0\main_sdram_timer_count1[9:0] + update \main_sdram_postponer_req_o $0\main_sdram_postponer_req_o[0:0] + update \main_sdram_postponer_count $0\main_sdram_postponer_count[0:0] + update \main_sdram_sequencer_done1 $0\main_sdram_sequencer_done1[0:0] + update \main_sdram_sequencer_counter $0\main_sdram_sequencer_counter[3:0] + update \main_sdram_sequencer_count $0\main_sdram_sequencer_count[0:0] + update \main_sdram_bankmachine0_cmd_buffer_lookahead_level $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] + update \main_sdram_bankmachine0_cmd_buffer_lookahead_produce $0\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] + update \main_sdram_bankmachine0_cmd_buffer_lookahead_consume $0\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] + update \main_sdram_bankmachine0_cmd_buffer_source_valid $0\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] + update \main_sdram_bankmachine0_cmd_buffer_source_first $0\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] + update \main_sdram_bankmachine0_cmd_buffer_source_last $0\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] + update \main_sdram_bankmachine0_cmd_buffer_source_payload_we $0\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] + update \main_sdram_bankmachine0_cmd_buffer_source_payload_addr $0\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] + update \main_sdram_bankmachine0_row $0\main_sdram_bankmachine0_row[12:0] + update \main_sdram_bankmachine0_row_opened $0\main_sdram_bankmachine0_row_opened[0:0] + update \main_sdram_bankmachine0_twtpcon_ready $0\main_sdram_bankmachine0_twtpcon_ready[0:0] + update \main_sdram_bankmachine0_twtpcon_count $0\main_sdram_bankmachine0_twtpcon_count[2:0] + update \main_sdram_bankmachine1_cmd_buffer_lookahead_level $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] + update \main_sdram_bankmachine1_cmd_buffer_lookahead_produce $0\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] + update \main_sdram_bankmachine1_cmd_buffer_lookahead_consume $0\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] + update \main_sdram_bankmachine1_cmd_buffer_source_valid $0\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] + update \main_sdram_bankmachine1_cmd_buffer_source_first $0\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] + update \main_sdram_bankmachine1_cmd_buffer_source_last $0\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] + update \main_sdram_bankmachine1_cmd_buffer_source_payload_we $0\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] + update \main_sdram_bankmachine1_cmd_buffer_source_payload_addr $0\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] + update \main_sdram_bankmachine1_row $0\main_sdram_bankmachine1_row[12:0] + update \main_sdram_bankmachine1_row_opened $0\main_sdram_bankmachine1_row_opened[0:0] + update \main_sdram_bankmachine1_twtpcon_ready $0\main_sdram_bankmachine1_twtpcon_ready[0:0] + update \main_sdram_bankmachine1_twtpcon_count $0\main_sdram_bankmachine1_twtpcon_count[2:0] + update \main_sdram_bankmachine2_cmd_buffer_lookahead_level $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] + update \main_sdram_bankmachine2_cmd_buffer_lookahead_produce $0\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] + update \main_sdram_bankmachine2_cmd_buffer_lookahead_consume $0\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] + update \main_sdram_bankmachine2_cmd_buffer_source_valid $0\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] + update \main_sdram_bankmachine2_cmd_buffer_source_first $0\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] + update \main_sdram_bankmachine2_cmd_buffer_source_last $0\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] + update \main_sdram_bankmachine2_cmd_buffer_source_payload_we $0\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] + update \main_sdram_bankmachine2_cmd_buffer_source_payload_addr $0\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] + update \main_sdram_bankmachine2_row $0\main_sdram_bankmachine2_row[12:0] + update \main_sdram_bankmachine2_row_opened $0\main_sdram_bankmachine2_row_opened[0:0] + update \main_sdram_bankmachine2_twtpcon_ready $0\main_sdram_bankmachine2_twtpcon_ready[0:0] + update \main_sdram_bankmachine2_twtpcon_count $0\main_sdram_bankmachine2_twtpcon_count[2:0] + update \main_sdram_bankmachine3_cmd_buffer_lookahead_level $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] + update \main_sdram_bankmachine3_cmd_buffer_lookahead_produce $0\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] + update \main_sdram_bankmachine3_cmd_buffer_lookahead_consume $0\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] + update \main_sdram_bankmachine3_cmd_buffer_source_valid $0\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] + update \main_sdram_bankmachine3_cmd_buffer_source_first $0\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] + update \main_sdram_bankmachine3_cmd_buffer_source_last $0\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] + update \main_sdram_bankmachine3_cmd_buffer_source_payload_we $0\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] + update \main_sdram_bankmachine3_cmd_buffer_source_payload_addr $0\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] + update \main_sdram_bankmachine3_row $0\main_sdram_bankmachine3_row[12:0] + update \main_sdram_bankmachine3_row_opened $0\main_sdram_bankmachine3_row_opened[0:0] + update \main_sdram_bankmachine3_twtpcon_ready $0\main_sdram_bankmachine3_twtpcon_ready[0:0] + update \main_sdram_bankmachine3_twtpcon_count $0\main_sdram_bankmachine3_twtpcon_count[2:0] + update \main_sdram_choose_cmd_grant $0\main_sdram_choose_cmd_grant[1:0] + update \main_sdram_choose_req_grant $0\main_sdram_choose_req_grant[1:0] + update \main_sdram_tccdcon_ready $0\main_sdram_tccdcon_ready[0:0] + update \main_sdram_tccdcon_count $0\main_sdram_tccdcon_count[0:0] + update \main_sdram_twtrcon_ready $0\main_sdram_twtrcon_ready[0:0] + update \main_sdram_twtrcon_count $0\main_sdram_twtrcon_count[2:0] + update \main_sdram_time0 $0\main_sdram_time0[4:0] + update \main_sdram_time1 $0\main_sdram_time1[3:0] + update \main_socbushandler_counter $0\main_socbushandler_counter[0:0] + update \main_socbushandler_dat_r $0\main_socbushandler_dat_r[63:0] + update \main_converter_counter $0\main_converter_counter[0:0] + update \main_converter_dat_r $0\main_converter_dat_r[31:0] + update \main_cmd_consumed $0\main_cmd_consumed[0:0] + update \main_wdata_consumed $0\main_wdata_consumed[0:0] + update \main_uart_phy_storage $0\main_uart_phy_storage[31:0] + update \main_uart_phy_re $0\main_uart_phy_re[0:0] + update \main_uart_phy_sink_ready $0\main_uart_phy_sink_ready[0:0] + update \main_uart_phy_uart_clk_txen $0\main_uart_phy_uart_clk_txen[0:0] + update \main_uart_phy_phase_accumulator_tx $0\main_uart_phy_phase_accumulator_tx[31:0] + update \main_uart_phy_tx_reg $0\main_uart_phy_tx_reg[7:0] + update \main_uart_phy_tx_bitcount $0\main_uart_phy_tx_bitcount[3:0] + update \main_uart_phy_tx_busy $0\main_uart_phy_tx_busy[0:0] + update \main_uart_phy_source_valid $0\main_uart_phy_source_valid[0:0] + update \main_uart_phy_source_payload_data $0\main_uart_phy_source_payload_data[7:0] + update \main_uart_phy_uart_clk_rxen $0\main_uart_phy_uart_clk_rxen[0:0] + update \main_uart_phy_phase_accumulator_rx $0\main_uart_phy_phase_accumulator_rx[31:0] + update \main_uart_phy_rx_r $0\main_uart_phy_rx_r[0:0] + update \main_uart_phy_rx_reg $0\main_uart_phy_rx_reg[7:0] + update \main_uart_phy_rx_bitcount $0\main_uart_phy_rx_bitcount[3:0] + update \main_uart_phy_rx_busy $0\main_uart_phy_rx_busy[0:0] + update \main_uart_tx_pending $0\main_uart_tx_pending[0:0] + update \main_uart_tx_old_trigger $0\main_uart_tx_old_trigger[0:0] + update \main_uart_rx_pending $0\main_uart_rx_pending[0:0] + update \main_uart_rx_old_trigger $0\main_uart_rx_old_trigger[0:0] + update \main_uart_eventmanager_storage $0\main_uart_eventmanager_storage[1:0] + update \main_uart_eventmanager_re $0\main_uart_eventmanager_re[0:0] + update \main_uart_tx_fifo_readable $0\main_uart_tx_fifo_readable[0:0] + update \main_uart_tx_fifo_level0 $0\main_uart_tx_fifo_level0[4:0] + update \main_uart_tx_fifo_produce $0\main_uart_tx_fifo_produce[3:0] + update \main_uart_tx_fifo_consume $0\main_uart_tx_fifo_consume[3:0] + update \main_uart_rx_fifo_readable $0\main_uart_rx_fifo_readable[0:0] + update \main_uart_rx_fifo_level0 $0\main_uart_rx_fifo_level0[4:0] + update \main_uart_rx_fifo_produce $0\main_uart_rx_fifo_produce[3:0] + update \main_uart_rx_fifo_consume $0\main_uart_rx_fifo_consume[3:0] + update \main_gpiotristateasic1_oe_storage $0\main_gpiotristateasic1_oe_storage[15:0] + update \main_gpiotristateasic1_oe_re $0\main_gpiotristateasic1_oe_re[0:0] + update \main_gpiotristateasic1_out_storage $0\main_gpiotristateasic1_out_storage[15:0] + update \main_gpiotristateasic1_out_re $0\main_gpiotristateasic1_out_re[0:0] + update \main_spimaster5_miso $0\main_spimaster5_miso[7:0] + update \main_spimaster11_storage $0\main_spimaster11_storage[15:0] + update \main_spimaster12_re $0\main_spimaster12_re[0:0] + update \main_spimaster16_storage $0\main_spimaster16_storage[7:0] + update \main_spimaster17_re $0\main_spimaster17_re[0:0] + update \main_spimaster21_storage $0\main_spimaster21_storage[0:0] + update \main_spimaster22_re $0\main_spimaster22_re[0:0] + update \main_spimaster23_storage $0\main_spimaster23_storage[0:0] + update \main_spimaster24_re $0\main_spimaster24_re[0:0] + update \main_spimaster27_count $0\main_spimaster27_count[2:0] + update \main_spimaster30_clk_divider $0\main_spimaster30_clk_divider[15:0] + update \main_spimaster33_mosi_data $0\main_spimaster33_mosi_data[7:0] + update \main_spimaster34_mosi_sel $0\main_spimaster34_mosi_sel[2:0] + update \main_spimaster35_miso_data $0\main_spimaster35_miso_data[7:0] + update \main_spisdcard_miso $0\main_spisdcard_miso[7:0] + update \main_spisdcard_control_storage $0\main_spisdcard_control_storage[15:0] + update \main_spisdcard_control_re $0\main_spisdcard_control_re[0:0] + update \main_spisdcard_mosi_storage $0\main_spisdcard_mosi_storage[7:0] + update \main_spisdcard_mosi_re $0\main_spisdcard_mosi_re[0:0] + update \main_spisdcard_cs_storage $0\main_spisdcard_cs_storage[0:0] + update \main_spisdcard_cs_re $0\main_spisdcard_cs_re[0:0] + update \main_spisdcard_loopback_storage $0\main_spisdcard_loopback_storage[0:0] + update \main_spisdcard_loopback_re $0\main_spisdcard_loopback_re[0:0] + update \main_spisdcard_count $0\main_spisdcard_count[2:0] + update \main_spisdcard_clk_divider1 $0\main_spisdcard_clk_divider1[15:0] + update \main_spisdcard_mosi_data $0\main_spisdcard_mosi_data[7:0] + update \main_spisdcard_mosi_sel $0\main_spisdcard_mosi_sel[2:0] + update \main_spisdcard_miso_data $0\main_spisdcard_miso_data[7:0] + update \main_spimaster1_storage $0\main_spimaster1_storage[15:0] + update \main_spimaster1_re $0\main_spimaster1_re[0:0] + update \main_dummy $0\main_dummy[23:0] + update \main_pwm0_counter $0\main_pwm0_counter[31:0] + update \main_pwm0_enable_storage $0\main_pwm0_enable_storage[0:0] + update \main_pwm0_enable_re $0\main_pwm0_enable_re[0:0] + update \main_pwm0_width_storage $0\main_pwm0_width_storage[31:0] + update \main_pwm0_width_re $0\main_pwm0_width_re[0:0] + update \main_pwm0_period_storage $0\main_pwm0_period_storage[31:0] + update \main_pwm0_period_re $0\main_pwm0_period_re[0:0] + update \main_pwm1_counter $0\main_pwm1_counter[31:0] + update \main_pwm1_enable_storage $0\main_pwm1_enable_storage[0:0] + update \main_pwm1_enable_re $0\main_pwm1_enable_re[0:0] + update \main_pwm1_width_storage $0\main_pwm1_width_storage[31:0] + update \main_pwm1_width_re $0\main_pwm1_width_re[0:0] + update \main_pwm1_period_storage $0\main_pwm1_period_storage[31:0] + update \main_pwm1_period_re $0\main_pwm1_period_re[0:0] + update \main_i2c_storage $0\main_i2c_storage[2:0] + update \main_i2c_re $0\main_i2c_re[0:0] + update \main_sdphy_clocker_storage $0\main_sdphy_clocker_storage[8:0] + update \main_sdphy_clocker_re $0\main_sdphy_clocker_re[0:0] + update \main_sdphy_clocker_clk0 $0\main_sdphy_clocker_clk0[0:0] + update \main_sdphy_clocker_clks $0\main_sdphy_clocker_clks[8:0] + update \main_sdphy_clocker_clk_d $0\main_sdphy_clocker_clk_d[0:0] + update \main_sdphy_init_count $0\main_sdphy_init_count[7:0] + update \main_sdphy_cmdw_count $0\main_sdphy_cmdw_count[7:0] + update \main_sdphy_cmdr_timeout $0\main_sdphy_cmdr_timeout[31:0] + update \main_sdphy_cmdr_count $0\main_sdphy_cmdr_count[7:0] + update \main_sdphy_cmdr_cmdr_run $0\main_sdphy_cmdr_cmdr_run[0:0] + update \main_sdphy_cmdr_cmdr_converter_source_first $0\main_sdphy_cmdr_cmdr_converter_source_first[0:0] + update \main_sdphy_cmdr_cmdr_converter_source_last $0\main_sdphy_cmdr_cmdr_converter_source_last[0:0] + update \main_sdphy_cmdr_cmdr_converter_source_payload_data $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] + update \main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count $0\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] + update \main_sdphy_cmdr_cmdr_converter_demux $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] + update \main_sdphy_cmdr_cmdr_converter_strobe_all $0\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] + update \main_sdphy_cmdr_cmdr_buf_source_valid $0\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] + update \main_sdphy_cmdr_cmdr_buf_source_first $0\main_sdphy_cmdr_cmdr_buf_source_first[0:0] + update \main_sdphy_cmdr_cmdr_buf_source_last $0\main_sdphy_cmdr_cmdr_buf_source_last[0:0] + update \main_sdphy_cmdr_cmdr_buf_source_payload_data $0\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0] + update \main_sdphy_cmdr_cmdr_reset $0\main_sdphy_cmdr_cmdr_reset[0:0] + update \main_sdphy_dataw_count $0\main_sdphy_dataw_count[7:0] + update \main_sdphy_dataw_crcr_run $0\main_sdphy_dataw_crcr_run[0:0] + update \main_sdphy_dataw_crcr_converter_source_first $0\main_sdphy_dataw_crcr_converter_source_first[0:0] + update \main_sdphy_dataw_crcr_converter_source_last $0\main_sdphy_dataw_crcr_converter_source_last[0:0] + update \main_sdphy_dataw_crcr_converter_source_payload_data $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] + update \main_sdphy_dataw_crcr_converter_source_payload_valid_token_count $0\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] + update \main_sdphy_dataw_crcr_converter_demux $0\main_sdphy_dataw_crcr_converter_demux[2:0] + update \main_sdphy_dataw_crcr_converter_strobe_all $0\main_sdphy_dataw_crcr_converter_strobe_all[0:0] + update \main_sdphy_dataw_crcr_buf_source_valid $0\main_sdphy_dataw_crcr_buf_source_valid[0:0] + update \main_sdphy_dataw_crcr_buf_source_first $0\main_sdphy_dataw_crcr_buf_source_first[0:0] + update \main_sdphy_dataw_crcr_buf_source_last $0\main_sdphy_dataw_crcr_buf_source_last[0:0] + update \main_sdphy_dataw_crcr_buf_source_payload_data $0\main_sdphy_dataw_crcr_buf_source_payload_data[7:0] + update \main_sdphy_dataw_crcr_reset $0\main_sdphy_dataw_crcr_reset[0:0] + update \main_sdphy_datar_timeout $0\main_sdphy_datar_timeout[31:0] + update \main_sdphy_datar_count $0\main_sdphy_datar_count[9:0] + update \main_sdphy_datar_datar_run $0\main_sdphy_datar_datar_run[0:0] + update \main_sdphy_datar_datar_converter_source_first $0\main_sdphy_datar_datar_converter_source_first[0:0] + update \main_sdphy_datar_datar_converter_source_last $0\main_sdphy_datar_datar_converter_source_last[0:0] + update \main_sdphy_datar_datar_converter_source_payload_data $0\main_sdphy_datar_datar_converter_source_payload_data[7:0] + update \main_sdphy_datar_datar_converter_source_payload_valid_token_count $0\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] + update \main_sdphy_datar_datar_converter_demux $0\main_sdphy_datar_datar_converter_demux[0:0] + update \main_sdphy_datar_datar_converter_strobe_all $0\main_sdphy_datar_datar_converter_strobe_all[0:0] + update \main_sdphy_datar_datar_buf_source_valid $0\main_sdphy_datar_datar_buf_source_valid[0:0] + update \main_sdphy_datar_datar_buf_source_first $0\main_sdphy_datar_datar_buf_source_first[0:0] + update \main_sdphy_datar_datar_buf_source_last $0\main_sdphy_datar_datar_buf_source_last[0:0] + update \main_sdphy_datar_datar_buf_source_payload_data $0\main_sdphy_datar_datar_buf_source_payload_data[7:0] + update \main_sdphy_datar_datar_reset $0\main_sdphy_datar_datar_reset[0:0] + update \main_sdcore_cmd_argument_storage $0\main_sdcore_cmd_argument_storage[31:0] + update \main_sdcore_cmd_argument_re $0\main_sdcore_cmd_argument_re[0:0] + update \main_sdcore_cmd_command_storage $0\main_sdcore_cmd_command_storage[31:0] + update \main_sdcore_cmd_command_re $0\main_sdcore_cmd_command_re[0:0] + update \main_sdcore_cmd_response_status $0\main_sdcore_cmd_response_status[127:0] + update \main_sdcore_block_length_storage $0\main_sdcore_block_length_storage[9:0] + update \main_sdcore_block_length_re $0\main_sdcore_block_length_re[0:0] + update \main_sdcore_block_count_storage $0\main_sdcore_block_count_storage[31:0] + update \main_sdcore_block_count_re $0\main_sdcore_block_count_re[0:0] + update \main_sdcore_crc7_inserter_crcreg0 $0\main_sdcore_crc7_inserter_crcreg0[6:0] + update \main_sdcore_crc16_inserter_cnt $0\main_sdcore_crc16_inserter_cnt[2:0] + update \main_sdcore_crc16_inserter_crc0_crcreg0 $0\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] + update \main_sdcore_crc16_inserter_crc1_crcreg0 $0\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] + update \main_sdcore_crc16_inserter_crc2_crcreg0 $0\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] + update \main_sdcore_crc16_inserter_crc3_crcreg0 $0\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] + update \main_sdcore_crc16_inserter_crctmp0 $0\main_sdcore_crc16_inserter_crctmp0[15:0] + update \main_sdcore_crc16_inserter_crctmp1 $0\main_sdcore_crc16_inserter_crctmp1[15:0] + update \main_sdcore_crc16_inserter_crctmp2 $0\main_sdcore_crc16_inserter_crctmp2[15:0] + update \main_sdcore_crc16_inserter_crctmp3 $0\main_sdcore_crc16_inserter_crctmp3[15:0] + update \main_sdcore_crc16_checker_val $0\main_sdcore_crc16_checker_val[7:0] + update \main_sdcore_crc16_checker_cnt $0\main_sdcore_crc16_checker_cnt[3:0] + update \main_sdcore_crc16_checker_crc0_crcreg0 $0\main_sdcore_crc16_checker_crc0_crcreg0[15:0] + update \main_sdcore_crc16_checker_crc1_crcreg0 $0\main_sdcore_crc16_checker_crc1_crcreg0[15:0] + update \main_sdcore_crc16_checker_crc2_crcreg0 $0\main_sdcore_crc16_checker_crc2_crcreg0[15:0] + update \main_sdcore_crc16_checker_crc3_crcreg0 $0\main_sdcore_crc16_checker_crc3_crcreg0[15:0] + update \main_sdcore_crc16_checker_crctmp0 $0\main_sdcore_crc16_checker_crctmp0[15:0] + update \main_sdcore_crc16_checker_crctmp1 $0\main_sdcore_crc16_checker_crctmp1[15:0] + update \main_sdcore_crc16_checker_crctmp2 $0\main_sdcore_crc16_checker_crctmp2[15:0] + update \main_sdcore_crc16_checker_crctmp3 $0\main_sdcore_crc16_checker_crctmp3[15:0] + update \main_sdcore_crc16_checker_fifo0 $0\main_sdcore_crc16_checker_fifo0[15:0] + update \main_sdcore_crc16_checker_fifo1 $0\main_sdcore_crc16_checker_fifo1[15:0] + update \main_sdcore_crc16_checker_fifo2 $0\main_sdcore_crc16_checker_fifo2[15:0] + update \main_sdcore_crc16_checker_fifo3 $0\main_sdcore_crc16_checker_fifo3[15:0] + update \main_sdcore_cmd_count $0\main_sdcore_cmd_count[2:0] + update \main_sdcore_cmd_done $0\main_sdcore_cmd_done[0:0] + update \main_sdcore_cmd_error $0\main_sdcore_cmd_error[0:0] + update \main_sdcore_cmd_timeout $0\main_sdcore_cmd_timeout[0:0] + update \main_sdcore_data_count $0\main_sdcore_data_count[31:0] + update \main_sdcore_data_done $0\main_sdcore_data_done[0:0] + update \main_sdcore_data_error $0\main_sdcore_data_error[0:0] + update \main_sdcore_data_timeout $0\main_sdcore_data_timeout[0:0] + update \main_sdblock2mem_fifo_level $0\main_sdblock2mem_fifo_level[5:0] + update \main_sdblock2mem_fifo_produce $0\main_sdblock2mem_fifo_produce[4:0] + update \main_sdblock2mem_fifo_consume $0\main_sdblock2mem_fifo_consume[4:0] + update \main_sdblock2mem_converter_source_first $0\main_sdblock2mem_converter_source_first[0:0] + update \main_sdblock2mem_converter_source_last $0\main_sdblock2mem_converter_source_last[0:0] + update \main_sdblock2mem_converter_source_payload_data $0\main_sdblock2mem_converter_source_payload_data[63:0] + update \main_sdblock2mem_converter_source_payload_valid_token_count $0\main_sdblock2mem_converter_source_payload_valid_token_count[3:0] + update \main_sdblock2mem_converter_demux $0\main_sdblock2mem_converter_demux[2:0] + update \main_sdblock2mem_converter_strobe_all $0\main_sdblock2mem_converter_strobe_all[0:0] + update \main_sdblock2mem_wishbonedmawriter_base_storage $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] + update \main_sdblock2mem_wishbonedmawriter_base_re $0\main_sdblock2mem_wishbonedmawriter_base_re[0:0] + update \main_sdblock2mem_wishbonedmawriter_length_storage $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] + update \main_sdblock2mem_wishbonedmawriter_length_re $0\main_sdblock2mem_wishbonedmawriter_length_re[0:0] + update \main_sdblock2mem_wishbonedmawriter_enable_storage $0\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] + update \main_sdblock2mem_wishbonedmawriter_enable_re $0\main_sdblock2mem_wishbonedmawriter_enable_re[0:0] + update \main_sdblock2mem_wishbonedmawriter_loop_storage $0\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] + update \main_sdblock2mem_wishbonedmawriter_loop_re $0\main_sdblock2mem_wishbonedmawriter_loop_re[0:0] + update \main_sdblock2mem_wishbonedmawriter_offset $0\main_sdblock2mem_wishbonedmawriter_offset[31:0] + update \main_sdmem2block_dma_data $0\main_sdmem2block_dma_data[63:0] + update \main_sdmem2block_dma_base_storage $0\main_sdmem2block_dma_base_storage[63:0] + update \main_sdmem2block_dma_base_re $0\main_sdmem2block_dma_base_re[0:0] + update \main_sdmem2block_dma_length_storage $0\main_sdmem2block_dma_length_storage[31:0] + update \main_sdmem2block_dma_length_re $0\main_sdmem2block_dma_length_re[0:0] + update \main_sdmem2block_dma_enable_storage $0\main_sdmem2block_dma_enable_storage[0:0] + update \main_sdmem2block_dma_enable_re $0\main_sdmem2block_dma_enable_re[0:0] + update \main_sdmem2block_dma_loop_storage $0\main_sdmem2block_dma_loop_storage[0:0] + update \main_sdmem2block_dma_loop_re $0\main_sdmem2block_dma_loop_re[0:0] + update \main_sdmem2block_dma_offset $0\main_sdmem2block_dma_offset[31:0] + update \main_sdmem2block_converter_mux $0\main_sdmem2block_converter_mux[2:0] + update \main_sdmem2block_fifo_level $0\main_sdmem2block_fifo_level[5:0] + update \main_sdmem2block_fifo_produce $0\main_sdmem2block_fifo_produce[4:0] + update \main_sdmem2block_fifo_consume $0\main_sdmem2block_fifo_consume[4:0] + update \builder_converter0_state $0\builder_converter0_state[0:0] + update \builder_converter1_state $0\builder_converter1_state[0:0] + update \builder_converter2_state $0\builder_converter2_state[0:0] + update \builder_refresher_state $0\builder_refresher_state[1:0] + update \builder_bankmachine0_state $0\builder_bankmachine0_state[2:0] + update \builder_bankmachine1_state $0\builder_bankmachine1_state[2:0] + update \builder_bankmachine2_state $0\builder_bankmachine2_state[2:0] + update \builder_bankmachine3_state $0\builder_bankmachine3_state[2:0] + update \builder_multiplexer_state $0\builder_multiplexer_state[2:0] + update \builder_new_master_wdata_ready $0\builder_new_master_wdata_ready[0:0] + update \builder_new_master_rdata_valid0 $0\builder_new_master_rdata_valid0[0:0] + update \builder_new_master_rdata_valid1 $0\builder_new_master_rdata_valid1[0:0] + update \builder_new_master_rdata_valid2 $0\builder_new_master_rdata_valid2[0:0] + update \builder_new_master_rdata_valid3 $0\builder_new_master_rdata_valid3[0:0] + update \builder_converter_state $0\builder_converter_state[0:0] + update \builder_spimaster0_state $0\builder_spimaster0_state[1:0] + update \builder_spimaster1_state $0\builder_spimaster1_state[1:0] + update \builder_sdphy_sdphyinit_state $0\builder_sdphy_sdphyinit_state[0:0] + update \builder_sdphy_sdphycmdw_state $0\builder_sdphy_sdphycmdw_state[1:0] + update \builder_sdphy_sdphycmdr_state $0\builder_sdphy_sdphycmdr_state[2:0] + update \builder_sdphy_sdphycrcr_state $0\builder_sdphy_sdphycrcr_state[0:0] + update \builder_sdphy_fsm_state $0\builder_sdphy_fsm_state[2:0] + update \builder_sdphy_sdphydatar_state $0\builder_sdphy_sdphydatar_state[2:0] + update \builder_sdcore_crcupstreaminserter_state $0\builder_sdcore_crcupstreaminserter_state[0:0] + update \builder_sdcore_fsm_state $0\builder_sdcore_fsm_state[2:0] + update \builder_sdblock2memdma_state $0\builder_sdblock2memdma_state[1:0] + update \builder_sdmem2blockdma_fsm_state $0\builder_sdmem2blockdma_fsm_state[0:0] + update \builder_sdmem2blockdma_resetinserter_state $0\builder_sdmem2blockdma_resetinserter_state[1:0] + update \builder_libresocsim_adr $0\builder_libresocsim_adr[13:0] + update \builder_libresocsim_we $0\builder_libresocsim_we[0:0] + update \builder_libresocsim_dat_w $0\builder_libresocsim_dat_w[7:0] + update \builder_grant $0\builder_grant[2:0] + update \builder_slave_sel_r $0\builder_slave_sel_r[12:0] + update \builder_count $0\builder_count[19:0] + update \builder_interface0_bank_bus_dat_r $0\builder_interface0_bank_bus_dat_r[7:0] + update \builder_interface1_bank_bus_dat_r $0\builder_interface1_bank_bus_dat_r[7:0] + update \builder_interface2_bank_bus_dat_r $0\builder_interface2_bank_bus_dat_r[7:0] + update \builder_interface3_bank_bus_dat_r $0\builder_interface3_bank_bus_dat_r[7:0] + update \builder_interface4_bank_bus_dat_r $0\builder_interface4_bank_bus_dat_r[7:0] + update \builder_interface5_bank_bus_dat_r $0\builder_interface5_bank_bus_dat_r[7:0] + update \builder_interface6_bank_bus_dat_r $0\builder_interface6_bank_bus_dat_r[7:0] + update \builder_interface7_bank_bus_dat_r $0\builder_interface7_bank_bus_dat_r[7:0] + update \builder_interface8_bank_bus_dat_r $0\builder_interface8_bank_bus_dat_r[7:0] + update \builder_interface9_bank_bus_dat_r $0\builder_interface9_bank_bus_dat_r[7:0] + update \builder_interface10_bank_bus_dat_r $0\builder_interface10_bank_bus_dat_r[7:0] + update \builder_interface11_bank_bus_dat_r $0\builder_interface11_bank_bus_dat_r[7:0] + update \builder_interface12_bank_bus_dat_r $0\builder_interface12_bank_bus_dat_r[7:0] + update \builder_interface13_bank_bus_dat_r $0\builder_interface13_bank_bus_dat_r[7:0] + update \builder_interface14_bank_bus_dat_r $0\builder_interface14_bank_bus_dat_r[7:0] + update \builder_state $0\builder_state[1:0] + update \builder_multiregimpl0_regs0 $0\builder_multiregimpl0_regs0[0:0] + update \builder_multiregimpl0_regs1 $0\builder_multiregimpl0_regs1[0:0] + update \builder_multiregimpl1_regs0 $0\builder_multiregimpl1_regs0[0:0] + update \builder_multiregimpl1_regs1 $0\builder_multiregimpl1_regs1[0:0] + update \builder_multiregimpl2_regs0 $0\builder_multiregimpl2_regs0[0:0] + update \builder_multiregimpl2_regs1 $0\builder_multiregimpl2_regs1[0:0] + update \builder_multiregimpl3_regs0 $0\builder_multiregimpl3_regs0[0:0] + update \builder_multiregimpl3_regs1 $0\builder_multiregimpl3_regs1[0:0] + update \builder_multiregimpl4_regs0 $0\builder_multiregimpl4_regs0[0:0] + update \builder_multiregimpl4_regs1 $0\builder_multiregimpl4_regs1[0:0] + update \builder_multiregimpl5_regs0 $0\builder_multiregimpl5_regs0[0:0] + update \builder_multiregimpl5_regs1 $0\builder_multiregimpl5_regs1[0:0] + update \builder_multiregimpl6_regs0 $0\builder_multiregimpl6_regs0[0:0] + update \builder_multiregimpl6_regs1 $0\builder_multiregimpl6_regs1[0:0] + update \builder_multiregimpl7_regs0 $0\builder_multiregimpl7_regs0[0:0] + update \builder_multiregimpl7_regs1 $0\builder_multiregimpl7_regs1[0:0] + update \builder_multiregimpl8_regs0 $0\builder_multiregimpl8_regs0[0:0] + update \builder_multiregimpl8_regs1 $0\builder_multiregimpl8_regs1[0:0] + update \builder_multiregimpl9_regs0 $0\builder_multiregimpl9_regs0[0:0] + update \builder_multiregimpl9_regs1 $0\builder_multiregimpl9_regs1[0:0] + update \builder_multiregimpl10_regs0 $0\builder_multiregimpl10_regs0[0:0] + update \builder_multiregimpl10_regs1 $0\builder_multiregimpl10_regs1[0:0] + update \builder_multiregimpl11_regs0 $0\builder_multiregimpl11_regs0[0:0] + update \builder_multiregimpl11_regs1 $0\builder_multiregimpl11_regs1[0:0] + update \builder_multiregimpl12_regs0 $0\builder_multiregimpl12_regs0[0:0] + update \builder_multiregimpl12_regs1 $0\builder_multiregimpl12_regs1[0:0] + update \builder_multiregimpl13_regs0 $0\builder_multiregimpl13_regs0[0:0] + update \builder_multiregimpl13_regs1 $0\builder_multiregimpl13_regs1[0:0] + update \builder_multiregimpl14_regs0 $0\builder_multiregimpl14_regs0[0:0] + update \builder_multiregimpl14_regs1 $0\builder_multiregimpl14_regs1[0:0] + update \builder_multiregimpl15_regs0 $0\builder_multiregimpl15_regs0[0:0] + update \builder_multiregimpl15_regs1 $0\builder_multiregimpl15_regs1[0:0] + update \builder_multiregimpl16_regs0 $0\builder_multiregimpl16_regs0[0:0] + update \builder_multiregimpl16_regs1 $0\builder_multiregimpl16_regs1[0:0] + end + attribute \src "ls180.v:781.11-781.68" + process $proc$ls180.v:781$3374 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] 4'0000 + sync always + sync init + update \main_sdram_bankmachine3_cmd_buffer_lookahead_level $1\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] + end + attribute \src "ls180.v:782.5-782.64" + process $proc$ls180.v:782$3375 + assign { } { } + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_replace[0:0] 1'0 + sync always + update \main_sdram_bankmachine3_cmd_buffer_lookahead_replace $0\main_sdram_bankmachine3_cmd_buffer_lookahead_replace[0:0] + sync init + end + attribute \src "ls180.v:783.11-783.70" + process $proc$ls180.v:783$3376 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine3_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] + end + attribute \src "ls180.v:784.11-784.70" + process $proc$ls180.v:784$3377 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine3_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] + end + attribute \src "ls180.v:785.11-785.73" + process $proc$ls180.v:785$3378 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr $1\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] + end + attribute \src "ls180.v:806.5-806.59" + process $proc$ls180.v:806$3379 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_cmd_buffer_source_valid $1\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] + end + attribute \src "ls180.v:808.5-808.59" + process $proc$ls180.v:808$3380 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_cmd_buffer_source_first $1\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] + end + attribute \src "ls180.v:809.5-809.58" + process $proc$ls180.v:809$3381 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_cmd_buffer_source_last $1\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] + end + attribute \src "ls180.v:810.5-810.64" + process $proc$ls180.v:810$3382 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_cmd_buffer_source_payload_we $1\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] + end + attribute \src "ls180.v:811.12-811.74" + process $proc$ls180.v:811$3383 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000 + sync always + sync init + update \main_sdram_bankmachine3_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] + end + attribute \src "ls180.v:812.12-812.47" + process $proc$ls180.v:812$3384 + assign { } { } + assign $1\main_sdram_bankmachine3_row[12:0] 13'0000000000000 + sync always + sync init + update \main_sdram_bankmachine3_row $1\main_sdram_bankmachine3_row[12:0] + end + attribute \src "ls180.v:813.5-813.46" + process $proc$ls180.v:813$3385 + assign { } { } + assign $1\main_sdram_bankmachine3_row_opened[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_row_opened $1\main_sdram_bankmachine3_row_opened[0:0] + end + attribute \src "ls180.v:815.5-815.44" + process $proc$ls180.v:815$3386 + assign { } { } + assign $1\main_sdram_bankmachine3_row_open[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_row_open $1\main_sdram_bankmachine3_row_open[0:0] + end + attribute \src "ls180.v:816.5-816.45" + process $proc$ls180.v:816$3387 + assign { } { } + assign $1\main_sdram_bankmachine3_row_close[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_row_close $1\main_sdram_bankmachine3_row_close[0:0] + end + attribute \src "ls180.v:817.5-817.54" + process $proc$ls180.v:817$3388 + assign { } { } + assign $1\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_row_col_n_addr_sel $1\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] + end + attribute \src "ls180.v:819.32-819.76" + process $proc$ls180.v:819$3389 + assign { } { } + assign $1\main_sdram_bankmachine3_twtpcon_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_twtpcon_ready $1\main_sdram_bankmachine3_twtpcon_ready[0:0] + end + attribute \src "ls180.v:820.11-820.55" + process $proc$ls180.v:820$3390 + assign { } { } + assign $1\main_sdram_bankmachine3_twtpcon_count[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine3_twtpcon_count $1\main_sdram_bankmachine3_twtpcon_count[2:0] + end + attribute \src "ls180.v:822.32-822.75" + process $proc$ls180.v:822$3391 + assign { } { } + assign $0\main_sdram_bankmachine3_trccon_ready[0:0] 1'1 + sync always + update \main_sdram_bankmachine3_trccon_ready $0\main_sdram_bankmachine3_trccon_ready[0:0] + sync init + end + attribute \src "ls180.v:824.32-824.76" + process $proc$ls180.v:824$3392 + assign { } { } + assign $0\main_sdram_bankmachine3_trascon_ready[0:0] 1'1 + sync always + update \main_sdram_bankmachine3_trascon_ready $0\main_sdram_bankmachine3_trascon_ready[0:0] + sync init + end + attribute \src "ls180.v:827.5-827.44" + process $proc$ls180.v:827$3393 + assign { } { } + assign $0\main_sdram_choose_cmd_want_reads[0:0] 1'0 + sync always + update \main_sdram_choose_cmd_want_reads $0\main_sdram_choose_cmd_want_reads[0:0] + sync init + end + attribute \src "ls180.v:828.5-828.45" + process $proc$ls180.v:828$3394 + assign { } { } + assign $0\main_sdram_choose_cmd_want_writes[0:0] 1'0 + sync always + update \main_sdram_choose_cmd_want_writes $0\main_sdram_choose_cmd_want_writes[0:0] + sync init + end + attribute \src "ls180.v:829.5-829.43" + process $proc$ls180.v:829$3395 + assign { } { } + assign $0\main_sdram_choose_cmd_want_cmds[0:0] 1'0 + sync always + update \main_sdram_choose_cmd_want_cmds $0\main_sdram_choose_cmd_want_cmds[0:0] + sync init + end + attribute \src "ls180.v:830.5-830.48" + process $proc$ls180.v:830$3396 + assign { } { } + assign $0\main_sdram_choose_cmd_want_activates[0:0] 1'0 + sync always + update \main_sdram_choose_cmd_want_activates $0\main_sdram_choose_cmd_want_activates[0:0] + sync init + end + attribute \src "ls180.v:832.5-832.43" + process $proc$ls180.v:832$3397 + assign { } { } + assign $0\main_sdram_choose_cmd_cmd_ready[0:0] 1'0 + sync always + update \main_sdram_choose_cmd_cmd_ready $0\main_sdram_choose_cmd_cmd_ready[0:0] + sync init + end + attribute \src "ls180.v:835.5-835.49" + process $proc$ls180.v:835$3398 + assign { } { } + assign $1\main_sdram_choose_cmd_cmd_payload_cas[0:0] 1'0 + sync always + sync init + update \main_sdram_choose_cmd_cmd_payload_cas $1\main_sdram_choose_cmd_cmd_payload_cas[0:0] + end + attribute \src "ls180.v:836.5-836.49" + process $proc$ls180.v:836$3399 + assign { } { } + assign $1\main_sdram_choose_cmd_cmd_payload_ras[0:0] 1'0 + sync always + sync init + update \main_sdram_choose_cmd_cmd_payload_ras $1\main_sdram_choose_cmd_cmd_payload_ras[0:0] + end + attribute \src "ls180.v:837.5-837.48" + process $proc$ls180.v:837$3400 + assign { } { } + assign $1\main_sdram_choose_cmd_cmd_payload_we[0:0] 1'0 + sync always + sync init + update \main_sdram_choose_cmd_cmd_payload_we $1\main_sdram_choose_cmd_cmd_payload_we[0:0] + end + attribute \src "ls180.v:841.11-841.46" + process $proc$ls180.v:841$3401 + assign { } { } + assign $1\main_sdram_choose_cmd_valids[3:0] 4'0000 + sync always + sync init + update \main_sdram_choose_cmd_valids $1\main_sdram_choose_cmd_valids[3:0] + end + attribute \src "ls180.v:843.11-843.45" + process $proc$ls180.v:843$3402 + assign { } { } + assign $1\main_sdram_choose_cmd_grant[1:0] 2'00 + sync always + sync init + update \main_sdram_choose_cmd_grant $1\main_sdram_choose_cmd_grant[1:0] + end + attribute \src "ls180.v:845.5-845.44" + process $proc$ls180.v:845$3403 + assign { } { } + assign $1\main_sdram_choose_req_want_reads[0:0] 1'0 + sync always + sync init + update \main_sdram_choose_req_want_reads $1\main_sdram_choose_req_want_reads[0:0] + end + attribute \src "ls180.v:846.5-846.45" + process $proc$ls180.v:846$3404 + assign { } { } + assign $1\main_sdram_choose_req_want_writes[0:0] 1'0 + sync always + sync init + update \main_sdram_choose_req_want_writes $1\main_sdram_choose_req_want_writes[0:0] + end + attribute \src "ls180.v:848.5-848.48" + process $proc$ls180.v:848$3405 + assign { } { } + assign $1\main_sdram_choose_req_want_activates[0:0] 1'0 + sync always + sync init + update \main_sdram_choose_req_want_activates $1\main_sdram_choose_req_want_activates[0:0] + end + attribute \src "ls180.v:85.11-85.52" + process $proc$ls180.v:85$3134 + assign { } { } + assign $0\main_libresocsim_libresoc_ibus_cti[2:0] 3'000 + sync always + update \main_libresocsim_libresoc_ibus_cti $0\main_libresocsim_libresoc_ibus_cti[2:0] + sync init + end + attribute \src "ls180.v:850.5-850.43" + process $proc$ls180.v:850$3406 + assign { } { } + assign $1\main_sdram_choose_req_cmd_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_choose_req_cmd_ready $1\main_sdram_choose_req_cmd_ready[0:0] + end + attribute \src "ls180.v:853.5-853.49" + process $proc$ls180.v:853$3407 + assign { } { } + assign $1\main_sdram_choose_req_cmd_payload_cas[0:0] 1'0 + sync always + sync init + update \main_sdram_choose_req_cmd_payload_cas $1\main_sdram_choose_req_cmd_payload_cas[0:0] + end + attribute \src "ls180.v:854.5-854.49" + process $proc$ls180.v:854$3408 + assign { } { } + assign $1\main_sdram_choose_req_cmd_payload_ras[0:0] 1'0 + sync always + sync init + update \main_sdram_choose_req_cmd_payload_ras $1\main_sdram_choose_req_cmd_payload_ras[0:0] + end + attribute \src "ls180.v:855.5-855.48" + process $proc$ls180.v:855$3409 + assign { } { } + assign $1\main_sdram_choose_req_cmd_payload_we[0:0] 1'0 + sync always + sync init + update \main_sdram_choose_req_cmd_payload_we $1\main_sdram_choose_req_cmd_payload_we[0:0] + end + attribute \src "ls180.v:859.11-859.46" + process $proc$ls180.v:859$3410 + assign { } { } + assign $1\main_sdram_choose_req_valids[3:0] 4'0000 + sync always + sync init + update \main_sdram_choose_req_valids $1\main_sdram_choose_req_valids[3:0] + end + attribute \src "ls180.v:86.11-86.52" + process $proc$ls180.v:86$3135 + assign { } { } + assign $0\main_libresocsim_libresoc_ibus_bte[1:0] 2'00 + sync always + update \main_libresocsim_libresoc_ibus_bte $0\main_libresocsim_libresoc_ibus_bte[1:0] + sync init + end + attribute \src "ls180.v:861.11-861.45" + process $proc$ls180.v:861$3411 + assign { } { } + assign $1\main_sdram_choose_req_grant[1:0] 2'00 + sync always + sync init + update \main_sdram_choose_req_grant $1\main_sdram_choose_req_grant[1:0] + end + attribute \src "ls180.v:863.12-863.36" + process $proc$ls180.v:863$3412 + assign { } { } + assign $0\main_sdram_nop_a[12:0] 13'0000000000000 + sync always + update \main_sdram_nop_a $0\main_sdram_nop_a[12:0] + sync init + end + attribute \src "ls180.v:864.11-864.35" + process $proc$ls180.v:864$3413 + assign { } { } + assign $0\main_sdram_nop_ba[1:0] 2'00 + sync always + update \main_sdram_nop_ba $0\main_sdram_nop_ba[1:0] + sync init + end + attribute \src "ls180.v:865.11-865.40" + process $proc$ls180.v:865$3414 + assign { } { } + assign $1\main_sdram_steerer_sel[1:0] 2'00 + sync always + sync init + update \main_sdram_steerer_sel $1\main_sdram_steerer_sel[1:0] + end + attribute \src "ls180.v:866.5-866.31" + process $proc$ls180.v:866$3415 + assign { } { } + assign $0\main_sdram_steerer0[0:0] 1'1 + sync always + update \main_sdram_steerer0 $0\main_sdram_steerer0[0:0] + sync init + end + attribute \src "ls180.v:867.5-867.31" + process $proc$ls180.v:867$3416 + assign { } { } + assign $0\main_sdram_steerer1[0:0] 1'1 + sync always + update \main_sdram_steerer1 $0\main_sdram_steerer1[0:0] + sync init + end + attribute \src "ls180.v:869.32-869.63" + process $proc$ls180.v:869$3417 + assign { } { } + assign $0\main_sdram_trrdcon_ready[0:0] 1'1 + sync always + update \main_sdram_trrdcon_ready $0\main_sdram_trrdcon_ready[0:0] + sync init + end + attribute \src "ls180.v:871.32-871.63" + process $proc$ls180.v:871$3418 + assign { } { } + assign $0\main_sdram_tfawcon_ready[0:0] 1'1 + sync always + update \main_sdram_tfawcon_ready $0\main_sdram_tfawcon_ready[0:0] + sync init + end + attribute \src "ls180.v:873.32-873.63" + process $proc$ls180.v:873$3419 + assign { } { } + assign $1\main_sdram_tccdcon_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_tccdcon_ready $1\main_sdram_tccdcon_ready[0:0] + end + attribute \src "ls180.v:874.5-874.36" + process $proc$ls180.v:874$3420 + assign { } { } + assign $1\main_sdram_tccdcon_count[0:0] 1'0 + sync always + sync init + update \main_sdram_tccdcon_count $1\main_sdram_tccdcon_count[0:0] + end + attribute \src "ls180.v:876.32-876.63" + process $proc$ls180.v:876$3421 + assign { } { } + assign $1\main_sdram_twtrcon_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_twtrcon_ready $1\main_sdram_twtrcon_ready[0:0] + end + attribute \src "ls180.v:877.11-877.42" + process $proc$ls180.v:877$3422 + assign { } { } + assign $1\main_sdram_twtrcon_count[2:0] 3'000 + sync always + sync init + update \main_sdram_twtrcon_count $1\main_sdram_twtrcon_count[2:0] + end + attribute \src "ls180.v:88.12-88.58" + process $proc$ls180.v:88$3136 + assign { } { } + assign $1\main_libresocsim_libresoc_xics_icp_adr[29:0] 30'000000000000000000000000000000 + sync always + sync init + update \main_libresocsim_libresoc_xics_icp_adr $1\main_libresocsim_libresoc_xics_icp_adr[29:0] + end + attribute \src "ls180.v:880.5-880.26" + process $proc$ls180.v:880$3423 + assign { } { } + assign $1\main_sdram_en0[0:0] 1'0 + sync always + sync init + update \main_sdram_en0 $1\main_sdram_en0[0:0] + end + attribute \src "ls180.v:882.11-882.34" + process $proc$ls180.v:882$3424 + assign { } { } + assign $1\main_sdram_time0[4:0] 5'00000 + sync always + sync init + update \main_sdram_time0 $1\main_sdram_time0[4:0] + end + attribute \src "ls180.v:883.5-883.26" + process $proc$ls180.v:883$3425 + assign { } { } + assign $1\main_sdram_en1[0:0] 1'0 + sync always + sync init + update \main_sdram_en1 $1\main_sdram_en1[0:0] + end + attribute \src "ls180.v:885.11-885.34" + process $proc$ls180.v:885$3426 + assign { } { } + assign $1\main_sdram_time1[3:0] 4'0000 + sync always + sync init + update \main_sdram_time1 $1\main_sdram_time1[3:0] + end + attribute \src "ls180.v:89.12-89.60" + process $proc$ls180.v:89$3137 + assign { } { } + assign $1\main_libresocsim_libresoc_xics_icp_dat_w[31:0] 0 + sync always + sync init + update \main_libresocsim_libresoc_xics_icp_dat_w $1\main_libresocsim_libresoc_xics_icp_dat_w[31:0] + end + attribute \src "ls180.v:900.12-900.37" + process $proc$ls180.v:900$3427 + assign { } { } + assign $1\main_wb_sdram_adr[29:0] 30'000000000000000000000000000000 + sync always + sync init + update \main_wb_sdram_adr $1\main_wb_sdram_adr[29:0] + end + attribute \src "ls180.v:901.12-901.39" + process $proc$ls180.v:901$3428 + assign { } { } + assign $1\main_wb_sdram_dat_w[31:0] 0 + sync always + sync init + update \main_wb_sdram_dat_w $1\main_wb_sdram_dat_w[31:0] + end + attribute \src "ls180.v:903.11-903.35" + process $proc$ls180.v:903$3429 + assign { } { } + assign $1\main_wb_sdram_sel[3:0] 4'0000 + sync always + sync init + update \main_wb_sdram_sel $1\main_wb_sdram_sel[3:0] + end + attribute \src "ls180.v:904.5-904.29" + process $proc$ls180.v:904$3430 + assign { } { } + assign $1\main_wb_sdram_cyc[0:0] 1'0 + sync always + sync init + update \main_wb_sdram_cyc $1\main_wb_sdram_cyc[0:0] + end + attribute \src "ls180.v:905.5-905.29" + process $proc$ls180.v:905$3431 + assign { } { } + assign $1\main_wb_sdram_stb[0:0] 1'0 + sync always + sync init + update \main_wb_sdram_stb $1\main_wb_sdram_stb[0:0] + end + attribute \src "ls180.v:906.5-906.29" + process $proc$ls180.v:906$3432 + assign { } { } + assign $1\main_wb_sdram_ack[0:0] 1'0 + sync always + sync init + update \main_wb_sdram_ack $1\main_wb_sdram_ack[0:0] + end + attribute \src "ls180.v:907.5-907.28" + process $proc$ls180.v:907$3433 + assign { } { } + assign $1\main_wb_sdram_we[0:0] 1'0 + sync always + sync init + update \main_wb_sdram_we $1\main_wb_sdram_we[0:0] + end + attribute \src "ls180.v:91.11-91.56" + process $proc$ls180.v:91$3138 + assign { } { } + assign $1\main_libresocsim_libresoc_xics_icp_sel[3:0] 4'0000 + sync always + sync init + update \main_libresocsim_libresoc_xics_icp_sel $1\main_libresocsim_libresoc_xics_icp_sel[3:0] + end + attribute \src "ls180.v:914.5-914.54" + process $proc$ls180.v:914$3434 + assign { } { } + assign $1\main_socbushandler_converted_interface_ack[0:0] 1'0 + sync always + sync init + update \main_socbushandler_converted_interface_ack $1\main_socbushandler_converted_interface_ack[0:0] + end + attribute \src "ls180.v:918.5-918.54" + process $proc$ls180.v:918$3435 + assign { } { } + assign $0\main_socbushandler_converted_interface_err[0:0] 1'0 + sync always + update \main_socbushandler_converted_interface_err $0\main_socbushandler_converted_interface_err[0:0] + sync init + end + attribute \src "ls180.v:919.5-919.35" + process $proc$ls180.v:919$3436 + assign { } { } + assign $1\main_socbushandler_skip[0:0] 1'0 + sync always + sync init + update \main_socbushandler_skip $1\main_socbushandler_skip[0:0] + end + attribute \src "ls180.v:92.5-92.50" + process $proc$ls180.v:92$3139 + assign { } { } + assign $1\main_libresocsim_libresoc_xics_icp_cyc[0:0] 1'0 + sync always + sync init + update \main_libresocsim_libresoc_xics_icp_cyc $1\main_libresocsim_libresoc_xics_icp_cyc[0:0] + end + attribute \src "ls180.v:920.5-920.38" + process $proc$ls180.v:920$3437 + assign { } { } + assign $1\main_socbushandler_counter[0:0] 1'0 + sync always + sync init + update \main_socbushandler_counter $1\main_socbushandler_counter[0:0] + end + attribute \src "ls180.v:922.12-922.44" + process $proc$ls180.v:922$3438 + assign { } { } + assign $1\main_socbushandler_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \main_socbushandler_dat_r $1\main_socbushandler_dat_r[63:0] + end + attribute \src "ls180.v:923.12-923.40" + process $proc$ls180.v:923$3439 + assign { } { } + assign $1\main_litedram_wb_adr[29:0] 30'000000000000000000000000000000 + sync always + sync init + update \main_litedram_wb_adr $1\main_litedram_wb_adr[29:0] + end + attribute \src "ls180.v:924.12-924.42" + process $proc$ls180.v:924$3440 + assign { } { } + assign $1\main_litedram_wb_dat_w[15:0] 16'0000000000000000 + sync always + sync init + update \main_litedram_wb_dat_w $1\main_litedram_wb_dat_w[15:0] + end + attribute \src "ls180.v:926.11-926.38" + process $proc$ls180.v:926$3441 + assign { } { } + assign $1\main_litedram_wb_sel[1:0] 2'00 + sync always + sync init + update \main_litedram_wb_sel $1\main_litedram_wb_sel[1:0] + end + attribute \src "ls180.v:927.5-927.32" + process $proc$ls180.v:927$3442 + assign { } { } + assign $1\main_litedram_wb_cyc[0:0] 1'0 + sync always + sync init + update \main_litedram_wb_cyc $1\main_litedram_wb_cyc[0:0] + end + attribute \src "ls180.v:928.5-928.32" + process $proc$ls180.v:928$3443 + assign { } { } + assign $1\main_litedram_wb_stb[0:0] 1'0 + sync always + sync init + update \main_litedram_wb_stb $1\main_litedram_wb_stb[0:0] + end + attribute \src "ls180.v:93.5-93.50" + process $proc$ls180.v:93$3140 + assign { } { } + assign $1\main_libresocsim_libresoc_xics_icp_stb[0:0] 1'0 + sync always + sync init + update \main_libresocsim_libresoc_xics_icp_stb $1\main_libresocsim_libresoc_xics_icp_stb[0:0] + end + attribute \src "ls180.v:930.5-930.31" + process $proc$ls180.v:930$3444 + assign { } { } + assign $1\main_litedram_wb_we[0:0] 1'0 + sync always + sync init + update \main_litedram_wb_we $1\main_litedram_wb_we[0:0] + end + attribute \src "ls180.v:931.5-931.31" + process $proc$ls180.v:931$3445 + assign { } { } + assign $1\main_converter_skip[0:0] 1'0 + sync always + sync init + update \main_converter_skip $1\main_converter_skip[0:0] + end + attribute \src "ls180.v:932.5-932.34" + process $proc$ls180.v:932$3446 + assign { } { } + assign $1\main_converter_counter[0:0] 1'0 + sync always + sync init + update \main_converter_counter $1\main_converter_counter[0:0] + end + attribute \src "ls180.v:934.12-934.40" + process $proc$ls180.v:934$3447 + assign { } { } + assign $1\main_converter_dat_r[31:0] 0 + sync always + sync init + update \main_converter_dat_r $1\main_converter_dat_r[31:0] + end + attribute \src "ls180.v:935.5-935.29" + process $proc$ls180.v:935$3448 + assign { } { } + assign $1\main_cmd_consumed[0:0] 1'0 + sync always + sync init + update \main_cmd_consumed $1\main_cmd_consumed[0:0] + end + attribute \src "ls180.v:936.5-936.31" + process $proc$ls180.v:936$3449 + assign { } { } + assign $1\main_wdata_consumed[0:0] 1'0 + sync always + sync init + update \main_wdata_consumed $1\main_wdata_consumed[0:0] + end + attribute \src "ls180.v:940.12-940.47" + process $proc$ls180.v:940$3450 + assign { } { } + assign $1\main_uart_phy_storage[31:0] 9895604 + sync always + sync init + update \main_uart_phy_storage $1\main_uart_phy_storage[31:0] + end + attribute \src "ls180.v:941.5-941.28" + process $proc$ls180.v:941$3451 + assign { } { } + assign $1\main_uart_phy_re[0:0] 1'0 + sync always + sync init + update \main_uart_phy_re $1\main_uart_phy_re[0:0] + end + attribute \src "ls180.v:943.5-943.36" + process $proc$ls180.v:943$3452 + assign { } { } + assign $1\main_uart_phy_sink_ready[0:0] 1'0 + sync always + sync init + update \main_uart_phy_sink_ready $1\main_uart_phy_sink_ready[0:0] + end + attribute \src "ls180.v:947.5-947.39" + process $proc$ls180.v:947$3453 + assign { } { } + assign $1\main_uart_phy_uart_clk_txen[0:0] 1'0 + sync always + sync init + update \main_uart_phy_uart_clk_txen $1\main_uart_phy_uart_clk_txen[0:0] + end + attribute \src "ls180.v:948.12-948.54" + process $proc$ls180.v:948$3454 + assign { } { } + assign $1\main_uart_phy_phase_accumulator_tx[31:0] 0 + sync always + sync init + update \main_uart_phy_phase_accumulator_tx $1\main_uart_phy_phase_accumulator_tx[31:0] + end + attribute \src "ls180.v:949.11-949.38" + process $proc$ls180.v:949$3455 + assign { } { } + assign $1\main_uart_phy_tx_reg[7:0] 8'00000000 + sync always + sync init + update \main_uart_phy_tx_reg $1\main_uart_phy_tx_reg[7:0] + end + attribute \src "ls180.v:95.5-95.49" + process $proc$ls180.v:95$3141 + assign { } { } + assign $1\main_libresocsim_libresoc_xics_icp_we[0:0] 1'0 + sync always + sync init + update \main_libresocsim_libresoc_xics_icp_we $1\main_libresocsim_libresoc_xics_icp_we[0:0] + end + attribute \src "ls180.v:950.11-950.43" + process $proc$ls180.v:950$3456 + assign { } { } + assign $1\main_uart_phy_tx_bitcount[3:0] 4'0000 + sync always + sync init + update \main_uart_phy_tx_bitcount $1\main_uart_phy_tx_bitcount[3:0] + end + attribute \src "ls180.v:951.5-951.33" + process $proc$ls180.v:951$3457 + assign { } { } + assign $1\main_uart_phy_tx_busy[0:0] 1'0 + sync always + sync init + update \main_uart_phy_tx_busy $1\main_uart_phy_tx_busy[0:0] + end + attribute \src "ls180.v:952.5-952.38" + process $proc$ls180.v:952$3458 + assign { } { } + assign $1\main_uart_phy_source_valid[0:0] 1'0 + sync always + sync init + update \main_uart_phy_source_valid $1\main_uart_phy_source_valid[0:0] + end + attribute \src "ls180.v:954.5-954.38" + process $proc$ls180.v:954$3459 + assign { } { } + assign $0\main_uart_phy_source_first[0:0] 1'0 + sync always + update \main_uart_phy_source_first $0\main_uart_phy_source_first[0:0] + sync init + end + attribute \src "ls180.v:955.5-955.37" + process $proc$ls180.v:955$3460 + assign { } { } + assign $0\main_uart_phy_source_last[0:0] 1'0 + sync always + update \main_uart_phy_source_last $0\main_uart_phy_source_last[0:0] + sync init + end + attribute \src "ls180.v:956.11-956.51" + process $proc$ls180.v:956$3461 + assign { } { } + assign $1\main_uart_phy_source_payload_data[7:0] 8'00000000 + sync always + sync init + update \main_uart_phy_source_payload_data $1\main_uart_phy_source_payload_data[7:0] + end + attribute \src "ls180.v:957.5-957.39" + process $proc$ls180.v:957$3462 + assign { } { } + assign $1\main_uart_phy_uart_clk_rxen[0:0] 1'0 + sync always + sync init + update \main_uart_phy_uart_clk_rxen $1\main_uart_phy_uart_clk_rxen[0:0] + end + attribute \src "ls180.v:958.12-958.54" + process $proc$ls180.v:958$3463 + assign { } { } + assign $1\main_uart_phy_phase_accumulator_rx[31:0] 0 + sync always + sync init + update \main_uart_phy_phase_accumulator_rx $1\main_uart_phy_phase_accumulator_rx[31:0] + end + attribute \src "ls180.v:960.5-960.30" + process $proc$ls180.v:960$3464 + assign { } { } + assign $1\main_uart_phy_rx_r[0:0] 1'0 + sync always + sync init + update \main_uart_phy_rx_r $1\main_uart_phy_rx_r[0:0] + end + attribute \src "ls180.v:961.11-961.38" + process $proc$ls180.v:961$3465 + assign { } { } + assign $1\main_uart_phy_rx_reg[7:0] 8'00000000 + sync always + sync init + update \main_uart_phy_rx_reg $1\main_uart_phy_rx_reg[7:0] + end + attribute \src "ls180.v:962.11-962.43" + process $proc$ls180.v:962$3466 + assign { } { } + assign $1\main_uart_phy_rx_bitcount[3:0] 4'0000 + sync always + sync init + update \main_uart_phy_rx_bitcount $1\main_uart_phy_rx_bitcount[3:0] + end + attribute \src "ls180.v:963.5-963.33" + process $proc$ls180.v:963$3467 + assign { } { } + assign $1\main_uart_phy_rx_busy[0:0] 1'0 + sync always + sync init + update \main_uart_phy_rx_busy $1\main_uart_phy_rx_busy[0:0] + end + attribute \src "ls180.v:97.12-97.58" + process $proc$ls180.v:97$3142 + assign { } { } + assign $1\main_libresocsim_libresoc_xics_ics_adr[29:0] 30'000000000000000000000000000000 + sync always + sync init + update \main_libresocsim_libresoc_xics_ics_adr $1\main_libresocsim_libresoc_xics_ics_adr[29:0] + end + attribute \src "ls180.v:974.5-974.32" + process $proc$ls180.v:974$3468 + assign { } { } + assign $1\main_uart_tx_pending[0:0] 1'0 + sync always + sync init + update \main_uart_tx_pending $1\main_uart_tx_pending[0:0] + end + attribute \src "ls180.v:976.5-976.30" + process $proc$ls180.v:976$3469 + assign { } { } + assign $1\main_uart_tx_clear[0:0] 1'0 + sync always + sync init + update \main_uart_tx_clear $1\main_uart_tx_clear[0:0] + end + attribute \src "ls180.v:977.5-977.36" + process $proc$ls180.v:977$3470 + assign { } { } + assign $1\main_uart_tx_old_trigger[0:0] 1'0 + sync always + sync init + update \main_uart_tx_old_trigger $1\main_uart_tx_old_trigger[0:0] + end + attribute \src "ls180.v:979.5-979.32" + process $proc$ls180.v:979$3471 + assign { } { } + assign $1\main_uart_rx_pending[0:0] 1'0 + sync always + sync init + update \main_uart_rx_pending $1\main_uart_rx_pending[0:0] + end + attribute \src "ls180.v:98.12-98.60" + process $proc$ls180.v:98$3143 + assign { } { } + assign $1\main_libresocsim_libresoc_xics_ics_dat_w[31:0] 0 + sync always + sync init + update \main_libresocsim_libresoc_xics_ics_dat_w $1\main_libresocsim_libresoc_xics_ics_dat_w[31:0] + end + attribute \src "ls180.v:981.5-981.30" + process $proc$ls180.v:981$3472 + assign { } { } + assign $1\main_uart_rx_clear[0:0] 1'0 + sync always + sync init + update \main_uart_rx_clear $1\main_uart_rx_clear[0:0] + end + attribute \src "ls180.v:982.5-982.36" + process $proc$ls180.v:982$3473 + assign { } { } + assign $1\main_uart_rx_old_trigger[0:0] 1'0 + sync always + sync init + update \main_uart_rx_old_trigger $1\main_uart_rx_old_trigger[0:0] + end + attribute \src "ls180.v:986.11-986.49" + process $proc$ls180.v:986$3474 + assign { } { } + assign $1\main_uart_eventmanager_status_w[1:0] 2'00 + sync always + sync init + update \main_uart_eventmanager_status_w $1\main_uart_eventmanager_status_w[1:0] + end + attribute \src "ls180.v:990.11-990.50" + process $proc$ls180.v:990$3475 + assign { } { } + assign $1\main_uart_eventmanager_pending_w[1:0] 2'00 + sync always + sync init + update \main_uart_eventmanager_pending_w $1\main_uart_eventmanager_pending_w[1:0] + end + attribute \src "ls180.v:991.11-991.48" + process $proc$ls180.v:991$3476 + assign { } { } + assign $1\main_uart_eventmanager_storage[1:0] 2'00 + sync always + sync init + update \main_uart_eventmanager_storage $1\main_uart_eventmanager_storage[1:0] + end + attribute \src "ls180.v:992.5-992.37" + process $proc$ls180.v:992$3477 + assign { } { } + assign $1\main_uart_eventmanager_re[0:0] 1'0 + sync always + sync init + update \main_uart_eventmanager_re $1\main_uart_eventmanager_re[0:0] + end + connect \main_libresocsim_libresoc_reset \main_libresocsim_reset + connect \main_libresocsim_libresoc_clk_sel \sys_clksel_i + connect \sys_pll_18_o \main_libresocsim_libresoc_pll_18_o + connect \sys_pll_lck_o \main_libresocsim_libresoc_pll_lck_o + connect \main_libresocsim_libresoc_jtag_tck \jtag_tck + connect \main_libresocsim_libresoc_jtag_tms \jtag_tms + connect \main_libresocsim_libresoc_jtag_tdi \jtag_tdi + connect \jtag_tdo \main_libresocsim_libresoc_jtag_tdo + connect \main_nc \nc + connect \main_sdblock2mem_sink_sink_valid0 \main_sdcore_source_source_valid + connect \main_sdcore_source_source_ready \main_sdblock2mem_sink_sink_ready0 + connect \main_sdblock2mem_sink_sink_first \main_sdcore_source_source_first + connect \main_sdblock2mem_sink_sink_last \main_sdcore_source_source_last + connect \main_sdblock2mem_sink_sink_payload_data0 \main_sdcore_source_source_payload_data + connect \main_sdcore_sink_sink_valid \main_sdmem2block_source_source_valid0 + connect \main_sdmem2block_source_source_ready0 \main_sdcore_sink_sink_ready + connect \main_sdcore_sink_sink_first \main_sdmem2block_source_source_first0 + connect \main_sdcore_sink_sink_last \main_sdmem2block_source_source_last0 + connect \main_sdcore_sink_sink_payload_data \main_sdmem2block_source_source_payload_data0 + connect \main_libresocsim_bus_error \builder_error + connect \main_converter0_reset $not$ls180.v:2890$50_Y + connect \main_interface0_converted_interface_dat_r { \main_libresocsim_libresoc_xics_icp_dat_r \main_converter0_dat_r [63:32] } + connect \main_converter1_reset $not$ls180.v:2950$61_Y + connect \main_interface1_converted_interface_dat_r { \main_libresocsim_libresoc_xics_ics_dat_r \main_converter1_dat_r [63:32] } + connect \main_socbushandler_reset $not$ls180.v:3010$72_Y + connect \main_socbushandler_converted_interface_dat_r { \main_wb_sdram_dat_r \main_socbushandler_dat_r [63:32] } + connect \main_libresocsim_reset \main_libresocsim_reset_re + connect \main_libresocsim_bus_errors_status \main_libresocsim_bus_errors + connect \main_libresocsim_adr \main_libresocsim_ram_bus_adr [5:0] + connect \main_libresocsim_ram_bus_dat_r \main_libresocsim_dat_r + connect \main_libresocsim_dat_w \main_libresocsim_ram_bus_dat_w + connect \main_libresocsim_zero_trigger $ne$ls180.v:3086$108_Y + connect \main_libresocsim_eventmanager_status_w \main_libresocsim_zero_status + connect \main_libresocsim_eventmanager_pending_w \main_libresocsim_zero_pending + connect \main_libresocsim_irq $and$ls180.v:3095$111_Y + connect \main_libresocsim_zero_status \main_libresocsim_zero_trigger + connect \main_sram0_adr \main_interface0_ram_bus_adr [5:0] + connect \main_interface0_ram_bus_dat_r \main_sram0_dat_r + connect \main_sram0_dat_w \main_interface0_ram_bus_dat_w + connect \main_sram1_adr \main_interface1_ram_bus_adr [5:0] + connect \main_interface1_ram_bus_dat_r \main_sram1_dat_r + connect \main_sram1_dat_w \main_interface1_ram_bus_dat_w + connect \main_sram2_adr \main_interface2_ram_bus_adr [5:0] + connect \main_interface2_ram_bus_dat_r \main_sram2_dat_r + connect \main_sram2_dat_w \main_interface2_ram_bus_dat_w + connect \main_sram3_adr \main_interface3_ram_bus_adr [5:0] + connect \main_interface3_ram_bus_dat_r \main_sram3_dat_r + connect \main_sram3_dat_w \main_interface3_ram_bus_dat_w + connect \sys_clk_1 \sys_clk + connect \por_clk \sys_clk + connect \sys_rst_1 \main_int_rst + connect \main_dfi_p0_address \main_sdram_master_p0_address + connect \main_dfi_p0_bank \main_sdram_master_p0_bank + connect \main_dfi_p0_cas_n \main_sdram_master_p0_cas_n + connect \main_dfi_p0_cs_n \main_sdram_master_p0_cs_n + connect \main_dfi_p0_ras_n \main_sdram_master_p0_ras_n + connect \main_dfi_p0_we_n \main_sdram_master_p0_we_n + connect \main_dfi_p0_cke \main_sdram_master_p0_cke + connect \main_dfi_p0_odt \main_sdram_master_p0_odt + connect \main_dfi_p0_reset_n \main_sdram_master_p0_reset_n + connect \main_dfi_p0_act_n \main_sdram_master_p0_act_n + connect \main_dfi_p0_wrdata \main_sdram_master_p0_wrdata + connect \main_dfi_p0_wrdata_en \main_sdram_master_p0_wrdata_en + connect \main_dfi_p0_wrdata_mask \main_sdram_master_p0_wrdata_mask + connect \main_dfi_p0_rddata_en \main_sdram_master_p0_rddata_en + connect \main_sdram_master_p0_rddata \main_dfi_p0_rddata + connect \main_sdram_master_p0_rddata_valid \main_dfi_p0_rddata_valid + connect \main_sdram_slave_p0_address \main_sdram_dfi_p0_address + connect \main_sdram_slave_p0_bank \main_sdram_dfi_p0_bank + connect \main_sdram_slave_p0_cas_n \main_sdram_dfi_p0_cas_n + connect \main_sdram_slave_p0_cs_n \main_sdram_dfi_p0_cs_n + connect \main_sdram_slave_p0_ras_n \main_sdram_dfi_p0_ras_n + connect \main_sdram_slave_p0_we_n \main_sdram_dfi_p0_we_n + connect \main_sdram_slave_p0_cke \main_sdram_dfi_p0_cke + connect \main_sdram_slave_p0_odt \main_sdram_dfi_p0_odt + connect \main_sdram_slave_p0_reset_n \main_sdram_dfi_p0_reset_n + connect \main_sdram_slave_p0_act_n \main_sdram_dfi_p0_act_n + connect \main_sdram_slave_p0_wrdata \main_sdram_dfi_p0_wrdata + connect \main_sdram_slave_p0_wrdata_en \main_sdram_dfi_p0_wrdata_en + connect \main_sdram_slave_p0_wrdata_mask \main_sdram_dfi_p0_wrdata_mask + connect \main_sdram_slave_p0_rddata_en \main_sdram_dfi_p0_rddata_en + connect \main_sdram_dfi_p0_rddata \main_sdram_slave_p0_rddata + connect \main_sdram_dfi_p0_rddata_valid \main_sdram_slave_p0_rddata_valid + connect \main_sdram_inti_p0_cke \main_sdram_cke + connect \main_sdram_inti_p0_odt \main_sdram_odt + connect \main_sdram_inti_p0_reset_n \main_sdram_reset_n + connect \main_sdram_inti_p0_address \main_sdram_address_storage + connect \main_sdram_inti_p0_bank \main_sdram_baddress_storage + connect \main_sdram_inti_p0_wrdata_en $and$ls180.v:3265$218_Y + connect \main_sdram_inti_p0_rddata_en $and$ls180.v:3266$219_Y + connect \main_sdram_inti_p0_wrdata \main_sdram_wrdata_storage + connect \main_sdram_inti_p0_wrdata_mask 2'00 + connect \main_sdram_bankmachine0_req_valid \main_sdram_interface_bank0_valid + connect \main_sdram_interface_bank0_ready \main_sdram_bankmachine0_req_ready + connect \main_sdram_bankmachine0_req_we \main_sdram_interface_bank0_we + connect \main_sdram_bankmachine0_req_addr \main_sdram_interface_bank0_addr + connect \main_sdram_interface_bank0_lock \main_sdram_bankmachine0_req_lock + connect \main_sdram_interface_bank0_wdata_ready \main_sdram_bankmachine0_req_wdata_ready + connect \main_sdram_interface_bank0_rdata_valid \main_sdram_bankmachine0_req_rdata_valid + connect \main_sdram_bankmachine1_req_valid \main_sdram_interface_bank1_valid + connect \main_sdram_interface_bank1_ready \main_sdram_bankmachine1_req_ready + connect \main_sdram_bankmachine1_req_we \main_sdram_interface_bank1_we + connect \main_sdram_bankmachine1_req_addr \main_sdram_interface_bank1_addr + connect \main_sdram_interface_bank1_lock \main_sdram_bankmachine1_req_lock + connect \main_sdram_interface_bank1_wdata_ready \main_sdram_bankmachine1_req_wdata_ready + connect \main_sdram_interface_bank1_rdata_valid \main_sdram_bankmachine1_req_rdata_valid + connect \main_sdram_bankmachine2_req_valid \main_sdram_interface_bank2_valid + connect \main_sdram_interface_bank2_ready \main_sdram_bankmachine2_req_ready + connect \main_sdram_bankmachine2_req_we \main_sdram_interface_bank2_we + connect \main_sdram_bankmachine2_req_addr \main_sdram_interface_bank2_addr + connect \main_sdram_interface_bank2_lock \main_sdram_bankmachine2_req_lock + connect \main_sdram_interface_bank2_wdata_ready \main_sdram_bankmachine2_req_wdata_ready + connect \main_sdram_interface_bank2_rdata_valid \main_sdram_bankmachine2_req_rdata_valid + connect \main_sdram_bankmachine3_req_valid \main_sdram_interface_bank3_valid + connect \main_sdram_interface_bank3_ready \main_sdram_bankmachine3_req_ready + connect \main_sdram_bankmachine3_req_we \main_sdram_interface_bank3_we + connect \main_sdram_bankmachine3_req_addr \main_sdram_interface_bank3_addr + connect \main_sdram_interface_bank3_lock \main_sdram_bankmachine3_req_lock + connect \main_sdram_interface_bank3_wdata_ready \main_sdram_bankmachine3_req_wdata_ready + connect \main_sdram_interface_bank3_rdata_valid \main_sdram_bankmachine3_req_rdata_valid + connect \main_sdram_timer_wait $not$ls180.v:3297$220_Y + connect \main_sdram_postponer_req_i \main_sdram_timer_done0 + connect \main_sdram_wants_refresh \main_sdram_postponer_req_o + connect \main_sdram_timer_done1 $eq$ls180.v:3300$221_Y + connect \main_sdram_timer_done0 \main_sdram_timer_done1 + connect \main_sdram_timer_count0 \main_sdram_timer_count1 + connect \main_sdram_sequencer_start1 $or$ls180.v:3303$223_Y + connect \main_sdram_sequencer_done0 $and$ls180.v:3304$225_Y + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_valid \main_sdram_bankmachine0_req_valid + connect \main_sdram_bankmachine0_req_ready \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_ready + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we \main_sdram_bankmachine0_req_we + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_addr \main_sdram_bankmachine0_req_addr + connect \main_sdram_bankmachine0_cmd_buffer_sink_valid \main_sdram_bankmachine0_cmd_buffer_lookahead_source_valid + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_source_ready \main_sdram_bankmachine0_cmd_buffer_sink_ready + connect \main_sdram_bankmachine0_cmd_buffer_sink_first \main_sdram_bankmachine0_cmd_buffer_lookahead_source_first + connect \main_sdram_bankmachine0_cmd_buffer_sink_last \main_sdram_bankmachine0_cmd_buffer_lookahead_source_last + connect \main_sdram_bankmachine0_cmd_buffer_sink_payload_we \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we + connect \main_sdram_bankmachine0_cmd_buffer_sink_payload_addr \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr + connect \main_sdram_bankmachine0_cmd_buffer_source_ready $or$ls180.v:3346$227_Y + connect \main_sdram_bankmachine0_req_lock $or$ls180.v:3347$228_Y + connect \main_sdram_bankmachine0_row_hit $eq$ls180.v:3348$229_Y + connect \main_sdram_bankmachine0_cmd_payload_ba 2'00 + connect \main_sdram_bankmachine0_twtpcon_valid $and$ls180.v:3358$234_Y + connect \main_sdram_bankmachine0_trccon_valid $and$ls180.v:3359$236_Y + connect \main_sdram_bankmachine0_trascon_valid $and$ls180.v:3360$238_Y + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din { \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we } + connect { \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we } \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_ready \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_valid + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_addr + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_source_valid \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_source_first \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_source_last \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re \main_sdram_bankmachine0_cmd_buffer_lookahead_source_ready + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_we $and$ls180.v:3392$246_Y + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read $and$ls180.v:3393$247_Y + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr \main_sdram_bankmachine0_cmd_buffer_lookahead_consume + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable $ne$ls180.v:3396$248_Y + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable $ne$ls180.v:3397$249_Y + connect \main_sdram_bankmachine0_cmd_buffer_sink_ready $or$ls180.v:3398$251_Y + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_valid \main_sdram_bankmachine1_req_valid + connect \main_sdram_bankmachine1_req_ready \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_ready + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we \main_sdram_bankmachine1_req_we + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_addr \main_sdram_bankmachine1_req_addr + connect \main_sdram_bankmachine1_cmd_buffer_sink_valid \main_sdram_bankmachine1_cmd_buffer_lookahead_source_valid + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_source_ready \main_sdram_bankmachine1_cmd_buffer_sink_ready + connect \main_sdram_bankmachine1_cmd_buffer_sink_first \main_sdram_bankmachine1_cmd_buffer_lookahead_source_first + connect \main_sdram_bankmachine1_cmd_buffer_sink_last \main_sdram_bankmachine1_cmd_buffer_lookahead_source_last + connect \main_sdram_bankmachine1_cmd_buffer_sink_payload_we \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we + connect \main_sdram_bankmachine1_cmd_buffer_sink_payload_addr \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr + connect \main_sdram_bankmachine1_cmd_buffer_source_ready $or$ls180.v:3503$257_Y + connect \main_sdram_bankmachine1_req_lock $or$ls180.v:3504$258_Y + connect \main_sdram_bankmachine1_row_hit $eq$ls180.v:3505$259_Y + connect \main_sdram_bankmachine1_cmd_payload_ba 2'01 + connect \main_sdram_bankmachine1_twtpcon_valid $and$ls180.v:3515$264_Y + connect \main_sdram_bankmachine1_trccon_valid $and$ls180.v:3516$266_Y + connect \main_sdram_bankmachine1_trascon_valid $and$ls180.v:3517$268_Y + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din { \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we } + connect { \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we } \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_ready \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_valid + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_addr + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_source_valid \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_source_first \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_source_last \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re \main_sdram_bankmachine1_cmd_buffer_lookahead_source_ready + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_we $and$ls180.v:3549$276_Y + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read $and$ls180.v:3550$277_Y + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr \main_sdram_bankmachine1_cmd_buffer_lookahead_consume + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable $ne$ls180.v:3553$278_Y + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable $ne$ls180.v:3554$279_Y + connect \main_sdram_bankmachine1_cmd_buffer_sink_ready $or$ls180.v:3555$281_Y + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_valid \main_sdram_bankmachine2_req_valid + connect \main_sdram_bankmachine2_req_ready \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_ready + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we \main_sdram_bankmachine2_req_we + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_addr \main_sdram_bankmachine2_req_addr + connect \main_sdram_bankmachine2_cmd_buffer_sink_valid \main_sdram_bankmachine2_cmd_buffer_lookahead_source_valid + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_source_ready \main_sdram_bankmachine2_cmd_buffer_sink_ready + connect \main_sdram_bankmachine2_cmd_buffer_sink_first \main_sdram_bankmachine2_cmd_buffer_lookahead_source_first + connect \main_sdram_bankmachine2_cmd_buffer_sink_last \main_sdram_bankmachine2_cmd_buffer_lookahead_source_last + connect \main_sdram_bankmachine2_cmd_buffer_sink_payload_we \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we + connect \main_sdram_bankmachine2_cmd_buffer_sink_payload_addr \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr + connect \main_sdram_bankmachine2_cmd_buffer_source_ready $or$ls180.v:3660$287_Y + connect \main_sdram_bankmachine2_req_lock $or$ls180.v:3661$288_Y + connect \main_sdram_bankmachine2_row_hit $eq$ls180.v:3662$289_Y + connect \main_sdram_bankmachine2_cmd_payload_ba 2'10 + connect \main_sdram_bankmachine2_twtpcon_valid $and$ls180.v:3672$294_Y + connect \main_sdram_bankmachine2_trccon_valid $and$ls180.v:3673$296_Y + connect \main_sdram_bankmachine2_trascon_valid $and$ls180.v:3674$298_Y + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din { \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we } + connect { \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we } \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_ready \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_valid + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_addr + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_source_valid \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_source_first \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_source_last \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re \main_sdram_bankmachine2_cmd_buffer_lookahead_source_ready + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_we $and$ls180.v:3706$306_Y + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read $and$ls180.v:3707$307_Y + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr \main_sdram_bankmachine2_cmd_buffer_lookahead_consume + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable $ne$ls180.v:3710$308_Y + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable $ne$ls180.v:3711$309_Y + connect \main_sdram_bankmachine2_cmd_buffer_sink_ready $or$ls180.v:3712$311_Y + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_valid \main_sdram_bankmachine3_req_valid + connect \main_sdram_bankmachine3_req_ready \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_ready + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we \main_sdram_bankmachine3_req_we + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_addr \main_sdram_bankmachine3_req_addr + connect \main_sdram_bankmachine3_cmd_buffer_sink_valid \main_sdram_bankmachine3_cmd_buffer_lookahead_source_valid + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_source_ready \main_sdram_bankmachine3_cmd_buffer_sink_ready + connect \main_sdram_bankmachine3_cmd_buffer_sink_first \main_sdram_bankmachine3_cmd_buffer_lookahead_source_first + connect \main_sdram_bankmachine3_cmd_buffer_sink_last \main_sdram_bankmachine3_cmd_buffer_lookahead_source_last + connect \main_sdram_bankmachine3_cmd_buffer_sink_payload_we \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we + connect \main_sdram_bankmachine3_cmd_buffer_sink_payload_addr \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr + connect \main_sdram_bankmachine3_cmd_buffer_source_ready $or$ls180.v:3817$317_Y + connect \main_sdram_bankmachine3_req_lock $or$ls180.v:3818$318_Y + connect \main_sdram_bankmachine3_row_hit $eq$ls180.v:3819$319_Y + connect \main_sdram_bankmachine3_cmd_payload_ba 2'11 + connect \main_sdram_bankmachine3_twtpcon_valid $and$ls180.v:3829$324_Y + connect \main_sdram_bankmachine3_trccon_valid $and$ls180.v:3830$326_Y + connect \main_sdram_bankmachine3_trascon_valid $and$ls180.v:3831$328_Y + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din { \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we } + connect { \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we } \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_ready \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_valid + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_addr + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_source_valid \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_source_first \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_source_last \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re \main_sdram_bankmachine3_cmd_buffer_lookahead_source_ready + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_we $and$ls180.v:3863$336_Y + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read $and$ls180.v:3864$337_Y + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr \main_sdram_bankmachine3_cmd_buffer_lookahead_consume + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable $ne$ls180.v:3867$338_Y + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable $ne$ls180.v:3868$339_Y + connect \main_sdram_bankmachine3_cmd_buffer_sink_ready $or$ls180.v:3869$341_Y + connect \main_sdram_choose_req_want_cmds 1'1 + connect \main_sdram_trrdcon_valid $and$ls180.v:3965$352_Y + connect \main_sdram_tfawcon_valid $and$ls180.v:3966$358_Y + connect \main_sdram_ras_allowed $and$ls180.v:3967$359_Y + connect \main_sdram_tccdcon_valid $and$ls180.v:3968$362_Y + connect \main_sdram_cas_allowed \main_sdram_tccdcon_ready + connect \main_sdram_twtrcon_valid $and$ls180.v:3970$364_Y + connect \main_sdram_read_available $or$ls180.v:3971$371_Y + connect \main_sdram_write_available $or$ls180.v:3972$378_Y + connect \main_sdram_max_time0 $eq$ls180.v:3973$379_Y + connect \main_sdram_max_time1 $eq$ls180.v:3974$380_Y + connect \main_sdram_bankmachine0_refresh_req \main_sdram_cmd_valid + connect \main_sdram_bankmachine1_refresh_req \main_sdram_cmd_valid + connect \main_sdram_bankmachine2_refresh_req \main_sdram_cmd_valid + connect \main_sdram_bankmachine3_refresh_req \main_sdram_cmd_valid + connect \main_sdram_go_to_refresh $and$ls180.v:3979$383_Y + connect \main_sdram_interface_rdata \main_sdram_dfi_p0_rddata + connect \main_sdram_dfi_p0_wrdata \main_sdram_interface_wdata + connect \main_sdram_dfi_p0_wrdata_mask $not$ls180.v:3982$384_Y + connect \main_sdram_choose_cmd_request \main_sdram_choose_cmd_valids + connect \main_sdram_choose_cmd_cmd_valid \builder_comb_rhs_array_muxed0 + connect \main_sdram_choose_cmd_cmd_payload_a \builder_comb_rhs_array_muxed1 + connect \main_sdram_choose_cmd_cmd_payload_ba \builder_comb_rhs_array_muxed2 + connect \main_sdram_choose_cmd_cmd_payload_is_read \builder_comb_rhs_array_muxed3 + connect \main_sdram_choose_cmd_cmd_payload_is_write \builder_comb_rhs_array_muxed4 + connect \main_sdram_choose_cmd_cmd_payload_is_cmd \builder_comb_rhs_array_muxed5 + connect \main_sdram_choose_cmd_ce $or$ls180.v:4015$442_Y + connect \main_sdram_choose_req_request \main_sdram_choose_req_valids + connect \main_sdram_choose_req_cmd_valid \builder_comb_rhs_array_muxed6 + connect \main_sdram_choose_req_cmd_payload_a \builder_comb_rhs_array_muxed7 + connect \main_sdram_choose_req_cmd_payload_ba \builder_comb_rhs_array_muxed8 + connect \main_sdram_choose_req_cmd_payload_is_read \builder_comb_rhs_array_muxed9 + connect \main_sdram_choose_req_cmd_payload_is_write \builder_comb_rhs_array_muxed10 + connect \main_sdram_choose_req_cmd_payload_is_cmd \builder_comb_rhs_array_muxed11 + connect \main_sdram_choose_req_ce $or$ls180.v:4084$528_Y + connect \main_sdram_dfi_p0_reset_n 1'1 + connect \main_sdram_dfi_p0_cke \main_sdram_steerer0 + connect \main_sdram_dfi_p0_odt \main_sdram_steerer1 + connect \builder_roundrobin0_request $and$ls180.v:4161$560_Y + connect \builder_roundrobin0_ce $and$ls180.v:4162$563_Y + connect \main_sdram_interface_bank0_addr \builder_comb_rhs_array_muxed12 + connect \main_sdram_interface_bank0_we \builder_comb_rhs_array_muxed13 + connect \main_sdram_interface_bank0_valid \builder_comb_rhs_array_muxed14 + connect \builder_roundrobin1_request $and$ls180.v:4166$576_Y + connect \builder_roundrobin1_ce $and$ls180.v:4167$579_Y + connect \main_sdram_interface_bank1_addr \builder_comb_rhs_array_muxed15 + connect \main_sdram_interface_bank1_we \builder_comb_rhs_array_muxed16 + connect \main_sdram_interface_bank1_valid \builder_comb_rhs_array_muxed17 + connect \builder_roundrobin2_request $and$ls180.v:4171$592_Y + connect \builder_roundrobin2_ce $and$ls180.v:4172$595_Y + connect \main_sdram_interface_bank2_addr \builder_comb_rhs_array_muxed18 + connect \main_sdram_interface_bank2_we \builder_comb_rhs_array_muxed19 + connect \main_sdram_interface_bank2_valid \builder_comb_rhs_array_muxed20 + connect \builder_roundrobin3_request $and$ls180.v:4176$608_Y + connect \builder_roundrobin3_ce $and$ls180.v:4177$611_Y + connect \main_sdram_interface_bank3_addr \builder_comb_rhs_array_muxed21 + connect \main_sdram_interface_bank3_we \builder_comb_rhs_array_muxed22 + connect \main_sdram_interface_bank3_valid \builder_comb_rhs_array_muxed23 + connect \main_port_cmd_ready $or$ls180.v:4181$675_Y + connect \main_port_wdata_ready \builder_new_master_wdata_ready + connect \main_port_rdata_valid \builder_new_master_rdata_valid3 + connect \main_port_rdata_payload_data \main_sdram_interface_rdata + connect \builder_roundrobin0_grant 1'0 + connect \builder_roundrobin1_grant 1'0 + connect \builder_roundrobin2_grant 1'0 + connect \builder_roundrobin3_grant 1'0 + connect \main_converter_reset $not$ls180.v:4203$677_Y + connect \main_wb_sdram_dat_r { \main_litedram_wb_dat_r \main_converter_dat_r [31:16] } + connect \main_port_cmd_payload_addr $sub$ls180.v:4263$688_Y [23:0] + connect \main_port_cmd_payload_we \main_litedram_wb_we + connect \main_port_wdata_payload_data \main_litedram_wb_dat_w + connect \main_port_wdata_payload_we \main_litedram_wb_sel + connect \main_litedram_wb_dat_r \main_port_rdata_payload_data + connect \main_port_flush $not$ls180.v:4268$689_Y + connect \main_port_cmd_last $not$ls180.v:4269$690_Y + connect \main_port_cmd_valid $and$ls180.v:4270$693_Y + connect \main_port_wdata_valid $and$ls180.v:4271$697_Y + connect \main_port_rdata_ready $and$ls180.v:4272$700_Y + connect \main_litedram_wb_ack $and$ls180.v:4273$705_Y + connect \main_ack_cmd $or$ls180.v:4274$707_Y + connect \main_ack_wdata $or$ls180.v:4275$709_Y + connect \main_ack_rdata $and$ls180.v:4276$710_Y + connect \main_uart_uart_sink_valid \main_uart_phy_source_valid + connect \main_uart_phy_source_ready \main_uart_uart_sink_ready + connect \main_uart_uart_sink_first \main_uart_phy_source_first + connect \main_uart_uart_sink_last \main_uart_phy_source_last + connect \main_uart_uart_sink_payload_data \main_uart_phy_source_payload_data + connect \main_uart_phy_sink_valid \main_uart_uart_source_valid + connect \main_uart_uart_source_ready \main_uart_phy_sink_ready + connect \main_uart_phy_sink_first \main_uart_uart_source_first + connect \main_uart_phy_sink_last \main_uart_uart_source_last + connect \main_uart_phy_sink_payload_data \main_uart_uart_source_payload_data + connect \main_uart_tx_fifo_sink_valid \main_uart_rxtx_re + connect \main_uart_tx_fifo_sink_payload_data \main_uart_rxtx_r + connect \main_uart_txfull_status $not$ls180.v:4289$711_Y + connect \main_uart_txempty_status $not$ls180.v:4290$712_Y + connect \main_uart_uart_source_valid \main_uart_tx_fifo_source_valid + connect \main_uart_tx_fifo_source_ready \main_uart_uart_source_ready + connect \main_uart_uart_source_first \main_uart_tx_fifo_source_first + connect \main_uart_uart_source_last \main_uart_tx_fifo_source_last + connect \main_uart_uart_source_payload_data \main_uart_tx_fifo_source_payload_data + connect \main_uart_tx_trigger $not$ls180.v:4296$713_Y + connect \main_uart_rx_fifo_sink_valid \main_uart_uart_sink_valid + connect \main_uart_uart_sink_ready \main_uart_rx_fifo_sink_ready + connect \main_uart_rx_fifo_sink_first \main_uart_uart_sink_first + connect \main_uart_rx_fifo_sink_last \main_uart_uart_sink_last + connect \main_uart_rx_fifo_sink_payload_data \main_uart_uart_sink_payload_data + connect \main_uart_rxempty_status $not$ls180.v:4302$714_Y + connect \main_uart_rxfull_status $not$ls180.v:4303$715_Y + connect \main_uart_rxtx_w \main_uart_rx_fifo_source_payload_data + connect \main_uart_rx_fifo_source_ready $or$ls180.v:4305$717_Y + connect \main_uart_rx_trigger $not$ls180.v:4306$718_Y + connect \main_uart_irq $or$ls180.v:4329$727_Y + connect \main_uart_tx_status \main_uart_tx_trigger + connect \main_uart_rx_status \main_uart_rx_trigger + connect \main_uart_tx_fifo_syncfifo_din { \main_uart_tx_fifo_fifo_in_last \main_uart_tx_fifo_fifo_in_first \main_uart_tx_fifo_fifo_in_payload_data } + connect { \main_uart_tx_fifo_fifo_out_last \main_uart_tx_fifo_fifo_out_first \main_uart_tx_fifo_fifo_out_payload_data } \main_uart_tx_fifo_syncfifo_dout + connect \main_uart_tx_fifo_sink_ready \main_uart_tx_fifo_syncfifo_writable + connect \main_uart_tx_fifo_syncfifo_we \main_uart_tx_fifo_sink_valid + connect \main_uart_tx_fifo_fifo_in_first \main_uart_tx_fifo_sink_first + connect \main_uart_tx_fifo_fifo_in_last \main_uart_tx_fifo_sink_last + connect \main_uart_tx_fifo_fifo_in_payload_data \main_uart_tx_fifo_sink_payload_data + connect \main_uart_tx_fifo_source_valid \main_uart_tx_fifo_readable + connect \main_uart_tx_fifo_source_first \main_uart_tx_fifo_fifo_out_first + connect \main_uart_tx_fifo_source_last \main_uart_tx_fifo_fifo_out_last + connect \main_uart_tx_fifo_source_payload_data \main_uart_tx_fifo_fifo_out_payload_data + connect \main_uart_tx_fifo_re \main_uart_tx_fifo_source_ready + connect \main_uart_tx_fifo_syncfifo_re $and$ls180.v:4344$730_Y + connect \main_uart_tx_fifo_level1 $add$ls180.v:4345$731_Y + connect \main_uart_tx_fifo_wrport_dat_w \main_uart_tx_fifo_syncfifo_din + connect \main_uart_tx_fifo_wrport_we $and$ls180.v:4355$735_Y + connect \main_uart_tx_fifo_do_read $and$ls180.v:4356$736_Y + connect \main_uart_tx_fifo_rdport_adr \main_uart_tx_fifo_consume + connect \main_uart_tx_fifo_syncfifo_dout \main_uart_tx_fifo_rdport_dat_r + connect \main_uart_tx_fifo_rdport_re \main_uart_tx_fifo_do_read + connect \main_uart_tx_fifo_syncfifo_writable $ne$ls180.v:4360$737_Y + connect \main_uart_tx_fifo_syncfifo_readable $ne$ls180.v:4361$738_Y + connect \main_uart_rx_fifo_syncfifo_din { \main_uart_rx_fifo_fifo_in_last \main_uart_rx_fifo_fifo_in_first \main_uart_rx_fifo_fifo_in_payload_data } + connect { \main_uart_rx_fifo_fifo_out_last \main_uart_rx_fifo_fifo_out_first \main_uart_rx_fifo_fifo_out_payload_data } \main_uart_rx_fifo_syncfifo_dout + connect \main_uart_rx_fifo_sink_ready \main_uart_rx_fifo_syncfifo_writable + connect \main_uart_rx_fifo_syncfifo_we \main_uart_rx_fifo_sink_valid + connect \main_uart_rx_fifo_fifo_in_first \main_uart_rx_fifo_sink_first + connect \main_uart_rx_fifo_fifo_in_last \main_uart_rx_fifo_sink_last + connect \main_uart_rx_fifo_fifo_in_payload_data \main_uart_rx_fifo_sink_payload_data + connect \main_uart_rx_fifo_source_valid \main_uart_rx_fifo_readable + connect \main_uart_rx_fifo_source_first \main_uart_rx_fifo_fifo_out_first + connect \main_uart_rx_fifo_source_last \main_uart_rx_fifo_fifo_out_last + connect \main_uart_rx_fifo_source_payload_data \main_uart_rx_fifo_fifo_out_payload_data + connect \main_uart_rx_fifo_re \main_uart_rx_fifo_source_ready + connect \main_uart_rx_fifo_syncfifo_re $and$ls180.v:4374$741_Y + connect \main_uart_rx_fifo_level1 $add$ls180.v:4375$742_Y + connect \main_uart_rx_fifo_wrport_dat_w \main_uart_rx_fifo_syncfifo_din + connect \main_uart_rx_fifo_wrport_we $and$ls180.v:4385$746_Y + connect \main_uart_rx_fifo_do_read $and$ls180.v:4386$747_Y + connect \main_uart_rx_fifo_rdport_adr \main_uart_rx_fifo_consume + connect \main_uart_rx_fifo_syncfifo_dout \main_uart_rx_fifo_rdport_dat_r + connect \main_uart_rx_fifo_rdport_re \main_uart_rx_fifo_do_read + connect \main_uart_rx_fifo_syncfifo_writable $ne$ls180.v:4390$748_Y + connect \main_uart_rx_fifo_syncfifo_readable $ne$ls180.v:4391$749_Y + connect \main_gpiotristateasic0_pads_i \gpio_i + connect \main_gpiotristateasic0_pads_oe \main_gpiotristateasic0_oe_storage + connect \main_gpiotristateasic0_pads_o \main_gpiotristateasic0_out_storage + connect \main_gpiotristateasic1_pads_i \gpio_i + connect \main_gpiotristateasic1_pads_oe \main_gpiotristateasic1_oe_storage + connect \main_gpiotristateasic1_pads_o \main_gpiotristateasic1_out_storage + connect \main_spimaster0_start \main_spimaster9_start + connect \main_spimaster1_length \main_spimaster10_length + connect \main_spimaster4_mosi \main_spimaster16_storage + connect \main_spimaster13_done \main_spimaster2_done + connect \main_spimaster18_status \main_spimaster5_miso + connect \main_spimaster6_cs \main_spimaster21_storage + connect \main_spimaster7_loopback \main_spimaster23_storage + connect \main_spimaster31_clk_rise $eq$ls180.v:4415$753_Y + connect \main_spimaster32_clk_fall $eq$ls180.v:4416$755_Y + connect \main_spisdcard_start0 \main_spisdcard_start1 + connect \main_spisdcard_length0 \main_spisdcard_length1 + connect \main_spisdcard_mosi \main_spisdcard_mosi_storage + connect \main_spisdcard_done1 \main_spisdcard_done0 + connect \main_spisdcard_miso_status \main_spisdcard_miso + connect \main_spisdcard_cs \main_spisdcard_cs_storage + connect \main_spisdcard_loopback \main_spisdcard_loopback_storage + connect \main_spisdcard_clk_rise $eq$ls180.v:4473$761_Y + connect \main_spisdcard_clk_fall $eq$ls180.v:4474$763_Y + connect \main_spisdcard_clk_divider0 \main_spimaster1_storage + connect \i2c_scl \main_i2c_scl + connect \i2c_sda_oe \main_i2c_oe + connect \i2c_sda_o \main_i2c_sda0 + connect \main_i2c_sda1 \i2c_sda_i + connect \main_sdphy_status 1'0 + connect \main_sdphy_sdpads_clk $or$ls180.v:4530$771_Y + connect \main_sdphy_sdpads_cmd_oe $or$ls180.v:4531$775_Y + connect \main_sdphy_sdpads_cmd_o $or$ls180.v:4532$779_Y + connect \main_sdphy_sdpads_data_oe $or$ls180.v:4533$783_Y + connect \main_sdphy_sdpads_data_o $or$ls180.v:4534$787_Y + connect \main_sdphy_init_pads_out_ready \main_sdphy_clocker_ce + connect \main_sdphy_cmdw_pads_out_ready \main_sdphy_clocker_ce + connect \main_sdphy_cmdr_pads_out_ready \main_sdphy_clocker_ce + connect \main_sdphy_dataw_pads_out_ready \main_sdphy_clocker_ce + connect \main_sdphy_datar_pads_out_ready \main_sdphy_clocker_ce + connect \main_sdphy_init_pads_in_valid \main_sdphy_clocker_ce + connect \main_sdphy_init_pads_in_payload_cmd_i \main_sdphy_sdpads_cmd_i + connect \main_sdphy_init_pads_in_payload_data_i \main_sdphy_sdpads_data_i + connect \main_sdphy_cmdw_pads_in_valid \main_sdphy_clocker_ce + connect \main_sdphy_cmdw_pads_in_payload_cmd_i \main_sdphy_sdpads_cmd_i + connect \main_sdphy_cmdw_pads_in_payload_data_i \main_sdphy_sdpads_data_i + connect \main_sdphy_cmdr_pads_in_pads_in_valid \main_sdphy_clocker_ce + connect \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_i \main_sdphy_sdpads_cmd_i + connect \main_sdphy_cmdr_pads_in_pads_in_payload_data_i \main_sdphy_sdpads_data_i + connect \main_sdphy_dataw_pads_in_valid \main_sdphy_clocker_ce + connect \main_sdphy_dataw_pads_in_payload_cmd_i \main_sdphy_sdpads_cmd_i + connect \main_sdphy_dataw_pads_in_payload_data_i \main_sdphy_sdpads_data_i + connect \main_sdphy_datar_pads_in_pads_in_valid \main_sdphy_clocker_ce + connect \main_sdphy_datar_pads_in_pads_in_payload_cmd_i \main_sdphy_sdpads_cmd_i + connect \main_sdphy_datar_pads_in_pads_in_payload_data_i \main_sdphy_sdpads_data_i + connect \main_sdphy_clocker_stop $or$ls180.v:4555$788_Y + connect \main_sdphy_clocker_ce $and$ls180.v:4585$791_Y + connect \main_sdphy_cmdr_cmdr_pads_in_valid \main_sdphy_cmdr_pads_in_pads_in_valid + connect \main_sdphy_cmdr_pads_in_pads_in_ready \main_sdphy_cmdr_cmdr_pads_in_ready + connect \main_sdphy_cmdr_cmdr_pads_in_first \main_sdphy_cmdr_pads_in_pads_in_first + connect \main_sdphy_cmdr_cmdr_pads_in_last \main_sdphy_cmdr_pads_in_pads_in_last + connect \main_sdphy_cmdr_cmdr_pads_in_payload_clk \main_sdphy_cmdr_pads_in_pads_in_payload_clk + connect \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_i \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_i + connect \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_o \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_o + connect \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_oe \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_oe + connect \main_sdphy_cmdr_cmdr_pads_in_payload_data_i \main_sdphy_cmdr_pads_in_pads_in_payload_data_i + connect \main_sdphy_cmdr_cmdr_pads_in_payload_data_o \main_sdphy_cmdr_pads_in_pads_in_payload_data_o + connect \main_sdphy_cmdr_cmdr_pads_in_payload_data_oe \main_sdphy_cmdr_pads_in_pads_in_payload_data_oe + connect \main_sdphy_cmdr_cmdr_start $eq$ls180.v:4708$801_Y + connect \main_sdphy_cmdr_cmdr_converter_sink_valid $and$ls180.v:4709$803_Y + connect \main_sdphy_cmdr_cmdr_converter_sink_payload_data \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_i + connect \main_sdphy_cmdr_cmdr_buf_sink_valid \main_sdphy_cmdr_cmdr_source_source_valid1 + connect \main_sdphy_cmdr_cmdr_source_source_ready1 \main_sdphy_cmdr_cmdr_buf_sink_ready + connect \main_sdphy_cmdr_cmdr_buf_sink_first \main_sdphy_cmdr_cmdr_source_source_first1 + connect \main_sdphy_cmdr_cmdr_buf_sink_last \main_sdphy_cmdr_cmdr_source_source_last1 + connect \main_sdphy_cmdr_cmdr_buf_sink_payload_data \main_sdphy_cmdr_cmdr_source_source_payload_data1 + connect \main_sdphy_cmdr_cmdr_source_source_valid0 \main_sdphy_cmdr_cmdr_buf_source_valid + connect \main_sdphy_cmdr_cmdr_buf_source_ready \main_sdphy_cmdr_cmdr_source_source_ready0 + connect \main_sdphy_cmdr_cmdr_source_source_first0 \main_sdphy_cmdr_cmdr_buf_source_first + connect \main_sdphy_cmdr_cmdr_source_source_last0 \main_sdphy_cmdr_cmdr_buf_source_last + connect \main_sdphy_cmdr_cmdr_source_source_payload_data0 \main_sdphy_cmdr_cmdr_buf_source_payload_data + connect \main_sdphy_cmdr_cmdr_source_source_valid1 \main_sdphy_cmdr_cmdr_converter_source_valid + connect \main_sdphy_cmdr_cmdr_converter_source_ready \main_sdphy_cmdr_cmdr_source_source_ready1 + connect \main_sdphy_cmdr_cmdr_source_source_first1 \main_sdphy_cmdr_cmdr_converter_source_first + connect \main_sdphy_cmdr_cmdr_source_source_last1 \main_sdphy_cmdr_cmdr_converter_source_last + connect \main_sdphy_cmdr_cmdr_source_source_payload_data1 \main_sdphy_cmdr_cmdr_converter_source_payload_data + connect \main_sdphy_cmdr_cmdr_converter_sink_ready $or$ls180.v:4726$805_Y + connect \main_sdphy_cmdr_cmdr_converter_source_valid \main_sdphy_cmdr_cmdr_converter_strobe_all + connect \main_sdphy_cmdr_cmdr_converter_load_part $and$ls180.v:4728$806_Y + connect \main_sdphy_cmdr_cmdr_buf_sink_ready $or$ls180.v:4729$808_Y + connect \main_sdphy_dataw_crcr_pads_in_valid \main_sdphy_dataw_pads_in_pads_in_valid + connect \main_sdphy_dataw_pads_in_pads_in_ready \main_sdphy_dataw_crcr_pads_in_ready + connect \main_sdphy_dataw_crcr_pads_in_first \main_sdphy_dataw_pads_in_pads_in_first + connect \main_sdphy_dataw_crcr_pads_in_last \main_sdphy_dataw_pads_in_pads_in_last + connect \main_sdphy_dataw_crcr_pads_in_payload_clk \main_sdphy_dataw_pads_in_pads_in_payload_clk + connect \main_sdphy_dataw_crcr_pads_in_payload_cmd_i \main_sdphy_dataw_pads_in_pads_in_payload_cmd_i + connect \main_sdphy_dataw_crcr_pads_in_payload_cmd_o \main_sdphy_dataw_pads_in_pads_in_payload_cmd_o + connect \main_sdphy_dataw_crcr_pads_in_payload_cmd_oe \main_sdphy_dataw_pads_in_pads_in_payload_cmd_oe + connect \main_sdphy_dataw_crcr_pads_in_payload_data_i \main_sdphy_dataw_pads_in_pads_in_payload_data_i + connect \main_sdphy_dataw_crcr_pads_in_payload_data_o \main_sdphy_dataw_pads_in_pads_in_payload_data_o + connect \main_sdphy_dataw_crcr_pads_in_payload_data_oe \main_sdphy_dataw_pads_in_pads_in_payload_data_oe + connect \main_sdphy_dataw_crcr_start $eq$ls180.v:4835$823_Y + connect \main_sdphy_dataw_crcr_converter_sink_valid $and$ls180.v:4836$824_Y + connect \main_sdphy_dataw_crcr_converter_sink_payload_data \main_sdphy_dataw_crcr_pads_in_payload_data_i [0] + connect \main_sdphy_dataw_crcr_buf_sink_valid \main_sdphy_dataw_crcr_source_source_valid1 + connect \main_sdphy_dataw_crcr_source_source_ready1 \main_sdphy_dataw_crcr_buf_sink_ready + connect \main_sdphy_dataw_crcr_buf_sink_first \main_sdphy_dataw_crcr_source_source_first1 + connect \main_sdphy_dataw_crcr_buf_sink_last \main_sdphy_dataw_crcr_source_source_last1 + connect \main_sdphy_dataw_crcr_buf_sink_payload_data \main_sdphy_dataw_crcr_source_source_payload_data1 + connect \main_sdphy_dataw_crcr_source_source_valid0 \main_sdphy_dataw_crcr_buf_source_valid + connect \main_sdphy_dataw_crcr_buf_source_ready \main_sdphy_dataw_crcr_source_source_ready0 + connect \main_sdphy_dataw_crcr_source_source_first0 \main_sdphy_dataw_crcr_buf_source_first + connect \main_sdphy_dataw_crcr_source_source_last0 \main_sdphy_dataw_crcr_buf_source_last + connect \main_sdphy_dataw_crcr_source_source_payload_data0 \main_sdphy_dataw_crcr_buf_source_payload_data + connect \main_sdphy_dataw_crcr_source_source_valid1 \main_sdphy_dataw_crcr_converter_source_valid + connect \main_sdphy_dataw_crcr_converter_source_ready \main_sdphy_dataw_crcr_source_source_ready1 + connect \main_sdphy_dataw_crcr_source_source_first1 \main_sdphy_dataw_crcr_converter_source_first + connect \main_sdphy_dataw_crcr_source_source_last1 \main_sdphy_dataw_crcr_converter_source_last + connect \main_sdphy_dataw_crcr_source_source_payload_data1 \main_sdphy_dataw_crcr_converter_source_payload_data + connect \main_sdphy_dataw_crcr_converter_sink_ready $or$ls180.v:4853$826_Y + connect \main_sdphy_dataw_crcr_converter_source_valid \main_sdphy_dataw_crcr_converter_strobe_all + connect \main_sdphy_dataw_crcr_converter_load_part $and$ls180.v:4855$827_Y + connect \main_sdphy_dataw_crcr_buf_sink_ready $or$ls180.v:4856$829_Y + connect \main_sdphy_datar_datar_pads_in_valid \main_sdphy_datar_pads_in_pads_in_valid + connect \main_sdphy_datar_pads_in_pads_in_ready \main_sdphy_datar_datar_pads_in_ready + connect \main_sdphy_datar_datar_pads_in_first \main_sdphy_datar_pads_in_pads_in_first + connect \main_sdphy_datar_datar_pads_in_last \main_sdphy_datar_pads_in_pads_in_last + connect \main_sdphy_datar_datar_pads_in_payload_clk \main_sdphy_datar_pads_in_pads_in_payload_clk + connect \main_sdphy_datar_datar_pads_in_payload_cmd_i \main_sdphy_datar_pads_in_pads_in_payload_cmd_i + connect \main_sdphy_datar_datar_pads_in_payload_cmd_o \main_sdphy_datar_pads_in_pads_in_payload_cmd_o + connect \main_sdphy_datar_datar_pads_in_payload_cmd_oe \main_sdphy_datar_pads_in_pads_in_payload_cmd_oe + connect \main_sdphy_datar_datar_pads_in_payload_data_i \main_sdphy_datar_pads_in_pads_in_payload_data_i + connect \main_sdphy_datar_datar_pads_in_payload_data_o \main_sdphy_datar_pads_in_pads_in_payload_data_o + connect \main_sdphy_datar_datar_pads_in_payload_data_oe \main_sdphy_datar_pads_in_pads_in_payload_data_oe + connect \main_sdphy_datar_datar_start $eq$ls180.v:4969$838_Y + connect \main_sdphy_datar_datar_converter_sink_valid $and$ls180.v:4970$839_Y + connect \main_sdphy_datar_datar_converter_sink_payload_data \main_sdphy_datar_datar_pads_in_payload_data_i + connect \main_sdphy_datar_datar_buf_sink_valid \main_sdphy_datar_datar_source_source_valid1 + connect \main_sdphy_datar_datar_source_source_ready1 \main_sdphy_datar_datar_buf_sink_ready + connect \main_sdphy_datar_datar_buf_sink_first \main_sdphy_datar_datar_source_source_first1 + connect \main_sdphy_datar_datar_buf_sink_last \main_sdphy_datar_datar_source_source_last1 + connect \main_sdphy_datar_datar_buf_sink_payload_data \main_sdphy_datar_datar_source_source_payload_data1 + connect \main_sdphy_datar_datar_source_source_valid0 \main_sdphy_datar_datar_buf_source_valid + connect \main_sdphy_datar_datar_buf_source_ready \main_sdphy_datar_datar_source_source_ready0 + connect \main_sdphy_datar_datar_source_source_first0 \main_sdphy_datar_datar_buf_source_first + connect \main_sdphy_datar_datar_source_source_last0 \main_sdphy_datar_datar_buf_source_last + connect \main_sdphy_datar_datar_source_source_payload_data0 \main_sdphy_datar_datar_buf_source_payload_data + connect \main_sdphy_datar_datar_source_source_valid1 \main_sdphy_datar_datar_converter_source_valid + connect \main_sdphy_datar_datar_converter_source_ready \main_sdphy_datar_datar_source_source_ready1 + connect \main_sdphy_datar_datar_source_source_first1 \main_sdphy_datar_datar_converter_source_first + connect \main_sdphy_datar_datar_source_source_last1 \main_sdphy_datar_datar_converter_source_last + connect \main_sdphy_datar_datar_source_source_payload_data1 \main_sdphy_datar_datar_converter_source_payload_data + connect \main_sdphy_datar_datar_converter_sink_ready $or$ls180.v:4987$841_Y + connect \main_sdphy_datar_datar_converter_source_valid \main_sdphy_datar_datar_converter_strobe_all + connect \main_sdphy_datar_datar_converter_load_part $and$ls180.v:4989$842_Y + connect \main_sdphy_datar_datar_buf_sink_ready $or$ls180.v:4990$844_Y + connect \main_sdcore_crc16_inserter_sink_valid \main_sdcore_sink_sink_valid + connect \main_sdcore_sink_sink_ready \main_sdcore_crc16_inserter_sink_ready + connect \main_sdcore_crc16_inserter_sink_first \main_sdcore_sink_sink_first + connect \main_sdcore_crc16_inserter_sink_last \main_sdcore_sink_sink_last + connect \main_sdcore_crc16_inserter_sink_payload_data \main_sdcore_sink_sink_payload_data + connect \main_sdcore_source_source_valid \main_sdcore_crc16_checker_source_valid + connect \main_sdcore_crc16_checker_source_ready \main_sdcore_source_source_ready + connect \main_sdcore_source_source_first \main_sdcore_crc16_checker_source_first + connect \main_sdcore_source_source_last \main_sdcore_crc16_checker_source_last + connect \main_sdcore_source_source_payload_data \main_sdcore_crc16_checker_source_payload_data + connect \main_sdcore_cmd_type \main_sdcore_cmd_command_storage [1:0] + connect \main_sdcore_data_type \main_sdcore_cmd_command_storage [6:5] + connect \main_sdcore_cmd_event_status { 1'0 \main_sdcore_cmd_timeout \main_sdcore_cmd_error \main_sdcore_cmd_done } + connect \main_sdcore_data_event_status { $not$ls180.v:5106$859_Y \main_sdcore_data_timeout \main_sdcore_data_error \main_sdcore_data_done } + connect \main_sdcore_crc7_inserter_val { 2'01 \main_sdcore_cmd_command_storage [13:8] \main_sdcore_cmd_argument_storage } + connect \main_sdcore_crc7_inserter_clr 1'1 + connect \main_sdcore_crc7_inserter_enable 1'1 + connect \main_sdcore_crc7_inserter_crcreg1 { \main_sdcore_crc7_inserter_crcreg0 [5:3] $xor$ls180.v:5110$862_Y \main_sdcore_crc7_inserter_crcreg0 [1:0] $xor$ls180.v:5110$860_Y } + connect \main_sdcore_crc7_inserter_crcreg2 { \main_sdcore_crc7_inserter_crcreg1 [5:3] $xor$ls180.v:5111$865_Y \main_sdcore_crc7_inserter_crcreg1 [1:0] $xor$ls180.v:5111$863_Y } + connect \main_sdcore_crc7_inserter_crcreg3 { \main_sdcore_crc7_inserter_crcreg2 [5:3] $xor$ls180.v:5112$868_Y \main_sdcore_crc7_inserter_crcreg2 [1:0] $xor$ls180.v:5112$866_Y } + connect \main_sdcore_crc7_inserter_crcreg4 { \main_sdcore_crc7_inserter_crcreg3 [5:3] $xor$ls180.v:5113$871_Y \main_sdcore_crc7_inserter_crcreg3 [1:0] $xor$ls180.v:5113$869_Y } + connect \main_sdcore_crc7_inserter_crcreg5 { \main_sdcore_crc7_inserter_crcreg4 [5:3] $xor$ls180.v:5114$874_Y \main_sdcore_crc7_inserter_crcreg4 [1:0] $xor$ls180.v:5114$872_Y } + connect \main_sdcore_crc7_inserter_crcreg6 { \main_sdcore_crc7_inserter_crcreg5 [5:3] $xor$ls180.v:5115$877_Y \main_sdcore_crc7_inserter_crcreg5 [1:0] $xor$ls180.v:5115$875_Y } + connect \main_sdcore_crc7_inserter_crcreg7 { \main_sdcore_crc7_inserter_crcreg6 [5:3] $xor$ls180.v:5116$880_Y \main_sdcore_crc7_inserter_crcreg6 [1:0] $xor$ls180.v:5116$878_Y } + connect \main_sdcore_crc7_inserter_crcreg8 { \main_sdcore_crc7_inserter_crcreg7 [5:3] $xor$ls180.v:5117$883_Y \main_sdcore_crc7_inserter_crcreg7 [1:0] $xor$ls180.v:5117$881_Y } + connect \main_sdcore_crc7_inserter_crcreg9 { \main_sdcore_crc7_inserter_crcreg8 [5:3] $xor$ls180.v:5118$886_Y \main_sdcore_crc7_inserter_crcreg8 [1:0] $xor$ls180.v:5118$884_Y } + connect \main_sdcore_crc7_inserter_crcreg10 { \main_sdcore_crc7_inserter_crcreg9 [5:3] $xor$ls180.v:5119$889_Y \main_sdcore_crc7_inserter_crcreg9 [1:0] $xor$ls180.v:5119$887_Y } + connect \main_sdcore_crc7_inserter_crcreg11 { \main_sdcore_crc7_inserter_crcreg10 [5:3] $xor$ls180.v:5120$892_Y \main_sdcore_crc7_inserter_crcreg10 [1:0] $xor$ls180.v:5120$890_Y } + connect \main_sdcore_crc7_inserter_crcreg12 { \main_sdcore_crc7_inserter_crcreg11 [5:3] $xor$ls180.v:5121$895_Y \main_sdcore_crc7_inserter_crcreg11 [1:0] $xor$ls180.v:5121$893_Y } + connect \main_sdcore_crc7_inserter_crcreg13 { \main_sdcore_crc7_inserter_crcreg12 [5:3] $xor$ls180.v:5122$898_Y \main_sdcore_crc7_inserter_crcreg12 [1:0] $xor$ls180.v:5122$896_Y } + connect \main_sdcore_crc7_inserter_crcreg14 { \main_sdcore_crc7_inserter_crcreg13 [5:3] $xor$ls180.v:5123$901_Y \main_sdcore_crc7_inserter_crcreg13 [1:0] $xor$ls180.v:5123$899_Y } + connect \main_sdcore_crc7_inserter_crcreg15 { \main_sdcore_crc7_inserter_crcreg14 [5:3] $xor$ls180.v:5124$904_Y \main_sdcore_crc7_inserter_crcreg14 [1:0] $xor$ls180.v:5124$902_Y } + connect \main_sdcore_crc7_inserter_crcreg16 { \main_sdcore_crc7_inserter_crcreg15 [5:3] $xor$ls180.v:5125$907_Y \main_sdcore_crc7_inserter_crcreg15 [1:0] $xor$ls180.v:5125$905_Y } + connect \main_sdcore_crc7_inserter_crcreg17 { \main_sdcore_crc7_inserter_crcreg16 [5:3] $xor$ls180.v:5126$910_Y \main_sdcore_crc7_inserter_crcreg16 [1:0] $xor$ls180.v:5126$908_Y } + connect \main_sdcore_crc7_inserter_crcreg18 { \main_sdcore_crc7_inserter_crcreg17 [5:3] $xor$ls180.v:5127$913_Y \main_sdcore_crc7_inserter_crcreg17 [1:0] $xor$ls180.v:5127$911_Y } + connect \main_sdcore_crc7_inserter_crcreg19 { \main_sdcore_crc7_inserter_crcreg18 [5:3] $xor$ls180.v:5128$916_Y \main_sdcore_crc7_inserter_crcreg18 [1:0] $xor$ls180.v:5128$914_Y } + connect \main_sdcore_crc7_inserter_crcreg20 { \main_sdcore_crc7_inserter_crcreg19 [5:3] $xor$ls180.v:5129$919_Y \main_sdcore_crc7_inserter_crcreg19 [1:0] $xor$ls180.v:5129$917_Y } + connect \main_sdcore_crc7_inserter_crcreg21 { \main_sdcore_crc7_inserter_crcreg20 [5:3] $xor$ls180.v:5130$922_Y \main_sdcore_crc7_inserter_crcreg20 [1:0] $xor$ls180.v:5130$920_Y } + connect \main_sdcore_crc7_inserter_crcreg22 { \main_sdcore_crc7_inserter_crcreg21 [5:3] $xor$ls180.v:5131$925_Y \main_sdcore_crc7_inserter_crcreg21 [1:0] $xor$ls180.v:5131$923_Y } + connect \main_sdcore_crc7_inserter_crcreg23 { \main_sdcore_crc7_inserter_crcreg22 [5:3] $xor$ls180.v:5132$928_Y \main_sdcore_crc7_inserter_crcreg22 [1:0] $xor$ls180.v:5132$926_Y } + connect \main_sdcore_crc7_inserter_crcreg24 { \main_sdcore_crc7_inserter_crcreg23 [5:3] $xor$ls180.v:5133$931_Y \main_sdcore_crc7_inserter_crcreg23 [1:0] $xor$ls180.v:5133$929_Y } + connect \main_sdcore_crc7_inserter_crcreg25 { \main_sdcore_crc7_inserter_crcreg24 [5:3] $xor$ls180.v:5134$934_Y \main_sdcore_crc7_inserter_crcreg24 [1:0] $xor$ls180.v:5134$932_Y } + connect \main_sdcore_crc7_inserter_crcreg26 { \main_sdcore_crc7_inserter_crcreg25 [5:3] $xor$ls180.v:5135$937_Y \main_sdcore_crc7_inserter_crcreg25 [1:0] $xor$ls180.v:5135$935_Y } + connect \main_sdcore_crc7_inserter_crcreg27 { \main_sdcore_crc7_inserter_crcreg26 [5:3] $xor$ls180.v:5136$940_Y \main_sdcore_crc7_inserter_crcreg26 [1:0] $xor$ls180.v:5136$938_Y } + connect \main_sdcore_crc7_inserter_crcreg28 { \main_sdcore_crc7_inserter_crcreg27 [5:3] $xor$ls180.v:5137$943_Y \main_sdcore_crc7_inserter_crcreg27 [1:0] $xor$ls180.v:5137$941_Y } + connect \main_sdcore_crc7_inserter_crcreg29 { \main_sdcore_crc7_inserter_crcreg28 [5:3] $xor$ls180.v:5138$946_Y \main_sdcore_crc7_inserter_crcreg28 [1:0] $xor$ls180.v:5138$944_Y } + connect \main_sdcore_crc7_inserter_crcreg30 { \main_sdcore_crc7_inserter_crcreg29 [5:3] $xor$ls180.v:5139$949_Y \main_sdcore_crc7_inserter_crcreg29 [1:0] $xor$ls180.v:5139$947_Y } + connect \main_sdcore_crc7_inserter_crcreg31 { \main_sdcore_crc7_inserter_crcreg30 [5:3] $xor$ls180.v:5140$952_Y \main_sdcore_crc7_inserter_crcreg30 [1:0] $xor$ls180.v:5140$950_Y } + connect \main_sdcore_crc7_inserter_crcreg32 { \main_sdcore_crc7_inserter_crcreg31 [5:3] $xor$ls180.v:5141$955_Y \main_sdcore_crc7_inserter_crcreg31 [1:0] $xor$ls180.v:5141$953_Y } + connect \main_sdcore_crc7_inserter_crcreg33 { \main_sdcore_crc7_inserter_crcreg32 [5:3] $xor$ls180.v:5142$958_Y \main_sdcore_crc7_inserter_crcreg32 [1:0] $xor$ls180.v:5142$956_Y } + connect \main_sdcore_crc7_inserter_crcreg34 { \main_sdcore_crc7_inserter_crcreg33 [5:3] $xor$ls180.v:5143$961_Y \main_sdcore_crc7_inserter_crcreg33 [1:0] $xor$ls180.v:5143$959_Y } + connect \main_sdcore_crc7_inserter_crcreg35 { \main_sdcore_crc7_inserter_crcreg34 [5:3] $xor$ls180.v:5144$964_Y \main_sdcore_crc7_inserter_crcreg34 [1:0] $xor$ls180.v:5144$962_Y } + connect \main_sdcore_crc7_inserter_crcreg36 { \main_sdcore_crc7_inserter_crcreg35 [5:3] $xor$ls180.v:5145$967_Y \main_sdcore_crc7_inserter_crcreg35 [1:0] $xor$ls180.v:5145$965_Y } + connect \main_sdcore_crc7_inserter_crcreg37 { \main_sdcore_crc7_inserter_crcreg36 [5:3] $xor$ls180.v:5146$970_Y \main_sdcore_crc7_inserter_crcreg36 [1:0] $xor$ls180.v:5146$968_Y } + connect \main_sdcore_crc7_inserter_crcreg38 { \main_sdcore_crc7_inserter_crcreg37 [5:3] $xor$ls180.v:5147$973_Y \main_sdcore_crc7_inserter_crcreg37 [1:0] $xor$ls180.v:5147$971_Y } + connect \main_sdcore_crc7_inserter_crcreg39 { \main_sdcore_crc7_inserter_crcreg38 [5:3] $xor$ls180.v:5148$976_Y \main_sdcore_crc7_inserter_crcreg38 [1:0] $xor$ls180.v:5148$974_Y } + connect \main_sdcore_crc7_inserter_crcreg40 { \main_sdcore_crc7_inserter_crcreg39 [5:3] $xor$ls180.v:5149$979_Y \main_sdcore_crc7_inserter_crcreg39 [1:0] $xor$ls180.v:5149$977_Y } + connect \main_sdcore_crc16_inserter_crc0_val { \main_sdcore_crc16_inserter_sink_payload_data [4] \main_sdcore_crc16_inserter_sink_payload_data [0] } + connect \main_sdcore_crc16_inserter_crc0_clr $and$ls180.v:5159$982_Y + connect \main_sdcore_crc16_inserter_crc0_enable $and$ls180.v:5160$983_Y + connect \main_sdcore_crc16_inserter_crc1_val { \main_sdcore_crc16_inserter_sink_payload_data [5] \main_sdcore_crc16_inserter_sink_payload_data [1] } + connect \main_sdcore_crc16_inserter_crc1_clr $and$ls180.v:5162$985_Y + connect \main_sdcore_crc16_inserter_crc1_enable $and$ls180.v:5163$986_Y + connect \main_sdcore_crc16_inserter_crc2_val { \main_sdcore_crc16_inserter_sink_payload_data [6] \main_sdcore_crc16_inserter_sink_payload_data [2] } + connect \main_sdcore_crc16_inserter_crc2_clr $and$ls180.v:5165$988_Y + connect \main_sdcore_crc16_inserter_crc2_enable $and$ls180.v:5166$989_Y + connect \main_sdcore_crc16_inserter_crc3_val { \main_sdcore_crc16_inserter_sink_payload_data [7] \main_sdcore_crc16_inserter_sink_payload_data [3] } + connect \main_sdcore_crc16_inserter_crc3_clr $and$ls180.v:5168$991_Y + connect \main_sdcore_crc16_inserter_crc3_enable $and$ls180.v:5169$992_Y + connect \main_sdcore_crc16_inserter_crc0_crcreg1 { \main_sdcore_crc16_inserter_crc0_crcreg0 [14:12] $xor$ls180.v:5170$997_Y \main_sdcore_crc16_inserter_crc0_crcreg0 [10:5] $xor$ls180.v:5170$995_Y \main_sdcore_crc16_inserter_crc0_crcreg0 [3:0] $xor$ls180.v:5170$993_Y } + connect \main_sdcore_crc16_inserter_crc0_crcreg2 { \main_sdcore_crc16_inserter_crc0_crcreg1 [14:12] $xor$ls180.v:5171$1002_Y \main_sdcore_crc16_inserter_crc0_crcreg1 [10:5] $xor$ls180.v:5171$1000_Y \main_sdcore_crc16_inserter_crc0_crcreg1 [3:0] $xor$ls180.v:5171$998_Y } + connect \main_sdcore_crc16_inserter_crc1_crcreg1 { \main_sdcore_crc16_inserter_crc1_crcreg0 [14:12] $xor$ls180.v:5180$1008_Y \main_sdcore_crc16_inserter_crc1_crcreg0 [10:5] $xor$ls180.v:5180$1006_Y \main_sdcore_crc16_inserter_crc1_crcreg0 [3:0] $xor$ls180.v:5180$1004_Y } + connect \main_sdcore_crc16_inserter_crc1_crcreg2 { \main_sdcore_crc16_inserter_crc1_crcreg1 [14:12] $xor$ls180.v:5181$1013_Y \main_sdcore_crc16_inserter_crc1_crcreg1 [10:5] $xor$ls180.v:5181$1011_Y \main_sdcore_crc16_inserter_crc1_crcreg1 [3:0] $xor$ls180.v:5181$1009_Y } + connect \main_sdcore_crc16_inserter_crc2_crcreg1 { \main_sdcore_crc16_inserter_crc2_crcreg0 [14:12] $xor$ls180.v:5190$1019_Y \main_sdcore_crc16_inserter_crc2_crcreg0 [10:5] $xor$ls180.v:5190$1017_Y \main_sdcore_crc16_inserter_crc2_crcreg0 [3:0] $xor$ls180.v:5190$1015_Y } + connect \main_sdcore_crc16_inserter_crc2_crcreg2 { \main_sdcore_crc16_inserter_crc2_crcreg1 [14:12] $xor$ls180.v:5191$1024_Y \main_sdcore_crc16_inserter_crc2_crcreg1 [10:5] $xor$ls180.v:5191$1022_Y \main_sdcore_crc16_inserter_crc2_crcreg1 [3:0] $xor$ls180.v:5191$1020_Y } + connect \main_sdcore_crc16_inserter_crc3_crcreg1 { \main_sdcore_crc16_inserter_crc3_crcreg0 [14:12] $xor$ls180.v:5200$1030_Y \main_sdcore_crc16_inserter_crc3_crcreg0 [10:5] $xor$ls180.v:5200$1028_Y \main_sdcore_crc16_inserter_crc3_crcreg0 [3:0] $xor$ls180.v:5200$1026_Y } + connect \main_sdcore_crc16_inserter_crc3_crcreg2 { \main_sdcore_crc16_inserter_crc3_crcreg1 [14:12] $xor$ls180.v:5201$1035_Y \main_sdcore_crc16_inserter_crc3_crcreg1 [10:5] $xor$ls180.v:5201$1033_Y \main_sdcore_crc16_inserter_crc3_crcreg1 [3:0] $xor$ls180.v:5201$1031_Y } + connect \main_sdcore_crc16_checker_crc0_val { \main_sdcore_crc16_checker_val [7] \main_sdcore_crc16_checker_val [3] } + connect \main_sdcore_crc16_checker_crc0_enable $and$ls180.v:5297$1051_Y + connect \main_sdcore_crc16_checker_crc1_val { \main_sdcore_crc16_checker_val [6] \main_sdcore_crc16_checker_val [2] } + connect \main_sdcore_crc16_checker_crc1_enable $and$ls180.v:5307$1054_Y + connect \main_sdcore_crc16_checker_crc2_val { \main_sdcore_crc16_checker_val [5] \main_sdcore_crc16_checker_val [1] } + connect \main_sdcore_crc16_checker_crc2_enable $and$ls180.v:5317$1057_Y + connect \main_sdcore_crc16_checker_crc3_val { \main_sdcore_crc16_checker_val [4] \main_sdcore_crc16_checker_val [0] } + connect \main_sdcore_crc16_checker_crc3_enable $and$ls180.v:5327$1060_Y + connect \main_sdcore_crc16_checker_source_payload_data \main_sdcore_crc16_checker_val + connect \main_sdcore_crc16_checker_source_last \main_sdcore_crc16_checker_sink_last + connect \main_sdcore_crc16_checker_crc0_crcreg1 { \main_sdcore_crc16_checker_crc0_crcreg0 [14:12] $xor$ls180.v:5352$1072_Y \main_sdcore_crc16_checker_crc0_crcreg0 [10:5] $xor$ls180.v:5352$1070_Y \main_sdcore_crc16_checker_crc0_crcreg0 [3:0] $xor$ls180.v:5352$1068_Y } + connect \main_sdcore_crc16_checker_crc0_crcreg2 { \main_sdcore_crc16_checker_crc0_crcreg1 [14:12] $xor$ls180.v:5353$1077_Y \main_sdcore_crc16_checker_crc0_crcreg1 [10:5] $xor$ls180.v:5353$1075_Y \main_sdcore_crc16_checker_crc0_crcreg1 [3:0] $xor$ls180.v:5353$1073_Y } + connect \main_sdcore_crc16_checker_crc1_crcreg1 { \main_sdcore_crc16_checker_crc1_crcreg0 [14:12] $xor$ls180.v:5362$1083_Y \main_sdcore_crc16_checker_crc1_crcreg0 [10:5] $xor$ls180.v:5362$1081_Y \main_sdcore_crc16_checker_crc1_crcreg0 [3:0] $xor$ls180.v:5362$1079_Y } + connect \main_sdcore_crc16_checker_crc1_crcreg2 { \main_sdcore_crc16_checker_crc1_crcreg1 [14:12] $xor$ls180.v:5363$1088_Y \main_sdcore_crc16_checker_crc1_crcreg1 [10:5] $xor$ls180.v:5363$1086_Y \main_sdcore_crc16_checker_crc1_crcreg1 [3:0] $xor$ls180.v:5363$1084_Y } + connect \main_sdcore_crc16_checker_crc2_crcreg1 { \main_sdcore_crc16_checker_crc2_crcreg0 [14:12] $xor$ls180.v:5372$1094_Y \main_sdcore_crc16_checker_crc2_crcreg0 [10:5] $xor$ls180.v:5372$1092_Y \main_sdcore_crc16_checker_crc2_crcreg0 [3:0] $xor$ls180.v:5372$1090_Y } + connect \main_sdcore_crc16_checker_crc2_crcreg2 { \main_sdcore_crc16_checker_crc2_crcreg1 [14:12] $xor$ls180.v:5373$1099_Y \main_sdcore_crc16_checker_crc2_crcreg1 [10:5] $xor$ls180.v:5373$1097_Y \main_sdcore_crc16_checker_crc2_crcreg1 [3:0] $xor$ls180.v:5373$1095_Y } + connect \main_sdcore_crc16_checker_crc3_crcreg1 { \main_sdcore_crc16_checker_crc3_crcreg0 [14:12] $xor$ls180.v:5382$1105_Y \main_sdcore_crc16_checker_crc3_crcreg0 [10:5] $xor$ls180.v:5382$1103_Y \main_sdcore_crc16_checker_crc3_crcreg0 [3:0] $xor$ls180.v:5382$1101_Y } + connect \main_sdcore_crc16_checker_crc3_crcreg2 { \main_sdcore_crc16_checker_crc3_crcreg1 [14:12] $xor$ls180.v:5383$1110_Y \main_sdcore_crc16_checker_crc3_crcreg1 [10:5] $xor$ls180.v:5383$1108_Y \main_sdcore_crc16_checker_crc3_crcreg1 [3:0] $xor$ls180.v:5383$1106_Y } + connect \main_sdblock2mem_fifo_sink_valid \main_sdblock2mem_sink_sink_valid0 + connect \main_sdblock2mem_sink_sink_ready0 \main_sdblock2mem_fifo_sink_ready + connect \main_sdblock2mem_fifo_sink_first \main_sdblock2mem_sink_sink_first + connect \main_sdblock2mem_fifo_sink_last \main_sdblock2mem_sink_sink_last + connect \main_sdblock2mem_fifo_sink_payload_data \main_sdblock2mem_sink_sink_payload_data0 + connect \main_sdblock2mem_converter_sink_valid \main_sdblock2mem_fifo_source_valid + connect \main_sdblock2mem_fifo_source_ready \main_sdblock2mem_converter_sink_ready + connect \main_sdblock2mem_converter_sink_first \main_sdblock2mem_fifo_source_first + connect \main_sdblock2mem_converter_sink_last \main_sdblock2mem_fifo_source_last + connect \main_sdblock2mem_converter_sink_payload_data \main_sdblock2mem_fifo_source_payload_data + connect \main_sdblock2mem_wishbonedmawriter_sink_valid \main_sdblock2mem_source_source_valid + connect \main_sdblock2mem_source_source_ready \main_sdblock2mem_wishbonedmawriter_sink_ready + connect \main_sdblock2mem_wishbonedmawriter_sink_first \main_sdblock2mem_source_source_first + connect \main_sdblock2mem_wishbonedmawriter_sink_last \main_sdblock2mem_source_source_last + connect \main_sdblock2mem_wishbonedmawriter_sink_payload_data \main_sdblock2mem_source_source_payload_data + connect \main_sdblock2mem_fifo_syncfifo_din { \main_sdblock2mem_fifo_fifo_in_last \main_sdblock2mem_fifo_fifo_in_first \main_sdblock2mem_fifo_fifo_in_payload_data } + connect { \main_sdblock2mem_fifo_fifo_out_last \main_sdblock2mem_fifo_fifo_out_first \main_sdblock2mem_fifo_fifo_out_payload_data } \main_sdblock2mem_fifo_syncfifo_dout + connect \main_sdblock2mem_fifo_sink_ready \main_sdblock2mem_fifo_syncfifo_writable + connect \main_sdblock2mem_fifo_syncfifo_we \main_sdblock2mem_fifo_sink_valid + connect \main_sdblock2mem_fifo_fifo_in_first \main_sdblock2mem_fifo_sink_first + connect \main_sdblock2mem_fifo_fifo_in_last \main_sdblock2mem_fifo_sink_last + connect \main_sdblock2mem_fifo_fifo_in_payload_data \main_sdblock2mem_fifo_sink_payload_data + connect \main_sdblock2mem_fifo_source_valid \main_sdblock2mem_fifo_syncfifo_readable + connect \main_sdblock2mem_fifo_source_first \main_sdblock2mem_fifo_fifo_out_first + connect \main_sdblock2mem_fifo_source_last \main_sdblock2mem_fifo_fifo_out_last + connect \main_sdblock2mem_fifo_source_payload_data \main_sdblock2mem_fifo_fifo_out_payload_data + connect \main_sdblock2mem_fifo_syncfifo_re \main_sdblock2mem_fifo_source_ready + connect \main_sdblock2mem_fifo_wrport_dat_w \main_sdblock2mem_fifo_syncfifo_din + connect \main_sdblock2mem_fifo_wrport_we $and$ls180.v:5619$1140_Y + connect \main_sdblock2mem_fifo_do_read $and$ls180.v:5620$1141_Y + connect \main_sdblock2mem_fifo_rdport_adr \main_sdblock2mem_fifo_consume + connect \main_sdblock2mem_fifo_syncfifo_dout \main_sdblock2mem_fifo_rdport_dat_r + connect \main_sdblock2mem_fifo_syncfifo_writable $ne$ls180.v:5623$1142_Y + connect \main_sdblock2mem_fifo_syncfifo_readable $ne$ls180.v:5624$1143_Y + connect \main_sdblock2mem_source_source_valid \main_sdblock2mem_converter_source_valid + connect \main_sdblock2mem_converter_source_ready \main_sdblock2mem_source_source_ready + connect \main_sdblock2mem_source_source_first \main_sdblock2mem_converter_source_first + connect \main_sdblock2mem_source_source_last \main_sdblock2mem_converter_source_last + connect \main_sdblock2mem_source_source_payload_data \main_sdblock2mem_converter_source_payload_data + connect \main_sdblock2mem_converter_sink_ready $or$ls180.v:5630$1145_Y + connect \main_sdblock2mem_converter_source_valid \main_sdblock2mem_converter_strobe_all + connect \main_sdblock2mem_converter_load_part $and$ls180.v:5632$1146_Y + connect \main_interface0_bus_stb \main_sdblock2mem_sink_sink_valid1 + connect \main_interface0_bus_cyc \main_sdblock2mem_sink_sink_valid1 + connect \main_interface0_bus_we 1'1 + connect \main_interface0_bus_sel 8'11111111 + connect \main_interface0_bus_adr \main_sdblock2mem_sink_sink_payload_address + connect \main_interface0_bus_dat_w { \main_sdblock2mem_sink_sink_payload_data1 [7:0] \main_sdblock2mem_sink_sink_payload_data1 [15:8] \main_sdblock2mem_sink_sink_payload_data1 [23:16] \main_sdblock2mem_sink_sink_payload_data1 [31:24] \main_sdblock2mem_sink_sink_payload_data1 [39:32] \main_sdblock2mem_sink_sink_payload_data1 [47:40] \main_sdblock2mem_sink_sink_payload_data1 [55:48] \main_sdblock2mem_sink_sink_payload_data1 [63:56] } + connect \main_sdblock2mem_sink_sink_ready1 \main_interface0_bus_ack + connect \main_sdblock2mem_wishbonedmawriter_base \main_sdblock2mem_wishbonedmawriter_base_storage [34:3] + connect \main_sdblock2mem_wishbonedmawriter_length { 3'000 \main_sdblock2mem_wishbonedmawriter_length_storage [31:3] } + connect \main_sdblock2mem_wishbonedmawriter_reset $not$ls180.v:5642$1147_Y + connect \main_sdmem2block_converter_sink_valid \main_sdmem2block_dma_source_valid + connect \main_sdmem2block_dma_source_ready \main_sdmem2block_converter_sink_ready + connect \main_sdmem2block_converter_sink_first \main_sdmem2block_dma_source_first + connect \main_sdmem2block_converter_sink_last \main_sdmem2block_dma_source_last + connect \main_sdmem2block_converter_sink_payload_data \main_sdmem2block_dma_source_payload_data + connect \main_sdmem2block_fifo_sink_valid \main_sdmem2block_source_source_valid1 + connect \main_sdmem2block_source_source_ready1 \main_sdmem2block_fifo_sink_ready + connect \main_sdmem2block_fifo_sink_first \main_sdmem2block_source_source_first1 + connect \main_sdmem2block_fifo_sink_last \main_sdmem2block_source_source_last1 + connect \main_sdmem2block_fifo_sink_payload_data \main_sdmem2block_source_source_payload_data1 + connect \main_sdmem2block_source_source_valid0 \main_sdmem2block_fifo_source_valid + connect \main_sdmem2block_fifo_source_ready \main_sdmem2block_source_source_ready0 + connect \main_sdmem2block_source_source_first0 \main_sdmem2block_fifo_source_first + connect \main_sdmem2block_source_source_last0 \main_sdmem2block_fifo_source_last + connect \main_sdmem2block_source_source_payload_data0 \main_sdmem2block_fifo_source_payload_data + connect \main_sdmem2block_dma_base \main_sdmem2block_dma_base_storage [34:3] + connect \main_sdmem2block_dma_length { 3'000 \main_sdmem2block_dma_length_storage [31:3] } + connect \main_sdmem2block_dma_offset_status \main_sdmem2block_dma_offset + connect \main_sdmem2block_dma_reset $not$ls180.v:5701$1154_Y + connect \main_sdmem2block_source_source_valid1 \main_sdmem2block_converter_source_valid + connect \main_sdmem2block_converter_source_ready \main_sdmem2block_source_source_ready1 + connect \main_sdmem2block_source_source_first1 \main_sdmem2block_converter_source_first + connect \main_sdmem2block_source_source_last1 \main_sdmem2block_converter_source_last + connect \main_sdmem2block_source_source_payload_data1 \main_sdmem2block_converter_source_payload_data + connect \main_sdmem2block_converter_first $eq$ls180.v:5782$1162_Y + connect \main_sdmem2block_converter_last $eq$ls180.v:5783$1163_Y + connect \main_sdmem2block_converter_source_valid \main_sdmem2block_converter_sink_valid + connect \main_sdmem2block_converter_source_first $and$ls180.v:5785$1164_Y + connect \main_sdmem2block_converter_source_last $and$ls180.v:5786$1165_Y + connect \main_sdmem2block_converter_sink_ready $and$ls180.v:5787$1166_Y + connect \main_sdmem2block_converter_source_payload_valid_token_count \main_sdmem2block_converter_last + connect \main_sdmem2block_fifo_syncfifo_din { \main_sdmem2block_fifo_fifo_in_last \main_sdmem2block_fifo_fifo_in_first \main_sdmem2block_fifo_fifo_in_payload_data } + connect { \main_sdmem2block_fifo_fifo_out_last \main_sdmem2block_fifo_fifo_out_first \main_sdmem2block_fifo_fifo_out_payload_data } \main_sdmem2block_fifo_syncfifo_dout + connect \main_sdmem2block_fifo_sink_ready \main_sdmem2block_fifo_syncfifo_writable + connect \main_sdmem2block_fifo_syncfifo_we \main_sdmem2block_fifo_sink_valid + connect \main_sdmem2block_fifo_fifo_in_first \main_sdmem2block_fifo_sink_first + connect \main_sdmem2block_fifo_fifo_in_last \main_sdmem2block_fifo_sink_last + connect \main_sdmem2block_fifo_fifo_in_payload_data \main_sdmem2block_fifo_sink_payload_data + connect \main_sdmem2block_fifo_source_valid \main_sdmem2block_fifo_syncfifo_readable + connect \main_sdmem2block_fifo_source_first \main_sdmem2block_fifo_fifo_out_first + connect \main_sdmem2block_fifo_source_last \main_sdmem2block_fifo_fifo_out_last + connect \main_sdmem2block_fifo_source_payload_data \main_sdmem2block_fifo_fifo_out_payload_data + connect \main_sdmem2block_fifo_syncfifo_re \main_sdmem2block_fifo_source_ready + connect \main_sdmem2block_fifo_wrport_dat_w \main_sdmem2block_fifo_syncfifo_din + connect \main_sdmem2block_fifo_wrport_we $and$ls180.v:5839$1171_Y + connect \main_sdmem2block_fifo_do_read $and$ls180.v:5840$1172_Y + connect \main_sdmem2block_fifo_rdport_adr \main_sdmem2block_fifo_consume + connect \main_sdmem2block_fifo_syncfifo_dout \main_sdmem2block_fifo_rdport_dat_r + connect \main_sdmem2block_fifo_syncfifo_writable $ne$ls180.v:5843$1173_Y + connect \main_sdmem2block_fifo_syncfifo_readable $ne$ls180.v:5844$1174_Y + connect \builder_shared_adr \builder_comb_rhs_array_muxed24 [29:0] + connect \builder_shared_dat_w \builder_comb_rhs_array_muxed25 [31:0] + connect \builder_shared_sel \builder_comb_rhs_array_muxed26 [3:0] + connect \builder_shared_cyc \builder_comb_rhs_array_muxed27 + connect \builder_shared_stb \builder_comb_rhs_array_muxed28 + connect \builder_shared_we \builder_comb_rhs_array_muxed29 + connect \builder_shared_cti \builder_comb_rhs_array_muxed30 + connect \builder_shared_bte \builder_comb_rhs_array_muxed31 + connect \main_libresocsim_libresoc_ibus_dat_r { 32'00000000000000000000000000000000 \builder_shared_dat_r } + connect \main_libresocsim_libresoc_dbus_dat_r { 32'00000000000000000000000000000000 \builder_shared_dat_r } + connect \main_libresocsim_libresoc_jtag_wb_dat_r { 32'00000000000000000000000000000000 \builder_shared_dat_r } + connect \main_interface0_bus_dat_r { 32'00000000000000000000000000000000 \builder_shared_dat_r } + connect \main_interface1_bus_dat_r { 32'00000000000000000000000000000000 \builder_shared_dat_r } + connect \main_libresocsim_libresoc_ibus_ack $and$ls180.v:5895$1180_Y + connect \main_libresocsim_libresoc_dbus_ack $and$ls180.v:5896$1182_Y + connect \main_libresocsim_libresoc_jtag_wb_ack $and$ls180.v:5897$1184_Y + connect \main_interface0_bus_ack $and$ls180.v:5898$1186_Y + connect \main_interface1_bus_ack $and$ls180.v:5899$1188_Y + connect \main_libresocsim_libresoc_ibus_err $and$ls180.v:5900$1190_Y + connect \main_libresocsim_libresoc_dbus_err $and$ls180.v:5901$1192_Y + connect \main_libresocsim_libresoc_jtag_wb_err $and$ls180.v:5902$1194_Y + connect \main_interface0_bus_err $and$ls180.v:5903$1196_Y + connect \main_interface1_bus_err $and$ls180.v:5904$1198_Y + connect \builder_request { \main_interface1_bus_cyc \main_interface0_bus_cyc \main_libresocsim_libresoc_jtag_wb_cyc \main_libresocsim_libresoc_dbus_cyc \main_libresocsim_libresoc_ibus_cyc } + connect \main_libresocsim_ram_bus_adr \builder_shared_adr + connect \main_libresocsim_ram_bus_dat_w { 32'00000000000000000000000000000000 \builder_shared_dat_w } + connect \main_libresocsim_ram_bus_sel { 4'0000 \builder_shared_sel } + connect \main_libresocsim_ram_bus_stb \builder_shared_stb + connect \main_libresocsim_ram_bus_we \builder_shared_we + connect \main_libresocsim_ram_bus_cti \builder_shared_cti + connect \main_libresocsim_ram_bus_bte \builder_shared_bte + connect \main_interface0_ram_bus_adr \builder_shared_adr + connect \main_interface0_ram_bus_dat_w { 32'00000000000000000000000000000000 \builder_shared_dat_w } + connect \main_interface0_ram_bus_sel { 4'0000 \builder_shared_sel } + connect \main_interface0_ram_bus_stb \builder_shared_stb + connect \main_interface0_ram_bus_we \builder_shared_we + connect \main_interface0_ram_bus_cti \builder_shared_cti + connect \main_interface0_ram_bus_bte \builder_shared_bte + connect \main_interface1_ram_bus_adr \builder_shared_adr + connect \main_interface1_ram_bus_dat_w { 32'00000000000000000000000000000000 \builder_shared_dat_w } + connect \main_interface1_ram_bus_sel { 4'0000 \builder_shared_sel } + connect \main_interface1_ram_bus_stb \builder_shared_stb + connect \main_interface1_ram_bus_we \builder_shared_we + connect \main_interface1_ram_bus_cti \builder_shared_cti + connect \main_interface1_ram_bus_bte \builder_shared_bte + connect \main_interface2_ram_bus_adr \builder_shared_adr + connect \main_interface2_ram_bus_dat_w { 32'00000000000000000000000000000000 \builder_shared_dat_w } + connect \main_interface2_ram_bus_sel { 4'0000 \builder_shared_sel } + connect \main_interface2_ram_bus_stb \builder_shared_stb + connect \main_interface2_ram_bus_we \builder_shared_we + connect \main_interface2_ram_bus_cti \builder_shared_cti + connect \main_interface2_ram_bus_bte \builder_shared_bte + connect \main_interface3_ram_bus_adr \builder_shared_adr + connect \main_interface3_ram_bus_dat_w { 32'00000000000000000000000000000000 \builder_shared_dat_w } + connect \main_interface3_ram_bus_sel { 4'0000 \builder_shared_sel } + connect \main_interface3_ram_bus_stb \builder_shared_stb + connect \main_interface3_ram_bus_we \builder_shared_we + connect \main_interface3_ram_bus_cti \builder_shared_cti + connect \main_interface3_ram_bus_bte \builder_shared_bte + connect \main_interface0_converted_interface_adr \builder_shared_adr + connect \main_interface0_converted_interface_dat_w { 32'00000000000000000000000000000000 \builder_shared_dat_w } + connect \main_interface0_converted_interface_sel { 4'0000 \builder_shared_sel } + connect \main_interface0_converted_interface_stb \builder_shared_stb + connect \main_interface0_converted_interface_we \builder_shared_we + connect \main_interface0_converted_interface_cti \builder_shared_cti + connect \main_interface0_converted_interface_bte \builder_shared_bte + connect \main_interface1_converted_interface_adr \builder_shared_adr + connect \main_interface1_converted_interface_dat_w { 32'00000000000000000000000000000000 \builder_shared_dat_w } + connect \main_interface1_converted_interface_sel { 4'0000 \builder_shared_sel } + connect \main_interface1_converted_interface_stb \builder_shared_stb + connect \main_interface1_converted_interface_we \builder_shared_we + connect \main_interface1_converted_interface_cti \builder_shared_cti + connect \main_interface1_converted_interface_bte \builder_shared_bte + connect \main_libresocsim_libresoc_interface0_adr \builder_shared_adr [28:0] + connect \main_libresocsim_libresoc_interface0_dat_w { 32'00000000000000000000000000000000 \builder_shared_dat_w } + connect \main_libresocsim_libresoc_interface0_sel { 4'0000 \builder_shared_sel } + connect \main_libresocsim_libresoc_interface0_stb \builder_shared_stb + connect \main_libresocsim_libresoc_interface0_we \builder_shared_we + connect \main_libresocsim_libresoc_interface0_cti \builder_shared_cti + connect \main_libresocsim_libresoc_interface0_bte \builder_shared_bte + connect \main_libresocsim_libresoc_interface1_adr \builder_shared_adr [28:0] + connect \main_libresocsim_libresoc_interface1_dat_w { 32'00000000000000000000000000000000 \builder_shared_dat_w } + connect \main_libresocsim_libresoc_interface1_sel { 4'0000 \builder_shared_sel } + connect \main_libresocsim_libresoc_interface1_stb \builder_shared_stb + connect \main_libresocsim_libresoc_interface1_we \builder_shared_we + connect \main_libresocsim_libresoc_interface1_cti \builder_shared_cti + connect \main_libresocsim_libresoc_interface1_bte \builder_shared_bte + connect \main_libresocsim_libresoc_interface2_adr \builder_shared_adr [28:0] + connect \main_libresocsim_libresoc_interface2_dat_w { 32'00000000000000000000000000000000 \builder_shared_dat_w } + connect \main_libresocsim_libresoc_interface2_sel { 4'0000 \builder_shared_sel } + connect \main_libresocsim_libresoc_interface2_stb \builder_shared_stb + connect \main_libresocsim_libresoc_interface2_we \builder_shared_we + connect \main_libresocsim_libresoc_interface2_cti \builder_shared_cti + connect \main_libresocsim_libresoc_interface2_bte \builder_shared_bte + connect \main_libresocsim_libresoc_interface3_adr \builder_shared_adr [28:0] + connect \main_libresocsim_libresoc_interface3_dat_w { 32'00000000000000000000000000000000 \builder_shared_dat_w } + connect \main_libresocsim_libresoc_interface3_sel { 4'0000 \builder_shared_sel } + connect \main_libresocsim_libresoc_interface3_stb \builder_shared_stb + connect \main_libresocsim_libresoc_interface3_we \builder_shared_we + connect \main_libresocsim_libresoc_interface3_cti \builder_shared_cti + connect \main_libresocsim_libresoc_interface3_bte \builder_shared_bte + connect \main_socbushandler_converted_interface_adr \builder_shared_adr + connect \main_socbushandler_converted_interface_dat_w { 32'00000000000000000000000000000000 \builder_shared_dat_w } + connect \main_socbushandler_converted_interface_sel { 4'0000 \builder_shared_sel } + connect \main_socbushandler_converted_interface_stb \builder_shared_stb + connect \main_socbushandler_converted_interface_we \builder_shared_we + connect \main_socbushandler_converted_interface_cti \builder_shared_cti + connect \main_socbushandler_converted_interface_bte \builder_shared_bte + connect \builder_libresocsim_converted_interface_adr \builder_shared_adr + connect \builder_libresocsim_converted_interface_dat_w { 32'00000000000000000000000000000000 \builder_shared_dat_w } + connect \builder_libresocsim_converted_interface_sel { 4'0000 \builder_shared_sel } + connect \builder_libresocsim_converted_interface_stb \builder_shared_stb + connect \builder_libresocsim_converted_interface_we \builder_shared_we + connect \builder_libresocsim_converted_interface_cti \builder_shared_cti + connect \builder_libresocsim_converted_interface_bte \builder_shared_bte + connect \main_libresocsim_ram_bus_cyc $and$ls180.v:6013$1213_Y + connect \main_interface0_ram_bus_cyc $and$ls180.v:6014$1214_Y + connect \main_interface1_ram_bus_cyc $and$ls180.v:6015$1215_Y + connect \main_interface2_ram_bus_cyc $and$ls180.v:6016$1216_Y + connect \main_interface3_ram_bus_cyc $and$ls180.v:6017$1217_Y + connect \main_interface0_converted_interface_cyc $and$ls180.v:6018$1218_Y + connect \main_interface1_converted_interface_cyc $and$ls180.v:6019$1219_Y + connect \main_libresocsim_libresoc_interface0_cyc $and$ls180.v:6020$1220_Y + connect \main_libresocsim_libresoc_interface1_cyc $and$ls180.v:6021$1221_Y + connect \main_libresocsim_libresoc_interface2_cyc $and$ls180.v:6022$1222_Y + connect \main_libresocsim_libresoc_interface3_cyc $and$ls180.v:6023$1223_Y + connect \main_socbushandler_converted_interface_cyc $and$ls180.v:6024$1224_Y + connect \builder_libresocsim_converted_interface_cyc $and$ls180.v:6025$1225_Y + connect \builder_shared_err $or$ls180.v:6026$1237_Y + connect \builder_wait $and$ls180.v:6027$1240_Y + connect \builder_done $eq$ls180.v:6040$1279_Y + connect \builder_csrbank0_sel $eq$ls180.v:6041$1280_Y + connect \builder_csrbank0_reset0_r \builder_interface0_bank_bus_dat_w [0] + connect \builder_csrbank0_reset0_re $and$ls180.v:6043$1283_Y + connect \builder_csrbank0_reset0_we $and$ls180.v:6044$1287_Y + connect \builder_csrbank0_scratch3_r \builder_interface0_bank_bus_dat_w + connect \builder_csrbank0_scratch3_re $and$ls180.v:6046$1290_Y + connect \builder_csrbank0_scratch3_we $and$ls180.v:6047$1294_Y + connect \builder_csrbank0_scratch2_r \builder_interface0_bank_bus_dat_w + connect \builder_csrbank0_scratch2_re $and$ls180.v:6049$1297_Y + connect \builder_csrbank0_scratch2_we $and$ls180.v:6050$1301_Y + connect \builder_csrbank0_scratch1_r \builder_interface0_bank_bus_dat_w + connect \builder_csrbank0_scratch1_re $and$ls180.v:6052$1304_Y + connect \builder_csrbank0_scratch1_we $and$ls180.v:6053$1308_Y + connect \builder_csrbank0_scratch0_r \builder_interface0_bank_bus_dat_w + connect \builder_csrbank0_scratch0_re $and$ls180.v:6055$1311_Y + connect \builder_csrbank0_scratch0_we $and$ls180.v:6056$1315_Y + connect \builder_csrbank0_bus_errors3_r \builder_interface0_bank_bus_dat_w + connect \builder_csrbank0_bus_errors3_re $and$ls180.v:6058$1318_Y + connect \builder_csrbank0_bus_errors3_we $and$ls180.v:6059$1322_Y + connect \builder_csrbank0_bus_errors2_r \builder_interface0_bank_bus_dat_w + connect \builder_csrbank0_bus_errors2_re $and$ls180.v:6061$1325_Y + connect \builder_csrbank0_bus_errors2_we $and$ls180.v:6062$1329_Y + connect \builder_csrbank0_bus_errors1_r \builder_interface0_bank_bus_dat_w + connect \builder_csrbank0_bus_errors1_re $and$ls180.v:6064$1332_Y + connect \builder_csrbank0_bus_errors1_we $and$ls180.v:6065$1336_Y + connect \builder_csrbank0_bus_errors0_r \builder_interface0_bank_bus_dat_w + connect \builder_csrbank0_bus_errors0_re $and$ls180.v:6067$1339_Y + connect \builder_csrbank0_bus_errors0_we $and$ls180.v:6068$1343_Y + connect \builder_csrbank0_reset0_w \main_libresocsim_reset_storage + connect \builder_csrbank0_scratch3_w \main_libresocsim_scratch_storage [31:24] + connect \builder_csrbank0_scratch2_w \main_libresocsim_scratch_storage [23:16] + connect \builder_csrbank0_scratch1_w \main_libresocsim_scratch_storage [15:8] + connect \builder_csrbank0_scratch0_w \main_libresocsim_scratch_storage [7:0] + connect \builder_csrbank0_bus_errors3_w \main_libresocsim_bus_errors_status [31:24] + connect \builder_csrbank0_bus_errors2_w \main_libresocsim_bus_errors_status [23:16] + connect \builder_csrbank0_bus_errors1_w \main_libresocsim_bus_errors_status [15:8] + connect \builder_csrbank0_bus_errors0_w \main_libresocsim_bus_errors_status [7:0] + connect \main_libresocsim_bus_errors_we \builder_csrbank0_bus_errors0_we + connect \builder_csrbank1_sel $eq$ls180.v:6079$1344_Y + connect \builder_csrbank1_oe1_r \builder_interface1_bank_bus_dat_w + connect \builder_csrbank1_oe1_re $and$ls180.v:6081$1347_Y + connect \builder_csrbank1_oe1_we $and$ls180.v:6082$1351_Y + connect \builder_csrbank1_oe0_r \builder_interface1_bank_bus_dat_w + connect \builder_csrbank1_oe0_re $and$ls180.v:6084$1354_Y + connect \builder_csrbank1_oe0_we $and$ls180.v:6085$1358_Y + connect \builder_csrbank1_in1_r \builder_interface1_bank_bus_dat_w + connect \builder_csrbank1_in1_re $and$ls180.v:6087$1361_Y + connect \builder_csrbank1_in1_we $and$ls180.v:6088$1365_Y + connect \builder_csrbank1_in0_r \builder_interface1_bank_bus_dat_w + connect \builder_csrbank1_in0_re $and$ls180.v:6090$1368_Y + connect \builder_csrbank1_in0_we $and$ls180.v:6091$1372_Y + connect \builder_csrbank1_out1_r \builder_interface1_bank_bus_dat_w + connect \builder_csrbank1_out1_re $and$ls180.v:6093$1375_Y + connect \builder_csrbank1_out1_we $and$ls180.v:6094$1379_Y + connect \builder_csrbank1_out0_r \builder_interface1_bank_bus_dat_w + connect \builder_csrbank1_out0_re $and$ls180.v:6096$1382_Y + connect \builder_csrbank1_out0_we $and$ls180.v:6097$1386_Y + connect \builder_csrbank1_oe1_w \main_gpiotristateasic1_oe_storage [15:8] + connect \builder_csrbank1_oe0_w \main_gpiotristateasic1_oe_storage [7:0] + connect \builder_csrbank1_in1_w \main_gpiotristateasic1_status [15:8] + connect \builder_csrbank1_in0_w \main_gpiotristateasic1_status [7:0] + connect \main_gpiotristateasic1_we \builder_csrbank1_in0_we + connect \builder_csrbank1_out1_w \main_gpiotristateasic1_out_storage [15:8] + connect \builder_csrbank1_out0_w \main_gpiotristateasic1_out_storage [7:0] + connect \builder_csrbank2_sel $eq$ls180.v:6105$1387_Y + connect \builder_csrbank2_w0_r \builder_interface2_bank_bus_dat_w [2:0] + connect \builder_csrbank2_w0_re $and$ls180.v:6107$1390_Y + connect \builder_csrbank2_w0_we $and$ls180.v:6108$1394_Y + connect \builder_csrbank2_r_r \builder_interface2_bank_bus_dat_w [0] + connect \builder_csrbank2_r_re $and$ls180.v:6110$1397_Y + connect \builder_csrbank2_r_we $and$ls180.v:6111$1401_Y + connect \main_i2c_scl \main_i2c_storage [0] + connect \main_i2c_oe \main_i2c_storage [1] + connect \main_i2c_sda0 \main_i2c_storage [2] + connect \builder_csrbank2_w0_w \main_i2c_storage + connect \main_i2c_status \main_i2c_sda1 + connect \builder_csrbank2_r_w \main_i2c_status + connect \main_i2c_we \builder_csrbank2_r_we + connect \builder_csrbank3_sel $eq$ls180.v:6119$1402_Y + connect \builder_csrbank3_enable0_r \builder_interface3_bank_bus_dat_w [0] + connect \builder_csrbank3_enable0_re $and$ls180.v:6121$1405_Y + connect \builder_csrbank3_enable0_we $and$ls180.v:6122$1409_Y + connect \builder_csrbank3_width3_r \builder_interface3_bank_bus_dat_w + connect \builder_csrbank3_width3_re $and$ls180.v:6124$1412_Y + connect \builder_csrbank3_width3_we $and$ls180.v:6125$1416_Y + connect \builder_csrbank3_width2_r \builder_interface3_bank_bus_dat_w + connect \builder_csrbank3_width2_re $and$ls180.v:6127$1419_Y + connect \builder_csrbank3_width2_we $and$ls180.v:6128$1423_Y + connect \builder_csrbank3_width1_r \builder_interface3_bank_bus_dat_w + connect \builder_csrbank3_width1_re $and$ls180.v:6130$1426_Y + connect \builder_csrbank3_width1_we $and$ls180.v:6131$1430_Y + connect \builder_csrbank3_width0_r \builder_interface3_bank_bus_dat_w + connect \builder_csrbank3_width0_re $and$ls180.v:6133$1433_Y + connect \builder_csrbank3_width0_we $and$ls180.v:6134$1437_Y + connect \builder_csrbank3_period3_r \builder_interface3_bank_bus_dat_w + connect \builder_csrbank3_period3_re $and$ls180.v:6136$1440_Y + connect \builder_csrbank3_period3_we $and$ls180.v:6137$1444_Y + connect \builder_csrbank3_period2_r \builder_interface3_bank_bus_dat_w + connect \builder_csrbank3_period2_re $and$ls180.v:6139$1447_Y + connect \builder_csrbank3_period2_we $and$ls180.v:6140$1451_Y + connect \builder_csrbank3_period1_r \builder_interface3_bank_bus_dat_w + connect \builder_csrbank3_period1_re $and$ls180.v:6142$1454_Y + connect \builder_csrbank3_period1_we $and$ls180.v:6143$1458_Y + connect \builder_csrbank3_period0_r \builder_interface3_bank_bus_dat_w + connect \builder_csrbank3_period0_re $and$ls180.v:6145$1461_Y + connect \builder_csrbank3_period0_we $and$ls180.v:6146$1465_Y + connect \builder_csrbank3_enable0_w \main_pwm0_enable_storage + connect \builder_csrbank3_width3_w \main_pwm0_width_storage [31:24] + connect \builder_csrbank3_width2_w \main_pwm0_width_storage [23:16] + connect \builder_csrbank3_width1_w \main_pwm0_width_storage [15:8] + connect \builder_csrbank3_width0_w \main_pwm0_width_storage [7:0] + connect \builder_csrbank3_period3_w \main_pwm0_period_storage [31:24] + connect \builder_csrbank3_period2_w \main_pwm0_period_storage [23:16] + connect \builder_csrbank3_period1_w \main_pwm0_period_storage [15:8] + connect \builder_csrbank3_period0_w \main_pwm0_period_storage [7:0] + connect \builder_csrbank4_sel $eq$ls180.v:6156$1466_Y + connect \builder_csrbank4_enable0_r \builder_interface4_bank_bus_dat_w [0] + connect \builder_csrbank4_enable0_re $and$ls180.v:6158$1469_Y + connect \builder_csrbank4_enable0_we $and$ls180.v:6159$1473_Y + connect \builder_csrbank4_width3_r \builder_interface4_bank_bus_dat_w + connect \builder_csrbank4_width3_re $and$ls180.v:6161$1476_Y + connect \builder_csrbank4_width3_we $and$ls180.v:6162$1480_Y + connect \builder_csrbank4_width2_r \builder_interface4_bank_bus_dat_w + connect \builder_csrbank4_width2_re $and$ls180.v:6164$1483_Y + connect \builder_csrbank4_width2_we $and$ls180.v:6165$1487_Y + connect \builder_csrbank4_width1_r \builder_interface4_bank_bus_dat_w + connect \builder_csrbank4_width1_re $and$ls180.v:6167$1490_Y + connect \builder_csrbank4_width1_we $and$ls180.v:6168$1494_Y + connect \builder_csrbank4_width0_r \builder_interface4_bank_bus_dat_w + connect \builder_csrbank4_width0_re $and$ls180.v:6170$1497_Y + connect \builder_csrbank4_width0_we $and$ls180.v:6171$1501_Y + connect \builder_csrbank4_period3_r \builder_interface4_bank_bus_dat_w + connect \builder_csrbank4_period3_re $and$ls180.v:6173$1504_Y + connect \builder_csrbank4_period3_we $and$ls180.v:6174$1508_Y + connect \builder_csrbank4_period2_r \builder_interface4_bank_bus_dat_w + connect \builder_csrbank4_period2_re $and$ls180.v:6176$1511_Y + connect \builder_csrbank4_period2_we $and$ls180.v:6177$1515_Y + connect \builder_csrbank4_period1_r \builder_interface4_bank_bus_dat_w + connect \builder_csrbank4_period1_re $and$ls180.v:6179$1518_Y + connect \builder_csrbank4_period1_we $and$ls180.v:6180$1522_Y + connect \builder_csrbank4_period0_r \builder_interface4_bank_bus_dat_w + connect \builder_csrbank4_period0_re $and$ls180.v:6182$1525_Y + connect \builder_csrbank4_period0_we $and$ls180.v:6183$1529_Y + connect \builder_csrbank4_enable0_w \main_pwm1_enable_storage + connect \builder_csrbank4_width3_w \main_pwm1_width_storage [31:24] + connect \builder_csrbank4_width2_w \main_pwm1_width_storage [23:16] + connect \builder_csrbank4_width1_w \main_pwm1_width_storage [15:8] + connect \builder_csrbank4_width0_w \main_pwm1_width_storage [7:0] + connect \builder_csrbank4_period3_w \main_pwm1_period_storage [31:24] + connect \builder_csrbank4_period2_w \main_pwm1_period_storage [23:16] + connect \builder_csrbank4_period1_w \main_pwm1_period_storage [15:8] + connect \builder_csrbank4_period0_w \main_pwm1_period_storage [7:0] + connect \builder_csrbank5_sel $eq$ls180.v:6193$1530_Y + connect \builder_csrbank5_dma_base7_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_dma_base7_re $and$ls180.v:6195$1533_Y + connect \builder_csrbank5_dma_base7_we $and$ls180.v:6196$1537_Y + connect \builder_csrbank5_dma_base6_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_dma_base6_re $and$ls180.v:6198$1540_Y + connect \builder_csrbank5_dma_base6_we $and$ls180.v:6199$1544_Y + connect \builder_csrbank5_dma_base5_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_dma_base5_re $and$ls180.v:6201$1547_Y + connect \builder_csrbank5_dma_base5_we $and$ls180.v:6202$1551_Y + connect \builder_csrbank5_dma_base4_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_dma_base4_re $and$ls180.v:6204$1554_Y + connect \builder_csrbank5_dma_base4_we $and$ls180.v:6205$1558_Y + connect \builder_csrbank5_dma_base3_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_dma_base3_re $and$ls180.v:6207$1561_Y + connect \builder_csrbank5_dma_base3_we $and$ls180.v:6208$1565_Y + connect \builder_csrbank5_dma_base2_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_dma_base2_re $and$ls180.v:6210$1568_Y + connect \builder_csrbank5_dma_base2_we $and$ls180.v:6211$1572_Y + connect \builder_csrbank5_dma_base1_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_dma_base1_re $and$ls180.v:6213$1575_Y + connect \builder_csrbank5_dma_base1_we $and$ls180.v:6214$1579_Y + connect \builder_csrbank5_dma_base0_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_dma_base0_re $and$ls180.v:6216$1582_Y + connect \builder_csrbank5_dma_base0_we $and$ls180.v:6217$1586_Y + connect \builder_csrbank5_dma_length3_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_dma_length3_re $and$ls180.v:6219$1589_Y + connect \builder_csrbank5_dma_length3_we $and$ls180.v:6220$1593_Y + connect \builder_csrbank5_dma_length2_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_dma_length2_re $and$ls180.v:6222$1596_Y + connect \builder_csrbank5_dma_length2_we $and$ls180.v:6223$1600_Y + connect \builder_csrbank5_dma_length1_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_dma_length1_re $and$ls180.v:6225$1603_Y + connect \builder_csrbank5_dma_length1_we $and$ls180.v:6226$1607_Y + connect \builder_csrbank5_dma_length0_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_dma_length0_re $and$ls180.v:6228$1610_Y + connect \builder_csrbank5_dma_length0_we $and$ls180.v:6229$1614_Y + connect \builder_csrbank5_dma_enable0_r \builder_interface5_bank_bus_dat_w [0] + connect \builder_csrbank5_dma_enable0_re $and$ls180.v:6231$1617_Y + connect \builder_csrbank5_dma_enable0_we $and$ls180.v:6232$1621_Y + connect \builder_csrbank5_dma_done_r \builder_interface5_bank_bus_dat_w [0] + connect \builder_csrbank5_dma_done_re $and$ls180.v:6234$1624_Y + connect \builder_csrbank5_dma_done_we $and$ls180.v:6235$1628_Y + connect \builder_csrbank5_dma_loop0_r \builder_interface5_bank_bus_dat_w [0] + connect \builder_csrbank5_dma_loop0_re $and$ls180.v:6237$1631_Y + connect \builder_csrbank5_dma_loop0_we $and$ls180.v:6238$1635_Y + connect \builder_csrbank5_dma_base7_w \main_sdblock2mem_wishbonedmawriter_base_storage [63:56] + connect \builder_csrbank5_dma_base6_w \main_sdblock2mem_wishbonedmawriter_base_storage [55:48] + connect \builder_csrbank5_dma_base5_w \main_sdblock2mem_wishbonedmawriter_base_storage [47:40] + connect \builder_csrbank5_dma_base4_w \main_sdblock2mem_wishbonedmawriter_base_storage [39:32] + connect \builder_csrbank5_dma_base3_w \main_sdblock2mem_wishbonedmawriter_base_storage [31:24] + connect \builder_csrbank5_dma_base2_w \main_sdblock2mem_wishbonedmawriter_base_storage [23:16] + connect \builder_csrbank5_dma_base1_w \main_sdblock2mem_wishbonedmawriter_base_storage [15:8] + connect \builder_csrbank5_dma_base0_w \main_sdblock2mem_wishbonedmawriter_base_storage [7:0] + connect \builder_csrbank5_dma_length3_w \main_sdblock2mem_wishbonedmawriter_length_storage [31:24] + connect \builder_csrbank5_dma_length2_w \main_sdblock2mem_wishbonedmawriter_length_storage [23:16] + connect \builder_csrbank5_dma_length1_w \main_sdblock2mem_wishbonedmawriter_length_storage [15:8] + connect \builder_csrbank5_dma_length0_w \main_sdblock2mem_wishbonedmawriter_length_storage [7:0] + connect \builder_csrbank5_dma_enable0_w \main_sdblock2mem_wishbonedmawriter_enable_storage + connect \builder_csrbank5_dma_done_w \main_sdblock2mem_wishbonedmawriter_status + connect \main_sdblock2mem_wishbonedmawriter_we \builder_csrbank5_dma_done_we + connect \builder_csrbank5_dma_loop0_w \main_sdblock2mem_wishbonedmawriter_loop_storage + connect \builder_csrbank6_sel $eq$ls180.v:6255$1636_Y + connect \builder_csrbank6_cmd_argument3_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_argument3_re $and$ls180.v:6257$1639_Y + connect \builder_csrbank6_cmd_argument3_we $and$ls180.v:6258$1643_Y + connect \builder_csrbank6_cmd_argument2_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_argument2_re $and$ls180.v:6260$1646_Y + connect \builder_csrbank6_cmd_argument2_we $and$ls180.v:6261$1650_Y + connect \builder_csrbank6_cmd_argument1_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_argument1_re $and$ls180.v:6263$1653_Y + connect \builder_csrbank6_cmd_argument1_we $and$ls180.v:6264$1657_Y + connect \builder_csrbank6_cmd_argument0_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_argument0_re $and$ls180.v:6266$1660_Y + connect \builder_csrbank6_cmd_argument0_we $and$ls180.v:6267$1664_Y + connect \builder_csrbank6_cmd_command3_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_command3_re $and$ls180.v:6269$1667_Y + connect \builder_csrbank6_cmd_command3_we $and$ls180.v:6270$1671_Y + connect \builder_csrbank6_cmd_command2_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_command2_re $and$ls180.v:6272$1674_Y + connect \builder_csrbank6_cmd_command2_we $and$ls180.v:6273$1678_Y + connect \builder_csrbank6_cmd_command1_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_command1_re $and$ls180.v:6275$1681_Y + connect \builder_csrbank6_cmd_command1_we $and$ls180.v:6276$1685_Y + connect \builder_csrbank6_cmd_command0_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_command0_re $and$ls180.v:6278$1688_Y + connect \builder_csrbank6_cmd_command0_we $and$ls180.v:6279$1692_Y + connect \main_sdcore_cmd_send_r \builder_interface6_bank_bus_dat_w [0] + connect \main_sdcore_cmd_send_re $and$ls180.v:6281$1695_Y + connect \main_sdcore_cmd_send_we $and$ls180.v:6282$1699_Y + connect \builder_csrbank6_cmd_response15_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_response15_re $and$ls180.v:6284$1702_Y + connect \builder_csrbank6_cmd_response15_we $and$ls180.v:6285$1706_Y + connect \builder_csrbank6_cmd_response14_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_response14_re $and$ls180.v:6287$1709_Y + connect \builder_csrbank6_cmd_response14_we $and$ls180.v:6288$1713_Y + connect \builder_csrbank6_cmd_response13_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_response13_re $and$ls180.v:6290$1716_Y + connect \builder_csrbank6_cmd_response13_we $and$ls180.v:6291$1720_Y + connect \builder_csrbank6_cmd_response12_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_response12_re $and$ls180.v:6293$1723_Y + connect \builder_csrbank6_cmd_response12_we $and$ls180.v:6294$1727_Y + connect \builder_csrbank6_cmd_response11_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_response11_re $and$ls180.v:6296$1730_Y + connect \builder_csrbank6_cmd_response11_we $and$ls180.v:6297$1734_Y + connect \builder_csrbank6_cmd_response10_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_response10_re $and$ls180.v:6299$1737_Y + connect \builder_csrbank6_cmd_response10_we $and$ls180.v:6300$1741_Y + connect \builder_csrbank6_cmd_response9_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_response9_re $and$ls180.v:6302$1744_Y + connect \builder_csrbank6_cmd_response9_we $and$ls180.v:6303$1748_Y + connect \builder_csrbank6_cmd_response8_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_response8_re $and$ls180.v:6305$1751_Y + connect \builder_csrbank6_cmd_response8_we $and$ls180.v:6306$1755_Y + connect \builder_csrbank6_cmd_response7_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_response7_re $and$ls180.v:6308$1758_Y + connect \builder_csrbank6_cmd_response7_we $and$ls180.v:6309$1762_Y + connect \builder_csrbank6_cmd_response6_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_response6_re $and$ls180.v:6311$1765_Y + connect \builder_csrbank6_cmd_response6_we $and$ls180.v:6312$1769_Y + connect \builder_csrbank6_cmd_response5_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_response5_re $and$ls180.v:6314$1772_Y + connect \builder_csrbank6_cmd_response5_we $and$ls180.v:6315$1776_Y + connect \builder_csrbank6_cmd_response4_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_response4_re $and$ls180.v:6317$1779_Y + connect \builder_csrbank6_cmd_response4_we $and$ls180.v:6318$1783_Y + connect \builder_csrbank6_cmd_response3_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_response3_re $and$ls180.v:6320$1786_Y + connect \builder_csrbank6_cmd_response3_we $and$ls180.v:6321$1790_Y + connect \builder_csrbank6_cmd_response2_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_response2_re $and$ls180.v:6323$1793_Y + connect \builder_csrbank6_cmd_response2_we $and$ls180.v:6324$1797_Y + connect \builder_csrbank6_cmd_response1_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_response1_re $and$ls180.v:6326$1800_Y + connect \builder_csrbank6_cmd_response1_we $and$ls180.v:6327$1804_Y + connect \builder_csrbank6_cmd_response0_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_cmd_response0_re $and$ls180.v:6329$1807_Y + connect \builder_csrbank6_cmd_response0_we $and$ls180.v:6330$1811_Y + connect \builder_csrbank6_cmd_event_r \builder_interface6_bank_bus_dat_w [3:0] + connect \builder_csrbank6_cmd_event_re $and$ls180.v:6332$1814_Y + connect \builder_csrbank6_cmd_event_we $and$ls180.v:6333$1818_Y + connect \builder_csrbank6_data_event_r \builder_interface6_bank_bus_dat_w [3:0] + connect \builder_csrbank6_data_event_re $and$ls180.v:6335$1821_Y + connect \builder_csrbank6_data_event_we $and$ls180.v:6336$1825_Y + connect \builder_csrbank6_block_length1_r \builder_interface6_bank_bus_dat_w [1:0] + connect \builder_csrbank6_block_length1_re $and$ls180.v:6338$1828_Y + connect \builder_csrbank6_block_length1_we $and$ls180.v:6339$1832_Y + connect \builder_csrbank6_block_length0_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_block_length0_re $and$ls180.v:6341$1835_Y + connect \builder_csrbank6_block_length0_we $and$ls180.v:6342$1839_Y + connect \builder_csrbank6_block_count3_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_block_count3_re $and$ls180.v:6344$1842_Y + connect \builder_csrbank6_block_count3_we $and$ls180.v:6345$1846_Y + connect \builder_csrbank6_block_count2_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_block_count2_re $and$ls180.v:6347$1849_Y + connect \builder_csrbank6_block_count2_we $and$ls180.v:6348$1853_Y + connect \builder_csrbank6_block_count1_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_block_count1_re $and$ls180.v:6350$1856_Y + connect \builder_csrbank6_block_count1_we $and$ls180.v:6351$1860_Y + connect \builder_csrbank6_block_count0_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_block_count0_re $and$ls180.v:6353$1863_Y + connect \builder_csrbank6_block_count0_we $and$ls180.v:6354$1867_Y + connect \builder_csrbank6_cmd_argument3_w \main_sdcore_cmd_argument_storage [31:24] + connect \builder_csrbank6_cmd_argument2_w \main_sdcore_cmd_argument_storage [23:16] + connect \builder_csrbank6_cmd_argument1_w \main_sdcore_cmd_argument_storage [15:8] + connect \builder_csrbank6_cmd_argument0_w \main_sdcore_cmd_argument_storage [7:0] + connect \builder_csrbank6_cmd_command3_w \main_sdcore_cmd_command_storage [31:24] + connect \builder_csrbank6_cmd_command2_w \main_sdcore_cmd_command_storage [23:16] + connect \builder_csrbank6_cmd_command1_w \main_sdcore_cmd_command_storage [15:8] + connect \builder_csrbank6_cmd_command0_w \main_sdcore_cmd_command_storage [7:0] + connect \builder_csrbank6_cmd_response15_w \main_sdcore_cmd_response_status [127:120] + connect \builder_csrbank6_cmd_response14_w \main_sdcore_cmd_response_status [119:112] + connect \builder_csrbank6_cmd_response13_w \main_sdcore_cmd_response_status [111:104] + connect \builder_csrbank6_cmd_response12_w \main_sdcore_cmd_response_status [103:96] + connect \builder_csrbank6_cmd_response11_w \main_sdcore_cmd_response_status [95:88] + connect \builder_csrbank6_cmd_response10_w \main_sdcore_cmd_response_status [87:80] + connect \builder_csrbank6_cmd_response9_w \main_sdcore_cmd_response_status [79:72] + connect \builder_csrbank6_cmd_response8_w \main_sdcore_cmd_response_status [71:64] + connect \builder_csrbank6_cmd_response7_w \main_sdcore_cmd_response_status [63:56] + connect \builder_csrbank6_cmd_response6_w \main_sdcore_cmd_response_status [55:48] + connect \builder_csrbank6_cmd_response5_w \main_sdcore_cmd_response_status [47:40] + connect \builder_csrbank6_cmd_response4_w \main_sdcore_cmd_response_status [39:32] + connect \builder_csrbank6_cmd_response3_w \main_sdcore_cmd_response_status [31:24] + connect \builder_csrbank6_cmd_response2_w \main_sdcore_cmd_response_status [23:16] + connect \builder_csrbank6_cmd_response1_w \main_sdcore_cmd_response_status [15:8] + connect \builder_csrbank6_cmd_response0_w \main_sdcore_cmd_response_status [7:0] + connect \main_sdcore_cmd_response_we \builder_csrbank6_cmd_response0_we + connect \builder_csrbank6_cmd_event_w \main_sdcore_cmd_event_status + connect \main_sdcore_cmd_event_we \builder_csrbank6_cmd_event_we + connect \builder_csrbank6_data_event_w \main_sdcore_data_event_status + connect \main_sdcore_data_event_we \builder_csrbank6_data_event_we + connect \builder_csrbank6_block_length1_w \main_sdcore_block_length_storage [9:8] + connect \builder_csrbank6_block_length0_w \main_sdcore_block_length_storage [7:0] + connect \builder_csrbank6_block_count3_w \main_sdcore_block_count_storage [31:24] + connect \builder_csrbank6_block_count2_w \main_sdcore_block_count_storage [23:16] + connect \builder_csrbank6_block_count1_w \main_sdcore_block_count_storage [15:8] + connect \builder_csrbank6_block_count0_w \main_sdcore_block_count_storage [7:0] + connect \builder_csrbank7_sel $eq$ls180.v:6390$1868_Y + connect \builder_csrbank7_dma_base7_r \builder_interface7_bank_bus_dat_w + connect \builder_csrbank7_dma_base7_re $and$ls180.v:6392$1871_Y + connect \builder_csrbank7_dma_base7_we $and$ls180.v:6393$1875_Y + connect \builder_csrbank7_dma_base6_r \builder_interface7_bank_bus_dat_w + connect \builder_csrbank7_dma_base6_re $and$ls180.v:6395$1878_Y + connect \builder_csrbank7_dma_base6_we $and$ls180.v:6396$1882_Y + connect \builder_csrbank7_dma_base5_r \builder_interface7_bank_bus_dat_w + connect \builder_csrbank7_dma_base5_re $and$ls180.v:6398$1885_Y + connect \builder_csrbank7_dma_base5_we $and$ls180.v:6399$1889_Y + connect \builder_csrbank7_dma_base4_r \builder_interface7_bank_bus_dat_w + connect \builder_csrbank7_dma_base4_re $and$ls180.v:6401$1892_Y + connect \builder_csrbank7_dma_base4_we $and$ls180.v:6402$1896_Y + connect \builder_csrbank7_dma_base3_r \builder_interface7_bank_bus_dat_w + connect \builder_csrbank7_dma_base3_re $and$ls180.v:6404$1899_Y + connect \builder_csrbank7_dma_base3_we $and$ls180.v:6405$1903_Y + connect \builder_csrbank7_dma_base2_r \builder_interface7_bank_bus_dat_w + connect \builder_csrbank7_dma_base2_re $and$ls180.v:6407$1906_Y + connect \builder_csrbank7_dma_base2_we $and$ls180.v:6408$1910_Y + connect \builder_csrbank7_dma_base1_r \builder_interface7_bank_bus_dat_w + connect \builder_csrbank7_dma_base1_re $and$ls180.v:6410$1913_Y + connect \builder_csrbank7_dma_base1_we $and$ls180.v:6411$1917_Y + connect \builder_csrbank7_dma_base0_r \builder_interface7_bank_bus_dat_w + connect \builder_csrbank7_dma_base0_re $and$ls180.v:6413$1920_Y + connect \builder_csrbank7_dma_base0_we $and$ls180.v:6414$1924_Y + connect \builder_csrbank7_dma_length3_r \builder_interface7_bank_bus_dat_w + connect \builder_csrbank7_dma_length3_re $and$ls180.v:6416$1927_Y + connect \builder_csrbank7_dma_length3_we $and$ls180.v:6417$1931_Y + connect \builder_csrbank7_dma_length2_r \builder_interface7_bank_bus_dat_w + connect \builder_csrbank7_dma_length2_re $and$ls180.v:6419$1934_Y + connect \builder_csrbank7_dma_length2_we $and$ls180.v:6420$1938_Y + connect \builder_csrbank7_dma_length1_r \builder_interface7_bank_bus_dat_w + connect \builder_csrbank7_dma_length1_re $and$ls180.v:6422$1941_Y + connect \builder_csrbank7_dma_length1_we $and$ls180.v:6423$1945_Y + connect \builder_csrbank7_dma_length0_r \builder_interface7_bank_bus_dat_w + connect \builder_csrbank7_dma_length0_re $and$ls180.v:6425$1948_Y + connect \builder_csrbank7_dma_length0_we $and$ls180.v:6426$1952_Y + connect \builder_csrbank7_dma_enable0_r \builder_interface7_bank_bus_dat_w [0] + connect \builder_csrbank7_dma_enable0_re $and$ls180.v:6428$1955_Y + connect \builder_csrbank7_dma_enable0_we $and$ls180.v:6429$1959_Y + connect \builder_csrbank7_dma_done_r \builder_interface7_bank_bus_dat_w [0] + connect \builder_csrbank7_dma_done_re $and$ls180.v:6431$1962_Y + connect \builder_csrbank7_dma_done_we $and$ls180.v:6432$1966_Y + connect \builder_csrbank7_dma_loop0_r \builder_interface7_bank_bus_dat_w [0] + connect \builder_csrbank7_dma_loop0_re $and$ls180.v:6434$1969_Y + connect \builder_csrbank7_dma_loop0_we $and$ls180.v:6435$1973_Y + connect \builder_csrbank7_dma_offset3_r \builder_interface7_bank_bus_dat_w + connect \builder_csrbank7_dma_offset3_re $and$ls180.v:6437$1976_Y + connect \builder_csrbank7_dma_offset3_we $and$ls180.v:6438$1980_Y + connect \builder_csrbank7_dma_offset2_r \builder_interface7_bank_bus_dat_w + connect \builder_csrbank7_dma_offset2_re $and$ls180.v:6440$1983_Y + connect \builder_csrbank7_dma_offset2_we $and$ls180.v:6441$1987_Y + connect \builder_csrbank7_dma_offset1_r \builder_interface7_bank_bus_dat_w + connect \builder_csrbank7_dma_offset1_re $and$ls180.v:6443$1990_Y + connect \builder_csrbank7_dma_offset1_we $and$ls180.v:6444$1994_Y + connect \builder_csrbank7_dma_offset0_r \builder_interface7_bank_bus_dat_w + connect \builder_csrbank7_dma_offset0_re $and$ls180.v:6446$1997_Y + connect \builder_csrbank7_dma_offset0_we $and$ls180.v:6447$2001_Y + connect \builder_csrbank7_dma_base7_w \main_sdmem2block_dma_base_storage [63:56] + connect \builder_csrbank7_dma_base6_w \main_sdmem2block_dma_base_storage [55:48] + connect \builder_csrbank7_dma_base5_w \main_sdmem2block_dma_base_storage [47:40] + connect \builder_csrbank7_dma_base4_w \main_sdmem2block_dma_base_storage [39:32] + connect \builder_csrbank7_dma_base3_w \main_sdmem2block_dma_base_storage [31:24] + connect \builder_csrbank7_dma_base2_w \main_sdmem2block_dma_base_storage [23:16] + connect \builder_csrbank7_dma_base1_w \main_sdmem2block_dma_base_storage [15:8] + connect \builder_csrbank7_dma_base0_w \main_sdmem2block_dma_base_storage [7:0] + connect \builder_csrbank7_dma_length3_w \main_sdmem2block_dma_length_storage [31:24] + connect \builder_csrbank7_dma_length2_w \main_sdmem2block_dma_length_storage [23:16] + connect \builder_csrbank7_dma_length1_w \main_sdmem2block_dma_length_storage [15:8] + connect \builder_csrbank7_dma_length0_w \main_sdmem2block_dma_length_storage [7:0] + connect \builder_csrbank7_dma_enable0_w \main_sdmem2block_dma_enable_storage + connect \builder_csrbank7_dma_done_w \main_sdmem2block_dma_done_status + connect \main_sdmem2block_dma_done_we \builder_csrbank7_dma_done_we + connect \builder_csrbank7_dma_loop0_w \main_sdmem2block_dma_loop_storage + connect \builder_csrbank7_dma_offset3_w \main_sdmem2block_dma_offset_status [31:24] + connect \builder_csrbank7_dma_offset2_w \main_sdmem2block_dma_offset_status [23:16] + connect \builder_csrbank7_dma_offset1_w \main_sdmem2block_dma_offset_status [15:8] + connect \builder_csrbank7_dma_offset0_w \main_sdmem2block_dma_offset_status [7:0] + connect \main_sdmem2block_dma_offset_we \builder_csrbank7_dma_offset0_we + connect \builder_csrbank8_sel $eq$ls180.v:6469$2002_Y + connect \builder_csrbank8_card_detect_r \builder_interface8_bank_bus_dat_w [0] + connect \builder_csrbank8_card_detect_re $and$ls180.v:6471$2005_Y + connect \builder_csrbank8_card_detect_we $and$ls180.v:6472$2009_Y + connect \builder_csrbank8_clocker_divider1_r \builder_interface8_bank_bus_dat_w [0] + connect \builder_csrbank8_clocker_divider1_re $and$ls180.v:6474$2012_Y + connect \builder_csrbank8_clocker_divider1_we $and$ls180.v:6475$2016_Y + connect \builder_csrbank8_clocker_divider0_r \builder_interface8_bank_bus_dat_w + connect \builder_csrbank8_clocker_divider0_re $and$ls180.v:6477$2019_Y + connect \builder_csrbank8_clocker_divider0_we $and$ls180.v:6478$2023_Y + connect \main_sdphy_init_initialize_r \builder_interface8_bank_bus_dat_w [0] + connect \main_sdphy_init_initialize_re $and$ls180.v:6480$2026_Y + connect \main_sdphy_init_initialize_we $and$ls180.v:6481$2030_Y + connect \builder_csrbank8_card_detect_w \main_sdphy_status + connect \main_sdphy_we \builder_csrbank8_card_detect_we + connect \builder_csrbank8_clocker_divider1_w \main_sdphy_clocker_storage [8] + connect \builder_csrbank8_clocker_divider0_w \main_sdphy_clocker_storage [7:0] + connect \builder_csrbank9_sel $eq$ls180.v:6486$2031_Y + connect \builder_csrbank9_dfii_control0_r \builder_interface9_bank_bus_dat_w [3:0] + connect \builder_csrbank9_dfii_control0_re $and$ls180.v:6488$2034_Y + connect \builder_csrbank9_dfii_control0_we $and$ls180.v:6489$2038_Y + connect \builder_csrbank9_dfii_pi0_command0_r \builder_interface9_bank_bus_dat_w [5:0] + connect \builder_csrbank9_dfii_pi0_command0_re $and$ls180.v:6491$2041_Y + connect \builder_csrbank9_dfii_pi0_command0_we $and$ls180.v:6492$2045_Y + connect \main_sdram_command_issue_r \builder_interface9_bank_bus_dat_w [0] + connect \main_sdram_command_issue_re $and$ls180.v:6494$2048_Y + connect \main_sdram_command_issue_we $and$ls180.v:6495$2052_Y + connect \builder_csrbank9_dfii_pi0_address1_r \builder_interface9_bank_bus_dat_w [4:0] + connect \builder_csrbank9_dfii_pi0_address1_re $and$ls180.v:6497$2055_Y + connect \builder_csrbank9_dfii_pi0_address1_we $and$ls180.v:6498$2059_Y + connect \builder_csrbank9_dfii_pi0_address0_r \builder_interface9_bank_bus_dat_w + connect \builder_csrbank9_dfii_pi0_address0_re $and$ls180.v:6500$2062_Y + connect \builder_csrbank9_dfii_pi0_address0_we $and$ls180.v:6501$2066_Y + connect \builder_csrbank9_dfii_pi0_baddress0_r \builder_interface9_bank_bus_dat_w [1:0] + connect \builder_csrbank9_dfii_pi0_baddress0_re $and$ls180.v:6503$2069_Y + connect \builder_csrbank9_dfii_pi0_baddress0_we $and$ls180.v:6504$2073_Y + connect \builder_csrbank9_dfii_pi0_wrdata1_r \builder_interface9_bank_bus_dat_w + connect \builder_csrbank9_dfii_pi0_wrdata1_re $and$ls180.v:6506$2076_Y + connect \builder_csrbank9_dfii_pi0_wrdata1_we $and$ls180.v:6507$2080_Y + connect \builder_csrbank9_dfii_pi0_wrdata0_r \builder_interface9_bank_bus_dat_w + connect \builder_csrbank9_dfii_pi0_wrdata0_re $and$ls180.v:6509$2083_Y + connect \builder_csrbank9_dfii_pi0_wrdata0_we $and$ls180.v:6510$2087_Y + connect \builder_csrbank9_dfii_pi0_rddata1_r \builder_interface9_bank_bus_dat_w + connect \builder_csrbank9_dfii_pi0_rddata1_re $and$ls180.v:6512$2090_Y + connect \builder_csrbank9_dfii_pi0_rddata1_we $and$ls180.v:6513$2094_Y + connect \builder_csrbank9_dfii_pi0_rddata0_r \builder_interface9_bank_bus_dat_w + connect \builder_csrbank9_dfii_pi0_rddata0_re $and$ls180.v:6515$2097_Y + connect \builder_csrbank9_dfii_pi0_rddata0_we $and$ls180.v:6516$2101_Y + connect \main_sdram_sel \main_sdram_storage [0] + connect \main_sdram_cke \main_sdram_storage [1] + connect \main_sdram_odt \main_sdram_storage [2] + connect \main_sdram_reset_n \main_sdram_storage [3] + connect \builder_csrbank9_dfii_control0_w \main_sdram_storage + connect \builder_csrbank9_dfii_pi0_command0_w \main_sdram_command_storage + connect \builder_csrbank9_dfii_pi0_address1_w \main_sdram_address_storage [12:8] + connect \builder_csrbank9_dfii_pi0_address0_w \main_sdram_address_storage [7:0] + connect \builder_csrbank9_dfii_pi0_baddress0_w \main_sdram_baddress_storage + connect \builder_csrbank9_dfii_pi0_wrdata1_w \main_sdram_wrdata_storage [15:8] + connect \builder_csrbank9_dfii_pi0_wrdata0_w \main_sdram_wrdata_storage [7:0] + connect \builder_csrbank9_dfii_pi0_rddata1_w \main_sdram_status [15:8] + connect \builder_csrbank9_dfii_pi0_rddata0_w \main_sdram_status [7:0] + connect \main_sdram_we \builder_csrbank9_dfii_pi0_rddata0_we + connect \builder_csrbank10_sel $eq$ls180.v:6531$2102_Y + connect \builder_csrbank10_control1_r \builder_interface10_bank_bus_dat_w + connect \builder_csrbank10_control1_re $and$ls180.v:6533$2105_Y + connect \builder_csrbank10_control1_we $and$ls180.v:6534$2109_Y + connect \builder_csrbank10_control0_r \builder_interface10_bank_bus_dat_w + connect \builder_csrbank10_control0_re $and$ls180.v:6536$2112_Y + connect \builder_csrbank10_control0_we $and$ls180.v:6537$2116_Y + connect \builder_csrbank10_status_r \builder_interface10_bank_bus_dat_w [0] + connect \builder_csrbank10_status_re $and$ls180.v:6539$2119_Y + connect \builder_csrbank10_status_we $and$ls180.v:6540$2123_Y + connect \builder_csrbank10_mosi0_r \builder_interface10_bank_bus_dat_w + connect \builder_csrbank10_mosi0_re $and$ls180.v:6542$2126_Y + connect \builder_csrbank10_mosi0_we $and$ls180.v:6543$2130_Y + connect \builder_csrbank10_miso_r \builder_interface10_bank_bus_dat_w + connect \builder_csrbank10_miso_re $and$ls180.v:6545$2133_Y + connect \builder_csrbank10_miso_we $and$ls180.v:6546$2137_Y + connect \builder_csrbank10_cs0_r \builder_interface10_bank_bus_dat_w [0] + connect \builder_csrbank10_cs0_re $and$ls180.v:6548$2140_Y + connect \builder_csrbank10_cs0_we $and$ls180.v:6549$2144_Y + connect \builder_csrbank10_loopback0_r \builder_interface10_bank_bus_dat_w [0] + connect \builder_csrbank10_loopback0_re $and$ls180.v:6551$2147_Y + connect \builder_csrbank10_loopback0_we $and$ls180.v:6552$2151_Y + connect \main_spimaster10_length \main_spimaster11_storage [15:8] + connect \builder_csrbank10_control1_w \main_spimaster11_storage [15:8] + connect \builder_csrbank10_control0_w \main_spimaster11_storage [7:0] + connect \main_spimaster14_status \main_spimaster13_done + connect \builder_csrbank10_status_w \main_spimaster14_status + connect \main_spimaster15_we \builder_csrbank10_status_we + connect \builder_csrbank10_mosi0_w \main_spimaster16_storage + connect \builder_csrbank10_miso_w \main_spimaster18_status + connect \main_spimaster19_we \builder_csrbank10_miso_we + connect \main_spimaster20_sel \main_spimaster21_storage + connect \builder_csrbank10_cs0_w \main_spimaster21_storage + connect \builder_csrbank10_loopback0_w \main_spimaster23_storage + connect \builder_csrbank11_sel $eq$ls180.v:6571$2153_Y + connect \builder_csrbank11_control1_r \builder_interface11_bank_bus_dat_w + connect \builder_csrbank11_control1_re $and$ls180.v:6573$2156_Y + connect \builder_csrbank11_control1_we $and$ls180.v:6574$2160_Y + connect \builder_csrbank11_control0_r \builder_interface11_bank_bus_dat_w + connect \builder_csrbank11_control0_re $and$ls180.v:6576$2163_Y + connect \builder_csrbank11_control0_we $and$ls180.v:6577$2167_Y + connect \builder_csrbank11_status_r \builder_interface11_bank_bus_dat_w [0] + connect \builder_csrbank11_status_re $and$ls180.v:6579$2170_Y + connect \builder_csrbank11_status_we $and$ls180.v:6580$2174_Y + connect \builder_csrbank11_mosi0_r \builder_interface11_bank_bus_dat_w + connect \builder_csrbank11_mosi0_re $and$ls180.v:6582$2177_Y + connect \builder_csrbank11_mosi0_we $and$ls180.v:6583$2181_Y + connect \builder_csrbank11_miso_r \builder_interface11_bank_bus_dat_w + connect \builder_csrbank11_miso_re $and$ls180.v:6585$2184_Y + connect \builder_csrbank11_miso_we $and$ls180.v:6586$2188_Y + connect \builder_csrbank11_cs0_r \builder_interface11_bank_bus_dat_w [0] + connect \builder_csrbank11_cs0_re $and$ls180.v:6588$2191_Y + connect \builder_csrbank11_cs0_we $and$ls180.v:6589$2195_Y + connect \builder_csrbank11_loopback0_r \builder_interface11_bank_bus_dat_w [0] + connect \builder_csrbank11_loopback0_re $and$ls180.v:6591$2198_Y + connect \builder_csrbank11_loopback0_we $and$ls180.v:6592$2202_Y + connect \builder_csrbank11_clk_divider1_r \builder_interface11_bank_bus_dat_w + connect \builder_csrbank11_clk_divider1_re $and$ls180.v:6594$2205_Y + connect \builder_csrbank11_clk_divider1_we $and$ls180.v:6595$2209_Y + connect \builder_csrbank11_clk_divider0_r \builder_interface11_bank_bus_dat_w + connect \builder_csrbank11_clk_divider0_re $and$ls180.v:6597$2212_Y + connect \builder_csrbank11_clk_divider0_we $and$ls180.v:6598$2216_Y + connect \main_spisdcard_length1 \main_spisdcard_control_storage [15:8] + connect \builder_csrbank11_control1_w \main_spisdcard_control_storage [15:8] + connect \builder_csrbank11_control0_w \main_spisdcard_control_storage [7:0] + connect \main_spisdcard_status_status \main_spisdcard_done1 + connect \builder_csrbank11_status_w \main_spisdcard_status_status + connect \main_spisdcard_status_we \builder_csrbank11_status_we + connect \builder_csrbank11_mosi0_w \main_spisdcard_mosi_storage + connect \builder_csrbank11_miso_w \main_spisdcard_miso_status + connect \main_spisdcard_miso_we \builder_csrbank11_miso_we + connect \main_spisdcard_sel \main_spisdcard_cs_storage + connect \builder_csrbank11_cs0_w \main_spisdcard_cs_storage + connect \builder_csrbank11_loopback0_w \main_spisdcard_loopback_storage + connect \builder_csrbank11_clk_divider1_w \main_spimaster1_storage [15:8] + connect \builder_csrbank11_clk_divider0_w \main_spimaster1_storage [7:0] + connect \builder_csrbank12_sel $eq$ls180.v:6619$2218_Y + connect \builder_csrbank12_load3_r \builder_interface12_bank_bus_dat_w + connect \builder_csrbank12_load3_re $and$ls180.v:6621$2221_Y + connect \builder_csrbank12_load3_we $and$ls180.v:6622$2225_Y + connect \builder_csrbank12_load2_r \builder_interface12_bank_bus_dat_w + connect \builder_csrbank12_load2_re $and$ls180.v:6624$2228_Y + connect \builder_csrbank12_load2_we $and$ls180.v:6625$2232_Y + connect \builder_csrbank12_load1_r \builder_interface12_bank_bus_dat_w + connect \builder_csrbank12_load1_re $and$ls180.v:6627$2235_Y + connect \builder_csrbank12_load1_we $and$ls180.v:6628$2239_Y + connect \builder_csrbank12_load0_r \builder_interface12_bank_bus_dat_w + connect \builder_csrbank12_load0_re $and$ls180.v:6630$2242_Y + connect \builder_csrbank12_load0_we $and$ls180.v:6631$2246_Y + connect \builder_csrbank12_reload3_r \builder_interface12_bank_bus_dat_w + connect \builder_csrbank12_reload3_re $and$ls180.v:6633$2249_Y + connect \builder_csrbank12_reload3_we $and$ls180.v:6634$2253_Y + connect \builder_csrbank12_reload2_r \builder_interface12_bank_bus_dat_w + connect \builder_csrbank12_reload2_re $and$ls180.v:6636$2256_Y + connect \builder_csrbank12_reload2_we $and$ls180.v:6637$2260_Y + connect \builder_csrbank12_reload1_r \builder_interface12_bank_bus_dat_w + connect \builder_csrbank12_reload1_re $and$ls180.v:6639$2263_Y + connect \builder_csrbank12_reload1_we $and$ls180.v:6640$2267_Y + connect \builder_csrbank12_reload0_r \builder_interface12_bank_bus_dat_w + connect \builder_csrbank12_reload0_re $and$ls180.v:6642$2270_Y + connect \builder_csrbank12_reload0_we $and$ls180.v:6643$2274_Y + connect \builder_csrbank12_en0_r \builder_interface12_bank_bus_dat_w [0] + connect \builder_csrbank12_en0_re $and$ls180.v:6645$2277_Y + connect \builder_csrbank12_en0_we $and$ls180.v:6646$2281_Y + connect \builder_csrbank12_update_value0_r \builder_interface12_bank_bus_dat_w [0] + connect \builder_csrbank12_update_value0_re $and$ls180.v:6648$2284_Y + connect \builder_csrbank12_update_value0_we $and$ls180.v:6649$2288_Y + connect \builder_csrbank12_value3_r \builder_interface12_bank_bus_dat_w + connect \builder_csrbank12_value3_re $and$ls180.v:6651$2291_Y + connect \builder_csrbank12_value3_we $and$ls180.v:6652$2295_Y + connect \builder_csrbank12_value2_r \builder_interface12_bank_bus_dat_w + connect \builder_csrbank12_value2_re $and$ls180.v:6654$2298_Y + connect \builder_csrbank12_value2_we $and$ls180.v:6655$2302_Y + connect \builder_csrbank12_value1_r \builder_interface12_bank_bus_dat_w + connect \builder_csrbank12_value1_re $and$ls180.v:6657$2305_Y + connect \builder_csrbank12_value1_we $and$ls180.v:6658$2309_Y + connect \builder_csrbank12_value0_r \builder_interface12_bank_bus_dat_w + connect \builder_csrbank12_value0_re $and$ls180.v:6660$2312_Y + connect \builder_csrbank12_value0_we $and$ls180.v:6661$2316_Y + connect \main_libresocsim_eventmanager_status_r \builder_interface12_bank_bus_dat_w [0] + connect \main_libresocsim_eventmanager_status_re $and$ls180.v:6663$2319_Y + connect \main_libresocsim_eventmanager_status_we $and$ls180.v:6664$2323_Y + connect \main_libresocsim_eventmanager_pending_r \builder_interface12_bank_bus_dat_w [0] + connect \main_libresocsim_eventmanager_pending_re $and$ls180.v:6666$2326_Y + connect \main_libresocsim_eventmanager_pending_we $and$ls180.v:6667$2330_Y + connect \builder_csrbank12_ev_enable0_r \builder_interface12_bank_bus_dat_w [0] + connect \builder_csrbank12_ev_enable0_re $and$ls180.v:6669$2333_Y + connect \builder_csrbank12_ev_enable0_we $and$ls180.v:6670$2337_Y + connect \builder_csrbank12_load3_w \main_libresocsim_load_storage [31:24] + connect \builder_csrbank12_load2_w \main_libresocsim_load_storage [23:16] + connect \builder_csrbank12_load1_w \main_libresocsim_load_storage [15:8] + connect \builder_csrbank12_load0_w \main_libresocsim_load_storage [7:0] + connect \builder_csrbank12_reload3_w \main_libresocsim_reload_storage [31:24] + connect \builder_csrbank12_reload2_w \main_libresocsim_reload_storage [23:16] + connect \builder_csrbank12_reload1_w \main_libresocsim_reload_storage [15:8] + connect \builder_csrbank12_reload0_w \main_libresocsim_reload_storage [7:0] + connect \builder_csrbank12_en0_w \main_libresocsim_en_storage + connect \builder_csrbank12_update_value0_w \main_libresocsim_update_value_storage + connect \builder_csrbank12_value3_w \main_libresocsim_value_status [31:24] + connect \builder_csrbank12_value2_w \main_libresocsim_value_status [23:16] + connect \builder_csrbank12_value1_w \main_libresocsim_value_status [15:8] + connect \builder_csrbank12_value0_w \main_libresocsim_value_status [7:0] + connect \main_libresocsim_value_we \builder_csrbank12_value0_we + connect \builder_csrbank12_ev_enable0_w \main_libresocsim_eventmanager_storage + connect \builder_csrbank13_sel $eq$ls180.v:6687$2338_Y + connect \main_uart_rxtx_r \builder_interface13_bank_bus_dat_w + connect \main_uart_rxtx_re $and$ls180.v:6689$2341_Y + connect \main_uart_rxtx_we $and$ls180.v:6690$2345_Y + connect \builder_csrbank13_txfull_r \builder_interface13_bank_bus_dat_w [0] + connect \builder_csrbank13_txfull_re $and$ls180.v:6692$2348_Y + connect \builder_csrbank13_txfull_we $and$ls180.v:6693$2352_Y + connect \builder_csrbank13_rxempty_r \builder_interface13_bank_bus_dat_w [0] + connect \builder_csrbank13_rxempty_re $and$ls180.v:6695$2355_Y + connect \builder_csrbank13_rxempty_we $and$ls180.v:6696$2359_Y + connect \main_uart_eventmanager_status_r \builder_interface13_bank_bus_dat_w [1:0] + connect \main_uart_eventmanager_status_re $and$ls180.v:6698$2362_Y + connect \main_uart_eventmanager_status_we $and$ls180.v:6699$2366_Y + connect \main_uart_eventmanager_pending_r \builder_interface13_bank_bus_dat_w [1:0] + connect \main_uart_eventmanager_pending_re $and$ls180.v:6701$2369_Y + connect \main_uart_eventmanager_pending_we $and$ls180.v:6702$2373_Y + connect \builder_csrbank13_ev_enable0_r \builder_interface13_bank_bus_dat_w [1:0] + connect \builder_csrbank13_ev_enable0_re $and$ls180.v:6704$2376_Y + connect \builder_csrbank13_ev_enable0_we $and$ls180.v:6705$2380_Y + connect \builder_csrbank13_txempty_r \builder_interface13_bank_bus_dat_w [0] + connect \builder_csrbank13_txempty_re $and$ls180.v:6707$2383_Y + connect \builder_csrbank13_txempty_we $and$ls180.v:6708$2387_Y + connect \builder_csrbank13_rxfull_r \builder_interface13_bank_bus_dat_w [0] + connect \builder_csrbank13_rxfull_re $and$ls180.v:6710$2390_Y + connect \builder_csrbank13_rxfull_we $and$ls180.v:6711$2394_Y + connect \builder_csrbank13_txfull_w \main_uart_txfull_status + connect \main_uart_txfull_we \builder_csrbank13_txfull_we + connect \builder_csrbank13_rxempty_w \main_uart_rxempty_status + connect \main_uart_rxempty_we \builder_csrbank13_rxempty_we + connect \builder_csrbank13_ev_enable0_w \main_uart_eventmanager_storage + connect \builder_csrbank13_txempty_w \main_uart_txempty_status + connect \main_uart_txempty_we \builder_csrbank13_txempty_we + connect \builder_csrbank13_rxfull_w \main_uart_rxfull_status + connect \main_uart_rxfull_we \builder_csrbank13_rxfull_we + connect \builder_csrbank14_sel $eq$ls180.v:6721$2395_Y + connect \builder_csrbank14_tuning_word3_r \builder_interface14_bank_bus_dat_w + connect \builder_csrbank14_tuning_word3_re $and$ls180.v:6723$2398_Y + connect \builder_csrbank14_tuning_word3_we $and$ls180.v:6724$2402_Y + connect \builder_csrbank14_tuning_word2_r \builder_interface14_bank_bus_dat_w + connect \builder_csrbank14_tuning_word2_re $and$ls180.v:6726$2405_Y + connect \builder_csrbank14_tuning_word2_we $and$ls180.v:6727$2409_Y + connect \builder_csrbank14_tuning_word1_r \builder_interface14_bank_bus_dat_w + connect \builder_csrbank14_tuning_word1_re $and$ls180.v:6729$2412_Y + connect \builder_csrbank14_tuning_word1_we $and$ls180.v:6730$2416_Y + connect \builder_csrbank14_tuning_word0_r \builder_interface14_bank_bus_dat_w + connect \builder_csrbank14_tuning_word0_re $and$ls180.v:6732$2419_Y + connect \builder_csrbank14_tuning_word0_we $and$ls180.v:6733$2423_Y + connect \builder_csrbank14_tuning_word3_w \main_uart_phy_storage [31:24] + connect \builder_csrbank14_tuning_word2_w \main_uart_phy_storage [23:16] + connect \builder_csrbank14_tuning_word1_w \main_uart_phy_storage [15:8] + connect \builder_csrbank14_tuning_word0_w \main_uart_phy_storage [7:0] + connect \builder_csr_interconnect_adr \builder_libresocsim_adr + connect \builder_csr_interconnect_we \builder_libresocsim_we + connect \builder_csr_interconnect_dat_w \builder_libresocsim_dat_w + connect \builder_libresocsim_dat_r \builder_csr_interconnect_dat_r + connect \builder_interface0_bank_bus_adr \builder_csr_interconnect_adr + connect \builder_interface1_bank_bus_adr \builder_csr_interconnect_adr + connect \builder_interface2_bank_bus_adr \builder_csr_interconnect_adr + connect \builder_interface3_bank_bus_adr \builder_csr_interconnect_adr + connect \builder_interface4_bank_bus_adr \builder_csr_interconnect_adr + connect \builder_interface5_bank_bus_adr \builder_csr_interconnect_adr + connect \builder_interface6_bank_bus_adr \builder_csr_interconnect_adr + connect \builder_interface7_bank_bus_adr \builder_csr_interconnect_adr + connect \builder_interface8_bank_bus_adr \builder_csr_interconnect_adr + connect \builder_interface9_bank_bus_adr \builder_csr_interconnect_adr + connect \builder_interface10_bank_bus_adr \builder_csr_interconnect_adr + connect \builder_interface11_bank_bus_adr \builder_csr_interconnect_adr + connect \builder_interface12_bank_bus_adr \builder_csr_interconnect_adr + connect \builder_interface13_bank_bus_adr \builder_csr_interconnect_adr + connect \builder_interface14_bank_bus_adr \builder_csr_interconnect_adr + connect \builder_interface0_bank_bus_we \builder_csr_interconnect_we + connect \builder_interface1_bank_bus_we \builder_csr_interconnect_we + connect \builder_interface2_bank_bus_we \builder_csr_interconnect_we + connect \builder_interface3_bank_bus_we \builder_csr_interconnect_we + connect \builder_interface4_bank_bus_we \builder_csr_interconnect_we + connect \builder_interface5_bank_bus_we \builder_csr_interconnect_we + connect \builder_interface6_bank_bus_we \builder_csr_interconnect_we + connect \builder_interface7_bank_bus_we \builder_csr_interconnect_we + connect \builder_interface8_bank_bus_we \builder_csr_interconnect_we + connect \builder_interface9_bank_bus_we \builder_csr_interconnect_we + connect \builder_interface10_bank_bus_we \builder_csr_interconnect_we + connect \builder_interface11_bank_bus_we \builder_csr_interconnect_we + connect \builder_interface12_bank_bus_we \builder_csr_interconnect_we + connect \builder_interface13_bank_bus_we \builder_csr_interconnect_we + connect \builder_interface14_bank_bus_we \builder_csr_interconnect_we + connect \builder_interface0_bank_bus_dat_w \builder_csr_interconnect_dat_w + connect \builder_interface1_bank_bus_dat_w \builder_csr_interconnect_dat_w + connect \builder_interface2_bank_bus_dat_w \builder_csr_interconnect_dat_w + connect \builder_interface3_bank_bus_dat_w \builder_csr_interconnect_dat_w + connect \builder_interface4_bank_bus_dat_w \builder_csr_interconnect_dat_w + connect \builder_interface5_bank_bus_dat_w \builder_csr_interconnect_dat_w + connect \builder_interface6_bank_bus_dat_w \builder_csr_interconnect_dat_w + connect \builder_interface7_bank_bus_dat_w \builder_csr_interconnect_dat_w + connect \builder_interface8_bank_bus_dat_w \builder_csr_interconnect_dat_w + connect \builder_interface9_bank_bus_dat_w \builder_csr_interconnect_dat_w + connect \builder_interface10_bank_bus_dat_w \builder_csr_interconnect_dat_w + connect \builder_interface11_bank_bus_dat_w \builder_csr_interconnect_dat_w + connect \builder_interface12_bank_bus_dat_w \builder_csr_interconnect_dat_w + connect \builder_interface13_bank_bus_dat_w \builder_csr_interconnect_dat_w + connect \builder_interface14_bank_bus_dat_w \builder_csr_interconnect_dat_w + connect \builder_csr_interconnect_dat_r $or$ls180.v:6787$2437_Y + connect \sdrio_clk \sys_clk_1 + connect \sdrio_clk_1 \sys_clk_1 + connect \sdrio_clk_2 \sys_clk_1 + connect \sdrio_clk_3 \sys_clk_1 + connect \sdrio_clk_4 \sys_clk_1 + connect \sdrio_clk_5 \sys_clk_1 + connect \sdrio_clk_6 \sys_clk_1 + connect \sdrio_clk_7 \sys_clk_1 + connect \sdrio_clk_8 \sys_clk_1 + connect \sdrio_clk_9 \sys_clk_1 + connect \sdrio_clk_10 \sys_clk_1 + connect \sdrio_clk_11 \sys_clk_1 + connect \sdrio_clk_12 \sys_clk_1 + connect \sdrio_clk_13 \sys_clk_1 + connect \sdrio_clk_14 \sys_clk_1 + connect \sdrio_clk_15 \sys_clk_1 + connect \sdrio_clk_16 \sys_clk_1 + connect \sdrio_clk_17 \sys_clk_1 + connect \sdrio_clk_18 \sys_clk_1 + connect \sdrio_clk_19 \sys_clk_1 + connect \sdrio_clk_20 \sys_clk_1 + connect \sdrio_clk_21 \sys_clk_1 + connect \sdrio_clk_22 \sys_clk_1 + connect \sdrio_clk_23 \sys_clk_1 + connect \sdrio_clk_24 \sys_clk_1 + connect \sdrio_clk_25 \sys_clk_1 + connect \sdrio_clk_26 \sys_clk_1 + connect \sdrio_clk_27 \sys_clk_1 + connect \sdrio_clk_28 \sys_clk_1 + connect \sdrio_clk_29 \sys_clk_1 + connect \sdrio_clk_30 \sys_clk_1 + connect \sdrio_clk_31 \sys_clk_1 + connect \sdrio_clk_32 \sys_clk_1 + connect \sdrio_clk_33 \sys_clk_1 + connect \sdrio_clk_34 \sys_clk_1 + connect \sdrio_clk_35 \sys_clk_1 + connect \sdrio_clk_36 \sys_clk_1 + connect \sdrio_clk_37 \sys_clk_1 + connect \sdrio_clk_38 \sys_clk_1 + connect \sdrio_clk_39 \sys_clk_1 + connect \sdrio_clk_40 \sys_clk_1 + connect \sdrio_clk_41 \sys_clk_1 + connect \sdrio_clk_42 \sys_clk_1 + connect \sdrio_clk_43 \sys_clk_1 + connect \sdrio_clk_44 \sys_clk_1 + connect \sdrio_clk_45 \sys_clk_1 + connect \sdrio_clk_46 \sys_clk_1 + connect \sdrio_clk_47 \sys_clk_1 + connect \sdrio_clk_48 \sys_clk_1 + connect \sdrio_clk_49 \sys_clk_1 + connect \sdrio_clk_50 \sys_clk_1 + connect \sdrio_clk_51 \sys_clk_1 + connect \sdrio_clk_52 \sys_clk_1 + connect \sdrio_clk_53 \sys_clk_1 + connect \sdrio_clk_54 \sys_clk_1 + connect \sdrio_clk_55 \sys_clk_1 + connect \main_uart_phy_rx \builder_multiregimpl0_regs1 + connect \main_pwm0_enable \main_pwm0_enable_storage + connect \main_pwm0_width \main_pwm0_width_storage + connect \main_pwm0_period \main_pwm0_period_storage + connect \main_pwm1_enable \main_pwm1_enable_storage + connect \main_pwm1_width \main_pwm1_width_storage + connect \main_pwm1_period \main_pwm1_period_storage + connect \sdrio_clk_56 \sys_clk_1 + connect \sdrio_clk_57 \sys_clk_1 + connect \sdrio_clk_58 \sys_clk_1 + connect \sdrio_clk_59 \sys_clk_1 + connect \sdrio_clk_60 \sys_clk_1 + connect \sdrio_clk_61 \sys_clk_1 + connect \sdrio_clk_62 \sys_clk_1 + connect \sdrio_clk_63 \sys_clk_1 + connect \sdrio_clk_64 \sys_clk_1 + connect \sdrio_clk_65 \sys_clk_1 + connect \sdrio_clk_66 \sys_clk_1 + connect \sdrio_clk_67 \sys_clk_1 + connect \sdrio_clk_68 \sys_clk_1 + connect \main_libresocsim_dat_r $memrd$\mem$ls180.v:10370$2916_DATA + connect \main_sram0_dat_r $memrd$\mem_1$ls180.v:10398$2942_DATA + connect \main_sram1_dat_r $memrd$\mem_2$ls180.v:10426$2968_DATA + connect \main_sram2_dat_r $memrd$\mem_3$ls180.v:10454$2994_DATA + connect \main_sram3_dat_r $memrd$\mem_4$ls180.v:10482$3020_DATA + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_r \memdat + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage$ls180.v:10500$3027_DATA + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_r \memdat_1 + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_1$ls180.v:10514$3034_DATA + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_r \memdat_2 + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_2$ls180.v:10528$3041_DATA + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_r \memdat_3 + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_3$ls180.v:10542$3048_DATA + connect \main_uart_tx_fifo_wrport_dat_r \memdat_4 + connect \main_uart_tx_fifo_rdport_dat_r \memdat_5 + connect \main_uart_rx_fifo_wrport_dat_r \memdat_6 + connect \main_uart_rx_fifo_rdport_dat_r \memdat_7 + connect \main_sdblock2mem_fifo_wrport_dat_r \memdat_8 + connect \main_sdblock2mem_fifo_rdport_dat_r $memrd$\storage_6$ls180.v:10590$3069_DATA + connect \main_sdmem2block_fifo_wrport_dat_r \memdat_9 + connect \main_sdmem2block_fifo_rdport_dat_r $memrd$\storage_7$ls180.v:10604$3076_DATA +end +attribute \src "libresoc.v:149327.1-149385.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.lsd_l" +attribute \generator "nMigen" +module \lsd_l + attribute \src "libresoc.v:149328.7-149328.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:149373.3-149381.6" + wire $0\q_int$next[0:0]$7145 + attribute \src "libresoc.v:149371.3-149372.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:149373.3-149381.6" + wire $1\q_int$next[0:0]$7146 + attribute \src "libresoc.v:149350.7-149350.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:149363.17-149363.96" + wire $and$libresoc.v:149363$7135_Y + attribute \src "libresoc.v:149368.17-149368.96" + wire $and$libresoc.v:149368$7140_Y + attribute \src "libresoc.v:149365.18-149365.93" + wire $not$libresoc.v:149365$7137_Y + attribute \src "libresoc.v:149367.17-149367.92" + wire $not$libresoc.v:149367$7139_Y + attribute \src "libresoc.v:149370.17-149370.92" + wire $not$libresoc.v:149370$7142_Y + attribute \src "libresoc.v:149364.18-149364.98" + wire $or$libresoc.v:149364$7136_Y + attribute \src "libresoc.v:149366.18-149366.99" + wire $or$libresoc.v:149366$7138_Y + attribute \src "libresoc.v:149369.17-149369.97" + wire $or$libresoc.v:149369$7141_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 1 \coresync_rst + attribute \src "libresoc.v:149328.7-149328.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire output 4 \q_lsd + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" + wire \qlq_lsd + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \qn_lsd + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire input 3 \r_lsd + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire input 2 \s_lsd + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:149363$7135 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:149363$7135_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:149368$7140 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:149368$7140_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:149365$7137 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_lsd + connect \Y $not$libresoc.v:149365$7137_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:149367$7139 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_lsd + connect \Y $not$libresoc.v:149367$7139_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:149370$7142 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_lsd + connect \Y $not$libresoc.v:149370$7142_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:149364$7136 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_lsd + connect \Y $or$libresoc.v:149364$7136_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:149366$7138 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_lsd + connect \B \q_int + connect \Y $or$libresoc.v:149366$7138_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:149369$7141 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_lsd + connect \Y $or$libresoc.v:149369$7141_Y + end + attribute \src "libresoc.v:149328.7-149328.20" + process $proc$libresoc.v:149328$7147 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:149350.7-149350.19" + process $proc$libresoc.v:149350$7148 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:149371.3-149372.27" + process $proc$libresoc.v:149371$7143 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:149373.3-149381.6" + process $proc$libresoc.v:149373$7144 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$7145 $1\q_int$next[0:0]$7146 + attribute \src "libresoc.v:149374.5-149374.29" + switch \initial + attribute \src "libresoc.v:149374.9-149374.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$7146 1'0 + case + assign $1\q_int$next[0:0]$7146 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$7145 + end + connect \$9 $and$libresoc.v:149363$7135_Y + connect \$11 $or$libresoc.v:149364$7136_Y + connect \$13 $not$libresoc.v:149365$7137_Y + connect \$15 $or$libresoc.v:149366$7138_Y + connect \$1 $not$libresoc.v:149367$7139_Y + connect \$3 $and$libresoc.v:149368$7140_Y + connect \$5 $or$libresoc.v:149369$7141_Y + connect \$7 $not$libresoc.v:149370$7142_Y + connect \qlq_lsd \$15 + connect \qn_lsd \$13 + connect \q_lsd \$11 +end +attribute \src "libresoc.v:149389.1-149923.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.l0.lsmem" +attribute \generator "nMigen" +module \lsmem + attribute \src "libresoc.v:149777.3-149802.6" + wire width 45 $0\dbus__adr$next[44:0]$7234 + attribute \src "libresoc.v:149627.3-149628.35" + wire width 45 $0\dbus__adr[44:0] + attribute \src "libresoc.v:149637.3-149664.6" + wire $0\dbus__cyc$next[0:0]$7208 + attribute \src "libresoc.v:149635.3-149636.35" + wire $0\dbus__cyc[0:0] + attribute \src "libresoc.v:149829.3-149854.6" + wire width 64 $0\dbus__dat_w$next[63:0]$7244 + attribute \src "libresoc.v:149623.3-149624.39" + wire width 64 $0\dbus__dat_w[63:0] + attribute \src "libresoc.v:149721.3-149751.6" + wire width 8 $0\dbus__sel$next[7:0]$7222 + attribute \src "libresoc.v:149631.3-149632.35" + wire width 8 $0\dbus__sel[7:0] + attribute \src "libresoc.v:149665.3-149692.6" + wire $0\dbus__stb$next[0:0]$7214 + attribute \src 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"libresoc.v:149777.3-149802.6" + wire width 45 $2\dbus__adr$next[44:0]$7236 + attribute \src "libresoc.v:149637.3-149664.6" + wire $2\dbus__cyc$next[0:0]$7210 + attribute \src "libresoc.v:149829.3-149854.6" + wire width 64 $2\dbus__dat_w$next[63:0]$7246 + attribute \src "libresoc.v:149721.3-149751.6" + wire width 8 $2\dbus__sel$next[7:0]$7224 + attribute \src "libresoc.v:149665.3-149692.6" + wire $2\dbus__stb$next[0:0]$7216 + attribute \src "libresoc.v:149803.3-149828.6" + wire $2\dbus__we$next[0:0]$7241 + attribute \src "libresoc.v:149901.3-149920.6" + wire width 45 $2\m_badaddr_o$next[44:0]$7261 + attribute \src "libresoc.v:149703.3-149720.6" + wire $2\m_busy_o[0:0] + attribute \src "libresoc.v:149752.3-149776.6" + wire width 64 $2\m_ld_data_o$next[63:0]$7230 + attribute \src "libresoc.v:149855.3-149877.6" + wire $2\m_load_err_o$next[0:0]$7251 + attribute \src "libresoc.v:149878.3-149900.6" + wire $2\m_store_err_o$next[0:0]$7256 + attribute \src "libresoc.v:149777.3-149802.6" + wire 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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:140" + cell $and $and$libresoc.v:149614$7194 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dbus__cyc + connect \B \dbus__err + connect \Y $and$libresoc.v:149614$7194_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" + cell $not $not$libresoc.v:149570$7150 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \m_valid_i + connect \Y $not$libresoc.v:149570$7150_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" + cell $not $not$libresoc.v:149575$7155 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \x_stall_i + connect \Y $not$libresoc.v:149575$7155_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" + cell $not $not$libresoc.v:149578$7158 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \m_valid_i + connect \Y $not$libresoc.v:149578$7158_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" + cell $not $not$libresoc.v:149582$7162 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \x_stall_i + connect \Y $not$libresoc.v:149582$7162_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" + cell $not $not$libresoc.v:149586$7166 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \m_valid_i + connect \Y $not$libresoc.v:149586$7166_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" + cell $not $not$libresoc.v:149590$7170 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \x_stall_i + connect \Y $not$libresoc.v:149590$7170_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" + cell $not $not$libresoc.v:149593$7173 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \m_valid_i + connect \Y $not$libresoc.v:149593$7173_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" + cell $not $not$libresoc.v:149596$7176 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \x_stall_i + connect \Y $not$libresoc.v:149596$7176_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" + cell $not $not$libresoc.v:149598$7178 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \x_stall_i + connect \Y $not$libresoc.v:149598$7178_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" + cell $not $not$libresoc.v:149602$7182 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \x_stall_i + connect \Y $not$libresoc.v:149602$7182_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" + cell $not $not$libresoc.v:149606$7186 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \x_stall_i + connect \Y $not$libresoc.v:149606$7186_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:146" + cell $not $not$libresoc.v:149610$7190 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \m_stall_i + connect \Y $not$libresoc.v:149610$7190_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:142" + cell $not $not$libresoc.v:149611$7191 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dbus__we + connect \Y $not$libresoc.v:149611$7191_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:146" + cell $not $not$libresoc.v:149613$7193 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \m_stall_i + connect \Y $not$libresoc.v:149613$7193_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:146" + cell $not $not$libresoc.v:149615$7195 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \m_stall_i + connect \Y $not$libresoc.v:149615$7195_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" + cell $or $or$libresoc.v:149569$7149 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dbus__ack + connect \B \dbus__err + connect \Y $or$libresoc.v:149569$7149_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" + cell $or $or$libresoc.v:149571$7151 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \$11 + connect \Y $or$libresoc.v:149571$7151_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" + cell $or $or$libresoc.v:149572$7152 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \x_ld_i + connect \B \x_st_i + connect \Y $or$libresoc.v:149572$7152_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" + cell $or $or$libresoc.v:149574$7154 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \x_ld_i + connect \B \x_st_i + connect \Y $or$libresoc.v:149574$7154_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" + cell $or $or$libresoc.v:149577$7157 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dbus__ack + connect \B \dbus__err + connect \Y $or$libresoc.v:149577$7157_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" + cell $or $or$libresoc.v:149579$7159 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$23 + connect \B \$25 + connect \Y $or$libresoc.v:149579$7159_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" + cell $or $or$libresoc.v:149580$7160 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \x_ld_i + connect \B \x_st_i + connect \Y $or$libresoc.v:149580$7160_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" + cell $or $or$libresoc.v:149584$7164 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dbus__ack + connect \B \dbus__err + connect \Y $or$libresoc.v:149584$7164_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" + cell $or $or$libresoc.v:149587$7167 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$37 + connect \B \$39 + connect \Y $or$libresoc.v:149587$7167_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" + cell $or $or$libresoc.v:149588$7168 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \x_ld_i + connect \B \x_st_i + connect \Y $or$libresoc.v:149588$7168_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" + cell $or $or$libresoc.v:149592$7172 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dbus__ack + connect \B \dbus__err + connect \Y $or$libresoc.v:149592$7172_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" + cell $or $or$libresoc.v:149594$7174 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$51 + connect \B \$53 + connect \Y $or$libresoc.v:149594$7174_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" + cell $or $or$libresoc.v:149595$7175 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \x_ld_i + connect \B \x_st_i + connect \Y $or$libresoc.v:149595$7175_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" + cell $or $or$libresoc.v:149600$7180 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \x_ld_i + connect \B \x_st_i + connect \Y $or$libresoc.v:149600$7180_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" + cell $or $or$libresoc.v:149604$7184 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \x_ld_i + connect \B \x_st_i + connect \Y $or$libresoc.v:149604$7184_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:154" + cell $or $or$libresoc.v:149616$7196 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \m_load_err_o + connect \B \m_store_err_o + connect \Y $or$libresoc.v:149616$7196_Y + end + attribute \src "libresoc.v:149390.7-149390.20" + process $proc$libresoc.v:149390$7263 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:149495.14-149495.42" + process $proc$libresoc.v:149495$7264 + assign { } { } + assign $1\dbus__adr[44:0] 45'000000000000000000000000000000000000000000000 + sync always + sync init + update \dbus__adr $1\dbus__adr[44:0] + end + attribute \src "libresoc.v:149500.7-149500.23" + process $proc$libresoc.v:149500$7265 + assign { } { } + assign $1\dbus__cyc[0:0] 1'0 + sync always + sync init + update \dbus__cyc $1\dbus__cyc[0:0] + end + attribute \src "libresoc.v:149507.14-149507.48" + process $proc$libresoc.v:149507$7266 + assign { } { } + assign $1\dbus__dat_w[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \dbus__dat_w $1\dbus__dat_w[63:0] + end + attribute \src "libresoc.v:149514.13-149514.30" + process $proc$libresoc.v:149514$7267 + assign { } { } + assign $1\dbus__sel[7:0] 8'00000000 + sync always + sync init + update \dbus__sel $1\dbus__sel[7:0] + end + attribute \src "libresoc.v:149519.7-149519.23" + process $proc$libresoc.v:149519$7268 + assign { } { } + assign $1\dbus__stb[0:0] 1'0 + sync always + sync init + update \dbus__stb $1\dbus__stb[0:0] + end + attribute \src "libresoc.v:149524.7-149524.22" + process $proc$libresoc.v:149524$7269 + assign { } { } + assign $1\dbus__we[0:0] 1'0 + sync always + sync init + update \dbus__we $1\dbus__we[0:0] + end + attribute \src "libresoc.v:149528.14-149528.44" + process $proc$libresoc.v:149528$7270 + assign { } { } + assign $1\m_badaddr_o[44:0] 45'000000000000000000000000000000000000000000000 + sync always + sync init + update \m_badaddr_o $1\m_badaddr_o[44:0] + end + attribute \src "libresoc.v:149535.14-149535.48" + process $proc$libresoc.v:149535$7271 + assign { } { } + assign $1\m_ld_data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \m_ld_data_o $1\m_ld_data_o[63:0] + end + attribute \src "libresoc.v:149539.7-149539.26" + process $proc$libresoc.v:149539$7272 + assign { } { } + assign $1\m_load_err_o[0:0] 1'0 + sync always + sync init + update \m_load_err_o $1\m_load_err_o[0:0] + end + attribute \src "libresoc.v:149545.7-149545.27" + process $proc$libresoc.v:149545$7273 + assign { } { } + assign $1\m_store_err_o[0:0] 1'0 + sync always + sync init + update \m_store_err_o $1\m_store_err_o[0:0] + end + attribute \src "libresoc.v:149617.3-149618.39" + process $proc$libresoc.v:149617$7197 + assign { } { } + assign $0\m_badaddr_o[44:0] \m_badaddr_o$next + sync posedge \coresync_clk + update \m_badaddr_o $0\m_badaddr_o[44:0] + end + attribute \src "libresoc.v:149619.3-149620.43" + process $proc$libresoc.v:149619$7198 + assign { } { } + assign $0\m_store_err_o[0:0] \m_store_err_o$next + sync posedge \coresync_clk + update \m_store_err_o $0\m_store_err_o[0:0] + end + attribute \src "libresoc.v:149621.3-149622.41" + process $proc$libresoc.v:149621$7199 + assign { } { } + assign $0\m_load_err_o[0:0] \m_load_err_o$next + sync posedge \coresync_clk + update \m_load_err_o $0\m_load_err_o[0:0] + end + attribute \src "libresoc.v:149623.3-149624.39" + process $proc$libresoc.v:149623$7200 + assign { } { } + assign $0\dbus__dat_w[63:0] \dbus__dat_w$next + sync posedge \coresync_clk + update \dbus__dat_w $0\dbus__dat_w[63:0] + end + attribute \src "libresoc.v:149625.3-149626.33" + process $proc$libresoc.v:149625$7201 + assign { } { } + assign $0\dbus__we[0:0] \dbus__we$next + sync posedge \coresync_clk + update \dbus__we $0\dbus__we[0:0] + end + attribute \src "libresoc.v:149627.3-149628.35" + process $proc$libresoc.v:149627$7202 + assign { } { } + assign $0\dbus__adr[44:0] \dbus__adr$next + sync posedge \coresync_clk + update \dbus__adr $0\dbus__adr[44:0] + end + attribute \src "libresoc.v:149629.3-149630.39" + process $proc$libresoc.v:149629$7203 + assign { } { } + assign $0\m_ld_data_o[63:0] \m_ld_data_o$next + sync posedge \coresync_clk + update \m_ld_data_o $0\m_ld_data_o[63:0] + end + attribute \src "libresoc.v:149631.3-149632.35" + process $proc$libresoc.v:149631$7204 + assign { } { } + assign $0\dbus__sel[7:0] \dbus__sel$next + sync posedge \coresync_clk + update \dbus__sel $0\dbus__sel[7:0] + end + attribute \src "libresoc.v:149633.3-149634.35" + process $proc$libresoc.v:149633$7205 + assign { } { } + assign $0\dbus__stb[0:0] \dbus__stb$next + sync posedge \coresync_clk + update \dbus__stb $0\dbus__stb[0:0] + end + attribute \src "libresoc.v:149635.3-149636.35" + process $proc$libresoc.v:149635$7206 + assign { } { } + assign $0\dbus__cyc[0:0] \dbus__cyc$next + sync posedge \coresync_clk + update \dbus__cyc $0\dbus__cyc[0:0] + end + attribute \src "libresoc.v:149637.3-149664.6" + process $proc$libresoc.v:149637$7207 + assign { } { } + assign { } { } + assign { } { } + assign $0\dbus__cyc$next[0:0]$7208 $4\dbus__cyc$next[0:0]$7212 + attribute \src "libresoc.v:149638.5-149638.29" + switch \initial + attribute \src "libresoc.v:149638.9-149638.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:111" + switch \wb_dcache_en + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dbus__cyc$next[0:0]$7209 $2\dbus__cyc$next[0:0]$7210 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + switch { \$7 \dbus__cyc } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $2\dbus__cyc$next[0:0]$7210 $3\dbus__cyc$next[0:0]$7211 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" + switch \$13 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\dbus__cyc$next[0:0]$7211 1'0 + case + assign $3\dbus__cyc$next[0:0]$7211 \dbus__cyc + end + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $2\dbus__cyc$next[0:0]$7210 1'1 + case + assign $2\dbus__cyc$next[0:0]$7210 \dbus__cyc + end + case + assign $1\dbus__cyc$next[0:0]$7209 \dbus__cyc + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\dbus__cyc$next[0:0]$7212 1'0 + case + assign $4\dbus__cyc$next[0:0]$7212 $1\dbus__cyc$next[0:0]$7209 + end + sync always + update \dbus__cyc$next $0\dbus__cyc$next[0:0]$7208 + end + attribute \src "libresoc.v:149665.3-149692.6" + process $proc$libresoc.v:149665$7213 + assign { } { } + assign { } { } + assign { } { } + assign $0\dbus__stb$next[0:0]$7214 $4\dbus__stb$next[0:0]$7218 + attribute \src "libresoc.v:149666.5-149666.29" + switch \initial + attribute \src "libresoc.v:149666.9-149666.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:111" + switch \wb_dcache_en + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dbus__stb$next[0:0]$7215 $2\dbus__stb$next[0:0]$7216 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + switch { \$21 \dbus__cyc } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $2\dbus__stb$next[0:0]$7216 $3\dbus__stb$next[0:0]$7217 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" + switch \$27 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\dbus__stb$next[0:0]$7217 1'0 + case + assign $3\dbus__stb$next[0:0]$7217 \dbus__stb + end + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $2\dbus__stb$next[0:0]$7216 1'1 + case + assign $2\dbus__stb$next[0:0]$7216 \dbus__stb + end + case + assign $1\dbus__stb$next[0:0]$7215 \dbus__stb + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\dbus__stb$next[0:0]$7218 1'0 + case + assign $4\dbus__stb$next[0:0]$7218 $1\dbus__stb$next[0:0]$7215 + end + sync always + update \dbus__stb$next $0\dbus__stb$next[0:0]$7214 + end + attribute \src "libresoc.v:149693.3-149702.6" + process $proc$libresoc.v:149693$7219 + assign { } { } + assign { } { } + assign $0\x_busy_o[0:0] $1\x_busy_o[0:0] + attribute \src "libresoc.v:149694.5-149694.29" + switch \initial + attribute \src "libresoc.v:149694.9-149694.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:111" + switch \wb_dcache_en + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\x_busy_o[0:0] \dbus__cyc + case + assign $1\x_busy_o[0:0] 1'0 + end + sync always + update \x_busy_o $0\x_busy_o[0:0] + end + attribute \src "libresoc.v:149703.3-149720.6" + process $proc$libresoc.v:149703$7220 + assign { } { } + assign { } { } + assign $0\m_busy_o[0:0] $1\m_busy_o[0:0] + attribute \src "libresoc.v:149704.5-149704.29" + switch \initial + attribute \src "libresoc.v:149704.9-149704.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:111" + switch \wb_dcache_en + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\m_busy_o[0:0] $2\m_busy_o[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:154" + switch \$95 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\m_busy_o[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\m_busy_o[0:0] \dbus__cyc + end + case + assign $1\m_busy_o[0:0] 1'0 + end + sync always + update \m_busy_o $0\m_busy_o[0:0] + end + attribute \src "libresoc.v:149721.3-149751.6" + process $proc$libresoc.v:149721$7221 + assign { } { } + assign { } { } + assign { } { } + assign $0\dbus__sel$next[7:0]$7222 $4\dbus__sel$next[7:0]$7226 + attribute \src "libresoc.v:149722.5-149722.29" + switch \initial + attribute \src "libresoc.v:149722.9-149722.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:111" + switch \wb_dcache_en + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dbus__sel$next[7:0]$7223 $2\dbus__sel$next[7:0]$7224 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + switch { \$35 \dbus__cyc } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $2\dbus__sel$next[7:0]$7224 $3\dbus__sel$next[7:0]$7225 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" + switch \$41 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\dbus__sel$next[7:0]$7225 8'00000000 + case + assign $3\dbus__sel$next[7:0]$7225 \dbus__sel + end + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $2\dbus__sel$next[7:0]$7224 \x_mask_i + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\dbus__sel$next[7:0]$7224 8'00000000 + end + case + assign $1\dbus__sel$next[7:0]$7223 \dbus__sel + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\dbus__sel$next[7:0]$7226 8'00000000 + case + assign $4\dbus__sel$next[7:0]$7226 $1\dbus__sel$next[7:0]$7223 + end + sync always + update \dbus__sel$next $0\dbus__sel$next[7:0]$7222 + end + attribute \src "libresoc.v:149752.3-149776.6" + process $proc$libresoc.v:149752$7227 + assign { } { } + assign { } { } + assign { } { } + assign $0\m_ld_data_o$next[63:0]$7228 $4\m_ld_data_o$next[63:0]$7232 + attribute \src "libresoc.v:149753.5-149753.29" + switch \initial + attribute \src "libresoc.v:149753.9-149753.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:111" + switch \wb_dcache_en + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\m_ld_data_o$next[63:0]$7229 $2\m_ld_data_o$next[63:0]$7230 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + switch { \$49 \dbus__cyc } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $2\m_ld_data_o$next[63:0]$7230 $3\m_ld_data_o$next[63:0]$7231 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" + switch \$55 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\m_ld_data_o$next[63:0]$7231 \dbus__dat_r + case + assign $3\m_ld_data_o$next[63:0]$7231 \m_ld_data_o + end + case + assign $2\m_ld_data_o$next[63:0]$7230 \m_ld_data_o + end + case + assign $1\m_ld_data_o$next[63:0]$7229 \m_ld_data_o + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\m_ld_data_o$next[63:0]$7232 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $4\m_ld_data_o$next[63:0]$7232 $1\m_ld_data_o$next[63:0]$7229 + end + sync always + update \m_ld_data_o$next $0\m_ld_data_o$next[63:0]$7228 + end + attribute \src "libresoc.v:149777.3-149802.6" + process $proc$libresoc.v:149777$7233 + assign { } { } + assign { } { } + assign { } { } + assign $0\dbus__adr$next[44:0]$7234 $3\dbus__adr$next[44:0]$7237 + attribute \src "libresoc.v:149778.5-149778.29" + switch \initial + attribute \src "libresoc.v:149778.9-149778.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:111" + switch \wb_dcache_en + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dbus__adr$next[44:0]$7235 $2\dbus__adr$next[44:0]$7236 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + switch { \$63 \dbus__cyc } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign $2\dbus__adr$next[44:0]$7236 \dbus__adr + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $2\dbus__adr$next[44:0]$7236 \x_addr_i [47:3] + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\dbus__adr$next[44:0]$7236 45'000000000000000000000000000000000000000000000 + end + case + assign $1\dbus__adr$next[44:0]$7235 \dbus__adr + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\dbus__adr$next[44:0]$7237 45'000000000000000000000000000000000000000000000 + case + assign $3\dbus__adr$next[44:0]$7237 $1\dbus__adr$next[44:0]$7235 + end + sync always + update \dbus__adr$next $0\dbus__adr$next[44:0]$7234 + end + attribute \src "libresoc.v:149803.3-149828.6" + process $proc$libresoc.v:149803$7238 + assign { } { } + assign { } { } + assign { } { } + assign $0\dbus__we$next[0:0]$7239 $3\dbus__we$next[0:0]$7242 + attribute \src "libresoc.v:149804.5-149804.29" + switch \initial + attribute \src "libresoc.v:149804.9-149804.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:111" + switch \wb_dcache_en + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dbus__we$next[0:0]$7240 $2\dbus__we$next[0:0]$7241 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + switch { \$71 \dbus__cyc } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign $2\dbus__we$next[0:0]$7241 \dbus__we + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $2\dbus__we$next[0:0]$7241 \x_st_i + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\dbus__we$next[0:0]$7241 1'0 + end + case + assign $1\dbus__we$next[0:0]$7240 \dbus__we + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\dbus__we$next[0:0]$7242 1'0 + case + assign $3\dbus__we$next[0:0]$7242 $1\dbus__we$next[0:0]$7240 + end + sync always + update \dbus__we$next $0\dbus__we$next[0:0]$7239 + end + attribute \src "libresoc.v:149829.3-149854.6" + process $proc$libresoc.v:149829$7243 + assign { } { } + assign { } { } + assign { } { } + assign $0\dbus__dat_w$next[63:0]$7244 $3\dbus__dat_w$next[63:0]$7247 + attribute \src "libresoc.v:149830.5-149830.29" + switch \initial + attribute \src "libresoc.v:149830.9-149830.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:111" + switch \wb_dcache_en + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dbus__dat_w$next[63:0]$7245 $2\dbus__dat_w$next[63:0]$7246 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + switch { \$79 \dbus__cyc } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign $2\dbus__dat_w$next[63:0]$7246 \dbus__dat_w + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $2\dbus__dat_w$next[63:0]$7246 \x_st_data_i + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\dbus__dat_w$next[63:0]$7246 64'0000000000000000000000000000000000000000000000000000000000000000 + end + case + assign $1\dbus__dat_w$next[63:0]$7245 \dbus__dat_w + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\dbus__dat_w$next[63:0]$7247 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $3\dbus__dat_w$next[63:0]$7247 $1\dbus__dat_w$next[63:0]$7245 + end + sync always + update \dbus__dat_w$next $0\dbus__dat_w$next[63:0]$7244 + end + attribute \src "libresoc.v:149855.3-149877.6" + process $proc$libresoc.v:149855$7248 + assign { } { } + assign { } { } + assign { } { } + assign $0\m_load_err_o$next[0:0]$7249 $3\m_load_err_o$next[0:0]$7252 + attribute \src "libresoc.v:149856.5-149856.29" + switch \initial + attribute \src "libresoc.v:149856.9-149856.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:111" + switch \wb_dcache_en + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\m_load_err_o$next[0:0]$7250 $2\m_load_err_o$next[0:0]$7251 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:140" + switch { \$83 \$81 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $2\m_load_err_o$next[0:0]$7251 \$85 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $2\m_load_err_o$next[0:0]$7251 1'0 + case + assign $2\m_load_err_o$next[0:0]$7251 \m_load_err_o + end + case + assign $1\m_load_err_o$next[0:0]$7250 \m_load_err_o + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\m_load_err_o$next[0:0]$7252 1'0 + case + assign $3\m_load_err_o$next[0:0]$7252 $1\m_load_err_o$next[0:0]$7250 + end + sync always + update \m_load_err_o$next $0\m_load_err_o$next[0:0]$7249 + end + attribute \src "libresoc.v:149878.3-149900.6" + process $proc$libresoc.v:149878$7253 + assign { } { } + assign { } { } + assign { } { } + assign $0\m_store_err_o$next[0:0]$7254 $3\m_store_err_o$next[0:0]$7257 + attribute \src "libresoc.v:149879.5-149879.29" + switch \initial + attribute \src "libresoc.v:149879.9-149879.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:111" + switch \wb_dcache_en + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\m_store_err_o$next[0:0]$7255 $2\m_store_err_o$next[0:0]$7256 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:140" + switch { \$89 \$87 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $2\m_store_err_o$next[0:0]$7256 \dbus__we + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $2\m_store_err_o$next[0:0]$7256 1'0 + case + assign $2\m_store_err_o$next[0:0]$7256 \m_store_err_o + end + case + assign $1\m_store_err_o$next[0:0]$7255 \m_store_err_o + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\m_store_err_o$next[0:0]$7257 1'0 + case + assign $3\m_store_err_o$next[0:0]$7257 $1\m_store_err_o$next[0:0]$7255 + end + sync always + update \m_store_err_o$next $0\m_store_err_o$next[0:0]$7254 + end + attribute \src "libresoc.v:149901.3-149920.6" + process $proc$libresoc.v:149901$7258 + assign { } { } + assign { } { } + assign { } { } + assign $0\m_badaddr_o$next[44:0]$7259 $3\m_badaddr_o$next[44:0]$7262 + attribute \src "libresoc.v:149902.5-149902.29" + switch \initial + attribute \src "libresoc.v:149902.9-149902.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:111" + switch \wb_dcache_en + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\m_badaddr_o$next[44:0]$7260 $2\m_badaddr_o$next[44:0]$7261 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:140" + switch { \$93 \$91 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $2\m_badaddr_o$next[44:0]$7261 \dbus__adr + case + assign $2\m_badaddr_o$next[44:0]$7261 \m_badaddr_o + end + case + assign $1\m_badaddr_o$next[44:0]$7260 \m_badaddr_o + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\m_badaddr_o$next[44:0]$7262 45'000000000000000000000000000000000000000000000 + case + assign $3\m_badaddr_o$next[44:0]$7262 $1\m_badaddr_o$next[44:0]$7260 + end + sync always + update \m_badaddr_o$next $0\m_badaddr_o$next[44:0]$7259 + end + connect \$9 $or$libresoc.v:149569$7149_Y + connect \$11 $not$libresoc.v:149570$7150_Y + connect \$13 $or$libresoc.v:149571$7151_Y + connect \$15 $or$libresoc.v:149572$7152_Y + connect \$17 $and$libresoc.v:149573$7153_Y + connect \$1 $or$libresoc.v:149574$7154_Y + connect \$19 $not$libresoc.v:149575$7155_Y + connect \$21 $and$libresoc.v:149576$7156_Y + connect \$23 $or$libresoc.v:149577$7157_Y + connect \$25 $not$libresoc.v:149578$7158_Y + connect \$27 $or$libresoc.v:149579$7159_Y + connect \$29 $or$libresoc.v:149580$7160_Y + connect \$31 $and$libresoc.v:149581$7161_Y + connect \$33 $not$libresoc.v:149582$7162_Y + connect \$35 $and$libresoc.v:149583$7163_Y + connect \$37 $or$libresoc.v:149584$7164_Y + connect \$3 $and$libresoc.v:149585$7165_Y + connect \$39 $not$libresoc.v:149586$7166_Y + connect \$41 $or$libresoc.v:149587$7167_Y + connect \$43 $or$libresoc.v:149588$7168_Y + connect \$45 $and$libresoc.v:149589$7169_Y + connect \$47 $not$libresoc.v:149590$7170_Y + connect \$49 $and$libresoc.v:149591$7171_Y + connect \$51 $or$libresoc.v:149592$7172_Y + connect \$53 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"/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:61" + wire width 66 \add_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:62" + wire width 66 \add_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:63" + wire width 66 \add_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 17 \alu_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 40 \alu_op__data_len$18 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 input 2 \alu_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 output 25 \alu_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 3 \alu_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 26 \alu_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 4 \alu_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 27 \alu_op__imm_data__ok$5 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 13 \alu_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 36 \alu_op__input_carry$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 18 \alu_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 41 \alu_op__insn$19 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \alu_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 24 \alu_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \alu_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 32 \alu_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 11 \alu_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 34 \alu_op__invert_out$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 15 \alu_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 38 \alu_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 16 \alu_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 39 \alu_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 7 \alu_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 30 \alu_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \alu_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 31 \alu_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \alu_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 37 \alu_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 6 \alu_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 29 \alu_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 5 \alu_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 28 \alu_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \alu_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 35 \alu_op__write_cr0$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \alu_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 33 \alu_op__zero_a$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:66" + wire width 64 \b_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:150" + wire width 2 \ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:100" + wire \carry_32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:101" + wire \carry_64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 output 44 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 45 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:178" + wire width 8 \eqs + attribute \src "libresoc.v:149928.7-149928.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:54" + wire \is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:104" + wire \msb_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:105" + wire \msb_b + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 input 51 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 output 23 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 42 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 43 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:156" + wire width 2 \ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 19 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 20 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:179" + wire width 8 \src1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:98" + wire width 5 \tval + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 input 22 \xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 output 46 \xer_ca$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 47 \xer_ca_ok + attribute \src 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$eq$libresoc.v:150416$7305_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:81" + cell $eq $eq$libresoc.v:150418$7307 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \alu_op__insn_type + connect \B 7'0000010 + connect \Y $eq$libresoc.v:150418$7307_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" + cell $eq $eq$libresoc.v:150419$7308 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \alu_op__insn_type + connect \B 7'0001010 + connect \Y $eq$libresoc.v:150419$7308_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:123" + cell $ne $ne$libresoc.v:150433$7322 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \msb_a + connect \B \msb_b + connect \Y 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parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_op__insn [21] + connect \Y $not$libresoc.v:150409$7298_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:109" + cell $not $not$libresoc.v:150422$7311 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \ra + connect \Y $not$libresoc.v:150422$7311_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:113" + cell $not $not$libresoc.v:150427$7316 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$58 + connect \Y $not$libresoc.v:150427$7316_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:114" + cell $not $not$libresoc.v:150430$7319 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$64 + connect \Y $not$libresoc.v:150430$7319_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:132" 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"/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:183" + cell $reduce_or $reduce_or$libresoc.v:150389$7278 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \eqs + connect \Y $reduce_or$libresoc.v:150389$7278_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:113" + cell $reduce_or $reduce_or$libresoc.v:150426$7315 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \Y_WIDTH 1 + connect \A \$59 + connect \Y $reduce_or$libresoc.v:150426$7315_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:114" + cell $reduce_or $reduce_or$libresoc.v:150429$7318 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \Y_WIDTH 1 + connect \A \$65 + connect \Y $reduce_or$libresoc.v:150429$7318_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:120" + cell $mux $ternary$libresoc.v:150438$7327 + parameter \WIDTH 1 + connect \A \a_n [63] + connect \B \a_n [31] + connect \S \is_32bit + connect \Y $ternary$libresoc.v:150438$7327_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:121" + cell $mux $ternary$libresoc.v:150441$7330 + parameter \WIDTH 1 + connect \A \rb [63] + connect \B \rb [31] + connect \S \is_32bit + connect \Y $ternary$libresoc.v:150441$7330_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:131" + cell $mux $ternary$libresoc.v:150445$7334 + parameter \WIDTH 1 + connect \A \carry_64 + connect \B \carry_32 + connect \S \is_32bit + connect \Y $ternary$libresoc.v:150445$7334_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:152" + cell $xor $xor$libresoc.v:150390$7279 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \a_i [32] + connect \B \b_i [32] + connect \Y $xor$libresoc.v:150390$7279_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:152" + cell $xor $xor$libresoc.v:150391$7280 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \add_o [33] + connect \B \$109 + connect \Y $xor$libresoc.v:150391$7280_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" + cell $xor $xor$libresoc.v:150392$7281 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ca [0] + connect \B \add_o [64] + connect \Y $xor$libresoc.v:150392$7281_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" + cell $xor $xor$libresoc.v:150393$7282 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \a_i [63] + connect \B \b_i [63] + connect \Y $xor$libresoc.v:150393$7282_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" + cell $xor $xor$libresoc.v:150396$7285 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ca [1] + connect \B \add_o [32] + connect \Y $xor$libresoc.v:150396$7285_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" + cell $xor $xor$libresoc.v:150397$7286 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \a_i [31] + connect \B \b_i [31] + connect \Y $xor$libresoc.v:150397$7286_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:110" + cell $xor $xor$libresoc.v:150423$7312 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \add_o [33] + connect \B \ra [32] + connect \Y $xor$libresoc.v:150423$7312_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:110" + cell $xor $xor$libresoc.v:150424$7313 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$53 + connect \B \rb [32] + connect \Y $xor$libresoc.v:150424$7313_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:113" + cell $xor $xor$libresoc.v:150425$7314 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 32 + connect \A \a_n [31:0] + connect \B \rb [31:0] + connect \Y $xor$libresoc.v:150425$7314_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:114" + cell $xor $xor$libresoc.v:150428$7317 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 32 + connect \A \a_n [63:32] + connect \B \rb [63:32] + connect \Y $xor$libresoc.v:150428$7317_Y + end + attribute \src "libresoc.v:149928.7-149928.20" + process $proc$libresoc.v:149928$7364 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:150446.3-150455.6" + process $proc$libresoc.v:150446$7335 + assign { } { } + assign { } { } + assign $0\is_32bit[0:0] $1\is_32bit[0:0] + attribute \src "libresoc.v:150447.5-150447.29" + switch \initial + attribute \src "libresoc.v:150447.9-150447.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:56" + switch \$22 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\is_32bit[0:0] \$24 + case + assign $1\is_32bit[0:0] 1'0 + end + sync always + update \is_32bit $0\is_32bit[0:0] + end + attribute \src "libresoc.v:150456.3-150478.6" + process $proc$libresoc.v:150456$7336 + assign { } { } + assign $0\a_i[63:0] $1\a_i[63:0] + attribute \src "libresoc.v:150457.5-150457.29" + switch \initial + attribute \src "libresoc.v:150457.9-150457.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:67" + switch { \is_32bit \$26 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\a_i[63:0] \ra + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\a_i[63:0] $2\a_i[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:71" + switch \alu_op__is_signed + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\a_i[63:0] { \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31:0] } + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\a_i[63:0] { 32'00000000000000000000000000000000 \ra [31:0] } + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\a_i[63:0] \ra + end + sync always + update \a_i $0\a_i[63:0] + end + attribute \src "libresoc.v:150479.3-150489.6" + process $proc$libresoc.v:150479$7337 + assign { } { } + assign { } { } + assign $0\zerohi[0:0] $1\zerohi[0:0] + attribute \src "libresoc.v:150480.5-150480.29" + switch \initial + attribute \src "libresoc.v:150480.9-150480.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" + switch \alu_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0001010 + assign { } { } + assign $1\zerohi[0:0] \$63 + case + assign $1\zerohi[0:0] 1'0 + end + sync always + update \zerohi $0\zerohi[0:0] + end + attribute \src "libresoc.v:150490.3-150516.6" + process $proc$libresoc.v:150490$7338 + assign { } { } + assign { } { } + assign $0\tval[4:0] $1\tval[4:0] + attribute \src "libresoc.v:150491.5-150491.29" + switch \initial + attribute \src "libresoc.v:150491.9-150491.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" + switch \alu_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0001010 + assign { } { } + assign $1\tval[4:0] $2\tval[4:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" + switch \$71 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { $2\tval[4:0] [4:3] $2\tval[4:0] [1:0] } 4'0000 + assign $2\tval[4:0] [2] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\tval[4:0] $3\tval[4:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:123" + switch \$73 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\tval[4:0] { \msb_a \msb_b 1'0 \msb_b \msb_a } + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $3\tval[4:0] { \a_lt \$77 1'0 \a_lt \$75 } + end + end + case + assign $1\tval[4:0] 5'00000 + end + sync always + update \tval $0\tval[4:0] + end + attribute \src "libresoc.v:150517.3-150535.6" + process $proc$libresoc.v:150517$7339 + assign { } { } + assign { } { } + assign $0\msb_a[0:0] $1\msb_a[0:0] + attribute \src "libresoc.v:150518.5-150518.29" + switch \initial + attribute \src "libresoc.v:150518.9-150518.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" + switch \alu_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0001010 + assign { } { } + assign $1\msb_a[0:0] $2\msb_a[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" + switch \$81 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $2\msb_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\msb_a[0:0] \$83 + end + case + assign $1\msb_a[0:0] 1'0 + end + sync always + update \msb_a $0\msb_a[0:0] + end + attribute \src "libresoc.v:150536.3-150554.6" + process $proc$libresoc.v:150536$7340 + assign { } { } + assign { } { } + assign $0\msb_b[0:0] $1\msb_b[0:0] + attribute \src "libresoc.v:150537.5-150537.29" + switch \initial + attribute \src "libresoc.v:150537.9-150537.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" + switch \alu_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0001010 + assign { } { } + assign $1\msb_b[0:0] $2\msb_b[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" + switch \$87 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $2\msb_b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\msb_b[0:0] \$89 + end + case + assign $1\msb_b[0:0] 1'0 + end + sync always + update \msb_b $0\msb_b[0:0] + end + attribute \src "libresoc.v:150555.3-150581.6" + process $proc$libresoc.v:150555$7341 + assign { } { } + assign { } { } + assign $0\a_lt[0:0] $1\a_lt[0:0] + attribute \src "libresoc.v:150556.5-150556.29" + switch \initial + attribute \src "libresoc.v:150556.9-150556.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" + switch \alu_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0001010 + assign { } { } + assign $1\a_lt[0:0] $2\a_lt[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" + switch \$93 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $2\a_lt[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\a_lt[0:0] $3\a_lt[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:123" + switch \$95 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $3\a_lt[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $3\a_lt[0:0] \$97 + end + end + case + assign $1\a_lt[0:0] 1'0 + end + sync always + update \a_lt $0\a_lt[0:0] + end + attribute \src "libresoc.v:150582.3-150607.6" + process $proc$libresoc.v:150582$7342 + assign { } { } + assign { } { } + assign $0\cr_a[3:0] $1\cr_a[3:0] + attribute \src "libresoc.v:150583.5-150583.29" + switch \initial + attribute \src "libresoc.v:150583.9-150583.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" + switch \alu_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0001010 + assign { } { } + assign $1\cr_a[3:0] [1:0] { \tval [2] \xer_so } + assign $1\cr_a[3:0] [3:2] $2\cr_a[3:2] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:134" + switch \alu_op__is_signed + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_a[3:2] \tval [4:3] + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cr_a[3:2] \tval [1:0] + end + attribute \src "libresoc.v:0.0-0.0" + case 7'0001100 + assign { } { } + assign $1\cr_a[3:0] { 1'0 \$99 2'00 } + case + assign $1\cr_a[3:0] 4'0000 + end + sync always + update \cr_a $0\cr_a[3:0] + end + attribute \src "libresoc.v:150608.3-150622.6" + process $proc$libresoc.v:150608$7343 + assign { } { } + assign { } { } + assign $0\cr_a_ok[0:0] $1\cr_a_ok[0:0] + attribute \src "libresoc.v:150609.5-150609.29" + switch \initial + attribute \src "libresoc.v:150609.9-150609.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" + switch \alu_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0001010 + assign { } { } + assign $1\cr_a_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 7'0001100 + assign { } { } + assign $1\cr_a_ok[0:0] 1'1 + case + assign $1\cr_a_ok[0:0] 1'0 + end + sync always + update \cr_a_ok $0\cr_a_ok[0:0] + end + attribute \src "libresoc.v:150623.3-150660.6" + process $proc$libresoc.v:150623$7344 + assign { } { } + assign { } { } + assign $0\o[63:0] $1\o[63:0] + attribute \src "libresoc.v:150624.5-150624.29" + switch \initial + attribute \src "libresoc.v:150624.9-150624.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" + switch \alu_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000010 + assign { } { } + assign $1\o[63:0] \add_o [64:1] + attribute \src "libresoc.v:0.0-0.0" + case 7'0011111 + assign { } { } + assign { } { } + assign { } { } + assign $1\o[63:0] $4\o[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:166" + switch \$101 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\o[63:0] { \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7:0] } + case + assign $2\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:168" + switch \$103 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\o[63:0] { \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15:0] } + case + assign $3\o[63:0] $2\o[63:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:170" + switch \$105 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\o[63:0] { \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31:0] } + case + assign $4\o[63:0] $3\o[63:0] + end + attribute \src "libresoc.v:0.0-0.0" + case 7'0001100 + assign $1\o[63:0] [63:1] 63'000000000000000000000000000000000000000000000000000000000000000 + assign $1\o[63:0] [0] \$107 + case + assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \o $0\o[63:0] + end + attribute \src "libresoc.v:150661.3-150679.6" + process $proc$libresoc.v:150661$7345 + assign { } { } + assign { } { } + assign $0\o_ok[0:0] $1\o_ok[0:0] + attribute \src "libresoc.v:150662.5-150662.29" + switch \initial + attribute \src "libresoc.v:150662.9-150662.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" + switch \alu_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000010 + assign { } { } + assign $1\o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 7'0011111 + assign { } { } + assign $1\o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 7'0001100 + assign { } { } + assign $1\o_ok[0:0] 1'0 + case + assign $1\o_ok[0:0] 1'0 + end + sync always + update \o_ok $0\o_ok[0:0] + end + attribute \src "libresoc.v:150680.3-150693.6" + process $proc$libresoc.v:150680$7346 + assign { } { } + assign { } { } + assign $0\ca[1:0] $1\ca[1:0] + attribute \src "libresoc.v:150681.5-150681.29" + switch \initial + attribute \src "libresoc.v:150681.9-150681.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" + switch \alu_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000010 + assign { } { } + assign $1\ca[1:0] [0] \add_o [65] + assign $1\ca[1:0] [1] \$111 + case + assign $1\ca[1:0] 2'00 + end + sync always + update \ca $0\ca[1:0] + end + attribute \src "libresoc.v:150694.3-150716.6" + process $proc$libresoc.v:150694$7347 + assign { } { } + assign $0\b_i[63:0] $1\b_i[63:0] + attribute \src "libresoc.v:150695.5-150695.29" + switch \initial + attribute \src "libresoc.v:150695.9-150695.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:67" + switch { \is_32bit \$28 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\b_i[63:0] \rb + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\b_i[63:0] $2\b_i[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:71" + switch \alu_op__is_signed + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\b_i[63:0] { \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31:0] } + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\b_i[63:0] { 32'00000000000000000000000000000000 \rb [31:0] } + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\b_i[63:0] \rb + end + sync always + update \b_i $0\b_i[63:0] + end + attribute \src "libresoc.v:150717.3-150727.6" + process $proc$libresoc.v:150717$7348 + assign { } { } + assign { } { } + assign $0\xer_ca$20[1:0]$7349 $1\xer_ca$20[1:0]$7350 + attribute \src "libresoc.v:150718.5-150718.29" + switch \initial + attribute \src "libresoc.v:150718.9-150718.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" + switch \alu_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000010 + assign { } { } + assign $1\xer_ca$20[1:0]$7350 \ca + case + assign $1\xer_ca$20[1:0]$7350 2'00 + end + sync always + update \xer_ca$20 $0\xer_ca$20[1:0]$7349 + end + attribute \src "libresoc.v:150728.3-150738.6" + process $proc$libresoc.v:150728$7351 + assign { } { } + assign { } { } + assign $0\xer_ca_ok[0:0] $1\xer_ca_ok[0:0] + attribute \src "libresoc.v:150729.5-150729.29" + switch \initial + attribute \src "libresoc.v:150729.9-150729.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" + switch \alu_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000010 + assign { } { } + assign $1\xer_ca_ok[0:0] 1'1 + case + assign $1\xer_ca_ok[0:0] 1'0 + end + sync always + update \xer_ca_ok $0\xer_ca_ok[0:0] + end + attribute \src "libresoc.v:150739.3-150752.6" + process $proc$libresoc.v:150739$7352 + assign { } { } + assign { } { } + assign $0\ov[1:0] $1\ov[1:0] + attribute \src "libresoc.v:150740.5-150740.29" + switch \initial + attribute \src "libresoc.v:150740.9-150740.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" + switch \alu_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000010 + assign { } { } + assign $1\ov[1:0] [0] \$119 + assign $1\ov[1:0] [1] \$127 + case + assign $1\ov[1:0] 2'00 + end + sync always + update \ov $0\ov[1:0] + end + attribute \src "libresoc.v:150753.3-150763.6" + process $proc$libresoc.v:150753$7353 + assign { } { } + assign { } { } + assign $0\xer_ov[1:0] $1\xer_ov[1:0] + attribute \src "libresoc.v:150754.5-150754.29" + switch \initial + attribute \src "libresoc.v:150754.9-150754.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" + switch \alu_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000010 + assign { } { } + assign $1\xer_ov[1:0] \ov + case + assign $1\xer_ov[1:0] 2'00 + end + sync always + update \xer_ov $0\xer_ov[1:0] + end + attribute \src "libresoc.v:150764.3-150774.6" + process $proc$libresoc.v:150764$7354 + assign { } { } + assign { } { } + assign $0\xer_ov_ok[0:0] $1\xer_ov_ok[0:0] + attribute \src "libresoc.v:150765.5-150765.29" + switch \initial + attribute \src "libresoc.v:150765.9-150765.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" + switch \alu_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000010 + assign { } { } + assign $1\xer_ov_ok[0:0] 1'1 + case + assign $1\xer_ov_ok[0:0] 1'0 + end + sync always + update \xer_ov_ok $0\xer_ov_ok[0:0] + end + attribute \src "libresoc.v:150775.3-150785.6" + process $proc$libresoc.v:150775$7355 + assign { } { } + assign { } { } + assign $0\src1[7:0] $1\src1[7:0] + attribute \src "libresoc.v:150776.5-150776.29" + switch \initial + attribute \src "libresoc.v:150776.9-150776.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" + switch \alu_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0001100 + assign { } { } + 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$proc$libresoc.v:150806$7357 + assign { } { } + assign { } { } + assign $0\add_a[65:0] $1\add_a[65:0] + attribute \src "libresoc.v:150807.5-150807.29" + switch \initial + attribute \src "libresoc.v:150807.9-150807.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" + switch \$34 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\add_a[65:0] { 1'0 \a_i \xer_ca [0] } + case + assign $1\add_a[65:0] 66'000000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \add_a $0\add_a[65:0] + end + attribute \src "libresoc.v:150816.3-150825.6" + process $proc$libresoc.v:150816$7358 + assign { } { } + assign { } { } + assign $0\add_b[65:0] $1\add_b[65:0] + attribute \src "libresoc.v:150817.5-150817.29" + switch \initial + attribute \src "libresoc.v:150817.9-150817.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" + switch \$40 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"/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:65" + wire \rotator_carry_out_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:60" + wire \rotator_clear_left + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:61" + wire \rotator_clear_right + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:57" + wire \rotator_is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:51" + wire width 5 \rotator_mb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:53" + wire \rotator_mb_extra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:50" + wire width 5 \rotator_me + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:54" + wire width 64 \rotator_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:64" + wire width 64 \rotator_result_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:58" + wire \rotator_right_shift + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:55" + wire width 64 \rotator_rs + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:56" + wire width 7 \rotator_shift + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:62" + wire \rotator_sign_ext_rs + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 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"/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 3 \sr_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 25 \sr_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 4 \sr_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 26 \sr_op__imm_data__ok$5 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 11 \sr_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 33 \sr_op__input_carry$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \sr_op__input_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 35 \sr_op__input_cr$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 17 \sr_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 39 \sr_op__insn$18 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \sr_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 23 \sr_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \sr_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 32 \sr_op__invert_in$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 15 \sr_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 37 \sr_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 16 \sr_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 38 \sr_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 7 \sr_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 29 \sr_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \sr_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 30 \sr_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \sr_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 34 \sr_op__output_carry$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \sr_op__output_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 36 \sr_op__output_cr$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 6 \sr_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 28 \sr_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 5 \sr_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 27 \sr_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \sr_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 31 \sr_op__write_cr0$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 output 43 \xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 21 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 42 \xer_so$19 + attribute \module_not_derived 1 + attribute \src "libresoc.v:151199.11-151214.4" + cell \rotator \rotator + connect \arith \rotator_arith + connect \carry_out_o \rotator_carry_out_o + connect \clear_left \rotator_clear_left + connect \clear_right \rotator_clear_right + connect \is_32bit \rotator_is_32bit + connect \mb \rotator_mb + connect \mb_extra \rotator_mb_extra + connect \me \rotator_me + connect \ra \rotator_ra + connect \result_o \rotator_result_o + connect \right_shift \rotator_right_shift + connect \rs \rotator_rs + connect \shift \rotator_shift + connect \sign_ext_rs \rotator_sign_ext_rs + end + attribute \src "libresoc.v:150889.7-150889.20" + process $proc$libresoc.v:150889$7367 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:151215.3-151249.6" + process $proc$libresoc.v:151215$7365 + assign { } { } + assign { } { } + assign $0\o_ok[0:0] $1\o_ok[0:0] + attribute \src "libresoc.v:151216.5-151216.29" + switch \initial + attribute \src "libresoc.v:151216.9-151216.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:70" + switch \sr_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0111100 + assign $1\o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 7'0111101 + assign $1\o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 7'0111000 + assign $1\o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 7'0111001 + assign $1\o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 7'0111010 + assign $1\o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 7'0100000 + assign $1\o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\o_ok[0:0] 1'0 + end + sync always + update \o_ok $0\o_ok[0:0] + end + attribute \src "libresoc.v:151250.3-151280.6" + process $proc$libresoc.v:151250$7366 + assign { } { } + assign { } { } + assign $0\mode[3:0] $1\mode[3:0] + attribute \src "libresoc.v:151251.5-151251.29" + switch \initial + attribute \src "libresoc.v:151251.9-151251.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:70" + switch \sr_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0111100 + assign { } { } + assign $1\mode[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0111101 + assign { } { } + assign $1\mode[3:0] 4'0001 + attribute \src "libresoc.v:0.0-0.0" + case 7'0111000 + assign { } { } + assign $1\mode[3:0] 4'0110 + attribute \src "libresoc.v:0.0-0.0" + case 7'0111001 + assign { } { } + assign $1\mode[3:0] 4'0010 + attribute \src "libresoc.v:0.0-0.0" + case 7'0111010 + assign { } { } + assign $1\mode[3:0] 4'0100 + attribute \src "libresoc.v:0.0-0.0" + case 7'0100000 + assign { } { } + assign $1\mode[3:0] 4'1000 + case + assign $1\mode[3:0] 4'0000 + end + sync always + update \mode $0\mode[3:0] + end + connect { \sr_op__insn$18 \sr_op__is_signed$17 \sr_op__is_32bit$16 \sr_op__output_cr$15 \sr_op__input_cr$14 \sr_op__output_carry$13 \sr_op__input_carry$12 \sr_op__invert_in$11 \sr_op__write_cr0$10 \sr_op__oe__ok$9 \sr_op__oe__oe$8 \sr_op__rc__ok$7 \sr_op__rc__rc$6 \sr_op__imm_data__ok$5 \sr_op__imm_data__data$4 \sr_op__fn_unit$3 \sr_op__insn_type$2 } { \sr_op__insn \sr_op__is_signed \sr_op__is_32bit \sr_op__output_cr \sr_op__input_cr \sr_op__output_carry \sr_op__input_carry \sr_op__invert_in \sr_op__write_cr0 \sr_op__oe__ok \sr_op__oe__oe \sr_op__rc__ok \sr_op__rc__rc \sr_op__imm_data__ok \sr_op__imm_data__data \sr_op__fn_unit \sr_op__insn_type } + connect \muxid$1 \muxid + connect \xer_so$19 \xer_so + connect \xer_ca { \rotator_carry_out_o \rotator_carry_out_o } + connect \o \rotator_result_o + connect { \rotator_sign_ext_rs \rotator_clear_right \rotator_clear_left \rotator_right_shift } \mode + connect \rotator_arith \sr_op__is_signed + connect \rotator_is_32bit \sr_op__is_32bit + connect \rotator_shift \rb [6:0] + connect \rotator_ra \ra + connect \rotator_rs \rc + connect \rotator_mb_extra \mb_extra + connect \rotator_mb \mb + connect \rotator_me \me + connect \mb_extra \sr_op__insn [5] + connect \me \sr_op__insn [5:1] + connect \mb \sr_op__insn [10:6] +end +attribute \src "libresoc.v:151302.1-151834.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.alu_branch0.pipe.main" +attribute \generator "nMigen" +module \main$22 + attribute \src "libresoc.v:151741.3-151764.6" + wire $0\bc_taken[0:0] + attribute \src "libresoc.v:151620.3-151631.6" + wire width 64 $0\br_addr[63:0] + attribute \src "libresoc.v:151632.3-151658.6" + wire width 64 $0\br_imm_addr[63:0] + attribute \src "libresoc.v:151659.3-151677.6" + wire $0\br_taken[0:0] + attribute \src "libresoc.v:151713.3-151727.6" + wire $0\cr_bit[0:0] + attribute \src "libresoc.v:151791.3-151811.6" + wire width 64 $0\ctr_m[63:0] + attribute \src "libresoc.v:151765.3-151777.6" + wire width 64 $0\ctr_n[63:0] + attribute \src "libresoc.v:151728.3-151740.6" + wire $0\ctr_write[0:0] + attribute \src "libresoc.v:151812.3-151824.6" + wire $0\ctr_zero_bo1[0:0] + attribute \src "libresoc.v:151778.3-151790.6" + wire width 64 $0\fast1$10[63:0]$7400 + attribute \src "libresoc.v:151678.3-151692.6" + wire $0\fast1_ok[0:0] + attribute \src "libresoc.v:151693.3-151702.6" + wire width 64 $0\fast2$11[63:0]$7392 + attribute \src "libresoc.v:151703.3-151712.6" + wire $0\fast2_ok[0:0] + attribute \src "libresoc.v:151303.7-151303.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:151741.3-151764.6" + wire $1\bc_taken[0:0] + attribute \src "libresoc.v:151620.3-151631.6" + wire width 64 $1\br_addr[63:0] + attribute \src "libresoc.v:151632.3-151658.6" + wire width 64 $1\br_imm_addr[63:0] + attribute \src "libresoc.v:151659.3-151677.6" + wire $1\br_taken[0:0] + attribute \src "libresoc.v:151713.3-151727.6" + wire $1\cr_bit[0:0] + attribute \src "libresoc.v:151791.3-151811.6" + wire width 64 $1\ctr_m[63:0] + attribute \src "libresoc.v:151765.3-151777.6" + wire width 64 $1\ctr_n[63:0] + attribute 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\enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 2 \br_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 14 \br_op__insn_type$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \br_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 20 \br_op__is_32bit$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 7 \br_op__lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 19 \br_op__lk$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:89" + wire \br_taken + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 4 input 11 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:110" + wire \cr_bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:129" + wire width 64 \ctr_m + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:124" + wire width 64 \ctr_n + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:115" + wire \ctr_write + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:135" + wire \ctr_zero_bo1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 9 \fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 21 \fast1$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 22 \fast1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 10 \fast2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 23 \fast2$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 24 \fast2_ok + attribute \src "libresoc.v:151303.7-151303.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 input 27 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 output 12 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 25 \nia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 26 \nia_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:95" + cell $add $add$libresoc.v:151604$7370 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \br_imm_addr + connect \B \br_op__cia + connect \Y $add$libresoc.v:151604$7370_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:175" + cell $add $add$libresoc.v:151619$7386 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 65 + connect \A \br_op__cia + connect \B 3'100 + connect \Y $add$libresoc.v:151619$7386_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:138" + cell $and $and$libresoc.v:151611$7377 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ctr_zero_bo1 + connect \B \$29 + connect \Y $and$libresoc.v:151611$7377_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:140" + cell $and $and$libresoc.v:151612$7378 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ctr_zero_bo1 + connect \B \cr_bit + connect \Y $and$libresoc.v:151612$7378_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:160" + cell $and $and$libresoc.v:151618$7385 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \br_op__insn [10] + connect \B \$44 + connect \Y $and$libresoc.v:151618$7385_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:92" + cell $eq $eq$libresoc.v:151602$7368 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \br_op__insn_type + connect \B 7'0001000 + connect \Y $eq$libresoc.v:151602$7368_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:121" + cell $eq $eq$libresoc.v:151605$7371 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cr_bit + connect \B \bo [3] + connect \Y $eq$libresoc.v:151605$7371_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:137" + cell $eq $eq$libresoc.v:151607$7373 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \bo [4:3] + connect \B 1'0 + connect \Y $eq$libresoc.v:151607$7373_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:139" + cell $eq $eq$libresoc.v:151608$7374 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \bo [4:3] + connect \B 1'1 + connect \Y $eq$libresoc.v:151608$7374_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:141" + cell $eq $eq$libresoc.v:151609$7375 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \bo [4] + connect \B 1'1 + connect \Y $eq$libresoc.v:151609$7375_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" + cell $pos $extend$libresoc.v:151614$7380 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \Y_WIDTH 64 + connect \A \fast1 [31:0] + connect \Y $extend$libresoc.v:151614$7380_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:138" + cell $not $not$libresoc.v:151610$7376 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cr_bit + connect \Y $not$libresoc.v:151610$7376_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:160" + cell $not $not$libresoc.v:151617$7384 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \br_op__insn [6] + connect \Y $not$libresoc.v:151617$7384_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:92" + cell $or $or$libresoc.v:151603$7369 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \br_op__insn [1] + connect \B \$12 + connect \Y $or$libresoc.v:151603$7369_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:121" + cell $or $or$libresoc.v:151606$7372 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$19 + connect \B \bo [4] + connect \Y $or$libresoc.v:151606$7372_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" + cell $pos $pos$libresoc.v:151614$7381 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:151614$7380_Y + connect \Y $pos$libresoc.v:151614$7381_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:136" + cell $reduce_or $reduce_or$libresoc.v:151615$7382 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 1 + connect \A \ctr_n + connect \Y $reduce_or$libresoc.v:151615$7382_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:125" + cell $sub $sub$libresoc.v:151613$7379 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 65 + connect \A \fast1 + connect \B 1'1 + connect \Y $sub$libresoc.v:151613$7379_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:136" + cell $xor $xor$libresoc.v:151616$7383 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \bo [1] + connect \B \$40 + connect \Y $xor$libresoc.v:151616$7383_Y + end + attribute \src "libresoc.v:151303.7-151303.20" + process $proc$libresoc.v:151303$7404 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:151620.3-151631.6" + process $proc$libresoc.v:151620$7387 + assign { } { } + assign $0\br_addr[63:0] $1\br_addr[63:0] + attribute \src "libresoc.v:151621.5-151621.29" + switch \initial + attribute \src "libresoc.v:151621.9-151621.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:92" + switch \$14 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\br_addr[63:0] \br_imm_addr + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\br_addr[63:0] \$16 [63:0] + end + sync always + update \br_addr $0\br_addr[63:0] + end + attribute \src "libresoc.v:151632.3-151658.6" + process $proc$libresoc.v:151632$7388 + assign { } { } + assign { } { } + assign $0\br_imm_addr[63:0] $1\br_imm_addr[63:0] + attribute \src "libresoc.v:151633.5-151633.29" + switch \initial + attribute \src "libresoc.v:151633.9-151633.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:145" + switch \br_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000110 + assign { } { } + assign $1\br_imm_addr[63:0] { \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25:2] 2'00 } + attribute \src "libresoc.v:0.0-0.0" + case 7'0000111 + assign { } { } + assign $1\br_imm_addr[63:0] { \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15:2] 2'00 } + attribute \src "libresoc.v:0.0-0.0" + case 7'0001000 + assign { } { } + assign $1\br_imm_addr[63:0] $2\br_imm_addr[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:160" + switch \$46 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\br_imm_addr[63:0] { \fast1 [63:2] 2'00 } + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\br_imm_addr[63:0] { \fast2 [63:2] 2'00 } + end + case + assign $1\br_imm_addr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \br_imm_addr $0\br_imm_addr[63:0] + end + attribute \src "libresoc.v:151659.3-151677.6" + process $proc$libresoc.v:151659$7389 + assign { } { } + assign { } { } + assign $0\br_taken[0:0] $1\br_taken[0:0] + attribute \src "libresoc.v:151660.5-151660.29" + switch \initial + attribute \src "libresoc.v:151660.9-151660.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:145" + switch \br_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000110 + assign { } { } + assign $1\br_taken[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000111 + assign { } { } + assign $1\br_taken[0:0] \bc_taken + attribute \src "libresoc.v:0.0-0.0" + case 7'0001000 + assign { } { } + assign $1\br_taken[0:0] \bc_taken + case + assign $1\br_taken[0:0] 1'0 + end + sync always + update \br_taken $0\br_taken[0:0] + end + attribute \src "libresoc.v:151678.3-151692.6" + process $proc$libresoc.v:151678$7390 + assign { } { } + assign { } { } + assign $0\fast1_ok[0:0] $1\fast1_ok[0:0] + attribute \src "libresoc.v:151679.5-151679.29" + switch \initial + attribute \src "libresoc.v:151679.9-151679.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:145" + switch \br_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000111 + assign { } { } + assign $1\fast1_ok[0:0] \ctr_write + attribute \src "libresoc.v:0.0-0.0" + case 7'0001000 + assign { } { } + assign $1\fast1_ok[0:0] \ctr_write + case + assign $1\fast1_ok[0:0] 1'0 + end + sync always + update \fast1_ok $0\fast1_ok[0:0] + end + attribute \src "libresoc.v:151693.3-151702.6" + process $proc$libresoc.v:151693$7391 + assign { } { } + assign { } { } + assign $0\fast2$11[63:0]$7392 $1\fast2$11[63:0]$7393 + attribute \src "libresoc.v:151694.5-151694.29" + switch \initial + attribute \src "libresoc.v:151694.9-151694.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:172" + switch \br_op__lk + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fast2$11[63:0]$7393 \$48 [63:0] + case + assign $1\fast2$11[63:0]$7393 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fast2$11 $0\fast2$11[63:0]$7392 + end + attribute \src "libresoc.v:151703.3-151712.6" + process $proc$libresoc.v:151703$7394 + assign { } { } + assign { } { } + assign $0\fast2_ok[0:0] $1\fast2_ok[0:0] + attribute \src "libresoc.v:151704.5-151704.29" + switch \initial + attribute \src "libresoc.v:151704.9-151704.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:172" + switch \br_op__lk + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fast2_ok[0:0] 1'1 + case + assign $1\fast2_ok[0:0] 1'0 + end + sync always + update \fast2_ok $0\fast2_ok[0:0] + end + attribute \src "libresoc.v:151713.3-151727.6" + process $proc$libresoc.v:151713$7395 + assign { } { } + assign { } { } + assign $0\cr_bit[0:0] $1\cr_bit[0:0] + attribute \src "libresoc.v:151714.5-151714.29" + switch \initial + attribute \src "libresoc.v:151714.9-151714.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:112" + switch \bi + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cr_bit[0:0] \cr_a [3] + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cr_bit[0:0] \cr_a [2] + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\cr_bit[0:0] \cr_a [1] + attribute \src "libresoc.v:0.0-0.0" + case 2'-- + assign { } { } + assign $1\cr_bit[0:0] \cr_a [0] + case + assign $1\cr_bit[0:0] 1'0 + end + sync always + update \cr_bit $0\cr_bit[0:0] + end + attribute \src "libresoc.v:151728.3-151740.6" + process $proc$libresoc.v:151728$7396 + assign { } { } + assign { } { } + assign $0\ctr_write[0:0] $1\ctr_write[0:0] + attribute \src "libresoc.v:151729.5-151729.29" + switch \initial + attribute \src "libresoc.v:151729.9-151729.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:120" + switch \bo [2] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $1\ctr_write[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\ctr_write[0:0] 1'1 + end + sync always + update \ctr_write $0\ctr_write[0:0] + end + attribute \src "libresoc.v:151741.3-151764.6" + process $proc$libresoc.v:151741$7397 + assign { } { } + assign { } { } + assign $0\bc_taken[0:0] $1\bc_taken[0:0] + attribute \src "libresoc.v:151742.5-151742.29" + switch \initial + attribute \src "libresoc.v:151742.9-151742.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:120" + switch \bo [2] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\bc_taken[0:0] \$21 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\bc_taken[0:0] $2\bc_taken[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:137" + switch { \$27 \$25 \$23 } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign { } { } + assign $2\bc_taken[0:0] \$31 + attribute \src "libresoc.v:0.0-0.0" + case 3'-1- + assign { } { } + assign $2\bc_taken[0:0] \$33 + attribute \src "libresoc.v:0.0-0.0" + case 3'1-- + assign { } { } + assign $2\bc_taken[0:0] \ctr_zero_bo1 + case + assign $2\bc_taken[0:0] 1'0 + end + end + sync always + update \bc_taken $0\bc_taken[0:0] + end + attribute \src "libresoc.v:151765.3-151777.6" + process $proc$libresoc.v:151765$7398 + assign { } { } + assign { } { } + assign $0\ctr_n[63:0] $1\ctr_n[63:0] + attribute \src "libresoc.v:151766.5-151766.29" + switch \initial + attribute \src "libresoc.v:151766.9-151766.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:120" + switch \bo [2] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $1\ctr_n[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\ctr_n[63:0] \$35 [63:0] + end + sync always + update \ctr_n $0\ctr_n[63:0] + end + attribute \src "libresoc.v:151778.3-151790.6" + process $proc$libresoc.v:151778$7399 + assign { } { } + assign { } { } + assign $0\fast1$10[63:0]$7400 $1\fast1$10[63:0]$7401 + attribute \src "libresoc.v:151779.5-151779.29" + switch \initial + attribute \src "libresoc.v:151779.9-151779.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:120" + switch \bo [2] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $1\fast1$10[63:0]$7401 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\fast1$10[63:0]$7401 \ctr_n + end + sync always + update \fast1$10 $0\fast1$10[63:0]$7400 + end + attribute \src "libresoc.v:151791.3-151811.6" + process $proc$libresoc.v:151791$7402 + assign { } { } + assign { } { } + assign $0\ctr_m[63:0] $1\ctr_m[63:0] + attribute \src "libresoc.v:151792.5-151792.29" + switch \initial + attribute \src "libresoc.v:151792.9-151792.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:120" + switch \bo [2] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $1\ctr_m[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\ctr_m[63:0] $2\ctr_m[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:130" + switch \br_op__is_32bit + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ctr_m[63:0] \$38 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\ctr_m[63:0] \fast1 + end + end + sync always + update \ctr_m $0\ctr_m[63:0] + end + attribute \src "libresoc.v:151812.3-151824.6" + process $proc$libresoc.v:151812$7403 + assign { } { } + assign { } { } + assign $0\ctr_zero_bo1[0:0] $1\ctr_zero_bo1[0:0] + attribute \src "libresoc.v:151813.5-151813.29" + switch \initial + attribute \src "libresoc.v:151813.9-151813.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:120" + switch \bo [2] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $1\ctr_zero_bo1[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\ctr_zero_bo1[0:0] \$42 + end + sync always + update \ctr_zero_bo1 $0\ctr_zero_bo1[0:0] + end + connect \$12 $eq$libresoc.v:151602$7368_Y + connect \$14 $or$libresoc.v:151603$7369_Y + connect \$17 $add$libresoc.v:151604$7370_Y + connect \$19 $eq$libresoc.v:151605$7371_Y + connect \$21 $or$libresoc.v:151606$7372_Y + connect \$23 $eq$libresoc.v:151607$7373_Y + connect \$25 $eq$libresoc.v:151608$7374_Y + connect \$27 $eq$libresoc.v:151609$7375_Y + connect \$29 $not$libresoc.v:151610$7376_Y + connect \$31 $and$libresoc.v:151611$7377_Y + connect \$33 $and$libresoc.v:151612$7378_Y + connect \$36 $sub$libresoc.v:151613$7379_Y + connect \$38 $pos$libresoc.v:151614$7381_Y + connect \$40 $reduce_or$libresoc.v:151615$7382_Y + connect \$42 $xor$libresoc.v:151616$7383_Y + connect \$44 $not$libresoc.v:151617$7384_Y + connect \$46 $and$libresoc.v:151618$7385_Y + connect \$49 $add$libresoc.v:151619$7386_Y + connect \$16 \$17 + connect \$35 \$36 + connect \$48 \$49 + connect { \br_op__is_32bit$9 \br_op__lk$8 \br_op__imm_data__ok$7 \br_op__imm_data__data$6 \br_op__insn$5 \br_op__fn_unit$4 \br_op__insn_type$3 \br_op__cia$2 } { \br_op__is_32bit \br_op__lk \br_op__imm_data__ok \br_op__imm_data__data \br_op__insn \br_op__fn_unit \br_op__insn_type \br_op__cia } + connect \muxid$1 \muxid + connect \nia_ok \br_taken + connect \nia \br_addr + connect \bi \br_op__insn [17:16] + connect \bo \br_op__insn [25:21] +end +attribute \src "libresoc.v:151838.1-152784.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.pipe2.main" +attribute \generator "nMigen" +module \main$38 + attribute \src "libresoc.v:152749.3-152760.6" + wire width 64 $0\a[63:0] + attribute \src "libresoc.v:152247.3-152258.6" + wire width 64 $0\a_s[63:0] + attribute \src "libresoc.v:152761.3-152772.6" + wire width 64 $0\b[63:0] + attribute \src "libresoc.v:152530.3-152541.6" + wire width 64 $0\b_s[63:0] + attribute \src "libresoc.v:152323.3-152354.6" + wire width 64 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31 \nia_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 24 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 25 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 10 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 11 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:176" + wire \should_trap + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:134" + wire width 5 \to + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:171" + wire width 5 \trap_bits + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 5 \trap_op__cia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 19 \trap_op__cia$6 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 input 2 \trap_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute 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attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src 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attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute 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input 4 \trap_op__msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 18 \trap_op__msr$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 input 8 \trap_op__trapaddr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 output 22 \trap_op__trapaddr$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 8 input 7 \trap_op__traptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 8 output 21 \trap_op__traptype$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \trapexc_$signal + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \trapexc_$signal$60 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \trapexc_$signal$61 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \trapexc_$signal$62 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \trapexc_$signal$67 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \trapexc_$signal$68 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \trapexc_$signal$69 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" + wire \trapexc_$signal$70 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:315" + cell $add $add$libresoc.v:152223$7421 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 65 + connect \A \trap_op__cia + connect \B 3'100 + connect \Y $add$libresoc.v:152223$7421_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:177" + cell $and $and$libresoc.v:152217$7414 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \trap_bits + connect \B \to + connect \Y $and$libresoc.v:152217$7414_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:193" + cell $and $and$libresoc.v:152225$7423 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 8 + connect \A \trap_op__traptype + connect \B 2'10 + connect \Y $and$libresoc.v:152225$7423_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:195" + cell $and $and$libresoc.v:152227$7425 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 8 + connect \A \trap_op__traptype + connect \B 1'1 + connect \Y $and$libresoc.v:152227$7425_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:197" + cell $and $and$libresoc.v:152229$7427 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 8 + connect \A \trap_op__traptype + connect \B 4'1000 + connect \Y $and$libresoc.v:152229$7427_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:199" + cell $and $and$libresoc.v:152231$7429 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 8 + connect \A \trap_op__traptype + connect \B 7'1000000 + connect \Y $and$libresoc.v:152231$7429_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:213" + cell $and $and$libresoc.v:152233$7431 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A \trap_op__traptype + connect \B 8'10000000 + connect \Y $and$libresoc.v:152233$7431_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:199" + cell $and $and$libresoc.v:152235$7433 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 8 + connect \A \trap_op__traptype + connect \B 7'1000000 + connect \Y $and$libresoc.v:152235$7433_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:241" + cell $and $and$libresoc.v:152241$7440 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$79 + connect \B \$81 + connect \Y $and$libresoc.v:152241$7440_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:296" + cell $and $and$libresoc.v:152246$7445 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$89 + connect \B \$91 + connect \Y $and$libresoc.v:152246$7445_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:167" + cell $eq $eq$libresoc.v:152216$7413 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 1 + connect \A \a + connect \B \b + connect \Y $eq$libresoc.v:152216$7413_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:190" + cell $eq $eq$libresoc.v:152224$7422 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \trap_op__traptype + connect \B 1'0 + connect \Y $eq$libresoc.v:152224$7422_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:234" + cell $eq $eq$libresoc.v:152238$7437 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \trap_op__insn_type + connect \B 7'1001000 + connect \Y $eq$libresoc.v:152238$7437_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:240" + cell $eq $eq$libresoc.v:152239$7438 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \trap_op__msr [34:32] + connect \B 3'010 + connect \Y $eq$libresoc.v:152239$7438_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:241" + cell $eq $eq$libresoc.v:152240$7439 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \ra [34:32] + connect \B 3'000 + connect \Y $eq$libresoc.v:152240$7439_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:295" + cell $eq $eq$libresoc.v:152244$7443 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \trap_op__msr [34:32] + connect \B 3'010 + connect \Y $eq$libresoc.v:152244$7443_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:296" + cell $eq $eq$libresoc.v:152245$7444 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \fast2 [34:32] + connect \B 3'000 + connect \Y $eq$libresoc.v:152245$7444_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" + cell $pos $extend$libresoc.v:152210$7405 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \Y_WIDTH 64 + connect \A \ra [31:0] + connect \Y $extend$libresoc.v:152210$7405_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" + cell $pos $extend$libresoc.v:152211$7407 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \Y_WIDTH 64 + connect \A \rb [31:0] + connect \Y $extend$libresoc.v:152211$7407_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:189" + cell $pos $extend$libresoc.v:152222$7419 + parameter \A_SIGNED 0 + parameter \A_WIDTH 20 + parameter \Y_WIDTH 64 + connect \A \$36 + connect \Y $extend$libresoc.v:152222$7419_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + cell $pos $extend$libresoc.v:152237$7435 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \trap_op__msr + connect \Y $extend$libresoc.v:152237$7435_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:164" + cell $gt $gt$libresoc.v:152213$7410 + parameter \A_SIGNED 1 + parameter \A_WIDTH 64 + parameter \B_SIGNED 1 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 1 + connect \A \a_s + connect \B \b_s + connect \Y $gt$libresoc.v:152213$7410_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:166" + cell $gt $gt$libresoc.v:152215$7412 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 1 + connect \A \a + connect \B \b + connect \Y $gt$libresoc.v:152215$7412_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:163" + cell $lt $lt$libresoc.v:152212$7409 + parameter \A_SIGNED 1 + parameter \A_WIDTH 64 + parameter \B_SIGNED 1 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 1 + connect \A \a_s + connect \B \b_s + connect \Y $lt$libresoc.v:152212$7409_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:165" + cell $lt $lt$libresoc.v:152214$7411 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 1 + connect \A \a + connect \B \b + connect \Y $lt$libresoc.v:152214$7411_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:256" + cell $not $not$libresoc.v:152242$7441 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \trap_op__msr [60] + connect \Y $not$libresoc.v:152242$7441_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:282" + cell $not $not$libresoc.v:152243$7442 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \trap_op__insn [9] + connect \Y $not$libresoc.v:152243$7442_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:177" + cell $or $or$libresoc.v:152220$7417 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$27 + connect \B \$31 + connect \Y $or$libresoc.v:152220$7417_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" + cell $pos $pos$libresoc.v:152210$7406 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:152210$7405_Y + connect \Y $pos$libresoc.v:152210$7406_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" + cell $pos $pos$libresoc.v:152211$7408 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:152211$7407_Y + connect \Y $pos$libresoc.v:152211$7408_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:189" + cell $pos $pos$libresoc.v:152222$7420 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:152222$7419_Y + connect \Y $pos$libresoc.v:152222$7420_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + cell $pos $pos$libresoc.v:152237$7436 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \Y_WIDTH 65 + connect \A $extend$libresoc.v:152237$7435_Y + connect \Y $pos$libresoc.v:152237$7436_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:177" + cell $reduce_or $reduce_or$libresoc.v:152218$7415 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \$28 + connect \Y $reduce_or$libresoc.v:152218$7415_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:177" + cell $reduce_or $reduce_or$libresoc.v:152219$7416 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \trap_op__traptype + connect \Y $reduce_or$libresoc.v:152219$7416_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + cell $reduce_or $reduce_or$libresoc.v:152226$7424 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \$45 + connect \Y $reduce_or$libresoc.v:152226$7424_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + cell $reduce_or $reduce_or$libresoc.v:152228$7426 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \$49 + connect \Y $reduce_or$libresoc.v:152228$7426_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + cell $reduce_or $reduce_or$libresoc.v:152230$7428 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \$53 + connect \Y $reduce_or$libresoc.v:152230$7428_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + cell $reduce_or $reduce_or$libresoc.v:152232$7430 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \$57 + connect \Y $reduce_or$libresoc.v:152232$7430_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + cell $reduce_or $reduce_or$libresoc.v:152234$7432 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \$64 + connect \Y $reduce_or$libresoc.v:152234$7432_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + cell $reduce_or $reduce_or$libresoc.v:152236$7434 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \$72 + connect \Y $reduce_or$libresoc.v:152236$7434_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:189" + cell $sshl $sshl$libresoc.v:152221$7418 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 20 + connect \A \trap_op__trapaddr + connect \B 3'100 + connect \Y $sshl$libresoc.v:152221$7418_Y + end + attribute \src "libresoc.v:151839.7-151839.20" + process $proc$libresoc.v:151839$7506 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:152247.3-152258.6" + process $proc$libresoc.v:152247$7446 + assign { } { } + assign $0\a_s[63:0] $1\a_s[63:0] + attribute \src "libresoc.v:152248.5-152248.29" + switch \initial + attribute \src "libresoc.v:152248.9-152248.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:145" + switch \trap_op__is_32bit + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\a_s[63:0] { \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31:0] } + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\a_s[63:0] \ra + end + sync always + update \a_s $0\a_s[63:0] + end + attribute \src "libresoc.v:152259.3-152290.6" + process $proc$libresoc.v:152259$7447 + assign { } { } + assign { } { } + assign $0\nia[63:0] $1\nia[63:0] + attribute \src "libresoc.v:152260.5-152260.29" + switch \initial + attribute \src "libresoc.v:152260.9-152260.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:180" + switch \trap_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0111111 + assign { } { } + assign $1\nia[63:0] $2\nia[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187" + switch \should_trap + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\nia[63:0] \$35 + case + assign $2\nia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + case 7'1001000 , 7'1001010 + assign $1\nia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'1000111 + assign $1\nia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'1000110 + assign { } { } + assign $1\nia[63:0] { \fast1 [63:2] 2'00 } + attribute \src "libresoc.v:0.0-0.0" + case 7'1001001 + assign { } { } + assign $1\nia[63:0] 64'0000000000000000000000000000000000000000000000000000110000000000 + case + assign $1\nia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \nia $0\nia[63:0] + end + attribute \src "libresoc.v:152291.3-152322.6" + process $proc$libresoc.v:152291$7448 + assign { } { } + assign { } { } + assign $0\nia_ok[0:0] $1\nia_ok[0:0] + attribute \src "libresoc.v:152292.5-152292.29" + switch \initial + attribute \src "libresoc.v:152292.9-152292.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:180" + switch \trap_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0111111 + assign { } { } + assign $1\nia_ok[0:0] $2\nia_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187" + switch \should_trap + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\nia_ok[0:0] 1'1 + case + assign $2\nia_ok[0:0] 1'0 + end + attribute \src "libresoc.v:0.0-0.0" + case 7'1001000 , 7'1001010 + assign $1\nia_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'1000111 + assign $1\nia_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'1000110 + assign { } { } + assign $1\nia_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 7'1001001 + assign { } { } + assign $1\nia_ok[0:0] 1'1 + case + assign $1\nia_ok[0:0] 1'0 + end + sync always + update \nia_ok $0\nia_ok[0:0] + end + attribute \src "libresoc.v:152323.3-152354.6" + process $proc$libresoc.v:152323$7449 + assign { } { } + assign { } { } + assign $0\fast1$11[63:0]$7450 $1\fast1$11[63:0]$7451 + attribute \src "libresoc.v:152324.5-152324.29" + switch \initial + attribute \src "libresoc.v:152324.9-152324.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:180" + switch \trap_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0111111 + assign { } { } + assign $1\fast1$11[63:0]$7451 $2\fast1$11[63:0]$7452 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187" + switch \should_trap + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\fast1$11[63:0]$7452 \trap_op__cia + case + assign $2\fast1$11[63:0]$7452 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + case 7'1001000 , 7'1001010 + assign $1\fast1$11[63:0]$7451 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'1000111 + assign $1\fast1$11[63:0]$7451 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'1000110 + assign $1\fast1$11[63:0]$7451 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'1001001 + assign { } { } + assign $1\fast1$11[63:0]$7451 \$39 [63:0] + case + assign $1\fast1$11[63:0]$7451 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fast1$11 $0\fast1$11[63:0]$7450 + end + attribute \src "libresoc.v:152355.3-152386.6" + process $proc$libresoc.v:152355$7453 + assign { } { } + assign { } { } + assign $0\fast1_ok[0:0] $1\fast1_ok[0:0] + attribute \src "libresoc.v:152356.5-152356.29" + switch \initial + attribute \src "libresoc.v:152356.9-152356.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:180" + switch \trap_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0111111 + assign { } { } + assign $1\fast1_ok[0:0] $2\fast1_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187" + switch \should_trap + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\fast1_ok[0:0] 1'1 + case + assign $2\fast1_ok[0:0] 1'0 + end + attribute \src "libresoc.v:0.0-0.0" + case 7'1001000 , 7'1001010 + assign $1\fast1_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'1000111 + assign $1\fast1_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'1000110 + assign $1\fast1_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'1001001 + assign { } { } + assign $1\fast1_ok[0:0] 1'1 + case + assign $1\fast1_ok[0:0] 1'0 + end + sync always + update \fast1_ok $0\fast1_ok[0:0] + end + attribute \src "libresoc.v:152387.3-152469.6" + process $proc$libresoc.v:152387$7454 + assign { } { } + assign { } { } + assign $0\fast2$12[63:0]$7455 $1\fast2$12[63:0]$7456 + attribute \src "libresoc.v:152388.5-152388.29" + switch \initial + attribute \src "libresoc.v:152388.9-152388.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:180" + switch \trap_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0111111 + assign { } { } + assign $1\fast2$12[63:0]$7456 $2\fast2$12[63:0]$7457 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187" + switch \should_trap + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { $2\fast2$12[63:0]$7457 [29] $2\fast2$12[63:0]$7457 [27] $2\fast2$12[63:0]$7457 [21] } 3'000 + assign $2\fast2$12[63:0]$7457 [15:0] \trap_op__msr [15:0] + assign $2\fast2$12[63:0]$7457 [26:22] \trap_op__msr [26:22] + assign $2\fast2$12[63:0]$7457 [63:31] \trap_op__msr [63:31] + assign $2\fast2$12[63:0]$7457 [17] $3\fast2$12[17:17]$7458 + assign { } { } + assign $2\fast2$12[63:0]$7457 [20] $5\fast2$12[20:20]$7460 + assign $2\fast2$12[63:0]$7457 [16] $6\fast2$12[16:16]$7461 + assign $2\fast2$12[63:0]$7457 [18] $7\fast2$12[19:18]$7462 [0] + assign $2\fast2$12[63:0]$7457 [28] $8\fast2$12[28:28]$7463 + assign $2\fast2$12[63:0]$7457 [30] $9\fast2$12[30:30]$7464 + assign $2\fast2$12[63:0]$7457 [19] $10\fast2$12[19:19]$7465 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:190" + switch \$42 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fast2$12[17:17]$7458 1'1 + case + assign $3\fast2$12[17:17]$7458 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:193" + switch \$44 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\fast2$12[18:18]$7459 1'1 + case + assign $4\fast2$12[18:18]$7459 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:195" + switch \$48 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\fast2$12[20:20]$7460 1'1 + case + assign $5\fast2$12[20:20]$7460 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:197" + switch \$52 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\fast2$12[16:16]$7461 1'1 + case + assign $6\fast2$12[16:16]$7461 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:199" + switch \$56 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign $9\fast2$12[30:30]$7464 \trapexc_$signal + assign $8\fast2$12[28:28]$7463 \trapexc_$signal$60 + assign $7\fast2$12[19:18]$7462 [1] \trapexc_$signal$61 + assign $7\fast2$12[19:18]$7462 [0] \trapexc_$signal$62 + case + assign $7\fast2$12[19:18]$7462 { 1'0 $4\fast2$12[18:18]$7459 } + assign $8\fast2$12[28:28]$7463 1'0 + assign $9\fast2$12[30:30]$7464 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:213" + switch \$63 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $10\fast2$12[19:19]$7465 1'1 + case + assign $10\fast2$12[19:19]$7465 $7\fast2$12[19:18]$7462 [1] + end + case + assign $2\fast2$12[63:0]$7457 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + case 7'1001000 , 7'1001010 + assign $1\fast2$12[63:0]$7456 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'1000111 + assign $1\fast2$12[63:0]$7456 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'1000110 + assign $1\fast2$12[63:0]$7456 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'1001001 + assign { } { } + assign { $1\fast2$12[63:0]$7456 [30:27] $1\fast2$12[63:0]$7456 [21:16] } 10'0000000000 + assign $1\fast2$12[63:0]$7456 [15:0] \trap_op__msr [15:0] + assign $1\fast2$12[63:0]$7456 [26:22] \trap_op__msr [26:22] + assign $1\fast2$12[63:0]$7456 [63:31] \trap_op__msr [63:31] + case + assign $1\fast2$12[63:0]$7456 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fast2$12 $0\fast2$12[63:0]$7455 + end + attribute \src "libresoc.v:152470.3-152501.6" + process $proc$libresoc.v:152470$7466 + assign { } { } + assign { } { } + assign $0\fast2_ok[0:0] $1\fast2_ok[0:0] + attribute \src "libresoc.v:152471.5-152471.29" + switch \initial + attribute \src "libresoc.v:152471.9-152471.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:180" + switch \trap_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0111111 + assign { } { } + assign $1\fast2_ok[0:0] $2\fast2_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187" + switch \should_trap + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\fast2_ok[0:0] 1'1 + case + assign $2\fast2_ok[0:0] 1'0 + end + attribute \src "libresoc.v:0.0-0.0" + case 7'1001000 , 7'1001010 + assign $1\fast2_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'1000111 + assign $1\fast2_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'1000110 + assign $1\fast2_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'1001001 + assign { } { } + assign $1\fast2_ok[0:0] 1'1 + case + assign $1\fast2_ok[0:0] 1'0 + end + sync always + update \fast2_ok $0\fast2_ok[0:0] + end + attribute \src "libresoc.v:152502.3-152529.6" + process $proc$libresoc.v:152502$7467 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\trapexc_$signal[0:0]$7468 $1\trapexc_$signal[0:0]$7476 + assign $0\trapexc_$signal$60[0:0]$7469 $1\trapexc_$signal$60[0:0]$7477 + assign $0\trapexc_$signal$61[0:0]$7470 $1\trapexc_$signal$61[0:0]$7478 + assign $0\trapexc_$signal$62[0:0]$7471 $1\trapexc_$signal$62[0:0]$7479 + assign $0\trapexc_$signal$67[0:0]$7472 $1\trapexc_$signal$67[0:0]$7480 + assign $0\trapexc_$signal$68[0:0]$7473 $1\trapexc_$signal$68[0:0]$7481 + assign $0\trapexc_$signal$69[0:0]$7474 $1\trapexc_$signal$69[0:0]$7482 + assign $0\trapexc_$signal$70[0:0]$7475 $1\trapexc_$signal$70[0:0]$7483 + attribute \src "libresoc.v:152503.5-152503.29" + switch \initial + attribute \src "libresoc.v:152503.9-152503.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:180" + switch \trap_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0111111 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\trapexc_$signal[0:0]$7476 $2\trapexc_$signal[0:0]$7484 + assign $1\trapexc_$signal$60[0:0]$7477 $2\trapexc_$signal$60[0:0]$7485 + assign $1\trapexc_$signal$61[0:0]$7478 $2\trapexc_$signal$61[0:0]$7486 + assign $1\trapexc_$signal$62[0:0]$7479 $2\trapexc_$signal$62[0:0]$7487 + assign $1\trapexc_$signal$67[0:0]$7480 $2\trapexc_$signal$67[0:0]$7488 + assign $1\trapexc_$signal$68[0:0]$7481 $2\trapexc_$signal$68[0:0]$7489 + assign $1\trapexc_$signal$69[0:0]$7482 $2\trapexc_$signal$69[0:0]$7490 + assign $1\trapexc_$signal$70[0:0]$7483 $2\trapexc_$signal$70[0:0]$7491 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187" + switch \should_trap + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $2\trapexc_$signal[0:0]$7484 $3\trapexc_$signal[0:0]$7492 + assign $2\trapexc_$signal$60[0:0]$7485 $3\trapexc_$signal$60[0:0]$7493 + assign $2\trapexc_$signal$61[0:0]$7486 $3\trapexc_$signal$61[0:0]$7494 + assign $2\trapexc_$signal$62[0:0]$7487 $3\trapexc_$signal$62[0:0]$7495 + assign $2\trapexc_$signal$67[0:0]$7488 $3\trapexc_$signal$67[0:0]$7496 + assign $2\trapexc_$signal$68[0:0]$7489 $3\trapexc_$signal$68[0:0]$7497 + assign $2\trapexc_$signal$69[0:0]$7490 $3\trapexc_$signal$69[0:0]$7498 + assign $2\trapexc_$signal$70[0:0]$7491 $3\trapexc_$signal$70[0:0]$7499 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:199" + switch \$71 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $3\trapexc_$signal$70[0:0]$7499 $3\trapexc_$signal$62[0:0]$7495 $3\trapexc_$signal$60[0:0]$7493 $3\trapexc_$signal$61[0:0]$7494 $3\trapexc_$signal[0:0]$7492 $3\trapexc_$signal$69[0:0]$7498 $3\trapexc_$signal$68[0:0]$7497 $3\trapexc_$signal$67[0:0]$7496 } \trap_op__ldst_exc + case + assign $3\trapexc_$signal[0:0]$7492 1'0 + assign $3\trapexc_$signal$60[0:0]$7493 1'0 + assign $3\trapexc_$signal$61[0:0]$7494 1'0 + assign $3\trapexc_$signal$62[0:0]$7495 1'0 + assign $3\trapexc_$signal$67[0:0]$7496 1'0 + assign $3\trapexc_$signal$68[0:0]$7497 1'0 + assign $3\trapexc_$signal$69[0:0]$7498 1'0 + assign $3\trapexc_$signal$70[0:0]$7499 1'0 + end + case + assign $2\trapexc_$signal[0:0]$7484 1'0 + assign $2\trapexc_$signal$60[0:0]$7485 1'0 + assign $2\trapexc_$signal$61[0:0]$7486 1'0 + assign $2\trapexc_$signal$62[0:0]$7487 1'0 + assign $2\trapexc_$signal$67[0:0]$7488 1'0 + assign $2\trapexc_$signal$68[0:0]$7489 1'0 + assign $2\trapexc_$signal$69[0:0]$7490 1'0 + assign $2\trapexc_$signal$70[0:0]$7491 1'0 + end + case + assign $1\trapexc_$signal[0:0]$7476 1'0 + assign $1\trapexc_$signal$60[0:0]$7477 1'0 + assign $1\trapexc_$signal$61[0:0]$7478 1'0 + assign $1\trapexc_$signal$62[0:0]$7479 1'0 + assign $1\trapexc_$signal$67[0:0]$7480 1'0 + assign $1\trapexc_$signal$68[0:0]$7481 1'0 + assign $1\trapexc_$signal$69[0:0]$7482 1'0 + assign $1\trapexc_$signal$70[0:0]$7483 1'0 + end + sync always + update \trapexc_$signal $0\trapexc_$signal[0:0]$7468 + update \trapexc_$signal$60 $0\trapexc_$signal$60[0:0]$7469 + update \trapexc_$signal$61 $0\trapexc_$signal$61[0:0]$7470 + update \trapexc_$signal$62 $0\trapexc_$signal$62[0:0]$7471 + update \trapexc_$signal$67 $0\trapexc_$signal$67[0:0]$7472 + update \trapexc_$signal$68 $0\trapexc_$signal$68[0:0]$7473 + update \trapexc_$signal$69 $0\trapexc_$signal$69[0:0]$7474 + update \trapexc_$signal$70 $0\trapexc_$signal$70[0:0]$7475 + end + attribute \src "libresoc.v:152530.3-152541.6" + process $proc$libresoc.v:152530$7500 + assign { } { } + assign $0\b_s[63:0] $1\b_s[63:0] + attribute \src "libresoc.v:152531.5-152531.29" + switch \initial + attribute \src "libresoc.v:152531.9-152531.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:145" + switch \trap_op__is_32bit + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\b_s[63:0] { \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31:0] } + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\b_s[63:0] \rb + end + sync always + update \b_s $0\b_s[63:0] + end + attribute \src "libresoc.v:152542.3-152710.6" + process $proc$libresoc.v:152542$7501 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\msr[63:0] $1\msr[63:0] + assign $0\msr_ok[0:0] $1\msr_ok[0:0] + attribute \src "libresoc.v:152543.5-152543.29" + switch \initial + attribute \src "libresoc.v:152543.9-152543.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:180" + switch \trap_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0111111 + assign { } { } + assign { } { } + assign $1\msr[63:0] $2\msr[63:0] + assign $1\msr_ok[0:0] $2\msr_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187" + switch \should_trap + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\msr[63:0] [62:59] $2\msr[63:0] [57:33] $2\msr[63:0] [31:26] $2\msr[63:0] [24] $2\msr[63:0] [22:16] $2\msr[63:0] [12] $2\msr[63:0] [7:6] $2\msr[63:0] [2] } { \trap_op__msr [62:59] \trap_op__msr [57:33] \trap_op__msr [31:26] \trap_op__msr [24] \trap_op__msr [22:16] \trap_op__msr [12] \trap_op__msr [7:6] \trap_op__msr [2] } + assign $2\msr[63:0] [63] 1'1 + assign $2\msr[63:0] [15] 1'0 + assign $2\msr[63:0] [14] 1'0 + assign $2\msr[63:0] [5] 1'0 + assign $2\msr[63:0] [4] 1'0 + assign $2\msr[63:0] [1] 1'0 + assign $2\msr[63:0] [0] 1'1 + assign $2\msr[63:0] [11] 1'0 + assign $2\msr[63:0] [8] 1'0 + assign $2\msr[63:0] [23] 1'0 + assign $2\msr[63:0] [32] 1'0 + assign $2\msr[63:0] [25] 1'0 + assign $2\msr[63:0] [13] 1'0 + assign $2\msr[63:0] [3] 1'0 + assign $2\msr[63:0] [10] 1'0 + assign $2\msr[63:0] [9] 1'0 + assign $2\msr[63:0] [58] 1'0 + assign $2\msr_ok[0:0] 1'1 + case + assign $2\msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\msr_ok[0:0] 1'0 + end + attribute \src "libresoc.v:0.0-0.0" + case 7'1001000 , 7'1001010 + assign { } { } + assign { } { } + assign $1\msr[63:0] [0] \$75 [0] + assign $1\msr[63:0] [11:1] $3\msr[11:1] + assign $1\msr[63:0] [59:13] $4\msr[59:13] + assign $1\msr[63:0] [63:61] $5\msr[63:61] + assign $1\msr[63:0] [12] $12\msr[12:12] + assign $1\msr[63:0] [60] $13\msr[60:60] + assign $1\msr_ok[0:0] 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:227" + switch \trap_op__insn [21] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $3\msr[11:1] [10:1] \$75 [11:2] + assign { $4\msr[59:13] [46:3] $4\msr[59:13] [1:0] } { \$75 [59:16] \$75 [14:13] } + assign $5\msr[63:61] \$75 [63:61] + assign $3\msr[11:1] [0] \ra [1] + assign $4\msr[59:13] [2] \ra [15] + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign { } { } + assign { $3\msr[11:1] [10:5] $3\msr[11:1] [2:0] } { $6\msr[11:1] [10:5] $6\msr[11:1] [2:0] } + assign { $4\msr[59:13] [46:3] $4\msr[59:13] [1:0] } { $7\msr[59:13] [46:3] $7\msr[59:13] [1:0] } + assign $5\msr[63:61] $8\msr[63:61] + assign $3\msr[11:1] [4:3] $10\msr[5:4] + assign $4\msr[59:13] [2] $11\msr[15:15] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:234" + switch \$77 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign $6\msr[11:1] \ra [11:1] + assign { $7\msr[59:13] [46:22] $7\msr[59:13] [18:0] } { \ra [59:35] \ra [31:13] } + assign $8\msr[63:61] \ra [63:61] + assign $7\msr[59:13] [21:19] $9\msr[34:32] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:241" + switch \$83 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $9\msr[34:32] \trap_op__msr [34:32] + case + assign $9\msr[34:32] \ra [34:32] + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $7\msr[59:13] [46:19] \$75 [59:32] + assign $8\msr[63:61] \$75 [63:61] + assign $6\msr[11:1] \ra [11:1] + assign $7\msr[59:13] [18:0] \ra [31:13] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:49" + switch $7\msr[59:13] [1] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $11\msr[15:15] 1'1 + assign $10\msr[5:4] [1] 1'1 + assign $10\msr[5:4] [0] 1'1 + case + assign $10\msr[5:4] $6\msr[11:1] [4:3] + assign $11\msr[15:15] $7\msr[59:13] [2] + end + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:256" + switch \$85 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $13\msr[60:60] \trap_op__msr [60] + assign $12\msr[12:12] \trap_op__msr [12] + case + assign $12\msr[12:12] \$75 [12] + assign $13\msr[60:60] \$75 [60] + end + attribute \src "libresoc.v:0.0-0.0" + case 7'1000111 + assign $1\msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\msr_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'1000110 + assign { $1\msr[63:0] [30:27] $1\msr[63:0] [21:16] } 10'0000000000 + assign { } { } + assign { $1\msr[63:0] [14:13] $1\msr[63:0] [11:6] $1\msr[63:0] [3:0] } { \fast2 [14:13] \fast2 [11:6] \fast2 [3:0] } + assign $1\msr[63:0] [26:22] \fast2 [26:22] + assign { $1\msr[63:0] [63:35] $1\msr[63:0] [31] } { \fast2 [63:35] \fast2 [31] } + assign $1\msr[63:0] [12] $14\msr[12:12] + assign $1\msr[63:0] [5:4] $16\msr[5:4] + assign $1\msr[63:0] [15] $17\msr[15:15] + assign $1\msr[63:0] [34:32] $18\msr[34:32] + assign $1\msr_ok[0:0] 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:282" + switch \$87 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $14\msr[12:12] $15\msr[12:12] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:283" + switch \trap_op__msr [60] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $15\msr[12:12] \fast2 [12] + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $15\msr[12:12] \trap_op__msr [12] + end + case + assign $14\msr[12:12] \fast2 [12] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:49" + switch \fast2 [14] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $17\msr[15:15] 1'1 + assign $16\msr[5:4] [1] 1'1 + assign $16\msr[5:4] [0] 1'1 + case + assign $16\msr[5:4] \fast2 [5:4] + assign $17\msr[15:15] \fast2 [15] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:296" + switch \$93 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $18\msr[34:32] \trap_op__msr [34:32] + case + assign $18\msr[34:32] \fast2 [34:32] + end + attribute \src "libresoc.v:0.0-0.0" + case 7'1001001 + assign { } { } + assign { } { } + assign { $1\msr[63:0] [62:59] $1\msr[63:0] [57:33] $1\msr[63:0] [31:26] $1\msr[63:0] [24] $1\msr[63:0] [22:16] $1\msr[63:0] [12] $1\msr[63:0] [7:6] $1\msr[63:0] [2] } { \trap_op__msr [62:59] \trap_op__msr [57:33] \trap_op__msr [31:26] \trap_op__msr [24] \trap_op__msr [22:16] \trap_op__msr [12] \trap_op__msr [7:6] \trap_op__msr [2] } + assign $1\msr[63:0] [63] 1'1 + assign $1\msr[63:0] [15] 1'0 + assign $1\msr[63:0] [14] 1'0 + assign $1\msr[63:0] [5] 1'0 + assign $1\msr[63:0] [4] 1'0 + assign $1\msr[63:0] [1] 1'0 + assign $1\msr[63:0] [0] 1'1 + assign $1\msr[63:0] [11] 1'0 + assign $1\msr[63:0] [8] 1'0 + assign $1\msr[63:0] [23] 1'0 + assign $1\msr[63:0] [32] 1'0 + assign $1\msr[63:0] [25] 1'0 + assign $1\msr[63:0] [13] 1'0 + assign $1\msr[63:0] [3] 1'0 + assign $1\msr[63:0] [10] 1'0 + assign $1\msr[63:0] [9] 1'0 + assign $1\msr[63:0] [58] 1'0 + assign $1\msr_ok[0:0] 1'1 + case + assign $1\msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\msr_ok[0:0] 1'0 + end + sync always + update \msr $0\msr[63:0] + update \msr_ok $0\msr_ok[0:0] + end + attribute \src "libresoc.v:152711.3-152729.6" + process $proc$libresoc.v:152711$7502 + assign { } { } + assign { } { } + assign $0\o[63:0] $1\o[63:0] + attribute \src "libresoc.v:152712.5-152712.29" + switch \initial + attribute \src "libresoc.v:152712.9-152712.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:180" + switch \trap_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0111111 + assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'1001000 , 7'1001010 + assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'1000111 + assign { } { } + assign $1\o[63:0] \trap_op__msr + case + assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \o $0\o[63:0] + end + attribute \src "libresoc.v:152730.3-152748.6" + process $proc$libresoc.v:152730$7503 + assign { } { } + assign { } { } + assign $0\o_ok[0:0] $1\o_ok[0:0] + attribute \src "libresoc.v:152731.5-152731.29" + switch \initial + attribute \src "libresoc.v:152731.9-152731.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:180" + switch \trap_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0111111 + assign $1\o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'1001000 , 7'1001010 + assign $1\o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'1000111 + assign { } { } + assign $1\o_ok[0:0] 1'1 + case + assign $1\o_ok[0:0] 1'0 + end + sync always + update \o_ok $0\o_ok[0:0] + end + attribute \src "libresoc.v:152749.3-152760.6" + process $proc$libresoc.v:152749$7504 + assign { } { } + assign $0\a[63:0] $1\a[63:0] + attribute \src "libresoc.v:152750.5-152750.29" + switch \initial + attribute \src "libresoc.v:152750.9-152750.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:145" + switch \trap_op__is_32bit + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\a[63:0] \$13 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\a[63:0] \ra + end + sync always + update \a $0\a[63:0] + end + attribute \src "libresoc.v:152761.3-152772.6" + process $proc$libresoc.v:152761$7505 + assign { } { } + assign $0\b[63:0] $1\b[63:0] + attribute \src "libresoc.v:152762.5-152762.29" + switch \initial + attribute \src "libresoc.v:152762.9-152762.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:145" + switch \trap_op__is_32bit + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\b[63:0] \$15 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\b[63:0] \rb + end + sync always + update \b $0\b[63:0] + end + connect \$13 $pos$libresoc.v:152210$7406_Y + connect \$15 $pos$libresoc.v:152211$7408_Y + connect \$17 $lt$libresoc.v:152212$7409_Y + connect \$19 $gt$libresoc.v:152213$7410_Y + connect \$21 $lt$libresoc.v:152214$7411_Y + connect \$23 $gt$libresoc.v:152215$7412_Y + connect \$25 $eq$libresoc.v:152216$7413_Y + connect \$28 $and$libresoc.v:152217$7414_Y + connect \$27 $reduce_or$libresoc.v:152218$7415_Y + connect \$31 $reduce_or$libresoc.v:152219$7416_Y + connect \$33 $or$libresoc.v:152220$7417_Y + connect \$36 $sshl$libresoc.v:152221$7418_Y + connect \$35 $pos$libresoc.v:152222$7420_Y + connect \$40 $add$libresoc.v:152223$7421_Y + connect \$42 $eq$libresoc.v:152224$7422_Y + connect \$45 $and$libresoc.v:152225$7423_Y + connect \$44 $reduce_or$libresoc.v:152226$7424_Y + connect \$49 $and$libresoc.v:152227$7425_Y + connect \$48 $reduce_or$libresoc.v:152228$7426_Y + connect \$53 $and$libresoc.v:152229$7427_Y + connect \$52 $reduce_or$libresoc.v:152230$7428_Y + connect \$57 $and$libresoc.v:152231$7429_Y + connect \$56 $reduce_or$libresoc.v:152232$7430_Y + connect \$64 $and$libresoc.v:152233$7431_Y + connect \$63 $reduce_or$libresoc.v:152234$7432_Y + connect \$72 $and$libresoc.v:152235$7433_Y + connect \$71 $reduce_or$libresoc.v:152236$7434_Y + connect \$75 $pos$libresoc.v:152237$7436_Y + connect \$77 $eq$libresoc.v:152238$7437_Y + connect \$79 $eq$libresoc.v:152239$7438_Y + connect \$81 $eq$libresoc.v:152240$7439_Y + connect \$83 $and$libresoc.v:152241$7440_Y + connect \$85 $not$libresoc.v:152242$7441_Y + connect \$87 $not$libresoc.v:152243$7442_Y + connect \$89 $eq$libresoc.v:152244$7443_Y + connect \$91 $eq$libresoc.v:152245$7444_Y + connect \$93 $and$libresoc.v:152246$7445_Y + connect \$39 \$40 + connect { \trap_op__ldst_exc$10 \trap_op__trapaddr$9 \trap_op__traptype$8 \trap_op__is_32bit$7 \trap_op__cia$6 \trap_op__msr$5 \trap_op__insn$4 \trap_op__fn_unit$3 \trap_op__insn_type$2 } { \trap_op__ldst_exc \trap_op__trapaddr \trap_op__traptype \trap_op__is_32bit \trap_op__cia \trap_op__msr \trap_op__insn \trap_op__fn_unit \trap_op__insn_type } + connect \muxid$1 \muxid + connect \should_trap \$33 + connect \trap_bits { \lt_s \gt_s \equal \lt_u \gt_u } + connect \equal \$25 + connect \gt_u \$23 + connect \lt_u \$21 + connect \gt_s \$19 + connect \lt_s \$17 + connect \to \trap_op__insn [25:21] +end +attribute \src "libresoc.v:152788.1-153533.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe1.main" +attribute \generator "nMigen" +module \main$51 + attribute \src "libresoc.v:153500.3-153510.6" + wire width 32 $0\a32[31:0] + attribute \src "libresoc.v:153445.3-153455.6" + wire width 64 $0\b[63:0] + attribute \src "libresoc.v:153423.3-153433.6" + wire width 64 $0\bpermd_rb[63:0] + attribute \src "libresoc.v:153412.3-153422.6" + wire width 64 $0\bpermd_rs[63:0] + attribute \src "libresoc.v:153401.3-153411.6" + wire width 64 $0\clz_sig_in[63:0] + attribute \src "libresoc.v:153511.3-153529.6" + wire width 64 $0\cntz_i[63:0] + attribute \src "libresoc.v:153489.3-153499.6" + wire $0\count_right[0:0] + attribute \src "libresoc.v:152789.7-152789.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:153346.3-153400.6" + wire width 64 $0\o[63:0] + attribute \src "libresoc.v:153346.3-153400.6" + wire $0\o_ok[0:0] + attribute \src "libresoc.v:153467.3-153477.6" + wire $0\par0[0:0] + attribute \src "libresoc.v:153478.3-153488.6" + wire $0\par1[0:0] + attribute \src "libresoc.v:153434.3-153444.6" + wire width 64 $0\popcount_a[63:0] + attribute \src "libresoc.v:153456.3-153466.6" + wire width 64 $0\popcount_data_len[63:0] + attribute \src "libresoc.v:153500.3-153510.6" + wire width 32 $1\a32[31:0] + attribute \src "libresoc.v:153445.3-153455.6" + wire width 64 $1\b[63:0] + attribute \src "libresoc.v:153423.3-153433.6" + wire width 64 $1\bpermd_rb[63:0] + attribute \src "libresoc.v:153412.3-153422.6" + wire width 64 $1\bpermd_rs[63:0] + attribute \src "libresoc.v:153401.3-153411.6" + wire width 64 $1\clz_sig_in[63:0] + attribute \src "libresoc.v:153511.3-153529.6" + wire width 64 $1\cntz_i[63:0] + attribute \src "libresoc.v:153489.3-153499.6" + wire $1\count_right[0:0] + attribute \src "libresoc.v:153346.3-153400.6" + wire width 64 $1\o[63:0] + attribute \src "libresoc.v:153346.3-153400.6" + wire $1\o_ok[0:0] + attribute \src "libresoc.v:153467.3-153477.6" + wire $1\par0[0:0] + attribute \src "libresoc.v:153478.3-153488.6" + wire $1\par1[0:0] + attribute \src "libresoc.v:153434.3-153444.6" + wire width 64 $1\popcount_a[63:0] + attribute \src "libresoc.v:153456.3-153466.6" + wire width 64 $1\popcount_data_len[63:0] + attribute \src "libresoc.v:153511.3-153529.6" + wire width 64 $2\cntz_i[63:0] + attribute \src "libresoc.v:153346.3-153400.6" + wire width 64 $2\o[63:0] + attribute \src "libresoc.v:153293.18-153293.103" + wire width 64 $and$libresoc.v:153293$7553_Y + attribute \src "libresoc.v:153252.18-153252.118" + wire $eq$libresoc.v:153252$7507_Y + attribute \src "libresoc.v:153253.19-153253.119" + wire $eq$libresoc.v:153253$7508_Y + attribute \src "libresoc.v:153254.19-153254.119" + wire $eq$libresoc.v:153254$7509_Y + attribute \src "libresoc.v:153255.19-153255.119" + wire $eq$libresoc.v:153255$7510_Y + attribute \src "libresoc.v:153256.19-153256.119" + wire $eq$libresoc.v:153256$7511_Y + attribute \src "libresoc.v:153257.19-153257.119" + wire $eq$libresoc.v:153257$7512_Y + attribute \src "libresoc.v:153258.19-153258.119" + wire $eq$libresoc.v:153258$7513_Y + attribute \src "libresoc.v:153259.19-153259.119" + wire $eq$libresoc.v:153259$7514_Y + attribute \src "libresoc.v:153260.19-153260.119" + wire $eq$libresoc.v:153260$7515_Y + attribute \src "libresoc.v:153261.19-153261.119" + wire $eq$libresoc.v:153261$7516_Y + attribute \src "libresoc.v:153262.19-153262.119" + wire $eq$libresoc.v:153262$7517_Y + attribute \src "libresoc.v:153263.19-153263.119" + wire $eq$libresoc.v:153263$7518_Y + attribute \src "libresoc.v:153264.19-153264.119" + wire $eq$libresoc.v:153264$7519_Y + attribute \src "libresoc.v:153265.19-153265.119" + wire $eq$libresoc.v:153265$7520_Y + attribute \src "libresoc.v:153266.19-153266.119" + wire $eq$libresoc.v:153266$7521_Y + attribute \src "libresoc.v:153267.19-153267.119" + wire $eq$libresoc.v:153267$7522_Y + attribute \src "libresoc.v:153268.19-153268.119" + wire $eq$libresoc.v:153268$7523_Y + attribute \src "libresoc.v:153269.19-153269.119" + wire $eq$libresoc.v:153269$7524_Y + attribute \src "libresoc.v:153270.19-153270.119" + wire $eq$libresoc.v:153270$7525_Y + attribute \src "libresoc.v:153271.19-153271.119" + wire $eq$libresoc.v:153271$7526_Y + attribute \src "libresoc.v:153272.19-153272.119" + wire $eq$libresoc.v:153272$7527_Y + attribute \src "libresoc.v:153273.19-153273.119" + wire $eq$libresoc.v:153273$7528_Y + attribute \src "libresoc.v:153274.19-153274.119" + wire $eq$libresoc.v:153274$7529_Y + attribute \src "libresoc.v:153275.19-153275.119" + wire $eq$libresoc.v:153275$7530_Y + attribute \src "libresoc.v:153276.19-153276.119" + wire $eq$libresoc.v:153276$7531_Y + attribute \src "libresoc.v:153277.19-153277.119" + wire $eq$libresoc.v:153277$7532_Y + attribute \src "libresoc.v:153278.19-153278.119" + wire $eq$libresoc.v:153278$7533_Y + attribute \src "libresoc.v:153279.19-153279.119" + wire $eq$libresoc.v:153279$7534_Y + attribute \src "libresoc.v:153280.19-153280.128" + wire $eq$libresoc.v:153280$7535_Y + attribute \src "libresoc.v:153296.18-153296.114" + wire $eq$libresoc.v:153296$7556_Y + attribute \src "libresoc.v:153297.18-153297.114" + wire $eq$libresoc.v:153297$7557_Y + attribute \src "libresoc.v:153298.18-153298.114" + wire $eq$libresoc.v:153298$7558_Y + attribute \src "libresoc.v:153299.18-153299.114" + wire $eq$libresoc.v:153299$7559_Y + attribute \src "libresoc.v:153300.18-153300.114" + wire $eq$libresoc.v:153300$7560_Y + attribute \src "libresoc.v:153301.18-153301.114" + wire $eq$libresoc.v:153301$7561_Y + attribute \src "libresoc.v:153302.18-153302.114" + wire $eq$libresoc.v:153302$7562_Y + attribute \src "libresoc.v:153303.18-153303.114" + wire $eq$libresoc.v:153303$7563_Y + attribute \src "libresoc.v:153304.18-153304.116" + wire $eq$libresoc.v:153304$7564_Y + attribute \src "libresoc.v:153305.18-153305.116" + wire $eq$libresoc.v:153305$7565_Y + attribute \src "libresoc.v:153306.18-153306.116" + wire $eq$libresoc.v:153306$7566_Y + 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+ attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 23 \logical_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 31 \logical_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 34 \logical_op__invert_out$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 15 \logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 37 \logical_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 16 \logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 38 \logical_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 7 \logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 29 \logical_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 30 \logical_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 36 \logical_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 6 \logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 28 \logical_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 5 \logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 27 \logical_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 35 \logical_op__write_cr0$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 32 \logical_op__zero_a$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 input 44 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 output 22 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 41 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 42 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:84" + wire \par0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:85" + wire \par1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:27" + wire width 64 \popcount_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:29" + wire width 64 \popcount_data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:30" + wire width 64 \popcount_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 19 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 20 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 21 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 43 \xer_so$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:54" + cell $and $and$libresoc.v:153293$7553 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \ra + connect \B \rb + connect \Y $and$libresoc.v:153293$7553_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:153252$7507 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [39:32] + connect \B \rb [39:32] + connect \Y $eq$libresoc.v:153252$7507_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:153253$7508 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [39:32] + connect \B \rb [39:32] + connect \Y $eq$libresoc.v:153253$7508_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:153254$7509 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [39:32] + connect \B \rb [39:32] + connect \Y $eq$libresoc.v:153254$7509_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:153255$7510 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [39:32] + connect \B \rb [39:32] + connect \Y $eq$libresoc.v:153255$7510_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:153256$7511 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [47:40] + connect \B \rb [47:40] + connect \Y $eq$libresoc.v:153256$7511_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:153257$7512 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [47:40] + connect \B \rb [47:40] + connect \Y $eq$libresoc.v:153257$7512_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:153258$7513 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [47:40] + connect \B \rb [47:40] + connect \Y $eq$libresoc.v:153258$7513_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:153259$7514 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [47:40] + connect \B \rb [47:40] + connect \Y $eq$libresoc.v:153259$7514_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:153260$7515 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [47:40] + connect \B \rb [47:40] + connect \Y $eq$libresoc.v:153260$7515_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:153261$7516 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [47:40] + connect \B \rb [47:40] + connect \Y $eq$libresoc.v:153261$7516_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:153262$7517 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [47:40] + connect \B \rb [47:40] + connect \Y $eq$libresoc.v:153262$7517_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:153263$7518 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [47:40] + connect \B \rb [47:40] + connect \Y $eq$libresoc.v:153263$7518_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:153264$7519 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [55:48] + connect \B \rb [55:48] + connect \Y $eq$libresoc.v:153264$7519_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:153265$7520 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [55:48] + connect \B \rb [55:48] + connect \Y $eq$libresoc.v:153265$7520_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:153266$7521 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [55:48] + connect \B \rb [55:48] + connect \Y $eq$libresoc.v:153266$7521_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:153267$7522 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [55:48] + connect \B \rb [55:48] + connect \Y $eq$libresoc.v:153267$7522_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:153268$7523 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [55:48] + connect \B \rb [55:48] + connect \Y $eq$libresoc.v:153268$7523_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:153269$7524 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [55:48] + connect \B \rb [55:48] + connect \Y $eq$libresoc.v:153269$7524_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:153270$7525 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [55:48] + connect \B \rb [55:48] + connect \Y $eq$libresoc.v:153270$7525_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:153271$7526 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [55:48] + connect \B \rb [55:48] + connect \Y $eq$libresoc.v:153271$7526_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:153272$7527 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [63:56] + connect \B \rb [63:56] + connect \Y $eq$libresoc.v:153272$7527_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:153273$7528 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [63:56] + connect \B \rb [63:56] + connect \Y $eq$libresoc.v:153273$7528_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:153274$7529 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [63:56] + connect \B \rb [63:56] + connect \Y $eq$libresoc.v:153274$7529_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:153275$7530 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [63:56] + connect \B \rb [63:56] + connect \Y $eq$libresoc.v:153275$7530_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:153276$7531 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [63:56] + connect \B \rb [63:56] + connect \Y $eq$libresoc.v:153276$7531_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:153277$7532 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [63:56] + connect \B \rb [63:56] + connect \Y $eq$libresoc.v:153277$7532_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:153278$7533 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [63:56] + connect \B \rb [63:56] + connect \Y $eq$libresoc.v:153278$7533_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:153279$7534 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [63:56] + connect \B \rb [63:56] + connect \Y $eq$libresoc.v:153279$7534_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:88" + cell $eq $eq$libresoc.v:153280$7535 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \logical_op__data_len [3] + connect \B 1'1 + connect \Y $eq$libresoc.v:153280$7535_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:153296$7556 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [7:0] + connect \B \rb [7:0] + connect \Y $eq$libresoc.v:153296$7556_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:153297$7557 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [7:0] + connect \B \rb [7:0] + connect \Y $eq$libresoc.v:153297$7557_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:153298$7558 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [7:0] + connect \B \rb [7:0] + connect \Y $eq$libresoc.v:153298$7558_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:153299$7559 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [7:0] + connect \B \rb [7:0] + connect \Y $eq$libresoc.v:153299$7559_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:153300$7560 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [7:0] + connect \B \rb [7:0] + connect \Y $eq$libresoc.v:153300$7560_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:153301$7561 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [7:0] + connect \B \rb [7:0] + connect \Y $eq$libresoc.v:153301$7561_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:153302$7562 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [7:0] + connect \B \rb [7:0] + connect \Y $eq$libresoc.v:153302$7562_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:153303$7563 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [7:0] + connect \B \rb [7:0] + connect \Y $eq$libresoc.v:153303$7563_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:153304$7564 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [15:8] + connect \B \rb [15:8] + connect \Y $eq$libresoc.v:153304$7564_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:153305$7565 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [15:8] + connect \B \rb [15:8] + connect \Y $eq$libresoc.v:153305$7565_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:153306$7566 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [15:8] + connect \B \rb [15:8] + connect \Y $eq$libresoc.v:153306$7566_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:153307$7567 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$eq$libresoc.v:153310$7570 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [15:8] + connect \B \rb [15:8] + connect \Y $eq$libresoc.v:153310$7570_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:153311$7571 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [15:8] + connect \B \rb [15:8] + connect \Y $eq$libresoc.v:153311$7571_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:153312$7572 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [23:16] + connect \B \rb [23:16] + connect \Y $eq$libresoc.v:153312$7572_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:153313$7573 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [23:16] + connect \B \rb [23:16] + connect \Y $eq$libresoc.v:153313$7573_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:153314$7574 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [23:16] + connect \B \rb [23:16] + connect \Y $eq$libresoc.v:153314$7574_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:153315$7575 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [23:16] + connect \B \rb [23:16] + connect \Y $eq$libresoc.v:153315$7575_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" 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"/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:153319$7579 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [23:16] + connect \B \rb [23:16] + connect \Y $eq$libresoc.v:153319$7579_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:153320$7580 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [31:24] + connect \B \rb [31:24] + connect \Y $eq$libresoc.v:153320$7580_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:153321$7581 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [31:24] + connect \B \rb [31:24] + connect \Y $eq$libresoc.v:153321$7581_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:153322$7582 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [31:24] + connect \B \rb [31:24] + connect \Y $eq$libresoc.v:153322$7582_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:153323$7583 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [31:24] + connect \B \rb [31:24] + connect \Y $eq$libresoc.v:153323$7583_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:153324$7584 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [31:24] + connect \B \rb [31:24] + connect \Y $eq$libresoc.v:153324$7584_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:153325$7585 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [31:24] + connect \B \rb [31:24] + connect \Y $eq$libresoc.v:153325$7585_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:153326$7586 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [31:24] + connect \B \rb [31:24] + connect \Y $eq$libresoc.v:153326$7586_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:153327$7587 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [31:24] + connect \B \rb [31:24] + connect \Y $eq$libresoc.v:153327$7587_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:153328$7588 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [39:32] + connect \B \rb [39:32] + connect \Y $eq$libresoc.v:153328$7588_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:153329$7589 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [39:32] + connect \B \rb [39:32] + connect \Y $eq$libresoc.v:153329$7589_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:153330$7590 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [39:32] + connect \B \rb [39:32] + connect \Y $eq$libresoc.v:153330$7590_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$libresoc.v:153331$7591 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [39:32] + connect \B \rb [39:32] + connect \Y $eq$libresoc.v:153331$7591_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:89" + cell $pos $extend$libresoc.v:153282$7537 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 64 + connect \A \$158 + connect \Y $extend$libresoc.v:153282$7537_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:18" + cell $pos $extend$libresoc.v:153284$7540 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 8 + connect \A \clz_lz + connect \Y $extend$libresoc.v:153284$7540_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:113" + cell $pos $extend$libresoc.v:153286$7543 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 64 + connect \A \$166 + connect \Y $extend$libresoc.v:153286$7543_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + cell $pos $extend$libresoc.v:153287$7545 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 64 + connect \A \logical_op__data_len + connect \Y $extend$libresoc.v:153287$7545_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:107" + cell $pos $extend$libresoc.v:153291$7550 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \Y_WIDTH 64 + connect \A \$176 + connect \Y $extend$libresoc.v:153291$7550_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:56" + cell $or $or$libresoc.v:153294$7554 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \ra + connect \B \rb + connect \Y $or$libresoc.v:153294$7554_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:89" + cell $pos $pos$libresoc.v:153282$7538 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:153282$7537_Y + connect \Y $pos$libresoc.v:153282$7538_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:18" + cell $pos $pos$libresoc.v:153284$7541 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $extend$libresoc.v:153284$7540_Y + connect \Y $pos$libresoc.v:153284$7541_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:113" + cell $pos $pos$libresoc.v:153286$7544 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:153286$7543_Y + connect \Y $pos$libresoc.v:153286$7544_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + cell $pos $pos$libresoc.v:153287$7546 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:153287$7545_Y + connect \Y $pos$libresoc.v:153287$7546_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:107" + cell $pos $pos$libresoc.v:153291$7551 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:153291$7550_Y + connect \Y $pos$libresoc.v:153291$7551_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:86" + cell $reduce_xor $reduce_xor$libresoc.v:153288$7547 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \ra [24] \ra [16] \ra [8] \ra [0] } + connect \Y $reduce_xor$libresoc.v:153288$7547_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:87" + cell $reduce_xor $reduce_xor$libresoc.v:153289$7548 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \ra [56] \ra [48] \ra [40] \ra [32] } + connect \Y $reduce_xor$libresoc.v:153289$7548_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:113" + cell $sub $sub$libresoc.v:153283$7539 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 8 + connect \A \clz_lz + connect \B 6'100000 + connect \Y $sub$libresoc.v:153283$7539_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:113" + cell $mux $ternary$libresoc.v:153285$7542 + parameter \WIDTH 8 + connect \A \$164 + connect \B \$162 + connect \S \logical_op__is_32bit + connect \Y $ternary$libresoc.v:153285$7542_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:107" + cell $mux $ternary$libresoc.v:153290$7549 + parameter \WIDTH 32 + connect \A \a32 + connect \B { \a32 [0] \a32 [1] \a32 [2] \a32 [3] \a32 [4] \a32 [5] \a32 [6] \a32 [7] \a32 [8] \a32 [9] \a32 [10] \a32 [11] \a32 [12] \a32 [13] \a32 [14] \a32 [15] \a32 [16] \a32 [17] \a32 [18] \a32 [19] \a32 [20] \a32 [21] \a32 [22] \a32 [23] \a32 [24] \a32 [25] \a32 [26] \a32 [27] \a32 [28] \a32 [29] \a32 [30] \a32 [31] } + connect \S \count_right + connect \Y $ternary$libresoc.v:153290$7549_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:109" + cell $mux $ternary$libresoc.v:153292$7552 + parameter \WIDTH 64 + connect \A \ra + connect \B { \ra [0] \ra [1] \ra [2] \ra [3] \ra [4] \ra [5] \ra [6] \ra [7] \ra [8] \ra [9] \ra [10] \ra [11] \ra [12] \ra [13] \ra [14] \ra [15] \ra [16] \ra [17] \ra [18] \ra [19] \ra [20] \ra [21] \ra [22] \ra [23] \ra [24] \ra [25] \ra [26] \ra [27] \ra [28] \ra [29] \ra [30] \ra [31] \ra [32] \ra [33] \ra [34] \ra [35] \ra [36] \ra [37] \ra [38] \ra [39] \ra [40] \ra [41] \ra [42] \ra [43] \ra [44] \ra [45] \ra [46] \ra [47] \ra [48] \ra [49] \ra [50] \ra [51] \ra [52] \ra [53] \ra [54] \ra [55] \ra [56] \ra [57] \ra [58] \ra [59] \ra [60] \ra [61] \ra [62] \ra [63] } + connect \S \count_right + connect \Y $ternary$libresoc.v:153292$7552_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:89" + cell $xor $xor$libresoc.v:153281$7536 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \par0 + connect \B \par1 + connect \Y $xor$libresoc.v:153281$7536_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:58" + cell $xor $xor$libresoc.v:153295$7555 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \ra + connect \B \rb + connect \Y $xor$libresoc.v:153295$7555_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:153332.10-153336.4" + cell \bpermd \bpermd + connect \ra \bpermd_ra + connect \rb \bpermd_rb + connect \rs \bpermd_rs + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:153337.7-153340.4" + cell \clz \clz + connect \lz \clz_lz + connect \sig_in \clz_sig_in + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:153341.12-153345.4" + cell \popcount \popcount + connect \a \popcount_a + connect \data_len \popcount_data_len + connect \o \popcount_o + end + attribute \src "libresoc.v:152789.7-152789.20" + process $proc$libresoc.v:152789$7604 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:153346.3-153400.6" + process $proc$libresoc.v:153346$7592 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\o_ok[0:0] $1\o_ok[0:0] + assign $0\o[63:0] $1\o[63:0] + attribute \src "libresoc.v:153347.5-153347.29" + switch \initial + attribute \src "libresoc.v:153347.9-153347.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" + switch \logical_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0000100 + assign $1\o_ok[0:0] 1'1 + assign { } { } + assign $1\o[63:0] \$21 + attribute \src "libresoc.v:0.0-0.0" + case 7'0110101 + assign $1\o_ok[0:0] 1'1 + assign { } { } + assign $1\o[63:0] \$23 + attribute \src "libresoc.v:0.0-0.0" + case 7'1000011 + assign $1\o_ok[0:0] 1'1 + assign { } { } + assign $1\o[63:0] \$25 + attribute \src "libresoc.v:0.0-0.0" + case 7'0001011 + assign $1\o_ok[0:0] 1'1 + assign { } { } + assign $1\o[63:0] { \$139 \$141 \$143 \$145 \$147 \$149 \$151 \$153 \$123 \$125 \$127 \$129 \$131 \$133 \$135 \$137 \$107 \$109 \$111 \$113 \$115 \$117 \$119 \$121 \$91 \$93 \$95 \$97 \$99 \$101 \$103 \$105 \$75 \$77 \$79 \$81 \$83 \$85 \$87 \$89 \$59 \$61 \$63 \$65 \$67 \$69 \$71 \$73 \$43 \$45 \$47 \$49 \$51 \$53 \$55 \$57 \$27 \$29 \$31 \$33 \$35 \$37 \$39 \$41 } + attribute \src "libresoc.v:0.0-0.0" + case 7'0110110 + assign $1\o_ok[0:0] 1'1 + assign { } { } + assign $1\o[63:0] \popcount_o + attribute \src "libresoc.v:0.0-0.0" + case 7'0110111 + assign $1\o_ok[0:0] 1'1 + assign { } { } + assign $1\o[63:0] $2\o[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:88" + switch \$155 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\o[63:0] \$157 + attribute \src "libresoc.v:0.0-0.0" + case + assign { $2\o[63:0] [63:33] $2\o[63:0] [31:1] } 62'00000000000000000000000000000000000000000000000000000000000000 + assign $2\o[63:0] [0] \par0 + assign $2\o[63:0] [32] \par1 + end + attribute \src "libresoc.v:0.0-0.0" + case 7'0001110 + assign $1\o_ok[0:0] 1'1 + assign { } { } + assign $1\o[63:0] \$161 + attribute \src "libresoc.v:0.0-0.0" + case 7'0001001 + assign $1\o_ok[0:0] 1'1 + assign { } { } + assign $1\o[63:0] \bpermd_ra + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\o_ok[0:0] 1'0 + end + sync always + update \o_ok $0\o_ok[0:0] + update \o $0\o[63:0] + end + attribute \src "libresoc.v:153401.3-153411.6" + process $proc$libresoc.v:153401$7593 + assign { } { } + assign { } { } + assign $0\clz_sig_in[63:0] $1\clz_sig_in[63:0] + attribute \src "libresoc.v:153402.5-153402.29" + switch \initial + attribute \src "libresoc.v:153402.9-153402.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" + switch \logical_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0001110 + assign { } { } + assign $1\clz_sig_in[63:0] \cntz_i + case + assign $1\clz_sig_in[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \clz_sig_in $0\clz_sig_in[63:0] + end + attribute \src "libresoc.v:153412.3-153422.6" + process $proc$libresoc.v:153412$7594 + assign { } { } + assign { } { } + assign $0\bpermd_rs[63:0] $1\bpermd_rs[63:0] + attribute \src "libresoc.v:153413.5-153413.29" + switch \initial + attribute \src "libresoc.v:153413.9-153413.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" + switch \logical_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0001001 + assign { } { } + assign $1\bpermd_rs[63:0] \ra + case + assign $1\bpermd_rs[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \bpermd_rs $0\bpermd_rs[63:0] + end + attribute \src "libresoc.v:153423.3-153433.6" + process $proc$libresoc.v:153423$7595 + assign { } { } + assign { } { } + assign $0\bpermd_rb[63:0] $1\bpermd_rb[63:0] + attribute \src "libresoc.v:153424.5-153424.29" + switch \initial + attribute \src "libresoc.v:153424.9-153424.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" + switch \logical_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0001001 + assign { } { } + assign $1\bpermd_rb[63:0] \rb + case + assign $1\bpermd_rb[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \bpermd_rb $0\bpermd_rb[63:0] + end + attribute \src "libresoc.v:153434.3-153444.6" + process $proc$libresoc.v:153434$7596 + assign { } { } + assign { } { } + assign $0\popcount_a[63:0] $1\popcount_a[63:0] + attribute \src "libresoc.v:153435.5-153435.29" + switch \initial + attribute \src "libresoc.v:153435.9-153435.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" + switch \logical_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0110110 + assign { } { } + assign $1\popcount_a[63:0] \ra + case + assign $1\popcount_a[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \popcount_a $0\popcount_a[63:0] + end + attribute \src "libresoc.v:153445.3-153455.6" + process $proc$libresoc.v:153445$7597 + assign { } { } + assign { } { } + assign $0\b[63:0] $1\b[63:0] + attribute \src "libresoc.v:153446.5-153446.29" + switch \initial + attribute \src "libresoc.v:153446.9-153446.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" + switch \logical_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0110110 + assign { } { } + assign $1\b[63:0] \rb + case + assign $1\b[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \b $0\b[63:0] + end + attribute \src "libresoc.v:153456.3-153466.6" + process $proc$libresoc.v:153456$7598 + assign { } { } + assign { } { } + assign $0\popcount_data_len[63:0] $1\popcount_data_len[63:0] + attribute \src "libresoc.v:153457.5-153457.29" + switch \initial + attribute \src "libresoc.v:153457.9-153457.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" + switch \logical_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0110110 + assign { } { } + assign $1\popcount_data_len[63:0] \$169 + case + assign $1\popcount_data_len[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \popcount_data_len $0\popcount_data_len[63:0] + end + attribute \src "libresoc.v:153467.3-153477.6" + process $proc$libresoc.v:153467$7599 + assign { } { } + assign { } { } + assign $0\par0[0:0] $1\par0[0:0] + attribute \src "libresoc.v:153468.5-153468.29" + switch \initial + attribute \src "libresoc.v:153468.9-153468.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" + switch \logical_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0110111 + assign { } { } + assign $1\par0[0:0] \$171 + case + assign $1\par0[0:0] 1'0 + end + sync always + update \par0 $0\par0[0:0] + end + attribute \src "libresoc.v:153478.3-153488.6" + process $proc$libresoc.v:153478$7600 + assign { } { } + assign { } { } + assign $0\par1[0:0] $1\par1[0:0] + attribute \src "libresoc.v:153479.5-153479.29" + switch \initial + attribute \src "libresoc.v:153479.9-153479.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" + switch \logical_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0110111 + assign { } { } + assign $1\par1[0:0] \$173 + case + assign $1\par1[0:0] 1'0 + end + sync always + update \par1 $0\par1[0:0] + end + attribute \src "libresoc.v:153489.3-153499.6" + process $proc$libresoc.v:153489$7601 + assign { } { } + assign { } { } + assign $0\count_right[0:0] $1\count_right[0:0] + attribute \src "libresoc.v:153490.5-153490.29" + switch \initial + attribute \src "libresoc.v:153490.9-153490.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" + switch \logical_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0001110 + assign { } { } + assign $1\count_right[0:0] \logical_op__insn [10] + case + assign $1\count_right[0:0] 1'0 + end + sync always + update \count_right $0\count_right[0:0] + end + attribute \src "libresoc.v:153500.3-153510.6" + process $proc$libresoc.v:153500$7602 + assign { } { } + assign { } { } + assign $0\a32[31:0] $1\a32[31:0] + attribute \src "libresoc.v:153501.5-153501.29" + switch \initial + attribute \src "libresoc.v:153501.9-153501.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" + switch \logical_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0001110 + assign { } { } + assign $1\a32[31:0] \ra [31:0] + case + assign $1\a32[31:0] 0 + end + sync always + update \a32 $0\a32[31:0] + end + attribute \src "libresoc.v:153511.3-153529.6" + process $proc$libresoc.v:153511$7603 + assign { } { } + assign { } { } + assign $0\cntz_i[63:0] $1\cntz_i[63:0] + attribute \src "libresoc.v:153512.5-153512.29" + switch \initial + attribute \src "libresoc.v:153512.9-153512.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" + switch \logical_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0001110 + assign { } { } + assign $1\cntz_i[63:0] $2\cntz_i[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:106" + switch \logical_op__is_32bit + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cntz_i[63:0] \$175 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\cntz_i[63:0] \$179 + end + case + assign $1\cntz_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \cntz_i $0\cntz_i[63:0] + end + connect \$99 $eq$libresoc.v:153252$7507_Y + connect \$101 $eq$libresoc.v:153253$7508_Y + connect \$103 $eq$libresoc.v:153254$7509_Y + connect \$105 $eq$libresoc.v:153255$7510_Y + connect \$107 $eq$libresoc.v:153256$7511_Y + connect \$109 $eq$libresoc.v:153257$7512_Y + connect \$111 $eq$libresoc.v:153258$7513_Y + connect \$113 $eq$libresoc.v:153259$7514_Y + connect \$115 $eq$libresoc.v:153260$7515_Y + connect \$117 $eq$libresoc.v:153261$7516_Y + connect \$119 $eq$libresoc.v:153262$7517_Y + connect \$121 $eq$libresoc.v:153263$7518_Y + connect \$123 $eq$libresoc.v:153264$7519_Y + connect \$125 $eq$libresoc.v:153265$7520_Y + connect \$127 $eq$libresoc.v:153266$7521_Y + connect \$129 $eq$libresoc.v:153267$7522_Y + connect \$131 $eq$libresoc.v:153268$7523_Y + connect \$133 $eq$libresoc.v:153269$7524_Y + connect \$135 $eq$libresoc.v:153270$7525_Y + connect \$137 $eq$libresoc.v:153271$7526_Y + connect \$139 $eq$libresoc.v:153272$7527_Y + connect \$141 $eq$libresoc.v:153273$7528_Y + connect \$143 $eq$libresoc.v:153274$7529_Y + connect \$145 $eq$libresoc.v:153275$7530_Y + connect \$147 $eq$libresoc.v:153276$7531_Y + connect \$149 $eq$libresoc.v:153277$7532_Y + connect \$151 $eq$libresoc.v:153278$7533_Y + connect \$153 $eq$libresoc.v:153279$7534_Y + connect \$155 $eq$libresoc.v:153280$7535_Y + connect \$158 $xor$libresoc.v:153281$7536_Y + connect \$157 $pos$libresoc.v:153282$7538_Y + connect \$162 $sub$libresoc.v:153283$7539_Y + connect \$164 $pos$libresoc.v:153284$7541_Y + connect \$166 $ternary$libresoc.v:153285$7542_Y + connect \$161 $pos$libresoc.v:153286$7544_Y + connect \$169 $pos$libresoc.v:153287$7546_Y + connect \$171 $reduce_xor$libresoc.v:153288$7547_Y + connect \$173 $reduce_xor$libresoc.v:153289$7548_Y + connect \$176 $ternary$libresoc.v:153290$7549_Y + connect \$175 $pos$libresoc.v:153291$7551_Y + connect \$179 $ternary$libresoc.v:153292$7552_Y + connect \$21 $and$libresoc.v:153293$7553_Y + connect \$23 $or$libresoc.v:153294$7554_Y + connect \$25 $xor$libresoc.v:153295$7555_Y + connect \$27 $eq$libresoc.v:153296$7556_Y + connect \$29 $eq$libresoc.v:153297$7557_Y + connect \$31 $eq$libresoc.v:153298$7558_Y + connect \$33 $eq$libresoc.v:153299$7559_Y + connect \$35 $eq$libresoc.v:153300$7560_Y + connect \$37 $eq$libresoc.v:153301$7561_Y + connect \$39 $eq$libresoc.v:153302$7562_Y + connect \$41 $eq$libresoc.v:153303$7563_Y + connect \$43 $eq$libresoc.v:153304$7564_Y + connect \$45 $eq$libresoc.v:153305$7565_Y + connect \$47 $eq$libresoc.v:153306$7566_Y + connect \$49 $eq$libresoc.v:153307$7567_Y + connect \$51 $eq$libresoc.v:153308$7568_Y + connect \$53 $eq$libresoc.v:153309$7569_Y + connect \$55 $eq$libresoc.v:153310$7570_Y + connect \$57 $eq$libresoc.v:153311$7571_Y + connect \$59 $eq$libresoc.v:153312$7572_Y + connect \$61 $eq$libresoc.v:153313$7573_Y + connect \$63 $eq$libresoc.v:153314$7574_Y + connect \$65 $eq$libresoc.v:153315$7575_Y + connect \$67 $eq$libresoc.v:153316$7576_Y + connect \$69 $eq$libresoc.v:153317$7577_Y + connect \$71 $eq$libresoc.v:153318$7578_Y + connect \$73 $eq$libresoc.v:153319$7579_Y + connect \$75 $eq$libresoc.v:153320$7580_Y + connect \$77 $eq$libresoc.v:153321$7581_Y + connect \$79 $eq$libresoc.v:153322$7582_Y + connect \$81 $eq$libresoc.v:153323$7583_Y + connect \$83 $eq$libresoc.v:153324$7584_Y + connect \$85 $eq$libresoc.v:153325$7585_Y + connect \$87 $eq$libresoc.v:153326$7586_Y + connect \$89 $eq$libresoc.v:153327$7587_Y + connect \$91 $eq$libresoc.v:153328$7588_Y + connect \$93 $eq$libresoc.v:153329$7589_Y + connect \$95 $eq$libresoc.v:153330$7590_Y + connect \$97 $eq$libresoc.v:153331$7591_Y + connect { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } + connect \muxid$1 \muxid + connect \xer_so$20 \xer_so +end +attribute \src "libresoc.v:153537.1-154048.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.alu_cr0.pipe.main" +attribute \generator "nMigen" +module \main$9 + attribute \src "libresoc.v:153903.3-153913.6" + wire width 2 $0\BC[1:0] + attribute \src "libresoc.v:153957.3-153967.6" + wire width 2 $0\ba[1:0] + attribute \src "libresoc.v:153968.3-153978.6" + wire width 2 $0\bb[1:0] + attribute \src "libresoc.v:153979.3-153999.6" + wire $0\bit_a[0:0] + attribute \src "libresoc.v:154000.3-154020.6" + wire $0\bit_b[0:0] + attribute \src "libresoc.v:154021.3-154031.6" + wire $0\bit_o[0:0] + attribute \src "libresoc.v:153946.3-153956.6" + wire width 2 $0\bt[1:0] + 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+ connect \Y $extend$libresoc.v:153813$7614_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + cell $pos $extend$libresoc.v:153814$7616 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 5 + connect \A \cr_a + connect \Y $extend$libresoc.v:153814$7616_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + cell $pos $pos$libresoc.v:153811$7612 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:153811$7611_Y + connect \Y $pos$libresoc.v:153811$7612_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:140" + cell $pos $pos$libresoc.v:153813$7615 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \Y_WIDTH 65 + connect \A $extend$libresoc.v:153813$7614_Y + connect \Y $pos$libresoc.v:153813$7615_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + cell $pos $pos$libresoc.v:153814$7617 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A $extend$libresoc.v:153814$7616_Y + connect \Y $pos$libresoc.v:153814$7617_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:86" + cell $sub $sub$libresoc.v:153805$7605 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 3 + connect \A 2'11 + connect \B \cr_op__insn [22:21] + connect \Y $sub$libresoc.v:153805$7605_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:87" + cell $sub $sub$libresoc.v:153806$7606 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 3 + connect \A 2'11 + connect \B \cr_op__insn [17:16] + connect \Y $sub$libresoc.v:153806$7606_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:88" + cell $sub $sub$libresoc.v:153807$7607 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 3 + connect \A 2'11 + connect \B \cr_op__insn [12:11] + connect \Y $sub$libresoc.v:153807$7607_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:99" + cell $mux $ternary$libresoc.v:153808$7608 + parameter \WIDTH 1 + connect \A \lut [1] + connect \B \lut [3] + connect \S \bit_a + connect \Y $ternary$libresoc.v:153808$7608_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:100" + cell $mux $ternary$libresoc.v:153809$7609 + parameter \WIDTH 1 + connect \A \lut [0] + connect \B \lut [2] + connect \S \bit_a + connect \Y $ternary$libresoc.v:153809$7609_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:100" + cell $mux $ternary$libresoc.v:153810$7610 + parameter \WIDTH 1 + connect \A \$20 + connect \B \$18 + connect \S \bit_b + connect \Y $ternary$libresoc.v:153810$7610_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:140" + cell $mux $ternary$libresoc.v:153812$7613 + parameter \WIDTH 64 + connect \A \rb + connect \B \ra + connect \S \cr_bit + connect \Y $ternary$libresoc.v:153812$7613_Y + end + attribute \src "libresoc.v:153538.7-153538.20" + process $proc$libresoc.v:153538$7636 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:153815.3-153849.6" + process $proc$libresoc.v:153815$7618 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\cr_a_ok[0:0] $1\cr_a_ok[0:0] + assign $0\cr_a$6[3:0]$7619 $1\cr_a$6[3:0]$7620 + attribute \src "libresoc.v:153816.5-153816.29" + switch \initial + attribute \src "libresoc.v:153816.9-153816.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" + switch \cr_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0101010 + assign { } { } + assign { } { } + assign $1\cr_a$6[3:0]$7620 \$7 [3:0] + assign $1\cr_a_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 7'1000101 + assign { } { } + assign { } { } + assign { } { } + assign $1\cr_a$6[3:0]$7620 $2\cr_a$6[3:0]$7621 + assign $1\cr_a_ok[0:0] 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:105" + switch \bt + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign $2\cr_a$6[3:0]$7621 [3:1] \cr_c [3:1] + assign $2\cr_a$6[3:0]$7621 [0] \bit_o + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { $2\cr_a$6[3:0]$7621 [3:2] $2\cr_a$6[3:0]$7621 [0] } { \cr_c [3:2] \cr_c [0] } + assign $2\cr_a$6[3:0]$7621 [1] \bit_o + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { $2\cr_a$6[3:0]$7621 [3] $2\cr_a$6[3:0]$7621 [1:0] } { \cr_c [3] \cr_c [1:0] } + assign $2\cr_a$6[3:0]$7621 [2] \bit_o + attribute \src "libresoc.v:0.0-0.0" + case 2'-- + assign $2\cr_a$6[3:0]$7621 [2:0] \cr_c [2:0] + assign $2\cr_a$6[3:0]$7621 [3] \bit_o + case + assign $2\cr_a$6[3:0]$7621 \cr_c + end + case + assign $1\cr_a_ok[0:0] 1'0 + assign $1\cr_a$6[3:0]$7620 4'0000 + end + sync always + update \cr_a_ok $0\cr_a_ok[0:0] + update \cr_a$6 $0\cr_a$6[3:0]$7619 + end + attribute \src "libresoc.v:153850.3-153860.6" + process $proc$libresoc.v:153850$7622 + assign { } { } + assign { } { } + assign $0\full_cr_ok[0:0] $1\full_cr_ok[0:0] + attribute \src "libresoc.v:153851.5-153851.29" + switch \initial + attribute \src "libresoc.v:153851.9-153851.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" + switch \cr_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0110000 + assign { } { } + assign $1\full_cr_ok[0:0] 1'1 + case + assign $1\full_cr_ok[0:0] 1'0 + end + sync always + update \full_cr_ok $0\full_cr_ok[0:0] + end + attribute \src "libresoc.v:153861.3-153902.6" + process $proc$libresoc.v:153861$7623 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\o_ok[0:0] $1\o_ok[0:0] + assign $0\o[63:0] $1\o[63:0] + attribute \src "libresoc.v:153862.5-153862.29" + switch \initial + attribute \src "libresoc.v:153862.9-153862.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" + switch \cr_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0101101 + assign { } { } + assign { } { } + assign $1\o[63:0] \$24 + assign $1\o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 7'0100011 + assign { } { } + assign { } { } + assign $1\o[63:0] \$26 [63:0] + assign $1\o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 7'0111011 + assign { } { } + assign { } { } + assign $1\o[63:0] $2\o[63:0] + assign $1\o_ok[0:0] 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:144" + switch { \cr_a [2] \cr_a [3] } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $2\o[63:0] 64'1111111111111111111111111111111111111111111111111111111111111111 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $2\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000001 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + case + assign $1\o_ok[0:0] 1'0 + assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \o_ok $0\o_ok[0:0] + update \o $0\o[63:0] + end + attribute \src "libresoc.v:153903.3-153913.6" + process $proc$libresoc.v:153903$7624 + assign { } { } + assign { } { } + assign $0\BC[1:0] $1\BC[1:0] + attribute \src "libresoc.v:153904.5-153904.29" + switch \initial + attribute \src "libresoc.v:153904.9-153904.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" + switch \cr_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0100011 + assign { } { } + assign $1\BC[1:0] \cr_op__insn [7:6] + case + assign $1\BC[1:0] 2'00 + end + sync always + update \BC $0\BC[1:0] + end + attribute \src "libresoc.v:153914.3-153934.6" + process $proc$libresoc.v:153914$7625 + assign { } { } + assign { } { } + assign $0\cr_bit[0:0] $1\cr_bit[0:0] + attribute \src "libresoc.v:153915.5-153915.29" + switch \initial + attribute \src "libresoc.v:153915.9-153915.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" + switch \cr_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0100011 + assign { } { } + assign $1\cr_bit[0:0] $2\cr_bit[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:137" + switch \BC + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $2\cr_bit[0:0] \cr_a [3] + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $2\cr_bit[0:0] \cr_a [2] + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $2\cr_bit[0:0] \cr_a [1] + attribute \src "libresoc.v:0.0-0.0" + case 2'-- + assign { } { } + assign $2\cr_bit[0:0] \cr_a [0] + case + assign $2\cr_bit[0:0] 1'0 + end + case + assign $1\cr_bit[0:0] 1'0 + end + sync always + update \cr_bit $0\cr_bit[0:0] + end + attribute \src "libresoc.v:153935.3-153945.6" + process $proc$libresoc.v:153935$7626 + assign { } { } + assign { } { } + assign $0\lut[3:0] $1\lut[3:0] + attribute \src "libresoc.v:153936.5-153936.29" + switch \initial + attribute \src "libresoc.v:153936.9-153936.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" + switch \cr_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'1000101 + assign { } { } + assign $1\lut[3:0] \cr_op__insn [9:6] + case + assign $1\lut[3:0] 4'0000 + end + sync always + update \lut $0\lut[3:0] + end + attribute \src "libresoc.v:153946.3-153956.6" + process $proc$libresoc.v:153946$7627 + assign { } { } + assign { } { } + assign $0\bt[1:0] $1\bt[1:0] + attribute \src "libresoc.v:153947.5-153947.29" + switch \initial + attribute \src "libresoc.v:153947.9-153947.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" + switch \cr_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'1000101 + assign { } { } + assign $1\bt[1:0] \$9 [1:0] + case + assign $1\bt[1:0] 2'00 + end + sync always + update \bt $0\bt[1:0] + end + attribute \src "libresoc.v:153957.3-153967.6" + process $proc$libresoc.v:153957$7628 + assign { } { } + assign { } { } + assign $0\ba[1:0] $1\ba[1:0] + attribute \src "libresoc.v:153958.5-153958.29" + switch \initial + attribute \src "libresoc.v:153958.9-153958.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" + switch \cr_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'1000101 + assign { } { } + assign $1\ba[1:0] \$12 [1:0] + case + assign $1\ba[1:0] 2'00 + end + sync always + update \ba $0\ba[1:0] + end + attribute \src "libresoc.v:153968.3-153978.6" + process $proc$libresoc.v:153968$7629 + assign { } { } + assign { } { } + assign $0\bb[1:0] $1\bb[1:0] + attribute \src "libresoc.v:153969.5-153969.29" + switch \initial + attribute \src "libresoc.v:153969.9-153969.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" + switch \cr_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'1000101 + assign { } { } + assign $1\bb[1:0] \$15 [1:0] + case + assign $1\bb[1:0] 2'00 + end + sync always + update \bb $0\bb[1:0] + end + attribute \src "libresoc.v:153979.3-153999.6" + process $proc$libresoc.v:153979$7630 + assign { } { } + assign { } { } + assign $0\bit_a[0:0] $1\bit_a[0:0] + attribute \src "libresoc.v:153980.5-153980.29" + switch \initial + attribute \src "libresoc.v:153980.9-153980.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" + switch \cr_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'1000101 + assign { } { } + assign $1\bit_a[0:0] $2\bit_a[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:93" + switch \ba + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $2\bit_a[0:0] \cr_a [0] + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $2\bit_a[0:0] \cr_a [1] + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $2\bit_a[0:0] \cr_a [2] + attribute \src "libresoc.v:0.0-0.0" + case 2'-- + assign { } { } + assign $2\bit_a[0:0] \cr_a [3] + case + assign $2\bit_a[0:0] 1'0 + end + case + assign $1\bit_a[0:0] 1'0 + end + sync always + update \bit_a $0\bit_a[0:0] + end + attribute \src "libresoc.v:154000.3-154020.6" + process $proc$libresoc.v:154000$7631 + assign { } { } + assign { } { } + assign $0\bit_b[0:0] $1\bit_b[0:0] + attribute \src "libresoc.v:154001.5-154001.29" + switch \initial + attribute \src "libresoc.v:154001.9-154001.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" + switch \cr_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'1000101 + assign { } { } + assign $1\bit_b[0:0] $2\bit_b[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:94" + switch \bb + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $2\bit_b[0:0] \cr_b [0] + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $2\bit_b[0:0] \cr_b [1] + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $2\bit_b[0:0] \cr_b [2] + attribute \src "libresoc.v:0.0-0.0" + case 2'-- + assign { } { } + assign $2\bit_b[0:0] \cr_b [3] + case + assign $2\bit_b[0:0] 1'0 + end + case + assign $1\bit_b[0:0] 1'0 + end + sync always + update \bit_b $0\bit_b[0:0] + end + attribute \src "libresoc.v:154021.3-154031.6" + process $proc$libresoc.v:154021$7632 + assign { } { } + assign { } { } + assign $0\bit_o[0:0] $1\bit_o[0:0] + attribute \src "libresoc.v:154022.5-154022.29" + switch \initial + attribute \src "libresoc.v:154022.9-154022.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" + switch \cr_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'1000101 + assign { } { } + assign $1\bit_o[0:0] \$22 + case + assign $1\bit_o[0:0] 1'0 + end + sync always + update \bit_o $0\bit_o[0:0] + end + attribute \src "libresoc.v:154032.3-154042.6" + process $proc$libresoc.v:154032$7633 + assign { } { } + assign { } { } + assign $0\full_cr$5[31:0]$7634 $1\full_cr$5[31:0]$7635 + attribute \src "libresoc.v:154033.5-154033.29" + switch \initial + attribute \src "libresoc.v:154033.9-154033.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" + switch \cr_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0110000 + assign { } { } + assign $1\full_cr$5[31:0]$7635 \ra [31:0] + case + assign $1\full_cr$5[31:0]$7635 0 + end + sync always + update \full_cr$5 $0\full_cr$5[31:0]$7634 + end + connect \$10 $sub$libresoc.v:153805$7605_Y + connect \$13 $sub$libresoc.v:153806$7606_Y + connect \$16 $sub$libresoc.v:153807$7607_Y + connect \$18 $ternary$libresoc.v:153808$7608_Y + connect \$20 $ternary$libresoc.v:153809$7609_Y + connect \$22 $ternary$libresoc.v:153810$7610_Y + connect \$24 $pos$libresoc.v:153811$7612_Y + connect \$27 $ternary$libresoc.v:153812$7613_Y + connect \$26 $pos$libresoc.v:153813$7615_Y + connect \$7 $pos$libresoc.v:153814$7617_Y + connect \$9 \$10 + connect \$12 \$13 + connect \$15 \$16 + connect { \cr_op__insn$4 \cr_op__fn_unit$3 \cr_op__insn_type$2 } { \cr_op__insn \cr_op__fn_unit \cr_op__insn_type } + connect \muxid$1 \muxid +end +attribute \src "libresoc.v:154052.1-155209.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0" +attribute \generator "nMigen" +module \mul0 + attribute \src "libresoc.v:154780.3-154781.25" + wire $0\all_rd_dly[0:0] + attribute \src "libresoc.v:154778.3-154779.40" + wire $0\alu_done_dly[0:0] + attribute \src "libresoc.v:155121.3-155129.6" + wire $0\alu_l_r_alu$next[0:0]$7842 + attribute \src "libresoc.v:154706.3-154707.39" + wire $0\alu_l_r_alu[0:0] + attribute \src "libresoc.v:154961.3-154993.6" + wire width 13 $0\alu_mul0_mul_op__fn_unit$next[12:0]$7767 + attribute \src "libresoc.v:154734.3-154735.65" + wire width 13 $0\alu_mul0_mul_op__fn_unit[12:0] + attribute \src "libresoc.v:154961.3-154993.6" + wire width 64 $0\alu_mul0_mul_op__imm_data__data$next[63:0]$7768 + attribute \src "libresoc.v:154736.3-154737.79" + wire width 64 $0\alu_mul0_mul_op__imm_data__data[63:0] + attribute \src "libresoc.v:154961.3-154993.6" + wire $0\alu_mul0_mul_op__imm_data__ok$next[0:0]$7769 + attribute \src "libresoc.v:154738.3-154739.75" + wire $0\alu_mul0_mul_op__imm_data__ok[0:0] + attribute \src "libresoc.v:154961.3-154993.6" + wire width 32 $0\alu_mul0_mul_op__insn$next[31:0]$7770 + attribute \src "libresoc.v:154754.3-154755.59" + wire width 32 $0\alu_mul0_mul_op__insn[31:0] + attribute \src "libresoc.v:154961.3-154993.6" + wire width 7 $0\alu_mul0_mul_op__insn_type$next[6:0]$7771 + attribute \src "libresoc.v:154732.3-154733.69" + wire width 7 $0\alu_mul0_mul_op__insn_type[6:0] + attribute \src "libresoc.v:154961.3-154993.6" + wire $0\alu_mul0_mul_op__is_32bit$next[0:0]$7772 + attribute \src "libresoc.v:154750.3-154751.67" + wire $0\alu_mul0_mul_op__is_32bit[0:0] + attribute \src "libresoc.v:154961.3-154993.6" + wire $0\alu_mul0_mul_op__is_signed$next[0:0]$7773 + attribute \src "libresoc.v:154752.3-154753.69" + wire $0\alu_mul0_mul_op__is_signed[0:0] + attribute \src "libresoc.v:154961.3-154993.6" + wire $0\alu_mul0_mul_op__oe__oe$next[0:0]$7774 + attribute \src "libresoc.v:154744.3-154745.63" + wire $0\alu_mul0_mul_op__oe__oe[0:0] + attribute \src "libresoc.v:154961.3-154993.6" + wire $0\alu_mul0_mul_op__oe__ok$next[0:0]$7775 + attribute \src "libresoc.v:154746.3-154747.63" + wire $0\alu_mul0_mul_op__oe__ok[0:0] + attribute \src "libresoc.v:154961.3-154993.6" + wire $0\alu_mul0_mul_op__rc__ok$next[0:0]$7776 + attribute \src "libresoc.v:154742.3-154743.63" + wire $0\alu_mul0_mul_op__rc__ok[0:0] + attribute \src "libresoc.v:154961.3-154993.6" + wire $0\alu_mul0_mul_op__rc__rc$next[0:0]$7777 + attribute \src "libresoc.v:154740.3-154741.63" + wire $0\alu_mul0_mul_op__rc__rc[0:0] + attribute \src "libresoc.v:154961.3-154993.6" + wire $0\alu_mul0_mul_op__write_cr0$next[0:0]$7778 + attribute \src "libresoc.v:154748.3-154749.69" + wire $0\alu_mul0_mul_op__write_cr0[0:0] + attribute \src "libresoc.v:155112.3-155120.6" + wire $0\alui_l_r_alui$next[0:0]$7839 + attribute \src "libresoc.v:154708.3-154709.43" + wire $0\alui_l_r_alui[0:0] + attribute \src "libresoc.v:154994.3-155015.6" + wire width 64 $0\data_r0__o$next[63:0]$7798 + attribute \src "libresoc.v:154728.3-154729.37" + wire width 64 $0\data_r0__o[63:0] + attribute \src "libresoc.v:154994.3-155015.6" + wire $0\data_r0__o_ok$next[0:0]$7799 + attribute \src "libresoc.v:154730.3-154731.43" + wire $0\data_r0__o_ok[0:0] + attribute \src "libresoc.v:155016.3-155037.6" + wire width 4 $0\data_r1__cr_a$next[3:0]$7806 + attribute \src "libresoc.v:154724.3-154725.43" + wire width 4 $0\data_r1__cr_a[3:0] + attribute \src "libresoc.v:155016.3-155037.6" + wire $0\data_r1__cr_a_ok$next[0:0]$7807 + attribute \src "libresoc.v:154726.3-154727.49" + wire $0\data_r1__cr_a_ok[0:0] + attribute \src "libresoc.v:155038.3-155059.6" + wire width 2 $0\data_r2__xer_ov$next[1:0]$7814 + attribute \src "libresoc.v:154720.3-154721.47" + wire width 2 $0\data_r2__xer_ov[1:0] + attribute \src "libresoc.v:155038.3-155059.6" + wire $0\data_r2__xer_ov_ok$next[0:0]$7815 + attribute \src "libresoc.v:154722.3-154723.53" + wire $0\data_r2__xer_ov_ok[0:0] + attribute \src "libresoc.v:155060.3-155081.6" + wire $0\data_r3__xer_so$next[0:0]$7822 + attribute \src "libresoc.v:154716.3-154717.47" + wire $0\data_r3__xer_so[0:0] + attribute \src "libresoc.v:155060.3-155081.6" + wire $0\data_r3__xer_so_ok$next[0:0]$7823 + attribute \src "libresoc.v:154718.3-154719.53" + wire $0\data_r3__xer_so_ok[0:0] + attribute \src "libresoc.v:155130.3-155139.6" + wire width 64 $0\dest1_o[63:0] + attribute \src "libresoc.v:155140.3-155149.6" + wire width 4 $0\dest2_o[3:0] + attribute \src "libresoc.v:155150.3-155159.6" + wire width 2 $0\dest3_o[1:0] + attribute \src "libresoc.v:155160.3-155169.6" + wire $0\dest4_o[0:0] + attribute \src "libresoc.v:154053.7-154053.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:154916.3-154924.6" + wire $0\opc_l_r_opc$next[0:0]$7752 + attribute \src "libresoc.v:154764.3-154765.39" + wire $0\opc_l_r_opc[0:0] + attribute \src "libresoc.v:154907.3-154915.6" + wire $0\opc_l_s_opc$next[0:0]$7749 + attribute \src "libresoc.v:154766.3-154767.39" + wire $0\opc_l_s_opc[0:0] + attribute \src "libresoc.v:155170.3-155178.6" + wire width 4 $0\prev_wr_go$next[3:0]$7849 + attribute \src "libresoc.v:154776.3-154777.37" + wire width 4 $0\prev_wr_go[3:0] + attribute \src "libresoc.v:154861.3-154870.6" + wire $0\req_done[0:0] + attribute \src "libresoc.v:154952.3-154960.6" + wire width 4 $0\req_l_r_req$next[3:0]$7764 + attribute \src "libresoc.v:154756.3-154757.39" + wire width 4 $0\req_l_r_req[3:0] + attribute \src "libresoc.v:154943.3-154951.6" + wire width 4 $0\req_l_s_req$next[3:0]$7761 + attribute \src "libresoc.v:154758.3-154759.39" + wire width 4 $0\req_l_s_req[3:0] + attribute \src "libresoc.v:154880.3-154888.6" + wire $0\rok_l_r_rdok$next[0:0]$7740 + attribute \src "libresoc.v:154772.3-154773.41" + wire $0\rok_l_r_rdok[0:0] + attribute \src "libresoc.v:154871.3-154879.6" + wire $0\rok_l_s_rdok$next[0:0]$7737 + attribute \src "libresoc.v:154774.3-154775.41" + wire $0\rok_l_s_rdok[0:0] + attribute \src "libresoc.v:154898.3-154906.6" + wire $0\rst_l_r_rst$next[0:0]$7746 + attribute \src "libresoc.v:154768.3-154769.39" + wire $0\rst_l_r_rst[0:0] + attribute \src "libresoc.v:154889.3-154897.6" + wire $0\rst_l_s_rst$next[0:0]$7743 + attribute \src "libresoc.v:154770.3-154771.39" + wire $0\rst_l_s_rst[0:0] + attribute \src "libresoc.v:154934.3-154942.6" + wire width 3 $0\src_l_r_src$next[2:0]$7758 + attribute \src "libresoc.v:154760.3-154761.39" + wire width 3 $0\src_l_r_src[2:0] + attribute \src "libresoc.v:154925.3-154933.6" + wire width 3 $0\src_l_s_src$next[2:0]$7755 + attribute \src "libresoc.v:154762.3-154763.39" + wire width 3 $0\src_l_s_src[2:0] + attribute \src "libresoc.v:155082.3-155091.6" + wire width 64 $0\src_r0$next[63:0]$7830 + attribute \src "libresoc.v:154714.3-154715.29" + wire width 64 $0\src_r0[63:0] + attribute \src "libresoc.v:155092.3-155101.6" + wire width 64 $0\src_r1$next[63:0]$7833 + attribute \src "libresoc.v:154712.3-154713.29" + wire width 64 $0\src_r1[63:0] + attribute \src "libresoc.v:155102.3-155111.6" + wire $0\src_r2$next[0:0]$7836 + attribute \src "libresoc.v:154710.3-154711.29" + wire $0\src_r2[0:0] + attribute \src "libresoc.v:154177.7-154177.24" + wire $1\all_rd_dly[0:0] + attribute \src "libresoc.v:154187.7-154187.26" + wire $1\alu_done_dly[0:0] + attribute \src "libresoc.v:155121.3-155129.6" + wire $1\alu_l_r_alu$next[0:0]$7843 + attribute \src "libresoc.v:154195.7-154195.25" + wire $1\alu_l_r_alu[0:0] + attribute \src "libresoc.v:154961.3-154993.6" + wire width 13 $1\alu_mul0_mul_op__fn_unit$next[12:0]$7779 + attribute \src "libresoc.v:154217.14-154217.49" + wire width 13 $1\alu_mul0_mul_op__fn_unit[12:0] + attribute \src "libresoc.v:154961.3-154993.6" + wire width 64 $1\alu_mul0_mul_op__imm_data__data$next[63:0]$7780 + attribute \src "libresoc.v:154221.14-154221.68" + wire width 64 $1\alu_mul0_mul_op__imm_data__data[63:0] + attribute \src "libresoc.v:154961.3-154993.6" + wire $1\alu_mul0_mul_op__imm_data__ok$next[0:0]$7781 + attribute \src "libresoc.v:154225.7-154225.43" + wire $1\alu_mul0_mul_op__imm_data__ok[0:0] + attribute \src "libresoc.v:154961.3-154993.6" + wire width 32 $1\alu_mul0_mul_op__insn$next[31:0]$7782 + attribute \src "libresoc.v:154229.14-154229.43" + wire width 32 $1\alu_mul0_mul_op__insn[31:0] + attribute \src "libresoc.v:154961.3-154993.6" + wire width 7 $1\alu_mul0_mul_op__insn_type$next[6:0]$7783 + attribute \src "libresoc.v:154307.13-154307.47" + wire width 7 $1\alu_mul0_mul_op__insn_type[6:0] + attribute \src "libresoc.v:154961.3-154993.6" + wire $1\alu_mul0_mul_op__is_32bit$next[0:0]$7784 + attribute \src "libresoc.v:154311.7-154311.39" + wire $1\alu_mul0_mul_op__is_32bit[0:0] + attribute \src "libresoc.v:154961.3-154993.6" + wire $1\alu_mul0_mul_op__is_signed$next[0:0]$7785 + attribute \src "libresoc.v:154315.7-154315.40" + wire $1\alu_mul0_mul_op__is_signed[0:0] + attribute \src "libresoc.v:154961.3-154993.6" + wire $1\alu_mul0_mul_op__oe__oe$next[0:0]$7786 + attribute \src "libresoc.v:154319.7-154319.37" + wire $1\alu_mul0_mul_op__oe__oe[0:0] + attribute \src "libresoc.v:154961.3-154993.6" + wire $1\alu_mul0_mul_op__oe__ok$next[0:0]$7787 + attribute \src "libresoc.v:154323.7-154323.37" + wire $1\alu_mul0_mul_op__oe__ok[0:0] + attribute \src "libresoc.v:154961.3-154993.6" + wire $1\alu_mul0_mul_op__rc__ok$next[0:0]$7788 + attribute \src "libresoc.v:154327.7-154327.37" + wire $1\alu_mul0_mul_op__rc__ok[0:0] + attribute \src "libresoc.v:154961.3-154993.6" + wire $1\alu_mul0_mul_op__rc__rc$next[0:0]$7789 + attribute \src "libresoc.v:154331.7-154331.37" + wire $1\alu_mul0_mul_op__rc__rc[0:0] + attribute \src "libresoc.v:154961.3-154993.6" + wire $1\alu_mul0_mul_op__write_cr0$next[0:0]$7790 + attribute \src "libresoc.v:154335.7-154335.40" + wire $1\alu_mul0_mul_op__write_cr0[0:0] + attribute \src "libresoc.v:155112.3-155120.6" + wire $1\alui_l_r_alui$next[0:0]$7840 + attribute \src "libresoc.v:154365.7-154365.27" + wire $1\alui_l_r_alui[0:0] + attribute \src "libresoc.v:154994.3-155015.6" + wire width 64 $1\data_r0__o$next[63:0]$7800 + attribute \src "libresoc.v:154399.14-154399.47" + wire width 64 $1\data_r0__o[63:0] + attribute \src "libresoc.v:154994.3-155015.6" + wire $1\data_r0__o_ok$next[0:0]$7801 + attribute \src "libresoc.v:154403.7-154403.27" + wire $1\data_r0__o_ok[0:0] + attribute \src "libresoc.v:155016.3-155037.6" + wire width 4 $1\data_r1__cr_a$next[3:0]$7808 + attribute \src "libresoc.v:154407.13-154407.33" + wire width 4 $1\data_r1__cr_a[3:0] + attribute \src "libresoc.v:155016.3-155037.6" + wire $1\data_r1__cr_a_ok$next[0:0]$7809 + attribute \src "libresoc.v:154411.7-154411.30" + wire $1\data_r1__cr_a_ok[0:0] + attribute \src "libresoc.v:155038.3-155059.6" + wire width 2 $1\data_r2__xer_ov$next[1:0]$7816 + attribute \src "libresoc.v:154415.13-154415.35" + wire width 2 $1\data_r2__xer_ov[1:0] + attribute \src "libresoc.v:155038.3-155059.6" + wire $1\data_r2__xer_ov_ok$next[0:0]$7817 + attribute \src "libresoc.v:154419.7-154419.32" + wire $1\data_r2__xer_ov_ok[0:0] + attribute \src "libresoc.v:155060.3-155081.6" + wire $1\data_r3__xer_so$next[0:0]$7824 + attribute \src "libresoc.v:154423.7-154423.29" + wire $1\data_r3__xer_so[0:0] + attribute \src "libresoc.v:155060.3-155081.6" + wire $1\data_r3__xer_so_ok$next[0:0]$7825 + attribute \src "libresoc.v:154427.7-154427.32" + wire $1\data_r3__xer_so_ok[0:0] + attribute \src "libresoc.v:155130.3-155139.6" + wire width 64 $1\dest1_o[63:0] + attribute \src "libresoc.v:155140.3-155149.6" + wire width 4 $1\dest2_o[3:0] + attribute \src "libresoc.v:155150.3-155159.6" + wire width 2 $1\dest3_o[1:0] + attribute \src "libresoc.v:155160.3-155169.6" + wire $1\dest4_o[0:0] + attribute \src "libresoc.v:154916.3-154924.6" + wire $1\opc_l_r_opc$next[0:0]$7753 + attribute \src "libresoc.v:154447.7-154447.25" + wire $1\opc_l_r_opc[0:0] + attribute \src "libresoc.v:154907.3-154915.6" + wire $1\opc_l_s_opc$next[0:0]$7750 + attribute \src "libresoc.v:154451.7-154451.25" + wire $1\opc_l_s_opc[0:0] + attribute \src "libresoc.v:155170.3-155178.6" + wire width 4 $1\prev_wr_go$next[3:0]$7850 + attribute \src "libresoc.v:154567.13-154567.30" + wire width 4 $1\prev_wr_go[3:0] + attribute \src "libresoc.v:154861.3-154870.6" + wire $1\req_done[0:0] + attribute \src "libresoc.v:154952.3-154960.6" + wire width 4 $1\req_l_r_req$next[3:0]$7765 + attribute \src "libresoc.v:154575.13-154575.31" + wire width 4 $1\req_l_r_req[3:0] + attribute \src "libresoc.v:154943.3-154951.6" + wire width 4 $1\req_l_s_req$next[3:0]$7762 + attribute \src "libresoc.v:154579.13-154579.31" + wire width 4 $1\req_l_s_req[3:0] + attribute \src "libresoc.v:154880.3-154888.6" + wire $1\rok_l_r_rdok$next[0:0]$7741 + attribute \src "libresoc.v:154591.7-154591.26" + wire $1\rok_l_r_rdok[0:0] + attribute \src "libresoc.v:154871.3-154879.6" + wire $1\rok_l_s_rdok$next[0:0]$7738 + attribute \src "libresoc.v:154595.7-154595.26" + wire $1\rok_l_s_rdok[0:0] + attribute \src "libresoc.v:154898.3-154906.6" + wire $1\rst_l_r_rst$next[0:0]$7747 + attribute \src "libresoc.v:154599.7-154599.25" + wire $1\rst_l_r_rst[0:0] + attribute \src "libresoc.v:154889.3-154897.6" + wire $1\rst_l_s_rst$next[0:0]$7744 + attribute \src "libresoc.v:154603.7-154603.25" + wire $1\rst_l_s_rst[0:0] + attribute \src "libresoc.v:154934.3-154942.6" + wire width 3 $1\src_l_r_src$next[2:0]$7759 + attribute \src "libresoc.v:154617.13-154617.31" + wire width 3 $1\src_l_r_src[2:0] + attribute \src "libresoc.v:154925.3-154933.6" + wire width 3 $1\src_l_s_src$next[2:0]$7756 + attribute \src "libresoc.v:154621.13-154621.31" + wire width 3 $1\src_l_s_src[2:0] + attribute \src "libresoc.v:155082.3-155091.6" + wire width 64 $1\src_r0$next[63:0]$7831 + attribute \src "libresoc.v:154627.14-154627.43" + wire width 64 $1\src_r0[63:0] + attribute \src "libresoc.v:155092.3-155101.6" + wire width 64 $1\src_r1$next[63:0]$7834 + attribute \src "libresoc.v:154631.14-154631.43" + wire width 64 $1\src_r1[63:0] + attribute \src "libresoc.v:155102.3-155111.6" + wire $1\src_r2$next[0:0]$7837 + attribute \src "libresoc.v:154635.7-154635.20" + wire $1\src_r2[0:0] + attribute \src "libresoc.v:154961.3-154993.6" + wire width 64 $2\alu_mul0_mul_op__imm_data__data$next[63:0]$7791 + attribute \src "libresoc.v:154961.3-154993.6" + wire $2\alu_mul0_mul_op__imm_data__ok$next[0:0]$7792 + attribute \src "libresoc.v:154961.3-154993.6" + wire $2\alu_mul0_mul_op__oe__oe$next[0:0]$7793 + attribute \src "libresoc.v:154961.3-154993.6" + wire $2\alu_mul0_mul_op__oe__ok$next[0:0]$7794 + attribute \src "libresoc.v:154961.3-154993.6" + wire $2\alu_mul0_mul_op__rc__ok$next[0:0]$7795 + attribute \src "libresoc.v:154961.3-154993.6" + wire $2\alu_mul0_mul_op__rc__rc$next[0:0]$7796 + attribute \src "libresoc.v:154994.3-155015.6" + wire width 64 $2\data_r0__o$next[63:0]$7802 + attribute \src "libresoc.v:154994.3-155015.6" + wire $2\data_r0__o_ok$next[0:0]$7803 + attribute \src "libresoc.v:155016.3-155037.6" + wire width 4 $2\data_r1__cr_a$next[3:0]$7810 + attribute \src "libresoc.v:155016.3-155037.6" + wire $2\data_r1__cr_a_ok$next[0:0]$7811 + attribute \src "libresoc.v:155038.3-155059.6" + wire width 2 $2\data_r2__xer_ov$next[1:0]$7818 + attribute \src "libresoc.v:155038.3-155059.6" + wire $2\data_r2__xer_ov_ok$next[0:0]$7819 + attribute \src "libresoc.v:155060.3-155081.6" + wire $2\data_r3__xer_so$next[0:0]$7826 + attribute \src "libresoc.v:155060.3-155081.6" + wire $2\data_r3__xer_so_ok$next[0:0]$7827 + attribute \src "libresoc.v:154994.3-155015.6" + wire $3\data_r0__o_ok$next[0:0]$7804 + attribute \src "libresoc.v:155016.3-155037.6" + wire $3\data_r1__cr_a_ok$next[0:0]$7812 + attribute \src "libresoc.v:155038.3-155059.6" + wire $3\data_r2__xer_ov_ok$next[0:0]$7820 + attribute \src "libresoc.v:155060.3-155081.6" + wire $3\data_r3__xer_so_ok$next[0:0]$7828 + attribute \src "libresoc.v:154646.19-154646.113" + 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\enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \alu_mul0_mul_op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \alu_mul0_mul_op__insn_type$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_mul0_mul_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_mul0_mul_op__is_32bit$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_mul0_mul_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_mul0_mul_op__is_signed$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_mul0_mul_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_mul0_mul_op__oe__oe$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_mul0_mul_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_mul0_mul_op__oe__ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_mul0_mul_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_mul0_mul_op__rc__ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_mul0_mul_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_mul0_mul_op__rc__rc$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_mul0_mul_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_mul0_mul_op__write_cr0$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire \alu_mul0_n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire \alu_mul0_n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \alu_mul0_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" + wire \alu_mul0_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" + wire \alu_mul0_p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \alu_mul0_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \alu_mul0_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \alu_mul0_xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \alu_mul0_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \alu_mul0_xer_so$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:197" + wire \alu_pulse + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198" + wire width 4 \alu_pulsem + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire \alui_l_q_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \alui_l_r_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \alui_l_r_alui$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire \alui_l_s_alui + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 32 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 26 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" + wire output 15 \cu_busy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:108" + wire \cu_done_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:104" + wire \cu_go_die_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" + wire input 14 \cu_issue_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 input 18 \cu_rd__go_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 output 17 \cu_rd__rel_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" + wire width 3 input 16 \cu_rdmaskn_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:102" + wire \cu_shadown_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 4 input 24 \cu_wr__go_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 4 output 23 \cu_wr__rel_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:97" + wire width 4 \cu_wrmask_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 64 \data_r0__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 64 \data_r0__o$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r0__o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r0__o_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 4 \data_r1__cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 4 \data_r1__cr_a$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r1__cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r1__cr_a_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 2 \data_r2__xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 2 \data_r2__xer_ov$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r2__xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r2__xer_ov_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r3__xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r3__xer_so$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r3__xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r3__xer_so_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 25 \dest1_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 4 output 27 \dest2_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 2 output 29 \dest3_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire output 31 \dest4_o + attribute \src "libresoc.v:154053.7-154053.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 22 \o_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire \opc_l_q_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \opc_l_r_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \opc_l_r_opc$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire \opc_l_s_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire \opc_l_s_opc$next + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 input 3 \oper_i_alu_mul0__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 4 \oper_i_alu_mul0__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 5 \oper_i_alu_mul0__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 13 \oper_i_alu_mul0__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 2 \oper_i_alu_mul0__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 11 \oper_i_alu_mul0__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \oper_i_alu_mul0__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \oper_i_alu_mul0__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \oper_i_alu_mul0__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 7 \oper_i_alu_mul0__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 6 \oper_i_alu_mul0__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \oper_i_alu_mul0__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" + wire width 4 \prev_wr_go + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" + wire width 4 \prev_wr_go$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212" + wire \req_done + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire width 4 \req_l_q_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 4 \req_l_r_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 4 \req_l_r_req$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire width 4 \req_l_s_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire width 4 \req_l_s_req$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226" + wire \reset + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:229" + wire width 3 \reset_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:228" + wire width 4 \reset_w + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire \rok_l_q_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \rok_l_r_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \rok_l_r_rdok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire \rok_l_s_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire 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\A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_issue_i + connect \B \cu_go_die_i + connect \Y $or$libresoc.v:154682$7673_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" + cell $or $or$libresoc.v:154684$7675 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \cu_wr__go_i + connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } + connect \Y $or$libresoc.v:154684$7675_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" + cell $or $or$libresoc.v:154685$7676 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \cu_rd__go_i + connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } + connect \Y $or$libresoc.v:154685$7676_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" + cell $or $or$libresoc.v:154688$7679 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \reset_w + connect \B \prev_wr_go + connect \Y $or$libresoc.v:154688$7679_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $or $or$libresoc.v:154694$7685 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \$5 + connect \B \cu_rd__go_i + connect \Y $or$libresoc.v:154694$7685_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $reduce_and $reduce_and$libresoc.v:154700$7691 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \$7 + connect \Y $reduce_and$libresoc.v:154700$7691_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $reduce_or $reduce_or$libresoc.v:154665$7656 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \$26 + connect \Y $reduce_or$libresoc.v:154665$7656_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $reduce_or $reduce_or$libresoc.v:154669$7660 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \cu_wr__go_i + connect \Y $reduce_or$libresoc.v:154669$7660_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $reduce_or $reduce_or$libresoc.v:154670$7661 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \prev_wr_go + connect \Y $reduce_or$libresoc.v:154670$7661_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" + cell $mux $ternary$libresoc.v:154693$7684 + parameter \WIDTH 1 + connect \A \src_l_q_src [1] + connect \B \opc_l_q_opc + connect \S \alu_mul0_mul_op__imm_data__ok + connect \Y $ternary$libresoc.v:154693$7684_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" + cell $mux $ternary$libresoc.v:154695$7686 + parameter \WIDTH 64 + connect \A \src2_i + connect \B \alu_mul0_mul_op__imm_data__data + connect \S \alu_mul0_mul_op__imm_data__ok + connect \Y $ternary$libresoc.v:154695$7686_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" + cell $mux $ternary$libresoc.v:154696$7687 + parameter \WIDTH 64 + connect \A \src_r0 + connect \B \src1_i + connect \S \src_l_q_src [0] + connect \Y $ternary$libresoc.v:154696$7687_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" + cell $mux $ternary$libresoc.v:154697$7688 + parameter \WIDTH 64 + connect \A \src_r1 + connect \B \src_or_imm + connect \S \src_sel + connect \Y $ternary$libresoc.v:154697$7688_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" + cell $mux $ternary$libresoc.v:154698$7689 + parameter \WIDTH 1 + connect \A \src_r2 + connect \B \src3_i + connect \S \src_l_q_src [2] + connect \Y $ternary$libresoc.v:154698$7689_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:154782.15-154788.4" + cell \alu_l$107 \alu_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_alu \alu_l_q_alu + connect \r_alu \alu_l_r_alu + connect \s_alu \alu_l_s_alu + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:154789.12-154819.4" + cell \alu_mul0 \alu_mul0 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cr_a \alu_mul0_cr_a + connect \cr_a_ok \cr_a_ok + connect \mul_op__fn_unit \alu_mul0_mul_op__fn_unit + connect \mul_op__imm_data__data \alu_mul0_mul_op__imm_data__data + connect \mul_op__imm_data__ok \alu_mul0_mul_op__imm_data__ok + connect \mul_op__insn \alu_mul0_mul_op__insn + connect \mul_op__insn_type \alu_mul0_mul_op__insn_type + connect \mul_op__is_32bit \alu_mul0_mul_op__is_32bit + connect \mul_op__is_signed \alu_mul0_mul_op__is_signed + connect \mul_op__oe__oe \alu_mul0_mul_op__oe__oe + connect \mul_op__oe__ok \alu_mul0_mul_op__oe__ok + connect \mul_op__rc__ok \alu_mul0_mul_op__rc__ok + connect \mul_op__rc__rc \alu_mul0_mul_op__rc__rc + connect \mul_op__write_cr0 \alu_mul0_mul_op__write_cr0 + connect \n_ready_i \alu_mul0_n_ready_i + connect \n_valid_o \alu_mul0_n_valid_o + connect \o \alu_mul0_o + connect \o_ok \o_ok + connect \p_ready_o \alu_mul0_p_ready_o + connect \p_valid_i \alu_mul0_p_valid_i + connect \ra \alu_mul0_ra + connect \rb \alu_mul0_rb + connect \xer_ov \alu_mul0_xer_ov + connect \xer_ov_ok \xer_ov_ok + connect \xer_so \alu_mul0_xer_so + connect \xer_so$1 \alu_mul0_xer_so$1 + connect \xer_so_ok \xer_so_ok + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:154820.16-154826.4" + cell \alui_l$106 \alui_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_alui \alui_l_q_alui + connect \r_alui \alui_l_r_alui + connect \s_alui \alui_l_s_alui + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:154827.15-154833.4" + cell \opc_l$102 \opc_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_opc \opc_l_q_opc + connect \r_opc \opc_l_r_opc + connect \s_opc \opc_l_s_opc + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:154834.15-154840.4" + cell \req_l$103 \req_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_req \req_l_q_req + connect \r_req \req_l_r_req + connect \s_req \req_l_s_req + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:154841.15-154847.4" + cell \rok_l$105 \rok_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_rdok \rok_l_q_rdok + connect \r_rdok \rok_l_r_rdok + connect \s_rdok \rok_l_s_rdok + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:154848.15-154853.4" + cell \rst_l$104 \rst_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \r_rst \rst_l_r_rst + connect \s_rst \rst_l_s_rst + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:154854.15-154860.4" + cell \src_l$101 \src_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_src \src_l_q_src + connect \r_src \src_l_r_src + connect \s_src \src_l_s_src + end + attribute \src "libresoc.v:154053.7-154053.20" + process $proc$libresoc.v:154053$7851 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:154177.7-154177.24" + process $proc$libresoc.v:154177$7852 + assign { } { } + assign $1\all_rd_dly[0:0] 1'0 + sync always + sync init + update \all_rd_dly $1\all_rd_dly[0:0] + end + attribute \src "libresoc.v:154187.7-154187.26" + process $proc$libresoc.v:154187$7853 + assign { } { } + assign $1\alu_done_dly[0:0] 1'0 + sync always + sync init + update \alu_done_dly $1\alu_done_dly[0:0] + end + attribute \src "libresoc.v:154195.7-154195.25" + process $proc$libresoc.v:154195$7854 + assign { } { } + assign $1\alu_l_r_alu[0:0] 1'1 + sync always + sync init + update \alu_l_r_alu $1\alu_l_r_alu[0:0] + end + attribute \src "libresoc.v:154217.14-154217.49" + process $proc$libresoc.v:154217$7855 + assign { } { } + assign $1\alu_mul0_mul_op__fn_unit[12:0] 13'0000000000000 + sync always + sync init + update \alu_mul0_mul_op__fn_unit $1\alu_mul0_mul_op__fn_unit[12:0] + end + attribute \src "libresoc.v:154221.14-154221.68" + process $proc$libresoc.v:154221$7856 + assign { } { } + assign $1\alu_mul0_mul_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \alu_mul0_mul_op__imm_data__data $1\alu_mul0_mul_op__imm_data__data[63:0] + end + attribute \src "libresoc.v:154225.7-154225.43" + process $proc$libresoc.v:154225$7857 + assign { } { } + assign $1\alu_mul0_mul_op__imm_data__ok[0:0] 1'0 + sync always + sync init + update \alu_mul0_mul_op__imm_data__ok $1\alu_mul0_mul_op__imm_data__ok[0:0] + end + attribute \src "libresoc.v:154229.14-154229.43" + process $proc$libresoc.v:154229$7858 + assign { } { } + assign $1\alu_mul0_mul_op__insn[31:0] 0 + sync always + sync init + update \alu_mul0_mul_op__insn $1\alu_mul0_mul_op__insn[31:0] + end + attribute \src "libresoc.v:154307.13-154307.47" + process $proc$libresoc.v:154307$7859 + assign { } { } + assign $1\alu_mul0_mul_op__insn_type[6:0] 7'0000000 + sync always + sync init + update \alu_mul0_mul_op__insn_type $1\alu_mul0_mul_op__insn_type[6:0] + end + attribute \src "libresoc.v:154311.7-154311.39" + process $proc$libresoc.v:154311$7860 + assign { } { } + assign $1\alu_mul0_mul_op__is_32bit[0:0] 1'0 + sync always + sync init + update \alu_mul0_mul_op__is_32bit $1\alu_mul0_mul_op__is_32bit[0:0] + end + attribute \src "libresoc.v:154315.7-154315.40" + process $proc$libresoc.v:154315$7861 + assign { } { } + assign $1\alu_mul0_mul_op__is_signed[0:0] 1'0 + sync always + sync init + update \alu_mul0_mul_op__is_signed $1\alu_mul0_mul_op__is_signed[0:0] + end + attribute \src "libresoc.v:154319.7-154319.37" + process $proc$libresoc.v:154319$7862 + assign { } { } + assign $1\alu_mul0_mul_op__oe__oe[0:0] 1'0 + sync always + sync init + update \alu_mul0_mul_op__oe__oe $1\alu_mul0_mul_op__oe__oe[0:0] + end + attribute \src "libresoc.v:154323.7-154323.37" + process $proc$libresoc.v:154323$7863 + assign { } { } + assign $1\alu_mul0_mul_op__oe__ok[0:0] 1'0 + sync always + sync init + update \alu_mul0_mul_op__oe__ok $1\alu_mul0_mul_op__oe__ok[0:0] + end + attribute \src "libresoc.v:154327.7-154327.37" + process $proc$libresoc.v:154327$7864 + assign { } { } + assign $1\alu_mul0_mul_op__rc__ok[0:0] 1'0 + sync always + sync init + update \alu_mul0_mul_op__rc__ok $1\alu_mul0_mul_op__rc__ok[0:0] + end + attribute \src "libresoc.v:154331.7-154331.37" + process $proc$libresoc.v:154331$7865 + assign { } { } + assign $1\alu_mul0_mul_op__rc__rc[0:0] 1'0 + sync always + sync init + update \alu_mul0_mul_op__rc__rc $1\alu_mul0_mul_op__rc__rc[0:0] + end + attribute \src "libresoc.v:154335.7-154335.40" + process $proc$libresoc.v:154335$7866 + assign { } { } + assign $1\alu_mul0_mul_op__write_cr0[0:0] 1'0 + sync always + sync init + update \alu_mul0_mul_op__write_cr0 $1\alu_mul0_mul_op__write_cr0[0:0] + end + attribute \src "libresoc.v:154365.7-154365.27" + process $proc$libresoc.v:154365$7867 + assign { } { } + assign $1\alui_l_r_alui[0:0] 1'1 + sync always + sync init + update \alui_l_r_alui $1\alui_l_r_alui[0:0] + end + attribute \src "libresoc.v:154399.14-154399.47" + process $proc$libresoc.v:154399$7868 + assign { } { } + assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \data_r0__o $1\data_r0__o[63:0] + end + attribute \src "libresoc.v:154403.7-154403.27" + process $proc$libresoc.v:154403$7869 + assign { } { } + assign $1\data_r0__o_ok[0:0] 1'0 + sync always + sync init + update \data_r0__o_ok $1\data_r0__o_ok[0:0] + end + attribute \src "libresoc.v:154407.13-154407.33" + process $proc$libresoc.v:154407$7870 + assign { } { } + assign $1\data_r1__cr_a[3:0] 4'0000 + sync always + sync init + update \data_r1__cr_a $1\data_r1__cr_a[3:0] + end + attribute \src "libresoc.v:154411.7-154411.30" + process $proc$libresoc.v:154411$7871 + assign { } { } + assign $1\data_r1__cr_a_ok[0:0] 1'0 + sync always + sync init + update \data_r1__cr_a_ok $1\data_r1__cr_a_ok[0:0] + end + attribute \src "libresoc.v:154415.13-154415.35" + process $proc$libresoc.v:154415$7872 + assign { } { } + assign $1\data_r2__xer_ov[1:0] 2'00 + sync always + sync init + update \data_r2__xer_ov $1\data_r2__xer_ov[1:0] + end + attribute \src "libresoc.v:154419.7-154419.32" + process $proc$libresoc.v:154419$7873 + assign { } { } + assign $1\data_r2__xer_ov_ok[0:0] 1'0 + sync always + sync init + update \data_r2__xer_ov_ok $1\data_r2__xer_ov_ok[0:0] + end + attribute \src "libresoc.v:154423.7-154423.29" + process $proc$libresoc.v:154423$7874 + assign { } { } + assign $1\data_r3__xer_so[0:0] 1'0 + sync always + sync init + update \data_r3__xer_so $1\data_r3__xer_so[0:0] + end + attribute \src "libresoc.v:154427.7-154427.32" + process $proc$libresoc.v:154427$7875 + assign { } { } + assign $1\data_r3__xer_so_ok[0:0] 1'0 + sync always + sync init + update \data_r3__xer_so_ok $1\data_r3__xer_so_ok[0:0] + end + attribute \src "libresoc.v:154447.7-154447.25" + process $proc$libresoc.v:154447$7876 + assign { } { } + assign $1\opc_l_r_opc[0:0] 1'1 + sync always + sync init + update \opc_l_r_opc $1\opc_l_r_opc[0:0] + end + attribute \src "libresoc.v:154451.7-154451.25" + process $proc$libresoc.v:154451$7877 + assign { } { } + assign $1\opc_l_s_opc[0:0] 1'0 + sync always + sync init + update \opc_l_s_opc $1\opc_l_s_opc[0:0] + end + attribute \src "libresoc.v:154567.13-154567.30" + process $proc$libresoc.v:154567$7878 + assign { } { } + assign $1\prev_wr_go[3:0] 4'0000 + sync always + sync init + update \prev_wr_go $1\prev_wr_go[3:0] + end + attribute \src "libresoc.v:154575.13-154575.31" + process $proc$libresoc.v:154575$7879 + assign { } { } + assign $1\req_l_r_req[3:0] 4'1111 + sync always + sync init + update \req_l_r_req $1\req_l_r_req[3:0] + end + attribute \src "libresoc.v:154579.13-154579.31" + process $proc$libresoc.v:154579$7880 + assign { } { } + assign $1\req_l_s_req[3:0] 4'0000 + sync always + sync init + update \req_l_s_req $1\req_l_s_req[3:0] + end + attribute \src "libresoc.v:154591.7-154591.26" + process $proc$libresoc.v:154591$7881 + assign { } { } + assign $1\rok_l_r_rdok[0:0] 1'1 + sync always + sync init + update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] + end + attribute \src "libresoc.v:154595.7-154595.26" + process $proc$libresoc.v:154595$7882 + assign { } { } + assign $1\rok_l_s_rdok[0:0] 1'0 + sync always + sync init + update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] + end + attribute \src "libresoc.v:154599.7-154599.25" + process $proc$libresoc.v:154599$7883 + assign { } { } + assign $1\rst_l_r_rst[0:0] 1'1 + sync always + sync init + update \rst_l_r_rst $1\rst_l_r_rst[0:0] + end + attribute \src "libresoc.v:154603.7-154603.25" + process $proc$libresoc.v:154603$7884 + assign { } { } + assign $1\rst_l_s_rst[0:0] 1'0 + sync always + sync init + update \rst_l_s_rst $1\rst_l_s_rst[0:0] + end + attribute \src "libresoc.v:154617.13-154617.31" + process $proc$libresoc.v:154617$7885 + assign { } { } + assign $1\src_l_r_src[2:0] 3'111 + sync always + sync init + update \src_l_r_src $1\src_l_r_src[2:0] + end + attribute \src "libresoc.v:154621.13-154621.31" + process $proc$libresoc.v:154621$7886 + assign { } { } + assign $1\src_l_s_src[2:0] 3'000 + sync always + sync init + update \src_l_s_src $1\src_l_s_src[2:0] + end + attribute \src "libresoc.v:154627.14-154627.43" + process $proc$libresoc.v:154627$7887 + assign { } { } + assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \src_r0 $1\src_r0[63:0] + end + attribute \src "libresoc.v:154631.14-154631.43" + process $proc$libresoc.v:154631$7888 + assign { } { } + assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \src_r1 $1\src_r1[63:0] + end + attribute \src "libresoc.v:154635.7-154635.20" + process $proc$libresoc.v:154635$7889 + assign { } { } + assign $1\src_r2[0:0] 1'0 + sync always + sync init + update \src_r2 $1\src_r2[0:0] + end + attribute \src "libresoc.v:154706.3-154707.39" + process $proc$libresoc.v:154706$7697 + assign { } { } + assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next + sync posedge \coresync_clk + update \alu_l_r_alu $0\alu_l_r_alu[0:0] + end + attribute \src "libresoc.v:154708.3-154709.43" + process $proc$libresoc.v:154708$7698 + assign { } { } + assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next + sync posedge \coresync_clk + update \alui_l_r_alui $0\alui_l_r_alui[0:0] + end + attribute \src "libresoc.v:154710.3-154711.29" + process $proc$libresoc.v:154710$7699 + assign { } { } + assign $0\src_r2[0:0] \src_r2$next + sync posedge \coresync_clk + update \src_r2 $0\src_r2[0:0] + end + attribute \src "libresoc.v:154712.3-154713.29" + process $proc$libresoc.v:154712$7700 + assign { } { } + assign $0\src_r1[63:0] \src_r1$next + sync posedge \coresync_clk + update \src_r1 $0\src_r1[63:0] + end + attribute \src "libresoc.v:154714.3-154715.29" + process $proc$libresoc.v:154714$7701 + assign { } { } + assign $0\src_r0[63:0] \src_r0$next + sync posedge \coresync_clk + update \src_r0 $0\src_r0[63:0] + end + attribute \src "libresoc.v:154716.3-154717.47" + process $proc$libresoc.v:154716$7702 + assign { } { } + assign $0\data_r3__xer_so[0:0] \data_r3__xer_so$next + sync posedge \coresync_clk + update \data_r3__xer_so $0\data_r3__xer_so[0:0] + end + attribute \src "libresoc.v:154718.3-154719.53" + process $proc$libresoc.v:154718$7703 + assign { } { } + assign $0\data_r3__xer_so_ok[0:0] \data_r3__xer_so_ok$next + sync posedge \coresync_clk + update \data_r3__xer_so_ok $0\data_r3__xer_so_ok[0:0] + end + attribute \src "libresoc.v:154720.3-154721.47" + process $proc$libresoc.v:154720$7704 + assign { } { } + assign $0\data_r2__xer_ov[1:0] \data_r2__xer_ov$next + sync posedge \coresync_clk + update \data_r2__xer_ov $0\data_r2__xer_ov[1:0] + end + attribute \src "libresoc.v:154722.3-154723.53" + process $proc$libresoc.v:154722$7705 + assign { } { } + assign $0\data_r2__xer_ov_ok[0:0] \data_r2__xer_ov_ok$next + sync posedge \coresync_clk + update \data_r2__xer_ov_ok $0\data_r2__xer_ov_ok[0:0] + end + attribute \src "libresoc.v:154724.3-154725.43" + process $proc$libresoc.v:154724$7706 + assign { } { } + assign $0\data_r1__cr_a[3:0] \data_r1__cr_a$next + sync posedge \coresync_clk + update \data_r1__cr_a $0\data_r1__cr_a[3:0] + end + attribute \src "libresoc.v:154726.3-154727.49" + process $proc$libresoc.v:154726$7707 + assign { } { } + assign $0\data_r1__cr_a_ok[0:0] \data_r1__cr_a_ok$next + sync posedge \coresync_clk + update \data_r1__cr_a_ok $0\data_r1__cr_a_ok[0:0] + end + attribute \src "libresoc.v:154728.3-154729.37" + process $proc$libresoc.v:154728$7708 + assign { } { } + assign $0\data_r0__o[63:0] \data_r0__o$next + sync posedge \coresync_clk + update \data_r0__o $0\data_r0__o[63:0] + end + attribute \src "libresoc.v:154730.3-154731.43" + process $proc$libresoc.v:154730$7709 + assign { } { } + assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next + sync posedge \coresync_clk + update \data_r0__o_ok $0\data_r0__o_ok[0:0] + end + attribute \src "libresoc.v:154732.3-154733.69" + process $proc$libresoc.v:154732$7710 + assign { } { } + assign $0\alu_mul0_mul_op__insn_type[6:0] \alu_mul0_mul_op__insn_type$next + sync posedge \coresync_clk + update \alu_mul0_mul_op__insn_type $0\alu_mul0_mul_op__insn_type[6:0] + end + attribute \src "libresoc.v:154734.3-154735.65" + process $proc$libresoc.v:154734$7711 + assign { } { } + assign $0\alu_mul0_mul_op__fn_unit[12:0] \alu_mul0_mul_op__fn_unit$next + sync posedge \coresync_clk + update \alu_mul0_mul_op__fn_unit $0\alu_mul0_mul_op__fn_unit[12:0] + end + attribute \src "libresoc.v:154736.3-154737.79" + process $proc$libresoc.v:154736$7712 + assign { } { } + assign $0\alu_mul0_mul_op__imm_data__data[63:0] \alu_mul0_mul_op__imm_data__data$next + sync posedge \coresync_clk + update \alu_mul0_mul_op__imm_data__data $0\alu_mul0_mul_op__imm_data__data[63:0] + end + attribute \src "libresoc.v:154738.3-154739.75" + process $proc$libresoc.v:154738$7713 + assign { } { } + assign $0\alu_mul0_mul_op__imm_data__ok[0:0] \alu_mul0_mul_op__imm_data__ok$next + sync posedge \coresync_clk + update \alu_mul0_mul_op__imm_data__ok $0\alu_mul0_mul_op__imm_data__ok[0:0] + end + attribute \src "libresoc.v:154740.3-154741.63" + process $proc$libresoc.v:154740$7714 + assign { } { } + assign $0\alu_mul0_mul_op__rc__rc[0:0] \alu_mul0_mul_op__rc__rc$next + sync posedge \coresync_clk + update \alu_mul0_mul_op__rc__rc $0\alu_mul0_mul_op__rc__rc[0:0] + end + attribute \src "libresoc.v:154742.3-154743.63" + process $proc$libresoc.v:154742$7715 + assign { } { } + assign $0\alu_mul0_mul_op__rc__ok[0:0] \alu_mul0_mul_op__rc__ok$next + sync posedge \coresync_clk + update \alu_mul0_mul_op__rc__ok $0\alu_mul0_mul_op__rc__ok[0:0] + end + attribute \src "libresoc.v:154744.3-154745.63" + process $proc$libresoc.v:154744$7716 + assign { } { } + assign $0\alu_mul0_mul_op__oe__oe[0:0] \alu_mul0_mul_op__oe__oe$next + sync posedge \coresync_clk + update \alu_mul0_mul_op__oe__oe $0\alu_mul0_mul_op__oe__oe[0:0] + end + attribute \src "libresoc.v:154746.3-154747.63" + process $proc$libresoc.v:154746$7717 + assign { } { } + assign $0\alu_mul0_mul_op__oe__ok[0:0] \alu_mul0_mul_op__oe__ok$next + sync posedge \coresync_clk + update \alu_mul0_mul_op__oe__ok $0\alu_mul0_mul_op__oe__ok[0:0] + end + attribute \src "libresoc.v:154748.3-154749.69" + process $proc$libresoc.v:154748$7718 + assign { } { } + assign $0\alu_mul0_mul_op__write_cr0[0:0] \alu_mul0_mul_op__write_cr0$next + sync posedge \coresync_clk + update \alu_mul0_mul_op__write_cr0 $0\alu_mul0_mul_op__write_cr0[0:0] + end + attribute \src "libresoc.v:154750.3-154751.67" + process $proc$libresoc.v:154750$7719 + assign { } { } + assign $0\alu_mul0_mul_op__is_32bit[0:0] \alu_mul0_mul_op__is_32bit$next + sync posedge \coresync_clk + update \alu_mul0_mul_op__is_32bit $0\alu_mul0_mul_op__is_32bit[0:0] + end + attribute \src "libresoc.v:154752.3-154753.69" + process $proc$libresoc.v:154752$7720 + assign { } { } + assign $0\alu_mul0_mul_op__is_signed[0:0] \alu_mul0_mul_op__is_signed$next + sync posedge \coresync_clk + update \alu_mul0_mul_op__is_signed $0\alu_mul0_mul_op__is_signed[0:0] + end + attribute \src "libresoc.v:154754.3-154755.59" + process $proc$libresoc.v:154754$7721 + assign { } { } + assign $0\alu_mul0_mul_op__insn[31:0] \alu_mul0_mul_op__insn$next + sync posedge \coresync_clk + update \alu_mul0_mul_op__insn $0\alu_mul0_mul_op__insn[31:0] + end + attribute \src "libresoc.v:154756.3-154757.39" + process $proc$libresoc.v:154756$7722 + assign { } { } + assign $0\req_l_r_req[3:0] \req_l_r_req$next + sync posedge \coresync_clk + update \req_l_r_req $0\req_l_r_req[3:0] + end + attribute \src "libresoc.v:154758.3-154759.39" + process $proc$libresoc.v:154758$7723 + assign { } { } + assign $0\req_l_s_req[3:0] \req_l_s_req$next + sync posedge \coresync_clk + update \req_l_s_req $0\req_l_s_req[3:0] + end + attribute \src "libresoc.v:154760.3-154761.39" + process $proc$libresoc.v:154760$7724 + assign { } { } + assign $0\src_l_r_src[2:0] \src_l_r_src$next + sync posedge \coresync_clk + update \src_l_r_src $0\src_l_r_src[2:0] + end + attribute \src "libresoc.v:154762.3-154763.39" + process $proc$libresoc.v:154762$7725 + assign { } { } + assign $0\src_l_s_src[2:0] \src_l_s_src$next + sync posedge \coresync_clk + update \src_l_s_src $0\src_l_s_src[2:0] + end + attribute \src "libresoc.v:154764.3-154765.39" + process $proc$libresoc.v:154764$7726 + assign { } { } + assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next + sync posedge \coresync_clk + update \opc_l_r_opc $0\opc_l_r_opc[0:0] + end + attribute \src "libresoc.v:154766.3-154767.39" + process $proc$libresoc.v:154766$7727 + assign { } { } + assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next + sync posedge \coresync_clk + update \opc_l_s_opc $0\opc_l_s_opc[0:0] + end + attribute \src "libresoc.v:154768.3-154769.39" + process $proc$libresoc.v:154768$7728 + assign { } { } + assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next + sync posedge \coresync_clk + update \rst_l_r_rst $0\rst_l_r_rst[0:0] + end + attribute \src "libresoc.v:154770.3-154771.39" + process $proc$libresoc.v:154770$7729 + assign { } { } + assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next + sync posedge \coresync_clk + update \rst_l_s_rst $0\rst_l_s_rst[0:0] + end + attribute \src "libresoc.v:154772.3-154773.41" + process $proc$libresoc.v:154772$7730 + assign { } { } + assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next + sync posedge \coresync_clk + update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] + end + attribute \src "libresoc.v:154774.3-154775.41" + process $proc$libresoc.v:154774$7731 + assign { } { } + assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next + sync posedge \coresync_clk + update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] + end + attribute \src "libresoc.v:154776.3-154777.37" + process $proc$libresoc.v:154776$7732 + assign { } { } + assign $0\prev_wr_go[3:0] \prev_wr_go$next + sync posedge \coresync_clk + update \prev_wr_go $0\prev_wr_go[3:0] + end + attribute \src "libresoc.v:154778.3-154779.40" + process $proc$libresoc.v:154778$7733 + assign { } { } + assign $0\alu_done_dly[0:0] \alu_mul0_n_valid_o + sync posedge \coresync_clk + update \alu_done_dly $0\alu_done_dly[0:0] + end + attribute \src "libresoc.v:154780.3-154781.25" + process $proc$libresoc.v:154780$7734 + assign { } { } + assign $0\all_rd_dly[0:0] \$10 + sync posedge \coresync_clk + update \all_rd_dly $0\all_rd_dly[0:0] + end + attribute \src "libresoc.v:154861.3-154870.6" + process $proc$libresoc.v:154861$7735 + assign { } { } + assign { } { } + assign $0\req_done[0:0] $1\req_done[0:0] + attribute \src "libresoc.v:154862.5-154862.29" + switch \initial + attribute \src "libresoc.v:154862.9-154862.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + switch \$54 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\req_done[0:0] 1'1 + case + assign $1\req_done[0:0] \$46 + end + sync always + update \req_done $0\req_done[0:0] + end + attribute \src "libresoc.v:154871.3-154879.6" + process $proc$libresoc.v:154871$7736 + assign { } { } + assign { } { } + assign $0\rok_l_s_rdok$next[0:0]$7737 $1\rok_l_s_rdok$next[0:0]$7738 + attribute \src "libresoc.v:154872.5-154872.29" + switch \initial + attribute \src "libresoc.v:154872.9-154872.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rok_l_s_rdok$next[0:0]$7738 1'0 + case + assign $1\rok_l_s_rdok$next[0:0]$7738 \cu_issue_i + end + sync always + update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$7737 + end + attribute \src "libresoc.v:154880.3-154888.6" + process $proc$libresoc.v:154880$7739 + assign { } { } + assign { } { } + assign $0\rok_l_r_rdok$next[0:0]$7740 $1\rok_l_r_rdok$next[0:0]$7741 + attribute \src "libresoc.v:154881.5-154881.29" + switch \initial + attribute \src "libresoc.v:154881.9-154881.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rok_l_r_rdok$next[0:0]$7741 1'1 + case + assign $1\rok_l_r_rdok$next[0:0]$7741 \$64 + end + sync always + update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$7740 + end + attribute \src "libresoc.v:154889.3-154897.6" + process $proc$libresoc.v:154889$7742 + assign { } { } + assign { } { } + assign $0\rst_l_s_rst$next[0:0]$7743 $1\rst_l_s_rst$next[0:0]$7744 + attribute \src "libresoc.v:154890.5-154890.29" + switch \initial + attribute \src "libresoc.v:154890.9-154890.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rst_l_s_rst$next[0:0]$7744 1'0 + case + assign $1\rst_l_s_rst$next[0:0]$7744 \all_rd + end + sync always + update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$7743 + end + attribute \src "libresoc.v:154898.3-154906.6" + process $proc$libresoc.v:154898$7745 + assign { } { } + assign { } { } + assign $0\rst_l_r_rst$next[0:0]$7746 $1\rst_l_r_rst$next[0:0]$7747 + attribute \src "libresoc.v:154899.5-154899.29" + switch \initial + attribute \src "libresoc.v:154899.9-154899.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rst_l_r_rst$next[0:0]$7747 1'1 + case + assign $1\rst_l_r_rst$next[0:0]$7747 \rst_r + end + sync always + update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$7746 + end + attribute \src "libresoc.v:154907.3-154915.6" + process $proc$libresoc.v:154907$7748 + assign { } { } + assign { } { } + assign $0\opc_l_s_opc$next[0:0]$7749 $1\opc_l_s_opc$next[0:0]$7750 + attribute \src "libresoc.v:154908.5-154908.29" + switch \initial + attribute \src "libresoc.v:154908.9-154908.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\opc_l_s_opc$next[0:0]$7750 1'0 + case + assign $1\opc_l_s_opc$next[0:0]$7750 \cu_issue_i + end + sync always + update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$7749 + end + attribute \src "libresoc.v:154916.3-154924.6" + process $proc$libresoc.v:154916$7751 + assign { } { } + assign { } { } + assign $0\opc_l_r_opc$next[0:0]$7752 $1\opc_l_r_opc$next[0:0]$7753 + attribute \src "libresoc.v:154917.5-154917.29" + switch \initial + attribute \src "libresoc.v:154917.9-154917.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\opc_l_r_opc$next[0:0]$7753 1'1 + case + assign $1\opc_l_r_opc$next[0:0]$7753 \req_done + end + sync always + update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$7752 + end + attribute \src "libresoc.v:154925.3-154933.6" + process $proc$libresoc.v:154925$7754 + assign { } { } + assign { } { } + assign $0\src_l_s_src$next[2:0]$7755 $1\src_l_s_src$next[2:0]$7756 + attribute \src "libresoc.v:154926.5-154926.29" + switch \initial + attribute \src "libresoc.v:154926.9-154926.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_l_s_src$next[2:0]$7756 3'000 + case + assign $1\src_l_s_src$next[2:0]$7756 { \cu_issue_i \cu_issue_i \cu_issue_i } + end + sync always + update \src_l_s_src$next $0\src_l_s_src$next[2:0]$7755 + end + attribute \src "libresoc.v:154934.3-154942.6" + process $proc$libresoc.v:154934$7757 + assign { } { } + assign { } { } + assign $0\src_l_r_src$next[2:0]$7758 $1\src_l_r_src$next[2:0]$7759 + attribute \src "libresoc.v:154935.5-154935.29" + switch \initial + attribute \src "libresoc.v:154935.9-154935.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_l_r_src$next[2:0]$7759 3'111 + case + assign $1\src_l_r_src$next[2:0]$7759 \reset_r + end + sync always + update \src_l_r_src$next $0\src_l_r_src$next[2:0]$7758 + end + attribute \src "libresoc.v:154943.3-154951.6" + process $proc$libresoc.v:154943$7760 + assign { } { } + assign { } { } + assign $0\req_l_s_req$next[3:0]$7761 $1\req_l_s_req$next[3:0]$7762 + attribute \src "libresoc.v:154944.5-154944.29" + switch \initial + attribute \src "libresoc.v:154944.9-154944.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\req_l_s_req$next[3:0]$7762 4'0000 + case + assign $1\req_l_s_req$next[3:0]$7762 \$66 + end + sync always + update \req_l_s_req$next $0\req_l_s_req$next[3:0]$7761 + end + attribute \src "libresoc.v:154952.3-154960.6" + process $proc$libresoc.v:154952$7763 + assign { } { } + assign { } { } + assign $0\req_l_r_req$next[3:0]$7764 $1\req_l_r_req$next[3:0]$7765 + attribute \src "libresoc.v:154953.5-154953.29" + switch \initial + attribute \src "libresoc.v:154953.9-154953.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\req_l_r_req$next[3:0]$7765 4'1111 + case + assign $1\req_l_r_req$next[3:0]$7765 \$68 + end + sync always + update \req_l_r_req$next $0\req_l_r_req$next[3:0]$7764 + end + attribute \src "libresoc.v:154961.3-154993.6" + process $proc$libresoc.v:154961$7766 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\alu_mul0_mul_op__fn_unit$next[12:0]$7767 $1\alu_mul0_mul_op__fn_unit$next[12:0]$7779 + assign { } { } + assign { } { } + assign $0\alu_mul0_mul_op__insn$next[31:0]$7770 $1\alu_mul0_mul_op__insn$next[31:0]$7782 + assign $0\alu_mul0_mul_op__insn_type$next[6:0]$7771 $1\alu_mul0_mul_op__insn_type$next[6:0]$7783 + assign $0\alu_mul0_mul_op__is_32bit$next[0:0]$7772 $1\alu_mul0_mul_op__is_32bit$next[0:0]$7784 + assign $0\alu_mul0_mul_op__is_signed$next[0:0]$7773 $1\alu_mul0_mul_op__is_signed$next[0:0]$7785 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\alu_mul0_mul_op__write_cr0$next[0:0]$7778 $1\alu_mul0_mul_op__write_cr0$next[0:0]$7790 + assign $0\alu_mul0_mul_op__imm_data__data$next[63:0]$7768 $2\alu_mul0_mul_op__imm_data__data$next[63:0]$7791 + assign $0\alu_mul0_mul_op__imm_data__ok$next[0:0]$7769 $2\alu_mul0_mul_op__imm_data__ok$next[0:0]$7792 + assign $0\alu_mul0_mul_op__oe__oe$next[0:0]$7774 $2\alu_mul0_mul_op__oe__oe$next[0:0]$7793 + assign $0\alu_mul0_mul_op__oe__ok$next[0:0]$7775 $2\alu_mul0_mul_op__oe__ok$next[0:0]$7794 + assign $0\alu_mul0_mul_op__rc__ok$next[0:0]$7776 $2\alu_mul0_mul_op__rc__ok$next[0:0]$7795 + assign $0\alu_mul0_mul_op__rc__rc$next[0:0]$7777 $2\alu_mul0_mul_op__rc__rc$next[0:0]$7796 + attribute \src "libresoc.v:154962.5-154962.29" + switch \initial + attribute \src "libresoc.v:154962.9-154962.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\alu_mul0_mul_op__insn$next[31:0]$7782 $1\alu_mul0_mul_op__is_signed$next[0:0]$7785 $1\alu_mul0_mul_op__is_32bit$next[0:0]$7784 $1\alu_mul0_mul_op__write_cr0$next[0:0]$7790 $1\alu_mul0_mul_op__oe__ok$next[0:0]$7787 $1\alu_mul0_mul_op__oe__oe$next[0:0]$7786 $1\alu_mul0_mul_op__rc__ok$next[0:0]$7788 $1\alu_mul0_mul_op__rc__rc$next[0:0]$7789 $1\alu_mul0_mul_op__imm_data__ok$next[0:0]$7781 $1\alu_mul0_mul_op__imm_data__data$next[63:0]$7780 $1\alu_mul0_mul_op__fn_unit$next[12:0]$7779 $1\alu_mul0_mul_op__insn_type$next[6:0]$7783 } { \oper_i_alu_mul0__insn \oper_i_alu_mul0__is_signed \oper_i_alu_mul0__is_32bit \oper_i_alu_mul0__write_cr0 \oper_i_alu_mul0__oe__ok \oper_i_alu_mul0__oe__oe \oper_i_alu_mul0__rc__ok \oper_i_alu_mul0__rc__rc \oper_i_alu_mul0__imm_data__ok \oper_i_alu_mul0__imm_data__data \oper_i_alu_mul0__fn_unit \oper_i_alu_mul0__insn_type } + case + assign $1\alu_mul0_mul_op__fn_unit$next[12:0]$7779 \alu_mul0_mul_op__fn_unit + assign $1\alu_mul0_mul_op__imm_data__data$next[63:0]$7780 \alu_mul0_mul_op__imm_data__data + assign $1\alu_mul0_mul_op__imm_data__ok$next[0:0]$7781 \alu_mul0_mul_op__imm_data__ok + assign $1\alu_mul0_mul_op__insn$next[31:0]$7782 \alu_mul0_mul_op__insn + assign $1\alu_mul0_mul_op__insn_type$next[6:0]$7783 \alu_mul0_mul_op__insn_type + assign $1\alu_mul0_mul_op__is_32bit$next[0:0]$7784 \alu_mul0_mul_op__is_32bit + assign $1\alu_mul0_mul_op__is_signed$next[0:0]$7785 \alu_mul0_mul_op__is_signed + assign $1\alu_mul0_mul_op__oe__oe$next[0:0]$7786 \alu_mul0_mul_op__oe__oe + assign $1\alu_mul0_mul_op__oe__ok$next[0:0]$7787 \alu_mul0_mul_op__oe__ok + assign $1\alu_mul0_mul_op__rc__ok$next[0:0]$7788 \alu_mul0_mul_op__rc__ok + assign $1\alu_mul0_mul_op__rc__rc$next[0:0]$7789 \alu_mul0_mul_op__rc__rc + assign $1\alu_mul0_mul_op__write_cr0$next[0:0]$7790 \alu_mul0_mul_op__write_cr0 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $2\alu_mul0_mul_op__imm_data__data$next[63:0]$7791 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\alu_mul0_mul_op__imm_data__ok$next[0:0]$7792 1'0 + assign $2\alu_mul0_mul_op__rc__rc$next[0:0]$7796 1'0 + assign $2\alu_mul0_mul_op__rc__ok$next[0:0]$7795 1'0 + assign $2\alu_mul0_mul_op__oe__oe$next[0:0]$7793 1'0 + assign $2\alu_mul0_mul_op__oe__ok$next[0:0]$7794 1'0 + case + assign $2\alu_mul0_mul_op__imm_data__data$next[63:0]$7791 $1\alu_mul0_mul_op__imm_data__data$next[63:0]$7780 + assign $2\alu_mul0_mul_op__imm_data__ok$next[0:0]$7792 $1\alu_mul0_mul_op__imm_data__ok$next[0:0]$7781 + assign $2\alu_mul0_mul_op__oe__oe$next[0:0]$7793 $1\alu_mul0_mul_op__oe__oe$next[0:0]$7786 + assign $2\alu_mul0_mul_op__oe__ok$next[0:0]$7794 $1\alu_mul0_mul_op__oe__ok$next[0:0]$7787 + assign $2\alu_mul0_mul_op__rc__ok$next[0:0]$7795 $1\alu_mul0_mul_op__rc__ok$next[0:0]$7788 + assign $2\alu_mul0_mul_op__rc__rc$next[0:0]$7796 $1\alu_mul0_mul_op__rc__rc$next[0:0]$7789 + end + sync always + update \alu_mul0_mul_op__fn_unit$next $0\alu_mul0_mul_op__fn_unit$next[12:0]$7767 + update \alu_mul0_mul_op__imm_data__data$next $0\alu_mul0_mul_op__imm_data__data$next[63:0]$7768 + update \alu_mul0_mul_op__imm_data__ok$next $0\alu_mul0_mul_op__imm_data__ok$next[0:0]$7769 + update \alu_mul0_mul_op__insn$next $0\alu_mul0_mul_op__insn$next[31:0]$7770 + update \alu_mul0_mul_op__insn_type$next $0\alu_mul0_mul_op__insn_type$next[6:0]$7771 + update \alu_mul0_mul_op__is_32bit$next $0\alu_mul0_mul_op__is_32bit$next[0:0]$7772 + update \alu_mul0_mul_op__is_signed$next $0\alu_mul0_mul_op__is_signed$next[0:0]$7773 + update \alu_mul0_mul_op__oe__oe$next $0\alu_mul0_mul_op__oe__oe$next[0:0]$7774 + update \alu_mul0_mul_op__oe__ok$next $0\alu_mul0_mul_op__oe__ok$next[0:0]$7775 + update \alu_mul0_mul_op__rc__ok$next $0\alu_mul0_mul_op__rc__ok$next[0:0]$7776 + update \alu_mul0_mul_op__rc__rc$next $0\alu_mul0_mul_op__rc__rc$next[0:0]$7777 + update \alu_mul0_mul_op__write_cr0$next $0\alu_mul0_mul_op__write_cr0$next[0:0]$7778 + end + attribute \src "libresoc.v:154994.3-155015.6" + process $proc$libresoc.v:154994$7797 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r0__o$next[63:0]$7798 $2\data_r0__o$next[63:0]$7802 + assign { } { } + assign $0\data_r0__o_ok$next[0:0]$7799 $3\data_r0__o_ok$next[0:0]$7804 + attribute \src "libresoc.v:154995.5-154995.29" + switch \initial + attribute \src "libresoc.v:154995.9-154995.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r0__o_ok$next[0:0]$7801 $1\data_r0__o$next[63:0]$7800 } { \o_ok \alu_mul0_o } + case + assign $1\data_r0__o$next[63:0]$7800 \data_r0__o + assign $1\data_r0__o_ok$next[0:0]$7801 \data_r0__o_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r0__o_ok$next[0:0]$7803 $2\data_r0__o$next[63:0]$7802 } 65'00000000000000000000000000000000000000000000000000000000000000000 + case + assign $2\data_r0__o$next[63:0]$7802 $1\data_r0__o$next[63:0]$7800 + assign $2\data_r0__o_ok$next[0:0]$7803 $1\data_r0__o_ok$next[0:0]$7801 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r0__o_ok$next[0:0]$7804 1'0 + case + assign $3\data_r0__o_ok$next[0:0]$7804 $2\data_r0__o_ok$next[0:0]$7803 + end + sync always + update \data_r0__o$next $0\data_r0__o$next[63:0]$7798 + update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$7799 + end + attribute \src "libresoc.v:155016.3-155037.6" + process $proc$libresoc.v:155016$7805 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r1__cr_a$next[3:0]$7806 $2\data_r1__cr_a$next[3:0]$7810 + assign { } { } + assign $0\data_r1__cr_a_ok$next[0:0]$7807 $3\data_r1__cr_a_ok$next[0:0]$7812 + attribute \src "libresoc.v:155017.5-155017.29" + switch \initial + attribute \src "libresoc.v:155017.9-155017.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r1__cr_a_ok$next[0:0]$7809 $1\data_r1__cr_a$next[3:0]$7808 } { \cr_a_ok \alu_mul0_cr_a } + case + assign $1\data_r1__cr_a$next[3:0]$7808 \data_r1__cr_a + assign $1\data_r1__cr_a_ok$next[0:0]$7809 \data_r1__cr_a_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r1__cr_a_ok$next[0:0]$7811 $2\data_r1__cr_a$next[3:0]$7810 } 5'00000 + case + assign $2\data_r1__cr_a$next[3:0]$7810 $1\data_r1__cr_a$next[3:0]$7808 + assign $2\data_r1__cr_a_ok$next[0:0]$7811 $1\data_r1__cr_a_ok$next[0:0]$7809 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r1__cr_a_ok$next[0:0]$7812 1'0 + case + assign $3\data_r1__cr_a_ok$next[0:0]$7812 $2\data_r1__cr_a_ok$next[0:0]$7811 + end + sync always + update \data_r1__cr_a$next $0\data_r1__cr_a$next[3:0]$7806 + update \data_r1__cr_a_ok$next $0\data_r1__cr_a_ok$next[0:0]$7807 + end + attribute \src "libresoc.v:155038.3-155059.6" + process $proc$libresoc.v:155038$7813 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r2__xer_ov$next[1:0]$7814 $2\data_r2__xer_ov$next[1:0]$7818 + assign { } { } + assign $0\data_r2__xer_ov_ok$next[0:0]$7815 $3\data_r2__xer_ov_ok$next[0:0]$7820 + attribute \src "libresoc.v:155039.5-155039.29" + switch \initial + attribute \src "libresoc.v:155039.9-155039.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r2__xer_ov_ok$next[0:0]$7817 $1\data_r2__xer_ov$next[1:0]$7816 } { \xer_ov_ok \alu_mul0_xer_ov } + case + assign $1\data_r2__xer_ov$next[1:0]$7816 \data_r2__xer_ov + assign $1\data_r2__xer_ov_ok$next[0:0]$7817 \data_r2__xer_ov_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r2__xer_ov_ok$next[0:0]$7819 $2\data_r2__xer_ov$next[1:0]$7818 } 3'000 + case + assign $2\data_r2__xer_ov$next[1:0]$7818 $1\data_r2__xer_ov$next[1:0]$7816 + assign $2\data_r2__xer_ov_ok$next[0:0]$7819 $1\data_r2__xer_ov_ok$next[0:0]$7817 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r2__xer_ov_ok$next[0:0]$7820 1'0 + case + assign $3\data_r2__xer_ov_ok$next[0:0]$7820 $2\data_r2__xer_ov_ok$next[0:0]$7819 + end + sync always + update \data_r2__xer_ov$next $0\data_r2__xer_ov$next[1:0]$7814 + update \data_r2__xer_ov_ok$next $0\data_r2__xer_ov_ok$next[0:0]$7815 + end + attribute \src "libresoc.v:155060.3-155081.6" + process $proc$libresoc.v:155060$7821 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r3__xer_so$next[0:0]$7822 $2\data_r3__xer_so$next[0:0]$7826 + assign { } { } + assign $0\data_r3__xer_so_ok$next[0:0]$7823 $3\data_r3__xer_so_ok$next[0:0]$7828 + attribute \src "libresoc.v:155061.5-155061.29" + switch \initial + attribute \src "libresoc.v:155061.9-155061.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r3__xer_so_ok$next[0:0]$7825 $1\data_r3__xer_so$next[0:0]$7824 } { \xer_so_ok \alu_mul0_xer_so } + case + assign $1\data_r3__xer_so$next[0:0]$7824 \data_r3__xer_so + assign $1\data_r3__xer_so_ok$next[0:0]$7825 \data_r3__xer_so_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r3__xer_so_ok$next[0:0]$7827 $2\data_r3__xer_so$next[0:0]$7826 } 2'00 + case + assign $2\data_r3__xer_so$next[0:0]$7826 $1\data_r3__xer_so$next[0:0]$7824 + assign $2\data_r3__xer_so_ok$next[0:0]$7827 $1\data_r3__xer_so_ok$next[0:0]$7825 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r3__xer_so_ok$next[0:0]$7828 1'0 + case + assign $3\data_r3__xer_so_ok$next[0:0]$7828 $2\data_r3__xer_so_ok$next[0:0]$7827 + end + sync always + update \data_r3__xer_so$next $0\data_r3__xer_so$next[0:0]$7822 + update \data_r3__xer_so_ok$next $0\data_r3__xer_so_ok$next[0:0]$7823 + end + attribute \src "libresoc.v:155082.3-155091.6" + process $proc$libresoc.v:155082$7829 + assign { } { } + assign { } { } + assign $0\src_r0$next[63:0]$7830 $1\src_r0$next[63:0]$7831 + attribute \src "libresoc.v:155083.5-155083.29" + switch \initial + attribute \src "libresoc.v:155083.9-155083.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" + switch \src_l_q_src [0] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r0$next[63:0]$7831 \src1_i + case + assign $1\src_r0$next[63:0]$7831 \src_r0 + end + sync always + update \src_r0$next $0\src_r0$next[63:0]$7830 + end + attribute \src "libresoc.v:155092.3-155101.6" + process $proc$libresoc.v:155092$7832 + assign { } { } + assign { } { } + assign $0\src_r1$next[63:0]$7833 $1\src_r1$next[63:0]$7834 + attribute \src "libresoc.v:155093.5-155093.29" + switch \initial + attribute \src "libresoc.v:155093.9-155093.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" + switch \src_sel + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r1$next[63:0]$7834 \src_or_imm + case + assign $1\src_r1$next[63:0]$7834 \src_r1 + end + sync always + update \src_r1$next $0\src_r1$next[63:0]$7833 + end + attribute \src "libresoc.v:155102.3-155111.6" + process $proc$libresoc.v:155102$7835 + assign { } { } + assign { } { } + assign $0\src_r2$next[0:0]$7836 $1\src_r2$next[0:0]$7837 + attribute \src "libresoc.v:155103.5-155103.29" + switch \initial + attribute \src "libresoc.v:155103.9-155103.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" + switch \src_l_q_src [2] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r2$next[0:0]$7837 \src3_i + case + assign $1\src_r2$next[0:0]$7837 \src_r2 + end + sync always + update \src_r2$next $0\src_r2$next[0:0]$7836 + end + attribute \src "libresoc.v:155112.3-155120.6" + process $proc$libresoc.v:155112$7838 + assign { } { } + assign { } { } + assign $0\alui_l_r_alui$next[0:0]$7839 $1\alui_l_r_alui$next[0:0]$7840 + attribute \src "libresoc.v:155113.5-155113.29" + switch \initial + attribute \src "libresoc.v:155113.9-155113.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\alui_l_r_alui$next[0:0]$7840 1'1 + case + assign $1\alui_l_r_alui$next[0:0]$7840 \$88 + end + sync always + update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$7839 + end + attribute \src "libresoc.v:155121.3-155129.6" + process $proc$libresoc.v:155121$7841 + assign { } { } + assign { } { } + assign $0\alu_l_r_alu$next[0:0]$7842 $1\alu_l_r_alu$next[0:0]$7843 + attribute \src "libresoc.v:155122.5-155122.29" + switch \initial + attribute \src "libresoc.v:155122.9-155122.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\alu_l_r_alu$next[0:0]$7843 1'1 + case + assign $1\alu_l_r_alu$next[0:0]$7843 \$90 + end + sync always + update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$7842 + end + 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"/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$116 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest2_o[3:0] \data_r1__cr_a + case + assign $1\dest2_o[3:0] 4'0000 + end + sync always + update \dest2_o $0\dest2_o[3:0] + end + attribute \src "libresoc.v:155150.3-155159.6" + process $proc$libresoc.v:155150$7846 + assign { } { } + assign { } { } + assign $0\dest3_o[1:0] $1\dest3_o[1:0] + attribute \src "libresoc.v:155151.5-155151.29" + switch \initial + attribute \src "libresoc.v:155151.9-155151.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$118 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest3_o[1:0] \data_r2__xer_ov + case + assign $1\dest3_o[1:0] 2'00 + end + sync always + update \dest3_o $0\dest3_o[1:0] + end + attribute \src "libresoc.v:155160.3-155169.6" + process $proc$libresoc.v:155160$7847 + assign { } { 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attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 output 18 \mul_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 3 \mul_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 19 \mul_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 4 \mul_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 20 \mul_op__imm_data__ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 12 \mul_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 28 \mul_op__insn$13 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \mul_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 17 \mul_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \mul_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 26 \mul_op__is_32bit$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 11 \mul_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 27 \mul_op__is_signed$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 7 \mul_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 23 \mul_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \mul_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 24 \mul_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 6 \mul_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 22 \mul_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 5 \mul_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 21 \mul_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \mul_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 25 \mul_op__write_cr0$10 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 input 34 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 output 16 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" + wire output 32 \neg_res + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" + wire output 33 \neg_res32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 13 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 29 \ra$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 14 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 30 \rb$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:33" + wire \sign32_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:34" + wire \sign32_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:31" + wire \sign_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:32" + wire \sign_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 15 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire output 31 \xer_so$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:38" + cell $and $and$libresoc.v:155509$7891 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$17 + connect \B \mul_op__is_signed + connect \Y $and$libresoc.v:155509$7891_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:39" + cell $and $and$libresoc.v:155511$7893 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$21 + connect \B \mul_op__is_signed + connect \Y $and$libresoc.v:155511$7893_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:40" + cell $and $and$libresoc.v:155512$7894 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ra [31] + connect \B \mul_op__is_signed + connect \Y $and$libresoc.v:155512$7894_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:41" + cell $and $and$libresoc.v:155513$7895 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \rb [31] + connect \B \mul_op__is_signed + connect \Y $and$libresoc.v:155513$7895_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:52" + cell $pos $extend$libresoc.v:155516$7898 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \ra + connect \Y $extend$libresoc.v:155516$7898_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + cell $pos $extend$libresoc.v:155517$7900 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \ra + connect \Y $extend$libresoc.v:155517$7900_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:53" + cell $pos $extend$libresoc.v:155519$7903 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \rb + connect \Y $extend$libresoc.v:155519$7903_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + cell $pos $extend$libresoc.v:155520$7905 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \rb + connect \Y $extend$libresoc.v:155520$7905_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:52" + cell $neg $neg$libresoc.v:155516$7899 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \Y_WIDTH 65 + connect \A $extend$libresoc.v:155516$7898_Y + connect \Y $neg$libresoc.v:155516$7899_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:53" + cell $neg $neg$libresoc.v:155519$7904 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \Y_WIDTH 65 + connect \A $extend$libresoc.v:155519$7903_Y + connect \Y $neg$libresoc.v:155519$7904_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + cell $pos $pos$libresoc.v:155517$7901 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \Y_WIDTH 65 + connect \A $extend$libresoc.v:155517$7900_Y + connect \Y $pos$libresoc.v:155517$7901_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + cell $pos $pos$libresoc.v:155520$7906 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \Y_WIDTH 65 + connect \A $extend$libresoc.v:155520$7905_Y + connect \Y $pos$libresoc.v:155520$7906_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:38" + cell $mux $ternary$libresoc.v:155508$7890 + parameter \WIDTH 1 + connect \A \ra [63] + connect \B \ra [31] + connect \S \mul_op__is_32bit + connect \Y $ternary$libresoc.v:155508$7890_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:39" + cell $mux $ternary$libresoc.v:155510$7892 + parameter \WIDTH 1 + connect \A \rb [63] + connect \B \rb [31] + connect \S \mul_op__is_32bit + connect \Y $ternary$libresoc.v:155510$7892_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:52" + cell $mux $ternary$libresoc.v:155518$7902 + parameter \WIDTH 65 + connect \A \$36 + connect \B \$34 + connect \S \sign_a + connect \Y $ternary$libresoc.v:155518$7902_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:53" + cell $mux $ternary$libresoc.v:155521$7907 + parameter \WIDTH 65 + connect \A \$43 + connect \B \$41 + connect \S \sign_b + connect \Y $ternary$libresoc.v:155521$7907_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:41" + cell $mux $ternary$libresoc.v:155522$7908 + parameter \WIDTH 32 + connect \A \abs_a [63:32] + connect \B 0 + connect \S \is_32bit + connect \Y $ternary$libresoc.v:155522$7908_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:41" + cell $mux $ternary$libresoc.v:155523$7909 + parameter \WIDTH 32 + connect \A \abs_b [63:32] + connect \B 0 + connect \S \is_32bit + connect \Y $ternary$libresoc.v:155523$7909_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:44" + cell $xor $xor$libresoc.v:155514$7896 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \sign_a + connect \B \sign_b + connect \Y $xor$libresoc.v:155514$7896_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:45" + cell $xor $xor$libresoc.v:155515$7897 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \sign32_a + connect \B \sign32_b + connect \Y $xor$libresoc.v:155515$7897_Y + end + connect \$17 $ternary$libresoc.v:155508$7890_Y + connect \$19 $and$libresoc.v:155509$7891_Y + connect \$21 $ternary$libresoc.v:155510$7892_Y + connect \$23 $and$libresoc.v:155511$7893_Y + connect \$25 $and$libresoc.v:155512$7894_Y + connect \$27 $and$libresoc.v:155513$7895_Y + connect \$29 $xor$libresoc.v:155514$7896_Y + connect \$31 $xor$libresoc.v:155515$7897_Y + connect \$34 $neg$libresoc.v:155516$7899_Y + connect \$36 $pos$libresoc.v:155517$7901_Y + connect \$38 $ternary$libresoc.v:155518$7902_Y + connect \$41 $neg$libresoc.v:155519$7904_Y + connect \$43 $pos$libresoc.v:155520$7906_Y + connect \$45 $ternary$libresoc.v:155521$7907_Y + connect \$47 $ternary$libresoc.v:155522$7908_Y + connect \$49 $ternary$libresoc.v:155523$7909_Y + connect \$33 \$38 + connect \$40 \$45 + connect { \mul_op__insn$13 \mul_op__is_signed$12 \mul_op__is_32bit$11 \mul_op__write_cr0$10 \mul_op__oe__ok$9 \mul_op__oe__oe$8 \mul_op__rc__ok$7 \mul_op__rc__rc$6 \mul_op__imm_data__ok$5 \mul_op__imm_data__data$4 \mul_op__fn_unit$3 \mul_op__insn_type$2 } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__oe__ok \mul_op__oe__oe \mul_op__rc__ok \mul_op__rc__rc \mul_op__imm_data__ok \mul_op__imm_data__data \mul_op__fn_unit \mul_op__insn_type } + connect \muxid$1 \muxid + connect \xer_so$16 \xer_so + connect \rb$15 [63:32] \$49 + connect \rb$15 [31:0] \abs_b [31:0] + connect \ra$14 [63:32] \$47 + connect \ra$14 [31:0] \abs_a [31:0] + connect \abs_b \$45 [63:0] + connect \abs_a \$38 [63:0] + connect \neg_res32 \$31 + connect \neg_res \$29 + connect \sign32_b \$27 + connect \sign32_a \$25 + connect \sign_b \$23 + connect \sign_a \$19 + connect \is_32bit \mul_op__is_32bit +end +attribute \src "libresoc.v:155546.1-155805.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe2.mul2" +attribute \generator "nMigen" +module \mul2 + attribute \src "libresoc.v:155798.18-155798.98" + wire width 129 $extend$libresoc.v:155798$7911_Y + attribute \src "libresoc.v:155797.18-155797.99" + wire width 128 $mul$libresoc.v:155797$7910_Y + attribute \src "libresoc.v:155798.18-155798.98" + wire width 129 $pos$libresoc.v:155798$7912_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/main_stage.py:28" + wire width 129 \$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/main_stage.py:28" + wire width 128 \$18 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 input 2 \mul_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 output 20 \mul_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 3 \mul_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 21 \mul_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 4 \mul_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 22 \mul_op__imm_data__ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 12 \mul_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 30 \mul_op__insn$13 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \mul_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute 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8 \mul_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 26 \mul_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 6 \mul_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 24 \mul_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 5 \mul_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 23 \mul_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \mul_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 27 \mul_op__write_cr0$10 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 input 35 \muxid + attribute \src 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$mul$libresoc.v:155797$7910_Y + connect \$17 $pos$libresoc.v:155798$7912_Y + connect { \mul_op__insn$13 \mul_op__is_signed$12 \mul_op__is_32bit$11 \mul_op__write_cr0$10 \mul_op__oe__ok$9 \mul_op__oe__oe$8 \mul_op__rc__ok$7 \mul_op__rc__rc$6 \mul_op__imm_data__ok$5 \mul_op__imm_data__data$4 \mul_op__fn_unit$3 \mul_op__insn_type$2 } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__oe__ok \mul_op__oe__oe \mul_op__rc__ok \mul_op__rc__rc \mul_op__imm_data__ok \mul_op__imm_data__data \mul_op__fn_unit \mul_op__insn_type } + connect \muxid$1 \muxid + connect \xer_so$14 \xer_so + connect \neg_res32$16 \neg_res32 + connect \neg_res$15 \neg_res + connect \o \$17 +end +attribute \src "libresoc.v:155809.1-156190.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe3.mul3" +attribute \generator "nMigen" +module \mul3 + attribute \src "libresoc.v:155810.7-155810.20" + wire $0\initial[0:0] + attribute \src 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$reduce_or$libresoc.v:156096$7918_Y + attribute \src "libresoc.v:156100.18-156100.107" + wire $reduce_or$libresoc.v:156100$7922_Y + attribute \src "libresoc.v:156095.18-156095.114" + wire width 130 $ternary$libresoc.v:156095$7917_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41" + wire width 130 \$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41" + wire width 130 \$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 130 \$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41" + wire width 130 \$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" + wire \$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" + wire \$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" + wire \$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" + wire \$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" + wire \$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" + wire \$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 \$39 + attribute \src "libresoc.v:155810.7-155810.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:36" + wire \is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:40" + wire width 129 \mul_o + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 input 2 \mul_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 output 18 \mul_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 3 \mul_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 19 \mul_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 4 \mul_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 20 \mul_op__imm_data__ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 12 \mul_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 28 \mul_op__insn$13 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \mul_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 17 \mul_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \mul_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 26 \mul_op__is_32bit$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 11 \mul_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 27 \mul_op__is_signed$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 7 \mul_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 23 \mul_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \mul_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 24 \mul_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 6 \mul_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 22 \mul_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 5 \mul_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 21 \mul_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \mul_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 25 \mul_op__write_cr0$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:60" + wire \mul_ov + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 input 35 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 output 16 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" + wire input 15 \neg_res + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 129 input 13 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 29 \o$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 30 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 output 31 \xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 32 \xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 14 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 33 \xer_so$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 34 \xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" + cell $and $and$libresoc.v:156099$7921 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$23 + connect \B \$25 + connect \Y $and$libresoc.v:156099$7921_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" + cell $and $and$libresoc.v:156103$7925 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$31 + connect \B \$33 + connect \Y $and$libresoc.v:156103$7925_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41" + cell $pos $extend$libresoc.v:156093$7913 + parameter \A_SIGNED 0 + parameter \A_WIDTH 129 + parameter \Y_WIDTH 130 + connect \A \o + connect \Y $extend$libresoc.v:156093$7913_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + cell $pos $extend$libresoc.v:156094$7915 + parameter \A_SIGNED 0 + parameter \A_WIDTH 129 + parameter \Y_WIDTH 130 + connect \A \o + connect \Y $extend$libresoc.v:156094$7915_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + cell $pos $extend$libresoc.v:156104$7926 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 2 + connect \A \xer_so + connect \Y $extend$libresoc.v:156104$7926_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41" + cell $neg $neg$libresoc.v:156093$7914 + parameter \A_SIGNED 0 + parameter \A_WIDTH 130 + parameter \Y_WIDTH 130 + connect \A $extend$libresoc.v:156093$7913_Y + connect \Y $neg$libresoc.v:156093$7914_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" + cell $not $not$libresoc.v:156098$7920 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$26 + connect \Y $not$libresoc.v:156098$7920_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" + cell $not $not$libresoc.v:156102$7924 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$34 + connect \Y $not$libresoc.v:156102$7924_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + cell $pos $pos$libresoc.v:156094$7916 + parameter \A_SIGNED 0 + parameter \A_WIDTH 130 + parameter \Y_WIDTH 130 + connect \A $extend$libresoc.v:156094$7915_Y + connect \Y $pos$libresoc.v:156094$7916_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + cell $pos $pos$libresoc.v:156104$7927 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A $extend$libresoc.v:156104$7926_Y + connect \Y $pos$libresoc.v:156104$7927_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" + cell $reduce_and $reduce_and$libresoc.v:156097$7919 + parameter \A_SIGNED 0 + parameter \A_WIDTH 33 + parameter \Y_WIDTH 1 + connect \A \mul_o [63:31] + connect \Y $reduce_and$libresoc.v:156097$7919_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" + cell $reduce_and $reduce_and$libresoc.v:156101$7923 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \Y_WIDTH 1 + connect \A \mul_o [127:63] + connect \Y $reduce_and$libresoc.v:156101$7923_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" + cell $reduce_or $reduce_or$libresoc.v:156096$7918 + parameter \A_SIGNED 0 + parameter \A_WIDTH 33 + parameter \Y_WIDTH 1 + connect \A \mul_o [63:31] + connect \Y $reduce_or$libresoc.v:156096$7918_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" + cell $reduce_or $reduce_or$libresoc.v:156100$7922 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \Y_WIDTH 1 + connect \A \mul_o [127:63] + connect \Y $reduce_or$libresoc.v:156100$7922_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41" + cell $mux $ternary$libresoc.v:156095$7917 + parameter \WIDTH 130 + connect \A \$19 + connect \B \$17 + connect \S \neg_res + connect \Y $ternary$libresoc.v:156095$7917_Y + end + attribute \src "libresoc.v:155810.7-155810.20" + process $proc$libresoc.v:155810$7935 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:156105.3-156123.6" + process $proc$libresoc.v:156105$7928 + assign { } { } + assign { } { } + assign $0\o$14[63:0]$7929 $1\o$14[63:0]$7930 + attribute \src "libresoc.v:156106.5-156106.29" + switch \initial + attribute \src "libresoc.v:156106.9-156106.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:44" + switch \mul_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0110100 + assign { } { } + assign $1\o$14[63:0]$7930 { \mul_o [63:32] \mul_o [63:32] } + attribute \src "libresoc.v:0.0-0.0" + case 7'0110011 + assign { } { } + assign $1\o$14[63:0]$7930 \mul_o [127:64] + attribute \src "libresoc.v:0.0-0.0" + case 7'0110010 + assign { } { } + assign $1\o$14[63:0]$7930 \mul_o [63:0] + case + assign $1\o$14[63:0]$7930 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \o$14 $0\o$14[63:0]$7929 + end + attribute \src "libresoc.v:156124.3-156142.6" + process $proc$libresoc.v:156124$7931 + assign { } { } + assign { } { } + assign $0\o_ok[0:0] $1\o_ok[0:0] + attribute \src "libresoc.v:156125.5-156125.29" + switch \initial + attribute \src "libresoc.v:156125.9-156125.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:44" + switch \mul_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0110100 + assign { } { } + assign $1\o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 7'0110011 + assign { } { } + assign $1\o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 7'0110010 + assign { } { } + assign $1\o_ok[0:0] 1'1 + case + assign $1\o_ok[0:0] 1'0 + end + sync always + update \o_ok $0\o_ok[0:0] + end + attribute \src "libresoc.v:156143.3-156161.6" + process $proc$libresoc.v:156143$7932 + assign { } { } + assign { } { } + assign $0\mul_ov[0:0] $1\mul_ov[0:0] + attribute \src "libresoc.v:156144.5-156144.29" + switch \initial + attribute \src "libresoc.v:156144.9-156144.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:44" + switch \mul_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0110010 + assign { } { } + assign $1\mul_ov[0:0] $2\mul_ov[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:61" + switch \is_32bit + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\mul_ov[0:0] \$29 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\mul_ov[0:0] \$37 + end + case + assign $1\mul_ov[0:0] 1'0 + end + sync always + update \mul_ov $0\mul_ov[0:0] + end + attribute \src "libresoc.v:156162.3-156172.6" + process $proc$libresoc.v:156162$7933 + assign { } { } + assign { } { } + assign $0\xer_ov[1:0] $1\xer_ov[1:0] + attribute \src "libresoc.v:156163.5-156163.29" + switch \initial + attribute \src "libresoc.v:156163.9-156163.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:44" + switch \mul_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0110010 + assign { } { } + assign $1\xer_ov[1:0] { \mul_ov \mul_ov } + case + assign $1\xer_ov[1:0] 2'00 + end + sync always + update \xer_ov $0\xer_ov[1:0] + end + attribute \src "libresoc.v:156173.3-156183.6" + process $proc$libresoc.v:156173$7934 + assign { } { } + assign { } { } + assign $0\xer_ov_ok[0:0] $1\xer_ov_ok[0:0] + attribute \src "libresoc.v:156174.5-156174.29" + switch \initial + attribute \src "libresoc.v:156174.9-156174.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:44" + switch \mul_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0110010 + assign { } { } + assign $1\xer_ov_ok[0:0] 1'1 + case + assign $1\xer_ov_ok[0:0] 1'0 + end + sync always + update \xer_ov_ok $0\xer_ov_ok[0:0] + end + connect \$17 $neg$libresoc.v:156093$7914_Y + connect \$19 $pos$libresoc.v:156094$7916_Y + connect \$21 $ternary$libresoc.v:156095$7917_Y + connect \$23 $reduce_or$libresoc.v:156096$7918_Y + connect \$26 $reduce_and$libresoc.v:156097$7919_Y + connect \$25 $not$libresoc.v:156098$7920_Y + connect \$29 $and$libresoc.v:156099$7921_Y + connect \$31 $reduce_or$libresoc.v:156100$7922_Y + connect \$34 $reduce_and$libresoc.v:156101$7923_Y + connect \$33 $not$libresoc.v:156102$7924_Y + connect \$37 $and$libresoc.v:156103$7925_Y + connect \$39 $pos$libresoc.v:156104$7927_Y + connect \$16 \$21 + connect { \mul_op__insn$13 \mul_op__is_signed$12 \mul_op__is_32bit$11 \mul_op__write_cr0$10 \mul_op__oe__ok$9 \mul_op__oe__oe$8 \mul_op__rc__ok$7 \mul_op__rc__rc$6 \mul_op__imm_data__ok$5 \mul_op__imm_data__data$4 \mul_op__fn_unit$3 \mul_op__insn_type$2 } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__oe__ok \mul_op__oe__oe \mul_op__rc__ok \mul_op__rc__rc \mul_op__imm_data__ok \mul_op__imm_data__data \mul_op__fn_unit \mul_op__insn_type } + connect \muxid$1 \muxid + connect { \xer_so_ok \xer_so$15 } \$39 + connect \mul_o \$21 [128:0] + connect \is_32bit \mul_op__is_32bit +end +attribute \src "libresoc.v:156194.1-157397.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe1" +attribute \generator "nMigen" +module \mul_pipe1 + attribute \src "libresoc.v:156195.7-156195.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:157274.3-157309.6" + wire width 13 $0\mul_op__fn_unit$next[12:0]$7964 + attribute \src "libresoc.v:157139.3-157140.47" + wire width 13 $0\mul_op__fn_unit[12:0] + attribute \src "libresoc.v:157274.3-157309.6" + wire width 64 $0\mul_op__imm_data__data$next[63:0]$7965 + attribute \src "libresoc.v:157141.3-157142.61" + wire width 64 $0\mul_op__imm_data__data[63:0] + attribute \src "libresoc.v:157274.3-157309.6" + wire $0\mul_op__imm_data__ok$next[0:0]$7966 + attribute \src "libresoc.v:157143.3-157144.57" + wire $0\mul_op__imm_data__ok[0:0] + attribute \src "libresoc.v:157274.3-157309.6" + wire width 32 $0\mul_op__insn$next[31:0]$7967 + attribute \src "libresoc.v:157159.3-157160.41" + wire width 32 $0\mul_op__insn[31:0] + attribute \src "libresoc.v:157274.3-157309.6" + wire width 7 $0\mul_op__insn_type$next[6:0]$7968 + attribute \src "libresoc.v:157137.3-157138.51" + wire width 7 $0\mul_op__insn_type[6:0] + attribute \src "libresoc.v:157274.3-157309.6" + wire $0\mul_op__is_32bit$next[0:0]$7969 + attribute \src "libresoc.v:157155.3-157156.49" + wire $0\mul_op__is_32bit[0:0] + attribute \src "libresoc.v:157274.3-157309.6" + wire $0\mul_op__is_signed$next[0:0]$7970 + attribute \src "libresoc.v:157157.3-157158.51" + wire $0\mul_op__is_signed[0:0] + attribute \src "libresoc.v:157274.3-157309.6" + wire $0\mul_op__oe__oe$next[0:0]$7971 + attribute \src "libresoc.v:157149.3-157150.45" + wire $0\mul_op__oe__oe[0:0] + attribute \src "libresoc.v:157274.3-157309.6" + wire $0\mul_op__oe__ok$next[0:0]$7972 + attribute \src "libresoc.v:157151.3-157152.45" + wire $0\mul_op__oe__ok[0:0] + attribute \src "libresoc.v:157274.3-157309.6" + wire $0\mul_op__rc__ok$next[0:0]$7973 + attribute \src "libresoc.v:157147.3-157148.45" + wire $0\mul_op__rc__ok[0:0] + attribute \src "libresoc.v:157274.3-157309.6" + wire $0\mul_op__rc__rc$next[0:0]$7974 + attribute \src "libresoc.v:157145.3-157146.45" + wire $0\mul_op__rc__rc[0:0] + attribute \src "libresoc.v:157274.3-157309.6" + wire $0\mul_op__write_cr0$next[0:0]$7975 + attribute \src "libresoc.v:157153.3-157154.51" + wire $0\mul_op__write_cr0[0:0] + attribute \src "libresoc.v:157261.3-157273.6" + wire width 2 $0\muxid$next[1:0]$7961 + attribute \src "libresoc.v:157161.3-157162.27" + wire width 2 $0\muxid[1:0] + attribute \src "libresoc.v:157349.3-157361.6" + wire $0\neg_res$next[0:0]$8004 + attribute \src "libresoc.v:157362.3-157374.6" + wire $0\neg_res32$next[0:0]$8007 + attribute \src "libresoc.v:157127.3-157128.35" + wire $0\neg_res32[0:0] + attribute \src "libresoc.v:157129.3-157130.31" + wire $0\neg_res[0:0] + attribute \src "libresoc.v:157243.3-157260.6" + wire $0\r_busy$next[0:0]$7957 + attribute \src "libresoc.v:157163.3-157164.29" + wire $0\r_busy[0:0] + attribute \src "libresoc.v:157310.3-157322.6" + wire width 64 $0\ra$next[63:0]$7995 + attribute \src "libresoc.v:157135.3-157136.21" + wire width 64 $0\ra[63:0] + attribute \src "libresoc.v:157323.3-157335.6" + wire width 64 $0\rb$next[63:0]$7998 + attribute \src "libresoc.v:157133.3-157134.21" + wire width 64 $0\rb[63:0] + attribute \src "libresoc.v:157336.3-157348.6" + wire $0\xer_so$next[0:0]$8001 + attribute \src "libresoc.v:157131.3-157132.29" + wire $0\xer_so[0:0] + attribute \src "libresoc.v:157274.3-157309.6" + wire width 13 $1\mul_op__fn_unit$next[12:0]$7976 + attribute \src "libresoc.v:156702.14-156702.40" + wire width 13 $1\mul_op__fn_unit[12:0] + attribute \src "libresoc.v:157274.3-157309.6" + wire width 64 $1\mul_op__imm_data__data$next[63:0]$7977 + attribute \src "libresoc.v:156739.14-156739.59" + wire width 64 $1\mul_op__imm_data__data[63:0] + attribute \src "libresoc.v:157274.3-157309.6" + wire $1\mul_op__imm_data__ok$next[0:0]$7978 + attribute \src "libresoc.v:156748.7-156748.34" + wire $1\mul_op__imm_data__ok[0:0] + attribute \src "libresoc.v:157274.3-157309.6" + wire width 32 $1\mul_op__insn$next[31:0]$7979 + attribute \src "libresoc.v:156757.14-156757.34" + wire width 32 $1\mul_op__insn[31:0] + attribute \src "libresoc.v:157274.3-157309.6" + wire width 7 $1\mul_op__insn_type$next[6:0]$7980 + attribute \src "libresoc.v:156840.13-156840.38" + wire width 7 $1\mul_op__insn_type[6:0] + attribute \src "libresoc.v:157274.3-157309.6" + wire $1\mul_op__is_32bit$next[0:0]$7981 + attribute \src "libresoc.v:156997.7-156997.30" + wire $1\mul_op__is_32bit[0:0] + attribute \src "libresoc.v:157274.3-157309.6" + wire $1\mul_op__is_signed$next[0:0]$7982 + attribute \src "libresoc.v:157006.7-157006.31" + wire $1\mul_op__is_signed[0:0] + attribute \src "libresoc.v:157274.3-157309.6" + wire $1\mul_op__oe__oe$next[0:0]$7983 + attribute \src "libresoc.v:157015.7-157015.28" + wire $1\mul_op__oe__oe[0:0] + attribute \src "libresoc.v:157274.3-157309.6" + wire $1\mul_op__oe__ok$next[0:0]$7984 + attribute \src "libresoc.v:157024.7-157024.28" + wire $1\mul_op__oe__ok[0:0] + attribute \src "libresoc.v:157274.3-157309.6" + wire $1\mul_op__rc__ok$next[0:0]$7985 + attribute \src "libresoc.v:157033.7-157033.28" + wire $1\mul_op__rc__ok[0:0] + attribute \src "libresoc.v:157274.3-157309.6" + wire $1\mul_op__rc__rc$next[0:0]$7986 + attribute \src "libresoc.v:157042.7-157042.28" + wire $1\mul_op__rc__rc[0:0] + attribute \src "libresoc.v:157274.3-157309.6" + wire $1\mul_op__write_cr0$next[0:0]$7987 + attribute \src "libresoc.v:157051.7-157051.31" + wire $1\mul_op__write_cr0[0:0] + attribute \src "libresoc.v:157261.3-157273.6" + wire width 2 $1\muxid$next[1:0]$7962 + attribute \src "libresoc.v:157060.13-157060.25" + wire width 2 $1\muxid[1:0] + attribute \src "libresoc.v:157349.3-157361.6" + wire $1\neg_res$next[0:0]$8005 + attribute \src "libresoc.v:157362.3-157374.6" + wire $1\neg_res32$next[0:0]$8008 + attribute \src "libresoc.v:157082.7-157082.23" + wire $1\neg_res32[0:0] + attribute \src "libresoc.v:157075.7-157075.21" + wire $1\neg_res[0:0] + attribute \src "libresoc.v:157243.3-157260.6" + wire $1\r_busy$next[0:0]$7958 + attribute \src "libresoc.v:157096.7-157096.20" + wire $1\r_busy[0:0] + attribute \src "libresoc.v:157310.3-157322.6" + wire width 64 $1\ra$next[63:0]$7996 + attribute \src "libresoc.v:157101.14-157101.39" + wire width 64 $1\ra[63:0] + attribute \src "libresoc.v:157323.3-157335.6" + wire width 64 $1\rb$next[63:0]$7999 + attribute \src "libresoc.v:157110.14-157110.39" + wire width 64 $1\rb[63:0] + attribute \src "libresoc.v:157336.3-157348.6" + wire $1\xer_so$next[0:0]$8002 + attribute \src "libresoc.v:157119.7-157119.20" + wire $1\xer_so[0:0] + attribute \src "libresoc.v:157274.3-157309.6" + wire width 64 $2\mul_op__imm_data__data$next[63:0]$7988 + attribute \src "libresoc.v:157274.3-157309.6" + wire $2\mul_op__imm_data__ok$next[0:0]$7989 + attribute \src "libresoc.v:157274.3-157309.6" + wire $2\mul_op__oe__oe$next[0:0]$7990 + attribute \src "libresoc.v:157274.3-157309.6" + wire $2\mul_op__oe__ok$next[0:0]$7991 + attribute \src "libresoc.v:157274.3-157309.6" + wire $2\mul_op__rc__ok$next[0:0]$7992 + attribute \src "libresoc.v:157274.3-157309.6" + wire $2\mul_op__rc__rc$next[0:0]$7993 + attribute \src "libresoc.v:157243.3-157260.6" + wire $2\r_busy$next[0:0]$7959 + attribute \src "libresoc.v:157126.18-157126.118" + wire $and$libresoc.v:157126$7936_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" + wire \$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 40 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 1 \coresync_rst + attribute \src "libresoc.v:156195.7-156195.15" + wire \initial + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \input_mul_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \input_mul_op__fn_unit$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \input_mul_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \input_mul_op__imm_data__data$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_mul_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_mul_op__imm_data__ok$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \input_mul_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \input_mul_op__insn$29 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \input_mul_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \input_mul_op__insn_type$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_mul_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_mul_op__is_32bit$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_mul_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_mul_op__is_signed$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_mul_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_mul_op__oe__oe$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_mul_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_mul_op__oe__ok$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_mul_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_mul_op__rc__ok$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_mul_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_mul_op__rc__rc$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_mul_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_mul_op__write_cr0$26 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \input_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \input_muxid$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_ra$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_rb$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \input_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \input_xer_so$32 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \mul1_mul_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \mul1_mul_op__fn_unit$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \mul1_mul_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \mul1_mul_op__imm_data__data$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul1_mul_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul1_mul_op__imm_data__ok$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \mul1_mul_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \mul1_mul_op__insn$45 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \mul1_mul_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \mul1_mul_op__insn_type$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul1_mul_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul1_mul_op__is_32bit$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul1_mul_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul1_mul_op__is_signed$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul1_mul_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul1_mul_op__oe__oe$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul1_mul_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul1_mul_op__oe__ok$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul1_mul_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul1_mul_op__rc__ok$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul1_mul_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul1_mul_op__rc__rc$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul1_mul_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul1_mul_op__write_cr0$42 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \mul1_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \mul1_muxid$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" + wire \mul1_neg_res + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" + wire \mul1_neg_res32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \mul1_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \mul1_ra$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \mul1_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \mul1_rb$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \mul1_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \mul1_xer_so$48 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 output 6 \mul_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 input 26 \mul_op__fn_unit$3 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \mul_op__fn_unit$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \mul_op__fn_unit$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 7 \mul_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 27 \mul_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \mul_op__imm_data__data$55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \mul_op__imm_data__data$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 8 \mul_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 28 \mul_op__imm_data__ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__imm_data__ok$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__imm_data__ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 16 \mul_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 36 \mul_op__insn$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \mul_op__insn$64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \mul_op__insn$next + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 5 \mul_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 25 \mul_op__insn_type$2 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \mul_op__insn_type$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \mul_op__insn_type$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 14 \mul_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 34 \mul_op__is_32bit$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__is_32bit$62 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__is_32bit$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 15 \mul_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 35 \mul_op__is_signed$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__is_signed$63 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__is_signed$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 11 \mul_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__oe__oe$59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 31 \mul_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__oe__oe$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 12 \mul_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__oe__ok$60 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 32 \mul_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__oe__ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 10 \mul_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__rc__ok$58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 30 \mul_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__rc__ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 9 \mul_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__rc__rc$57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 29 \mul_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__rc__rc$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 13 \mul_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 33 \mul_op__write_cr0$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__write_cr0$61 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__write_cr0$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 output 4 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 input 24 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid$52 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + wire \n_i_rdy_data + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire input 3 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire output 2 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" + wire output 20 \neg_res + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" + wire \neg_res$68 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" + wire \neg_res$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" + wire output 21 \neg_res32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" + wire \neg_res32$69 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" + wire \neg_res32$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" + wire output 23 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" + wire input 22 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" + wire \p_valid_i$49 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" + wire \p_valid_i_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire \r_busy$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 17 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 37 \ra$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \ra$65 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \ra$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 18 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 38 \rb$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \rb$66 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \rb$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire output 19 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 39 \xer_so$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \xer_so$67 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \xer_so$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" + cell $and $and$libresoc.v:157126$7936 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i$49 + connect \B \p_ready_o + connect \Y $and$libresoc.v:157126$7936_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:157165.14-157198.4" + cell \input$95 \input + connect \mul_op__fn_unit \input_mul_op__fn_unit + connect \mul_op__fn_unit$3 \input_mul_op__fn_unit$19 + connect \mul_op__imm_data__data \input_mul_op__imm_data__data + connect \mul_op__imm_data__data$4 \input_mul_op__imm_data__data$20 + connect \mul_op__imm_data__ok \input_mul_op__imm_data__ok + connect \mul_op__imm_data__ok$5 \input_mul_op__imm_data__ok$21 + connect \mul_op__insn \input_mul_op__insn + connect \mul_op__insn$13 \input_mul_op__insn$29 + connect \mul_op__insn_type \input_mul_op__insn_type + connect \mul_op__insn_type$2 \input_mul_op__insn_type$18 + connect \mul_op__is_32bit \input_mul_op__is_32bit + connect \mul_op__is_32bit$11 \input_mul_op__is_32bit$27 + connect \mul_op__is_signed \input_mul_op__is_signed + connect \mul_op__is_signed$12 \input_mul_op__is_signed$28 + connect \mul_op__oe__oe \input_mul_op__oe__oe + connect \mul_op__oe__oe$8 \input_mul_op__oe__oe$24 + connect \mul_op__oe__ok \input_mul_op__oe__ok + connect \mul_op__oe__ok$9 \input_mul_op__oe__ok$25 + connect \mul_op__rc__ok \input_mul_op__rc__ok + connect \mul_op__rc__ok$7 \input_mul_op__rc__ok$23 + connect \mul_op__rc__rc \input_mul_op__rc__rc + connect \mul_op__rc__rc$6 \input_mul_op__rc__rc$22 + connect \mul_op__write_cr0 \input_mul_op__write_cr0 + connect \mul_op__write_cr0$10 \input_mul_op__write_cr0$26 + connect \muxid \input_muxid + connect \muxid$1 \input_muxid$17 + connect \ra \input_ra + connect \ra$14 \input_ra$30 + connect \rb \input_rb + connect \rb$15 \input_rb$31 + connect \xer_so \input_xer_so + connect \xer_so$16 \input_xer_so$32 + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:157199.8-157234.4" + cell \mul1 \mul1 + connect \mul_op__fn_unit \mul1_mul_op__fn_unit + connect \mul_op__fn_unit$3 \mul1_mul_op__fn_unit$35 + connect \mul_op__imm_data__data \mul1_mul_op__imm_data__data + connect \mul_op__imm_data__data$4 \mul1_mul_op__imm_data__data$36 + connect \mul_op__imm_data__ok \mul1_mul_op__imm_data__ok + connect \mul_op__imm_data__ok$5 \mul1_mul_op__imm_data__ok$37 + connect \mul_op__insn \mul1_mul_op__insn + connect \mul_op__insn$13 \mul1_mul_op__insn$45 + connect \mul_op__insn_type \mul1_mul_op__insn_type + connect \mul_op__insn_type$2 \mul1_mul_op__insn_type$34 + connect \mul_op__is_32bit \mul1_mul_op__is_32bit + connect \mul_op__is_32bit$11 \mul1_mul_op__is_32bit$43 + connect \mul_op__is_signed \mul1_mul_op__is_signed + connect \mul_op__is_signed$12 \mul1_mul_op__is_signed$44 + connect \mul_op__oe__oe \mul1_mul_op__oe__oe + connect \mul_op__oe__oe$8 \mul1_mul_op__oe__oe$40 + connect \mul_op__oe__ok \mul1_mul_op__oe__ok + connect \mul_op__oe__ok$9 \mul1_mul_op__oe__ok$41 + connect \mul_op__rc__ok \mul1_mul_op__rc__ok + connect \mul_op__rc__ok$7 \mul1_mul_op__rc__ok$39 + connect \mul_op__rc__rc \mul1_mul_op__rc__rc + connect \mul_op__rc__rc$6 \mul1_mul_op__rc__rc$38 + connect \mul_op__write_cr0 \mul1_mul_op__write_cr0 + connect \mul_op__write_cr0$10 \mul1_mul_op__write_cr0$42 + connect \muxid \mul1_muxid + connect \muxid$1 \mul1_muxid$33 + connect \neg_res \mul1_neg_res + connect \neg_res32 \mul1_neg_res32 + connect \ra \mul1_ra + connect \ra$14 \mul1_ra$46 + connect \rb \mul1_rb + connect \rb$15 \mul1_rb$47 + connect \xer_so \mul1_xer_so + connect \xer_so$16 \mul1_xer_so$48 + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:157235.10-157238.4" + cell \n$94 \n + connect \n_ready_i \n_ready_i + connect \n_valid_o \n_valid_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:157239.10-157242.4" + cell \p$93 \p + connect \p_ready_o \p_ready_o + connect \p_valid_i \p_valid_i + end + attribute \src "libresoc.v:156195.7-156195.20" + process $proc$libresoc.v:156195$8009 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:156702.14-156702.40" + process $proc$libresoc.v:156702$8010 + assign { } { } + assign $1\mul_op__fn_unit[12:0] 13'0000000000000 + sync always + sync init + update \mul_op__fn_unit $1\mul_op__fn_unit[12:0] + end + attribute \src "libresoc.v:156739.14-156739.59" + process $proc$libresoc.v:156739$8011 + assign { } { } + assign $1\mul_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \mul_op__imm_data__data $1\mul_op__imm_data__data[63:0] + end + attribute \src "libresoc.v:156748.7-156748.34" + process $proc$libresoc.v:156748$8012 + assign { } { } + assign $1\mul_op__imm_data__ok[0:0] 1'0 + sync always + sync init + update \mul_op__imm_data__ok $1\mul_op__imm_data__ok[0:0] + end + attribute \src "libresoc.v:156757.14-156757.34" + process $proc$libresoc.v:156757$8013 + assign { } { } + assign $1\mul_op__insn[31:0] 0 + sync always + sync init + update \mul_op__insn $1\mul_op__insn[31:0] + end + attribute \src "libresoc.v:156840.13-156840.38" + process $proc$libresoc.v:156840$8014 + assign { } { } + assign $1\mul_op__insn_type[6:0] 7'0000000 + sync always + sync init + update \mul_op__insn_type $1\mul_op__insn_type[6:0] + end + attribute \src "libresoc.v:156997.7-156997.30" + process $proc$libresoc.v:156997$8015 + assign { } { } + assign $1\mul_op__is_32bit[0:0] 1'0 + sync always + sync init + update \mul_op__is_32bit $1\mul_op__is_32bit[0:0] + end + attribute \src "libresoc.v:157006.7-157006.31" + process $proc$libresoc.v:157006$8016 + assign { } { } + assign $1\mul_op__is_signed[0:0] 1'0 + sync always + sync init + update \mul_op__is_signed $1\mul_op__is_signed[0:0] + end + attribute \src "libresoc.v:157015.7-157015.28" + process $proc$libresoc.v:157015$8017 + assign { } { } + assign $1\mul_op__oe__oe[0:0] 1'0 + sync always + sync init + update \mul_op__oe__oe $1\mul_op__oe__oe[0:0] + end + attribute \src "libresoc.v:157024.7-157024.28" + process $proc$libresoc.v:157024$8018 + assign { } { } + assign $1\mul_op__oe__ok[0:0] 1'0 + sync always + sync init + update \mul_op__oe__ok $1\mul_op__oe__ok[0:0] + end + attribute \src "libresoc.v:157033.7-157033.28" + process $proc$libresoc.v:157033$8019 + assign { } { } + assign $1\mul_op__rc__ok[0:0] 1'0 + sync always + sync init + update \mul_op__rc__ok $1\mul_op__rc__ok[0:0] + end + attribute \src "libresoc.v:157042.7-157042.28" + process $proc$libresoc.v:157042$8020 + assign { } { } + assign $1\mul_op__rc__rc[0:0] 1'0 + sync always + sync init + update \mul_op__rc__rc $1\mul_op__rc__rc[0:0] + end + attribute \src "libresoc.v:157051.7-157051.31" + process $proc$libresoc.v:157051$8021 + assign { } { } + assign $1\mul_op__write_cr0[0:0] 1'0 + sync always + sync init + update \mul_op__write_cr0 $1\mul_op__write_cr0[0:0] + end + attribute \src "libresoc.v:157060.13-157060.25" + process $proc$libresoc.v:157060$8022 + assign { } { } + assign $1\muxid[1:0] 2'00 + sync always + sync init + update \muxid $1\muxid[1:0] + end + attribute \src "libresoc.v:157075.7-157075.21" + process $proc$libresoc.v:157075$8023 + assign { } { } + assign $1\neg_res[0:0] 1'0 + sync always + sync init + update \neg_res $1\neg_res[0:0] + end + attribute \src "libresoc.v:157082.7-157082.23" + process $proc$libresoc.v:157082$8024 + assign { } { } + assign $1\neg_res32[0:0] 1'0 + sync always + sync init + update \neg_res32 $1\neg_res32[0:0] + end + attribute \src "libresoc.v:157096.7-157096.20" + process $proc$libresoc.v:157096$8025 + assign { } { } + assign $1\r_busy[0:0] 1'0 + sync always + sync init + update \r_busy $1\r_busy[0:0] + end + attribute \src "libresoc.v:157101.14-157101.39" + process $proc$libresoc.v:157101$8026 + assign { } { } + assign $1\ra[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \ra $1\ra[63:0] + end + attribute \src "libresoc.v:157110.14-157110.39" + process $proc$libresoc.v:157110$8027 + assign { } { } + assign $1\rb[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \rb $1\rb[63:0] + end + attribute \src "libresoc.v:157119.7-157119.20" + process $proc$libresoc.v:157119$8028 + assign { } { } + assign $1\xer_so[0:0] 1'0 + sync always + sync init + update \xer_so $1\xer_so[0:0] + end + attribute \src "libresoc.v:157127.3-157128.35" + process $proc$libresoc.v:157127$7937 + assign { } { } + assign $0\neg_res32[0:0] \neg_res32$next + sync posedge \coresync_clk + update \neg_res32 $0\neg_res32[0:0] + end + attribute \src "libresoc.v:157129.3-157130.31" + process $proc$libresoc.v:157129$7938 + assign { } { } + assign $0\neg_res[0:0] \neg_res$next + sync posedge \coresync_clk + update \neg_res $0\neg_res[0:0] + end + attribute \src "libresoc.v:157131.3-157132.29" + process $proc$libresoc.v:157131$7939 + assign { } { } + assign $0\xer_so[0:0] \xer_so$next + sync posedge \coresync_clk + update \xer_so $0\xer_so[0:0] + end + attribute \src "libresoc.v:157133.3-157134.21" + process $proc$libresoc.v:157133$7940 + assign { } { } + assign $0\rb[63:0] \rb$next + sync posedge \coresync_clk + update \rb $0\rb[63:0] + end + attribute \src "libresoc.v:157135.3-157136.21" + process $proc$libresoc.v:157135$7941 + assign { } { } + assign $0\ra[63:0] \ra$next + sync posedge \coresync_clk + update \ra $0\ra[63:0] + end + attribute \src "libresoc.v:157137.3-157138.51" + process $proc$libresoc.v:157137$7942 + assign { } { } + assign $0\mul_op__insn_type[6:0] \mul_op__insn_type$next + sync posedge \coresync_clk + update \mul_op__insn_type $0\mul_op__insn_type[6:0] + end + attribute \src "libresoc.v:157139.3-157140.47" + process $proc$libresoc.v:157139$7943 + assign { } { } + assign $0\mul_op__fn_unit[12:0] \mul_op__fn_unit$next + sync posedge \coresync_clk + update \mul_op__fn_unit $0\mul_op__fn_unit[12:0] + end + attribute \src "libresoc.v:157141.3-157142.61" + process $proc$libresoc.v:157141$7944 + assign { } { } + assign $0\mul_op__imm_data__data[63:0] \mul_op__imm_data__data$next + sync posedge \coresync_clk + update \mul_op__imm_data__data $0\mul_op__imm_data__data[63:0] + end + attribute \src "libresoc.v:157143.3-157144.57" + process $proc$libresoc.v:157143$7945 + assign { } { } + assign $0\mul_op__imm_data__ok[0:0] \mul_op__imm_data__ok$next + sync posedge \coresync_clk + update \mul_op__imm_data__ok $0\mul_op__imm_data__ok[0:0] + end + attribute \src "libresoc.v:157145.3-157146.45" + process $proc$libresoc.v:157145$7946 + assign { } { } + assign $0\mul_op__rc__rc[0:0] \mul_op__rc__rc$next + sync posedge \coresync_clk + update \mul_op__rc__rc $0\mul_op__rc__rc[0:0] + end + attribute \src "libresoc.v:157147.3-157148.45" + process $proc$libresoc.v:157147$7947 + assign { } { } + assign $0\mul_op__rc__ok[0:0] \mul_op__rc__ok$next + sync posedge \coresync_clk + update \mul_op__rc__ok $0\mul_op__rc__ok[0:0] + end + attribute \src "libresoc.v:157149.3-157150.45" + process $proc$libresoc.v:157149$7948 + assign { } { } + assign $0\mul_op__oe__oe[0:0] \mul_op__oe__oe$next + sync posedge \coresync_clk + update \mul_op__oe__oe $0\mul_op__oe__oe[0:0] + end + attribute \src "libresoc.v:157151.3-157152.45" + process $proc$libresoc.v:157151$7949 + assign { } { } + assign $0\mul_op__oe__ok[0:0] \mul_op__oe__ok$next + sync posedge \coresync_clk + update \mul_op__oe__ok $0\mul_op__oe__ok[0:0] + end + attribute \src "libresoc.v:157153.3-157154.51" + process $proc$libresoc.v:157153$7950 + assign { } { } + assign $0\mul_op__write_cr0[0:0] \mul_op__write_cr0$next + sync posedge \coresync_clk + update \mul_op__write_cr0 $0\mul_op__write_cr0[0:0] + end + attribute \src "libresoc.v:157155.3-157156.49" + process $proc$libresoc.v:157155$7951 + assign { } { } + assign $0\mul_op__is_32bit[0:0] \mul_op__is_32bit$next + sync posedge \coresync_clk + update \mul_op__is_32bit $0\mul_op__is_32bit[0:0] + end + attribute \src "libresoc.v:157157.3-157158.51" + process $proc$libresoc.v:157157$7952 + assign { } { } + assign $0\mul_op__is_signed[0:0] \mul_op__is_signed$next + sync posedge \coresync_clk + update \mul_op__is_signed $0\mul_op__is_signed[0:0] + end + attribute \src "libresoc.v:157159.3-157160.41" + process $proc$libresoc.v:157159$7953 + assign { } { } + assign $0\mul_op__insn[31:0] \mul_op__insn$next + sync posedge \coresync_clk + update \mul_op__insn $0\mul_op__insn[31:0] + end + attribute \src "libresoc.v:157161.3-157162.27" + process $proc$libresoc.v:157161$7954 + assign { } { } + assign $0\muxid[1:0] \muxid$next + sync posedge \coresync_clk + update \muxid $0\muxid[1:0] + end + attribute \src "libresoc.v:157163.3-157164.29" + process $proc$libresoc.v:157163$7955 + assign { } { } + assign $0\r_busy[0:0] \r_busy$next + sync posedge \coresync_clk + update \r_busy $0\r_busy[0:0] + end + attribute \src "libresoc.v:157243.3-157260.6" + process $proc$libresoc.v:157243$7956 + assign { } { } + assign { } { } + assign { } { } + assign $0\r_busy$next[0:0]$7957 $2\r_busy$next[0:0]$7959 + attribute \src "libresoc.v:157244.5-157244.29" + switch \initial + attribute \src "libresoc.v:157244.9-157244.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\r_busy$next[0:0]$7958 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\r_busy$next[0:0]$7958 1'0 + case + assign $1\r_busy$next[0:0]$7958 \r_busy + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r_busy$next[0:0]$7959 1'0 + case + assign $2\r_busy$next[0:0]$7959 $1\r_busy$next[0:0]$7958 + end + sync always + update \r_busy$next $0\r_busy$next[0:0]$7957 + end + attribute \src "libresoc.v:157261.3-157273.6" + process $proc$libresoc.v:157261$7960 + assign { } { } + assign { } { } + assign $0\muxid$next[1:0]$7961 $1\muxid$next[1:0]$7962 + attribute \src "libresoc.v:157262.5-157262.29" + switch \initial + attribute \src "libresoc.v:157262.9-157262.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\muxid$next[1:0]$7962 \muxid$52 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\muxid$next[1:0]$7962 \muxid$52 + case + assign $1\muxid$next[1:0]$7962 \muxid + end + sync always + update \muxid$next $0\muxid$next[1:0]$7961 + end + attribute \src "libresoc.v:157274.3-157309.6" + process $proc$libresoc.v:157274$7963 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\mul_op__fn_unit$next[12:0]$7964 $1\mul_op__fn_unit$next[12:0]$7976 + assign { } { } + assign { } { } + assign $0\mul_op__insn$next[31:0]$7967 $1\mul_op__insn$next[31:0]$7979 + assign $0\mul_op__insn_type$next[6:0]$7968 $1\mul_op__insn_type$next[6:0]$7980 + assign $0\mul_op__is_32bit$next[0:0]$7969 $1\mul_op__is_32bit$next[0:0]$7981 + assign $0\mul_op__is_signed$next[0:0]$7970 $1\mul_op__is_signed$next[0:0]$7982 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\mul_op__write_cr0$next[0:0]$7975 $1\mul_op__write_cr0$next[0:0]$7987 + assign $0\mul_op__imm_data__data$next[63:0]$7965 $2\mul_op__imm_data__data$next[63:0]$7988 + assign $0\mul_op__imm_data__ok$next[0:0]$7966 $2\mul_op__imm_data__ok$next[0:0]$7989 + assign $0\mul_op__oe__oe$next[0:0]$7971 $2\mul_op__oe__oe$next[0:0]$7990 + assign $0\mul_op__oe__ok$next[0:0]$7972 $2\mul_op__oe__ok$next[0:0]$7991 + assign $0\mul_op__rc__ok$next[0:0]$7973 $2\mul_op__rc__ok$next[0:0]$7992 + assign $0\mul_op__rc__rc$next[0:0]$7974 $2\mul_op__rc__rc$next[0:0]$7993 + attribute \src "libresoc.v:157275.5-157275.29" + switch \initial + attribute \src "libresoc.v:157275.9-157275.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\mul_op__insn$next[31:0]$7979 $1\mul_op__is_signed$next[0:0]$7982 $1\mul_op__is_32bit$next[0:0]$7981 $1\mul_op__write_cr0$next[0:0]$7987 $1\mul_op__oe__ok$next[0:0]$7984 $1\mul_op__oe__oe$next[0:0]$7983 $1\mul_op__rc__ok$next[0:0]$7985 $1\mul_op__rc__rc$next[0:0]$7986 $1\mul_op__imm_data__ok$next[0:0]$7978 $1\mul_op__imm_data__data$next[63:0]$7977 $1\mul_op__fn_unit$next[12:0]$7976 $1\mul_op__insn_type$next[6:0]$7980 } { \mul_op__insn$64 \mul_op__is_signed$63 \mul_op__is_32bit$62 \mul_op__write_cr0$61 \mul_op__oe__ok$60 \mul_op__oe__oe$59 \mul_op__rc__ok$58 \mul_op__rc__rc$57 \mul_op__imm_data__ok$56 \mul_op__imm_data__data$55 \mul_op__fn_unit$54 \mul_op__insn_type$53 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\mul_op__insn$next[31:0]$7979 $1\mul_op__is_signed$next[0:0]$7982 $1\mul_op__is_32bit$next[0:0]$7981 $1\mul_op__write_cr0$next[0:0]$7987 $1\mul_op__oe__ok$next[0:0]$7984 $1\mul_op__oe__oe$next[0:0]$7983 $1\mul_op__rc__ok$next[0:0]$7985 $1\mul_op__rc__rc$next[0:0]$7986 $1\mul_op__imm_data__ok$next[0:0]$7978 $1\mul_op__imm_data__data$next[63:0]$7977 $1\mul_op__fn_unit$next[12:0]$7976 $1\mul_op__insn_type$next[6:0]$7980 } { \mul_op__insn$64 \mul_op__is_signed$63 \mul_op__is_32bit$62 \mul_op__write_cr0$61 \mul_op__oe__ok$60 \mul_op__oe__oe$59 \mul_op__rc__ok$58 \mul_op__rc__rc$57 \mul_op__imm_data__ok$56 \mul_op__imm_data__data$55 \mul_op__fn_unit$54 \mul_op__insn_type$53 } + case + assign $1\mul_op__fn_unit$next[12:0]$7976 \mul_op__fn_unit + assign $1\mul_op__imm_data__data$next[63:0]$7977 \mul_op__imm_data__data + assign $1\mul_op__imm_data__ok$next[0:0]$7978 \mul_op__imm_data__ok + assign $1\mul_op__insn$next[31:0]$7979 \mul_op__insn + assign $1\mul_op__insn_type$next[6:0]$7980 \mul_op__insn_type + assign $1\mul_op__is_32bit$next[0:0]$7981 \mul_op__is_32bit + assign $1\mul_op__is_signed$next[0:0]$7982 \mul_op__is_signed + assign $1\mul_op__oe__oe$next[0:0]$7983 \mul_op__oe__oe + assign $1\mul_op__oe__ok$next[0:0]$7984 \mul_op__oe__ok + assign $1\mul_op__rc__ok$next[0:0]$7985 \mul_op__rc__ok + assign $1\mul_op__rc__rc$next[0:0]$7986 \mul_op__rc__rc + assign $1\mul_op__write_cr0$next[0:0]$7987 \mul_op__write_cr0 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $2\mul_op__imm_data__data$next[63:0]$7988 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\mul_op__imm_data__ok$next[0:0]$7989 1'0 + assign $2\mul_op__rc__rc$next[0:0]$7993 1'0 + assign $2\mul_op__rc__ok$next[0:0]$7992 1'0 + assign $2\mul_op__oe__oe$next[0:0]$7990 1'0 + assign $2\mul_op__oe__ok$next[0:0]$7991 1'0 + case + assign $2\mul_op__imm_data__data$next[63:0]$7988 $1\mul_op__imm_data__data$next[63:0]$7977 + assign $2\mul_op__imm_data__ok$next[0:0]$7989 $1\mul_op__imm_data__ok$next[0:0]$7978 + assign $2\mul_op__oe__oe$next[0:0]$7990 $1\mul_op__oe__oe$next[0:0]$7983 + assign $2\mul_op__oe__ok$next[0:0]$7991 $1\mul_op__oe__ok$next[0:0]$7984 + assign $2\mul_op__rc__ok$next[0:0]$7992 $1\mul_op__rc__ok$next[0:0]$7985 + assign $2\mul_op__rc__rc$next[0:0]$7993 $1\mul_op__rc__rc$next[0:0]$7986 + end + sync always + update \mul_op__fn_unit$next $0\mul_op__fn_unit$next[12:0]$7964 + update \mul_op__imm_data__data$next $0\mul_op__imm_data__data$next[63:0]$7965 + update \mul_op__imm_data__ok$next $0\mul_op__imm_data__ok$next[0:0]$7966 + update \mul_op__insn$next $0\mul_op__insn$next[31:0]$7967 + update \mul_op__insn_type$next $0\mul_op__insn_type$next[6:0]$7968 + update \mul_op__is_32bit$next $0\mul_op__is_32bit$next[0:0]$7969 + update \mul_op__is_signed$next $0\mul_op__is_signed$next[0:0]$7970 + update \mul_op__oe__oe$next $0\mul_op__oe__oe$next[0:0]$7971 + update \mul_op__oe__ok$next $0\mul_op__oe__ok$next[0:0]$7972 + update \mul_op__rc__ok$next $0\mul_op__rc__ok$next[0:0]$7973 + update \mul_op__rc__rc$next $0\mul_op__rc__rc$next[0:0]$7974 + update \mul_op__write_cr0$next $0\mul_op__write_cr0$next[0:0]$7975 + end + attribute \src "libresoc.v:157310.3-157322.6" + process $proc$libresoc.v:157310$7994 + assign { } { } + assign { } { } + assign $0\ra$next[63:0]$7995 $1\ra$next[63:0]$7996 + attribute \src "libresoc.v:157311.5-157311.29" + switch \initial + attribute \src "libresoc.v:157311.9-157311.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\ra$next[63:0]$7996 \ra$65 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\ra$next[63:0]$7996 \ra$65 + case + assign $1\ra$next[63:0]$7996 \ra + end + sync always + update \ra$next $0\ra$next[63:0]$7995 + end + attribute \src "libresoc.v:157323.3-157335.6" + process $proc$libresoc.v:157323$7997 + assign { } { } + assign { } { } + assign $0\rb$next[63:0]$7998 $1\rb$next[63:0]$7999 + attribute \src "libresoc.v:157324.5-157324.29" + switch \initial + attribute \src "libresoc.v:157324.9-157324.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\rb$next[63:0]$7999 \rb$66 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\rb$next[63:0]$7999 \rb$66 + case + assign $1\rb$next[63:0]$7999 \rb + end + sync always + update \rb$next $0\rb$next[63:0]$7998 + end + attribute \src "libresoc.v:157336.3-157348.6" + process $proc$libresoc.v:157336$8000 + assign { } { } + assign { } { } + assign $0\xer_so$next[0:0]$8001 $1\xer_so$next[0:0]$8002 + attribute \src "libresoc.v:157337.5-157337.29" + switch \initial + attribute \src "libresoc.v:157337.9-157337.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\xer_so$next[0:0]$8002 \xer_so$67 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\xer_so$next[0:0]$8002 \xer_so$67 + case + assign $1\xer_so$next[0:0]$8002 \xer_so + end + sync always + update \xer_so$next $0\xer_so$next[0:0]$8001 + end + attribute \src "libresoc.v:157349.3-157361.6" + process $proc$libresoc.v:157349$8003 + assign { } { } + assign { } { } + assign $0\neg_res$next[0:0]$8004 $1\neg_res$next[0:0]$8005 + attribute \src "libresoc.v:157350.5-157350.29" + switch \initial + attribute \src "libresoc.v:157350.9-157350.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\neg_res$next[0:0]$8005 \neg_res$68 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\neg_res$next[0:0]$8005 \neg_res$68 + case + assign $1\neg_res$next[0:0]$8005 \neg_res + end + sync always + update \neg_res$next $0\neg_res$next[0:0]$8004 + end + attribute \src "libresoc.v:157362.3-157374.6" + process $proc$libresoc.v:157362$8006 + assign { } { } + assign { } { } + assign $0\neg_res32$next[0:0]$8007 $1\neg_res32$next[0:0]$8008 + attribute \src "libresoc.v:157363.5-157363.29" + switch \initial + attribute \src "libresoc.v:157363.9-157363.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\neg_res32$next[0:0]$8008 \neg_res32$69 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\neg_res32$next[0:0]$8008 \neg_res32$69 + case + assign $1\neg_res32$next[0:0]$8008 \neg_res32 + end + sync always + update \neg_res32$next $0\neg_res32$next[0:0]$8007 + end + connect \$50 $and$libresoc.v:157126$7936_Y + connect \p_ready_o \n_i_rdy_data + connect \n_valid_o \r_busy + connect \neg_res32$69 \mul1_neg_res32 + connect \neg_res$68 \mul1_neg_res + connect \xer_so$67 \mul1_xer_so$48 + connect \rb$66 \mul1_rb$47 + connect \ra$65 \mul1_ra$46 + connect { \mul_op__insn$64 \mul_op__is_signed$63 \mul_op__is_32bit$62 \mul_op__write_cr0$61 \mul_op__oe__ok$60 \mul_op__oe__oe$59 \mul_op__rc__ok$58 \mul_op__rc__rc$57 \mul_op__imm_data__ok$56 \mul_op__imm_data__data$55 \mul_op__fn_unit$54 \mul_op__insn_type$53 } { \mul1_mul_op__insn$45 \mul1_mul_op__is_signed$44 \mul1_mul_op__is_32bit$43 \mul1_mul_op__write_cr0$42 \mul1_mul_op__oe__ok$41 \mul1_mul_op__oe__oe$40 \mul1_mul_op__rc__ok$39 \mul1_mul_op__rc__rc$38 \mul1_mul_op__imm_data__ok$37 \mul1_mul_op__imm_data__data$36 \mul1_mul_op__fn_unit$35 \mul1_mul_op__insn_type$34 } + connect \muxid$52 \mul1_muxid$33 + connect \p_valid_i_p_ready_o \$50 + connect \n_i_rdy_data \n_ready_i + connect \p_valid_i$49 \p_valid_i + connect \mul1_xer_so \input_xer_so$32 + connect \mul1_rb \input_rb$31 + connect \mul1_ra \input_ra$30 + connect { \mul1_mul_op__insn \mul1_mul_op__is_signed \mul1_mul_op__is_32bit \mul1_mul_op__write_cr0 \mul1_mul_op__oe__ok \mul1_mul_op__oe__oe \mul1_mul_op__rc__ok \mul1_mul_op__rc__rc \mul1_mul_op__imm_data__ok \mul1_mul_op__imm_data__data \mul1_mul_op__fn_unit \mul1_mul_op__insn_type } { \input_mul_op__insn$29 \input_mul_op__is_signed$28 \input_mul_op__is_32bit$27 \input_mul_op__write_cr0$26 \input_mul_op__oe__ok$25 \input_mul_op__oe__oe$24 \input_mul_op__rc__ok$23 \input_mul_op__rc__rc$22 \input_mul_op__imm_data__ok$21 \input_mul_op__imm_data__data$20 \input_mul_op__fn_unit$19 \input_mul_op__insn_type$18 } + connect \mul1_muxid \input_muxid$17 + connect \input_xer_so \xer_so$16 + connect \input_rb \rb$15 + connect \input_ra \ra$14 + connect { \input_mul_op__insn \input_mul_op__is_signed \input_mul_op__is_32bit \input_mul_op__write_cr0 \input_mul_op__oe__ok \input_mul_op__oe__oe \input_mul_op__rc__ok \input_mul_op__rc__rc \input_mul_op__imm_data__ok \input_mul_op__imm_data__data \input_mul_op__fn_unit \input_mul_op__insn_type } { \mul_op__insn$13 \mul_op__is_signed$12 \mul_op__is_32bit$11 \mul_op__write_cr0$10 \mul_op__oe__ok$9 \mul_op__oe__oe$8 \mul_op__rc__ok$7 \mul_op__rc__rc$6 \mul_op__imm_data__ok$5 \mul_op__imm_data__data$4 \mul_op__fn_unit$3 \mul_op__insn_type$2 } + connect \input_muxid \muxid$1 +end +attribute \src "libresoc.v:157401.1-158311.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe2" +attribute \generator "nMigen" +module \mul_pipe2 + attribute \src "libresoc.v:157402.7-157402.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:158205.3-158240.6" + wire width 13 $0\mul_op__fn_unit$3$next[12:0]$8072 + attribute \src "libresoc.v:158103.3-158104.53" + wire width 13 $0\mul_op__fn_unit$3[12:0]$8040 + attribute \src "libresoc.v:157687.14-157687.44" + wire width 13 $0\mul_op__fn_unit$3[12:0]$8116 + attribute \src "libresoc.v:158205.3-158240.6" + wire width 64 $0\mul_op__imm_data__data$4$next[63:0]$8073 + attribute \src "libresoc.v:158105.3-158106.67" + wire width 64 $0\mul_op__imm_data__data$4[63:0]$8042 + attribute \src "libresoc.v:157712.14-157712.63" + wire width 64 $0\mul_op__imm_data__data$4[63:0]$8118 + attribute \src "libresoc.v:158205.3-158240.6" + wire $0\mul_op__imm_data__ok$5$next[0:0]$8074 + attribute \src "libresoc.v:158107.3-158108.63" + wire $0\mul_op__imm_data__ok$5[0:0]$8044 + attribute \src "libresoc.v:157721.7-157721.38" + wire $0\mul_op__imm_data__ok$5[0:0]$8120 + attribute \src "libresoc.v:158205.3-158240.6" + wire width 32 $0\mul_op__insn$13$next[31:0]$8075 + attribute \src "libresoc.v:158123.3-158124.49" + wire width 32 $0\mul_op__insn$13[31:0]$8060 + attribute \src "libresoc.v:157728.14-157728.39" + wire width 32 $0\mul_op__insn$13[31:0]$8122 + attribute \src "libresoc.v:158205.3-158240.6" + wire width 7 $0\mul_op__insn_type$2$next[6:0]$8076 + attribute \src "libresoc.v:158101.3-158102.57" + wire width 7 $0\mul_op__insn_type$2[6:0]$8038 + attribute \src "libresoc.v:157885.13-157885.42" + wire width 7 $0\mul_op__insn_type$2[6:0]$8124 + attribute \src "libresoc.v:158205.3-158240.6" + wire $0\mul_op__is_32bit$11$next[0:0]$8077 + attribute \src "libresoc.v:158119.3-158120.57" + wire $0\mul_op__is_32bit$11[0:0]$8056 + attribute \src "libresoc.v:157968.7-157968.35" + wire $0\mul_op__is_32bit$11[0:0]$8126 + attribute \src "libresoc.v:158205.3-158240.6" + wire $0\mul_op__is_signed$12$next[0:0]$8078 + attribute \src "libresoc.v:158121.3-158122.59" + wire $0\mul_op__is_signed$12[0:0]$8058 + attribute \src "libresoc.v:157977.7-157977.36" + wire $0\mul_op__is_signed$12[0:0]$8128 + attribute \src "libresoc.v:158205.3-158240.6" + wire $0\mul_op__oe__oe$8$next[0:0]$8079 + attribute \src "libresoc.v:158113.3-158114.51" + wire $0\mul_op__oe__oe$8[0:0]$8050 + attribute \src "libresoc.v:157988.7-157988.32" + wire $0\mul_op__oe__oe$8[0:0]$8130 + attribute \src "libresoc.v:158205.3-158240.6" + wire $0\mul_op__oe__ok$9$next[0:0]$8080 + attribute \src "libresoc.v:158115.3-158116.51" + wire $0\mul_op__oe__ok$9[0:0]$8052 + attribute \src "libresoc.v:157997.7-157997.32" + wire $0\mul_op__oe__ok$9[0:0]$8132 + attribute \src "libresoc.v:158205.3-158240.6" + wire $0\mul_op__rc__ok$7$next[0:0]$8081 + attribute \src "libresoc.v:158111.3-158112.51" + wire $0\mul_op__rc__ok$7[0:0]$8048 + attribute \src "libresoc.v:158006.7-158006.32" + wire $0\mul_op__rc__ok$7[0:0]$8134 + attribute \src "libresoc.v:158205.3-158240.6" + wire $0\mul_op__rc__rc$6$next[0:0]$8082 + attribute \src "libresoc.v:158109.3-158110.51" + wire $0\mul_op__rc__rc$6[0:0]$8046 + attribute \src "libresoc.v:158015.7-158015.32" + wire $0\mul_op__rc__rc$6[0:0]$8136 + attribute \src "libresoc.v:158205.3-158240.6" + wire $0\mul_op__write_cr0$10$next[0:0]$8083 + attribute \src "libresoc.v:158117.3-158118.59" + wire $0\mul_op__write_cr0$10[0:0]$8054 + attribute \src "libresoc.v:158022.7-158022.36" + wire $0\mul_op__write_cr0$10[0:0]$8138 + attribute \src "libresoc.v:158192.3-158204.6" + wire width 2 $0\muxid$1$next[1:0]$8069 + attribute \src "libresoc.v:158125.3-158126.33" + wire width 2 $0\muxid$1[1:0]$8062 + attribute \src "libresoc.v:158031.13-158031.29" + wire width 2 $0\muxid$1[1:0]$8140 + attribute \src "libresoc.v:158267.3-158279.6" + wire $0\neg_res$15$next[0:0]$8109 + attribute \src "libresoc.v:158095.3-158096.39" + wire $0\neg_res$15[0:0]$8033 + attribute \src "libresoc.v:158046.7-158046.26" + wire $0\neg_res$15[0:0]$8142 + attribute \src "libresoc.v:158280.3-158292.6" + wire $0\neg_res32$16$next[0:0]$8112 + attribute \src "libresoc.v:158093.3-158094.43" + wire $0\neg_res32$16[0:0]$8031 + attribute \src "libresoc.v:158055.7-158055.28" + wire $0\neg_res32$16[0:0]$8144 + attribute \src "libresoc.v:158241.3-158253.6" + wire width 129 $0\o$next[128:0]$8103 + attribute \src "libresoc.v:158099.3-158100.19" + wire width 129 $0\o[128:0] + attribute \src "libresoc.v:158174.3-158191.6" + wire $0\r_busy$next[0:0]$8065 + attribute \src "libresoc.v:158127.3-158128.29" + wire $0\r_busy[0:0] + attribute \src "libresoc.v:158254.3-158266.6" + wire $0\xer_so$14$next[0:0]$8106 + attribute \src "libresoc.v:158097.3-158098.37" + wire $0\xer_so$14[0:0]$8035 + attribute \src "libresoc.v:158087.7-158087.25" + wire $0\xer_so$14[0:0]$8148 + attribute \src "libresoc.v:158205.3-158240.6" + wire width 13 $1\mul_op__fn_unit$3$next[12:0]$8084 + attribute \src "libresoc.v:158205.3-158240.6" + wire width 64 $1\mul_op__imm_data__data$4$next[63:0]$8085 + attribute \src "libresoc.v:158205.3-158240.6" + wire $1\mul_op__imm_data__ok$5$next[0:0]$8086 + attribute \src "libresoc.v:158205.3-158240.6" + wire width 32 $1\mul_op__insn$13$next[31:0]$8087 + attribute \src "libresoc.v:158205.3-158240.6" + wire width 7 $1\mul_op__insn_type$2$next[6:0]$8088 + attribute \src "libresoc.v:158205.3-158240.6" + wire $1\mul_op__is_32bit$11$next[0:0]$8089 + attribute \src "libresoc.v:158205.3-158240.6" + wire $1\mul_op__is_signed$12$next[0:0]$8090 + attribute \src "libresoc.v:158205.3-158240.6" + wire $1\mul_op__oe__oe$8$next[0:0]$8091 + attribute \src "libresoc.v:158205.3-158240.6" + wire $1\mul_op__oe__ok$9$next[0:0]$8092 + attribute \src "libresoc.v:158205.3-158240.6" + wire $1\mul_op__rc__ok$7$next[0:0]$8093 + attribute \src "libresoc.v:158205.3-158240.6" + wire $1\mul_op__rc__rc$6$next[0:0]$8094 + attribute \src "libresoc.v:158205.3-158240.6" + wire $1\mul_op__write_cr0$10$next[0:0]$8095 + attribute \src "libresoc.v:158192.3-158204.6" + wire width 2 $1\muxid$1$next[1:0]$8070 + attribute \src "libresoc.v:158267.3-158279.6" + wire $1\neg_res$15$next[0:0]$8110 + attribute \src "libresoc.v:158280.3-158292.6" + wire $1\neg_res32$16$next[0:0]$8113 + attribute \src "libresoc.v:158241.3-158253.6" + wire width 129 $1\o$next[128:0]$8104 + attribute \src "libresoc.v:158062.15-158062.57" + wire width 129 $1\o[128:0] + attribute \src "libresoc.v:158174.3-158191.6" + wire $1\r_busy$next[0:0]$8066 + attribute \src "libresoc.v:158076.7-158076.20" + wire $1\r_busy[0:0] + attribute \src "libresoc.v:158254.3-158266.6" + wire $1\xer_so$14$next[0:0]$8107 + attribute \src "libresoc.v:158205.3-158240.6" + wire width 64 $2\mul_op__imm_data__data$4$next[63:0]$8096 + attribute \src "libresoc.v:158205.3-158240.6" + wire $2\mul_op__imm_data__ok$5$next[0:0]$8097 + attribute \src "libresoc.v:158205.3-158240.6" + wire $2\mul_op__oe__oe$8$next[0:0]$8098 + attribute \src "libresoc.v:158205.3-158240.6" + wire $2\mul_op__oe__ok$9$next[0:0]$8099 + attribute \src "libresoc.v:158205.3-158240.6" + wire $2\mul_op__rc__ok$7$next[0:0]$8100 + attribute \src "libresoc.v:158205.3-158240.6" + wire $2\mul_op__rc__rc$6$next[0:0]$8101 + attribute \src "libresoc.v:158174.3-158191.6" + wire $2\r_busy$next[0:0]$8067 + attribute \src "libresoc.v:158092.18-158092.118" + wire $and$libresoc.v:158092$8029_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" + wire \$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 41 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 1 \coresync_rst + attribute \src "libresoc.v:157402.7-157402.15" + wire \initial + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \mul2_mul_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \mul2_mul_op__fn_unit$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \mul2_mul_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \mul2_mul_op__imm_data__data$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul2_mul_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul2_mul_op__imm_data__ok$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \mul2_mul_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \mul2_mul_op__insn$29 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \mul2_mul_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \mul2_mul_op__insn_type$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul2_mul_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul2_mul_op__is_32bit$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul2_mul_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul2_mul_op__is_signed$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul2_mul_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul2_mul_op__oe__oe$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul2_mul_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul2_mul_op__oe__ok$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul2_mul_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul2_mul_op__rc__ok$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul2_mul_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul2_mul_op__rc__rc$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul2_mul_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul2_mul_op__write_cr0$26 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \mul2_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \mul2_muxid$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" + wire \mul2_neg_res + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" + wire \mul2_neg_res$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" + wire \mul2_neg_res32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24" + wire \mul2_neg_res32$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 129 \mul2_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \mul2_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \mul2_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \mul2_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \mul2_xer_so$30 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 input 6 \mul_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 output 26 \mul_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \mul_op__fn_unit$3$next + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \mul_op__fn_unit$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 7 \mul_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \mul_op__imm_data__data$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 27 \mul_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \mul_op__imm_data__data$4$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \mul_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__imm_data__ok$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 28 \mul_op__imm_data__ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__imm_data__ok$5$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 16 \mul_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 36 \mul_op__insn$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \mul_op__insn$13$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \mul_op__insn$48 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 5 \mul_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 25 \mul_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \mul_op__insn_type$2$next + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \mul_op__insn_type$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \mul_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 34 \mul_op__is_32bit$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__is_32bit$11$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__is_32bit$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 15 \mul_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 35 \mul_op__is_signed$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__is_signed$12$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__is_signed$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 11 \mul_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__oe__oe$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 31 \mul_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__oe__oe$8$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \mul_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__oe__ok$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 32 \mul_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__oe__ok$9$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \mul_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__rc__ok$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 30 \mul_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__rc__ok$7$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \mul_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__rc__rc$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 29 \mul_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__rc__rc$6$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \mul_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 33 \mul_op__write_cr0$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__write_cr0$10$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__write_cr0$45 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 input 4 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 output 24 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid$1$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid$36 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + wire \n_i_rdy_data + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire input 23 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire output 22 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" + wire input 20 \neg_res + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" + wire output 39 \neg_res$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" + wire \neg_res$15$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" + wire \neg_res$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" + wire input 21 \neg_res32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24" + wire output 40 \neg_res32$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24" + wire \neg_res32$16$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24" + wire \neg_res32$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 129 output 37 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 129 \o$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 129 \o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" + wire output 3 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" + wire input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" + wire \p_valid_i$33 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" + wire \p_valid_i_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire \r_busy$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 17 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 18 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 19 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire output 38 \xer_so$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \xer_so$14$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \xer_so$50 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" + cell $and $and$libresoc.v:158092$8029 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i$33 + connect \B \p_ready_o + connect \Y $and$libresoc.v:158092$8029_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:158129.8-158165.4" + cell \mul2 \mul2 + connect \mul_op__fn_unit \mul2_mul_op__fn_unit + connect \mul_op__fn_unit$3 \mul2_mul_op__fn_unit$19 + connect \mul_op__imm_data__data \mul2_mul_op__imm_data__data + connect \mul_op__imm_data__data$4 \mul2_mul_op__imm_data__data$20 + connect \mul_op__imm_data__ok \mul2_mul_op__imm_data__ok + connect \mul_op__imm_data__ok$5 \mul2_mul_op__imm_data__ok$21 + connect \mul_op__insn \mul2_mul_op__insn + connect \mul_op__insn$13 \mul2_mul_op__insn$29 + connect \mul_op__insn_type \mul2_mul_op__insn_type + connect \mul_op__insn_type$2 \mul2_mul_op__insn_type$18 + connect \mul_op__is_32bit \mul2_mul_op__is_32bit + connect \mul_op__is_32bit$11 \mul2_mul_op__is_32bit$27 + connect \mul_op__is_signed \mul2_mul_op__is_signed + connect \mul_op__is_signed$12 \mul2_mul_op__is_signed$28 + connect \mul_op__oe__oe \mul2_mul_op__oe__oe + connect \mul_op__oe__oe$8 \mul2_mul_op__oe__oe$24 + connect \mul_op__oe__ok \mul2_mul_op__oe__ok + connect \mul_op__oe__ok$9 \mul2_mul_op__oe__ok$25 + connect \mul_op__rc__ok \mul2_mul_op__rc__ok + connect \mul_op__rc__ok$7 \mul2_mul_op__rc__ok$23 + connect \mul_op__rc__rc \mul2_mul_op__rc__rc + connect \mul_op__rc__rc$6 \mul2_mul_op__rc__rc$22 + connect \mul_op__write_cr0 \mul2_mul_op__write_cr0 + connect \mul_op__write_cr0$10 \mul2_mul_op__write_cr0$26 + connect \muxid \mul2_muxid + connect \muxid$1 \mul2_muxid$17 + connect \neg_res \mul2_neg_res + connect \neg_res$15 \mul2_neg_res$31 + connect \neg_res32 \mul2_neg_res32 + connect \neg_res32$16 \mul2_neg_res32$32 + connect \o \mul2_o + connect \ra \mul2_ra + connect \rb \mul2_rb + connect \xer_so \mul2_xer_so + connect \xer_so$14 \mul2_xer_so$30 + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:158166.10-158169.4" + cell \n$97 \n + connect \n_ready_i \n_ready_i + connect \n_valid_o \n_valid_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:158170.10-158173.4" + cell \p$96 \p + connect \p_ready_o \p_ready_o + connect \p_valid_i \p_valid_i + end + attribute \src "libresoc.v:157402.7-157402.20" + process $proc$libresoc.v:157402$8114 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:157687.14-157687.44" + process $proc$libresoc.v:157687$8115 + assign { } { } + assign $0\mul_op__fn_unit$3[12:0]$8116 13'0000000000000 + sync always + sync init + update \mul_op__fn_unit$3 $0\mul_op__fn_unit$3[12:0]$8116 + end + attribute \src "libresoc.v:157712.14-157712.63" + process $proc$libresoc.v:157712$8117 + assign { } { } + assign $0\mul_op__imm_data__data$4[63:0]$8118 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \mul_op__imm_data__data$4 $0\mul_op__imm_data__data$4[63:0]$8118 + end + attribute \src "libresoc.v:157721.7-157721.38" + process $proc$libresoc.v:157721$8119 + assign { } { } + assign $0\mul_op__imm_data__ok$5[0:0]$8120 1'0 + sync always + sync init + update \mul_op__imm_data__ok$5 $0\mul_op__imm_data__ok$5[0:0]$8120 + end + attribute \src "libresoc.v:157728.14-157728.39" + process $proc$libresoc.v:157728$8121 + assign { } { } + assign $0\mul_op__insn$13[31:0]$8122 0 + sync always + sync init + update \mul_op__insn$13 $0\mul_op__insn$13[31:0]$8122 + end + attribute \src "libresoc.v:157885.13-157885.42" + process $proc$libresoc.v:157885$8123 + assign { } { } + assign $0\mul_op__insn_type$2[6:0]$8124 7'0000000 + sync always + sync init + update \mul_op__insn_type$2 $0\mul_op__insn_type$2[6:0]$8124 + end + attribute \src "libresoc.v:157968.7-157968.35" + process $proc$libresoc.v:157968$8125 + assign { } { } + assign $0\mul_op__is_32bit$11[0:0]$8126 1'0 + sync always + sync init + update \mul_op__is_32bit$11 $0\mul_op__is_32bit$11[0:0]$8126 + end + attribute \src "libresoc.v:157977.7-157977.36" + process $proc$libresoc.v:157977$8127 + assign { } { } + assign $0\mul_op__is_signed$12[0:0]$8128 1'0 + sync always + sync init + update \mul_op__is_signed$12 $0\mul_op__is_signed$12[0:0]$8128 + end + attribute \src "libresoc.v:157988.7-157988.32" + process $proc$libresoc.v:157988$8129 + assign { } { } + assign $0\mul_op__oe__oe$8[0:0]$8130 1'0 + sync always + sync init + update \mul_op__oe__oe$8 $0\mul_op__oe__oe$8[0:0]$8130 + end + attribute \src "libresoc.v:157997.7-157997.32" + process $proc$libresoc.v:157997$8131 + assign { } { } + assign $0\mul_op__oe__ok$9[0:0]$8132 1'0 + sync always + sync init + update \mul_op__oe__ok$9 $0\mul_op__oe__ok$9[0:0]$8132 + end + attribute \src "libresoc.v:158006.7-158006.32" + process $proc$libresoc.v:158006$8133 + assign { } { } + assign $0\mul_op__rc__ok$7[0:0]$8134 1'0 + sync always + sync init + update \mul_op__rc__ok$7 $0\mul_op__rc__ok$7[0:0]$8134 + end + attribute \src "libresoc.v:158015.7-158015.32" + process $proc$libresoc.v:158015$8135 + assign { } { } + assign $0\mul_op__rc__rc$6[0:0]$8136 1'0 + sync always + sync init + update \mul_op__rc__rc$6 $0\mul_op__rc__rc$6[0:0]$8136 + end + attribute \src "libresoc.v:158022.7-158022.36" + process $proc$libresoc.v:158022$8137 + assign { } { } + assign $0\mul_op__write_cr0$10[0:0]$8138 1'0 + sync always + sync init + update \mul_op__write_cr0$10 $0\mul_op__write_cr0$10[0:0]$8138 + end + attribute \src "libresoc.v:158031.13-158031.29" + process $proc$libresoc.v:158031$8139 + assign { } { } + assign $0\muxid$1[1:0]$8140 2'00 + sync always + sync init + update \muxid$1 $0\muxid$1[1:0]$8140 + end + attribute \src "libresoc.v:158046.7-158046.26" + process $proc$libresoc.v:158046$8141 + assign { } { } + assign $0\neg_res$15[0:0]$8142 1'0 + sync always + sync init + update \neg_res$15 $0\neg_res$15[0:0]$8142 + end + attribute \src "libresoc.v:158055.7-158055.28" + process $proc$libresoc.v:158055$8143 + assign { } { } + assign $0\neg_res32$16[0:0]$8144 1'0 + sync always + sync init + update \neg_res32$16 $0\neg_res32$16[0:0]$8144 + end + attribute \src "libresoc.v:158062.15-158062.57" + process $proc$libresoc.v:158062$8145 + assign { } { } + assign $1\o[128:0] 129'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \o $1\o[128:0] + end + attribute \src "libresoc.v:158076.7-158076.20" + process $proc$libresoc.v:158076$8146 + assign { } { } + assign $1\r_busy[0:0] 1'0 + sync always + sync init + update \r_busy $1\r_busy[0:0] + end + attribute \src "libresoc.v:158087.7-158087.25" + process $proc$libresoc.v:158087$8147 + assign { } { } + assign $0\xer_so$14[0:0]$8148 1'0 + sync always + sync init + update \xer_so$14 $0\xer_so$14[0:0]$8148 + end + attribute \src "libresoc.v:158093.3-158094.43" + process $proc$libresoc.v:158093$8030 + assign { } { } + assign $0\neg_res32$16[0:0]$8031 \neg_res32$16$next + sync posedge \coresync_clk + update \neg_res32$16 $0\neg_res32$16[0:0]$8031 + end + attribute \src "libresoc.v:158095.3-158096.39" + process $proc$libresoc.v:158095$8032 + assign { } { } + assign $0\neg_res$15[0:0]$8033 \neg_res$15$next + sync posedge \coresync_clk + update \neg_res$15 $0\neg_res$15[0:0]$8033 + end + attribute \src "libresoc.v:158097.3-158098.37" + process $proc$libresoc.v:158097$8034 + assign { } { } + assign $0\xer_so$14[0:0]$8035 \xer_so$14$next + sync posedge \coresync_clk + update \xer_so$14 $0\xer_so$14[0:0]$8035 + end + attribute \src "libresoc.v:158099.3-158100.19" + process $proc$libresoc.v:158099$8036 + assign { } { } + assign $0\o[128:0] \o$next + sync posedge \coresync_clk + update \o $0\o[128:0] + end + attribute \src "libresoc.v:158101.3-158102.57" + process $proc$libresoc.v:158101$8037 + assign { } { } + assign $0\mul_op__insn_type$2[6:0]$8038 \mul_op__insn_type$2$next + sync posedge \coresync_clk + update \mul_op__insn_type$2 $0\mul_op__insn_type$2[6:0]$8038 + end + attribute \src "libresoc.v:158103.3-158104.53" + process $proc$libresoc.v:158103$8039 + assign { } { } + assign $0\mul_op__fn_unit$3[12:0]$8040 \mul_op__fn_unit$3$next + sync posedge \coresync_clk + update \mul_op__fn_unit$3 $0\mul_op__fn_unit$3[12:0]$8040 + end + attribute \src "libresoc.v:158105.3-158106.67" + process $proc$libresoc.v:158105$8041 + assign { } { } + assign $0\mul_op__imm_data__data$4[63:0]$8042 \mul_op__imm_data__data$4$next + sync posedge \coresync_clk + update \mul_op__imm_data__data$4 $0\mul_op__imm_data__data$4[63:0]$8042 + end + attribute \src "libresoc.v:158107.3-158108.63" + process $proc$libresoc.v:158107$8043 + assign { } { } + assign $0\mul_op__imm_data__ok$5[0:0]$8044 \mul_op__imm_data__ok$5$next + sync posedge \coresync_clk + update \mul_op__imm_data__ok$5 $0\mul_op__imm_data__ok$5[0:0]$8044 + end + attribute \src "libresoc.v:158109.3-158110.51" + process $proc$libresoc.v:158109$8045 + assign { } { } + assign $0\mul_op__rc__rc$6[0:0]$8046 \mul_op__rc__rc$6$next + sync posedge \coresync_clk + update \mul_op__rc__rc$6 $0\mul_op__rc__rc$6[0:0]$8046 + end + attribute \src "libresoc.v:158111.3-158112.51" + process $proc$libresoc.v:158111$8047 + assign { } { } + assign $0\mul_op__rc__ok$7[0:0]$8048 \mul_op__rc__ok$7$next + sync posedge \coresync_clk + update \mul_op__rc__ok$7 $0\mul_op__rc__ok$7[0:0]$8048 + end + attribute \src "libresoc.v:158113.3-158114.51" + process $proc$libresoc.v:158113$8049 + assign { } { } + assign $0\mul_op__oe__oe$8[0:0]$8050 \mul_op__oe__oe$8$next + sync posedge \coresync_clk + update \mul_op__oe__oe$8 $0\mul_op__oe__oe$8[0:0]$8050 + end + attribute \src "libresoc.v:158115.3-158116.51" + process $proc$libresoc.v:158115$8051 + assign { } { } + assign $0\mul_op__oe__ok$9[0:0]$8052 \mul_op__oe__ok$9$next + sync posedge \coresync_clk + update \mul_op__oe__ok$9 $0\mul_op__oe__ok$9[0:0]$8052 + end + attribute \src "libresoc.v:158117.3-158118.59" + process $proc$libresoc.v:158117$8053 + assign { } { } + assign $0\mul_op__write_cr0$10[0:0]$8054 \mul_op__write_cr0$10$next + sync posedge \coresync_clk + update \mul_op__write_cr0$10 $0\mul_op__write_cr0$10[0:0]$8054 + end + attribute \src "libresoc.v:158119.3-158120.57" + process $proc$libresoc.v:158119$8055 + assign { } { } + assign $0\mul_op__is_32bit$11[0:0]$8056 \mul_op__is_32bit$11$next + sync posedge \coresync_clk + update \mul_op__is_32bit$11 $0\mul_op__is_32bit$11[0:0]$8056 + end + attribute \src "libresoc.v:158121.3-158122.59" + process $proc$libresoc.v:158121$8057 + assign { } { } + assign $0\mul_op__is_signed$12[0:0]$8058 \mul_op__is_signed$12$next + sync posedge \coresync_clk + update \mul_op__is_signed$12 $0\mul_op__is_signed$12[0:0]$8058 + end + attribute \src "libresoc.v:158123.3-158124.49" + process $proc$libresoc.v:158123$8059 + assign { } { } + assign $0\mul_op__insn$13[31:0]$8060 \mul_op__insn$13$next + sync posedge \coresync_clk + update \mul_op__insn$13 $0\mul_op__insn$13[31:0]$8060 + end + attribute \src "libresoc.v:158125.3-158126.33" + process $proc$libresoc.v:158125$8061 + assign { } { } + assign $0\muxid$1[1:0]$8062 \muxid$1$next + sync posedge \coresync_clk + update \muxid$1 $0\muxid$1[1:0]$8062 + end + attribute \src "libresoc.v:158127.3-158128.29" + process $proc$libresoc.v:158127$8063 + assign { } { } + assign $0\r_busy[0:0] \r_busy$next + sync posedge \coresync_clk + update \r_busy $0\r_busy[0:0] + end + attribute \src "libresoc.v:158174.3-158191.6" + process $proc$libresoc.v:158174$8064 + assign { } { } + assign { } { } + assign { } { } + assign $0\r_busy$next[0:0]$8065 $2\r_busy$next[0:0]$8067 + attribute \src "libresoc.v:158175.5-158175.29" + switch \initial + attribute \src "libresoc.v:158175.9-158175.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\r_busy$next[0:0]$8066 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\r_busy$next[0:0]$8066 1'0 + case + assign $1\r_busy$next[0:0]$8066 \r_busy + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r_busy$next[0:0]$8067 1'0 + case + assign $2\r_busy$next[0:0]$8067 $1\r_busy$next[0:0]$8066 + end + sync always + update \r_busy$next $0\r_busy$next[0:0]$8065 + end + attribute \src "libresoc.v:158192.3-158204.6" + process $proc$libresoc.v:158192$8068 + assign { } { } + assign { } { } + assign $0\muxid$1$next[1:0]$8069 $1\muxid$1$next[1:0]$8070 + attribute \src "libresoc.v:158193.5-158193.29" + switch \initial + attribute \src "libresoc.v:158193.9-158193.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\muxid$1$next[1:0]$8070 \muxid$36 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\muxid$1$next[1:0]$8070 \muxid$36 + case + assign $1\muxid$1$next[1:0]$8070 \muxid$1 + end + sync always + update \muxid$1$next $0\muxid$1$next[1:0]$8069 + end + attribute \src "libresoc.v:158205.3-158240.6" + process $proc$libresoc.v:158205$8071 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\mul_op__fn_unit$3$next[12:0]$8072 $1\mul_op__fn_unit$3$next[12:0]$8084 + assign { } { } + assign { } { } + assign $0\mul_op__insn$13$next[31:0]$8075 $1\mul_op__insn$13$next[31:0]$8087 + assign $0\mul_op__insn_type$2$next[6:0]$8076 $1\mul_op__insn_type$2$next[6:0]$8088 + assign $0\mul_op__is_32bit$11$next[0:0]$8077 $1\mul_op__is_32bit$11$next[0:0]$8089 + assign $0\mul_op__is_signed$12$next[0:0]$8078 $1\mul_op__is_signed$12$next[0:0]$8090 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\mul_op__write_cr0$10$next[0:0]$8083 $1\mul_op__write_cr0$10$next[0:0]$8095 + assign $0\mul_op__imm_data__data$4$next[63:0]$8073 $2\mul_op__imm_data__data$4$next[63:0]$8096 + assign $0\mul_op__imm_data__ok$5$next[0:0]$8074 $2\mul_op__imm_data__ok$5$next[0:0]$8097 + assign $0\mul_op__oe__oe$8$next[0:0]$8079 $2\mul_op__oe__oe$8$next[0:0]$8098 + assign $0\mul_op__oe__ok$9$next[0:0]$8080 $2\mul_op__oe__ok$9$next[0:0]$8099 + assign $0\mul_op__rc__ok$7$next[0:0]$8081 $2\mul_op__rc__ok$7$next[0:0]$8100 + assign $0\mul_op__rc__rc$6$next[0:0]$8082 $2\mul_op__rc__rc$6$next[0:0]$8101 + attribute \src "libresoc.v:158206.5-158206.29" + switch \initial + attribute \src "libresoc.v:158206.9-158206.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\mul_op__insn$13$next[31:0]$8087 $1\mul_op__is_signed$12$next[0:0]$8090 $1\mul_op__is_32bit$11$next[0:0]$8089 $1\mul_op__write_cr0$10$next[0:0]$8095 $1\mul_op__oe__ok$9$next[0:0]$8092 $1\mul_op__oe__oe$8$next[0:0]$8091 $1\mul_op__rc__ok$7$next[0:0]$8093 $1\mul_op__rc__rc$6$next[0:0]$8094 $1\mul_op__imm_data__ok$5$next[0:0]$8086 $1\mul_op__imm_data__data$4$next[63:0]$8085 $1\mul_op__fn_unit$3$next[12:0]$8084 $1\mul_op__insn_type$2$next[6:0]$8088 } { \mul_op__insn$48 \mul_op__is_signed$47 \mul_op__is_32bit$46 \mul_op__write_cr0$45 \mul_op__oe__ok$44 \mul_op__oe__oe$43 \mul_op__rc__ok$42 \mul_op__rc__rc$41 \mul_op__imm_data__ok$40 \mul_op__imm_data__data$39 \mul_op__fn_unit$38 \mul_op__insn_type$37 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\mul_op__insn$13$next[31:0]$8087 $1\mul_op__is_signed$12$next[0:0]$8090 $1\mul_op__is_32bit$11$next[0:0]$8089 $1\mul_op__write_cr0$10$next[0:0]$8095 $1\mul_op__oe__ok$9$next[0:0]$8092 $1\mul_op__oe__oe$8$next[0:0]$8091 $1\mul_op__rc__ok$7$next[0:0]$8093 $1\mul_op__rc__rc$6$next[0:0]$8094 $1\mul_op__imm_data__ok$5$next[0:0]$8086 $1\mul_op__imm_data__data$4$next[63:0]$8085 $1\mul_op__fn_unit$3$next[12:0]$8084 $1\mul_op__insn_type$2$next[6:0]$8088 } { \mul_op__insn$48 \mul_op__is_signed$47 \mul_op__is_32bit$46 \mul_op__write_cr0$45 \mul_op__oe__ok$44 \mul_op__oe__oe$43 \mul_op__rc__ok$42 \mul_op__rc__rc$41 \mul_op__imm_data__ok$40 \mul_op__imm_data__data$39 \mul_op__fn_unit$38 \mul_op__insn_type$37 } + case + assign $1\mul_op__fn_unit$3$next[12:0]$8084 \mul_op__fn_unit$3 + assign $1\mul_op__imm_data__data$4$next[63:0]$8085 \mul_op__imm_data__data$4 + assign $1\mul_op__imm_data__ok$5$next[0:0]$8086 \mul_op__imm_data__ok$5 + assign $1\mul_op__insn$13$next[31:0]$8087 \mul_op__insn$13 + assign $1\mul_op__insn_type$2$next[6:0]$8088 \mul_op__insn_type$2 + assign $1\mul_op__is_32bit$11$next[0:0]$8089 \mul_op__is_32bit$11 + assign $1\mul_op__is_signed$12$next[0:0]$8090 \mul_op__is_signed$12 + assign $1\mul_op__oe__oe$8$next[0:0]$8091 \mul_op__oe__oe$8 + assign $1\mul_op__oe__ok$9$next[0:0]$8092 \mul_op__oe__ok$9 + assign $1\mul_op__rc__ok$7$next[0:0]$8093 \mul_op__rc__ok$7 + assign $1\mul_op__rc__rc$6$next[0:0]$8094 \mul_op__rc__rc$6 + assign $1\mul_op__write_cr0$10$next[0:0]$8095 \mul_op__write_cr0$10 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $2\mul_op__imm_data__data$4$next[63:0]$8096 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\mul_op__imm_data__ok$5$next[0:0]$8097 1'0 + assign $2\mul_op__rc__rc$6$next[0:0]$8101 1'0 + assign $2\mul_op__rc__ok$7$next[0:0]$8100 1'0 + assign $2\mul_op__oe__oe$8$next[0:0]$8098 1'0 + assign $2\mul_op__oe__ok$9$next[0:0]$8099 1'0 + case + assign $2\mul_op__imm_data__data$4$next[63:0]$8096 $1\mul_op__imm_data__data$4$next[63:0]$8085 + assign $2\mul_op__imm_data__ok$5$next[0:0]$8097 $1\mul_op__imm_data__ok$5$next[0:0]$8086 + assign $2\mul_op__oe__oe$8$next[0:0]$8098 $1\mul_op__oe__oe$8$next[0:0]$8091 + assign $2\mul_op__oe__ok$9$next[0:0]$8099 $1\mul_op__oe__ok$9$next[0:0]$8092 + assign $2\mul_op__rc__ok$7$next[0:0]$8100 $1\mul_op__rc__ok$7$next[0:0]$8093 + assign $2\mul_op__rc__rc$6$next[0:0]$8101 $1\mul_op__rc__rc$6$next[0:0]$8094 + end + sync always + update \mul_op__fn_unit$3$next $0\mul_op__fn_unit$3$next[12:0]$8072 + update \mul_op__imm_data__data$4$next $0\mul_op__imm_data__data$4$next[63:0]$8073 + update \mul_op__imm_data__ok$5$next $0\mul_op__imm_data__ok$5$next[0:0]$8074 + update \mul_op__insn$13$next $0\mul_op__insn$13$next[31:0]$8075 + update \mul_op__insn_type$2$next $0\mul_op__insn_type$2$next[6:0]$8076 + update \mul_op__is_32bit$11$next $0\mul_op__is_32bit$11$next[0:0]$8077 + update \mul_op__is_signed$12$next $0\mul_op__is_signed$12$next[0:0]$8078 + update \mul_op__oe__oe$8$next $0\mul_op__oe__oe$8$next[0:0]$8079 + update \mul_op__oe__ok$9$next $0\mul_op__oe__ok$9$next[0:0]$8080 + update \mul_op__rc__ok$7$next $0\mul_op__rc__ok$7$next[0:0]$8081 + update \mul_op__rc__rc$6$next $0\mul_op__rc__rc$6$next[0:0]$8082 + update \mul_op__write_cr0$10$next $0\mul_op__write_cr0$10$next[0:0]$8083 + end + attribute \src "libresoc.v:158241.3-158253.6" + process $proc$libresoc.v:158241$8102 + assign { } { } + assign { } { } + assign $0\o$next[128:0]$8103 $1\o$next[128:0]$8104 + attribute \src "libresoc.v:158242.5-158242.29" + switch \initial + attribute \src "libresoc.v:158242.9-158242.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\o$next[128:0]$8104 \o$49 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\o$next[128:0]$8104 \o$49 + case + assign $1\o$next[128:0]$8104 \o + end + sync always + update \o$next $0\o$next[128:0]$8103 + end + attribute \src "libresoc.v:158254.3-158266.6" + process $proc$libresoc.v:158254$8105 + assign { } { } + assign { } { } + assign $0\xer_so$14$next[0:0]$8106 $1\xer_so$14$next[0:0]$8107 + attribute \src "libresoc.v:158255.5-158255.29" + switch \initial + attribute \src "libresoc.v:158255.9-158255.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\xer_so$14$next[0:0]$8107 \xer_so$50 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\xer_so$14$next[0:0]$8107 \xer_so$50 + case + assign $1\xer_so$14$next[0:0]$8107 \xer_so$14 + end + sync always + update \xer_so$14$next $0\xer_so$14$next[0:0]$8106 + end + attribute \src "libresoc.v:158267.3-158279.6" + process $proc$libresoc.v:158267$8108 + assign { } { } + assign { } { } + assign $0\neg_res$15$next[0:0]$8109 $1\neg_res$15$next[0:0]$8110 + attribute \src "libresoc.v:158268.5-158268.29" + switch \initial + attribute \src "libresoc.v:158268.9-158268.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\neg_res$15$next[0:0]$8110 \neg_res$51 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\neg_res$15$next[0:0]$8110 \neg_res$51 + case + assign $1\neg_res$15$next[0:0]$8110 \neg_res$15 + end + sync always + update \neg_res$15$next $0\neg_res$15$next[0:0]$8109 + end + attribute \src "libresoc.v:158280.3-158292.6" + process $proc$libresoc.v:158280$8111 + assign { } { } + assign { } { } + assign $0\neg_res32$16$next[0:0]$8112 $1\neg_res32$16$next[0:0]$8113 + attribute \src "libresoc.v:158281.5-158281.29" + switch \initial + attribute \src "libresoc.v:158281.9-158281.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\neg_res32$16$next[0:0]$8113 \neg_res32$52 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\neg_res32$16$next[0:0]$8113 \neg_res32$52 + case + assign $1\neg_res32$16$next[0:0]$8113 \neg_res32$16 + end + sync always + update \neg_res32$16$next $0\neg_res32$16$next[0:0]$8112 + end + connect \$34 $and$libresoc.v:158092$8029_Y + connect \p_ready_o \n_i_rdy_data + connect \n_valid_o \r_busy + connect \neg_res32$52 \mul2_neg_res32$32 + connect \neg_res$51 \mul2_neg_res$31 + connect \xer_so$50 \mul2_xer_so$30 + connect \o$49 \mul2_o + connect { \mul_op__insn$48 \mul_op__is_signed$47 \mul_op__is_32bit$46 \mul_op__write_cr0$45 \mul_op__oe__ok$44 \mul_op__oe__oe$43 \mul_op__rc__ok$42 \mul_op__rc__rc$41 \mul_op__imm_data__ok$40 \mul_op__imm_data__data$39 \mul_op__fn_unit$38 \mul_op__insn_type$37 } { \mul2_mul_op__insn$29 \mul2_mul_op__is_signed$28 \mul2_mul_op__is_32bit$27 \mul2_mul_op__write_cr0$26 \mul2_mul_op__oe__ok$25 \mul2_mul_op__oe__oe$24 \mul2_mul_op__rc__ok$23 \mul2_mul_op__rc__rc$22 \mul2_mul_op__imm_data__ok$21 \mul2_mul_op__imm_data__data$20 \mul2_mul_op__fn_unit$19 \mul2_mul_op__insn_type$18 } + connect \muxid$36 \mul2_muxid$17 + connect \p_valid_i_p_ready_o \$34 + connect \n_i_rdy_data \n_ready_i + connect \p_valid_i$33 \p_valid_i + connect \mul2_neg_res32 \neg_res32 + connect \mul2_neg_res \neg_res + connect \mul2_xer_so \xer_so + connect \mul2_rb \rb + connect \mul2_ra \ra + connect { \mul2_mul_op__insn \mul2_mul_op__is_signed \mul2_mul_op__is_32bit \mul2_mul_op__write_cr0 \mul2_mul_op__oe__ok \mul2_mul_op__oe__oe \mul2_mul_op__rc__ok \mul2_mul_op__rc__rc \mul2_mul_op__imm_data__ok \mul2_mul_op__imm_data__data \mul2_mul_op__fn_unit \mul2_mul_op__insn_type } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__oe__ok \mul_op__oe__oe \mul_op__rc__ok \mul_op__rc__rc \mul_op__imm_data__ok \mul_op__imm_data__data \mul_op__fn_unit \mul_op__insn_type } + connect \mul2_muxid \muxid +end +attribute \src "libresoc.v:158315.1-159597.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe3" +attribute \generator "nMigen" +module \mul_pipe3 + attribute \src "libresoc.v:159515.3-159533.6" + wire width 4 $0\cr_a$next[3:0]$8232 + attribute \src "libresoc.v:159307.3-159308.25" + wire width 4 $0\cr_a[3:0] + attribute \src "libresoc.v:159515.3-159533.6" + wire $0\cr_a_ok$next[0:0]$8233 + attribute \src "libresoc.v:159309.3-159310.31" + wire $0\cr_a_ok[0:0] + attribute \src "libresoc.v:158316.7-158316.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:159460.3-159495.6" + wire width 13 $0\mul_op__fn_unit$3$next[12:0]$8195 + attribute \src "libresoc.v:159317.3-159318.53" + wire width 13 $0\mul_op__fn_unit$3[12:0]$8163 + attribute \src "libresoc.v:158621.14-158621.44" + wire width 13 $0\mul_op__fn_unit$3[12:0]$8253 + attribute \src "libresoc.v:159460.3-159495.6" + wire width 64 $0\mul_op__imm_data__data$4$next[63:0]$8196 + attribute \src "libresoc.v:159319.3-159320.67" + wire width 64 $0\mul_op__imm_data__data$4[63:0]$8165 + attribute \src "libresoc.v:158644.14-158644.63" + wire width 64 $0\mul_op__imm_data__data$4[63:0]$8255 + attribute \src "libresoc.v:159460.3-159495.6" + wire $0\mul_op__imm_data__ok$5$next[0:0]$8197 + attribute \src "libresoc.v:159321.3-159322.63" + wire $0\mul_op__imm_data__ok$5[0:0]$8167 + attribute \src "libresoc.v:158653.7-158653.38" + wire $0\mul_op__imm_data__ok$5[0:0]$8257 + attribute \src "libresoc.v:159460.3-159495.6" + wire width 32 $0\mul_op__insn$13$next[31:0]$8198 + attribute \src "libresoc.v:159337.3-159338.49" + wire width 32 $0\mul_op__insn$13[31:0]$8183 + attribute \src "libresoc.v:158662.14-158662.39" + wire width 32 $0\mul_op__insn$13[31:0]$8259 + attribute \src "libresoc.v:159460.3-159495.6" + wire width 7 $0\mul_op__insn_type$2$next[6:0]$8199 + attribute \src "libresoc.v:159315.3-159316.57" + wire width 7 $0\mul_op__insn_type$2[6:0]$8161 + attribute \src "libresoc.v:158819.13-158819.42" + wire width 7 $0\mul_op__insn_type$2[6:0]$8261 + attribute \src "libresoc.v:159460.3-159495.6" + wire $0\mul_op__is_32bit$11$next[0:0]$8200 + attribute \src "libresoc.v:159333.3-159334.57" + wire $0\mul_op__is_32bit$11[0:0]$8179 + attribute \src "libresoc.v:158902.7-158902.35" + wire $0\mul_op__is_32bit$11[0:0]$8263 + attribute \src "libresoc.v:159460.3-159495.6" + wire $0\mul_op__is_signed$12$next[0:0]$8201 + attribute \src "libresoc.v:159335.3-159336.59" + wire $0\mul_op__is_signed$12[0:0]$8181 + attribute \src "libresoc.v:158911.7-158911.36" + wire $0\mul_op__is_signed$12[0:0]$8265 + attribute \src "libresoc.v:159460.3-159495.6" + wire $0\mul_op__oe__oe$8$next[0:0]$8202 + attribute \src "libresoc.v:159327.3-159328.51" + wire $0\mul_op__oe__oe$8[0:0]$8173 + attribute \src "libresoc.v:158922.7-158922.32" + wire $0\mul_op__oe__oe$8[0:0]$8267 + attribute \src "libresoc.v:159460.3-159495.6" + wire $0\mul_op__oe__ok$9$next[0:0]$8203 + attribute \src "libresoc.v:159329.3-159330.51" + wire $0\mul_op__oe__ok$9[0:0]$8175 + attribute \src "libresoc.v:158931.7-158931.32" + wire $0\mul_op__oe__ok$9[0:0]$8269 + attribute \src "libresoc.v:159460.3-159495.6" + wire $0\mul_op__rc__ok$7$next[0:0]$8204 + attribute \src "libresoc.v:159325.3-159326.51" + wire $0\mul_op__rc__ok$7[0:0]$8171 + attribute \src "libresoc.v:158940.7-158940.32" + wire $0\mul_op__rc__ok$7[0:0]$8271 + attribute \src "libresoc.v:159460.3-159495.6" + wire $0\mul_op__rc__rc$6$next[0:0]$8205 + attribute \src "libresoc.v:159323.3-159324.51" + wire $0\mul_op__rc__rc$6[0:0]$8169 + attribute \src "libresoc.v:158947.7-158947.32" + wire $0\mul_op__rc__rc$6[0:0]$8273 + attribute \src "libresoc.v:159460.3-159495.6" + wire $0\mul_op__write_cr0$10$next[0:0]$8206 + attribute \src "libresoc.v:159331.3-159332.59" + wire $0\mul_op__write_cr0$10[0:0]$8177 + attribute \src "libresoc.v:158956.7-158956.36" + wire $0\mul_op__write_cr0$10[0:0]$8275 + attribute \src "libresoc.v:159447.3-159459.6" + wire width 2 $0\muxid$1$next[1:0]$8192 + attribute \src "libresoc.v:159339.3-159340.33" + wire width 2 $0\muxid$1[1:0]$8185 + attribute \src "libresoc.v:158965.13-158965.29" + wire width 2 $0\muxid$1[1:0]$8277 + attribute \src "libresoc.v:159496.3-159514.6" + wire width 64 $0\o$14$next[63:0]$8227 + attribute \src "libresoc.v:159311.3-159312.27" + wire width 64 $0\o$14[63:0]$8158 + attribute \src "libresoc.v:158986.14-158986.43" + wire width 64 $0\o$14[63:0]$8279 + attribute \src "libresoc.v:159496.3-159514.6" + wire $0\o_ok$next[0:0]$8226 + attribute \src "libresoc.v:159313.3-159314.25" + wire $0\o_ok[0:0] + attribute \src "libresoc.v:159429.3-159446.6" + wire $0\r_busy$next[0:0]$8188 + attribute \src "libresoc.v:159341.3-159342.29" + wire $0\r_busy[0:0] + attribute \src "libresoc.v:159534.3-159552.6" + wire width 2 $0\xer_ov$next[1:0]$8238 + attribute \src "libresoc.v:159303.3-159304.29" + wire width 2 $0\xer_ov[1:0] + attribute \src "libresoc.v:159534.3-159552.6" + wire $0\xer_ov_ok$next[0:0]$8239 + attribute \src "libresoc.v:159305.3-159306.35" + wire $0\xer_ov_ok[0:0] + attribute \src "libresoc.v:159553.3-159571.6" + wire $0\xer_so$15$next[0:0]$8245 + attribute \src "libresoc.v:159299.3-159300.37" + wire $0\xer_so$15[0:0]$8151 + attribute \src "libresoc.v:159284.7-159284.25" + wire $0\xer_so$15[0:0]$8285 + attribute \src "libresoc.v:159553.3-159571.6" + wire $0\xer_so_ok$next[0:0]$8244 + attribute \src "libresoc.v:159301.3-159302.35" + wire $0\xer_so_ok[0:0] + attribute \src "libresoc.v:159515.3-159533.6" + wire width 4 $1\cr_a$next[3:0]$8234 + attribute \src "libresoc.v:158325.13-158325.24" + wire width 4 $1\cr_a[3:0] + attribute \src "libresoc.v:159515.3-159533.6" + wire $1\cr_a_ok$next[0:0]$8235 + attribute \src "libresoc.v:158334.7-158334.21" + wire $1\cr_a_ok[0:0] + attribute \src "libresoc.v:159460.3-159495.6" + wire width 13 $1\mul_op__fn_unit$3$next[12:0]$8207 + attribute \src "libresoc.v:159460.3-159495.6" + wire width 64 $1\mul_op__imm_data__data$4$next[63:0]$8208 + attribute \src "libresoc.v:159460.3-159495.6" + wire $1\mul_op__imm_data__ok$5$next[0:0]$8209 + attribute \src "libresoc.v:159460.3-159495.6" + wire width 32 $1\mul_op__insn$13$next[31:0]$8210 + attribute \src "libresoc.v:159460.3-159495.6" + wire width 7 $1\mul_op__insn_type$2$next[6:0]$8211 + attribute \src "libresoc.v:159460.3-159495.6" + wire $1\mul_op__is_32bit$11$next[0:0]$8212 + attribute \src "libresoc.v:159460.3-159495.6" + wire $1\mul_op__is_signed$12$next[0:0]$8213 + attribute \src "libresoc.v:159460.3-159495.6" + wire $1\mul_op__oe__oe$8$next[0:0]$8214 + attribute \src "libresoc.v:159460.3-159495.6" + wire $1\mul_op__oe__ok$9$next[0:0]$8215 + attribute \src "libresoc.v:159460.3-159495.6" + wire $1\mul_op__rc__ok$7$next[0:0]$8216 + attribute \src "libresoc.v:159460.3-159495.6" + wire $1\mul_op__rc__rc$6$next[0:0]$8217 + attribute \src "libresoc.v:159460.3-159495.6" + wire $1\mul_op__write_cr0$10$next[0:0]$8218 + attribute \src "libresoc.v:159447.3-159459.6" + wire width 2 $1\muxid$1$next[1:0]$8193 + attribute \src "libresoc.v:159496.3-159514.6" + wire width 64 $1\o$14$next[63:0]$8229 + attribute \src "libresoc.v:159496.3-159514.6" + wire $1\o_ok$next[0:0]$8228 + attribute \src "libresoc.v:158993.7-158993.18" + wire $1\o_ok[0:0] + attribute \src "libresoc.v:159429.3-159446.6" + wire $1\r_busy$next[0:0]$8189 + attribute \src "libresoc.v:159261.7-159261.20" + wire $1\r_busy[0:0] + attribute \src "libresoc.v:159534.3-159552.6" + wire width 2 $1\xer_ov$next[1:0]$8240 + attribute \src "libresoc.v:159266.13-159266.26" + wire width 2 $1\xer_ov[1:0] + attribute \src "libresoc.v:159534.3-159552.6" + wire $1\xer_ov_ok$next[0:0]$8241 + attribute \src "libresoc.v:159273.7-159273.23" + wire $1\xer_ov_ok[0:0] + attribute \src "libresoc.v:159553.3-159571.6" + wire $1\xer_so$15$next[0:0]$8247 + attribute \src "libresoc.v:159553.3-159571.6" + wire $1\xer_so_ok$next[0:0]$8246 + attribute \src "libresoc.v:159291.7-159291.23" + wire $1\xer_so_ok[0:0] + attribute \src "libresoc.v:159515.3-159533.6" + wire $2\cr_a_ok$next[0:0]$8236 + attribute \src "libresoc.v:159460.3-159495.6" + wire width 64 $2\mul_op__imm_data__data$4$next[63:0]$8219 + attribute \src "libresoc.v:159460.3-159495.6" + wire $2\mul_op__imm_data__ok$5$next[0:0]$8220 + attribute \src "libresoc.v:159460.3-159495.6" + wire $2\mul_op__oe__oe$8$next[0:0]$8221 + attribute \src "libresoc.v:159460.3-159495.6" + wire $2\mul_op__oe__ok$9$next[0:0]$8222 + attribute \src "libresoc.v:159460.3-159495.6" + wire $2\mul_op__rc__ok$7$next[0:0]$8223 + attribute \src "libresoc.v:159460.3-159495.6" + wire $2\mul_op__rc__rc$6$next[0:0]$8224 + attribute \src "libresoc.v:159496.3-159514.6" + wire $2\o_ok$next[0:0]$8230 + attribute \src "libresoc.v:159429.3-159446.6" + wire $2\r_busy$next[0:0]$8190 + attribute \src "libresoc.v:159534.3-159552.6" + wire $2\xer_ov_ok$next[0:0]$8242 + attribute \src "libresoc.v:159553.3-159571.6" + wire $2\xer_so_ok$next[0:0]$8248 + attribute \src "libresoc.v:159298.18-159298.118" + wire $and$libresoc.v:159298$8149_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" + wire \$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 44 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 output 38 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \cr_a$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \cr_a$73 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \cr_a$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 39 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_a_ok$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_a_ok$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_a_ok$74 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_a_ok$next + attribute \src "libresoc.v:158316.7-158316.15" + wire \initial + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \mul3_mul_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \mul3_mul_op__fn_unit$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \mul3_mul_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \mul3_mul_op__imm_data__data$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul3_mul_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul3_mul_op__imm_data__ok$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \mul3_mul_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \mul3_mul_op__insn$28 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \mul3_mul_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \mul3_mul_op__insn_type$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul3_mul_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul3_mul_op__is_32bit$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul3_mul_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul3_mul_op__is_signed$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul3_mul_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul3_mul_op__oe__oe$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul3_mul_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul3_mul_op__oe__ok$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul3_mul_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul3_mul_op__rc__ok$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul3_mul_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul3_mul_op__rc__rc$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul3_mul_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul3_mul_op__write_cr0$25 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \mul3_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \mul3_muxid$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" + wire \mul3_neg_res + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 129 \mul3_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \mul3_o$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \mul3_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \mul3_xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \mul3_xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \mul3_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \mul3_xer_so$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \mul3_xer_so_ok + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 input 6 \mul_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 output 25 \mul_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \mul_op__fn_unit$3$next + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \mul_op__fn_unit$60 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 7 \mul_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 26 \mul_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \mul_op__imm_data__data$4$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \mul_op__imm_data__data$61 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \mul_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 27 \mul_op__imm_data__ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__imm_data__ok$5$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__imm_data__ok$62 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 16 \mul_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 35 \mul_op__insn$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \mul_op__insn$13$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \mul_op__insn$70 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 5 \mul_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 24 \mul_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \mul_op__insn_type$2$next + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \mul_op__insn_type$59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \mul_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 33 \mul_op__is_32bit$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__is_32bit$11$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__is_32bit$68 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 15 \mul_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 34 \mul_op__is_signed$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__is_signed$12$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__is_signed$69 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 11 \mul_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__oe__oe$65 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 30 \mul_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__oe__oe$8$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \mul_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__oe__ok$66 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 31 \mul_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__oe__ok$9$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \mul_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__rc__ok$64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 29 \mul_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__rc__ok$7$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \mul_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 28 \mul_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__rc__rc$6$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__rc__rc$63 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \mul_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 32 \mul_op__write_cr0$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__write_cr0$10$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__write_cr0$67 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 input 4 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 output 23 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid$1$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid$58 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + wire \n_i_rdy_data + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire input 22 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire output 21 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" + wire input 19 \neg_res + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24" + wire input 20 \neg_res32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24" + wire \neg_res32$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 129 input 17 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 36 \o$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \o$14$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \o$71 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 37 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \o_ok$72 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \o_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \output_cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \output_cr_a$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \output_cr_a_ok + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \output_mul_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \output_mul_op__fn_unit$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \output_mul_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \output_mul_op__imm_data__data$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_mul_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_mul_op__imm_data__ok$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \output_mul_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \output_mul_op__insn$43 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \output_mul_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \output_mul_op__insn_type$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_mul_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_mul_op__is_32bit$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_mul_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_mul_op__is_signed$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_mul_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_mul_op__oe__oe$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_mul_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_mul_op__oe__ok$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_mul_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_mul_op__rc__ok$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_mul_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_mul_op__rc__rc$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_mul_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_mul_op__write_cr0$40 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \output_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \output_muxid$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \output_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \output_o$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \output_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \output_o_ok$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \output_xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \output_xer_ov$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \output_xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \output_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \output_xer_so$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \output_xer_so_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" + wire output 3 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" + wire input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" + wire \p_valid_i$55 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" + wire \p_valid_i_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire \r_busy$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 output 40 \xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \xer_ov$75 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \xer_ov$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 41 \xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_ov_ok$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_ov_ok$76 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_ov_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 18 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 42 \xer_so$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so$15$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so$77 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 43 \xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so_ok$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so_ok$78 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so_ok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" + cell $and $and$libresoc.v:159298$8149 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i$55 + connect \B \p_ready_o + connect \Y $and$libresoc.v:159298$8149_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:159343.8-159379.4" + cell \mul3 \mul3 + connect \mul_op__fn_unit \mul3_mul_op__fn_unit + connect \mul_op__fn_unit$3 \mul3_mul_op__fn_unit$18 + connect \mul_op__imm_data__data \mul3_mul_op__imm_data__data + connect \mul_op__imm_data__data$4 \mul3_mul_op__imm_data__data$19 + connect \mul_op__imm_data__ok \mul3_mul_op__imm_data__ok + connect \mul_op__imm_data__ok$5 \mul3_mul_op__imm_data__ok$20 + connect \mul_op__insn \mul3_mul_op__insn + connect \mul_op__insn$13 \mul3_mul_op__insn$28 + connect \mul_op__insn_type \mul3_mul_op__insn_type + connect \mul_op__insn_type$2 \mul3_mul_op__insn_type$17 + connect \mul_op__is_32bit \mul3_mul_op__is_32bit + connect \mul_op__is_32bit$11 \mul3_mul_op__is_32bit$26 + connect \mul_op__is_signed \mul3_mul_op__is_signed + connect \mul_op__is_signed$12 \mul3_mul_op__is_signed$27 + connect \mul_op__oe__oe \mul3_mul_op__oe__oe + connect \mul_op__oe__oe$8 \mul3_mul_op__oe__oe$23 + connect \mul_op__oe__ok \mul3_mul_op__oe__ok + connect \mul_op__oe__ok$9 \mul3_mul_op__oe__ok$24 + connect \mul_op__rc__ok \mul3_mul_op__rc__ok + connect \mul_op__rc__ok$7 \mul3_mul_op__rc__ok$22 + connect \mul_op__rc__rc \mul3_mul_op__rc__rc + connect \mul_op__rc__rc$6 \mul3_mul_op__rc__rc$21 + connect \mul_op__write_cr0 \mul3_mul_op__write_cr0 + connect \mul_op__write_cr0$10 \mul3_mul_op__write_cr0$25 + connect \muxid \mul3_muxid + connect \muxid$1 \mul3_muxid$16 + connect \neg_res \mul3_neg_res + connect \o \mul3_o + connect \o$14 \mul3_o$29 + connect \o_ok \mul3_o_ok + connect \xer_ov \mul3_xer_ov + connect \xer_ov_ok \mul3_xer_ov_ok + connect \xer_so \mul3_xer_so + connect \xer_so$15 \mul3_xer_so$30 + connect \xer_so_ok \mul3_xer_so_ok + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:159380.10-159383.4" + cell \n$99 \n + connect \n_ready_i \n_ready_i + connect \n_valid_o \n_valid_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:159384.16-159424.4" + cell \output$100 \output + connect \cr_a \output_cr_a + connect \cr_a$16 \output_cr_a$46 + connect \cr_a_ok \output_cr_a_ok + connect \mul_op__fn_unit \output_mul_op__fn_unit + connect \mul_op__fn_unit$3 \output_mul_op__fn_unit$33 + connect \mul_op__imm_data__data \output_mul_op__imm_data__data + connect \mul_op__imm_data__data$4 \output_mul_op__imm_data__data$34 + connect \mul_op__imm_data__ok \output_mul_op__imm_data__ok + connect \mul_op__imm_data__ok$5 \output_mul_op__imm_data__ok$35 + connect \mul_op__insn \output_mul_op__insn + connect \mul_op__insn$13 \output_mul_op__insn$43 + connect \mul_op__insn_type \output_mul_op__insn_type + connect \mul_op__insn_type$2 \output_mul_op__insn_type$32 + connect \mul_op__is_32bit \output_mul_op__is_32bit + connect \mul_op__is_32bit$11 \output_mul_op__is_32bit$41 + connect \mul_op__is_signed \output_mul_op__is_signed + connect \mul_op__is_signed$12 \output_mul_op__is_signed$42 + connect \mul_op__oe__oe \output_mul_op__oe__oe + connect \mul_op__oe__oe$8 \output_mul_op__oe__oe$38 + connect \mul_op__oe__ok \output_mul_op__oe__ok + connect \mul_op__oe__ok$9 \output_mul_op__oe__ok$39 + connect \mul_op__rc__ok \output_mul_op__rc__ok + connect \mul_op__rc__ok$7 \output_mul_op__rc__ok$37 + connect \mul_op__rc__rc \output_mul_op__rc__rc + connect \mul_op__rc__rc$6 \output_mul_op__rc__rc$36 + connect \mul_op__write_cr0 \output_mul_op__write_cr0 + connect \mul_op__write_cr0$10 \output_mul_op__write_cr0$40 + connect \muxid \output_muxid + connect \muxid$1 \output_muxid$31 + connect \o \output_o + connect \o$14 \output_o$44 + connect \o_ok \output_o_ok + connect \o_ok$15 \output_o_ok$45 + connect \xer_ov \output_xer_ov + connect \xer_ov$17 \output_xer_ov$47 + connect \xer_ov_ok \output_xer_ov_ok + connect \xer_so \output_xer_so + connect \xer_so$18 \output_xer_so$48 + connect \xer_so_ok \output_xer_so_ok + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:159425.10-159428.4" + cell \p$98 \p + connect \p_ready_o \p_ready_o + connect \p_valid_i \p_valid_i + end + attribute \src "libresoc.v:158316.7-158316.20" + process $proc$libresoc.v:158316$8249 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:158325.13-158325.24" + process $proc$libresoc.v:158325$8250 + assign { } { } + assign $1\cr_a[3:0] 4'0000 + sync always + sync init + update \cr_a $1\cr_a[3:0] + end + attribute \src "libresoc.v:158334.7-158334.21" + process $proc$libresoc.v:158334$8251 + assign { } { } + assign $1\cr_a_ok[0:0] 1'0 + sync always + sync init + update \cr_a_ok $1\cr_a_ok[0:0] + end + attribute \src "libresoc.v:158621.14-158621.44" + process $proc$libresoc.v:158621$8252 + assign { } { } + assign $0\mul_op__fn_unit$3[12:0]$8253 13'0000000000000 + sync always + sync init + update \mul_op__fn_unit$3 $0\mul_op__fn_unit$3[12:0]$8253 + end + attribute \src "libresoc.v:158644.14-158644.63" + process $proc$libresoc.v:158644$8254 + assign { } { } + assign $0\mul_op__imm_data__data$4[63:0]$8255 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \mul_op__imm_data__data$4 $0\mul_op__imm_data__data$4[63:0]$8255 + end + attribute \src "libresoc.v:158653.7-158653.38" + process $proc$libresoc.v:158653$8256 + assign { } { } + assign $0\mul_op__imm_data__ok$5[0:0]$8257 1'0 + sync always + sync init + update \mul_op__imm_data__ok$5 $0\mul_op__imm_data__ok$5[0:0]$8257 + end + attribute \src "libresoc.v:158662.14-158662.39" + process $proc$libresoc.v:158662$8258 + assign { } { } + assign $0\mul_op__insn$13[31:0]$8259 0 + sync always + sync init + update \mul_op__insn$13 $0\mul_op__insn$13[31:0]$8259 + end + attribute \src "libresoc.v:158819.13-158819.42" + process $proc$libresoc.v:158819$8260 + assign { } { } + assign $0\mul_op__insn_type$2[6:0]$8261 7'0000000 + sync always + sync init + update \mul_op__insn_type$2 $0\mul_op__insn_type$2[6:0]$8261 + end + attribute \src "libresoc.v:158902.7-158902.35" + process $proc$libresoc.v:158902$8262 + assign { } { } + assign $0\mul_op__is_32bit$11[0:0]$8263 1'0 + sync always + sync init + update \mul_op__is_32bit$11 $0\mul_op__is_32bit$11[0:0]$8263 + end + attribute \src "libresoc.v:158911.7-158911.36" + process $proc$libresoc.v:158911$8264 + assign { } { } + assign $0\mul_op__is_signed$12[0:0]$8265 1'0 + sync always + sync init + update \mul_op__is_signed$12 $0\mul_op__is_signed$12[0:0]$8265 + end + attribute \src "libresoc.v:158922.7-158922.32" + process $proc$libresoc.v:158922$8266 + assign { } { } + assign $0\mul_op__oe__oe$8[0:0]$8267 1'0 + sync always + sync init + update \mul_op__oe__oe$8 $0\mul_op__oe__oe$8[0:0]$8267 + end + attribute \src "libresoc.v:158931.7-158931.32" + process $proc$libresoc.v:158931$8268 + assign { } { } + assign $0\mul_op__oe__ok$9[0:0]$8269 1'0 + sync always + sync init + update \mul_op__oe__ok$9 $0\mul_op__oe__ok$9[0:0]$8269 + end + attribute \src "libresoc.v:158940.7-158940.32" + process $proc$libresoc.v:158940$8270 + assign { } { } + assign $0\mul_op__rc__ok$7[0:0]$8271 1'0 + sync always + sync init + update \mul_op__rc__ok$7 $0\mul_op__rc__ok$7[0:0]$8271 + end + attribute \src "libresoc.v:158947.7-158947.32" + process $proc$libresoc.v:158947$8272 + assign { } { } + assign $0\mul_op__rc__rc$6[0:0]$8273 1'0 + sync always + sync init + update \mul_op__rc__rc$6 $0\mul_op__rc__rc$6[0:0]$8273 + end + attribute \src "libresoc.v:158956.7-158956.36" + process $proc$libresoc.v:158956$8274 + assign { } { } + assign $0\mul_op__write_cr0$10[0:0]$8275 1'0 + sync always + sync init + update \mul_op__write_cr0$10 $0\mul_op__write_cr0$10[0:0]$8275 + end + attribute \src "libresoc.v:158965.13-158965.29" + process $proc$libresoc.v:158965$8276 + assign { } { } + assign $0\muxid$1[1:0]$8277 2'00 + sync always + sync init + update \muxid$1 $0\muxid$1[1:0]$8277 + end + attribute \src "libresoc.v:158986.14-158986.43" + process $proc$libresoc.v:158986$8278 + assign { } { } + assign $0\o$14[63:0]$8279 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \o$14 $0\o$14[63:0]$8279 + end + attribute \src "libresoc.v:158993.7-158993.18" + process $proc$libresoc.v:158993$8280 + assign { } { } + assign $1\o_ok[0:0] 1'0 + sync always + sync init + update \o_ok $1\o_ok[0:0] + end + attribute \src "libresoc.v:159261.7-159261.20" + process $proc$libresoc.v:159261$8281 + assign { } { } + assign $1\r_busy[0:0] 1'0 + sync always + sync init + update \r_busy $1\r_busy[0:0] + end + attribute \src "libresoc.v:159266.13-159266.26" + process $proc$libresoc.v:159266$8282 + assign { } { } + assign $1\xer_ov[1:0] 2'00 + sync always + sync init + update \xer_ov $1\xer_ov[1:0] + end + attribute \src "libresoc.v:159273.7-159273.23" + process $proc$libresoc.v:159273$8283 + assign { } { } + assign $1\xer_ov_ok[0:0] 1'0 + sync always + sync init + update \xer_ov_ok $1\xer_ov_ok[0:0] + end + attribute \src "libresoc.v:159284.7-159284.25" + process $proc$libresoc.v:159284$8284 + assign { } { } + assign $0\xer_so$15[0:0]$8285 1'0 + sync always + sync init + update \xer_so$15 $0\xer_so$15[0:0]$8285 + end + attribute \src "libresoc.v:159291.7-159291.23" + process $proc$libresoc.v:159291$8286 + assign { } { } + assign $1\xer_so_ok[0:0] 1'0 + sync always + sync init + update \xer_so_ok $1\xer_so_ok[0:0] + end + attribute \src "libresoc.v:159299.3-159300.37" + process $proc$libresoc.v:159299$8150 + assign { } { } + assign $0\xer_so$15[0:0]$8151 \xer_so$15$next + sync posedge \coresync_clk + update \xer_so$15 $0\xer_so$15[0:0]$8151 + end + attribute \src "libresoc.v:159301.3-159302.35" + process $proc$libresoc.v:159301$8152 + assign { } { } + assign $0\xer_so_ok[0:0] \xer_so_ok$next + sync posedge \coresync_clk + update \xer_so_ok $0\xer_so_ok[0:0] + end + attribute \src "libresoc.v:159303.3-159304.29" + process $proc$libresoc.v:159303$8153 + assign { } { } + assign $0\xer_ov[1:0] \xer_ov$next + sync posedge \coresync_clk + update \xer_ov $0\xer_ov[1:0] + end + attribute \src "libresoc.v:159305.3-159306.35" + process $proc$libresoc.v:159305$8154 + assign { } { } + assign $0\xer_ov_ok[0:0] \xer_ov_ok$next + sync posedge \coresync_clk + update \xer_ov_ok $0\xer_ov_ok[0:0] + end + attribute \src "libresoc.v:159307.3-159308.25" + process $proc$libresoc.v:159307$8155 + assign { } { } + assign $0\cr_a[3:0] \cr_a$next + sync posedge \coresync_clk + update \cr_a $0\cr_a[3:0] + end + attribute \src "libresoc.v:159309.3-159310.31" + process $proc$libresoc.v:159309$8156 + assign { } { } + assign $0\cr_a_ok[0:0] \cr_a_ok$next + sync posedge \coresync_clk + update \cr_a_ok $0\cr_a_ok[0:0] + end + attribute \src "libresoc.v:159311.3-159312.27" + process $proc$libresoc.v:159311$8157 + assign { } { } + assign $0\o$14[63:0]$8158 \o$14$next + sync posedge \coresync_clk + update \o$14 $0\o$14[63:0]$8158 + end + attribute \src "libresoc.v:159313.3-159314.25" + process $proc$libresoc.v:159313$8159 + assign { } { } + assign $0\o_ok[0:0] \o_ok$next + sync posedge \coresync_clk + update \o_ok $0\o_ok[0:0] + end + attribute \src "libresoc.v:159315.3-159316.57" + process $proc$libresoc.v:159315$8160 + assign { } { } + assign $0\mul_op__insn_type$2[6:0]$8161 \mul_op__insn_type$2$next + sync posedge \coresync_clk + update \mul_op__insn_type$2 $0\mul_op__insn_type$2[6:0]$8161 + end + attribute \src "libresoc.v:159317.3-159318.53" + process $proc$libresoc.v:159317$8162 + assign { } { } + assign $0\mul_op__fn_unit$3[12:0]$8163 \mul_op__fn_unit$3$next + sync posedge \coresync_clk + update \mul_op__fn_unit$3 $0\mul_op__fn_unit$3[12:0]$8163 + end + attribute \src "libresoc.v:159319.3-159320.67" + process $proc$libresoc.v:159319$8164 + assign { } { } + assign $0\mul_op__imm_data__data$4[63:0]$8165 \mul_op__imm_data__data$4$next + sync posedge \coresync_clk + update \mul_op__imm_data__data$4 $0\mul_op__imm_data__data$4[63:0]$8165 + end + attribute \src "libresoc.v:159321.3-159322.63" + process $proc$libresoc.v:159321$8166 + assign { } { } + assign $0\mul_op__imm_data__ok$5[0:0]$8167 \mul_op__imm_data__ok$5$next + sync posedge \coresync_clk + update \mul_op__imm_data__ok$5 $0\mul_op__imm_data__ok$5[0:0]$8167 + end + attribute \src "libresoc.v:159323.3-159324.51" + process $proc$libresoc.v:159323$8168 + assign { } { } + assign $0\mul_op__rc__rc$6[0:0]$8169 \mul_op__rc__rc$6$next + sync posedge \coresync_clk + update \mul_op__rc__rc$6 $0\mul_op__rc__rc$6[0:0]$8169 + end + attribute \src "libresoc.v:159325.3-159326.51" + process $proc$libresoc.v:159325$8170 + assign { } { } + assign $0\mul_op__rc__ok$7[0:0]$8171 \mul_op__rc__ok$7$next + sync posedge \coresync_clk + update \mul_op__rc__ok$7 $0\mul_op__rc__ok$7[0:0]$8171 + end + attribute \src "libresoc.v:159327.3-159328.51" + process $proc$libresoc.v:159327$8172 + assign { } { } + assign $0\mul_op__oe__oe$8[0:0]$8173 \mul_op__oe__oe$8$next + sync posedge \coresync_clk + update \mul_op__oe__oe$8 $0\mul_op__oe__oe$8[0:0]$8173 + end + attribute \src "libresoc.v:159329.3-159330.51" + process $proc$libresoc.v:159329$8174 + assign { } { } + assign $0\mul_op__oe__ok$9[0:0]$8175 \mul_op__oe__ok$9$next + sync posedge \coresync_clk + update \mul_op__oe__ok$9 $0\mul_op__oe__ok$9[0:0]$8175 + end + attribute \src "libresoc.v:159331.3-159332.59" + process $proc$libresoc.v:159331$8176 + assign { } { } + assign $0\mul_op__write_cr0$10[0:0]$8177 \mul_op__write_cr0$10$next + sync posedge \coresync_clk + update \mul_op__write_cr0$10 $0\mul_op__write_cr0$10[0:0]$8177 + end + attribute \src "libresoc.v:159333.3-159334.57" + process $proc$libresoc.v:159333$8178 + assign { } { } + assign $0\mul_op__is_32bit$11[0:0]$8179 \mul_op__is_32bit$11$next + sync posedge \coresync_clk + update \mul_op__is_32bit$11 $0\mul_op__is_32bit$11[0:0]$8179 + end + attribute \src "libresoc.v:159335.3-159336.59" + process $proc$libresoc.v:159335$8180 + assign { } { } + assign $0\mul_op__is_signed$12[0:0]$8181 \mul_op__is_signed$12$next + sync posedge \coresync_clk + update \mul_op__is_signed$12 $0\mul_op__is_signed$12[0:0]$8181 + end + attribute \src "libresoc.v:159337.3-159338.49" + process $proc$libresoc.v:159337$8182 + assign { } { } + assign $0\mul_op__insn$13[31:0]$8183 \mul_op__insn$13$next + sync posedge \coresync_clk + update \mul_op__insn$13 $0\mul_op__insn$13[31:0]$8183 + end + attribute \src "libresoc.v:159339.3-159340.33" + process $proc$libresoc.v:159339$8184 + assign { } { } + assign $0\muxid$1[1:0]$8185 \muxid$1$next + sync posedge \coresync_clk + update \muxid$1 $0\muxid$1[1:0]$8185 + end + attribute \src "libresoc.v:159341.3-159342.29" + process $proc$libresoc.v:159341$8186 + assign { } { } + assign $0\r_busy[0:0] \r_busy$next + sync posedge \coresync_clk + update \r_busy $0\r_busy[0:0] + end + attribute \src "libresoc.v:159429.3-159446.6" + process $proc$libresoc.v:159429$8187 + assign { } { } + assign { } { } + assign { } { } + assign $0\r_busy$next[0:0]$8188 $2\r_busy$next[0:0]$8190 + attribute \src "libresoc.v:159430.5-159430.29" + switch \initial + attribute \src "libresoc.v:159430.9-159430.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\r_busy$next[0:0]$8189 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\r_busy$next[0:0]$8189 1'0 + case + assign $1\r_busy$next[0:0]$8189 \r_busy + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r_busy$next[0:0]$8190 1'0 + case + assign $2\r_busy$next[0:0]$8190 $1\r_busy$next[0:0]$8189 + end + sync always + update \r_busy$next $0\r_busy$next[0:0]$8188 + end + attribute \src "libresoc.v:159447.3-159459.6" + process $proc$libresoc.v:159447$8191 + assign { } { } + assign { } { } + assign $0\muxid$1$next[1:0]$8192 $1\muxid$1$next[1:0]$8193 + attribute \src "libresoc.v:159448.5-159448.29" + switch \initial + attribute \src "libresoc.v:159448.9-159448.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\muxid$1$next[1:0]$8193 \muxid$58 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\muxid$1$next[1:0]$8193 \muxid$58 + case + assign $1\muxid$1$next[1:0]$8193 \muxid$1 + end + sync always + update \muxid$1$next $0\muxid$1$next[1:0]$8192 + end + attribute \src "libresoc.v:159460.3-159495.6" + process $proc$libresoc.v:159460$8194 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\mul_op__fn_unit$3$next[12:0]$8195 $1\mul_op__fn_unit$3$next[12:0]$8207 + assign { } { } + assign { } { } + assign $0\mul_op__insn$13$next[31:0]$8198 $1\mul_op__insn$13$next[31:0]$8210 + assign $0\mul_op__insn_type$2$next[6:0]$8199 $1\mul_op__insn_type$2$next[6:0]$8211 + assign $0\mul_op__is_32bit$11$next[0:0]$8200 $1\mul_op__is_32bit$11$next[0:0]$8212 + assign $0\mul_op__is_signed$12$next[0:0]$8201 $1\mul_op__is_signed$12$next[0:0]$8213 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\mul_op__write_cr0$10$next[0:0]$8206 $1\mul_op__write_cr0$10$next[0:0]$8218 + assign $0\mul_op__imm_data__data$4$next[63:0]$8196 $2\mul_op__imm_data__data$4$next[63:0]$8219 + assign $0\mul_op__imm_data__ok$5$next[0:0]$8197 $2\mul_op__imm_data__ok$5$next[0:0]$8220 + assign $0\mul_op__oe__oe$8$next[0:0]$8202 $2\mul_op__oe__oe$8$next[0:0]$8221 + assign $0\mul_op__oe__ok$9$next[0:0]$8203 $2\mul_op__oe__ok$9$next[0:0]$8222 + assign $0\mul_op__rc__ok$7$next[0:0]$8204 $2\mul_op__rc__ok$7$next[0:0]$8223 + assign $0\mul_op__rc__rc$6$next[0:0]$8205 $2\mul_op__rc__rc$6$next[0:0]$8224 + attribute \src "libresoc.v:159461.5-159461.29" + switch \initial + attribute \src "libresoc.v:159461.9-159461.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\mul_op__insn$13$next[31:0]$8210 $1\mul_op__is_signed$12$next[0:0]$8213 $1\mul_op__is_32bit$11$next[0:0]$8212 $1\mul_op__write_cr0$10$next[0:0]$8218 $1\mul_op__oe__ok$9$next[0:0]$8215 $1\mul_op__oe__oe$8$next[0:0]$8214 $1\mul_op__rc__ok$7$next[0:0]$8216 $1\mul_op__rc__rc$6$next[0:0]$8217 $1\mul_op__imm_data__ok$5$next[0:0]$8209 $1\mul_op__imm_data__data$4$next[63:0]$8208 $1\mul_op__fn_unit$3$next[12:0]$8207 $1\mul_op__insn_type$2$next[6:0]$8211 } { \mul_op__insn$70 \mul_op__is_signed$69 \mul_op__is_32bit$68 \mul_op__write_cr0$67 \mul_op__oe__ok$66 \mul_op__oe__oe$65 \mul_op__rc__ok$64 \mul_op__rc__rc$63 \mul_op__imm_data__ok$62 \mul_op__imm_data__data$61 \mul_op__fn_unit$60 \mul_op__insn_type$59 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\mul_op__insn$13$next[31:0]$8210 $1\mul_op__is_signed$12$next[0:0]$8213 $1\mul_op__is_32bit$11$next[0:0]$8212 $1\mul_op__write_cr0$10$next[0:0]$8218 $1\mul_op__oe__ok$9$next[0:0]$8215 $1\mul_op__oe__oe$8$next[0:0]$8214 $1\mul_op__rc__ok$7$next[0:0]$8216 $1\mul_op__rc__rc$6$next[0:0]$8217 $1\mul_op__imm_data__ok$5$next[0:0]$8209 $1\mul_op__imm_data__data$4$next[63:0]$8208 $1\mul_op__fn_unit$3$next[12:0]$8207 $1\mul_op__insn_type$2$next[6:0]$8211 } { \mul_op__insn$70 \mul_op__is_signed$69 \mul_op__is_32bit$68 \mul_op__write_cr0$67 \mul_op__oe__ok$66 \mul_op__oe__oe$65 \mul_op__rc__ok$64 \mul_op__rc__rc$63 \mul_op__imm_data__ok$62 \mul_op__imm_data__data$61 \mul_op__fn_unit$60 \mul_op__insn_type$59 } + case + assign $1\mul_op__fn_unit$3$next[12:0]$8207 \mul_op__fn_unit$3 + assign $1\mul_op__imm_data__data$4$next[63:0]$8208 \mul_op__imm_data__data$4 + assign $1\mul_op__imm_data__ok$5$next[0:0]$8209 \mul_op__imm_data__ok$5 + assign $1\mul_op__insn$13$next[31:0]$8210 \mul_op__insn$13 + assign $1\mul_op__insn_type$2$next[6:0]$8211 \mul_op__insn_type$2 + assign $1\mul_op__is_32bit$11$next[0:0]$8212 \mul_op__is_32bit$11 + assign $1\mul_op__is_signed$12$next[0:0]$8213 \mul_op__is_signed$12 + assign $1\mul_op__oe__oe$8$next[0:0]$8214 \mul_op__oe__oe$8 + assign $1\mul_op__oe__ok$9$next[0:0]$8215 \mul_op__oe__ok$9 + assign $1\mul_op__rc__ok$7$next[0:0]$8216 \mul_op__rc__ok$7 + assign $1\mul_op__rc__rc$6$next[0:0]$8217 \mul_op__rc__rc$6 + assign $1\mul_op__write_cr0$10$next[0:0]$8218 \mul_op__write_cr0$10 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $2\mul_op__imm_data__data$4$next[63:0]$8219 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\mul_op__imm_data__ok$5$next[0:0]$8220 1'0 + assign $2\mul_op__rc__rc$6$next[0:0]$8224 1'0 + assign $2\mul_op__rc__ok$7$next[0:0]$8223 1'0 + assign $2\mul_op__oe__oe$8$next[0:0]$8221 1'0 + assign $2\mul_op__oe__ok$9$next[0:0]$8222 1'0 + case + assign $2\mul_op__imm_data__data$4$next[63:0]$8219 $1\mul_op__imm_data__data$4$next[63:0]$8208 + assign $2\mul_op__imm_data__ok$5$next[0:0]$8220 $1\mul_op__imm_data__ok$5$next[0:0]$8209 + assign $2\mul_op__oe__oe$8$next[0:0]$8221 $1\mul_op__oe__oe$8$next[0:0]$8214 + assign $2\mul_op__oe__ok$9$next[0:0]$8222 $1\mul_op__oe__ok$9$next[0:0]$8215 + assign $2\mul_op__rc__ok$7$next[0:0]$8223 $1\mul_op__rc__ok$7$next[0:0]$8216 + assign $2\mul_op__rc__rc$6$next[0:0]$8224 $1\mul_op__rc__rc$6$next[0:0]$8217 + end + sync always + update \mul_op__fn_unit$3$next $0\mul_op__fn_unit$3$next[12:0]$8195 + update \mul_op__imm_data__data$4$next $0\mul_op__imm_data__data$4$next[63:0]$8196 + update \mul_op__imm_data__ok$5$next $0\mul_op__imm_data__ok$5$next[0:0]$8197 + update \mul_op__insn$13$next $0\mul_op__insn$13$next[31:0]$8198 + update \mul_op__insn_type$2$next $0\mul_op__insn_type$2$next[6:0]$8199 + update \mul_op__is_32bit$11$next $0\mul_op__is_32bit$11$next[0:0]$8200 + update \mul_op__is_signed$12$next $0\mul_op__is_signed$12$next[0:0]$8201 + update \mul_op__oe__oe$8$next $0\mul_op__oe__oe$8$next[0:0]$8202 + update \mul_op__oe__ok$9$next $0\mul_op__oe__ok$9$next[0:0]$8203 + update \mul_op__rc__ok$7$next $0\mul_op__rc__ok$7$next[0:0]$8204 + update \mul_op__rc__rc$6$next $0\mul_op__rc__rc$6$next[0:0]$8205 + update \mul_op__write_cr0$10$next $0\mul_op__write_cr0$10$next[0:0]$8206 + end + attribute \src "libresoc.v:159496.3-159514.6" + process $proc$libresoc.v:159496$8225 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\o$14$next[63:0]$8227 $1\o$14$next[63:0]$8229 + assign $0\o_ok$next[0:0]$8226 $2\o_ok$next[0:0]$8230 + attribute \src "libresoc.v:159497.5-159497.29" + switch \initial + attribute \src "libresoc.v:159497.9-159497.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\o_ok$next[0:0]$8228 $1\o$14$next[63:0]$8229 } { \o_ok$72 \o$71 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\o_ok$next[0:0]$8228 $1\o$14$next[63:0]$8229 } { \o_ok$72 \o$71 } + case + assign $1\o_ok$next[0:0]$8228 \o_ok + assign $1\o$14$next[63:0]$8229 \o$14 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\o_ok$next[0:0]$8230 1'0 + case + assign $2\o_ok$next[0:0]$8230 $1\o_ok$next[0:0]$8228 + end + sync always + update \o_ok$next $0\o_ok$next[0:0]$8226 + update \o$14$next $0\o$14$next[63:0]$8227 + end + attribute \src "libresoc.v:159515.3-159533.6" + process $proc$libresoc.v:159515$8231 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\cr_a$next[3:0]$8232 $1\cr_a$next[3:0]$8234 + assign { } { } + assign $0\cr_a_ok$next[0:0]$8233 $2\cr_a_ok$next[0:0]$8236 + attribute \src "libresoc.v:159516.5-159516.29" + switch \initial + attribute \src "libresoc.v:159516.9-159516.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\cr_a_ok$next[0:0]$8235 $1\cr_a$next[3:0]$8234 } { \cr_a_ok$74 \cr_a$73 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\cr_a_ok$next[0:0]$8235 $1\cr_a$next[3:0]$8234 } { \cr_a_ok$74 \cr_a$73 } + case + assign $1\cr_a$next[3:0]$8234 \cr_a + assign $1\cr_a_ok$next[0:0]$8235 \cr_a_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_a_ok$next[0:0]$8236 1'0 + case + assign $2\cr_a_ok$next[0:0]$8236 $1\cr_a_ok$next[0:0]$8235 + end + sync always + update \cr_a$next $0\cr_a$next[3:0]$8232 + update \cr_a_ok$next $0\cr_a_ok$next[0:0]$8233 + end + attribute \src "libresoc.v:159534.3-159552.6" + process $proc$libresoc.v:159534$8237 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\xer_ov$next[1:0]$8238 $1\xer_ov$next[1:0]$8240 + assign { } { } + assign $0\xer_ov_ok$next[0:0]$8239 $2\xer_ov_ok$next[0:0]$8242 + attribute \src "libresoc.v:159535.5-159535.29" + switch \initial + attribute \src "libresoc.v:159535.9-159535.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\xer_ov_ok$next[0:0]$8241 $1\xer_ov$next[1:0]$8240 } { \xer_ov_ok$76 \xer_ov$75 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\xer_ov_ok$next[0:0]$8241 $1\xer_ov$next[1:0]$8240 } { \xer_ov_ok$76 \xer_ov$75 } + case + assign $1\xer_ov$next[1:0]$8240 \xer_ov + assign $1\xer_ov_ok$next[0:0]$8241 \xer_ov_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\xer_ov_ok$next[0:0]$8242 1'0 + case + assign $2\xer_ov_ok$next[0:0]$8242 $1\xer_ov_ok$next[0:0]$8241 + end + sync always + update \xer_ov$next $0\xer_ov$next[1:0]$8238 + update \xer_ov_ok$next $0\xer_ov_ok$next[0:0]$8239 + end + attribute \src "libresoc.v:159553.3-159571.6" + process $proc$libresoc.v:159553$8243 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\xer_so$15$next[0:0]$8245 $1\xer_so$15$next[0:0]$8247 + assign $0\xer_so_ok$next[0:0]$8244 $2\xer_so_ok$next[0:0]$8248 + attribute \src "libresoc.v:159554.5-159554.29" + switch \initial + attribute \src "libresoc.v:159554.9-159554.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\xer_so_ok$next[0:0]$8246 $1\xer_so$15$next[0:0]$8247 } { \xer_so_ok$78 \xer_so$77 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\xer_so_ok$next[0:0]$8246 $1\xer_so$15$next[0:0]$8247 } { \xer_so_ok$78 \xer_so$77 } + case + assign $1\xer_so_ok$next[0:0]$8246 \xer_so_ok + assign $1\xer_so$15$next[0:0]$8247 \xer_so$15 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\xer_so_ok$next[0:0]$8248 1'0 + case + assign $2\xer_so_ok$next[0:0]$8248 $1\xer_so_ok$next[0:0]$8246 + end + sync always + update \xer_so_ok$next $0\xer_so_ok$next[0:0]$8244 + update \xer_so$15$next $0\xer_so$15$next[0:0]$8245 + end + connect \$56 $and$libresoc.v:159298$8149_Y + connect \cr_a$51 4'0000 + connect \cr_a_ok$52 1'0 + connect \p_ready_o \n_i_rdy_data + connect \n_valid_o \r_busy + connect { \xer_so_ok$78 \xer_so$77 } { \output_xer_so_ok \output_xer_so$48 } + connect { \xer_ov_ok$76 \xer_ov$75 } { \output_xer_ov_ok \output_xer_ov$47 } + connect { \cr_a_ok$74 \cr_a$73 } { \output_cr_a_ok \output_cr_a$46 } + connect { \o_ok$72 \o$71 } { \output_o_ok$45 \output_o$44 } + connect { \mul_op__insn$70 \mul_op__is_signed$69 \mul_op__is_32bit$68 \mul_op__write_cr0$67 \mul_op__oe__ok$66 \mul_op__oe__oe$65 \mul_op__rc__ok$64 \mul_op__rc__rc$63 \mul_op__imm_data__ok$62 \mul_op__imm_data__data$61 \mul_op__fn_unit$60 \mul_op__insn_type$59 } { \output_mul_op__insn$43 \output_mul_op__is_signed$42 \output_mul_op__is_32bit$41 \output_mul_op__write_cr0$40 \output_mul_op__oe__ok$39 \output_mul_op__oe__oe$38 \output_mul_op__rc__ok$37 \output_mul_op__rc__rc$36 \output_mul_op__imm_data__ok$35 \output_mul_op__imm_data__data$34 \output_mul_op__fn_unit$33 \output_mul_op__insn_type$32 } + connect \muxid$58 \output_muxid$31 + connect \p_valid_i_p_ready_o \$56 + connect \n_i_rdy_data \n_ready_i + connect \p_valid_i$55 \p_valid_i + connect { \xer_so_ok$54 \output_xer_so } { \mul3_xer_so_ok \mul3_xer_so$30 } + connect { \xer_ov_ok$53 \output_xer_ov } { \mul3_xer_ov_ok \mul3_xer_ov } + connect { \cr_a_ok$50 \output_cr_a } 5'00000 + connect { \output_o_ok \output_o } { \mul3_o_ok \mul3_o$29 } + connect { \output_mul_op__insn \output_mul_op__is_signed \output_mul_op__is_32bit \output_mul_op__write_cr0 \output_mul_op__oe__ok \output_mul_op__oe__oe \output_mul_op__rc__ok \output_mul_op__rc__rc \output_mul_op__imm_data__ok \output_mul_op__imm_data__data \output_mul_op__fn_unit \output_mul_op__insn_type } { \mul3_mul_op__insn$28 \mul3_mul_op__is_signed$27 \mul3_mul_op__is_32bit$26 \mul3_mul_op__write_cr0$25 \mul3_mul_op__oe__ok$24 \mul3_mul_op__oe__oe$23 \mul3_mul_op__rc__ok$22 \mul3_mul_op__rc__rc$21 \mul3_mul_op__imm_data__ok$20 \mul3_mul_op__imm_data__data$19 \mul3_mul_op__fn_unit$18 \mul3_mul_op__insn_type$17 } + connect \output_muxid \mul3_muxid$16 + connect \neg_res32$49 \neg_res32 + connect \mul3_neg_res \neg_res + connect \mul3_xer_so \xer_so + connect \mul3_o \o + connect { \mul3_mul_op__insn \mul3_mul_op__is_signed \mul3_mul_op__is_32bit \mul3_mul_op__write_cr0 \mul3_mul_op__oe__ok \mul3_mul_op__oe__oe \mul3_mul_op__rc__ok \mul3_mul_op__rc__rc \mul3_mul_op__imm_data__ok \mul3_mul_op__imm_data__data \mul3_mul_op__fn_unit \mul3_mul_op__insn_type } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__oe__ok \mul_op__oe__oe \mul_op__rc__ok \mul_op__rc__rc \mul_op__imm_data__ok \mul_op__imm_data__data \mul_op__fn_unit \mul_op__insn_type } + connect \mul3_muxid \muxid +end +attribute \src "libresoc.v:159601.1-159612.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.n" +attribute \generator "nMigen" +module \n + attribute \src "libresoc.v:159610.17-159610.111" + wire $and$libresoc.v:159610$8287_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire input 1 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire input 2 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" + wire \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" + cell $and $and$libresoc.v:159610$8287 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \n_ready_i + connect \B \n_valid_o + connect \Y $and$libresoc.v:159610$8287_Y + end + connect \$1 $and$libresoc.v:159610$8287_Y + connect \trigger \$1 +end +attribute \src "libresoc.v:159616.1-159627.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.n" +attribute \generator "nMigen" +module \n$109 + attribute \src "libresoc.v:159625.17-159625.111" + wire $and$libresoc.v:159625$8288_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire input 1 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire input 2 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" + wire \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" + cell $and $and$libresoc.v:159625$8288 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \n_ready_i + connect \B \n_valid_o + connect \Y $and$libresoc.v:159625$8288_Y + end + connect \$1 $and$libresoc.v:159625$8288_Y + connect \trigger \$1 +end +attribute \src "libresoc.v:159631.1-159642.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1.n" +attribute \generator "nMigen" +module \n$112 + attribute \src "libresoc.v:159640.17-159640.111" + wire $and$libresoc.v:159640$8289_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire input 1 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire input 2 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" + wire \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" + cell $and $and$libresoc.v:159640$8289 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \n_ready_i + connect \B \n_valid_o + connect \Y $and$libresoc.v:159640$8289_Y + end + connect \$1 $and$libresoc.v:159640$8289_Y + connect \trigger \$1 +end +attribute \src "libresoc.v:159646.1-159657.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe2.n" +attribute \generator "nMigen" +module \n$117 + attribute \src "libresoc.v:159655.17-159655.111" + wire $and$libresoc.v:159655$8290_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire input 1 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire input 2 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" + wire \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" + cell $and $and$libresoc.v:159655$8290 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \n_ready_i + connect \B \n_valid_o + connect \Y $and$libresoc.v:159655$8290_Y + end + connect \$1 $and$libresoc.v:159655$8290_Y + connect \trigger \$1 +end +attribute \src "libresoc.v:159661.1-159672.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.alu_branch0.n" +attribute \generator "nMigen" +module \n$18 + attribute \src "libresoc.v:159670.17-159670.111" + wire $and$libresoc.v:159670$8291_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire input 1 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire input 2 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" + wire \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" + cell $and $and$libresoc.v:159670$8291 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \n_ready_i + connect \B \n_valid_o + connect \Y $and$libresoc.v:159670$8291_Y + end + connect \$1 $and$libresoc.v:159670$8291_Y + connect \trigger \$1 +end +attribute \src "libresoc.v:159676.1-159687.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe1.n" +attribute \generator "nMigen" +module \n$2 + attribute \src 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always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:160019.3-160077.6" + process $proc$libresoc.v:160019$8313 + assign { } { } + assign { } { } + assign $0\spec[2:0] $1\spec[2:0] + attribute \src "libresoc.v:160020.5-160020.29" + switch \initial + attribute \src "libresoc.v:160020.9-160020.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:104" + switch \etype + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign $1\spec[2:0] [0] 1'0 + assign $1\spec[2:0] [2:1] $2\spec[2:1] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:107" + switch \idx + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $2\spec[2:1] [1] \extra [8] + assign $2\spec[2:1] [0] \extra [7] + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $2\spec[2:1] [1] \extra [6] + assign $2\spec[2:1] [0] \extra [5] + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $2\spec[2:1] [1] \extra [4] + assign $2\spec[2:1] [0] \extra [3] + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $2\spec[2:1] [1] \extra [2] + assign $2\spec[2:1] [0] \extra [1] + case + assign $2\spec[2:1] 2'00 + end + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\spec[2:0] $3\spec[2:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:122" + switch \idx + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $3\spec[2:0] \extra [8:6] + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $3\spec[2:0] \extra [5:3] + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $3\spec[2:0] \extra [2:0] + case + assign $3\spec[2:0] 3'000 + end + case + assign $1\spec[2:0] 3'000 + end + sync always + update \spec $0\spec[2:0] + end + attribute \src "libresoc.v:160078.3-160089.6" + process $proc$libresoc.v:160078$8314 + assign { } { } + assign $0\reg_out[6:0] $1\reg_out[6:0] + attribute \src "libresoc.v:160079.5-160079.29" + switch \initial + attribute \src "libresoc.v:160079.9-160079.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:166" + switch \isvec + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\reg_out[6:0] { \reg_in \spec [1:0] } + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\reg_out[6:0] { \spec [1:0] \reg_in } + end + sync always + update \reg_out $0\reg_out[6:0] + end + connect \idx 3'000 + connect \isvec \spec [2] +end +attribute \src "libresoc.v:160096.1-160196.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.o_svdec" +attribute \generator "nMigen" +module \o_svdec + attribute \src "libresoc.v:160097.7-160097.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:160183.3-160194.6" + wire width 7 $0\reg_out[6:0] + attribute \src "libresoc.v:160124.3-160182.6" + wire width 3 $0\spec[2:0] + attribute \src "libresoc.v:160183.3-160194.6" + wire width 7 $1\reg_out[6:0] + attribute \src "libresoc.v:160124.3-160182.6" + wire width 3 $1\spec[2:0] + attribute \src "libresoc.v:160124.3-160182.6" + wire width 2 $2\spec[2:1] + attribute \src "libresoc.v:160124.3-160182.6" + wire width 3 $3\spec[2:0] + attribute \enum_base_type "SVEtype" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "EXTRA2" + attribute \enum_value_10 "EXTRA3" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:90" + wire width 2 input 1 \etype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:89" + wire width 9 input 6 \extra + attribute \enum_base_type "SVEXTRA" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "Idx0" + attribute \enum_value_010 "Idx1" + attribute \enum_value_011 "Idx2" + attribute \enum_value_100 "Idx3" + attribute \enum_value_101 "Idx_1_2" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:91" + wire width 3 input 5 \idx + attribute \src "libresoc.v:160097.7-160097.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:149" + wire output 3 \isvec + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:147" + wire width 5 input 2 \reg_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:148" + wire width 7 output 4 \reg_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92" + wire width 3 \spec + attribute \src "libresoc.v:160097.7-160097.20" + process $proc$libresoc.v:160097$8318 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:160124.3-160182.6" + process $proc$libresoc.v:160124$8316 + assign { } { } + assign { } { } + assign $0\spec[2:0] $1\spec[2:0] + attribute \src "libresoc.v:160125.5-160125.29" + switch \initial + attribute \src "libresoc.v:160125.9-160125.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:104" + switch \etype + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign $1\spec[2:0] [0] 1'0 + assign $1\spec[2:0] [2:1] $2\spec[2:1] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:107" + switch \idx + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $2\spec[2:1] [1] \extra [8] + assign $2\spec[2:1] [0] \extra [7] + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $2\spec[2:1] [1] \extra [6] + assign $2\spec[2:1] [0] \extra [5] + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $2\spec[2:1] [1] \extra [4] + assign $2\spec[2:1] [0] \extra [3] + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign { } { } + assign $2\spec[2:1] [1] \extra [2] + assign $2\spec[2:1] [0] \extra [1] + case + assign $2\spec[2:1] 2'00 + end + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\spec[2:0] $3\spec[2:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:122" + switch \idx + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign { } { } + assign $3\spec[2:0] \extra [8:6] + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign { } { } + assign $3\spec[2:0] \extra [5:3] + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign { } { } + assign $3\spec[2:0] \extra [2:0] + case + assign $3\spec[2:0] 3'000 + end + case + assign $1\spec[2:0] 3'000 + end + sync always + update \spec $0\spec[2:0] + end + attribute \src "libresoc.v:160183.3-160194.6" + process $proc$libresoc.v:160183$8317 + assign { } { } + assign $0\reg_out[6:0] $1\reg_out[6:0] + attribute \src "libresoc.v:160184.5-160184.29" + switch \initial + attribute \src "libresoc.v:160184.9-160184.17" + case 1'1 + case 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$not$libresoc.v:160300$8335 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_opc + connect \Y $not$libresoc.v:160300$8335_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:160302$8337 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_opc + connect \Y $not$libresoc.v:160302$8337_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:160305$8340 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_opc + connect \Y $not$libresoc.v:160305$8340_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:160299$8334 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_opc + connect \Y $or$libresoc.v:160299$8334_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:160301$8336 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_opc + connect \B \q_int + connect \Y $or$libresoc.v:160301$8336_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:160304$8339 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_opc + connect \Y $or$libresoc.v:160304$8339_Y + end + attribute \src "libresoc.v:160263.7-160263.20" + process $proc$libresoc.v:160263$8345 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:160285.7-160285.19" + process $proc$libresoc.v:160285$8346 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] 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\q_opc + connect \Y $not$libresoc.v:160362$8349_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:160364$8351 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_opc + connect \Y $not$libresoc.v:160364$8351_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:160367$8354 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_opc + connect \Y $not$libresoc.v:160367$8354_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:160361$8348 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_opc + connect \Y $or$libresoc.v:160361$8348_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:160363$8350 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_opc + connect \B \q_int + connect \Y $or$libresoc.v:160363$8350_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:160366$8353 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_opc + connect \Y $or$libresoc.v:160366$8353_Y + end + attribute \src "libresoc.v:160325.7-160325.20" + process $proc$libresoc.v:160325$8359 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:160347.7-160347.19" + process $proc$libresoc.v:160347$8360 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:160368.3-160369.27" + process $proc$libresoc.v:160368$8355 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:160370.3-160378.6" + process $proc$libresoc.v:160370$8356 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$8357 $1\q_int$next[0:0]$8358 + attribute \src "libresoc.v:160371.5-160371.29" + switch \initial + attribute \src "libresoc.v:160371.9-160371.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$8358 1'0 + case + assign $1\q_int$next[0:0]$8358 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$8357 + end + connect \$9 $and$libresoc.v:160360$8347_Y + connect \$11 $or$libresoc.v:160361$8348_Y + connect \$13 $not$libresoc.v:160362$8349_Y + connect \$15 $or$libresoc.v:160363$8350_Y + connect \$1 $not$libresoc.v:160364$8351_Y + connect \$3 $and$libresoc.v:160365$8352_Y + connect \$5 $or$libresoc.v:160366$8353_Y + connect \$7 $not$libresoc.v:160367$8354_Y + connect \qlq_opc \$15 + connect \qn_opc \$13 + connect \q_opc \$11 +end +attribute \src "libresoc.v:160386.1-160444.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.opc_l" +attribute \generator "nMigen" +module \opc_l$120 + attribute \src "libresoc.v:160387.7-160387.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:160432.3-160440.6" + wire $0\q_int$next[0:0]$8371 + attribute \src "libresoc.v:160430.3-160431.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:160432.3-160440.6" + wire $1\q_int$next[0:0]$8372 + attribute \src "libresoc.v:160409.7-160409.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:160422.17-160422.96" + wire $and$libresoc.v:160422$8361_Y + attribute \src "libresoc.v:160427.17-160427.96" + wire $and$libresoc.v:160427$8366_Y + attribute \src "libresoc.v:160424.18-160424.93" + wire $not$libresoc.v:160424$8363_Y + attribute \src "libresoc.v:160426.17-160426.92" + wire $not$libresoc.v:160426$8365_Y + attribute \src "libresoc.v:160429.17-160429.92" + wire $not$libresoc.v:160429$8368_Y + attribute \src "libresoc.v:160423.18-160423.98" + wire $or$libresoc.v:160423$8362_Y + attribute \src "libresoc.v:160425.18-160425.99" + wire $or$libresoc.v:160425$8364_Y + attribute \src "libresoc.v:160428.17-160428.97" + wire $or$libresoc.v:160428$8367_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 1 \coresync_rst + attribute \src "libresoc.v:160387.7-160387.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire output 4 \q_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" + wire \qlq_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \qn_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire input 3 \r_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire input 2 \s_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:160422$8361 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:160422$8361_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:160427$8366 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:160427$8366_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:160424$8363 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_opc + connect \Y $not$libresoc.v:160424$8363_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:160426$8365 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_opc + connect \Y $not$libresoc.v:160426$8365_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:160429$8368 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_opc + connect \Y $not$libresoc.v:160429$8368_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:160423$8362 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_opc + connect \Y $or$libresoc.v:160423$8362_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:160425$8364 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_opc + connect \B \q_int + connect \Y $or$libresoc.v:160425$8364_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:160428$8367 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_opc + connect \Y $or$libresoc.v:160428$8367_Y + end + attribute \src "libresoc.v:160387.7-160387.20" + process $proc$libresoc.v:160387$8373 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:160409.7-160409.19" + process $proc$libresoc.v:160409$8374 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:160430.3-160431.27" + process $proc$libresoc.v:160430$8369 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:160432.3-160440.6" + process $proc$libresoc.v:160432$8370 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$8371 $1\q_int$next[0:0]$8372 + attribute \src "libresoc.v:160433.5-160433.29" + switch \initial + attribute \src "libresoc.v:160433.9-160433.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$8372 1'0 + case + assign $1\q_int$next[0:0]$8372 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$8371 + end + connect \$9 $and$libresoc.v:160422$8361_Y + connect \$11 $or$libresoc.v:160423$8362_Y + connect \$13 $not$libresoc.v:160424$8363_Y + connect \$15 $or$libresoc.v:160425$8364_Y + connect \$1 $not$libresoc.v:160426$8365_Y + connect \$3 $and$libresoc.v:160427$8366_Y + connect \$5 $or$libresoc.v:160428$8367_Y + connect \$7 $not$libresoc.v:160429$8368_Y + connect \qlq_opc \$15 + connect \qn_opc \$13 + connect \q_opc \$11 +end +attribute \src "libresoc.v:160448.1-160506.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.opc_l" +attribute \generator "nMigen" +module \opc_l$126 + attribute \src "libresoc.v:160449.7-160449.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:160494.3-160502.6" + wire $0\q_int$next[0:0]$8385 + attribute \src "libresoc.v:160492.3-160493.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:160494.3-160502.6" + wire $1\q_int$next[0:0]$8386 + attribute \src "libresoc.v:160471.7-160471.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:160484.17-160484.96" + wire $and$libresoc.v:160484$8375_Y + attribute \src "libresoc.v:160489.17-160489.96" + wire $and$libresoc.v:160489$8380_Y + attribute \src "libresoc.v:160486.18-160486.93" + wire $not$libresoc.v:160486$8377_Y + attribute \src "libresoc.v:160488.17-160488.92" + wire $not$libresoc.v:160488$8379_Y + attribute \src "libresoc.v:160491.17-160491.92" + wire $not$libresoc.v:160491$8382_Y + attribute \src "libresoc.v:160485.18-160485.98" + wire $or$libresoc.v:160485$8376_Y + attribute \src "libresoc.v:160487.18-160487.99" + wire $or$libresoc.v:160487$8378_Y + attribute \src "libresoc.v:160490.17-160490.97" + wire $or$libresoc.v:160490$8381_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 1 \coresync_rst + attribute \src "libresoc.v:160449.7-160449.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire output 4 \q_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" + wire \qlq_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \qn_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire input 3 \r_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire input 2 \s_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:160484$8375 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:160484$8375_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:160489$8380 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:160489$8380_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:160486$8377 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_opc + connect \Y $not$libresoc.v:160486$8377_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:160488$8379 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_opc + connect \Y $not$libresoc.v:160488$8379_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:160491$8382 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_opc + connect \Y $not$libresoc.v:160491$8382_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:160485$8376 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_opc + connect \Y $or$libresoc.v:160485$8376_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:160487$8378 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_opc + connect \B \q_int + connect \Y $or$libresoc.v:160487$8378_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:160490$8381 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_opc + connect \Y $or$libresoc.v:160490$8381_Y + end + attribute \src "libresoc.v:160449.7-160449.20" + process $proc$libresoc.v:160449$8387 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:160471.7-160471.19" + process $proc$libresoc.v:160471$8388 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:160492.3-160493.27" + process $proc$libresoc.v:160492$8383 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:160494.3-160502.6" + process $proc$libresoc.v:160494$8384 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$8385 $1\q_int$next[0:0]$8386 + attribute \src "libresoc.v:160495.5-160495.29" + switch \initial + attribute \src "libresoc.v:160495.9-160495.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$8386 1'0 + case + assign $1\q_int$next[0:0]$8386 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$8385 + end + connect \$9 $and$libresoc.v:160484$8375_Y + connect \$11 $or$libresoc.v:160485$8376_Y + connect \$13 $not$libresoc.v:160486$8377_Y + connect \$15 $or$libresoc.v:160487$8378_Y + connect \$1 $not$libresoc.v:160488$8379_Y + connect \$3 $and$libresoc.v:160489$8380_Y + connect \$5 $or$libresoc.v:160490$8381_Y + connect \$7 $not$libresoc.v:160491$8382_Y + connect \qlq_opc \$15 + connect \qn_opc \$13 + connect \q_opc \$11 +end +attribute \src "libresoc.v:160510.1-160568.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.opc_l" +attribute \generator "nMigen" +module \opc_l$24 + attribute \src "libresoc.v:160511.7-160511.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:160556.3-160564.6" + wire $0\q_int$next[0:0]$8399 + attribute \src "libresoc.v:160554.3-160555.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:160556.3-160564.6" + wire $1\q_int$next[0:0]$8400 + attribute \src "libresoc.v:160533.7-160533.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:160546.17-160546.96" + wire $and$libresoc.v:160546$8389_Y + attribute \src "libresoc.v:160551.17-160551.96" + wire $and$libresoc.v:160551$8394_Y + attribute \src "libresoc.v:160548.18-160548.93" + wire $not$libresoc.v:160548$8391_Y + attribute \src "libresoc.v:160550.17-160550.92" + wire $not$libresoc.v:160550$8393_Y + attribute \src "libresoc.v:160553.17-160553.92" + wire $not$libresoc.v:160553$8396_Y + attribute \src "libresoc.v:160547.18-160547.98" + wire $or$libresoc.v:160547$8390_Y + attribute \src "libresoc.v:160549.18-160549.99" + wire $or$libresoc.v:160549$8392_Y + attribute \src "libresoc.v:160552.17-160552.97" + wire $or$libresoc.v:160552$8395_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 1 \coresync_rst + attribute \src "libresoc.v:160511.7-160511.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire output 4 \q_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" + wire \qlq_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \qn_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire input 3 \r_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire input 2 \s_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:160546$8389 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:160546$8389_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:160551$8394 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:160551$8394_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:160548$8391 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_opc + connect \Y $not$libresoc.v:160548$8391_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:160550$8393 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_opc + connect \Y $not$libresoc.v:160550$8393_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:160553$8396 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_opc + connect \Y $not$libresoc.v:160553$8396_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:160547$8390 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_opc + connect \Y $or$libresoc.v:160547$8390_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:160549$8392 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_opc + connect \B \q_int + connect \Y $or$libresoc.v:160549$8392_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:160552$8395 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_opc + connect \Y $or$libresoc.v:160552$8395_Y + end + attribute \src "libresoc.v:160511.7-160511.20" + process $proc$libresoc.v:160511$8401 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:160533.7-160533.19" + process $proc$libresoc.v:160533$8402 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:160554.3-160555.27" + process $proc$libresoc.v:160554$8397 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:160556.3-160564.6" + process $proc$libresoc.v:160556$8398 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$8399 $1\q_int$next[0:0]$8400 + attribute \src "libresoc.v:160557.5-160557.29" + switch \initial + attribute \src "libresoc.v:160557.9-160557.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$8400 1'0 + case + assign $1\q_int$next[0:0]$8400 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$8399 + end + connect \$9 $and$libresoc.v:160546$8389_Y + connect \$11 $or$libresoc.v:160547$8390_Y + connect \$13 $not$libresoc.v:160548$8391_Y + connect \$15 $or$libresoc.v:160549$8392_Y + connect \$1 $not$libresoc.v:160550$8393_Y + connect \$3 $and$libresoc.v:160551$8394_Y + connect \$5 $or$libresoc.v:160552$8395_Y + connect \$7 $not$libresoc.v:160553$8396_Y + connect \qlq_opc \$15 + connect \qn_opc \$13 + connect \q_opc \$11 +end +attribute \src "libresoc.v:160572.1-160630.10" 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"libresoc.v:160609.18-160609.98" + wire $or$libresoc.v:160609$8404_Y + attribute \src "libresoc.v:160611.18-160611.99" + wire $or$libresoc.v:160611$8406_Y + attribute \src "libresoc.v:160614.17-160614.97" + wire $or$libresoc.v:160614$8409_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 1 \coresync_rst + attribute \src "libresoc.v:160573.7-160573.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire output 4 \q_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" + wire \qlq_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \qn_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire input 3 \r_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire input 2 \s_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:160608$8403 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:160608$8403_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:160613$8408 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:160613$8408_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:160610$8405 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_opc + connect \Y $not$libresoc.v:160610$8405_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:160612$8407 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_opc + connect \Y $not$libresoc.v:160612$8407_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:160615$8410 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_opc + connect \Y $not$libresoc.v:160615$8410_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:160609$8404 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_opc + connect \Y $or$libresoc.v:160609$8404_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:160611$8406 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_opc + connect \B \q_int + connect \Y $or$libresoc.v:160611$8406_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:160614$8409 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_opc + connect \Y $or$libresoc.v:160614$8409_Y + end + attribute \src "libresoc.v:160573.7-160573.20" + process $proc$libresoc.v:160573$8415 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:160595.7-160595.19" + process $proc$libresoc.v:160595$8416 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:160616.3-160617.27" + process $proc$libresoc.v:160616$8411 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:160618.3-160626.6" + process $proc$libresoc.v:160618$8412 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$8413 $1\q_int$next[0:0]$8414 + attribute \src "libresoc.v:160619.5-160619.29" + switch \initial + attribute \src "libresoc.v:160619.9-160619.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$8414 1'0 + case + assign $1\q_int$next[0:0]$8414 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$8413 + end + connect \$9 $and$libresoc.v:160608$8403_Y + connect \$11 $or$libresoc.v:160609$8404_Y + connect \$13 $not$libresoc.v:160610$8405_Y + connect \$15 $or$libresoc.v:160611$8406_Y + connect \$1 $not$libresoc.v:160612$8407_Y + connect \$3 $and$libresoc.v:160613$8408_Y + connect \$5 $or$libresoc.v:160614$8409_Y + connect \$7 $not$libresoc.v:160615$8410_Y + connect \qlq_opc \$15 + connect \qn_opc \$13 + connect \q_opc \$11 +end +attribute \src "libresoc.v:160634.1-160692.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.opc_l" +attribute \generator "nMigen" +module \opc_l$56 + attribute \src "libresoc.v:160635.7-160635.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:160680.3-160688.6" + wire $0\q_int$next[0:0]$8427 + attribute \src "libresoc.v:160678.3-160679.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:160680.3-160688.6" + wire $1\q_int$next[0:0]$8428 + attribute \src "libresoc.v:160657.7-160657.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:160670.17-160670.96" + wire $and$libresoc.v:160670$8417_Y + attribute \src "libresoc.v:160675.17-160675.96" + wire $and$libresoc.v:160675$8422_Y + attribute \src "libresoc.v:160672.18-160672.93" + wire $not$libresoc.v:160672$8419_Y + attribute \src "libresoc.v:160674.17-160674.92" + wire $not$libresoc.v:160674$8421_Y + attribute \src "libresoc.v:160677.17-160677.92" + wire $not$libresoc.v:160677$8424_Y + attribute \src "libresoc.v:160671.18-160671.98" + wire $or$libresoc.v:160671$8418_Y + attribute \src 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"/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 1 \coresync_rst + attribute \src "libresoc.v:160635.7-160635.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire output 4 \q_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" + wire \qlq_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \qn_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire input 3 \r_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire input 2 \s_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:160670$8417 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:160670$8417_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:160675$8422 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:160675$8422_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:160672$8419 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_opc + connect \Y $not$libresoc.v:160672$8419_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:160674$8421 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_opc + connect \Y $not$libresoc.v:160674$8421_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:160677$8424 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_opc + connect \Y $not$libresoc.v:160677$8424_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:160671$8418 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_opc + connect \Y $or$libresoc.v:160671$8418_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:160673$8420 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_opc + connect \B \q_int + connect \Y $or$libresoc.v:160673$8420_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:160676$8423 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_opc + connect \Y $or$libresoc.v:160676$8423_Y + end + attribute \src "libresoc.v:160635.7-160635.20" + process $proc$libresoc.v:160635$8429 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:160657.7-160657.19" + process $proc$libresoc.v:160657$8430 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:160678.3-160679.27" + process $proc$libresoc.v:160678$8425 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:160680.3-160688.6" + process $proc$libresoc.v:160680$8426 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$8427 $1\q_int$next[0:0]$8428 + attribute \src "libresoc.v:160681.5-160681.29" + switch \initial + attribute \src "libresoc.v:160681.9-160681.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$8428 1'0 + case + assign $1\q_int$next[0:0]$8428 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$8427 + end + connect \$9 $and$libresoc.v:160670$8417_Y + connect \$11 $or$libresoc.v:160671$8418_Y + connect \$13 $not$libresoc.v:160672$8419_Y + connect \$15 $or$libresoc.v:160673$8420_Y + connect \$1 $not$libresoc.v:160674$8421_Y + connect \$3 $and$libresoc.v:160675$8422_Y + connect \$5 $or$libresoc.v:160676$8423_Y + connect \$7 $not$libresoc.v:160677$8424_Y + connect \qlq_opc \$15 + connect \qn_opc \$13 + connect \q_opc \$11 +end +attribute \src "libresoc.v:160696.1-160754.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.opc_l" +attribute \generator "nMigen" +module \opc_l$68 + attribute \src "libresoc.v:160697.7-160697.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:160742.3-160750.6" + wire $0\q_int$next[0:0]$8441 + attribute \src "libresoc.v:160740.3-160741.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:160742.3-160750.6" + wire $1\q_int$next[0:0]$8442 + attribute \src "libresoc.v:160719.7-160719.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:160732.17-160732.96" + wire $and$libresoc.v:160732$8431_Y + attribute \src "libresoc.v:160737.17-160737.96" + wire $and$libresoc.v:160737$8436_Y + attribute \src "libresoc.v:160734.18-160734.93" + wire $not$libresoc.v:160734$8433_Y + attribute \src "libresoc.v:160736.17-160736.92" + wire $not$libresoc.v:160736$8435_Y + attribute \src "libresoc.v:160739.17-160739.92" + wire $not$libresoc.v:160739$8438_Y + attribute \src "libresoc.v:160733.18-160733.98" + wire $or$libresoc.v:160733$8432_Y + attribute \src "libresoc.v:160735.18-160735.99" + wire $or$libresoc.v:160735$8434_Y + attribute \src "libresoc.v:160738.17-160738.97" + wire $or$libresoc.v:160738$8437_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 1 \coresync_rst + attribute \src "libresoc.v:160697.7-160697.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire output 4 \q_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" + wire \qlq_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \qn_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire input 3 \r_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire input 2 \s_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:160732$8431 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:160732$8431_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:160737$8436 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:160737$8436_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:160734$8433 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_opc + connect \Y $not$libresoc.v:160734$8433_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:160736$8435 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_opc + connect \Y $not$libresoc.v:160736$8435_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:160739$8438 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_opc + connect \Y $not$libresoc.v:160739$8438_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:160733$8432 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_opc + connect \Y $or$libresoc.v:160733$8432_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:160735$8434 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_opc + connect \B \q_int + connect \Y $or$libresoc.v:160735$8434_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:160738$8437 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_opc + connect \Y $or$libresoc.v:160738$8437_Y + end + attribute \src "libresoc.v:160697.7-160697.20" + process $proc$libresoc.v:160697$8443 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:160719.7-160719.19" + process $proc$libresoc.v:160719$8444 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:160740.3-160741.27" + process $proc$libresoc.v:160740$8439 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:160742.3-160750.6" + process $proc$libresoc.v:160742$8440 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$8441 $1\q_int$next[0:0]$8442 + attribute \src "libresoc.v:160743.5-160743.29" + switch \initial + attribute \src "libresoc.v:160743.9-160743.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$8442 1'0 + case + assign $1\q_int$next[0:0]$8442 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$8441 + end + connect \$9 $and$libresoc.v:160732$8431_Y + connect \$11 $or$libresoc.v:160733$8432_Y + connect \$13 $not$libresoc.v:160734$8433_Y + connect \$15 $or$libresoc.v:160735$8434_Y + connect \$1 $not$libresoc.v:160736$8435_Y + connect \$3 $and$libresoc.v:160737$8436_Y + connect \$5 $or$libresoc.v:160738$8437_Y + connect \$7 $not$libresoc.v:160739$8438_Y + connect \qlq_opc \$15 + connect \qn_opc \$13 + connect \q_opc \$11 +end +attribute \src "libresoc.v:160758.1-160816.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.opc_l" +attribute \generator "nMigen" +module \opc_l$85 + attribute \src "libresoc.v:160759.7-160759.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:160804.3-160812.6" + wire $0\q_int$next[0:0]$8455 + attribute \src "libresoc.v:160802.3-160803.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:160804.3-160812.6" + wire $1\q_int$next[0:0]$8456 + attribute \src "libresoc.v:160781.7-160781.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:160794.17-160794.96" + wire $and$libresoc.v:160794$8445_Y + attribute \src "libresoc.v:160799.17-160799.96" + wire $and$libresoc.v:160799$8450_Y + attribute \src "libresoc.v:160796.18-160796.93" + wire $not$libresoc.v:160796$8447_Y + attribute \src "libresoc.v:160798.17-160798.92" + wire $not$libresoc.v:160798$8449_Y + attribute \src "libresoc.v:160801.17-160801.92" + wire $not$libresoc.v:160801$8452_Y + attribute \src "libresoc.v:160795.18-160795.98" + wire $or$libresoc.v:160795$8446_Y + attribute \src "libresoc.v:160797.18-160797.99" + wire $or$libresoc.v:160797$8448_Y + attribute \src "libresoc.v:160800.17-160800.97" + wire $or$libresoc.v:160800$8451_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 1 \coresync_rst + attribute \src "libresoc.v:160759.7-160759.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire output 4 \q_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" + wire \qlq_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \qn_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire input 3 \r_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire input 2 \s_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:160794$8445 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:160794$8445_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:160799$8450 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:160799$8450_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:160796$8447 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_opc + connect \Y $not$libresoc.v:160796$8447_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:160798$8449 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_opc + connect \Y $not$libresoc.v:160798$8449_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:160801$8452 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_opc + connect \Y $not$libresoc.v:160801$8452_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:160795$8446 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_opc + connect \Y $or$libresoc.v:160795$8446_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:160797$8448 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_opc + connect \B \q_int + connect \Y $or$libresoc.v:160797$8448_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:160800$8451 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_opc + connect \Y $or$libresoc.v:160800$8451_Y + end + attribute \src "libresoc.v:160759.7-160759.20" + process $proc$libresoc.v:160759$8457 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:160781.7-160781.19" + process $proc$libresoc.v:160781$8458 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:160802.3-160803.27" + process $proc$libresoc.v:160802$8453 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:160804.3-160812.6" + process $proc$libresoc.v:160804$8454 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$8455 $1\q_int$next[0:0]$8456 + attribute \src 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attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute 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attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute 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"/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 33 \alu_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \alu_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 39 \alu_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 6 \alu_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 31 \alu_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 5 \alu_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 30 \alu_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \alu_op__write_cr0 + attribute \src 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 49 \xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 input 23 \xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 output 50 \xer_ov$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 51 \xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire input 24 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 52 \xer_so$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 53 \xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29" + cell $and $and$libresoc.v:161168$8459 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 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parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \alu_op__insn_type + connect \B 7'0001010 + connect \Y $eq$libresoc.v:161172$8465_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" + cell $eq $eq$libresoc.v:161173$8466 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \alu_op__insn_type + connect \B 7'0001100 + connect \Y $eq$libresoc.v:161173$8466_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" + cell $pos $extend$libresoc.v:161170$8461 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \$30 + connect \Y $extend$libresoc.v:161170$8461_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + cell $pos $extend$libresoc.v:161171$8463 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \o + connect \Y $extend$libresoc.v:161171$8463_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" + cell $not $not$libresoc.v:161169$8460 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \o + connect \Y $not$libresoc.v:161169$8460_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" + cell $not $not$libresoc.v:161175$8468 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \msb_test + connect \Y $not$libresoc.v:161175$8468_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" + cell $not $not$libresoc.v:161178$8471 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_nzero + connect \Y $not$libresoc.v:161178$8471_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" + cell $or $or$libresoc.v:161177$8470 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_cmpeqb + connect \B \is_cmp + connect \Y $or$libresoc.v:161177$8470_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:33" + cell $or $or$libresoc.v:161180$8473 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \xer_so + connect \B \xer_ov [0] + connect \Y $or$libresoc.v:161180$8473_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" + cell $pos $pos$libresoc.v:161170$8462 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \Y_WIDTH 65 + connect \A $extend$libresoc.v:161170$8461_Y + connect \Y $pos$libresoc.v:161170$8462_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + cell $pos $pos$libresoc.v:161171$8464 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \Y_WIDTH 65 + connect \A $extend$libresoc.v:161171$8463_Y + connect \Y $pos$libresoc.v:161171$8464_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" + cell $reduce_or $reduce_or$libresoc.v:161174$8467 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 1 + connect \A \target + connect \Y $reduce_or$libresoc.v:161174$8467_Y + end + attribute \src "libresoc.v:160821.7-160821.20" + process $proc$libresoc.v:160821$8487 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:161181.3-161192.6" + process $proc$libresoc.v:161181$8474 + assign { } { } + assign $0\so[0:0] $1\so[0:0] + attribute \src "libresoc.v:161182.5-161182.29" + switch \initial + attribute \src "libresoc.v:161182.9-161182.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:30" + switch \oe + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\so[0:0] \xer_so$25 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\so[0:0] \xer_so + end + sync always + update \so $0\so[0:0] + end + attribute \src "libresoc.v:161193.3-161204.6" + process $proc$libresoc.v:161193$8475 + assign { } { } + assign $0\cr0[3:0] $1\cr0[3:0] + attribute \src "libresoc.v:161194.5-161194.29" + switch \initial + attribute \src "libresoc.v:161194.9-161194.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" + switch \$45 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cr0[3:0] \cr_a + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cr0[3:0] { \is_negative \is_positive \$47 \so } + end + sync always + update \cr0 $0\cr0[3:0] + end + attribute \src "libresoc.v:161205.3-161216.6" + process $proc$libresoc.v:161205$8476 + assign { } { } + assign $0\o$28[64:0]$8477 $1\o$28[64:0]$8478 + attribute \src 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\$52 + case + assign $1\xer_so$25[0:0]$8481 1'0 + end + sync always + update \xer_so$25 $0\xer_so$25[0:0]$8480 + end + attribute \src "libresoc.v:161227.3-161236.6" + process $proc$libresoc.v:161227$8482 + assign { } { } + assign { } { } + assign $0\xer_so_ok[0:0] $1\xer_so_ok[0:0] + attribute \src "libresoc.v:161228.5-161228.29" + switch \initial + attribute \src "libresoc.v:161228.9-161228.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" + switch \oe$49 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\xer_so_ok[0:0] 1'1 + case + assign $1\xer_so_ok[0:0] 1'0 + end + sync always + update \xer_so_ok $0\xer_so_ok[0:0] + end + attribute \src "libresoc.v:161237.3-161246.6" + process $proc$libresoc.v:161237$8483 + assign { } { } + assign { } { } + assign $0\xer_ov$24[1:0]$8484 $1\xer_ov$24[1:0]$8485 + attribute \src "libresoc.v:161238.5-161238.29" + switch \initial + attribute \src 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\src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:65" + wire \is_nzero + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:66" + wire \is_positive + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:68" + wire \msb_test + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 input 2 \mul_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 output 20 \mul_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 3 \mul_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 21 \mul_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 4 \mul_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 22 \mul_op__imm_data__ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 12 \mul_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 30 \mul_op__insn$13 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \mul_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 19 \mul_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \mul_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 28 \mul_op__is_32bit$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 11 \mul_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 29 \mul_op__is_signed$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 7 \mul_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 25 \mul_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \mul_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 26 \mul_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 6 \mul_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 24 \mul_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 5 \mul_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 23 \mul_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \mul_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 27 \mul_op__write_cr0$10 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 input 39 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 output 18 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 input 13 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 31 \o$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:38" + wire width 65 \o$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire input 14 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 32 \o_ok$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:28" + wire \oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:29" + wire \oe$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:27" + wire \so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:50" + wire width 64 \target + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 input 16 \xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 output 35 \xer_ov$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 36 \xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire input 17 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 37 \xer_so$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 38 \xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29" + cell $and $and$libresoc.v:161584$8488 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \mul_op__oe__oe + connect \B \mul_op__oe__ok + connect \Y $and$libresoc.v:161584$8488_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" + cell $and $and$libresoc.v:161590$8495 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_nzero + connect \B \$30 + connect \Y $and$libresoc.v:161590$8495_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" + cell $and $and$libresoc.v:161593$8498 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \mul_op__oe__oe + connect \B \mul_op__oe__ok + connect \Y $and$libresoc.v:161593$8498_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" + cell $eq $eq$libresoc.v:161586$8491 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \mul_op__insn_type + connect \B 7'0001010 + connect \Y $eq$libresoc.v:161586$8491_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" + cell $eq $eq$libresoc.v:161587$8492 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \mul_op__insn_type + connect \B 7'0001100 + connect \Y $eq$libresoc.v:161587$8492_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + cell $pos $extend$libresoc.v:161585$8489 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \o + connect \Y $extend$libresoc.v:161585$8489_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" + cell $not $not$libresoc.v:161589$8494 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \msb_test + connect \Y $not$libresoc.v:161589$8494_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" + cell $not $not$libresoc.v:161592$8497 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_nzero + connect \Y $not$libresoc.v:161592$8497_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" + cell $or $or$libresoc.v:161591$8496 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_cmpeqb + connect \B \is_cmp + connect \Y $or$libresoc.v:161591$8496_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:33" + cell $or $or$libresoc.v:161594$8499 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \xer_so + connect \B \xer_ov [0] + connect \Y $or$libresoc.v:161594$8499_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + cell $pos $pos$libresoc.v:161585$8490 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \Y_WIDTH 65 + connect \A $extend$libresoc.v:161585$8489_Y + connect \Y $pos$libresoc.v:161585$8490_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" + cell $reduce_or $reduce_or$libresoc.v:161588$8493 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 1 + connect \A \target + connect \Y $reduce_or$libresoc.v:161588$8493_Y + end + attribute \src "libresoc.v:161279.7-161279.20" + process $proc$libresoc.v:161279$8510 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:161595.3-161606.6" + process $proc$libresoc.v:161595$8500 + assign { } { } + assign $0\so[0:0] $1\so[0:0] + attribute \src "libresoc.v:161596.5-161596.29" + switch \initial + attribute \src "libresoc.v:161596.9-161596.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:30" + switch \oe + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\so[0:0] \xer_so$18 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\so[0:0] \xer_so + end + sync always + update \so $0\so[0:0] + end + attribute \src "libresoc.v:161607.3-161618.6" + process $proc$libresoc.v:161607$8501 + assign { } { } + assign $0\cr0[3:0] $1\cr0[3:0] + attribute \src "libresoc.v:161608.5-161608.29" + switch \initial + attribute \src "libresoc.v:161608.9-161608.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" + switch \$34 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cr0[3:0] \cr_a + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cr0[3:0] { \is_negative \is_positive \$36 \so } + end + sync always + update \cr0 $0\cr0[3:0] + end + attribute \src "libresoc.v:161619.3-161628.6" + process $proc$libresoc.v:161619$8502 + assign { } { } + assign { } { } + assign $0\xer_so$18[0:0]$8503 $1\xer_so$18[0:0]$8504 + attribute \src "libresoc.v:161620.5-161620.29" + switch \initial + attribute \src "libresoc.v:161620.9-161620.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" + switch \oe$38 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\xer_so$18[0:0]$8504 \$41 + case + assign $1\xer_so$18[0:0]$8504 1'0 + end + sync always + update \xer_so$18 $0\xer_so$18[0:0]$8503 + end + attribute \src "libresoc.v:161629.3-161638.6" + process $proc$libresoc.v:161629$8505 + assign { } { } + assign { } { } + assign $0\xer_so_ok[0:0] $1\xer_so_ok[0:0] + attribute \src "libresoc.v:161630.5-161630.29" + switch \initial + attribute \src "libresoc.v:161630.9-161630.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" + switch \oe$38 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\xer_so_ok[0:0] 1'1 + case + assign $1\xer_so_ok[0:0] 1'0 + end + sync always + update \xer_so_ok $0\xer_so_ok[0:0] + end + attribute \src "libresoc.v:161639.3-161648.6" + process $proc$libresoc.v:161639$8506 + assign { } { } + assign { } { } + assign $0\xer_ov$17[1:0]$8507 $1\xer_ov$17[1:0]$8508 + attribute \src "libresoc.v:161640.5-161640.29" + switch \initial + attribute \src "libresoc.v:161640.9-161640.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" + switch \oe$38 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\xer_ov$17[1:0]$8508 \xer_ov + case + assign $1\xer_ov$17[1:0]$8508 2'00 + end + sync always + update \xer_ov$17 $0\xer_ov$17[1:0]$8507 + end + attribute \src "libresoc.v:161649.3-161658.6" + process $proc$libresoc.v:161649$8509 + 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\enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \sr_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute 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input 17 \logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 41 \logical_op__data_len$18 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 input 2 \logical_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 output 26 \logical_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 3 \logical_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 27 \logical_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 4 \logical_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 28 \logical_op__imm_data__ok$5 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 11 \logical_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 35 \logical_op__input_carry$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 18 \logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 42 \logical_op__insn$19 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \logical_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 25 \logical_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 33 \logical_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 36 \logical_op__invert_out$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 15 \logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 39 \logical_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 16 \logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 40 \logical_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 7 \logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 31 \logical_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 32 \logical_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 38 \logical_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 6 \logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 30 \logical_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 5 \logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 29 \logical_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 37 \logical_op__write_cr0$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 34 \logical_op__zero_a$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:68" + wire \msb_test + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 input 51 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 output 24 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 input 19 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 43 \o$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:38" + wire width 65 \o$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire input 20 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 44 \o_ok$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:28" + wire \oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:29" + wire \oe$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:27" + wire \so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:50" + wire width 64 \target + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 input 22 \xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 output 47 \xer_ov$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 48 \xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire input 23 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 49 \xer_so$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 50 \xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29" + cell $and $and$libresoc.v:162742$8539 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \logical_op__oe__oe + connect \B \logical_op__oe__ok + connect \Y $and$libresoc.v:162742$8539_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" + cell $and $and$libresoc.v:162750$8549 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_nzero + connect \B \$40 + connect \Y $and$libresoc.v:162750$8549_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" + cell $and $and$libresoc.v:162753$8552 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \logical_op__oe__oe + connect \B \logical_op__oe__ok + connect \Y $and$libresoc.v:162753$8552_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" + cell $eq $eq$libresoc.v:162746$8545 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \logical_op__insn_type + connect \B 7'0001010 + connect \Y $eq$libresoc.v:162746$8545_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" + cell $eq $eq$libresoc.v:162747$8546 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \logical_op__insn_type + connect \B 7'0001100 + connect \Y $eq$libresoc.v:162747$8546_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" + cell $pos $extend$libresoc.v:162744$8541 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \$29 + connect \Y $extend$libresoc.v:162744$8541_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + cell $pos $extend$libresoc.v:162745$8543 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \o + connect \Y $extend$libresoc.v:162745$8543_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" + cell $not $not$libresoc.v:162743$8540 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \o + connect \Y $not$libresoc.v:162743$8540_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" + cell $not $not$libresoc.v:162749$8548 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \msb_test + connect \Y $not$libresoc.v:162749$8548_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" + cell $not $not$libresoc.v:162752$8551 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_nzero + connect \Y $not$libresoc.v:162752$8551_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" + cell $or $or$libresoc.v:162751$8550 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_cmpeqb + connect \B \is_cmp + connect \Y $or$libresoc.v:162751$8550_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:33" + cell $or $or$libresoc.v:162754$8553 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \xer_so + connect \B \xer_ov [0] + connect \Y $or$libresoc.v:162754$8553_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" + cell $pos $pos$libresoc.v:162744$8542 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \Y_WIDTH 65 + connect \A $extend$libresoc.v:162744$8541_Y + connect \Y $pos$libresoc.v:162744$8542_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + cell $pos $pos$libresoc.v:162745$8544 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \Y_WIDTH 65 + connect \A $extend$libresoc.v:162745$8543_Y + connect \Y $pos$libresoc.v:162745$8544_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" + cell $reduce_or $reduce_or$libresoc.v:162748$8547 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 1 + connect \A \target + connect \Y $reduce_or$libresoc.v:162748$8547_Y + end + attribute \src "libresoc.v:162401.7-162401.20" + process $proc$libresoc.v:162401$8567 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:162755.3-162766.6" + process $proc$libresoc.v:162755$8554 + assign { } { } + assign $0\so[0:0] $1\so[0:0] + attribute \src "libresoc.v:162756.5-162756.29" + switch \initial + attribute \src "libresoc.v:162756.9-162756.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:30" + switch \oe + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\so[0:0] \xer_so$24 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\so[0:0] \xer_so + end + sync always + update \so $0\so[0:0] + end + attribute \src "libresoc.v:162767.3-162778.6" + process $proc$libresoc.v:162767$8555 + assign { } { } + assign $0\cr0[3:0] $1\cr0[3:0] + attribute \src "libresoc.v:162768.5-162768.29" + switch \initial + attribute \src "libresoc.v:162768.9-162768.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" + switch \$44 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cr0[3:0] \cr_a + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\cr0[3:0] { \is_negative \is_positive \$46 \so } + end + sync always + update \cr0 $0\cr0[3:0] + end + attribute \src "libresoc.v:162779.3-162790.6" + process $proc$libresoc.v:162779$8556 + assign { } { } + assign $0\o$27[64:0]$8557 $1\o$27[64:0]$8558 + attribute \src "libresoc.v:162780.5-162780.29" + switch \initial + attribute \src "libresoc.v:162780.9-162780.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:40" + switch \logical_op__invert_out + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\o$27[64:0]$8558 \$28 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\o$27[64:0]$8558 \$32 + end + sync always + update \o$27 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attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 28 \logical_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 36 \logical_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 39 \logical_op__invert_out$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 15 \logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 42 \logical_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 16 \logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 43 \logical_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 7 \logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 34 \logical_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 35 \logical_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 41 \logical_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 6 \logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 33 \logical_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 5 \logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 32 \logical_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 40 \logical_op__write_cr0$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 37 \logical_op__zero_a$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 input 51 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 output 27 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 46 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 47 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:75" + wire \ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:26" + wire width 65 \quotient_65 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:24" + wire \quotient_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40" + wire width 64 input 25 \quotient_root + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:41" + wire width 192 input 26 \remainder + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:27" + wire width 64 \remainder_64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:25" + wire \remainder_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:97" + wire width 32 \remainder_s32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:99" + wire width 64 \remainder_s32_as_s64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 output 48 \xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 49 \xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 19 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 50 \xer_so$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:80" + cell $and $and$libresoc.v:163200$8581 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \logical_op__is_signed + connect \B \$38 + connect \Y $and$libresoc.v:163200$8581_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:65" + cell $pos $extend$libresoc.v:163192$8569 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \quotient_root + connect \Y $extend$libresoc.v:163192$8569_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40" + cell $pos $extend$libresoc.v:163193$8571 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \quotient_root + connect \Y $extend$libresoc.v:163193$8571_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:67" + cell $pos $extend$libresoc.v:163195$8574 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \remainder [127:64] + connect \Y $extend$libresoc.v:163195$8574_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" + cell $pos $extend$libresoc.v:163196$8576 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \remainder [127:64] + connect \Y $extend$libresoc.v:163196$8576_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:108" + cell $pos $extend$libresoc.v:163204$8585 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \Y_WIDTH 64 + connect \A \quotient_65 [31:0] + connect \Y $extend$libresoc.v:163204$8585_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:110" + cell $pos $extend$libresoc.v:163205$8587 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \Y_WIDTH 64 + connect \A \quotient_65 [31:0] + connect \Y $extend$libresoc.v:163205$8587_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:117" + cell $pos $extend$libresoc.v:163206$8589 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \Y_WIDTH 64 + connect \A \quotient_65 [31:0] + connect \Y $extend$libresoc.v:163206$8589_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:119" + cell $pos $extend$libresoc.v:163207$8591 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \Y_WIDTH 64 + connect \A \quotient_65 [31:0] + connect \Y $extend$libresoc.v:163207$8591_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:128" + cell $pos $extend$libresoc.v:163208$8593 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \Y_WIDTH 64 + connect \A \remainder_64 [31:0] + connect \Y $extend$libresoc.v:163208$8593_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:84" + cell $ne $ne$libresoc.v:163201$8582 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \quotient_65 [32] + connect \B \quotient_65 [31] + connect \Y $ne$libresoc.v:163201$8582_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:65" + cell $neg $neg$libresoc.v:163192$8570 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \Y_WIDTH 65 + connect \A $extend$libresoc.v:163192$8569_Y + connect \Y $neg$libresoc.v:163192$8570_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:67" + cell $neg $neg$libresoc.v:163195$8575 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \Y_WIDTH 65 + connect \A $extend$libresoc.v:163195$8574_Y + connect \Y $neg$libresoc.v:163195$8575_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:78" + cell $not $not$libresoc.v:163198$8579 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \logical_op__is_32bit + connect \Y $not$libresoc.v:163198$8579_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:102" + cell $not $not$libresoc.v:163203$8584 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ov + connect \Y $not$libresoc.v:163203$8584_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40" + cell $pos $pos$libresoc.v:163193$8572 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \Y_WIDTH 65 + connect \A $extend$libresoc.v:163193$8571_Y + connect \Y $pos$libresoc.v:163193$8572_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" + cell $pos $pos$libresoc.v:163196$8577 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \Y_WIDTH 65 + connect \A $extend$libresoc.v:163196$8576_Y + connect \Y $pos$libresoc.v:163196$8577_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:97" + cell $pos $pos$libresoc.v:163202$8583 + parameter \A_SIGNED 1 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A { \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 } + connect \Y $pos$libresoc.v:163202$8583_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:108" + cell $pos $pos$libresoc.v:163204$8586 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:163204$8585_Y + connect \Y $pos$libresoc.v:163204$8586_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:110" + cell $pos $pos$libresoc.v:163205$8588 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:163205$8587_Y + connect \Y $pos$libresoc.v:163205$8588_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:117" + cell $pos $pos$libresoc.v:163206$8590 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:163206$8589_Y + connect \Y $pos$libresoc.v:163206$8590_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:119" + cell $pos $pos$libresoc.v:163207$8592 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:163207$8591_Y + connect \Y $pos$libresoc.v:163207$8592_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:128" + cell $pos $pos$libresoc.v:163208$8594 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:163208$8593_Y + connect \Y $pos$libresoc.v:163208$8594_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:65" + cell $mux $ternary$libresoc.v:163194$8573 + parameter \WIDTH 65 + connect \A \$25 + connect \B \$23 + connect \S \quotient_neg + connect \Y $ternary$libresoc.v:163194$8573_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:67" + cell $mux $ternary$libresoc.v:163197$8578 + parameter \WIDTH 65 + connect \A \$32 + connect \B \$30 + connect \S \remainder_neg + connect \Y $ternary$libresoc.v:163197$8578_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:55" + cell $xor $xor$libresoc.v:163191$8568 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dividend_neg + connect \B \divisor_neg + connect \Y $xor$libresoc.v:163191$8568_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:80" + cell $xor $xor$libresoc.v:163199$8580 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \quotient_65 [64] + connect \B \quotient_65 [63] + connect \Y $xor$libresoc.v:163199$8580_Y + end + attribute \src "libresoc.v:162851.7-162851.20" + process $proc$libresoc.v:162851$8597 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:163209.3-163280.6" + process $proc$libresoc.v:163209$8595 + assign { } { } + assign { } { } + assign $0\o[63:0] $1\o[63:0] + attribute \src "libresoc.v:163210.5-163210.29" + switch \initial + attribute \src "libresoc.v:163210.9-163210.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:102" + switch \$46 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\o[63:0] $2\o[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:103" + switch \logical_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0011110 + assign { } { } + assign $2\o[63:0] $3\o[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:105" + switch \logical_op__is_32bit + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\o[63:0] $4\o[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:106" + switch \logical_op__is_signed + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\o[63:0] \$48 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $4\o[63:0] \$50 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $3\o[63:0] \quotient_65 [63:0] + end + attribute \src "libresoc.v:0.0-0.0" + case 7'0011101 + assign { } { } + assign $2\o[63:0] $5\o[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:114" + switch \logical_op__is_32bit + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\o[63:0] $6\o[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:115" + switch \logical_op__is_signed + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\o[63:0] \$52 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $6\o[63:0] \$54 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $5\o[63:0] \quotient_65 [63:0] + end + attribute \src "libresoc.v:0.0-0.0" + case 7'0101111 + assign { } { } + assign $2\o[63:0] $7\o[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:123" + switch \logical_op__is_32bit + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\o[63:0] $8\o[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:124" + switch \logical_op__is_signed + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $8\o[63:0] \remainder_s32_as_s64 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $8\o[63:0] \$56 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $7\o[63:0] \remainder_64 + end + case + assign $2\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + case + assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \o $0\o[63:0] + end + attribute \src "libresoc.v:163281.3-163314.6" + process $proc$libresoc.v:163281$8596 + assign { } { } + assign $0\ov[0:0] $1\ov[0:0] + attribute \src "libresoc.v:163282.5-163282.29" + switch \initial + attribute \src "libresoc.v:163282.9-163282.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:76" + switch { \logical_op__is_signed \$36 \div_by_zero } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign { } { } + assign $1\ov[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 3'-1- + assign { } { } + assign { } { } + assign $1\ov[0:0] $2\ov[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:80" + switch \$40 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ov[0:0] 1'1 + case + assign $2\ov[0:0] \dive_abs_ov64 + end + attribute \src "libresoc.v:0.0-0.0" + case 3'1-- + assign { } { } + assign { } { } + assign $1\ov[0:0] $3\ov[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:84" + switch \$42 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\ov[0:0] 1'1 + case + assign $3\ov[0:0] \dive_abs_ov32 + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\ov[0:0] \dive_abs_ov32 + end + sync always + update \ov $0\ov[0:0] + end + connect \$21 $xor$libresoc.v:163191$8568_Y + connect \$23 $neg$libresoc.v:163192$8570_Y + connect \$25 $pos$libresoc.v:163193$8572_Y + connect \$27 $ternary$libresoc.v:163194$8573_Y + connect \$30 $neg$libresoc.v:163195$8575_Y + connect \$32 $pos$libresoc.v:163196$8577_Y + connect \$34 $ternary$libresoc.v:163197$8578_Y + connect \$36 $not$libresoc.v:163198$8579_Y + connect \$38 $xor$libresoc.v:163199$8580_Y + connect \$40 $and$libresoc.v:163200$8581_Y + connect \$42 $ne$libresoc.v:163201$8582_Y + connect \$44 $pos$libresoc.v:163202$8583_Y + connect \$46 $not$libresoc.v:163203$8584_Y + connect \$48 $pos$libresoc.v:163204$8586_Y + connect \$50 $pos$libresoc.v:163205$8588_Y + connect \$52 $pos$libresoc.v:163206$8590_Y + connect \$54 $pos$libresoc.v:163207$8592_Y + connect \$56 $pos$libresoc.v:163208$8594_Y + connect \$29 \$34 + connect { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } + connect \muxid$1 \muxid + connect \xer_so$20 \xer_so + connect \remainder_s32_as_s64 \$44 + connect \remainder_s32 \remainder_64 [31:0] + connect \o_ok 1'1 + connect \xer_ov { \ov \ov } + connect \xer_ov_ok 1'1 + connect \remainder_64 \$34 [63:0] + connect \quotient_65 \$27 + connect \remainder_neg \dividend_neg + connect \quotient_neg \$21 +end +attribute \src "libresoc.v:163332.1-163343.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.p" +attribute \generator "nMigen" +module \p + attribute \src "libresoc.v:163341.17-163341.111" + wire $and$libresoc.v:163341$8598_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" + wire input 1 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" + wire input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" + wire \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" + cell $and $and$libresoc.v:163341$8598 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i + connect \B \p_ready_o + connect \Y $and$libresoc.v:163341$8598_Y + end + connect \$1 $and$libresoc.v:163341$8598_Y + connect \trigger \$1 +end +attribute \src "libresoc.v:163347.1-163358.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe1.p" +attribute \generator "nMigen" +module \p$1 + attribute \src "libresoc.v:163356.17-163356.111" + wire $and$libresoc.v:163356$8599_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" + wire input 1 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" + wire input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" + wire \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" + cell $and $and$libresoc.v:163356$8599 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i + connect \B \p_ready_o + connect \Y $and$libresoc.v:163356$8599_Y + end + connect \$1 $and$libresoc.v:163356$8599_Y + connect \trigger \$1 +end +attribute \src "libresoc.v:163362.1-163373.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.p" +attribute \generator "nMigen" +module \p$108 + attribute \src "libresoc.v:163371.17-163371.111" + wire $and$libresoc.v:163371$8600_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" + wire input 1 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" + wire input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" + wire \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" + cell $and $and$libresoc.v:163371$8600 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i + connect \B \p_ready_o + connect \Y $and$libresoc.v:163371$8600_Y + end + connect \$1 $and$libresoc.v:163371$8600_Y + connect \trigger \$1 +end +attribute \src "libresoc.v:163377.1-163388.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1.p" +attribute \generator "nMigen" +module \p$111 + attribute \src "libresoc.v:163386.17-163386.111" + wire $and$libresoc.v:163386$8601_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" + wire input 1 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" + wire input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" + wire \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" + cell $and $and$libresoc.v:163386$8601 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i + connect \B \p_ready_o + connect \Y $and$libresoc.v:163386$8601_Y + end + connect \$1 $and$libresoc.v:163386$8601_Y + connect \trigger \$1 +end +attribute \src "libresoc.v:163392.1-163403.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe2.p" +attribute \generator "nMigen" +module \p$116 + attribute \src "libresoc.v:163401.17-163401.111" + wire $and$libresoc.v:163401$8602_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" + wire input 1 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" + wire input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" + wire \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" + cell $and $and$libresoc.v:163401$8602 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i + connect \B \p_ready_o + connect \Y $and$libresoc.v:163401$8602_Y + end + connect \$1 $and$libresoc.v:163401$8602_Y + connect \trigger \$1 +end +attribute \src "libresoc.v:163407.1-163418.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.alu_branch0.p" +attribute \generator "nMigen" +module \p$17 + attribute \src "libresoc.v:163416.17-163416.111" + wire $and$libresoc.v:163416$8603_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" + wire input 1 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" + wire input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" + wire \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" + cell $and $and$libresoc.v:163416$8603 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i + connect \B \p_ready_o + connect \Y $and$libresoc.v:163416$8603_Y + end + connect \$1 $and$libresoc.v:163416$8603_Y + connect \trigger \$1 +end +attribute \src "libresoc.v:163422.1-163433.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.alu_branch0.pipe.p" +attribute \generator "nMigen" +module \p$20 + attribute \src "libresoc.v:163431.17-163431.111" + wire $and$libresoc.v:163431$8604_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" + wire input 1 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" + wire input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" + wire \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" + cell $and $and$libresoc.v:163431$8604 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i + connect \B \p_ready_o + connect \Y $and$libresoc.v:163431$8604_Y + end + connect \$1 $and$libresoc.v:163431$8604_Y + connect \trigger \$1 +end +attribute \src "libresoc.v:163437.1-163448.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe2.p" +attribute \generator "nMigen" +module \p$3 + attribute \src "libresoc.v:163446.17-163446.111" + wire $and$libresoc.v:163446$8605_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" + wire input 1 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" + wire input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" + wire \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" + cell $and $and$libresoc.v:163446$8605 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i + connect \B \p_ready_o + connect \Y $and$libresoc.v:163446$8605_Y + end + connect \$1 $and$libresoc.v:163446$8605_Y + connect \trigger \$1 +end +attribute \src "libresoc.v:163452.1-163463.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.p" +attribute \generator "nMigen" +module \p$30 + attribute \src "libresoc.v:163461.17-163461.111" + wire $and$libresoc.v:163461$8606_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" + wire input 1 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" + wire input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" + wire \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" + cell $and $and$libresoc.v:163461$8606 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i + connect \B \p_ready_o + connect \Y $and$libresoc.v:163461$8606_Y + end + connect \$1 $and$libresoc.v:163461$8606_Y + connect \trigger \$1 +end +attribute \src "libresoc.v:163467.1-163478.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.pipe1.p" +attribute \generator "nMigen" +module \p$33 + attribute \src "libresoc.v:163476.17-163476.111" + wire $and$libresoc.v:163476$8607_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" + wire input 1 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" + wire input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" + wire \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" + cell $and $and$libresoc.v:163476$8607 + parameter \A_SIGNED 0 + parameter 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$0\fsm_state[1:0] + attribute \src "libresoc.v:163750.7-163750.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:164336.3-164345.6" + wire $0\ld_active_r_ld_active[0:0] + attribute \src "libresoc.v:164044.3-164045.35" + wire $0\lds_dly[0:0] + attribute \src "libresoc.v:164269.3-164299.6" + wire $0\ldst_port0_addr_ok_o[0:0] + attribute \src "libresoc.v:164326.3-164335.6" + wire width 64 $0\ldst_port0_ld_data_o[63:0] + attribute \src "libresoc.v:164346.3-164355.6" + wire $0\ldst_port0_ld_data_o_ok[0:0] + attribute \src "libresoc.v:164175.3-164190.6" + wire width 4 $0\lenexp_addr_i[3:0] + attribute \src "libresoc.v:164159.3-164174.6" + wire width 4 $0\lenexp_len_i[3:0] + attribute \src "libresoc.v:164445.3-164453.6" + wire $0\lsui_active_dly$next[0:0]$8710 + attribute \src "libresoc.v:164036.3-164037.47" + wire $0\lsui_active_dly[0:0] + attribute \src "libresoc.v:164376.3-164395.6" + wire $0\lsui_busy[0:0] + attribute \src "libresoc.v:164040.3-164041.36" + wire $0\reset_delay[0:0] + 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"libresoc.v:164526.3-164541.6" + wire $1\adrok_l_r_addr_acked[0:0] + attribute \src "libresoc.v:164490.3-164525.6" + wire $1\adrok_l_s_addr_acked$next[0:0]$8717 + attribute \src "libresoc.v:163844.7-163844.34" + wire $1\adrok_l_s_addr_acked[0:0] + attribute \src "libresoc.v:164140.3-164148.6" + wire $1\busy_delay$next[0:0]$8685 + attribute \src "libresoc.v:163848.7-163848.24" + wire $1\busy_delay[0:0] + attribute \src "libresoc.v:164474.3-164489.6" + wire $1\busy_l_r_busy[0:0] + attribute \src "libresoc.v:164464.3-164473.6" + wire $1\busy_l_s_busy[0:0] + attribute \src "libresoc.v:164454.3-164463.6" + wire $1\cyc_l_r_cyc[0:0] + attribute \src "libresoc.v:164435.3-164444.6" + wire $1\cyc_l_s_cyc[0:0] + attribute \src "libresoc.v:164396.3-164434.6" + wire width 2 $1\fsm_state$next[1:0]$8703 + attribute \src "libresoc.v:163870.13-163870.29" + wire width 2 $1\fsm_state[1:0] + attribute \src "libresoc.v:164336.3-164345.6" + wire $1\ld_active_r_ld_active[0:0] + attribute \src "libresoc.v:163884.7-163884.21" + wire $1\lds_dly[0:0] + attribute \src "libresoc.v:164269.3-164299.6" + wire $1\ldst_port0_addr_ok_o[0:0] + attribute \src "libresoc.v:164326.3-164335.6" + wire width 64 $1\ldst_port0_ld_data_o[63:0] + attribute \src "libresoc.v:164346.3-164355.6" + wire $1\ldst_port0_ld_data_o_ok[0:0] + attribute \src "libresoc.v:164175.3-164190.6" + wire width 4 $1\lenexp_addr_i[3:0] + attribute \src "libresoc.v:164159.3-164174.6" + wire width 4 $1\lenexp_len_i[3:0] + attribute \src "libresoc.v:164445.3-164453.6" + wire $1\lsui_active_dly$next[0:0]$8711 + attribute \src "libresoc.v:163927.7-163927.29" + wire $1\lsui_active_dly[0:0] + attribute \src "libresoc.v:164376.3-164395.6" + wire $1\lsui_busy[0:0] + attribute \src "libresoc.v:163939.7-163939.25" + wire $1\reset_delay[0:0] + attribute \src "libresoc.v:164316.3-164325.6" + wire $1\reset_l_r_reset[0:0] + attribute \src "libresoc.v:164300.3-164315.6" + wire $1\reset_l_s_reset[0:0] + attribute \src "libresoc.v:164149.3-164158.6" + wire $1\st_active_r_st_active[0:0] + attribute \src "libresoc.v:164130.3-164139.6" + wire $1\st_done_r_st_done[0:0] + attribute \src "libresoc.v:164115.3-164129.6" + wire $1\st_done_s_st_done$next[0:0]$8680 + attribute \src "libresoc.v:163959.7-163959.31" + wire $1\st_done_s_st_done[0:0] + attribute \src "libresoc.v:164356.3-164365.6" + wire width 64 $1\stdata[63:0] + attribute \src "libresoc.v:163967.7-163967.21" + wire $1\sts_dly[0:0] + attribute \src "libresoc.v:164191.3-164216.6" + wire $1\valid_l_s_valid[0:0] + attribute \src "libresoc.v:164243.3-164268.6" + wire width 48 $1\x_addr_i[47:0] + attribute \src "libresoc.v:164217.3-164242.6" + wire width 8 $1\x_mask_i[7:0] + attribute \src "libresoc.v:164366.3-164375.6" + wire width 64 $1\x_st_data_i[63:0] + attribute \src "libresoc.v:164526.3-164541.6" + wire $2\adrok_l_r_addr_acked[0:0] + attribute \src "libresoc.v:164490.3-164525.6" + wire $2\adrok_l_s_addr_acked$next[0:0]$8718 + attribute \src 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"/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:271" + cell $mul $mul$libresoc.v:164020$8654 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 8 + connect \A \lenexp_addr_i + connect \B 4'1000 + connect \Y $mul$libresoc.v:164020$8654_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:216" + cell $not $not$libresoc.v:163995$8627 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \busy_delay + connect \Y $not$libresoc.v:163995$8627_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $not $not$libresoc.v:163997$8629 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \lds_dly + connect \Y $not$libresoc.v:163997$8629_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $not $not$libresoc.v:163999$8631 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \sts_dly + connect \Y $not$libresoc.v:163999$8631_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:64" + cell $not $not$libresoc.v:164009$8643 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \lsui_busy + connect \Y $not$libresoc.v:164009$8643_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:61" + cell $not $not$libresoc.v:164012$8646 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$38 + connect \Y $not$libresoc.v:164012$8646_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:64" + cell $not $not$libresoc.v:164018$8652 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \lsui_busy + connect \Y $not$libresoc.v:164018$8652_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:224" + cell $not $not$libresoc.v:164021$8655 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \busy_delay + connect \Y $not$libresoc.v:164021$8655_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:95" + cell $not $not$libresoc.v:164028$8662 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \x_busy_o + connect \Y $not$libresoc.v:164028$8662_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:99" + cell $not $not$libresoc.v:164029$8663 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ldst_port0_is_st_i + connect \Y $not$libresoc.v:164029$8663_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:99" + cell $not $not$libresoc.v:164030$8664 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ldst_port0_busy_o + connect \Y $not$libresoc.v:164030$8664_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:108" + cell $not $not$libresoc.v:164033$8667 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \x_busy_o + connect \Y $not$libresoc.v:164033$8667_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $not $not$libresoc.v:164034$8668 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \lsui_active_dly + connect \Y $not$libresoc.v:164034$8668_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:61" + cell $or $or$libresoc.v:164010$8644 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \x_busy_o + connect \B \lsui_busy + connect \Y $or$libresoc.v:164010$8644_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:223" + cell $or $or$libresoc.v:164011$8645 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ldst_port0_is_ld_i + connect \B \ldst_port0_is_st_i + connect \Y $or$libresoc.v:164011$8645_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" + cell $or $or$libresoc.v:164024$8658 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ldst_port0_is_ld_i + connect \B \ldst_port0_is_st_i + connect \Y $or$libresoc.v:164024$8658_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" + cell $or $or$libresoc.v:164026$8660 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ldst_port0_is_ld_i + connect \B \ldst_port0_is_st_i + connect \Y $or$libresoc.v:164026$8660_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" + cell $pos $pos$libresoc.v:164002$8635 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A $extend$libresoc.v:164002$8634_Y + connect \Y $pos$libresoc.v:164002$8635_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" + cell $pos $pos$libresoc.v:164003$8637 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A $extend$libresoc.v:164003$8636_Y + connect \Y $pos$libresoc.v:164003$8637_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:271" + cell $sshl $sshl$libresoc.v:164022$8656 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 319 + connect \A \ldst_port0_st_data_i + connect \B \$57 + connect \Y $sshl$libresoc.v:164022$8656_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:258" + cell $sshr $sshr$libresoc.v:164015$8649 + parameter \A_SIGNED 0 + parameter \A_WIDTH 176 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 176 + connect \A \$42 + connect \B \$44 + connect \Y $sshr$libresoc.v:164015$8649_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:164052.11-164059.4" + cell \adrok_l \adrok_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_addr_acked \adrok_l_q_addr_acked + connect \qn_addr_acked \adrok_l_qn_addr_acked + connect \r_addr_acked \adrok_l_r_addr_acked + connect \s_addr_acked \adrok_l_s_addr_acked + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:164060.10-164066.4" + cell \busy_l \busy_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_busy \busy_l_q_busy + connect \r_busy \busy_l_r_busy + connect \s_busy \busy_l_s_busy + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:164067.9-164073.4" + cell \cyc_l \cyc_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_cyc \cyc_l_q_cyc + connect \r_cyc \cyc_l_r_cyc + connect \s_cyc \cyc_l_s_cyc + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:164074.13-164080.4" + cell \ld_active \ld_active + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_ld_active \ld_active_q_ld_active + connect \r_ld_active \ld_active_r_ld_active + connect \s_ld_active \ld_active_s_ld_active + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:164081.10-164086.4" + cell \lenexp \lenexp + connect \addr_i \lenexp_addr_i + connect \len_i \lenexp_len_i + connect \lexp_o \lenexp_lexp_o + connect \rexp_o \lenexp_rexp_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:164087.11-164093.4" + cell \reset_l \reset_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_reset \reset_l_q_reset + connect \r_reset \reset_l_r_reset + connect \s_reset \reset_l_s_reset + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:164094.13-164100.4" + cell \st_active \st_active + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_st_active \st_active_q_st_active + connect \r_st_active \st_active_r_st_active + connect \s_st_active \st_active_s_st_active + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:164101.11-164107.4" + cell \st_done \st_done + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_st_done \st_done_q_st_done + connect \r_st_done \st_done_r_st_done + connect \s_st_done \st_done_s_st_done + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:164108.11-164114.4" + cell \valid_l \valid_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_valid \valid_l_q_valid + connect \r_valid \valid_l_r_valid + connect \s_valid \valid_l_s_valid + end + attribute \src "libresoc.v:163750.7-163750.20" + process $proc$libresoc.v:163750$8724 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:163844.7-163844.34" + process $proc$libresoc.v:163844$8725 + assign { } { } + assign $1\adrok_l_s_addr_acked[0:0] 1'0 + sync always + sync init + update \adrok_l_s_addr_acked $1\adrok_l_s_addr_acked[0:0] + end + attribute \src "libresoc.v:163848.7-163848.24" + process $proc$libresoc.v:163848$8726 + assign { } { } + assign $1\busy_delay[0:0] 1'0 + sync always + sync init + update \busy_delay $1\busy_delay[0:0] + end + attribute \src "libresoc.v:163870.13-163870.29" + process $proc$libresoc.v:163870$8727 + assign { } { } + assign $1\fsm_state[1:0] 2'00 + sync always + sync init + update \fsm_state $1\fsm_state[1:0] + end + attribute \src "libresoc.v:163884.7-163884.21" + process $proc$libresoc.v:163884$8728 + assign { } { } + assign $1\lds_dly[0:0] 1'0 + sync always + sync init + update \lds_dly $1\lds_dly[0:0] + end + attribute \src "libresoc.v:163927.7-163927.29" + process $proc$libresoc.v:163927$8729 + assign { } { } + assign $1\lsui_active_dly[0:0] 1'0 + sync always + sync init + update \lsui_active_dly $1\lsui_active_dly[0:0] + end + attribute \src "libresoc.v:163939.7-163939.25" + process $proc$libresoc.v:163939$8730 + assign { } { } + assign $1\reset_delay[0:0] 1'0 + sync always + sync init + update \reset_delay $1\reset_delay[0:0] + end + attribute \src "libresoc.v:163959.7-163959.31" + process $proc$libresoc.v:163959$8731 + assign { } { } + assign $1\st_done_s_st_done[0:0] 1'0 + sync always + sync init + update \st_done_s_st_done $1\st_done_s_st_done[0:0] + end + attribute \src "libresoc.v:163967.7-163967.21" + process $proc$libresoc.v:163967$8732 + assign { } { } + assign $1\sts_dly[0:0] 1'0 + sync always + sync init + update \sts_dly $1\sts_dly[0:0] + end + attribute \src "libresoc.v:164036.3-164037.47" + process $proc$libresoc.v:164036$8670 + assign { } { } + assign $0\lsui_active_dly[0:0] \lsui_active_dly$next + sync posedge \coresync_clk + update \lsui_active_dly $0\lsui_active_dly[0:0] + end + attribute \src "libresoc.v:164038.3-164039.35" + process $proc$libresoc.v:164038$8671 + assign { } { } + assign $0\fsm_state[1:0] \fsm_state$next + sync posedge \coresync_clk + update \fsm_state $0\fsm_state[1:0] + end + attribute \src "libresoc.v:164040.3-164041.36" + process $proc$libresoc.v:164040$8672 + assign { } { } + assign $0\reset_delay[0:0] \reset_l_q_reset + sync posedge \coresync_clk + update \reset_delay $0\reset_delay[0:0] + end + attribute \src "libresoc.v:164042.3-164043.35" + process $proc$libresoc.v:164042$8673 + assign { } { } + assign $0\sts_dly[0:0] \ldst_port0_is_st_i + sync posedge \coresync_clk + update \sts_dly $0\sts_dly[0:0] + end + attribute \src "libresoc.v:164044.3-164045.35" + process $proc$libresoc.v:164044$8674 + assign { } { } + assign $0\lds_dly[0:0] \ldst_port0_is_ld_i + sync posedge \coresync_clk + update \lds_dly $0\lds_dly[0:0] + end + attribute \src "libresoc.v:164046.3-164047.37" + process $proc$libresoc.v:164046$8675 + assign { } { } + assign $0\busy_delay[0:0] \busy_delay$next + sync posedge \coresync_clk + update \busy_delay $0\busy_delay[0:0] + end + attribute \src "libresoc.v:164048.3-164049.57" + process $proc$libresoc.v:164048$8676 + assign { } { } + assign $0\adrok_l_s_addr_acked[0:0] \adrok_l_s_addr_acked$next + sync posedge \coresync_clk + update \adrok_l_s_addr_acked $0\adrok_l_s_addr_acked[0:0] + end + attribute \src "libresoc.v:164050.3-164051.51" + process $proc$libresoc.v:164050$8677 + assign { } { } + assign $0\st_done_s_st_done[0:0] \st_done_s_st_done$next + sync posedge \coresync_clk + update \st_done_s_st_done $0\st_done_s_st_done[0:0] + end + attribute \src "libresoc.v:164115.3-164129.6" + process $proc$libresoc.v:164115$8678 + assign { } { } + assign { } { } + assign { } { } + assign $0\st_done_s_st_done$next[0:0]$8679 $2\st_done_s_st_done$next[0:0]$8681 + attribute \src "libresoc.v:164116.5-164116.29" + switch \initial + attribute \src "libresoc.v:164116.9-164116.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:267" + switch \$1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\st_done_s_st_done$next[0:0]$8680 1'1 + case + assign $1\st_done_s_st_done$next[0:0]$8680 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\st_done_s_st_done$next[0:0]$8681 1'0 + case + assign $2\st_done_s_st_done$next[0:0]$8681 $1\st_done_s_st_done$next[0:0]$8680 + end + sync always + update \st_done_s_st_done$next $0\st_done_s_st_done$next[0:0]$8679 + end + attribute \src "libresoc.v:164130.3-164139.6" + process $proc$libresoc.v:164130$8682 + assign { } { } + assign { } { } + assign $0\st_done_r_st_done[0:0] $1\st_done_r_st_done[0:0] + attribute \src "libresoc.v:164131.5-164131.29" + switch \initial + attribute \src "libresoc.v:164131.9-164131.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:286" + switch \reset_l_q_reset + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\st_done_r_st_done[0:0] 1'1 + case + assign $1\st_done_r_st_done[0:0] 1'0 + end + sync always + update \st_done_r_st_done $0\st_done_r_st_done[0:0] + end + attribute \src "libresoc.v:164140.3-164148.6" + process $proc$libresoc.v:164140$8683 + assign { } { } + assign { } { } + assign $0\busy_delay$next[0:0]$8684 $1\busy_delay$next[0:0]$8685 + attribute \src "libresoc.v:164141.5-164141.29" + switch \initial + attribute \src "libresoc.v:164141.9-164141.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\busy_delay$next[0:0]$8685 1'0 + case + assign $1\busy_delay$next[0:0]$8685 \ldst_port0_busy_o + end + sync always + update \busy_delay$next $0\busy_delay$next[0:0]$8684 + end + attribute \src "libresoc.v:164149.3-164158.6" + process $proc$libresoc.v:164149$8686 + assign { } { } + assign { } { } + assign $0\st_active_r_st_active[0:0] $1\st_active_r_st_active[0:0] + attribute \src "libresoc.v:164150.5-164150.29" + switch \initial + attribute \src "libresoc.v:164150.9-164150.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:286" + switch \reset_l_q_reset + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\st_active_r_st_active[0:0] 1'1 + case + assign $1\st_active_r_st_active[0:0] 1'0 + end + sync always + update \st_active_r_st_active $0\st_active_r_st_active[0:0] + end + attribute \src "libresoc.v:164159.3-164174.6" + process $proc$libresoc.v:164159$8687 + assign { } { } + assign { } { } + assign { } { } + assign $0\lenexp_len_i[3:0] $2\lenexp_len_i[3:0] + attribute \src "libresoc.v:164160.5-164160.29" + switch \initial + attribute \src "libresoc.v:164160.9-164160.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:228" + switch \ld_active_q_ld_active + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\lenexp_len_i[3:0] \ldst_port0_data_len + case + assign $1\lenexp_len_i[3:0] 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:240" + switch \st_active_q_st_active + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\lenexp_len_i[3:0] \ldst_port0_data_len + case + assign $2\lenexp_len_i[3:0] $1\lenexp_len_i[3:0] + end + sync always + update \lenexp_len_i $0\lenexp_len_i[3:0] + end + attribute \src "libresoc.v:164175.3-164190.6" + process $proc$libresoc.v:164175$8688 + assign { } { } + assign { } { } + assign { } { } + assign $0\lenexp_addr_i[3:0] $2\lenexp_addr_i[3:0] + attribute \src "libresoc.v:164176.5-164176.29" + switch \initial + attribute \src "libresoc.v:164176.9-164176.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:228" + switch \ld_active_q_ld_active + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\lenexp_addr_i[3:0] \$21 + case + assign $1\lenexp_addr_i[3:0] 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:240" + switch \st_active_q_st_active + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\lenexp_addr_i[3:0] \$23 + case + assign $2\lenexp_addr_i[3:0] $1\lenexp_addr_i[3:0] + end + sync always + update \lenexp_addr_i $0\lenexp_addr_i[3:0] + end + attribute \src "libresoc.v:164191.3-164216.6" + process $proc$libresoc.v:164191$8689 + assign { } { } + assign { } { } + assign { } { } + assign $0\valid_l_s_valid[0:0] $3\valid_l_s_valid[0:0] + attribute \src "libresoc.v:164192.5-164192.29" + switch \initial + attribute \src "libresoc.v:164192.9-164192.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:228" + switch \ld_active_q_ld_active + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\valid_l_s_valid[0:0] $2\valid_l_s_valid[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" + switch \$25 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\valid_l_s_valid[0:0] 1'1 + case + assign $2\valid_l_s_valid[0:0] 1'0 + end + case + assign $1\valid_l_s_valid[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:240" + switch \st_active_q_st_active + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\valid_l_s_valid[0:0] $4\valid_l_s_valid[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:245" + switch \ldst_port0_addr_i_ok + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\valid_l_s_valid[0:0] 1'1 + case + assign $4\valid_l_s_valid[0:0] $1\valid_l_s_valid[0:0] + end + case + assign $3\valid_l_s_valid[0:0] $1\valid_l_s_valid[0:0] + end + sync always + update \valid_l_s_valid $0\valid_l_s_valid[0:0] + end + attribute \src "libresoc.v:164217.3-164242.6" + process $proc$libresoc.v:164217$8690 + assign { } { } + assign { } { } + assign { } { } + assign $0\x_mask_i[7:0] $3\x_mask_i[7:0] + attribute \src "libresoc.v:164218.5-164218.29" + switch \initial + attribute \src "libresoc.v:164218.9-164218.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:228" + switch \ld_active_q_ld_active + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\x_mask_i[7:0] $2\x_mask_i[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" + switch \$27 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\x_mask_i[7:0] \lenexp_lexp_o [7:0] + case + assign $2\x_mask_i[7:0] 8'00000000 + end + case + assign $1\x_mask_i[7:0] 8'00000000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:240" + switch \st_active_q_st_active + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\x_mask_i[7:0] $4\x_mask_i[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:245" + switch \ldst_port0_addr_i_ok + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\x_mask_i[7:0] \lenexp_lexp_o [7:0] + case + assign $4\x_mask_i[7:0] $1\x_mask_i[7:0] + end + case + assign $3\x_mask_i[7:0] $1\x_mask_i[7:0] + end + sync always + update \x_mask_i $0\x_mask_i[7:0] + end + attribute \src "libresoc.v:164243.3-164268.6" + process $proc$libresoc.v:164243$8691 + assign { } { } + assign { } { } + assign { } { } + assign $0\x_addr_i[47:0] $3\x_addr_i[47:0] + attribute \src "libresoc.v:164244.5-164244.29" + switch \initial + attribute \src "libresoc.v:164244.9-164244.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:228" + switch \ld_active_q_ld_active + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\x_addr_i[47:0] $2\x_addr_i[47:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" + switch \$29 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\x_addr_i[47:0] \ldst_port0_addr_i + case + assign $2\x_addr_i[47:0] 48'000000000000000000000000000000000000000000000000 + end + case + assign $1\x_addr_i[47:0] 48'000000000000000000000000000000000000000000000000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:240" + switch \st_active_q_st_active + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\x_addr_i[47:0] $4\x_addr_i[47:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:245" + switch \ldst_port0_addr_i_ok + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\x_addr_i[47:0] \ldst_port0_addr_i + case + assign $4\x_addr_i[47:0] $1\x_addr_i[47:0] + end + case + assign $3\x_addr_i[47:0] $1\x_addr_i[47:0] + end + sync always + update \x_addr_i $0\x_addr_i[47:0] + end + attribute \src "libresoc.v:164269.3-164299.6" + process $proc$libresoc.v:164269$8692 + assign { } { } + assign { } { } + assign { } { } + assign $0\ldst_port0_addr_ok_o[0:0] $3\ldst_port0_addr_ok_o[0:0] + attribute \src "libresoc.v:164270.5-164270.29" + switch \initial + attribute \src "libresoc.v:164270.9-164270.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:228" + switch \ld_active_q_ld_active + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ldst_port0_addr_ok_o[0:0] $2\ldst_port0_addr_ok_o[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" + switch \$31 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ldst_port0_addr_ok_o[0:0] 1'1 + case + assign $2\ldst_port0_addr_ok_o[0:0] 1'0 + end + case + assign $1\ldst_port0_addr_ok_o[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:240" + switch \st_active_q_st_active + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\ldst_port0_addr_ok_o[0:0] $4\ldst_port0_addr_ok_o[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:245" + switch \ldst_port0_addr_i_ok + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\ldst_port0_addr_ok_o[0:0] $5\ldst_port0_addr_ok_o[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:247" + switch \adrok_l_qn_addr_acked + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\ldst_port0_addr_ok_o[0:0] 1'1 + case + assign $5\ldst_port0_addr_ok_o[0:0] $1\ldst_port0_addr_ok_o[0:0] + end + case + assign $4\ldst_port0_addr_ok_o[0:0] $1\ldst_port0_addr_ok_o[0:0] + end + case + assign $3\ldst_port0_addr_ok_o[0:0] $1\ldst_port0_addr_ok_o[0:0] + end + sync always + update \ldst_port0_addr_ok_o $0\ldst_port0_addr_ok_o[0:0] + end + attribute \src "libresoc.v:164300.3-164315.6" + process $proc$libresoc.v:164300$8693 + assign { } { } + assign { } { } + assign { } { } + assign $0\reset_l_s_reset[0:0] $2\reset_l_s_reset[0:0] + attribute \src "libresoc.v:164301.5-164301.29" + switch \initial + attribute \src "libresoc.v:164301.9-164301.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:259" + switch \$33 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\reset_l_s_reset[0:0] \$35 + case + assign $1\reset_l_s_reset[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:276" + switch \st_done_q_st_done + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\reset_l_s_reset[0:0] \$37 + case + assign $2\reset_l_s_reset[0:0] $1\reset_l_s_reset[0:0] + end + sync always + update \reset_l_s_reset $0\reset_l_s_reset[0:0] + end + attribute \src "libresoc.v:164316.3-164325.6" + process $proc$libresoc.v:164316$8694 + assign { } { } + assign { } { } + assign $0\reset_l_r_reset[0:0] $1\reset_l_r_reset[0:0] + attribute \src "libresoc.v:164317.5-164317.29" + switch \initial + attribute \src "libresoc.v:164317.9-164317.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:286" + switch \reset_l_q_reset + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\reset_l_r_reset[0:0] 1'1 + case + assign $1\reset_l_r_reset[0:0] 1'0 + end + sync always + update \reset_l_r_reset $0\reset_l_r_reset[0:0] + end + attribute \src "libresoc.v:164326.3-164335.6" + process $proc$libresoc.v:164326$8695 + assign { } { } + assign { } { } + assign $0\ldst_port0_ld_data_o[63:0] $1\ldst_port0_ld_data_o[63:0] + attribute \src "libresoc.v:164327.5-164327.29" + switch \initial + attribute \src "libresoc.v:164327.9-164327.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:259" + switch \$48 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ldst_port0_ld_data_o[63:0] \lddata + case + assign $1\ldst_port0_ld_data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \ldst_port0_ld_data_o $0\ldst_port0_ld_data_o[63:0] + end + attribute \src "libresoc.v:164336.3-164345.6" + process $proc$libresoc.v:164336$8696 + assign { } { } + assign { } { } + assign $0\ld_active_r_ld_active[0:0] $1\ld_active_r_ld_active[0:0] + attribute \src "libresoc.v:164337.5-164337.29" + switch \initial + attribute \src "libresoc.v:164337.9-164337.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:286" + switch \reset_l_q_reset + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ld_active_r_ld_active[0:0] 1'1 + case + assign $1\ld_active_r_ld_active[0:0] 1'0 + end + sync always + update \ld_active_r_ld_active $0\ld_active_r_ld_active[0:0] + end + attribute \src "libresoc.v:164346.3-164355.6" + process $proc$libresoc.v:164346$8697 + assign { } { } + assign { } { } + assign $0\ldst_port0_ld_data_o_ok[0:0] $1\ldst_port0_ld_data_o_ok[0:0] + attribute \src "libresoc.v:164347.5-164347.29" + switch \initial + attribute \src "libresoc.v:164347.9-164347.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:259" + switch \$50 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ldst_port0_ld_data_o_ok[0:0] \$52 + case + assign $1\ldst_port0_ld_data_o_ok[0:0] 1'0 + end + sync always + update \ldst_port0_ld_data_o_ok $0\ldst_port0_ld_data_o_ok[0:0] + end + attribute \src "libresoc.v:164356.3-164365.6" + process $proc$libresoc.v:164356$8698 + assign { } { } + assign { } { } + assign $0\stdata[63:0] $1\stdata[63:0] + attribute \src "libresoc.v:164357.5-164357.29" + switch \initial + attribute \src "libresoc.v:164357.9-164357.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:267" + switch \$54 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\stdata[63:0] \$56 [63:0] + case + assign $1\stdata[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \stdata $0\stdata[63:0] + end + attribute \src "libresoc.v:164366.3-164375.6" + process $proc$libresoc.v:164366$8699 + assign { } { } + assign { } { } + assign $0\x_st_data_i[63:0] $1\x_st_data_i[63:0] + attribute \src "libresoc.v:164367.5-164367.29" + switch \initial + attribute \src "libresoc.v:164367.9-164367.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:267" + switch \$61 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\x_st_data_i[63:0] \stdata + case + assign $1\x_st_data_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \x_st_data_i $0\x_st_data_i[63:0] + end + attribute \src "libresoc.v:164376.3-164395.6" + process $proc$libresoc.v:164376$8700 + assign { } { } + assign { } { } + assign $0\lsui_busy[0:0] $1\lsui_busy[0:0] + attribute \src "libresoc.v:164377.5-164377.29" + switch \initial + attribute \src "libresoc.v:164377.9-164377.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:85" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\lsui_busy[0:0] $2\lsui_busy[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" + switch \$65 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\lsui_busy[0:0] 1'1 + case + assign $2\lsui_busy[0:0] 1'0 + end + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\lsui_busy[0:0] 1'1 + case + assign $1\lsui_busy[0:0] 1'0 + end + sync always + update \lsui_busy $0\lsui_busy[0:0] + end + attribute \src "libresoc.v:164396.3-164434.6" + process $proc$libresoc.v:164396$8701 + assign { } { } + assign { } { } + assign { } { } + assign $0\fsm_state$next[1:0]$8702 $5\fsm_state$next[1:0]$8707 + attribute \src "libresoc.v:164397.5-164397.29" + switch \initial + attribute \src "libresoc.v:164397.9-164397.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:85" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\fsm_state$next[1:0]$8703 $2\fsm_state$next[1:0]$8704 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" + switch \$69 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\fsm_state$next[1:0]$8704 2'01 + case + assign $2\fsm_state$next[1:0]$8704 \fsm_state + end + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\fsm_state$next[1:0]$8703 $3\fsm_state$next[1:0]$8705 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:95" + switch \$71 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fsm_state$next[1:0]$8705 2'10 + case + assign $3\fsm_state$next[1:0]$8705 \fsm_state + end + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\fsm_state$next[1:0]$8703 $4\fsm_state$next[1:0]$8706 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:99" + switch \$77 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\fsm_state$next[1:0]$8706 2'00 + case + assign $4\fsm_state$next[1:0]$8706 \fsm_state + end + case + assign $1\fsm_state$next[1:0]$8703 \fsm_state + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\fsm_state$next[1:0]$8707 2'00 + case + assign $5\fsm_state$next[1:0]$8707 $1\fsm_state$next[1:0]$8703 + end + sync always + update \fsm_state$next $0\fsm_state$next[1:0]$8702 + end + attribute \src "libresoc.v:164435.3-164444.6" + process $proc$libresoc.v:164435$8708 + assign { } { } + assign { } { } + assign $0\cyc_l_s_cyc[0:0] $1\cyc_l_s_cyc[0:0] + attribute \src "libresoc.v:164436.5-164436.29" + switch \initial + attribute \src "libresoc.v:164436.9-164436.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:299" + switch \reset_l_s_reset + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cyc_l_s_cyc[0:0] 1'1 + case + assign $1\cyc_l_s_cyc[0:0] 1'0 + end + sync always + update \cyc_l_s_cyc $0\cyc_l_s_cyc[0:0] + end + attribute \src "libresoc.v:164445.3-164453.6" + process $proc$libresoc.v:164445$8709 + assign { } { } + assign { } { } + assign $0\lsui_active_dly$next[0:0]$8710 $1\lsui_active_dly$next[0:0]$8711 + attribute \src "libresoc.v:164446.5-164446.29" + switch \initial + attribute \src "libresoc.v:164446.9-164446.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\lsui_active_dly$next[0:0]$8711 1'0 + case + assign $1\lsui_active_dly$next[0:0]$8711 \lsui_active + end + sync always + update \lsui_active_dly$next $0\lsui_active_dly$next[0:0]$8710 + end + attribute \src "libresoc.v:164454.3-164463.6" + process $proc$libresoc.v:164454$8712 + assign { } { } + assign { } { } + assign $0\cyc_l_r_cyc[0:0] $1\cyc_l_r_cyc[0:0] + attribute \src "libresoc.v:164455.5-164455.29" + switch \initial + attribute \src "libresoc.v:164455.9-164455.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:302" + switch \cyc_l_q_cyc + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cyc_l_r_cyc[0:0] 1'1 + case + assign $1\cyc_l_r_cyc[0:0] 1'0 + end + sync always + update \cyc_l_r_cyc $0\cyc_l_r_cyc[0:0] + end + attribute \src "libresoc.v:164464.3-164473.6" + process $proc$libresoc.v:164464$8713 + assign { } { } + assign { } { } + assign $0\busy_l_s_busy[0:0] $1\busy_l_s_busy[0:0] + attribute \src "libresoc.v:164465.5-164465.29" + switch \initial + attribute \src "libresoc.v:164465.9-164465.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:223" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\busy_l_s_busy[0:0] \$5 + case + assign $1\busy_l_s_busy[0:0] 1'0 + end + sync always + update \busy_l_s_busy $0\busy_l_s_busy[0:0] + end + attribute \src "libresoc.v:164474.3-164489.6" + process $proc$libresoc.v:164474$8714 + assign { } { } + assign { } { } + assign { } { } + assign $0\busy_l_r_busy[0:0] $2\busy_l_r_busy[0:0] + attribute \src "libresoc.v:164475.5-164475.29" + switch \initial + attribute \src "libresoc.v:164475.9-164475.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:294" + switch \ldst_port0_exc_$signal + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\busy_l_r_busy[0:0] 1'1 + case + assign $1\busy_l_r_busy[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:302" + switch \cyc_l_q_cyc + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\busy_l_r_busy[0:0] 1'1 + case + assign $2\busy_l_r_busy[0:0] $1\busy_l_r_busy[0:0] + end + sync always + update \busy_l_r_busy $0\busy_l_r_busy[0:0] + end + attribute \src "libresoc.v:164490.3-164525.6" + process $proc$libresoc.v:164490$8715 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\adrok_l_s_addr_acked$next[0:0]$8716 $6\adrok_l_s_addr_acked$next[0:0]$8722 + attribute \src "libresoc.v:164491.5-164491.29" + switch \initial + attribute \src "libresoc.v:164491.9-164491.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:228" + switch \ld_active_q_ld_active + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\adrok_l_s_addr_acked$next[0:0]$8717 $2\adrok_l_s_addr_acked$next[0:0]$8718 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" + switch \$7 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\adrok_l_s_addr_acked$next[0:0]$8718 1'1 + case + assign $2\adrok_l_s_addr_acked$next[0:0]$8718 1'0 + end + case + assign $1\adrok_l_s_addr_acked$next[0:0]$8717 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:240" + switch \st_active_q_st_active + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\adrok_l_s_addr_acked$next[0:0]$8719 $4\adrok_l_s_addr_acked$next[0:0]$8720 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:245" + switch \ldst_port0_addr_i_ok + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\adrok_l_s_addr_acked$next[0:0]$8720 $5\adrok_l_s_addr_acked$next[0:0]$8721 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:247" + switch \adrok_l_qn_addr_acked + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\adrok_l_s_addr_acked$next[0:0]$8721 1'1 + case + assign $5\adrok_l_s_addr_acked$next[0:0]$8721 $1\adrok_l_s_addr_acked$next[0:0]$8717 + end + case + assign $4\adrok_l_s_addr_acked$next[0:0]$8720 $1\adrok_l_s_addr_acked$next[0:0]$8717 + end + case + assign $3\adrok_l_s_addr_acked$next[0:0]$8719 $1\adrok_l_s_addr_acked$next[0:0]$8717 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\adrok_l_s_addr_acked$next[0:0]$8722 1'0 + case + assign $6\adrok_l_s_addr_acked$next[0:0]$8722 $3\adrok_l_s_addr_acked$next[0:0]$8719 + end + sync always + update \adrok_l_s_addr_acked$next $0\adrok_l_s_addr_acked$next[0:0]$8716 + end + attribute \src "libresoc.v:164526.3-164541.6" + process $proc$libresoc.v:164526$8723 + assign { } { } + assign { } { } + assign { } { } + assign $0\adrok_l_r_addr_acked[0:0] $2\adrok_l_r_addr_acked[0:0] + attribute \src "libresoc.v:164527.5-164527.29" + switch \initial + attribute \src "libresoc.v:164527.9-164527.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:282" + switch \reset_delay + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\adrok_l_r_addr_acked[0:0] 1'1 + case + assign $1\adrok_l_r_addr_acked[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:286" + switch \reset_l_q_reset + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\adrok_l_r_addr_acked[0:0] 1'1 + case + assign $2\adrok_l_r_addr_acked[0:0] $1\adrok_l_r_addr_acked[0:0] + end + sync always + update \adrok_l_r_addr_acked $0\adrok_l_r_addr_acked[0:0] + end + connect \$9 $not$libresoc.v:163995$8627_Y + connect \$11 $and$libresoc.v:163996$8628_Y + connect \$13 $not$libresoc.v:163997$8629_Y + connect \$15 $and$libresoc.v:163998$8630_Y + connect \$17 $not$libresoc.v:163999$8631_Y + connect \$1 $and$libresoc.v:164000$8632_Y + connect \$19 $and$libresoc.v:164001$8633_Y + connect \$21 $pos$libresoc.v:164002$8635_Y + connect \$23 $pos$libresoc.v:164003$8637_Y + connect \$25 $and$libresoc.v:164004$8638_Y + connect \$27 $and$libresoc.v:164005$8639_Y + connect \$29 $and$libresoc.v:164006$8640_Y + connect \$31 $and$libresoc.v:164007$8641_Y + connect \$33 $and$libresoc.v:164008$8642_Y + connect \$35 $not$libresoc.v:164009$8643_Y + connect \$38 $or$libresoc.v:164010$8644_Y + connect \$3 $or$libresoc.v:164011$8645_Y + connect \$37 $not$libresoc.v:164012$8646_Y + connect \$42 $and$libresoc.v:164013$8647_Y + connect \$44 $mul$libresoc.v:164014$8648_Y + connect \$46 $sshr$libresoc.v:164015$8649_Y + connect \$48 $and$libresoc.v:164016$8650_Y + connect \$50 $and$libresoc.v:164017$8651_Y + connect \$52 $not$libresoc.v:164018$8652_Y + connect \$54 $and$libresoc.v:164019$8653_Y + connect \$57 $mul$libresoc.v:164020$8654_Y + connect \$5 $not$libresoc.v:164021$8655_Y + connect \$59 $sshl$libresoc.v:164022$8656_Y + connect \$61 $and$libresoc.v:164023$8657_Y + connect \$63 $or$libresoc.v:164024$8658_Y + connect \$65 $and$libresoc.v:164025$8659_Y + connect \$67 $or$libresoc.v:164026$8660_Y + connect \$69 $and$libresoc.v:164027$8661_Y + connect \$71 $not$libresoc.v:164028$8662_Y + connect \$73 $not$libresoc.v:164029$8663_Y + connect \$75 $not$libresoc.v:164030$8664_Y + connect \$77 $and$libresoc.v:164031$8665_Y + connect \$7 $and$libresoc.v:164032$8666_Y + connect \$79 $not$libresoc.v:164033$8667_Y + connect \$81 $not$libresoc.v:164034$8668_Y + connect \$83 $and$libresoc.v:164035$8669_Y + connect \$41 \$46 + connect \$56 \$59 + connect \valid_l_r_valid \lsui_active_rise + connect \lsui_active_rise \$83 + connect \lsui_active \$79 + connect \x_valid_i \valid_l_q_valid + connect \m_valid_i \valid_l_q_valid + connect \x_st_i \ldst_port0_is_st_i + connect \x_ld_i \ldst_port0_is_ld_i + connect \ldst_port0_busy_o \busy_l_q_busy + connect \reset_delay$next \reset_l_q_reset + connect \lddata \$46 [63:0] + connect \st_active_s_st_active \sts_rise + connect \sts_rise \$19 + connect \sts_dly$next \sts + connect \ld_active_s_ld_active \lds_rise + connect \lds_rise \$15 + connect \lds_dly$next \lds + connect \busy_edge \$11 + connect \sts \ldst_port0_is_st_i + connect \lds \ldst_port0_is_ld_i +end +attribute \src "libresoc.v:164567.1-165337.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.alu_cr0.pipe" +attribute \generator "nMigen" +module \pipe + attribute \src "libresoc.v:165300.3-165318.6" + wire width 4 $0\cr_a$6$next[3:0]$8779 + attribute \src "libresoc.v:165164.3-165165.31" + wire width 4 $0\cr_a$6[3:0]$8735 + attribute \src "libresoc.v:164581.13-164581.28" + wire width 4 $0\cr_a$6[3:0]$8785 + attribute \src "libresoc.v:165300.3-165318.6" + wire $0\cr_a_ok$next[0:0]$8778 + attribute \src "libresoc.v:165166.3-165167.31" + wire $0\cr_a_ok[0:0] + attribute \src "libresoc.v:165247.3-165261.6" + wire width 13 $0\cr_op__fn_unit$3$next[12:0]$8759 + attribute \src "libresoc.v:165178.3-165179.51" + wire width 13 $0\cr_op__fn_unit$3[12:0]$8745 + attribute \src "libresoc.v:164643.14-164643.43" + wire width 13 $0\cr_op__fn_unit$3[12:0]$8788 + attribute \src "libresoc.v:165247.3-165261.6" + wire width 32 $0\cr_op__insn$4$next[31:0]$8760 + attribute \src "libresoc.v:165180.3-165181.45" + wire width 32 $0\cr_op__insn$4[31:0]$8747 + attribute \src "libresoc.v:164652.14-164652.37" + wire width 32 $0\cr_op__insn$4[31:0]$8790 + attribute \src "libresoc.v:165247.3-165261.6" + wire width 7 $0\cr_op__insn_type$2$next[6:0]$8761 + attribute \src "libresoc.v:165176.3-165177.55" + wire width 7 $0\cr_op__insn_type$2[6:0]$8743 + attribute \src "libresoc.v:164883.13-164883.41" + wire width 7 $0\cr_op__insn_type$2[6:0]$8792 + attribute \src "libresoc.v:165281.3-165299.6" + wire width 32 $0\full_cr$5$next[31:0]$8772 + attribute \src "libresoc.v:165168.3-165169.37" + wire width 32 $0\full_cr$5[31:0]$8738 + attribute \src "libresoc.v:164892.14-164892.33" + wire width 32 $0\full_cr$5[31:0]$8794 + attribute \src "libresoc.v:165281.3-165299.6" + wire $0\full_cr_ok$next[0:0]$8773 + attribute \src "libresoc.v:165170.3-165171.37" + wire $0\full_cr_ok[0:0] + attribute \src "libresoc.v:164568.7-164568.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:165234.3-165246.6" + wire width 2 $0\muxid$1$next[1:0]$8756 + attribute \src "libresoc.v:165182.3-165183.33" + wire width 2 $0\muxid$1[1:0]$8749 + attribute \src "libresoc.v:165122.13-165122.29" + wire width 2 $0\muxid$1[1:0]$8797 + attribute \src "libresoc.v:165262.3-165280.6" + wire width 64 $0\o$next[63:0]$8766 + attribute \src "libresoc.v:165172.3-165173.19" + wire width 64 $0\o[63:0] + attribute \src "libresoc.v:165262.3-165280.6" + wire $0\o_ok$next[0:0]$8767 + attribute \src "libresoc.v:165174.3-165175.25" + wire $0\o_ok[0:0] + attribute \src "libresoc.v:165216.3-165233.6" + wire $0\r_busy$next[0:0]$8752 + attribute \src "libresoc.v:165184.3-165185.29" + wire $0\r_busy[0:0] + attribute \src "libresoc.v:165300.3-165318.6" + wire width 4 $1\cr_a$6$next[3:0]$8781 + attribute \src "libresoc.v:165300.3-165318.6" + wire $1\cr_a_ok$next[0:0]$8780 + attribute \src "libresoc.v:164586.7-164586.21" + wire $1\cr_a_ok[0:0] + attribute \src "libresoc.v:165247.3-165261.6" + wire width 13 $1\cr_op__fn_unit$3$next[12:0]$8762 + attribute \src "libresoc.v:165247.3-165261.6" + wire width 32 $1\cr_op__insn$4$next[31:0]$8763 + attribute \src "libresoc.v:165247.3-165261.6" + wire width 7 $1\cr_op__insn_type$2$next[6:0]$8764 + attribute \src "libresoc.v:165281.3-165299.6" + wire width 32 $1\full_cr$5$next[31:0]$8774 + attribute \src "libresoc.v:165281.3-165299.6" + wire $1\full_cr_ok$next[0:0]$8775 + attribute \src "libresoc.v:164897.7-164897.24" + wire $1\full_cr_ok[0:0] + attribute \src "libresoc.v:165234.3-165246.6" + wire width 2 $1\muxid$1$next[1:0]$8757 + attribute \src "libresoc.v:165262.3-165280.6" + wire width 64 $1\o$next[63:0]$8768 + attribute \src "libresoc.v:165135.14-165135.38" + wire width 64 $1\o[63:0] + attribute \src "libresoc.v:165262.3-165280.6" + wire $1\o_ok$next[0:0]$8769 + attribute \src "libresoc.v:165142.7-165142.18" + wire $1\o_ok[0:0] + attribute \src "libresoc.v:165216.3-165233.6" + wire $1\r_busy$next[0:0]$8753 + attribute \src "libresoc.v:165156.7-165156.20" + wire $1\r_busy[0:0] + attribute \src "libresoc.v:165300.3-165318.6" + wire $2\cr_a_ok$next[0:0]$8782 + attribute \src "libresoc.v:165281.3-165299.6" + wire $2\full_cr_ok$next[0:0]$8776 + attribute \src "libresoc.v:165262.3-165280.6" + wire $2\o_ok$next[0:0]$8770 + attribute \src "libresoc.v:165216.3-165233.6" + wire $2\r_busy$next[0:0]$8754 + attribute \src "libresoc.v:165163.18-165163.118" + wire $and$libresoc.v:165163$8733_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" + wire \$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 26 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 4 input 11 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \cr_a$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 output 24 \cr_a$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \cr_a$6$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 25 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_a_ok$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_a_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 4 input 12 \cr_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 4 input 13 \cr_c + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 input 6 \cr_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + 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\enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \main_cr_op__insn_type$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 32 \main_full_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 32 \main_full_cr$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \main_full_cr_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \main_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \main_muxid$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \main_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \main_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \main_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \main_rb + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 input 4 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 output 16 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid$1$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid$16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + wire \n_i_rdy_data + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire input 15 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire output 14 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 20 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \o$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \o$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 21 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \o_ok$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \o_ok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" + wire output 3 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" + wire input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" + wire \p_valid_i$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" + wire \p_valid_i_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire \r_busy$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 8 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 9 \rb + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" + cell $and $and$libresoc.v:165163$8733 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i$13 + connect \B \p_ready_o + connect \Y $and$libresoc.v:165163$8733_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:165186.12-165207.4" + cell \main$9 \main + connect \cr_a \main_cr_a + connect \cr_a$6 \main_cr_a$12 + connect \cr_a_ok \main_cr_a_ok + connect \cr_b \main_cr_b + connect \cr_c \main_cr_c + connect \cr_op__fn_unit \main_cr_op__fn_unit + connect \cr_op__fn_unit$3 \main_cr_op__fn_unit$9 + connect \cr_op__insn \main_cr_op__insn + connect \cr_op__insn$4 \main_cr_op__insn$10 + connect \cr_op__insn_type \main_cr_op__insn_type + connect \cr_op__insn_type$2 \main_cr_op__insn_type$8 + connect \full_cr \main_full_cr + connect \full_cr$5 \main_full_cr$11 + connect \full_cr_ok \main_full_cr_ok + connect \muxid \main_muxid + connect \muxid$1 \main_muxid$7 + connect \o \main_o + connect \o_ok \main_o_ok + connect \ra \main_ra + connect \rb \main_rb + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:165208.9-165211.4" + cell \n$8 \n + connect \n_ready_i \n_ready_i + connect \n_valid_o \n_valid_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:165212.9-165215.4" + cell \p$7 \p + connect \p_ready_o \p_ready_o + connect \p_valid_i \p_valid_i + end + attribute \src "libresoc.v:164568.7-164568.20" + process $proc$libresoc.v:164568$8783 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:164581.13-164581.28" + process $proc$libresoc.v:164581$8784 + assign { } { } + assign $0\cr_a$6[3:0]$8785 4'0000 + sync always + sync init + update \cr_a$6 $0\cr_a$6[3:0]$8785 + end + attribute \src "libresoc.v:164586.7-164586.21" + process $proc$libresoc.v:164586$8786 + assign { } { } + assign $1\cr_a_ok[0:0] 1'0 + sync always + sync init + update \cr_a_ok $1\cr_a_ok[0:0] + end + attribute \src "libresoc.v:164643.14-164643.43" + process $proc$libresoc.v:164643$8787 + assign { } { } + assign $0\cr_op__fn_unit$3[12:0]$8788 13'0000000000000 + sync always + sync init + update \cr_op__fn_unit$3 $0\cr_op__fn_unit$3[12:0]$8788 + end + attribute \src "libresoc.v:164652.14-164652.37" + process $proc$libresoc.v:164652$8789 + assign { } { } + assign $0\cr_op__insn$4[31:0]$8790 0 + sync always + sync init + update \cr_op__insn$4 $0\cr_op__insn$4[31:0]$8790 + end + attribute \src "libresoc.v:164883.13-164883.41" + process $proc$libresoc.v:164883$8791 + assign { } { } + assign $0\cr_op__insn_type$2[6:0]$8792 7'0000000 + sync always + sync init + update \cr_op__insn_type$2 $0\cr_op__insn_type$2[6:0]$8792 + end + attribute \src "libresoc.v:164892.14-164892.33" + process $proc$libresoc.v:164892$8793 + assign { } { } + assign $0\full_cr$5[31:0]$8794 0 + sync always + sync init + update \full_cr$5 $0\full_cr$5[31:0]$8794 + end + attribute \src "libresoc.v:164897.7-164897.24" + process $proc$libresoc.v:164897$8795 + assign { } { } + assign $1\full_cr_ok[0:0] 1'0 + sync always + sync init + update \full_cr_ok $1\full_cr_ok[0:0] + end + attribute \src "libresoc.v:165122.13-165122.29" + process $proc$libresoc.v:165122$8796 + assign { } { } + assign $0\muxid$1[1:0]$8797 2'00 + sync always + sync init + update \muxid$1 $0\muxid$1[1:0]$8797 + end + attribute \src "libresoc.v:165135.14-165135.38" + process $proc$libresoc.v:165135$8798 + assign { } { } + assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \o $1\o[63:0] + end + attribute \src "libresoc.v:165142.7-165142.18" + process $proc$libresoc.v:165142$8799 + assign { } { } + assign $1\o_ok[0:0] 1'0 + sync always + sync init + update \o_ok $1\o_ok[0:0] + end + attribute \src "libresoc.v:165156.7-165156.20" + process $proc$libresoc.v:165156$8800 + assign { } { } + assign $1\r_busy[0:0] 1'0 + sync always + sync init + update \r_busy $1\r_busy[0:0] + end + attribute \src "libresoc.v:165164.3-165165.31" + process $proc$libresoc.v:165164$8734 + assign { } { } + assign $0\cr_a$6[3:0]$8735 \cr_a$6$next + sync posedge \coresync_clk + update \cr_a$6 $0\cr_a$6[3:0]$8735 + end + attribute \src "libresoc.v:165166.3-165167.31" + process $proc$libresoc.v:165166$8736 + assign { } { } + assign $0\cr_a_ok[0:0] \cr_a_ok$next + sync posedge \coresync_clk + update \cr_a_ok $0\cr_a_ok[0:0] + end + attribute \src "libresoc.v:165168.3-165169.37" + process $proc$libresoc.v:165168$8737 + assign { } { } + assign $0\full_cr$5[31:0]$8738 \full_cr$5$next + sync posedge \coresync_clk + update \full_cr$5 $0\full_cr$5[31:0]$8738 + end + attribute \src "libresoc.v:165170.3-165171.37" + process $proc$libresoc.v:165170$8739 + assign { } { } + assign $0\full_cr_ok[0:0] \full_cr_ok$next + sync posedge \coresync_clk + update \full_cr_ok $0\full_cr_ok[0:0] + end + attribute \src "libresoc.v:165172.3-165173.19" + process $proc$libresoc.v:165172$8740 + assign { } { } + assign $0\o[63:0] \o$next + sync posedge \coresync_clk + update \o $0\o[63:0] + end + attribute \src "libresoc.v:165174.3-165175.25" + process $proc$libresoc.v:165174$8741 + assign { } { } + assign $0\o_ok[0:0] \o_ok$next + sync posedge \coresync_clk + update \o_ok $0\o_ok[0:0] + end + attribute \src "libresoc.v:165176.3-165177.55" + process $proc$libresoc.v:165176$8742 + assign { } { } + assign $0\cr_op__insn_type$2[6:0]$8743 \cr_op__insn_type$2$next + sync posedge \coresync_clk + update \cr_op__insn_type$2 $0\cr_op__insn_type$2[6:0]$8743 + end + attribute \src "libresoc.v:165178.3-165179.51" + process $proc$libresoc.v:165178$8744 + assign { } { } + assign $0\cr_op__fn_unit$3[12:0]$8745 \cr_op__fn_unit$3$next + sync posedge \coresync_clk + update \cr_op__fn_unit$3 $0\cr_op__fn_unit$3[12:0]$8745 + end + attribute \src "libresoc.v:165180.3-165181.45" + process $proc$libresoc.v:165180$8746 + assign { } { } + assign $0\cr_op__insn$4[31:0]$8747 \cr_op__insn$4$next + sync posedge \coresync_clk + update \cr_op__insn$4 $0\cr_op__insn$4[31:0]$8747 + end + attribute \src "libresoc.v:165182.3-165183.33" + process $proc$libresoc.v:165182$8748 + assign { } { } + assign $0\muxid$1[1:0]$8749 \muxid$1$next + sync posedge \coresync_clk + update \muxid$1 $0\muxid$1[1:0]$8749 + end + attribute \src "libresoc.v:165184.3-165185.29" + process $proc$libresoc.v:165184$8750 + assign { } { } + assign $0\r_busy[0:0] \r_busy$next + sync posedge \coresync_clk + update \r_busy $0\r_busy[0:0] + end + attribute \src "libresoc.v:165216.3-165233.6" + process $proc$libresoc.v:165216$8751 + assign { } { } + assign { } { } + assign { } { } + assign $0\r_busy$next[0:0]$8752 $2\r_busy$next[0:0]$8754 + attribute \src "libresoc.v:165217.5-165217.29" + switch \initial + attribute \src "libresoc.v:165217.9-165217.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\r_busy$next[0:0]$8753 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\r_busy$next[0:0]$8753 1'0 + case + assign $1\r_busy$next[0:0]$8753 \r_busy + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r_busy$next[0:0]$8754 1'0 + case + assign $2\r_busy$next[0:0]$8754 $1\r_busy$next[0:0]$8753 + end + sync always + update \r_busy$next $0\r_busy$next[0:0]$8752 + end + attribute \src "libresoc.v:165234.3-165246.6" + process $proc$libresoc.v:165234$8755 + assign { } { } + assign { } { } + assign $0\muxid$1$next[1:0]$8756 $1\muxid$1$next[1:0]$8757 + attribute \src "libresoc.v:165235.5-165235.29" + switch \initial + attribute \src "libresoc.v:165235.9-165235.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\muxid$1$next[1:0]$8757 \muxid$16 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\muxid$1$next[1:0]$8757 \muxid$16 + case + assign $1\muxid$1$next[1:0]$8757 \muxid$1 + end + sync always + update \muxid$1$next $0\muxid$1$next[1:0]$8756 + end + attribute \src "libresoc.v:165247.3-165261.6" + process $proc$libresoc.v:165247$8758 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\cr_op__fn_unit$3$next[12:0]$8759 $1\cr_op__fn_unit$3$next[12:0]$8762 + assign $0\cr_op__insn$4$next[31:0]$8760 $1\cr_op__insn$4$next[31:0]$8763 + assign $0\cr_op__insn_type$2$next[6:0]$8761 $1\cr_op__insn_type$2$next[6:0]$8764 + attribute \src "libresoc.v:165248.5-165248.29" + switch \initial + attribute \src "libresoc.v:165248.9-165248.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { } { } + assign { $1\cr_op__insn$4$next[31:0]$8763 $1\cr_op__fn_unit$3$next[12:0]$8762 $1\cr_op__insn_type$2$next[6:0]$8764 } { \cr_op__insn$19 \cr_op__fn_unit$18 \cr_op__insn_type$17 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { } { } + assign { $1\cr_op__insn$4$next[31:0]$8763 $1\cr_op__fn_unit$3$next[12:0]$8762 $1\cr_op__insn_type$2$next[6:0]$8764 } { \cr_op__insn$19 \cr_op__fn_unit$18 \cr_op__insn_type$17 } + case + assign $1\cr_op__fn_unit$3$next[12:0]$8762 \cr_op__fn_unit$3 + assign $1\cr_op__insn$4$next[31:0]$8763 \cr_op__insn$4 + assign $1\cr_op__insn_type$2$next[6:0]$8764 \cr_op__insn_type$2 + end + sync always + update \cr_op__fn_unit$3$next $0\cr_op__fn_unit$3$next[12:0]$8759 + update \cr_op__insn$4$next $0\cr_op__insn$4$next[31:0]$8760 + update \cr_op__insn_type$2$next $0\cr_op__insn_type$2$next[6:0]$8761 + end + attribute \src "libresoc.v:165262.3-165280.6" + process $proc$libresoc.v:165262$8765 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\o$next[63:0]$8766 $1\o$next[63:0]$8768 + assign { } { } + assign $0\o_ok$next[0:0]$8767 $2\o_ok$next[0:0]$8770 + attribute \src "libresoc.v:165263.5-165263.29" + switch \initial + attribute \src "libresoc.v:165263.9-165263.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\o_ok$next[0:0]$8769 $1\o$next[63:0]$8768 } { \o_ok$21 \o$20 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\o_ok$next[0:0]$8769 $1\o$next[63:0]$8768 } { \o_ok$21 \o$20 } + case + assign $1\o$next[63:0]$8768 \o + assign $1\o_ok$next[0:0]$8769 \o_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\o_ok$next[0:0]$8770 1'0 + case + assign $2\o_ok$next[0:0]$8770 $1\o_ok$next[0:0]$8769 + end + sync always + update \o$next $0\o$next[63:0]$8766 + update \o_ok$next $0\o_ok$next[0:0]$8767 + end + attribute \src "libresoc.v:165281.3-165299.6" + process $proc$libresoc.v:165281$8771 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\full_cr$5$next[31:0]$8772 $1\full_cr$5$next[31:0]$8774 + assign { } { } + assign $0\full_cr_ok$next[0:0]$8773 $2\full_cr_ok$next[0:0]$8776 + attribute \src "libresoc.v:165282.5-165282.29" + switch \initial + attribute \src "libresoc.v:165282.9-165282.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\full_cr_ok$next[0:0]$8775 $1\full_cr$5$next[31:0]$8774 } { \full_cr_ok$23 \full_cr$22 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\full_cr_ok$next[0:0]$8775 $1\full_cr$5$next[31:0]$8774 } { \full_cr_ok$23 \full_cr$22 } + case + assign $1\full_cr$5$next[31:0]$8774 \full_cr$5 + assign $1\full_cr_ok$next[0:0]$8775 \full_cr_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\full_cr_ok$next[0:0]$8776 1'0 + case + assign $2\full_cr_ok$next[0:0]$8776 $1\full_cr_ok$next[0:0]$8775 + end + sync always + update \full_cr$5$next $0\full_cr$5$next[31:0]$8772 + update \full_cr_ok$next $0\full_cr_ok$next[0:0]$8773 + end + attribute \src "libresoc.v:165300.3-165318.6" + process $proc$libresoc.v:165300$8777 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\cr_a$6$next[3:0]$8779 $1\cr_a$6$next[3:0]$8781 + assign $0\cr_a_ok$next[0:0]$8778 $2\cr_a_ok$next[0:0]$8782 + attribute \src "libresoc.v:165301.5-165301.29" + switch \initial + attribute \src "libresoc.v:165301.9-165301.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\cr_a_ok$next[0:0]$8780 $1\cr_a$6$next[3:0]$8781 } { \cr_a_ok$25 \cr_a$24 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\cr_a_ok$next[0:0]$8780 $1\cr_a$6$next[3:0]$8781 } { \cr_a_ok$25 \cr_a$24 } + case + assign $1\cr_a_ok$next[0:0]$8780 \cr_a_ok + assign $1\cr_a$6$next[3:0]$8781 \cr_a$6 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_a_ok$next[0:0]$8782 1'0 + case + assign $2\cr_a_ok$next[0:0]$8782 $1\cr_a_ok$next[0:0]$8780 + end + sync always + update \cr_a_ok$next $0\cr_a_ok$next[0:0]$8778 + update \cr_a$6$next $0\cr_a$6$next[3:0]$8779 + end + connect \$14 $and$libresoc.v:165163$8733_Y + connect \p_ready_o \n_i_rdy_data + connect \n_valid_o \r_busy + connect { \cr_a_ok$25 \cr_a$24 } { \main_cr_a_ok \main_cr_a$12 } + connect { \full_cr_ok$23 \full_cr$22 } { \main_full_cr_ok \main_full_cr$11 } + connect { \o_ok$21 \o$20 } { \main_o_ok \main_o } + connect { \cr_op__insn$19 \cr_op__fn_unit$18 \cr_op__insn_type$17 } { \main_cr_op__insn$10 \main_cr_op__fn_unit$9 \main_cr_op__insn_type$8 } + connect \muxid$16 \main_muxid$7 + connect \p_valid_i_p_ready_o \$14 + connect \n_i_rdy_data \n_ready_i + connect \p_valid_i$13 \p_valid_i + connect \main_cr_c \cr_c + connect \main_cr_b \cr_b + connect \main_cr_a \cr_a + connect \main_full_cr \full_cr + connect \main_rb \rb + connect \main_ra \ra + connect { \main_cr_op__insn \main_cr_op__fn_unit \main_cr_op__insn_type } { \cr_op__insn \cr_op__fn_unit \cr_op__insn_type } + connect \main_muxid \muxid +end +attribute \src "libresoc.v:165341.1-166191.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.alu_branch0.pipe" +attribute \generator "nMigen" +module \pipe$19 + attribute \src "libresoc.v:166091.3-166118.6" + wire width 64 $0\br_op__cia$2$next[63:0]$8837 + attribute \src "libresoc.v:166003.3-166004.43" + wire width 64 $0\br_op__cia$2[63:0]$8811 + attribute \src "libresoc.v:165349.14-165349.51" + wire width 64 $0\br_op__cia$2[63:0]$8875 + attribute \src "libresoc.v:166091.3-166118.6" + wire width 13 $0\br_op__fn_unit$4$next[12:0]$8838 + attribute \src "libresoc.v:166007.3-166008.51" + wire width 13 $0\br_op__fn_unit$4[12:0]$8815 + attribute \src "libresoc.v:165402.14-165402.43" + wire width 13 $0\br_op__fn_unit$4[12:0]$8877 + attribute \src "libresoc.v:166091.3-166118.6" + wire width 64 $0\br_op__imm_data__data$6$next[63:0]$8839 + attribute \src "libresoc.v:166011.3-166012.65" + wire width 64 $0\br_op__imm_data__data$6[63:0]$8819 + attribute \src "libresoc.v:165411.14-165411.62" + wire width 64 $0\br_op__imm_data__data$6[63:0]$8879 + attribute \src "libresoc.v:166091.3-166118.6" + wire $0\br_op__imm_data__ok$7$next[0:0]$8840 + attribute \src "libresoc.v:166013.3-166014.61" + wire $0\br_op__imm_data__ok$7[0:0]$8821 + attribute \src "libresoc.v:165420.7-165420.37" + wire $0\br_op__imm_data__ok$7[0:0]$8881 + attribute \src "libresoc.v:166091.3-166118.6" + wire width 32 $0\br_op__insn$5$next[31:0]$8841 + attribute \src "libresoc.v:166009.3-166010.45" + wire width 32 $0\br_op__insn$5[31:0]$8817 + attribute \src "libresoc.v:165429.14-165429.37" + wire width 32 $0\br_op__insn$5[31:0]$8883 + attribute \src "libresoc.v:166091.3-166118.6" + wire width 7 $0\br_op__insn_type$3$next[6:0]$8842 + attribute \src "libresoc.v:166005.3-166006.55" + wire width 7 $0\br_op__insn_type$3[6:0]$8813 + attribute \src "libresoc.v:165660.13-165660.41" + wire width 7 $0\br_op__insn_type$3[6:0]$8885 + attribute \src "libresoc.v:166091.3-166118.6" + wire $0\br_op__is_32bit$9$next[0:0]$8843 + attribute \src "libresoc.v:166017.3-166018.53" + wire $0\br_op__is_32bit$9[0:0]$8825 + attribute \src "libresoc.v:165669.7-165669.33" + wire $0\br_op__is_32bit$9[0:0]$8887 + attribute \src "libresoc.v:166091.3-166118.6" + wire $0\br_op__lk$8$next[0:0]$8844 + attribute \src "libresoc.v:166015.3-166016.41" + wire $0\br_op__lk$8[0:0]$8823 + attribute \src "libresoc.v:165678.7-165678.27" + wire $0\br_op__lk$8[0:0]$8889 + attribute \src "libresoc.v:166119.3-166137.6" + wire width 64 $0\fast1$10$next[63:0]$8856 + attribute \src "libresoc.v:165999.3-166000.35" + wire width 64 $0\fast1$10[63:0]$8808 + attribute \src "libresoc.v:165691.14-165691.47" + wire width 64 $0\fast1$10[63:0]$8891 + attribute \src "libresoc.v:166119.3-166137.6" + wire $0\fast1_ok$next[0:0]$8857 + attribute \src "libresoc.v:166001.3-166002.33" + wire $0\fast1_ok[0:0] + attribute \src "libresoc.v:166138.3-166156.6" + wire width 64 $0\fast2$11$next[63:0]$8862 + attribute \src "libresoc.v:165995.3-165996.35" + wire width 64 $0\fast2$11[63:0]$8805 + attribute \src "libresoc.v:165707.14-165707.47" + wire width 64 $0\fast2$11[63:0]$8894 + attribute \src "libresoc.v:166138.3-166156.6" + wire $0\fast2_ok$next[0:0]$8863 + attribute \src "libresoc.v:165997.3-165998.33" + wire $0\fast2_ok[0:0] + attribute \src "libresoc.v:165342.7-165342.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:166078.3-166090.6" + wire width 2 $0\muxid$1$next[1:0]$8834 + attribute \src "libresoc.v:166019.3-166020.33" + wire width 2 $0\muxid$1[1:0]$8827 + attribute \src "libresoc.v:165953.13-165953.29" + wire width 2 $0\muxid$1[1:0]$8897 + attribute \src "libresoc.v:166157.3-166175.6" + wire width 64 $0\nia$next[63:0]$8868 + attribute \src "libresoc.v:165991.3-165992.23" + wire width 64 $0\nia[63:0] + attribute \src "libresoc.v:166157.3-166175.6" + wire $0\nia_ok$next[0:0]$8869 + attribute \src "libresoc.v:165993.3-165994.29" + wire $0\nia_ok[0:0] + attribute \src "libresoc.v:166060.3-166077.6" + wire $0\r_busy$next[0:0]$8830 + attribute \src "libresoc.v:166021.3-166022.29" + wire $0\r_busy[0:0] + attribute \src "libresoc.v:166091.3-166118.6" + wire width 64 $1\br_op__cia$2$next[63:0]$8845 + attribute \src "libresoc.v:166091.3-166118.6" + wire width 13 $1\br_op__fn_unit$4$next[12:0]$8846 + attribute \src "libresoc.v:166091.3-166118.6" + wire width 64 $1\br_op__imm_data__data$6$next[63:0]$8847 + attribute \src "libresoc.v:166091.3-166118.6" + wire $1\br_op__imm_data__ok$7$next[0:0]$8848 + attribute \src "libresoc.v:166091.3-166118.6" + wire width 32 $1\br_op__insn$5$next[31:0]$8849 + attribute \src "libresoc.v:166091.3-166118.6" + wire width 7 $1\br_op__insn_type$3$next[6:0]$8850 + attribute \src "libresoc.v:166091.3-166118.6" + wire $1\br_op__is_32bit$9$next[0:0]$8851 + attribute \src "libresoc.v:166091.3-166118.6" + wire $1\br_op__lk$8$next[0:0]$8852 + attribute \src "libresoc.v:166119.3-166137.6" + wire width 64 $1\fast1$10$next[63:0]$8858 + attribute \src "libresoc.v:166119.3-166137.6" + wire $1\fast1_ok$next[0:0]$8859 + attribute \src "libresoc.v:165698.7-165698.22" + wire $1\fast1_ok[0:0] + attribute \src "libresoc.v:166138.3-166156.6" + wire width 64 $1\fast2$11$next[63:0]$8864 + attribute \src "libresoc.v:166138.3-166156.6" + wire $1\fast2_ok$next[0:0]$8865 + attribute \src "libresoc.v:165714.7-165714.22" + wire $1\fast2_ok[0:0] + attribute \src "libresoc.v:166078.3-166090.6" + wire width 2 $1\muxid$1$next[1:0]$8835 + attribute \src "libresoc.v:166157.3-166175.6" + wire width 64 $1\nia$next[63:0]$8870 + attribute \src "libresoc.v:165966.14-165966.40" + wire width 64 $1\nia[63:0] + attribute \src "libresoc.v:166157.3-166175.6" + wire $1\nia_ok$next[0:0]$8871 + attribute \src "libresoc.v:165973.7-165973.20" + wire $1\nia_ok[0:0] + attribute \src "libresoc.v:166060.3-166077.6" + wire $1\r_busy$next[0:0]$8831 + attribute \src "libresoc.v:165987.7-165987.20" + wire $1\r_busy[0:0] + attribute \src "libresoc.v:166091.3-166118.6" + wire width 64 $2\br_op__imm_data__data$6$next[63:0]$8853 + attribute \src "libresoc.v:166091.3-166118.6" + wire $2\br_op__imm_data__ok$7$next[0:0]$8854 + attribute \src "libresoc.v:166119.3-166137.6" + wire $2\fast1_ok$next[0:0]$8860 + attribute \src "libresoc.v:166138.3-166156.6" + wire $2\fast2_ok$next[0:0]$8866 + attribute \src "libresoc.v:166157.3-166175.6" + wire $2\nia_ok$next[0:0]$8872 + attribute \src "libresoc.v:166060.3-166077.6" + wire $2\r_busy$next[0:0]$8832 + attribute \src "libresoc.v:165990.18-165990.118" + wire $and$libresoc.v:165990$8801_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" + wire \$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 5 \br_op__cia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 19 \br_op__cia$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \br_op__cia$2$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \br_op__cia$27 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 input 7 \br_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \br_op__fn_unit$29 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 output 21 \br_op__fn_unit$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \br_op__fn_unit$4$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 9 \br_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \br_op__imm_data__data$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 23 \br_op__imm_data__data$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \br_op__imm_data__data$6$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \br_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \br_op__imm_data__ok$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 24 \br_op__imm_data__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \br_op__imm_data__ok$7$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 8 \br_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \br_op__insn$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 22 \br_op__insn$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \br_op__insn$5$next + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 6 \br_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \br_op__insn_type$28 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 20 \br_op__insn_type$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \br_op__insn_type$3$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \br_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \br_op__is_32bit$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 26 \br_op__is_32bit$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \br_op__is_32bit$9$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 11 \br_op__lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \br_op__lk$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 25 \br_op__lk$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \br_op__lk$8$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 33 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 4 input 15 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 13 \fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 27 \fast1$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \fast1$10$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \fast1$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 28 \fast1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \fast1_ok$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \fast1_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 14 \fast2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 29 \fast2$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \fast2$11$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \fast2$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 30 \fast2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \fast2_ok$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \fast2_ok$next + attribute \src "libresoc.v:165342.7-165342.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \main_br_op__cia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \main_br_op__cia$13 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \main_br_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \main_br_op__fn_unit$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \main_br_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \main_br_op__imm_data__data$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_br_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_br_op__imm_data__ok$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \main_br_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \main_br_op__insn$16 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \main_br_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \main_br_op__insn_type$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_br_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_br_op__is_32bit$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_br_op__lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_br_op__lk$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 4 \main_cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \main_fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \main_fast1$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \main_fast1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \main_fast2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \main_fast2$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \main_fast2_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \main_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \main_muxid$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \main_nia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \main_nia_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 input 4 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 output 18 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid$1$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid$26 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + wire \n_i_rdy_data + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire input 17 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire output 16 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 31 \nia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \nia$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \nia$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 32 \nia_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \nia_ok$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \nia_ok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" + wire output 3 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" + wire input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" + wire \p_valid_i$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" + wire \p_valid_i_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire \r_busy$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" + cell $and $and$libresoc.v:165990$8801 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i$23 + connect \B \p_ready_o + connect \Y $and$libresoc.v:165990$8801_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:166023.13-166051.4" + cell \main$22 \main + connect \br_op__cia \main_br_op__cia + connect \br_op__cia$2 \main_br_op__cia$13 + connect \br_op__fn_unit \main_br_op__fn_unit + connect \br_op__fn_unit$4 \main_br_op__fn_unit$15 + connect \br_op__imm_data__data \main_br_op__imm_data__data + connect \br_op__imm_data__data$6 \main_br_op__imm_data__data$17 + connect \br_op__imm_data__ok \main_br_op__imm_data__ok + connect \br_op__imm_data__ok$7 \main_br_op__imm_data__ok$18 + connect \br_op__insn \main_br_op__insn + connect \br_op__insn$5 \main_br_op__insn$16 + connect \br_op__insn_type \main_br_op__insn_type + connect \br_op__insn_type$3 \main_br_op__insn_type$14 + connect \br_op__is_32bit \main_br_op__is_32bit + connect \br_op__is_32bit$9 \main_br_op__is_32bit$20 + connect \br_op__lk \main_br_op__lk + connect \br_op__lk$8 \main_br_op__lk$19 + connect \cr_a \main_cr_a + connect \fast1 \main_fast1 + connect \fast1$10 \main_fast1$21 + connect \fast1_ok \main_fast1_ok + connect \fast2 \main_fast2 + connect \fast2$11 \main_fast2$22 + connect \fast2_ok \main_fast2_ok + connect \muxid \main_muxid + connect \muxid$1 \main_muxid$12 + connect \nia \main_nia + connect \nia_ok \main_nia_ok + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:166052.10-166055.4" + cell \n$21 \n + connect \n_ready_i \n_ready_i + connect \n_valid_o \n_valid_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:166056.10-166059.4" + cell \p$20 \p + connect \p_ready_o \p_ready_o + connect \p_valid_i \p_valid_i + end + attribute \src "libresoc.v:165342.7-165342.20" + process $proc$libresoc.v:165342$8873 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:165349.14-165349.51" + process $proc$libresoc.v:165349$8874 + assign { } { } + assign $0\br_op__cia$2[63:0]$8875 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \br_op__cia$2 $0\br_op__cia$2[63:0]$8875 + end + attribute \src "libresoc.v:165402.14-165402.43" + process $proc$libresoc.v:165402$8876 + assign { } { } + assign $0\br_op__fn_unit$4[12:0]$8877 13'0000000000000 + sync always + sync init + update \br_op__fn_unit$4 $0\br_op__fn_unit$4[12:0]$8877 + end + attribute \src "libresoc.v:165411.14-165411.62" + process $proc$libresoc.v:165411$8878 + assign { } { } + assign $0\br_op__imm_data__data$6[63:0]$8879 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \br_op__imm_data__data$6 $0\br_op__imm_data__data$6[63:0]$8879 + end + attribute \src "libresoc.v:165420.7-165420.37" + process $proc$libresoc.v:165420$8880 + assign { } { } + assign $0\br_op__imm_data__ok$7[0:0]$8881 1'0 + sync always + sync init + update \br_op__imm_data__ok$7 $0\br_op__imm_data__ok$7[0:0]$8881 + end + attribute \src "libresoc.v:165429.14-165429.37" + process $proc$libresoc.v:165429$8882 + assign { } { } + assign $0\br_op__insn$5[31:0]$8883 0 + sync always + sync init + update \br_op__insn$5 $0\br_op__insn$5[31:0]$8883 + end + attribute \src "libresoc.v:165660.13-165660.41" + process $proc$libresoc.v:165660$8884 + assign { } { } + assign $0\br_op__insn_type$3[6:0]$8885 7'0000000 + sync always + sync init + update \br_op__insn_type$3 $0\br_op__insn_type$3[6:0]$8885 + end + attribute \src "libresoc.v:165669.7-165669.33" + process $proc$libresoc.v:165669$8886 + assign { } { } + assign $0\br_op__is_32bit$9[0:0]$8887 1'0 + sync always + sync init + update \br_op__is_32bit$9 $0\br_op__is_32bit$9[0:0]$8887 + end + attribute \src "libresoc.v:165678.7-165678.27" + process $proc$libresoc.v:165678$8888 + assign { } { } + assign $0\br_op__lk$8[0:0]$8889 1'0 + sync always + sync init + update \br_op__lk$8 $0\br_op__lk$8[0:0]$8889 + end + attribute \src "libresoc.v:165691.14-165691.47" + process $proc$libresoc.v:165691$8890 + assign { } { } + assign $0\fast1$10[63:0]$8891 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \fast1$10 $0\fast1$10[63:0]$8891 + end + attribute \src "libresoc.v:165698.7-165698.22" + process $proc$libresoc.v:165698$8892 + assign { } { } + assign $1\fast1_ok[0:0] 1'0 + sync always + sync init + update \fast1_ok $1\fast1_ok[0:0] + end + attribute \src "libresoc.v:165707.14-165707.47" + process $proc$libresoc.v:165707$8893 + assign { } { } + assign $0\fast2$11[63:0]$8894 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \fast2$11 $0\fast2$11[63:0]$8894 + end + attribute \src "libresoc.v:165714.7-165714.22" + process $proc$libresoc.v:165714$8895 + assign { } { } + assign $1\fast2_ok[0:0] 1'0 + sync always + sync init + update \fast2_ok $1\fast2_ok[0:0] + end + attribute \src "libresoc.v:165953.13-165953.29" + process $proc$libresoc.v:165953$8896 + assign { } { } + assign $0\muxid$1[1:0]$8897 2'00 + sync always + sync init + update \muxid$1 $0\muxid$1[1:0]$8897 + end + attribute \src "libresoc.v:165966.14-165966.40" + process $proc$libresoc.v:165966$8898 + assign { } { } + assign $1\nia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \nia $1\nia[63:0] + end + attribute \src "libresoc.v:165973.7-165973.20" + process $proc$libresoc.v:165973$8899 + assign { } { } + assign $1\nia_ok[0:0] 1'0 + sync always + sync init + update \nia_ok $1\nia_ok[0:0] + end + attribute \src "libresoc.v:165987.7-165987.20" + process $proc$libresoc.v:165987$8900 + assign { } { } + assign $1\r_busy[0:0] 1'0 + sync always + sync init + update \r_busy $1\r_busy[0:0] + end + attribute \src "libresoc.v:165991.3-165992.23" + process $proc$libresoc.v:165991$8802 + assign { } { } + assign $0\nia[63:0] \nia$next + sync posedge \coresync_clk + update \nia $0\nia[63:0] + end + attribute \src "libresoc.v:165993.3-165994.29" + process $proc$libresoc.v:165993$8803 + assign { } { } + assign $0\nia_ok[0:0] \nia_ok$next + sync posedge \coresync_clk + update \nia_ok $0\nia_ok[0:0] + end + attribute \src "libresoc.v:165995.3-165996.35" + process $proc$libresoc.v:165995$8804 + assign { } { } + assign $0\fast2$11[63:0]$8805 \fast2$11$next + sync posedge \coresync_clk + update \fast2$11 $0\fast2$11[63:0]$8805 + end + attribute \src "libresoc.v:165997.3-165998.33" + process $proc$libresoc.v:165997$8806 + assign { } { } + assign $0\fast2_ok[0:0] \fast2_ok$next + sync posedge \coresync_clk + update \fast2_ok $0\fast2_ok[0:0] + end + attribute \src "libresoc.v:165999.3-166000.35" + process $proc$libresoc.v:165999$8807 + assign { } { } + assign $0\fast1$10[63:0]$8808 \fast1$10$next + sync posedge \coresync_clk + update \fast1$10 $0\fast1$10[63:0]$8808 + end + attribute \src "libresoc.v:166001.3-166002.33" + process $proc$libresoc.v:166001$8809 + assign { } { } + assign $0\fast1_ok[0:0] \fast1_ok$next + sync posedge \coresync_clk + update \fast1_ok $0\fast1_ok[0:0] + end + attribute \src "libresoc.v:166003.3-166004.43" + process $proc$libresoc.v:166003$8810 + assign { } { } + assign $0\br_op__cia$2[63:0]$8811 \br_op__cia$2$next + sync posedge \coresync_clk + update \br_op__cia$2 $0\br_op__cia$2[63:0]$8811 + end + attribute \src "libresoc.v:166005.3-166006.55" + process $proc$libresoc.v:166005$8812 + assign { } { } + assign $0\br_op__insn_type$3[6:0]$8813 \br_op__insn_type$3$next + sync posedge \coresync_clk + update \br_op__insn_type$3 $0\br_op__insn_type$3[6:0]$8813 + end + attribute \src "libresoc.v:166007.3-166008.51" + process $proc$libresoc.v:166007$8814 + assign { } { } + assign $0\br_op__fn_unit$4[12:0]$8815 \br_op__fn_unit$4$next + sync posedge \coresync_clk + update \br_op__fn_unit$4 $0\br_op__fn_unit$4[12:0]$8815 + end + attribute \src "libresoc.v:166009.3-166010.45" + process $proc$libresoc.v:166009$8816 + assign { } { } + assign $0\br_op__insn$5[31:0]$8817 \br_op__insn$5$next + sync posedge \coresync_clk + update \br_op__insn$5 $0\br_op__insn$5[31:0]$8817 + end + attribute \src "libresoc.v:166011.3-166012.65" + process $proc$libresoc.v:166011$8818 + assign { } { } + assign $0\br_op__imm_data__data$6[63:0]$8819 \br_op__imm_data__data$6$next + sync posedge \coresync_clk + update \br_op__imm_data__data$6 $0\br_op__imm_data__data$6[63:0]$8819 + end + attribute \src "libresoc.v:166013.3-166014.61" + process $proc$libresoc.v:166013$8820 + assign { } { } + assign $0\br_op__imm_data__ok$7[0:0]$8821 \br_op__imm_data__ok$7$next + sync posedge \coresync_clk + update \br_op__imm_data__ok$7 $0\br_op__imm_data__ok$7[0:0]$8821 + end + attribute \src "libresoc.v:166015.3-166016.41" + process $proc$libresoc.v:166015$8822 + assign { } { } + assign $0\br_op__lk$8[0:0]$8823 \br_op__lk$8$next + sync posedge \coresync_clk + update \br_op__lk$8 $0\br_op__lk$8[0:0]$8823 + end + attribute \src "libresoc.v:166017.3-166018.53" + process $proc$libresoc.v:166017$8824 + assign { } { } + assign $0\br_op__is_32bit$9[0:0]$8825 \br_op__is_32bit$9$next + sync posedge \coresync_clk + update \br_op__is_32bit$9 $0\br_op__is_32bit$9[0:0]$8825 + end + attribute \src "libresoc.v:166019.3-166020.33" + process $proc$libresoc.v:166019$8826 + assign { } { } + assign $0\muxid$1[1:0]$8827 \muxid$1$next + sync posedge \coresync_clk + update \muxid$1 $0\muxid$1[1:0]$8827 + end + attribute \src "libresoc.v:166021.3-166022.29" + process $proc$libresoc.v:166021$8828 + assign { } { } + assign $0\r_busy[0:0] \r_busy$next + sync posedge \coresync_clk + update \r_busy $0\r_busy[0:0] + end + attribute \src "libresoc.v:166060.3-166077.6" + process $proc$libresoc.v:166060$8829 + assign { } { } + assign { } { } + assign { } { } + assign $0\r_busy$next[0:0]$8830 $2\r_busy$next[0:0]$8832 + attribute \src "libresoc.v:166061.5-166061.29" + switch \initial + attribute \src "libresoc.v:166061.9-166061.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\r_busy$next[0:0]$8831 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\r_busy$next[0:0]$8831 1'0 + case + assign $1\r_busy$next[0:0]$8831 \r_busy + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r_busy$next[0:0]$8832 1'0 + case + assign $2\r_busy$next[0:0]$8832 $1\r_busy$next[0:0]$8831 + end + sync always + update \r_busy$next $0\r_busy$next[0:0]$8830 + end + attribute \src "libresoc.v:166078.3-166090.6" + process $proc$libresoc.v:166078$8833 + assign { } { } + assign { } { } + assign $0\muxid$1$next[1:0]$8834 $1\muxid$1$next[1:0]$8835 + attribute \src "libresoc.v:166079.5-166079.29" + switch \initial + attribute \src "libresoc.v:166079.9-166079.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\muxid$1$next[1:0]$8835 \muxid$26 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\muxid$1$next[1:0]$8835 \muxid$26 + case + assign $1\muxid$1$next[1:0]$8835 \muxid$1 + end + sync always + update \muxid$1$next $0\muxid$1$next[1:0]$8834 + end + attribute \src "libresoc.v:166091.3-166118.6" + process $proc$libresoc.v:166091$8836 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\br_op__cia$2$next[63:0]$8837 $1\br_op__cia$2$next[63:0]$8845 + assign $0\br_op__fn_unit$4$next[12:0]$8838 $1\br_op__fn_unit$4$next[12:0]$8846 + assign { } { } + assign { } { } + assign $0\br_op__insn$5$next[31:0]$8841 $1\br_op__insn$5$next[31:0]$8849 + assign $0\br_op__insn_type$3$next[6:0]$8842 $1\br_op__insn_type$3$next[6:0]$8850 + assign $0\br_op__is_32bit$9$next[0:0]$8843 $1\br_op__is_32bit$9$next[0:0]$8851 + assign $0\br_op__lk$8$next[0:0]$8844 $1\br_op__lk$8$next[0:0]$8852 + assign $0\br_op__imm_data__data$6$next[63:0]$8839 $2\br_op__imm_data__data$6$next[63:0]$8853 + assign $0\br_op__imm_data__ok$7$next[0:0]$8840 $2\br_op__imm_data__ok$7$next[0:0]$8854 + attribute \src "libresoc.v:166092.5-166092.29" + switch \initial + attribute \src "libresoc.v:166092.9-166092.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\br_op__is_32bit$9$next[0:0]$8851 $1\br_op__lk$8$next[0:0]$8852 $1\br_op__imm_data__ok$7$next[0:0]$8848 $1\br_op__imm_data__data$6$next[63:0]$8847 $1\br_op__insn$5$next[31:0]$8849 $1\br_op__fn_unit$4$next[12:0]$8846 $1\br_op__insn_type$3$next[6:0]$8850 $1\br_op__cia$2$next[63:0]$8845 } { \br_op__is_32bit$34 \br_op__lk$33 \br_op__imm_data__ok$32 \br_op__imm_data__data$31 \br_op__insn$30 \br_op__fn_unit$29 \br_op__insn_type$28 \br_op__cia$27 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\br_op__is_32bit$9$next[0:0]$8851 $1\br_op__lk$8$next[0:0]$8852 $1\br_op__imm_data__ok$7$next[0:0]$8848 $1\br_op__imm_data__data$6$next[63:0]$8847 $1\br_op__insn$5$next[31:0]$8849 $1\br_op__fn_unit$4$next[12:0]$8846 $1\br_op__insn_type$3$next[6:0]$8850 $1\br_op__cia$2$next[63:0]$8845 } { \br_op__is_32bit$34 \br_op__lk$33 \br_op__imm_data__ok$32 \br_op__imm_data__data$31 \br_op__insn$30 \br_op__fn_unit$29 \br_op__insn_type$28 \br_op__cia$27 } + case + assign $1\br_op__cia$2$next[63:0]$8845 \br_op__cia$2 + assign $1\br_op__fn_unit$4$next[12:0]$8846 \br_op__fn_unit$4 + assign $1\br_op__imm_data__data$6$next[63:0]$8847 \br_op__imm_data__data$6 + assign $1\br_op__imm_data__ok$7$next[0:0]$8848 \br_op__imm_data__ok$7 + assign $1\br_op__insn$5$next[31:0]$8849 \br_op__insn$5 + assign $1\br_op__insn_type$3$next[6:0]$8850 \br_op__insn_type$3 + assign $1\br_op__is_32bit$9$next[0:0]$8851 \br_op__is_32bit$9 + assign $1\br_op__lk$8$next[0:0]$8852 \br_op__lk$8 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $2\br_op__imm_data__data$6$next[63:0]$8853 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\br_op__imm_data__ok$7$next[0:0]$8854 1'0 + case + assign $2\br_op__imm_data__data$6$next[63:0]$8853 $1\br_op__imm_data__data$6$next[63:0]$8847 + assign $2\br_op__imm_data__ok$7$next[0:0]$8854 $1\br_op__imm_data__ok$7$next[0:0]$8848 + end + sync always + update \br_op__cia$2$next $0\br_op__cia$2$next[63:0]$8837 + update \br_op__fn_unit$4$next $0\br_op__fn_unit$4$next[12:0]$8838 + update \br_op__imm_data__data$6$next $0\br_op__imm_data__data$6$next[63:0]$8839 + update \br_op__imm_data__ok$7$next $0\br_op__imm_data__ok$7$next[0:0]$8840 + update \br_op__insn$5$next $0\br_op__insn$5$next[31:0]$8841 + update \br_op__insn_type$3$next $0\br_op__insn_type$3$next[6:0]$8842 + update \br_op__is_32bit$9$next $0\br_op__is_32bit$9$next[0:0]$8843 + update \br_op__lk$8$next $0\br_op__lk$8$next[0:0]$8844 + end + attribute \src "libresoc.v:166119.3-166137.6" + process $proc$libresoc.v:166119$8855 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\fast1$10$next[63:0]$8856 $1\fast1$10$next[63:0]$8858 + assign { } { } + assign $0\fast1_ok$next[0:0]$8857 $2\fast1_ok$next[0:0]$8860 + attribute \src "libresoc.v:166120.5-166120.29" + switch \initial + attribute \src "libresoc.v:166120.9-166120.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\fast1_ok$next[0:0]$8859 $1\fast1$10$next[63:0]$8858 } { \fast1_ok$36 \fast1$35 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\fast1_ok$next[0:0]$8859 $1\fast1$10$next[63:0]$8858 } { \fast1_ok$36 \fast1$35 } + case + assign $1\fast1$10$next[63:0]$8858 \fast1$10 + assign $1\fast1_ok$next[0:0]$8859 \fast1_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\fast1_ok$next[0:0]$8860 1'0 + case + assign $2\fast1_ok$next[0:0]$8860 $1\fast1_ok$next[0:0]$8859 + end + sync always + update \fast1$10$next $0\fast1$10$next[63:0]$8856 + update \fast1_ok$next $0\fast1_ok$next[0:0]$8857 + end + attribute \src "libresoc.v:166138.3-166156.6" + process $proc$libresoc.v:166138$8861 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\fast2$11$next[63:0]$8862 $1\fast2$11$next[63:0]$8864 + assign { } { } + assign $0\fast2_ok$next[0:0]$8863 $2\fast2_ok$next[0:0]$8866 + attribute \src "libresoc.v:166139.5-166139.29" + switch \initial + attribute \src "libresoc.v:166139.9-166139.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\fast2_ok$next[0:0]$8865 $1\fast2$11$next[63:0]$8864 } { \fast2_ok$38 \fast2$37 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\fast2_ok$next[0:0]$8865 $1\fast2$11$next[63:0]$8864 } { \fast2_ok$38 \fast2$37 } + case + assign $1\fast2$11$next[63:0]$8864 \fast2$11 + assign $1\fast2_ok$next[0:0]$8865 \fast2_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\fast2_ok$next[0:0]$8866 1'0 + case + assign $2\fast2_ok$next[0:0]$8866 $1\fast2_ok$next[0:0]$8865 + end + sync always + update \fast2$11$next $0\fast2$11$next[63:0]$8862 + update \fast2_ok$next $0\fast2_ok$next[0:0]$8863 + end + attribute \src "libresoc.v:166157.3-166175.6" + process $proc$libresoc.v:166157$8867 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\nia$next[63:0]$8868 $1\nia$next[63:0]$8870 + assign { } { } + assign $0\nia_ok$next[0:0]$8869 $2\nia_ok$next[0:0]$8872 + attribute \src "libresoc.v:166158.5-166158.29" + switch \initial + attribute \src "libresoc.v:166158.9-166158.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\nia_ok$next[0:0]$8871 $1\nia$next[63:0]$8870 } { \nia_ok$40 \nia$39 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\nia_ok$next[0:0]$8871 $1\nia$next[63:0]$8870 } { \nia_ok$40 \nia$39 } + case + assign $1\nia$next[63:0]$8870 \nia + assign $1\nia_ok$next[0:0]$8871 \nia_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\nia_ok$next[0:0]$8872 1'0 + case + assign $2\nia_ok$next[0:0]$8872 $1\nia_ok$next[0:0]$8871 + end + sync always + update \nia$next $0\nia$next[63:0]$8868 + update \nia_ok$next $0\nia_ok$next[0:0]$8869 + end + connect \$24 $and$libresoc.v:165990$8801_Y + connect \p_ready_o \n_i_rdy_data + connect \n_valid_o \r_busy + connect { \nia_ok$40 \nia$39 } { \main_nia_ok \main_nia } + connect { \fast2_ok$38 \fast2$37 } { \main_fast2_ok \main_fast2$22 } + connect { \fast1_ok$36 \fast1$35 } { \main_fast1_ok \main_fast1$21 } + connect { \br_op__is_32bit$34 \br_op__lk$33 \br_op__imm_data__ok$32 \br_op__imm_data__data$31 \br_op__insn$30 \br_op__fn_unit$29 \br_op__insn_type$28 \br_op__cia$27 } { \main_br_op__is_32bit$20 \main_br_op__lk$19 \main_br_op__imm_data__ok$18 \main_br_op__imm_data__data$17 \main_br_op__insn$16 \main_br_op__fn_unit$15 \main_br_op__insn_type$14 \main_br_op__cia$13 } + connect \muxid$26 \main_muxid$12 + connect \p_valid_i_p_ready_o \$24 + connect \n_i_rdy_data \n_ready_i + connect \p_valid_i$23 \p_valid_i + connect \main_cr_a \cr_a + connect \main_fast2 \fast2 + connect \main_fast1 \fast1 + connect { \main_br_op__is_32bit \main_br_op__lk \main_br_op__imm_data__ok \main_br_op__imm_data__data \main_br_op__insn \main_br_op__fn_unit \main_br_op__insn_type \main_br_op__cia } { \br_op__is_32bit \br_op__lk \br_op__imm_data__ok \br_op__imm_data__data \br_op__insn \br_op__fn_unit \br_op__insn_type \br_op__cia } + connect \main_muxid \muxid +end +attribute \src "libresoc.v:166195.1-167115.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.alu_spr0.pipe" +attribute \generator "nMigen" +module \pipe$64 + attribute \src "libresoc.v:167018.3-167036.6" + wire width 64 $0\fast1$7$next[63:0]$8960 + attribute \src "libresoc.v:166871.3-166872.33" + wire width 64 $0\fast1$7[63:0]$8912 + attribute \src "libresoc.v:166209.14-166209.46" + wire width 64 $0\fast1$7[63:0]$8984 + attribute \src "libresoc.v:167018.3-167036.6" + wire $0\fast1_ok$next[0:0]$8959 + attribute \src "libresoc.v:166873.3-166874.33" + wire $0\fast1_ok[0:0] + attribute \src "libresoc.v:166196.7-166196.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:166951.3-166963.6" + wire width 2 $0\muxid$1$next[1:0]$8935 + attribute \src "libresoc.v:166891.3-166892.33" + wire width 2 $0\muxid$1[1:0]$8928 + attribute \src "libresoc.v:166223.13-166223.29" + wire width 2 $0\muxid$1[1:0]$8987 + attribute \src "libresoc.v:166980.3-166998.6" + wire width 64 $0\o$next[63:0]$8947 + attribute \src "libresoc.v:166879.3-166880.19" + wire width 64 $0\o[63:0] + attribute \src "libresoc.v:166980.3-166998.6" + wire $0\o_ok$next[0:0]$8948 + attribute \src "libresoc.v:166881.3-166882.25" + wire $0\o_ok[0:0] + attribute \src "libresoc.v:166933.3-166950.6" + wire $0\r_busy$next[0:0]$8931 + attribute \src "libresoc.v:166893.3-166894.29" + wire $0\r_busy[0:0] + attribute \src "libresoc.v:166999.3-167017.6" + wire width 64 $0\spr1$6$next[63:0]$8953 + attribute \src "libresoc.v:166875.3-166876.31" + wire width 64 $0\spr1$6[63:0]$8915 + attribute \src "libresoc.v:166268.14-166268.45" + wire width 64 $0\spr1$6[63:0]$8992 + attribute \src "libresoc.v:166999.3-167017.6" + wire $0\spr1_ok$next[0:0]$8954 + attribute \src "libresoc.v:166877.3-166878.31" + wire $0\spr1_ok[0:0] + attribute \src "libresoc.v:166964.3-166979.6" + wire width 13 $0\spr_op__fn_unit$3$next[12:0]$8938 + attribute \src "libresoc.v:166885.3-166886.53" + wire width 13 $0\spr_op__fn_unit$3[12:0]$8922 + attribute \src "libresoc.v:166558.14-166558.44" + wire width 13 $0\spr_op__fn_unit$3[12:0]$8995 + attribute \src "libresoc.v:166964.3-166979.6" + wire width 32 $0\spr_op__insn$4$next[31:0]$8939 + attribute \src "libresoc.v:166887.3-166888.47" + wire width 32 $0\spr_op__insn$4[31:0]$8924 + attribute \src "libresoc.v:166567.14-166567.38" + wire width 32 $0\spr_op__insn$4[31:0]$8997 + attribute \src "libresoc.v:166964.3-166979.6" + wire width 7 $0\spr_op__insn_type$2$next[6:0]$8940 + attribute \src "libresoc.v:166883.3-166884.57" + wire width 7 $0\spr_op__insn_type$2[6:0]$8920 + attribute \src "libresoc.v:166722.13-166722.42" + wire width 7 $0\spr_op__insn_type$2[6:0]$8999 + attribute \src "libresoc.v:166964.3-166979.6" + wire $0\spr_op__is_32bit$5$next[0:0]$8941 + attribute \src "libresoc.v:166889.3-166890.55" + wire $0\spr_op__is_32bit$5[0:0]$8926 + attribute \src "libresoc.v:166807.7-166807.34" + wire $0\spr_op__is_32bit$5[0:0]$9001 + attribute \src "libresoc.v:167075.3-167093.6" + wire width 2 $0\xer_ca$10$next[1:0]$8977 + attribute \src "libresoc.v:166859.3-166860.37" + wire width 2 $0\xer_ca$10[1:0]$8903 + attribute \src "libresoc.v:166814.13-166814.31" + wire width 2 $0\xer_ca$10[1:0]$9003 + attribute \src "libresoc.v:167075.3-167093.6" + wire $0\xer_ca_ok$next[0:0]$8978 + attribute \src "libresoc.v:166861.3-166862.35" + wire $0\xer_ca_ok[0:0] + attribute \src "libresoc.v:167056.3-167074.6" + wire width 2 $0\xer_ov$9$next[1:0]$8972 + attribute \src "libresoc.v:166863.3-166864.35" + wire width 2 $0\xer_ov$9[1:0]$8906 + attribute \src "libresoc.v:166832.13-166832.30" + wire width 2 $0\xer_ov$9[1:0]$9006 + attribute \src "libresoc.v:167056.3-167074.6" + wire $0\xer_ov_ok$next[0:0]$8971 + attribute \src "libresoc.v:166865.3-166866.35" + wire $0\xer_ov_ok[0:0] + attribute \src "libresoc.v:167037.3-167055.6" + wire $0\xer_so$8$next[0:0]$8966 + attribute \src "libresoc.v:166867.3-166868.35" + wire $0\xer_so$8[0:0]$8909 + attribute \src "libresoc.v:166848.7-166848.24" + wire $0\xer_so$8[0:0]$9009 + attribute \src "libresoc.v:167037.3-167055.6" + wire $0\xer_so_ok$next[0:0]$8965 + attribute \src "libresoc.v:166869.3-166870.35" + wire $0\xer_so_ok[0:0] + attribute \src "libresoc.v:167018.3-167036.6" + wire width 64 $1\fast1$7$next[63:0]$8962 + attribute \src "libresoc.v:167018.3-167036.6" + wire $1\fast1_ok$next[0:0]$8961 + attribute \src "libresoc.v:166214.7-166214.22" + wire $1\fast1_ok[0:0] + attribute \src "libresoc.v:166951.3-166963.6" + wire width 2 $1\muxid$1$next[1:0]$8936 + attribute \src "libresoc.v:166980.3-166998.6" + wire width 64 $1\o$next[63:0]$8949 + attribute \src "libresoc.v:166236.14-166236.38" + wire width 64 $1\o[63:0] + attribute \src "libresoc.v:166980.3-166998.6" + wire $1\o_ok$next[0:0]$8950 + attribute \src "libresoc.v:166243.7-166243.18" + wire $1\o_ok[0:0] + attribute \src "libresoc.v:166933.3-166950.6" + wire $1\r_busy$next[0:0]$8932 + attribute \src "libresoc.v:166257.7-166257.20" + wire $1\r_busy[0:0] + attribute \src "libresoc.v:166999.3-167017.6" + wire width 64 $1\spr1$6$next[63:0]$8955 + attribute \src "libresoc.v:166999.3-167017.6" + wire $1\spr1_ok$next[0:0]$8956 + attribute \src "libresoc.v:166273.7-166273.21" + wire $1\spr1_ok[0:0] + attribute \src "libresoc.v:166964.3-166979.6" + wire width 13 $1\spr_op__fn_unit$3$next[12:0]$8942 + attribute \src "libresoc.v:166964.3-166979.6" + wire width 32 $1\spr_op__insn$4$next[31:0]$8943 + attribute \src "libresoc.v:166964.3-166979.6" + wire width 7 $1\spr_op__insn_type$2$next[6:0]$8944 + attribute \src "libresoc.v:166964.3-166979.6" + wire $1\spr_op__is_32bit$5$next[0:0]$8945 + attribute \src "libresoc.v:167075.3-167093.6" + wire width 2 $1\xer_ca$10$next[1:0]$8979 + attribute \src "libresoc.v:167075.3-167093.6" + wire $1\xer_ca_ok$next[0:0]$8980 + attribute \src "libresoc.v:166821.7-166821.23" + wire $1\xer_ca_ok[0:0] + attribute \src "libresoc.v:167056.3-167074.6" + wire width 2 $1\xer_ov$9$next[1:0]$8974 + attribute \src "libresoc.v:167056.3-167074.6" + wire $1\xer_ov_ok$next[0:0]$8973 + attribute \src "libresoc.v:166837.7-166837.23" + wire $1\xer_ov_ok[0:0] + attribute \src "libresoc.v:167037.3-167055.6" + wire $1\xer_so$8$next[0:0]$8968 + attribute \src "libresoc.v:167037.3-167055.6" + wire $1\xer_so_ok$next[0:0]$8967 + attribute \src "libresoc.v:166853.7-166853.23" + wire $1\xer_so_ok[0:0] + attribute \src "libresoc.v:167018.3-167036.6" + wire $2\fast1_ok$next[0:0]$8963 + attribute \src "libresoc.v:166980.3-166998.6" + wire $2\o_ok$next[0:0]$8951 + attribute \src "libresoc.v:166933.3-166950.6" + wire $2\r_busy$next[0:0]$8933 + attribute \src "libresoc.v:166999.3-167017.6" + wire $2\spr1_ok$next[0:0]$8957 + attribute \src "libresoc.v:167075.3-167093.6" + wire $2\xer_ca_ok$next[0:0]$8981 + attribute \src "libresoc.v:167056.3-167074.6" + wire $2\xer_ov_ok$next[0:0]$8975 + attribute \src "libresoc.v:167037.3-167055.6" + wire $2\xer_so_ok$next[0:0]$8969 + attribute \src "libresoc.v:166858.18-166858.118" + wire $and$libresoc.v:166858$8901_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" + wire \$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 34 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 11 \fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \fast1$33 + attribute \src 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\spr_main_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \spr_main_muxid$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \spr_main_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \spr_main_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \spr_main_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \spr_main_spr1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \spr_main_spr1$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \spr_main_spr1_ok + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 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attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute 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attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute 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attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 input 6 \spr_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \spr_op__fn_unit$26 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + 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width 32 \spr_op__insn$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 20 \spr_op__insn$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \spr_op__insn$4$next + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 5 \spr_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 18 \spr_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \spr_op__insn_type$2$next + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \spr_op__insn_type$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \spr_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \spr_op__is_32bit$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 21 \spr_op__is_32bit$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \spr_op__is_32bit$5$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 input 14 \xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 output 32 \xer_ca$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \xer_ca$10$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \xer_ca$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 33 \xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_ca_ok$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_ca_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 input 13 \xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \xer_ov$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 output 30 \xer_ov$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \xer_ov$9$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 31 \xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_ov_ok$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_ov_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 12 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 28 \xer_so$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so$8$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 29 \xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so_ok$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so_ok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" + cell $and $and$libresoc.v:166858$8901 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i$21 + connect \B \p_ready_o + connect \Y $and$libresoc.v:166858$8901_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:166895.10-166898.4" + cell \n$66 \n + connect \n_ready_i \n_ready_i + connect \n_valid_o \n_valid_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:166899.10-166902.4" + cell \p$65 \p + connect \p_ready_o \p_ready_o + connect \p_valid_i \p_valid_i + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:166903.12-166932.4" + cell \spr_main \spr_main + connect \fast1 \spr_main_fast1 + connect \fast1$7 \spr_main_fast1$17 + connect \fast1_ok \spr_main_fast1_ok + connect \muxid \spr_main_muxid + connect \muxid$1 \spr_main_muxid$11 + connect \o \spr_main_o + connect \o_ok \spr_main_o_ok + connect \ra \spr_main_ra + connect \spr1 \spr_main_spr1 + connect \spr1$6 \spr_main_spr1$16 + connect \spr1_ok \spr_main_spr1_ok + connect \spr_op__fn_unit \spr_main_spr_op__fn_unit + connect \spr_op__fn_unit$3 \spr_main_spr_op__fn_unit$13 + connect \spr_op__insn \spr_main_spr_op__insn + connect \spr_op__insn$4 \spr_main_spr_op__insn$14 + connect \spr_op__insn_type \spr_main_spr_op__insn_type + connect \spr_op__insn_type$2 \spr_main_spr_op__insn_type$12 + connect \spr_op__is_32bit \spr_main_spr_op__is_32bit + connect \spr_op__is_32bit$5 \spr_main_spr_op__is_32bit$15 + connect \xer_ca \spr_main_xer_ca + connect \xer_ca$10 \spr_main_xer_ca$20 + connect \xer_ca_ok \spr_main_xer_ca_ok + connect \xer_ov \spr_main_xer_ov + connect \xer_ov$9 \spr_main_xer_ov$19 + connect \xer_ov_ok \spr_main_xer_ov_ok + connect \xer_so \spr_main_xer_so + connect \xer_so$8 \spr_main_xer_so$18 + connect \xer_so_ok \spr_main_xer_so_ok + end + attribute \src "libresoc.v:166196.7-166196.20" + process $proc$libresoc.v:166196$8982 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:166209.14-166209.46" + process $proc$libresoc.v:166209$8983 + assign { } { } + assign $0\fast1$7[63:0]$8984 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \fast1$7 $0\fast1$7[63:0]$8984 + end + attribute \src "libresoc.v:166214.7-166214.22" + process $proc$libresoc.v:166214$8985 + assign { } { } + assign $1\fast1_ok[0:0] 1'0 + sync always + sync init + update \fast1_ok $1\fast1_ok[0:0] + end + attribute \src "libresoc.v:166223.13-166223.29" + process $proc$libresoc.v:166223$8986 + assign { } { } + assign $0\muxid$1[1:0]$8987 2'00 + sync always + sync init + update \muxid$1 $0\muxid$1[1:0]$8987 + end + attribute \src "libresoc.v:166236.14-166236.38" + process $proc$libresoc.v:166236$8988 + assign { } { } + assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \o $1\o[63:0] + end + attribute \src "libresoc.v:166243.7-166243.18" + process $proc$libresoc.v:166243$8989 + assign { } { } + assign $1\o_ok[0:0] 1'0 + sync always + sync init + update \o_ok $1\o_ok[0:0] + end + attribute \src "libresoc.v:166257.7-166257.20" + process $proc$libresoc.v:166257$8990 + assign { } { } + assign $1\r_busy[0:0] 1'0 + sync always + sync init + update \r_busy $1\r_busy[0:0] + end + attribute \src "libresoc.v:166268.14-166268.45" + process $proc$libresoc.v:166268$8991 + assign { } { } + assign $0\spr1$6[63:0]$8992 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \spr1$6 $0\spr1$6[63:0]$8992 + end + attribute \src "libresoc.v:166273.7-166273.21" + process $proc$libresoc.v:166273$8993 + assign { } { } + assign $1\spr1_ok[0:0] 1'0 + sync always + sync init + update \spr1_ok $1\spr1_ok[0:0] + end + attribute \src "libresoc.v:166558.14-166558.44" + process $proc$libresoc.v:166558$8994 + assign { } { } + assign $0\spr_op__fn_unit$3[12:0]$8995 13'0000000000000 + sync always + sync init + update \spr_op__fn_unit$3 $0\spr_op__fn_unit$3[12:0]$8995 + end + attribute \src "libresoc.v:166567.14-166567.38" + process $proc$libresoc.v:166567$8996 + assign { } { } + assign $0\spr_op__insn$4[31:0]$8997 0 + sync always + sync init + update \spr_op__insn$4 $0\spr_op__insn$4[31:0]$8997 + end + attribute \src "libresoc.v:166722.13-166722.42" + process $proc$libresoc.v:166722$8998 + assign { } { } + assign $0\spr_op__insn_type$2[6:0]$8999 7'0000000 + sync always + sync init + update \spr_op__insn_type$2 $0\spr_op__insn_type$2[6:0]$8999 + end + attribute \src "libresoc.v:166807.7-166807.34" + process $proc$libresoc.v:166807$9000 + assign { } { } + assign $0\spr_op__is_32bit$5[0:0]$9001 1'0 + sync always + sync init + update \spr_op__is_32bit$5 $0\spr_op__is_32bit$5[0:0]$9001 + end + attribute \src "libresoc.v:166814.13-166814.31" + process $proc$libresoc.v:166814$9002 + assign { } { } + assign $0\xer_ca$10[1:0]$9003 2'00 + sync always + sync init + update \xer_ca$10 $0\xer_ca$10[1:0]$9003 + end + attribute \src "libresoc.v:166821.7-166821.23" + process $proc$libresoc.v:166821$9004 + assign { } { } + assign $1\xer_ca_ok[0:0] 1'0 + sync always + sync init + update \xer_ca_ok $1\xer_ca_ok[0:0] + end + attribute \src "libresoc.v:166832.13-166832.30" + process $proc$libresoc.v:166832$9005 + assign { } { } + assign $0\xer_ov$9[1:0]$9006 2'00 + sync always + sync init + update \xer_ov$9 $0\xer_ov$9[1:0]$9006 + end + attribute \src "libresoc.v:166837.7-166837.23" + process $proc$libresoc.v:166837$9007 + assign { } { } + assign $1\xer_ov_ok[0:0] 1'0 + sync always + sync init + update \xer_ov_ok $1\xer_ov_ok[0:0] + end + attribute \src "libresoc.v:166848.7-166848.24" + process $proc$libresoc.v:166848$9008 + assign { } { } + assign $0\xer_so$8[0:0]$9009 1'0 + sync always + sync init + update \xer_so$8 $0\xer_so$8[0:0]$9009 + end + attribute \src "libresoc.v:166853.7-166853.23" + process $proc$libresoc.v:166853$9010 + assign { } { } + assign $1\xer_so_ok[0:0] 1'0 + sync always + sync init + update \xer_so_ok $1\xer_so_ok[0:0] + end + attribute \src "libresoc.v:166859.3-166860.37" + process $proc$libresoc.v:166859$8902 + assign { } { } + assign $0\xer_ca$10[1:0]$8903 \xer_ca$10$next + sync posedge \coresync_clk + update \xer_ca$10 $0\xer_ca$10[1:0]$8903 + end + attribute \src "libresoc.v:166861.3-166862.35" + process $proc$libresoc.v:166861$8904 + assign { } { } + assign $0\xer_ca_ok[0:0] \xer_ca_ok$next + sync posedge \coresync_clk + update \xer_ca_ok $0\xer_ca_ok[0:0] + end + attribute \src "libresoc.v:166863.3-166864.35" + process $proc$libresoc.v:166863$8905 + assign { } { } + assign $0\xer_ov$9[1:0]$8906 \xer_ov$9$next + sync posedge \coresync_clk + update \xer_ov$9 $0\xer_ov$9[1:0]$8906 + end + attribute \src "libresoc.v:166865.3-166866.35" + process $proc$libresoc.v:166865$8907 + assign { } { } + assign $0\xer_ov_ok[0:0] \xer_ov_ok$next + sync posedge \coresync_clk + update \xer_ov_ok $0\xer_ov_ok[0:0] + end + attribute \src "libresoc.v:166867.3-166868.35" + process $proc$libresoc.v:166867$8908 + assign { } { } + assign $0\xer_so$8[0:0]$8909 \xer_so$8$next + sync posedge \coresync_clk + update \xer_so$8 $0\xer_so$8[0:0]$8909 + end + attribute \src "libresoc.v:166869.3-166870.35" + process $proc$libresoc.v:166869$8910 + assign { } { } + assign $0\xer_so_ok[0:0] \xer_so_ok$next + sync posedge \coresync_clk + update \xer_so_ok $0\xer_so_ok[0:0] + end + attribute \src "libresoc.v:166871.3-166872.33" + process $proc$libresoc.v:166871$8911 + assign { } { } + assign $0\fast1$7[63:0]$8912 \fast1$7$next + sync posedge \coresync_clk + update \fast1$7 $0\fast1$7[63:0]$8912 + end + attribute \src "libresoc.v:166873.3-166874.33" + process $proc$libresoc.v:166873$8913 + assign { } { } + assign $0\fast1_ok[0:0] \fast1_ok$next + sync posedge \coresync_clk + update \fast1_ok $0\fast1_ok[0:0] + end + attribute \src "libresoc.v:166875.3-166876.31" + process $proc$libresoc.v:166875$8914 + assign { } { } + assign $0\spr1$6[63:0]$8915 \spr1$6$next + sync posedge \coresync_clk + update \spr1$6 $0\spr1$6[63:0]$8915 + end + attribute \src "libresoc.v:166877.3-166878.31" + process $proc$libresoc.v:166877$8916 + assign { } { } + assign $0\spr1_ok[0:0] \spr1_ok$next + sync posedge \coresync_clk + update \spr1_ok $0\spr1_ok[0:0] + end + attribute \src "libresoc.v:166879.3-166880.19" + process $proc$libresoc.v:166879$8917 + assign { } { } + assign $0\o[63:0] \o$next + sync posedge \coresync_clk + update \o $0\o[63:0] + end + attribute \src "libresoc.v:166881.3-166882.25" + process $proc$libresoc.v:166881$8918 + assign { } { } + assign $0\o_ok[0:0] \o_ok$next + sync posedge \coresync_clk + update \o_ok $0\o_ok[0:0] + end + attribute \src "libresoc.v:166883.3-166884.57" + process $proc$libresoc.v:166883$8919 + assign { } { } + assign $0\spr_op__insn_type$2[6:0]$8920 \spr_op__insn_type$2$next + sync posedge \coresync_clk + update \spr_op__insn_type$2 $0\spr_op__insn_type$2[6:0]$8920 + end + attribute \src "libresoc.v:166885.3-166886.53" + process $proc$libresoc.v:166885$8921 + assign { } { } + assign $0\spr_op__fn_unit$3[12:0]$8922 \spr_op__fn_unit$3$next + sync posedge \coresync_clk + update \spr_op__fn_unit$3 $0\spr_op__fn_unit$3[12:0]$8922 + end + attribute \src "libresoc.v:166887.3-166888.47" + process $proc$libresoc.v:166887$8923 + assign { } { } + assign $0\spr_op__insn$4[31:0]$8924 \spr_op__insn$4$next + sync posedge \coresync_clk + update \spr_op__insn$4 $0\spr_op__insn$4[31:0]$8924 + end + attribute \src "libresoc.v:166889.3-166890.55" + process $proc$libresoc.v:166889$8925 + assign { } { } + assign $0\spr_op__is_32bit$5[0:0]$8926 \spr_op__is_32bit$5$next + sync posedge \coresync_clk + update \spr_op__is_32bit$5 $0\spr_op__is_32bit$5[0:0]$8926 + end + attribute \src "libresoc.v:166891.3-166892.33" + process $proc$libresoc.v:166891$8927 + assign { } { } + assign $0\muxid$1[1:0]$8928 \muxid$1$next + sync posedge \coresync_clk + update \muxid$1 $0\muxid$1[1:0]$8928 + end + attribute \src "libresoc.v:166893.3-166894.29" + process $proc$libresoc.v:166893$8929 + assign { } { } + assign $0\r_busy[0:0] \r_busy$next + sync posedge \coresync_clk + update \r_busy $0\r_busy[0:0] + end + attribute \src "libresoc.v:166933.3-166950.6" + process $proc$libresoc.v:166933$8930 + assign { } { } + assign { } { } + assign { } { } + assign $0\r_busy$next[0:0]$8931 $2\r_busy$next[0:0]$8933 + attribute \src "libresoc.v:166934.5-166934.29" + switch \initial + attribute \src "libresoc.v:166934.9-166934.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\r_busy$next[0:0]$8932 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\r_busy$next[0:0]$8932 1'0 + case + assign $1\r_busy$next[0:0]$8932 \r_busy + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r_busy$next[0:0]$8933 1'0 + case + assign $2\r_busy$next[0:0]$8933 $1\r_busy$next[0:0]$8932 + end + sync always + update \r_busy$next $0\r_busy$next[0:0]$8931 + end + attribute \src "libresoc.v:166951.3-166963.6" + process $proc$libresoc.v:166951$8934 + assign { } { } + assign { } { } + assign $0\muxid$1$next[1:0]$8935 $1\muxid$1$next[1:0]$8936 + attribute \src "libresoc.v:166952.5-166952.29" + switch \initial + attribute \src "libresoc.v:166952.9-166952.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\muxid$1$next[1:0]$8936 \muxid$24 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\muxid$1$next[1:0]$8936 \muxid$24 + case + assign $1\muxid$1$next[1:0]$8936 \muxid$1 + end + sync always + update \muxid$1$next $0\muxid$1$next[1:0]$8935 + end + attribute \src "libresoc.v:166964.3-166979.6" + process $proc$libresoc.v:166964$8937 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\spr_op__fn_unit$3$next[12:0]$8938 $1\spr_op__fn_unit$3$next[12:0]$8942 + assign $0\spr_op__insn$4$next[31:0]$8939 $1\spr_op__insn$4$next[31:0]$8943 + assign $0\spr_op__insn_type$2$next[6:0]$8940 $1\spr_op__insn_type$2$next[6:0]$8944 + assign $0\spr_op__is_32bit$5$next[0:0]$8941 $1\spr_op__is_32bit$5$next[0:0]$8945 + attribute \src "libresoc.v:166965.5-166965.29" + switch \initial + attribute \src "libresoc.v:166965.9-166965.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\spr_op__is_32bit$5$next[0:0]$8945 $1\spr_op__insn$4$next[31:0]$8943 $1\spr_op__fn_unit$3$next[12:0]$8942 $1\spr_op__insn_type$2$next[6:0]$8944 } { \spr_op__is_32bit$28 \spr_op__insn$27 \spr_op__fn_unit$26 \spr_op__insn_type$25 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\spr_op__is_32bit$5$next[0:0]$8945 $1\spr_op__insn$4$next[31:0]$8943 $1\spr_op__fn_unit$3$next[12:0]$8942 $1\spr_op__insn_type$2$next[6:0]$8944 } { \spr_op__is_32bit$28 \spr_op__insn$27 \spr_op__fn_unit$26 \spr_op__insn_type$25 } + case + assign $1\spr_op__fn_unit$3$next[12:0]$8942 \spr_op__fn_unit$3 + assign $1\spr_op__insn$4$next[31:0]$8943 \spr_op__insn$4 + assign $1\spr_op__insn_type$2$next[6:0]$8944 \spr_op__insn_type$2 + assign $1\spr_op__is_32bit$5$next[0:0]$8945 \spr_op__is_32bit$5 + end + sync always + update \spr_op__fn_unit$3$next $0\spr_op__fn_unit$3$next[12:0]$8938 + update \spr_op__insn$4$next $0\spr_op__insn$4$next[31:0]$8939 + update \spr_op__insn_type$2$next $0\spr_op__insn_type$2$next[6:0]$8940 + update \spr_op__is_32bit$5$next $0\spr_op__is_32bit$5$next[0:0]$8941 + end + attribute \src "libresoc.v:166980.3-166998.6" + process $proc$libresoc.v:166980$8946 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\o$next[63:0]$8947 $1\o$next[63:0]$8949 + assign { } { } + assign $0\o_ok$next[0:0]$8948 $2\o_ok$next[0:0]$8951 + attribute \src "libresoc.v:166981.5-166981.29" + switch \initial + attribute \src "libresoc.v:166981.9-166981.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\o_ok$next[0:0]$8950 $1\o$next[63:0]$8949 } { \o_ok$30 \o$29 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\o_ok$next[0:0]$8950 $1\o$next[63:0]$8949 } { \o_ok$30 \o$29 } + case + assign $1\o$next[63:0]$8949 \o + assign $1\o_ok$next[0:0]$8950 \o_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\o_ok$next[0:0]$8951 1'0 + case + assign $2\o_ok$next[0:0]$8951 $1\o_ok$next[0:0]$8950 + end + sync always + update \o$next $0\o$next[63:0]$8947 + update \o_ok$next $0\o_ok$next[0:0]$8948 + end + attribute \src "libresoc.v:166999.3-167017.6" + process $proc$libresoc.v:166999$8952 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\spr1$6$next[63:0]$8953 $1\spr1$6$next[63:0]$8955 + assign { } { } + assign $0\spr1_ok$next[0:0]$8954 $2\spr1_ok$next[0:0]$8957 + attribute \src "libresoc.v:167000.5-167000.29" + switch \initial + attribute \src "libresoc.v:167000.9-167000.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\spr1_ok$next[0:0]$8956 $1\spr1$6$next[63:0]$8955 } { \spr1_ok$32 \spr1$31 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\spr1_ok$next[0:0]$8956 $1\spr1$6$next[63:0]$8955 } { \spr1_ok$32 \spr1$31 } + case + assign $1\spr1$6$next[63:0]$8955 \spr1$6 + assign $1\spr1_ok$next[0:0]$8956 \spr1_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\spr1_ok$next[0:0]$8957 1'0 + case + assign $2\spr1_ok$next[0:0]$8957 $1\spr1_ok$next[0:0]$8956 + end + sync always + update \spr1$6$next $0\spr1$6$next[63:0]$8953 + update \spr1_ok$next $0\spr1_ok$next[0:0]$8954 + end + attribute \src "libresoc.v:167018.3-167036.6" + process $proc$libresoc.v:167018$8958 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\fast1$7$next[63:0]$8960 $1\fast1$7$next[63:0]$8962 + assign $0\fast1_ok$next[0:0]$8959 $2\fast1_ok$next[0:0]$8963 + attribute \src "libresoc.v:167019.5-167019.29" + switch \initial + attribute \src "libresoc.v:167019.9-167019.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\fast1_ok$next[0:0]$8961 $1\fast1$7$next[63:0]$8962 } { \fast1_ok$34 \fast1$33 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\fast1_ok$next[0:0]$8961 $1\fast1$7$next[63:0]$8962 } { \fast1_ok$34 \fast1$33 } + case + assign $1\fast1_ok$next[0:0]$8961 \fast1_ok + assign $1\fast1$7$next[63:0]$8962 \fast1$7 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\fast1_ok$next[0:0]$8963 1'0 + case + assign $2\fast1_ok$next[0:0]$8963 $1\fast1_ok$next[0:0]$8961 + end + sync always + update \fast1_ok$next $0\fast1_ok$next[0:0]$8959 + update \fast1$7$next $0\fast1$7$next[63:0]$8960 + end + attribute \src "libresoc.v:167037.3-167055.6" + process $proc$libresoc.v:167037$8964 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\xer_so$8$next[0:0]$8966 $1\xer_so$8$next[0:0]$8968 + assign $0\xer_so_ok$next[0:0]$8965 $2\xer_so_ok$next[0:0]$8969 + attribute \src "libresoc.v:167038.5-167038.29" + switch \initial + attribute \src "libresoc.v:167038.9-167038.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\xer_so_ok$next[0:0]$8967 $1\xer_so$8$next[0:0]$8968 } { \xer_so_ok$36 \xer_so$35 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\xer_so_ok$next[0:0]$8967 $1\xer_so$8$next[0:0]$8968 } { \xer_so_ok$36 \xer_so$35 } + case + assign $1\xer_so_ok$next[0:0]$8967 \xer_so_ok + assign $1\xer_so$8$next[0:0]$8968 \xer_so$8 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\xer_so_ok$next[0:0]$8969 1'0 + case + assign $2\xer_so_ok$next[0:0]$8969 $1\xer_so_ok$next[0:0]$8967 + end + sync always + update \xer_so_ok$next $0\xer_so_ok$next[0:0]$8965 + update \xer_so$8$next $0\xer_so$8$next[0:0]$8966 + end + attribute \src "libresoc.v:167056.3-167074.6" + process $proc$libresoc.v:167056$8970 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\xer_ov$9$next[1:0]$8972 $1\xer_ov$9$next[1:0]$8974 + assign $0\xer_ov_ok$next[0:0]$8971 $2\xer_ov_ok$next[0:0]$8975 + attribute \src "libresoc.v:167057.5-167057.29" + switch \initial + attribute \src "libresoc.v:167057.9-167057.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\xer_ov_ok$next[0:0]$8973 $1\xer_ov$9$next[1:0]$8974 } { \xer_ov_ok$38 \xer_ov$37 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\xer_ov_ok$next[0:0]$8973 $1\xer_ov$9$next[1:0]$8974 } { \xer_ov_ok$38 \xer_ov$37 } + case + assign $1\xer_ov_ok$next[0:0]$8973 \xer_ov_ok + assign $1\xer_ov$9$next[1:0]$8974 \xer_ov$9 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\xer_ov_ok$next[0:0]$8975 1'0 + case + assign $2\xer_ov_ok$next[0:0]$8975 $1\xer_ov_ok$next[0:0]$8973 + end + sync always + update \xer_ov_ok$next $0\xer_ov_ok$next[0:0]$8971 + update \xer_ov$9$next $0\xer_ov$9$next[1:0]$8972 + end + attribute \src "libresoc.v:167075.3-167093.6" + process $proc$libresoc.v:167075$8976 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\xer_ca$10$next[1:0]$8977 $1\xer_ca$10$next[1:0]$8979 + assign { } { } + assign $0\xer_ca_ok$next[0:0]$8978 $2\xer_ca_ok$next[0:0]$8981 + attribute \src "libresoc.v:167076.5-167076.29" + switch \initial + attribute \src "libresoc.v:167076.9-167076.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\xer_ca_ok$next[0:0]$8980 $1\xer_ca$10$next[1:0]$8979 } { \xer_ca_ok$40 \xer_ca$39 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\xer_ca_ok$next[0:0]$8980 $1\xer_ca$10$next[1:0]$8979 } { \xer_ca_ok$40 \xer_ca$39 } + case + assign $1\xer_ca$10$next[1:0]$8979 \xer_ca$10 + assign $1\xer_ca_ok$next[0:0]$8980 \xer_ca_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\xer_ca_ok$next[0:0]$8981 1'0 + case + assign $2\xer_ca_ok$next[0:0]$8981 $1\xer_ca_ok$next[0:0]$8980 + end + sync always + update \xer_ca$10$next $0\xer_ca$10$next[1:0]$8977 + update \xer_ca_ok$next $0\xer_ca_ok$next[0:0]$8978 + end + connect \$22 $and$libresoc.v:166858$8901_Y + connect \p_ready_o \n_i_rdy_data + connect \n_valid_o \r_busy + connect { \xer_ca_ok$40 \xer_ca$39 } { \spr_main_xer_ca_ok \spr_main_xer_ca$20 } + connect { \xer_ov_ok$38 \xer_ov$37 } { \spr_main_xer_ov_ok \spr_main_xer_ov$19 } + connect { \xer_so_ok$36 \xer_so$35 } { \spr_main_xer_so_ok \spr_main_xer_so$18 } + connect { \fast1_ok$34 \fast1$33 } { \spr_main_fast1_ok \spr_main_fast1$17 } + connect { \spr1_ok$32 \spr1$31 } { \spr_main_spr1_ok \spr_main_spr1$16 } + connect { \o_ok$30 \o$29 } { \spr_main_o_ok \spr_main_o } + connect { \spr_op__is_32bit$28 \spr_op__insn$27 \spr_op__fn_unit$26 \spr_op__insn_type$25 } { \spr_main_spr_op__is_32bit$15 \spr_main_spr_op__insn$14 \spr_main_spr_op__fn_unit$13 \spr_main_spr_op__insn_type$12 } + connect \muxid$24 \spr_main_muxid$11 + connect \p_valid_i_p_ready_o \$22 + connect \n_i_rdy_data \n_ready_i + connect \p_valid_i$21 \p_valid_i + connect \spr_main_xer_ca \xer_ca + connect \spr_main_xer_ov \xer_ov + connect \spr_main_xer_so \xer_so + connect \spr_main_fast1 \fast1 + connect \spr_main_spr1 \spr1 + connect \spr_main_ra \ra + connect { \spr_main_spr_op__is_32bit \spr_main_spr_op__insn \spr_main_spr_op__fn_unit \spr_main_spr_op__insn_type } { \spr_op__is_32bit \spr_op__insn \spr_op__fn_unit \spr_op__insn_type } + connect \spr_main_muxid \muxid +end +attribute \src "libresoc.v:167119.1-168597.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe1" +attribute \generator "nMigen" +module \pipe1 + attribute \src "libresoc.v:168511.3-168552.6" + wire width 4 $0\alu_op__data_len$next[3:0]$9074 + attribute \src "libresoc.v:168287.3-168288.49" + wire width 4 $0\alu_op__data_len[3:0] + attribute \src "libresoc.v:168511.3-168552.6" + wire width 13 $0\alu_op__fn_unit$next[12:0]$9075 + attribute \src "libresoc.v:168257.3-168258.47" + wire width 13 $0\alu_op__fn_unit[12:0] + attribute \src "libresoc.v:168511.3-168552.6" + wire width 64 $0\alu_op__imm_data__data$next[63:0]$9076 + attribute \src "libresoc.v:168259.3-168260.61" + wire width 64 $0\alu_op__imm_data__data[63:0] + attribute \src "libresoc.v:168511.3-168552.6" + wire $0\alu_op__imm_data__ok$next[0:0]$9077 + attribute \src "libresoc.v:168261.3-168262.57" + wire $0\alu_op__imm_data__ok[0:0] + attribute \src "libresoc.v:168511.3-168552.6" + wire width 2 $0\alu_op__input_carry$next[1:0]$9078 + attribute \src "libresoc.v:168279.3-168280.55" + wire width 2 $0\alu_op__input_carry[1:0] + attribute \src "libresoc.v:168511.3-168552.6" + wire width 32 $0\alu_op__insn$next[31:0]$9079 + attribute \src "libresoc.v:168289.3-168290.41" + wire width 32 $0\alu_op__insn[31:0] + attribute \src "libresoc.v:168511.3-168552.6" + wire width 7 $0\alu_op__insn_type$next[6:0]$9080 + attribute \src "libresoc.v:168255.3-168256.51" + wire width 7 $0\alu_op__insn_type[6:0] + attribute \src "libresoc.v:168511.3-168552.6" + wire $0\alu_op__invert_in$next[0:0]$9081 + attribute \src "libresoc.v:168271.3-168272.51" + wire $0\alu_op__invert_in[0:0] + attribute \src "libresoc.v:168511.3-168552.6" + wire $0\alu_op__invert_out$next[0:0]$9082 + attribute \src "libresoc.v:168275.3-168276.53" + wire $0\alu_op__invert_out[0:0] + attribute \src "libresoc.v:168511.3-168552.6" + wire $0\alu_op__is_32bit$next[0:0]$9083 + attribute \src "libresoc.v:168283.3-168284.49" + wire $0\alu_op__is_32bit[0:0] + attribute \src "libresoc.v:168511.3-168552.6" + wire $0\alu_op__is_signed$next[0:0]$9084 + attribute \src "libresoc.v:168285.3-168286.51" + wire $0\alu_op__is_signed[0:0] + attribute \src "libresoc.v:168511.3-168552.6" + wire $0\alu_op__oe__oe$next[0:0]$9085 + attribute \src "libresoc.v:168267.3-168268.45" + wire $0\alu_op__oe__oe[0:0] + attribute \src "libresoc.v:168511.3-168552.6" + wire $0\alu_op__oe__ok$next[0:0]$9086 + attribute \src "libresoc.v:168269.3-168270.45" + wire $0\alu_op__oe__ok[0:0] + attribute \src "libresoc.v:168511.3-168552.6" + wire $0\alu_op__output_carry$next[0:0]$9087 + attribute \src "libresoc.v:168281.3-168282.57" + wire $0\alu_op__output_carry[0:0] + attribute \src "libresoc.v:168511.3-168552.6" + wire $0\alu_op__rc__ok$next[0:0]$9088 + attribute \src "libresoc.v:168265.3-168266.45" + wire $0\alu_op__rc__ok[0:0] + attribute \src "libresoc.v:168511.3-168552.6" + wire $0\alu_op__rc__rc$next[0:0]$9089 + attribute \src "libresoc.v:168263.3-168264.45" + wire $0\alu_op__rc__rc[0:0] + attribute \src "libresoc.v:168511.3-168552.6" + wire $0\alu_op__write_cr0$next[0:0]$9090 + attribute \src "libresoc.v:168277.3-168278.51" + wire $0\alu_op__write_cr0[0:0] + attribute \src "libresoc.v:168511.3-168552.6" + wire $0\alu_op__zero_a$next[0:0]$9091 + attribute \src "libresoc.v:168273.3-168274.45" + wire $0\alu_op__zero_a[0:0] + attribute \src "libresoc.v:168404.3-168422.6" + wire width 4 $0\cr_a$next[3:0]$9043 + attribute \src "libresoc.v:168247.3-168248.25" + wire width 4 $0\cr_a[3:0] + attribute \src "libresoc.v:168404.3-168422.6" + wire $0\cr_a_ok$next[0:0]$9044 + attribute \src "libresoc.v:168249.3-168250.31" + wire $0\cr_a_ok[0:0] + attribute \src "libresoc.v:167120.7-167120.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:168498.3-168510.6" + wire width 2 $0\muxid$next[1:0]$9071 + attribute \src "libresoc.v:168291.3-168292.27" + wire width 2 $0\muxid[1:0] + attribute \src "libresoc.v:168553.3-168571.6" + wire width 64 $0\o$next[63:0]$9117 + attribute \src "libresoc.v:168251.3-168252.19" + wire width 64 $0\o[63:0] + attribute \src "libresoc.v:168553.3-168571.6" + wire $0\o_ok$next[0:0]$9118 + attribute \src "libresoc.v:168253.3-168254.25" + wire $0\o_ok[0:0] + attribute \src "libresoc.v:168480.3-168497.6" + wire $0\r_busy$next[0:0]$9067 + attribute \src "libresoc.v:168293.3-168294.29" + wire $0\r_busy[0:0] + attribute \src "libresoc.v:168423.3-168441.6" + wire width 2 $0\xer_ca$next[1:0]$9050 + attribute \src "libresoc.v:168243.3-168244.29" + wire width 2 $0\xer_ca[1:0] + attribute \src "libresoc.v:168423.3-168441.6" + wire $0\xer_ca_ok$next[0:0]$9049 + attribute \src "libresoc.v:168245.3-168246.35" + wire $0\xer_ca_ok[0:0] + attribute \src "libresoc.v:168442.3-168460.6" + wire width 2 $0\xer_ov$next[1:0]$9055 + attribute \src "libresoc.v:168239.3-168240.29" + wire width 2 $0\xer_ov[1:0] + attribute \src "libresoc.v:168442.3-168460.6" + wire $0\xer_ov_ok$next[0:0]$9056 + attribute \src "libresoc.v:168241.3-168242.35" + wire $0\xer_ov_ok[0:0] + attribute \src "libresoc.v:168461.3-168479.6" + wire $0\xer_so$next[0:0]$9061 + attribute \src "libresoc.v:168235.3-168236.29" + wire $0\xer_so[0:0] + attribute \src "libresoc.v:168461.3-168479.6" + wire $0\xer_so_ok$next[0:0]$9062 + attribute \src "libresoc.v:168237.3-168238.35" + wire $0\xer_so_ok[0:0] + attribute \src "libresoc.v:168511.3-168552.6" + wire width 4 $1\alu_op__data_len$next[3:0]$9092 + attribute \src "libresoc.v:167125.13-167125.36" + wire width 4 $1\alu_op__data_len[3:0] + attribute \src "libresoc.v:168511.3-168552.6" + wire width 13 $1\alu_op__fn_unit$next[12:0]$9093 + attribute \src "libresoc.v:167148.14-167148.40" + wire width 13 $1\alu_op__fn_unit[12:0] + attribute \src "libresoc.v:168511.3-168552.6" + wire width 64 $1\alu_op__imm_data__data$next[63:0]$9094 + attribute \src "libresoc.v:167185.14-167185.59" + wire width 64 $1\alu_op__imm_data__data[63:0] + attribute \src "libresoc.v:168511.3-168552.6" + wire $1\alu_op__imm_data__ok$next[0:0]$9095 + attribute \src "libresoc.v:167194.7-167194.34" + wire $1\alu_op__imm_data__ok[0:0] + attribute \src "libresoc.v:168511.3-168552.6" + wire width 2 $1\alu_op__input_carry$next[1:0]$9096 + attribute \src "libresoc.v:167207.13-167207.39" + wire width 2 $1\alu_op__input_carry[1:0] + attribute \src "libresoc.v:168511.3-168552.6" + wire width 32 $1\alu_op__insn$next[31:0]$9097 + attribute \src "libresoc.v:167224.14-167224.34" + wire width 32 $1\alu_op__insn[31:0] + attribute \src "libresoc.v:168511.3-168552.6" + wire width 7 $1\alu_op__insn_type$next[6:0]$9098 + attribute \src "libresoc.v:167307.13-167307.38" + wire width 7 $1\alu_op__insn_type[6:0] + attribute \src "libresoc.v:168511.3-168552.6" + wire $1\alu_op__invert_in$next[0:0]$9099 + attribute \src "libresoc.v:167464.7-167464.31" + wire $1\alu_op__invert_in[0:0] + attribute \src "libresoc.v:168511.3-168552.6" + wire $1\alu_op__invert_out$next[0:0]$9100 + attribute \src "libresoc.v:167473.7-167473.32" + wire $1\alu_op__invert_out[0:0] + attribute \src "libresoc.v:168511.3-168552.6" + wire $1\alu_op__is_32bit$next[0:0]$9101 + attribute \src "libresoc.v:167482.7-167482.30" + wire $1\alu_op__is_32bit[0:0] + attribute \src "libresoc.v:168511.3-168552.6" + wire $1\alu_op__is_signed$next[0:0]$9102 + attribute \src "libresoc.v:167491.7-167491.31" + wire $1\alu_op__is_signed[0:0] + attribute \src "libresoc.v:168511.3-168552.6" + wire $1\alu_op__oe__oe$next[0:0]$9103 + attribute \src "libresoc.v:167500.7-167500.28" + wire $1\alu_op__oe__oe[0:0] + attribute \src "libresoc.v:168511.3-168552.6" + wire $1\alu_op__oe__ok$next[0:0]$9104 + attribute \src "libresoc.v:167509.7-167509.28" + wire $1\alu_op__oe__ok[0:0] + attribute \src "libresoc.v:168511.3-168552.6" + wire $1\alu_op__output_carry$next[0:0]$9105 + attribute \src "libresoc.v:167518.7-167518.34" + wire $1\alu_op__output_carry[0:0] + attribute \src "libresoc.v:168511.3-168552.6" + wire $1\alu_op__rc__ok$next[0:0]$9106 + attribute \src "libresoc.v:167527.7-167527.28" + wire $1\alu_op__rc__ok[0:0] + attribute \src "libresoc.v:168511.3-168552.6" + wire $1\alu_op__rc__rc$next[0:0]$9107 + attribute \src "libresoc.v:167536.7-167536.28" + wire $1\alu_op__rc__rc[0:0] + attribute \src "libresoc.v:168511.3-168552.6" + wire $1\alu_op__write_cr0$next[0:0]$9108 + attribute \src "libresoc.v:167545.7-167545.31" + wire $1\alu_op__write_cr0[0:0] + attribute \src "libresoc.v:168511.3-168552.6" + wire $1\alu_op__zero_a$next[0:0]$9109 + attribute \src "libresoc.v:167554.7-167554.28" + wire $1\alu_op__zero_a[0:0] + attribute \src "libresoc.v:168404.3-168422.6" + wire width 4 $1\cr_a$next[3:0]$9045 + attribute \src "libresoc.v:167567.13-167567.24" + wire width 4 $1\cr_a[3:0] + attribute \src "libresoc.v:168404.3-168422.6" + wire $1\cr_a_ok$next[0:0]$9046 + attribute \src "libresoc.v:167574.7-167574.21" + wire $1\cr_a_ok[0:0] + attribute \src "libresoc.v:168498.3-168510.6" + wire width 2 $1\muxid$next[1:0]$9072 + attribute \src "libresoc.v:168143.13-168143.25" + wire width 2 $1\muxid[1:0] + attribute \src "libresoc.v:168553.3-168571.6" + wire width 64 $1\o$next[63:0]$9119 + attribute \src "libresoc.v:168158.14-168158.38" + wire width 64 $1\o[63:0] + attribute \src "libresoc.v:168553.3-168571.6" + wire $1\o_ok$next[0:0]$9120 + attribute \src "libresoc.v:168165.7-168165.18" + wire $1\o_ok[0:0] + attribute \src "libresoc.v:168480.3-168497.6" + wire $1\r_busy$next[0:0]$9068 + attribute \src "libresoc.v:168179.7-168179.20" + wire $1\r_busy[0:0] + attribute \src "libresoc.v:168423.3-168441.6" + wire width 2 $1\xer_ca$next[1:0]$9052 + attribute \src "libresoc.v:168188.13-168188.26" + wire width 2 $1\xer_ca[1:0] + attribute \src "libresoc.v:168423.3-168441.6" + wire $1\xer_ca_ok$next[0:0]$9051 + attribute \src "libresoc.v:168197.7-168197.23" + wire $1\xer_ca_ok[0:0] + attribute \src "libresoc.v:168442.3-168460.6" + wire width 2 $1\xer_ov$next[1:0]$9057 + attribute \src "libresoc.v:168204.13-168204.26" + wire width 2 $1\xer_ov[1:0] + attribute \src "libresoc.v:168442.3-168460.6" + wire $1\xer_ov_ok$next[0:0]$9058 + attribute \src "libresoc.v:168211.7-168211.23" + wire $1\xer_ov_ok[0:0] + attribute \src "libresoc.v:168461.3-168479.6" + wire $1\xer_so$next[0:0]$9063 + attribute \src "libresoc.v:168218.7-168218.20" + wire $1\xer_so[0:0] + attribute \src "libresoc.v:168461.3-168479.6" + wire $1\xer_so_ok$next[0:0]$9064 + attribute \src "libresoc.v:168227.7-168227.23" + wire $1\xer_so_ok[0:0] + attribute \src "libresoc.v:168511.3-168552.6" + wire width 64 $2\alu_op__imm_data__data$next[63:0]$9110 + attribute \src "libresoc.v:168511.3-168552.6" + wire $2\alu_op__imm_data__ok$next[0:0]$9111 + attribute \src "libresoc.v:168511.3-168552.6" + wire $2\alu_op__oe__oe$next[0:0]$9112 + attribute \src "libresoc.v:168511.3-168552.6" + wire $2\alu_op__oe__ok$next[0:0]$9113 + attribute \src "libresoc.v:168511.3-168552.6" + wire $2\alu_op__rc__ok$next[0:0]$9114 + attribute \src "libresoc.v:168511.3-168552.6" + wire $2\alu_op__rc__rc$next[0:0]$9115 + attribute \src "libresoc.v:168404.3-168422.6" + wire $2\cr_a_ok$next[0:0]$9047 + attribute \src "libresoc.v:168553.3-168571.6" + wire $2\o_ok$next[0:0]$9121 + attribute \src "libresoc.v:168480.3-168497.6" + wire $2\r_busy$next[0:0]$9069 + attribute \src "libresoc.v:168423.3-168441.6" + wire $2\xer_ca_ok$next[0:0]$9053 + attribute \src "libresoc.v:168442.3-168460.6" + wire $2\xer_ov_ok$next[0:0]$9059 + attribute \src "libresoc.v:168461.3-168479.6" + wire $2\xer_so_ok$next[0:0]$9065 + attribute \src "libresoc.v:168234.18-168234.118" + wire $and$libresoc.v:168234$9011_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" + wire \$67 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 21 \alu_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 52 \alu_op__data_len$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \alu_op__data_len$86 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \alu_op__data_len$next + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 output 6 \alu_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 input 37 \alu_op__fn_unit$3 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \alu_op__fn_unit$71 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \alu_op__fn_unit$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 7 \alu_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 38 \alu_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \alu_op__imm_data__data$72 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \alu_op__imm_data__data$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 8 \alu_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 39 \alu_op__imm_data__ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__imm_data__ok$73 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__imm_data__ok$next + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 17 \alu_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 48 \alu_op__input_carry$14 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \alu_op__input_carry$82 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \alu_op__input_carry$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 22 \alu_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 53 \alu_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \alu_op__insn$87 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \alu_op__insn$next + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 5 \alu_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 36 \alu_op__insn_type$2 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \alu_op__insn_type$70 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \alu_op__insn_type$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 13 \alu_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 44 \alu_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__invert_in$78 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__invert_in$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 15 \alu_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 46 \alu_op__invert_out$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__invert_out$80 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__invert_out$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 19 \alu_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 50 \alu_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__is_32bit$84 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__is_32bit$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 20 \alu_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 51 \alu_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__is_signed$85 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__is_signed$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 11 \alu_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__oe__oe$76 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 42 \alu_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__oe__oe$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 12 \alu_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__oe__ok$77 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 43 \alu_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__oe__ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 18 \alu_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 49 \alu_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__output_carry$83 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__output_carry$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 10 \alu_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 41 \alu_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__rc__ok$75 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__rc__ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 9 \alu_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 40 \alu_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__rc__rc$74 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__rc__rc$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 16 \alu_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 47 \alu_op__write_cr0$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__write_cr0$81 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__write_cr0$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 14 \alu_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 45 \alu_op__zero_a$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__zero_a$79 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__zero_a$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 58 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 output 25 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \cr_a$90 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \cr_a$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 26 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_a_ok$91 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_a_ok$next + attribute \src "libresoc.v:167120.7-167120.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \input_alu_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \input_alu_op__data_len$39 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \input_alu_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \input_alu_op__fn_unit$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \input_alu_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \input_alu_op__imm_data__data$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__imm_data__ok$26 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \input_alu_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \input_alu_op__input_carry$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \input_alu_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \input_alu_op__insn$40 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \input_alu_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \input_alu_op__insn_type$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__invert_in$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__invert_out$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__is_32bit$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__is_signed$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__oe__oe$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__oe__ok$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__output_carry$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__rc__ok$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__rc__rc$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__write_cr0$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__zero_a$32 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \input_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \input_muxid$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_ra$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_rb$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 \input_xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 \input_xer_ca$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \input_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \input_xer_so$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \main_alu_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \main_alu_op__data_len$62 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \main_alu_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \main_alu_op__fn_unit$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \main_alu_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \main_alu_op__imm_data__data$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_alu_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_alu_op__imm_data__ok$49 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \main_alu_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \main_alu_op__input_carry$58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \main_alu_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \main_alu_op__insn$63 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 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\enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \main_alu_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute 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\main_alu_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_alu_op__is_32bit$60 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_alu_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_alu_op__is_signed$61 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_alu_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_alu_op__oe__oe$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_alu_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_alu_op__oe__ok$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_alu_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_alu_op__output_carry$59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_alu_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_alu_op__rc__ok$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_alu_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_alu_op__rc__rc$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_alu_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_alu_op__write_cr0$57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_alu_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_alu_op__zero_a$55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \main_cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \main_cr_a_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \main_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \main_muxid$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \main_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \main_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \main_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \main_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 \main_xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \main_xer_ca$64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \main_xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \main_xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \main_xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \main_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \main_xer_so$65 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 output 4 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 input 35 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid$69 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + wire \n_i_rdy_data + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire input 3 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire output 2 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 23 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \o$88 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \o$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 24 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \o_ok$89 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \o_ok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" + wire output 34 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" + wire input 33 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" + wire \p_valid_i$66 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" + wire \p_valid_i_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire \r_busy$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 54 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 55 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 output 27 \xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 input 57 \xer_ca$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \xer_ca$92 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \xer_ca$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 28 \xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_ca_ok$93 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_ca_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 output 29 \xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \xer_ov$94 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \xer_ov$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 30 \xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_ov_ok$95 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_ov_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 31 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 56 \xer_so$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so$96 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 32 \xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so_ok$97 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so_ok$98 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so_ok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" + cell $and $and$libresoc.v:168234$9011 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i$66 + connect \B \p_ready_o + connect \Y $and$libresoc.v:168234$9011_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:168295.11-168342.4" + cell \input \input + connect \alu_op__data_len \input_alu_op__data_len + connect \alu_op__data_len$18 \input_alu_op__data_len$39 + connect \alu_op__fn_unit \input_alu_op__fn_unit + connect \alu_op__fn_unit$3 \input_alu_op__fn_unit$24 + connect \alu_op__imm_data__data \input_alu_op__imm_data__data + connect \alu_op__imm_data__data$4 \input_alu_op__imm_data__data$25 + connect \alu_op__imm_data__ok \input_alu_op__imm_data__ok + connect \alu_op__imm_data__ok$5 \input_alu_op__imm_data__ok$26 + connect \alu_op__input_carry \input_alu_op__input_carry + connect \alu_op__input_carry$14 \input_alu_op__input_carry$35 + connect \alu_op__insn \input_alu_op__insn + connect \alu_op__insn$19 \input_alu_op__insn$40 + connect \alu_op__insn_type \input_alu_op__insn_type + connect \alu_op__insn_type$2 \input_alu_op__insn_type$23 + connect \alu_op__invert_in \input_alu_op__invert_in + connect \alu_op__invert_in$10 \input_alu_op__invert_in$31 + connect \alu_op__invert_out \input_alu_op__invert_out + connect \alu_op__invert_out$12 \input_alu_op__invert_out$33 + connect \alu_op__is_32bit \input_alu_op__is_32bit + connect \alu_op__is_32bit$16 \input_alu_op__is_32bit$37 + connect \alu_op__is_signed \input_alu_op__is_signed + connect \alu_op__is_signed$17 \input_alu_op__is_signed$38 + connect \alu_op__oe__oe \input_alu_op__oe__oe + connect \alu_op__oe__oe$8 \input_alu_op__oe__oe$29 + connect \alu_op__oe__ok \input_alu_op__oe__ok + connect \alu_op__oe__ok$9 \input_alu_op__oe__ok$30 + connect \alu_op__output_carry \input_alu_op__output_carry + connect \alu_op__output_carry$15 \input_alu_op__output_carry$36 + connect \alu_op__rc__ok \input_alu_op__rc__ok + connect \alu_op__rc__ok$7 \input_alu_op__rc__ok$28 + connect \alu_op__rc__rc \input_alu_op__rc__rc + connect \alu_op__rc__rc$6 \input_alu_op__rc__rc$27 + connect \alu_op__write_cr0 \input_alu_op__write_cr0 + connect \alu_op__write_cr0$13 \input_alu_op__write_cr0$34 + connect \alu_op__zero_a \input_alu_op__zero_a + connect \alu_op__zero_a$11 \input_alu_op__zero_a$32 + connect \muxid \input_muxid + connect \muxid$1 \input_muxid$22 + connect \ra \input_ra + connect \ra$20 \input_ra$41 + connect \rb \input_rb + connect \rb$21 \input_rb$42 + connect \xer_ca \input_xer_ca + connect \xer_ca$23 \input_xer_ca$44 + connect \xer_so \input_xer_so + connect \xer_so$22 \input_xer_so$43 + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:168343.8-168395.4" + cell \main \main + connect \alu_op__data_len \main_alu_op__data_len + connect \alu_op__data_len$18 \main_alu_op__data_len$62 + connect \alu_op__fn_unit \main_alu_op__fn_unit + connect \alu_op__fn_unit$3 \main_alu_op__fn_unit$47 + connect \alu_op__imm_data__data \main_alu_op__imm_data__data + connect \alu_op__imm_data__data$4 \main_alu_op__imm_data__data$48 + connect \alu_op__imm_data__ok \main_alu_op__imm_data__ok + connect \alu_op__imm_data__ok$5 \main_alu_op__imm_data__ok$49 + connect \alu_op__input_carry \main_alu_op__input_carry + connect \alu_op__input_carry$14 \main_alu_op__input_carry$58 + connect \alu_op__insn \main_alu_op__insn + connect \alu_op__insn$19 \main_alu_op__insn$63 + connect \alu_op__insn_type \main_alu_op__insn_type + connect \alu_op__insn_type$2 \main_alu_op__insn_type$46 + connect \alu_op__invert_in \main_alu_op__invert_in + connect \alu_op__invert_in$10 \main_alu_op__invert_in$54 + connect \alu_op__invert_out \main_alu_op__invert_out + connect \alu_op__invert_out$12 \main_alu_op__invert_out$56 + connect \alu_op__is_32bit \main_alu_op__is_32bit + connect \alu_op__is_32bit$16 \main_alu_op__is_32bit$60 + connect \alu_op__is_signed \main_alu_op__is_signed + connect \alu_op__is_signed$17 \main_alu_op__is_signed$61 + connect \alu_op__oe__oe \main_alu_op__oe__oe + connect \alu_op__oe__oe$8 \main_alu_op__oe__oe$52 + connect \alu_op__oe__ok \main_alu_op__oe__ok + connect \alu_op__oe__ok$9 \main_alu_op__oe__ok$53 + connect \alu_op__output_carry \main_alu_op__output_carry + connect \alu_op__output_carry$15 \main_alu_op__output_carry$59 + connect \alu_op__rc__ok \main_alu_op__rc__ok + connect \alu_op__rc__ok$7 \main_alu_op__rc__ok$51 + connect \alu_op__rc__rc \main_alu_op__rc__rc + connect \alu_op__rc__rc$6 \main_alu_op__rc__rc$50 + connect \alu_op__write_cr0 \main_alu_op__write_cr0 + connect \alu_op__write_cr0$13 \main_alu_op__write_cr0$57 + connect \alu_op__zero_a \main_alu_op__zero_a + connect \alu_op__zero_a$11 \main_alu_op__zero_a$55 + connect \cr_a \main_cr_a + connect \cr_a_ok \main_cr_a_ok + connect \muxid \main_muxid + connect \muxid$1 \main_muxid$45 + connect \o \main_o + connect \o_ok \main_o_ok + connect \ra \main_ra + connect \rb \main_rb + connect \xer_ca \main_xer_ca + connect \xer_ca$20 \main_xer_ca$64 + connect \xer_ca_ok \main_xer_ca_ok + connect \xer_ov \main_xer_ov + connect \xer_ov_ok \main_xer_ov_ok + connect \xer_so \main_xer_so + connect \xer_so$21 \main_xer_so$65 + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:168396.9-168399.4" + cell \n$2 \n + connect \n_ready_i \n_ready_i + connect \n_valid_o \n_valid_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:168400.9-168403.4" + cell \p$1 \p + connect \p_ready_o \p_ready_o + connect \p_valid_i \p_valid_i + end + attribute \src "libresoc.v:167120.7-167120.20" + process $proc$libresoc.v:167120$9122 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:167125.13-167125.36" + process $proc$libresoc.v:167125$9123 + assign { } { } + assign $1\alu_op__data_len[3:0] 4'0000 + sync always + sync init + update \alu_op__data_len $1\alu_op__data_len[3:0] + end + attribute \src "libresoc.v:167148.14-167148.40" + process $proc$libresoc.v:167148$9124 + assign { } { } + assign $1\alu_op__fn_unit[12:0] 13'0000000000000 + sync always + sync init + update \alu_op__fn_unit $1\alu_op__fn_unit[12:0] + end + attribute \src "libresoc.v:167185.14-167185.59" + process $proc$libresoc.v:167185$9125 + assign { } { } + assign $1\alu_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \alu_op__imm_data__data $1\alu_op__imm_data__data[63:0] + end + attribute \src "libresoc.v:167194.7-167194.34" + process $proc$libresoc.v:167194$9126 + assign { } { } + assign $1\alu_op__imm_data__ok[0:0] 1'0 + sync always + sync init + update \alu_op__imm_data__ok $1\alu_op__imm_data__ok[0:0] + end + attribute \src "libresoc.v:167207.13-167207.39" + process $proc$libresoc.v:167207$9127 + assign { } { } + assign $1\alu_op__input_carry[1:0] 2'00 + sync always + sync init + update \alu_op__input_carry $1\alu_op__input_carry[1:0] + end + attribute \src "libresoc.v:167224.14-167224.34" + process $proc$libresoc.v:167224$9128 + assign { } { } + assign $1\alu_op__insn[31:0] 0 + sync always + sync init + update \alu_op__insn $1\alu_op__insn[31:0] + end + attribute \src "libresoc.v:167307.13-167307.38" + process $proc$libresoc.v:167307$9129 + assign { } { } + assign $1\alu_op__insn_type[6:0] 7'0000000 + sync always + sync init + update \alu_op__insn_type $1\alu_op__insn_type[6:0] + end + attribute \src "libresoc.v:167464.7-167464.31" + process $proc$libresoc.v:167464$9130 + assign { } { } + assign $1\alu_op__invert_in[0:0] 1'0 + sync always + sync init + update \alu_op__invert_in $1\alu_op__invert_in[0:0] + end + attribute \src "libresoc.v:167473.7-167473.32" + process $proc$libresoc.v:167473$9131 + assign { } { } + assign $1\alu_op__invert_out[0:0] 1'0 + sync always + sync init + update \alu_op__invert_out $1\alu_op__invert_out[0:0] + end + attribute \src "libresoc.v:167482.7-167482.30" + process $proc$libresoc.v:167482$9132 + assign { } { } + assign $1\alu_op__is_32bit[0:0] 1'0 + sync always + sync init + update \alu_op__is_32bit $1\alu_op__is_32bit[0:0] + end + attribute \src "libresoc.v:167491.7-167491.31" + process $proc$libresoc.v:167491$9133 + assign { } { } + assign $1\alu_op__is_signed[0:0] 1'0 + sync always + sync init + update \alu_op__is_signed $1\alu_op__is_signed[0:0] + end + attribute \src "libresoc.v:167500.7-167500.28" + process $proc$libresoc.v:167500$9134 + assign { } { } + assign $1\alu_op__oe__oe[0:0] 1'0 + sync always + sync init + update \alu_op__oe__oe $1\alu_op__oe__oe[0:0] + end + attribute \src "libresoc.v:167509.7-167509.28" + process $proc$libresoc.v:167509$9135 + assign { } { } + assign $1\alu_op__oe__ok[0:0] 1'0 + sync always + sync init + update \alu_op__oe__ok $1\alu_op__oe__ok[0:0] + end + attribute \src "libresoc.v:167518.7-167518.34" + process $proc$libresoc.v:167518$9136 + assign { } { } + assign $1\alu_op__output_carry[0:0] 1'0 + sync always + sync init + update \alu_op__output_carry $1\alu_op__output_carry[0:0] + end + attribute \src "libresoc.v:167527.7-167527.28" + process $proc$libresoc.v:167527$9137 + assign { } { } + assign $1\alu_op__rc__ok[0:0] 1'0 + sync always + sync init + update \alu_op__rc__ok $1\alu_op__rc__ok[0:0] + end + attribute \src "libresoc.v:167536.7-167536.28" + process $proc$libresoc.v:167536$9138 + assign { } { } + assign $1\alu_op__rc__rc[0:0] 1'0 + sync always + sync init + update \alu_op__rc__rc $1\alu_op__rc__rc[0:0] + end + attribute \src "libresoc.v:167545.7-167545.31" + process $proc$libresoc.v:167545$9139 + assign { } { } + assign $1\alu_op__write_cr0[0:0] 1'0 + sync always + sync init + update \alu_op__write_cr0 $1\alu_op__write_cr0[0:0] + end + attribute \src "libresoc.v:167554.7-167554.28" + process $proc$libresoc.v:167554$9140 + assign { } { } + assign $1\alu_op__zero_a[0:0] 1'0 + sync always + sync init + update \alu_op__zero_a $1\alu_op__zero_a[0:0] + end + attribute \src "libresoc.v:167567.13-167567.24" + process $proc$libresoc.v:167567$9141 + assign { } { } + assign $1\cr_a[3:0] 4'0000 + sync always + sync init + update \cr_a $1\cr_a[3:0] + end + attribute \src "libresoc.v:167574.7-167574.21" + process $proc$libresoc.v:167574$9142 + assign { } { } + assign $1\cr_a_ok[0:0] 1'0 + sync always + sync init + update \cr_a_ok $1\cr_a_ok[0:0] + end + attribute \src "libresoc.v:168143.13-168143.25" + process $proc$libresoc.v:168143$9143 + assign { } { } + assign $1\muxid[1:0] 2'00 + sync always + sync init + update \muxid $1\muxid[1:0] + end + attribute \src "libresoc.v:168158.14-168158.38" + process $proc$libresoc.v:168158$9144 + assign { } { } + assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \o $1\o[63:0] + end + attribute \src "libresoc.v:168165.7-168165.18" + process $proc$libresoc.v:168165$9145 + assign { } { } + assign $1\o_ok[0:0] 1'0 + sync always + sync init + update \o_ok $1\o_ok[0:0] + end + attribute \src "libresoc.v:168179.7-168179.20" + process $proc$libresoc.v:168179$9146 + assign { } { } + assign $1\r_busy[0:0] 1'0 + sync always + sync init + update \r_busy $1\r_busy[0:0] + end + attribute \src "libresoc.v:168188.13-168188.26" + process $proc$libresoc.v:168188$9147 + assign { } { } + assign $1\xer_ca[1:0] 2'00 + sync always + sync init + update \xer_ca $1\xer_ca[1:0] + end + attribute \src "libresoc.v:168197.7-168197.23" + process $proc$libresoc.v:168197$9148 + assign { } { } + assign $1\xer_ca_ok[0:0] 1'0 + sync always + sync init + update \xer_ca_ok $1\xer_ca_ok[0:0] + end + attribute \src "libresoc.v:168204.13-168204.26" + process $proc$libresoc.v:168204$9149 + assign { } { } + assign $1\xer_ov[1:0] 2'00 + sync always + sync init + update \xer_ov $1\xer_ov[1:0] + end + attribute \src "libresoc.v:168211.7-168211.23" + process $proc$libresoc.v:168211$9150 + assign { } { } + assign $1\xer_ov_ok[0:0] 1'0 + sync always + sync init + update \xer_ov_ok $1\xer_ov_ok[0:0] + end + attribute \src "libresoc.v:168218.7-168218.20" + process $proc$libresoc.v:168218$9151 + assign { } { } + assign $1\xer_so[0:0] 1'0 + sync always + sync init + update \xer_so $1\xer_so[0:0] + end + attribute \src "libresoc.v:168227.7-168227.23" + process $proc$libresoc.v:168227$9152 + assign { } { } + assign $1\xer_so_ok[0:0] 1'0 + sync always + sync init + update \xer_so_ok $1\xer_so_ok[0:0] + end + attribute \src "libresoc.v:168235.3-168236.29" + process $proc$libresoc.v:168235$9012 + assign { } { } + assign $0\xer_so[0:0] \xer_so$next + sync posedge \coresync_clk + update \xer_so $0\xer_so[0:0] + end + attribute \src "libresoc.v:168237.3-168238.35" + process $proc$libresoc.v:168237$9013 + assign { } { } + assign $0\xer_so_ok[0:0] \xer_so_ok$next + sync posedge \coresync_clk + update \xer_so_ok $0\xer_so_ok[0:0] + end + attribute \src "libresoc.v:168239.3-168240.29" + process $proc$libresoc.v:168239$9014 + assign { } { } + assign $0\xer_ov[1:0] \xer_ov$next + sync posedge \coresync_clk + update \xer_ov $0\xer_ov[1:0] + end + attribute \src "libresoc.v:168241.3-168242.35" + process $proc$libresoc.v:168241$9015 + assign { } { } + assign $0\xer_ov_ok[0:0] \xer_ov_ok$next + sync posedge \coresync_clk + update \xer_ov_ok $0\xer_ov_ok[0:0] + end + attribute \src "libresoc.v:168243.3-168244.29" + process $proc$libresoc.v:168243$9016 + assign { } { } + assign $0\xer_ca[1:0] \xer_ca$next + sync posedge \coresync_clk + update \xer_ca $0\xer_ca[1:0] + end + attribute \src "libresoc.v:168245.3-168246.35" + process $proc$libresoc.v:168245$9017 + assign { } { } + assign $0\xer_ca_ok[0:0] \xer_ca_ok$next + sync posedge \coresync_clk + update \xer_ca_ok $0\xer_ca_ok[0:0] + end + attribute \src "libresoc.v:168247.3-168248.25" + process $proc$libresoc.v:168247$9018 + assign { } { } + assign $0\cr_a[3:0] \cr_a$next + sync posedge \coresync_clk + update \cr_a $0\cr_a[3:0] + end + attribute \src "libresoc.v:168249.3-168250.31" + process $proc$libresoc.v:168249$9019 + assign { } { } + assign $0\cr_a_ok[0:0] \cr_a_ok$next + sync posedge \coresync_clk + update \cr_a_ok $0\cr_a_ok[0:0] + end + attribute \src "libresoc.v:168251.3-168252.19" + process $proc$libresoc.v:168251$9020 + assign { } { } + assign $0\o[63:0] \o$next + sync posedge \coresync_clk + update \o $0\o[63:0] + end + attribute \src "libresoc.v:168253.3-168254.25" + process $proc$libresoc.v:168253$9021 + assign { } { } + assign $0\o_ok[0:0] \o_ok$next + sync posedge \coresync_clk + update \o_ok $0\o_ok[0:0] + end + attribute \src "libresoc.v:168255.3-168256.51" + process $proc$libresoc.v:168255$9022 + assign { } { } + assign $0\alu_op__insn_type[6:0] \alu_op__insn_type$next + sync posedge \coresync_clk + update \alu_op__insn_type $0\alu_op__insn_type[6:0] + end + attribute \src "libresoc.v:168257.3-168258.47" + process $proc$libresoc.v:168257$9023 + assign { } { } + assign $0\alu_op__fn_unit[12:0] \alu_op__fn_unit$next + sync posedge \coresync_clk + update \alu_op__fn_unit $0\alu_op__fn_unit[12:0] + end + attribute \src "libresoc.v:168259.3-168260.61" + process $proc$libresoc.v:168259$9024 + assign { } { } + assign $0\alu_op__imm_data__data[63:0] \alu_op__imm_data__data$next + sync posedge \coresync_clk + update \alu_op__imm_data__data $0\alu_op__imm_data__data[63:0] + end + attribute \src "libresoc.v:168261.3-168262.57" + process $proc$libresoc.v:168261$9025 + assign { } { } + assign $0\alu_op__imm_data__ok[0:0] \alu_op__imm_data__ok$next + sync posedge \coresync_clk + update \alu_op__imm_data__ok $0\alu_op__imm_data__ok[0:0] + end + attribute \src "libresoc.v:168263.3-168264.45" + process $proc$libresoc.v:168263$9026 + assign { } { } + assign $0\alu_op__rc__rc[0:0] \alu_op__rc__rc$next + sync posedge \coresync_clk + update \alu_op__rc__rc $0\alu_op__rc__rc[0:0] + end + attribute \src "libresoc.v:168265.3-168266.45" + process $proc$libresoc.v:168265$9027 + assign { } { } + assign $0\alu_op__rc__ok[0:0] \alu_op__rc__ok$next + sync posedge \coresync_clk + update \alu_op__rc__ok $0\alu_op__rc__ok[0:0] + end + attribute \src "libresoc.v:168267.3-168268.45" + process $proc$libresoc.v:168267$9028 + assign { } { } + assign $0\alu_op__oe__oe[0:0] \alu_op__oe__oe$next + sync posedge \coresync_clk + update \alu_op__oe__oe $0\alu_op__oe__oe[0:0] + end + attribute \src "libresoc.v:168269.3-168270.45" + process $proc$libresoc.v:168269$9029 + assign { } { } + assign $0\alu_op__oe__ok[0:0] \alu_op__oe__ok$next + sync posedge \coresync_clk + update \alu_op__oe__ok $0\alu_op__oe__ok[0:0] + end + attribute \src "libresoc.v:168271.3-168272.51" + process $proc$libresoc.v:168271$9030 + assign { } { } + assign $0\alu_op__invert_in[0:0] \alu_op__invert_in$next + sync posedge \coresync_clk + update \alu_op__invert_in $0\alu_op__invert_in[0:0] + end + attribute \src "libresoc.v:168273.3-168274.45" + process $proc$libresoc.v:168273$9031 + assign { } { } + assign $0\alu_op__zero_a[0:0] \alu_op__zero_a$next + sync posedge \coresync_clk + update \alu_op__zero_a $0\alu_op__zero_a[0:0] + end + attribute \src "libresoc.v:168275.3-168276.53" + process $proc$libresoc.v:168275$9032 + assign { } { } + assign $0\alu_op__invert_out[0:0] \alu_op__invert_out$next + sync posedge \coresync_clk + update \alu_op__invert_out $0\alu_op__invert_out[0:0] + end + attribute \src "libresoc.v:168277.3-168278.51" + process $proc$libresoc.v:168277$9033 + assign { } { } + assign $0\alu_op__write_cr0[0:0] \alu_op__write_cr0$next + sync posedge \coresync_clk + update \alu_op__write_cr0 $0\alu_op__write_cr0[0:0] + end + attribute \src "libresoc.v:168279.3-168280.55" + process $proc$libresoc.v:168279$9034 + assign { } { } + assign $0\alu_op__input_carry[1:0] \alu_op__input_carry$next + sync posedge \coresync_clk + update \alu_op__input_carry $0\alu_op__input_carry[1:0] + end + attribute \src "libresoc.v:168281.3-168282.57" + process $proc$libresoc.v:168281$9035 + assign { } { } + assign $0\alu_op__output_carry[0:0] \alu_op__output_carry$next + sync posedge \coresync_clk + update \alu_op__output_carry $0\alu_op__output_carry[0:0] + end + attribute \src "libresoc.v:168283.3-168284.49" + process $proc$libresoc.v:168283$9036 + assign { } { } + assign $0\alu_op__is_32bit[0:0] \alu_op__is_32bit$next + sync posedge \coresync_clk + update \alu_op__is_32bit $0\alu_op__is_32bit[0:0] + end + attribute \src "libresoc.v:168285.3-168286.51" + process $proc$libresoc.v:168285$9037 + assign { } { } + assign $0\alu_op__is_signed[0:0] \alu_op__is_signed$next + sync posedge \coresync_clk + update \alu_op__is_signed $0\alu_op__is_signed[0:0] + end + attribute \src "libresoc.v:168287.3-168288.49" + process $proc$libresoc.v:168287$9038 + assign { } { } + assign $0\alu_op__data_len[3:0] \alu_op__data_len$next + sync posedge \coresync_clk + update \alu_op__data_len $0\alu_op__data_len[3:0] + end + attribute \src "libresoc.v:168289.3-168290.41" + process $proc$libresoc.v:168289$9039 + assign { } { } + assign $0\alu_op__insn[31:0] \alu_op__insn$next + sync posedge \coresync_clk + update \alu_op__insn $0\alu_op__insn[31:0] + end + attribute \src "libresoc.v:168291.3-168292.27" + process $proc$libresoc.v:168291$9040 + assign { } { } + assign $0\muxid[1:0] \muxid$next + sync posedge \coresync_clk + update \muxid $0\muxid[1:0] + end + attribute \src "libresoc.v:168293.3-168294.29" + process $proc$libresoc.v:168293$9041 + assign { } { } + assign $0\r_busy[0:0] \r_busy$next + sync posedge \coresync_clk + update \r_busy $0\r_busy[0:0] + end + attribute \src "libresoc.v:168404.3-168422.6" + process $proc$libresoc.v:168404$9042 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\cr_a$next[3:0]$9043 $1\cr_a$next[3:0]$9045 + assign { } { } + assign $0\cr_a_ok$next[0:0]$9044 $2\cr_a_ok$next[0:0]$9047 + attribute \src "libresoc.v:168405.5-168405.29" + switch \initial + attribute \src "libresoc.v:168405.9-168405.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\cr_a_ok$next[0:0]$9046 $1\cr_a$next[3:0]$9045 } { \cr_a_ok$91 \cr_a$90 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\cr_a_ok$next[0:0]$9046 $1\cr_a$next[3:0]$9045 } { \cr_a_ok$91 \cr_a$90 } + case + assign $1\cr_a$next[3:0]$9045 \cr_a + assign $1\cr_a_ok$next[0:0]$9046 \cr_a_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_a_ok$next[0:0]$9047 1'0 + case + assign $2\cr_a_ok$next[0:0]$9047 $1\cr_a_ok$next[0:0]$9046 + end + sync always + update \cr_a$next $0\cr_a$next[3:0]$9043 + update \cr_a_ok$next $0\cr_a_ok$next[0:0]$9044 + end + attribute \src "libresoc.v:168423.3-168441.6" + process $proc$libresoc.v:168423$9048 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\xer_ca$next[1:0]$9050 $1\xer_ca$next[1:0]$9052 + assign $0\xer_ca_ok$next[0:0]$9049 $2\xer_ca_ok$next[0:0]$9053 + attribute \src "libresoc.v:168424.5-168424.29" + switch \initial + attribute \src "libresoc.v:168424.9-168424.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\xer_ca_ok$next[0:0]$9051 $1\xer_ca$next[1:0]$9052 } { \xer_ca_ok$93 \xer_ca$92 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\xer_ca_ok$next[0:0]$9051 $1\xer_ca$next[1:0]$9052 } { \xer_ca_ok$93 \xer_ca$92 } + case + assign $1\xer_ca_ok$next[0:0]$9051 \xer_ca_ok + assign $1\xer_ca$next[1:0]$9052 \xer_ca + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\xer_ca_ok$next[0:0]$9053 1'0 + case + assign $2\xer_ca_ok$next[0:0]$9053 $1\xer_ca_ok$next[0:0]$9051 + end + sync always + update \xer_ca_ok$next $0\xer_ca_ok$next[0:0]$9049 + update \xer_ca$next $0\xer_ca$next[1:0]$9050 + end + attribute \src "libresoc.v:168442.3-168460.6" + process $proc$libresoc.v:168442$9054 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\xer_ov$next[1:0]$9055 $1\xer_ov$next[1:0]$9057 + assign { } { } + assign $0\xer_ov_ok$next[0:0]$9056 $2\xer_ov_ok$next[0:0]$9059 + attribute \src "libresoc.v:168443.5-168443.29" + switch \initial + attribute \src "libresoc.v:168443.9-168443.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\xer_ov_ok$next[0:0]$9058 $1\xer_ov$next[1:0]$9057 } { \xer_ov_ok$95 \xer_ov$94 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\xer_ov_ok$next[0:0]$9058 $1\xer_ov$next[1:0]$9057 } { \xer_ov_ok$95 \xer_ov$94 } + case + assign $1\xer_ov$next[1:0]$9057 \xer_ov + assign $1\xer_ov_ok$next[0:0]$9058 \xer_ov_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\xer_ov_ok$next[0:0]$9059 1'0 + case + assign $2\xer_ov_ok$next[0:0]$9059 $1\xer_ov_ok$next[0:0]$9058 + end + sync always + update \xer_ov$next $0\xer_ov$next[1:0]$9055 + update \xer_ov_ok$next $0\xer_ov_ok$next[0:0]$9056 + end + attribute \src "libresoc.v:168461.3-168479.6" + process $proc$libresoc.v:168461$9060 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\xer_so$next[0:0]$9061 $1\xer_so$next[0:0]$9063 + assign { } { } + assign $0\xer_so_ok$next[0:0]$9062 $2\xer_so_ok$next[0:0]$9065 + attribute \src "libresoc.v:168462.5-168462.29" + switch \initial + attribute \src "libresoc.v:168462.9-168462.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\xer_so_ok$next[0:0]$9064 $1\xer_so$next[0:0]$9063 } { \xer_so_ok$97 \xer_so$96 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\xer_so_ok$next[0:0]$9064 $1\xer_so$next[0:0]$9063 } { \xer_so_ok$97 \xer_so$96 } + case + assign $1\xer_so$next[0:0]$9063 \xer_so + assign $1\xer_so_ok$next[0:0]$9064 \xer_so_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\xer_so_ok$next[0:0]$9065 1'0 + case + assign $2\xer_so_ok$next[0:0]$9065 $1\xer_so_ok$next[0:0]$9064 + end + sync always + update \xer_so$next $0\xer_so$next[0:0]$9061 + update \xer_so_ok$next $0\xer_so_ok$next[0:0]$9062 + end + attribute \src "libresoc.v:168480.3-168497.6" + process $proc$libresoc.v:168480$9066 + assign { } { } + assign { } { } + assign { } { } + assign $0\r_busy$next[0:0]$9067 $2\r_busy$next[0:0]$9069 + attribute \src "libresoc.v:168481.5-168481.29" + switch \initial + attribute \src "libresoc.v:168481.9-168481.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\r_busy$next[0:0]$9068 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\r_busy$next[0:0]$9068 1'0 + case + assign $1\r_busy$next[0:0]$9068 \r_busy + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r_busy$next[0:0]$9069 1'0 + case + assign $2\r_busy$next[0:0]$9069 $1\r_busy$next[0:0]$9068 + end + sync always + update \r_busy$next $0\r_busy$next[0:0]$9067 + end + attribute \src "libresoc.v:168498.3-168510.6" + process $proc$libresoc.v:168498$9070 + assign { } { } + assign { } { } + assign $0\muxid$next[1:0]$9071 $1\muxid$next[1:0]$9072 + attribute \src "libresoc.v:168499.5-168499.29" + switch \initial + attribute \src "libresoc.v:168499.9-168499.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\muxid$next[1:0]$9072 \muxid$69 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\muxid$next[1:0]$9072 \muxid$69 + case + assign $1\muxid$next[1:0]$9072 \muxid + end + sync always + update \muxid$next $0\muxid$next[1:0]$9071 + end + attribute \src "libresoc.v:168511.3-168552.6" + process $proc$libresoc.v:168511$9073 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\alu_op__data_len$next[3:0]$9074 $1\alu_op__data_len$next[3:0]$9092 + assign $0\alu_op__fn_unit$next[12:0]$9075 $1\alu_op__fn_unit$next[12:0]$9093 + assign { } { } + assign { } { } + assign $0\alu_op__input_carry$next[1:0]$9078 $1\alu_op__input_carry$next[1:0]$9096 + assign $0\alu_op__insn$next[31:0]$9079 $1\alu_op__insn$next[31:0]$9097 + assign $0\alu_op__insn_type$next[6:0]$9080 $1\alu_op__insn_type$next[6:0]$9098 + assign $0\alu_op__invert_in$next[0:0]$9081 $1\alu_op__invert_in$next[0:0]$9099 + assign $0\alu_op__invert_out$next[0:0]$9082 $1\alu_op__invert_out$next[0:0]$9100 + assign $0\alu_op__is_32bit$next[0:0]$9083 $1\alu_op__is_32bit$next[0:0]$9101 + assign $0\alu_op__is_signed$next[0:0]$9084 $1\alu_op__is_signed$next[0:0]$9102 + assign { } { } + assign { } { } + assign $0\alu_op__output_carry$next[0:0]$9087 $1\alu_op__output_carry$next[0:0]$9105 + assign { } { } + assign { } { } + assign $0\alu_op__write_cr0$next[0:0]$9090 $1\alu_op__write_cr0$next[0:0]$9108 + assign $0\alu_op__zero_a$next[0:0]$9091 $1\alu_op__zero_a$next[0:0]$9109 + assign $0\alu_op__imm_data__data$next[63:0]$9076 $2\alu_op__imm_data__data$next[63:0]$9110 + assign $0\alu_op__imm_data__ok$next[0:0]$9077 $2\alu_op__imm_data__ok$next[0:0]$9111 + assign $0\alu_op__oe__oe$next[0:0]$9085 $2\alu_op__oe__oe$next[0:0]$9112 + assign $0\alu_op__oe__ok$next[0:0]$9086 $2\alu_op__oe__ok$next[0:0]$9113 + assign $0\alu_op__rc__ok$next[0:0]$9088 $2\alu_op__rc__ok$next[0:0]$9114 + assign $0\alu_op__rc__rc$next[0:0]$9089 $2\alu_op__rc__rc$next[0:0]$9115 + attribute \src "libresoc.v:168512.5-168512.29" + switch \initial + attribute \src "libresoc.v:168512.9-168512.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\alu_op__insn$next[31:0]$9097 $1\alu_op__data_len$next[3:0]$9092 $1\alu_op__is_signed$next[0:0]$9102 $1\alu_op__is_32bit$next[0:0]$9101 $1\alu_op__output_carry$next[0:0]$9105 $1\alu_op__input_carry$next[1:0]$9096 $1\alu_op__write_cr0$next[0:0]$9108 $1\alu_op__invert_out$next[0:0]$9100 $1\alu_op__zero_a$next[0:0]$9109 $1\alu_op__invert_in$next[0:0]$9099 $1\alu_op__oe__ok$next[0:0]$9104 $1\alu_op__oe__oe$next[0:0]$9103 $1\alu_op__rc__ok$next[0:0]$9106 $1\alu_op__rc__rc$next[0:0]$9107 $1\alu_op__imm_data__ok$next[0:0]$9095 $1\alu_op__imm_data__data$next[63:0]$9094 $1\alu_op__fn_unit$next[12:0]$9093 $1\alu_op__insn_type$next[6:0]$9098 } { \alu_op__insn$87 \alu_op__data_len$86 \alu_op__is_signed$85 \alu_op__is_32bit$84 \alu_op__output_carry$83 \alu_op__input_carry$82 \alu_op__write_cr0$81 \alu_op__invert_out$80 \alu_op__zero_a$79 \alu_op__invert_in$78 \alu_op__oe__ok$77 \alu_op__oe__oe$76 \alu_op__rc__ok$75 \alu_op__rc__rc$74 \alu_op__imm_data__ok$73 \alu_op__imm_data__data$72 \alu_op__fn_unit$71 \alu_op__insn_type$70 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\alu_op__insn$next[31:0]$9097 $1\alu_op__data_len$next[3:0]$9092 $1\alu_op__is_signed$next[0:0]$9102 $1\alu_op__is_32bit$next[0:0]$9101 $1\alu_op__output_carry$next[0:0]$9105 $1\alu_op__input_carry$next[1:0]$9096 $1\alu_op__write_cr0$next[0:0]$9108 $1\alu_op__invert_out$next[0:0]$9100 $1\alu_op__zero_a$next[0:0]$9109 $1\alu_op__invert_in$next[0:0]$9099 $1\alu_op__oe__ok$next[0:0]$9104 $1\alu_op__oe__oe$next[0:0]$9103 $1\alu_op__rc__ok$next[0:0]$9106 $1\alu_op__rc__rc$next[0:0]$9107 $1\alu_op__imm_data__ok$next[0:0]$9095 $1\alu_op__imm_data__data$next[63:0]$9094 $1\alu_op__fn_unit$next[12:0]$9093 $1\alu_op__insn_type$next[6:0]$9098 } { \alu_op__insn$87 \alu_op__data_len$86 \alu_op__is_signed$85 \alu_op__is_32bit$84 \alu_op__output_carry$83 \alu_op__input_carry$82 \alu_op__write_cr0$81 \alu_op__invert_out$80 \alu_op__zero_a$79 \alu_op__invert_in$78 \alu_op__oe__ok$77 \alu_op__oe__oe$76 \alu_op__rc__ok$75 \alu_op__rc__rc$74 \alu_op__imm_data__ok$73 \alu_op__imm_data__data$72 \alu_op__fn_unit$71 \alu_op__insn_type$70 } + case + assign $1\alu_op__data_len$next[3:0]$9092 \alu_op__data_len + assign $1\alu_op__fn_unit$next[12:0]$9093 \alu_op__fn_unit + assign $1\alu_op__imm_data__data$next[63:0]$9094 \alu_op__imm_data__data + assign $1\alu_op__imm_data__ok$next[0:0]$9095 \alu_op__imm_data__ok + assign $1\alu_op__input_carry$next[1:0]$9096 \alu_op__input_carry + assign $1\alu_op__insn$next[31:0]$9097 \alu_op__insn + assign $1\alu_op__insn_type$next[6:0]$9098 \alu_op__insn_type + assign $1\alu_op__invert_in$next[0:0]$9099 \alu_op__invert_in + assign $1\alu_op__invert_out$next[0:0]$9100 \alu_op__invert_out + assign $1\alu_op__is_32bit$next[0:0]$9101 \alu_op__is_32bit + assign $1\alu_op__is_signed$next[0:0]$9102 \alu_op__is_signed + assign $1\alu_op__oe__oe$next[0:0]$9103 \alu_op__oe__oe + assign $1\alu_op__oe__ok$next[0:0]$9104 \alu_op__oe__ok + assign $1\alu_op__output_carry$next[0:0]$9105 \alu_op__output_carry + assign $1\alu_op__rc__ok$next[0:0]$9106 \alu_op__rc__ok + assign $1\alu_op__rc__rc$next[0:0]$9107 \alu_op__rc__rc + assign $1\alu_op__write_cr0$next[0:0]$9108 \alu_op__write_cr0 + assign $1\alu_op__zero_a$next[0:0]$9109 \alu_op__zero_a + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $2\alu_op__imm_data__data$next[63:0]$9110 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\alu_op__imm_data__ok$next[0:0]$9111 1'0 + assign $2\alu_op__rc__rc$next[0:0]$9115 1'0 + assign $2\alu_op__rc__ok$next[0:0]$9114 1'0 + assign $2\alu_op__oe__oe$next[0:0]$9112 1'0 + assign $2\alu_op__oe__ok$next[0:0]$9113 1'0 + case + assign $2\alu_op__imm_data__data$next[63:0]$9110 $1\alu_op__imm_data__data$next[63:0]$9094 + assign $2\alu_op__imm_data__ok$next[0:0]$9111 $1\alu_op__imm_data__ok$next[0:0]$9095 + assign $2\alu_op__oe__oe$next[0:0]$9112 $1\alu_op__oe__oe$next[0:0]$9103 + assign $2\alu_op__oe__ok$next[0:0]$9113 $1\alu_op__oe__ok$next[0:0]$9104 + assign $2\alu_op__rc__ok$next[0:0]$9114 $1\alu_op__rc__ok$next[0:0]$9106 + assign $2\alu_op__rc__rc$next[0:0]$9115 $1\alu_op__rc__rc$next[0:0]$9107 + end + sync always + update \alu_op__data_len$next $0\alu_op__data_len$next[3:0]$9074 + update \alu_op__fn_unit$next $0\alu_op__fn_unit$next[12:0]$9075 + update \alu_op__imm_data__data$next $0\alu_op__imm_data__data$next[63:0]$9076 + update \alu_op__imm_data__ok$next $0\alu_op__imm_data__ok$next[0:0]$9077 + update \alu_op__input_carry$next $0\alu_op__input_carry$next[1:0]$9078 + update \alu_op__insn$next $0\alu_op__insn$next[31:0]$9079 + update \alu_op__insn_type$next $0\alu_op__insn_type$next[6:0]$9080 + update \alu_op__invert_in$next $0\alu_op__invert_in$next[0:0]$9081 + update \alu_op__invert_out$next $0\alu_op__invert_out$next[0:0]$9082 + update \alu_op__is_32bit$next $0\alu_op__is_32bit$next[0:0]$9083 + update \alu_op__is_signed$next $0\alu_op__is_signed$next[0:0]$9084 + update \alu_op__oe__oe$next $0\alu_op__oe__oe$next[0:0]$9085 + update \alu_op__oe__ok$next $0\alu_op__oe__ok$next[0:0]$9086 + update \alu_op__output_carry$next $0\alu_op__output_carry$next[0:0]$9087 + update \alu_op__rc__ok$next $0\alu_op__rc__ok$next[0:0]$9088 + update \alu_op__rc__rc$next $0\alu_op__rc__rc$next[0:0]$9089 + update \alu_op__write_cr0$next $0\alu_op__write_cr0$next[0:0]$9090 + update \alu_op__zero_a$next $0\alu_op__zero_a$next[0:0]$9091 + end + attribute \src "libresoc.v:168553.3-168571.6" + process $proc$libresoc.v:168553$9116 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\o$next[63:0]$9117 $1\o$next[63:0]$9119 + assign { } { } + assign $0\o_ok$next[0:0]$9118 $2\o_ok$next[0:0]$9121 + attribute \src "libresoc.v:168554.5-168554.29" + switch \initial + attribute \src "libresoc.v:168554.9-168554.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\o_ok$next[0:0]$9120 $1\o$next[63:0]$9119 } { \o_ok$89 \o$88 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\o_ok$next[0:0]$9120 $1\o$next[63:0]$9119 } { \o_ok$89 \o$88 } + case + assign $1\o$next[63:0]$9119 \o + assign $1\o_ok$next[0:0]$9120 \o_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\o_ok$next[0:0]$9121 1'0 + case + assign $2\o_ok$next[0:0]$9121 $1\o_ok$next[0:0]$9120 + end + sync always + update \o$next $0\o$next[63:0]$9117 + update \o_ok$next $0\o_ok$next[0:0]$9118 + end + connect \$67 $and$libresoc.v:168234$9011_Y + connect \xer_so_ok$98 1'0 + connect \p_ready_o \n_i_rdy_data + connect \n_valid_o \r_busy + connect { \xer_so_ok$97 \xer_so$96 } { 1'0 \main_xer_so$65 } + connect { \xer_ov_ok$95 \xer_ov$94 } { \main_xer_ov_ok \main_xer_ov } + connect { \xer_ca_ok$93 \xer_ca$92 } { \main_xer_ca_ok \main_xer_ca$64 } + connect { \cr_a_ok$91 \cr_a$90 } { \main_cr_a_ok \main_cr_a } + connect { \o_ok$89 \o$88 } { \main_o_ok \main_o } + connect { \alu_op__insn$87 \alu_op__data_len$86 \alu_op__is_signed$85 \alu_op__is_32bit$84 \alu_op__output_carry$83 \alu_op__input_carry$82 \alu_op__write_cr0$81 \alu_op__invert_out$80 \alu_op__zero_a$79 \alu_op__invert_in$78 \alu_op__oe__ok$77 \alu_op__oe__oe$76 \alu_op__rc__ok$75 \alu_op__rc__rc$74 \alu_op__imm_data__ok$73 \alu_op__imm_data__data$72 \alu_op__fn_unit$71 \alu_op__insn_type$70 } { \main_alu_op__insn$63 \main_alu_op__data_len$62 \main_alu_op__is_signed$61 \main_alu_op__is_32bit$60 \main_alu_op__output_carry$59 \main_alu_op__input_carry$58 \main_alu_op__write_cr0$57 \main_alu_op__invert_out$56 \main_alu_op__zero_a$55 \main_alu_op__invert_in$54 \main_alu_op__oe__ok$53 \main_alu_op__oe__oe$52 \main_alu_op__rc__ok$51 \main_alu_op__rc__rc$50 \main_alu_op__imm_data__ok$49 \main_alu_op__imm_data__data$48 \main_alu_op__fn_unit$47 \main_alu_op__insn_type$46 } + connect \muxid$69 \main_muxid$45 + connect \p_valid_i_p_ready_o \$67 + connect \n_i_rdy_data \n_ready_i + connect \p_valid_i$66 \p_valid_i + connect \main_xer_ca \input_xer_ca$44 + connect \main_xer_so \input_xer_so$43 + connect \main_rb \input_rb$42 + connect \main_ra \input_ra$41 + connect { \main_alu_op__insn \main_alu_op__data_len \main_alu_op__is_signed \main_alu_op__is_32bit \main_alu_op__output_carry \main_alu_op__input_carry \main_alu_op__write_cr0 \main_alu_op__invert_out \main_alu_op__zero_a \main_alu_op__invert_in \main_alu_op__oe__ok \main_alu_op__oe__oe \main_alu_op__rc__ok \main_alu_op__rc__rc \main_alu_op__imm_data__ok \main_alu_op__imm_data__data \main_alu_op__fn_unit \main_alu_op__insn_type } { \input_alu_op__insn$40 \input_alu_op__data_len$39 \input_alu_op__is_signed$38 \input_alu_op__is_32bit$37 \input_alu_op__output_carry$36 \input_alu_op__input_carry$35 \input_alu_op__write_cr0$34 \input_alu_op__invert_out$33 \input_alu_op__zero_a$32 \input_alu_op__invert_in$31 \input_alu_op__oe__ok$30 \input_alu_op__oe__oe$29 \input_alu_op__rc__ok$28 \input_alu_op__rc__rc$27 \input_alu_op__imm_data__ok$26 \input_alu_op__imm_data__data$25 \input_alu_op__fn_unit$24 \input_alu_op__insn_type$23 } + connect \main_muxid \input_muxid$22 + connect \input_xer_ca \xer_ca$21 + connect \input_xer_so \xer_so$20 + connect \input_rb \rb + connect \input_ra \ra + connect { \input_alu_op__insn \input_alu_op__data_len \input_alu_op__is_signed \input_alu_op__is_32bit \input_alu_op__output_carry \input_alu_op__input_carry \input_alu_op__write_cr0 \input_alu_op__invert_out \input_alu_op__zero_a \input_alu_op__invert_in \input_alu_op__oe__ok \input_alu_op__oe__oe \input_alu_op__rc__ok \input_alu_op__rc__rc \input_alu_op__imm_data__ok \input_alu_op__imm_data__data \input_alu_op__fn_unit \input_alu_op__insn_type } { \alu_op__insn$19 \alu_op__data_len$18 \alu_op__is_signed$17 \alu_op__is_32bit$16 \alu_op__output_carry$15 \alu_op__input_carry$14 \alu_op__write_cr0$13 \alu_op__invert_out$12 \alu_op__zero_a$11 \alu_op__invert_in$10 \alu_op__oe__ok$9 \alu_op__oe__oe$8 \alu_op__rc__ok$7 \alu_op__rc__rc$6 \alu_op__imm_data__ok$5 \alu_op__imm_data__data$4 \alu_op__fn_unit$3 \alu_op__insn_type$2 } + connect \input_muxid \muxid$1 +end +attribute \src "libresoc.v:168601.1-170023.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1" +attribute \generator "nMigen" +module \pipe1$110 + attribute \src "libresoc.v:169956.3-169974.6" + wire width 4 $0\cr_a$next[3:0]$9242 + attribute \src "libresoc.v:169698.3-169699.25" + wire width 4 $0\cr_a[3:0] + attribute \src "libresoc.v:169956.3-169974.6" + wire $0\cr_a_ok$next[0:0]$9243 + attribute \src "libresoc.v:169700.3-169701.31" + wire $0\cr_a_ok[0:0] + attribute \src "libresoc.v:168602.7-168602.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:169883.3-169895.6" + wire width 2 $0\muxid$next[1:0]$9192 + attribute \src "libresoc.v:169740.3-169741.27" + wire width 2 $0\muxid[1:0] + attribute \src "libresoc.v:169937.3-169955.6" + wire width 64 $0\o$next[63:0]$9236 + attribute \src "libresoc.v:169702.3-169703.19" + wire width 64 $0\o[63:0] + attribute \src "libresoc.v:169937.3-169955.6" + wire $0\o_ok$next[0:0]$9237 + attribute \src "libresoc.v:169704.3-169705.25" + wire $0\o_ok[0:0] + attribute \src "libresoc.v:169865.3-169882.6" + wire $0\r_busy$next[0:0]$9188 + attribute \src "libresoc.v:169742.3-169743.29" + wire $0\r_busy[0:0] + attribute \src "libresoc.v:169896.3-169936.6" + wire width 13 $0\sr_op__fn_unit$next[12:0]$9195 + attribute \src "libresoc.v:169708.3-169709.45" + wire width 13 $0\sr_op__fn_unit[12:0] + attribute \src "libresoc.v:169896.3-169936.6" + wire width 64 $0\sr_op__imm_data__data$next[63:0]$9196 + attribute \src "libresoc.v:169710.3-169711.59" + wire width 64 $0\sr_op__imm_data__data[63:0] + attribute \src "libresoc.v:169896.3-169936.6" + wire $0\sr_op__imm_data__ok$next[0:0]$9197 + attribute \src "libresoc.v:169712.3-169713.55" + wire $0\sr_op__imm_data__ok[0:0] + attribute \src "libresoc.v:169896.3-169936.6" + wire width 2 $0\sr_op__input_carry$next[1:0]$9198 + attribute \src "libresoc.v:169726.3-169727.53" + wire width 2 $0\sr_op__input_carry[1:0] + attribute \src "libresoc.v:169896.3-169936.6" + wire $0\sr_op__input_cr$next[0:0]$9199 + attribute \src "libresoc.v:169730.3-169731.47" + wire $0\sr_op__input_cr[0:0] + attribute \src "libresoc.v:169896.3-169936.6" + wire width 32 $0\sr_op__insn$next[31:0]$9200 + attribute \src "libresoc.v:169738.3-169739.39" + wire width 32 $0\sr_op__insn[31:0] + attribute \src "libresoc.v:169896.3-169936.6" + wire width 7 $0\sr_op__insn_type$next[6:0]$9201 + attribute \src "libresoc.v:169706.3-169707.49" + wire width 7 $0\sr_op__insn_type[6:0] + attribute \src "libresoc.v:169896.3-169936.6" + wire $0\sr_op__invert_in$next[0:0]$9202 + attribute \src "libresoc.v:169724.3-169725.49" + wire $0\sr_op__invert_in[0:0] + attribute \src "libresoc.v:169896.3-169936.6" + wire $0\sr_op__is_32bit$next[0:0]$9203 + attribute \src "libresoc.v:169734.3-169735.47" + wire $0\sr_op__is_32bit[0:0] + attribute \src "libresoc.v:169896.3-169936.6" + wire $0\sr_op__is_signed$next[0:0]$9204 + attribute \src "libresoc.v:169736.3-169737.49" + wire $0\sr_op__is_signed[0:0] + attribute \src "libresoc.v:169896.3-169936.6" + wire $0\sr_op__oe__oe$next[0:0]$9205 + attribute \src "libresoc.v:169718.3-169719.43" + wire $0\sr_op__oe__oe[0:0] + attribute \src "libresoc.v:169896.3-169936.6" + wire $0\sr_op__oe__ok$next[0:0]$9206 + attribute \src "libresoc.v:169720.3-169721.43" + wire $0\sr_op__oe__ok[0:0] + attribute \src "libresoc.v:169896.3-169936.6" + wire $0\sr_op__output_carry$next[0:0]$9207 + attribute \src "libresoc.v:169728.3-169729.55" + wire $0\sr_op__output_carry[0:0] + attribute \src "libresoc.v:169896.3-169936.6" + wire $0\sr_op__output_cr$next[0:0]$9208 + attribute \src "libresoc.v:169732.3-169733.49" + wire $0\sr_op__output_cr[0:0] + attribute \src "libresoc.v:169896.3-169936.6" + wire $0\sr_op__rc__ok$next[0:0]$9209 + attribute \src "libresoc.v:169716.3-169717.43" + wire $0\sr_op__rc__ok[0:0] + attribute \src "libresoc.v:169896.3-169936.6" + wire $0\sr_op__rc__rc$next[0:0]$9210 + attribute \src "libresoc.v:169714.3-169715.43" + wire $0\sr_op__rc__rc[0:0] + attribute \src "libresoc.v:169896.3-169936.6" + wire $0\sr_op__write_cr0$next[0:0]$9211 + attribute \src "libresoc.v:169722.3-169723.49" + wire $0\sr_op__write_cr0[0:0] + attribute \src "libresoc.v:169846.3-169864.6" + wire width 2 $0\xer_ca$next[1:0]$9183 + attribute \src "libresoc.v:169690.3-169691.29" + wire width 2 $0\xer_ca[1:0] + attribute \src "libresoc.v:169846.3-169864.6" + wire $0\xer_ca_ok$next[0:0]$9182 + attribute \src "libresoc.v:169692.3-169693.35" + wire $0\xer_ca_ok[0:0] + attribute \src "libresoc.v:169975.3-169993.6" + wire $0\xer_so$next[0:0]$9248 + attribute \src "libresoc.v:169694.3-169695.29" + wire $0\xer_so[0:0] + attribute \src "libresoc.v:169975.3-169993.6" + wire $0\xer_so_ok$next[0:0]$9249 + attribute \src "libresoc.v:169696.3-169697.35" + wire $0\xer_so_ok[0:0] + attribute \src "libresoc.v:169956.3-169974.6" + wire width 4 $1\cr_a$next[3:0]$9244 + attribute \src "libresoc.v:168611.13-168611.24" + wire width 4 $1\cr_a[3:0] + attribute \src "libresoc.v:169956.3-169974.6" + wire $1\cr_a_ok$next[0:0]$9245 + attribute \src "libresoc.v:168620.7-168620.21" + wire $1\cr_a_ok[0:0] + attribute \src "libresoc.v:169883.3-169895.6" + wire width 2 $1\muxid$next[1:0]$9193 + attribute \src "libresoc.v:169177.13-169177.25" + wire width 2 $1\muxid[1:0] + attribute \src "libresoc.v:169937.3-169955.6" + wire width 64 $1\o$next[63:0]$9238 + attribute \src "libresoc.v:169192.14-169192.38" + wire width 64 $1\o[63:0] + attribute \src "libresoc.v:169937.3-169955.6" + wire $1\o_ok$next[0:0]$9239 + attribute \src "libresoc.v:169199.7-169199.18" + wire $1\o_ok[0:0] + attribute \src "libresoc.v:169865.3-169882.6" + wire $1\r_busy$next[0:0]$9189 + attribute \src "libresoc.v:169213.7-169213.20" + wire $1\r_busy[0:0] + attribute \src "libresoc.v:169896.3-169936.6" + wire width 13 $1\sr_op__fn_unit$next[12:0]$9212 + attribute \src "libresoc.v:169238.14-169238.39" + wire width 13 $1\sr_op__fn_unit[12:0] + attribute \src "libresoc.v:169896.3-169936.6" + wire width 64 $1\sr_op__imm_data__data$next[63:0]$9213 + attribute \src "libresoc.v:169275.14-169275.58" + wire width 64 $1\sr_op__imm_data__data[63:0] + attribute \src "libresoc.v:169896.3-169936.6" + wire $1\sr_op__imm_data__ok$next[0:0]$9214 + attribute \src "libresoc.v:169284.7-169284.33" + wire $1\sr_op__imm_data__ok[0:0] + attribute \src "libresoc.v:169896.3-169936.6" + wire width 2 $1\sr_op__input_carry$next[1:0]$9215 + attribute \src "libresoc.v:169297.13-169297.38" + wire width 2 $1\sr_op__input_carry[1:0] + attribute \src "libresoc.v:169896.3-169936.6" + wire $1\sr_op__input_cr$next[0:0]$9216 + attribute \src "libresoc.v:169314.7-169314.29" + wire $1\sr_op__input_cr[0:0] + attribute \src "libresoc.v:169896.3-169936.6" + wire width 32 $1\sr_op__insn$next[31:0]$9217 + attribute \src "libresoc.v:169323.14-169323.33" + wire width 32 $1\sr_op__insn[31:0] + attribute \src "libresoc.v:169896.3-169936.6" + wire width 7 $1\sr_op__insn_type$next[6:0]$9218 + attribute \src "libresoc.v:169406.13-169406.37" + wire width 7 $1\sr_op__insn_type[6:0] + attribute \src "libresoc.v:169896.3-169936.6" + wire $1\sr_op__invert_in$next[0:0]$9219 + attribute \src "libresoc.v:169563.7-169563.30" + wire $1\sr_op__invert_in[0:0] + attribute \src "libresoc.v:169896.3-169936.6" + wire $1\sr_op__is_32bit$next[0:0]$9220 + attribute \src "libresoc.v:169572.7-169572.29" + wire $1\sr_op__is_32bit[0:0] + attribute \src "libresoc.v:169896.3-169936.6" + wire $1\sr_op__is_signed$next[0:0]$9221 + attribute \src "libresoc.v:169581.7-169581.30" + wire $1\sr_op__is_signed[0:0] + attribute \src "libresoc.v:169896.3-169936.6" + wire $1\sr_op__oe__oe$next[0:0]$9222 + attribute \src "libresoc.v:169590.7-169590.27" + wire $1\sr_op__oe__oe[0:0] + attribute \src "libresoc.v:169896.3-169936.6" + wire $1\sr_op__oe__ok$next[0:0]$9223 + attribute \src "libresoc.v:169599.7-169599.27" + wire $1\sr_op__oe__ok[0:0] + attribute \src "libresoc.v:169896.3-169936.6" + wire $1\sr_op__output_carry$next[0:0]$9224 + attribute \src "libresoc.v:169608.7-169608.33" + wire $1\sr_op__output_carry[0:0] + attribute \src "libresoc.v:169896.3-169936.6" + wire $1\sr_op__output_cr$next[0:0]$9225 + attribute \src "libresoc.v:169617.7-169617.30" + wire $1\sr_op__output_cr[0:0] + attribute \src "libresoc.v:169896.3-169936.6" + wire $1\sr_op__rc__ok$next[0:0]$9226 + attribute \src "libresoc.v:169626.7-169626.27" + wire $1\sr_op__rc__ok[0:0] + attribute \src "libresoc.v:169896.3-169936.6" + wire $1\sr_op__rc__rc$next[0:0]$9227 + attribute \src "libresoc.v:169635.7-169635.27" + wire $1\sr_op__rc__rc[0:0] + attribute \src "libresoc.v:169896.3-169936.6" + wire $1\sr_op__write_cr0$next[0:0]$9228 + attribute \src "libresoc.v:169644.7-169644.30" + wire $1\sr_op__write_cr0[0:0] + attribute \src "libresoc.v:169846.3-169864.6" + wire width 2 $1\xer_ca$next[1:0]$9185 + attribute \src "libresoc.v:169653.13-169653.26" + wire width 2 $1\xer_ca[1:0] + attribute \src "libresoc.v:169846.3-169864.6" + wire $1\xer_ca_ok$next[0:0]$9184 + attribute \src "libresoc.v:169664.7-169664.23" + wire $1\xer_ca_ok[0:0] + attribute \src "libresoc.v:169975.3-169993.6" + wire $1\xer_so$next[0:0]$9250 + attribute \src "libresoc.v:169673.7-169673.20" + wire $1\xer_so[0:0] + attribute \src "libresoc.v:169975.3-169993.6" + wire $1\xer_so_ok$next[0:0]$9251 + attribute \src "libresoc.v:169682.7-169682.23" + wire $1\xer_so_ok[0:0] + attribute \src "libresoc.v:169956.3-169974.6" + wire $2\cr_a_ok$next[0:0]$9246 + attribute \src "libresoc.v:169937.3-169955.6" + wire $2\o_ok$next[0:0]$9240 + attribute \src "libresoc.v:169865.3-169882.6" + wire $2\r_busy$next[0:0]$9190 + attribute \src "libresoc.v:169896.3-169936.6" + wire width 64 $2\sr_op__imm_data__data$next[63:0]$9229 + attribute \src "libresoc.v:169896.3-169936.6" + wire $2\sr_op__imm_data__ok$next[0:0]$9230 + attribute \src "libresoc.v:169896.3-169936.6" + wire $2\sr_op__oe__oe$next[0:0]$9231 + attribute \src "libresoc.v:169896.3-169936.6" + wire $2\sr_op__oe__ok$next[0:0]$9232 + attribute \src "libresoc.v:169896.3-169936.6" + wire $2\sr_op__rc__ok$next[0:0]$9233 + attribute \src "libresoc.v:169896.3-169936.6" + wire $2\sr_op__rc__rc$next[0:0]$9234 + attribute \src "libresoc.v:169846.3-169864.6" + wire $2\xer_ca_ok$next[0:0]$9186 + attribute \src "libresoc.v:169975.3-169993.6" + wire $2\xer_so_ok$next[0:0]$9252 + attribute \src "libresoc.v:169689.18-169689.118" + wire $and$libresoc.v:169689$9153_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" + wire \$65 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 55 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 output 24 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \cr_a$87 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \cr_a$89 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \cr_a$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 25 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_a_ok$88 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_a_ok$90 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_a_ok$next + attribute \src "libresoc.v:168602.7-168602.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \input_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \input_muxid$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_ra$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_rb$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_rc$41 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \input_sr_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \input_sr_op__fn_unit$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \input_sr_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \input_sr_op__imm_data__data$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__imm_data__ok$25 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \input_sr_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \input_sr_op__input_carry$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__input_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__input_cr$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \input_sr_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \input_sr_op__insn$38 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute 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\enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \input_sr_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \input_sr_op__insn_type$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__invert_in$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__is_32bit$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__is_signed$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__oe__oe$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__oe__ok$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__output_carry 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\input_sr_op__write_cr0$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 \input_xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 \input_xer_ca$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \input_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \input_xer_so$42 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \main_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \main_muxid$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \main_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \main_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \main_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \main_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \main_rc + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \main_sr_op__fn_unit + attribute \enum_base_type "Function" + attribute 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"/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_sr_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_sr_op__imm_data__ok$48 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \main_sr_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \main_sr_op__input_carry$55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_sr_op__input_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_sr_op__input_cr$57 + attribute \src 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attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute 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"/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_sr_op__invert_in$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_sr_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_sr_op__is_32bit$59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_sr_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_sr_op__is_signed$60 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_sr_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_sr_op__oe__oe$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_sr_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_sr_op__oe__ok$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_sr_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_sr_op__output_carry$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_sr_op__output_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_sr_op__output_cr$58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_sr_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_sr_op__rc__ok$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_sr_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_sr_op__rc__rc$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_sr_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_sr_op__write_cr0$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \main_xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \main_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \main_xer_so$62 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 output 4 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 input 32 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid$67 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + wire \n_i_rdy_data + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire input 3 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire output 2 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 22 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \o$85 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \o$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 23 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \o_ok$86 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \o_ok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" + wire output 31 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" + wire input 30 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" + wire \p_valid_i$64 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" + wire \p_valid_i_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire \r_busy$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 50 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 51 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 52 \rc + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 output 6 \sr_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute 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"/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \sr_op__fn_unit$69 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \sr_op__fn_unit$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 7 \sr_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 35 \sr_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \sr_op__imm_data__data$70 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \sr_op__imm_data__data$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 8 \sr_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 36 \sr_op__imm_data__ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__imm_data__ok$71 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__imm_data__ok$next + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 15 \sr_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 43 \sr_op__input_carry$12 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \sr_op__input_carry$78 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \sr_op__input_carry$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 17 \sr_op__input_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 45 \sr_op__input_cr$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__input_cr$80 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__input_cr$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 21 \sr_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 49 \sr_op__insn$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \sr_op__insn$84 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \sr_op__insn$next + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 5 \sr_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 33 \sr_op__insn_type$2 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \sr_op__insn_type$68 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \sr_op__insn_type$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 14 \sr_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 42 \sr_op__invert_in$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__invert_in$77 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__invert_in$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 19 \sr_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 47 \sr_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__is_32bit$82 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__is_32bit$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 20 \sr_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 48 \sr_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__is_signed$83 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__is_signed$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 11 \sr_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__oe__oe$74 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 39 \sr_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__oe__oe$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 12 \sr_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__oe__ok$75 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 40 \sr_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__oe__ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 16 \sr_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 44 \sr_op__output_carry$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__output_carry$79 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__output_carry$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 18 \sr_op__output_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 46 \sr_op__output_cr$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__output_cr$81 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__output_cr$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 10 \sr_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 38 \sr_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__rc__ok$73 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__rc__ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 9 \sr_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 37 \sr_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__rc__rc$72 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__rc__rc$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 13 \sr_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 41 \sr_op__write_cr0$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__write_cr0$76 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__write_cr0$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 output 28 \xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 input 54 \xer_ca$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 \xer_ca$63 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \xer_ca$94 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \xer_ca$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 29 \xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_ca_ok$95 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_ca_ok$96 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_ca_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 26 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 53 \xer_so$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so$91 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 27 \xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so_ok$92 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so_ok$93 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so_ok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" + cell $and $and$libresoc.v:169689$9153 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i$64 + connect \B \p_ready_o + connect \Y $and$libresoc.v:169689$9153_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:169744.15-169791.4" + cell \input$113 \input + connect \muxid \input_muxid + connect \muxid$1 \input_muxid$21 + connect \ra \input_ra + connect \ra$19 \input_ra$39 + connect \rb \input_rb + connect \rb$20 \input_rb$40 + connect \rc \input_rc + connect \rc$21 \input_rc$41 + connect \sr_op__fn_unit \input_sr_op__fn_unit + connect \sr_op__fn_unit$3 \input_sr_op__fn_unit$23 + connect \sr_op__imm_data__data \input_sr_op__imm_data__data + connect \sr_op__imm_data__data$4 \input_sr_op__imm_data__data$24 + connect \sr_op__imm_data__ok \input_sr_op__imm_data__ok + connect \sr_op__imm_data__ok$5 \input_sr_op__imm_data__ok$25 + connect \sr_op__input_carry \input_sr_op__input_carry + connect \sr_op__input_carry$12 \input_sr_op__input_carry$32 + connect \sr_op__input_cr \input_sr_op__input_cr + connect \sr_op__input_cr$14 \input_sr_op__input_cr$34 + connect \sr_op__insn \input_sr_op__insn + connect \sr_op__insn$18 \input_sr_op__insn$38 + connect \sr_op__insn_type \input_sr_op__insn_type + connect \sr_op__insn_type$2 \input_sr_op__insn_type$22 + connect \sr_op__invert_in \input_sr_op__invert_in + connect \sr_op__invert_in$11 \input_sr_op__invert_in$31 + connect \sr_op__is_32bit \input_sr_op__is_32bit + connect \sr_op__is_32bit$16 \input_sr_op__is_32bit$36 + connect \sr_op__is_signed \input_sr_op__is_signed + connect \sr_op__is_signed$17 \input_sr_op__is_signed$37 + connect \sr_op__oe__oe \input_sr_op__oe__oe + connect \sr_op__oe__oe$8 \input_sr_op__oe__oe$28 + connect \sr_op__oe__ok \input_sr_op__oe__ok + connect \sr_op__oe__ok$9 \input_sr_op__oe__ok$29 + connect \sr_op__output_carry \input_sr_op__output_carry + connect \sr_op__output_carry$13 \input_sr_op__output_carry$33 + connect \sr_op__output_cr \input_sr_op__output_cr + connect \sr_op__output_cr$15 \input_sr_op__output_cr$35 + connect \sr_op__rc__ok \input_sr_op__rc__ok + connect \sr_op__rc__ok$7 \input_sr_op__rc__ok$27 + connect \sr_op__rc__rc \input_sr_op__rc__rc + connect \sr_op__rc__rc$6 \input_sr_op__rc__rc$26 + connect \sr_op__write_cr0 \input_sr_op__write_cr0 + connect \sr_op__write_cr0$10 \input_sr_op__write_cr0$30 + connect \xer_ca \input_xer_ca + connect \xer_ca$23 \input_xer_ca$43 + connect \xer_so \input_xer_so + connect \xer_so$22 \input_xer_so$42 + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:169792.14-169837.4" + cell \main$114 \main + connect \muxid \main_muxid + connect \muxid$1 \main_muxid$44 + connect \o \main_o + connect \o_ok \main_o_ok + connect \ra \main_ra + connect \rb \main_rb + connect \rc \main_rc + connect \sr_op__fn_unit \main_sr_op__fn_unit + connect \sr_op__fn_unit$3 \main_sr_op__fn_unit$46 + connect \sr_op__imm_data__data \main_sr_op__imm_data__data + connect \sr_op__imm_data__data$4 \main_sr_op__imm_data__data$47 + connect \sr_op__imm_data__ok \main_sr_op__imm_data__ok + connect \sr_op__imm_data__ok$5 \main_sr_op__imm_data__ok$48 + connect \sr_op__input_carry \main_sr_op__input_carry + connect \sr_op__input_carry$12 \main_sr_op__input_carry$55 + connect \sr_op__input_cr \main_sr_op__input_cr + connect \sr_op__input_cr$14 \main_sr_op__input_cr$57 + connect \sr_op__insn \main_sr_op__insn + connect \sr_op__insn$18 \main_sr_op__insn$61 + connect \sr_op__insn_type \main_sr_op__insn_type + connect \sr_op__insn_type$2 \main_sr_op__insn_type$45 + connect \sr_op__invert_in \main_sr_op__invert_in + connect \sr_op__invert_in$11 \main_sr_op__invert_in$54 + connect \sr_op__is_32bit \main_sr_op__is_32bit + connect \sr_op__is_32bit$16 \main_sr_op__is_32bit$59 + connect \sr_op__is_signed \main_sr_op__is_signed + connect \sr_op__is_signed$17 \main_sr_op__is_signed$60 + connect \sr_op__oe__oe \main_sr_op__oe__oe + connect \sr_op__oe__oe$8 \main_sr_op__oe__oe$51 + connect \sr_op__oe__ok \main_sr_op__oe__ok + connect \sr_op__oe__ok$9 \main_sr_op__oe__ok$52 + connect \sr_op__output_carry \main_sr_op__output_carry + connect \sr_op__output_carry$13 \main_sr_op__output_carry$56 + connect \sr_op__output_cr \main_sr_op__output_cr + connect \sr_op__output_cr$15 \main_sr_op__output_cr$58 + connect \sr_op__rc__ok \main_sr_op__rc__ok + connect \sr_op__rc__ok$7 \main_sr_op__rc__ok$50 + connect \sr_op__rc__rc \main_sr_op__rc__rc + connect \sr_op__rc__rc$6 \main_sr_op__rc__rc$49 + connect \sr_op__write_cr0 \main_sr_op__write_cr0 + connect \sr_op__write_cr0$10 \main_sr_op__write_cr0$53 + connect \xer_ca \main_xer_ca + connect \xer_so \main_xer_so + connect \xer_so$19 \main_xer_so$62 + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:169838.11-169841.4" + cell \n$112 \n + connect \n_ready_i \n_ready_i + connect \n_valid_o \n_valid_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:169842.11-169845.4" + cell \p$111 \p + connect \p_ready_o \p_ready_o + connect \p_valid_i \p_valid_i + end + attribute \src "libresoc.v:168602.7-168602.20" + process $proc$libresoc.v:168602$9253 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:168611.13-168611.24" + process $proc$libresoc.v:168611$9254 + assign { } { } + assign $1\cr_a[3:0] 4'0000 + sync always + sync init + update \cr_a $1\cr_a[3:0] + end + attribute \src "libresoc.v:168620.7-168620.21" + process $proc$libresoc.v:168620$9255 + assign { } { } + assign $1\cr_a_ok[0:0] 1'0 + sync always + sync init + update \cr_a_ok $1\cr_a_ok[0:0] + end + attribute \src "libresoc.v:169177.13-169177.25" + process $proc$libresoc.v:169177$9256 + assign { } { } + assign $1\muxid[1:0] 2'00 + sync always + sync init + update \muxid $1\muxid[1:0] + end + attribute \src "libresoc.v:169192.14-169192.38" + process $proc$libresoc.v:169192$9257 + assign { } { } + assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \o $1\o[63:0] + end + attribute \src "libresoc.v:169199.7-169199.18" + process $proc$libresoc.v:169199$9258 + assign { } { } + assign $1\o_ok[0:0] 1'0 + sync always + sync init + update \o_ok $1\o_ok[0:0] + end + attribute \src "libresoc.v:169213.7-169213.20" + process $proc$libresoc.v:169213$9259 + assign { } { } + assign $1\r_busy[0:0] 1'0 + sync always + sync init + update \r_busy $1\r_busy[0:0] + end + attribute \src "libresoc.v:169238.14-169238.39" + process $proc$libresoc.v:169238$9260 + assign { } { } + assign $1\sr_op__fn_unit[12:0] 13'0000000000000 + sync always + sync init + update \sr_op__fn_unit $1\sr_op__fn_unit[12:0] + end + attribute \src "libresoc.v:169275.14-169275.58" + process $proc$libresoc.v:169275$9261 + assign { } { } + assign $1\sr_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \sr_op__imm_data__data $1\sr_op__imm_data__data[63:0] + end + attribute \src "libresoc.v:169284.7-169284.33" + process $proc$libresoc.v:169284$9262 + assign { } { } + assign $1\sr_op__imm_data__ok[0:0] 1'0 + sync always + sync init + update \sr_op__imm_data__ok $1\sr_op__imm_data__ok[0:0] + end + attribute \src "libresoc.v:169297.13-169297.38" + process $proc$libresoc.v:169297$9263 + assign { } { } + assign $1\sr_op__input_carry[1:0] 2'00 + sync always + sync init + update \sr_op__input_carry $1\sr_op__input_carry[1:0] + end + attribute \src "libresoc.v:169314.7-169314.29" + process $proc$libresoc.v:169314$9264 + assign { } { } + assign $1\sr_op__input_cr[0:0] 1'0 + sync always + sync init + update \sr_op__input_cr $1\sr_op__input_cr[0:0] + end + attribute \src "libresoc.v:169323.14-169323.33" + process $proc$libresoc.v:169323$9265 + assign { } { } + assign $1\sr_op__insn[31:0] 0 + sync always + sync init + update \sr_op__insn $1\sr_op__insn[31:0] + end + attribute \src "libresoc.v:169406.13-169406.37" + process $proc$libresoc.v:169406$9266 + assign { } { } + assign $1\sr_op__insn_type[6:0] 7'0000000 + sync always + sync init + update \sr_op__insn_type $1\sr_op__insn_type[6:0] + end + attribute \src "libresoc.v:169563.7-169563.30" + process $proc$libresoc.v:169563$9267 + assign { } { } + assign $1\sr_op__invert_in[0:0] 1'0 + sync always + sync init + update \sr_op__invert_in $1\sr_op__invert_in[0:0] + end + attribute \src "libresoc.v:169572.7-169572.29" + process $proc$libresoc.v:169572$9268 + assign { } { } + assign $1\sr_op__is_32bit[0:0] 1'0 + sync always + sync init + update \sr_op__is_32bit $1\sr_op__is_32bit[0:0] + end + attribute \src "libresoc.v:169581.7-169581.30" + process $proc$libresoc.v:169581$9269 + assign { } { } + assign $1\sr_op__is_signed[0:0] 1'0 + sync always + sync init + update \sr_op__is_signed $1\sr_op__is_signed[0:0] + end + attribute \src "libresoc.v:169590.7-169590.27" + process $proc$libresoc.v:169590$9270 + assign { } { } + assign $1\sr_op__oe__oe[0:0] 1'0 + sync always + sync init + update \sr_op__oe__oe $1\sr_op__oe__oe[0:0] + end + attribute \src "libresoc.v:169599.7-169599.27" + process $proc$libresoc.v:169599$9271 + assign { } { } + assign $1\sr_op__oe__ok[0:0] 1'0 + sync always + sync init + update \sr_op__oe__ok $1\sr_op__oe__ok[0:0] + end + attribute \src "libresoc.v:169608.7-169608.33" + process $proc$libresoc.v:169608$9272 + assign { } { } + assign $1\sr_op__output_carry[0:0] 1'0 + sync always + sync init + update \sr_op__output_carry $1\sr_op__output_carry[0:0] + end + attribute \src "libresoc.v:169617.7-169617.30" + process $proc$libresoc.v:169617$9273 + assign { } { } + assign $1\sr_op__output_cr[0:0] 1'0 + sync always + sync init + update \sr_op__output_cr $1\sr_op__output_cr[0:0] + end + attribute \src "libresoc.v:169626.7-169626.27" + process $proc$libresoc.v:169626$9274 + assign { } { } + assign $1\sr_op__rc__ok[0:0] 1'0 + sync always + sync init + update \sr_op__rc__ok $1\sr_op__rc__ok[0:0] + end + attribute \src "libresoc.v:169635.7-169635.27" + process $proc$libresoc.v:169635$9275 + assign { } { } + assign $1\sr_op__rc__rc[0:0] 1'0 + sync always + sync init + update \sr_op__rc__rc $1\sr_op__rc__rc[0:0] + end + attribute \src "libresoc.v:169644.7-169644.30" + process $proc$libresoc.v:169644$9276 + assign { } { } + assign $1\sr_op__write_cr0[0:0] 1'0 + sync always + sync init + update \sr_op__write_cr0 $1\sr_op__write_cr0[0:0] + end + attribute \src "libresoc.v:169653.13-169653.26" + process $proc$libresoc.v:169653$9277 + assign { } { } + assign $1\xer_ca[1:0] 2'00 + sync always + sync init + update \xer_ca $1\xer_ca[1:0] + end + attribute \src "libresoc.v:169664.7-169664.23" + process $proc$libresoc.v:169664$9278 + assign { } { } + assign $1\xer_ca_ok[0:0] 1'0 + sync always + sync init + update \xer_ca_ok $1\xer_ca_ok[0:0] + end + attribute \src "libresoc.v:169673.7-169673.20" + process $proc$libresoc.v:169673$9279 + assign { } { } + assign $1\xer_so[0:0] 1'0 + sync always + sync init + update \xer_so $1\xer_so[0:0] + end + attribute \src "libresoc.v:169682.7-169682.23" + process $proc$libresoc.v:169682$9280 + assign { } { } + assign $1\xer_so_ok[0:0] 1'0 + sync always + sync init + update \xer_so_ok $1\xer_so_ok[0:0] + end + attribute \src "libresoc.v:169690.3-169691.29" + process $proc$libresoc.v:169690$9154 + assign { } { } + assign $0\xer_ca[1:0] \xer_ca$next + sync posedge \coresync_clk + update \xer_ca $0\xer_ca[1:0] + end + attribute \src "libresoc.v:169692.3-169693.35" + process $proc$libresoc.v:169692$9155 + assign { } { } + assign $0\xer_ca_ok[0:0] \xer_ca_ok$next + sync posedge \coresync_clk + update \xer_ca_ok $0\xer_ca_ok[0:0] + end + attribute \src "libresoc.v:169694.3-169695.29" + process $proc$libresoc.v:169694$9156 + assign { } { } + assign $0\xer_so[0:0] \xer_so$next + sync posedge \coresync_clk + update \xer_so $0\xer_so[0:0] + end + attribute \src "libresoc.v:169696.3-169697.35" + process $proc$libresoc.v:169696$9157 + assign { } { } + assign $0\xer_so_ok[0:0] \xer_so_ok$next + sync posedge \coresync_clk + update \xer_so_ok $0\xer_so_ok[0:0] + end + attribute \src "libresoc.v:169698.3-169699.25" + process $proc$libresoc.v:169698$9158 + assign { } { } + assign $0\cr_a[3:0] \cr_a$next + sync posedge \coresync_clk + update \cr_a $0\cr_a[3:0] + end + attribute \src "libresoc.v:169700.3-169701.31" + process $proc$libresoc.v:169700$9159 + assign { } { } + assign $0\cr_a_ok[0:0] \cr_a_ok$next + sync posedge \coresync_clk + update \cr_a_ok $0\cr_a_ok[0:0] + end + attribute \src "libresoc.v:169702.3-169703.19" + process $proc$libresoc.v:169702$9160 + assign { } { } + assign $0\o[63:0] \o$next + sync posedge \coresync_clk + update \o $0\o[63:0] + end + attribute \src "libresoc.v:169704.3-169705.25" + process $proc$libresoc.v:169704$9161 + assign { } { } + assign $0\o_ok[0:0] \o_ok$next + sync posedge \coresync_clk + update \o_ok $0\o_ok[0:0] + end + attribute \src "libresoc.v:169706.3-169707.49" + process $proc$libresoc.v:169706$9162 + assign { } { } + assign $0\sr_op__insn_type[6:0] \sr_op__insn_type$next + sync posedge \coresync_clk + update \sr_op__insn_type $0\sr_op__insn_type[6:0] + end + attribute \src "libresoc.v:169708.3-169709.45" + process $proc$libresoc.v:169708$9163 + assign { } { } + assign $0\sr_op__fn_unit[12:0] \sr_op__fn_unit$next + sync posedge \coresync_clk + update \sr_op__fn_unit $0\sr_op__fn_unit[12:0] + end + attribute \src "libresoc.v:169710.3-169711.59" + process $proc$libresoc.v:169710$9164 + assign { } { } + assign $0\sr_op__imm_data__data[63:0] \sr_op__imm_data__data$next + sync posedge \coresync_clk + update \sr_op__imm_data__data $0\sr_op__imm_data__data[63:0] + end + attribute \src "libresoc.v:169712.3-169713.55" + process $proc$libresoc.v:169712$9165 + assign { } { } + assign $0\sr_op__imm_data__ok[0:0] \sr_op__imm_data__ok$next + sync posedge \coresync_clk + update \sr_op__imm_data__ok $0\sr_op__imm_data__ok[0:0] + end + attribute \src "libresoc.v:169714.3-169715.43" + process $proc$libresoc.v:169714$9166 + assign { } { } + assign $0\sr_op__rc__rc[0:0] \sr_op__rc__rc$next + sync posedge \coresync_clk + update \sr_op__rc__rc $0\sr_op__rc__rc[0:0] + end + attribute \src "libresoc.v:169716.3-169717.43" + process $proc$libresoc.v:169716$9167 + assign { } { } + assign $0\sr_op__rc__ok[0:0] \sr_op__rc__ok$next + sync posedge \coresync_clk + update \sr_op__rc__ok $0\sr_op__rc__ok[0:0] + end + attribute \src "libresoc.v:169718.3-169719.43" + process $proc$libresoc.v:169718$9168 + assign { } { } + assign $0\sr_op__oe__oe[0:0] \sr_op__oe__oe$next + sync posedge \coresync_clk + update \sr_op__oe__oe $0\sr_op__oe__oe[0:0] + end + attribute \src "libresoc.v:169720.3-169721.43" + process $proc$libresoc.v:169720$9169 + assign { } { } + assign $0\sr_op__oe__ok[0:0] \sr_op__oe__ok$next + sync posedge \coresync_clk + update \sr_op__oe__ok $0\sr_op__oe__ok[0:0] + end + attribute \src "libresoc.v:169722.3-169723.49" + process $proc$libresoc.v:169722$9170 + assign { } { } + assign $0\sr_op__write_cr0[0:0] \sr_op__write_cr0$next + sync posedge \coresync_clk + update \sr_op__write_cr0 $0\sr_op__write_cr0[0:0] + end + attribute \src "libresoc.v:169724.3-169725.49" + process $proc$libresoc.v:169724$9171 + assign { } { } + assign $0\sr_op__invert_in[0:0] \sr_op__invert_in$next + sync posedge \coresync_clk + update \sr_op__invert_in $0\sr_op__invert_in[0:0] + end + attribute \src "libresoc.v:169726.3-169727.53" + process $proc$libresoc.v:169726$9172 + assign { } { } + assign $0\sr_op__input_carry[1:0] \sr_op__input_carry$next + sync posedge \coresync_clk + update \sr_op__input_carry $0\sr_op__input_carry[1:0] + end + attribute \src "libresoc.v:169728.3-169729.55" + process $proc$libresoc.v:169728$9173 + assign { } { } + assign $0\sr_op__output_carry[0:0] \sr_op__output_carry$next + sync posedge \coresync_clk + update \sr_op__output_carry $0\sr_op__output_carry[0:0] + end + attribute \src "libresoc.v:169730.3-169731.47" + process $proc$libresoc.v:169730$9174 + assign { } { } + assign $0\sr_op__input_cr[0:0] \sr_op__input_cr$next + sync posedge \coresync_clk + update \sr_op__input_cr $0\sr_op__input_cr[0:0] + end + attribute \src "libresoc.v:169732.3-169733.49" + process $proc$libresoc.v:169732$9175 + assign { } { } + assign $0\sr_op__output_cr[0:0] \sr_op__output_cr$next + sync posedge \coresync_clk + update \sr_op__output_cr $0\sr_op__output_cr[0:0] + end + attribute \src "libresoc.v:169734.3-169735.47" + process $proc$libresoc.v:169734$9176 + assign { } { } + assign $0\sr_op__is_32bit[0:0] \sr_op__is_32bit$next + sync posedge \coresync_clk + update \sr_op__is_32bit $0\sr_op__is_32bit[0:0] + end + attribute \src "libresoc.v:169736.3-169737.49" + process $proc$libresoc.v:169736$9177 + assign { } { } + assign $0\sr_op__is_signed[0:0] \sr_op__is_signed$next + sync posedge \coresync_clk + update \sr_op__is_signed $0\sr_op__is_signed[0:0] + end + attribute \src "libresoc.v:169738.3-169739.39" + process $proc$libresoc.v:169738$9178 + assign { } { } + assign $0\sr_op__insn[31:0] \sr_op__insn$next + sync posedge \coresync_clk + update \sr_op__insn $0\sr_op__insn[31:0] + end + attribute \src "libresoc.v:169740.3-169741.27" + process $proc$libresoc.v:169740$9179 + assign { } { } + assign $0\muxid[1:0] \muxid$next + sync posedge \coresync_clk + update \muxid $0\muxid[1:0] + end + attribute \src "libresoc.v:169742.3-169743.29" + process $proc$libresoc.v:169742$9180 + assign { } { } + assign $0\r_busy[0:0] \r_busy$next + sync posedge \coresync_clk + update \r_busy $0\r_busy[0:0] + end + attribute \src "libresoc.v:169846.3-169864.6" + process $proc$libresoc.v:169846$9181 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\xer_ca$next[1:0]$9183 $1\xer_ca$next[1:0]$9185 + assign $0\xer_ca_ok$next[0:0]$9182 $2\xer_ca_ok$next[0:0]$9186 + attribute \src "libresoc.v:169847.5-169847.29" + switch \initial + attribute \src "libresoc.v:169847.9-169847.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\xer_ca_ok$next[0:0]$9184 $1\xer_ca$next[1:0]$9185 } { \xer_ca_ok$95 \xer_ca$94 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\xer_ca_ok$next[0:0]$9184 $1\xer_ca$next[1:0]$9185 } { \xer_ca_ok$95 \xer_ca$94 } + case + assign $1\xer_ca_ok$next[0:0]$9184 \xer_ca_ok + assign $1\xer_ca$next[1:0]$9185 \xer_ca + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\xer_ca_ok$next[0:0]$9186 1'0 + case + assign $2\xer_ca_ok$next[0:0]$9186 $1\xer_ca_ok$next[0:0]$9184 + end + sync always + update \xer_ca_ok$next $0\xer_ca_ok$next[0:0]$9182 + update \xer_ca$next $0\xer_ca$next[1:0]$9183 + end + attribute \src "libresoc.v:169865.3-169882.6" + process $proc$libresoc.v:169865$9187 + assign { } { } + assign { } { } + assign { } { } + assign $0\r_busy$next[0:0]$9188 $2\r_busy$next[0:0]$9190 + attribute \src "libresoc.v:169866.5-169866.29" + switch \initial + attribute \src "libresoc.v:169866.9-169866.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\r_busy$next[0:0]$9189 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\r_busy$next[0:0]$9189 1'0 + case + assign $1\r_busy$next[0:0]$9189 \r_busy + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r_busy$next[0:0]$9190 1'0 + case + assign $2\r_busy$next[0:0]$9190 $1\r_busy$next[0:0]$9189 + end + sync always + update \r_busy$next $0\r_busy$next[0:0]$9188 + end + attribute \src "libresoc.v:169883.3-169895.6" + process $proc$libresoc.v:169883$9191 + assign { } { } + assign { } { } + assign $0\muxid$next[1:0]$9192 $1\muxid$next[1:0]$9193 + attribute \src "libresoc.v:169884.5-169884.29" + switch \initial + attribute \src "libresoc.v:169884.9-169884.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\muxid$next[1:0]$9193 \muxid$67 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\muxid$next[1:0]$9193 \muxid$67 + case + assign $1\muxid$next[1:0]$9193 \muxid + end + sync always + update \muxid$next $0\muxid$next[1:0]$9192 + end + attribute \src "libresoc.v:169896.3-169936.6" + process $proc$libresoc.v:169896$9194 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\sr_op__fn_unit$next[12:0]$9195 $1\sr_op__fn_unit$next[12:0]$9212 + assign { } { } + assign { } { } + assign $0\sr_op__input_carry$next[1:0]$9198 $1\sr_op__input_carry$next[1:0]$9215 + assign $0\sr_op__input_cr$next[0:0]$9199 $1\sr_op__input_cr$next[0:0]$9216 + assign $0\sr_op__insn$next[31:0]$9200 $1\sr_op__insn$next[31:0]$9217 + assign $0\sr_op__insn_type$next[6:0]$9201 $1\sr_op__insn_type$next[6:0]$9218 + assign $0\sr_op__invert_in$next[0:0]$9202 $1\sr_op__invert_in$next[0:0]$9219 + assign $0\sr_op__is_32bit$next[0:0]$9203 $1\sr_op__is_32bit$next[0:0]$9220 + assign $0\sr_op__is_signed$next[0:0]$9204 $1\sr_op__is_signed$next[0:0]$9221 + assign { } { } + assign { } { } + assign $0\sr_op__output_carry$next[0:0]$9207 $1\sr_op__output_carry$next[0:0]$9224 + assign $0\sr_op__output_cr$next[0:0]$9208 $1\sr_op__output_cr$next[0:0]$9225 + assign { } { } + assign { } { } + assign $0\sr_op__write_cr0$next[0:0]$9211 $1\sr_op__write_cr0$next[0:0]$9228 + assign $0\sr_op__imm_data__data$next[63:0]$9196 $2\sr_op__imm_data__data$next[63:0]$9229 + assign $0\sr_op__imm_data__ok$next[0:0]$9197 $2\sr_op__imm_data__ok$next[0:0]$9230 + assign $0\sr_op__oe__oe$next[0:0]$9205 $2\sr_op__oe__oe$next[0:0]$9231 + assign $0\sr_op__oe__ok$next[0:0]$9206 $2\sr_op__oe__ok$next[0:0]$9232 + assign $0\sr_op__rc__ok$next[0:0]$9209 $2\sr_op__rc__ok$next[0:0]$9233 + assign $0\sr_op__rc__rc$next[0:0]$9210 $2\sr_op__rc__rc$next[0:0]$9234 + attribute \src "libresoc.v:169897.5-169897.29" + switch \initial + attribute \src "libresoc.v:169897.9-169897.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\sr_op__insn$next[31:0]$9217 $1\sr_op__is_signed$next[0:0]$9221 $1\sr_op__is_32bit$next[0:0]$9220 $1\sr_op__output_cr$next[0:0]$9225 $1\sr_op__input_cr$next[0:0]$9216 $1\sr_op__output_carry$next[0:0]$9224 $1\sr_op__input_carry$next[1:0]$9215 $1\sr_op__invert_in$next[0:0]$9219 $1\sr_op__write_cr0$next[0:0]$9228 $1\sr_op__oe__ok$next[0:0]$9223 $1\sr_op__oe__oe$next[0:0]$9222 $1\sr_op__rc__ok$next[0:0]$9226 $1\sr_op__rc__rc$next[0:0]$9227 $1\sr_op__imm_data__ok$next[0:0]$9214 $1\sr_op__imm_data__data$next[63:0]$9213 $1\sr_op__fn_unit$next[12:0]$9212 $1\sr_op__insn_type$next[6:0]$9218 } { \sr_op__insn$84 \sr_op__is_signed$83 \sr_op__is_32bit$82 \sr_op__output_cr$81 \sr_op__input_cr$80 \sr_op__output_carry$79 \sr_op__input_carry$78 \sr_op__invert_in$77 \sr_op__write_cr0$76 \sr_op__oe__ok$75 \sr_op__oe__oe$74 \sr_op__rc__ok$73 \sr_op__rc__rc$72 \sr_op__imm_data__ok$71 \sr_op__imm_data__data$70 \sr_op__fn_unit$69 \sr_op__insn_type$68 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\sr_op__insn$next[31:0]$9217 $1\sr_op__is_signed$next[0:0]$9221 $1\sr_op__is_32bit$next[0:0]$9220 $1\sr_op__output_cr$next[0:0]$9225 $1\sr_op__input_cr$next[0:0]$9216 $1\sr_op__output_carry$next[0:0]$9224 $1\sr_op__input_carry$next[1:0]$9215 $1\sr_op__invert_in$next[0:0]$9219 $1\sr_op__write_cr0$next[0:0]$9228 $1\sr_op__oe__ok$next[0:0]$9223 $1\sr_op__oe__oe$next[0:0]$9222 $1\sr_op__rc__ok$next[0:0]$9226 $1\sr_op__rc__rc$next[0:0]$9227 $1\sr_op__imm_data__ok$next[0:0]$9214 $1\sr_op__imm_data__data$next[63:0]$9213 $1\sr_op__fn_unit$next[12:0]$9212 $1\sr_op__insn_type$next[6:0]$9218 } { \sr_op__insn$84 \sr_op__is_signed$83 \sr_op__is_32bit$82 \sr_op__output_cr$81 \sr_op__input_cr$80 \sr_op__output_carry$79 \sr_op__input_carry$78 \sr_op__invert_in$77 \sr_op__write_cr0$76 \sr_op__oe__ok$75 \sr_op__oe__oe$74 \sr_op__rc__ok$73 \sr_op__rc__rc$72 \sr_op__imm_data__ok$71 \sr_op__imm_data__data$70 \sr_op__fn_unit$69 \sr_op__insn_type$68 } + case + assign $1\sr_op__fn_unit$next[12:0]$9212 \sr_op__fn_unit + assign $1\sr_op__imm_data__data$next[63:0]$9213 \sr_op__imm_data__data + assign $1\sr_op__imm_data__ok$next[0:0]$9214 \sr_op__imm_data__ok + assign $1\sr_op__input_carry$next[1:0]$9215 \sr_op__input_carry + assign $1\sr_op__input_cr$next[0:0]$9216 \sr_op__input_cr + assign $1\sr_op__insn$next[31:0]$9217 \sr_op__insn + assign $1\sr_op__insn_type$next[6:0]$9218 \sr_op__insn_type + assign $1\sr_op__invert_in$next[0:0]$9219 \sr_op__invert_in + assign $1\sr_op__is_32bit$next[0:0]$9220 \sr_op__is_32bit + assign $1\sr_op__is_signed$next[0:0]$9221 \sr_op__is_signed + assign $1\sr_op__oe__oe$next[0:0]$9222 \sr_op__oe__oe + assign $1\sr_op__oe__ok$next[0:0]$9223 \sr_op__oe__ok + assign $1\sr_op__output_carry$next[0:0]$9224 \sr_op__output_carry + assign $1\sr_op__output_cr$next[0:0]$9225 \sr_op__output_cr + assign $1\sr_op__rc__ok$next[0:0]$9226 \sr_op__rc__ok + assign $1\sr_op__rc__rc$next[0:0]$9227 \sr_op__rc__rc + assign $1\sr_op__write_cr0$next[0:0]$9228 \sr_op__write_cr0 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $2\sr_op__imm_data__data$next[63:0]$9229 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\sr_op__imm_data__ok$next[0:0]$9230 1'0 + assign $2\sr_op__rc__rc$next[0:0]$9234 1'0 + assign $2\sr_op__rc__ok$next[0:0]$9233 1'0 + assign $2\sr_op__oe__oe$next[0:0]$9231 1'0 + assign $2\sr_op__oe__ok$next[0:0]$9232 1'0 + case + assign $2\sr_op__imm_data__data$next[63:0]$9229 $1\sr_op__imm_data__data$next[63:0]$9213 + assign $2\sr_op__imm_data__ok$next[0:0]$9230 $1\sr_op__imm_data__ok$next[0:0]$9214 + assign $2\sr_op__oe__oe$next[0:0]$9231 $1\sr_op__oe__oe$next[0:0]$9222 + assign $2\sr_op__oe__ok$next[0:0]$9232 $1\sr_op__oe__ok$next[0:0]$9223 + assign $2\sr_op__rc__ok$next[0:0]$9233 $1\sr_op__rc__ok$next[0:0]$9226 + assign $2\sr_op__rc__rc$next[0:0]$9234 $1\sr_op__rc__rc$next[0:0]$9227 + end + sync always + update \sr_op__fn_unit$next $0\sr_op__fn_unit$next[12:0]$9195 + update \sr_op__imm_data__data$next $0\sr_op__imm_data__data$next[63:0]$9196 + update \sr_op__imm_data__ok$next $0\sr_op__imm_data__ok$next[0:0]$9197 + update \sr_op__input_carry$next $0\sr_op__input_carry$next[1:0]$9198 + update \sr_op__input_cr$next $0\sr_op__input_cr$next[0:0]$9199 + update \sr_op__insn$next $0\sr_op__insn$next[31:0]$9200 + update \sr_op__insn_type$next $0\sr_op__insn_type$next[6:0]$9201 + update \sr_op__invert_in$next $0\sr_op__invert_in$next[0:0]$9202 + update \sr_op__is_32bit$next $0\sr_op__is_32bit$next[0:0]$9203 + update \sr_op__is_signed$next $0\sr_op__is_signed$next[0:0]$9204 + update \sr_op__oe__oe$next $0\sr_op__oe__oe$next[0:0]$9205 + update \sr_op__oe__ok$next $0\sr_op__oe__ok$next[0:0]$9206 + update \sr_op__output_carry$next $0\sr_op__output_carry$next[0:0]$9207 + update \sr_op__output_cr$next $0\sr_op__output_cr$next[0:0]$9208 + update \sr_op__rc__ok$next $0\sr_op__rc__ok$next[0:0]$9209 + update \sr_op__rc__rc$next $0\sr_op__rc__rc$next[0:0]$9210 + update \sr_op__write_cr0$next $0\sr_op__write_cr0$next[0:0]$9211 + end + attribute \src "libresoc.v:169937.3-169955.6" + process $proc$libresoc.v:169937$9235 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\o$next[63:0]$9236 $1\o$next[63:0]$9238 + assign { } { } + assign $0\o_ok$next[0:0]$9237 $2\o_ok$next[0:0]$9240 + attribute \src "libresoc.v:169938.5-169938.29" + switch \initial + attribute \src "libresoc.v:169938.9-169938.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\o_ok$next[0:0]$9239 $1\o$next[63:0]$9238 } { \o_ok$86 \o$85 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\o_ok$next[0:0]$9239 $1\o$next[63:0]$9238 } { \o_ok$86 \o$85 } + case + assign $1\o$next[63:0]$9238 \o + assign $1\o_ok$next[0:0]$9239 \o_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\o_ok$next[0:0]$9240 1'0 + case + assign $2\o_ok$next[0:0]$9240 $1\o_ok$next[0:0]$9239 + end + sync always + update \o$next $0\o$next[63:0]$9236 + update \o_ok$next $0\o_ok$next[0:0]$9237 + end + attribute \src "libresoc.v:169956.3-169974.6" + process $proc$libresoc.v:169956$9241 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\cr_a$next[3:0]$9242 $1\cr_a$next[3:0]$9244 + assign { } { } + assign $0\cr_a_ok$next[0:0]$9243 $2\cr_a_ok$next[0:0]$9246 + attribute \src "libresoc.v:169957.5-169957.29" + switch \initial + attribute \src "libresoc.v:169957.9-169957.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\cr_a_ok$next[0:0]$9245 $1\cr_a$next[3:0]$9244 } { \cr_a_ok$88 \cr_a$87 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\cr_a_ok$next[0:0]$9245 $1\cr_a$next[3:0]$9244 } { \cr_a_ok$88 \cr_a$87 } + case + assign $1\cr_a$next[3:0]$9244 \cr_a + assign $1\cr_a_ok$next[0:0]$9245 \cr_a_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_a_ok$next[0:0]$9246 1'0 + case + assign $2\cr_a_ok$next[0:0]$9246 $1\cr_a_ok$next[0:0]$9245 + end + sync always + update \cr_a$next $0\cr_a$next[3:0]$9242 + update \cr_a_ok$next $0\cr_a_ok$next[0:0]$9243 + end + attribute \src "libresoc.v:169975.3-169993.6" + process $proc$libresoc.v:169975$9247 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\xer_so$next[0:0]$9248 $1\xer_so$next[0:0]$9250 + assign { } { } + assign $0\xer_so_ok$next[0:0]$9249 $2\xer_so_ok$next[0:0]$9252 + attribute \src "libresoc.v:169976.5-169976.29" + switch \initial + attribute \src "libresoc.v:169976.9-169976.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\xer_so_ok$next[0:0]$9251 $1\xer_so$next[0:0]$9250 } { \xer_so_ok$92 \xer_so$91 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\xer_so_ok$next[0:0]$9251 $1\xer_so$next[0:0]$9250 } { \xer_so_ok$92 \xer_so$91 } + case + assign $1\xer_so$next[0:0]$9250 \xer_so + assign $1\xer_so_ok$next[0:0]$9251 \xer_so_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\xer_so_ok$next[0:0]$9252 1'0 + case + assign $2\xer_so_ok$next[0:0]$9252 $1\xer_so_ok$next[0:0]$9251 + end + sync always + update \xer_so$next $0\xer_so$next[0:0]$9248 + update \xer_so_ok$next $0\xer_so_ok$next[0:0]$9249 + end + connect \$65 $and$libresoc.v:169689$9153_Y + connect \cr_a$89 4'0000 + connect \cr_a_ok$90 1'0 + connect \xer_so_ok$93 1'0 + connect \xer_ca_ok$96 1'0 + connect \p_ready_o \n_i_rdy_data + connect \n_valid_o \r_busy + connect { \xer_ca_ok$95 \xer_ca$94 } { 1'0 \main_xer_ca } + connect { \xer_so_ok$92 \xer_so$91 } { 1'0 \main_xer_so$62 } + connect { \cr_a_ok$88 \cr_a$87 } 5'00000 + connect { \o_ok$86 \o$85 } { \main_o_ok \main_o } + connect { \sr_op__insn$84 \sr_op__is_signed$83 \sr_op__is_32bit$82 \sr_op__output_cr$81 \sr_op__input_cr$80 \sr_op__output_carry$79 \sr_op__input_carry$78 \sr_op__invert_in$77 \sr_op__write_cr0$76 \sr_op__oe__ok$75 \sr_op__oe__oe$74 \sr_op__rc__ok$73 \sr_op__rc__rc$72 \sr_op__imm_data__ok$71 \sr_op__imm_data__data$70 \sr_op__fn_unit$69 \sr_op__insn_type$68 } { \main_sr_op__insn$61 \main_sr_op__is_signed$60 \main_sr_op__is_32bit$59 \main_sr_op__output_cr$58 \main_sr_op__input_cr$57 \main_sr_op__output_carry$56 \main_sr_op__input_carry$55 \main_sr_op__invert_in$54 \main_sr_op__write_cr0$53 \main_sr_op__oe__ok$52 \main_sr_op__oe__oe$51 \main_sr_op__rc__ok$50 \main_sr_op__rc__rc$49 \main_sr_op__imm_data__ok$48 \main_sr_op__imm_data__data$47 \main_sr_op__fn_unit$46 \main_sr_op__insn_type$45 } + connect \muxid$67 \main_muxid$44 + connect \p_valid_i_p_ready_o \$65 + connect \n_i_rdy_data \n_ready_i + connect \p_valid_i$64 \p_valid_i + connect \xer_ca$63 \input_xer_ca$43 + connect \main_xer_so \input_xer_so$42 + connect \main_rc \input_rc$41 + connect \main_rb \input_rb$40 + connect \main_ra \input_ra$39 + connect { \main_sr_op__insn \main_sr_op__is_signed \main_sr_op__is_32bit \main_sr_op__output_cr \main_sr_op__input_cr \main_sr_op__output_carry \main_sr_op__input_carry \main_sr_op__invert_in \main_sr_op__write_cr0 \main_sr_op__oe__ok \main_sr_op__oe__oe \main_sr_op__rc__ok \main_sr_op__rc__rc \main_sr_op__imm_data__ok \main_sr_op__imm_data__data \main_sr_op__fn_unit \main_sr_op__insn_type } { \input_sr_op__insn$38 \input_sr_op__is_signed$37 \input_sr_op__is_32bit$36 \input_sr_op__output_cr$35 \input_sr_op__input_cr$34 \input_sr_op__output_carry$33 \input_sr_op__input_carry$32 \input_sr_op__invert_in$31 \input_sr_op__write_cr0$30 \input_sr_op__oe__ok$29 \input_sr_op__oe__oe$28 \input_sr_op__rc__ok$27 \input_sr_op__rc__rc$26 \input_sr_op__imm_data__ok$25 \input_sr_op__imm_data__data$24 \input_sr_op__fn_unit$23 \input_sr_op__insn_type$22 } + connect \main_muxid \input_muxid$21 + connect \input_xer_ca \xer_ca$20 + connect \input_xer_so \xer_so$19 + connect \input_rc \rc + connect \input_rb \rb + connect \input_ra \ra + connect { \input_sr_op__insn \input_sr_op__is_signed \input_sr_op__is_32bit \input_sr_op__output_cr \input_sr_op__input_cr \input_sr_op__output_carry \input_sr_op__input_carry \input_sr_op__invert_in \input_sr_op__write_cr0 \input_sr_op__oe__ok \input_sr_op__oe__oe \input_sr_op__rc__ok \input_sr_op__rc__rc \input_sr_op__imm_data__ok \input_sr_op__imm_data__data \input_sr_op__fn_unit \input_sr_op__insn_type } { \sr_op__insn$18 \sr_op__is_signed$17 \sr_op__is_32bit$16 \sr_op__output_cr$15 \sr_op__input_cr$14 \sr_op__output_carry$13 \sr_op__input_carry$12 \sr_op__invert_in$11 \sr_op__write_cr0$10 \sr_op__oe__ok$9 \sr_op__oe__oe$8 \sr_op__rc__ok$7 \sr_op__rc__rc$6 \sr_op__imm_data__ok$5 \sr_op__imm_data__data$4 \sr_op__fn_unit$3 \sr_op__insn_type$2 } + connect \input_muxid \muxid$1 +end +attribute \src "libresoc.v:170027.1-170865.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.pipe1" +attribute \generator "nMigen" +module \pipe1$32 + attribute \src "libresoc.v:170822.3-170834.6" + wire width 64 $0\fast1$next[63:0]$9330 + attribute \src "libresoc.v:170678.3-170679.27" + wire width 64 $0\fast1[63:0] + attribute \src "libresoc.v:170835.3-170847.6" + wire width 64 $0\fast2$next[63:0]$9333 + attribute \src "libresoc.v:170676.3-170677.27" + wire width 64 $0\fast2[63:0] + attribute \src "libresoc.v:170028.7-170028.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:170762.3-170774.6" + wire width 2 $0\muxid$next[1:0]$9302 + attribute \src "libresoc.v:170702.3-170703.27" + wire width 2 $0\muxid[1:0] + attribute \src "libresoc.v:170744.3-170761.6" + wire $0\r_busy$next[0:0]$9298 + attribute \src "libresoc.v:170704.3-170705.29" + wire $0\r_busy[0:0] + attribute \src "libresoc.v:170796.3-170808.6" + wire width 64 $0\ra$next[63:0]$9324 + attribute \src "libresoc.v:170682.3-170683.21" + wire width 64 $0\ra[63:0] + attribute \src "libresoc.v:170809.3-170821.6" + wire width 64 $0\rb$next[63:0]$9327 + attribute \src "libresoc.v:170680.3-170681.21" + wire width 64 $0\rb[63:0] + attribute \src "libresoc.v:170775.3-170795.6" + wire width 64 $0\trap_op__cia$next[63:0]$9305 + attribute \src "libresoc.v:170692.3-170693.41" + wire width 64 $0\trap_op__cia[63:0] + attribute \src "libresoc.v:170775.3-170795.6" + wire width 13 $0\trap_op__fn_unit$next[12:0]$9306 + attribute \src "libresoc.v:170686.3-170687.49" + wire width 13 $0\trap_op__fn_unit[12:0] + attribute \src "libresoc.v:170775.3-170795.6" + wire width 32 $0\trap_op__insn$next[31:0]$9307 + attribute \src "libresoc.v:170688.3-170689.43" + wire width 32 $0\trap_op__insn[31:0] + attribute \src "libresoc.v:170775.3-170795.6" + wire width 7 $0\trap_op__insn_type$next[6:0]$9308 + attribute \src "libresoc.v:170684.3-170685.53" + wire width 7 $0\trap_op__insn_type[6:0] + attribute \src "libresoc.v:170775.3-170795.6" + wire $0\trap_op__is_32bit$next[0:0]$9309 + attribute \src "libresoc.v:170694.3-170695.51" + wire $0\trap_op__is_32bit[0:0] + attribute \src "libresoc.v:170775.3-170795.6" + wire width 8 $0\trap_op__ldst_exc$next[7:0]$9310 + attribute \src "libresoc.v:170700.3-170701.51" + wire width 8 $0\trap_op__ldst_exc[7:0] + attribute \src "libresoc.v:170775.3-170795.6" + wire width 64 $0\trap_op__msr$next[63:0]$9311 + attribute \src "libresoc.v:170690.3-170691.41" + wire width 64 $0\trap_op__msr[63:0] + attribute \src "libresoc.v:170775.3-170795.6" + wire width 13 $0\trap_op__trapaddr$next[12:0]$9312 + attribute \src "libresoc.v:170698.3-170699.51" + wire width 13 $0\trap_op__trapaddr[12:0] + attribute \src "libresoc.v:170775.3-170795.6" + wire width 8 $0\trap_op__traptype$next[7:0]$9313 + attribute \src "libresoc.v:170696.3-170697.51" + wire width 8 $0\trap_op__traptype[7:0] + attribute \src "libresoc.v:170822.3-170834.6" + wire width 64 $1\fast1$next[63:0]$9331 + attribute \src "libresoc.v:170269.14-170269.42" + wire width 64 $1\fast1[63:0] + attribute \src "libresoc.v:170835.3-170847.6" + wire width 64 $1\fast2$next[63:0]$9334 + attribute \src "libresoc.v:170278.14-170278.42" + wire width 64 $1\fast2[63:0] + attribute \src "libresoc.v:170762.3-170774.6" + wire width 2 $1\muxid$next[1:0]$9303 + attribute \src "libresoc.v:170287.13-170287.25" + wire width 2 $1\muxid[1:0] + attribute \src "libresoc.v:170744.3-170761.6" + wire $1\r_busy$next[0:0]$9299 + attribute \src "libresoc.v:170309.7-170309.20" + wire $1\r_busy[0:0] + attribute \src "libresoc.v:170796.3-170808.6" + wire width 64 $1\ra$next[63:0]$9325 + attribute \src "libresoc.v:170314.14-170314.39" + wire width 64 $1\ra[63:0] + attribute \src "libresoc.v:170809.3-170821.6" + wire width 64 $1\rb$next[63:0]$9328 + attribute \src "libresoc.v:170323.14-170323.39" + wire width 64 $1\rb[63:0] + attribute \src "libresoc.v:170775.3-170795.6" + wire width 64 $1\trap_op__cia$next[63:0]$9314 + attribute \src "libresoc.v:170332.14-170332.49" + wire width 64 $1\trap_op__cia[63:0] + attribute \src "libresoc.v:170775.3-170795.6" + wire width 13 $1\trap_op__fn_unit$next[12:0]$9315 + attribute \src "libresoc.v:170355.14-170355.41" + wire width 13 $1\trap_op__fn_unit[12:0] + attribute \src "libresoc.v:170775.3-170795.6" + wire width 32 $1\trap_op__insn$next[31:0]$9316 + attribute \src "libresoc.v:170392.14-170392.35" + wire width 32 $1\trap_op__insn[31:0] + attribute \src "libresoc.v:170775.3-170795.6" + wire width 7 $1\trap_op__insn_type$next[6:0]$9317 + attribute \src "libresoc.v:170475.13-170475.39" + wire width 7 $1\trap_op__insn_type[6:0] + attribute \src "libresoc.v:170775.3-170795.6" + wire $1\trap_op__is_32bit$next[0:0]$9318 + attribute \src "libresoc.v:170632.7-170632.31" + wire $1\trap_op__is_32bit[0:0] + attribute \src "libresoc.v:170775.3-170795.6" + wire width 8 $1\trap_op__ldst_exc$next[7:0]$9319 + attribute \src "libresoc.v:170641.13-170641.38" + wire width 8 $1\trap_op__ldst_exc[7:0] + attribute \src "libresoc.v:170775.3-170795.6" + wire width 64 $1\trap_op__msr$next[63:0]$9320 + attribute \src "libresoc.v:170650.14-170650.49" + wire width 64 $1\trap_op__msr[63:0] + attribute \src "libresoc.v:170775.3-170795.6" + wire width 13 $1\trap_op__trapaddr$next[12:0]$9321 + attribute \src "libresoc.v:170659.14-170659.42" + wire width 13 $1\trap_op__trapaddr[12:0] + attribute \src "libresoc.v:170775.3-170795.6" + wire width 8 $1\trap_op__traptype$next[7:0]$9322 + attribute \src "libresoc.v:170668.13-170668.38" + wire width 8 $1\trap_op__traptype[7:0] + attribute \src "libresoc.v:170744.3-170761.6" + wire $2\r_busy$next[0:0]$9300 + attribute \src "libresoc.v:170675.18-170675.118" + wire $and$libresoc.v:170675$9281_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" + wire \$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 34 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \dummy_fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \dummy_fast1$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \dummy_fast2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \dummy_fast2$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \dummy_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \dummy_muxid$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \dummy_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \dummy_ra$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \dummy_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \dummy_rb$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \dummy_trap_op__cia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \dummy_trap_op__cia$20 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \dummy_trap_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \dummy_trap_op__fn_unit$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \dummy_trap_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \dummy_trap_op__insn$18 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + 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\enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 21 \trap_op__insn_type$2 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \trap_op__insn_type$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \trap_op__insn_type$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 10 \trap_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \trap_op__is_32bit$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 26 \trap_op__is_32bit$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \trap_op__is_32bit$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 8 output 13 \trap_op__ldst_exc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 8 input 29 \trap_op__ldst_exc$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 8 \trap_op__ldst_exc$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 8 \trap_op__ldst_exc$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 8 \trap_op__msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \trap_op__msr$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 24 \trap_op__msr$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \trap_op__msr$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 output 12 \trap_op__trapaddr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \trap_op__trapaddr$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 input 28 \trap_op__trapaddr$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \trap_op__trapaddr$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 8 output 11 \trap_op__traptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 8 \trap_op__traptype$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 8 input 27 \trap_op__traptype$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 8 \trap_op__traptype$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" + cell $and $and$libresoc.v:170675$9281 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i$29 + connect \B \p_ready_o + connect \Y $and$libresoc.v:170675$9281_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:170706.9-170735.4" + cell \dummy \dummy + connect \fast1 \dummy_fast1 + connect \fast1$13 \dummy_fast1$27 + connect \fast2 \dummy_fast2 + connect \fast2$14 \dummy_fast2$28 + connect \muxid \dummy_muxid + connect \muxid$1 \dummy_muxid$15 + connect \ra \dummy_ra + connect \ra$11 \dummy_ra$25 + connect \rb \dummy_rb + connect \rb$12 \dummy_rb$26 + connect \trap_op__cia \dummy_trap_op__cia + connect \trap_op__cia$6 \dummy_trap_op__cia$20 + connect \trap_op__fn_unit \dummy_trap_op__fn_unit + connect \trap_op__fn_unit$3 \dummy_trap_op__fn_unit$17 + connect \trap_op__insn \dummy_trap_op__insn + connect \trap_op__insn$4 \dummy_trap_op__insn$18 + connect \trap_op__insn_type \dummy_trap_op__insn_type + connect \trap_op__insn_type$2 \dummy_trap_op__insn_type$16 + connect \trap_op__is_32bit \dummy_trap_op__is_32bit + connect \trap_op__is_32bit$7 \dummy_trap_op__is_32bit$21 + connect \trap_op__ldst_exc \dummy_trap_op__ldst_exc + connect \trap_op__ldst_exc$10 \dummy_trap_op__ldst_exc$24 + connect \trap_op__msr \dummy_trap_op__msr + connect \trap_op__msr$5 \dummy_trap_op__msr$19 + connect \trap_op__trapaddr \dummy_trap_op__trapaddr + connect \trap_op__trapaddr$9 \dummy_trap_op__trapaddr$23 + connect \trap_op__traptype \dummy_trap_op__traptype + connect \trap_op__traptype$8 \dummy_trap_op__traptype$22 + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:170736.10-170739.4" + cell \n$34 \n + connect \n_ready_i \n_ready_i + connect \n_valid_o \n_valid_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:170740.10-170743.4" + cell \p$33 \p + connect \p_ready_o \p_ready_o + connect \p_valid_i \p_valid_i + end + attribute \src "libresoc.v:170028.7-170028.20" + process $proc$libresoc.v:170028$9335 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:170269.14-170269.42" + process $proc$libresoc.v:170269$9336 + assign { } { } + assign $1\fast1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \fast1 $1\fast1[63:0] + end + attribute \src "libresoc.v:170278.14-170278.42" + process $proc$libresoc.v:170278$9337 + assign { } { } + assign $1\fast2[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \fast2 $1\fast2[63:0] + end + attribute \src "libresoc.v:170287.13-170287.25" + process $proc$libresoc.v:170287$9338 + assign { } { } + assign $1\muxid[1:0] 2'00 + sync always + sync init + update \muxid $1\muxid[1:0] + end + attribute \src "libresoc.v:170309.7-170309.20" + process $proc$libresoc.v:170309$9339 + assign { } { } + assign $1\r_busy[0:0] 1'0 + sync always + sync init + update \r_busy $1\r_busy[0:0] + end + attribute \src "libresoc.v:170314.14-170314.39" + process $proc$libresoc.v:170314$9340 + assign { } { } + assign $1\ra[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \ra $1\ra[63:0] + end + attribute \src "libresoc.v:170323.14-170323.39" + process $proc$libresoc.v:170323$9341 + assign { } { } + assign $1\rb[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \rb $1\rb[63:0] + end + attribute \src "libresoc.v:170332.14-170332.49" + process $proc$libresoc.v:170332$9342 + assign { } { } + assign $1\trap_op__cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \trap_op__cia $1\trap_op__cia[63:0] + end + attribute \src "libresoc.v:170355.14-170355.41" + process $proc$libresoc.v:170355$9343 + assign { } { } + assign $1\trap_op__fn_unit[12:0] 13'0000000000000 + sync always + sync init + update \trap_op__fn_unit $1\trap_op__fn_unit[12:0] + end + attribute \src "libresoc.v:170392.14-170392.35" + process $proc$libresoc.v:170392$9344 + assign { } { } + assign $1\trap_op__insn[31:0] 0 + sync always + sync init + update \trap_op__insn $1\trap_op__insn[31:0] + end + attribute \src "libresoc.v:170475.13-170475.39" + process $proc$libresoc.v:170475$9345 + assign { } { } + assign $1\trap_op__insn_type[6:0] 7'0000000 + sync always + sync init + update \trap_op__insn_type $1\trap_op__insn_type[6:0] + end + attribute \src "libresoc.v:170632.7-170632.31" + process $proc$libresoc.v:170632$9346 + assign { } { } + assign $1\trap_op__is_32bit[0:0] 1'0 + sync always + sync init + update \trap_op__is_32bit $1\trap_op__is_32bit[0:0] + end + attribute \src "libresoc.v:170641.13-170641.38" + process $proc$libresoc.v:170641$9347 + assign { } { } + assign $1\trap_op__ldst_exc[7:0] 8'00000000 + sync always + sync init + update \trap_op__ldst_exc $1\trap_op__ldst_exc[7:0] + end + attribute \src "libresoc.v:170650.14-170650.49" + process $proc$libresoc.v:170650$9348 + assign { } { } + assign $1\trap_op__msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \trap_op__msr $1\trap_op__msr[63:0] + end + attribute \src "libresoc.v:170659.14-170659.42" + process $proc$libresoc.v:170659$9349 + assign { } { } + assign $1\trap_op__trapaddr[12:0] 13'0000000000000 + sync always + sync init + update \trap_op__trapaddr $1\trap_op__trapaddr[12:0] + end + attribute \src "libresoc.v:170668.13-170668.38" + process $proc$libresoc.v:170668$9350 + assign { } { } + assign $1\trap_op__traptype[7:0] 8'00000000 + sync always + sync init + update \trap_op__traptype $1\trap_op__traptype[7:0] + end + attribute \src "libresoc.v:170676.3-170677.27" + process $proc$libresoc.v:170676$9282 + assign { } { } + assign $0\fast2[63:0] \fast2$next + sync posedge \coresync_clk + update \fast2 $0\fast2[63:0] + end + attribute \src "libresoc.v:170678.3-170679.27" + process $proc$libresoc.v:170678$9283 + assign { } { } + assign $0\fast1[63:0] \fast1$next + sync posedge \coresync_clk + update \fast1 $0\fast1[63:0] + end + attribute \src "libresoc.v:170680.3-170681.21" + process $proc$libresoc.v:170680$9284 + assign { } { } + assign $0\rb[63:0] \rb$next + sync posedge \coresync_clk + update \rb $0\rb[63:0] + end + attribute \src "libresoc.v:170682.3-170683.21" + process $proc$libresoc.v:170682$9285 + assign { } { } + assign $0\ra[63:0] \ra$next + sync posedge \coresync_clk + update \ra $0\ra[63:0] + end + attribute \src "libresoc.v:170684.3-170685.53" + process $proc$libresoc.v:170684$9286 + assign { } { } + assign $0\trap_op__insn_type[6:0] \trap_op__insn_type$next + sync posedge \coresync_clk + update \trap_op__insn_type $0\trap_op__insn_type[6:0] + end + attribute \src "libresoc.v:170686.3-170687.49" + process $proc$libresoc.v:170686$9287 + assign { } { } + assign $0\trap_op__fn_unit[12:0] \trap_op__fn_unit$next + sync posedge \coresync_clk + update \trap_op__fn_unit $0\trap_op__fn_unit[12:0] + end + attribute \src "libresoc.v:170688.3-170689.43" + process $proc$libresoc.v:170688$9288 + assign { } { } + assign $0\trap_op__insn[31:0] \trap_op__insn$next + sync posedge \coresync_clk + update \trap_op__insn $0\trap_op__insn[31:0] + end + attribute \src "libresoc.v:170690.3-170691.41" + process $proc$libresoc.v:170690$9289 + assign { } { } + assign $0\trap_op__msr[63:0] \trap_op__msr$next + sync posedge \coresync_clk + update \trap_op__msr $0\trap_op__msr[63:0] + end + attribute \src "libresoc.v:170692.3-170693.41" + process $proc$libresoc.v:170692$9290 + assign { } { } + assign $0\trap_op__cia[63:0] \trap_op__cia$next + sync posedge \coresync_clk + update \trap_op__cia $0\trap_op__cia[63:0] + end + attribute \src "libresoc.v:170694.3-170695.51" + process $proc$libresoc.v:170694$9291 + assign { } { } + assign $0\trap_op__is_32bit[0:0] \trap_op__is_32bit$next + sync posedge \coresync_clk + update \trap_op__is_32bit $0\trap_op__is_32bit[0:0] + end + attribute \src "libresoc.v:170696.3-170697.51" + process $proc$libresoc.v:170696$9292 + assign { } { } + assign $0\trap_op__traptype[7:0] \trap_op__traptype$next + sync posedge \coresync_clk + update \trap_op__traptype $0\trap_op__traptype[7:0] + end + attribute \src "libresoc.v:170698.3-170699.51" + process $proc$libresoc.v:170698$9293 + assign { } { } + assign $0\trap_op__trapaddr[12:0] \trap_op__trapaddr$next + sync posedge \coresync_clk + update \trap_op__trapaddr $0\trap_op__trapaddr[12:0] + end + attribute \src "libresoc.v:170700.3-170701.51" + process $proc$libresoc.v:170700$9294 + assign { } { } + assign $0\trap_op__ldst_exc[7:0] \trap_op__ldst_exc$next + sync posedge \coresync_clk + update \trap_op__ldst_exc $0\trap_op__ldst_exc[7:0] + end + attribute \src "libresoc.v:170702.3-170703.27" + process $proc$libresoc.v:170702$9295 + assign { } { } + assign $0\muxid[1:0] \muxid$next + sync posedge \coresync_clk + update \muxid $0\muxid[1:0] + end + attribute \src "libresoc.v:170704.3-170705.29" + process $proc$libresoc.v:170704$9296 + assign { } { } + assign $0\r_busy[0:0] \r_busy$next + sync posedge \coresync_clk + update \r_busy $0\r_busy[0:0] + end + attribute \src "libresoc.v:170744.3-170761.6" + process $proc$libresoc.v:170744$9297 + assign { } { } + assign { } { } + assign { } { } + assign $0\r_busy$next[0:0]$9298 $2\r_busy$next[0:0]$9300 + attribute \src "libresoc.v:170745.5-170745.29" + switch \initial + attribute \src "libresoc.v:170745.9-170745.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\r_busy$next[0:0]$9299 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\r_busy$next[0:0]$9299 1'0 + case + assign $1\r_busy$next[0:0]$9299 \r_busy + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r_busy$next[0:0]$9300 1'0 + case + assign $2\r_busy$next[0:0]$9300 $1\r_busy$next[0:0]$9299 + end + sync always + update \r_busy$next $0\r_busy$next[0:0]$9298 + end + attribute \src "libresoc.v:170762.3-170774.6" + process $proc$libresoc.v:170762$9301 + assign { } { } + assign { } { } + assign $0\muxid$next[1:0]$9302 $1\muxid$next[1:0]$9303 + attribute \src "libresoc.v:170763.5-170763.29" + switch \initial + attribute \src "libresoc.v:170763.9-170763.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\muxid$next[1:0]$9303 \muxid$32 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\muxid$next[1:0]$9303 \muxid$32 + case + assign $1\muxid$next[1:0]$9303 \muxid + end + sync always + update \muxid$next $0\muxid$next[1:0]$9302 + end + attribute \src "libresoc.v:170775.3-170795.6" + process $proc$libresoc.v:170775$9304 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\trap_op__cia$next[63:0]$9305 $1\trap_op__cia$next[63:0]$9314 + assign $0\trap_op__fn_unit$next[12:0]$9306 $1\trap_op__fn_unit$next[12:0]$9315 + assign $0\trap_op__insn$next[31:0]$9307 $1\trap_op__insn$next[31:0]$9316 + assign $0\trap_op__insn_type$next[6:0]$9308 $1\trap_op__insn_type$next[6:0]$9317 + assign $0\trap_op__is_32bit$next[0:0]$9309 $1\trap_op__is_32bit$next[0:0]$9318 + assign $0\trap_op__ldst_exc$next[7:0]$9310 $1\trap_op__ldst_exc$next[7:0]$9319 + assign $0\trap_op__msr$next[63:0]$9311 $1\trap_op__msr$next[63:0]$9320 + assign $0\trap_op__trapaddr$next[12:0]$9312 $1\trap_op__trapaddr$next[12:0]$9321 + assign $0\trap_op__traptype$next[7:0]$9313 $1\trap_op__traptype$next[7:0]$9322 + attribute \src "libresoc.v:170776.5-170776.29" + switch \initial + attribute \src "libresoc.v:170776.9-170776.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\trap_op__ldst_exc$next[7:0]$9319 $1\trap_op__trapaddr$next[12:0]$9321 $1\trap_op__traptype$next[7:0]$9322 $1\trap_op__is_32bit$next[0:0]$9318 $1\trap_op__cia$next[63:0]$9314 $1\trap_op__msr$next[63:0]$9320 $1\trap_op__insn$next[31:0]$9316 $1\trap_op__fn_unit$next[12:0]$9315 $1\trap_op__insn_type$next[6:0]$9317 } { \trap_op__ldst_exc$41 \trap_op__trapaddr$40 \trap_op__traptype$39 \trap_op__is_32bit$38 \trap_op__cia$37 \trap_op__msr$36 \trap_op__insn$35 \trap_op__fn_unit$34 \trap_op__insn_type$33 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\trap_op__ldst_exc$next[7:0]$9319 $1\trap_op__trapaddr$next[12:0]$9321 $1\trap_op__traptype$next[7:0]$9322 $1\trap_op__is_32bit$next[0:0]$9318 $1\trap_op__cia$next[63:0]$9314 $1\trap_op__msr$next[63:0]$9320 $1\trap_op__insn$next[31:0]$9316 $1\trap_op__fn_unit$next[12:0]$9315 $1\trap_op__insn_type$next[6:0]$9317 } { \trap_op__ldst_exc$41 \trap_op__trapaddr$40 \trap_op__traptype$39 \trap_op__is_32bit$38 \trap_op__cia$37 \trap_op__msr$36 \trap_op__insn$35 \trap_op__fn_unit$34 \trap_op__insn_type$33 } + case + assign $1\trap_op__cia$next[63:0]$9314 \trap_op__cia + assign $1\trap_op__fn_unit$next[12:0]$9315 \trap_op__fn_unit + assign $1\trap_op__insn$next[31:0]$9316 \trap_op__insn + assign $1\trap_op__insn_type$next[6:0]$9317 \trap_op__insn_type + assign $1\trap_op__is_32bit$next[0:0]$9318 \trap_op__is_32bit + assign $1\trap_op__ldst_exc$next[7:0]$9319 \trap_op__ldst_exc + assign $1\trap_op__msr$next[63:0]$9320 \trap_op__msr + assign $1\trap_op__trapaddr$next[12:0]$9321 \trap_op__trapaddr + assign $1\trap_op__traptype$next[7:0]$9322 \trap_op__traptype + end + sync always + update \trap_op__cia$next $0\trap_op__cia$next[63:0]$9305 + update \trap_op__fn_unit$next $0\trap_op__fn_unit$next[12:0]$9306 + update \trap_op__insn$next $0\trap_op__insn$next[31:0]$9307 + update \trap_op__insn_type$next $0\trap_op__insn_type$next[6:0]$9308 + update \trap_op__is_32bit$next $0\trap_op__is_32bit$next[0:0]$9309 + update \trap_op__ldst_exc$next $0\trap_op__ldst_exc$next[7:0]$9310 + update \trap_op__msr$next $0\trap_op__msr$next[63:0]$9311 + update \trap_op__trapaddr$next $0\trap_op__trapaddr$next[12:0]$9312 + update \trap_op__traptype$next $0\trap_op__traptype$next[7:0]$9313 + end + attribute \src "libresoc.v:170796.3-170808.6" + process $proc$libresoc.v:170796$9323 + assign { } { } + assign { } { } + assign $0\ra$next[63:0]$9324 $1\ra$next[63:0]$9325 + attribute \src "libresoc.v:170797.5-170797.29" + switch \initial + attribute \src "libresoc.v:170797.9-170797.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\ra$next[63:0]$9325 \ra$42 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\ra$next[63:0]$9325 \ra$42 + case + assign $1\ra$next[63:0]$9325 \ra + end + sync always + update \ra$next $0\ra$next[63:0]$9324 + end + attribute \src "libresoc.v:170809.3-170821.6" + process $proc$libresoc.v:170809$9326 + assign { } { } + assign { } { } + assign $0\rb$next[63:0]$9327 $1\rb$next[63:0]$9328 + attribute \src "libresoc.v:170810.5-170810.29" + switch \initial + attribute \src "libresoc.v:170810.9-170810.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\rb$next[63:0]$9328 \rb$43 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\rb$next[63:0]$9328 \rb$43 + case + assign $1\rb$next[63:0]$9328 \rb + end + sync always + update \rb$next $0\rb$next[63:0]$9327 + end + attribute \src "libresoc.v:170822.3-170834.6" + process $proc$libresoc.v:170822$9329 + assign { } { } + assign { } { } + assign $0\fast1$next[63:0]$9330 $1\fast1$next[63:0]$9331 + attribute \src "libresoc.v:170823.5-170823.29" + switch \initial + attribute \src "libresoc.v:170823.9-170823.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\fast1$next[63:0]$9331 \fast1$44 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\fast1$next[63:0]$9331 \fast1$44 + case + assign $1\fast1$next[63:0]$9331 \fast1 + end + sync always + update \fast1$next $0\fast1$next[63:0]$9330 + end + attribute \src "libresoc.v:170835.3-170847.6" + process $proc$libresoc.v:170835$9332 + assign { } { } + assign { } { } + assign $0\fast2$next[63:0]$9333 $1\fast2$next[63:0]$9334 + attribute \src "libresoc.v:170836.5-170836.29" + switch \initial + attribute \src "libresoc.v:170836.9-170836.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\fast2$next[63:0]$9334 \fast2$45 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\fast2$next[63:0]$9334 \fast2$45 + case + assign $1\fast2$next[63:0]$9334 \fast2 + end + sync always + update \fast2$next $0\fast2$next[63:0]$9333 + end + connect \$30 $and$libresoc.v:170675$9281_Y + connect \p_ready_o \n_i_rdy_data + connect \n_valid_o \r_busy + connect \fast2$45 \dummy_fast2$28 + connect \fast1$44 \dummy_fast1$27 + connect \rb$43 \dummy_rb$26 + connect \ra$42 \dummy_ra$25 + connect { \trap_op__ldst_exc$41 \trap_op__trapaddr$40 \trap_op__traptype$39 \trap_op__is_32bit$38 \trap_op__cia$37 \trap_op__msr$36 \trap_op__insn$35 \trap_op__fn_unit$34 \trap_op__insn_type$33 } { \dummy_trap_op__ldst_exc$24 \dummy_trap_op__trapaddr$23 \dummy_trap_op__traptype$22 \dummy_trap_op__is_32bit$21 \dummy_trap_op__cia$20 \dummy_trap_op__msr$19 \dummy_trap_op__insn$18 \dummy_trap_op__fn_unit$17 \dummy_trap_op__insn_type$16 } + connect \muxid$32 \dummy_muxid$15 + connect \p_valid_i_p_ready_o \$30 + connect \n_i_rdy_data \n_ready_i + connect \p_valid_i$29 \p_valid_i + connect \dummy_fast2 \fast2$14 + connect \dummy_fast1 \fast1$13 + connect \dummy_rb \rb$12 + connect \dummy_ra \ra$11 + connect { \dummy_trap_op__ldst_exc \dummy_trap_op__trapaddr \dummy_trap_op__traptype \dummy_trap_op__is_32bit \dummy_trap_op__cia \dummy_trap_op__msr \dummy_trap_op__insn \dummy_trap_op__fn_unit \dummy_trap_op__insn_type } { \trap_op__ldst_exc$10 \trap_op__trapaddr$9 \trap_op__traptype$8 \trap_op__is_32bit$7 \trap_op__cia$6 \trap_op__msr$5 \trap_op__insn$4 \trap_op__fn_unit$3 \trap_op__insn_type$2 } + connect \dummy_muxid \muxid$1 +end +attribute \src "libresoc.v:170869.1-172044.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe2" +attribute \generator "nMigen" +module \pipe2 + attribute \src "libresoc.v:171888.3-171929.6" + wire width 4 $0\alu_op__data_len$18$next[3:0]$9419 + attribute \src "libresoc.v:171785.3-171786.57" + wire width 4 $0\alu_op__data_len$18[3:0]$9405 + attribute \src "libresoc.v:170877.13-170877.41" + wire width 4 $0\alu_op__data_len$18[3:0]$9493 + attribute \src "libresoc.v:171888.3-171929.6" + wire width 13 $0\alu_op__fn_unit$3$next[12:0]$9420 + attribute \src "libresoc.v:171755.3-171756.53" + wire width 13 $0\alu_op__fn_unit$3[12:0]$9375 + attribute \src "libresoc.v:170914.14-170914.44" + wire width 13 $0\alu_op__fn_unit$3[12:0]$9495 + attribute \src "libresoc.v:171888.3-171929.6" + wire width 64 $0\alu_op__imm_data__data$4$next[63:0]$9421 + attribute \src "libresoc.v:171757.3-171758.67" + wire width 64 $0\alu_op__imm_data__data$4[63:0]$9377 + attribute \src "libresoc.v:170937.14-170937.63" + wire width 64 $0\alu_op__imm_data__data$4[63:0]$9497 + attribute \src "libresoc.v:171888.3-171929.6" + wire $0\alu_op__imm_data__ok$5$next[0:0]$9422 + attribute \src "libresoc.v:171759.3-171760.63" + wire $0\alu_op__imm_data__ok$5[0:0]$9379 + attribute \src "libresoc.v:170946.7-170946.38" + wire $0\alu_op__imm_data__ok$5[0:0]$9499 + attribute \src "libresoc.v:171888.3-171929.6" + wire width 2 $0\alu_op__input_carry$14$next[1:0]$9423 + attribute \src "libresoc.v:171777.3-171778.63" + wire width 2 $0\alu_op__input_carry$14[1:0]$9397 + attribute \src "libresoc.v:170963.13-170963.44" + wire width 2 $0\alu_op__input_carry$14[1:0]$9501 + attribute \src "libresoc.v:171888.3-171929.6" + wire width 32 $0\alu_op__insn$19$next[31:0]$9424 + attribute \src "libresoc.v:171787.3-171788.49" + wire width 32 $0\alu_op__insn$19[31:0]$9407 + attribute \src "libresoc.v:170976.14-170976.39" + wire width 32 $0\alu_op__insn$19[31:0]$9503 + attribute \src "libresoc.v:171888.3-171929.6" + wire width 7 $0\alu_op__insn_type$2$next[6:0]$9425 + attribute \src "libresoc.v:171753.3-171754.57" + wire width 7 $0\alu_op__insn_type$2[6:0]$9373 + attribute \src "libresoc.v:171133.13-171133.42" + wire width 7 $0\alu_op__insn_type$2[6:0]$9505 + attribute \src "libresoc.v:171888.3-171929.6" + wire $0\alu_op__invert_in$10$next[0:0]$9426 + attribute \src "libresoc.v:171769.3-171770.59" + wire $0\alu_op__invert_in$10[0:0]$9389 + attribute \src "libresoc.v:171216.7-171216.36" + wire $0\alu_op__invert_in$10[0:0]$9507 + attribute \src "libresoc.v:171888.3-171929.6" + wire $0\alu_op__invert_out$12$next[0:0]$9427 + attribute \src "libresoc.v:171773.3-171774.61" + wire $0\alu_op__invert_out$12[0:0]$9393 + attribute \src "libresoc.v:171225.7-171225.37" + wire $0\alu_op__invert_out$12[0:0]$9509 + attribute \src "libresoc.v:171888.3-171929.6" + wire $0\alu_op__is_32bit$16$next[0:0]$9428 + attribute \src "libresoc.v:171781.3-171782.57" + wire $0\alu_op__is_32bit$16[0:0]$9401 + attribute \src "libresoc.v:171234.7-171234.35" + wire $0\alu_op__is_32bit$16[0:0]$9511 + attribute \src "libresoc.v:171888.3-171929.6" + wire $0\alu_op__is_signed$17$next[0:0]$9429 + attribute \src "libresoc.v:171783.3-171784.59" + wire $0\alu_op__is_signed$17[0:0]$9403 + attribute \src "libresoc.v:171243.7-171243.36" + wire $0\alu_op__is_signed$17[0:0]$9513 + attribute \src "libresoc.v:171888.3-171929.6" + wire $0\alu_op__oe__oe$8$next[0:0]$9430 + attribute \src "libresoc.v:171765.3-171766.51" + wire $0\alu_op__oe__oe$8[0:0]$9385 + attribute \src "libresoc.v:171254.7-171254.32" + wire $0\alu_op__oe__oe$8[0:0]$9515 + attribute \src "libresoc.v:171888.3-171929.6" + wire $0\alu_op__oe__ok$9$next[0:0]$9431 + attribute \src "libresoc.v:171767.3-171768.51" + wire $0\alu_op__oe__ok$9[0:0]$9387 + attribute \src "libresoc.v:171263.7-171263.32" + wire $0\alu_op__oe__ok$9[0:0]$9517 + attribute \src "libresoc.v:171888.3-171929.6" + wire $0\alu_op__output_carry$15$next[0:0]$9432 + attribute \src "libresoc.v:171779.3-171780.65" + wire $0\alu_op__output_carry$15[0:0]$9399 + attribute \src "libresoc.v:171270.7-171270.39" + wire $0\alu_op__output_carry$15[0:0]$9519 + attribute \src "libresoc.v:171888.3-171929.6" + wire $0\alu_op__rc__ok$7$next[0:0]$9433 + attribute \src "libresoc.v:171763.3-171764.51" + wire $0\alu_op__rc__ok$7[0:0]$9383 + attribute \src "libresoc.v:171281.7-171281.32" + wire $0\alu_op__rc__ok$7[0:0]$9521 + attribute \src "libresoc.v:171888.3-171929.6" + wire $0\alu_op__rc__rc$6$next[0:0]$9434 + attribute \src "libresoc.v:171761.3-171762.51" + wire $0\alu_op__rc__rc$6[0:0]$9381 + attribute \src "libresoc.v:171288.7-171288.32" + wire $0\alu_op__rc__rc$6[0:0]$9523 + attribute \src "libresoc.v:171888.3-171929.6" + wire $0\alu_op__write_cr0$13$next[0:0]$9435 + attribute \src "libresoc.v:171775.3-171776.59" + wire $0\alu_op__write_cr0$13[0:0]$9395 + attribute \src "libresoc.v:171297.7-171297.36" + wire $0\alu_op__write_cr0$13[0:0]$9525 + attribute \src "libresoc.v:171888.3-171929.6" + wire $0\alu_op__zero_a$11$next[0:0]$9436 + attribute \src "libresoc.v:171771.3-171772.53" + wire $0\alu_op__zero_a$11[0:0]$9391 + attribute \src "libresoc.v:171306.7-171306.33" + wire $0\alu_op__zero_a$11[0:0]$9527 + attribute \src "libresoc.v:171949.3-171967.6" + wire width 4 $0\cr_a$22$next[3:0]$9468 + attribute \src "libresoc.v:171745.3-171746.33" + wire width 4 $0\cr_a$22[3:0]$9365 + attribute \src "libresoc.v:171319.13-171319.29" + wire width 4 $0\cr_a$22[3:0]$9529 + attribute \src "libresoc.v:171949.3-171967.6" + wire $0\cr_a_ok$23$next[0:0]$9469 + attribute \src "libresoc.v:171747.3-171748.39" + wire $0\cr_a_ok$23[0:0]$9367 + attribute \src "libresoc.v:171328.7-171328.26" + wire $0\cr_a_ok$23[0:0]$9531 + attribute \src "libresoc.v:170870.7-170870.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:171875.3-171887.6" + wire width 2 $0\muxid$1$next[1:0]$9416 + attribute \src "libresoc.v:171789.3-171790.33" + wire width 2 $0\muxid$1[1:0]$9409 + attribute \src "libresoc.v:171339.13-171339.29" + wire width 2 $0\muxid$1[1:0]$9533 + attribute \src "libresoc.v:171930.3-171948.6" + wire width 64 $0\o$20$next[63:0]$9462 + attribute \src "libresoc.v:171749.3-171750.27" + wire width 64 $0\o$20[63:0]$9369 + attribute \src "libresoc.v:171354.14-171354.43" + wire width 64 $0\o$20[63:0]$9535 + attribute \src "libresoc.v:171930.3-171948.6" + wire $0\o_ok$21$next[0:0]$9463 + attribute \src "libresoc.v:171751.3-171752.33" + wire $0\o_ok$21[0:0]$9371 + attribute \src "libresoc.v:171363.7-171363.23" + wire $0\o_ok$21[0:0]$9537 + attribute \src "libresoc.v:171857.3-171874.6" + wire $0\r_busy$next[0:0]$9412 + attribute \src "libresoc.v:171791.3-171792.29" + wire $0\r_busy[0:0] + attribute \src "libresoc.v:171968.3-171986.6" + wire width 2 $0\xer_ca$24$next[1:0]$9474 + attribute \src "libresoc.v:171741.3-171742.37" + wire width 2 $0\xer_ca$24[1:0]$9361 + attribute \src "libresoc.v:171676.13-171676.31" + wire width 2 $0\xer_ca$24[1:0]$9540 + attribute \src "libresoc.v:171968.3-171986.6" + wire $0\xer_ca_ok$25$next[0:0]$9475 + attribute \src "libresoc.v:171743.3-171744.43" + wire $0\xer_ca_ok$25[0:0]$9363 + attribute \src "libresoc.v:171685.7-171685.28" + wire $0\xer_ca_ok$25[0:0]$9542 + attribute \src "libresoc.v:171987.3-172005.6" + wire width 2 $0\xer_ov$26$next[1:0]$9480 + attribute \src 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\src "libresoc.v:171888.3-171929.6" + wire $1\alu_op__oe__oe$8$next[0:0]$9448 + attribute \src "libresoc.v:171888.3-171929.6" + wire $1\alu_op__oe__ok$9$next[0:0]$9449 + attribute \src "libresoc.v:171888.3-171929.6" + wire $1\alu_op__output_carry$15$next[0:0]$9450 + attribute \src "libresoc.v:171888.3-171929.6" + wire $1\alu_op__rc__ok$7$next[0:0]$9451 + attribute \src "libresoc.v:171888.3-171929.6" + wire $1\alu_op__rc__rc$6$next[0:0]$9452 + attribute \src "libresoc.v:171888.3-171929.6" + wire $1\alu_op__write_cr0$13$next[0:0]$9453 + attribute \src "libresoc.v:171888.3-171929.6" + wire $1\alu_op__zero_a$11$next[0:0]$9454 + attribute \src "libresoc.v:171949.3-171967.6" + wire width 4 $1\cr_a$22$next[3:0]$9470 + attribute \src "libresoc.v:171949.3-171967.6" + wire $1\cr_a_ok$23$next[0:0]$9471 + attribute \src "libresoc.v:171875.3-171887.6" + wire width 2 $1\muxid$1$next[1:0]$9417 + attribute \src "libresoc.v:171930.3-171948.6" + wire width 64 $1\o$20$next[63:0]$9464 + attribute \src "libresoc.v:171930.3-171948.6" + wire $1\o_ok$21$next[0:0]$9465 + attribute \src "libresoc.v:171857.3-171874.6" + wire $1\r_busy$next[0:0]$9413 + attribute \src "libresoc.v:171669.7-171669.20" + wire $1\r_busy[0:0] + attribute \src "libresoc.v:171968.3-171986.6" + wire width 2 $1\xer_ca$24$next[1:0]$9476 + attribute \src "libresoc.v:171968.3-171986.6" + wire $1\xer_ca_ok$25$next[0:0]$9477 + attribute \src "libresoc.v:171987.3-172005.6" + wire width 2 $1\xer_ov$26$next[1:0]$9482 + attribute \src "libresoc.v:171987.3-172005.6" + wire $1\xer_ov_ok$27$next[0:0]$9483 + attribute \src "libresoc.v:172006.3-172024.6" + wire $1\xer_so$28$next[0:0]$9488 + attribute \src "libresoc.v:172006.3-172024.6" + wire $1\xer_so_ok$29$next[0:0]$9489 + attribute \src "libresoc.v:171888.3-171929.6" + wire width 64 $2\alu_op__imm_data__data$4$next[63:0]$9455 + attribute \src "libresoc.v:171888.3-171929.6" + wire $2\alu_op__imm_data__ok$5$next[0:0]$9456 + attribute \src "libresoc.v:171888.3-171929.6" + wire $2\alu_op__oe__oe$8$next[0:0]$9457 + attribute \src "libresoc.v:171888.3-171929.6" + wire $2\alu_op__oe__ok$9$next[0:0]$9458 + attribute \src "libresoc.v:171888.3-171929.6" + wire $2\alu_op__rc__ok$7$next[0:0]$9459 + attribute \src "libresoc.v:171888.3-171929.6" + wire $2\alu_op__rc__rc$6$next[0:0]$9460 + attribute \src "libresoc.v:171949.3-171967.6" + wire $2\cr_a_ok$23$next[0:0]$9472 + attribute \src "libresoc.v:171930.3-171948.6" + wire $2\o_ok$21$next[0:0]$9466 + attribute \src "libresoc.v:171857.3-171874.6" + wire $2\r_busy$next[0:0]$9414 + attribute \src "libresoc.v:171968.3-171986.6" + wire $2\xer_ca_ok$25$next[0:0]$9478 + attribute \src "libresoc.v:171987.3-172005.6" + wire $2\xer_ov_ok$27$next[0:0]$9484 + attribute \src "libresoc.v:172006.3-172024.6" + wire $2\xer_so_ok$29$next[0:0]$9490 + attribute \src "libresoc.v:171732.18-171732.118" + wire $and$libresoc.v:171732$9351_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" + wire \$60 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 21 \alu_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 52 \alu_op__data_len$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \alu_op__data_len$18$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \alu_op__data_len$79 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 input 6 \alu_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 output 37 \alu_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \alu_op__fn_unit$3$next + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \alu_op__fn_unit$64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 7 \alu_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 38 \alu_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \alu_op__imm_data__data$4$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \alu_op__imm_data__data$65 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \alu_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 39 \alu_op__imm_data__ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__imm_data__ok$5$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__imm_data__ok$66 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 17 \alu_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 48 \alu_op__input_carry$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \alu_op__input_carry$14$next + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \alu_op__input_carry$75 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 22 \alu_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 53 \alu_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \alu_op__insn$19$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \alu_op__insn$80 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 5 \alu_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 36 \alu_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \alu_op__insn_type$2$next + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \alu_op__insn_type$63 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \alu_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 44 \alu_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__invert_in$10$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__invert_in$71 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 15 \alu_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 46 \alu_op__invert_out$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__invert_out$12$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__invert_out$73 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 19 \alu_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 50 \alu_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__is_32bit$16$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__is_32bit$77 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 20 \alu_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 51 \alu_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__is_signed$17$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__is_signed$78 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 11 \alu_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__oe__oe$69 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 42 \alu_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__oe__oe$8$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \alu_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__oe__ok$70 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 43 \alu_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__oe__ok$9$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 18 \alu_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 49 \alu_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__output_carry$15$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__output_carry$76 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \alu_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__rc__ok$68 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 41 \alu_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__rc__ok$7$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \alu_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 40 \alu_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__rc__rc$6$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__rc__rc$67 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 16 \alu_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 47 \alu_op__write_cr0$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__write_cr0$13$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__write_cr0$74 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \alu_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 45 \alu_op__zero_a$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__zero_a$11$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__zero_a$72 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 64 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 input 25 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 output 56 \cr_a$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \cr_a$22$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \cr_a$83 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire input 26 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 57 \cr_a_ok$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_a_ok$23$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_a_ok$55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_a_ok$84 + attribute \src "libresoc.v:170870.7-170870.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 input 4 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 output 35 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid$1$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid$62 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + wire \n_i_rdy_data + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire input 34 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire output 33 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 input 23 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 54 \o$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \o$20$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \o$81 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire input 24 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 55 \o_ok$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \o_ok$21$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \o_ok$82 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \output_alu_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \output_alu_op__data_len$47 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \output_alu_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \output_alu_op__fn_unit$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \output_alu_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \output_alu_op__imm_data__data$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_alu_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_alu_op__imm_data__ok$34 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \output_alu_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \output_alu_op__input_carry$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \output_alu_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \output_alu_op__insn$48 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \output_alu_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \output_alu_op__insn_type$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_alu_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_alu_op__invert_in$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_alu_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_alu_op__invert_out$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_alu_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_alu_op__is_32bit$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_alu_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_alu_op__is_signed$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_alu_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_alu_op__oe__oe$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_alu_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_alu_op__oe__ok$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_alu_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_alu_op__output_carry$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_alu_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_alu_op__rc__ok$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_alu_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_alu_op__rc__rc$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_alu_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_alu_op__write_cr0$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_alu_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_alu_op__zero_a$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \output_cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \output_cr_a$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \output_cr_a_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \output_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \output_muxid$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \output_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \output_o$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \output_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \output_o_ok$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \output_xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \output_xer_ca$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \output_xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \output_xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \output_xer_ov$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \output_xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \output_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \output_xer_so$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \output_xer_so_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" + wire output 3 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" + wire input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" + wire \p_valid_i$59 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" + wire \p_valid_i_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire \r_busy$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 input 27 \xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 output 58 \xer_ca$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \xer_ca$24$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \xer_ca$85 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire input 28 \xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 59 \xer_ca_ok$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_ca_ok$25$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_ca_ok$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_ca_ok$86 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 input 29 \xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 output 60 \xer_ov$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \xer_ov$26$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \xer_ov$87 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire input 30 \xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 61 \xer_ov_ok$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_ov_ok$27$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_ov_ok$57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_ov_ok$88 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire input 31 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 62 \xer_so$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so$28$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so$89 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire input 32 \xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 63 \xer_so_ok$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so_ok$29$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so_ok$58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so_ok$90 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" + cell $and $and$libresoc.v:171732$9351 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i$59 + connect \B \p_ready_o + connect \Y $and$libresoc.v:171732$9351_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:171793.9-171796.4" + cell \n$4 \n + connect \n_ready_i \n_ready_i + connect \n_valid_o \n_valid_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:171797.12-171852.4" + cell \output \output + connect \alu_op__data_len \output_alu_op__data_len + connect \alu_op__data_len$18 \output_alu_op__data_len$47 + connect \alu_op__fn_unit \output_alu_op__fn_unit + connect \alu_op__fn_unit$3 \output_alu_op__fn_unit$32 + connect \alu_op__imm_data__data \output_alu_op__imm_data__data + connect \alu_op__imm_data__data$4 \output_alu_op__imm_data__data$33 + connect \alu_op__imm_data__ok \output_alu_op__imm_data__ok + connect \alu_op__imm_data__ok$5 \output_alu_op__imm_data__ok$34 + connect \alu_op__input_carry \output_alu_op__input_carry + connect \alu_op__input_carry$14 \output_alu_op__input_carry$43 + connect \alu_op__insn \output_alu_op__insn + connect \alu_op__insn$19 \output_alu_op__insn$48 + connect \alu_op__insn_type \output_alu_op__insn_type + connect \alu_op__insn_type$2 \output_alu_op__insn_type$31 + connect \alu_op__invert_in \output_alu_op__invert_in + connect \alu_op__invert_in$10 \output_alu_op__invert_in$39 + connect \alu_op__invert_out \output_alu_op__invert_out + connect \alu_op__invert_out$12 \output_alu_op__invert_out$41 + connect \alu_op__is_32bit \output_alu_op__is_32bit + connect \alu_op__is_32bit$16 \output_alu_op__is_32bit$45 + connect \alu_op__is_signed \output_alu_op__is_signed + connect \alu_op__is_signed$17 \output_alu_op__is_signed$46 + connect \alu_op__oe__oe \output_alu_op__oe__oe + connect \alu_op__oe__oe$8 \output_alu_op__oe__oe$37 + connect \alu_op__oe__ok \output_alu_op__oe__ok + connect \alu_op__oe__ok$9 \output_alu_op__oe__ok$38 + connect \alu_op__output_carry \output_alu_op__output_carry + connect \alu_op__output_carry$15 \output_alu_op__output_carry$44 + connect \alu_op__rc__ok \output_alu_op__rc__ok + connect \alu_op__rc__ok$7 \output_alu_op__rc__ok$36 + connect \alu_op__rc__rc \output_alu_op__rc__rc + connect \alu_op__rc__rc$6 \output_alu_op__rc__rc$35 + connect \alu_op__write_cr0 \output_alu_op__write_cr0 + connect \alu_op__write_cr0$13 \output_alu_op__write_cr0$42 + connect \alu_op__zero_a \output_alu_op__zero_a + connect \alu_op__zero_a$11 \output_alu_op__zero_a$40 + connect \cr_a \output_cr_a + connect \cr_a$22 \output_cr_a$51 + connect \cr_a_ok \output_cr_a_ok + connect \muxid \output_muxid + connect \muxid$1 \output_muxid$30 + connect \o \output_o + connect \o$20 \output_o$49 + connect \o_ok \output_o_ok + connect \o_ok$21 \output_o_ok$50 + connect \xer_ca \output_xer_ca + connect \xer_ca$23 \output_xer_ca$52 + connect \xer_ca_ok \output_xer_ca_ok + connect \xer_ov \output_xer_ov + connect \xer_ov$24 \output_xer_ov$53 + connect \xer_ov_ok \output_xer_ov_ok + connect \xer_so \output_xer_so + connect \xer_so$25 \output_xer_so$54 + connect \xer_so_ok \output_xer_so_ok + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:171853.9-171856.4" + cell \p$3 \p + connect \p_ready_o \p_ready_o + connect \p_valid_i \p_valid_i + end + attribute \src "libresoc.v:170870.7-170870.20" + process $proc$libresoc.v:170870$9491 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:170877.13-170877.41" + process $proc$libresoc.v:170877$9492 + assign { } { } + assign $0\alu_op__data_len$18[3:0]$9493 4'0000 + sync always + sync init + update \alu_op__data_len$18 $0\alu_op__data_len$18[3:0]$9493 + end + attribute \src "libresoc.v:170914.14-170914.44" + process $proc$libresoc.v:170914$9494 + assign { } { } + assign $0\alu_op__fn_unit$3[12:0]$9495 13'0000000000000 + sync always + sync init + update \alu_op__fn_unit$3 $0\alu_op__fn_unit$3[12:0]$9495 + end + attribute \src "libresoc.v:170937.14-170937.63" + process $proc$libresoc.v:170937$9496 + assign { } { } + assign $0\alu_op__imm_data__data$4[63:0]$9497 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \alu_op__imm_data__data$4 $0\alu_op__imm_data__data$4[63:0]$9497 + end + attribute \src "libresoc.v:170946.7-170946.38" + process $proc$libresoc.v:170946$9498 + assign { } { } + assign $0\alu_op__imm_data__ok$5[0:0]$9499 1'0 + sync always + sync init + update \alu_op__imm_data__ok$5 $0\alu_op__imm_data__ok$5[0:0]$9499 + end + attribute \src "libresoc.v:170963.13-170963.44" + process $proc$libresoc.v:170963$9500 + assign { } { } + assign $0\alu_op__input_carry$14[1:0]$9501 2'00 + sync always + sync init + update \alu_op__input_carry$14 $0\alu_op__input_carry$14[1:0]$9501 + end + attribute \src "libresoc.v:170976.14-170976.39" + process $proc$libresoc.v:170976$9502 + assign { } { } + assign $0\alu_op__insn$19[31:0]$9503 0 + sync always + sync init + update \alu_op__insn$19 $0\alu_op__insn$19[31:0]$9503 + end + attribute \src "libresoc.v:171133.13-171133.42" + process $proc$libresoc.v:171133$9504 + assign { } { } + assign $0\alu_op__insn_type$2[6:0]$9505 7'0000000 + sync always + sync init + update \alu_op__insn_type$2 $0\alu_op__insn_type$2[6:0]$9505 + end + attribute \src "libresoc.v:171216.7-171216.36" + process $proc$libresoc.v:171216$9506 + assign { } { } + assign $0\alu_op__invert_in$10[0:0]$9507 1'0 + sync always + sync init + update \alu_op__invert_in$10 $0\alu_op__invert_in$10[0:0]$9507 + end + attribute \src "libresoc.v:171225.7-171225.37" + process $proc$libresoc.v:171225$9508 + assign { } { } + assign $0\alu_op__invert_out$12[0:0]$9509 1'0 + sync always + sync init + update \alu_op__invert_out$12 $0\alu_op__invert_out$12[0:0]$9509 + end + attribute \src "libresoc.v:171234.7-171234.35" + process $proc$libresoc.v:171234$9510 + assign { } { } + assign $0\alu_op__is_32bit$16[0:0]$9511 1'0 + sync always + sync init + update \alu_op__is_32bit$16 $0\alu_op__is_32bit$16[0:0]$9511 + end + attribute \src "libresoc.v:171243.7-171243.36" + process $proc$libresoc.v:171243$9512 + assign { } { } + assign $0\alu_op__is_signed$17[0:0]$9513 1'0 + sync always + sync init + update \alu_op__is_signed$17 $0\alu_op__is_signed$17[0:0]$9513 + end + attribute \src "libresoc.v:171254.7-171254.32" + process $proc$libresoc.v:171254$9514 + assign { } { } + assign $0\alu_op__oe__oe$8[0:0]$9515 1'0 + sync always + sync init + update \alu_op__oe__oe$8 $0\alu_op__oe__oe$8[0:0]$9515 + end + attribute \src "libresoc.v:171263.7-171263.32" + process $proc$libresoc.v:171263$9516 + assign { } { } + assign $0\alu_op__oe__ok$9[0:0]$9517 1'0 + sync always + sync init + update \alu_op__oe__ok$9 $0\alu_op__oe__ok$9[0:0]$9517 + end + attribute \src "libresoc.v:171270.7-171270.39" + process $proc$libresoc.v:171270$9518 + assign { } { } + assign $0\alu_op__output_carry$15[0:0]$9519 1'0 + sync always + sync init + update \alu_op__output_carry$15 $0\alu_op__output_carry$15[0:0]$9519 + end + attribute \src "libresoc.v:171281.7-171281.32" + process $proc$libresoc.v:171281$9520 + assign { } { } + assign $0\alu_op__rc__ok$7[0:0]$9521 1'0 + sync always + sync init + update \alu_op__rc__ok$7 $0\alu_op__rc__ok$7[0:0]$9521 + end + attribute \src "libresoc.v:171288.7-171288.32" + process $proc$libresoc.v:171288$9522 + assign { } { } + assign $0\alu_op__rc__rc$6[0:0]$9523 1'0 + sync always + sync init + update \alu_op__rc__rc$6 $0\alu_op__rc__rc$6[0:0]$9523 + end + attribute \src "libresoc.v:171297.7-171297.36" + process $proc$libresoc.v:171297$9524 + assign { } { } + assign $0\alu_op__write_cr0$13[0:0]$9525 1'0 + sync always + sync init + update \alu_op__write_cr0$13 $0\alu_op__write_cr0$13[0:0]$9525 + end + attribute \src "libresoc.v:171306.7-171306.33" + process $proc$libresoc.v:171306$9526 + assign { } { } + assign $0\alu_op__zero_a$11[0:0]$9527 1'0 + sync always + sync init + update \alu_op__zero_a$11 $0\alu_op__zero_a$11[0:0]$9527 + end + attribute \src "libresoc.v:171319.13-171319.29" + process $proc$libresoc.v:171319$9528 + assign { } { } + assign $0\cr_a$22[3:0]$9529 4'0000 + sync always + sync init + update \cr_a$22 $0\cr_a$22[3:0]$9529 + end + attribute \src "libresoc.v:171328.7-171328.26" + process $proc$libresoc.v:171328$9530 + assign { } { } + assign $0\cr_a_ok$23[0:0]$9531 1'0 + sync always + sync init + update \cr_a_ok$23 $0\cr_a_ok$23[0:0]$9531 + end + attribute \src "libresoc.v:171339.13-171339.29" + process $proc$libresoc.v:171339$9532 + assign { } { } + assign $0\muxid$1[1:0]$9533 2'00 + sync always + sync init + update \muxid$1 $0\muxid$1[1:0]$9533 + end + attribute \src "libresoc.v:171354.14-171354.43" + process $proc$libresoc.v:171354$9534 + assign { } { } + assign $0\o$20[63:0]$9535 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \o$20 $0\o$20[63:0]$9535 + end + attribute \src "libresoc.v:171363.7-171363.23" + process $proc$libresoc.v:171363$9536 + assign { } { } + assign $0\o_ok$21[0:0]$9537 1'0 + sync always + sync init + update \o_ok$21 $0\o_ok$21[0:0]$9537 + end + attribute \src "libresoc.v:171669.7-171669.20" + process $proc$libresoc.v:171669$9538 + assign { } { } + assign $1\r_busy[0:0] 1'0 + sync always + sync init + update \r_busy $1\r_busy[0:0] + end + attribute \src "libresoc.v:171676.13-171676.31" + process $proc$libresoc.v:171676$9539 + assign { } { } + assign $0\xer_ca$24[1:0]$9540 2'00 + sync always + sync init + update \xer_ca$24 $0\xer_ca$24[1:0]$9540 + end + attribute \src "libresoc.v:171685.7-171685.28" + process $proc$libresoc.v:171685$9541 + assign { } { } + assign $0\xer_ca_ok$25[0:0]$9542 1'0 + sync always + sync init + update \xer_ca_ok$25 $0\xer_ca_ok$25[0:0]$9542 + end + attribute \src "libresoc.v:171696.13-171696.31" + process $proc$libresoc.v:171696$9543 + assign { } { } + assign $0\xer_ov$26[1:0]$9544 2'00 + sync always + sync init + update \xer_ov$26 $0\xer_ov$26[1:0]$9544 + end + attribute \src "libresoc.v:171705.7-171705.28" + process $proc$libresoc.v:171705$9545 + assign { } { } + assign $0\xer_ov_ok$27[0:0]$9546 1'0 + sync always + sync init + update \xer_ov_ok$27 $0\xer_ov_ok$27[0:0]$9546 + end + attribute \src "libresoc.v:171716.7-171716.25" + process $proc$libresoc.v:171716$9547 + assign { } { } + assign $0\xer_so$28[0:0]$9548 1'0 + sync always + sync init + update \xer_so$28 $0\xer_so$28[0:0]$9548 + end + attribute \src "libresoc.v:171725.7-171725.28" + process $proc$libresoc.v:171725$9549 + assign { } { } + assign $0\xer_so_ok$29[0:0]$9550 1'0 + sync always + sync init + update \xer_so_ok$29 $0\xer_so_ok$29[0:0]$9550 + end + attribute \src "libresoc.v:171733.3-171734.37" + process $proc$libresoc.v:171733$9352 + assign { } { } + assign $0\xer_so$28[0:0]$9353 \xer_so$28$next + sync posedge \coresync_clk + update \xer_so$28 $0\xer_so$28[0:0]$9353 + end + attribute \src "libresoc.v:171735.3-171736.43" + process $proc$libresoc.v:171735$9354 + assign { } { } + assign $0\xer_so_ok$29[0:0]$9355 \xer_so_ok$29$next + sync posedge \coresync_clk + update \xer_so_ok$29 $0\xer_so_ok$29[0:0]$9355 + end + attribute \src "libresoc.v:171737.3-171738.37" + process $proc$libresoc.v:171737$9356 + assign { } { } + assign $0\xer_ov$26[1:0]$9357 \xer_ov$26$next + sync posedge \coresync_clk + update \xer_ov$26 $0\xer_ov$26[1:0]$9357 + end + attribute \src "libresoc.v:171739.3-171740.43" + process $proc$libresoc.v:171739$9358 + assign { } { } + assign $0\xer_ov_ok$27[0:0]$9359 \xer_ov_ok$27$next + sync posedge \coresync_clk + update \xer_ov_ok$27 $0\xer_ov_ok$27[0:0]$9359 + end + attribute \src "libresoc.v:171741.3-171742.37" + process $proc$libresoc.v:171741$9360 + assign { } { } + assign $0\xer_ca$24[1:0]$9361 \xer_ca$24$next + sync posedge \coresync_clk + update \xer_ca$24 $0\xer_ca$24[1:0]$9361 + end + attribute \src "libresoc.v:171743.3-171744.43" + process $proc$libresoc.v:171743$9362 + assign { } { } + assign $0\xer_ca_ok$25[0:0]$9363 \xer_ca_ok$25$next + sync posedge \coresync_clk + update \xer_ca_ok$25 $0\xer_ca_ok$25[0:0]$9363 + end + attribute \src "libresoc.v:171745.3-171746.33" + process $proc$libresoc.v:171745$9364 + assign { } { } + assign $0\cr_a$22[3:0]$9365 \cr_a$22$next + sync posedge \coresync_clk + update \cr_a$22 $0\cr_a$22[3:0]$9365 + end + attribute \src "libresoc.v:171747.3-171748.39" + process $proc$libresoc.v:171747$9366 + assign { } { } + assign $0\cr_a_ok$23[0:0]$9367 \cr_a_ok$23$next + sync posedge \coresync_clk + update \cr_a_ok$23 $0\cr_a_ok$23[0:0]$9367 + end + attribute \src "libresoc.v:171749.3-171750.27" + process $proc$libresoc.v:171749$9368 + assign { } { } + assign $0\o$20[63:0]$9369 \o$20$next + sync posedge \coresync_clk + update \o$20 $0\o$20[63:0]$9369 + end + attribute \src "libresoc.v:171751.3-171752.33" + process $proc$libresoc.v:171751$9370 + assign { } { } + assign $0\o_ok$21[0:0]$9371 \o_ok$21$next + sync posedge \coresync_clk + update \o_ok$21 $0\o_ok$21[0:0]$9371 + end + attribute \src "libresoc.v:171753.3-171754.57" + process $proc$libresoc.v:171753$9372 + assign { } { } + assign $0\alu_op__insn_type$2[6:0]$9373 \alu_op__insn_type$2$next + sync posedge \coresync_clk + update \alu_op__insn_type$2 $0\alu_op__insn_type$2[6:0]$9373 + end + attribute \src "libresoc.v:171755.3-171756.53" + process $proc$libresoc.v:171755$9374 + assign { } { } + assign $0\alu_op__fn_unit$3[12:0]$9375 \alu_op__fn_unit$3$next + sync posedge \coresync_clk + update \alu_op__fn_unit$3 $0\alu_op__fn_unit$3[12:0]$9375 + end + attribute \src "libresoc.v:171757.3-171758.67" + process $proc$libresoc.v:171757$9376 + assign { } { } + assign $0\alu_op__imm_data__data$4[63:0]$9377 \alu_op__imm_data__data$4$next + sync posedge \coresync_clk + update \alu_op__imm_data__data$4 $0\alu_op__imm_data__data$4[63:0]$9377 + end + attribute \src "libresoc.v:171759.3-171760.63" + process $proc$libresoc.v:171759$9378 + assign { } { } + assign $0\alu_op__imm_data__ok$5[0:0]$9379 \alu_op__imm_data__ok$5$next + sync posedge \coresync_clk + update \alu_op__imm_data__ok$5 $0\alu_op__imm_data__ok$5[0:0]$9379 + end + attribute \src "libresoc.v:171761.3-171762.51" + process $proc$libresoc.v:171761$9380 + assign { } { } + assign $0\alu_op__rc__rc$6[0:0]$9381 \alu_op__rc__rc$6$next + sync posedge \coresync_clk + update \alu_op__rc__rc$6 $0\alu_op__rc__rc$6[0:0]$9381 + end + attribute \src "libresoc.v:171763.3-171764.51" + process $proc$libresoc.v:171763$9382 + assign { } { } + assign $0\alu_op__rc__ok$7[0:0]$9383 \alu_op__rc__ok$7$next + sync posedge \coresync_clk + update \alu_op__rc__ok$7 $0\alu_op__rc__ok$7[0:0]$9383 + end + attribute \src "libresoc.v:171765.3-171766.51" + process $proc$libresoc.v:171765$9384 + assign { } { } + assign $0\alu_op__oe__oe$8[0:0]$9385 \alu_op__oe__oe$8$next + sync posedge \coresync_clk + update \alu_op__oe__oe$8 $0\alu_op__oe__oe$8[0:0]$9385 + end + attribute \src "libresoc.v:171767.3-171768.51" + process $proc$libresoc.v:171767$9386 + assign { } { } + assign $0\alu_op__oe__ok$9[0:0]$9387 \alu_op__oe__ok$9$next + sync posedge \coresync_clk + update \alu_op__oe__ok$9 $0\alu_op__oe__ok$9[0:0]$9387 + end + attribute \src "libresoc.v:171769.3-171770.59" + process $proc$libresoc.v:171769$9388 + assign { } { } + assign $0\alu_op__invert_in$10[0:0]$9389 \alu_op__invert_in$10$next + sync posedge \coresync_clk + update \alu_op__invert_in$10 $0\alu_op__invert_in$10[0:0]$9389 + end + attribute \src "libresoc.v:171771.3-171772.53" + process $proc$libresoc.v:171771$9390 + assign { } { } + assign $0\alu_op__zero_a$11[0:0]$9391 \alu_op__zero_a$11$next + sync posedge \coresync_clk + update \alu_op__zero_a$11 $0\alu_op__zero_a$11[0:0]$9391 + end + attribute \src "libresoc.v:171773.3-171774.61" + process $proc$libresoc.v:171773$9392 + assign { } { } + assign $0\alu_op__invert_out$12[0:0]$9393 \alu_op__invert_out$12$next + sync posedge \coresync_clk + update \alu_op__invert_out$12 $0\alu_op__invert_out$12[0:0]$9393 + end + attribute \src "libresoc.v:171775.3-171776.59" + process $proc$libresoc.v:171775$9394 + assign { } { } + assign $0\alu_op__write_cr0$13[0:0]$9395 \alu_op__write_cr0$13$next + sync posedge \coresync_clk + update \alu_op__write_cr0$13 $0\alu_op__write_cr0$13[0:0]$9395 + end + attribute \src "libresoc.v:171777.3-171778.63" + process $proc$libresoc.v:171777$9396 + assign { } { } + assign $0\alu_op__input_carry$14[1:0]$9397 \alu_op__input_carry$14$next + sync posedge \coresync_clk + update \alu_op__input_carry$14 $0\alu_op__input_carry$14[1:0]$9397 + end + attribute \src "libresoc.v:171779.3-171780.65" + process $proc$libresoc.v:171779$9398 + assign { } { } + assign $0\alu_op__output_carry$15[0:0]$9399 \alu_op__output_carry$15$next + sync posedge \coresync_clk + update \alu_op__output_carry$15 $0\alu_op__output_carry$15[0:0]$9399 + end + attribute \src "libresoc.v:171781.3-171782.57" + process $proc$libresoc.v:171781$9400 + assign { } { } + assign $0\alu_op__is_32bit$16[0:0]$9401 \alu_op__is_32bit$16$next + sync posedge \coresync_clk + update \alu_op__is_32bit$16 $0\alu_op__is_32bit$16[0:0]$9401 + end + attribute \src "libresoc.v:171783.3-171784.59" + process $proc$libresoc.v:171783$9402 + assign { } { } + assign $0\alu_op__is_signed$17[0:0]$9403 \alu_op__is_signed$17$next + sync posedge \coresync_clk + update \alu_op__is_signed$17 $0\alu_op__is_signed$17[0:0]$9403 + end + attribute \src "libresoc.v:171785.3-171786.57" + process $proc$libresoc.v:171785$9404 + assign { } { } + assign $0\alu_op__data_len$18[3:0]$9405 \alu_op__data_len$18$next + sync posedge \coresync_clk + update \alu_op__data_len$18 $0\alu_op__data_len$18[3:0]$9405 + end + attribute \src "libresoc.v:171787.3-171788.49" + process $proc$libresoc.v:171787$9406 + assign { } { } + assign $0\alu_op__insn$19[31:0]$9407 \alu_op__insn$19$next + sync posedge \coresync_clk + update \alu_op__insn$19 $0\alu_op__insn$19[31:0]$9407 + end + attribute \src "libresoc.v:171789.3-171790.33" + process $proc$libresoc.v:171789$9408 + assign { } { } + assign $0\muxid$1[1:0]$9409 \muxid$1$next + sync posedge \coresync_clk + update \muxid$1 $0\muxid$1[1:0]$9409 + end + attribute \src "libresoc.v:171791.3-171792.29" + process $proc$libresoc.v:171791$9410 + assign { } { } + assign $0\r_busy[0:0] \r_busy$next + sync posedge \coresync_clk + update \r_busy $0\r_busy[0:0] + end + attribute \src "libresoc.v:171857.3-171874.6" + process $proc$libresoc.v:171857$9411 + assign { } { } + assign { } { } + assign { } { } + assign $0\r_busy$next[0:0]$9412 $2\r_busy$next[0:0]$9414 + attribute \src "libresoc.v:171858.5-171858.29" + switch \initial + attribute \src "libresoc.v:171858.9-171858.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\r_busy$next[0:0]$9413 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\r_busy$next[0:0]$9413 1'0 + case + assign $1\r_busy$next[0:0]$9413 \r_busy + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r_busy$next[0:0]$9414 1'0 + case + assign $2\r_busy$next[0:0]$9414 $1\r_busy$next[0:0]$9413 + end + sync always + update \r_busy$next $0\r_busy$next[0:0]$9412 + end + attribute \src "libresoc.v:171875.3-171887.6" + process $proc$libresoc.v:171875$9415 + assign { } { } + assign { } { } + assign $0\muxid$1$next[1:0]$9416 $1\muxid$1$next[1:0]$9417 + attribute \src "libresoc.v:171876.5-171876.29" + switch \initial + attribute \src "libresoc.v:171876.9-171876.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\muxid$1$next[1:0]$9417 \muxid$62 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\muxid$1$next[1:0]$9417 \muxid$62 + case + assign $1\muxid$1$next[1:0]$9417 \muxid$1 + end + sync always + update \muxid$1$next $0\muxid$1$next[1:0]$9416 + end + attribute \src "libresoc.v:171888.3-171929.6" + process $proc$libresoc.v:171888$9418 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\alu_op__data_len$18$next[3:0]$9419 $1\alu_op__data_len$18$next[3:0]$9437 + assign $0\alu_op__fn_unit$3$next[12:0]$9420 $1\alu_op__fn_unit$3$next[12:0]$9438 + assign { } { } + assign { } { } + assign $0\alu_op__input_carry$14$next[1:0]$9423 $1\alu_op__input_carry$14$next[1:0]$9441 + assign $0\alu_op__insn$19$next[31:0]$9424 $1\alu_op__insn$19$next[31:0]$9442 + assign $0\alu_op__insn_type$2$next[6:0]$9425 $1\alu_op__insn_type$2$next[6:0]$9443 + assign $0\alu_op__invert_in$10$next[0:0]$9426 $1\alu_op__invert_in$10$next[0:0]$9444 + assign $0\alu_op__invert_out$12$next[0:0]$9427 $1\alu_op__invert_out$12$next[0:0]$9445 + assign $0\alu_op__is_32bit$16$next[0:0]$9428 $1\alu_op__is_32bit$16$next[0:0]$9446 + assign $0\alu_op__is_signed$17$next[0:0]$9429 $1\alu_op__is_signed$17$next[0:0]$9447 + assign { } { } + assign { } { } + assign $0\alu_op__output_carry$15$next[0:0]$9432 $1\alu_op__output_carry$15$next[0:0]$9450 + assign { } { } + assign { } { } + assign $0\alu_op__write_cr0$13$next[0:0]$9435 $1\alu_op__write_cr0$13$next[0:0]$9453 + assign $0\alu_op__zero_a$11$next[0:0]$9436 $1\alu_op__zero_a$11$next[0:0]$9454 + assign $0\alu_op__imm_data__data$4$next[63:0]$9421 $2\alu_op__imm_data__data$4$next[63:0]$9455 + assign $0\alu_op__imm_data__ok$5$next[0:0]$9422 $2\alu_op__imm_data__ok$5$next[0:0]$9456 + assign $0\alu_op__oe__oe$8$next[0:0]$9430 $2\alu_op__oe__oe$8$next[0:0]$9457 + assign $0\alu_op__oe__ok$9$next[0:0]$9431 $2\alu_op__oe__ok$9$next[0:0]$9458 + assign $0\alu_op__rc__ok$7$next[0:0]$9433 $2\alu_op__rc__ok$7$next[0:0]$9459 + assign $0\alu_op__rc__rc$6$next[0:0]$9434 $2\alu_op__rc__rc$6$next[0:0]$9460 + attribute \src "libresoc.v:171889.5-171889.29" + switch \initial + attribute \src "libresoc.v:171889.9-171889.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\alu_op__insn$19$next[31:0]$9442 $1\alu_op__data_len$18$next[3:0]$9437 $1\alu_op__is_signed$17$next[0:0]$9447 $1\alu_op__is_32bit$16$next[0:0]$9446 $1\alu_op__output_carry$15$next[0:0]$9450 $1\alu_op__input_carry$14$next[1:0]$9441 $1\alu_op__write_cr0$13$next[0:0]$9453 $1\alu_op__invert_out$12$next[0:0]$9445 $1\alu_op__zero_a$11$next[0:0]$9454 $1\alu_op__invert_in$10$next[0:0]$9444 $1\alu_op__oe__ok$9$next[0:0]$9449 $1\alu_op__oe__oe$8$next[0:0]$9448 $1\alu_op__rc__ok$7$next[0:0]$9451 $1\alu_op__rc__rc$6$next[0:0]$9452 $1\alu_op__imm_data__ok$5$next[0:0]$9440 $1\alu_op__imm_data__data$4$next[63:0]$9439 $1\alu_op__fn_unit$3$next[12:0]$9438 $1\alu_op__insn_type$2$next[6:0]$9443 } { \alu_op__insn$80 \alu_op__data_len$79 \alu_op__is_signed$78 \alu_op__is_32bit$77 \alu_op__output_carry$76 \alu_op__input_carry$75 \alu_op__write_cr0$74 \alu_op__invert_out$73 \alu_op__zero_a$72 \alu_op__invert_in$71 \alu_op__oe__ok$70 \alu_op__oe__oe$69 \alu_op__rc__ok$68 \alu_op__rc__rc$67 \alu_op__imm_data__ok$66 \alu_op__imm_data__data$65 \alu_op__fn_unit$64 \alu_op__insn_type$63 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\alu_op__insn$19$next[31:0]$9442 $1\alu_op__data_len$18$next[3:0]$9437 $1\alu_op__is_signed$17$next[0:0]$9447 $1\alu_op__is_32bit$16$next[0:0]$9446 $1\alu_op__output_carry$15$next[0:0]$9450 $1\alu_op__input_carry$14$next[1:0]$9441 $1\alu_op__write_cr0$13$next[0:0]$9453 $1\alu_op__invert_out$12$next[0:0]$9445 $1\alu_op__zero_a$11$next[0:0]$9454 $1\alu_op__invert_in$10$next[0:0]$9444 $1\alu_op__oe__ok$9$next[0:0]$9449 $1\alu_op__oe__oe$8$next[0:0]$9448 $1\alu_op__rc__ok$7$next[0:0]$9451 $1\alu_op__rc__rc$6$next[0:0]$9452 $1\alu_op__imm_data__ok$5$next[0:0]$9440 $1\alu_op__imm_data__data$4$next[63:0]$9439 $1\alu_op__fn_unit$3$next[12:0]$9438 $1\alu_op__insn_type$2$next[6:0]$9443 } { \alu_op__insn$80 \alu_op__data_len$79 \alu_op__is_signed$78 \alu_op__is_32bit$77 \alu_op__output_carry$76 \alu_op__input_carry$75 \alu_op__write_cr0$74 \alu_op__invert_out$73 \alu_op__zero_a$72 \alu_op__invert_in$71 \alu_op__oe__ok$70 \alu_op__oe__oe$69 \alu_op__rc__ok$68 \alu_op__rc__rc$67 \alu_op__imm_data__ok$66 \alu_op__imm_data__data$65 \alu_op__fn_unit$64 \alu_op__insn_type$63 } + case + assign $1\alu_op__data_len$18$next[3:0]$9437 \alu_op__data_len$18 + assign $1\alu_op__fn_unit$3$next[12:0]$9438 \alu_op__fn_unit$3 + assign $1\alu_op__imm_data__data$4$next[63:0]$9439 \alu_op__imm_data__data$4 + assign $1\alu_op__imm_data__ok$5$next[0:0]$9440 \alu_op__imm_data__ok$5 + assign $1\alu_op__input_carry$14$next[1:0]$9441 \alu_op__input_carry$14 + assign $1\alu_op__insn$19$next[31:0]$9442 \alu_op__insn$19 + assign $1\alu_op__insn_type$2$next[6:0]$9443 \alu_op__insn_type$2 + assign $1\alu_op__invert_in$10$next[0:0]$9444 \alu_op__invert_in$10 + assign $1\alu_op__invert_out$12$next[0:0]$9445 \alu_op__invert_out$12 + assign $1\alu_op__is_32bit$16$next[0:0]$9446 \alu_op__is_32bit$16 + assign $1\alu_op__is_signed$17$next[0:0]$9447 \alu_op__is_signed$17 + assign $1\alu_op__oe__oe$8$next[0:0]$9448 \alu_op__oe__oe$8 + assign $1\alu_op__oe__ok$9$next[0:0]$9449 \alu_op__oe__ok$9 + assign $1\alu_op__output_carry$15$next[0:0]$9450 \alu_op__output_carry$15 + assign $1\alu_op__rc__ok$7$next[0:0]$9451 \alu_op__rc__ok$7 + assign $1\alu_op__rc__rc$6$next[0:0]$9452 \alu_op__rc__rc$6 + assign $1\alu_op__write_cr0$13$next[0:0]$9453 \alu_op__write_cr0$13 + assign $1\alu_op__zero_a$11$next[0:0]$9454 \alu_op__zero_a$11 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $2\alu_op__imm_data__data$4$next[63:0]$9455 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\alu_op__imm_data__ok$5$next[0:0]$9456 1'0 + assign $2\alu_op__rc__rc$6$next[0:0]$9460 1'0 + assign $2\alu_op__rc__ok$7$next[0:0]$9459 1'0 + assign $2\alu_op__oe__oe$8$next[0:0]$9457 1'0 + assign $2\alu_op__oe__ok$9$next[0:0]$9458 1'0 + case + assign $2\alu_op__imm_data__data$4$next[63:0]$9455 $1\alu_op__imm_data__data$4$next[63:0]$9439 + assign $2\alu_op__imm_data__ok$5$next[0:0]$9456 $1\alu_op__imm_data__ok$5$next[0:0]$9440 + assign $2\alu_op__oe__oe$8$next[0:0]$9457 $1\alu_op__oe__oe$8$next[0:0]$9448 + assign $2\alu_op__oe__ok$9$next[0:0]$9458 $1\alu_op__oe__ok$9$next[0:0]$9449 + assign $2\alu_op__rc__ok$7$next[0:0]$9459 $1\alu_op__rc__ok$7$next[0:0]$9451 + assign $2\alu_op__rc__rc$6$next[0:0]$9460 $1\alu_op__rc__rc$6$next[0:0]$9452 + end + sync always + update \alu_op__data_len$18$next $0\alu_op__data_len$18$next[3:0]$9419 + update \alu_op__fn_unit$3$next $0\alu_op__fn_unit$3$next[12:0]$9420 + update \alu_op__imm_data__data$4$next $0\alu_op__imm_data__data$4$next[63:0]$9421 + update \alu_op__imm_data__ok$5$next $0\alu_op__imm_data__ok$5$next[0:0]$9422 + update \alu_op__input_carry$14$next $0\alu_op__input_carry$14$next[1:0]$9423 + update \alu_op__insn$19$next $0\alu_op__insn$19$next[31:0]$9424 + update \alu_op__insn_type$2$next $0\alu_op__insn_type$2$next[6:0]$9425 + update \alu_op__invert_in$10$next $0\alu_op__invert_in$10$next[0:0]$9426 + update \alu_op__invert_out$12$next $0\alu_op__invert_out$12$next[0:0]$9427 + update \alu_op__is_32bit$16$next $0\alu_op__is_32bit$16$next[0:0]$9428 + update \alu_op__is_signed$17$next $0\alu_op__is_signed$17$next[0:0]$9429 + update \alu_op__oe__oe$8$next $0\alu_op__oe__oe$8$next[0:0]$9430 + update \alu_op__oe__ok$9$next $0\alu_op__oe__ok$9$next[0:0]$9431 + update \alu_op__output_carry$15$next $0\alu_op__output_carry$15$next[0:0]$9432 + update \alu_op__rc__ok$7$next $0\alu_op__rc__ok$7$next[0:0]$9433 + update \alu_op__rc__rc$6$next $0\alu_op__rc__rc$6$next[0:0]$9434 + update \alu_op__write_cr0$13$next $0\alu_op__write_cr0$13$next[0:0]$9435 + update \alu_op__zero_a$11$next $0\alu_op__zero_a$11$next[0:0]$9436 + end + attribute \src "libresoc.v:171930.3-171948.6" + process $proc$libresoc.v:171930$9461 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\o$20$next[63:0]$9462 $1\o$20$next[63:0]$9464 + assign { } { } + assign $0\o_ok$21$next[0:0]$9463 $2\o_ok$21$next[0:0]$9466 + attribute \src "libresoc.v:171931.5-171931.29" + switch \initial + attribute \src "libresoc.v:171931.9-171931.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\o_ok$21$next[0:0]$9465 $1\o$20$next[63:0]$9464 } { \o_ok$82 \o$81 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\o_ok$21$next[0:0]$9465 $1\o$20$next[63:0]$9464 } { \o_ok$82 \o$81 } + case + assign $1\o$20$next[63:0]$9464 \o$20 + assign $1\o_ok$21$next[0:0]$9465 \o_ok$21 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\o_ok$21$next[0:0]$9466 1'0 + case + assign $2\o_ok$21$next[0:0]$9466 $1\o_ok$21$next[0:0]$9465 + end + sync always + update \o$20$next $0\o$20$next[63:0]$9462 + update \o_ok$21$next $0\o_ok$21$next[0:0]$9463 + end + attribute \src "libresoc.v:171949.3-171967.6" + process $proc$libresoc.v:171949$9467 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\cr_a$22$next[3:0]$9468 $1\cr_a$22$next[3:0]$9470 + assign { } { } + assign $0\cr_a_ok$23$next[0:0]$9469 $2\cr_a_ok$23$next[0:0]$9472 + attribute \src "libresoc.v:171950.5-171950.29" + switch \initial + attribute \src "libresoc.v:171950.9-171950.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\cr_a_ok$23$next[0:0]$9471 $1\cr_a$22$next[3:0]$9470 } { \cr_a_ok$84 \cr_a$83 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\cr_a_ok$23$next[0:0]$9471 $1\cr_a$22$next[3:0]$9470 } { \cr_a_ok$84 \cr_a$83 } + case + assign $1\cr_a$22$next[3:0]$9470 \cr_a$22 + assign $1\cr_a_ok$23$next[0:0]$9471 \cr_a_ok$23 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_a_ok$23$next[0:0]$9472 1'0 + case + assign $2\cr_a_ok$23$next[0:0]$9472 $1\cr_a_ok$23$next[0:0]$9471 + end + sync always + update \cr_a$22$next $0\cr_a$22$next[3:0]$9468 + update \cr_a_ok$23$next $0\cr_a_ok$23$next[0:0]$9469 + end + attribute \src "libresoc.v:171968.3-171986.6" + process $proc$libresoc.v:171968$9473 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\xer_ca$24$next[1:0]$9474 $1\xer_ca$24$next[1:0]$9476 + assign { } { } + assign $0\xer_ca_ok$25$next[0:0]$9475 $2\xer_ca_ok$25$next[0:0]$9478 + attribute \src "libresoc.v:171969.5-171969.29" + switch \initial + attribute \src "libresoc.v:171969.9-171969.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\xer_ca_ok$25$next[0:0]$9477 $1\xer_ca$24$next[1:0]$9476 } { \xer_ca_ok$86 \xer_ca$85 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\xer_ca_ok$25$next[0:0]$9477 $1\xer_ca$24$next[1:0]$9476 } { \xer_ca_ok$86 \xer_ca$85 } + case + assign $1\xer_ca$24$next[1:0]$9476 \xer_ca$24 + assign $1\xer_ca_ok$25$next[0:0]$9477 \xer_ca_ok$25 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\xer_ca_ok$25$next[0:0]$9478 1'0 + case + assign $2\xer_ca_ok$25$next[0:0]$9478 $1\xer_ca_ok$25$next[0:0]$9477 + end + sync always + update \xer_ca$24$next $0\xer_ca$24$next[1:0]$9474 + update \xer_ca_ok$25$next $0\xer_ca_ok$25$next[0:0]$9475 + end + attribute \src "libresoc.v:171987.3-172005.6" + process $proc$libresoc.v:171987$9479 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\xer_ov$26$next[1:0]$9480 $1\xer_ov$26$next[1:0]$9482 + assign { } { } + assign $0\xer_ov_ok$27$next[0:0]$9481 $2\xer_ov_ok$27$next[0:0]$9484 + attribute \src "libresoc.v:171988.5-171988.29" + switch \initial + attribute \src "libresoc.v:171988.9-171988.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\xer_ov_ok$27$next[0:0]$9483 $1\xer_ov$26$next[1:0]$9482 } { \xer_ov_ok$88 \xer_ov$87 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\xer_ov_ok$27$next[0:0]$9483 $1\xer_ov$26$next[1:0]$9482 } { \xer_ov_ok$88 \xer_ov$87 } + case + assign $1\xer_ov$26$next[1:0]$9482 \xer_ov$26 + assign $1\xer_ov_ok$27$next[0:0]$9483 \xer_ov_ok$27 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\xer_ov_ok$27$next[0:0]$9484 1'0 + case + assign $2\xer_ov_ok$27$next[0:0]$9484 $1\xer_ov_ok$27$next[0:0]$9483 + end + sync always + update \xer_ov$26$next $0\xer_ov$26$next[1:0]$9480 + update \xer_ov_ok$27$next $0\xer_ov_ok$27$next[0:0]$9481 + end + attribute \src "libresoc.v:172006.3-172024.6" + process $proc$libresoc.v:172006$9485 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\xer_so$28$next[0:0]$9486 $1\xer_so$28$next[0:0]$9488 + assign { } { } + assign $0\xer_so_ok$29$next[0:0]$9487 $2\xer_so_ok$29$next[0:0]$9490 + attribute \src "libresoc.v:172007.5-172007.29" + switch \initial + attribute \src "libresoc.v:172007.9-172007.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\xer_so_ok$29$next[0:0]$9489 $1\xer_so$28$next[0:0]$9488 } { \xer_so_ok$90 \xer_so$89 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\xer_so_ok$29$next[0:0]$9489 $1\xer_so$28$next[0:0]$9488 } { \xer_so_ok$90 \xer_so$89 } + case + assign $1\xer_so$28$next[0:0]$9488 \xer_so$28 + assign $1\xer_so_ok$29$next[0:0]$9489 \xer_so_ok$29 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\xer_so_ok$29$next[0:0]$9490 1'0 + case + assign $2\xer_so_ok$29$next[0:0]$9490 $1\xer_so_ok$29$next[0:0]$9489 + end + sync always + update \xer_so$28$next $0\xer_so$28$next[0:0]$9486 + update \xer_so_ok$29$next $0\xer_so_ok$29$next[0:0]$9487 + end + connect \$60 $and$libresoc.v:171732$9351_Y + connect \p_ready_o \n_i_rdy_data + connect \n_valid_o \r_busy + connect { \xer_so_ok$90 \xer_so$89 } { \output_xer_so_ok \output_xer_so$54 } + connect { \xer_ov_ok$88 \xer_ov$87 } { \output_xer_ov_ok \output_xer_ov$53 } + connect { \xer_ca_ok$86 \xer_ca$85 } { \output_xer_ca_ok \output_xer_ca$52 } + connect { \cr_a_ok$84 \cr_a$83 } { \output_cr_a_ok \output_cr_a$51 } + connect { \o_ok$82 \o$81 } { \output_o_ok$50 \output_o$49 } + connect { \alu_op__insn$80 \alu_op__data_len$79 \alu_op__is_signed$78 \alu_op__is_32bit$77 \alu_op__output_carry$76 \alu_op__input_carry$75 \alu_op__write_cr0$74 \alu_op__invert_out$73 \alu_op__zero_a$72 \alu_op__invert_in$71 \alu_op__oe__ok$70 \alu_op__oe__oe$69 \alu_op__rc__ok$68 \alu_op__rc__rc$67 \alu_op__imm_data__ok$66 \alu_op__imm_data__data$65 \alu_op__fn_unit$64 \alu_op__insn_type$63 } { \output_alu_op__insn$48 \output_alu_op__data_len$47 \output_alu_op__is_signed$46 \output_alu_op__is_32bit$45 \output_alu_op__output_carry$44 \output_alu_op__input_carry$43 \output_alu_op__write_cr0$42 \output_alu_op__invert_out$41 \output_alu_op__zero_a$40 \output_alu_op__invert_in$39 \output_alu_op__oe__ok$38 \output_alu_op__oe__oe$37 \output_alu_op__rc__ok$36 \output_alu_op__rc__rc$35 \output_alu_op__imm_data__ok$34 \output_alu_op__imm_data__data$33 \output_alu_op__fn_unit$32 \output_alu_op__insn_type$31 } + connect \muxid$62 \output_muxid$30 + connect \p_valid_i_p_ready_o \$60 + connect \n_i_rdy_data \n_ready_i + connect \p_valid_i$59 \p_valid_i + connect { \xer_so_ok$58 \output_xer_so } { \xer_so_ok \xer_so } + connect { \xer_ov_ok$57 \output_xer_ov } { \xer_ov_ok \xer_ov } + connect { \xer_ca_ok$56 \output_xer_ca } { \xer_ca_ok \xer_ca } + connect { \cr_a_ok$55 \output_cr_a } { \cr_a_ok \cr_a } + connect { \output_o_ok \output_o } { \o_ok \o } + connect { \output_alu_op__insn \output_alu_op__data_len \output_alu_op__is_signed \output_alu_op__is_32bit \output_alu_op__output_carry \output_alu_op__input_carry \output_alu_op__write_cr0 \output_alu_op__invert_out \output_alu_op__zero_a \output_alu_op__invert_in \output_alu_op__oe__ok \output_alu_op__oe__oe \output_alu_op__rc__ok \output_alu_op__rc__rc \output_alu_op__imm_data__ok \output_alu_op__imm_data__data \output_alu_op__fn_unit \output_alu_op__insn_type } { \alu_op__insn \alu_op__data_len \alu_op__is_signed \alu_op__is_32bit \alu_op__output_carry \alu_op__input_carry \alu_op__write_cr0 \alu_op__invert_out \alu_op__zero_a \alu_op__invert_in \alu_op__oe__ok \alu_op__oe__oe \alu_op__rc__ok \alu_op__rc__rc \alu_op__imm_data__ok \alu_op__imm_data__data \alu_op__fn_unit \alu_op__insn_type } + connect \output_muxid \muxid +end +attribute \src "libresoc.v:172048.1-173107.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe2" +attribute \generator "nMigen" +module \pipe2$115 + attribute \src "libresoc.v:173053.3-173071.6" + wire width 4 $0\cr_a$21$next[3:0]$9656 + attribute \src "libresoc.v:172859.3-172860.33" + wire width 4 $0\cr_a$21[3:0]$9557 + attribute \src "libresoc.v:172060.13-172060.29" + wire width 4 $0\cr_a$21[3:0]$9669 + attribute \src "libresoc.v:173053.3-173071.6" + wire $0\cr_a_ok$22$next[0:0]$9657 + attribute \src "libresoc.v:172861.3-172862.39" + wire $0\cr_a_ok$22[0:0]$9559 + attribute \src "libresoc.v:172069.7-172069.26" + wire $0\cr_a_ok$22[0:0]$9671 + attribute \src "libresoc.v:172049.7-172049.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:172980.3-172992.6" + wire width 2 $0\muxid$1$next[1:0]$9606 + attribute \src "libresoc.v:172901.3-172902.33" + wire width 2 $0\muxid$1[1:0]$9599 + attribute \src "libresoc.v:172080.13-172080.29" + wire width 2 $0\muxid$1[1:0]$9673 + attribute \src "libresoc.v:173034.3-173052.6" + wire width 64 $0\o$19$next[63:0]$9650 + attribute \src "libresoc.v:172863.3-172864.27" + wire width 64 $0\o$19[63:0]$9561 + attribute \src "libresoc.v:172095.14-172095.43" + wire width 64 $0\o$19[63:0]$9675 + attribute \src "libresoc.v:173034.3-173052.6" + wire $0\o_ok$20$next[0:0]$9651 + attribute \src "libresoc.v:172865.3-172866.33" + wire $0\o_ok$20[0:0]$9563 + attribute \src "libresoc.v:172104.7-172104.23" + wire $0\o_ok$20[0:0]$9677 + attribute \src "libresoc.v:172962.3-172979.6" + wire $0\r_busy$next[0:0]$9602 + attribute \src "libresoc.v:172903.3-172904.29" + wire $0\r_busy[0:0] + attribute \src "libresoc.v:172993.3-173033.6" + wire width 13 $0\sr_op__fn_unit$3$next[12:0]$9609 + attribute \src "libresoc.v:172869.3-172870.51" + wire width 13 $0\sr_op__fn_unit$3[12:0]$9567 + attribute \src "libresoc.v:172431.14-172431.43" + wire width 13 $0\sr_op__fn_unit$3[12:0]$9680 + attribute \src "libresoc.v:172993.3-173033.6" + wire width 64 $0\sr_op__imm_data__data$4$next[63:0]$9610 + attribute \src "libresoc.v:172871.3-172872.65" + wire width 64 $0\sr_op__imm_data__data$4[63:0]$9569 + attribute \src "libresoc.v:172454.14-172454.62" + wire width 64 $0\sr_op__imm_data__data$4[63:0]$9682 + attribute \src "libresoc.v:172993.3-173033.6" + wire $0\sr_op__imm_data__ok$5$next[0:0]$9611 + attribute \src "libresoc.v:172873.3-172874.61" + wire $0\sr_op__imm_data__ok$5[0:0]$9571 + attribute \src "libresoc.v:172463.7-172463.37" + wire $0\sr_op__imm_data__ok$5[0:0]$9684 + attribute \src "libresoc.v:172993.3-173033.6" + wire width 2 $0\sr_op__input_carry$12$next[1:0]$9612 + attribute \src "libresoc.v:172887.3-172888.61" + wire width 2 $0\sr_op__input_carry$12[1:0]$9585 + attribute \src "libresoc.v:172480.13-172480.43" + wire width 2 $0\sr_op__input_carry$12[1:0]$9686 + attribute \src "libresoc.v:172993.3-173033.6" + wire $0\sr_op__input_cr$14$next[0:0]$9613 + attribute \src "libresoc.v:172891.3-172892.55" + wire $0\sr_op__input_cr$14[0:0]$9589 + attribute \src "libresoc.v:172493.7-172493.34" + wire $0\sr_op__input_cr$14[0:0]$9688 + attribute \src "libresoc.v:172993.3-173033.6" + wire width 32 $0\sr_op__insn$18$next[31:0]$9614 + attribute \src "libresoc.v:172899.3-172900.47" + wire width 32 $0\sr_op__insn$18[31:0]$9597 + attribute \src "libresoc.v:172502.14-172502.38" + wire width 32 $0\sr_op__insn$18[31:0]$9690 + attribute \src "libresoc.v:172993.3-173033.6" + wire width 7 $0\sr_op__insn_type$2$next[6:0]$9615 + attribute \src "libresoc.v:172867.3-172868.55" + wire width 7 $0\sr_op__insn_type$2[6:0]$9565 + attribute \src "libresoc.v:172659.13-172659.41" + wire width 7 $0\sr_op__insn_type$2[6:0]$9692 + attribute \src "libresoc.v:172993.3-173033.6" + wire $0\sr_op__invert_in$11$next[0:0]$9616 + attribute \src "libresoc.v:172885.3-172886.57" + wire $0\sr_op__invert_in$11[0:0]$9583 + attribute \src "libresoc.v:172742.7-172742.35" + wire $0\sr_op__invert_in$11[0:0]$9694 + attribute \src "libresoc.v:172993.3-173033.6" + wire $0\sr_op__is_32bit$16$next[0:0]$9617 + attribute \src "libresoc.v:172895.3-172896.55" + wire $0\sr_op__is_32bit$16[0:0]$9593 + attribute \src "libresoc.v:172751.7-172751.34" + wire $0\sr_op__is_32bit$16[0:0]$9696 + attribute \src "libresoc.v:172993.3-173033.6" + wire $0\sr_op__is_signed$17$next[0:0]$9618 + attribute \src "libresoc.v:172897.3-172898.57" + wire $0\sr_op__is_signed$17[0:0]$9595 + attribute \src "libresoc.v:172760.7-172760.35" + wire $0\sr_op__is_signed$17[0:0]$9698 + attribute \src "libresoc.v:172993.3-173033.6" + wire $0\sr_op__oe__oe$8$next[0:0]$9619 + attribute \src "libresoc.v:172879.3-172880.49" + wire $0\sr_op__oe__oe$8[0:0]$9577 + attribute \src "libresoc.v:172771.7-172771.31" + wire $0\sr_op__oe__oe$8[0:0]$9700 + attribute \src "libresoc.v:172993.3-173033.6" + wire $0\sr_op__oe__ok$9$next[0:0]$9620 + attribute \src "libresoc.v:172881.3-172882.49" + wire $0\sr_op__oe__ok$9[0:0]$9579 + attribute \src "libresoc.v:172780.7-172780.31" + wire $0\sr_op__oe__ok$9[0:0]$9702 + attribute \src "libresoc.v:172993.3-173033.6" + wire $0\sr_op__output_carry$13$next[0:0]$9621 + attribute \src "libresoc.v:172889.3-172890.63" + wire $0\sr_op__output_carry$13[0:0]$9587 + attribute \src "libresoc.v:172787.7-172787.38" + wire $0\sr_op__output_carry$13[0:0]$9704 + attribute \src "libresoc.v:172993.3-173033.6" + wire $0\sr_op__output_cr$15$next[0:0]$9622 + attribute \src "libresoc.v:172893.3-172894.57" + wire $0\sr_op__output_cr$15[0:0]$9591 + attribute \src "libresoc.v:172796.7-172796.35" + wire $0\sr_op__output_cr$15[0:0]$9706 + attribute \src "libresoc.v:172993.3-173033.6" + wire $0\sr_op__rc__ok$7$next[0:0]$9623 + attribute \src "libresoc.v:172877.3-172878.49" + wire $0\sr_op__rc__ok$7[0:0]$9575 + attribute \src "libresoc.v:172807.7-172807.31" + wire $0\sr_op__rc__ok$7[0:0]$9708 + attribute \src "libresoc.v:172993.3-173033.6" + wire $0\sr_op__rc__rc$6$next[0:0]$9624 + attribute \src "libresoc.v:172875.3-172876.49" + wire $0\sr_op__rc__rc$6[0:0]$9573 + attribute \src "libresoc.v:172816.7-172816.31" + wire $0\sr_op__rc__rc$6[0:0]$9710 + attribute \src "libresoc.v:172993.3-173033.6" + wire $0\sr_op__write_cr0$10$next[0:0]$9625 + attribute \src "libresoc.v:172883.3-172884.57" + wire $0\sr_op__write_cr0$10[0:0]$9581 + attribute \src "libresoc.v:172823.7-172823.35" + wire $0\sr_op__write_cr0$10[0:0]$9712 + attribute \src "libresoc.v:173072.3-173090.6" + wire width 2 $0\xer_ca$23$next[1:0]$9662 + attribute \src "libresoc.v:172855.3-172856.37" + wire width 2 $0\xer_ca$23[1:0]$9553 + attribute \src "libresoc.v:172832.13-172832.31" + wire width 2 $0\xer_ca$23[1:0]$9714 + attribute \src "libresoc.v:173072.3-173090.6" + wire $0\xer_ca_ok$24$next[0:0]$9663 + attribute \src "libresoc.v:172857.3-172858.43" + wire $0\xer_ca_ok$24[0:0]$9555 + attribute \src "libresoc.v:172841.7-172841.28" + wire $0\xer_ca_ok$24[0:0]$9716 + attribute \src "libresoc.v:173053.3-173071.6" + wire width 4 $1\cr_a$21$next[3:0]$9658 + attribute \src "libresoc.v:173053.3-173071.6" + wire $1\cr_a_ok$22$next[0:0]$9659 + attribute \src "libresoc.v:172980.3-172992.6" + wire width 2 $1\muxid$1$next[1:0]$9607 + attribute \src "libresoc.v:173034.3-173052.6" + wire width 64 $1\o$19$next[63:0]$9652 + attribute \src "libresoc.v:173034.3-173052.6" + wire $1\o_ok$20$next[0:0]$9653 + attribute \src "libresoc.v:172962.3-172979.6" + wire $1\r_busy$next[0:0]$9603 + attribute \src "libresoc.v:172396.7-172396.20" + wire $1\r_busy[0:0] + attribute \src "libresoc.v:172993.3-173033.6" + wire width 13 $1\sr_op__fn_unit$3$next[12:0]$9626 + attribute \src "libresoc.v:172993.3-173033.6" + wire width 64 $1\sr_op__imm_data__data$4$next[63:0]$9627 + attribute \src "libresoc.v:172993.3-173033.6" + wire $1\sr_op__imm_data__ok$5$next[0:0]$9628 + attribute \src "libresoc.v:172993.3-173033.6" + wire width 2 $1\sr_op__input_carry$12$next[1:0]$9629 + attribute \src "libresoc.v:172993.3-173033.6" + wire $1\sr_op__input_cr$14$next[0:0]$9630 + attribute \src "libresoc.v:172993.3-173033.6" + wire width 32 $1\sr_op__insn$18$next[31:0]$9631 + attribute \src "libresoc.v:172993.3-173033.6" + wire width 7 $1\sr_op__insn_type$2$next[6:0]$9632 + attribute \src "libresoc.v:172993.3-173033.6" + wire $1\sr_op__invert_in$11$next[0:0]$9633 + attribute \src "libresoc.v:172993.3-173033.6" + wire $1\sr_op__is_32bit$16$next[0:0]$9634 + attribute \src "libresoc.v:172993.3-173033.6" + wire $1\sr_op__is_signed$17$next[0:0]$9635 + attribute \src "libresoc.v:172993.3-173033.6" + wire $1\sr_op__oe__oe$8$next[0:0]$9636 + attribute \src "libresoc.v:172993.3-173033.6" + wire $1\sr_op__oe__ok$9$next[0:0]$9637 + attribute \src "libresoc.v:172993.3-173033.6" + wire $1\sr_op__output_carry$13$next[0:0]$9638 + attribute \src "libresoc.v:172993.3-173033.6" + wire $1\sr_op__output_cr$15$next[0:0]$9639 + attribute \src "libresoc.v:172993.3-173033.6" + wire $1\sr_op__rc__ok$7$next[0:0]$9640 + attribute \src "libresoc.v:172993.3-173033.6" + wire $1\sr_op__rc__rc$6$next[0:0]$9641 + attribute \src "libresoc.v:172993.3-173033.6" + wire $1\sr_op__write_cr0$10$next[0:0]$9642 + attribute \src "libresoc.v:173072.3-173090.6" + wire width 2 $1\xer_ca$23$next[1:0]$9664 + attribute \src "libresoc.v:173072.3-173090.6" + wire $1\xer_ca_ok$24$next[0:0]$9665 + attribute \src "libresoc.v:173053.3-173071.6" + wire $2\cr_a_ok$22$next[0:0]$9660 + attribute \src "libresoc.v:173034.3-173052.6" + wire $2\o_ok$20$next[0:0]$9654 + attribute \src "libresoc.v:172962.3-172979.6" + wire $2\r_busy$next[0:0]$9604 + attribute \src "libresoc.v:172993.3-173033.6" + wire width 64 $2\sr_op__imm_data__data$4$next[63:0]$9643 + attribute \src "libresoc.v:172993.3-173033.6" + wire $2\sr_op__imm_data__ok$5$next[0:0]$9644 + attribute \src "libresoc.v:172993.3-173033.6" + wire $2\sr_op__oe__oe$8$next[0:0]$9645 + attribute \src "libresoc.v:172993.3-173033.6" + wire $2\sr_op__oe__ok$9$next[0:0]$9646 + attribute \src "libresoc.v:172993.3-173033.6" + wire $2\sr_op__rc__ok$7$next[0:0]$9647 + attribute \src "libresoc.v:172993.3-173033.6" + wire $2\sr_op__rc__rc$6$next[0:0]$9648 + attribute \src "libresoc.v:173072.3-173090.6" + wire $2\xer_ca_ok$24$next[0:0]$9666 + attribute \src "libresoc.v:172854.18-172854.118" + wire $and$libresoc.v:172854$9551_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" + wire \$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 56 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 input 24 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 output 52 \cr_a$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \cr_a$21$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \cr_a$73 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire input 25 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 53 \cr_a_ok$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_a_ok$22$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_a_ok$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_a_ok$74 + attribute \src "libresoc.v:172049.7-172049.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 input 4 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 output 32 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid$1$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid$53 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + wire \n_i_rdy_data + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire input 31 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire output 30 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 input 22 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 50 \o$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \o$19$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \o$71 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire input 23 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 51 \o_ok$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \o_ok$20$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \o_ok$72 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \output_cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \output_cr_a$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \output_cr_a_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \output_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \output_muxid$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \output_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \output_o$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \output_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \output_o_ok$44 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \output_sr_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \output_sr_op__fn_unit$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \output_sr_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \output_sr_op__imm_data__data$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_sr_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_sr_op__imm_data__ok$29 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \output_sr_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \output_sr_op__input_carry$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_sr_op__input_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_sr_op__input_cr$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \output_sr_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \output_sr_op__insn$42 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \output_sr_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \output_sr_op__insn_type$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_sr_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_sr_op__invert_in$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_sr_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_sr_op__is_32bit$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_sr_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_sr_op__is_signed$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_sr_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_sr_op__oe__oe$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_sr_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_sr_op__oe__ok$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_sr_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_sr_op__output_carry$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_sr_op__output_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_sr_op__output_cr$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_sr_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_sr_op__rc__ok$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_sr_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_sr_op__rc__rc$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_sr_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_sr_op__write_cr0$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \output_xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \output_xer_ca$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \output_xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \output_xer_so + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" + wire output 3 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" + wire input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" + wire \p_valid_i$50 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" + wire \p_valid_i_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire \r_busy$next + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 input 6 \sr_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 output 34 \sr_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \sr_op__fn_unit$3$next + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \sr_op__fn_unit$55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 7 \sr_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 35 \sr_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \sr_op__imm_data__data$4$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \sr_op__imm_data__data$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \sr_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 36 \sr_op__imm_data__ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__imm_data__ok$5$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__imm_data__ok$57 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 15 \sr_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 43 \sr_op__input_carry$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \sr_op__input_carry$12$next + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \sr_op__input_carry$64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 17 \sr_op__input_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 45 \sr_op__input_cr$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__input_cr$14$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__input_cr$66 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 21 \sr_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 49 \sr_op__insn$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \sr_op__insn$18$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \sr_op__insn$70 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 5 \sr_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 33 \sr_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \sr_op__insn_type$2$next + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \sr_op__insn_type$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \sr_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 42 \sr_op__invert_in$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__invert_in$11$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__invert_in$63 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 19 \sr_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 47 \sr_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__is_32bit$16$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__is_32bit$68 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 20 \sr_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 48 \sr_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__is_signed$17$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__is_signed$69 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 11 \sr_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__oe__oe$60 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 39 \sr_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__oe__oe$8$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \sr_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__oe__ok$61 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 40 \sr_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__oe__ok$9$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 16 \sr_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 44 \sr_op__output_carry$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__output_carry$13$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__output_carry$65 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 18 \sr_op__output_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 46 \sr_op__output_cr$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__output_cr$15$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__output_cr$67 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \sr_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__rc__ok$59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 38 \sr_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__rc__ok$7$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \sr_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__rc__rc$58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 37 \sr_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__rc__rc$6$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \sr_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 41 \sr_op__write_cr0$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__write_cr0$10$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__write_cr0$62 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 input 28 \xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 output 54 \xer_ca$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \xer_ca$23$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \xer_ca$75 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire input 29 \xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 55 \xer_ca_ok$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_ca_ok$24$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_ca_ok$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_ca_ok$76 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire input 26 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire input 27 \xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \xer_so_ok$48 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" + cell $and $and$libresoc.v:172854$9551 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i$50 + connect \B \p_ready_o + connect \Y $and$libresoc.v:172854$9551_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:172905.11-172908.4" + cell \n$117 \n + connect \n_ready_i \n_ready_i + connect \n_valid_o \n_valid_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:172909.16-172957.4" + cell \output$118 \output + connect \cr_a \output_cr_a + connect \cr_a$21 \output_cr_a$45 + connect \cr_a_ok \output_cr_a_ok + connect \muxid \output_muxid + connect \muxid$1 \output_muxid$25 + connect \o \output_o + connect \o$19 \output_o$43 + connect \o_ok \output_o_ok + connect \o_ok$20 \output_o_ok$44 + connect \sr_op__fn_unit \output_sr_op__fn_unit + connect \sr_op__fn_unit$3 \output_sr_op__fn_unit$27 + connect \sr_op__imm_data__data \output_sr_op__imm_data__data + connect \sr_op__imm_data__data$4 \output_sr_op__imm_data__data$28 + connect \sr_op__imm_data__ok \output_sr_op__imm_data__ok + connect \sr_op__imm_data__ok$5 \output_sr_op__imm_data__ok$29 + connect \sr_op__input_carry \output_sr_op__input_carry + connect \sr_op__input_carry$12 \output_sr_op__input_carry$36 + connect \sr_op__input_cr \output_sr_op__input_cr + connect \sr_op__input_cr$14 \output_sr_op__input_cr$38 + connect \sr_op__insn \output_sr_op__insn + connect \sr_op__insn$18 \output_sr_op__insn$42 + connect \sr_op__insn_type \output_sr_op__insn_type + connect \sr_op__insn_type$2 \output_sr_op__insn_type$26 + connect \sr_op__invert_in \output_sr_op__invert_in + connect \sr_op__invert_in$11 \output_sr_op__invert_in$35 + connect \sr_op__is_32bit \output_sr_op__is_32bit + connect \sr_op__is_32bit$16 \output_sr_op__is_32bit$40 + connect \sr_op__is_signed \output_sr_op__is_signed + connect \sr_op__is_signed$17 \output_sr_op__is_signed$41 + connect \sr_op__oe__oe \output_sr_op__oe__oe + connect \sr_op__oe__oe$8 \output_sr_op__oe__oe$32 + connect \sr_op__oe__ok \output_sr_op__oe__ok + connect \sr_op__oe__ok$9 \output_sr_op__oe__ok$33 + connect \sr_op__output_carry \output_sr_op__output_carry + connect \sr_op__output_carry$13 \output_sr_op__output_carry$37 + connect \sr_op__output_cr \output_sr_op__output_cr + connect \sr_op__output_cr$15 \output_sr_op__output_cr$39 + connect \sr_op__rc__ok \output_sr_op__rc__ok + connect \sr_op__rc__ok$7 \output_sr_op__rc__ok$31 + connect \sr_op__rc__rc \output_sr_op__rc__rc + connect \sr_op__rc__rc$6 \output_sr_op__rc__rc$30 + connect \sr_op__write_cr0 \output_sr_op__write_cr0 + connect \sr_op__write_cr0$10 \output_sr_op__write_cr0$34 + connect \xer_ca \output_xer_ca + connect \xer_ca$22 \output_xer_ca$46 + connect \xer_ca_ok \output_xer_ca_ok + connect \xer_so \output_xer_so + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:172958.11-172961.4" + cell \p$116 \p + connect \p_ready_o \p_ready_o + connect \p_valid_i \p_valid_i + end + attribute \src "libresoc.v:172049.7-172049.20" + process $proc$libresoc.v:172049$9667 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:172060.13-172060.29" + process $proc$libresoc.v:172060$9668 + assign { } { } + assign $0\cr_a$21[3:0]$9669 4'0000 + sync always + sync init + update \cr_a$21 $0\cr_a$21[3:0]$9669 + end + attribute \src "libresoc.v:172069.7-172069.26" + process $proc$libresoc.v:172069$9670 + assign { } { } + assign $0\cr_a_ok$22[0:0]$9671 1'0 + sync always + sync init + update \cr_a_ok$22 $0\cr_a_ok$22[0:0]$9671 + end + attribute \src "libresoc.v:172080.13-172080.29" + process $proc$libresoc.v:172080$9672 + assign { } { } + assign $0\muxid$1[1:0]$9673 2'00 + sync always + sync init + update \muxid$1 $0\muxid$1[1:0]$9673 + end + attribute \src "libresoc.v:172095.14-172095.43" + process $proc$libresoc.v:172095$9674 + assign { } { } + assign $0\o$19[63:0]$9675 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \o$19 $0\o$19[63:0]$9675 + end + attribute \src "libresoc.v:172104.7-172104.23" + process $proc$libresoc.v:172104$9676 + assign { } { } + assign $0\o_ok$20[0:0]$9677 1'0 + sync always + sync init + update \o_ok$20 $0\o_ok$20[0:0]$9677 + end + attribute \src "libresoc.v:172396.7-172396.20" + process $proc$libresoc.v:172396$9678 + assign { } { } + assign $1\r_busy[0:0] 1'0 + sync always + sync init + update \r_busy $1\r_busy[0:0] + end + attribute \src "libresoc.v:172431.14-172431.43" + process $proc$libresoc.v:172431$9679 + assign { } { } + assign $0\sr_op__fn_unit$3[12:0]$9680 13'0000000000000 + sync always + sync init + update \sr_op__fn_unit$3 $0\sr_op__fn_unit$3[12:0]$9680 + end + attribute \src "libresoc.v:172454.14-172454.62" + process $proc$libresoc.v:172454$9681 + assign { } { } + assign $0\sr_op__imm_data__data$4[63:0]$9682 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \sr_op__imm_data__data$4 $0\sr_op__imm_data__data$4[63:0]$9682 + end + attribute \src "libresoc.v:172463.7-172463.37" + process $proc$libresoc.v:172463$9683 + assign { } { } + assign $0\sr_op__imm_data__ok$5[0:0]$9684 1'0 + sync always + sync init + update \sr_op__imm_data__ok$5 $0\sr_op__imm_data__ok$5[0:0]$9684 + end + attribute \src "libresoc.v:172480.13-172480.43" + process $proc$libresoc.v:172480$9685 + assign { } { } + assign $0\sr_op__input_carry$12[1:0]$9686 2'00 + sync always + sync init + update \sr_op__input_carry$12 $0\sr_op__input_carry$12[1:0]$9686 + end + attribute \src "libresoc.v:172493.7-172493.34" + process $proc$libresoc.v:172493$9687 + assign { } { } + assign $0\sr_op__input_cr$14[0:0]$9688 1'0 + sync always + sync init + update \sr_op__input_cr$14 $0\sr_op__input_cr$14[0:0]$9688 + end + attribute \src "libresoc.v:172502.14-172502.38" + process $proc$libresoc.v:172502$9689 + assign { } { } + assign $0\sr_op__insn$18[31:0]$9690 0 + sync always + sync init + update \sr_op__insn$18 $0\sr_op__insn$18[31:0]$9690 + end + attribute \src "libresoc.v:172659.13-172659.41" + process $proc$libresoc.v:172659$9691 + assign { } { } + assign $0\sr_op__insn_type$2[6:0]$9692 7'0000000 + sync always + sync init + update \sr_op__insn_type$2 $0\sr_op__insn_type$2[6:0]$9692 + end + attribute \src "libresoc.v:172742.7-172742.35" + process $proc$libresoc.v:172742$9693 + assign { } { } + assign $0\sr_op__invert_in$11[0:0]$9694 1'0 + sync always + sync init + update \sr_op__invert_in$11 $0\sr_op__invert_in$11[0:0]$9694 + end + attribute \src "libresoc.v:172751.7-172751.34" + process $proc$libresoc.v:172751$9695 + assign { } { } + assign $0\sr_op__is_32bit$16[0:0]$9696 1'0 + sync always + sync init + update \sr_op__is_32bit$16 $0\sr_op__is_32bit$16[0:0]$9696 + end + attribute \src "libresoc.v:172760.7-172760.35" + process $proc$libresoc.v:172760$9697 + assign { } { } + assign $0\sr_op__is_signed$17[0:0]$9698 1'0 + sync always + sync init + update \sr_op__is_signed$17 $0\sr_op__is_signed$17[0:0]$9698 + end + attribute \src "libresoc.v:172771.7-172771.31" + process $proc$libresoc.v:172771$9699 + assign { } { } + assign $0\sr_op__oe__oe$8[0:0]$9700 1'0 + sync always + sync init + update \sr_op__oe__oe$8 $0\sr_op__oe__oe$8[0:0]$9700 + end + attribute \src "libresoc.v:172780.7-172780.31" + process $proc$libresoc.v:172780$9701 + assign { } { } + assign $0\sr_op__oe__ok$9[0:0]$9702 1'0 + sync always + sync init + update \sr_op__oe__ok$9 $0\sr_op__oe__ok$9[0:0]$9702 + end + attribute \src "libresoc.v:172787.7-172787.38" + process $proc$libresoc.v:172787$9703 + assign { } { } + assign $0\sr_op__output_carry$13[0:0]$9704 1'0 + sync always + sync init + update \sr_op__output_carry$13 $0\sr_op__output_carry$13[0:0]$9704 + end + attribute \src "libresoc.v:172796.7-172796.35" + process $proc$libresoc.v:172796$9705 + assign { } { } + assign $0\sr_op__output_cr$15[0:0]$9706 1'0 + sync always + sync init + update \sr_op__output_cr$15 $0\sr_op__output_cr$15[0:0]$9706 + end + attribute \src "libresoc.v:172807.7-172807.31" + process $proc$libresoc.v:172807$9707 + assign { } { } + assign $0\sr_op__rc__ok$7[0:0]$9708 1'0 + sync always + sync init + update \sr_op__rc__ok$7 $0\sr_op__rc__ok$7[0:0]$9708 + end + attribute \src "libresoc.v:172816.7-172816.31" + process $proc$libresoc.v:172816$9709 + assign { } { } + assign $0\sr_op__rc__rc$6[0:0]$9710 1'0 + sync always + sync init + update \sr_op__rc__rc$6 $0\sr_op__rc__rc$6[0:0]$9710 + end + attribute \src "libresoc.v:172823.7-172823.35" + process $proc$libresoc.v:172823$9711 + assign { } { } + assign $0\sr_op__write_cr0$10[0:0]$9712 1'0 + sync always + sync init + update \sr_op__write_cr0$10 $0\sr_op__write_cr0$10[0:0]$9712 + end + attribute \src "libresoc.v:172832.13-172832.31" + process $proc$libresoc.v:172832$9713 + assign { } { } + assign $0\xer_ca$23[1:0]$9714 2'00 + sync always + sync init + update \xer_ca$23 $0\xer_ca$23[1:0]$9714 + end + attribute \src "libresoc.v:172841.7-172841.28" + process $proc$libresoc.v:172841$9715 + assign { } { } + assign $0\xer_ca_ok$24[0:0]$9716 1'0 + sync always + sync init + update \xer_ca_ok$24 $0\xer_ca_ok$24[0:0]$9716 + end + attribute \src "libresoc.v:172855.3-172856.37" + process $proc$libresoc.v:172855$9552 + assign { } { } + assign $0\xer_ca$23[1:0]$9553 \xer_ca$23$next + sync posedge \coresync_clk + update \xer_ca$23 $0\xer_ca$23[1:0]$9553 + end + attribute \src "libresoc.v:172857.3-172858.43" + process $proc$libresoc.v:172857$9554 + assign { } { } + assign $0\xer_ca_ok$24[0:0]$9555 \xer_ca_ok$24$next + sync posedge \coresync_clk + update \xer_ca_ok$24 $0\xer_ca_ok$24[0:0]$9555 + end + attribute \src "libresoc.v:172859.3-172860.33" + process $proc$libresoc.v:172859$9556 + assign { } { } + assign $0\cr_a$21[3:0]$9557 \cr_a$21$next + sync posedge \coresync_clk + update \cr_a$21 $0\cr_a$21[3:0]$9557 + end + attribute \src "libresoc.v:172861.3-172862.39" + process $proc$libresoc.v:172861$9558 + assign { } { } + assign $0\cr_a_ok$22[0:0]$9559 \cr_a_ok$22$next + sync posedge \coresync_clk + update \cr_a_ok$22 $0\cr_a_ok$22[0:0]$9559 + end + attribute \src "libresoc.v:172863.3-172864.27" + process $proc$libresoc.v:172863$9560 + assign { } { } + assign $0\o$19[63:0]$9561 \o$19$next + sync posedge \coresync_clk + update \o$19 $0\o$19[63:0]$9561 + end + attribute \src "libresoc.v:172865.3-172866.33" + process $proc$libresoc.v:172865$9562 + assign { } { } + assign $0\o_ok$20[0:0]$9563 \o_ok$20$next + sync posedge \coresync_clk + update \o_ok$20 $0\o_ok$20[0:0]$9563 + end + attribute \src "libresoc.v:172867.3-172868.55" + process $proc$libresoc.v:172867$9564 + assign { } { } + assign $0\sr_op__insn_type$2[6:0]$9565 \sr_op__insn_type$2$next + sync posedge \coresync_clk + update \sr_op__insn_type$2 $0\sr_op__insn_type$2[6:0]$9565 + end + attribute \src "libresoc.v:172869.3-172870.51" + process $proc$libresoc.v:172869$9566 + assign { } { } + assign $0\sr_op__fn_unit$3[12:0]$9567 \sr_op__fn_unit$3$next + sync posedge \coresync_clk + update \sr_op__fn_unit$3 $0\sr_op__fn_unit$3[12:0]$9567 + end + attribute \src "libresoc.v:172871.3-172872.65" + process $proc$libresoc.v:172871$9568 + assign { } { } + assign $0\sr_op__imm_data__data$4[63:0]$9569 \sr_op__imm_data__data$4$next + sync posedge \coresync_clk + update \sr_op__imm_data__data$4 $0\sr_op__imm_data__data$4[63:0]$9569 + end + attribute \src "libresoc.v:172873.3-172874.61" + process $proc$libresoc.v:172873$9570 + assign { } { } + assign $0\sr_op__imm_data__ok$5[0:0]$9571 \sr_op__imm_data__ok$5$next + sync posedge \coresync_clk + update \sr_op__imm_data__ok$5 $0\sr_op__imm_data__ok$5[0:0]$9571 + end + attribute \src "libresoc.v:172875.3-172876.49" + process $proc$libresoc.v:172875$9572 + assign { } { } + assign $0\sr_op__rc__rc$6[0:0]$9573 \sr_op__rc__rc$6$next + sync posedge \coresync_clk + update \sr_op__rc__rc$6 $0\sr_op__rc__rc$6[0:0]$9573 + end + attribute \src "libresoc.v:172877.3-172878.49" + process $proc$libresoc.v:172877$9574 + assign { } { } + assign $0\sr_op__rc__ok$7[0:0]$9575 \sr_op__rc__ok$7$next + sync posedge \coresync_clk + update \sr_op__rc__ok$7 $0\sr_op__rc__ok$7[0:0]$9575 + end + attribute \src "libresoc.v:172879.3-172880.49" + process $proc$libresoc.v:172879$9576 + assign { } { } + assign $0\sr_op__oe__oe$8[0:0]$9577 \sr_op__oe__oe$8$next + sync posedge \coresync_clk + update \sr_op__oe__oe$8 $0\sr_op__oe__oe$8[0:0]$9577 + end + attribute \src "libresoc.v:172881.3-172882.49" + process $proc$libresoc.v:172881$9578 + assign { } { } + assign $0\sr_op__oe__ok$9[0:0]$9579 \sr_op__oe__ok$9$next + sync posedge \coresync_clk + update \sr_op__oe__ok$9 $0\sr_op__oe__ok$9[0:0]$9579 + end + attribute \src "libresoc.v:172883.3-172884.57" + process $proc$libresoc.v:172883$9580 + assign { } { } + assign $0\sr_op__write_cr0$10[0:0]$9581 \sr_op__write_cr0$10$next + sync posedge \coresync_clk + update \sr_op__write_cr0$10 $0\sr_op__write_cr0$10[0:0]$9581 + end + attribute \src "libresoc.v:172885.3-172886.57" + process $proc$libresoc.v:172885$9582 + assign { } { } + assign $0\sr_op__invert_in$11[0:0]$9583 \sr_op__invert_in$11$next + sync posedge \coresync_clk + update \sr_op__invert_in$11 $0\sr_op__invert_in$11[0:0]$9583 + end + attribute \src "libresoc.v:172887.3-172888.61" + process $proc$libresoc.v:172887$9584 + assign { } { } + assign $0\sr_op__input_carry$12[1:0]$9585 \sr_op__input_carry$12$next + sync posedge \coresync_clk + update \sr_op__input_carry$12 $0\sr_op__input_carry$12[1:0]$9585 + end + attribute \src "libresoc.v:172889.3-172890.63" + process $proc$libresoc.v:172889$9586 + assign { } { } + assign $0\sr_op__output_carry$13[0:0]$9587 \sr_op__output_carry$13$next + sync posedge \coresync_clk + update \sr_op__output_carry$13 $0\sr_op__output_carry$13[0:0]$9587 + end + attribute \src "libresoc.v:172891.3-172892.55" + process $proc$libresoc.v:172891$9588 + assign { } { } + assign $0\sr_op__input_cr$14[0:0]$9589 \sr_op__input_cr$14$next + sync posedge \coresync_clk + update \sr_op__input_cr$14 $0\sr_op__input_cr$14[0:0]$9589 + end + attribute \src "libresoc.v:172893.3-172894.57" + process $proc$libresoc.v:172893$9590 + assign { } { } + assign $0\sr_op__output_cr$15[0:0]$9591 \sr_op__output_cr$15$next + sync posedge \coresync_clk + update \sr_op__output_cr$15 $0\sr_op__output_cr$15[0:0]$9591 + end + attribute \src "libresoc.v:172895.3-172896.55" + process $proc$libresoc.v:172895$9592 + assign { } { } + assign $0\sr_op__is_32bit$16[0:0]$9593 \sr_op__is_32bit$16$next + sync posedge \coresync_clk + update \sr_op__is_32bit$16 $0\sr_op__is_32bit$16[0:0]$9593 + end + attribute \src "libresoc.v:172897.3-172898.57" + process $proc$libresoc.v:172897$9594 + assign { } { } + assign $0\sr_op__is_signed$17[0:0]$9595 \sr_op__is_signed$17$next + sync posedge \coresync_clk + update \sr_op__is_signed$17 $0\sr_op__is_signed$17[0:0]$9595 + end + attribute \src "libresoc.v:172899.3-172900.47" + process $proc$libresoc.v:172899$9596 + assign { } { } + assign $0\sr_op__insn$18[31:0]$9597 \sr_op__insn$18$next + sync posedge \coresync_clk + update \sr_op__insn$18 $0\sr_op__insn$18[31:0]$9597 + end + attribute \src "libresoc.v:172901.3-172902.33" + process $proc$libresoc.v:172901$9598 + assign { } { } + assign $0\muxid$1[1:0]$9599 \muxid$1$next + sync posedge \coresync_clk + update \muxid$1 $0\muxid$1[1:0]$9599 + end + attribute \src "libresoc.v:172903.3-172904.29" + process $proc$libresoc.v:172903$9600 + assign { } { } + assign $0\r_busy[0:0] \r_busy$next + sync posedge \coresync_clk + update \r_busy $0\r_busy[0:0] + end + attribute \src "libresoc.v:172962.3-172979.6" + process $proc$libresoc.v:172962$9601 + assign { } { } + assign { } { } + assign { } { } + assign $0\r_busy$next[0:0]$9602 $2\r_busy$next[0:0]$9604 + attribute \src "libresoc.v:172963.5-172963.29" + switch \initial + attribute \src "libresoc.v:172963.9-172963.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\r_busy$next[0:0]$9603 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\r_busy$next[0:0]$9603 1'0 + case + assign $1\r_busy$next[0:0]$9603 \r_busy + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r_busy$next[0:0]$9604 1'0 + case + assign $2\r_busy$next[0:0]$9604 $1\r_busy$next[0:0]$9603 + end + sync always + update \r_busy$next $0\r_busy$next[0:0]$9602 + end + attribute \src "libresoc.v:172980.3-172992.6" + process $proc$libresoc.v:172980$9605 + assign { } { } + assign { } { } + assign $0\muxid$1$next[1:0]$9606 $1\muxid$1$next[1:0]$9607 + attribute \src "libresoc.v:172981.5-172981.29" + switch \initial + attribute \src "libresoc.v:172981.9-172981.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\muxid$1$next[1:0]$9607 \muxid$53 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\muxid$1$next[1:0]$9607 \muxid$53 + case + assign $1\muxid$1$next[1:0]$9607 \muxid$1 + end + sync always + update \muxid$1$next $0\muxid$1$next[1:0]$9606 + end + attribute \src "libresoc.v:172993.3-173033.6" + process $proc$libresoc.v:172993$9608 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\sr_op__fn_unit$3$next[12:0]$9609 $1\sr_op__fn_unit$3$next[12:0]$9626 + assign { } { } + assign { } { } + assign $0\sr_op__input_carry$12$next[1:0]$9612 $1\sr_op__input_carry$12$next[1:0]$9629 + assign $0\sr_op__input_cr$14$next[0:0]$9613 $1\sr_op__input_cr$14$next[0:0]$9630 + assign $0\sr_op__insn$18$next[31:0]$9614 $1\sr_op__insn$18$next[31:0]$9631 + assign $0\sr_op__insn_type$2$next[6:0]$9615 $1\sr_op__insn_type$2$next[6:0]$9632 + assign $0\sr_op__invert_in$11$next[0:0]$9616 $1\sr_op__invert_in$11$next[0:0]$9633 + assign $0\sr_op__is_32bit$16$next[0:0]$9617 $1\sr_op__is_32bit$16$next[0:0]$9634 + assign $0\sr_op__is_signed$17$next[0:0]$9618 $1\sr_op__is_signed$17$next[0:0]$9635 + assign { } { } + assign { } { } + assign $0\sr_op__output_carry$13$next[0:0]$9621 $1\sr_op__output_carry$13$next[0:0]$9638 + assign $0\sr_op__output_cr$15$next[0:0]$9622 $1\sr_op__output_cr$15$next[0:0]$9639 + assign { } { } + assign { } { } + assign $0\sr_op__write_cr0$10$next[0:0]$9625 $1\sr_op__write_cr0$10$next[0:0]$9642 + assign $0\sr_op__imm_data__data$4$next[63:0]$9610 $2\sr_op__imm_data__data$4$next[63:0]$9643 + assign $0\sr_op__imm_data__ok$5$next[0:0]$9611 $2\sr_op__imm_data__ok$5$next[0:0]$9644 + assign $0\sr_op__oe__oe$8$next[0:0]$9619 $2\sr_op__oe__oe$8$next[0:0]$9645 + assign $0\sr_op__oe__ok$9$next[0:0]$9620 $2\sr_op__oe__ok$9$next[0:0]$9646 + assign $0\sr_op__rc__ok$7$next[0:0]$9623 $2\sr_op__rc__ok$7$next[0:0]$9647 + assign $0\sr_op__rc__rc$6$next[0:0]$9624 $2\sr_op__rc__rc$6$next[0:0]$9648 + attribute \src "libresoc.v:172994.5-172994.29" + switch \initial + attribute \src "libresoc.v:172994.9-172994.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\sr_op__insn$18$next[31:0]$9631 $1\sr_op__is_signed$17$next[0:0]$9635 $1\sr_op__is_32bit$16$next[0:0]$9634 $1\sr_op__output_cr$15$next[0:0]$9639 $1\sr_op__input_cr$14$next[0:0]$9630 $1\sr_op__output_carry$13$next[0:0]$9638 $1\sr_op__input_carry$12$next[1:0]$9629 $1\sr_op__invert_in$11$next[0:0]$9633 $1\sr_op__write_cr0$10$next[0:0]$9642 $1\sr_op__oe__ok$9$next[0:0]$9637 $1\sr_op__oe__oe$8$next[0:0]$9636 $1\sr_op__rc__ok$7$next[0:0]$9640 $1\sr_op__rc__rc$6$next[0:0]$9641 $1\sr_op__imm_data__ok$5$next[0:0]$9628 $1\sr_op__imm_data__data$4$next[63:0]$9627 $1\sr_op__fn_unit$3$next[12:0]$9626 $1\sr_op__insn_type$2$next[6:0]$9632 } { \sr_op__insn$70 \sr_op__is_signed$69 \sr_op__is_32bit$68 \sr_op__output_cr$67 \sr_op__input_cr$66 \sr_op__output_carry$65 \sr_op__input_carry$64 \sr_op__invert_in$63 \sr_op__write_cr0$62 \sr_op__oe__ok$61 \sr_op__oe__oe$60 \sr_op__rc__ok$59 \sr_op__rc__rc$58 \sr_op__imm_data__ok$57 \sr_op__imm_data__data$56 \sr_op__fn_unit$55 \sr_op__insn_type$54 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\sr_op__insn$18$next[31:0]$9631 $1\sr_op__is_signed$17$next[0:0]$9635 $1\sr_op__is_32bit$16$next[0:0]$9634 $1\sr_op__output_cr$15$next[0:0]$9639 $1\sr_op__input_cr$14$next[0:0]$9630 $1\sr_op__output_carry$13$next[0:0]$9638 $1\sr_op__input_carry$12$next[1:0]$9629 $1\sr_op__invert_in$11$next[0:0]$9633 $1\sr_op__write_cr0$10$next[0:0]$9642 $1\sr_op__oe__ok$9$next[0:0]$9637 $1\sr_op__oe__oe$8$next[0:0]$9636 $1\sr_op__rc__ok$7$next[0:0]$9640 $1\sr_op__rc__rc$6$next[0:0]$9641 $1\sr_op__imm_data__ok$5$next[0:0]$9628 $1\sr_op__imm_data__data$4$next[63:0]$9627 $1\sr_op__fn_unit$3$next[12:0]$9626 $1\sr_op__insn_type$2$next[6:0]$9632 } { \sr_op__insn$70 \sr_op__is_signed$69 \sr_op__is_32bit$68 \sr_op__output_cr$67 \sr_op__input_cr$66 \sr_op__output_carry$65 \sr_op__input_carry$64 \sr_op__invert_in$63 \sr_op__write_cr0$62 \sr_op__oe__ok$61 \sr_op__oe__oe$60 \sr_op__rc__ok$59 \sr_op__rc__rc$58 \sr_op__imm_data__ok$57 \sr_op__imm_data__data$56 \sr_op__fn_unit$55 \sr_op__insn_type$54 } + case + assign $1\sr_op__fn_unit$3$next[12:0]$9626 \sr_op__fn_unit$3 + assign $1\sr_op__imm_data__data$4$next[63:0]$9627 \sr_op__imm_data__data$4 + assign $1\sr_op__imm_data__ok$5$next[0:0]$9628 \sr_op__imm_data__ok$5 + assign $1\sr_op__input_carry$12$next[1:0]$9629 \sr_op__input_carry$12 + assign $1\sr_op__input_cr$14$next[0:0]$9630 \sr_op__input_cr$14 + assign $1\sr_op__insn$18$next[31:0]$9631 \sr_op__insn$18 + assign $1\sr_op__insn_type$2$next[6:0]$9632 \sr_op__insn_type$2 + assign $1\sr_op__invert_in$11$next[0:0]$9633 \sr_op__invert_in$11 + assign $1\sr_op__is_32bit$16$next[0:0]$9634 \sr_op__is_32bit$16 + assign $1\sr_op__is_signed$17$next[0:0]$9635 \sr_op__is_signed$17 + assign $1\sr_op__oe__oe$8$next[0:0]$9636 \sr_op__oe__oe$8 + assign $1\sr_op__oe__ok$9$next[0:0]$9637 \sr_op__oe__ok$9 + assign $1\sr_op__output_carry$13$next[0:0]$9638 \sr_op__output_carry$13 + assign $1\sr_op__output_cr$15$next[0:0]$9639 \sr_op__output_cr$15 + assign $1\sr_op__rc__ok$7$next[0:0]$9640 \sr_op__rc__ok$7 + assign $1\sr_op__rc__rc$6$next[0:0]$9641 \sr_op__rc__rc$6 + assign $1\sr_op__write_cr0$10$next[0:0]$9642 \sr_op__write_cr0$10 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $2\sr_op__imm_data__data$4$next[63:0]$9643 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\sr_op__imm_data__ok$5$next[0:0]$9644 1'0 + assign $2\sr_op__rc__rc$6$next[0:0]$9648 1'0 + assign $2\sr_op__rc__ok$7$next[0:0]$9647 1'0 + assign $2\sr_op__oe__oe$8$next[0:0]$9645 1'0 + assign $2\sr_op__oe__ok$9$next[0:0]$9646 1'0 + case + assign $2\sr_op__imm_data__data$4$next[63:0]$9643 $1\sr_op__imm_data__data$4$next[63:0]$9627 + assign $2\sr_op__imm_data__ok$5$next[0:0]$9644 $1\sr_op__imm_data__ok$5$next[0:0]$9628 + assign $2\sr_op__oe__oe$8$next[0:0]$9645 $1\sr_op__oe__oe$8$next[0:0]$9636 + assign $2\sr_op__oe__ok$9$next[0:0]$9646 $1\sr_op__oe__ok$9$next[0:0]$9637 + assign $2\sr_op__rc__ok$7$next[0:0]$9647 $1\sr_op__rc__ok$7$next[0:0]$9640 + assign $2\sr_op__rc__rc$6$next[0:0]$9648 $1\sr_op__rc__rc$6$next[0:0]$9641 + end + sync always + update \sr_op__fn_unit$3$next $0\sr_op__fn_unit$3$next[12:0]$9609 + update \sr_op__imm_data__data$4$next $0\sr_op__imm_data__data$4$next[63:0]$9610 + update \sr_op__imm_data__ok$5$next $0\sr_op__imm_data__ok$5$next[0:0]$9611 + update \sr_op__input_carry$12$next $0\sr_op__input_carry$12$next[1:0]$9612 + update \sr_op__input_cr$14$next $0\sr_op__input_cr$14$next[0:0]$9613 + update \sr_op__insn$18$next $0\sr_op__insn$18$next[31:0]$9614 + update \sr_op__insn_type$2$next $0\sr_op__insn_type$2$next[6:0]$9615 + update \sr_op__invert_in$11$next $0\sr_op__invert_in$11$next[0:0]$9616 + update \sr_op__is_32bit$16$next $0\sr_op__is_32bit$16$next[0:0]$9617 + update \sr_op__is_signed$17$next $0\sr_op__is_signed$17$next[0:0]$9618 + update \sr_op__oe__oe$8$next $0\sr_op__oe__oe$8$next[0:0]$9619 + update \sr_op__oe__ok$9$next $0\sr_op__oe__ok$9$next[0:0]$9620 + update \sr_op__output_carry$13$next $0\sr_op__output_carry$13$next[0:0]$9621 + update \sr_op__output_cr$15$next $0\sr_op__output_cr$15$next[0:0]$9622 + update \sr_op__rc__ok$7$next $0\sr_op__rc__ok$7$next[0:0]$9623 + update \sr_op__rc__rc$6$next $0\sr_op__rc__rc$6$next[0:0]$9624 + update \sr_op__write_cr0$10$next $0\sr_op__write_cr0$10$next[0:0]$9625 + end + attribute \src "libresoc.v:173034.3-173052.6" + process $proc$libresoc.v:173034$9649 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\o$19$next[63:0]$9650 $1\o$19$next[63:0]$9652 + assign { } { } + assign $0\o_ok$20$next[0:0]$9651 $2\o_ok$20$next[0:0]$9654 + attribute \src "libresoc.v:173035.5-173035.29" + switch \initial + attribute \src "libresoc.v:173035.9-173035.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\o_ok$20$next[0:0]$9653 $1\o$19$next[63:0]$9652 } { \o_ok$72 \o$71 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\o_ok$20$next[0:0]$9653 $1\o$19$next[63:0]$9652 } { \o_ok$72 \o$71 } + case + assign $1\o$19$next[63:0]$9652 \o$19 + assign $1\o_ok$20$next[0:0]$9653 \o_ok$20 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\o_ok$20$next[0:0]$9654 1'0 + case + assign $2\o_ok$20$next[0:0]$9654 $1\o_ok$20$next[0:0]$9653 + end + sync always + update \o$19$next $0\o$19$next[63:0]$9650 + update \o_ok$20$next $0\o_ok$20$next[0:0]$9651 + end + attribute \src "libresoc.v:173053.3-173071.6" + process $proc$libresoc.v:173053$9655 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\cr_a$21$next[3:0]$9656 $1\cr_a$21$next[3:0]$9658 + assign { } { } + assign $0\cr_a_ok$22$next[0:0]$9657 $2\cr_a_ok$22$next[0:0]$9660 + attribute \src "libresoc.v:173054.5-173054.29" + switch \initial + attribute \src "libresoc.v:173054.9-173054.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\cr_a_ok$22$next[0:0]$9659 $1\cr_a$21$next[3:0]$9658 } { \cr_a_ok$74 \cr_a$73 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\cr_a_ok$22$next[0:0]$9659 $1\cr_a$21$next[3:0]$9658 } { \cr_a_ok$74 \cr_a$73 } + case + assign $1\cr_a$21$next[3:0]$9658 \cr_a$21 + assign $1\cr_a_ok$22$next[0:0]$9659 \cr_a_ok$22 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_a_ok$22$next[0:0]$9660 1'0 + case + assign $2\cr_a_ok$22$next[0:0]$9660 $1\cr_a_ok$22$next[0:0]$9659 + end + sync always + update \cr_a$21$next $0\cr_a$21$next[3:0]$9656 + update \cr_a_ok$22$next $0\cr_a_ok$22$next[0:0]$9657 + end + attribute \src "libresoc.v:173072.3-173090.6" + process $proc$libresoc.v:173072$9661 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\xer_ca$23$next[1:0]$9662 $1\xer_ca$23$next[1:0]$9664 + assign { } { } + assign $0\xer_ca_ok$24$next[0:0]$9663 $2\xer_ca_ok$24$next[0:0]$9666 + attribute \src "libresoc.v:173073.5-173073.29" + switch \initial + attribute \src "libresoc.v:173073.9-173073.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\xer_ca_ok$24$next[0:0]$9665 $1\xer_ca$23$next[1:0]$9664 } { \xer_ca_ok$76 \xer_ca$75 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\xer_ca_ok$24$next[0:0]$9665 $1\xer_ca$23$next[1:0]$9664 } { \xer_ca_ok$76 \xer_ca$75 } + case + assign $1\xer_ca$23$next[1:0]$9664 \xer_ca$23 + assign $1\xer_ca_ok$24$next[0:0]$9665 \xer_ca_ok$24 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\xer_ca_ok$24$next[0:0]$9666 1'0 + case + assign $2\xer_ca_ok$24$next[0:0]$9666 $1\xer_ca_ok$24$next[0:0]$9665 + end + sync always + update \xer_ca$23$next $0\xer_ca$23$next[1:0]$9662 + update \xer_ca_ok$24$next $0\xer_ca_ok$24$next[0:0]$9663 + end + connect \$51 $and$libresoc.v:172854$9551_Y + connect \p_ready_o \n_i_rdy_data + connect \n_valid_o \r_busy + connect { \xer_ca_ok$76 \xer_ca$75 } { \output_xer_ca_ok \output_xer_ca$46 } + connect { \cr_a_ok$74 \cr_a$73 } { \output_cr_a_ok \output_cr_a$45 } + connect { \o_ok$72 \o$71 } { \output_o_ok$44 \output_o$43 } + connect { \sr_op__insn$70 \sr_op__is_signed$69 \sr_op__is_32bit$68 \sr_op__output_cr$67 \sr_op__input_cr$66 \sr_op__output_carry$65 \sr_op__input_carry$64 \sr_op__invert_in$63 \sr_op__write_cr0$62 \sr_op__oe__ok$61 \sr_op__oe__oe$60 \sr_op__rc__ok$59 \sr_op__rc__rc$58 \sr_op__imm_data__ok$57 \sr_op__imm_data__data$56 \sr_op__fn_unit$55 \sr_op__insn_type$54 } { \output_sr_op__insn$42 \output_sr_op__is_signed$41 \output_sr_op__is_32bit$40 \output_sr_op__output_cr$39 \output_sr_op__input_cr$38 \output_sr_op__output_carry$37 \output_sr_op__input_carry$36 \output_sr_op__invert_in$35 \output_sr_op__write_cr0$34 \output_sr_op__oe__ok$33 \output_sr_op__oe__oe$32 \output_sr_op__rc__ok$31 \output_sr_op__rc__rc$30 \output_sr_op__imm_data__ok$29 \output_sr_op__imm_data__data$28 \output_sr_op__fn_unit$27 \output_sr_op__insn_type$26 } + connect \muxid$53 \output_muxid$25 + connect \p_valid_i_p_ready_o \$51 + connect \n_i_rdy_data \n_ready_i + connect \p_valid_i$50 \p_valid_i + connect { \xer_ca_ok$49 \output_xer_ca } { \xer_ca_ok \xer_ca } + connect { \xer_so_ok$48 \output_xer_so } { \xer_so_ok \xer_so } + connect { \cr_a_ok$47 \output_cr_a } { \cr_a_ok \cr_a } + connect { \output_o_ok \output_o } { \o_ok \o } + connect { \output_sr_op__insn \output_sr_op__is_signed \output_sr_op__is_32bit \output_sr_op__output_cr \output_sr_op__input_cr \output_sr_op__output_carry \output_sr_op__input_carry \output_sr_op__invert_in \output_sr_op__write_cr0 \output_sr_op__oe__ok \output_sr_op__oe__oe \output_sr_op__rc__ok \output_sr_op__rc__rc \output_sr_op__imm_data__ok \output_sr_op__imm_data__data \output_sr_op__fn_unit \output_sr_op__insn_type } { \sr_op__insn \sr_op__is_signed \sr_op__is_32bit \sr_op__output_cr \sr_op__input_cr \sr_op__output_carry \sr_op__input_carry \sr_op__invert_in \sr_op__write_cr0 \sr_op__oe__ok \sr_op__oe__oe \sr_op__rc__ok \sr_op__rc__rc \sr_op__imm_data__ok \sr_op__imm_data__data \sr_op__fn_unit \sr_op__insn_type } + connect \output_muxid \muxid +end +attribute \src "libresoc.v:173111.1-174065.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.pipe2" +attribute \generator "nMigen" +module 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$0\msr$next[63:0]$9802 + attribute \src "libresoc.v:173814.3-173815.23" + wire width 64 $0\msr[63:0] + attribute \src "libresoc.v:174028.3-174046.6" + wire $0\msr_ok$next[0:0]$9803 + attribute \src "libresoc.v:173816.3-173817.29" + wire $0\msr_ok[0:0] + attribute \src "libresoc.v:173918.3-173930.6" + wire width 2 $0\muxid$1$next[1:0]$9756 + attribute \src "libresoc.v:173852.3-173853.33" + wire width 2 $0\muxid$1[1:0]$9749 + attribute \src "libresoc.v:173413.13-173413.29" + wire width 2 $0\muxid$1[1:0]$9817 + attribute \src "libresoc.v:174009.3-174027.6" + wire width 64 $0\nia$next[63:0]$9796 + attribute \src "libresoc.v:173818.3-173819.23" + wire width 64 $0\nia[63:0] + attribute \src "libresoc.v:174009.3-174027.6" + wire $0\nia_ok$next[0:0]$9797 + attribute \src "libresoc.v:173820.3-173821.29" + wire $0\nia_ok[0:0] + attribute \src "libresoc.v:173952.3-173970.6" + wire width 64 $0\o$next[63:0]$9778 + attribute \src "libresoc.v:173830.3-173831.19" + wire width 64 $0\o[63:0] + attribute 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$1\fast1$11$next[63:0]$9787 + attribute \src "libresoc.v:173971.3-173989.6" + wire $1\fast1_ok$next[0:0]$9786 + attribute \src "libresoc.v:173130.7-173130.22" + wire $1\fast1_ok[0:0] + attribute \src "libresoc.v:173990.3-174008.6" + wire width 64 $1\fast2$12$next[63:0]$9793 + attribute \src "libresoc.v:173990.3-174008.6" + wire $1\fast2_ok$next[0:0]$9792 + attribute \src "libresoc.v:173146.7-173146.22" + wire $1\fast2_ok[0:0] + attribute \src "libresoc.v:174028.3-174046.6" + wire width 64 $1\msr$next[63:0]$9804 + attribute \src "libresoc.v:173397.14-173397.40" + wire width 64 $1\msr[63:0] + attribute \src "libresoc.v:174028.3-174046.6" + wire $1\msr_ok$next[0:0]$9805 + attribute \src "libresoc.v:173404.7-173404.20" + wire $1\msr_ok[0:0] + attribute \src "libresoc.v:173918.3-173930.6" + wire width 2 $1\muxid$1$next[1:0]$9757 + attribute \src "libresoc.v:174009.3-174027.6" + wire width 64 $1\nia$next[63:0]$9798 + attribute \src "libresoc.v:173426.14-173426.40" + wire width 64 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attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute 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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \main_trap_op__msr$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \main_trap_op__trapaddr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \main_trap_op__trapaddr$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 8 \main_trap_op__traptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 8 \main_trap_op__traptype$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 38 \msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \msr$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \msr$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 39 \msr_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \msr_ok$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \msr_ok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 input 4 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 output 20 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid$1$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + wire \n_i_rdy_data + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire input 19 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire output 18 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 36 \nia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \nia$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \nia$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 37 \nia_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \nia_ok$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \nia_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 30 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \o$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \o$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 31 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \o_ok$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \o_ok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" + wire output 3 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" + wire input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" + wire \p_valid_i$25 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" + wire \p_valid_i_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire \r_busy$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 14 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 15 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 9 \trap_op__cia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \trap_op__cia$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 25 \trap_op__cia$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \trap_op__cia$6$next + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute 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"SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 output 22 \trap_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \trap_op__fn_unit$3$next + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \trap_op__fn_unit$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 7 \trap_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \trap_op__insn$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 23 \trap_op__insn$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \trap_op__insn$4$next + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + 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\enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 21 \trap_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \trap_op__insn_type$2$next + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \trap_op__insn_type$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \trap_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \trap_op__is_32bit$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 26 \trap_op__is_32bit$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \trap_op__is_32bit$7$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 8 input 13 \trap_op__ldst_exc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 8 output 29 \trap_op__ldst_exc$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 8 \trap_op__ldst_exc$10$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 8 \trap_op__ldst_exc$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 8 \trap_op__msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \trap_op__msr$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 24 \trap_op__msr$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \trap_op__msr$5$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 input 12 \trap_op__trapaddr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \trap_op__trapaddr$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 output 28 \trap_op__trapaddr$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \trap_op__trapaddr$9$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 8 input 11 \trap_op__traptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 8 \trap_op__traptype$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 8 output 27 \trap_op__traptype$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 8 \trap_op__traptype$8$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" + cell $and $and$libresoc.v:173813$9717 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i$25 + connect \B \p_ready_o + connect \Y $and$libresoc.v:173813$9717_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:173856.13-173891.4" + cell \main$38 \main + connect \fast1 \main_fast1 + connect \fast1$11 \main_fast1$23 + connect \fast1_ok \main_fast1_ok + connect \fast2 \main_fast2 + connect \fast2$12 \main_fast2$24 + connect \fast2_ok \main_fast2_ok + connect \msr \main_msr + connect \msr_ok \main_msr_ok + connect \muxid \main_muxid + connect \muxid$1 \main_muxid$13 + connect \nia \main_nia + connect \nia_ok \main_nia_ok + connect \o \main_o + connect \o_ok \main_o_ok + connect \ra \main_ra + connect \rb \main_rb + connect \trap_op__cia \main_trap_op__cia + connect \trap_op__cia$6 \main_trap_op__cia$18 + connect \trap_op__fn_unit \main_trap_op__fn_unit + connect \trap_op__fn_unit$3 \main_trap_op__fn_unit$15 + connect \trap_op__insn \main_trap_op__insn + connect \trap_op__insn$4 \main_trap_op__insn$16 + connect \trap_op__insn_type \main_trap_op__insn_type + connect \trap_op__insn_type$2 \main_trap_op__insn_type$14 + connect \trap_op__is_32bit \main_trap_op__is_32bit + connect \trap_op__is_32bit$7 \main_trap_op__is_32bit$19 + connect \trap_op__ldst_exc \main_trap_op__ldst_exc + connect \trap_op__ldst_exc$10 \main_trap_op__ldst_exc$22 + connect \trap_op__msr \main_trap_op__msr + connect \trap_op__msr$5 \main_trap_op__msr$17 + connect \trap_op__trapaddr \main_trap_op__trapaddr + connect \trap_op__trapaddr$9 \main_trap_op__trapaddr$21 + connect \trap_op__traptype \main_trap_op__traptype + connect \trap_op__traptype$8 \main_trap_op__traptype$20 + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:173892.10-173895.4" + cell \n$37 \n + connect \n_ready_i \n_ready_i + connect \n_valid_o \n_valid_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:173896.10-173899.4" + cell \p$36 \p + connect \p_ready_o \p_ready_o + connect \p_valid_i \p_valid_i + end + attribute \src "libresoc.v:173112.7-173112.20" + process $proc$libresoc.v:173112$9807 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:173123.14-173123.47" + process $proc$libresoc.v:173123$9808 + assign { } { } + assign $0\fast1$11[63:0]$9809 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \fast1$11 $0\fast1$11[63:0]$9809 + end + attribute \src "libresoc.v:173130.7-173130.22" + process $proc$libresoc.v:173130$9810 + assign { } { } + assign $1\fast1_ok[0:0] 1'0 + sync always + sync init + update \fast1_ok $1\fast1_ok[0:0] + end + attribute \src "libresoc.v:173139.14-173139.47" + process $proc$libresoc.v:173139$9811 + assign { } { } + assign $0\fast2$12[63:0]$9812 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \fast2$12 $0\fast2$12[63:0]$9812 + end + attribute \src "libresoc.v:173146.7-173146.22" + process $proc$libresoc.v:173146$9813 + assign { } { } + assign $1\fast2_ok[0:0] 1'0 + sync always + sync init + update \fast2_ok $1\fast2_ok[0:0] + end + attribute \src "libresoc.v:173397.14-173397.40" + process $proc$libresoc.v:173397$9814 + assign { } { } + assign $1\msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \msr $1\msr[63:0] + end + attribute \src "libresoc.v:173404.7-173404.20" + process $proc$libresoc.v:173404$9815 + assign { } { } + assign $1\msr_ok[0:0] 1'0 + sync always + sync init + update \msr_ok $1\msr_ok[0:0] + end + attribute \src "libresoc.v:173413.13-173413.29" + process $proc$libresoc.v:173413$9816 + assign { } { } + assign $0\muxid$1[1:0]$9817 2'00 + sync always + sync init + update \muxid$1 $0\muxid$1[1:0]$9817 + end + attribute \src "libresoc.v:173426.14-173426.40" + process $proc$libresoc.v:173426$9818 + assign { } { } + assign $1\nia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \nia $1\nia[63:0] + end + attribute \src "libresoc.v:173433.7-173433.20" + process $proc$libresoc.v:173433$9819 + assign { } { } + assign $1\nia_ok[0:0] 1'0 + sync always + sync init + update \nia_ok $1\nia_ok[0:0] + end + attribute \src "libresoc.v:173440.14-173440.38" + process $proc$libresoc.v:173440$9820 + assign { } { } + assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \o $1\o[63:0] + end + attribute \src "libresoc.v:173447.7-173447.18" + process $proc$libresoc.v:173447$9821 + assign { } { } + assign $1\o_ok[0:0] 1'0 + sync always + sync init + update \o_ok $1\o_ok[0:0] + end + attribute \src "libresoc.v:173461.7-173461.20" + process $proc$libresoc.v:173461$9822 + assign { } { } + assign $1\r_busy[0:0] 1'0 + sync always + sync init + update \r_busy $1\r_busy[0:0] + end + attribute \src "libresoc.v:173474.14-173474.53" + process $proc$libresoc.v:173474$9823 + assign { } { } + assign $0\trap_op__cia$6[63:0]$9824 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \trap_op__cia$6 $0\trap_op__cia$6[63:0]$9824 + end + attribute \src "libresoc.v:173509.14-173509.45" + process $proc$libresoc.v:173509$9825 + assign { } { } + assign $0\trap_op__fn_unit$3[12:0]$9826 13'0000000000000 + sync always + sync init + update \trap_op__fn_unit$3 $0\trap_op__fn_unit$3[12:0]$9826 + end + attribute \src "libresoc.v:173534.14-173534.39" + process $proc$libresoc.v:173534$9827 + assign { } { } + assign $0\trap_op__insn$4[31:0]$9828 0 + sync always + sync init + update \trap_op__insn$4 $0\trap_op__insn$4[31:0]$9828 + end + attribute \src "libresoc.v:173689.13-173689.43" + process $proc$libresoc.v:173689$9829 + assign { } { } + assign $0\trap_op__insn_type$2[6:0]$9830 7'0000000 + sync always + sync init + update \trap_op__insn_type$2 $0\trap_op__insn_type$2[6:0]$9830 + end + attribute \src "libresoc.v:173774.7-173774.35" + process $proc$libresoc.v:173774$9831 + assign { } { } + assign $0\trap_op__is_32bit$7[0:0]$9832 1'0 + sync always + sync init + update \trap_op__is_32bit$7 $0\trap_op__is_32bit$7[0:0]$9832 + end + attribute \src "libresoc.v:173781.13-173781.43" + process $proc$libresoc.v:173781$9833 + assign { } { } + assign $0\trap_op__ldst_exc$10[7:0]$9834 8'00000000 + sync always + sync init + update \trap_op__ldst_exc$10 $0\trap_op__ldst_exc$10[7:0]$9834 + end + attribute \src "libresoc.v:173792.14-173792.53" + process $proc$libresoc.v:173792$9835 + assign { } { } + assign $0\trap_op__msr$5[63:0]$9836 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \trap_op__msr$5 $0\trap_op__msr$5[63:0]$9836 + end + attribute \src "libresoc.v:173801.14-173801.46" + process $proc$libresoc.v:173801$9837 + assign { } { } + assign $0\trap_op__trapaddr$9[12:0]$9838 13'0000000000000 + sync always + sync init + update \trap_op__trapaddr$9 $0\trap_op__trapaddr$9[12:0]$9838 + end + attribute \src "libresoc.v:173810.13-173810.42" + process $proc$libresoc.v:173810$9839 + assign { } { } + assign $0\trap_op__traptype$8[7:0]$9840 8'00000000 + sync always + sync init + update \trap_op__traptype$8 $0\trap_op__traptype$8[7:0]$9840 + end + attribute \src "libresoc.v:173814.3-173815.23" + process $proc$libresoc.v:173814$9718 + assign { } { } + assign $0\msr[63:0] \msr$next + sync posedge \coresync_clk + update \msr $0\msr[63:0] + end + attribute \src "libresoc.v:173816.3-173817.29" + process $proc$libresoc.v:173816$9719 + assign { } { } + assign $0\msr_ok[0:0] \msr_ok$next + sync posedge \coresync_clk + update \msr_ok $0\msr_ok[0:0] + end + attribute \src "libresoc.v:173818.3-173819.23" + process $proc$libresoc.v:173818$9720 + assign { } { } + assign $0\nia[63:0] \nia$next + sync posedge \coresync_clk + update \nia $0\nia[63:0] + end + attribute \src "libresoc.v:173820.3-173821.29" + process $proc$libresoc.v:173820$9721 + assign { } { } + assign $0\nia_ok[0:0] \nia_ok$next + sync posedge \coresync_clk + update \nia_ok $0\nia_ok[0:0] + end + attribute \src "libresoc.v:173822.3-173823.35" + process $proc$libresoc.v:173822$9722 + assign { } { } + assign $0\fast2$12[63:0]$9723 \fast2$12$next + sync posedge \coresync_clk + update \fast2$12 $0\fast2$12[63:0]$9723 + end + attribute \src "libresoc.v:173824.3-173825.33" + process $proc$libresoc.v:173824$9724 + assign { } { } + assign $0\fast2_ok[0:0] \fast2_ok$next + sync posedge \coresync_clk + update \fast2_ok $0\fast2_ok[0:0] + end + attribute \src "libresoc.v:173826.3-173827.35" + process $proc$libresoc.v:173826$9725 + assign { } { } + assign $0\fast1$11[63:0]$9726 \fast1$11$next + sync posedge \coresync_clk + update \fast1$11 $0\fast1$11[63:0]$9726 + end + attribute \src "libresoc.v:173828.3-173829.33" + process $proc$libresoc.v:173828$9727 + assign { } { } + assign $0\fast1_ok[0:0] \fast1_ok$next + sync posedge \coresync_clk + update \fast1_ok $0\fast1_ok[0:0] + end + attribute \src "libresoc.v:173830.3-173831.19" + process $proc$libresoc.v:173830$9728 + assign { } { } + assign $0\o[63:0] \o$next + sync posedge \coresync_clk + update \o $0\o[63:0] + end + attribute \src "libresoc.v:173832.3-173833.25" + process $proc$libresoc.v:173832$9729 + assign { } { } + assign $0\o_ok[0:0] \o_ok$next + sync posedge \coresync_clk + update \o_ok $0\o_ok[0:0] + end + attribute \src "libresoc.v:173834.3-173835.59" + process $proc$libresoc.v:173834$9730 + assign { } { } + assign $0\trap_op__insn_type$2[6:0]$9731 \trap_op__insn_type$2$next + sync posedge \coresync_clk + update \trap_op__insn_type$2 $0\trap_op__insn_type$2[6:0]$9731 + end + attribute \src "libresoc.v:173836.3-173837.55" + process $proc$libresoc.v:173836$9732 + assign { } { } + assign $0\trap_op__fn_unit$3[12:0]$9733 \trap_op__fn_unit$3$next + sync posedge \coresync_clk + update \trap_op__fn_unit$3 $0\trap_op__fn_unit$3[12:0]$9733 + end + attribute \src "libresoc.v:173838.3-173839.49" + process $proc$libresoc.v:173838$9734 + assign { } { } + assign $0\trap_op__insn$4[31:0]$9735 \trap_op__insn$4$next + sync posedge \coresync_clk + update \trap_op__insn$4 $0\trap_op__insn$4[31:0]$9735 + end + attribute \src "libresoc.v:173840.3-173841.47" + process $proc$libresoc.v:173840$9736 + assign { } { } + assign $0\trap_op__msr$5[63:0]$9737 \trap_op__msr$5$next + sync posedge \coresync_clk + update \trap_op__msr$5 $0\trap_op__msr$5[63:0]$9737 + end + attribute \src "libresoc.v:173842.3-173843.47" + process $proc$libresoc.v:173842$9738 + assign { } { } + assign $0\trap_op__cia$6[63:0]$9739 \trap_op__cia$6$next + sync posedge \coresync_clk + update \trap_op__cia$6 $0\trap_op__cia$6[63:0]$9739 + end + attribute \src "libresoc.v:173844.3-173845.57" + process $proc$libresoc.v:173844$9740 + assign { } { } + assign $0\trap_op__is_32bit$7[0:0]$9741 \trap_op__is_32bit$7$next + sync posedge \coresync_clk + update \trap_op__is_32bit$7 $0\trap_op__is_32bit$7[0:0]$9741 + end + attribute \src "libresoc.v:173846.3-173847.57" + process $proc$libresoc.v:173846$9742 + assign { } { } + assign $0\trap_op__traptype$8[7:0]$9743 \trap_op__traptype$8$next + sync posedge \coresync_clk + update \trap_op__traptype$8 $0\trap_op__traptype$8[7:0]$9743 + end + attribute \src "libresoc.v:173848.3-173849.57" + process $proc$libresoc.v:173848$9744 + assign { } { } + assign $0\trap_op__trapaddr$9[12:0]$9745 \trap_op__trapaddr$9$next + sync posedge \coresync_clk + update \trap_op__trapaddr$9 $0\trap_op__trapaddr$9[12:0]$9745 + end + attribute \src "libresoc.v:173850.3-173851.59" + process $proc$libresoc.v:173850$9746 + assign { } { } + assign $0\trap_op__ldst_exc$10[7:0]$9747 \trap_op__ldst_exc$10$next + sync posedge \coresync_clk + update \trap_op__ldst_exc$10 $0\trap_op__ldst_exc$10[7:0]$9747 + end + attribute \src "libresoc.v:173852.3-173853.33" + process $proc$libresoc.v:173852$9748 + assign { } { } + assign $0\muxid$1[1:0]$9749 \muxid$1$next + sync posedge \coresync_clk + update \muxid$1 $0\muxid$1[1:0]$9749 + end + attribute \src "libresoc.v:173854.3-173855.29" + process $proc$libresoc.v:173854$9750 + assign { } { } + assign $0\r_busy[0:0] \r_busy$next + sync posedge \coresync_clk + update \r_busy $0\r_busy[0:0] + end + attribute \src "libresoc.v:173900.3-173917.6" + process $proc$libresoc.v:173900$9751 + assign { } { } + assign { } { } + assign { } { } + assign $0\r_busy$next[0:0]$9752 $2\r_busy$next[0:0]$9754 + attribute \src "libresoc.v:173901.5-173901.29" + switch \initial + attribute \src "libresoc.v:173901.9-173901.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\r_busy$next[0:0]$9753 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\r_busy$next[0:0]$9753 1'0 + case + assign $1\r_busy$next[0:0]$9753 \r_busy + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r_busy$next[0:0]$9754 1'0 + case + assign $2\r_busy$next[0:0]$9754 $1\r_busy$next[0:0]$9753 + end + sync always + update \r_busy$next $0\r_busy$next[0:0]$9752 + end + attribute \src "libresoc.v:173918.3-173930.6" + process $proc$libresoc.v:173918$9755 + assign { } { } + assign { } { } + assign $0\muxid$1$next[1:0]$9756 $1\muxid$1$next[1:0]$9757 + attribute \src "libresoc.v:173919.5-173919.29" + switch \initial + attribute \src "libresoc.v:173919.9-173919.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\muxid$1$next[1:0]$9757 \muxid$28 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\muxid$1$next[1:0]$9757 \muxid$28 + case + assign $1\muxid$1$next[1:0]$9757 \muxid$1 + end + sync always + update \muxid$1$next $0\muxid$1$next[1:0]$9756 + end + attribute \src "libresoc.v:173931.3-173951.6" + process $proc$libresoc.v:173931$9758 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\trap_op__cia$6$next[63:0]$9759 $1\trap_op__cia$6$next[63:0]$9768 + assign $0\trap_op__fn_unit$3$next[12:0]$9760 $1\trap_op__fn_unit$3$next[12:0]$9769 + assign $0\trap_op__insn$4$next[31:0]$9761 $1\trap_op__insn$4$next[31:0]$9770 + assign $0\trap_op__insn_type$2$next[6:0]$9762 $1\trap_op__insn_type$2$next[6:0]$9771 + assign $0\trap_op__is_32bit$7$next[0:0]$9763 $1\trap_op__is_32bit$7$next[0:0]$9772 + assign $0\trap_op__ldst_exc$10$next[7:0]$9764 $1\trap_op__ldst_exc$10$next[7:0]$9773 + assign $0\trap_op__msr$5$next[63:0]$9765 $1\trap_op__msr$5$next[63:0]$9774 + assign $0\trap_op__trapaddr$9$next[12:0]$9766 $1\trap_op__trapaddr$9$next[12:0]$9775 + assign $0\trap_op__traptype$8$next[7:0]$9767 $1\trap_op__traptype$8$next[7:0]$9776 + attribute \src "libresoc.v:173932.5-173932.29" + switch \initial + attribute \src "libresoc.v:173932.9-173932.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\trap_op__ldst_exc$10$next[7:0]$9773 $1\trap_op__trapaddr$9$next[12:0]$9775 $1\trap_op__traptype$8$next[7:0]$9776 $1\trap_op__is_32bit$7$next[0:0]$9772 $1\trap_op__cia$6$next[63:0]$9768 $1\trap_op__msr$5$next[63:0]$9774 $1\trap_op__insn$4$next[31:0]$9770 $1\trap_op__fn_unit$3$next[12:0]$9769 $1\trap_op__insn_type$2$next[6:0]$9771 } { \trap_op__ldst_exc$37 \trap_op__trapaddr$36 \trap_op__traptype$35 \trap_op__is_32bit$34 \trap_op__cia$33 \trap_op__msr$32 \trap_op__insn$31 \trap_op__fn_unit$30 \trap_op__insn_type$29 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\trap_op__ldst_exc$10$next[7:0]$9773 $1\trap_op__trapaddr$9$next[12:0]$9775 $1\trap_op__traptype$8$next[7:0]$9776 $1\trap_op__is_32bit$7$next[0:0]$9772 $1\trap_op__cia$6$next[63:0]$9768 $1\trap_op__msr$5$next[63:0]$9774 $1\trap_op__insn$4$next[31:0]$9770 $1\trap_op__fn_unit$3$next[12:0]$9769 $1\trap_op__insn_type$2$next[6:0]$9771 } { \trap_op__ldst_exc$37 \trap_op__trapaddr$36 \trap_op__traptype$35 \trap_op__is_32bit$34 \trap_op__cia$33 \trap_op__msr$32 \trap_op__insn$31 \trap_op__fn_unit$30 \trap_op__insn_type$29 } + case + assign $1\trap_op__cia$6$next[63:0]$9768 \trap_op__cia$6 + assign $1\trap_op__fn_unit$3$next[12:0]$9769 \trap_op__fn_unit$3 + assign $1\trap_op__insn$4$next[31:0]$9770 \trap_op__insn$4 + assign $1\trap_op__insn_type$2$next[6:0]$9771 \trap_op__insn_type$2 + assign $1\trap_op__is_32bit$7$next[0:0]$9772 \trap_op__is_32bit$7 + assign $1\trap_op__ldst_exc$10$next[7:0]$9773 \trap_op__ldst_exc$10 + assign $1\trap_op__msr$5$next[63:0]$9774 \trap_op__msr$5 + assign $1\trap_op__trapaddr$9$next[12:0]$9775 \trap_op__trapaddr$9 + assign $1\trap_op__traptype$8$next[7:0]$9776 \trap_op__traptype$8 + end + sync always + update \trap_op__cia$6$next $0\trap_op__cia$6$next[63:0]$9759 + update \trap_op__fn_unit$3$next $0\trap_op__fn_unit$3$next[12:0]$9760 + update \trap_op__insn$4$next $0\trap_op__insn$4$next[31:0]$9761 + update \trap_op__insn_type$2$next $0\trap_op__insn_type$2$next[6:0]$9762 + update \trap_op__is_32bit$7$next $0\trap_op__is_32bit$7$next[0:0]$9763 + update \trap_op__ldst_exc$10$next $0\trap_op__ldst_exc$10$next[7:0]$9764 + update \trap_op__msr$5$next $0\trap_op__msr$5$next[63:0]$9765 + update \trap_op__trapaddr$9$next $0\trap_op__trapaddr$9$next[12:0]$9766 + update \trap_op__traptype$8$next $0\trap_op__traptype$8$next[7:0]$9767 + end + attribute \src "libresoc.v:173952.3-173970.6" + process $proc$libresoc.v:173952$9777 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\o$next[63:0]$9778 $1\o$next[63:0]$9780 + assign { } { } + assign $0\o_ok$next[0:0]$9779 $2\o_ok$next[0:0]$9782 + attribute \src "libresoc.v:173953.5-173953.29" + switch \initial + attribute \src "libresoc.v:173953.9-173953.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\o_ok$next[0:0]$9781 $1\o$next[63:0]$9780 } { \o_ok$39 \o$38 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\o_ok$next[0:0]$9781 $1\o$next[63:0]$9780 } { \o_ok$39 \o$38 } + case + assign $1\o$next[63:0]$9780 \o + assign $1\o_ok$next[0:0]$9781 \o_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\o_ok$next[0:0]$9782 1'0 + case + assign $2\o_ok$next[0:0]$9782 $1\o_ok$next[0:0]$9781 + end + sync always + update \o$next $0\o$next[63:0]$9778 + update \o_ok$next $0\o_ok$next[0:0]$9779 + end + attribute \src "libresoc.v:173971.3-173989.6" + process $proc$libresoc.v:173971$9783 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\fast1$11$next[63:0]$9785 $1\fast1$11$next[63:0]$9787 + assign $0\fast1_ok$next[0:0]$9784 $2\fast1_ok$next[0:0]$9788 + attribute \src "libresoc.v:173972.5-173972.29" + switch \initial + attribute \src "libresoc.v:173972.9-173972.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\fast1_ok$next[0:0]$9786 $1\fast1$11$next[63:0]$9787 } { \fast1_ok$41 \fast1$40 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\fast1_ok$next[0:0]$9786 $1\fast1$11$next[63:0]$9787 } { \fast1_ok$41 \fast1$40 } + case + assign $1\fast1_ok$next[0:0]$9786 \fast1_ok + assign $1\fast1$11$next[63:0]$9787 \fast1$11 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\fast1_ok$next[0:0]$9788 1'0 + case + assign $2\fast1_ok$next[0:0]$9788 $1\fast1_ok$next[0:0]$9786 + end + sync always + update \fast1_ok$next $0\fast1_ok$next[0:0]$9784 + update \fast1$11$next $0\fast1$11$next[63:0]$9785 + end + attribute \src "libresoc.v:173990.3-174008.6" + process $proc$libresoc.v:173990$9789 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\fast2$12$next[63:0]$9791 $1\fast2$12$next[63:0]$9793 + assign $0\fast2_ok$next[0:0]$9790 $2\fast2_ok$next[0:0]$9794 + attribute \src "libresoc.v:173991.5-173991.29" + switch \initial + attribute \src "libresoc.v:173991.9-173991.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\fast2_ok$next[0:0]$9792 $1\fast2$12$next[63:0]$9793 } { \fast2_ok$43 \fast2$42 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\fast2_ok$next[0:0]$9792 $1\fast2$12$next[63:0]$9793 } { \fast2_ok$43 \fast2$42 } + case + assign $1\fast2_ok$next[0:0]$9792 \fast2_ok + assign $1\fast2$12$next[63:0]$9793 \fast2$12 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\fast2_ok$next[0:0]$9794 1'0 + case + assign $2\fast2_ok$next[0:0]$9794 $1\fast2_ok$next[0:0]$9792 + end + sync always + update \fast2_ok$next $0\fast2_ok$next[0:0]$9790 + update \fast2$12$next $0\fast2$12$next[63:0]$9791 + end + attribute \src "libresoc.v:174009.3-174027.6" + process $proc$libresoc.v:174009$9795 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\nia$next[63:0]$9796 $1\nia$next[63:0]$9798 + assign { } { } + assign $0\nia_ok$next[0:0]$9797 $2\nia_ok$next[0:0]$9800 + attribute \src "libresoc.v:174010.5-174010.29" + switch \initial + attribute \src "libresoc.v:174010.9-174010.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\nia_ok$next[0:0]$9799 $1\nia$next[63:0]$9798 } { \nia_ok$45 \nia$44 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\nia_ok$next[0:0]$9799 $1\nia$next[63:0]$9798 } { \nia_ok$45 \nia$44 } + case + assign $1\nia$next[63:0]$9798 \nia + assign $1\nia_ok$next[0:0]$9799 \nia_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\nia_ok$next[0:0]$9800 1'0 + case + assign $2\nia_ok$next[0:0]$9800 $1\nia_ok$next[0:0]$9799 + end + sync always + update \nia$next $0\nia$next[63:0]$9796 + update \nia_ok$next $0\nia_ok$next[0:0]$9797 + end + attribute \src "libresoc.v:174028.3-174046.6" + process $proc$libresoc.v:174028$9801 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\msr$next[63:0]$9802 $1\msr$next[63:0]$9804 + assign { } { } + assign $0\msr_ok$next[0:0]$9803 $2\msr_ok$next[0:0]$9806 + attribute \src "libresoc.v:174029.5-174029.29" + switch \initial + attribute \src "libresoc.v:174029.9-174029.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\msr_ok$next[0:0]$9805 $1\msr$next[63:0]$9804 } { \msr_ok$47 \msr$46 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\msr_ok$next[0:0]$9805 $1\msr$next[63:0]$9804 } { \msr_ok$47 \msr$46 } + case + assign $1\msr$next[63:0]$9804 \msr + assign $1\msr_ok$next[0:0]$9805 \msr_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\msr_ok$next[0:0]$9806 1'0 + case + assign $2\msr_ok$next[0:0]$9806 $1\msr_ok$next[0:0]$9805 + end + sync always + update \msr$next $0\msr$next[63:0]$9802 + update \msr_ok$next $0\msr_ok$next[0:0]$9803 + end + connect \$26 $and$libresoc.v:173813$9717_Y + connect \p_ready_o \n_i_rdy_data + connect \n_valid_o \r_busy + connect { \msr_ok$47 \msr$46 } { \main_msr_ok \main_msr } + connect { \nia_ok$45 \nia$44 } { \main_nia_ok \main_nia } + connect { \fast2_ok$43 \fast2$42 } { \main_fast2_ok \main_fast2$24 } + connect { \fast1_ok$41 \fast1$40 } { \main_fast1_ok \main_fast1$23 } + connect { \o_ok$39 \o$38 } { \main_o_ok \main_o } + connect { \trap_op__ldst_exc$37 \trap_op__trapaddr$36 \trap_op__traptype$35 \trap_op__is_32bit$34 \trap_op__cia$33 \trap_op__msr$32 \trap_op__insn$31 \trap_op__fn_unit$30 \trap_op__insn_type$29 } { \main_trap_op__ldst_exc$22 \main_trap_op__trapaddr$21 \main_trap_op__traptype$20 \main_trap_op__is_32bit$19 \main_trap_op__cia$18 \main_trap_op__msr$17 \main_trap_op__insn$16 \main_trap_op__fn_unit$15 \main_trap_op__insn_type$14 } + connect \muxid$28 \main_muxid$13 + connect \p_valid_i_p_ready_o \$26 + connect \n_i_rdy_data \n_ready_i + connect \p_valid_i$25 \p_valid_i + connect \main_fast2 \fast2 + connect \main_fast1 \fast1 + connect \main_rb \rb + connect \main_ra \ra + connect { \main_trap_op__ldst_exc \main_trap_op__trapaddr \main_trap_op__traptype \main_trap_op__is_32bit \main_trap_op__cia \main_trap_op__msr \main_trap_op__insn \main_trap_op__fn_unit \main_trap_op__insn_type } { \trap_op__ldst_exc \trap_op__trapaddr \trap_op__traptype \trap_op__is_32bit \trap_op__cia \trap_op__msr \trap_op__insn \trap_op__fn_unit \trap_op__insn_type } + connect \main_muxid \muxid +end +attribute \src "libresoc.v:174069.1-175558.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_end" +attribute \generator "nMigen" +module \pipe_end + attribute \src "libresoc.v:175396.3-175414.6" + wire width 4 $0\cr_a$next[3:0]$9897 + attribute \src "libresoc.v:175215.3-175216.25" + wire width 4 $0\cr_a[3:0] + attribute \src "libresoc.v:175396.3-175414.6" + wire $0\cr_a_ok$next[0:0]$9898 + attribute \src "libresoc.v:175217.3-175218.31" + wire $0\cr_a_ok[0:0] + attribute \src "libresoc.v:174070.7-174070.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:175484.3-175525.6" + wire width 4 $0\logical_op__data_len$18$next[3:0]$9922 + attribute \src "libresoc.v:175255.3-175256.65" + wire width 4 $0\logical_op__data_len$18[3:0]$9884 + attribute \src "libresoc.v:174111.13-174111.45" + wire width 4 $0\logical_op__data_len$18[3:0]$9968 + attribute \src "libresoc.v:175484.3-175525.6" + wire width 13 $0\logical_op__fn_unit$3$next[12:0]$9923 + attribute \src "libresoc.v:175225.3-175226.61" + wire width 13 $0\logical_op__fn_unit$3[12:0]$9854 + attribute \src "libresoc.v:174148.14-174148.48" + wire width 13 $0\logical_op__fn_unit$3[12:0]$9970 + attribute \src "libresoc.v:175484.3-175525.6" + wire width 64 $0\logical_op__imm_data__data$4$next[63:0]$9924 + attribute \src "libresoc.v:175227.3-175228.75" + wire width 64 $0\logical_op__imm_data__data$4[63:0]$9856 + attribute \src "libresoc.v:174171.14-174171.67" + wire width 64 $0\logical_op__imm_data__data$4[63:0]$9972 + attribute \src "libresoc.v:175484.3-175525.6" + wire $0\logical_op__imm_data__ok$5$next[0:0]$9925 + attribute \src "libresoc.v:175229.3-175230.71" + wire $0\logical_op__imm_data__ok$5[0:0]$9858 + attribute \src "libresoc.v:174180.7-174180.42" + wire $0\logical_op__imm_data__ok$5[0:0]$9974 + attribute \src "libresoc.v:175484.3-175525.6" + wire width 2 $0\logical_op__input_carry$12$next[1:0]$9926 + attribute \src "libresoc.v:175243.3-175244.71" + wire width 2 $0\logical_op__input_carry$12[1:0]$9872 + attribute \src "libresoc.v:174197.13-174197.48" + wire width 2 $0\logical_op__input_carry$12[1:0]$9976 + attribute \src "libresoc.v:175484.3-175525.6" + wire width 32 $0\logical_op__insn$19$next[31:0]$9927 + attribute \src "libresoc.v:175257.3-175258.57" + wire width 32 $0\logical_op__insn$19[31:0]$9886 + attribute \src "libresoc.v:174210.14-174210.43" + wire width 32 $0\logical_op__insn$19[31:0]$9978 + attribute \src "libresoc.v:175484.3-175525.6" + wire width 7 $0\logical_op__insn_type$2$next[6:0]$9928 + attribute \src "libresoc.v:175223.3-175224.65" + wire width 7 $0\logical_op__insn_type$2[6:0]$9852 + attribute \src "libresoc.v:174367.13-174367.46" + wire width 7 $0\logical_op__insn_type$2[6:0]$9980 + attribute \src "libresoc.v:175484.3-175525.6" + wire $0\logical_op__invert_in$10$next[0:0]$9929 + attribute \src "libresoc.v:175239.3-175240.67" + wire $0\logical_op__invert_in$10[0:0]$9868 + attribute \src "libresoc.v:174450.7-174450.40" + wire $0\logical_op__invert_in$10[0:0]$9982 + attribute \src "libresoc.v:175484.3-175525.6" + wire $0\logical_op__invert_out$13$next[0:0]$9930 + attribute \src "libresoc.v:175245.3-175246.69" + wire $0\logical_op__invert_out$13[0:0]$9874 + attribute \src "libresoc.v:174459.7-174459.41" + wire $0\logical_op__invert_out$13[0:0]$9984 + attribute \src "libresoc.v:175484.3-175525.6" + wire $0\logical_op__is_32bit$16$next[0:0]$9931 + attribute \src "libresoc.v:175251.3-175252.65" + wire $0\logical_op__is_32bit$16[0:0]$9880 + attribute \src "libresoc.v:174468.7-174468.39" + wire $0\logical_op__is_32bit$16[0:0]$9986 + attribute \src "libresoc.v:175484.3-175525.6" + wire $0\logical_op__is_signed$17$next[0:0]$9932 + attribute \src "libresoc.v:175253.3-175254.67" + wire $0\logical_op__is_signed$17[0:0]$9882 + attribute \src "libresoc.v:174477.7-174477.40" + wire $0\logical_op__is_signed$17[0:0]$9988 + attribute \src "libresoc.v:175484.3-175525.6" + wire $0\logical_op__oe__oe$8$next[0:0]$9933 + attribute \src "libresoc.v:175235.3-175236.59" + wire $0\logical_op__oe__oe$8[0:0]$9864 + attribute \src "libresoc.v:174486.7-174486.36" + wire $0\logical_op__oe__oe$8[0:0]$9990 + attribute \src "libresoc.v:175484.3-175525.6" + wire $0\logical_op__oe__ok$9$next[0:0]$9934 + attribute \src "libresoc.v:175237.3-175238.59" + wire $0\logical_op__oe__ok$9[0:0]$9866 + attribute \src "libresoc.v:174497.7-174497.36" + wire $0\logical_op__oe__ok$9[0:0]$9992 + attribute \src "libresoc.v:175484.3-175525.6" + wire $0\logical_op__output_carry$15$next[0:0]$9935 + attribute \src "libresoc.v:175249.3-175250.73" + wire $0\logical_op__output_carry$15[0:0]$9878 + attribute \src "libresoc.v:174504.7-174504.43" + wire $0\logical_op__output_carry$15[0:0]$9994 + attribute \src "libresoc.v:175484.3-175525.6" + wire $0\logical_op__rc__ok$7$next[0:0]$9936 + attribute \src "libresoc.v:175233.3-175234.59" + wire $0\logical_op__rc__ok$7[0:0]$9862 + attribute \src "libresoc.v:174513.7-174513.36" + wire $0\logical_op__rc__ok$7[0:0]$9996 + attribute \src "libresoc.v:175484.3-175525.6" + wire $0\logical_op__rc__rc$6$next[0:0]$9937 + attribute \src "libresoc.v:175231.3-175232.59" + wire $0\logical_op__rc__rc$6[0:0]$9860 + attribute \src "libresoc.v:174522.7-174522.36" + wire $0\logical_op__rc__rc$6[0:0]$9998 + attribute \src "libresoc.v:175484.3-175525.6" + wire $0\logical_op__write_cr0$14$next[0:0]$9938 + attribute \src "libresoc.v:174531.7-174531.40" + wire $0\logical_op__write_cr0$14[0:0]$10000 + attribute \src "libresoc.v:175247.3-175248.67" + wire $0\logical_op__write_cr0$14[0:0]$9876 + attribute \src "libresoc.v:175484.3-175525.6" + wire $0\logical_op__zero_a$11$next[0:0]$9939 + attribute \src "libresoc.v:174540.7-174540.37" + wire $0\logical_op__zero_a$11[0:0]$10002 + attribute \src "libresoc.v:175241.3-175242.61" + wire $0\logical_op__zero_a$11[0:0]$9870 + attribute \src "libresoc.v:175471.3-175483.6" + wire width 2 $0\muxid$1$next[1:0]$9919 + attribute \src "libresoc.v:174549.13-174549.29" + wire width 2 $0\muxid$1[1:0]$10004 + attribute \src "libresoc.v:175259.3-175260.33" + wire width 2 $0\muxid$1[1:0]$9888 + attribute \src "libresoc.v:175377.3-175395.6" + wire width 64 $0\o$next[63:0]$9891 + attribute \src "libresoc.v:175219.3-175220.19" + wire width 64 $0\o[63:0] + attribute \src "libresoc.v:175377.3-175395.6" + wire $0\o_ok$next[0:0]$9892 + attribute \src "libresoc.v:175221.3-175222.25" + wire $0\o_ok[0:0] + attribute \src "libresoc.v:175453.3-175470.6" + wire $0\r_busy$next[0:0]$9915 + attribute \src "libresoc.v:175261.3-175262.29" + wire $0\r_busy[0:0] + attribute \src "libresoc.v:175415.3-175433.6" + wire width 2 $0\xer_ov$next[1:0]$9903 + attribute \src "libresoc.v:175211.3-175212.29" + wire width 2 $0\xer_ov[1:0] + attribute \src "libresoc.v:175415.3-175433.6" + wire $0\xer_ov_ok$next[0:0]$9904 + attribute \src "libresoc.v:175213.3-175214.35" + wire $0\xer_ov_ok[0:0] + attribute \src "libresoc.v:175434.3-175452.6" + wire $0\xer_so$20$next[0:0]$9910 + attribute \src "libresoc.v:175192.7-175192.25" + wire $0\xer_so$20[0:0]$10011 + attribute \src "libresoc.v:175207.3-175208.37" + wire $0\xer_so$20[0:0]$9843 + attribute \src "libresoc.v:175434.3-175452.6" + wire $0\xer_so_ok$next[0:0]$9909 + attribute \src "libresoc.v:175209.3-175210.35" + wire $0\xer_so_ok[0:0] + attribute \src "libresoc.v:175396.3-175414.6" + wire width 4 $1\cr_a$next[3:0]$9899 + attribute \src "libresoc.v:174079.13-174079.24" + wire width 4 $1\cr_a[3:0] + attribute \src "libresoc.v:175396.3-175414.6" + wire $1\cr_a_ok$next[0:0]$9900 + attribute \src "libresoc.v:174088.7-174088.21" + wire $1\cr_a_ok[0:0] + attribute \src "libresoc.v:175484.3-175525.6" + wire width 4 $1\logical_op__data_len$18$next[3:0]$9940 + attribute \src "libresoc.v:175484.3-175525.6" + wire width 13 $1\logical_op__fn_unit$3$next[12:0]$9941 + attribute \src "libresoc.v:175484.3-175525.6" + wire width 64 $1\logical_op__imm_data__data$4$next[63:0]$9942 + attribute \src "libresoc.v:175484.3-175525.6" + wire $1\logical_op__imm_data__ok$5$next[0:0]$9943 + attribute \src "libresoc.v:175484.3-175525.6" + wire width 2 $1\logical_op__input_carry$12$next[1:0]$9944 + attribute \src "libresoc.v:175484.3-175525.6" + wire width 32 $1\logical_op__insn$19$next[31:0]$9945 + attribute \src "libresoc.v:175484.3-175525.6" + wire width 7 $1\logical_op__insn_type$2$next[6:0]$9946 + attribute \src "libresoc.v:175484.3-175525.6" + wire $1\logical_op__invert_in$10$next[0:0]$9947 + attribute \src "libresoc.v:175484.3-175525.6" + wire $1\logical_op__invert_out$13$next[0:0]$9948 + attribute \src "libresoc.v:175484.3-175525.6" + wire $1\logical_op__is_32bit$16$next[0:0]$9949 + attribute \src "libresoc.v:175484.3-175525.6" + wire $1\logical_op__is_signed$17$next[0:0]$9950 + attribute \src "libresoc.v:175484.3-175525.6" + wire $1\logical_op__oe__oe$8$next[0:0]$9951 + attribute \src "libresoc.v:175484.3-175525.6" + wire $1\logical_op__oe__ok$9$next[0:0]$9952 + attribute \src "libresoc.v:175484.3-175525.6" + wire $1\logical_op__output_carry$15$next[0:0]$9953 + attribute \src "libresoc.v:175484.3-175525.6" + wire $1\logical_op__rc__ok$7$next[0:0]$9954 + attribute \src "libresoc.v:175484.3-175525.6" + wire $1\logical_op__rc__rc$6$next[0:0]$9955 + attribute \src "libresoc.v:175484.3-175525.6" + wire $1\logical_op__write_cr0$14$next[0:0]$9956 + attribute \src "libresoc.v:175484.3-175525.6" + wire $1\logical_op__zero_a$11$next[0:0]$9957 + attribute \src "libresoc.v:175471.3-175483.6" + wire width 2 $1\muxid$1$next[1:0]$9920 + attribute \src "libresoc.v:175377.3-175395.6" + wire width 64 $1\o$next[63:0]$9893 + attribute \src "libresoc.v:174562.14-174562.38" + wire width 64 $1\o[63:0] + attribute \src "libresoc.v:175377.3-175395.6" + wire $1\o_ok$next[0:0]$9894 + attribute \src "libresoc.v:174569.7-174569.18" + wire $1\o_ok[0:0] + attribute \src "libresoc.v:175453.3-175470.6" + wire $1\r_busy$next[0:0]$9916 + attribute \src "libresoc.v:175157.7-175157.20" + wire $1\r_busy[0:0] + attribute \src "libresoc.v:175415.3-175433.6" + wire width 2 $1\xer_ov$next[1:0]$9905 + attribute \src "libresoc.v:175172.13-175172.26" + wire width 2 $1\xer_ov[1:0] + attribute \src "libresoc.v:175415.3-175433.6" + wire $1\xer_ov_ok$next[0:0]$9906 + attribute \src "libresoc.v:175179.7-175179.23" + wire $1\xer_ov_ok[0:0] + attribute \src "libresoc.v:175434.3-175452.6" + wire $1\xer_so$20$next[0:0]$9912 + attribute \src "libresoc.v:175434.3-175452.6" + wire $1\xer_so_ok$next[0:0]$9911 + attribute \src "libresoc.v:175197.7-175197.23" + wire $1\xer_so_ok[0:0] + attribute \src "libresoc.v:175396.3-175414.6" + wire $2\cr_a_ok$next[0:0]$9901 + attribute \src "libresoc.v:175484.3-175525.6" + wire width 64 $2\logical_op__imm_data__data$4$next[63:0]$9958 + attribute \src "libresoc.v:175484.3-175525.6" + wire $2\logical_op__imm_data__ok$5$next[0:0]$9959 + attribute \src "libresoc.v:175484.3-175525.6" + wire $2\logical_op__oe__oe$8$next[0:0]$9960 + attribute \src "libresoc.v:175484.3-175525.6" + wire $2\logical_op__oe__ok$9$next[0:0]$9961 + attribute \src "libresoc.v:175484.3-175525.6" + wire $2\logical_op__rc__ok$7$next[0:0]$9962 + attribute \src "libresoc.v:175484.3-175525.6" + wire $2\logical_op__rc__rc$6$next[0:0]$9963 + attribute \src "libresoc.v:175377.3-175395.6" + wire $2\o_ok$next[0:0]$9895 + attribute \src "libresoc.v:175453.3-175470.6" + wire $2\r_busy$next[0:0]$9917 + attribute \src "libresoc.v:175415.3-175433.6" + wire $2\xer_ov_ok$next[0:0]$9907 + attribute \src "libresoc.v:175434.3-175452.6" + wire $2\xer_so_ok$next[0:0]$9913 + attribute \src "libresoc.v:175206.18-175206.118" + wire $and$libresoc.v:175206$9841_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" + wire \$74 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 62 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 output 56 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \cr_a$68 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \cr_a$97 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \cr_a$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 57 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_a_ok$67 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_a_ok$69 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_a_ok$98 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \cr_a_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire input 30 \div_by_zero + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire input 28 \dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire input 29 \dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire input 27 \dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire input 26 \divisor_neg + attribute \src "libresoc.v:174070.7-174070.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 21 \logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 52 \logical_op__data_len$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \logical_op__data_len$18$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \logical_op__data_len$93 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 input 6 \logical_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 output 37 \logical_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \logical_op__fn_unit$3$next + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \logical_op__fn_unit$78 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 7 \logical_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 38 \logical_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \logical_op__imm_data__data$4$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \logical_op__imm_data__data$79 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \logical_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 39 \logical_op__imm_data__ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__imm_data__ok$5$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__imm_data__ok$80 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 15 \logical_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 46 \logical_op__input_carry$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \logical_op__input_carry$12$next + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \logical_op__input_carry$87 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 22 \logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 53 \logical_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \logical_op__insn$19$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \logical_op__insn$94 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 5 \logical_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 36 \logical_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \logical_op__insn_type$2$next + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \logical_op__insn_type$77 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 44 \logical_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_in$10$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_in$85 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 16 \logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 47 \logical_op__invert_out$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_out$13$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_out$88 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 19 \logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 50 \logical_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_32bit$16$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_32bit$91 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 20 \logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 51 \logical_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_signed$17$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_signed$92 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 11 \logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 42 \logical_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__oe$8$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__oe$83 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__ok$84 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 43 \logical_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__ok$9$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 18 \logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 49 \logical_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__output_carry$15$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__output_carry$90 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 41 \logical_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__ok$7$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__ok$82 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 40 \logical_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__rc$6$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__rc$81 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 17 \logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 48 \logical_op__write_cr0$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__write_cr0$14$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__write_cr0$89 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 45 \logical_op__zero_a$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__zero_a$11$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__zero_a$86 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 input 4 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 output 35 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid$1$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid$76 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + wire \n_i_rdy_data + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire input 34 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire output 33 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 54 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \o$95 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \o$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 55 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \o_ok$96 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \o_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \output_cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 4 \output_cr_a$62 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \output_cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \output_logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \output_logical_op__data_len$58 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \output_logical_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \output_logical_op__fn_unit$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \output_logical_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \output_logical_op__imm_data__data$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__imm_data__ok$45 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \output_logical_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \output_logical_op__input_carry$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \output_logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \output_logical_op__insn$59 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \output_logical_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \output_logical_op__insn_type$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__invert_in$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__invert_out$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__is_32bit$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__is_signed$57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__oe__oe$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__oe__ok$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__output_carry$55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__rc__ok$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__rc__rc$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__write_cr0$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__zero_a$51 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \output_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \output_muxid$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \output_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 \output_o$60 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \output_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \output_o_ok$61 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire \output_stage_div_by_zero + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire \output_stage_dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire \output_stage_dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire \output_stage_dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire \output_stage_divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \output_stage_logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \output_stage_logical_op__data_len$38 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \output_stage_logical_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \output_stage_logical_op__fn_unit$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \output_stage_logical_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \output_stage_logical_op__imm_data__data$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_stage_logical_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_stage_logical_op__imm_data__ok$25 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \output_stage_logical_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src 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\logical_op__imm_data__ok$5 \output_stage_logical_op__imm_data__ok$25 + connect \logical_op__input_carry \output_stage_logical_op__input_carry + connect \logical_op__input_carry$12 \output_stage_logical_op__input_carry$32 + connect \logical_op__insn \output_stage_logical_op__insn + connect \logical_op__insn$19 \output_stage_logical_op__insn$39 + connect \logical_op__insn_type \output_stage_logical_op__insn_type + connect \logical_op__insn_type$2 \output_stage_logical_op__insn_type$22 + connect \logical_op__invert_in \output_stage_logical_op__invert_in + connect \logical_op__invert_in$10 \output_stage_logical_op__invert_in$30 + connect \logical_op__invert_out \output_stage_logical_op__invert_out + connect \logical_op__invert_out$13 \output_stage_logical_op__invert_out$33 + connect \logical_op__is_32bit \output_stage_logical_op__is_32bit + connect \logical_op__is_32bit$16 \output_stage_logical_op__is_32bit$36 + connect \logical_op__is_signed \output_stage_logical_op__is_signed + connect \logical_op__is_signed$17 \output_stage_logical_op__is_signed$37 + connect \logical_op__oe__oe \output_stage_logical_op__oe__oe + connect \logical_op__oe__oe$8 \output_stage_logical_op__oe__oe$28 + connect \logical_op__oe__ok \output_stage_logical_op__oe__ok + connect \logical_op__oe__ok$9 \output_stage_logical_op__oe__ok$29 + connect \logical_op__output_carry \output_stage_logical_op__output_carry + connect \logical_op__output_carry$15 \output_stage_logical_op__output_carry$35 + connect \logical_op__rc__ok \output_stage_logical_op__rc__ok + connect \logical_op__rc__ok$7 \output_stage_logical_op__rc__ok$27 + connect \logical_op__rc__rc \output_stage_logical_op__rc__rc + connect \logical_op__rc__rc$6 \output_stage_logical_op__rc__rc$26 + connect \logical_op__write_cr0 \output_stage_logical_op__write_cr0 + connect \logical_op__write_cr0$14 \output_stage_logical_op__write_cr0$34 + connect \logical_op__zero_a \output_stage_logical_op__zero_a + connect \logical_op__zero_a$11 \output_stage_logical_op__zero_a$31 + connect \muxid \output_stage_muxid + connect \muxid$1 \output_stage_muxid$21 + connect \o \output_stage_o + connect \o_ok \output_stage_o_ok + connect \quotient_root \output_stage_quotient_root + connect \remainder \output_stage_remainder + connect \xer_ov \output_stage_xer_ov + connect \xer_ov_ok \output_stage_xer_ov_ok + connect \xer_so \output_stage_xer_so + connect \xer_so$20 \output_stage_xer_so$40 + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:175373.10-175376.4" + cell \p$81 \p + connect \p_ready_o \p_ready_o + connect \p_valid_i \p_valid_i + end + attribute \src "libresoc.v:174070.7-174070.20" + process $proc$libresoc.v:174070$9964 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:174079.13-174079.24" + process $proc$libresoc.v:174079$9965 + assign { } { } + assign $1\cr_a[3:0] 4'0000 + sync always + sync init + update \cr_a $1\cr_a[3:0] + end + attribute \src "libresoc.v:174088.7-174088.21" + process $proc$libresoc.v:174088$9966 + assign { } { } + assign $1\cr_a_ok[0:0] 1'0 + sync always + sync init + update \cr_a_ok $1\cr_a_ok[0:0] + end + attribute \src "libresoc.v:174111.13-174111.45" + process $proc$libresoc.v:174111$9967 + assign { } { } + assign $0\logical_op__data_len$18[3:0]$9968 4'0000 + sync always + sync init + update \logical_op__data_len$18 $0\logical_op__data_len$18[3:0]$9968 + end + attribute \src "libresoc.v:174148.14-174148.48" + process $proc$libresoc.v:174148$9969 + assign { } { } + assign $0\logical_op__fn_unit$3[12:0]$9970 13'0000000000000 + sync always + sync init + update \logical_op__fn_unit$3 $0\logical_op__fn_unit$3[12:0]$9970 + end + attribute \src "libresoc.v:174171.14-174171.67" + process $proc$libresoc.v:174171$9971 + assign { } { } + assign $0\logical_op__imm_data__data$4[63:0]$9972 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \logical_op__imm_data__data$4 $0\logical_op__imm_data__data$4[63:0]$9972 + end + attribute \src "libresoc.v:174180.7-174180.42" + process $proc$libresoc.v:174180$9973 + assign { } { } + assign $0\logical_op__imm_data__ok$5[0:0]$9974 1'0 + sync always + sync init + update \logical_op__imm_data__ok$5 $0\logical_op__imm_data__ok$5[0:0]$9974 + end + attribute \src "libresoc.v:174197.13-174197.48" + process $proc$libresoc.v:174197$9975 + assign { } { } + assign $0\logical_op__input_carry$12[1:0]$9976 2'00 + sync always + sync init + update \logical_op__input_carry$12 $0\logical_op__input_carry$12[1:0]$9976 + end + attribute \src "libresoc.v:174210.14-174210.43" + process $proc$libresoc.v:174210$9977 + assign { } { } + assign $0\logical_op__insn$19[31:0]$9978 0 + sync always + sync init + update \logical_op__insn$19 $0\logical_op__insn$19[31:0]$9978 + end + attribute \src "libresoc.v:174367.13-174367.46" + process $proc$libresoc.v:174367$9979 + assign { } { } + assign $0\logical_op__insn_type$2[6:0]$9980 7'0000000 + sync always + sync init + update \logical_op__insn_type$2 $0\logical_op__insn_type$2[6:0]$9980 + end + attribute \src "libresoc.v:174450.7-174450.40" + process $proc$libresoc.v:174450$9981 + assign { } { } + assign $0\logical_op__invert_in$10[0:0]$9982 1'0 + sync always + sync init + update \logical_op__invert_in$10 $0\logical_op__invert_in$10[0:0]$9982 + end + attribute \src "libresoc.v:174459.7-174459.41" + process $proc$libresoc.v:174459$9983 + assign { } { } + assign $0\logical_op__invert_out$13[0:0]$9984 1'0 + sync always + sync init + update \logical_op__invert_out$13 $0\logical_op__invert_out$13[0:0]$9984 + end + attribute \src "libresoc.v:174468.7-174468.39" + process $proc$libresoc.v:174468$9985 + assign { } { } + assign $0\logical_op__is_32bit$16[0:0]$9986 1'0 + sync always + sync init + update \logical_op__is_32bit$16 $0\logical_op__is_32bit$16[0:0]$9986 + end + attribute \src "libresoc.v:174477.7-174477.40" + process $proc$libresoc.v:174477$9987 + assign { } { } + assign $0\logical_op__is_signed$17[0:0]$9988 1'0 + sync always + sync init + update \logical_op__is_signed$17 $0\logical_op__is_signed$17[0:0]$9988 + end + attribute \src "libresoc.v:174486.7-174486.36" + process $proc$libresoc.v:174486$9989 + assign { } { } + assign $0\logical_op__oe__oe$8[0:0]$9990 1'0 + sync always + sync init + update \logical_op__oe__oe$8 $0\logical_op__oe__oe$8[0:0]$9990 + end + attribute \src "libresoc.v:174497.7-174497.36" + process $proc$libresoc.v:174497$9991 + assign { } { } + assign $0\logical_op__oe__ok$9[0:0]$9992 1'0 + sync always + sync init + update \logical_op__oe__ok$9 $0\logical_op__oe__ok$9[0:0]$9992 + end + attribute \src "libresoc.v:174504.7-174504.43" + process $proc$libresoc.v:174504$9993 + assign { } { } + assign $0\logical_op__output_carry$15[0:0]$9994 1'0 + sync always + sync init + update \logical_op__output_carry$15 $0\logical_op__output_carry$15[0:0]$9994 + end + attribute \src "libresoc.v:174513.7-174513.36" + process $proc$libresoc.v:174513$9995 + assign { } { } + assign $0\logical_op__rc__ok$7[0:0]$9996 1'0 + sync always + sync init + update \logical_op__rc__ok$7 $0\logical_op__rc__ok$7[0:0]$9996 + end + attribute \src "libresoc.v:174522.7-174522.36" + process $proc$libresoc.v:174522$9997 + assign { } { } + assign $0\logical_op__rc__rc$6[0:0]$9998 1'0 + sync always + sync init + update \logical_op__rc__rc$6 $0\logical_op__rc__rc$6[0:0]$9998 + end + attribute \src "libresoc.v:174531.7-174531.40" + process $proc$libresoc.v:174531$9999 + assign { } { } + assign $0\logical_op__write_cr0$14[0:0]$10000 1'0 + sync always + sync init + update \logical_op__write_cr0$14 $0\logical_op__write_cr0$14[0:0]$10000 + end + attribute \src "libresoc.v:174540.7-174540.37" + process $proc$libresoc.v:174540$10001 + assign { } { } + assign $0\logical_op__zero_a$11[0:0]$10002 1'0 + sync always + sync init + update \logical_op__zero_a$11 $0\logical_op__zero_a$11[0:0]$10002 + end + attribute \src "libresoc.v:174549.13-174549.29" + process $proc$libresoc.v:174549$10003 + assign { } { } + assign $0\muxid$1[1:0]$10004 2'00 + sync always + sync init + update \muxid$1 $0\muxid$1[1:0]$10004 + end + attribute \src "libresoc.v:174562.14-174562.38" + process $proc$libresoc.v:174562$10005 + assign { } { } + assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \o $1\o[63:0] + end + attribute \src "libresoc.v:174569.7-174569.18" + process $proc$libresoc.v:174569$10006 + assign { } { } + assign $1\o_ok[0:0] 1'0 + sync always + sync init + update \o_ok $1\o_ok[0:0] + end + attribute \src "libresoc.v:175157.7-175157.20" + process $proc$libresoc.v:175157$10007 + assign { } { } + assign $1\r_busy[0:0] 1'0 + sync always + sync init + update \r_busy $1\r_busy[0:0] + end + attribute \src "libresoc.v:175172.13-175172.26" + process $proc$libresoc.v:175172$10008 + assign { } { } + assign $1\xer_ov[1:0] 2'00 + sync always + sync init + update \xer_ov $1\xer_ov[1:0] + end + attribute \src "libresoc.v:175179.7-175179.23" + process $proc$libresoc.v:175179$10009 + assign { } { } + assign $1\xer_ov_ok[0:0] 1'0 + sync always + sync init + update \xer_ov_ok $1\xer_ov_ok[0:0] + end + attribute \src "libresoc.v:175192.7-175192.25" + process $proc$libresoc.v:175192$10010 + assign { } { } + assign $0\xer_so$20[0:0]$10011 1'0 + sync always + sync init + update \xer_so$20 $0\xer_so$20[0:0]$10011 + end + attribute \src "libresoc.v:175197.7-175197.23" + process $proc$libresoc.v:175197$10012 + assign { } { } + assign $1\xer_so_ok[0:0] 1'0 + sync always + sync init + update \xer_so_ok $1\xer_so_ok[0:0] + end + attribute \src "libresoc.v:175207.3-175208.37" + process $proc$libresoc.v:175207$9842 + assign { } { } + assign $0\xer_so$20[0:0]$9843 \xer_so$20$next + sync posedge \coresync_clk + update \xer_so$20 $0\xer_so$20[0:0]$9843 + end + attribute \src "libresoc.v:175209.3-175210.35" + process $proc$libresoc.v:175209$9844 + assign { } { } + assign $0\xer_so_ok[0:0] \xer_so_ok$next + sync posedge \coresync_clk + update \xer_so_ok $0\xer_so_ok[0:0] + end + attribute \src "libresoc.v:175211.3-175212.29" + process $proc$libresoc.v:175211$9845 + assign { } { } + assign $0\xer_ov[1:0] \xer_ov$next + sync posedge \coresync_clk + update \xer_ov $0\xer_ov[1:0] + end + attribute \src "libresoc.v:175213.3-175214.35" + process $proc$libresoc.v:175213$9846 + assign { } { } + assign $0\xer_ov_ok[0:0] \xer_ov_ok$next + sync posedge \coresync_clk + update \xer_ov_ok $0\xer_ov_ok[0:0] + end + attribute \src "libresoc.v:175215.3-175216.25" + process $proc$libresoc.v:175215$9847 + assign { } { } + assign $0\cr_a[3:0] \cr_a$next + sync posedge \coresync_clk + update \cr_a $0\cr_a[3:0] + end + attribute \src "libresoc.v:175217.3-175218.31" + process $proc$libresoc.v:175217$9848 + assign { } { } + assign $0\cr_a_ok[0:0] \cr_a_ok$next + sync posedge \coresync_clk + update \cr_a_ok $0\cr_a_ok[0:0] + end + attribute \src "libresoc.v:175219.3-175220.19" + process $proc$libresoc.v:175219$9849 + assign { } { } + assign $0\o[63:0] \o$next + sync posedge \coresync_clk + update \o $0\o[63:0] + end + attribute \src "libresoc.v:175221.3-175222.25" + process $proc$libresoc.v:175221$9850 + assign { } { } + assign $0\o_ok[0:0] \o_ok$next + sync posedge \coresync_clk + update \o_ok $0\o_ok[0:0] + end + attribute \src "libresoc.v:175223.3-175224.65" + process $proc$libresoc.v:175223$9851 + assign { } { } + assign $0\logical_op__insn_type$2[6:0]$9852 \logical_op__insn_type$2$next + sync posedge \coresync_clk + update \logical_op__insn_type$2 $0\logical_op__insn_type$2[6:0]$9852 + end + attribute \src "libresoc.v:175225.3-175226.61" + process $proc$libresoc.v:175225$9853 + assign { } { } + assign $0\logical_op__fn_unit$3[12:0]$9854 \logical_op__fn_unit$3$next + sync posedge \coresync_clk + update \logical_op__fn_unit$3 $0\logical_op__fn_unit$3[12:0]$9854 + end + attribute \src "libresoc.v:175227.3-175228.75" + process $proc$libresoc.v:175227$9855 + assign { } { } + assign $0\logical_op__imm_data__data$4[63:0]$9856 \logical_op__imm_data__data$4$next + sync posedge \coresync_clk + update \logical_op__imm_data__data$4 $0\logical_op__imm_data__data$4[63:0]$9856 + end + attribute \src "libresoc.v:175229.3-175230.71" + process $proc$libresoc.v:175229$9857 + assign { } { } + assign $0\logical_op__imm_data__ok$5[0:0]$9858 \logical_op__imm_data__ok$5$next + sync posedge \coresync_clk + update \logical_op__imm_data__ok$5 $0\logical_op__imm_data__ok$5[0:0]$9858 + end + attribute \src "libresoc.v:175231.3-175232.59" + process $proc$libresoc.v:175231$9859 + assign { } { } + assign $0\logical_op__rc__rc$6[0:0]$9860 \logical_op__rc__rc$6$next + sync posedge \coresync_clk + update \logical_op__rc__rc$6 $0\logical_op__rc__rc$6[0:0]$9860 + end + attribute \src "libresoc.v:175233.3-175234.59" + process $proc$libresoc.v:175233$9861 + assign { } { } + assign $0\logical_op__rc__ok$7[0:0]$9862 \logical_op__rc__ok$7$next + sync posedge \coresync_clk + update \logical_op__rc__ok$7 $0\logical_op__rc__ok$7[0:0]$9862 + end + attribute \src "libresoc.v:175235.3-175236.59" + process $proc$libresoc.v:175235$9863 + assign { } { } + assign $0\logical_op__oe__oe$8[0:0]$9864 \logical_op__oe__oe$8$next + sync posedge \coresync_clk + update \logical_op__oe__oe$8 $0\logical_op__oe__oe$8[0:0]$9864 + end + attribute \src "libresoc.v:175237.3-175238.59" + process $proc$libresoc.v:175237$9865 + assign { } { } + assign $0\logical_op__oe__ok$9[0:0]$9866 \logical_op__oe__ok$9$next + sync posedge \coresync_clk + update \logical_op__oe__ok$9 $0\logical_op__oe__ok$9[0:0]$9866 + end + attribute \src "libresoc.v:175239.3-175240.67" + process $proc$libresoc.v:175239$9867 + assign { } { } + assign $0\logical_op__invert_in$10[0:0]$9868 \logical_op__invert_in$10$next + sync posedge \coresync_clk + update \logical_op__invert_in$10 $0\logical_op__invert_in$10[0:0]$9868 + end + attribute \src "libresoc.v:175241.3-175242.61" + process $proc$libresoc.v:175241$9869 + assign { } { } + assign $0\logical_op__zero_a$11[0:0]$9870 \logical_op__zero_a$11$next + sync posedge \coresync_clk + update \logical_op__zero_a$11 $0\logical_op__zero_a$11[0:0]$9870 + end + attribute \src "libresoc.v:175243.3-175244.71" + process $proc$libresoc.v:175243$9871 + assign { } { } + assign $0\logical_op__input_carry$12[1:0]$9872 \logical_op__input_carry$12$next + sync posedge \coresync_clk + update \logical_op__input_carry$12 $0\logical_op__input_carry$12[1:0]$9872 + end + attribute \src "libresoc.v:175245.3-175246.69" + process $proc$libresoc.v:175245$9873 + assign { } { } + assign $0\logical_op__invert_out$13[0:0]$9874 \logical_op__invert_out$13$next + sync posedge \coresync_clk + update \logical_op__invert_out$13 $0\logical_op__invert_out$13[0:0]$9874 + end + attribute \src "libresoc.v:175247.3-175248.67" + process $proc$libresoc.v:175247$9875 + assign { } { } + assign $0\logical_op__write_cr0$14[0:0]$9876 \logical_op__write_cr0$14$next + sync posedge \coresync_clk + update \logical_op__write_cr0$14 $0\logical_op__write_cr0$14[0:0]$9876 + end + attribute \src "libresoc.v:175249.3-175250.73" + process $proc$libresoc.v:175249$9877 + assign { } { } + assign $0\logical_op__output_carry$15[0:0]$9878 \logical_op__output_carry$15$next + sync posedge \coresync_clk + update \logical_op__output_carry$15 $0\logical_op__output_carry$15[0:0]$9878 + end + attribute \src "libresoc.v:175251.3-175252.65" + process $proc$libresoc.v:175251$9879 + assign { } { } + assign $0\logical_op__is_32bit$16[0:0]$9880 \logical_op__is_32bit$16$next + sync posedge \coresync_clk + update \logical_op__is_32bit$16 $0\logical_op__is_32bit$16[0:0]$9880 + end + attribute \src "libresoc.v:175253.3-175254.67" + process $proc$libresoc.v:175253$9881 + assign { } { } + assign $0\logical_op__is_signed$17[0:0]$9882 \logical_op__is_signed$17$next + sync posedge \coresync_clk + update \logical_op__is_signed$17 $0\logical_op__is_signed$17[0:0]$9882 + end + attribute \src "libresoc.v:175255.3-175256.65" + process $proc$libresoc.v:175255$9883 + assign { } { } + assign $0\logical_op__data_len$18[3:0]$9884 \logical_op__data_len$18$next + sync posedge \coresync_clk + update \logical_op__data_len$18 $0\logical_op__data_len$18[3:0]$9884 + end + attribute \src "libresoc.v:175257.3-175258.57" + process $proc$libresoc.v:175257$9885 + assign { } { } + assign $0\logical_op__insn$19[31:0]$9886 \logical_op__insn$19$next + sync posedge \coresync_clk + update \logical_op__insn$19 $0\logical_op__insn$19[31:0]$9886 + end + attribute \src "libresoc.v:175259.3-175260.33" + process $proc$libresoc.v:175259$9887 + assign { } { } + assign $0\muxid$1[1:0]$9888 \muxid$1$next + sync posedge \coresync_clk + update \muxid$1 $0\muxid$1[1:0]$9888 + end + attribute \src "libresoc.v:175261.3-175262.29" + process $proc$libresoc.v:175261$9889 + assign { } { } + assign $0\r_busy[0:0] \r_busy$next + sync posedge \coresync_clk + update \r_busy $0\r_busy[0:0] + end + attribute \src "libresoc.v:175377.3-175395.6" + process $proc$libresoc.v:175377$9890 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\o$next[63:0]$9891 $1\o$next[63:0]$9893 + assign { } { } + assign $0\o_ok$next[0:0]$9892 $2\o_ok$next[0:0]$9895 + attribute \src "libresoc.v:175378.5-175378.29" + switch \initial + attribute \src "libresoc.v:175378.9-175378.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\o_ok$next[0:0]$9894 $1\o$next[63:0]$9893 } { \o_ok$96 \o$95 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\o_ok$next[0:0]$9894 $1\o$next[63:0]$9893 } { \o_ok$96 \o$95 } + case + assign $1\o$next[63:0]$9893 \o + assign $1\o_ok$next[0:0]$9894 \o_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\o_ok$next[0:0]$9895 1'0 + case + assign $2\o_ok$next[0:0]$9895 $1\o_ok$next[0:0]$9894 + end + sync always + update \o$next $0\o$next[63:0]$9891 + update \o_ok$next $0\o_ok$next[0:0]$9892 + end + attribute \src "libresoc.v:175396.3-175414.6" + process $proc$libresoc.v:175396$9896 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\cr_a$next[3:0]$9897 $1\cr_a$next[3:0]$9899 + assign { } { } + assign $0\cr_a_ok$next[0:0]$9898 $2\cr_a_ok$next[0:0]$9901 + attribute \src "libresoc.v:175397.5-175397.29" + switch \initial + attribute \src "libresoc.v:175397.9-175397.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\cr_a_ok$next[0:0]$9900 $1\cr_a$next[3:0]$9899 } { \cr_a_ok$98 \cr_a$97 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\cr_a_ok$next[0:0]$9900 $1\cr_a$next[3:0]$9899 } { \cr_a_ok$98 \cr_a$97 } + case + assign $1\cr_a$next[3:0]$9899 \cr_a + assign $1\cr_a_ok$next[0:0]$9900 \cr_a_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_a_ok$next[0:0]$9901 1'0 + case + assign $2\cr_a_ok$next[0:0]$9901 $1\cr_a_ok$next[0:0]$9900 + end + sync always + update \cr_a$next $0\cr_a$next[3:0]$9897 + update \cr_a_ok$next $0\cr_a_ok$next[0:0]$9898 + end + attribute \src "libresoc.v:175415.3-175433.6" + process $proc$libresoc.v:175415$9902 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\xer_ov$next[1:0]$9903 $1\xer_ov$next[1:0]$9905 + assign { } { } + assign $0\xer_ov_ok$next[0:0]$9904 $2\xer_ov_ok$next[0:0]$9907 + attribute \src "libresoc.v:175416.5-175416.29" + switch \initial + attribute \src "libresoc.v:175416.9-175416.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\xer_ov_ok$next[0:0]$9906 $1\xer_ov$next[1:0]$9905 } { \xer_ov_ok$100 \xer_ov$99 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\xer_ov_ok$next[0:0]$9906 $1\xer_ov$next[1:0]$9905 } { \xer_ov_ok$100 \xer_ov$99 } + case + assign $1\xer_ov$next[1:0]$9905 \xer_ov + assign $1\xer_ov_ok$next[0:0]$9906 \xer_ov_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\xer_ov_ok$next[0:0]$9907 1'0 + case + assign $2\xer_ov_ok$next[0:0]$9907 $1\xer_ov_ok$next[0:0]$9906 + end + sync always + update \xer_ov$next $0\xer_ov$next[1:0]$9903 + update \xer_ov_ok$next $0\xer_ov_ok$next[0:0]$9904 + end + attribute \src "libresoc.v:175434.3-175452.6" + process $proc$libresoc.v:175434$9908 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\xer_so$20$next[0:0]$9910 $1\xer_so$20$next[0:0]$9912 + assign $0\xer_so_ok$next[0:0]$9909 $2\xer_so_ok$next[0:0]$9913 + attribute \src "libresoc.v:175435.5-175435.29" + switch \initial + attribute \src "libresoc.v:175435.9-175435.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\xer_so_ok$next[0:0]$9911 $1\xer_so$20$next[0:0]$9912 } { \xer_so_ok$102 \xer_so$101 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\xer_so_ok$next[0:0]$9911 $1\xer_so$20$next[0:0]$9912 } { \xer_so_ok$102 \xer_so$101 } + case + assign $1\xer_so_ok$next[0:0]$9911 \xer_so_ok + assign $1\xer_so$20$next[0:0]$9912 \xer_so$20 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\xer_so_ok$next[0:0]$9913 1'0 + case + assign $2\xer_so_ok$next[0:0]$9913 $1\xer_so_ok$next[0:0]$9911 + end + sync always + update \xer_so_ok$next $0\xer_so_ok$next[0:0]$9909 + update \xer_so$20$next $0\xer_so$20$next[0:0]$9910 + end + attribute \src "libresoc.v:175453.3-175470.6" + process $proc$libresoc.v:175453$9914 + assign { } { } + assign { } { } + assign { } { } + assign $0\r_busy$next[0:0]$9915 $2\r_busy$next[0:0]$9917 + attribute \src "libresoc.v:175454.5-175454.29" + switch \initial + attribute \src "libresoc.v:175454.9-175454.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\r_busy$next[0:0]$9916 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\r_busy$next[0:0]$9916 1'0 + case + assign $1\r_busy$next[0:0]$9916 \r_busy + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r_busy$next[0:0]$9917 1'0 + case + assign $2\r_busy$next[0:0]$9917 $1\r_busy$next[0:0]$9916 + end + sync always + update \r_busy$next $0\r_busy$next[0:0]$9915 + end + attribute \src "libresoc.v:175471.3-175483.6" + process $proc$libresoc.v:175471$9918 + assign { } { } + assign { } { } + assign $0\muxid$1$next[1:0]$9919 $1\muxid$1$next[1:0]$9920 + attribute \src "libresoc.v:175472.5-175472.29" + switch \initial + attribute \src "libresoc.v:175472.9-175472.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\muxid$1$next[1:0]$9920 \muxid$76 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\muxid$1$next[1:0]$9920 \muxid$76 + case + assign $1\muxid$1$next[1:0]$9920 \muxid$1 + end + sync always + update \muxid$1$next $0\muxid$1$next[1:0]$9919 + end + attribute \src "libresoc.v:175484.3-175525.6" + process $proc$libresoc.v:175484$9921 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\logical_op__data_len$18$next[3:0]$9922 $1\logical_op__data_len$18$next[3:0]$9940 + assign $0\logical_op__fn_unit$3$next[12:0]$9923 $1\logical_op__fn_unit$3$next[12:0]$9941 + assign { } { } + assign { } { } + assign $0\logical_op__input_carry$12$next[1:0]$9926 $1\logical_op__input_carry$12$next[1:0]$9944 + assign $0\logical_op__insn$19$next[31:0]$9927 $1\logical_op__insn$19$next[31:0]$9945 + assign $0\logical_op__insn_type$2$next[6:0]$9928 $1\logical_op__insn_type$2$next[6:0]$9946 + assign $0\logical_op__invert_in$10$next[0:0]$9929 $1\logical_op__invert_in$10$next[0:0]$9947 + assign $0\logical_op__invert_out$13$next[0:0]$9930 $1\logical_op__invert_out$13$next[0:0]$9948 + assign $0\logical_op__is_32bit$16$next[0:0]$9931 $1\logical_op__is_32bit$16$next[0:0]$9949 + assign $0\logical_op__is_signed$17$next[0:0]$9932 $1\logical_op__is_signed$17$next[0:0]$9950 + assign { } { } + assign { } { } + assign $0\logical_op__output_carry$15$next[0:0]$9935 $1\logical_op__output_carry$15$next[0:0]$9953 + assign { } { } + assign { } { } + assign $0\logical_op__write_cr0$14$next[0:0]$9938 $1\logical_op__write_cr0$14$next[0:0]$9956 + assign $0\logical_op__zero_a$11$next[0:0]$9939 $1\logical_op__zero_a$11$next[0:0]$9957 + assign $0\logical_op__imm_data__data$4$next[63:0]$9924 $2\logical_op__imm_data__data$4$next[63:0]$9958 + assign $0\logical_op__imm_data__ok$5$next[0:0]$9925 $2\logical_op__imm_data__ok$5$next[0:0]$9959 + assign $0\logical_op__oe__oe$8$next[0:0]$9933 $2\logical_op__oe__oe$8$next[0:0]$9960 + assign $0\logical_op__oe__ok$9$next[0:0]$9934 $2\logical_op__oe__ok$9$next[0:0]$9961 + assign $0\logical_op__rc__ok$7$next[0:0]$9936 $2\logical_op__rc__ok$7$next[0:0]$9962 + assign $0\logical_op__rc__rc$6$next[0:0]$9937 $2\logical_op__rc__rc$6$next[0:0]$9963 + attribute \src "libresoc.v:175485.5-175485.29" + switch \initial + attribute \src "libresoc.v:175485.9-175485.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\logical_op__insn$19$next[31:0]$9945 $1\logical_op__data_len$18$next[3:0]$9940 $1\logical_op__is_signed$17$next[0:0]$9950 $1\logical_op__is_32bit$16$next[0:0]$9949 $1\logical_op__output_carry$15$next[0:0]$9953 $1\logical_op__write_cr0$14$next[0:0]$9956 $1\logical_op__invert_out$13$next[0:0]$9948 $1\logical_op__input_carry$12$next[1:0]$9944 $1\logical_op__zero_a$11$next[0:0]$9957 $1\logical_op__invert_in$10$next[0:0]$9947 $1\logical_op__oe__ok$9$next[0:0]$9952 $1\logical_op__oe__oe$8$next[0:0]$9951 $1\logical_op__rc__ok$7$next[0:0]$9954 $1\logical_op__rc__rc$6$next[0:0]$9955 $1\logical_op__imm_data__ok$5$next[0:0]$9943 $1\logical_op__imm_data__data$4$next[63:0]$9942 $1\logical_op__fn_unit$3$next[12:0]$9941 $1\logical_op__insn_type$2$next[6:0]$9946 } { \logical_op__insn$94 \logical_op__data_len$93 \logical_op__is_signed$92 \logical_op__is_32bit$91 \logical_op__output_carry$90 \logical_op__write_cr0$89 \logical_op__invert_out$88 \logical_op__input_carry$87 \logical_op__zero_a$86 \logical_op__invert_in$85 \logical_op__oe__ok$84 \logical_op__oe__oe$83 \logical_op__rc__ok$82 \logical_op__rc__rc$81 \logical_op__imm_data__ok$80 \logical_op__imm_data__data$79 \logical_op__fn_unit$78 \logical_op__insn_type$77 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\logical_op__insn$19$next[31:0]$9945 $1\logical_op__data_len$18$next[3:0]$9940 $1\logical_op__is_signed$17$next[0:0]$9950 $1\logical_op__is_32bit$16$next[0:0]$9949 $1\logical_op__output_carry$15$next[0:0]$9953 $1\logical_op__write_cr0$14$next[0:0]$9956 $1\logical_op__invert_out$13$next[0:0]$9948 $1\logical_op__input_carry$12$next[1:0]$9944 $1\logical_op__zero_a$11$next[0:0]$9957 $1\logical_op__invert_in$10$next[0:0]$9947 $1\logical_op__oe__ok$9$next[0:0]$9952 $1\logical_op__oe__oe$8$next[0:0]$9951 $1\logical_op__rc__ok$7$next[0:0]$9954 $1\logical_op__rc__rc$6$next[0:0]$9955 $1\logical_op__imm_data__ok$5$next[0:0]$9943 $1\logical_op__imm_data__data$4$next[63:0]$9942 $1\logical_op__fn_unit$3$next[12:0]$9941 $1\logical_op__insn_type$2$next[6:0]$9946 } { \logical_op__insn$94 \logical_op__data_len$93 \logical_op__is_signed$92 \logical_op__is_32bit$91 \logical_op__output_carry$90 \logical_op__write_cr0$89 \logical_op__invert_out$88 \logical_op__input_carry$87 \logical_op__zero_a$86 \logical_op__invert_in$85 \logical_op__oe__ok$84 \logical_op__oe__oe$83 \logical_op__rc__ok$82 \logical_op__rc__rc$81 \logical_op__imm_data__ok$80 \logical_op__imm_data__data$79 \logical_op__fn_unit$78 \logical_op__insn_type$77 } + case + assign $1\logical_op__data_len$18$next[3:0]$9940 \logical_op__data_len$18 + assign $1\logical_op__fn_unit$3$next[12:0]$9941 \logical_op__fn_unit$3 + assign $1\logical_op__imm_data__data$4$next[63:0]$9942 \logical_op__imm_data__data$4 + assign $1\logical_op__imm_data__ok$5$next[0:0]$9943 \logical_op__imm_data__ok$5 + assign $1\logical_op__input_carry$12$next[1:0]$9944 \logical_op__input_carry$12 + assign $1\logical_op__insn$19$next[31:0]$9945 \logical_op__insn$19 + assign $1\logical_op__insn_type$2$next[6:0]$9946 \logical_op__insn_type$2 + assign $1\logical_op__invert_in$10$next[0:0]$9947 \logical_op__invert_in$10 + assign $1\logical_op__invert_out$13$next[0:0]$9948 \logical_op__invert_out$13 + assign $1\logical_op__is_32bit$16$next[0:0]$9949 \logical_op__is_32bit$16 + assign $1\logical_op__is_signed$17$next[0:0]$9950 \logical_op__is_signed$17 + assign $1\logical_op__oe__oe$8$next[0:0]$9951 \logical_op__oe__oe$8 + assign $1\logical_op__oe__ok$9$next[0:0]$9952 \logical_op__oe__ok$9 + assign $1\logical_op__output_carry$15$next[0:0]$9953 \logical_op__output_carry$15 + assign $1\logical_op__rc__ok$7$next[0:0]$9954 \logical_op__rc__ok$7 + assign $1\logical_op__rc__rc$6$next[0:0]$9955 \logical_op__rc__rc$6 + assign $1\logical_op__write_cr0$14$next[0:0]$9956 \logical_op__write_cr0$14 + assign $1\logical_op__zero_a$11$next[0:0]$9957 \logical_op__zero_a$11 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $2\logical_op__imm_data__data$4$next[63:0]$9958 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\logical_op__imm_data__ok$5$next[0:0]$9959 1'0 + assign $2\logical_op__rc__rc$6$next[0:0]$9963 1'0 + assign $2\logical_op__rc__ok$7$next[0:0]$9962 1'0 + assign $2\logical_op__oe__oe$8$next[0:0]$9960 1'0 + assign $2\logical_op__oe__ok$9$next[0:0]$9961 1'0 + case + assign $2\logical_op__imm_data__data$4$next[63:0]$9958 $1\logical_op__imm_data__data$4$next[63:0]$9942 + assign $2\logical_op__imm_data__ok$5$next[0:0]$9959 $1\logical_op__imm_data__ok$5$next[0:0]$9943 + assign $2\logical_op__oe__oe$8$next[0:0]$9960 $1\logical_op__oe__oe$8$next[0:0]$9951 + assign $2\logical_op__oe__ok$9$next[0:0]$9961 $1\logical_op__oe__ok$9$next[0:0]$9952 + assign $2\logical_op__rc__ok$7$next[0:0]$9962 $1\logical_op__rc__ok$7$next[0:0]$9954 + assign $2\logical_op__rc__rc$6$next[0:0]$9963 $1\logical_op__rc__rc$6$next[0:0]$9955 + end + sync always + update \logical_op__data_len$18$next $0\logical_op__data_len$18$next[3:0]$9922 + update \logical_op__fn_unit$3$next $0\logical_op__fn_unit$3$next[12:0]$9923 + update \logical_op__imm_data__data$4$next $0\logical_op__imm_data__data$4$next[63:0]$9924 + update \logical_op__imm_data__ok$5$next $0\logical_op__imm_data__ok$5$next[0:0]$9925 + update \logical_op__input_carry$12$next $0\logical_op__input_carry$12$next[1:0]$9926 + update \logical_op__insn$19$next $0\logical_op__insn$19$next[31:0]$9927 + update \logical_op__insn_type$2$next $0\logical_op__insn_type$2$next[6:0]$9928 + update \logical_op__invert_in$10$next $0\logical_op__invert_in$10$next[0:0]$9929 + update \logical_op__invert_out$13$next $0\logical_op__invert_out$13$next[0:0]$9930 + update \logical_op__is_32bit$16$next $0\logical_op__is_32bit$16$next[0:0]$9931 + update \logical_op__is_signed$17$next $0\logical_op__is_signed$17$next[0:0]$9932 + update \logical_op__oe__oe$8$next $0\logical_op__oe__oe$8$next[0:0]$9933 + update \logical_op__oe__ok$9$next $0\logical_op__oe__ok$9$next[0:0]$9934 + update \logical_op__output_carry$15$next $0\logical_op__output_carry$15$next[0:0]$9935 + update \logical_op__rc__ok$7$next $0\logical_op__rc__ok$7$next[0:0]$9936 + update \logical_op__rc__rc$6$next $0\logical_op__rc__rc$6$next[0:0]$9937 + update \logical_op__write_cr0$14$next $0\logical_op__write_cr0$14$next[0:0]$9938 + update \logical_op__zero_a$11$next $0\logical_op__zero_a$11$next[0:0]$9939 + end + connect \$74 $and$libresoc.v:175206$9841_Y + connect \cr_a$68 4'0000 + connect \cr_a_ok$69 1'0 + connect \xer_so_ok$72 1'0 + connect \p_ready_o \n_i_rdy_data + connect \n_valid_o \r_busy + connect { \xer_so_ok$102 \xer_so$101 } { \output_xer_so_ok \output_xer_so$64 } + connect { \xer_ov_ok$100 \xer_ov$99 } { \output_xer_ov_ok \output_xer_ov$63 } + connect { \cr_a_ok$98 \cr_a$97 } { \output_cr_a_ok \output_cr_a$62 } + connect { \o_ok$96 \o$95 } { \output_o_ok$61 \output_o$60 } + connect { \logical_op__insn$94 \logical_op__data_len$93 \logical_op__is_signed$92 \logical_op__is_32bit$91 \logical_op__output_carry$90 \logical_op__write_cr0$89 \logical_op__invert_out$88 \logical_op__input_carry$87 \logical_op__zero_a$86 \logical_op__invert_in$85 \logical_op__oe__ok$84 \logical_op__oe__oe$83 \logical_op__rc__ok$82 \logical_op__rc__rc$81 \logical_op__imm_data__ok$80 \logical_op__imm_data__data$79 \logical_op__fn_unit$78 \logical_op__insn_type$77 } { \output_logical_op__insn$59 \output_logical_op__data_len$58 \output_logical_op__is_signed$57 \output_logical_op__is_32bit$56 \output_logical_op__output_carry$55 \output_logical_op__write_cr0$54 \output_logical_op__invert_out$53 \output_logical_op__input_carry$52 \output_logical_op__zero_a$51 \output_logical_op__invert_in$50 \output_logical_op__oe__ok$49 \output_logical_op__oe__oe$48 \output_logical_op__rc__ok$47 \output_logical_op__rc__rc$46 \output_logical_op__imm_data__ok$45 \output_logical_op__imm_data__data$44 \output_logical_op__fn_unit$43 \output_logical_op__insn_type$42 } + connect \muxid$76 \output_muxid$41 + connect \p_valid_i_p_ready_o \$74 + connect \n_i_rdy_data \n_ready_i + connect \p_valid_i$73 \p_valid_i + connect { \xer_so_ok$71 \output_xer_so } { 1'0 \output_stage_xer_so$40 } + connect { \xer_ov_ok$70 \output_xer_ov } { \output_stage_xer_ov_ok \output_stage_xer_ov } + connect { \cr_a_ok$67 \output_cr_a } 5'00000 + connect { \output_o_ok \output_o } { \output_stage_o_ok \output_stage_o } + connect { \output_logical_op__insn \output_logical_op__data_len \output_logical_op__is_signed \output_logical_op__is_32bit \output_logical_op__output_carry \output_logical_op__write_cr0 \output_logical_op__invert_out \output_logical_op__input_carry \output_logical_op__zero_a \output_logical_op__invert_in \output_logical_op__oe__ok \output_logical_op__oe__oe \output_logical_op__rc__ok \output_logical_op__rc__rc \output_logical_op__imm_data__ok \output_logical_op__imm_data__data \output_logical_op__fn_unit \output_logical_op__insn_type } { \output_stage_logical_op__insn$39 \output_stage_logical_op__data_len$38 \output_stage_logical_op__is_signed$37 \output_stage_logical_op__is_32bit$36 \output_stage_logical_op__output_carry$35 \output_stage_logical_op__write_cr0$34 \output_stage_logical_op__invert_out$33 \output_stage_logical_op__input_carry$32 \output_stage_logical_op__zero_a$31 \output_stage_logical_op__invert_in$30 \output_stage_logical_op__oe__ok$29 \output_stage_logical_op__oe__oe$28 \output_stage_logical_op__rc__ok$27 \output_stage_logical_op__rc__rc$26 \output_stage_logical_op__imm_data__ok$25 \output_stage_logical_op__imm_data__data$24 \output_stage_logical_op__fn_unit$23 \output_stage_logical_op__insn_type$22 } + connect \output_muxid \output_stage_muxid$21 + connect \output_stage_remainder \remainder + connect \output_stage_quotient_root \quotient_root + connect \output_stage_div_by_zero \div_by_zero + connect \output_stage_dive_abs_ov64 \dive_abs_ov64 + connect \output_stage_dive_abs_ov32 \dive_abs_ov32 + connect \output_stage_dividend_neg \dividend_neg + connect \output_stage_divisor_neg \divisor_neg + connect \output_stage_xer_so \xer_so + connect \rb$66 \rb + connect \ra$65 \ra + connect { \output_stage_logical_op__insn \output_stage_logical_op__data_len \output_stage_logical_op__is_signed \output_stage_logical_op__is_32bit \output_stage_logical_op__output_carry \output_stage_logical_op__write_cr0 \output_stage_logical_op__invert_out \output_stage_logical_op__input_carry \output_stage_logical_op__zero_a \output_stage_logical_op__invert_in \output_stage_logical_op__oe__ok \output_stage_logical_op__oe__oe \output_stage_logical_op__rc__ok \output_stage_logical_op__rc__rc \output_stage_logical_op__imm_data__ok \output_stage_logical_op__imm_data__data \output_stage_logical_op__fn_unit \output_stage_logical_op__insn_type } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } + connect \output_stage_muxid \muxid +end +attribute \src "libresoc.v:175562.1-176543.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_middle_0" +attribute \generator "nMigen" +module \pipe_middle_0 + attribute \src "libresoc.v:176468.3-176482.6" + wire $0\div_by_zero$54$next[0:0]$10192 + attribute \src "libresoc.v:176142.3-176143.47" + wire $0\div_by_zero$54[0:0]$10027 + attribute \src "libresoc.v:175585.7-175585.30" + wire $0\div_by_zero$54[0:0]$10209 + attribute \src "libresoc.v:176264.3-176275.6" + wire width 64 $0\div_state_next_divisor[63:0] + attribute \src "libresoc.v:176252.3-176263.6" + wire width 128 $0\div_state_next_i_dividend_quotient[127:0] + attribute \src "libresoc.v:176240.3-176251.6" + wire width 7 $0\div_state_next_i_q_bits_known[6:0] + attribute \src "libresoc.v:176438.3-176452.6" + wire $0\dive_abs_ov32$52$next[0:0]$10184 + attribute \src "libresoc.v:176146.3-176147.51" + wire $0\dive_abs_ov32$52[0:0]$10031 + attribute \src "libresoc.v:175609.7-175609.32" + wire $0\dive_abs_ov32$52[0:0]$10211 + attribute \src "libresoc.v:176453.3-176467.6" + wire $0\dive_abs_ov64$53$next[0:0]$10188 + attribute \src "libresoc.v:176144.3-176145.51" + wire $0\dive_abs_ov64$53[0:0]$10029 + attribute \src "libresoc.v:175617.7-175617.32" + wire $0\dive_abs_ov64$53[0:0]$10213 + attribute \src "libresoc.v:176483.3-176497.6" + wire width 128 $0\dividend$68$next[127:0]$10196 + attribute \src "libresoc.v:176140.3-176141.41" + wire width 128 $0\dividend$68[127:0]$10025 + attribute \src "libresoc.v:175623.15-175623.68" + wire width 128 $0\dividend$68[127:0]$10215 + attribute \src "libresoc.v:176423.3-176437.6" + wire $0\dividend_neg$51$next[0:0]$10180 + attribute \src "libresoc.v:176148.3-176149.49" + wire $0\dividend_neg$51[0:0]$10033 + attribute \src "libresoc.v:175631.7-175631.31" + wire $0\dividend_neg$51[0:0]$10217 + attribute \src "libresoc.v:176408.3-176422.6" + wire $0\divisor_neg$50$next[0:0]$10176 + attribute \src "libresoc.v:176150.3-176151.47" + wire $0\divisor_neg$50[0:0]$10035 + attribute \src "libresoc.v:175639.7-175639.30" + wire $0\divisor_neg$50[0:0]$10219 + attribute \src "libresoc.v:176498.3-176512.6" + wire width 64 $0\divisor_radicand$65$next[63:0]$10200 + attribute \src "libresoc.v:176138.3-176139.57" + wire width 64 $0\divisor_radicand$65[63:0]$10023 + attribute \src "libresoc.v:175645.14-175645.58" + wire width 64 $0\divisor_radicand$65[63:0]$10221 + attribute \src "libresoc.v:176276.3-176303.6" + wire $0\empty$next[0:0]$10093 + attribute \src "libresoc.v:176196.3-176197.27" + wire $0\empty[0:0] + attribute \src "libresoc.v:175563.7-175563.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:176319.3-176362.6" + wire width 4 $0\logical_op__data_len$45$next[3:0]$10103 + attribute \src "libresoc.v:176190.3-176191.65" + wire width 4 $0\logical_op__data_len$45[3:0]$10075 + attribute \src "libresoc.v:175657.13-175657.45" + wire width 4 $0\logical_op__data_len$45[3:0]$10224 + attribute \src "libresoc.v:176319.3-176362.6" + wire width 13 $0\logical_op__fn_unit$30$next[12:0]$10104 + attribute \src "libresoc.v:176160.3-176161.63" + wire width 13 $0\logical_op__fn_unit$30[12:0]$10045 + attribute \src "libresoc.v:175707.14-175707.49" + wire width 13 $0\logical_op__fn_unit$30[12:0]$10226 + attribute \src "libresoc.v:176319.3-176362.6" + wire width 64 $0\logical_op__imm_data__data$31$next[63:0]$10105 + attribute \src "libresoc.v:176162.3-176163.77" + wire width 64 $0\logical_op__imm_data__data$31[63:0]$10047 + attribute \src "libresoc.v:175713.14-175713.68" + wire width 64 $0\logical_op__imm_data__data$31[63:0]$10228 + attribute \src "libresoc.v:176319.3-176362.6" + wire $0\logical_op__imm_data__ok$32$next[0:0]$10106 + attribute \src "libresoc.v:176164.3-176165.73" + wire $0\logical_op__imm_data__ok$32[0:0]$10049 + attribute \src "libresoc.v:175721.7-175721.43" + wire $0\logical_op__imm_data__ok$32[0:0]$10230 + attribute \src "libresoc.v:176319.3-176362.6" + wire width 2 $0\logical_op__input_carry$39$next[1:0]$10107 + attribute \src "libresoc.v:176178.3-176179.71" + wire width 2 $0\logical_op__input_carry$39[1:0]$10063 + attribute \src "libresoc.v:175743.13-175743.48" + wire width 2 $0\logical_op__input_carry$39[1:0]$10232 + attribute \src "libresoc.v:176319.3-176362.6" + wire width 32 $0\logical_op__insn$46$next[31:0]$10108 + attribute \src "libresoc.v:176192.3-176193.57" + wire width 32 $0\logical_op__insn$46[31:0]$10077 + attribute \src "libresoc.v:175751.14-175751.43" + wire width 32 $0\logical_op__insn$46[31:0]$10234 + attribute \src "libresoc.v:176319.3-176362.6" + wire width 7 $0\logical_op__insn_type$29$next[6:0]$10109 + attribute \src "libresoc.v:176158.3-176159.67" + wire width 7 $0\logical_op__insn_type$29[6:0]$10043 + attribute \src "libresoc.v:175981.13-175981.47" + wire width 7 $0\logical_op__insn_type$29[6:0]$10236 + attribute \src "libresoc.v:176319.3-176362.6" + wire $0\logical_op__invert_in$37$next[0:0]$10110 + attribute \src "libresoc.v:176174.3-176175.67" + wire $0\logical_op__invert_in$37[0:0]$10059 + attribute \src "libresoc.v:175989.7-175989.40" + wire $0\logical_op__invert_in$37[0:0]$10238 + attribute \src "libresoc.v:176319.3-176362.6" + wire $0\logical_op__invert_out$40$next[0:0]$10111 + attribute \src "libresoc.v:176180.3-176181.69" + wire $0\logical_op__invert_out$40[0:0]$10065 + attribute \src "libresoc.v:175997.7-175997.41" + wire $0\logical_op__invert_out$40[0:0]$10240 + attribute \src "libresoc.v:176319.3-176362.6" + wire $0\logical_op__is_32bit$43$next[0:0]$10112 + attribute \src "libresoc.v:176186.3-176187.65" + wire $0\logical_op__is_32bit$43[0:0]$10071 + attribute \src "libresoc.v:176005.7-176005.39" + wire $0\logical_op__is_32bit$43[0:0]$10242 + attribute \src "libresoc.v:176319.3-176362.6" + wire $0\logical_op__is_signed$44$next[0:0]$10113 + attribute \src "libresoc.v:176188.3-176189.67" + wire $0\logical_op__is_signed$44[0:0]$10073 + attribute \src "libresoc.v:176013.7-176013.40" + wire $0\logical_op__is_signed$44[0:0]$10244 + attribute \src "libresoc.v:176319.3-176362.6" + wire $0\logical_op__oe__oe$35$next[0:0]$10114 + attribute \src "libresoc.v:176170.3-176171.61" + wire $0\logical_op__oe__oe$35[0:0]$10055 + attribute \src "libresoc.v:176019.7-176019.37" + wire $0\logical_op__oe__oe$35[0:0]$10246 + attribute \src "libresoc.v:176319.3-176362.6" + wire $0\logical_op__oe__ok$36$next[0:0]$10115 + attribute \src "libresoc.v:176172.3-176173.61" + wire $0\logical_op__oe__ok$36[0:0]$10057 + attribute \src "libresoc.v:176027.7-176027.37" + wire $0\logical_op__oe__ok$36[0:0]$10248 + attribute \src "libresoc.v:176319.3-176362.6" + wire $0\logical_op__output_carry$42$next[0:0]$10116 + attribute \src "libresoc.v:176184.3-176185.73" + wire $0\logical_op__output_carry$42[0:0]$10069 + attribute \src "libresoc.v:176037.7-176037.43" + wire $0\logical_op__output_carry$42[0:0]$10250 + attribute \src "libresoc.v:176319.3-176362.6" + wire $0\logical_op__rc__ok$34$next[0:0]$10117 + attribute \src "libresoc.v:176168.3-176169.61" + wire $0\logical_op__rc__ok$34[0:0]$10053 + attribute \src "libresoc.v:176043.7-176043.37" + wire $0\logical_op__rc__ok$34[0:0]$10252 + attribute \src "libresoc.v:176319.3-176362.6" + wire $0\logical_op__rc__rc$33$next[0:0]$10118 + attribute \src "libresoc.v:176166.3-176167.61" + wire $0\logical_op__rc__rc$33[0:0]$10051 + attribute \src "libresoc.v:176051.7-176051.37" + wire $0\logical_op__rc__rc$33[0:0]$10254 + attribute \src "libresoc.v:176319.3-176362.6" + wire $0\logical_op__write_cr0$41$next[0:0]$10119 + attribute \src "libresoc.v:176182.3-176183.67" + wire $0\logical_op__write_cr0$41[0:0]$10067 + attribute \src "libresoc.v:176061.7-176061.40" + wire $0\logical_op__write_cr0$41[0:0]$10256 + attribute \src "libresoc.v:176319.3-176362.6" + wire $0\logical_op__zero_a$38$next[0:0]$10120 + attribute \src "libresoc.v:176176.3-176177.61" + wire $0\logical_op__zero_a$38[0:0]$10061 + attribute \src "libresoc.v:176069.7-176069.37" + wire $0\logical_op__zero_a$38[0:0]$10258 + attribute \src "libresoc.v:176304.3-176318.6" + wire width 2 $0\muxid$28$next[1:0]$10099 + attribute \src "libresoc.v:176194.3-176195.35" + wire width 2 $0\muxid$28[1:0]$10079 + attribute \src "libresoc.v:176077.13-176077.30" + wire width 2 $0\muxid$28[1:0]$10260 + attribute \src "libresoc.v:176513.3-176527.6" + wire width 2 $0\operation$69$next[1:0]$10204 + attribute \src "libresoc.v:176136.3-176137.43" + wire width 2 $0\operation$69[1:0]$10021 + attribute \src "libresoc.v:176087.13-176087.34" + wire width 2 $0\operation$69[1:0]$10262 + attribute \src "libresoc.v:176363.3-176377.6" + wire width 64 $0\ra$47$next[63:0]$10164 + attribute \src "libresoc.v:176156.3-176157.29" + wire width 64 $0\ra$47[63:0]$10041 + attribute \src "libresoc.v:176101.14-176101.44" + wire width 64 $0\ra$47[63:0]$10264 + attribute \src "libresoc.v:176378.3-176392.6" + wire width 64 $0\rb$48$next[63:0]$10168 + attribute \src "libresoc.v:176154.3-176155.29" + wire width 64 $0\rb$48[63:0]$10039 + attribute \src "libresoc.v:176109.14-176109.44" + wire width 64 $0\rb$48[63:0]$10266 + attribute \src "libresoc.v:176231.3-176239.6" + wire width 128 $0\saved_state_dividend_quotient$next[127:0]$10087 + attribute \src "libresoc.v:176198.3-176199.75" + wire width 128 $0\saved_state_dividend_quotient[127:0] + attribute \src "libresoc.v:176222.3-176230.6" + wire width 7 $0\saved_state_q_bits_known$next[6:0]$10084 + attribute \src "libresoc.v:176200.3-176201.65" + wire width 7 $0\saved_state_q_bits_known[6:0] + attribute \src "libresoc.v:176393.3-176407.6" + wire $0\xer_so$49$next[0:0]$10172 + attribute \src "libresoc.v:176152.3-176153.37" + wire $0\xer_so$49[0:0]$10037 + attribute \src "libresoc.v:176127.7-176127.25" + wire $0\xer_so$49[0:0]$10270 + attribute \src "libresoc.v:176468.3-176482.6" + wire $1\div_by_zero$54$next[0:0]$10193 + attribute \src "libresoc.v:176264.3-176275.6" + wire width 64 $1\div_state_next_divisor[63:0] + attribute \src "libresoc.v:176252.3-176263.6" + wire width 128 $1\div_state_next_i_dividend_quotient[127:0] + attribute \src "libresoc.v:176240.3-176251.6" + wire width 7 $1\div_state_next_i_q_bits_known[6:0] + attribute \src "libresoc.v:176438.3-176452.6" + wire $1\dive_abs_ov32$52$next[0:0]$10185 + attribute \src "libresoc.v:176453.3-176467.6" + wire $1\dive_abs_ov64$53$next[0:0]$10189 + attribute \src "libresoc.v:176483.3-176497.6" + wire width 128 $1\dividend$68$next[127:0]$10197 + attribute \src "libresoc.v:176423.3-176437.6" + wire $1\dividend_neg$51$next[0:0]$10181 + attribute \src "libresoc.v:176408.3-176422.6" + wire $1\divisor_neg$50$next[0:0]$10177 + attribute \src "libresoc.v:176498.3-176512.6" + wire width 64 $1\divisor_radicand$65$next[63:0]$10201 + attribute \src "libresoc.v:176276.3-176303.6" + wire $1\empty$next[0:0]$10094 + attribute \src "libresoc.v:175649.7-175649.19" + wire $1\empty[0:0] + attribute \src "libresoc.v:176319.3-176362.6" + wire width 4 $1\logical_op__data_len$45$next[3:0]$10121 + attribute \src "libresoc.v:176319.3-176362.6" + wire width 13 $1\logical_op__fn_unit$30$next[12:0]$10122 + attribute \src "libresoc.v:176319.3-176362.6" + wire width 64 $1\logical_op__imm_data__data$31$next[63:0]$10123 + attribute \src "libresoc.v:176319.3-176362.6" + wire $1\logical_op__imm_data__ok$32$next[0:0]$10124 + attribute \src "libresoc.v:176319.3-176362.6" + wire width 2 $1\logical_op__input_carry$39$next[1:0]$10125 + attribute \src "libresoc.v:176319.3-176362.6" + wire width 32 $1\logical_op__insn$46$next[31:0]$10126 + attribute \src "libresoc.v:176319.3-176362.6" + wire width 7 $1\logical_op__insn_type$29$next[6:0]$10127 + attribute \src "libresoc.v:176319.3-176362.6" + wire $1\logical_op__invert_in$37$next[0:0]$10128 + attribute \src "libresoc.v:176319.3-176362.6" + wire $1\logical_op__invert_out$40$next[0:0]$10129 + attribute \src "libresoc.v:176319.3-176362.6" + wire $1\logical_op__is_32bit$43$next[0:0]$10130 + attribute \src "libresoc.v:176319.3-176362.6" + wire $1\logical_op__is_signed$44$next[0:0]$10131 + attribute \src "libresoc.v:176319.3-176362.6" + wire $1\logical_op__oe__oe$35$next[0:0]$10132 + attribute \src "libresoc.v:176319.3-176362.6" + wire $1\logical_op__oe__ok$36$next[0:0]$10133 + attribute \src "libresoc.v:176319.3-176362.6" + wire $1\logical_op__output_carry$42$next[0:0]$10134 + attribute \src "libresoc.v:176319.3-176362.6" + wire $1\logical_op__rc__ok$34$next[0:0]$10135 + attribute \src "libresoc.v:176319.3-176362.6" + wire $1\logical_op__rc__rc$33$next[0:0]$10136 + attribute \src "libresoc.v:176319.3-176362.6" + wire $1\logical_op__write_cr0$41$next[0:0]$10137 + attribute \src "libresoc.v:176319.3-176362.6" + wire $1\logical_op__zero_a$38$next[0:0]$10138 + attribute \src "libresoc.v:176304.3-176318.6" + wire width 2 $1\muxid$28$next[1:0]$10100 + attribute \src "libresoc.v:176513.3-176527.6" + wire width 2 $1\operation$69$next[1:0]$10205 + attribute \src "libresoc.v:176363.3-176377.6" + wire width 64 $1\ra$47$next[63:0]$10165 + attribute \src "libresoc.v:176378.3-176392.6" + wire width 64 $1\rb$48$next[63:0]$10169 + attribute \src "libresoc.v:176231.3-176239.6" + wire width 128 $1\saved_state_dividend_quotient$next[127:0]$10088 + attribute \src "libresoc.v:176115.15-176115.84" + wire width 128 $1\saved_state_dividend_quotient[127:0] + attribute \src "libresoc.v:176222.3-176230.6" + wire width 7 $1\saved_state_q_bits_known$next[6:0]$10085 + attribute \src "libresoc.v:176119.13-176119.45" + wire width 7 $1\saved_state_q_bits_known[6:0] + attribute \src "libresoc.v:176393.3-176407.6" + wire $1\xer_so$49$next[0:0]$10173 + attribute \src "libresoc.v:176468.3-176482.6" + wire $2\div_by_zero$54$next[0:0]$10194 + attribute \src "libresoc.v:176438.3-176452.6" + wire $2\dive_abs_ov32$52$next[0:0]$10186 + attribute \src "libresoc.v:176453.3-176467.6" + wire $2\dive_abs_ov64$53$next[0:0]$10190 + attribute \src "libresoc.v:176483.3-176497.6" + wire width 128 $2\dividend$68$next[127:0]$10198 + attribute \src "libresoc.v:176423.3-176437.6" + wire $2\dividend_neg$51$next[0:0]$10182 + attribute \src "libresoc.v:176408.3-176422.6" + wire $2\divisor_neg$50$next[0:0]$10178 + attribute \src "libresoc.v:176498.3-176512.6" + wire width 64 $2\divisor_radicand$65$next[63:0]$10202 + attribute \src "libresoc.v:176276.3-176303.6" + wire $2\empty$next[0:0]$10095 + attribute \src "libresoc.v:176319.3-176362.6" + wire width 4 $2\logical_op__data_len$45$next[3:0]$10139 + attribute \src "libresoc.v:176319.3-176362.6" + wire width 13 $2\logical_op__fn_unit$30$next[12:0]$10140 + attribute \src "libresoc.v:176319.3-176362.6" + wire width 64 $2\logical_op__imm_data__data$31$next[63:0]$10141 + attribute \src "libresoc.v:176319.3-176362.6" + wire $2\logical_op__imm_data__ok$32$next[0:0]$10142 + attribute \src "libresoc.v:176319.3-176362.6" + wire width 2 $2\logical_op__input_carry$39$next[1:0]$10143 + attribute \src "libresoc.v:176319.3-176362.6" + wire width 32 $2\logical_op__insn$46$next[31:0]$10144 + attribute \src "libresoc.v:176319.3-176362.6" + wire width 7 $2\logical_op__insn_type$29$next[6:0]$10145 + attribute \src "libresoc.v:176319.3-176362.6" + wire $2\logical_op__invert_in$37$next[0:0]$10146 + attribute \src "libresoc.v:176319.3-176362.6" + wire $2\logical_op__invert_out$40$next[0:0]$10147 + attribute \src "libresoc.v:176319.3-176362.6" + wire $2\logical_op__is_32bit$43$next[0:0]$10148 + attribute \src "libresoc.v:176319.3-176362.6" + wire $2\logical_op__is_signed$44$next[0:0]$10149 + attribute \src "libresoc.v:176319.3-176362.6" + wire $2\logical_op__oe__oe$35$next[0:0]$10150 + attribute \src "libresoc.v:176319.3-176362.6" + wire $2\logical_op__oe__ok$36$next[0:0]$10151 + attribute \src "libresoc.v:176319.3-176362.6" + wire $2\logical_op__output_carry$42$next[0:0]$10152 + attribute \src "libresoc.v:176319.3-176362.6" + wire $2\logical_op__rc__ok$34$next[0:0]$10153 + attribute \src "libresoc.v:176319.3-176362.6" + wire $2\logical_op__rc__rc$33$next[0:0]$10154 + attribute \src "libresoc.v:176319.3-176362.6" + wire $2\logical_op__write_cr0$41$next[0:0]$10155 + attribute \src "libresoc.v:176319.3-176362.6" + wire $2\logical_op__zero_a$38$next[0:0]$10156 + attribute \src "libresoc.v:176304.3-176318.6" + wire width 2 $2\muxid$28$next[1:0]$10101 + attribute \src "libresoc.v:176513.3-176527.6" + wire width 2 $2\operation$69$next[1:0]$10206 + attribute \src "libresoc.v:176363.3-176377.6" + wire width 64 $2\ra$47$next[63:0]$10166 + attribute \src "libresoc.v:176378.3-176392.6" + wire width 64 $2\rb$48$next[63:0]$10170 + attribute \src "libresoc.v:176393.3-176407.6" + wire $2\xer_so$49$next[0:0]$10174 + attribute \src "libresoc.v:176276.3-176303.6" + wire $3\empty$next[0:0]$10096 + attribute \src "libresoc.v:176319.3-176362.6" + wire width 64 $3\logical_op__imm_data__data$31$next[63:0]$10157 + attribute \src "libresoc.v:176319.3-176362.6" + wire $3\logical_op__imm_data__ok$32$next[0:0]$10158 + attribute \src "libresoc.v:176319.3-176362.6" + wire $3\logical_op__oe__oe$35$next[0:0]$10159 + attribute \src "libresoc.v:176319.3-176362.6" + wire $3\logical_op__oe__ok$36$next[0:0]$10160 + attribute \src "libresoc.v:176319.3-176362.6" + wire $3\logical_op__rc__ok$34$next[0:0]$10161 + attribute \src "libresoc.v:176319.3-176362.6" + wire $3\logical_op__rc__rc$33$next[0:0]$10162 + attribute \src "libresoc.v:176276.3-176303.6" + wire $4\empty$next[0:0]$10097 + attribute \src "libresoc.v:176134.18-176134.98" + wire $and$libresoc.v:176134$10018_Y + attribute \src "libresoc.v:176135.18-176135.107" + wire $and$libresoc.v:176135$10019_Y + attribute \src "libresoc.v:176131.18-176131.92" + wire width 192 $extend$libresoc.v:176131$10014_Y + attribute \src "libresoc.v:176133.18-176133.119" + wire $ge$libresoc.v:176133$10017_Y + attribute \src "libresoc.v:176132.18-176132.93" + wire $not$libresoc.v:176132$10016_Y + attribute \src "libresoc.v:176131.18-176131.92" + wire width 192 $pos$libresoc.v:176131$10015_Y + attribute \src "libresoc.v:176130.18-176130.138" + wire width 191 $sshl$libresoc.v:176130$10013_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:169" + wire width 192 \$55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:169" + wire width 191 \$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:171" + wire \$59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:116" + wire \$61 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:171" + wire \$63 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" + wire \$66 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 65 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire input 30 \div_by_zero + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire output 62 \div_by_zero$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire \div_by_zero$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire \div_by_zero$54$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:89" + wire width 128 \div_state_init_dividend + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:105" + wire width 128 \div_state_init_o_dividend_quotient + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:103" + wire width 7 \div_state_init_o_q_bits_known + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:59" + wire width 64 \div_state_next_divisor + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:105" + wire width 128 \div_state_next_i_dividend_quotient + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:103" + wire width 7 \div_state_next_i_q_bits_known + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:105" + wire width 128 \div_state_next_o_dividend_quotient + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:103" + wire width 7 \div_state_next_o_q_bits_known + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire input 28 \dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire output 60 \dive_abs_ov32$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire \dive_abs_ov32$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire \dive_abs_ov32$52$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire input 29 \dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire output 61 \dive_abs_ov64$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire \dive_abs_ov64$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire \dive_abs_ov64$53$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" + wire width 128 input 31 \dividend + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" + wire width 128 \dividend$68 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" + wire width 128 \dividend$68$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire input 27 \dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire output 59 \dividend_neg$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire \dividend_neg$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire \dividend_neg$51$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire input 26 \divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire output 58 \divisor_neg$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire \divisor_neg$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire \divisor_neg$50$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" + wire width 64 input 32 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" + wire width 64 \divisor_radicand$65 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" + wire width 64 \divisor_radicand$65$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:140" + wire \empty + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:140" + wire \empty$next + attribute \src "libresoc.v:175563.7-175563.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 21 \logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 53 \logical_op__data_len$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \logical_op__data_len$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \logical_op__data_len$45$next + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 input 6 \logical_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 output 38 \logical_op__fn_unit$3 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \logical_op__fn_unit$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \logical_op__fn_unit$30$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 7 \logical_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \logical_op__imm_data__data$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \logical_op__imm_data__data$31$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 39 \logical_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \logical_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__imm_data__ok$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__imm_data__ok$32$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 40 \logical_op__imm_data__ok$5 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 15 \logical_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 47 \logical_op__input_carry$12 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \logical_op__input_carry$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \logical_op__input_carry$39$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 22 \logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 54 \logical_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \logical_op__insn$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \logical_op__insn$46$next + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 5 \logical_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 37 \logical_op__insn_type$2 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \logical_op__insn_type$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \logical_op__insn_type$29$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 45 \logical_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_in$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_in$37$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 16 \logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 48 \logical_op__invert_out$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_out$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_out$40$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 19 \logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 51 \logical_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_32bit$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_32bit$43$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 20 \logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 52 \logical_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_signed$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_signed$44$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 11 \logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__oe$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__oe$35$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 43 \logical_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__ok$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__ok$36$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 44 \logical_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 18 \logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 50 \logical_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__output_carry$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__output_carry$42$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__ok$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__ok$34$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 42 \logical_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__rc$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__rc$33$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 41 \logical_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 17 \logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 49 \logical_op__write_cr0$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__write_cr0$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__write_cr0$41$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 46 \logical_op__zero_a$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__zero_a$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__zero_a$38$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 input 4 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 output 36 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid$28$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire input 35 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire output 34 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" + wire width 2 input 33 \operation + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" + wire width 2 \operation$69 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" + wire width 2 \operation$69$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" + wire output 3 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" + wire input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40" + wire width 64 output 63 \quotient_root + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 23 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 55 \ra$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \ra$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \ra$47$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 24 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 56 \rb$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \rb$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \rb$48$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:41" + wire width 192 output 64 \remainder + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:105" + wire width 128 \saved_state_dividend_quotient + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:105" + wire width 128 \saved_state_dividend_quotient$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:103" + wire width 7 \saved_state_q_bits_known + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:103" + wire width 7 \saved_state_q_bits_known$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 25 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire output 57 \xer_so$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \xer_so$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \xer_so$49$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:171" + cell $and $and$libresoc.v:176134$10018 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$59 + connect \B \$61 + connect \Y $and$libresoc.v:176134$10018_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" + cell $and $and$libresoc.v:176135$10019 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \n_ready_i + connect \B \n_valid_o + connect \Y $and$libresoc.v:176135$10019_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:169" + cell $pos $extend$libresoc.v:176131$10014 + parameter \A_SIGNED 0 + parameter \A_WIDTH 191 + parameter \Y_WIDTH 192 + connect \A \$56 + connect \Y $extend$libresoc.v:176131$10014_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:116" + cell $ge $ge$libresoc.v:176133$10017 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \saved_state_q_bits_known + connect \B 6'111111 + connect \Y $ge$libresoc.v:176133$10017_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:171" + cell $not $not$libresoc.v:176132$10016 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \empty + connect \Y $not$libresoc.v:176132$10016_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:169" + cell $pos $pos$libresoc.v:176131$10015 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A $extend$libresoc.v:176131$10014_Y + connect \Y $pos$libresoc.v:176131$10015_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:169" + cell $sshl $sshl$libresoc.v:176130$10013 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 191 + connect \A \div_state_next_o_dividend_quotient [127:64] + connect \B 7'1000000 + connect \Y $sshl$libresoc.v:176130$10013_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:176202.18-176206.4" + cell \div_state_init \div_state_init + connect \dividend \div_state_init_dividend + connect \o_dividend_quotient \div_state_init_o_dividend_quotient + connect \o_q_bits_known \div_state_init_o_q_bits_known + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:176207.18-176213.4" + cell \div_state_next \div_state_next + connect \divisor \div_state_next_divisor + connect \i_dividend_quotient \div_state_next_i_dividend_quotient + connect \i_q_bits_known \div_state_next_i_q_bits_known + connect \o_dividend_quotient \div_state_next_o_dividend_quotient + connect \o_q_bits_known \div_state_next_o_q_bits_known + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:176214.10-176217.4" + cell \n$80 \n + connect \n_ready_i \n_ready_i + connect \n_valid_o \n_valid_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:176218.10-176221.4" + cell \p$79 \p + connect \p_ready_o \p_ready_o + connect \p_valid_i \p_valid_i + end + attribute \src "libresoc.v:175563.7-175563.20" + process $proc$libresoc.v:175563$10207 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:175585.7-175585.30" + process $proc$libresoc.v:175585$10208 + assign { } { } + assign $0\div_by_zero$54[0:0]$10209 1'0 + sync always + sync init + update \div_by_zero$54 $0\div_by_zero$54[0:0]$10209 + end + attribute \src "libresoc.v:175609.7-175609.32" + process $proc$libresoc.v:175609$10210 + assign { } { } + assign $0\dive_abs_ov32$52[0:0]$10211 1'0 + sync always + sync init + update \dive_abs_ov32$52 $0\dive_abs_ov32$52[0:0]$10211 + end + attribute \src "libresoc.v:175617.7-175617.32" + process $proc$libresoc.v:175617$10212 + assign { } { } + assign $0\dive_abs_ov64$53[0:0]$10213 1'0 + sync always + sync init + update \dive_abs_ov64$53 $0\dive_abs_ov64$53[0:0]$10213 + end + attribute \src "libresoc.v:175623.15-175623.68" + process $proc$libresoc.v:175623$10214 + assign { } { } + assign $0\dividend$68[127:0]$10215 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \dividend$68 $0\dividend$68[127:0]$10215 + end + attribute \src "libresoc.v:175631.7-175631.31" + process $proc$libresoc.v:175631$10216 + assign { } { } + assign $0\dividend_neg$51[0:0]$10217 1'0 + sync always + sync init + update \dividend_neg$51 $0\dividend_neg$51[0:0]$10217 + end + attribute \src "libresoc.v:175639.7-175639.30" + process $proc$libresoc.v:175639$10218 + assign { } { } + assign $0\divisor_neg$50[0:0]$10219 1'0 + sync always + sync init + update \divisor_neg$50 $0\divisor_neg$50[0:0]$10219 + end + attribute \src "libresoc.v:175645.14-175645.58" + process $proc$libresoc.v:175645$10220 + assign { } { } + assign $0\divisor_radicand$65[63:0]$10221 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \divisor_radicand$65 $0\divisor_radicand$65[63:0]$10221 + end + attribute \src "libresoc.v:175649.7-175649.19" + process $proc$libresoc.v:175649$10222 + assign { } { } + assign $1\empty[0:0] 1'1 + sync always + sync init + update \empty $1\empty[0:0] + end + attribute \src "libresoc.v:175657.13-175657.45" + process $proc$libresoc.v:175657$10223 + assign { } { } + assign $0\logical_op__data_len$45[3:0]$10224 4'0000 + sync always + sync init + update \logical_op__data_len$45 $0\logical_op__data_len$45[3:0]$10224 + end + attribute \src "libresoc.v:175707.14-175707.49" + process $proc$libresoc.v:175707$10225 + assign { } { } + assign $0\logical_op__fn_unit$30[12:0]$10226 13'0000000000000 + sync always + sync init + update \logical_op__fn_unit$30 $0\logical_op__fn_unit$30[12:0]$10226 + end + attribute \src "libresoc.v:175713.14-175713.68" + process $proc$libresoc.v:175713$10227 + assign { } { } + assign $0\logical_op__imm_data__data$31[63:0]$10228 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \logical_op__imm_data__data$31 $0\logical_op__imm_data__data$31[63:0]$10228 + end + attribute \src "libresoc.v:175721.7-175721.43" + process $proc$libresoc.v:175721$10229 + assign { } { } + assign $0\logical_op__imm_data__ok$32[0:0]$10230 1'0 + sync always + sync init + update \logical_op__imm_data__ok$32 $0\logical_op__imm_data__ok$32[0:0]$10230 + end + attribute \src "libresoc.v:175743.13-175743.48" + process $proc$libresoc.v:175743$10231 + assign { } { } + assign $0\logical_op__input_carry$39[1:0]$10232 2'00 + sync always + sync init + update \logical_op__input_carry$39 $0\logical_op__input_carry$39[1:0]$10232 + end + attribute \src "libresoc.v:175751.14-175751.43" + process $proc$libresoc.v:175751$10233 + assign { } { } + assign $0\logical_op__insn$46[31:0]$10234 0 + sync always + sync init + update \logical_op__insn$46 $0\logical_op__insn$46[31:0]$10234 + end + attribute \src "libresoc.v:175981.13-175981.47" + process $proc$libresoc.v:175981$10235 + assign { } { } + assign $0\logical_op__insn_type$29[6:0]$10236 7'0000000 + sync always + sync init + update \logical_op__insn_type$29 $0\logical_op__insn_type$29[6:0]$10236 + end + attribute \src "libresoc.v:175989.7-175989.40" + process $proc$libresoc.v:175989$10237 + assign { } { } + assign $0\logical_op__invert_in$37[0:0]$10238 1'0 + sync always + sync init + update \logical_op__invert_in$37 $0\logical_op__invert_in$37[0:0]$10238 + end + attribute \src "libresoc.v:175997.7-175997.41" + process $proc$libresoc.v:175997$10239 + assign { } { } + assign $0\logical_op__invert_out$40[0:0]$10240 1'0 + sync always + sync init + update \logical_op__invert_out$40 $0\logical_op__invert_out$40[0:0]$10240 + end + attribute \src "libresoc.v:176005.7-176005.39" + process $proc$libresoc.v:176005$10241 + assign { } { } + assign $0\logical_op__is_32bit$43[0:0]$10242 1'0 + sync always + sync init + update \logical_op__is_32bit$43 $0\logical_op__is_32bit$43[0:0]$10242 + end + attribute \src "libresoc.v:176013.7-176013.40" + process $proc$libresoc.v:176013$10243 + assign { } { } + assign $0\logical_op__is_signed$44[0:0]$10244 1'0 + sync always + sync init + update \logical_op__is_signed$44 $0\logical_op__is_signed$44[0:0]$10244 + end + attribute \src "libresoc.v:176019.7-176019.37" + process $proc$libresoc.v:176019$10245 + assign { } { } + assign $0\logical_op__oe__oe$35[0:0]$10246 1'0 + sync always + sync init + update \logical_op__oe__oe$35 $0\logical_op__oe__oe$35[0:0]$10246 + end + attribute \src "libresoc.v:176027.7-176027.37" + process $proc$libresoc.v:176027$10247 + assign { } { } + assign $0\logical_op__oe__ok$36[0:0]$10248 1'0 + sync always + sync init + update \logical_op__oe__ok$36 $0\logical_op__oe__ok$36[0:0]$10248 + end + attribute \src "libresoc.v:176037.7-176037.43" + process $proc$libresoc.v:176037$10249 + assign { } { } + assign $0\logical_op__output_carry$42[0:0]$10250 1'0 + sync always + sync init + update \logical_op__output_carry$42 $0\logical_op__output_carry$42[0:0]$10250 + end + attribute \src "libresoc.v:176043.7-176043.37" + process $proc$libresoc.v:176043$10251 + assign { } { } + assign $0\logical_op__rc__ok$34[0:0]$10252 1'0 + sync always + sync init + update \logical_op__rc__ok$34 $0\logical_op__rc__ok$34[0:0]$10252 + end + attribute \src "libresoc.v:176051.7-176051.37" + process $proc$libresoc.v:176051$10253 + assign { } { } + assign $0\logical_op__rc__rc$33[0:0]$10254 1'0 + sync always + sync init + update \logical_op__rc__rc$33 $0\logical_op__rc__rc$33[0:0]$10254 + end + attribute \src "libresoc.v:176061.7-176061.40" + process $proc$libresoc.v:176061$10255 + assign { } { } + assign $0\logical_op__write_cr0$41[0:0]$10256 1'0 + sync always + sync init + update \logical_op__write_cr0$41 $0\logical_op__write_cr0$41[0:0]$10256 + end + attribute \src "libresoc.v:176069.7-176069.37" + process $proc$libresoc.v:176069$10257 + assign { } { } + assign $0\logical_op__zero_a$38[0:0]$10258 1'0 + sync always + sync init + update \logical_op__zero_a$38 $0\logical_op__zero_a$38[0:0]$10258 + end + attribute \src "libresoc.v:176077.13-176077.30" + process $proc$libresoc.v:176077$10259 + assign { } { } + assign $0\muxid$28[1:0]$10260 2'00 + sync always + sync init + update \muxid$28 $0\muxid$28[1:0]$10260 + end + attribute \src "libresoc.v:176087.13-176087.34" + process $proc$libresoc.v:176087$10261 + assign { } { } + assign $0\operation$69[1:0]$10262 2'00 + sync always + sync init + update \operation$69 $0\operation$69[1:0]$10262 + end + attribute \src "libresoc.v:176101.14-176101.44" + process $proc$libresoc.v:176101$10263 + assign { } { } + assign $0\ra$47[63:0]$10264 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \ra$47 $0\ra$47[63:0]$10264 + end + attribute \src "libresoc.v:176109.14-176109.44" + process $proc$libresoc.v:176109$10265 + assign { } { } + assign $0\rb$48[63:0]$10266 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \rb$48 $0\rb$48[63:0]$10266 + end + attribute \src "libresoc.v:176115.15-176115.84" + process $proc$libresoc.v:176115$10267 + assign { } { } + assign $1\saved_state_dividend_quotient[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \saved_state_dividend_quotient $1\saved_state_dividend_quotient[127:0] + end + attribute \src "libresoc.v:176119.13-176119.45" + process $proc$libresoc.v:176119$10268 + assign { } { } + assign $1\saved_state_q_bits_known[6:0] 7'0000000 + sync always + sync init + update \saved_state_q_bits_known $1\saved_state_q_bits_known[6:0] + end + attribute \src "libresoc.v:176127.7-176127.25" + process $proc$libresoc.v:176127$10269 + assign { } { } + assign $0\xer_so$49[0:0]$10270 1'0 + sync always + sync init + update \xer_so$49 $0\xer_so$49[0:0]$10270 + end + attribute \src "libresoc.v:176136.3-176137.43" + process $proc$libresoc.v:176136$10020 + assign { } { } + assign $0\operation$69[1:0]$10021 \operation$69$next + sync posedge \coresync_clk + update \operation$69 $0\operation$69[1:0]$10021 + end + attribute \src "libresoc.v:176138.3-176139.57" + process $proc$libresoc.v:176138$10022 + assign { } { } + assign $0\divisor_radicand$65[63:0]$10023 \divisor_radicand$65$next + sync posedge \coresync_clk + update \divisor_radicand$65 $0\divisor_radicand$65[63:0]$10023 + end + attribute \src "libresoc.v:176140.3-176141.41" + process $proc$libresoc.v:176140$10024 + assign { } { } + assign $0\dividend$68[127:0]$10025 \dividend$68$next + sync posedge \coresync_clk + update \dividend$68 $0\dividend$68[127:0]$10025 + end + attribute \src "libresoc.v:176142.3-176143.47" + process $proc$libresoc.v:176142$10026 + assign { } { } + assign $0\div_by_zero$54[0:0]$10027 \div_by_zero$54$next + sync posedge \coresync_clk + update \div_by_zero$54 $0\div_by_zero$54[0:0]$10027 + end + attribute \src "libresoc.v:176144.3-176145.51" + process $proc$libresoc.v:176144$10028 + assign { } { } + assign $0\dive_abs_ov64$53[0:0]$10029 \dive_abs_ov64$53$next + sync posedge \coresync_clk + update \dive_abs_ov64$53 $0\dive_abs_ov64$53[0:0]$10029 + end + attribute \src "libresoc.v:176146.3-176147.51" + process $proc$libresoc.v:176146$10030 + assign { } { } + assign $0\dive_abs_ov32$52[0:0]$10031 \dive_abs_ov32$52$next + sync posedge \coresync_clk + update \dive_abs_ov32$52 $0\dive_abs_ov32$52[0:0]$10031 + end + attribute \src "libresoc.v:176148.3-176149.49" + process $proc$libresoc.v:176148$10032 + assign { } { } + assign $0\dividend_neg$51[0:0]$10033 \dividend_neg$51$next + sync posedge \coresync_clk + update \dividend_neg$51 $0\dividend_neg$51[0:0]$10033 + end + attribute \src "libresoc.v:176150.3-176151.47" + process $proc$libresoc.v:176150$10034 + assign { } { } + assign $0\divisor_neg$50[0:0]$10035 \divisor_neg$50$next + sync posedge \coresync_clk + update \divisor_neg$50 $0\divisor_neg$50[0:0]$10035 + end + attribute \src "libresoc.v:176152.3-176153.37" + process $proc$libresoc.v:176152$10036 + assign { } { } + assign $0\xer_so$49[0:0]$10037 \xer_so$49$next + sync posedge \coresync_clk + update \xer_so$49 $0\xer_so$49[0:0]$10037 + end + attribute \src "libresoc.v:176154.3-176155.29" + process $proc$libresoc.v:176154$10038 + assign { } { } + assign $0\rb$48[63:0]$10039 \rb$48$next + sync posedge \coresync_clk + update \rb$48 $0\rb$48[63:0]$10039 + end + attribute \src "libresoc.v:176156.3-176157.29" + process $proc$libresoc.v:176156$10040 + assign { } { } + assign $0\ra$47[63:0]$10041 \ra$47$next + sync posedge \coresync_clk + update \ra$47 $0\ra$47[63:0]$10041 + end + attribute \src "libresoc.v:176158.3-176159.67" + process $proc$libresoc.v:176158$10042 + assign { } { } + assign $0\logical_op__insn_type$29[6:0]$10043 \logical_op__insn_type$29$next + sync posedge \coresync_clk + update \logical_op__insn_type$29 $0\logical_op__insn_type$29[6:0]$10043 + end + attribute \src "libresoc.v:176160.3-176161.63" + process $proc$libresoc.v:176160$10044 + assign { } { } + assign $0\logical_op__fn_unit$30[12:0]$10045 \logical_op__fn_unit$30$next + sync posedge \coresync_clk + update \logical_op__fn_unit$30 $0\logical_op__fn_unit$30[12:0]$10045 + end + attribute \src "libresoc.v:176162.3-176163.77" + process $proc$libresoc.v:176162$10046 + assign { } { } + assign $0\logical_op__imm_data__data$31[63:0]$10047 \logical_op__imm_data__data$31$next + sync posedge \coresync_clk + update \logical_op__imm_data__data$31 $0\logical_op__imm_data__data$31[63:0]$10047 + end + attribute \src "libresoc.v:176164.3-176165.73" + process $proc$libresoc.v:176164$10048 + assign { } { } + assign $0\logical_op__imm_data__ok$32[0:0]$10049 \logical_op__imm_data__ok$32$next + sync posedge \coresync_clk + update \logical_op__imm_data__ok$32 $0\logical_op__imm_data__ok$32[0:0]$10049 + end + attribute \src "libresoc.v:176166.3-176167.61" + process $proc$libresoc.v:176166$10050 + assign { } { } + assign $0\logical_op__rc__rc$33[0:0]$10051 \logical_op__rc__rc$33$next + sync posedge \coresync_clk + update \logical_op__rc__rc$33 $0\logical_op__rc__rc$33[0:0]$10051 + end + attribute \src "libresoc.v:176168.3-176169.61" + process $proc$libresoc.v:176168$10052 + assign { } { } + assign $0\logical_op__rc__ok$34[0:0]$10053 \logical_op__rc__ok$34$next + sync posedge \coresync_clk + update \logical_op__rc__ok$34 $0\logical_op__rc__ok$34[0:0]$10053 + end + attribute \src "libresoc.v:176170.3-176171.61" + process $proc$libresoc.v:176170$10054 + assign { } { } + assign $0\logical_op__oe__oe$35[0:0]$10055 \logical_op__oe__oe$35$next + sync posedge \coresync_clk + update \logical_op__oe__oe$35 $0\logical_op__oe__oe$35[0:0]$10055 + end + attribute \src "libresoc.v:176172.3-176173.61" + process $proc$libresoc.v:176172$10056 + assign { } { } + assign $0\logical_op__oe__ok$36[0:0]$10057 \logical_op__oe__ok$36$next + sync posedge \coresync_clk + update \logical_op__oe__ok$36 $0\logical_op__oe__ok$36[0:0]$10057 + end + attribute \src "libresoc.v:176174.3-176175.67" + process $proc$libresoc.v:176174$10058 + assign { } { } + assign $0\logical_op__invert_in$37[0:0]$10059 \logical_op__invert_in$37$next + sync posedge \coresync_clk + update \logical_op__invert_in$37 $0\logical_op__invert_in$37[0:0]$10059 + end + attribute \src "libresoc.v:176176.3-176177.61" + process $proc$libresoc.v:176176$10060 + assign { } { } + assign $0\logical_op__zero_a$38[0:0]$10061 \logical_op__zero_a$38$next + sync posedge \coresync_clk + update \logical_op__zero_a$38 $0\logical_op__zero_a$38[0:0]$10061 + end + attribute \src "libresoc.v:176178.3-176179.71" + process $proc$libresoc.v:176178$10062 + assign { } { } + assign $0\logical_op__input_carry$39[1:0]$10063 \logical_op__input_carry$39$next + sync posedge \coresync_clk + update \logical_op__input_carry$39 $0\logical_op__input_carry$39[1:0]$10063 + end + attribute \src "libresoc.v:176180.3-176181.69" + process $proc$libresoc.v:176180$10064 + assign { } { } + assign $0\logical_op__invert_out$40[0:0]$10065 \logical_op__invert_out$40$next + sync posedge \coresync_clk + update \logical_op__invert_out$40 $0\logical_op__invert_out$40[0:0]$10065 + end + attribute \src "libresoc.v:176182.3-176183.67" + process $proc$libresoc.v:176182$10066 + assign { } { } + assign $0\logical_op__write_cr0$41[0:0]$10067 \logical_op__write_cr0$41$next + sync posedge \coresync_clk + update \logical_op__write_cr0$41 $0\logical_op__write_cr0$41[0:0]$10067 + end + attribute \src "libresoc.v:176184.3-176185.73" + process $proc$libresoc.v:176184$10068 + assign { } { } + assign $0\logical_op__output_carry$42[0:0]$10069 \logical_op__output_carry$42$next + sync posedge \coresync_clk + update \logical_op__output_carry$42 $0\logical_op__output_carry$42[0:0]$10069 + end + attribute \src "libresoc.v:176186.3-176187.65" + process $proc$libresoc.v:176186$10070 + assign { } { } + assign $0\logical_op__is_32bit$43[0:0]$10071 \logical_op__is_32bit$43$next + sync posedge \coresync_clk + update \logical_op__is_32bit$43 $0\logical_op__is_32bit$43[0:0]$10071 + end + attribute \src "libresoc.v:176188.3-176189.67" + process $proc$libresoc.v:176188$10072 + assign { } { } + assign $0\logical_op__is_signed$44[0:0]$10073 \logical_op__is_signed$44$next + sync posedge \coresync_clk + update \logical_op__is_signed$44 $0\logical_op__is_signed$44[0:0]$10073 + end + attribute \src "libresoc.v:176190.3-176191.65" + process $proc$libresoc.v:176190$10074 + assign { } { } + assign $0\logical_op__data_len$45[3:0]$10075 \logical_op__data_len$45$next + sync posedge \coresync_clk + update \logical_op__data_len$45 $0\logical_op__data_len$45[3:0]$10075 + end + attribute \src "libresoc.v:176192.3-176193.57" + process $proc$libresoc.v:176192$10076 + assign { } { } + assign $0\logical_op__insn$46[31:0]$10077 \logical_op__insn$46$next + sync posedge \coresync_clk + update \logical_op__insn$46 $0\logical_op__insn$46[31:0]$10077 + end + attribute \src "libresoc.v:176194.3-176195.35" + process $proc$libresoc.v:176194$10078 + assign { } { } + assign $0\muxid$28[1:0]$10079 \muxid$28$next + sync posedge \coresync_clk + update \muxid$28 $0\muxid$28[1:0]$10079 + end + attribute \src "libresoc.v:176196.3-176197.27" + process $proc$libresoc.v:176196$10080 + assign { } { } + assign $0\empty[0:0] \empty$next + sync posedge \coresync_clk + update \empty $0\empty[0:0] + end + attribute \src "libresoc.v:176198.3-176199.75" + process $proc$libresoc.v:176198$10081 + assign { } { } + assign $0\saved_state_dividend_quotient[127:0] \saved_state_dividend_quotient$next + sync posedge \coresync_clk + update \saved_state_dividend_quotient $0\saved_state_dividend_quotient[127:0] + end + attribute \src "libresoc.v:176200.3-176201.65" + process $proc$libresoc.v:176200$10082 + assign { } { } + assign $0\saved_state_q_bits_known[6:0] \saved_state_q_bits_known$next + sync posedge \coresync_clk + update \saved_state_q_bits_known $0\saved_state_q_bits_known[6:0] + end + attribute \src "libresoc.v:176222.3-176230.6" + process $proc$libresoc.v:176222$10083 + assign { } { } + assign { } { } + assign $0\saved_state_q_bits_known$next[6:0]$10084 $1\saved_state_q_bits_known$next[6:0]$10085 + attribute \src "libresoc.v:176223.5-176223.29" + switch \initial + attribute \src "libresoc.v:176223.9-176223.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\saved_state_q_bits_known$next[6:0]$10085 7'0000000 + case + assign $1\saved_state_q_bits_known$next[6:0]$10085 \div_state_next_o_q_bits_known + end + sync always + update \saved_state_q_bits_known$next $0\saved_state_q_bits_known$next[6:0]$10084 + end + attribute \src "libresoc.v:176231.3-176239.6" + process $proc$libresoc.v:176231$10086 + assign { } { } + assign { } { } + assign $0\saved_state_dividend_quotient$next[127:0]$10087 $1\saved_state_dividend_quotient$next[127:0]$10088 + attribute \src "libresoc.v:176232.5-176232.29" + switch \initial + attribute \src "libresoc.v:176232.9-176232.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\saved_state_dividend_quotient$next[127:0]$10088 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + case + assign $1\saved_state_dividend_quotient$next[127:0]$10088 \div_state_next_o_dividend_quotient + end + sync always + update \saved_state_dividend_quotient$next $0\saved_state_dividend_quotient$next[127:0]$10087 + end + attribute \src "libresoc.v:176240.3-176251.6" + process $proc$libresoc.v:176240$10089 + assign { } { } + assign $0\div_state_next_i_q_bits_known[6:0] $1\div_state_next_i_q_bits_known[6:0] + attribute \src "libresoc.v:176241.5-176241.29" + switch \initial + attribute \src "libresoc.v:176241.9-176241.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" + switch \empty + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\div_state_next_i_q_bits_known[6:0] \div_state_init_o_q_bits_known + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\div_state_next_i_q_bits_known[6:0] \saved_state_q_bits_known + end + sync always + update \div_state_next_i_q_bits_known $0\div_state_next_i_q_bits_known[6:0] + end + attribute \src "libresoc.v:176252.3-176263.6" + process $proc$libresoc.v:176252$10090 + assign { } { } + assign $0\div_state_next_i_dividend_quotient[127:0] $1\div_state_next_i_dividend_quotient[127:0] + attribute \src "libresoc.v:176253.5-176253.29" + switch \initial + attribute \src "libresoc.v:176253.9-176253.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" + switch \empty + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\div_state_next_i_dividend_quotient[127:0] \div_state_init_o_dividend_quotient + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\div_state_next_i_dividend_quotient[127:0] \saved_state_dividend_quotient + end + sync always + update \div_state_next_i_dividend_quotient $0\div_state_next_i_dividend_quotient[127:0] + end + attribute \src "libresoc.v:176264.3-176275.6" + process $proc$libresoc.v:176264$10091 + assign { } { } + assign $0\div_state_next_divisor[63:0] $1\div_state_next_divisor[63:0] + attribute \src "libresoc.v:176265.5-176265.29" + switch \initial + attribute \src "libresoc.v:176265.9-176265.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" + switch \empty + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\div_state_next_divisor[63:0] \divisor_radicand + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\div_state_next_divisor[63:0] \divisor_radicand$65 + end + sync always + update \div_state_next_divisor $0\div_state_next_divisor[63:0] + end + attribute \src "libresoc.v:176276.3-176303.6" + process $proc$libresoc.v:176276$10092 + assign { } { } + assign { } { } + assign { } { } + assign $0\empty$next[0:0]$10093 $4\empty$next[0:0]$10097 + attribute \src "libresoc.v:176277.5-176277.29" + switch \initial + attribute \src "libresoc.v:176277.9-176277.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" + switch \empty + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\empty$next[0:0]$10094 $2\empty$next[0:0]$10095 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" + switch \p_valid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\empty$next[0:0]$10095 1'0 + case + assign $2\empty$next[0:0]$10095 \empty + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\empty$next[0:0]$10094 $3\empty$next[0:0]$10096 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" + switch \$66 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\empty$next[0:0]$10096 1'1 + case + assign $3\empty$next[0:0]$10096 \empty + end + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\empty$next[0:0]$10097 1'1 + case + assign $4\empty$next[0:0]$10097 $1\empty$next[0:0]$10094 + end + sync always + update \empty$next $0\empty$next[0:0]$10093 + end + attribute \src "libresoc.v:176304.3-176318.6" + process $proc$libresoc.v:176304$10098 + assign { } { } + assign { } { } + assign $0\muxid$28$next[1:0]$10099 $1\muxid$28$next[1:0]$10100 + attribute \src "libresoc.v:176305.5-176305.29" + switch \initial + attribute \src "libresoc.v:176305.9-176305.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" + switch \empty + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\muxid$28$next[1:0]$10100 $2\muxid$28$next[1:0]$10101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" + switch \p_valid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\muxid$28$next[1:0]$10101 \muxid + case + assign $2\muxid$28$next[1:0]$10101 \muxid$28 + end + case + assign $1\muxid$28$next[1:0]$10100 \muxid$28 + end + sync always + update \muxid$28$next $0\muxid$28$next[1:0]$10099 + end + attribute \src "libresoc.v:176319.3-176362.6" + process $proc$libresoc.v:176319$10102 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\logical_op__data_len$45$next[3:0]$10103 $1\logical_op__data_len$45$next[3:0]$10121 + assign $0\logical_op__fn_unit$30$next[12:0]$10104 $1\logical_op__fn_unit$30$next[12:0]$10122 + assign { } { } + assign { } { } + assign $0\logical_op__input_carry$39$next[1:0]$10107 $1\logical_op__input_carry$39$next[1:0]$10125 + assign $0\logical_op__insn$46$next[31:0]$10108 $1\logical_op__insn$46$next[31:0]$10126 + assign $0\logical_op__insn_type$29$next[6:0]$10109 $1\logical_op__insn_type$29$next[6:0]$10127 + assign $0\logical_op__invert_in$37$next[0:0]$10110 $1\logical_op__invert_in$37$next[0:0]$10128 + assign $0\logical_op__invert_out$40$next[0:0]$10111 $1\logical_op__invert_out$40$next[0:0]$10129 + assign $0\logical_op__is_32bit$43$next[0:0]$10112 $1\logical_op__is_32bit$43$next[0:0]$10130 + assign $0\logical_op__is_signed$44$next[0:0]$10113 $1\logical_op__is_signed$44$next[0:0]$10131 + assign { } { } + assign { } { } + assign $0\logical_op__output_carry$42$next[0:0]$10116 $1\logical_op__output_carry$42$next[0:0]$10134 + assign { } { } + assign { } { } + assign $0\logical_op__write_cr0$41$next[0:0]$10119 $1\logical_op__write_cr0$41$next[0:0]$10137 + assign $0\logical_op__zero_a$38$next[0:0]$10120 $1\logical_op__zero_a$38$next[0:0]$10138 + assign $0\logical_op__imm_data__data$31$next[63:0]$10105 $3\logical_op__imm_data__data$31$next[63:0]$10157 + assign $0\logical_op__imm_data__ok$32$next[0:0]$10106 $3\logical_op__imm_data__ok$32$next[0:0]$10158 + assign $0\logical_op__oe__oe$35$next[0:0]$10114 $3\logical_op__oe__oe$35$next[0:0]$10159 + assign $0\logical_op__oe__ok$36$next[0:0]$10115 $3\logical_op__oe__ok$36$next[0:0]$10160 + assign $0\logical_op__rc__ok$34$next[0:0]$10117 $3\logical_op__rc__ok$34$next[0:0]$10161 + assign $0\logical_op__rc__rc$33$next[0:0]$10118 $3\logical_op__rc__rc$33$next[0:0]$10162 + attribute \src "libresoc.v:176320.5-176320.29" + switch \initial + attribute \src "libresoc.v:176320.9-176320.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" + switch \empty + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\logical_op__data_len$45$next[3:0]$10121 $2\logical_op__data_len$45$next[3:0]$10139 + assign $1\logical_op__fn_unit$30$next[12:0]$10122 $2\logical_op__fn_unit$30$next[12:0]$10140 + assign $1\logical_op__imm_data__data$31$next[63:0]$10123 $2\logical_op__imm_data__data$31$next[63:0]$10141 + assign $1\logical_op__imm_data__ok$32$next[0:0]$10124 $2\logical_op__imm_data__ok$32$next[0:0]$10142 + assign $1\logical_op__input_carry$39$next[1:0]$10125 $2\logical_op__input_carry$39$next[1:0]$10143 + assign $1\logical_op__insn$46$next[31:0]$10126 $2\logical_op__insn$46$next[31:0]$10144 + assign $1\logical_op__insn_type$29$next[6:0]$10127 $2\logical_op__insn_type$29$next[6:0]$10145 + assign $1\logical_op__invert_in$37$next[0:0]$10128 $2\logical_op__invert_in$37$next[0:0]$10146 + assign $1\logical_op__invert_out$40$next[0:0]$10129 $2\logical_op__invert_out$40$next[0:0]$10147 + assign $1\logical_op__is_32bit$43$next[0:0]$10130 $2\logical_op__is_32bit$43$next[0:0]$10148 + assign $1\logical_op__is_signed$44$next[0:0]$10131 $2\logical_op__is_signed$44$next[0:0]$10149 + assign $1\logical_op__oe__oe$35$next[0:0]$10132 $2\logical_op__oe__oe$35$next[0:0]$10150 + assign $1\logical_op__oe__ok$36$next[0:0]$10133 $2\logical_op__oe__ok$36$next[0:0]$10151 + assign $1\logical_op__output_carry$42$next[0:0]$10134 $2\logical_op__output_carry$42$next[0:0]$10152 + assign $1\logical_op__rc__ok$34$next[0:0]$10135 $2\logical_op__rc__ok$34$next[0:0]$10153 + assign $1\logical_op__rc__rc$33$next[0:0]$10136 $2\logical_op__rc__rc$33$next[0:0]$10154 + assign $1\logical_op__write_cr0$41$next[0:0]$10137 $2\logical_op__write_cr0$41$next[0:0]$10155 + assign $1\logical_op__zero_a$38$next[0:0]$10138 $2\logical_op__zero_a$38$next[0:0]$10156 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" + switch \p_valid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $2\logical_op__insn$46$next[31:0]$10144 $2\logical_op__data_len$45$next[3:0]$10139 $2\logical_op__is_signed$44$next[0:0]$10149 $2\logical_op__is_32bit$43$next[0:0]$10148 $2\logical_op__output_carry$42$next[0:0]$10152 $2\logical_op__write_cr0$41$next[0:0]$10155 $2\logical_op__invert_out$40$next[0:0]$10147 $2\logical_op__input_carry$39$next[1:0]$10143 $2\logical_op__zero_a$38$next[0:0]$10156 $2\logical_op__invert_in$37$next[0:0]$10146 $2\logical_op__oe__ok$36$next[0:0]$10151 $2\logical_op__oe__oe$35$next[0:0]$10150 $2\logical_op__rc__ok$34$next[0:0]$10153 $2\logical_op__rc__rc$33$next[0:0]$10154 $2\logical_op__imm_data__ok$32$next[0:0]$10142 $2\logical_op__imm_data__data$31$next[63:0]$10141 $2\logical_op__fn_unit$30$next[12:0]$10140 $2\logical_op__insn_type$29$next[6:0]$10145 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } + case + assign $2\logical_op__data_len$45$next[3:0]$10139 \logical_op__data_len$45 + assign $2\logical_op__fn_unit$30$next[12:0]$10140 \logical_op__fn_unit$30 + assign $2\logical_op__imm_data__data$31$next[63:0]$10141 \logical_op__imm_data__data$31 + assign $2\logical_op__imm_data__ok$32$next[0:0]$10142 \logical_op__imm_data__ok$32 + assign $2\logical_op__input_carry$39$next[1:0]$10143 \logical_op__input_carry$39 + assign $2\logical_op__insn$46$next[31:0]$10144 \logical_op__insn$46 + assign $2\logical_op__insn_type$29$next[6:0]$10145 \logical_op__insn_type$29 + assign $2\logical_op__invert_in$37$next[0:0]$10146 \logical_op__invert_in$37 + assign $2\logical_op__invert_out$40$next[0:0]$10147 \logical_op__invert_out$40 + assign $2\logical_op__is_32bit$43$next[0:0]$10148 \logical_op__is_32bit$43 + assign $2\logical_op__is_signed$44$next[0:0]$10149 \logical_op__is_signed$44 + assign $2\logical_op__oe__oe$35$next[0:0]$10150 \logical_op__oe__oe$35 + assign $2\logical_op__oe__ok$36$next[0:0]$10151 \logical_op__oe__ok$36 + assign $2\logical_op__output_carry$42$next[0:0]$10152 \logical_op__output_carry$42 + assign $2\logical_op__rc__ok$34$next[0:0]$10153 \logical_op__rc__ok$34 + assign $2\logical_op__rc__rc$33$next[0:0]$10154 \logical_op__rc__rc$33 + assign $2\logical_op__write_cr0$41$next[0:0]$10155 \logical_op__write_cr0$41 + assign $2\logical_op__zero_a$38$next[0:0]$10156 \logical_op__zero_a$38 + end + case + assign $1\logical_op__data_len$45$next[3:0]$10121 \logical_op__data_len$45 + assign $1\logical_op__fn_unit$30$next[12:0]$10122 \logical_op__fn_unit$30 + assign $1\logical_op__imm_data__data$31$next[63:0]$10123 \logical_op__imm_data__data$31 + assign $1\logical_op__imm_data__ok$32$next[0:0]$10124 \logical_op__imm_data__ok$32 + assign $1\logical_op__input_carry$39$next[1:0]$10125 \logical_op__input_carry$39 + assign $1\logical_op__insn$46$next[31:0]$10126 \logical_op__insn$46 + assign $1\logical_op__insn_type$29$next[6:0]$10127 \logical_op__insn_type$29 + assign $1\logical_op__invert_in$37$next[0:0]$10128 \logical_op__invert_in$37 + assign $1\logical_op__invert_out$40$next[0:0]$10129 \logical_op__invert_out$40 + assign $1\logical_op__is_32bit$43$next[0:0]$10130 \logical_op__is_32bit$43 + assign $1\logical_op__is_signed$44$next[0:0]$10131 \logical_op__is_signed$44 + assign $1\logical_op__oe__oe$35$next[0:0]$10132 \logical_op__oe__oe$35 + assign $1\logical_op__oe__ok$36$next[0:0]$10133 \logical_op__oe__ok$36 + assign $1\logical_op__output_carry$42$next[0:0]$10134 \logical_op__output_carry$42 + assign $1\logical_op__rc__ok$34$next[0:0]$10135 \logical_op__rc__ok$34 + assign $1\logical_op__rc__rc$33$next[0:0]$10136 \logical_op__rc__rc$33 + assign $1\logical_op__write_cr0$41$next[0:0]$10137 \logical_op__write_cr0$41 + assign $1\logical_op__zero_a$38$next[0:0]$10138 \logical_op__zero_a$38 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $3\logical_op__imm_data__data$31$next[63:0]$10157 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\logical_op__imm_data__ok$32$next[0:0]$10158 1'0 + assign $3\logical_op__rc__rc$33$next[0:0]$10162 1'0 + assign $3\logical_op__rc__ok$34$next[0:0]$10161 1'0 + assign $3\logical_op__oe__oe$35$next[0:0]$10159 1'0 + assign $3\logical_op__oe__ok$36$next[0:0]$10160 1'0 + case + assign $3\logical_op__imm_data__data$31$next[63:0]$10157 $1\logical_op__imm_data__data$31$next[63:0]$10123 + assign $3\logical_op__imm_data__ok$32$next[0:0]$10158 $1\logical_op__imm_data__ok$32$next[0:0]$10124 + assign $3\logical_op__oe__oe$35$next[0:0]$10159 $1\logical_op__oe__oe$35$next[0:0]$10132 + assign $3\logical_op__oe__ok$36$next[0:0]$10160 $1\logical_op__oe__ok$36$next[0:0]$10133 + assign $3\logical_op__rc__ok$34$next[0:0]$10161 $1\logical_op__rc__ok$34$next[0:0]$10135 + assign $3\logical_op__rc__rc$33$next[0:0]$10162 $1\logical_op__rc__rc$33$next[0:0]$10136 + end + sync always + update \logical_op__data_len$45$next $0\logical_op__data_len$45$next[3:0]$10103 + update \logical_op__fn_unit$30$next $0\logical_op__fn_unit$30$next[12:0]$10104 + update \logical_op__imm_data__data$31$next $0\logical_op__imm_data__data$31$next[63:0]$10105 + update \logical_op__imm_data__ok$32$next $0\logical_op__imm_data__ok$32$next[0:0]$10106 + update \logical_op__input_carry$39$next $0\logical_op__input_carry$39$next[1:0]$10107 + update \logical_op__insn$46$next $0\logical_op__insn$46$next[31:0]$10108 + update \logical_op__insn_type$29$next $0\logical_op__insn_type$29$next[6:0]$10109 + update \logical_op__invert_in$37$next $0\logical_op__invert_in$37$next[0:0]$10110 + update \logical_op__invert_out$40$next $0\logical_op__invert_out$40$next[0:0]$10111 + update \logical_op__is_32bit$43$next $0\logical_op__is_32bit$43$next[0:0]$10112 + update \logical_op__is_signed$44$next $0\logical_op__is_signed$44$next[0:0]$10113 + update \logical_op__oe__oe$35$next $0\logical_op__oe__oe$35$next[0:0]$10114 + update \logical_op__oe__ok$36$next $0\logical_op__oe__ok$36$next[0:0]$10115 + update \logical_op__output_carry$42$next $0\logical_op__output_carry$42$next[0:0]$10116 + update \logical_op__rc__ok$34$next $0\logical_op__rc__ok$34$next[0:0]$10117 + update \logical_op__rc__rc$33$next $0\logical_op__rc__rc$33$next[0:0]$10118 + update \logical_op__write_cr0$41$next $0\logical_op__write_cr0$41$next[0:0]$10119 + update \logical_op__zero_a$38$next $0\logical_op__zero_a$38$next[0:0]$10120 + end + attribute \src "libresoc.v:176363.3-176377.6" + process $proc$libresoc.v:176363$10163 + assign { } { } + assign { } { } + assign $0\ra$47$next[63:0]$10164 $1\ra$47$next[63:0]$10165 + attribute \src "libresoc.v:176364.5-176364.29" + switch \initial + attribute \src "libresoc.v:176364.9-176364.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" + switch \empty + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ra$47$next[63:0]$10165 $2\ra$47$next[63:0]$10166 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" + switch \p_valid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ra$47$next[63:0]$10166 \ra + case + assign $2\ra$47$next[63:0]$10166 \ra$47 + end + case + assign $1\ra$47$next[63:0]$10165 \ra$47 + end + sync always + update \ra$47$next $0\ra$47$next[63:0]$10164 + end + attribute \src "libresoc.v:176378.3-176392.6" + process $proc$libresoc.v:176378$10167 + assign { } { } + assign { } { } + assign $0\rb$48$next[63:0]$10168 $1\rb$48$next[63:0]$10169 + attribute \src "libresoc.v:176379.5-176379.29" + switch \initial + attribute \src "libresoc.v:176379.9-176379.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" + switch \empty + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rb$48$next[63:0]$10169 $2\rb$48$next[63:0]$10170 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" + switch \p_valid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\rb$48$next[63:0]$10170 \rb + case + assign $2\rb$48$next[63:0]$10170 \rb$48 + end + case + assign $1\rb$48$next[63:0]$10169 \rb$48 + end + sync always + update \rb$48$next $0\rb$48$next[63:0]$10168 + end + attribute \src "libresoc.v:176393.3-176407.6" + process $proc$libresoc.v:176393$10171 + assign { } { } + assign { } { } + assign $0\xer_so$49$next[0:0]$10172 $1\xer_so$49$next[0:0]$10173 + attribute \src "libresoc.v:176394.5-176394.29" + switch \initial + attribute \src "libresoc.v:176394.9-176394.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" + switch \empty + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\xer_so$49$next[0:0]$10173 $2\xer_so$49$next[0:0]$10174 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" + switch \p_valid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\xer_so$49$next[0:0]$10174 \xer_so + case + assign $2\xer_so$49$next[0:0]$10174 \xer_so$49 + end + case + assign $1\xer_so$49$next[0:0]$10173 \xer_so$49 + end + sync always + update \xer_so$49$next $0\xer_so$49$next[0:0]$10172 + end + attribute \src "libresoc.v:176408.3-176422.6" + process $proc$libresoc.v:176408$10175 + assign { } { } + assign { } { } + assign $0\divisor_neg$50$next[0:0]$10176 $1\divisor_neg$50$next[0:0]$10177 + attribute \src "libresoc.v:176409.5-176409.29" + switch \initial + attribute \src "libresoc.v:176409.9-176409.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" + switch \empty + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\divisor_neg$50$next[0:0]$10177 $2\divisor_neg$50$next[0:0]$10178 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" + switch \p_valid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\divisor_neg$50$next[0:0]$10178 \divisor_neg + case + assign $2\divisor_neg$50$next[0:0]$10178 \divisor_neg$50 + end + case + assign $1\divisor_neg$50$next[0:0]$10177 \divisor_neg$50 + end + sync always + update \divisor_neg$50$next $0\divisor_neg$50$next[0:0]$10176 + end + attribute \src "libresoc.v:176423.3-176437.6" + process $proc$libresoc.v:176423$10179 + assign { } { } + assign { } { } + assign $0\dividend_neg$51$next[0:0]$10180 $1\dividend_neg$51$next[0:0]$10181 + attribute \src "libresoc.v:176424.5-176424.29" + switch \initial + attribute \src "libresoc.v:176424.9-176424.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" + switch \empty + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dividend_neg$51$next[0:0]$10181 $2\dividend_neg$51$next[0:0]$10182 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" + switch \p_valid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\dividend_neg$51$next[0:0]$10182 \dividend_neg + case + assign $2\dividend_neg$51$next[0:0]$10182 \dividend_neg$51 + end + case + assign $1\dividend_neg$51$next[0:0]$10181 \dividend_neg$51 + end + sync always + update \dividend_neg$51$next $0\dividend_neg$51$next[0:0]$10180 + end + attribute \src "libresoc.v:176438.3-176452.6" + process $proc$libresoc.v:176438$10183 + assign { } { } + assign { } { } + assign $0\dive_abs_ov32$52$next[0:0]$10184 $1\dive_abs_ov32$52$next[0:0]$10185 + attribute \src "libresoc.v:176439.5-176439.29" + switch \initial + attribute \src "libresoc.v:176439.9-176439.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" + switch \empty + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dive_abs_ov32$52$next[0:0]$10185 $2\dive_abs_ov32$52$next[0:0]$10186 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" + switch \p_valid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\dive_abs_ov32$52$next[0:0]$10186 \dive_abs_ov32 + case + assign $2\dive_abs_ov32$52$next[0:0]$10186 \dive_abs_ov32$52 + end + case + assign $1\dive_abs_ov32$52$next[0:0]$10185 \dive_abs_ov32$52 + end + sync always + update \dive_abs_ov32$52$next $0\dive_abs_ov32$52$next[0:0]$10184 + end + attribute \src "libresoc.v:176453.3-176467.6" + process $proc$libresoc.v:176453$10187 + assign { } { } + assign { } { } + assign $0\dive_abs_ov64$53$next[0:0]$10188 $1\dive_abs_ov64$53$next[0:0]$10189 + attribute \src "libresoc.v:176454.5-176454.29" + switch \initial + attribute \src "libresoc.v:176454.9-176454.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" + switch \empty + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dive_abs_ov64$53$next[0:0]$10189 $2\dive_abs_ov64$53$next[0:0]$10190 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" + switch \p_valid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\dive_abs_ov64$53$next[0:0]$10190 \dive_abs_ov64 + case + assign $2\dive_abs_ov64$53$next[0:0]$10190 \dive_abs_ov64$53 + end + case + assign $1\dive_abs_ov64$53$next[0:0]$10189 \dive_abs_ov64$53 + end + sync always + update \dive_abs_ov64$53$next $0\dive_abs_ov64$53$next[0:0]$10188 + end + attribute \src "libresoc.v:176468.3-176482.6" + process $proc$libresoc.v:176468$10191 + assign { } { } + assign { } { } + assign $0\div_by_zero$54$next[0:0]$10192 $1\div_by_zero$54$next[0:0]$10193 + attribute \src "libresoc.v:176469.5-176469.29" + switch \initial + attribute \src "libresoc.v:176469.9-176469.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" + switch \empty + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\div_by_zero$54$next[0:0]$10193 $2\div_by_zero$54$next[0:0]$10194 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" + switch \p_valid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\div_by_zero$54$next[0:0]$10194 \div_by_zero + case + assign $2\div_by_zero$54$next[0:0]$10194 \div_by_zero$54 + end + case + assign $1\div_by_zero$54$next[0:0]$10193 \div_by_zero$54 + end + sync always + update \div_by_zero$54$next $0\div_by_zero$54$next[0:0]$10192 + end + attribute \src "libresoc.v:176483.3-176497.6" + process $proc$libresoc.v:176483$10195 + assign { } { } + assign { } { } + assign $0\dividend$68$next[127:0]$10196 $1\dividend$68$next[127:0]$10197 + attribute \src "libresoc.v:176484.5-176484.29" + switch \initial + attribute \src "libresoc.v:176484.9-176484.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" + switch \empty + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dividend$68$next[127:0]$10197 $2\dividend$68$next[127:0]$10198 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" + switch \p_valid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\dividend$68$next[127:0]$10198 \dividend + case + assign $2\dividend$68$next[127:0]$10198 \dividend$68 + end + case + assign $1\dividend$68$next[127:0]$10197 \dividend$68 + end + sync always + update \dividend$68$next $0\dividend$68$next[127:0]$10196 + end + attribute \src "libresoc.v:176498.3-176512.6" + process $proc$libresoc.v:176498$10199 + assign { } { } + assign { } { } + assign $0\divisor_radicand$65$next[63:0]$10200 $1\divisor_radicand$65$next[63:0]$10201 + attribute \src "libresoc.v:176499.5-176499.29" + switch \initial + attribute \src "libresoc.v:176499.9-176499.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" + switch \empty + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\divisor_radicand$65$next[63:0]$10201 $2\divisor_radicand$65$next[63:0]$10202 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" + switch \p_valid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\divisor_radicand$65$next[63:0]$10202 \divisor_radicand + case + assign $2\divisor_radicand$65$next[63:0]$10202 \divisor_radicand$65 + end + case + assign $1\divisor_radicand$65$next[63:0]$10201 \divisor_radicand$65 + end + sync always + update \divisor_radicand$65$next $0\divisor_radicand$65$next[63:0]$10200 + end + attribute \src "libresoc.v:176513.3-176527.6" + process $proc$libresoc.v:176513$10203 + assign { } { } + assign { } { } + assign $0\operation$69$next[1:0]$10204 $1\operation$69$next[1:0]$10205 + attribute \src "libresoc.v:176514.5-176514.29" + switch \initial + attribute \src "libresoc.v:176514.9-176514.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" + switch \empty + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\operation$69$next[1:0]$10205 $2\operation$69$next[1:0]$10206 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" + switch \p_valid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\operation$69$next[1:0]$10206 \operation + case + assign $2\operation$69$next[1:0]$10206 \operation$69 + end + case + assign $1\operation$69$next[1:0]$10205 \operation$69 + end + sync always + update \operation$69$next $0\operation$69$next[1:0]$10204 + end + connect \$56 $sshl$libresoc.v:176130$10013_Y + connect \$55 $pos$libresoc.v:176131$10015_Y + connect \$59 $not$libresoc.v:176132$10016_Y + connect \$61 $ge$libresoc.v:176133$10017_Y + connect \$63 $and$libresoc.v:176134$10018_Y + connect \$66 $and$libresoc.v:176135$10019_Y + connect \p_ready_o \empty + connect \n_valid_o \$63 + connect \remainder \$55 + connect \quotient_root \div_state_next_o_dividend_quotient [63:0] + connect \div_by_zero$27 \div_by_zero$54 + connect \dive_abs_ov64$26 \dive_abs_ov64$53 + connect \dive_abs_ov32$25 \dive_abs_ov32$52 + connect \dividend_neg$24 \dividend_neg$51 + connect \divisor_neg$23 \divisor_neg$50 + connect \xer_so$22 \xer_so$49 + connect \rb$21 \rb$48 + connect \ra$20 \ra$47 + connect { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn$46 \logical_op__data_len$45 \logical_op__is_signed$44 \logical_op__is_32bit$43 \logical_op__output_carry$42 \logical_op__write_cr0$41 \logical_op__invert_out$40 \logical_op__input_carry$39 \logical_op__zero_a$38 \logical_op__invert_in$37 \logical_op__oe__ok$36 \logical_op__oe__oe$35 \logical_op__rc__ok$34 \logical_op__rc__rc$33 \logical_op__imm_data__ok$32 \logical_op__imm_data__data$31 \logical_op__fn_unit$30 \logical_op__insn_type$29 } + connect \muxid$1 \muxid$28 + connect \div_state_init_dividend \dividend +end +attribute \src "libresoc.v:176547.1-178078.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_start" +attribute \generator "nMigen" +module \pipe_start + attribute \src "libresoc.v:177884.3-177896.6" + wire $0\div_by_zero$next[0:0]$10316 + attribute \src "libresoc.v:177670.3-177671.39" + wire $0\div_by_zero[0:0] + attribute \src "libresoc.v:177858.3-177870.6" + wire $0\dive_abs_ov32$next[0:0]$10310 + attribute \src "libresoc.v:177674.3-177675.43" + wire $0\dive_abs_ov32[0:0] + attribute \src "libresoc.v:177871.3-177883.6" + wire $0\dive_abs_ov64$next[0:0]$10313 + attribute \src "libresoc.v:177672.3-177673.43" + wire $0\dive_abs_ov64[0:0] + attribute \src "libresoc.v:177897.3-177909.6" + wire width 128 $0\dividend$next[127:0]$10319 + attribute \src "libresoc.v:177668.3-177669.33" + wire width 128 $0\dividend[127:0] + attribute \src "libresoc.v:177845.3-177857.6" + wire $0\dividend_neg$next[0:0]$10307 + attribute \src "libresoc.v:177676.3-177677.41" + wire $0\dividend_neg[0:0] + attribute \src "libresoc.v:177832.3-177844.6" + wire $0\divisor_neg$next[0:0]$10304 + attribute \src "libresoc.v:177678.3-177679.39" + wire $0\divisor_neg[0:0] + attribute \src "libresoc.v:177910.3-177922.6" + wire width 64 $0\divisor_radicand$next[63:0]$10322 + attribute \src "libresoc.v:177666.3-177667.49" + wire width 64 $0\divisor_radicand[63:0] + attribute \src "libresoc.v:176548.7-176548.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:177967.3-178008.6" + wire width 4 $0\logical_op__data_len$next[3:0]$10335 + attribute \src "libresoc.v:177718.3-177719.57" + wire width 4 $0\logical_op__data_len[3:0] + attribute \src "libresoc.v:177967.3-178008.6" + wire width 13 $0\logical_op__fn_unit$next[12:0]$10336 + attribute \src "libresoc.v:177688.3-177689.55" + wire width 13 $0\logical_op__fn_unit[12:0] + attribute \src "libresoc.v:177967.3-178008.6" + wire width 64 $0\logical_op__imm_data__data$next[63:0]$10337 + attribute \src "libresoc.v:177690.3-177691.69" + wire width 64 $0\logical_op__imm_data__data[63:0] + attribute \src "libresoc.v:177967.3-178008.6" + wire $0\logical_op__imm_data__ok$next[0:0]$10338 + attribute \src "libresoc.v:177692.3-177693.65" + wire $0\logical_op__imm_data__ok[0:0] + attribute \src "libresoc.v:177967.3-178008.6" + wire width 2 $0\logical_op__input_carry$next[1:0]$10339 + attribute \src "libresoc.v:177706.3-177707.63" + wire width 2 $0\logical_op__input_carry[1:0] + attribute \src "libresoc.v:177967.3-178008.6" + wire width 32 $0\logical_op__insn$next[31:0]$10340 + attribute \src "libresoc.v:177720.3-177721.49" + wire width 32 $0\logical_op__insn[31:0] + attribute \src "libresoc.v:177967.3-178008.6" + wire width 7 $0\logical_op__insn_type$next[6:0]$10341 + attribute \src "libresoc.v:177686.3-177687.59" + wire width 7 $0\logical_op__insn_type[6:0] + attribute \src "libresoc.v:177967.3-178008.6" + wire $0\logical_op__invert_in$next[0:0]$10342 + attribute \src "libresoc.v:177702.3-177703.59" + wire $0\logical_op__invert_in[0:0] + attribute \src "libresoc.v:177967.3-178008.6" + wire $0\logical_op__invert_out$next[0:0]$10343 + attribute \src "libresoc.v:177708.3-177709.61" + wire $0\logical_op__invert_out[0:0] + attribute \src "libresoc.v:177967.3-178008.6" + wire $0\logical_op__is_32bit$next[0:0]$10344 + attribute \src "libresoc.v:177714.3-177715.57" + wire $0\logical_op__is_32bit[0:0] + attribute \src "libresoc.v:177967.3-178008.6" + wire $0\logical_op__is_signed$next[0:0]$10345 + attribute \src "libresoc.v:177716.3-177717.59" + wire $0\logical_op__is_signed[0:0] + attribute \src "libresoc.v:177967.3-178008.6" + wire $0\logical_op__oe__oe$next[0:0]$10346 + attribute \src "libresoc.v:177698.3-177699.53" + wire $0\logical_op__oe__oe[0:0] + attribute \src "libresoc.v:177967.3-178008.6" + wire $0\logical_op__oe__ok$next[0:0]$10347 + attribute \src "libresoc.v:177700.3-177701.53" + wire $0\logical_op__oe__ok[0:0] + attribute \src "libresoc.v:177967.3-178008.6" + wire $0\logical_op__output_carry$next[0:0]$10348 + attribute \src "libresoc.v:177712.3-177713.65" + wire $0\logical_op__output_carry[0:0] + attribute \src "libresoc.v:177967.3-178008.6" + wire $0\logical_op__rc__ok$next[0:0]$10349 + attribute \src "libresoc.v:177696.3-177697.53" + wire $0\logical_op__rc__ok[0:0] + attribute \src "libresoc.v:177967.3-178008.6" + wire $0\logical_op__rc__rc$next[0:0]$10350 + attribute \src "libresoc.v:177694.3-177695.53" + wire $0\logical_op__rc__rc[0:0] + attribute \src "libresoc.v:177967.3-178008.6" + wire $0\logical_op__write_cr0$next[0:0]$10351 + attribute \src "libresoc.v:177710.3-177711.59" + wire $0\logical_op__write_cr0[0:0] + attribute \src "libresoc.v:177967.3-178008.6" + wire $0\logical_op__zero_a$next[0:0]$10352 + attribute \src "libresoc.v:177704.3-177705.53" + wire $0\logical_op__zero_a[0:0] + attribute \src "libresoc.v:177954.3-177966.6" + wire width 2 $0\muxid$next[1:0]$10332 + attribute \src "libresoc.v:177722.3-177723.27" + wire width 2 $0\muxid[1:0] + attribute \src "libresoc.v:177923.3-177935.6" + wire width 2 $0\operation$next[1:0]$10325 + attribute \src "libresoc.v:177664.3-177665.35" + wire width 2 $0\operation[1:0] + attribute \src "libresoc.v:177936.3-177953.6" + wire $0\r_busy$next[0:0]$10328 + attribute \src "libresoc.v:177724.3-177725.29" + wire $0\r_busy[0:0] + attribute \src "libresoc.v:178009.3-178021.6" + wire width 64 $0\ra$next[63:0]$10378 + attribute \src "libresoc.v:177684.3-177685.21" + wire width 64 $0\ra[63:0] + attribute \src "libresoc.v:178022.3-178034.6" + wire width 64 $0\rb$next[63:0]$10381 + attribute \src "libresoc.v:177682.3-177683.21" + wire width 64 $0\rb[63:0] + attribute \src "libresoc.v:178035.3-178047.6" + wire $0\xer_so$next[0:0]$10384 + attribute \src "libresoc.v:177680.3-177681.29" + wire $0\xer_so[0:0] + attribute \src "libresoc.v:177884.3-177896.6" + wire $1\div_by_zero$next[0:0]$10317 + attribute \src "libresoc.v:176557.7-176557.25" + wire $1\div_by_zero[0:0] + attribute \src "libresoc.v:177858.3-177870.6" + wire $1\dive_abs_ov32$next[0:0]$10311 + attribute \src "libresoc.v:176564.7-176564.27" + wire $1\dive_abs_ov32[0:0] + attribute \src "libresoc.v:177871.3-177883.6" + wire $1\dive_abs_ov64$next[0:0]$10314 + attribute \src "libresoc.v:176571.7-176571.27" + wire $1\dive_abs_ov64[0:0] + attribute \src "libresoc.v:177897.3-177909.6" + wire width 128 $1\dividend$next[127:0]$10320 + attribute \src "libresoc.v:176578.15-176578.63" + wire width 128 $1\dividend[127:0] + attribute \src "libresoc.v:177845.3-177857.6" + wire $1\dividend_neg$next[0:0]$10308 + attribute \src "libresoc.v:176585.7-176585.26" + wire $1\dividend_neg[0:0] + attribute \src "libresoc.v:177832.3-177844.6" + wire $1\divisor_neg$next[0:0]$10305 + attribute \src "libresoc.v:176592.7-176592.25" + wire $1\divisor_neg[0:0] + attribute \src "libresoc.v:177910.3-177922.6" + wire width 64 $1\divisor_radicand$next[63:0]$10323 + attribute \src "libresoc.v:176599.14-176599.53" + wire width 64 $1\divisor_radicand[63:0] + attribute \src "libresoc.v:177967.3-178008.6" + wire width 4 $1\logical_op__data_len$next[3:0]$10353 + attribute \src "libresoc.v:176878.13-176878.40" + wire width 4 $1\logical_op__data_len[3:0] + attribute \src "libresoc.v:177967.3-178008.6" + wire width 13 $1\logical_op__fn_unit$next[12:0]$10354 + attribute \src "libresoc.v:176901.14-176901.44" + wire width 13 $1\logical_op__fn_unit[12:0] + attribute \src "libresoc.v:177967.3-178008.6" + wire width 64 $1\logical_op__imm_data__data$next[63:0]$10355 + attribute \src "libresoc.v:176938.14-176938.63" + wire width 64 $1\logical_op__imm_data__data[63:0] + attribute \src "libresoc.v:177967.3-178008.6" + wire $1\logical_op__imm_data__ok$next[0:0]$10356 + attribute \src "libresoc.v:176947.7-176947.38" + wire $1\logical_op__imm_data__ok[0:0] + attribute \src "libresoc.v:177967.3-178008.6" + wire width 2 $1\logical_op__input_carry$next[1:0]$10357 + attribute \src "libresoc.v:176960.13-176960.43" + wire width 2 $1\logical_op__input_carry[1:0] + attribute \src "libresoc.v:177967.3-178008.6" + wire width 32 $1\logical_op__insn$next[31:0]$10358 + attribute \src "libresoc.v:176977.14-176977.38" + wire width 32 $1\logical_op__insn[31:0] + attribute \src "libresoc.v:177967.3-178008.6" + wire width 7 $1\logical_op__insn_type$next[6:0]$10359 + attribute \src "libresoc.v:177060.13-177060.42" + wire width 7 $1\logical_op__insn_type[6:0] + attribute \src "libresoc.v:177967.3-178008.6" + wire $1\logical_op__invert_in$next[0:0]$10360 + attribute \src "libresoc.v:177217.7-177217.35" + wire $1\logical_op__invert_in[0:0] + attribute \src "libresoc.v:177967.3-178008.6" + wire $1\logical_op__invert_out$next[0:0]$10361 + attribute \src "libresoc.v:177226.7-177226.36" + wire $1\logical_op__invert_out[0:0] + attribute \src "libresoc.v:177967.3-178008.6" + wire $1\logical_op__is_32bit$next[0:0]$10362 + attribute \src "libresoc.v:177235.7-177235.34" + wire $1\logical_op__is_32bit[0:0] + attribute \src "libresoc.v:177967.3-178008.6" + wire $1\logical_op__is_signed$next[0:0]$10363 + attribute \src "libresoc.v:177244.7-177244.35" + wire $1\logical_op__is_signed[0:0] + attribute \src "libresoc.v:177967.3-178008.6" + wire $1\logical_op__oe__oe$next[0:0]$10364 + attribute \src "libresoc.v:177253.7-177253.32" + wire $1\logical_op__oe__oe[0:0] + attribute \src "libresoc.v:177967.3-178008.6" + wire $1\logical_op__oe__ok$next[0:0]$10365 + attribute \src "libresoc.v:177262.7-177262.32" + wire $1\logical_op__oe__ok[0:0] + attribute \src "libresoc.v:177967.3-178008.6" + wire $1\logical_op__output_carry$next[0:0]$10366 + attribute \src "libresoc.v:177271.7-177271.38" + wire $1\logical_op__output_carry[0:0] + attribute \src "libresoc.v:177967.3-178008.6" + wire $1\logical_op__rc__ok$next[0:0]$10367 + attribute \src "libresoc.v:177280.7-177280.32" + wire $1\logical_op__rc__ok[0:0] + attribute \src "libresoc.v:177967.3-178008.6" + wire $1\logical_op__rc__rc$next[0:0]$10368 + attribute \src "libresoc.v:177289.7-177289.32" + wire $1\logical_op__rc__rc[0:0] + attribute \src "libresoc.v:177967.3-178008.6" + wire $1\logical_op__write_cr0$next[0:0]$10369 + attribute \src "libresoc.v:177298.7-177298.35" + wire $1\logical_op__write_cr0[0:0] + attribute \src "libresoc.v:177967.3-178008.6" + wire $1\logical_op__zero_a$next[0:0]$10370 + attribute \src "libresoc.v:177307.7-177307.32" + wire $1\logical_op__zero_a[0:0] + attribute \src "libresoc.v:177954.3-177966.6" + wire width 2 $1\muxid$next[1:0]$10333 + attribute \src "libresoc.v:177316.13-177316.25" + wire width 2 $1\muxid[1:0] + attribute \src "libresoc.v:177923.3-177935.6" + wire width 2 $1\operation$next[1:0]$10326 + attribute \src "libresoc.v:177331.13-177331.29" + wire width 2 $1\operation[1:0] + attribute \src "libresoc.v:177936.3-177953.6" + wire $1\r_busy$next[0:0]$10329 + attribute \src "libresoc.v:177345.7-177345.20" + wire $1\r_busy[0:0] + attribute \src "libresoc.v:178009.3-178021.6" + wire width 64 $1\ra$next[63:0]$10379 + attribute \src "libresoc.v:177350.14-177350.39" + wire width 64 $1\ra[63:0] + attribute \src "libresoc.v:178022.3-178034.6" + wire width 64 $1\rb$next[63:0]$10382 + attribute \src "libresoc.v:177361.14-177361.39" + wire width 64 $1\rb[63:0] + attribute \src "libresoc.v:178035.3-178047.6" + wire $1\xer_so$next[0:0]$10385 + attribute \src "libresoc.v:177656.7-177656.20" + wire $1\xer_so[0:0] + attribute \src "libresoc.v:177967.3-178008.6" + wire width 64 $2\logical_op__imm_data__data$next[63:0]$10371 + attribute \src "libresoc.v:177967.3-178008.6" + wire $2\logical_op__imm_data__ok$next[0:0]$10372 + attribute \src "libresoc.v:177967.3-178008.6" + wire $2\logical_op__oe__oe$next[0:0]$10373 + attribute \src "libresoc.v:177967.3-178008.6" + wire $2\logical_op__oe__ok$next[0:0]$10374 + attribute \src "libresoc.v:177967.3-178008.6" + wire $2\logical_op__rc__ok$next[0:0]$10375 + attribute \src "libresoc.v:177967.3-178008.6" + wire $2\logical_op__rc__rc$next[0:0]$10376 + attribute \src "libresoc.v:177936.3-177953.6" + wire $2\r_busy$next[0:0]$10330 + attribute \src "libresoc.v:177663.18-177663.118" + wire $and$libresoc.v:177663$10271_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" + wire \$66 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 58 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire output 30 \div_by_zero + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire \div_by_zero$96 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire \div_by_zero$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire output 28 \dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire \dive_abs_ov32$94 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire \dive_abs_ov32$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire output 29 \dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire \dive_abs_ov64$95 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire \dive_abs_ov64$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" + wire width 128 output 31 \dividend + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" + wire width 128 \dividend$97 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" + wire width 128 \dividend$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire output 27 \dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire \dividend_neg$93 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire \dividend_neg$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire output 26 \divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire \divisor_neg$92 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire \divisor_neg$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" + wire width 64 output 32 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" + wire width 64 \divisor_radicand$98 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" + wire width 64 \divisor_radicand$next + attribute \src "libresoc.v:176548.7-176548.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \input_logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \input_logical_op__data_len$40 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \input_logical_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \input_logical_op__fn_unit$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \input_logical_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \input_logical_op__imm_data__data$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__imm_data__ok$27 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \input_logical_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \input_logical_op__input_carry$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \input_logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \input_logical_op__insn$41 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \input_logical_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \input_logical_op__insn_type$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__invert_in$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__invert_out$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__is_32bit$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__is_signed$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__oe__oe$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__oe__ok$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__output_carry$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__rc__ok$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__rc__rc$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__write_cr0$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__zero_a$33 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \input_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \input_muxid$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_ra$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_rb$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \input_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \input_xer_so$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 21 \logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 53 \logical_op__data_len$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \logical_op__data_len$85 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \logical_op__data_len$next + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 output 6 \logical_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 input 38 \logical_op__fn_unit$3 + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \logical_op__fn_unit$70 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \logical_op__fn_unit$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 7 \logical_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 39 \logical_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \logical_op__imm_data__data$71 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \logical_op__imm_data__data$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 8 \logical_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 40 \logical_op__imm_data__ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__imm_data__ok$72 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__imm_data__ok$next + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 15 \logical_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 47 \logical_op__input_carry$12 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \logical_op__input_carry$79 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \logical_op__input_carry$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 22 \logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 54 \logical_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \logical_op__insn$86 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \logical_op__insn$next + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 5 \logical_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 37 \logical_op__insn_type$2 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \logical_op__insn_type$69 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \logical_op__insn_type$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 13 \logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 45 \logical_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_in$77 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_in$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 16 \logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 48 \logical_op__invert_out$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_out$80 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_out$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 19 \logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 51 \logical_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_32bit$83 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_32bit$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 20 \logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 52 \logical_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_signed$84 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_signed$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 11 \logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__oe$75 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 43 \logical_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__oe$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 12 \logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__ok$76 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 44 \logical_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 18 \logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 50 \logical_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__output_carry$82 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__output_carry$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 10 \logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 42 \logical_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__ok$74 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 9 \logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 41 \logical_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__rc$73 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__rc$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 17 \logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 49 \logical_op__write_cr0$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__write_cr0$81 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__write_cr0$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 14 \logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 46 \logical_op__zero_a$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__zero_a$78 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__zero_a$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 output 4 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 input 36 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid$68 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 \muxid$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + wire \n_i_rdy_data + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" + wire input 3 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" + wire output 2 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" + wire width 2 output 33 \operation + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" + wire width 2 \operation$99 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" + wire width 2 \operation$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" + wire output 35 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" + wire input 34 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" + wire \p_valid_i$65 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" + wire \p_valid_i_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire \r_busy$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 23 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 55 \ra$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \ra$87 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \ra$88 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \ra$next + 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wire \xer_so$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" + cell $and $and$libresoc.v:177663$10271 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i$65 + connect \B \p_ready_o + connect \Y $and$libresoc.v:177663$10271_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:177726.14-177771.4" + cell \input$78 \input + connect \logical_op__data_len \input_logical_op__data_len + connect \logical_op__data_len$18 \input_logical_op__data_len$40 + connect \logical_op__fn_unit \input_logical_op__fn_unit + connect \logical_op__fn_unit$3 \input_logical_op__fn_unit$25 + connect \logical_op__imm_data__data \input_logical_op__imm_data__data + connect \logical_op__imm_data__data$4 \input_logical_op__imm_data__data$26 + connect \logical_op__imm_data__ok \input_logical_op__imm_data__ok + connect \logical_op__imm_data__ok$5 \input_logical_op__imm_data__ok$27 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\input_logical_op__oe__oe$30 + connect \logical_op__oe__ok \input_logical_op__oe__ok + connect \logical_op__oe__ok$9 \input_logical_op__oe__ok$31 + connect \logical_op__output_carry \input_logical_op__output_carry + connect \logical_op__output_carry$15 \input_logical_op__output_carry$37 + connect \logical_op__rc__ok \input_logical_op__rc__ok + connect \logical_op__rc__ok$7 \input_logical_op__rc__ok$29 + connect \logical_op__rc__rc \input_logical_op__rc__rc + connect \logical_op__rc__rc$6 \input_logical_op__rc__rc$28 + connect \logical_op__write_cr0 \input_logical_op__write_cr0 + connect \logical_op__write_cr0$14 \input_logical_op__write_cr0$36 + connect \logical_op__zero_a \input_logical_op__zero_a + connect \logical_op__zero_a$11 \input_logical_op__zero_a$33 + connect \muxid \input_muxid + connect \muxid$1 \input_muxid$23 + connect \ra \input_ra + connect \ra$20 \input_ra$42 + connect \rb \input_rb + connect \rb$21 \input_rb$43 + connect \xer_so \input_xer_so + connect \xer_so$22 \input_xer_so$44 + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:177772.10-177775.4" + cell \n$77 \n + connect \n_ready_i \n_ready_i + connect \n_valid_o \n_valid_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:177776.10-177779.4" + cell \p$76 \p + connect \p_ready_o \p_ready_o + connect \p_valid_i \p_valid_i + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:177780.15-177831.4" + cell \setup_stage \setup_stage + connect \div_by_zero \setup_stage_div_by_zero + connect \dive_abs_ov32 \setup_stage_dive_abs_ov32 + connect \dive_abs_ov64 \setup_stage_dive_abs_ov64 + connect \dividend \setup_stage_dividend + connect \dividend_neg \setup_stage_dividend_neg + connect \divisor_neg \setup_stage_divisor_neg + connect \divisor_radicand \setup_stage_divisor_radicand + connect \logical_op__data_len \setup_stage_logical_op__data_len + connect \logical_op__data_len$18 \setup_stage_logical_op__data_len$62 + connect \logical_op__fn_unit \setup_stage_logical_op__fn_unit + connect \logical_op__fn_unit$3 \setup_stage_logical_op__fn_unit$47 + connect \logical_op__imm_data__data \setup_stage_logical_op__imm_data__data + connect \logical_op__imm_data__data$4 \setup_stage_logical_op__imm_data__data$48 + connect \logical_op__imm_data__ok \setup_stage_logical_op__imm_data__ok + connect \logical_op__imm_data__ok$5 \setup_stage_logical_op__imm_data__ok$49 + connect \logical_op__input_carry \setup_stage_logical_op__input_carry + connect \logical_op__input_carry$12 \setup_stage_logical_op__input_carry$56 + connect \logical_op__insn \setup_stage_logical_op__insn + connect \logical_op__insn$19 \setup_stage_logical_op__insn$63 + connect \logical_op__insn_type \setup_stage_logical_op__insn_type + connect \logical_op__insn_type$2 \setup_stage_logical_op__insn_type$46 + connect \logical_op__invert_in \setup_stage_logical_op__invert_in + connect \logical_op__invert_in$10 \setup_stage_logical_op__invert_in$54 + connect \logical_op__invert_out \setup_stage_logical_op__invert_out + connect \logical_op__invert_out$13 \setup_stage_logical_op__invert_out$57 + connect \logical_op__is_32bit \setup_stage_logical_op__is_32bit + connect \logical_op__is_32bit$16 \setup_stage_logical_op__is_32bit$60 + connect \logical_op__is_signed \setup_stage_logical_op__is_signed + connect \logical_op__is_signed$17 \setup_stage_logical_op__is_signed$61 + connect \logical_op__oe__oe \setup_stage_logical_op__oe__oe + connect \logical_op__oe__oe$8 \setup_stage_logical_op__oe__oe$52 + connect \logical_op__oe__ok \setup_stage_logical_op__oe__ok + connect \logical_op__oe__ok$9 \setup_stage_logical_op__oe__ok$53 + connect \logical_op__output_carry \setup_stage_logical_op__output_carry + connect \logical_op__output_carry$15 \setup_stage_logical_op__output_carry$59 + connect \logical_op__rc__ok \setup_stage_logical_op__rc__ok + connect \logical_op__rc__ok$7 \setup_stage_logical_op__rc__ok$51 + connect \logical_op__rc__rc \setup_stage_logical_op__rc__rc + connect \logical_op__rc__rc$6 \setup_stage_logical_op__rc__rc$50 + connect \logical_op__write_cr0 \setup_stage_logical_op__write_cr0 + connect \logical_op__write_cr0$14 \setup_stage_logical_op__write_cr0$58 + connect \logical_op__zero_a \setup_stage_logical_op__zero_a + connect \logical_op__zero_a$11 \setup_stage_logical_op__zero_a$55 + connect \muxid \setup_stage_muxid + connect \muxid$1 \setup_stage_muxid$45 + connect \operation \setup_stage_operation + connect \ra \setup_stage_ra + connect \rb \setup_stage_rb + connect \xer_so \setup_stage_xer_so + connect \xer_so$20 \setup_stage_xer_so$64 + end + attribute \src "libresoc.v:176548.7-176548.20" + process $proc$libresoc.v:176548$10386 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:176557.7-176557.25" + process $proc$libresoc.v:176557$10387 + assign { } { } + assign $1\div_by_zero[0:0] 1'0 + sync always + sync init + update \div_by_zero $1\div_by_zero[0:0] + end + attribute \src "libresoc.v:176564.7-176564.27" + process $proc$libresoc.v:176564$10388 + assign { } { } + assign $1\dive_abs_ov32[0:0] 1'0 + sync always + sync init + update \dive_abs_ov32 $1\dive_abs_ov32[0:0] + end + attribute \src "libresoc.v:176571.7-176571.27" + process $proc$libresoc.v:176571$10389 + assign { } { } + assign $1\dive_abs_ov64[0:0] 1'0 + sync always + sync init + update \dive_abs_ov64 $1\dive_abs_ov64[0:0] + end + attribute \src "libresoc.v:176578.15-176578.63" + process $proc$libresoc.v:176578$10390 + assign { } { } + assign $1\dividend[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \dividend $1\dividend[127:0] + end + attribute \src "libresoc.v:176585.7-176585.26" + process $proc$libresoc.v:176585$10391 + assign { } { } + assign $1\dividend_neg[0:0] 1'0 + sync always + sync init + update \dividend_neg $1\dividend_neg[0:0] + end + attribute \src "libresoc.v:176592.7-176592.25" + process $proc$libresoc.v:176592$10392 + assign { } { } + assign $1\divisor_neg[0:0] 1'0 + sync always + sync init + update \divisor_neg $1\divisor_neg[0:0] + end + attribute \src "libresoc.v:176599.14-176599.53" + process $proc$libresoc.v:176599$10393 + assign { } { } + assign $1\divisor_radicand[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \divisor_radicand $1\divisor_radicand[63:0] + end + attribute \src "libresoc.v:176878.13-176878.40" + process $proc$libresoc.v:176878$10394 + assign { } { } + assign $1\logical_op__data_len[3:0] 4'0000 + sync always + sync init + update \logical_op__data_len $1\logical_op__data_len[3:0] + end + attribute \src "libresoc.v:176901.14-176901.44" + process $proc$libresoc.v:176901$10395 + assign { } { } + assign $1\logical_op__fn_unit[12:0] 13'0000000000000 + sync always + sync init + update \logical_op__fn_unit $1\logical_op__fn_unit[12:0] + end + attribute \src "libresoc.v:176938.14-176938.63" + process $proc$libresoc.v:176938$10396 + assign { } { } + assign $1\logical_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \logical_op__imm_data__data $1\logical_op__imm_data__data[63:0] + end + attribute \src "libresoc.v:176947.7-176947.38" + process $proc$libresoc.v:176947$10397 + assign { } { } + assign $1\logical_op__imm_data__ok[0:0] 1'0 + sync always + sync init + update \logical_op__imm_data__ok $1\logical_op__imm_data__ok[0:0] + end + attribute \src "libresoc.v:176960.13-176960.43" + process $proc$libresoc.v:176960$10398 + assign { } { } + assign $1\logical_op__input_carry[1:0] 2'00 + sync always + sync init + update \logical_op__input_carry $1\logical_op__input_carry[1:0] + end + attribute \src "libresoc.v:176977.14-176977.38" + process $proc$libresoc.v:176977$10399 + assign { } { } + assign $1\logical_op__insn[31:0] 0 + sync always + sync init + update \logical_op__insn $1\logical_op__insn[31:0] + end + attribute \src "libresoc.v:177060.13-177060.42" + process $proc$libresoc.v:177060$10400 + assign { } { } + assign $1\logical_op__insn_type[6:0] 7'0000000 + sync always + sync init + update \logical_op__insn_type $1\logical_op__insn_type[6:0] + end + attribute \src "libresoc.v:177217.7-177217.35" + process $proc$libresoc.v:177217$10401 + assign { } { } + assign $1\logical_op__invert_in[0:0] 1'0 + sync always + sync init + update \logical_op__invert_in $1\logical_op__invert_in[0:0] + end + attribute \src "libresoc.v:177226.7-177226.36" + process $proc$libresoc.v:177226$10402 + assign { } { } + assign $1\logical_op__invert_out[0:0] 1'0 + sync always + sync init + update \logical_op__invert_out $1\logical_op__invert_out[0:0] + end + attribute \src "libresoc.v:177235.7-177235.34" + process $proc$libresoc.v:177235$10403 + assign { } { } + assign $1\logical_op__is_32bit[0:0] 1'0 + sync always + sync init + update \logical_op__is_32bit $1\logical_op__is_32bit[0:0] + end + attribute \src "libresoc.v:177244.7-177244.35" + process $proc$libresoc.v:177244$10404 + assign { } { } + assign $1\logical_op__is_signed[0:0] 1'0 + sync always + sync init + update \logical_op__is_signed $1\logical_op__is_signed[0:0] + end + attribute \src "libresoc.v:177253.7-177253.32" + process $proc$libresoc.v:177253$10405 + assign { } { } + assign $1\logical_op__oe__oe[0:0] 1'0 + sync always + sync init + update \logical_op__oe__oe $1\logical_op__oe__oe[0:0] + end + attribute \src "libresoc.v:177262.7-177262.32" + process $proc$libresoc.v:177262$10406 + assign { } { } + assign $1\logical_op__oe__ok[0:0] 1'0 + sync always + sync init + update \logical_op__oe__ok $1\logical_op__oe__ok[0:0] + end + attribute \src "libresoc.v:177271.7-177271.38" + process $proc$libresoc.v:177271$10407 + assign { } { } + assign $1\logical_op__output_carry[0:0] 1'0 + sync always + sync init + update \logical_op__output_carry $1\logical_op__output_carry[0:0] + end + attribute \src "libresoc.v:177280.7-177280.32" + process $proc$libresoc.v:177280$10408 + assign { } { } + assign $1\logical_op__rc__ok[0:0] 1'0 + sync always + sync init + update \logical_op__rc__ok $1\logical_op__rc__ok[0:0] + end + attribute \src "libresoc.v:177289.7-177289.32" + process $proc$libresoc.v:177289$10409 + assign { } { } + assign $1\logical_op__rc__rc[0:0] 1'0 + sync always + sync init + update \logical_op__rc__rc $1\logical_op__rc__rc[0:0] + end + attribute \src "libresoc.v:177298.7-177298.35" + process $proc$libresoc.v:177298$10410 + assign { } { } + assign $1\logical_op__write_cr0[0:0] 1'0 + sync always + sync init + update \logical_op__write_cr0 $1\logical_op__write_cr0[0:0] + end + attribute \src "libresoc.v:177307.7-177307.32" + process $proc$libresoc.v:177307$10411 + assign { } { } + assign $1\logical_op__zero_a[0:0] 1'0 + sync always + sync init + update \logical_op__zero_a $1\logical_op__zero_a[0:0] + end + attribute \src "libresoc.v:177316.13-177316.25" + process $proc$libresoc.v:177316$10412 + assign { } { } + assign $1\muxid[1:0] 2'00 + sync always + sync init + update \muxid $1\muxid[1:0] + end + attribute \src "libresoc.v:177331.13-177331.29" + process $proc$libresoc.v:177331$10413 + assign { } { } + assign $1\operation[1:0] 2'00 + sync always + sync init + update \operation $1\operation[1:0] + end + attribute \src "libresoc.v:177345.7-177345.20" + process $proc$libresoc.v:177345$10414 + assign { } { } + assign $1\r_busy[0:0] 1'0 + sync always + sync init + update \r_busy $1\r_busy[0:0] + end + attribute \src "libresoc.v:177350.14-177350.39" + process $proc$libresoc.v:177350$10415 + assign { } { } + assign $1\ra[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \ra $1\ra[63:0] + end + attribute \src "libresoc.v:177361.14-177361.39" + process $proc$libresoc.v:177361$10416 + assign { } { } + assign $1\rb[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \rb $1\rb[63:0] + end + attribute \src "libresoc.v:177656.7-177656.20" + process $proc$libresoc.v:177656$10417 + assign { } { } + assign $1\xer_so[0:0] 1'0 + sync always + sync init + update \xer_so $1\xer_so[0:0] + end + attribute \src "libresoc.v:177664.3-177665.35" + process $proc$libresoc.v:177664$10272 + assign { } { } + assign $0\operation[1:0] \operation$next + sync posedge \coresync_clk + update \operation $0\operation[1:0] + end + attribute \src "libresoc.v:177666.3-177667.49" + process $proc$libresoc.v:177666$10273 + assign { } { } + assign $0\divisor_radicand[63:0] \divisor_radicand$next + sync posedge \coresync_clk + update \divisor_radicand $0\divisor_radicand[63:0] + end + attribute \src "libresoc.v:177668.3-177669.33" + process $proc$libresoc.v:177668$10274 + assign { } { } + assign $0\dividend[127:0] \dividend$next + sync posedge \coresync_clk + update \dividend $0\dividend[127:0] + end + attribute \src "libresoc.v:177670.3-177671.39" + process $proc$libresoc.v:177670$10275 + assign { } { } + assign $0\div_by_zero[0:0] \div_by_zero$next + sync posedge \coresync_clk + update \div_by_zero $0\div_by_zero[0:0] + end + attribute \src "libresoc.v:177672.3-177673.43" + process $proc$libresoc.v:177672$10276 + assign { } { } + assign $0\dive_abs_ov64[0:0] \dive_abs_ov64$next + sync posedge \coresync_clk + update \dive_abs_ov64 $0\dive_abs_ov64[0:0] + end + attribute \src "libresoc.v:177674.3-177675.43" + process $proc$libresoc.v:177674$10277 + assign { } { } + assign $0\dive_abs_ov32[0:0] \dive_abs_ov32$next + sync posedge \coresync_clk + update \dive_abs_ov32 $0\dive_abs_ov32[0:0] + end + attribute \src "libresoc.v:177676.3-177677.41" + process $proc$libresoc.v:177676$10278 + assign { } { } + assign $0\dividend_neg[0:0] \dividend_neg$next + sync posedge \coresync_clk + update \dividend_neg $0\dividend_neg[0:0] + end + attribute \src "libresoc.v:177678.3-177679.39" + process $proc$libresoc.v:177678$10279 + assign { } { } + assign $0\divisor_neg[0:0] \divisor_neg$next + sync posedge \coresync_clk + update \divisor_neg $0\divisor_neg[0:0] + end + attribute \src "libresoc.v:177680.3-177681.29" + process $proc$libresoc.v:177680$10280 + assign { } { } + assign $0\xer_so[0:0] \xer_so$next + sync posedge \coresync_clk + update \xer_so $0\xer_so[0:0] + end + attribute \src "libresoc.v:177682.3-177683.21" + process $proc$libresoc.v:177682$10281 + assign { } { } + assign $0\rb[63:0] \rb$next + sync posedge \coresync_clk + update \rb $0\rb[63:0] + end + attribute \src "libresoc.v:177684.3-177685.21" + process $proc$libresoc.v:177684$10282 + assign { } { } + assign $0\ra[63:0] \ra$next + sync posedge \coresync_clk + update \ra $0\ra[63:0] + end + attribute \src "libresoc.v:177686.3-177687.59" + process $proc$libresoc.v:177686$10283 + assign { } { } + assign $0\logical_op__insn_type[6:0] \logical_op__insn_type$next + sync posedge \coresync_clk + update \logical_op__insn_type $0\logical_op__insn_type[6:0] + end + attribute \src "libresoc.v:177688.3-177689.55" + process $proc$libresoc.v:177688$10284 + assign { } { } + assign $0\logical_op__fn_unit[12:0] \logical_op__fn_unit$next + sync posedge \coresync_clk + update \logical_op__fn_unit $0\logical_op__fn_unit[12:0] + end + attribute \src "libresoc.v:177690.3-177691.69" + process $proc$libresoc.v:177690$10285 + assign { } { } + assign $0\logical_op__imm_data__data[63:0] \logical_op__imm_data__data$next + sync posedge \coresync_clk + update \logical_op__imm_data__data $0\logical_op__imm_data__data[63:0] + end + attribute \src "libresoc.v:177692.3-177693.65" + process $proc$libresoc.v:177692$10286 + assign { } { } + assign $0\logical_op__imm_data__ok[0:0] \logical_op__imm_data__ok$next + sync posedge \coresync_clk + update \logical_op__imm_data__ok $0\logical_op__imm_data__ok[0:0] + end + attribute \src "libresoc.v:177694.3-177695.53" + process $proc$libresoc.v:177694$10287 + assign { } { } + assign $0\logical_op__rc__rc[0:0] \logical_op__rc__rc$next + sync posedge \coresync_clk + update \logical_op__rc__rc $0\logical_op__rc__rc[0:0] + end + attribute \src "libresoc.v:177696.3-177697.53" + process $proc$libresoc.v:177696$10288 + assign { } { } + assign $0\logical_op__rc__ok[0:0] \logical_op__rc__ok$next + sync posedge \coresync_clk + update \logical_op__rc__ok $0\logical_op__rc__ok[0:0] + end + attribute \src "libresoc.v:177698.3-177699.53" + process $proc$libresoc.v:177698$10289 + assign { } { } + assign $0\logical_op__oe__oe[0:0] \logical_op__oe__oe$next + sync posedge \coresync_clk + update \logical_op__oe__oe $0\logical_op__oe__oe[0:0] + end + attribute \src "libresoc.v:177700.3-177701.53" + process $proc$libresoc.v:177700$10290 + assign { } { } + assign $0\logical_op__oe__ok[0:0] \logical_op__oe__ok$next + sync posedge \coresync_clk + update \logical_op__oe__ok $0\logical_op__oe__ok[0:0] + end + attribute \src "libresoc.v:177702.3-177703.59" + process $proc$libresoc.v:177702$10291 + assign { } { } + assign $0\logical_op__invert_in[0:0] \logical_op__invert_in$next + sync posedge \coresync_clk + update \logical_op__invert_in $0\logical_op__invert_in[0:0] + end + attribute \src "libresoc.v:177704.3-177705.53" + process $proc$libresoc.v:177704$10292 + assign { } { } + assign $0\logical_op__zero_a[0:0] \logical_op__zero_a$next + sync posedge \coresync_clk + update \logical_op__zero_a $0\logical_op__zero_a[0:0] + end + attribute \src "libresoc.v:177706.3-177707.63" + process $proc$libresoc.v:177706$10293 + assign { } { } + assign $0\logical_op__input_carry[1:0] \logical_op__input_carry$next + sync posedge \coresync_clk + update \logical_op__input_carry $0\logical_op__input_carry[1:0] + end + attribute \src "libresoc.v:177708.3-177709.61" + process $proc$libresoc.v:177708$10294 + assign { } { } + assign $0\logical_op__invert_out[0:0] \logical_op__invert_out$next + sync posedge \coresync_clk + update \logical_op__invert_out $0\logical_op__invert_out[0:0] + end + attribute \src "libresoc.v:177710.3-177711.59" + process $proc$libresoc.v:177710$10295 + assign { } { } + assign $0\logical_op__write_cr0[0:0] \logical_op__write_cr0$next + sync posedge \coresync_clk + update \logical_op__write_cr0 $0\logical_op__write_cr0[0:0] + end + attribute \src "libresoc.v:177712.3-177713.65" + process $proc$libresoc.v:177712$10296 + assign { } { } + assign $0\logical_op__output_carry[0:0] \logical_op__output_carry$next + sync posedge \coresync_clk + update \logical_op__output_carry $0\logical_op__output_carry[0:0] + end + attribute \src "libresoc.v:177714.3-177715.57" + process $proc$libresoc.v:177714$10297 + assign { } { } + assign $0\logical_op__is_32bit[0:0] \logical_op__is_32bit$next + sync posedge \coresync_clk + update \logical_op__is_32bit $0\logical_op__is_32bit[0:0] + end + attribute \src "libresoc.v:177716.3-177717.59" + process $proc$libresoc.v:177716$10298 + assign { } { } + assign $0\logical_op__is_signed[0:0] \logical_op__is_signed$next + sync posedge \coresync_clk + update \logical_op__is_signed $0\logical_op__is_signed[0:0] + end + attribute \src "libresoc.v:177718.3-177719.57" + process $proc$libresoc.v:177718$10299 + assign { } { } + assign $0\logical_op__data_len[3:0] \logical_op__data_len$next + sync posedge \coresync_clk + update \logical_op__data_len $0\logical_op__data_len[3:0] + end + attribute \src "libresoc.v:177720.3-177721.49" + process $proc$libresoc.v:177720$10300 + assign { } { } + assign $0\logical_op__insn[31:0] \logical_op__insn$next + sync posedge \coresync_clk + update \logical_op__insn $0\logical_op__insn[31:0] + end + attribute \src "libresoc.v:177722.3-177723.27" + process $proc$libresoc.v:177722$10301 + assign { } { } + assign $0\muxid[1:0] \muxid$next + sync posedge \coresync_clk + update \muxid $0\muxid[1:0] + end + attribute \src "libresoc.v:177724.3-177725.29" + process $proc$libresoc.v:177724$10302 + assign { } { } + assign $0\r_busy[0:0] \r_busy$next + sync posedge \coresync_clk + update \r_busy $0\r_busy[0:0] + end + attribute \src "libresoc.v:177832.3-177844.6" + process $proc$libresoc.v:177832$10303 + assign { } { } + assign { } { } + assign $0\divisor_neg$next[0:0]$10304 $1\divisor_neg$next[0:0]$10305 + attribute \src "libresoc.v:177833.5-177833.29" + switch \initial + attribute \src "libresoc.v:177833.9-177833.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\divisor_neg$next[0:0]$10305 \divisor_neg$92 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\divisor_neg$next[0:0]$10305 \divisor_neg$92 + case + assign $1\divisor_neg$next[0:0]$10305 \divisor_neg + end + sync always + update \divisor_neg$next $0\divisor_neg$next[0:0]$10304 + end + attribute \src "libresoc.v:177845.3-177857.6" + process $proc$libresoc.v:177845$10306 + assign { } { } + assign { } { } + assign $0\dividend_neg$next[0:0]$10307 $1\dividend_neg$next[0:0]$10308 + attribute \src "libresoc.v:177846.5-177846.29" + switch \initial + attribute \src "libresoc.v:177846.9-177846.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\dividend_neg$next[0:0]$10308 \dividend_neg$93 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\dividend_neg$next[0:0]$10308 \dividend_neg$93 + case + assign $1\dividend_neg$next[0:0]$10308 \dividend_neg + end + sync always + update \dividend_neg$next $0\dividend_neg$next[0:0]$10307 + end + attribute \src "libresoc.v:177858.3-177870.6" + process $proc$libresoc.v:177858$10309 + assign { } { } + assign { } { } + assign $0\dive_abs_ov32$next[0:0]$10310 $1\dive_abs_ov32$next[0:0]$10311 + attribute \src "libresoc.v:177859.5-177859.29" + switch \initial + attribute \src "libresoc.v:177859.9-177859.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\dive_abs_ov32$next[0:0]$10311 \dive_abs_ov32$94 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\dive_abs_ov32$next[0:0]$10311 \dive_abs_ov32$94 + case + assign $1\dive_abs_ov32$next[0:0]$10311 \dive_abs_ov32 + end + sync always + update \dive_abs_ov32$next $0\dive_abs_ov32$next[0:0]$10310 + end + attribute \src "libresoc.v:177871.3-177883.6" + process $proc$libresoc.v:177871$10312 + assign { } { } + assign { } { } + assign $0\dive_abs_ov64$next[0:0]$10313 $1\dive_abs_ov64$next[0:0]$10314 + attribute \src "libresoc.v:177872.5-177872.29" + switch \initial + attribute \src "libresoc.v:177872.9-177872.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\dive_abs_ov64$next[0:0]$10314 \dive_abs_ov64$95 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\dive_abs_ov64$next[0:0]$10314 \dive_abs_ov64$95 + case + assign $1\dive_abs_ov64$next[0:0]$10314 \dive_abs_ov64 + end + sync always + update \dive_abs_ov64$next $0\dive_abs_ov64$next[0:0]$10313 + end + attribute \src "libresoc.v:177884.3-177896.6" + process $proc$libresoc.v:177884$10315 + assign { } { } + assign { } { } + assign $0\div_by_zero$next[0:0]$10316 $1\div_by_zero$next[0:0]$10317 + attribute \src "libresoc.v:177885.5-177885.29" + switch \initial + attribute \src "libresoc.v:177885.9-177885.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\div_by_zero$next[0:0]$10317 \div_by_zero$96 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\div_by_zero$next[0:0]$10317 \div_by_zero$96 + case + assign $1\div_by_zero$next[0:0]$10317 \div_by_zero + end + sync always + update \div_by_zero$next $0\div_by_zero$next[0:0]$10316 + end + attribute \src "libresoc.v:177897.3-177909.6" + process $proc$libresoc.v:177897$10318 + assign { } { } + assign { } { } + assign $0\dividend$next[127:0]$10319 $1\dividend$next[127:0]$10320 + attribute \src "libresoc.v:177898.5-177898.29" + switch \initial + attribute \src "libresoc.v:177898.9-177898.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\dividend$next[127:0]$10320 \dividend$97 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\dividend$next[127:0]$10320 \dividend$97 + case + assign $1\dividend$next[127:0]$10320 \dividend + end + sync always + update \dividend$next $0\dividend$next[127:0]$10319 + end + attribute \src "libresoc.v:177910.3-177922.6" + process $proc$libresoc.v:177910$10321 + assign { } { } + assign { } { } + assign $0\divisor_radicand$next[63:0]$10322 $1\divisor_radicand$next[63:0]$10323 + attribute \src "libresoc.v:177911.5-177911.29" + switch \initial + attribute \src "libresoc.v:177911.9-177911.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\divisor_radicand$next[63:0]$10323 \divisor_radicand$98 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\divisor_radicand$next[63:0]$10323 \divisor_radicand$98 + case + assign $1\divisor_radicand$next[63:0]$10323 \divisor_radicand + end + sync always + update \divisor_radicand$next $0\divisor_radicand$next[63:0]$10322 + end + attribute \src "libresoc.v:177923.3-177935.6" + process $proc$libresoc.v:177923$10324 + assign { } { } + assign { } { } + assign $0\operation$next[1:0]$10325 $1\operation$next[1:0]$10326 + attribute \src "libresoc.v:177924.5-177924.29" + switch \initial + attribute \src "libresoc.v:177924.9-177924.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\operation$next[1:0]$10326 \operation$99 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\operation$next[1:0]$10326 \operation$99 + case + assign $1\operation$next[1:0]$10326 \operation + end + sync always + update \operation$next $0\operation$next[1:0]$10325 + end + attribute \src "libresoc.v:177936.3-177953.6" + process $proc$libresoc.v:177936$10327 + assign { } { } + assign { } { } + assign { } { } + assign $0\r_busy$next[0:0]$10328 $2\r_busy$next[0:0]$10330 + attribute \src "libresoc.v:177937.5-177937.29" + switch \initial + attribute \src "libresoc.v:177937.9-177937.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\r_busy$next[0:0]$10329 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\r_busy$next[0:0]$10329 1'0 + case + assign $1\r_busy$next[0:0]$10329 \r_busy + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r_busy$next[0:0]$10330 1'0 + case + assign $2\r_busy$next[0:0]$10330 $1\r_busy$next[0:0]$10329 + end + sync always + update \r_busy$next $0\r_busy$next[0:0]$10328 + end + attribute \src "libresoc.v:177954.3-177966.6" + process $proc$libresoc.v:177954$10331 + assign { } { } + assign { } { } + assign $0\muxid$next[1:0]$10332 $1\muxid$next[1:0]$10333 + attribute \src "libresoc.v:177955.5-177955.29" + switch \initial + attribute \src "libresoc.v:177955.9-177955.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\muxid$next[1:0]$10333 \muxid$68 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\muxid$next[1:0]$10333 \muxid$68 + case + assign $1\muxid$next[1:0]$10333 \muxid + end + sync always + update \muxid$next $0\muxid$next[1:0]$10332 + end + attribute \src "libresoc.v:177967.3-178008.6" + process $proc$libresoc.v:177967$10334 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\logical_op__data_len$next[3:0]$10335 $1\logical_op__data_len$next[3:0]$10353 + assign $0\logical_op__fn_unit$next[12:0]$10336 $1\logical_op__fn_unit$next[12:0]$10354 + assign { } { } + assign { } { } + assign $0\logical_op__input_carry$next[1:0]$10339 $1\logical_op__input_carry$next[1:0]$10357 + assign $0\logical_op__insn$next[31:0]$10340 $1\logical_op__insn$next[31:0]$10358 + assign $0\logical_op__insn_type$next[6:0]$10341 $1\logical_op__insn_type$next[6:0]$10359 + assign $0\logical_op__invert_in$next[0:0]$10342 $1\logical_op__invert_in$next[0:0]$10360 + assign $0\logical_op__invert_out$next[0:0]$10343 $1\logical_op__invert_out$next[0:0]$10361 + assign $0\logical_op__is_32bit$next[0:0]$10344 $1\logical_op__is_32bit$next[0:0]$10362 + assign $0\logical_op__is_signed$next[0:0]$10345 $1\logical_op__is_signed$next[0:0]$10363 + assign { } { } + assign { } { } + assign $0\logical_op__output_carry$next[0:0]$10348 $1\logical_op__output_carry$next[0:0]$10366 + assign { } { } + assign { } { } + assign $0\logical_op__write_cr0$next[0:0]$10351 $1\logical_op__write_cr0$next[0:0]$10369 + assign $0\logical_op__zero_a$next[0:0]$10352 $1\logical_op__zero_a$next[0:0]$10370 + assign $0\logical_op__imm_data__data$next[63:0]$10337 $2\logical_op__imm_data__data$next[63:0]$10371 + assign $0\logical_op__imm_data__ok$next[0:0]$10338 $2\logical_op__imm_data__ok$next[0:0]$10372 + assign $0\logical_op__oe__oe$next[0:0]$10346 $2\logical_op__oe__oe$next[0:0]$10373 + assign $0\logical_op__oe__ok$next[0:0]$10347 $2\logical_op__oe__ok$next[0:0]$10374 + assign $0\logical_op__rc__ok$next[0:0]$10349 $2\logical_op__rc__ok$next[0:0]$10375 + assign $0\logical_op__rc__rc$next[0:0]$10350 $2\logical_op__rc__rc$next[0:0]$10376 + attribute \src "libresoc.v:177968.5-177968.29" + switch \initial + attribute \src "libresoc.v:177968.9-177968.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\logical_op__insn$next[31:0]$10358 $1\logical_op__data_len$next[3:0]$10353 $1\logical_op__is_signed$next[0:0]$10363 $1\logical_op__is_32bit$next[0:0]$10362 $1\logical_op__output_carry$next[0:0]$10366 $1\logical_op__write_cr0$next[0:0]$10369 $1\logical_op__invert_out$next[0:0]$10361 $1\logical_op__input_carry$next[1:0]$10357 $1\logical_op__zero_a$next[0:0]$10370 $1\logical_op__invert_in$next[0:0]$10360 $1\logical_op__oe__ok$next[0:0]$10365 $1\logical_op__oe__oe$next[0:0]$10364 $1\logical_op__rc__ok$next[0:0]$10367 $1\logical_op__rc__rc$next[0:0]$10368 $1\logical_op__imm_data__ok$next[0:0]$10356 $1\logical_op__imm_data__data$next[63:0]$10355 $1\logical_op__fn_unit$next[12:0]$10354 $1\logical_op__insn_type$next[6:0]$10359 } { \logical_op__insn$86 \logical_op__data_len$85 \logical_op__is_signed$84 \logical_op__is_32bit$83 \logical_op__output_carry$82 \logical_op__write_cr0$81 \logical_op__invert_out$80 \logical_op__input_carry$79 \logical_op__zero_a$78 \logical_op__invert_in$77 \logical_op__oe__ok$76 \logical_op__oe__oe$75 \logical_op__rc__ok$74 \logical_op__rc__rc$73 \logical_op__imm_data__ok$72 \logical_op__imm_data__data$71 \logical_op__fn_unit$70 \logical_op__insn_type$69 } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\logical_op__insn$next[31:0]$10358 $1\logical_op__data_len$next[3:0]$10353 $1\logical_op__is_signed$next[0:0]$10363 $1\logical_op__is_32bit$next[0:0]$10362 $1\logical_op__output_carry$next[0:0]$10366 $1\logical_op__write_cr0$next[0:0]$10369 $1\logical_op__invert_out$next[0:0]$10361 $1\logical_op__input_carry$next[1:0]$10357 $1\logical_op__zero_a$next[0:0]$10370 $1\logical_op__invert_in$next[0:0]$10360 $1\logical_op__oe__ok$next[0:0]$10365 $1\logical_op__oe__oe$next[0:0]$10364 $1\logical_op__rc__ok$next[0:0]$10367 $1\logical_op__rc__rc$next[0:0]$10368 $1\logical_op__imm_data__ok$next[0:0]$10356 $1\logical_op__imm_data__data$next[63:0]$10355 $1\logical_op__fn_unit$next[12:0]$10354 $1\logical_op__insn_type$next[6:0]$10359 } { \logical_op__insn$86 \logical_op__data_len$85 \logical_op__is_signed$84 \logical_op__is_32bit$83 \logical_op__output_carry$82 \logical_op__write_cr0$81 \logical_op__invert_out$80 \logical_op__input_carry$79 \logical_op__zero_a$78 \logical_op__invert_in$77 \logical_op__oe__ok$76 \logical_op__oe__oe$75 \logical_op__rc__ok$74 \logical_op__rc__rc$73 \logical_op__imm_data__ok$72 \logical_op__imm_data__data$71 \logical_op__fn_unit$70 \logical_op__insn_type$69 } + case + assign $1\logical_op__data_len$next[3:0]$10353 \logical_op__data_len + assign $1\logical_op__fn_unit$next[12:0]$10354 \logical_op__fn_unit + assign $1\logical_op__imm_data__data$next[63:0]$10355 \logical_op__imm_data__data + assign $1\logical_op__imm_data__ok$next[0:0]$10356 \logical_op__imm_data__ok + assign $1\logical_op__input_carry$next[1:0]$10357 \logical_op__input_carry + assign $1\logical_op__insn$next[31:0]$10358 \logical_op__insn + assign $1\logical_op__insn_type$next[6:0]$10359 \logical_op__insn_type + assign $1\logical_op__invert_in$next[0:0]$10360 \logical_op__invert_in + assign $1\logical_op__invert_out$next[0:0]$10361 \logical_op__invert_out + assign $1\logical_op__is_32bit$next[0:0]$10362 \logical_op__is_32bit + assign $1\logical_op__is_signed$next[0:0]$10363 \logical_op__is_signed + assign $1\logical_op__oe__oe$next[0:0]$10364 \logical_op__oe__oe + assign $1\logical_op__oe__ok$next[0:0]$10365 \logical_op__oe__ok + assign $1\logical_op__output_carry$next[0:0]$10366 \logical_op__output_carry + assign $1\logical_op__rc__ok$next[0:0]$10367 \logical_op__rc__ok + assign $1\logical_op__rc__rc$next[0:0]$10368 \logical_op__rc__rc + assign $1\logical_op__write_cr0$next[0:0]$10369 \logical_op__write_cr0 + assign $1\logical_op__zero_a$next[0:0]$10370 \logical_op__zero_a + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $2\logical_op__imm_data__data$next[63:0]$10371 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\logical_op__imm_data__ok$next[0:0]$10372 1'0 + assign $2\logical_op__rc__rc$next[0:0]$10376 1'0 + assign $2\logical_op__rc__ok$next[0:0]$10375 1'0 + assign $2\logical_op__oe__oe$next[0:0]$10373 1'0 + assign $2\logical_op__oe__ok$next[0:0]$10374 1'0 + case + assign $2\logical_op__imm_data__data$next[63:0]$10371 $1\logical_op__imm_data__data$next[63:0]$10355 + assign $2\logical_op__imm_data__ok$next[0:0]$10372 $1\logical_op__imm_data__ok$next[0:0]$10356 + assign $2\logical_op__oe__oe$next[0:0]$10373 $1\logical_op__oe__oe$next[0:0]$10364 + assign $2\logical_op__oe__ok$next[0:0]$10374 $1\logical_op__oe__ok$next[0:0]$10365 + assign $2\logical_op__rc__ok$next[0:0]$10375 $1\logical_op__rc__ok$next[0:0]$10367 + assign $2\logical_op__rc__rc$next[0:0]$10376 $1\logical_op__rc__rc$next[0:0]$10368 + end + sync always + update \logical_op__data_len$next $0\logical_op__data_len$next[3:0]$10335 + update \logical_op__fn_unit$next $0\logical_op__fn_unit$next[12:0]$10336 + update \logical_op__imm_data__data$next $0\logical_op__imm_data__data$next[63:0]$10337 + update \logical_op__imm_data__ok$next $0\logical_op__imm_data__ok$next[0:0]$10338 + update \logical_op__input_carry$next $0\logical_op__input_carry$next[1:0]$10339 + update \logical_op__insn$next $0\logical_op__insn$next[31:0]$10340 + update \logical_op__insn_type$next $0\logical_op__insn_type$next[6:0]$10341 + update \logical_op__invert_in$next $0\logical_op__invert_in$next[0:0]$10342 + update \logical_op__invert_out$next $0\logical_op__invert_out$next[0:0]$10343 + update \logical_op__is_32bit$next $0\logical_op__is_32bit$next[0:0]$10344 + update \logical_op__is_signed$next $0\logical_op__is_signed$next[0:0]$10345 + update \logical_op__oe__oe$next $0\logical_op__oe__oe$next[0:0]$10346 + update \logical_op__oe__ok$next $0\logical_op__oe__ok$next[0:0]$10347 + update \logical_op__output_carry$next $0\logical_op__output_carry$next[0:0]$10348 + update \logical_op__rc__ok$next $0\logical_op__rc__ok$next[0:0]$10349 + update \logical_op__rc__rc$next $0\logical_op__rc__rc$next[0:0]$10350 + update \logical_op__write_cr0$next $0\logical_op__write_cr0$next[0:0]$10351 + update \logical_op__zero_a$next $0\logical_op__zero_a$next[0:0]$10352 + end + attribute \src "libresoc.v:178009.3-178021.6" + process $proc$libresoc.v:178009$10377 + assign { } { } + assign { } { } + assign $0\ra$next[63:0]$10378 $1\ra$next[63:0]$10379 + attribute \src "libresoc.v:178010.5-178010.29" + switch \initial + attribute \src "libresoc.v:178010.9-178010.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\ra$next[63:0]$10379 \ra$87 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\ra$next[63:0]$10379 \ra$87 + case + assign $1\ra$next[63:0]$10379 \ra + end + sync always + update \ra$next $0\ra$next[63:0]$10378 + end + attribute \src "libresoc.v:178022.3-178034.6" + process $proc$libresoc.v:178022$10380 + assign { } { } + assign { } { } + assign $0\rb$next[63:0]$10381 $1\rb$next[63:0]$10382 + attribute \src "libresoc.v:178023.5-178023.29" + switch \initial + attribute \src "libresoc.v:178023.9-178023.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\rb$next[63:0]$10382 \rb$89 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\rb$next[63:0]$10382 \rb$89 + case + assign $1\rb$next[63:0]$10382 \rb + end + sync always + update \rb$next $0\rb$next[63:0]$10381 + end + attribute \src "libresoc.v:178035.3-178047.6" + process $proc$libresoc.v:178035$10383 + assign { } { } + assign { } { } + assign $0\xer_so$next[0:0]$10384 $1\xer_so$next[0:0]$10385 + attribute \src "libresoc.v:178036.5-178036.29" + switch \initial + attribute \src "libresoc.v:178036.9-178036.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\xer_so$next[0:0]$10385 \xer_so$91 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\xer_so$next[0:0]$10385 \xer_so$91 + case + assign $1\xer_so$next[0:0]$10385 \xer_so + end + sync always + update \xer_so$next $0\xer_so$next[0:0]$10384 + end + connect \$66 $and$libresoc.v:177663$10271_Y + connect \ra$88 64'0000000000000000000000000000000000000000000000000000000000000000 + connect \rb$90 64'0000000000000000000000000000000000000000000000000000000000000000 + connect \p_ready_o \n_i_rdy_data + connect \n_valid_o \r_busy + connect \operation$99 \setup_stage_operation + connect \divisor_radicand$98 \setup_stage_divisor_radicand + connect \dividend$97 \setup_stage_dividend + connect \div_by_zero$96 \setup_stage_div_by_zero + connect \dive_abs_ov64$95 \setup_stage_dive_abs_ov64 + connect \dive_abs_ov32$94 \setup_stage_dive_abs_ov32 + connect \dividend_neg$93 \setup_stage_dividend_neg + connect \divisor_neg$92 \setup_stage_divisor_neg + connect \xer_so$91 \setup_stage_xer_so$64 + connect \rb$89 64'0000000000000000000000000000000000000000000000000000000000000000 + connect \ra$87 64'0000000000000000000000000000000000000000000000000000000000000000 + connect { \logical_op__insn$86 \logical_op__data_len$85 \logical_op__is_signed$84 \logical_op__is_32bit$83 \logical_op__output_carry$82 \logical_op__write_cr0$81 \logical_op__invert_out$80 \logical_op__input_carry$79 \logical_op__zero_a$78 \logical_op__invert_in$77 \logical_op__oe__ok$76 \logical_op__oe__oe$75 \logical_op__rc__ok$74 \logical_op__rc__rc$73 \logical_op__imm_data__ok$72 \logical_op__imm_data__data$71 \logical_op__fn_unit$70 \logical_op__insn_type$69 } { \setup_stage_logical_op__insn$63 \setup_stage_logical_op__data_len$62 \setup_stage_logical_op__is_signed$61 \setup_stage_logical_op__is_32bit$60 \setup_stage_logical_op__output_carry$59 \setup_stage_logical_op__write_cr0$58 \setup_stage_logical_op__invert_out$57 \setup_stage_logical_op__input_carry$56 \setup_stage_logical_op__zero_a$55 \setup_stage_logical_op__invert_in$54 \setup_stage_logical_op__oe__ok$53 \setup_stage_logical_op__oe__oe$52 \setup_stage_logical_op__rc__ok$51 \setup_stage_logical_op__rc__rc$50 \setup_stage_logical_op__imm_data__ok$49 \setup_stage_logical_op__imm_data__data$48 \setup_stage_logical_op__fn_unit$47 \setup_stage_logical_op__insn_type$46 } + connect \muxid$68 \setup_stage_muxid$45 + connect \p_valid_i_p_ready_o \$66 + connect \n_i_rdy_data \n_ready_i + connect \p_valid_i$65 \p_valid_i + connect \setup_stage_xer_so \input_xer_so$44 + connect \setup_stage_rb \input_rb$43 + connect \setup_stage_ra \input_ra$42 + connect { \setup_stage_logical_op__insn \setup_stage_logical_op__data_len \setup_stage_logical_op__is_signed \setup_stage_logical_op__is_32bit \setup_stage_logical_op__output_carry \setup_stage_logical_op__write_cr0 \setup_stage_logical_op__invert_out \setup_stage_logical_op__input_carry \setup_stage_logical_op__zero_a \setup_stage_logical_op__invert_in \setup_stage_logical_op__oe__ok \setup_stage_logical_op__oe__oe \setup_stage_logical_op__rc__ok \setup_stage_logical_op__rc__rc \setup_stage_logical_op__imm_data__ok \setup_stage_logical_op__imm_data__data \setup_stage_logical_op__fn_unit \setup_stage_logical_op__insn_type } { \input_logical_op__insn$41 \input_logical_op__data_len$40 \input_logical_op__is_signed$39 \input_logical_op__is_32bit$38 \input_logical_op__output_carry$37 \input_logical_op__write_cr0$36 \input_logical_op__invert_out$35 \input_logical_op__input_carry$34 \input_logical_op__zero_a$33 \input_logical_op__invert_in$32 \input_logical_op__oe__ok$31 \input_logical_op__oe__oe$30 \input_logical_op__rc__ok$29 \input_logical_op__rc__rc$28 \input_logical_op__imm_data__ok$27 \input_logical_op__imm_data__data$26 \input_logical_op__fn_unit$25 \input_logical_op__insn_type$24 } + connect \setup_stage_muxid \input_muxid$23 + connect \input_xer_so \xer_so$22 + connect \input_rb \rb$21 + connect \input_ra \ra$20 + connect { \input_logical_op__insn \input_logical_op__data_len \input_logical_op__is_signed \input_logical_op__is_32bit \input_logical_op__output_carry \input_logical_op__write_cr0 \input_logical_op__invert_out \input_logical_op__input_carry \input_logical_op__zero_a \input_logical_op__invert_in \input_logical_op__oe__ok \input_logical_op__oe__oe \input_logical_op__rc__ok \input_logical_op__rc__rc \input_logical_op__imm_data__ok \input_logical_op__imm_data__data \input_logical_op__fn_unit \input_logical_op__insn_type } { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } + connect \input_muxid \muxid$1 +end +attribute \src "libresoc.v:178082.1-178126.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.pll" +attribute \generator "nMigen" +module \pll + attribute \src "libresoc.v:178083.7-178083.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:178115.3-178124.6" + wire $0\pll_18_o[0:0] + attribute \src "libresoc.v:178105.3-178114.6" + wire $0\pll_lck_o[0:0] + attribute \src "libresoc.v:178115.3-178124.6" + wire $1\pll_18_o[0:0] + attribute \src "libresoc.v:178105.3-178114.6" + wire $1\pll_lck_o[0:0] + attribute \src "libresoc.v:178102.17-178102.105" + wire $eq$libresoc.v:178102$10418_Y + attribute \src "libresoc.v:178103.17-178103.105" + wire $eq$libresoc.v:178103$10419_Y + attribute \src "libresoc.v:178104.17-178104.98" + wire $not$libresoc.v:178104$10420_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:19" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:19" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:21" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:9" + wire input 1 \clk_24_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:11" + wire output 5 \clk_pll_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:10" + wire width 2 input 3 \clk_sel_i + attribute \src "libresoc.v:178083.7-178083.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:12" + wire output 2 \pll_18_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:13" + wire output 4 \pll_lck_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:19" + cell $eq $eq$libresoc.v:178102$10418 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \clk_sel_i + connect \B 2'00 + connect \Y $eq$libresoc.v:178102$10418_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:19" + cell $eq $eq$libresoc.v:178103$10419 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \clk_sel_i + connect \B 2'00 + connect \Y $eq$libresoc.v:178103$10419_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:21" + cell $not $not$libresoc.v:178104$10420 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \clk_24_i + connect \Y $not$libresoc.v:178104$10420_Y + end + attribute \src "libresoc.v:178083.7-178083.20" + process $proc$libresoc.v:178083$10423 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:178105.3-178114.6" + process $proc$libresoc.v:178105$10421 + assign { } { } + assign { } { } + assign $0\pll_lck_o[0:0] $1\pll_lck_o[0:0] + attribute \src "libresoc.v:178106.5-178106.29" + switch \initial + attribute \src "libresoc.v:178106.9-178106.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:19" + switch \$1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\pll_lck_o[0:0] \clk_24_i + case + assign $1\pll_lck_o[0:0] 1'0 + end + sync always + update \pll_lck_o $0\pll_lck_o[0:0] + end + attribute \src "libresoc.v:178115.3-178124.6" + process $proc$libresoc.v:178115$10422 + assign { } { } + assign { } { } + assign $0\pll_18_o[0:0] $1\pll_18_o[0:0] + attribute \src "libresoc.v:178116.5-178116.29" + switch \initial + attribute \src "libresoc.v:178116.9-178116.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:19" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\pll_18_o[0:0] \$5 + case + assign $1\pll_18_o[0:0] 1'0 + end + sync always + update \pll_18_o $0\pll_18_o[0:0] + end + connect \$1 $eq$libresoc.v:178102$10418_Y + connect \$3 $eq$libresoc.v:178103$10419_Y + connect \$5 $not$libresoc.v:178104$10420_Y + connect \clk_pll_o \clk_24_i +end +attribute \src "libresoc.v:178130.1-178772.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe1.main.popcount" +attribute \generator "nMigen" +module \popcount + attribute \src "libresoc.v:178131.7-178131.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:178619.3-178645.6" + wire width 64 $0\o[63:0] + attribute \src "libresoc.v:178619.3-178645.6" + wire width 64 $1\o[63:0] + attribute \src "libresoc.v:178543.19-178543.132" + wire width 4 $add$libresoc.v:178543$10424_Y + attribute \src "libresoc.v:178544.19-178544.132" + wire width 4 $add$libresoc.v:178544$10425_Y + attribute \src "libresoc.v:178545.19-178545.132" + wire width 4 $add$libresoc.v:178545$10426_Y + attribute \src "libresoc.v:178546.19-178546.132" + wire width 4 $add$libresoc.v:178546$10427_Y + attribute \src "libresoc.v:178547.19-178547.134" + wire width 4 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parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A { 2'00 \pop_2_28 } + connect \B { 2'00 \pop_2_29 } + connect \Y $add$libresoc.v:178557$10438_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:178558$10439 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A { 2'00 \pop_2_30 } + connect \B { 2'00 \pop_2_31 } + connect \Y $add$libresoc.v:178558$10439_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:178559$10440 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A { 2'00 \pop_3_0 } + connect \B { 2'00 \pop_3_1 } + connect \Y $add$libresoc.v:178559$10440_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:178560$10441 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [8] } + connect \B { 2'00 \a [9] } + connect \Y $add$libresoc.v:178560$10441_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:178561$10442 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A { 2'00 \pop_3_2 } + connect \B { 2'00 \pop_3_3 } + connect \Y $add$libresoc.v:178561$10442_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:178562$10443 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A { 2'00 \pop_3_4 } + connect \B { 2'00 \pop_3_5 } + connect \Y $add$libresoc.v:178562$10443_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:178563$10444 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A { 2'00 \pop_3_6 } + connect \B { 2'00 \pop_3_7 } + connect \Y $add$libresoc.v:178563$10444_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:178564$10445 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A { 2'00 \pop_3_8 } + connect \B { 2'00 \pop_3_9 } + connect \Y $add$libresoc.v:178564$10445_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:178565$10446 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A { 2'00 \pop_3_10 } + connect \B { 2'00 \pop_3_11 } + connect \Y $add$libresoc.v:178565$10446_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:178566$10447 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A { 2'00 \pop_3_12 } + connect \B { 2'00 \pop_3_13 } + connect \Y $add$libresoc.v:178566$10447_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:178567$10448 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A { 2'00 \pop_3_14 } + connect \B { 2'00 \pop_3_15 } + connect \Y $add$libresoc.v:178567$10448_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:178568$10449 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A { 2'00 \pop_4_0 } + connect \B { 2'00 \pop_4_1 } + connect \Y $add$libresoc.v:178568$10449_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:178569$10450 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A { 2'00 \pop_4_2 } + connect \B { 2'00 \pop_4_3 } + connect \Y $add$libresoc.v:178569$10450_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:178570$10451 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A { 2'00 \pop_4_4 } + connect \B { 2'00 \pop_4_5 } + connect \Y $add$libresoc.v:178570$10451_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:178571$10452 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [10] } + connect \B { 2'00 \a [11] } + connect \Y $add$libresoc.v:178571$10452_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:178572$10453 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A { 2'00 \pop_4_6 } + connect \B { 2'00 \pop_4_7 } + connect \Y $add$libresoc.v:178572$10453_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:178573$10454 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 7 + connect \A { 2'00 \pop_5_0 } + connect \B { 2'00 \pop_5_1 } + connect \Y $add$libresoc.v:178573$10454_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:178574$10455 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 7 + connect \A { 2'00 \pop_5_2 } + connect \B { 2'00 \pop_5_3 } + connect \Y $add$libresoc.v:178574$10455_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:178575$10456 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A { 2'00 \pop_6_0 } + connect \B { 2'00 \pop_6_1 } + connect \Y $add$libresoc.v:178575$10456_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:178586$10475 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [12] } + connect \B { 2'00 \a [13] } + connect \Y $add$libresoc.v:178586$10475_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:178590$10482 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [14] } + connect \B { 2'00 \a [15] } + connect \Y $add$libresoc.v:178590$10482_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:178591$10483 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [16] } + connect \B { 2'00 \a [17] } + connect \Y $add$libresoc.v:178591$10483_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:178592$10484 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [0] } + connect \B { 2'00 \a [1] } + connect \Y $add$libresoc.v:178592$10484_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:178593$10485 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [18] } + connect \B { 2'00 \a [19] } + connect \Y $add$libresoc.v:178593$10485_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:178594$10486 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [20] } + connect \B { 2'00 \a [21] } + connect \Y $add$libresoc.v:178594$10486_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:178595$10487 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [22] } + connect \B { 2'00 \a [23] } + connect \Y $add$libresoc.v:178595$10487_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:178596$10488 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [24] } + connect \B { 2'00 \a [25] } + connect \Y $add$libresoc.v:178596$10488_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:178597$10489 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [26] } + connect \B { 2'00 \a [27] } + connect \Y $add$libresoc.v:178597$10489_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:178598$10490 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [28] } + connect \B { 2'00 \a [29] } + connect \Y $add$libresoc.v:178598$10490_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:178599$10491 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [30] } + connect \B { 2'00 \a [31] } + connect \Y $add$libresoc.v:178599$10491_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:178600$10492 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [32] } + connect \B { 2'00 \a [33] } + connect \Y $add$libresoc.v:178600$10492_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:178601$10493 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [34] } + connect \B { 2'00 \a [35] } + connect \Y $add$libresoc.v:178601$10493_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:178602$10494 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [36] } + connect \B { 2'00 \a [37] } + connect \Y $add$libresoc.v:178602$10494_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:178603$10495 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [2] } + connect \B { 2'00 \a [3] } + connect \Y $add$libresoc.v:178603$10495_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:178604$10496 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [38] } + connect \B { 2'00 \a [39] } + connect \Y $add$libresoc.v:178604$10496_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:178605$10497 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [40] } + connect \B { 2'00 \a [41] } + connect \Y $add$libresoc.v:178605$10497_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:178606$10498 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [42] } + connect \B { 2'00 \a [43] } + connect \Y $add$libresoc.v:178606$10498_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:178607$10499 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [44] } + connect \B { 2'00 \a [45] } + connect \Y $add$libresoc.v:178607$10499_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:178608$10500 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [46] } + connect \B { 2'00 \a [47] } + connect \Y $add$libresoc.v:178608$10500_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:178609$10501 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [48] } + connect \B { 2'00 \a [49] } + connect \Y $add$libresoc.v:178609$10501_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:178610$10502 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [50] } + connect \B { 2'00 \a [51] } + connect \Y $add$libresoc.v:178610$10502_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:178611$10503 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [52] } + connect \B { 2'00 \a [53] } + connect \Y $add$libresoc.v:178611$10503_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:178612$10504 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [54] } + connect \B { 2'00 \a [55] } + connect \Y $add$libresoc.v:178612$10504_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:178613$10505 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [56] } + connect \B { 2'00 \a [57] } + connect \Y $add$libresoc.v:178613$10505_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:178614$10506 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [4] } + connect \B { 2'00 \a [5] } + connect \Y $add$libresoc.v:178614$10506_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:178615$10507 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [58] } + connect \B { 2'00 \a [59] } + connect \Y $add$libresoc.v:178615$10507_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:178616$10508 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [60] } + connect \B { 2'00 \a [61] } + connect \Y $add$libresoc.v:178616$10508_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:178617$10509 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [62] } + connect \B { 2'00 \a [63] } + connect \Y $add$libresoc.v:178617$10509_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$libresoc.v:178618$10510 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A { 2'00 \pop_2_0 } + connect \B { 2'00 \pop_2_1 } + connect \Y $add$libresoc.v:178618$10510_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:55" + cell $eq $eq$libresoc.v:178576$10457 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \data_len + connect \B 1'1 + connect \Y $eq$libresoc.v:178576$10457_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:59" + cell $eq $eq$libresoc.v:178577$10458 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \data_len + connect \B 3'100 + connect \Y $eq$libresoc.v:178577$10458_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $extend$libresoc.v:178578$10459 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 8 + connect \A \pop_4_0 + connect \Y $extend$libresoc.v:178578$10459_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $extend$libresoc.v:178579$10461 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 8 + connect \A \pop_4_1 + connect \Y $extend$libresoc.v:178579$10461_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $extend$libresoc.v:178580$10463 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 8 + connect \A \pop_4_2 + connect \Y $extend$libresoc.v:178580$10463_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $extend$libresoc.v:178581$10465 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 8 + connect \A \pop_4_3 + connect \Y $extend$libresoc.v:178581$10465_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $extend$libresoc.v:178582$10467 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 8 + connect \A \pop_4_4 + connect \Y $extend$libresoc.v:178582$10467_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $extend$libresoc.v:178583$10469 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 8 + connect \A \pop_4_5 + connect \Y $extend$libresoc.v:178583$10469_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $extend$libresoc.v:178584$10471 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 8 + connect \A \pop_4_6 + connect \Y $extend$libresoc.v:178584$10471_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $extend$libresoc.v:178585$10473 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 8 + connect \A \pop_4_7 + connect \Y $extend$libresoc.v:178585$10473_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $extend$libresoc.v:178587$10476 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 32 + connect \A \pop_6_0 + connect \Y $extend$libresoc.v:178587$10476_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $extend$libresoc.v:178588$10478 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 32 + connect \A \pop_6_1 + connect \Y $extend$libresoc.v:178588$10478_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $extend$libresoc.v:178589$10480 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 64 + connect \A \pop_7_0 + connect \Y $extend$libresoc.v:178589$10480_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $pos$libresoc.v:178578$10460 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $extend$libresoc.v:178578$10459_Y + connect \Y $pos$libresoc.v:178578$10460_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $pos$libresoc.v:178579$10462 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $extend$libresoc.v:178579$10461_Y + connect \Y $pos$libresoc.v:178579$10462_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $pos$libresoc.v:178580$10464 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $extend$libresoc.v:178580$10463_Y + connect \Y $pos$libresoc.v:178580$10464_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $pos$libresoc.v:178581$10466 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $extend$libresoc.v:178581$10465_Y + connect \Y $pos$libresoc.v:178581$10466_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $pos$libresoc.v:178582$10468 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $extend$libresoc.v:178582$10467_Y + connect \Y $pos$libresoc.v:178582$10468_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $pos$libresoc.v:178583$10470 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $extend$libresoc.v:178583$10469_Y + connect \Y $pos$libresoc.v:178583$10470_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $pos$libresoc.v:178584$10472 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $extend$libresoc.v:178584$10471_Y + connect \Y $pos$libresoc.v:178584$10472_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $pos$libresoc.v:178585$10474 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $extend$libresoc.v:178585$10473_Y + connect \Y $pos$libresoc.v:178585$10474_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $pos$libresoc.v:178587$10477 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \Y_WIDTH 32 + connect \A $extend$libresoc.v:178587$10476_Y + connect \Y $pos$libresoc.v:178587$10477_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $pos$libresoc.v:178588$10479 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \Y_WIDTH 32 + connect \A $extend$libresoc.v:178588$10478_Y + connect \Y $pos$libresoc.v:178588$10479_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $pos$libresoc.v:178589$10481 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:178589$10480_Y + connect \Y $pos$libresoc.v:178589$10481_Y + end + attribute \src "libresoc.v:178131.7-178131.20" + process $proc$libresoc.v:178131$10512 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:178619.3-178645.6" + process $proc$libresoc.v:178619$10511 + assign { } { } + assign $0\o[63:0] $1\o[63:0] + attribute \src "libresoc.v:178620.5-178620.29" + switch \initial + attribute \src "libresoc.v:178620.9-178620.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:55" + switch { \$192 \$190 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\o[63:0] [7:0] \$194 + assign $1\o[63:0] [15:8] \$196 + assign $1\o[63:0] [23:16] \$198 + assign $1\o[63:0] [31:24] \$200 + assign $1\o[63:0] [39:32] \$202 + assign $1\o[63:0] [47:40] \$204 + assign $1\o[63:0] [55:48] \$206 + assign $1\o[63:0] [63:56] \$208 + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\o[63:0] [31:0] \$210 + assign $1\o[63:0] [63:32] \$212 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\o[63:0] \$214 + end + sync always + update \o $0\o[63:0] + end + connect \$101 $add$libresoc.v:178543$10424_Y + connect \$104 $add$libresoc.v:178544$10425_Y + connect \$107 $add$libresoc.v:178545$10426_Y + connect \$110 $add$libresoc.v:178546$10427_Y + connect \$113 $add$libresoc.v:178547$10428_Y + connect \$116 $add$libresoc.v:178548$10429_Y + connect \$11 $add$libresoc.v:178549$10430_Y + connect \$119 $add$libresoc.v:178550$10431_Y + connect \$122 $add$libresoc.v:178551$10432_Y + connect \$125 $add$libresoc.v:178552$10433_Y + connect \$128 $add$libresoc.v:178553$10434_Y + connect \$131 $add$libresoc.v:178554$10435_Y + connect \$134 $add$libresoc.v:178555$10436_Y + connect \$137 $add$libresoc.v:178556$10437_Y + connect \$140 $add$libresoc.v:178557$10438_Y + connect \$143 $add$libresoc.v:178558$10439_Y + connect \$146 $add$libresoc.v:178559$10440_Y + connect \$14 $add$libresoc.v:178560$10441_Y + connect \$149 $add$libresoc.v:178561$10442_Y + connect \$152 $add$libresoc.v:178562$10443_Y + connect \$155 $add$libresoc.v:178563$10444_Y + connect \$158 $add$libresoc.v:178564$10445_Y + connect \$161 $add$libresoc.v:178565$10446_Y + connect \$164 $add$libresoc.v:178566$10447_Y + connect \$167 $add$libresoc.v:178567$10448_Y + connect \$170 $add$libresoc.v:178568$10449_Y + connect \$173 $add$libresoc.v:178569$10450_Y + connect \$176 $add$libresoc.v:178570$10451_Y + connect \$17 $add$libresoc.v:178571$10452_Y + connect \$179 $add$libresoc.v:178572$10453_Y + connect \$182 $add$libresoc.v:178573$10454_Y + connect \$185 $add$libresoc.v:178574$10455_Y + connect \$188 $add$libresoc.v:178575$10456_Y + connect \$190 $eq$libresoc.v:178576$10457_Y + connect \$192 $eq$libresoc.v:178577$10458_Y + connect \$194 $pos$libresoc.v:178578$10460_Y + connect \$196 $pos$libresoc.v:178579$10462_Y + connect \$198 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$add$libresoc.v:178601$10493_Y + connect \$56 $add$libresoc.v:178602$10494_Y + connect \$5 $add$libresoc.v:178603$10495_Y + connect \$59 $add$libresoc.v:178604$10496_Y + connect \$62 $add$libresoc.v:178605$10497_Y + connect \$65 $add$libresoc.v:178606$10498_Y + connect \$68 $add$libresoc.v:178607$10499_Y + connect \$71 $add$libresoc.v:178608$10500_Y + connect \$74 $add$libresoc.v:178609$10501_Y + connect \$77 $add$libresoc.v:178610$10502_Y + connect \$80 $add$libresoc.v:178611$10503_Y + connect \$83 $add$libresoc.v:178612$10504_Y + connect \$86 $add$libresoc.v:178613$10505_Y + connect \$8 $add$libresoc.v:178614$10506_Y + connect \$89 $add$libresoc.v:178615$10507_Y + connect \$92 $add$libresoc.v:178616$10508_Y + connect \$95 $add$libresoc.v:178617$10509_Y + connect \$98 $add$libresoc.v:178618$10510_Y + connect \$1 \$2 + connect \$4 \$5 + connect \$7 \$8 + connect \$10 \$11 + connect \$13 \$14 + connect \$16 \$17 + connect \$19 \$20 + connect \$22 \$23 + connect \$25 \$26 + connect \$28 \$29 + connect \$31 \$32 + connect \$34 \$35 + connect \$37 \$38 + connect \$40 \$41 + connect \$43 \$44 + connect \$46 \$47 + connect \$49 \$50 + connect \$52 \$53 + connect \$55 \$56 + connect \$58 \$59 + connect \$61 \$62 + connect \$64 \$65 + connect \$67 \$68 + connect \$70 \$71 + connect \$73 \$74 + connect \$76 \$77 + connect \$79 \$80 + connect \$82 \$83 + connect \$85 \$86 + connect \$88 \$89 + connect \$91 \$92 + connect \$94 \$95 + connect \$97 \$98 + connect \$100 \$101 + connect \$103 \$104 + connect \$106 \$107 + connect \$109 \$110 + connect \$112 \$113 + connect \$115 \$116 + connect \$118 \$119 + connect \$121 \$122 + connect \$124 \$125 + connect \$127 \$128 + connect \$130 \$131 + connect \$133 \$134 + connect \$136 \$137 + connect \$139 \$140 + connect \$142 \$143 + connect \$145 \$146 + connect \$148 \$149 + connect \$151 \$152 + connect \$154 \$155 + connect \$157 \$158 + connect \$160 \$161 + connect \$163 \$164 + connect \$166 \$167 + connect \$169 \$170 + connect \$172 \$173 + connect \$175 \$176 + connect \$178 \$179 + connect \$181 \$182 + connect \$184 \$185 + connect \$187 \$188 + connect \pop_7_0 \$188 [6:0] + connect \pop_6_1 \$185 [5:0] + connect \pop_6_0 \$182 [5:0] + connect \pop_5_3 \$179 [4:0] + connect \pop_5_2 \$176 [4:0] + connect \pop_5_1 \$173 [4:0] + connect \pop_5_0 \$170 [4:0] + connect \pop_4_7 \$167 [3:0] + connect \pop_4_6 \$164 [3:0] + connect \pop_4_5 \$161 [3:0] + connect \pop_4_4 \$158 [3:0] + connect \pop_4_3 \$155 [3:0] + connect \pop_4_2 \$152 [3:0] + connect \pop_4_1 \$149 [3:0] + connect \pop_4_0 \$146 [3:0] + connect \pop_3_15 \$143 [2:0] + connect \pop_3_14 \$140 [2:0] + connect \pop_3_13 \$137 [2:0] + connect \pop_3_12 \$134 [2:0] + connect \pop_3_11 \$131 [2:0] + connect \pop_3_10 \$128 [2:0] + connect \pop_3_9 \$125 [2:0] + connect \pop_3_8 \$122 [2:0] + connect \pop_3_7 \$119 [2:0] + connect \pop_3_6 \$116 [2:0] + connect \pop_3_5 \$113 [2:0] + connect \pop_3_4 \$110 [2:0] + connect \pop_3_3 \$107 [2:0] + connect \pop_3_2 \$104 [2:0] + connect \pop_3_1 \$101 [2:0] + connect \pop_3_0 \$98 [2:0] + connect \pop_2_31 \$95 [1:0] + connect \pop_2_30 \$92 [1:0] + connect \pop_2_29 \$89 [1:0] + connect \pop_2_28 \$86 [1:0] + connect \pop_2_27 \$83 [1:0] + connect \pop_2_26 \$80 [1:0] + connect \pop_2_25 \$77 [1:0] + connect \pop_2_24 \$74 [1:0] + connect \pop_2_23 \$71 [1:0] + connect \pop_2_22 \$68 [1:0] + connect \pop_2_21 \$65 [1:0] + connect \pop_2_20 \$62 [1:0] + connect \pop_2_19 \$59 [1:0] + connect \pop_2_18 \$56 [1:0] + connect \pop_2_17 \$53 [1:0] + connect \pop_2_16 \$50 [1:0] + connect \pop_2_15 \$47 [1:0] + connect \pop_2_14 \$44 [1:0] + connect \pop_2_13 \$41 [1:0] + connect \pop_2_12 \$38 [1:0] + connect \pop_2_11 \$35 [1:0] + connect \pop_2_10 \$32 [1:0] + connect \pop_2_9 \$29 [1:0] + connect \pop_2_8 \$26 [1:0] + connect \pop_2_7 \$23 [1:0] + connect \pop_2_6 \$20 [1:0] + connect \pop_2_5 \$17 [1:0] + connect \pop_2_4 \$14 [1:0] + connect \pop_2_3 \$11 [1:0] + connect \pop_2_2 \$8 [1:0] + connect \pop_2_1 \$5 [1:0] + connect \pop_2_0 \$2 [1:0] +end +attribute \src "libresoc.v:178776.1-178860.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec_cr_in.ppick" +attribute \generator "nMigen" +module \ppick + attribute \src "libresoc.v:178833.17-178833.91" + wire $not$libresoc.v:178833$10513_Y + attribute \src "libresoc.v:178835.18-178835.93" + wire $not$libresoc.v:178835$10515_Y + attribute \src "libresoc.v:178837.18-178837.93" + wire $not$libresoc.v:178837$10517_Y + attribute \src "libresoc.v:178838.17-178838.138" + wire width 8 $not$libresoc.v:178838$10518_Y + attribute \src "libresoc.v:178840.18-178840.93" + wire $not$libresoc.v:178840$10520_Y + attribute \src "libresoc.v:178842.18-178842.93" + wire $not$libresoc.v:178842$10522_Y + attribute \src "libresoc.v:178844.18-178844.93" + wire $not$libresoc.v:178844$10524_Y + attribute \src "libresoc.v:178847.17-178847.91" + wire $not$libresoc.v:178847$10527_Y + attribute \src "libresoc.v:178834.18-178834.116" + wire $reduce_or$libresoc.v:178834$10514_Y + attribute \src "libresoc.v:178836.18-178836.122" + wire $reduce_or$libresoc.v:178836$10516_Y + attribute \src "libresoc.v:178839.18-178839.128" + wire $reduce_or$libresoc.v:178839$10519_Y + attribute \src "libresoc.v:178841.18-178841.134" + wire $reduce_or$libresoc.v:178841$10521_Y + attribute \src "libresoc.v:178843.18-178843.140" + wire $reduce_or$libresoc.v:178843$10523_Y + attribute \src "libresoc.v:178845.18-178845.90" + wire $reduce_or$libresoc.v:178845$10525_Y + attribute \src "libresoc.v:178846.17-178846.103" + wire $reduce_or$libresoc.v:178846$10526_Y + attribute \src "libresoc.v:178848.17-178848.109" + wire $reduce_or$libresoc.v:178848$10528_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 8 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" + wire \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 8 input 2 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" + wire width 8 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" + wire width 8 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:178833$10513 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $not$libresoc.v:178833$10513_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:178835$10515 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$12 + connect \Y $not$libresoc.v:178835$10515_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:178837$10517 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$16 + connect \Y $not$libresoc.v:178837$10517_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + cell $not $not$libresoc.v:178838$10518 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } + connect \Y $not$libresoc.v:178838$10518_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:178840$10520 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$20 + connect \Y $not$libresoc.v:178840$10520_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:178842$10522 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$24 + connect \Y $not$libresoc.v:178842$10522_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:178844$10524 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$28 + connect \Y $not$libresoc.v:178844$10524_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:178847$10527 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$libresoc.v:178847$10527_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:178834$10514 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [5] \i [6] \i [7] \ni [3] } + connect \Y $reduce_or$libresoc.v:178834$10514_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:178836$10516 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } + connect \Y $reduce_or$libresoc.v:178836$10516_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:178839$10519 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } + connect \Y $reduce_or$libresoc.v:178839$10519_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:178841$10521 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } + connect \Y $reduce_or$libresoc.v:178841$10521_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:178843$10523 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } + connect \Y $reduce_or$libresoc.v:178843$10523_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" + cell $reduce_or $reduce_or$libresoc.v:178845$10525 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:178845$10525_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:178846$10526 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [7] \ni [1] } + connect \Y $reduce_or$libresoc.v:178846$10526_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:178848$10528 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [6] \i [7] \ni [2] } + connect \Y $reduce_or$libresoc.v:178848$10528_Y + end + connect \$7 $not$libresoc.v:178833$10513_Y + connect \$12 $reduce_or$libresoc.v:178834$10514_Y + connect \$11 $not$libresoc.v:178835$10515_Y + connect \$16 $reduce_or$libresoc.v:178836$10516_Y + connect \$15 $not$libresoc.v:178837$10517_Y + connect \$1 $not$libresoc.v:178838$10518_Y + connect \$20 $reduce_or$libresoc.v:178839$10519_Y + connect \$19 $not$libresoc.v:178840$10520_Y + connect \$24 $reduce_or$libresoc.v:178841$10521_Y + connect \$23 $not$libresoc.v:178842$10522_Y + connect \$28 $reduce_or$libresoc.v:178843$10523_Y + connect \$27 $not$libresoc.v:178844$10524_Y + connect \$31 $reduce_or$libresoc.v:178845$10525_Y + connect \$4 $reduce_or$libresoc.v:178846$10526_Y + connect \$3 $not$libresoc.v:178847$10527_Y + connect \$8 $reduce_or$libresoc.v:178848$10528_Y + connect \en_o \$31 + connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } + connect \t7 \$27 + connect \t6 \$23 + connect \t5 \$19 + connect \t4 \$15 + connect \t3 \$11 + connect \t2 \$7 + connect \t1 \$3 + connect \t0 \i [7] + connect \ni \$1 +end +attribute \src "libresoc.v:178864.1-178948.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec_cr_out.ppick" +attribute \generator "nMigen" +module \ppick$138 + attribute \src "libresoc.v:178921.17-178921.91" + wire $not$libresoc.v:178921$10529_Y + attribute \src "libresoc.v:178923.18-178923.93" + wire $not$libresoc.v:178923$10531_Y + attribute \src "libresoc.v:178925.18-178925.93" + wire $not$libresoc.v:178925$10533_Y + attribute \src "libresoc.v:178926.17-178926.138" + wire width 8 $not$libresoc.v:178926$10534_Y + attribute \src "libresoc.v:178928.18-178928.93" + wire $not$libresoc.v:178928$10536_Y + attribute \src "libresoc.v:178930.18-178930.93" + wire $not$libresoc.v:178930$10538_Y + attribute \src "libresoc.v:178932.18-178932.93" + wire $not$libresoc.v:178932$10540_Y + attribute \src "libresoc.v:178935.17-178935.91" + wire $not$libresoc.v:178935$10543_Y + attribute \src "libresoc.v:178922.18-178922.116" + wire $reduce_or$libresoc.v:178922$10530_Y + attribute \src "libresoc.v:178924.18-178924.122" + wire $reduce_or$libresoc.v:178924$10532_Y + attribute \src "libresoc.v:178927.18-178927.128" + wire $reduce_or$libresoc.v:178927$10535_Y + attribute \src "libresoc.v:178929.18-178929.134" + wire $reduce_or$libresoc.v:178929$10537_Y + attribute \src "libresoc.v:178931.18-178931.140" + wire $reduce_or$libresoc.v:178931$10539_Y + attribute \src "libresoc.v:178933.18-178933.90" + wire $reduce_or$libresoc.v:178933$10541_Y + attribute \src "libresoc.v:178934.17-178934.103" + wire $reduce_or$libresoc.v:178934$10542_Y + attribute \src "libresoc.v:178936.17-178936.109" + wire $reduce_or$libresoc.v:178936$10544_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 8 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" + wire output 1 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 8 input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" + wire width 8 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" + wire width 8 output 2 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:178921$10529 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $not$libresoc.v:178921$10529_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:178923$10531 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$12 + connect \Y $not$libresoc.v:178923$10531_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:178925$10533 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$16 + connect \Y $not$libresoc.v:178925$10533_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + cell $not $not$libresoc.v:178926$10534 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } + connect \Y $not$libresoc.v:178926$10534_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:178928$10536 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$20 + connect \Y $not$libresoc.v:178928$10536_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:178930$10538 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$24 + connect \Y $not$libresoc.v:178930$10538_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:178932$10540 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$28 + connect \Y $not$libresoc.v:178932$10540_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:178935$10543 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$libresoc.v:178935$10543_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:178922$10530 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [5] \i [6] \i [7] \ni [3] } + connect \Y $reduce_or$libresoc.v:178922$10530_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:178924$10532 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } + connect \Y $reduce_or$libresoc.v:178924$10532_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:178927$10535 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } + connect \Y $reduce_or$libresoc.v:178927$10535_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:178929$10537 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } + connect \Y $reduce_or$libresoc.v:178929$10537_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:178931$10539 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } + connect \Y $reduce_or$libresoc.v:178931$10539_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" + cell $reduce_or $reduce_or$libresoc.v:178933$10541 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:178933$10541_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:178934$10542 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [7] \ni [1] } + connect \Y $reduce_or$libresoc.v:178934$10542_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:178936$10544 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [6] \i [7] \ni [2] } + connect \Y $reduce_or$libresoc.v:178936$10544_Y + end + connect \$7 $not$libresoc.v:178921$10529_Y + connect \$12 $reduce_or$libresoc.v:178922$10530_Y + connect \$11 $not$libresoc.v:178923$10531_Y + connect \$16 $reduce_or$libresoc.v:178924$10532_Y + connect \$15 $not$libresoc.v:178925$10533_Y + connect \$1 $not$libresoc.v:178926$10534_Y + connect \$20 $reduce_or$libresoc.v:178927$10535_Y + connect \$19 $not$libresoc.v:178928$10536_Y + connect \$24 $reduce_or$libresoc.v:178929$10537_Y + connect \$23 $not$libresoc.v:178930$10538_Y + connect \$28 $reduce_or$libresoc.v:178931$10539_Y + connect \$27 $not$libresoc.v:178932$10540_Y + connect \$31 $reduce_or$libresoc.v:178933$10541_Y + connect \$4 $reduce_or$libresoc.v:178934$10542_Y + connect \$3 $not$libresoc.v:178935$10543_Y + connect \$8 $reduce_or$libresoc.v:178936$10544_Y + connect \en_o \$31 + connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } + connect \t7 \$27 + connect \t6 \$23 + connect \t5 \$19 + connect \t4 \$15 + connect \t3 \$11 + connect \t2 \$7 + connect \t1 \$3 + connect \t0 \i [7] + connect \ni \$1 +end +attribute \src "libresoc.v:178952.1-179036.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_CR.dec_cr_in.ppick" +attribute \generator "nMigen" +module \ppick$143 + attribute \src "libresoc.v:179009.17-179009.91" + wire $not$libresoc.v:179009$10545_Y + attribute \src "libresoc.v:179011.18-179011.93" + wire $not$libresoc.v:179011$10547_Y + attribute \src "libresoc.v:179013.18-179013.93" + wire $not$libresoc.v:179013$10549_Y + attribute \src "libresoc.v:179014.17-179014.138" + wire width 8 $not$libresoc.v:179014$10550_Y + attribute \src "libresoc.v:179016.18-179016.93" + wire $not$libresoc.v:179016$10552_Y + attribute \src "libresoc.v:179018.18-179018.93" + wire $not$libresoc.v:179018$10554_Y + attribute \src "libresoc.v:179020.18-179020.93" + wire $not$libresoc.v:179020$10556_Y + attribute \src "libresoc.v:179023.17-179023.91" + wire $not$libresoc.v:179023$10559_Y + attribute \src "libresoc.v:179010.18-179010.116" + wire $reduce_or$libresoc.v:179010$10546_Y + attribute \src "libresoc.v:179012.18-179012.122" + wire $reduce_or$libresoc.v:179012$10548_Y + attribute \src "libresoc.v:179015.18-179015.128" + wire $reduce_or$libresoc.v:179015$10551_Y + attribute \src "libresoc.v:179017.18-179017.134" + wire $reduce_or$libresoc.v:179017$10553_Y + attribute \src "libresoc.v:179019.18-179019.140" + wire $reduce_or$libresoc.v:179019$10555_Y + attribute \src "libresoc.v:179021.18-179021.90" + wire $reduce_or$libresoc.v:179021$10557_Y + attribute \src "libresoc.v:179022.17-179022.103" + wire $reduce_or$libresoc.v:179022$10558_Y + attribute \src "libresoc.v:179024.17-179024.109" + wire $reduce_or$libresoc.v:179024$10560_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 8 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" + wire \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 8 input 2 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" + wire width 8 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" + wire width 8 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:179009$10545 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $not$libresoc.v:179009$10545_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:179011$10547 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$12 + connect \Y $not$libresoc.v:179011$10547_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:179013$10549 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$16 + connect \Y $not$libresoc.v:179013$10549_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + cell $not $not$libresoc.v:179014$10550 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } + connect \Y $not$libresoc.v:179014$10550_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:179016$10552 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$20 + connect \Y $not$libresoc.v:179016$10552_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:179018$10554 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$24 + connect \Y $not$libresoc.v:179018$10554_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:179020$10556 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$28 + connect \Y $not$libresoc.v:179020$10556_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:179023$10559 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$libresoc.v:179023$10559_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:179010$10546 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [5] \i [6] \i [7] \ni [3] } + connect \Y $reduce_or$libresoc.v:179010$10546_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:179012$10548 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } + connect \Y $reduce_or$libresoc.v:179012$10548_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:179015$10551 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } + connect \Y $reduce_or$libresoc.v:179015$10551_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:179017$10553 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } + connect \Y $reduce_or$libresoc.v:179017$10553_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:179019$10555 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } + connect \Y $reduce_or$libresoc.v:179019$10555_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" + cell $reduce_or $reduce_or$libresoc.v:179021$10557 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:179021$10557_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:179022$10558 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [7] \ni [1] } + connect \Y $reduce_or$libresoc.v:179022$10558_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:179024$10560 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [6] \i [7] \ni [2] } + connect \Y $reduce_or$libresoc.v:179024$10560_Y + end + connect \$7 $not$libresoc.v:179009$10545_Y + connect \$12 $reduce_or$libresoc.v:179010$10546_Y + connect \$11 $not$libresoc.v:179011$10547_Y + connect \$16 $reduce_or$libresoc.v:179012$10548_Y + connect \$15 $not$libresoc.v:179013$10549_Y + connect \$1 $not$libresoc.v:179014$10550_Y + connect \$20 $reduce_or$libresoc.v:179015$10551_Y + connect \$19 $not$libresoc.v:179016$10552_Y + connect \$24 $reduce_or$libresoc.v:179017$10553_Y + connect \$23 $not$libresoc.v:179018$10554_Y + connect \$28 $reduce_or$libresoc.v:179019$10555_Y + connect \$27 $not$libresoc.v:179020$10556_Y + connect \$31 $reduce_or$libresoc.v:179021$10557_Y + connect \$4 $reduce_or$libresoc.v:179022$10558_Y + connect \$3 $not$libresoc.v:179023$10559_Y + connect \$8 $reduce_or$libresoc.v:179024$10560_Y + connect \en_o \$31 + connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } + connect \t7 \$27 + connect \t6 \$23 + connect \t5 \$19 + connect \t4 \$15 + connect \t3 \$11 + connect \t2 \$7 + connect \t1 \$3 + connect \t0 \i [7] + connect \ni \$1 +end +attribute \src "libresoc.v:179040.1-179124.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_CR.dec_cr_out.ppick" +attribute \generator "nMigen" +module \ppick$145 + attribute \src "libresoc.v:179097.17-179097.91" + wire $not$libresoc.v:179097$10561_Y + attribute \src "libresoc.v:179099.18-179099.93" + wire $not$libresoc.v:179099$10563_Y + attribute \src "libresoc.v:179101.18-179101.93" + wire $not$libresoc.v:179101$10565_Y + attribute \src "libresoc.v:179102.17-179102.138" + wire width 8 $not$libresoc.v:179102$10566_Y + attribute \src "libresoc.v:179104.18-179104.93" + wire $not$libresoc.v:179104$10568_Y + attribute \src "libresoc.v:179106.18-179106.93" + wire $not$libresoc.v:179106$10570_Y + attribute \src "libresoc.v:179108.18-179108.93" + wire $not$libresoc.v:179108$10572_Y + attribute \src "libresoc.v:179111.17-179111.91" + wire $not$libresoc.v:179111$10575_Y + attribute \src "libresoc.v:179098.18-179098.116" + wire $reduce_or$libresoc.v:179098$10562_Y + attribute \src "libresoc.v:179100.18-179100.122" + wire $reduce_or$libresoc.v:179100$10564_Y + attribute \src "libresoc.v:179103.18-179103.128" + wire $reduce_or$libresoc.v:179103$10567_Y + attribute \src "libresoc.v:179105.18-179105.134" + wire $reduce_or$libresoc.v:179105$10569_Y + attribute \src "libresoc.v:179107.18-179107.140" + wire $reduce_or$libresoc.v:179107$10571_Y + attribute \src "libresoc.v:179109.18-179109.90" + wire $reduce_or$libresoc.v:179109$10573_Y + attribute \src "libresoc.v:179110.17-179110.103" + wire $reduce_or$libresoc.v:179110$10574_Y + attribute \src "libresoc.v:179112.17-179112.109" + wire $reduce_or$libresoc.v:179112$10576_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 8 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" + wire output 1 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 8 input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" + wire width 8 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" + wire width 8 output 2 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:179097$10561 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $not$libresoc.v:179097$10561_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:179099$10563 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$12 + connect \Y $not$libresoc.v:179099$10563_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:179101$10565 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$16 + connect \Y $not$libresoc.v:179101$10565_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + cell $not $not$libresoc.v:179102$10566 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } + connect \Y $not$libresoc.v:179102$10566_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:179104$10568 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$20 + connect \Y $not$libresoc.v:179104$10568_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:179106$10570 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$24 + connect \Y $not$libresoc.v:179106$10570_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:179108$10572 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$28 + connect \Y $not$libresoc.v:179108$10572_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:179111$10575 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$libresoc.v:179111$10575_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:179098$10562 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [5] \i [6] \i [7] \ni [3] } + connect \Y $reduce_or$libresoc.v:179098$10562_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:179100$10564 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } + connect \Y $reduce_or$libresoc.v:179100$10564_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:179103$10567 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } + connect \Y $reduce_or$libresoc.v:179103$10567_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:179105$10569 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } + connect \Y $reduce_or$libresoc.v:179105$10569_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:179107$10571 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } + connect \Y $reduce_or$libresoc.v:179107$10571_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" + cell $reduce_or $reduce_or$libresoc.v:179109$10573 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:179109$10573_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:179110$10574 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [7] \ni [1] } + connect \Y $reduce_or$libresoc.v:179110$10574_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:179112$10576 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [6] \i [7] \ni [2] } + connect \Y $reduce_or$libresoc.v:179112$10576_Y + end + connect \$7 $not$libresoc.v:179097$10561_Y + connect \$12 $reduce_or$libresoc.v:179098$10562_Y + connect \$11 $not$libresoc.v:179099$10563_Y + connect \$16 $reduce_or$libresoc.v:179100$10564_Y + connect \$15 $not$libresoc.v:179101$10565_Y + connect \$1 $not$libresoc.v:179102$10566_Y + connect \$20 $reduce_or$libresoc.v:179103$10567_Y + connect \$19 $not$libresoc.v:179104$10568_Y + connect \$24 $reduce_or$libresoc.v:179105$10569_Y + connect \$23 $not$libresoc.v:179106$10570_Y + connect \$28 $reduce_or$libresoc.v:179107$10571_Y + connect \$27 $not$libresoc.v:179108$10572_Y + connect \$31 $reduce_or$libresoc.v:179109$10573_Y + connect \$4 $reduce_or$libresoc.v:179110$10574_Y + connect \$3 $not$libresoc.v:179111$10575_Y + connect \$8 $reduce_or$libresoc.v:179112$10576_Y + connect \en_o \$31 + connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } + connect \t7 \$27 + connect \t6 \$23 + connect \t5 \$19 + connect \t4 \$15 + connect \t3 \$11 + connect \t2 \$7 + connect \t1 \$3 + connect \t0 \i [7] + connect \ni \$1 +end +attribute \src "libresoc.v:179128.1-179212.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_BRANCH.dec_cr_in.ppick" +attribute \generator "nMigen" +module \ppick$150 + attribute \src "libresoc.v:179185.17-179185.91" + wire $not$libresoc.v:179185$10577_Y + attribute \src "libresoc.v:179187.18-179187.93" + wire $not$libresoc.v:179187$10579_Y + attribute \src "libresoc.v:179189.18-179189.93" + wire $not$libresoc.v:179189$10581_Y + attribute \src "libresoc.v:179190.17-179190.138" + wire width 8 $not$libresoc.v:179190$10582_Y + attribute \src "libresoc.v:179192.18-179192.93" + wire $not$libresoc.v:179192$10584_Y + attribute \src "libresoc.v:179194.18-179194.93" + wire $not$libresoc.v:179194$10586_Y + attribute \src "libresoc.v:179196.18-179196.93" + wire $not$libresoc.v:179196$10588_Y + attribute \src "libresoc.v:179199.17-179199.91" + wire $not$libresoc.v:179199$10591_Y + attribute \src "libresoc.v:179186.18-179186.116" + wire $reduce_or$libresoc.v:179186$10578_Y + attribute \src "libresoc.v:179188.18-179188.122" + wire $reduce_or$libresoc.v:179188$10580_Y + attribute \src "libresoc.v:179191.18-179191.128" + wire $reduce_or$libresoc.v:179191$10583_Y + attribute \src "libresoc.v:179193.18-179193.134" + wire $reduce_or$libresoc.v:179193$10585_Y + attribute \src "libresoc.v:179195.18-179195.140" + wire $reduce_or$libresoc.v:179195$10587_Y + attribute \src "libresoc.v:179197.18-179197.90" + wire $reduce_or$libresoc.v:179197$10589_Y + attribute \src "libresoc.v:179198.17-179198.103" + wire $reduce_or$libresoc.v:179198$10590_Y + attribute \src "libresoc.v:179200.17-179200.109" + wire $reduce_or$libresoc.v:179200$10592_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 8 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" + wire \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 8 input 2 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" + wire width 8 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" + wire width 8 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:179185$10577 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $not$libresoc.v:179185$10577_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:179187$10579 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$12 + connect \Y $not$libresoc.v:179187$10579_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:179189$10581 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$16 + connect \Y $not$libresoc.v:179189$10581_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + cell $not $not$libresoc.v:179190$10582 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } + connect \Y $not$libresoc.v:179190$10582_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:179192$10584 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$20 + connect \Y $not$libresoc.v:179192$10584_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:179194$10586 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$24 + connect \Y $not$libresoc.v:179194$10586_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:179196$10588 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$28 + connect \Y $not$libresoc.v:179196$10588_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:179199$10591 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$libresoc.v:179199$10591_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:179186$10578 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [5] \i [6] \i [7] \ni [3] } + connect \Y $reduce_or$libresoc.v:179186$10578_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:179188$10580 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } + connect \Y $reduce_or$libresoc.v:179188$10580_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:179191$10583 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } + connect \Y $reduce_or$libresoc.v:179191$10583_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:179193$10585 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } + connect \Y $reduce_or$libresoc.v:179193$10585_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:179195$10587 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } + connect \Y $reduce_or$libresoc.v:179195$10587_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" + cell $reduce_or $reduce_or$libresoc.v:179197$10589 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:179197$10589_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:179198$10590 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [7] \ni [1] } + connect \Y $reduce_or$libresoc.v:179198$10590_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:179200$10592 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [6] \i [7] \ni [2] } + connect \Y $reduce_or$libresoc.v:179200$10592_Y + end + connect \$7 $not$libresoc.v:179185$10577_Y + connect \$12 $reduce_or$libresoc.v:179186$10578_Y + connect \$11 $not$libresoc.v:179187$10579_Y + connect \$16 $reduce_or$libresoc.v:179188$10580_Y + connect \$15 $not$libresoc.v:179189$10581_Y + connect \$1 $not$libresoc.v:179190$10582_Y + connect \$20 $reduce_or$libresoc.v:179191$10583_Y + connect \$19 $not$libresoc.v:179192$10584_Y + connect \$24 $reduce_or$libresoc.v:179193$10585_Y + connect \$23 $not$libresoc.v:179194$10586_Y + connect \$28 $reduce_or$libresoc.v:179195$10587_Y + connect \$27 $not$libresoc.v:179196$10588_Y + connect \$31 $reduce_or$libresoc.v:179197$10589_Y + connect \$4 $reduce_or$libresoc.v:179198$10590_Y + connect \$3 $not$libresoc.v:179199$10591_Y + connect \$8 $reduce_or$libresoc.v:179200$10592_Y + connect \en_o \$31 + connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } + connect \t7 \$27 + connect \t6 \$23 + connect \t5 \$19 + connect \t4 \$15 + connect \t3 \$11 + connect \t2 \$7 + connect \t1 \$3 + connect \t0 \i [7] + connect \ni \$1 +end +attribute \src "libresoc.v:179216.1-179300.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_BRANCH.dec_cr_out.ppick" +attribute \generator "nMigen" +module \ppick$152 + attribute \src "libresoc.v:179273.17-179273.91" + wire $not$libresoc.v:179273$10593_Y + attribute \src "libresoc.v:179275.18-179275.93" + wire $not$libresoc.v:179275$10595_Y + attribute \src "libresoc.v:179277.18-179277.93" + wire $not$libresoc.v:179277$10597_Y + attribute \src "libresoc.v:179278.17-179278.138" + wire width 8 $not$libresoc.v:179278$10598_Y + attribute \src "libresoc.v:179280.18-179280.93" + wire $not$libresoc.v:179280$10600_Y + attribute \src "libresoc.v:179282.18-179282.93" + wire $not$libresoc.v:179282$10602_Y + attribute \src "libresoc.v:179284.18-179284.93" + wire $not$libresoc.v:179284$10604_Y + attribute \src "libresoc.v:179287.17-179287.91" + wire $not$libresoc.v:179287$10607_Y + attribute \src "libresoc.v:179274.18-179274.116" + wire $reduce_or$libresoc.v:179274$10594_Y + attribute \src "libresoc.v:179276.18-179276.122" + wire $reduce_or$libresoc.v:179276$10596_Y + attribute \src "libresoc.v:179279.18-179279.128" + wire $reduce_or$libresoc.v:179279$10599_Y + attribute \src "libresoc.v:179281.18-179281.134" + wire $reduce_or$libresoc.v:179281$10601_Y + attribute \src "libresoc.v:179283.18-179283.140" + wire $reduce_or$libresoc.v:179283$10603_Y + attribute \src "libresoc.v:179285.18-179285.90" + wire $reduce_or$libresoc.v:179285$10605_Y + attribute \src "libresoc.v:179286.17-179286.103" + wire $reduce_or$libresoc.v:179286$10606_Y + attribute \src "libresoc.v:179288.17-179288.109" + wire $reduce_or$libresoc.v:179288$10608_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 8 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" + wire output 1 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 8 input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" + wire width 8 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" + wire width 8 output 2 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:179273$10593 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $not$libresoc.v:179273$10593_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:179275$10595 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$12 + connect \Y $not$libresoc.v:179275$10595_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:179277$10597 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$16 + connect \Y $not$libresoc.v:179277$10597_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + cell $not $not$libresoc.v:179278$10598 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } + connect \Y $not$libresoc.v:179278$10598_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:179280$10600 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$20 + connect \Y $not$libresoc.v:179280$10600_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:179282$10602 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$24 + connect \Y $not$libresoc.v:179282$10602_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:179284$10604 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$28 + connect \Y $not$libresoc.v:179284$10604_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:179287$10607 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$libresoc.v:179287$10607_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:179274$10594 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [5] \i [6] \i [7] \ni [3] } + connect \Y $reduce_or$libresoc.v:179274$10594_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:179276$10596 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } + connect \Y $reduce_or$libresoc.v:179276$10596_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:179279$10599 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } + connect \Y $reduce_or$libresoc.v:179279$10599_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:179281$10601 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } + connect \Y $reduce_or$libresoc.v:179281$10601_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:179283$10603 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } + connect \Y $reduce_or$libresoc.v:179283$10603_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" + cell $reduce_or $reduce_or$libresoc.v:179285$10605 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:179285$10605_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:179286$10606 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [7] \ni [1] } + connect \Y $reduce_or$libresoc.v:179286$10606_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:179288$10608 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [6] \i [7] \ni [2] } + connect \Y $reduce_or$libresoc.v:179288$10608_Y + end + connect \$7 $not$libresoc.v:179273$10593_Y + connect \$12 $reduce_or$libresoc.v:179274$10594_Y + connect \$11 $not$libresoc.v:179275$10595_Y + connect \$16 $reduce_or$libresoc.v:179276$10596_Y + connect \$15 $not$libresoc.v:179277$10597_Y + connect \$1 $not$libresoc.v:179278$10598_Y + connect \$20 $reduce_or$libresoc.v:179279$10599_Y + connect \$19 $not$libresoc.v:179280$10600_Y + connect \$24 $reduce_or$libresoc.v:179281$10601_Y + connect \$23 $not$libresoc.v:179282$10602_Y + connect \$28 $reduce_or$libresoc.v:179283$10603_Y + connect \$27 $not$libresoc.v:179284$10604_Y + connect \$31 $reduce_or$libresoc.v:179285$10605_Y + connect \$4 $reduce_or$libresoc.v:179286$10606_Y + connect \$3 $not$libresoc.v:179287$10607_Y + connect \$8 $reduce_or$libresoc.v:179288$10608_Y + connect \en_o \$31 + connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } + connect \t7 \$27 + connect \t6 \$23 + connect \t5 \$19 + connect \t4 \$15 + connect \t3 \$11 + connect \t2 \$7 + connect \t1 \$3 + connect \t0 \i [7] + connect \ni \$1 +end +attribute \src "libresoc.v:179304.1-179388.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LOGICAL.dec_cr_in.ppick" +attribute \generator "nMigen" +module \ppick$158 + attribute \src "libresoc.v:179361.17-179361.91" + wire $not$libresoc.v:179361$10609_Y + attribute \src "libresoc.v:179363.18-179363.93" + wire $not$libresoc.v:179363$10611_Y + attribute \src "libresoc.v:179365.18-179365.93" + wire $not$libresoc.v:179365$10613_Y + attribute \src "libresoc.v:179366.17-179366.138" + wire width 8 $not$libresoc.v:179366$10614_Y + attribute \src "libresoc.v:179368.18-179368.93" + wire $not$libresoc.v:179368$10616_Y + attribute \src "libresoc.v:179370.18-179370.93" + wire $not$libresoc.v:179370$10618_Y + attribute \src "libresoc.v:179372.18-179372.93" + wire $not$libresoc.v:179372$10620_Y + attribute \src "libresoc.v:179375.17-179375.91" + wire $not$libresoc.v:179375$10623_Y + attribute \src "libresoc.v:179362.18-179362.116" + wire $reduce_or$libresoc.v:179362$10610_Y + attribute \src "libresoc.v:179364.18-179364.122" + wire $reduce_or$libresoc.v:179364$10612_Y + attribute \src "libresoc.v:179367.18-179367.128" + wire $reduce_or$libresoc.v:179367$10615_Y + attribute \src "libresoc.v:179369.18-179369.134" + wire $reduce_or$libresoc.v:179369$10617_Y + attribute \src "libresoc.v:179371.18-179371.140" + wire $reduce_or$libresoc.v:179371$10619_Y + attribute \src "libresoc.v:179373.18-179373.90" + wire $reduce_or$libresoc.v:179373$10621_Y + attribute \src "libresoc.v:179374.17-179374.103" + wire $reduce_or$libresoc.v:179374$10622_Y + attribute \src "libresoc.v:179376.17-179376.109" + wire $reduce_or$libresoc.v:179376$10624_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 8 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" + wire \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 8 input 2 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" + wire width 8 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" + wire width 8 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:179361$10609 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $not$libresoc.v:179361$10609_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:179363$10611 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$12 + connect \Y $not$libresoc.v:179363$10611_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:179365$10613 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$16 + connect \Y $not$libresoc.v:179365$10613_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + cell $not $not$libresoc.v:179366$10614 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } + connect \Y $not$libresoc.v:179366$10614_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:179368$10616 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$20 + connect \Y $not$libresoc.v:179368$10616_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:179370$10618 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$24 + connect \Y $not$libresoc.v:179370$10618_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:179372$10620 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$28 + connect \Y $not$libresoc.v:179372$10620_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:179375$10623 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$libresoc.v:179375$10623_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:179362$10610 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [5] \i [6] \i [7] \ni [3] } + connect \Y $reduce_or$libresoc.v:179362$10610_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:179364$10612 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } + connect \Y $reduce_or$libresoc.v:179364$10612_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:179367$10615 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } + connect \Y $reduce_or$libresoc.v:179367$10615_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:179369$10617 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } + connect \Y $reduce_or$libresoc.v:179369$10617_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:179371$10619 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } + connect \Y $reduce_or$libresoc.v:179371$10619_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" + cell $reduce_or $reduce_or$libresoc.v:179373$10621 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:179373$10621_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:179374$10622 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [7] \ni [1] } + connect \Y $reduce_or$libresoc.v:179374$10622_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:179376$10624 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [6] \i [7] \ni [2] } + connect \Y $reduce_or$libresoc.v:179376$10624_Y + end + connect \$7 $not$libresoc.v:179361$10609_Y + connect \$12 $reduce_or$libresoc.v:179362$10610_Y + connect \$11 $not$libresoc.v:179363$10611_Y + connect \$16 $reduce_or$libresoc.v:179364$10612_Y + connect \$15 $not$libresoc.v:179365$10613_Y + connect \$1 $not$libresoc.v:179366$10614_Y + connect \$20 $reduce_or$libresoc.v:179367$10615_Y + connect \$19 $not$libresoc.v:179368$10616_Y + connect \$24 $reduce_or$libresoc.v:179369$10617_Y + connect \$23 $not$libresoc.v:179370$10618_Y + connect \$28 $reduce_or$libresoc.v:179371$10619_Y + connect \$27 $not$libresoc.v:179372$10620_Y + connect \$31 $reduce_or$libresoc.v:179373$10621_Y + connect \$4 $reduce_or$libresoc.v:179374$10622_Y + connect \$3 $not$libresoc.v:179375$10623_Y + connect \$8 $reduce_or$libresoc.v:179376$10624_Y + connect \en_o \$31 + connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } + connect \t7 \$27 + connect \t6 \$23 + connect \t5 \$19 + connect \t4 \$15 + connect \t3 \$11 + connect \t2 \$7 + connect \t1 \$3 + connect \t0 \i [7] + connect \ni \$1 +end +attribute \src "libresoc.v:179392.1-179476.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LOGICAL.dec_cr_out.ppick" +attribute \generator "nMigen" +module \ppick$160 + attribute \src "libresoc.v:179449.17-179449.91" + wire $not$libresoc.v:179449$10625_Y + attribute \src "libresoc.v:179451.18-179451.93" + wire $not$libresoc.v:179451$10627_Y + attribute \src "libresoc.v:179453.18-179453.93" + wire $not$libresoc.v:179453$10629_Y + attribute \src "libresoc.v:179454.17-179454.138" + wire width 8 $not$libresoc.v:179454$10630_Y + attribute \src "libresoc.v:179456.18-179456.93" + wire $not$libresoc.v:179456$10632_Y + attribute \src "libresoc.v:179458.18-179458.93" + wire $not$libresoc.v:179458$10634_Y + attribute \src "libresoc.v:179460.18-179460.93" + wire $not$libresoc.v:179460$10636_Y + attribute \src "libresoc.v:179463.17-179463.91" + wire $not$libresoc.v:179463$10639_Y + attribute \src "libresoc.v:179450.18-179450.116" + wire $reduce_or$libresoc.v:179450$10626_Y + attribute \src "libresoc.v:179452.18-179452.122" + wire $reduce_or$libresoc.v:179452$10628_Y + attribute \src "libresoc.v:179455.18-179455.128" + wire $reduce_or$libresoc.v:179455$10631_Y + attribute \src "libresoc.v:179457.18-179457.134" + wire $reduce_or$libresoc.v:179457$10633_Y + attribute \src "libresoc.v:179459.18-179459.140" + wire $reduce_or$libresoc.v:179459$10635_Y + attribute \src "libresoc.v:179461.18-179461.90" + wire $reduce_or$libresoc.v:179461$10637_Y + attribute \src "libresoc.v:179462.17-179462.103" + wire $reduce_or$libresoc.v:179462$10638_Y + attribute \src "libresoc.v:179464.17-179464.109" + wire $reduce_or$libresoc.v:179464$10640_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 8 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" + wire output 1 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 8 input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" + wire width 8 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" + wire width 8 output 2 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:179449$10625 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $not$libresoc.v:179449$10625_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:179451$10627 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$12 + connect \Y $not$libresoc.v:179451$10627_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:179453$10629 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$16 + connect \Y $not$libresoc.v:179453$10629_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + cell $not $not$libresoc.v:179454$10630 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } + connect \Y $not$libresoc.v:179454$10630_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:179456$10632 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$20 + connect \Y $not$libresoc.v:179456$10632_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:179458$10634 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$24 + connect \Y $not$libresoc.v:179458$10634_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:179460$10636 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$28 + connect \Y $not$libresoc.v:179460$10636_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:179463$10639 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$libresoc.v:179463$10639_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:179450$10626 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [5] \i [6] \i [7] \ni [3] } + connect \Y $reduce_or$libresoc.v:179450$10626_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:179452$10628 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } + connect \Y $reduce_or$libresoc.v:179452$10628_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:179455$10631 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } + connect \Y $reduce_or$libresoc.v:179455$10631_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:179457$10633 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } + connect \Y $reduce_or$libresoc.v:179457$10633_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:179459$10635 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } + connect \Y $reduce_or$libresoc.v:179459$10635_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" + cell $reduce_or $reduce_or$libresoc.v:179461$10637 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:179461$10637_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:179462$10638 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [7] \ni [1] } + connect \Y $reduce_or$libresoc.v:179462$10638_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:179464$10640 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [6] \i [7] \ni [2] } + connect \Y $reduce_or$libresoc.v:179464$10640_Y + end + connect \$7 $not$libresoc.v:179449$10625_Y + connect \$12 $reduce_or$libresoc.v:179450$10626_Y + connect \$11 $not$libresoc.v:179451$10627_Y + connect \$16 $reduce_or$libresoc.v:179452$10628_Y + connect \$15 $not$libresoc.v:179453$10629_Y + connect \$1 $not$libresoc.v:179454$10630_Y + connect \$20 $reduce_or$libresoc.v:179455$10631_Y + connect \$19 $not$libresoc.v:179456$10632_Y + connect \$24 $reduce_or$libresoc.v:179457$10633_Y + connect \$23 $not$libresoc.v:179458$10634_Y + connect \$28 $reduce_or$libresoc.v:179459$10635_Y + connect \$27 $not$libresoc.v:179460$10636_Y + connect \$31 $reduce_or$libresoc.v:179461$10637_Y + connect \$4 $reduce_or$libresoc.v:179462$10638_Y + connect \$3 $not$libresoc.v:179463$10639_Y + connect \$8 $reduce_or$libresoc.v:179464$10640_Y + connect \en_o \$31 + connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } + connect \t7 \$27 + connect \t6 \$23 + connect \t5 \$19 + connect \t4 \$15 + connect \t3 \$11 + connect \t2 \$7 + connect \t1 \$3 + connect \t0 \i [7] + connect \ni \$1 +end +attribute \src "libresoc.v:179480.1-179564.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SPR.dec_cr_in.ppick" +attribute \generator "nMigen" +module \ppick$167 + attribute \src "libresoc.v:179537.17-179537.91" + wire $not$libresoc.v:179537$10641_Y + attribute \src "libresoc.v:179539.18-179539.93" + wire $not$libresoc.v:179539$10643_Y + attribute \src "libresoc.v:179541.18-179541.93" + wire $not$libresoc.v:179541$10645_Y + attribute \src "libresoc.v:179542.17-179542.138" + wire width 8 $not$libresoc.v:179542$10646_Y + attribute \src "libresoc.v:179544.18-179544.93" + wire $not$libresoc.v:179544$10648_Y + attribute \src "libresoc.v:179546.18-179546.93" + wire $not$libresoc.v:179546$10650_Y + attribute \src "libresoc.v:179548.18-179548.93" + wire $not$libresoc.v:179548$10652_Y + attribute \src "libresoc.v:179551.17-179551.91" + wire $not$libresoc.v:179551$10655_Y + attribute \src "libresoc.v:179538.18-179538.116" + wire $reduce_or$libresoc.v:179538$10642_Y + attribute \src "libresoc.v:179540.18-179540.122" + wire $reduce_or$libresoc.v:179540$10644_Y + attribute \src "libresoc.v:179543.18-179543.128" + wire $reduce_or$libresoc.v:179543$10647_Y + attribute \src "libresoc.v:179545.18-179545.134" + wire $reduce_or$libresoc.v:179545$10649_Y + attribute \src "libresoc.v:179547.18-179547.140" + wire $reduce_or$libresoc.v:179547$10651_Y + attribute \src "libresoc.v:179549.18-179549.90" + wire $reduce_or$libresoc.v:179549$10653_Y + attribute \src "libresoc.v:179550.17-179550.103" + wire $reduce_or$libresoc.v:179550$10654_Y + attribute \src "libresoc.v:179552.17-179552.109" + wire $reduce_or$libresoc.v:179552$10656_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 8 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" + wire \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 8 input 2 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" + wire width 8 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" + wire width 8 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:179537$10641 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $not$libresoc.v:179537$10641_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:179539$10643 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$12 + connect \Y $not$libresoc.v:179539$10643_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:179541$10645 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$16 + connect \Y $not$libresoc.v:179541$10645_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + cell $not $not$libresoc.v:179542$10646 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } + connect \Y $not$libresoc.v:179542$10646_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:179544$10648 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$20 + connect \Y $not$libresoc.v:179544$10648_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:179546$10650 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$24 + connect \Y $not$libresoc.v:179546$10650_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:179548$10652 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$28 + connect \Y $not$libresoc.v:179548$10652_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:179551$10655 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$libresoc.v:179551$10655_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:179538$10642 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [5] \i [6] \i [7] \ni [3] } + connect \Y $reduce_or$libresoc.v:179538$10642_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:179540$10644 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } + connect \Y $reduce_or$libresoc.v:179540$10644_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:179543$10647 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } + connect \Y $reduce_or$libresoc.v:179543$10647_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:179545$10649 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } + connect \Y $reduce_or$libresoc.v:179545$10649_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:179547$10651 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } + connect \Y $reduce_or$libresoc.v:179547$10651_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" + cell $reduce_or $reduce_or$libresoc.v:179549$10653 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:179549$10653_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:179550$10654 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [7] \ni [1] } + connect \Y $reduce_or$libresoc.v:179550$10654_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:179552$10656 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [6] \i [7] \ni [2] } + connect \Y $reduce_or$libresoc.v:179552$10656_Y + end + connect \$7 $not$libresoc.v:179537$10641_Y + connect \$12 $reduce_or$libresoc.v:179538$10642_Y + connect \$11 $not$libresoc.v:179539$10643_Y + connect \$16 $reduce_or$libresoc.v:179540$10644_Y + connect \$15 $not$libresoc.v:179541$10645_Y + connect \$1 $not$libresoc.v:179542$10646_Y + connect \$20 $reduce_or$libresoc.v:179543$10647_Y + connect \$19 $not$libresoc.v:179544$10648_Y + connect \$24 $reduce_or$libresoc.v:179545$10649_Y + connect \$23 $not$libresoc.v:179546$10650_Y + connect \$28 $reduce_or$libresoc.v:179547$10651_Y + connect \$27 $not$libresoc.v:179548$10652_Y + connect \$31 $reduce_or$libresoc.v:179549$10653_Y + connect \$4 $reduce_or$libresoc.v:179550$10654_Y + connect \$3 $not$libresoc.v:179551$10655_Y + connect \$8 $reduce_or$libresoc.v:179552$10656_Y + connect \en_o \$31 + connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } + connect \t7 \$27 + connect \t6 \$23 + connect \t5 \$19 + connect \t4 \$15 + connect \t3 \$11 + connect \t2 \$7 + connect \t1 \$3 + connect \t0 \i [7] + connect \ni \$1 +end +attribute \src "libresoc.v:179568.1-179652.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SPR.dec_cr_out.ppick" +attribute \generator "nMigen" +module \ppick$169 + attribute \src "libresoc.v:179625.17-179625.91" + wire $not$libresoc.v:179625$10657_Y + attribute \src "libresoc.v:179627.18-179627.93" + wire $not$libresoc.v:179627$10659_Y + attribute \src "libresoc.v:179629.18-179629.93" + wire $not$libresoc.v:179629$10661_Y + attribute \src "libresoc.v:179630.17-179630.138" + wire width 8 $not$libresoc.v:179630$10662_Y + attribute \src "libresoc.v:179632.18-179632.93" + wire $not$libresoc.v:179632$10664_Y + attribute \src "libresoc.v:179634.18-179634.93" + wire $not$libresoc.v:179634$10666_Y + attribute \src "libresoc.v:179636.18-179636.93" + wire $not$libresoc.v:179636$10668_Y + attribute \src "libresoc.v:179639.17-179639.91" + wire $not$libresoc.v:179639$10671_Y + attribute \src "libresoc.v:179626.18-179626.116" + wire $reduce_or$libresoc.v:179626$10658_Y + attribute \src "libresoc.v:179628.18-179628.122" + wire $reduce_or$libresoc.v:179628$10660_Y + attribute \src "libresoc.v:179631.18-179631.128" + wire $reduce_or$libresoc.v:179631$10663_Y + attribute \src "libresoc.v:179633.18-179633.134" + wire $reduce_or$libresoc.v:179633$10665_Y + attribute \src "libresoc.v:179635.18-179635.140" + wire $reduce_or$libresoc.v:179635$10667_Y + attribute \src "libresoc.v:179637.18-179637.90" + wire $reduce_or$libresoc.v:179637$10669_Y + attribute \src "libresoc.v:179638.17-179638.103" + wire $reduce_or$libresoc.v:179638$10670_Y + attribute \src "libresoc.v:179640.17-179640.109" + wire $reduce_or$libresoc.v:179640$10672_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 8 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" + wire output 1 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 8 input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" + wire width 8 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" + wire width 8 output 2 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:179625$10657 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $not$libresoc.v:179625$10657_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:179627$10659 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$12 + connect \Y $not$libresoc.v:179627$10659_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:179629$10661 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$16 + connect \Y $not$libresoc.v:179629$10661_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + cell $not $not$libresoc.v:179630$10662 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } + connect \Y $not$libresoc.v:179630$10662_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:179632$10664 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$20 + connect \Y $not$libresoc.v:179632$10664_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:179634$10666 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$24 + connect \Y $not$libresoc.v:179634$10666_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:179636$10668 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$28 + connect \Y $not$libresoc.v:179636$10668_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:179639$10671 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$libresoc.v:179639$10671_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:179626$10658 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [5] \i [6] \i [7] \ni [3] } + connect \Y $reduce_or$libresoc.v:179626$10658_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:179628$10660 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } + connect \Y $reduce_or$libresoc.v:179628$10660_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:179631$10663 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } + connect \Y $reduce_or$libresoc.v:179631$10663_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:179633$10665 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } + connect \Y $reduce_or$libresoc.v:179633$10665_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:179635$10667 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } + connect \Y $reduce_or$libresoc.v:179635$10667_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" + cell $reduce_or $reduce_or$libresoc.v:179637$10669 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:179637$10669_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:179638$10670 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [7] \ni [1] } + connect \Y $reduce_or$libresoc.v:179638$10670_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:179640$10672 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [6] \i [7] \ni [2] } + connect \Y $reduce_or$libresoc.v:179640$10672_Y + end + connect \$7 $not$libresoc.v:179625$10657_Y + connect \$12 $reduce_or$libresoc.v:179626$10658_Y + connect \$11 $not$libresoc.v:179627$10659_Y + connect \$16 $reduce_or$libresoc.v:179628$10660_Y + connect \$15 $not$libresoc.v:179629$10661_Y + connect \$1 $not$libresoc.v:179630$10662_Y + connect \$20 $reduce_or$libresoc.v:179631$10663_Y + connect \$19 $not$libresoc.v:179632$10664_Y + connect \$24 $reduce_or$libresoc.v:179633$10665_Y + connect \$23 $not$libresoc.v:179634$10666_Y + connect \$28 $reduce_or$libresoc.v:179635$10667_Y + connect \$27 $not$libresoc.v:179636$10668_Y + connect \$31 $reduce_or$libresoc.v:179637$10669_Y + connect \$4 $reduce_or$libresoc.v:179638$10670_Y + connect \$3 $not$libresoc.v:179639$10671_Y + connect \$8 $reduce_or$libresoc.v:179640$10672_Y + connect \en_o \$31 + connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } + connect \t7 \$27 + connect \t6 \$23 + connect \t5 \$19 + connect \t4 \$15 + connect \t3 \$11 + connect \t2 \$7 + connect \t1 \$3 + connect \t0 \i [7] + connect \ni \$1 +end +attribute \src "libresoc.v:179656.1-179740.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_DIV.dec_cr_in.ppick" +attribute \generator "nMigen" +module \ppick$174 + attribute \src "libresoc.v:179713.17-179713.91" + wire $not$libresoc.v:179713$10673_Y + attribute \src "libresoc.v:179715.18-179715.93" + wire $not$libresoc.v:179715$10675_Y + attribute \src "libresoc.v:179717.18-179717.93" + wire $not$libresoc.v:179717$10677_Y + attribute \src "libresoc.v:179718.17-179718.138" + wire width 8 $not$libresoc.v:179718$10678_Y + attribute \src "libresoc.v:179720.18-179720.93" + wire $not$libresoc.v:179720$10680_Y + attribute \src "libresoc.v:179722.18-179722.93" + wire $not$libresoc.v:179722$10682_Y + attribute \src "libresoc.v:179724.18-179724.93" + wire $not$libresoc.v:179724$10684_Y + attribute \src "libresoc.v:179727.17-179727.91" + wire $not$libresoc.v:179727$10687_Y + attribute \src "libresoc.v:179714.18-179714.116" + wire $reduce_or$libresoc.v:179714$10674_Y + attribute \src "libresoc.v:179716.18-179716.122" + wire $reduce_or$libresoc.v:179716$10676_Y + attribute \src "libresoc.v:179719.18-179719.128" + wire $reduce_or$libresoc.v:179719$10679_Y + attribute \src "libresoc.v:179721.18-179721.134" + wire $reduce_or$libresoc.v:179721$10681_Y + attribute \src "libresoc.v:179723.18-179723.140" + wire $reduce_or$libresoc.v:179723$10683_Y + attribute \src "libresoc.v:179725.18-179725.90" + wire $reduce_or$libresoc.v:179725$10685_Y + attribute \src "libresoc.v:179726.17-179726.103" + wire $reduce_or$libresoc.v:179726$10686_Y + attribute \src "libresoc.v:179728.17-179728.109" + wire $reduce_or$libresoc.v:179728$10688_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 8 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" + wire \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 8 input 2 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" + wire width 8 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" + wire width 8 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:179713$10673 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $not$libresoc.v:179713$10673_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:179715$10675 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$12 + connect \Y $not$libresoc.v:179715$10675_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:179717$10677 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$16 + connect \Y $not$libresoc.v:179717$10677_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + cell $not $not$libresoc.v:179718$10678 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } + connect \Y $not$libresoc.v:179718$10678_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:179720$10680 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$20 + connect \Y $not$libresoc.v:179720$10680_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:179722$10682 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$24 + connect \Y $not$libresoc.v:179722$10682_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:179724$10684 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$28 + connect \Y $not$libresoc.v:179724$10684_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:179727$10687 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$libresoc.v:179727$10687_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:179714$10674 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [5] \i [6] \i [7] \ni [3] } + connect \Y $reduce_or$libresoc.v:179714$10674_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:179716$10676 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } + connect \Y $reduce_or$libresoc.v:179716$10676_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:179719$10679 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } + connect \Y $reduce_or$libresoc.v:179719$10679_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:179721$10681 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } + connect \Y $reduce_or$libresoc.v:179721$10681_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:179723$10683 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } + connect \Y $reduce_or$libresoc.v:179723$10683_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" + cell $reduce_or $reduce_or$libresoc.v:179725$10685 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:179725$10685_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:179726$10686 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [7] \ni [1] } + connect \Y $reduce_or$libresoc.v:179726$10686_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:179728$10688 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [6] \i [7] \ni [2] } + connect \Y $reduce_or$libresoc.v:179728$10688_Y + end + connect \$7 $not$libresoc.v:179713$10673_Y + connect \$12 $reduce_or$libresoc.v:179714$10674_Y + connect \$11 $not$libresoc.v:179715$10675_Y + connect \$16 $reduce_or$libresoc.v:179716$10676_Y + connect \$15 $not$libresoc.v:179717$10677_Y + connect \$1 $not$libresoc.v:179718$10678_Y + connect \$20 $reduce_or$libresoc.v:179719$10679_Y + connect \$19 $not$libresoc.v:179720$10680_Y + connect \$24 $reduce_or$libresoc.v:179721$10681_Y + connect \$23 $not$libresoc.v:179722$10682_Y + connect \$28 $reduce_or$libresoc.v:179723$10683_Y + connect \$27 $not$libresoc.v:179724$10684_Y + connect \$31 $reduce_or$libresoc.v:179725$10685_Y + connect \$4 $reduce_or$libresoc.v:179726$10686_Y + connect \$3 $not$libresoc.v:179727$10687_Y + connect \$8 $reduce_or$libresoc.v:179728$10688_Y + connect \en_o \$31 + connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } + connect \t7 \$27 + connect \t6 \$23 + connect \t5 \$19 + connect \t4 \$15 + connect \t3 \$11 + connect \t2 \$7 + connect \t1 \$3 + connect \t0 \i [7] + connect \ni \$1 +end +attribute \src "libresoc.v:179744.1-179828.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_DIV.dec_cr_out.ppick" +attribute \generator "nMigen" +module \ppick$176 + attribute \src "libresoc.v:179801.17-179801.91" + wire $not$libresoc.v:179801$10689_Y + attribute \src "libresoc.v:179803.18-179803.93" + wire $not$libresoc.v:179803$10691_Y + attribute \src "libresoc.v:179805.18-179805.93" + wire $not$libresoc.v:179805$10693_Y + attribute \src "libresoc.v:179806.17-179806.138" + wire width 8 $not$libresoc.v:179806$10694_Y + attribute \src "libresoc.v:179808.18-179808.93" + wire $not$libresoc.v:179808$10696_Y + attribute \src "libresoc.v:179810.18-179810.93" + wire $not$libresoc.v:179810$10698_Y + attribute \src "libresoc.v:179812.18-179812.93" + wire $not$libresoc.v:179812$10700_Y + attribute \src "libresoc.v:179815.17-179815.91" + wire $not$libresoc.v:179815$10703_Y + attribute \src "libresoc.v:179802.18-179802.116" + wire $reduce_or$libresoc.v:179802$10690_Y + attribute \src "libresoc.v:179804.18-179804.122" + wire $reduce_or$libresoc.v:179804$10692_Y + attribute \src "libresoc.v:179807.18-179807.128" + wire $reduce_or$libresoc.v:179807$10695_Y + attribute \src "libresoc.v:179809.18-179809.134" + wire $reduce_or$libresoc.v:179809$10697_Y + attribute \src "libresoc.v:179811.18-179811.140" + wire $reduce_or$libresoc.v:179811$10699_Y + attribute \src "libresoc.v:179813.18-179813.90" + wire $reduce_or$libresoc.v:179813$10701_Y + attribute \src "libresoc.v:179814.17-179814.103" + wire $reduce_or$libresoc.v:179814$10702_Y + attribute \src "libresoc.v:179816.17-179816.109" + wire $reduce_or$libresoc.v:179816$10704_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 8 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" + wire output 1 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 8 input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" + wire width 8 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" + wire width 8 output 2 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:179801$10689 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $not$libresoc.v:179801$10689_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:179803$10691 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$12 + connect \Y $not$libresoc.v:179803$10691_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:179805$10693 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$16 + connect \Y $not$libresoc.v:179805$10693_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + cell $not $not$libresoc.v:179806$10694 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } + connect \Y $not$libresoc.v:179806$10694_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:179808$10696 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$20 + connect \Y $not$libresoc.v:179808$10696_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:179810$10698 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$24 + connect \Y $not$libresoc.v:179810$10698_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:179812$10700 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$28 + connect \Y $not$libresoc.v:179812$10700_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:179815$10703 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$libresoc.v:179815$10703_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:179802$10690 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [5] \i [6] \i [7] \ni [3] } + connect \Y $reduce_or$libresoc.v:179802$10690_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:179804$10692 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } + connect \Y $reduce_or$libresoc.v:179804$10692_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:179807$10695 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } + connect \Y $reduce_or$libresoc.v:179807$10695_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:179809$10697 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } + connect \Y $reduce_or$libresoc.v:179809$10697_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:179811$10699 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } + connect \Y $reduce_or$libresoc.v:179811$10699_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" + cell $reduce_or $reduce_or$libresoc.v:179813$10701 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:179813$10701_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:179814$10702 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [7] \ni [1] } + connect \Y $reduce_or$libresoc.v:179814$10702_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:179816$10704 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [6] \i [7] \ni [2] } + connect \Y $reduce_or$libresoc.v:179816$10704_Y + end + connect \$7 $not$libresoc.v:179801$10689_Y + connect \$12 $reduce_or$libresoc.v:179802$10690_Y + connect \$11 $not$libresoc.v:179803$10691_Y + connect \$16 $reduce_or$libresoc.v:179804$10692_Y + connect \$15 $not$libresoc.v:179805$10693_Y + connect \$1 $not$libresoc.v:179806$10694_Y + connect \$20 $reduce_or$libresoc.v:179807$10695_Y + connect \$19 $not$libresoc.v:179808$10696_Y + connect \$24 $reduce_or$libresoc.v:179809$10697_Y + connect \$23 $not$libresoc.v:179810$10698_Y + connect \$28 $reduce_or$libresoc.v:179811$10699_Y + connect \$27 $not$libresoc.v:179812$10700_Y + connect \$31 $reduce_or$libresoc.v:179813$10701_Y + connect \$4 $reduce_or$libresoc.v:179814$10702_Y + connect \$3 $not$libresoc.v:179815$10703_Y + connect \$8 $reduce_or$libresoc.v:179816$10704_Y + connect \en_o \$31 + connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } + connect \t7 \$27 + connect \t6 \$23 + connect \t5 \$19 + connect \t4 \$15 + connect \t3 \$11 + connect \t2 \$7 + connect \t1 \$3 + connect \t0 \i [7] + connect \ni \$1 +end +attribute \src "libresoc.v:179832.1-179916.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_MUL.dec_cr_in.ppick" +attribute \generator "nMigen" +module \ppick$183 + attribute \src "libresoc.v:179889.17-179889.91" + wire $not$libresoc.v:179889$10705_Y + attribute \src "libresoc.v:179891.18-179891.93" + wire $not$libresoc.v:179891$10707_Y + attribute \src "libresoc.v:179893.18-179893.93" + wire $not$libresoc.v:179893$10709_Y + attribute \src "libresoc.v:179894.17-179894.138" + wire width 8 $not$libresoc.v:179894$10710_Y + attribute \src "libresoc.v:179896.18-179896.93" + wire $not$libresoc.v:179896$10712_Y + attribute \src "libresoc.v:179898.18-179898.93" + wire $not$libresoc.v:179898$10714_Y + attribute \src "libresoc.v:179900.18-179900.93" + wire $not$libresoc.v:179900$10716_Y + attribute \src "libresoc.v:179903.17-179903.91" + wire $not$libresoc.v:179903$10719_Y + attribute \src "libresoc.v:179890.18-179890.116" + wire $reduce_or$libresoc.v:179890$10706_Y + attribute \src "libresoc.v:179892.18-179892.122" + wire $reduce_or$libresoc.v:179892$10708_Y + attribute \src "libresoc.v:179895.18-179895.128" + wire $reduce_or$libresoc.v:179895$10711_Y + attribute \src "libresoc.v:179897.18-179897.134" + wire $reduce_or$libresoc.v:179897$10713_Y + attribute \src "libresoc.v:179899.18-179899.140" + wire $reduce_or$libresoc.v:179899$10715_Y + attribute \src "libresoc.v:179901.18-179901.90" + wire $reduce_or$libresoc.v:179901$10717_Y + attribute \src "libresoc.v:179902.17-179902.103" + wire $reduce_or$libresoc.v:179902$10718_Y + attribute \src "libresoc.v:179904.17-179904.109" + wire $reduce_or$libresoc.v:179904$10720_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 8 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" + wire \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 8 input 2 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" + wire width 8 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" + wire width 8 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:179889$10705 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $not$libresoc.v:179889$10705_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:179891$10707 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$12 + connect \Y $not$libresoc.v:179891$10707_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:179893$10709 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$16 + connect \Y $not$libresoc.v:179893$10709_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + cell $not $not$libresoc.v:179894$10710 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } + connect \Y $not$libresoc.v:179894$10710_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:179896$10712 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$20 + connect \Y $not$libresoc.v:179896$10712_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:179898$10714 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$24 + connect \Y $not$libresoc.v:179898$10714_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:179900$10716 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$28 + connect \Y $not$libresoc.v:179900$10716_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:179903$10719 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$libresoc.v:179903$10719_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:179890$10706 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [5] \i [6] \i [7] \ni [3] } + connect \Y $reduce_or$libresoc.v:179890$10706_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:179892$10708 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } + connect \Y $reduce_or$libresoc.v:179892$10708_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:179895$10711 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } + connect \Y $reduce_or$libresoc.v:179895$10711_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:179897$10713 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } + connect \Y $reduce_or$libresoc.v:179897$10713_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:179899$10715 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } + connect \Y $reduce_or$libresoc.v:179899$10715_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" + cell $reduce_or $reduce_or$libresoc.v:179901$10717 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:179901$10717_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:179902$10718 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [7] \ni [1] } + connect \Y $reduce_or$libresoc.v:179902$10718_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:179904$10720 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [6] \i [7] \ni [2] } + connect \Y $reduce_or$libresoc.v:179904$10720_Y + end + connect \$7 $not$libresoc.v:179889$10705_Y + connect \$12 $reduce_or$libresoc.v:179890$10706_Y + connect \$11 $not$libresoc.v:179891$10707_Y + connect \$16 $reduce_or$libresoc.v:179892$10708_Y + connect \$15 $not$libresoc.v:179893$10709_Y + connect \$1 $not$libresoc.v:179894$10710_Y + connect \$20 $reduce_or$libresoc.v:179895$10711_Y + connect \$19 $not$libresoc.v:179896$10712_Y + connect \$24 $reduce_or$libresoc.v:179897$10713_Y + connect \$23 $not$libresoc.v:179898$10714_Y + connect \$28 $reduce_or$libresoc.v:179899$10715_Y + connect \$27 $not$libresoc.v:179900$10716_Y + connect \$31 $reduce_or$libresoc.v:179901$10717_Y + connect \$4 $reduce_or$libresoc.v:179902$10718_Y + connect \$3 $not$libresoc.v:179903$10719_Y + connect \$8 $reduce_or$libresoc.v:179904$10720_Y + connect \en_o \$31 + connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } + connect \t7 \$27 + connect \t6 \$23 + connect \t5 \$19 + connect \t4 \$15 + connect \t3 \$11 + connect \t2 \$7 + connect \t1 \$3 + connect \t0 \i [7] + connect \ni \$1 +end +attribute \src "libresoc.v:179920.1-180004.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_MUL.dec_cr_out.ppick" +attribute \generator "nMigen" +module \ppick$185 + attribute \src "libresoc.v:179977.17-179977.91" + wire $not$libresoc.v:179977$10721_Y + attribute \src "libresoc.v:179979.18-179979.93" + wire $not$libresoc.v:179979$10723_Y + attribute \src "libresoc.v:179981.18-179981.93" + wire $not$libresoc.v:179981$10725_Y + attribute \src "libresoc.v:179982.17-179982.138" + wire width 8 $not$libresoc.v:179982$10726_Y + attribute \src "libresoc.v:179984.18-179984.93" + wire $not$libresoc.v:179984$10728_Y + attribute \src "libresoc.v:179986.18-179986.93" + wire $not$libresoc.v:179986$10730_Y + attribute \src "libresoc.v:179988.18-179988.93" + wire $not$libresoc.v:179988$10732_Y + attribute \src "libresoc.v:179991.17-179991.91" + wire $not$libresoc.v:179991$10735_Y + attribute \src "libresoc.v:179978.18-179978.116" + wire $reduce_or$libresoc.v:179978$10722_Y + attribute \src "libresoc.v:179980.18-179980.122" + wire $reduce_or$libresoc.v:179980$10724_Y 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\$16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" + wire output 1 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 8 input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" + wire width 8 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" + wire width 8 output 2 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:179977$10721 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $not$libresoc.v:179977$10721_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:179979$10723 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$12 + connect \Y $not$libresoc.v:179979$10723_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:179981$10725 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$16 + connect \Y $not$libresoc.v:179981$10725_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + cell $not $not$libresoc.v:179982$10726 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } + connect \Y $not$libresoc.v:179982$10726_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:179984$10728 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$20 + connect \Y $not$libresoc.v:179984$10728_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:179986$10730 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$24 + connect \Y $not$libresoc.v:179986$10730_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:179988$10732 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$28 + connect \Y $not$libresoc.v:179988$10732_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:179991$10735 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$libresoc.v:179991$10735_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:179978$10722 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [5] \i [6] \i [7] \ni [3] } + connect \Y $reduce_or$libresoc.v:179978$10722_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:179980$10724 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } + connect \Y $reduce_or$libresoc.v:179980$10724_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:179983$10727 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } + connect \Y $reduce_or$libresoc.v:179983$10727_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:179985$10729 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } + connect \Y $reduce_or$libresoc.v:179985$10729_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:179987$10731 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } + connect \Y $reduce_or$libresoc.v:179987$10731_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" + cell $reduce_or $reduce_or$libresoc.v:179989$10733 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:179989$10733_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:179990$10734 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [7] \ni [1] } + connect \Y $reduce_or$libresoc.v:179990$10734_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:179992$10736 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [6] \i [7] \ni [2] } + connect \Y $reduce_or$libresoc.v:179992$10736_Y + end + connect \$7 $not$libresoc.v:179977$10721_Y + connect \$12 $reduce_or$libresoc.v:179978$10722_Y + connect \$11 $not$libresoc.v:179979$10723_Y + connect \$16 $reduce_or$libresoc.v:179980$10724_Y + connect \$15 $not$libresoc.v:179981$10725_Y + connect \$1 $not$libresoc.v:179982$10726_Y + connect \$20 $reduce_or$libresoc.v:179983$10727_Y + connect \$19 $not$libresoc.v:179984$10728_Y + connect \$24 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$not$libresoc.v:180067$10739_Y + attribute \src "libresoc.v:180069.18-180069.93" + wire $not$libresoc.v:180069$10741_Y + attribute \src "libresoc.v:180070.17-180070.138" + wire width 8 $not$libresoc.v:180070$10742_Y + attribute \src "libresoc.v:180072.18-180072.93" + wire $not$libresoc.v:180072$10744_Y + attribute \src "libresoc.v:180074.18-180074.93" + wire $not$libresoc.v:180074$10746_Y + attribute \src "libresoc.v:180076.18-180076.93" + wire $not$libresoc.v:180076$10748_Y + attribute \src "libresoc.v:180079.17-180079.91" + wire $not$libresoc.v:180079$10751_Y + attribute \src "libresoc.v:180066.18-180066.116" + wire $reduce_or$libresoc.v:180066$10738_Y + attribute \src "libresoc.v:180068.18-180068.122" + wire $reduce_or$libresoc.v:180068$10740_Y + attribute \src "libresoc.v:180071.18-180071.128" + wire $reduce_or$libresoc.v:180071$10743_Y + attribute \src "libresoc.v:180073.18-180073.134" + wire $reduce_or$libresoc.v:180073$10745_Y + attribute \src "libresoc.v:180075.18-180075.140" + wire $reduce_or$libresoc.v:180075$10747_Y + attribute \src "libresoc.v:180077.18-180077.90" + wire $reduce_or$libresoc.v:180077$10749_Y + attribute \src "libresoc.v:180078.17-180078.103" + wire $reduce_or$libresoc.v:180078$10750_Y + attribute \src "libresoc.v:180080.17-180080.109" + wire $reduce_or$libresoc.v:180080$10752_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 8 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" + wire \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 8 input 2 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" + wire width 8 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" + wire width 8 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:180065$10737 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $not$libresoc.v:180065$10737_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:180067$10739 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$12 + connect \Y $not$libresoc.v:180067$10739_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:180069$10741 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$16 + connect \Y $not$libresoc.v:180069$10741_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + cell $not $not$libresoc.v:180070$10742 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } + connect \Y $not$libresoc.v:180070$10742_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:180072$10744 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$20 + connect \Y $not$libresoc.v:180072$10744_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:180074$10746 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$24 + connect \Y $not$libresoc.v:180074$10746_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:180076$10748 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$28 + connect \Y $not$libresoc.v:180076$10748_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:180079$10751 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$libresoc.v:180079$10751_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:180066$10738 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [5] \i [6] \i [7] \ni [3] } + connect \Y $reduce_or$libresoc.v:180066$10738_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:180068$10740 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } + connect \Y $reduce_or$libresoc.v:180068$10740_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:180071$10743 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } + connect \Y $reduce_or$libresoc.v:180071$10743_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:180073$10745 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } + connect \Y $reduce_or$libresoc.v:180073$10745_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:180075$10747 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } + connect \Y $reduce_or$libresoc.v:180075$10747_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" + cell $reduce_or $reduce_or$libresoc.v:180077$10749 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:180077$10749_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:180078$10750 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [7] \ni [1] } + connect \Y $reduce_or$libresoc.v:180078$10750_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:180080$10752 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [6] \i [7] \ni [2] } + connect \Y $reduce_or$libresoc.v:180080$10752_Y + end + connect \$7 $not$libresoc.v:180065$10737_Y + connect \$12 $reduce_or$libresoc.v:180066$10738_Y + connect \$11 $not$libresoc.v:180067$10739_Y + connect \$16 $reduce_or$libresoc.v:180068$10740_Y + connect \$15 $not$libresoc.v:180069$10741_Y + connect \$1 $not$libresoc.v:180070$10742_Y + connect \$20 $reduce_or$libresoc.v:180071$10743_Y + connect \$19 $not$libresoc.v:180072$10744_Y + connect \$24 $reduce_or$libresoc.v:180073$10745_Y + connect \$23 $not$libresoc.v:180074$10746_Y + connect \$28 $reduce_or$libresoc.v:180075$10747_Y + connect \$27 $not$libresoc.v:180076$10748_Y + connect \$31 $reduce_or$libresoc.v:180077$10749_Y + connect \$4 $reduce_or$libresoc.v:180078$10750_Y + connect \$3 $not$libresoc.v:180079$10751_Y + connect \$8 $reduce_or$libresoc.v:180080$10752_Y + connect \en_o \$31 + connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } + connect \t7 \$27 + connect \t6 \$23 + connect \t5 \$19 + connect \t4 \$15 + connect \t3 \$11 + connect \t2 \$7 + connect \t1 \$3 + connect \t0 \i [7] + connect \ni \$1 +end +attribute \src "libresoc.v:180096.1-180180.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SHIFT_ROT.dec_cr_out.ppick" +attribute \generator "nMigen" +module \ppick$193 + attribute \src "libresoc.v:180153.17-180153.91" + wire $not$libresoc.v:180153$10753_Y + attribute \src "libresoc.v:180155.18-180155.93" + wire $not$libresoc.v:180155$10755_Y + attribute \src "libresoc.v:180157.18-180157.93" + wire $not$libresoc.v:180157$10757_Y + attribute \src "libresoc.v:180158.17-180158.138" + wire width 8 $not$libresoc.v:180158$10758_Y + attribute \src "libresoc.v:180160.18-180160.93" + wire $not$libresoc.v:180160$10760_Y + attribute \src "libresoc.v:180162.18-180162.93" + wire $not$libresoc.v:180162$10762_Y + attribute \src "libresoc.v:180164.18-180164.93" + wire $not$libresoc.v:180164$10764_Y + attribute \src "libresoc.v:180167.17-180167.91" + wire $not$libresoc.v:180167$10767_Y + attribute \src "libresoc.v:180154.18-180154.116" + wire $reduce_or$libresoc.v:180154$10754_Y + attribute \src "libresoc.v:180156.18-180156.122" + wire $reduce_or$libresoc.v:180156$10756_Y + attribute \src "libresoc.v:180159.18-180159.128" + wire $reduce_or$libresoc.v:180159$10759_Y + attribute \src "libresoc.v:180161.18-180161.134" + wire $reduce_or$libresoc.v:180161$10761_Y + attribute \src "libresoc.v:180163.18-180163.140" + wire $reduce_or$libresoc.v:180163$10763_Y + attribute \src "libresoc.v:180165.18-180165.90" + wire $reduce_or$libresoc.v:180165$10765_Y + attribute \src "libresoc.v:180166.17-180166.103" + wire $reduce_or$libresoc.v:180166$10766_Y + attribute \src "libresoc.v:180168.17-180168.109" + wire $reduce_or$libresoc.v:180168$10768_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 8 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" + wire output 1 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 8 input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" + wire width 8 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" + wire width 8 output 2 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:180153$10753 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $not$libresoc.v:180153$10753_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:180155$10755 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$12 + connect \Y $not$libresoc.v:180155$10755_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:180157$10757 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$16 + connect \Y $not$libresoc.v:180157$10757_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + cell $not $not$libresoc.v:180158$10758 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } + connect \Y $not$libresoc.v:180158$10758_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:180160$10760 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$20 + connect \Y $not$libresoc.v:180160$10760_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:180162$10762 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$24 + connect \Y $not$libresoc.v:180162$10762_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:180164$10764 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$28 + connect \Y $not$libresoc.v:180164$10764_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:180167$10767 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$libresoc.v:180167$10767_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:180154$10754 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [5] \i [6] \i [7] \ni [3] } + connect \Y $reduce_or$libresoc.v:180154$10754_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:180156$10756 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } + connect \Y $reduce_or$libresoc.v:180156$10756_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:180159$10759 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } + connect \Y $reduce_or$libresoc.v:180159$10759_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:180161$10761 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } + connect \Y $reduce_or$libresoc.v:180161$10761_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:180163$10763 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } + connect \Y $reduce_or$libresoc.v:180163$10763_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" + cell $reduce_or $reduce_or$libresoc.v:180165$10765 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:180165$10765_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:180166$10766 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [7] \ni [1] } + connect \Y $reduce_or$libresoc.v:180166$10766_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:180168$10768 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [6] \i [7] \ni [2] } + connect \Y $reduce_or$libresoc.v:180168$10768_Y + end + connect \$7 $not$libresoc.v:180153$10753_Y + connect \$12 $reduce_or$libresoc.v:180154$10754_Y + connect \$11 $not$libresoc.v:180155$10755_Y + connect \$16 $reduce_or$libresoc.v:180156$10756_Y + connect \$15 $not$libresoc.v:180157$10757_Y + connect \$1 $not$libresoc.v:180158$10758_Y + connect \$20 $reduce_or$libresoc.v:180159$10759_Y + connect \$19 $not$libresoc.v:180160$10760_Y + connect \$24 $reduce_or$libresoc.v:180161$10761_Y + connect \$23 $not$libresoc.v:180162$10762_Y + connect \$28 $reduce_or$libresoc.v:180163$10763_Y + connect \$27 $not$libresoc.v:180164$10764_Y + connect \$31 $reduce_or$libresoc.v:180165$10765_Y + connect \$4 $reduce_or$libresoc.v:180166$10766_Y + connect \$3 $not$libresoc.v:180167$10767_Y + connect \$8 $reduce_or$libresoc.v:180168$10768_Y + connect \en_o \$31 + connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } + connect \t7 \$27 + connect \t6 \$23 + connect \t5 \$19 + connect \t4 \$15 + connect \t3 \$11 + connect \t2 \$7 + connect \t1 \$3 + connect \t0 \i [7] + connect \ni \$1 +end +attribute \src "libresoc.v:180184.1-180268.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec_cr_in.ppick" +attribute \generator "nMigen" +module \ppick$199 + attribute \src "libresoc.v:180241.17-180241.91" + wire $not$libresoc.v:180241$10769_Y + attribute \src "libresoc.v:180243.18-180243.93" + wire $not$libresoc.v:180243$10771_Y + attribute \src "libresoc.v:180245.18-180245.93" + wire $not$libresoc.v:180245$10773_Y + attribute \src "libresoc.v:180246.17-180246.138" + wire width 8 $not$libresoc.v:180246$10774_Y + attribute \src "libresoc.v:180248.18-180248.93" + wire $not$libresoc.v:180248$10776_Y + attribute \src "libresoc.v:180250.18-180250.93" + wire $not$libresoc.v:180250$10778_Y + attribute \src "libresoc.v:180252.18-180252.93" + wire $not$libresoc.v:180252$10780_Y + attribute \src "libresoc.v:180255.17-180255.91" + wire $not$libresoc.v:180255$10783_Y + attribute \src "libresoc.v:180242.18-180242.116" + wire $reduce_or$libresoc.v:180242$10770_Y + attribute \src "libresoc.v:180244.18-180244.122" + wire $reduce_or$libresoc.v:180244$10772_Y + attribute \src "libresoc.v:180247.18-180247.128" + wire $reduce_or$libresoc.v:180247$10775_Y + attribute \src "libresoc.v:180249.18-180249.134" + wire $reduce_or$libresoc.v:180249$10777_Y + attribute \src "libresoc.v:180251.18-180251.140" + wire $reduce_or$libresoc.v:180251$10779_Y + attribute \src "libresoc.v:180253.18-180253.90" + wire $reduce_or$libresoc.v:180253$10781_Y + attribute \src "libresoc.v:180254.17-180254.103" + wire $reduce_or$libresoc.v:180254$10782_Y + attribute \src "libresoc.v:180256.17-180256.109" + wire $reduce_or$libresoc.v:180256$10784_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 8 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" + wire \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 8 input 2 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" + wire width 8 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" + wire width 8 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:180241$10769 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $not$libresoc.v:180241$10769_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:180243$10771 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$12 + connect \Y $not$libresoc.v:180243$10771_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:180245$10773 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$16 + connect \Y $not$libresoc.v:180245$10773_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + cell $not $not$libresoc.v:180246$10774 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } + connect \Y $not$libresoc.v:180246$10774_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:180248$10776 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$20 + connect \Y $not$libresoc.v:180248$10776_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:180250$10778 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$24 + connect \Y $not$libresoc.v:180250$10778_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:180252$10780 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$28 + connect \Y $not$libresoc.v:180252$10780_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:180255$10783 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$libresoc.v:180255$10783_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:180242$10770 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [5] \i [6] \i [7] \ni [3] } + connect \Y $reduce_or$libresoc.v:180242$10770_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:180244$10772 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } + connect \Y $reduce_or$libresoc.v:180244$10772_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:180247$10775 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } + connect \Y $reduce_or$libresoc.v:180247$10775_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:180249$10777 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } + connect \Y $reduce_or$libresoc.v:180249$10777_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:180251$10779 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } + connect \Y $reduce_or$libresoc.v:180251$10779_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" + cell $reduce_or $reduce_or$libresoc.v:180253$10781 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:180253$10781_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:180254$10782 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [7] \ni [1] } + connect \Y $reduce_or$libresoc.v:180254$10782_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:180256$10784 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [6] \i [7] \ni [2] } + connect \Y $reduce_or$libresoc.v:180256$10784_Y + end + connect \$7 $not$libresoc.v:180241$10769_Y + connect \$12 $reduce_or$libresoc.v:180242$10770_Y + connect \$11 $not$libresoc.v:180243$10771_Y + connect \$16 $reduce_or$libresoc.v:180244$10772_Y + connect \$15 $not$libresoc.v:180245$10773_Y + connect \$1 $not$libresoc.v:180246$10774_Y + connect \$20 $reduce_or$libresoc.v:180247$10775_Y + connect \$19 $not$libresoc.v:180248$10776_Y + connect \$24 $reduce_or$libresoc.v:180249$10777_Y + connect \$23 $not$libresoc.v:180250$10778_Y + connect \$28 $reduce_or$libresoc.v:180251$10779_Y + connect \$27 $not$libresoc.v:180252$10780_Y + connect \$31 $reduce_or$libresoc.v:180253$10781_Y + connect \$4 $reduce_or$libresoc.v:180254$10782_Y + connect \$3 $not$libresoc.v:180255$10783_Y + connect \$8 $reduce_or$libresoc.v:180256$10784_Y + connect \en_o \$31 + connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } + connect \t7 \$27 + connect \t6 \$23 + connect \t5 \$19 + connect \t4 \$15 + connect \t3 \$11 + connect \t2 \$7 + connect \t1 \$3 + connect \t0 \i [7] + connect \ni \$1 +end +attribute \src "libresoc.v:180272.1-180356.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec_cr_out.ppick" +attribute \generator "nMigen" +module \ppick$201 + attribute \src "libresoc.v:180329.17-180329.91" + wire $not$libresoc.v:180329$10785_Y + attribute \src "libresoc.v:180331.18-180331.93" + wire $not$libresoc.v:180331$10787_Y + attribute \src "libresoc.v:180333.18-180333.93" + wire $not$libresoc.v:180333$10789_Y + attribute \src "libresoc.v:180334.17-180334.138" + wire width 8 $not$libresoc.v:180334$10790_Y + attribute \src "libresoc.v:180336.18-180336.93" + wire $not$libresoc.v:180336$10792_Y + attribute \src "libresoc.v:180338.18-180338.93" + wire $not$libresoc.v:180338$10794_Y + attribute \src "libresoc.v:180340.18-180340.93" + wire $not$libresoc.v:180340$10796_Y + attribute \src "libresoc.v:180343.17-180343.91" + wire $not$libresoc.v:180343$10799_Y + attribute \src "libresoc.v:180330.18-180330.116" + wire $reduce_or$libresoc.v:180330$10786_Y + attribute \src "libresoc.v:180332.18-180332.122" + wire $reduce_or$libresoc.v:180332$10788_Y + attribute \src "libresoc.v:180335.18-180335.128" + wire $reduce_or$libresoc.v:180335$10791_Y + attribute \src "libresoc.v:180337.18-180337.134" + wire $reduce_or$libresoc.v:180337$10793_Y + attribute \src "libresoc.v:180339.18-180339.140" + wire $reduce_or$libresoc.v:180339$10795_Y + attribute \src "libresoc.v:180341.18-180341.90" + wire $reduce_or$libresoc.v:180341$10797_Y + attribute \src "libresoc.v:180342.17-180342.103" + wire $reduce_or$libresoc.v:180342$10798_Y + attribute \src "libresoc.v:180344.17-180344.109" + wire $reduce_or$libresoc.v:180344$10800_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 8 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" + wire output 1 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 8 input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" + wire width 8 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" + wire width 8 output 2 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:180329$10785 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $not$libresoc.v:180329$10785_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:180331$10787 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$12 + connect \Y $not$libresoc.v:180331$10787_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:180333$10789 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$16 + connect \Y $not$libresoc.v:180333$10789_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + cell $not $not$libresoc.v:180334$10790 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } + connect \Y $not$libresoc.v:180334$10790_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:180336$10792 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$20 + connect \Y $not$libresoc.v:180336$10792_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:180338$10794 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$24 + connect \Y $not$libresoc.v:180338$10794_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:180340$10796 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$28 + connect \Y $not$libresoc.v:180340$10796_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:180343$10799 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$libresoc.v:180343$10799_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:180330$10786 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [5] \i [6] \i [7] \ni [3] } + connect \Y $reduce_or$libresoc.v:180330$10786_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:180332$10788 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } + connect \Y $reduce_or$libresoc.v:180332$10788_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:180335$10791 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } + connect \Y $reduce_or$libresoc.v:180335$10791_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:180337$10793 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } + connect \Y $reduce_or$libresoc.v:180337$10793_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:180339$10795 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } + connect \Y $reduce_or$libresoc.v:180339$10795_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" + cell $reduce_or $reduce_or$libresoc.v:180341$10797 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:180341$10797_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:180342$10798 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [7] \ni [1] } + connect \Y $reduce_or$libresoc.v:180342$10798_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:180344$10800 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [6] \i [7] \ni [2] } + connect \Y $reduce_or$libresoc.v:180344$10800_Y + end + connect \$7 $not$libresoc.v:180329$10785_Y + connect \$12 $reduce_or$libresoc.v:180330$10786_Y + connect \$11 $not$libresoc.v:180331$10787_Y + connect \$16 $reduce_or$libresoc.v:180332$10788_Y + connect \$15 $not$libresoc.v:180333$10789_Y + connect \$1 $not$libresoc.v:180334$10790_Y + connect \$20 $reduce_or$libresoc.v:180335$10791_Y + connect \$19 $not$libresoc.v:180336$10792_Y + connect \$24 $reduce_or$libresoc.v:180337$10793_Y + connect \$23 $not$libresoc.v:180338$10794_Y + connect \$28 $reduce_or$libresoc.v:180339$10795_Y + connect \$27 $not$libresoc.v:180340$10796_Y + connect \$31 $reduce_or$libresoc.v:180341$10797_Y + connect \$4 $reduce_or$libresoc.v:180342$10798_Y + connect \$3 $not$libresoc.v:180343$10799_Y + connect \$8 $reduce_or$libresoc.v:180344$10800_Y + connect \en_o \$31 + connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } + connect \t7 \$27 + connect \t6 \$23 + connect \t5 \$19 + connect \t4 \$15 + connect \t3 \$11 + connect \t2 \$7 + connect \t1 \$3 + connect \t0 \i [7] + connect \ni \$1 +end +attribute \src "libresoc.v:180360.1-180444.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_cr_in.ppick" +attribute \generator "nMigen" +module \ppick$208 + attribute \src "libresoc.v:180417.17-180417.91" + wire $not$libresoc.v:180417$10801_Y + attribute \src "libresoc.v:180419.18-180419.93" + wire $not$libresoc.v:180419$10803_Y + attribute \src "libresoc.v:180421.18-180421.93" + wire $not$libresoc.v:180421$10805_Y + attribute \src "libresoc.v:180422.17-180422.138" + wire width 8 $not$libresoc.v:180422$10806_Y + attribute \src "libresoc.v:180424.18-180424.93" + wire $not$libresoc.v:180424$10808_Y + attribute \src "libresoc.v:180426.18-180426.93" + wire $not$libresoc.v:180426$10810_Y + attribute \src "libresoc.v:180428.18-180428.93" + wire $not$libresoc.v:180428$10812_Y + attribute \src "libresoc.v:180431.17-180431.91" + wire $not$libresoc.v:180431$10815_Y + attribute \src "libresoc.v:180418.18-180418.116" + wire $reduce_or$libresoc.v:180418$10802_Y + attribute \src "libresoc.v:180420.18-180420.122" + wire $reduce_or$libresoc.v:180420$10804_Y + attribute \src "libresoc.v:180423.18-180423.128" + wire $reduce_or$libresoc.v:180423$10807_Y + attribute \src "libresoc.v:180425.18-180425.134" + wire $reduce_or$libresoc.v:180425$10809_Y + attribute \src "libresoc.v:180427.18-180427.140" + wire $reduce_or$libresoc.v:180427$10811_Y + attribute \src "libresoc.v:180429.18-180429.90" + wire $reduce_or$libresoc.v:180429$10813_Y + attribute \src "libresoc.v:180430.17-180430.103" + wire $reduce_or$libresoc.v:180430$10814_Y + attribute \src "libresoc.v:180432.17-180432.109" + wire $reduce_or$libresoc.v:180432$10816_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 8 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" + wire \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 8 input 2 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" + wire width 8 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" + wire width 8 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:180417$10801 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $not$libresoc.v:180417$10801_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:180419$10803 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$12 + connect \Y $not$libresoc.v:180419$10803_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:180421$10805 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$16 + connect \Y $not$libresoc.v:180421$10805_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + cell $not $not$libresoc.v:180422$10806 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } + connect \Y $not$libresoc.v:180422$10806_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:180424$10808 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$20 + connect \Y $not$libresoc.v:180424$10808_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:180426$10810 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$24 + connect \Y $not$libresoc.v:180426$10810_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:180428$10812 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$28 + connect \Y $not$libresoc.v:180428$10812_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:180431$10815 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$libresoc.v:180431$10815_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:180418$10802 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [5] \i [6] \i [7] \ni [3] } + connect \Y $reduce_or$libresoc.v:180418$10802_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:180420$10804 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } + connect \Y $reduce_or$libresoc.v:180420$10804_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:180423$10807 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } + connect \Y $reduce_or$libresoc.v:180423$10807_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:180425$10809 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } + connect \Y $reduce_or$libresoc.v:180425$10809_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:180427$10811 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } + connect \Y $reduce_or$libresoc.v:180427$10811_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" + cell $reduce_or $reduce_or$libresoc.v:180429$10813 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:180429$10813_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:180430$10814 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [7] \ni [1] } + connect \Y $reduce_or$libresoc.v:180430$10814_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:180432$10816 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [6] \i [7] \ni [2] } + connect \Y $reduce_or$libresoc.v:180432$10816_Y + end + connect \$7 $not$libresoc.v:180417$10801_Y + connect \$12 $reduce_or$libresoc.v:180418$10802_Y + connect \$11 $not$libresoc.v:180419$10803_Y + connect \$16 $reduce_or$libresoc.v:180420$10804_Y + connect \$15 $not$libresoc.v:180421$10805_Y + connect \$1 $not$libresoc.v:180422$10806_Y + connect \$20 $reduce_or$libresoc.v:180423$10807_Y + connect \$19 $not$libresoc.v:180424$10808_Y + connect \$24 $reduce_or$libresoc.v:180425$10809_Y + connect \$23 $not$libresoc.v:180426$10810_Y + connect \$28 $reduce_or$libresoc.v:180427$10811_Y + connect \$27 $not$libresoc.v:180428$10812_Y + connect \$31 $reduce_or$libresoc.v:180429$10813_Y + connect \$4 $reduce_or$libresoc.v:180430$10814_Y + connect \$3 $not$libresoc.v:180431$10815_Y + connect \$8 $reduce_or$libresoc.v:180432$10816_Y + connect \en_o \$31 + connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } + connect \t7 \$27 + connect \t6 \$23 + connect \t5 \$19 + connect \t4 \$15 + connect \t3 \$11 + connect \t2 \$7 + connect \t1 \$3 + connect \t0 \i [7] + connect \ni \$1 +end +attribute \src "libresoc.v:180448.1-180532.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_cr_out.ppick" +attribute \generator "nMigen" +module \ppick$210 + attribute \src "libresoc.v:180505.17-180505.91" + wire $not$libresoc.v:180505$10817_Y + attribute \src "libresoc.v:180507.18-180507.93" + wire $not$libresoc.v:180507$10819_Y + attribute \src "libresoc.v:180509.18-180509.93" + wire $not$libresoc.v:180509$10821_Y + attribute \src "libresoc.v:180510.17-180510.138" + wire width 8 $not$libresoc.v:180510$10822_Y + attribute \src "libresoc.v:180512.18-180512.93" + wire $not$libresoc.v:180512$10824_Y + attribute \src "libresoc.v:180514.18-180514.93" + wire $not$libresoc.v:180514$10826_Y + attribute \src "libresoc.v:180516.18-180516.93" + wire $not$libresoc.v:180516$10828_Y + attribute \src "libresoc.v:180519.17-180519.91" + wire $not$libresoc.v:180519$10831_Y + attribute \src "libresoc.v:180506.18-180506.116" + wire $reduce_or$libresoc.v:180506$10818_Y + attribute \src "libresoc.v:180508.18-180508.122" + wire $reduce_or$libresoc.v:180508$10820_Y + attribute \src "libresoc.v:180511.18-180511.128" + wire $reduce_or$libresoc.v:180511$10823_Y + attribute \src "libresoc.v:180513.18-180513.134" + wire $reduce_or$libresoc.v:180513$10825_Y + attribute \src "libresoc.v:180515.18-180515.140" + wire $reduce_or$libresoc.v:180515$10827_Y + attribute \src "libresoc.v:180517.18-180517.90" + wire $reduce_or$libresoc.v:180517$10829_Y + attribute \src "libresoc.v:180518.17-180518.103" + wire $reduce_or$libresoc.v:180518$10830_Y + attribute \src "libresoc.v:180520.17-180520.109" + wire $reduce_or$libresoc.v:180520$10832_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 8 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" + wire output 1 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 8 input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" + wire width 8 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" + wire width 8 output 2 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:180505$10817 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $not$libresoc.v:180505$10817_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:180507$10819 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$12 + connect \Y $not$libresoc.v:180507$10819_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:180509$10821 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$16 + connect \Y $not$libresoc.v:180509$10821_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + cell $not $not$libresoc.v:180510$10822 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } + connect \Y $not$libresoc.v:180510$10822_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:180512$10824 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$20 + connect \Y $not$libresoc.v:180512$10824_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:180514$10826 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$24 + connect \Y $not$libresoc.v:180514$10826_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:180516$10828 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$28 + connect \Y $not$libresoc.v:180516$10828_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:180519$10831 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$libresoc.v:180519$10831_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:180506$10818 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [5] \i [6] \i [7] \ni [3] } + connect \Y $reduce_or$libresoc.v:180506$10818_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:180508$10820 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } + connect \Y $reduce_or$libresoc.v:180508$10820_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:180511$10823 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } + connect \Y $reduce_or$libresoc.v:180511$10823_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:180513$10825 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } + connect \Y $reduce_or$libresoc.v:180513$10825_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:180515$10827 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } + connect \Y $reduce_or$libresoc.v:180515$10827_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" + cell $reduce_or $reduce_or$libresoc.v:180517$10829 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:180517$10829_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:180518$10830 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [7] \ni [1] } + connect \Y $reduce_or$libresoc.v:180518$10830_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:180520$10832 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [6] \i [7] \ni [2] } + connect \Y $reduce_or$libresoc.v:180520$10832_Y + end + connect \$7 $not$libresoc.v:180505$10817_Y + connect \$12 $reduce_or$libresoc.v:180506$10818_Y + connect \$11 $not$libresoc.v:180507$10819_Y + connect \$16 $reduce_or$libresoc.v:180508$10820_Y + connect \$15 $not$libresoc.v:180509$10821_Y + connect \$1 $not$libresoc.v:180510$10822_Y + connect \$20 $reduce_or$libresoc.v:180511$10823_Y + connect \$19 $not$libresoc.v:180512$10824_Y + connect \$24 $reduce_or$libresoc.v:180513$10825_Y + connect \$23 $not$libresoc.v:180514$10826_Y + connect \$28 $reduce_or$libresoc.v:180515$10827_Y + connect \$27 $not$libresoc.v:180516$10828_Y + connect \$31 $reduce_or$libresoc.v:180517$10829_Y + connect \$4 $reduce_or$libresoc.v:180518$10830_Y + connect \$3 $not$libresoc.v:180519$10831_Y + connect \$8 $reduce_or$libresoc.v:180520$10832_Y + connect \en_o \$31 + connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } + connect \t7 \$27 + connect \t6 \$23 + connect \t5 \$19 + connect \t4 \$15 + connect \t3 \$11 + connect \t2 \$7 + connect \t1 \$3 + connect \t0 \i [7] + connect \ni \$1 +end +attribute \src "libresoc.v:180536.1-180566.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_CR_cr_a" +attribute \generator "nMigen" +module \rdpick_CR_cr_a + attribute \src "libresoc.v:180557.17-180557.89" + wire width 2 $not$libresoc.v:180557$10833_Y + attribute \src "libresoc.v:180559.17-180559.91" + wire $not$libresoc.v:180559$10835_Y + attribute \src "libresoc.v:180558.17-180558.103" + wire $reduce_or$libresoc.v:180558$10834_Y + attribute \src "libresoc.v:180560.17-180560.89" + wire $reduce_or$libresoc.v:180560$10836_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 2 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" + wire output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 2 input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" + wire width 2 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" + wire width 2 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + cell $not $not$libresoc.v:180557$10833 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \i + connect \Y $not$libresoc.v:180557$10833_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:180559$10835 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$libresoc.v:180559$10835_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:180558$10834 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [0] \ni [1] } + connect \Y $reduce_or$libresoc.v:180558$10834_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" + cell $reduce_or $reduce_or$libresoc.v:180560$10836 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:180560$10836_Y + end + connect \$1 $not$libresoc.v:180557$10833_Y + connect \$4 $reduce_or$libresoc.v:180558$10834_Y + connect \$3 $not$libresoc.v:180559$10835_Y + connect \$7 $reduce_or$libresoc.v:180560$10836_Y + connect \en_o \$7 + connect \o { \t1 \t0 } + connect \t1 \$3 + connect \t0 \i [0] + connect \ni \$1 +end +attribute \src "libresoc.v:180570.1-180591.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_CR_cr_b" +attribute \generator "nMigen" +module \rdpick_CR_cr_b + attribute \src "libresoc.v:180585.17-180585.89" + wire $not$libresoc.v:180585$10837_Y + attribute \src "libresoc.v:180586.17-180586.89" + wire $reduce_or$libresoc.v:180586$10838_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" + wire output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" + wire \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" + wire output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + cell $not $not$libresoc.v:180585$10837 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \i + connect \Y $not$libresoc.v:180585$10837_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" + cell $reduce_or $reduce_or$libresoc.v:180586$10838 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:180586$10838_Y + end + connect \$1 $not$libresoc.v:180585$10837_Y + connect \$3 $reduce_or$libresoc.v:180586$10838_Y + connect \en_o \$3 + connect \o \t0 + connect \t0 \i + connect \ni \$1 +end +attribute \src "libresoc.v:180595.1-180616.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_CR_cr_c" +attribute \generator "nMigen" +module \rdpick_CR_cr_c + attribute \src "libresoc.v:180610.17-180610.89" + wire $not$libresoc.v:180610$10839_Y + attribute \src "libresoc.v:180611.17-180611.89" + wire $reduce_or$libresoc.v:180611$10840_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" + wire output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" + wire \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" + wire output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + cell $not $not$libresoc.v:180610$10839 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \i + connect \Y $not$libresoc.v:180610$10839_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" + cell $reduce_or $reduce_or$libresoc.v:180611$10840 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:180611$10840_Y + end + connect \$1 $not$libresoc.v:180610$10839_Y + connect \$3 $reduce_or$libresoc.v:180611$10840_Y + connect \en_o \$3 + connect \o \t0 + connect \t0 \i + connect \ni \$1 +end +attribute \src "libresoc.v:180620.1-180641.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_CR_full_cr" +attribute \generator "nMigen" +module \rdpick_CR_full_cr + attribute \src "libresoc.v:180635.17-180635.89" + wire $not$libresoc.v:180635$10841_Y + attribute \src "libresoc.v:180636.17-180636.89" + wire $reduce_or$libresoc.v:180636$10842_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" + wire output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" + wire \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" + wire output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + cell $not $not$libresoc.v:180635$10841 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \i + connect \Y $not$libresoc.v:180635$10841_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" + cell $reduce_or $reduce_or$libresoc.v:180636$10842 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:180636$10842_Y + end + connect \$1 $not$libresoc.v:180635$10841_Y + connect \$3 $reduce_or$libresoc.v:180636$10842_Y + connect \en_o \$3 + connect \o \t0 + connect \t0 \i + connect \ni \$1 +end +attribute \src "libresoc.v:180645.1-180684.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_FAST_fast1" +attribute \generator "nMigen" +module \rdpick_FAST_fast1 + attribute \src "libresoc.v:180672.17-180672.91" + wire $not$libresoc.v:180672$10843_Y + attribute \src "libresoc.v:180674.17-180674.89" + wire width 3 $not$libresoc.v:180674$10845_Y + attribute \src "libresoc.v:180676.17-180676.91" + wire $not$libresoc.v:180676$10847_Y + attribute \src "libresoc.v:180673.18-180673.90" + wire $reduce_or$libresoc.v:180673$10844_Y + attribute \src "libresoc.v:180675.17-180675.103" + wire $reduce_or$libresoc.v:180675$10846_Y + attribute \src "libresoc.v:180677.17-180677.105" + wire $reduce_or$libresoc.v:180677$10848_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 3 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" + wire output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 3 input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" + wire width 3 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" + wire width 3 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:180672$10843 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $not$libresoc.v:180672$10843_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + cell $not $not$libresoc.v:180674$10845 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \i + connect \Y $not$libresoc.v:180674$10845_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:180676$10847 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$libresoc.v:180676$10847_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" + cell $reduce_or $reduce_or$libresoc.v:180673$10844 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:180673$10844_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:180675$10846 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [0] \ni [1] } + connect \Y $reduce_or$libresoc.v:180675$10846_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:180677$10848 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [1:0] \ni [2] } + connect \Y $reduce_or$libresoc.v:180677$10848_Y + end + connect \$7 $not$libresoc.v:180672$10843_Y + connect \$11 $reduce_or$libresoc.v:180673$10844_Y + connect \$1 $not$libresoc.v:180674$10845_Y + connect \$4 $reduce_or$libresoc.v:180675$10846_Y + connect \$3 $not$libresoc.v:180676$10847_Y + connect \$8 $reduce_or$libresoc.v:180677$10848_Y + connect \en_o \$11 + connect \o { \t2 \t1 \t0 } + connect \t2 \$7 + connect \t1 \$3 + connect \t0 \i [0] + connect \ni \$1 +end +attribute \src "libresoc.v:180688.1-180718.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_FAST_fast2" +attribute \generator "nMigen" +module \rdpick_FAST_fast2 + attribute \src "libresoc.v:180709.17-180709.89" + wire width 2 $not$libresoc.v:180709$10849_Y + attribute \src "libresoc.v:180711.17-180711.91" + wire $not$libresoc.v:180711$10851_Y + attribute \src "libresoc.v:180710.17-180710.103" + wire $reduce_or$libresoc.v:180710$10850_Y + attribute \src "libresoc.v:180712.17-180712.89" + wire $reduce_or$libresoc.v:180712$10852_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 2 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" + wire output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 2 input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" + wire width 2 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" + wire width 2 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + cell $not $not$libresoc.v:180709$10849 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \i + connect \Y $not$libresoc.v:180709$10849_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:180711$10851 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$libresoc.v:180711$10851_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:180710$10850 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [0] \ni [1] } + connect \Y $reduce_or$libresoc.v:180710$10850_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" + cell $reduce_or $reduce_or$libresoc.v:180712$10852 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:180712$10852_Y + end + connect \$1 $not$libresoc.v:180709$10849_Y + connect \$4 $reduce_or$libresoc.v:180710$10850_Y + connect \$3 $not$libresoc.v:180711$10851_Y + connect \$7 $reduce_or$libresoc.v:180712$10852_Y + connect \en_o \$7 + connect \o { \t1 \t0 } + connect \t1 \$3 + connect \t0 \i [0] + connect \ni \$1 +end +attribute \src "libresoc.v:180722.1-180815.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_INT_ra" +attribute \generator "nMigen" +module \rdpick_INT_ra + attribute \src "libresoc.v:180785.17-180785.91" + wire $not$libresoc.v:180785$10853_Y + attribute \src "libresoc.v:180787.18-180787.93" + wire $not$libresoc.v:180787$10855_Y + attribute \src "libresoc.v:180789.18-180789.93" + wire $not$libresoc.v:180789$10857_Y + attribute \src "libresoc.v:180790.17-180790.89" + wire width 9 $not$libresoc.v:180790$10858_Y + attribute \src "libresoc.v:180792.18-180792.93" + wire $not$libresoc.v:180792$10860_Y + attribute \src "libresoc.v:180794.18-180794.93" + wire $not$libresoc.v:180794$10862_Y + attribute \src "libresoc.v:180796.18-180796.93" + wire $not$libresoc.v:180796$10864_Y + attribute \src "libresoc.v:180798.18-180798.93" + wire $not$libresoc.v:180798$10866_Y + attribute \src "libresoc.v:180801.17-180801.91" + wire $not$libresoc.v:180801$10869_Y + attribute \src "libresoc.v:180786.18-180786.106" + wire $reduce_or$libresoc.v:180786$10854_Y + attribute \src "libresoc.v:180788.18-180788.106" + wire $reduce_or$libresoc.v:180788$10856_Y + attribute \src "libresoc.v:180791.18-180791.106" + wire $reduce_or$libresoc.v:180791$10859_Y + attribute \src "libresoc.v:180793.18-180793.106" + wire $reduce_or$libresoc.v:180793$10861_Y + attribute \src "libresoc.v:180795.18-180795.106" + wire $reduce_or$libresoc.v:180795$10863_Y + attribute \src "libresoc.v:180797.18-180797.106" + wire $reduce_or$libresoc.v:180797$10865_Y + attribute \src "libresoc.v:180799.18-180799.90" + wire $reduce_or$libresoc.v:180799$10867_Y + attribute \src "libresoc.v:180800.17-180800.103" + wire $reduce_or$libresoc.v:180800$10868_Y + attribute \src "libresoc.v:180802.17-180802.105" + wire $reduce_or$libresoc.v:180802$10870_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 9 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$32 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" + wire \$35 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" + wire output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 9 input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" + wire width 9 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" + wire width 9 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:180785$10853 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $not$libresoc.v:180785$10853_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:180787$10855 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$12 + connect \Y $not$libresoc.v:180787$10855_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:180789$10857 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$16 + connect \Y $not$libresoc.v:180789$10857_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + cell $not $not$libresoc.v:180790$10858 + parameter \A_SIGNED 0 + parameter \A_WIDTH 9 + parameter \Y_WIDTH 9 + connect \A \i + connect \Y $not$libresoc.v:180790$10858_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:180792$10860 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$20 + connect \Y $not$libresoc.v:180792$10860_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:180794$10862 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$24 + connect \Y $not$libresoc.v:180794$10862_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:180796$10864 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$28 + connect \Y $not$libresoc.v:180796$10864_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:180798$10866 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$32 + connect \Y $not$libresoc.v:180798$10866_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:180801$10869 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$libresoc.v:180801$10869_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:180786$10854 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [2:0] \ni [3] } + connect \Y $reduce_or$libresoc.v:180786$10854_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:180788$10856 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [3:0] \ni [4] } + connect \Y $reduce_or$libresoc.v:180788$10856_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:180791$10859 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A { \i [4:0] \ni [5] } + connect \Y $reduce_or$libresoc.v:180791$10859_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:180793$10861 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A { \i [5:0] \ni [6] } + connect \Y $reduce_or$libresoc.v:180793$10861_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:180795$10863 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A { \i [6:0] \ni [7] } + connect \Y $reduce_or$libresoc.v:180795$10863_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:180797$10865 + parameter \A_SIGNED 0 + parameter \A_WIDTH 9 + parameter \Y_WIDTH 1 + connect \A { \i [7:0] \ni [8] } + connect \Y $reduce_or$libresoc.v:180797$10865_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" + cell $reduce_or $reduce_or$libresoc.v:180799$10867 + parameter \A_SIGNED 0 + parameter \A_WIDTH 9 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:180799$10867_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:180800$10868 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [0] \ni [1] } + connect \Y $reduce_or$libresoc.v:180800$10868_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:180802$10870 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [1:0] \ni [2] } + connect \Y $reduce_or$libresoc.v:180802$10870_Y + end + connect \$7 $not$libresoc.v:180785$10853_Y + connect \$12 $reduce_or$libresoc.v:180786$10854_Y + connect \$11 $not$libresoc.v:180787$10855_Y + connect \$16 $reduce_or$libresoc.v:180788$10856_Y + connect \$15 $not$libresoc.v:180789$10857_Y + connect \$1 $not$libresoc.v:180790$10858_Y + connect \$20 $reduce_or$libresoc.v:180791$10859_Y + connect \$19 $not$libresoc.v:180792$10860_Y + connect \$24 $reduce_or$libresoc.v:180793$10861_Y + connect \$23 $not$libresoc.v:180794$10862_Y + connect \$28 $reduce_or$libresoc.v:180795$10863_Y + connect \$27 $not$libresoc.v:180796$10864_Y + connect \$32 $reduce_or$libresoc.v:180797$10865_Y + connect \$31 $not$libresoc.v:180798$10866_Y + connect \$35 $reduce_or$libresoc.v:180799$10867_Y + connect \$4 $reduce_or$libresoc.v:180800$10868_Y + connect \$3 $not$libresoc.v:180801$10869_Y + connect \$8 $reduce_or$libresoc.v:180802$10870_Y + connect \en_o \$35 + connect \o { \t8 \t7 \t6 \t5 \t4 \t3 \t2 \t1 \t0 } + connect \t8 \$31 + connect \t7 \$27 + connect \t6 \$23 + connect \t5 \$19 + connect \t4 \$15 + connect \t3 \$11 + connect \t2 \$7 + connect \t1 \$3 + connect \t0 \i [0] + connect \ni \$1 +end +attribute \src "libresoc.v:180819.1-180903.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_INT_rb" +attribute \generator "nMigen" +module \rdpick_INT_rb + attribute \src "libresoc.v:180876.17-180876.91" + wire $not$libresoc.v:180876$10871_Y + attribute \src "libresoc.v:180878.18-180878.93" + wire $not$libresoc.v:180878$10873_Y + attribute \src "libresoc.v:180880.18-180880.93" + wire $not$libresoc.v:180880$10875_Y + attribute \src "libresoc.v:180881.17-180881.89" + wire width 8 $not$libresoc.v:180881$10876_Y + attribute \src "libresoc.v:180883.18-180883.93" + wire $not$libresoc.v:180883$10878_Y + attribute \src "libresoc.v:180885.18-180885.93" + wire $not$libresoc.v:180885$10880_Y + attribute \src "libresoc.v:180887.18-180887.93" + wire $not$libresoc.v:180887$10882_Y + attribute \src "libresoc.v:180890.17-180890.91" + wire $not$libresoc.v:180890$10885_Y + attribute \src "libresoc.v:180877.18-180877.106" + wire $reduce_or$libresoc.v:180877$10872_Y + attribute \src "libresoc.v:180879.18-180879.106" + wire $reduce_or$libresoc.v:180879$10874_Y + attribute \src "libresoc.v:180882.18-180882.106" + wire $reduce_or$libresoc.v:180882$10877_Y + attribute \src "libresoc.v:180884.18-180884.106" + wire $reduce_or$libresoc.v:180884$10879_Y + attribute \src "libresoc.v:180886.18-180886.106" + wire $reduce_or$libresoc.v:180886$10881_Y + attribute \src "libresoc.v:180888.18-180888.90" + wire $reduce_or$libresoc.v:180888$10883_Y + attribute \src "libresoc.v:180889.17-180889.103" + wire $reduce_or$libresoc.v:180889$10884_Y + attribute \src "libresoc.v:180891.17-180891.105" + wire $reduce_or$libresoc.v:180891$10886_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 8 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" + wire output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 8 input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" + wire width 8 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" + wire width 8 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:180876$10871 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $not$libresoc.v:180876$10871_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:180878$10873 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$12 + connect \Y $not$libresoc.v:180878$10873_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:180880$10875 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$16 + connect \Y $not$libresoc.v:180880$10875_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + cell $not $not$libresoc.v:180881$10876 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A \i + connect \Y $not$libresoc.v:180881$10876_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:180883$10878 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$20 + connect \Y $not$libresoc.v:180883$10878_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:180885$10880 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$24 + connect \Y $not$libresoc.v:180885$10880_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:180887$10882 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$28 + connect \Y $not$libresoc.v:180887$10882_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:180890$10885 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$libresoc.v:180890$10885_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:180877$10872 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [2:0] \ni [3] } + connect \Y $reduce_or$libresoc.v:180877$10872_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:180879$10874 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [3:0] \ni [4] } + connect \Y $reduce_or$libresoc.v:180879$10874_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:180882$10877 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A { \i [4:0] \ni [5] } + connect \Y $reduce_or$libresoc.v:180882$10877_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:180884$10879 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A { \i [5:0] \ni [6] } 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$reduce_or$libresoc.v:180891$10886 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [1:0] \ni [2] } + connect \Y $reduce_or$libresoc.v:180891$10886_Y + end + connect \$7 $not$libresoc.v:180876$10871_Y + connect \$12 $reduce_or$libresoc.v:180877$10872_Y + connect \$11 $not$libresoc.v:180878$10873_Y + connect \$16 $reduce_or$libresoc.v:180879$10874_Y + connect \$15 $not$libresoc.v:180880$10875_Y + connect \$1 $not$libresoc.v:180881$10876_Y + connect \$20 $reduce_or$libresoc.v:180882$10877_Y + connect \$19 $not$libresoc.v:180883$10878_Y + connect \$24 $reduce_or$libresoc.v:180884$10879_Y + connect \$23 $not$libresoc.v:180885$10880_Y + connect \$28 $reduce_or$libresoc.v:180886$10881_Y + connect \$27 $not$libresoc.v:180887$10882_Y + connect \$31 $reduce_or$libresoc.v:180888$10883_Y + connect \$4 $reduce_or$libresoc.v:180889$10884_Y + connect \$3 $not$libresoc.v:180890$10885_Y + connect \$8 $reduce_or$libresoc.v:180891$10886_Y + connect \en_o \$31 + connect \o { \t7 \t6 \t5 \t4 \t3 \t2 \t1 \t0 } + connect \t7 \$27 + connect \t6 \$23 + connect \t5 \$19 + connect \t4 \$15 + connect \t3 \$11 + connect \t2 \$7 + connect \t1 \$3 + connect \t0 \i [0] + connect \ni \$1 +end +attribute \src "libresoc.v:180907.1-180937.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_INT_rc" +attribute \generator "nMigen" +module \rdpick_INT_rc + attribute \src "libresoc.v:180928.17-180928.89" + wire width 2 $not$libresoc.v:180928$10887_Y + attribute \src "libresoc.v:180930.17-180930.91" + wire $not$libresoc.v:180930$10889_Y + attribute \src "libresoc.v:180929.17-180929.103" + wire $reduce_or$libresoc.v:180929$10888_Y + attribute \src "libresoc.v:180931.17-180931.89" + wire $reduce_or$libresoc.v:180931$10890_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 2 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" + wire output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 2 input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" + wire width 2 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" + wire width 2 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + cell $not $not$libresoc.v:180928$10887 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \i + connect \Y $not$libresoc.v:180928$10887_Y + end + attribute \src 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\src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" + wire output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 3 input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" + wire width 3 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" + wire width 3 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:180993$10893 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $not$libresoc.v:180993$10893_Y + end + attribute \src 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$not$libresoc.v:181024$10899_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" + cell $reduce_or $reduce_or$libresoc.v:181025$10900 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:181025$10900_Y + end + connect \$1 $not$libresoc.v:181024$10899_Y + connect \$3 $reduce_or$libresoc.v:181025$10900_Y + connect \en_o \$3 + connect \o \t0 + connect \t0 \i + connect \ni \$1 +end +attribute \src "libresoc.v:181034.1-181100.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_XER_xer_so" +attribute \generator "nMigen" +module \rdpick_XER_xer_so + attribute \src "libresoc.v:181079.17-181079.91" + wire $not$libresoc.v:181079$10901_Y + attribute \src "libresoc.v:181081.18-181081.93" + wire $not$libresoc.v:181081$10903_Y + attribute \src "libresoc.v:181083.18-181083.93" + wire $not$libresoc.v:181083$10905_Y + attribute \src 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\$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" + wire output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 6 input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" + wire width 6 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" + wire width 6 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:181079$10901 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 + connect 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"/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:181184$10916 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$4 + connect \Y $not$libresoc.v:181184$10916_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:181185$10917 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$7 + connect \Y $not$libresoc.v:181185$10917_Y + end + attribute \src "libresoc.v:181105.7-181105.20" + process $proc$libresoc.v:181105$10995 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:181130.13-181130.30" + process $proc$libresoc.v:181130$10996 + assign { } { } + assign $1\r0__data_o[3:0] 4'0000 + sync always + sync init + update \r0__data_o $1\r0__data_o[3:0] + end + attribute \src "libresoc.v:181137.13-181137.31" + process $proc$libresoc.v:181137$10997 + assign { } { } + assign $1\r20__data_o[3:0] 4'0000 + sync always + sync init + update \r20__data_o $1\r20__data_o[3:0] + end + attribute \src "libresoc.v:181143.13-181143.25" + process $proc$libresoc.v:181143$10998 + assign { } { } + assign $1\reg[3:0] 4'0000 + sync always + sync init + update \reg $1\reg[3:0] + end + attribute \src "libresoc.v:181148.13-181148.33" + process $proc$libresoc.v:181148$10999 + assign { } { } + assign $1\src10__data_o[3:0] 4'0000 + sync always + sync init + update \src10__data_o $1\src10__data_o[3:0] + end + attribute \src "libresoc.v:181155.13-181155.33" + process $proc$libresoc.v:181155$11000 + assign { } { } + assign $1\src20__data_o[3:0] 4'0000 + sync always + sync init + update \src20__data_o $1\src20__data_o[3:0] + end + attribute \src "libresoc.v:181162.13-181162.33" + process $proc$libresoc.v:181162$11001 + assign { } { } + assign $1\src30__data_o[3:0] 4'0000 + sync always + sync init + update \src30__data_o $1\src30__data_o[3:0] + end + attribute \src "libresoc.v:181186.3-181187.25" + process $proc$libresoc.v:181186$10918 + assign { } { } + assign $0\reg[3:0] \reg$next + sync posedge \coresync_clk + update \reg $0\reg[3:0] + end + attribute \src "libresoc.v:181188.3-181189.39" + process $proc$libresoc.v:181188$10919 + assign { } { } + assign $0\r20__data_o[3:0] \r20__data_o$next + sync posedge \coresync_clk + update \r20__data_o $0\r20__data_o[3:0] + end + attribute \src "libresoc.v:181190.3-181191.37" + process $proc$libresoc.v:181190$10920 + assign { } { } + assign $0\r0__data_o[3:0] \r0__data_o$next + sync posedge \coresync_clk + update \r0__data_o $0\r0__data_o[3:0] + end + attribute \src "libresoc.v:181192.3-181193.43" + process $proc$libresoc.v:181192$10921 + assign { } { } + assign $0\src30__data_o[3:0] \src30__data_o$next + sync posedge \coresync_clk + update \src30__data_o $0\src30__data_o[3:0] + end + attribute \src "libresoc.v:181194.3-181195.43" + process $proc$libresoc.v:181194$10922 + assign { } { } + assign $0\src20__data_o[3:0] \src20__data_o$next + sync posedge \coresync_clk + update \src20__data_o $0\src20__data_o[3:0] + end + attribute \src "libresoc.v:181196.3-181197.43" + process $proc$libresoc.v:181196$10923 + assign { } { } + assign $0\src10__data_o[3:0] \src10__data_o$next + sync posedge \coresync_clk + update \src10__data_o $0\src10__data_o[3:0] + end + attribute \src "libresoc.v:181198.3-181237.6" + process $proc$libresoc.v:181198$10924 + assign { } { } + assign { } { } + assign { } { } + assign $0\src10__data_o$next[3:0]$10925 $6\src10__data_o$next[3:0]$10931 + attribute \src "libresoc.v:181199.5-181199.29" + switch \initial + attribute \src "libresoc.v:181199.9-181199.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src10__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src10__data_o$next[3:0]$10926 $5\src10__data_o$next[3:0]$10930 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest10__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src10__data_o$next[3:0]$10927 \dest10__data_i + case + assign $2\src10__data_o$next[3:0]$10927 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest20__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src10__data_o$next[3:0]$10928 \dest20__data_i + case + assign $3\src10__data_o$next[3:0]$10928 $2\src10__data_o$next[3:0]$10927 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src10__data_o$next[3:0]$10929 \w0__data_i + case + assign $4\src10__data_o$next[3:0]$10929 $3\src10__data_o$next[3:0]$10928 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src10__data_o$next[3:0]$10930 \reg + case + assign $5\src10__data_o$next[3:0]$10930 $4\src10__data_o$next[3:0]$10929 + end + case + assign $1\src10__data_o$next[3:0]$10926 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src10__data_o$next[3:0]$10931 4'0000 + case + assign $6\src10__data_o$next[3:0]$10931 $1\src10__data_o$next[3:0]$10926 + end + sync always + update \src10__data_o$next $0\src10__data_o$next[3:0]$10925 + end + attribute \src "libresoc.v:181238.3-181267.6" + process $proc$libresoc.v:181238$10932 + assign { } { } + assign { } { } + assign $0\wr_detect[0:0] $1\wr_detect[0:0] + attribute \src "libresoc.v:181239.5-181239.29" + switch \initial + attribute \src "libresoc.v:181239.9-181239.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src10__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect[0:0] $4\wr_detect[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest10__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect[0:0] 1'1 + case + assign $2\wr_detect[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest20__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect[0:0] 1'1 + case + assign $3\wr_detect[0:0] $2\wr_detect[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect[0:0] 1'1 + case + assign $4\wr_detect[0:0] $3\wr_detect[0:0] + end + case + assign $1\wr_detect[0:0] 1'0 + end + sync always + update \wr_detect $0\wr_detect[0:0] + end + attribute \src "libresoc.v:181268.3-181294.6" + process $proc$libresoc.v:181268$10933 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\reg$next[3:0]$10934 $4\reg$next[3:0]$10938 + attribute \src "libresoc.v:181269.5-181269.29" + switch \initial + attribute \src "libresoc.v:181269.9-181269.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest10__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\reg$next[3:0]$10935 \dest10__data_i + case + assign $1\reg$next[3:0]$10935 \reg + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest20__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\reg$next[3:0]$10936 \dest20__data_i + case + assign $2\reg$next[3:0]$10936 $1\reg$next[3:0]$10935 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \w0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\reg$next[3:0]$10937 \w0__data_i + case + assign $3\reg$next[3:0]$10937 $2\reg$next[3:0]$10936 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\reg$next[3:0]$10938 4'0000 + case + assign $4\reg$next[3:0]$10938 $3\reg$next[3:0]$10937 + end + sync always + update \reg$next $0\reg$next[3:0]$10934 + end + attribute \src "libresoc.v:181295.3-181334.6" + process $proc$libresoc.v:181295$10939 + assign { } { } + assign { } { } + assign { } { } + assign $0\src20__data_o$next[3:0]$10940 $6\src20__data_o$next[3:0]$10946 + attribute \src "libresoc.v:181296.5-181296.29" + switch \initial + attribute \src "libresoc.v:181296.9-181296.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src20__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src20__data_o$next[3:0]$10941 $5\src20__data_o$next[3:0]$10945 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest10__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src20__data_o$next[3:0]$10942 \dest10__data_i + case + assign $2\src20__data_o$next[3:0]$10942 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest20__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src20__data_o$next[3:0]$10943 \dest20__data_i + case + assign $3\src20__data_o$next[3:0]$10943 $2\src20__data_o$next[3:0]$10942 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src20__data_o$next[3:0]$10944 \w0__data_i + case + assign $4\src20__data_o$next[3:0]$10944 $3\src20__data_o$next[3:0]$10943 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src20__data_o$next[3:0]$10945 \reg + case + assign $5\src20__data_o$next[3:0]$10945 $4\src20__data_o$next[3:0]$10944 + end + case + assign $1\src20__data_o$next[3:0]$10941 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src20__data_o$next[3:0]$10946 4'0000 + case + assign $6\src20__data_o$next[3:0]$10946 $1\src20__data_o$next[3:0]$10941 + end + sync always + update \src20__data_o$next $0\src20__data_o$next[3:0]$10940 + end + attribute \src "libresoc.v:181335.3-181364.6" + process $proc$libresoc.v:181335$10947 + assign { } { } + assign { } { } + assign $0\wr_detect$4[0:0]$10948 $1\wr_detect$4[0:0]$10949 + attribute \src "libresoc.v:181336.5-181336.29" + switch \initial + attribute \src "libresoc.v:181336.9-181336.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src20__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$4[0:0]$10949 $4\wr_detect$4[0:0]$10952 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest10__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$4[0:0]$10950 1'1 + case + assign $2\wr_detect$4[0:0]$10950 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest20__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$4[0:0]$10951 1'1 + case + assign $3\wr_detect$4[0:0]$10951 $2\wr_detect$4[0:0]$10950 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$4[0:0]$10952 1'1 + case + assign $4\wr_detect$4[0:0]$10952 $3\wr_detect$4[0:0]$10951 + end + case + assign $1\wr_detect$4[0:0]$10949 1'0 + end + sync always + update \wr_detect$4 $0\wr_detect$4[0:0]$10948 + end + attribute \src "libresoc.v:181365.3-181404.6" + process $proc$libresoc.v:181365$10953 + assign { } { } + assign { } { } + assign { } { } + assign $0\src30__data_o$next[3:0]$10954 $6\src30__data_o$next[3:0]$10960 + attribute \src "libresoc.v:181366.5-181366.29" + switch \initial + attribute \src "libresoc.v:181366.9-181366.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src30__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src30__data_o$next[3:0]$10955 $5\src30__data_o$next[3:0]$10959 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest10__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src30__data_o$next[3:0]$10956 \dest10__data_i + case + assign $2\src30__data_o$next[3:0]$10956 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest20__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src30__data_o$next[3:0]$10957 \dest20__data_i + case + assign $3\src30__data_o$next[3:0]$10957 $2\src30__data_o$next[3:0]$10956 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src30__data_o$next[3:0]$10958 \w0__data_i + case + assign $4\src30__data_o$next[3:0]$10958 $3\src30__data_o$next[3:0]$10957 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$6 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src30__data_o$next[3:0]$10959 \reg + case + assign $5\src30__data_o$next[3:0]$10959 $4\src30__data_o$next[3:0]$10958 + end + case + assign $1\src30__data_o$next[3:0]$10955 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src30__data_o$next[3:0]$10960 4'0000 + case + assign $6\src30__data_o$next[3:0]$10960 $1\src30__data_o$next[3:0]$10955 + end + sync always + update \src30__data_o$next $0\src30__data_o$next[3:0]$10954 + end + attribute \src "libresoc.v:181405.3-181434.6" + process $proc$libresoc.v:181405$10961 + assign { } { } + assign { } { } + assign $0\wr_detect$7[0:0]$10962 $1\wr_detect$7[0:0]$10963 + attribute \src "libresoc.v:181406.5-181406.29" + switch \initial + attribute \src "libresoc.v:181406.9-181406.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src30__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$7[0:0]$10963 $4\wr_detect$7[0:0]$10966 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest10__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$7[0:0]$10964 1'1 + case + assign $2\wr_detect$7[0:0]$10964 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest20__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$7[0:0]$10965 1'1 + case + assign $3\wr_detect$7[0:0]$10965 $2\wr_detect$7[0:0]$10964 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$7[0:0]$10966 1'1 + case + assign $4\wr_detect$7[0:0]$10966 $3\wr_detect$7[0:0]$10965 + end + case + assign $1\wr_detect$7[0:0]$10963 1'0 + end + sync always + update \wr_detect$7 $0\wr_detect$7[0:0]$10962 + end + attribute \src "libresoc.v:181435.3-181474.6" + process $proc$libresoc.v:181435$10967 + assign { } { } + assign { } { } + assign { } { } + assign $0\r0__data_o$next[3:0]$10968 $6\r0__data_o$next[3:0]$10974 + attribute \src "libresoc.v:181436.5-181436.29" + switch \initial + attribute \src "libresoc.v:181436.9-181436.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r0__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\r0__data_o$next[3:0]$10969 $5\r0__data_o$next[3:0]$10973 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest10__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r0__data_o$next[3:0]$10970 \dest10__data_i + case + assign $2\r0__data_o$next[3:0]$10970 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest20__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\r0__data_o$next[3:0]$10971 \dest20__data_i + case + assign $3\r0__data_o$next[3:0]$10971 $2\r0__data_o$next[3:0]$10970 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\r0__data_o$next[3:0]$10972 \w0__data_i + case + assign $4\r0__data_o$next[3:0]$10972 $3\r0__data_o$next[3:0]$10971 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$9 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\r0__data_o$next[3:0]$10973 \reg + case + assign $5\r0__data_o$next[3:0]$10973 $4\r0__data_o$next[3:0]$10972 + end + case + assign $1\r0__data_o$next[3:0]$10969 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\r0__data_o$next[3:0]$10974 4'0000 + case + assign $6\r0__data_o$next[3:0]$10974 $1\r0__data_o$next[3:0]$10969 + end + sync always + update \r0__data_o$next $0\r0__data_o$next[3:0]$10968 + end + attribute \src "libresoc.v:181475.3-181504.6" + process $proc$libresoc.v:181475$10975 + assign { } { } + assign { } { } + assign $0\wr_detect$10[0:0]$10976 $1\wr_detect$10[0:0]$10977 + attribute \src "libresoc.v:181476.5-181476.29" + switch \initial + attribute \src "libresoc.v:181476.9-181476.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r0__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$10[0:0]$10977 $4\wr_detect$10[0:0]$10980 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest10__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$10[0:0]$10978 1'1 + case + assign $2\wr_detect$10[0:0]$10978 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest20__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$10[0:0]$10979 1'1 + case + assign $3\wr_detect$10[0:0]$10979 $2\wr_detect$10[0:0]$10978 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$10[0:0]$10980 1'1 + case + assign $4\wr_detect$10[0:0]$10980 $3\wr_detect$10[0:0]$10979 + end + case + assign $1\wr_detect$10[0:0]$10977 1'0 + end + sync always + update \wr_detect$10 $0\wr_detect$10[0:0]$10976 + end + attribute \src "libresoc.v:181505.3-181544.6" + process $proc$libresoc.v:181505$10981 + assign { } { } + assign { } { } + assign { } { } + assign $0\r20__data_o$next[3:0]$10982 $6\r20__data_o$next[3:0]$10988 + attribute \src "libresoc.v:181506.5-181506.29" + switch \initial + attribute \src "libresoc.v:181506.9-181506.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r20__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\r20__data_o$next[3:0]$10983 $5\r20__data_o$next[3:0]$10987 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest10__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r20__data_o$next[3:0]$10984 \dest10__data_i + case + assign $2\r20__data_o$next[3:0]$10984 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest20__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\r20__data_o$next[3:0]$10985 \dest20__data_i + case + assign $3\r20__data_o$next[3:0]$10985 $2\r20__data_o$next[3:0]$10984 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\r20__data_o$next[3:0]$10986 \w0__data_i + case + assign $4\r20__data_o$next[3:0]$10986 $3\r20__data_o$next[3:0]$10985 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$12 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\r20__data_o$next[3:0]$10987 \reg + case + assign $5\r20__data_o$next[3:0]$10987 $4\r20__data_o$next[3:0]$10986 + end + case + assign $1\r20__data_o$next[3:0]$10983 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\r20__data_o$next[3:0]$10988 4'0000 + case + assign $6\r20__data_o$next[3:0]$10988 $1\r20__data_o$next[3:0]$10983 + end + sync always + update \r20__data_o$next $0\r20__data_o$next[3:0]$10982 + end + attribute \src "libresoc.v:181545.3-181574.6" + process $proc$libresoc.v:181545$10989 + assign { } { } + assign { } { } + assign $0\wr_detect$13[0:0]$10990 $1\wr_detect$13[0:0]$10991 + attribute \src "libresoc.v:181546.5-181546.29" + switch \initial + attribute \src "libresoc.v:181546.9-181546.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r20__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$13[0:0]$10991 $4\wr_detect$13[0:0]$10994 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest10__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$13[0:0]$10992 1'1 + case + assign $2\wr_detect$13[0:0]$10992 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest20__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$13[0:0]$10993 1'1 + case + assign $3\wr_detect$13[0:0]$10993 $2\wr_detect$13[0:0]$10992 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$13[0:0]$10994 1'1 + case + assign $4\wr_detect$13[0:0]$10994 $3\wr_detect$13[0:0]$10993 + end + case + assign $1\wr_detect$13[0:0]$10991 1'0 + end + sync always + update \wr_detect$13 $0\wr_detect$13[0:0]$10990 + end + connect \$9 $not$libresoc.v:181181$10913_Y + connect \$12 $not$libresoc.v:181182$10914_Y + connect \$1 $not$libresoc.v:181183$10915_Y + connect \$3 $not$libresoc.v:181184$10916_Y + connect \$6 $not$libresoc.v:181185$10917_Y +end +attribute \src "libresoc.v:181579.1-182024.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.xer.reg_0" +attribute \generator "nMigen" +module \reg_0$132 + attribute \src "libresoc.v:181580.7-181580.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:181909.3-181954.6" + wire width 2 $0\r0__data_o$next[1:0]$11054 + attribute \src "libresoc.v:181655.3-181656.37" + wire width 2 $0\r0__data_o[1:0] + attribute \src "libresoc.v:181991.3-182023.6" + wire width 2 $0\reg$next[1:0]$11070 + attribute \src "libresoc.v:181653.3-181654.25" + wire width 2 $0\reg[1:0] + attribute \src "libresoc.v:181663.3-181708.6" + wire width 2 $0\src10__data_o$next[1:0]$11012 + attribute \src "libresoc.v:181661.3-181662.43" + wire width 2 $0\src10__data_o[1:0] + attribute \src "libresoc.v:181745.3-181790.6" + wire width 2 $0\src20__data_o$next[1:0]$11022 + attribute \src "libresoc.v:181659.3-181660.43" + wire width 2 $0\src20__data_o[1:0] + attribute \src "libresoc.v:181827.3-181872.6" + wire width 2 $0\src30__data_o$next[1:0]$11038 + attribute \src "libresoc.v:181657.3-181658.43" + wire width 2 $0\src30__data_o[1:0] + attribute \src "libresoc.v:181955.3-181990.6" + wire $0\wr_detect$10[0:0]$11063 + attribute \src "libresoc.v:181791.3-181826.6" + wire $0\wr_detect$4[0:0]$11031 + attribute \src "libresoc.v:181873.3-181908.6" + wire $0\wr_detect$7[0:0]$11047 + attribute \src "libresoc.v:181709.3-181744.6" + wire $0\wr_detect[0:0] + attribute \src "libresoc.v:181909.3-181954.6" + wire width 2 $1\r0__data_o$next[1:0]$11055 + attribute \src "libresoc.v:181607.13-181607.30" + wire width 2 $1\r0__data_o[1:0] + attribute \src "libresoc.v:181991.3-182023.6" + wire width 2 $1\reg$next[1:0]$11071 + attribute \src "libresoc.v:181613.13-181613.25" + wire width 2 $1\reg[1:0] + attribute \src "libresoc.v:181663.3-181708.6" + wire width 2 $1\src10__data_o$next[1:0]$11013 + attribute \src "libresoc.v:181618.13-181618.33" + wire width 2 $1\src10__data_o[1:0] + attribute \src "libresoc.v:181745.3-181790.6" + wire width 2 $1\src20__data_o$next[1:0]$11023 + attribute \src "libresoc.v:181625.13-181625.33" + wire width 2 $1\src20__data_o[1:0] + attribute \src "libresoc.v:181827.3-181872.6" + wire width 2 $1\src30__data_o$next[1:0]$11039 + attribute \src "libresoc.v:181632.13-181632.33" + wire width 2 $1\src30__data_o[1:0] + attribute \src "libresoc.v:181955.3-181990.6" + wire $1\wr_detect$10[0:0]$11064 + attribute \src "libresoc.v:181791.3-181826.6" + wire $1\wr_detect$4[0:0]$11032 + attribute \src "libresoc.v:181873.3-181908.6" + wire $1\wr_detect$7[0:0]$11048 + attribute \src "libresoc.v:181709.3-181744.6" + wire $1\wr_detect[0:0] + attribute \src "libresoc.v:181909.3-181954.6" + wire width 2 $2\r0__data_o$next[1:0]$11056 + attribute \src "libresoc.v:181991.3-182023.6" + wire width 2 $2\reg$next[1:0]$11072 + attribute \src "libresoc.v:181663.3-181708.6" + wire width 2 $2\src10__data_o$next[1:0]$11014 + attribute \src "libresoc.v:181745.3-181790.6" + wire width 2 $2\src20__data_o$next[1:0]$11024 + attribute \src "libresoc.v:181827.3-181872.6" + wire width 2 $2\src30__data_o$next[1:0]$11040 + attribute \src "libresoc.v:181955.3-181990.6" + wire $2\wr_detect$10[0:0]$11065 + attribute \src "libresoc.v:181791.3-181826.6" + wire $2\wr_detect$4[0:0]$11033 + attribute \src "libresoc.v:181873.3-181908.6" + wire $2\wr_detect$7[0:0]$11049 + attribute \src "libresoc.v:181709.3-181744.6" + wire $2\wr_detect[0:0] + attribute \src "libresoc.v:181909.3-181954.6" + wire width 2 $3\r0__data_o$next[1:0]$11057 + attribute \src "libresoc.v:181991.3-182023.6" + wire width 2 $3\reg$next[1:0]$11073 + attribute \src "libresoc.v:181663.3-181708.6" + wire width 2 $3\src10__data_o$next[1:0]$11015 + attribute \src "libresoc.v:181745.3-181790.6" + wire width 2 $3\src20__data_o$next[1:0]$11025 + attribute \src "libresoc.v:181827.3-181872.6" + wire width 2 $3\src30__data_o$next[1:0]$11041 + attribute \src "libresoc.v:181955.3-181990.6" + wire $3\wr_detect$10[0:0]$11066 + attribute \src "libresoc.v:181791.3-181826.6" + wire $3\wr_detect$4[0:0]$11034 + attribute \src "libresoc.v:181873.3-181908.6" + wire $3\wr_detect$7[0:0]$11050 + attribute \src "libresoc.v:181709.3-181744.6" + wire $3\wr_detect[0:0] + attribute \src "libresoc.v:181909.3-181954.6" + wire width 2 $4\r0__data_o$next[1:0]$11058 + attribute \src "libresoc.v:181991.3-182023.6" + wire width 2 $4\reg$next[1:0]$11074 + attribute \src "libresoc.v:181663.3-181708.6" + wire width 2 $4\src10__data_o$next[1:0]$11016 + attribute \src "libresoc.v:181745.3-181790.6" + wire width 2 $4\src20__data_o$next[1:0]$11026 + attribute \src "libresoc.v:181827.3-181872.6" + wire width 2 $4\src30__data_o$next[1:0]$11042 + attribute \src "libresoc.v:181955.3-181990.6" + wire $4\wr_detect$10[0:0]$11067 + attribute \src "libresoc.v:181791.3-181826.6" + wire $4\wr_detect$4[0:0]$11035 + attribute \src "libresoc.v:181873.3-181908.6" + wire $4\wr_detect$7[0:0]$11051 + attribute \src "libresoc.v:181709.3-181744.6" + wire $4\wr_detect[0:0] + attribute \src "libresoc.v:181909.3-181954.6" + wire width 2 $5\r0__data_o$next[1:0]$11059 + attribute \src "libresoc.v:181991.3-182023.6" + wire width 2 $5\reg$next[1:0]$11075 + attribute \src "libresoc.v:181663.3-181708.6" + wire width 2 $5\src10__data_o$next[1:0]$11017 + attribute \src "libresoc.v:181745.3-181790.6" + wire width 2 $5\src20__data_o$next[1:0]$11027 + attribute \src "libresoc.v:181827.3-181872.6" + wire width 2 $5\src30__data_o$next[1:0]$11043 + attribute \src "libresoc.v:181955.3-181990.6" + wire $5\wr_detect$10[0:0]$11068 + attribute \src "libresoc.v:181791.3-181826.6" + wire $5\wr_detect$4[0:0]$11036 + attribute \src "libresoc.v:181873.3-181908.6" + wire $5\wr_detect$7[0:0]$11052 + attribute \src "libresoc.v:181709.3-181744.6" + wire $5\wr_detect[0:0] + attribute \src "libresoc.v:181909.3-181954.6" + wire width 2 $6\r0__data_o$next[1:0]$11060 + attribute \src "libresoc.v:181663.3-181708.6" + wire width 2 $6\src10__data_o$next[1:0]$11018 + attribute \src "libresoc.v:181745.3-181790.6" + wire width 2 $6\src20__data_o$next[1:0]$11028 + attribute \src "libresoc.v:181827.3-181872.6" + wire width 2 $6\src30__data_o$next[1:0]$11044 + attribute \src "libresoc.v:181909.3-181954.6" + wire width 2 $7\r0__data_o$next[1:0]$11061 + attribute \src "libresoc.v:181663.3-181708.6" + wire width 2 $7\src10__data_o$next[1:0]$11019 + attribute \src "libresoc.v:181745.3-181790.6" + wire width 2 $7\src20__data_o$next[1:0]$11029 + attribute \src "libresoc.v:181827.3-181872.6" + wire width 2 $7\src30__data_o$next[1:0]$11045 + attribute \src "libresoc.v:181649.17-181649.104" + wire $not$libresoc.v:181649$11002_Y + attribute \src "libresoc.v:181650.17-181650.100" + wire $not$libresoc.v:181650$11003_Y + attribute \src "libresoc.v:181651.17-181651.103" + wire $not$libresoc.v:181651$11004_Y + attribute \src "libresoc.v:181652.17-181652.103" + wire $not$libresoc.v:181652$11005_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 18 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 2 input 9 \dest10__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 8 \dest10__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 2 input 11 \dest20__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 10 \dest20__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 2 input 13 \dest30__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 12 \dest30__wen + attribute \src "libresoc.v:181580.7-181580.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 2 output 14 \r0__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 2 \r0__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 15 \r0__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 2 \reg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 2 \reg$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 2 output 3 \src10__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 2 \src10__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 2 \src10__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 2 output 5 \src20__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 2 \src20__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 4 \src20__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 2 output 7 \src30__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 2 \src30__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 6 \src30__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 2 input 16 \w0__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 17 \w0__wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:181649$11002 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$10 + connect \Y $not$libresoc.v:181649$11002_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:181650$11003 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect + connect \Y $not$libresoc.v:181650$11003_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:181651$11004 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$4 + connect \Y $not$libresoc.v:181651$11004_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:181652$11005 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$7 + connect \Y $not$libresoc.v:181652$11005_Y + end + attribute \src "libresoc.v:181580.7-181580.20" + process $proc$libresoc.v:181580$11076 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:181607.13-181607.30" + process $proc$libresoc.v:181607$11077 + assign { } { } + assign $1\r0__data_o[1:0] 2'00 + sync always + sync init + update \r0__data_o $1\r0__data_o[1:0] + end + attribute \src "libresoc.v:181613.13-181613.25" + process $proc$libresoc.v:181613$11078 + assign { } { } + assign $1\reg[1:0] 2'00 + sync always + sync init + update \reg $1\reg[1:0] + end + attribute \src "libresoc.v:181618.13-181618.33" + process $proc$libresoc.v:181618$11079 + assign { } { } + assign $1\src10__data_o[1:0] 2'00 + sync always + sync init + update \src10__data_o $1\src10__data_o[1:0] + end + attribute \src "libresoc.v:181625.13-181625.33" + process $proc$libresoc.v:181625$11080 + assign { } { } + assign $1\src20__data_o[1:0] 2'00 + sync always + sync init + update \src20__data_o $1\src20__data_o[1:0] + end + attribute \src "libresoc.v:181632.13-181632.33" + process $proc$libresoc.v:181632$11081 + assign { } { } + assign $1\src30__data_o[1:0] 2'00 + sync always + sync init + update \src30__data_o $1\src30__data_o[1:0] + end + attribute \src "libresoc.v:181653.3-181654.25" + process $proc$libresoc.v:181653$11006 + assign { } { } + assign $0\reg[1:0] \reg$next + sync posedge \coresync_clk + update \reg $0\reg[1:0] + end + attribute \src "libresoc.v:181655.3-181656.37" + process $proc$libresoc.v:181655$11007 + assign { } { } + assign $0\r0__data_o[1:0] \r0__data_o$next + sync posedge \coresync_clk + update \r0__data_o $0\r0__data_o[1:0] + end + attribute \src "libresoc.v:181657.3-181658.43" + process $proc$libresoc.v:181657$11008 + assign { } { } + assign $0\src30__data_o[1:0] \src30__data_o$next + sync posedge \coresync_clk + update \src30__data_o $0\src30__data_o[1:0] + end + attribute \src "libresoc.v:181659.3-181660.43" + process $proc$libresoc.v:181659$11009 + assign { } { } + assign $0\src20__data_o[1:0] \src20__data_o$next + sync posedge \coresync_clk + update \src20__data_o $0\src20__data_o[1:0] + end + attribute \src "libresoc.v:181661.3-181662.43" + process $proc$libresoc.v:181661$11010 + assign { } { } + assign $0\src10__data_o[1:0] \src10__data_o$next + sync posedge \coresync_clk + update \src10__data_o $0\src10__data_o[1:0] + end + attribute \src "libresoc.v:181663.3-181708.6" + process $proc$libresoc.v:181663$11011 + assign { } { } + assign { } { } + assign { } { } + assign $0\src10__data_o$next[1:0]$11012 $7\src10__data_o$next[1:0]$11019 + attribute \src "libresoc.v:181664.5-181664.29" + switch \initial + attribute \src "libresoc.v:181664.9-181664.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src10__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src10__data_o$next[1:0]$11013 $6\src10__data_o$next[1:0]$11018 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest10__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src10__data_o$next[1:0]$11014 \dest10__data_i + case + assign $2\src10__data_o$next[1:0]$11014 2'00 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest20__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src10__data_o$next[1:0]$11015 \dest20__data_i + case + assign $3\src10__data_o$next[1:0]$11015 $2\src10__data_o$next[1:0]$11014 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest30__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src10__data_o$next[1:0]$11016 \dest30__data_i + case + assign $4\src10__data_o$next[1:0]$11016 $3\src10__data_o$next[1:0]$11015 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src10__data_o$next[1:0]$11017 \w0__data_i + case + assign $5\src10__data_o$next[1:0]$11017 $4\src10__data_o$next[1:0]$11016 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src10__data_o$next[1:0]$11018 \reg + case + assign $6\src10__data_o$next[1:0]$11018 $5\src10__data_o$next[1:0]$11017 + end + case + assign $1\src10__data_o$next[1:0]$11013 2'00 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\src10__data_o$next[1:0]$11019 2'00 + case + assign $7\src10__data_o$next[1:0]$11019 $1\src10__data_o$next[1:0]$11013 + end + sync always + update \src10__data_o$next $0\src10__data_o$next[1:0]$11012 + end + attribute \src "libresoc.v:181709.3-181744.6" + process $proc$libresoc.v:181709$11020 + assign { } { } + assign { } { } + assign $0\wr_detect[0:0] $1\wr_detect[0:0] + attribute \src "libresoc.v:181710.5-181710.29" + switch \initial + attribute \src "libresoc.v:181710.9-181710.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src10__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect[0:0] $5\wr_detect[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest10__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect[0:0] 1'1 + case + assign $2\wr_detect[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest20__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect[0:0] 1'1 + case + assign $3\wr_detect[0:0] $2\wr_detect[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest30__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect[0:0] 1'1 + case + assign $4\wr_detect[0:0] $3\wr_detect[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\wr_detect[0:0] 1'1 + case + assign $5\wr_detect[0:0] $4\wr_detect[0:0] + end + case + assign $1\wr_detect[0:0] 1'0 + end + sync always + update \wr_detect $0\wr_detect[0:0] + end + attribute \src "libresoc.v:181745.3-181790.6" + process $proc$libresoc.v:181745$11021 + assign { } { } + assign { } { } + assign { } { } + assign $0\src20__data_o$next[1:0]$11022 $7\src20__data_o$next[1:0]$11029 + attribute \src "libresoc.v:181746.5-181746.29" + switch \initial + attribute \src "libresoc.v:181746.9-181746.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src20__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src20__data_o$next[1:0]$11023 $6\src20__data_o$next[1:0]$11028 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest10__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src20__data_o$next[1:0]$11024 \dest10__data_i + case + assign $2\src20__data_o$next[1:0]$11024 2'00 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest20__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src20__data_o$next[1:0]$11025 \dest20__data_i + case + assign $3\src20__data_o$next[1:0]$11025 $2\src20__data_o$next[1:0]$11024 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest30__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src20__data_o$next[1:0]$11026 \dest30__data_i + case + assign $4\src20__data_o$next[1:0]$11026 $3\src20__data_o$next[1:0]$11025 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src20__data_o$next[1:0]$11027 \w0__data_i + case + assign $5\src20__data_o$next[1:0]$11027 $4\src20__data_o$next[1:0]$11026 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src20__data_o$next[1:0]$11028 \reg + case + assign $6\src20__data_o$next[1:0]$11028 $5\src20__data_o$next[1:0]$11027 + end + case + assign $1\src20__data_o$next[1:0]$11023 2'00 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\src20__data_o$next[1:0]$11029 2'00 + case + assign $7\src20__data_o$next[1:0]$11029 $1\src20__data_o$next[1:0]$11023 + end + sync always + update \src20__data_o$next $0\src20__data_o$next[1:0]$11022 + end + attribute \src "libresoc.v:181791.3-181826.6" + process $proc$libresoc.v:181791$11030 + assign { } { } + assign { } { } + assign $0\wr_detect$4[0:0]$11031 $1\wr_detect$4[0:0]$11032 + attribute \src "libresoc.v:181792.5-181792.29" + switch \initial + attribute \src "libresoc.v:181792.9-181792.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src20__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$4[0:0]$11032 $5\wr_detect$4[0:0]$11036 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest10__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$4[0:0]$11033 1'1 + case + assign $2\wr_detect$4[0:0]$11033 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest20__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$4[0:0]$11034 1'1 + case + assign $3\wr_detect$4[0:0]$11034 $2\wr_detect$4[0:0]$11033 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest30__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$4[0:0]$11035 1'1 + case + assign $4\wr_detect$4[0:0]$11035 $3\wr_detect$4[0:0]$11034 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\wr_detect$4[0:0]$11036 1'1 + case + assign $5\wr_detect$4[0:0]$11036 $4\wr_detect$4[0:0]$11035 + end + case + assign $1\wr_detect$4[0:0]$11032 1'0 + end + sync always + update \wr_detect$4 $0\wr_detect$4[0:0]$11031 + end + attribute \src "libresoc.v:181827.3-181872.6" + process $proc$libresoc.v:181827$11037 + assign { } { } + assign { } { } + assign { } { } + assign $0\src30__data_o$next[1:0]$11038 $7\src30__data_o$next[1:0]$11045 + attribute \src "libresoc.v:181828.5-181828.29" + switch \initial + attribute \src "libresoc.v:181828.9-181828.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src30__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src30__data_o$next[1:0]$11039 $6\src30__data_o$next[1:0]$11044 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest10__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src30__data_o$next[1:0]$11040 \dest10__data_i + case + assign $2\src30__data_o$next[1:0]$11040 2'00 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest20__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src30__data_o$next[1:0]$11041 \dest20__data_i + case + assign $3\src30__data_o$next[1:0]$11041 $2\src30__data_o$next[1:0]$11040 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest30__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src30__data_o$next[1:0]$11042 \dest30__data_i + case + assign $4\src30__data_o$next[1:0]$11042 $3\src30__data_o$next[1:0]$11041 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src30__data_o$next[1:0]$11043 \w0__data_i + case + assign $5\src30__data_o$next[1:0]$11043 $4\src30__data_o$next[1:0]$11042 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$6 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src30__data_o$next[1:0]$11044 \reg + case + assign $6\src30__data_o$next[1:0]$11044 $5\src30__data_o$next[1:0]$11043 + end + case + assign $1\src30__data_o$next[1:0]$11039 2'00 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\src30__data_o$next[1:0]$11045 2'00 + case + assign $7\src30__data_o$next[1:0]$11045 $1\src30__data_o$next[1:0]$11039 + end + sync always + update \src30__data_o$next $0\src30__data_o$next[1:0]$11038 + end + attribute \src "libresoc.v:181873.3-181908.6" + process $proc$libresoc.v:181873$11046 + assign { } { } + assign { } { } + assign $0\wr_detect$7[0:0]$11047 $1\wr_detect$7[0:0]$11048 + attribute \src "libresoc.v:181874.5-181874.29" + switch \initial + attribute \src "libresoc.v:181874.9-181874.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src30__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$7[0:0]$11048 $5\wr_detect$7[0:0]$11052 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest10__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$7[0:0]$11049 1'1 + case + assign $2\wr_detect$7[0:0]$11049 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest20__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$7[0:0]$11050 1'1 + case + assign $3\wr_detect$7[0:0]$11050 $2\wr_detect$7[0:0]$11049 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest30__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$7[0:0]$11051 1'1 + case + assign $4\wr_detect$7[0:0]$11051 $3\wr_detect$7[0:0]$11050 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\wr_detect$7[0:0]$11052 1'1 + case + assign $5\wr_detect$7[0:0]$11052 $4\wr_detect$7[0:0]$11051 + end + case + assign $1\wr_detect$7[0:0]$11048 1'0 + end + sync always + update \wr_detect$7 $0\wr_detect$7[0:0]$11047 + end + attribute \src "libresoc.v:181909.3-181954.6" + process $proc$libresoc.v:181909$11053 + assign { } { } + assign { } { } + assign { } { } + assign $0\r0__data_o$next[1:0]$11054 $7\r0__data_o$next[1:0]$11061 + attribute \src "libresoc.v:181910.5-181910.29" + switch \initial + attribute \src "libresoc.v:181910.9-181910.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r0__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\r0__data_o$next[1:0]$11055 $6\r0__data_o$next[1:0]$11060 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest10__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r0__data_o$next[1:0]$11056 \dest10__data_i + case + assign $2\r0__data_o$next[1:0]$11056 2'00 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest20__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\r0__data_o$next[1:0]$11057 \dest20__data_i + case + assign $3\r0__data_o$next[1:0]$11057 $2\r0__data_o$next[1:0]$11056 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest30__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\r0__data_o$next[1:0]$11058 \dest30__data_i + case + assign $4\r0__data_o$next[1:0]$11058 $3\r0__data_o$next[1:0]$11057 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\r0__data_o$next[1:0]$11059 \w0__data_i + case + assign $5\r0__data_o$next[1:0]$11059 $4\r0__data_o$next[1:0]$11058 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$9 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\r0__data_o$next[1:0]$11060 \reg + case + assign $6\r0__data_o$next[1:0]$11060 $5\r0__data_o$next[1:0]$11059 + end + case + assign $1\r0__data_o$next[1:0]$11055 2'00 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\r0__data_o$next[1:0]$11061 2'00 + case + assign $7\r0__data_o$next[1:0]$11061 $1\r0__data_o$next[1:0]$11055 + end + sync always + update \r0__data_o$next $0\r0__data_o$next[1:0]$11054 + end + attribute \src "libresoc.v:181955.3-181990.6" + process $proc$libresoc.v:181955$11062 + assign { } { } + assign { } { } + assign $0\wr_detect$10[0:0]$11063 $1\wr_detect$10[0:0]$11064 + attribute \src "libresoc.v:181956.5-181956.29" + switch \initial + attribute \src "libresoc.v:181956.9-181956.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r0__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$10[0:0]$11064 $5\wr_detect$10[0:0]$11068 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest10__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$10[0:0]$11065 1'1 + case + assign $2\wr_detect$10[0:0]$11065 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest20__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$10[0:0]$11066 1'1 + case + assign $3\wr_detect$10[0:0]$11066 $2\wr_detect$10[0:0]$11065 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest30__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$10[0:0]$11067 1'1 + case + assign $4\wr_detect$10[0:0]$11067 $3\wr_detect$10[0:0]$11066 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\wr_detect$10[0:0]$11068 1'1 + case + assign $5\wr_detect$10[0:0]$11068 $4\wr_detect$10[0:0]$11067 + end + case + assign $1\wr_detect$10[0:0]$11064 1'0 + end + sync always + update \wr_detect$10 $0\wr_detect$10[0:0]$11063 + end + attribute \src "libresoc.v:181991.3-182023.6" + process $proc$libresoc.v:181991$11069 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\reg$next[1:0]$11070 $5\reg$next[1:0]$11075 + attribute \src "libresoc.v:181992.5-181992.29" + switch \initial + attribute \src "libresoc.v:181992.9-181992.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest10__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\reg$next[1:0]$11071 \dest10__data_i + case + assign $1\reg$next[1:0]$11071 \reg + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest20__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\reg$next[1:0]$11072 \dest20__data_i + case + assign $2\reg$next[1:0]$11072 $1\reg$next[1:0]$11071 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest30__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\reg$next[1:0]$11073 \dest30__data_i + case + assign $3\reg$next[1:0]$11073 $2\reg$next[1:0]$11072 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \w0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\reg$next[1:0]$11074 \w0__data_i + case + assign $4\reg$next[1:0]$11074 $3\reg$next[1:0]$11073 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\reg$next[1:0]$11075 2'00 + case + assign $5\reg$next[1:0]$11075 $4\reg$next[1:0]$11074 + end + sync always + update \reg$next $0\reg$next[1:0]$11070 + end + connect \$9 $not$libresoc.v:181649$11002_Y + connect \$1 $not$libresoc.v:181650$11003_Y + connect \$3 $not$libresoc.v:181651$11004_Y + connect \$6 $not$libresoc.v:181652$11005_Y +end +attribute \src "libresoc.v:182028.1-182377.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.state.reg_0" +attribute \generator "nMigen" +module \reg_0$135 + attribute \src "libresoc.v:182098.3-182143.6" + wire width 64 $0\cia0__data_o$next[63:0]$11090 + attribute \src "libresoc.v:182096.3-182097.41" + wire width 64 $0\cia0__data_o[63:0] + attribute \src "libresoc.v:182029.7-182029.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:182180.3-182225.6" + wire width 64 $0\msr0__data_o$next[63:0]$11100 + attribute \src "libresoc.v:182094.3-182095.41" + wire width 64 $0\msr0__data_o[63:0] + attribute \src "libresoc.v:182344.3-182376.6" + wire width 64 $0\reg$next[63:0]$11132 + attribute \src "libresoc.v:182090.3-182091.25" + wire width 64 $0\reg[63:0] + attribute \src "libresoc.v:182262.3-182307.6" + wire width 64 $0\sv0__data_o$next[63:0]$11116 + attribute \src "libresoc.v:182092.3-182093.39" + wire width 64 $0\sv0__data_o[63:0] + attribute \src "libresoc.v:182226.3-182261.6" + wire $0\wr_detect$4[0:0]$11109 + attribute \src "libresoc.v:182308.3-182343.6" + wire $0\wr_detect$7[0:0]$11125 + attribute \src "libresoc.v:182144.3-182179.6" + wire $0\wr_detect[0:0] + attribute \src "libresoc.v:182098.3-182143.6" + wire width 64 $1\cia0__data_o$next[63:0]$11091 + attribute \src "libresoc.v:182038.14-182038.49" + wire width 64 $1\cia0__data_o[63:0] + attribute \src "libresoc.v:182180.3-182225.6" + wire width 64 $1\msr0__data_o$next[63:0]$11101 + attribute \src "libresoc.v:182055.14-182055.49" + wire width 64 $1\msr0__data_o[63:0] + attribute \src "libresoc.v:182344.3-182376.6" + wire width 64 $1\reg$next[63:0]$11133 + attribute \src "libresoc.v:182067.14-182067.42" + wire width 64 $1\reg[63:0] + attribute \src "libresoc.v:182262.3-182307.6" + wire width 64 $1\sv0__data_o$next[63:0]$11117 + attribute \src "libresoc.v:182074.14-182074.48" + wire width 64 $1\sv0__data_o[63:0] + attribute \src "libresoc.v:182226.3-182261.6" + wire $1\wr_detect$4[0:0]$11110 + attribute \src "libresoc.v:182308.3-182343.6" + wire $1\wr_detect$7[0:0]$11126 + attribute \src "libresoc.v:182144.3-182179.6" + wire $1\wr_detect[0:0] + attribute \src "libresoc.v:182098.3-182143.6" + wire width 64 $2\cia0__data_o$next[63:0]$11092 + attribute \src "libresoc.v:182180.3-182225.6" + wire width 64 $2\msr0__data_o$next[63:0]$11102 + attribute \src "libresoc.v:182344.3-182376.6" + wire width 64 $2\reg$next[63:0]$11134 + attribute \src "libresoc.v:182262.3-182307.6" + wire width 64 $2\sv0__data_o$next[63:0]$11118 + attribute \src "libresoc.v:182226.3-182261.6" + wire $2\wr_detect$4[0:0]$11111 + attribute \src "libresoc.v:182308.3-182343.6" + wire $2\wr_detect$7[0:0]$11127 + attribute \src "libresoc.v:182144.3-182179.6" + wire $2\wr_detect[0:0] + attribute \src "libresoc.v:182098.3-182143.6" + wire width 64 $3\cia0__data_o$next[63:0]$11093 + attribute \src "libresoc.v:182180.3-182225.6" + wire width 64 $3\msr0__data_o$next[63:0]$11103 + attribute \src "libresoc.v:182344.3-182376.6" + wire width 64 $3\reg$next[63:0]$11135 + attribute \src "libresoc.v:182262.3-182307.6" + wire width 64 $3\sv0__data_o$next[63:0]$11119 + attribute \src "libresoc.v:182226.3-182261.6" + wire $3\wr_detect$4[0:0]$11112 + attribute \src "libresoc.v:182308.3-182343.6" + wire $3\wr_detect$7[0:0]$11128 + attribute \src "libresoc.v:182144.3-182179.6" + wire $3\wr_detect[0:0] + attribute \src "libresoc.v:182098.3-182143.6" + wire width 64 $4\cia0__data_o$next[63:0]$11094 + attribute \src "libresoc.v:182180.3-182225.6" + wire width 64 $4\msr0__data_o$next[63:0]$11104 + attribute \src "libresoc.v:182344.3-182376.6" + wire width 64 $4\reg$next[63:0]$11136 + attribute \src "libresoc.v:182262.3-182307.6" + wire width 64 $4\sv0__data_o$next[63:0]$11120 + attribute \src "libresoc.v:182226.3-182261.6" + wire $4\wr_detect$4[0:0]$11113 + attribute \src "libresoc.v:182308.3-182343.6" + wire $4\wr_detect$7[0:0]$11129 + attribute \src "libresoc.v:182144.3-182179.6" + wire $4\wr_detect[0:0] + attribute \src "libresoc.v:182098.3-182143.6" + wire width 64 $5\cia0__data_o$next[63:0]$11095 + attribute \src "libresoc.v:182180.3-182225.6" + wire width 64 $5\msr0__data_o$next[63:0]$11105 + attribute \src "libresoc.v:182344.3-182376.6" + wire width 64 $5\reg$next[63:0]$11137 + attribute \src "libresoc.v:182262.3-182307.6" + wire width 64 $5\sv0__data_o$next[63:0]$11121 + attribute \src "libresoc.v:182226.3-182261.6" + wire $5\wr_detect$4[0:0]$11114 + attribute \src "libresoc.v:182308.3-182343.6" + wire $5\wr_detect$7[0:0]$11130 + attribute \src "libresoc.v:182144.3-182179.6" + wire $5\wr_detect[0:0] + attribute \src "libresoc.v:182098.3-182143.6" + wire width 64 $6\cia0__data_o$next[63:0]$11096 + attribute \src "libresoc.v:182180.3-182225.6" + wire width 64 $6\msr0__data_o$next[63:0]$11106 + attribute \src "libresoc.v:182262.3-182307.6" + wire width 64 $6\sv0__data_o$next[63:0]$11122 + attribute \src "libresoc.v:182098.3-182143.6" + wire width 64 $7\cia0__data_o$next[63:0]$11097 + attribute \src "libresoc.v:182180.3-182225.6" + wire width 64 $7\msr0__data_o$next[63:0]$11107 + attribute \src "libresoc.v:182262.3-182307.6" + wire width 64 $7\sv0__data_o$next[63:0]$11123 + attribute \src "libresoc.v:182087.17-182087.100" + wire $not$libresoc.v:182087$11082_Y + attribute \src "libresoc.v:182088.17-182088.103" + wire $not$libresoc.v:182088$11083_Y + attribute \src "libresoc.v:182089.17-182089.103" + wire $not$libresoc.v:182089$11084_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 output 3 \cia0__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 \cia0__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 2 \cia0__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 16 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 input 15 \d_wr10__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 14 \d_wr10__wen + attribute \src "libresoc.v:182029.7-182029.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 input 11 \msr0__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 output 5 \msr0__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 \msr0__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 4 \msr0__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 10 \msr0__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 input 9 \nia0__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 8 \nia0__wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 64 \reg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 64 \reg$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 input 13 \sv0__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 output 7 \sv0__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 \sv0__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 6 \sv0__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 12 \sv0__wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:182087$11082 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect + connect \Y $not$libresoc.v:182087$11082_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:182088$11083 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$4 + connect \Y $not$libresoc.v:182088$11083_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:182089$11084 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$7 + connect \Y $not$libresoc.v:182089$11084_Y + end + attribute \src "libresoc.v:182029.7-182029.20" + process $proc$libresoc.v:182029$11138 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:182038.14-182038.49" + process $proc$libresoc.v:182038$11139 + assign { } { } + assign $1\cia0__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \cia0__data_o $1\cia0__data_o[63:0] + end + attribute \src "libresoc.v:182055.14-182055.49" + process $proc$libresoc.v:182055$11140 + assign { } { } + assign $1\msr0__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \msr0__data_o $1\msr0__data_o[63:0] + end + attribute \src "libresoc.v:182067.14-182067.42" + process $proc$libresoc.v:182067$11141 + assign { } { } + assign $1\reg[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \reg $1\reg[63:0] + end + attribute \src "libresoc.v:182074.14-182074.48" + process $proc$libresoc.v:182074$11142 + assign { } { } + assign $1\sv0__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \sv0__data_o $1\sv0__data_o[63:0] + end + attribute \src "libresoc.v:182090.3-182091.25" + process $proc$libresoc.v:182090$11085 + assign { } { } + assign $0\reg[63:0] \reg$next + sync posedge \coresync_clk + update \reg $0\reg[63:0] + end + attribute \src "libresoc.v:182092.3-182093.39" + process $proc$libresoc.v:182092$11086 + assign { } { } + assign $0\sv0__data_o[63:0] \sv0__data_o$next + sync posedge \coresync_clk + update \sv0__data_o $0\sv0__data_o[63:0] + end + attribute \src "libresoc.v:182094.3-182095.41" + process $proc$libresoc.v:182094$11087 + assign { } { } + assign $0\msr0__data_o[63:0] \msr0__data_o$next + sync posedge \coresync_clk + update \msr0__data_o $0\msr0__data_o[63:0] + end + attribute \src "libresoc.v:182096.3-182097.41" + process $proc$libresoc.v:182096$11088 + assign { } { } + assign $0\cia0__data_o[63:0] \cia0__data_o$next + sync posedge \coresync_clk + update \cia0__data_o $0\cia0__data_o[63:0] + end + attribute \src "libresoc.v:182098.3-182143.6" + process $proc$libresoc.v:182098$11089 + assign { } { } + assign { } { } + assign { } { } + assign $0\cia0__data_o$next[63:0]$11090 $7\cia0__data_o$next[63:0]$11097 + attribute \src "libresoc.v:182099.5-182099.29" + switch \initial + attribute \src "libresoc.v:182099.9-182099.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \cia0__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\cia0__data_o$next[63:0]$11091 $6\cia0__data_o$next[63:0]$11096 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \nia0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cia0__data_o$next[63:0]$11092 \nia0__data_i + case + assign $2\cia0__data_o$next[63:0]$11092 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \msr0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\cia0__data_o$next[63:0]$11093 \msr0__data_i + case + assign $3\cia0__data_o$next[63:0]$11093 $2\cia0__data_o$next[63:0]$11092 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \sv0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\cia0__data_o$next[63:0]$11094 \sv0__data_i + case + assign $4\cia0__data_o$next[63:0]$11094 $3\cia0__data_o$next[63:0]$11093 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \d_wr10__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\cia0__data_o$next[63:0]$11095 \d_wr10__data_i + case + assign $5\cia0__data_o$next[63:0]$11095 $4\cia0__data_o$next[63:0]$11094 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\cia0__data_o$next[63:0]$11096 \reg + case + assign $6\cia0__data_o$next[63:0]$11096 $5\cia0__data_o$next[63:0]$11095 + end + case + assign $1\cia0__data_o$next[63:0]$11091 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\cia0__data_o$next[63:0]$11097 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $7\cia0__data_o$next[63:0]$11097 $1\cia0__data_o$next[63:0]$11091 + end + sync always + update \cia0__data_o$next $0\cia0__data_o$next[63:0]$11090 + end + attribute \src "libresoc.v:182144.3-182179.6" + process $proc$libresoc.v:182144$11098 + assign { } { } + assign { } { } + assign $0\wr_detect[0:0] $1\wr_detect[0:0] + attribute \src "libresoc.v:182145.5-182145.29" + switch \initial + attribute \src "libresoc.v:182145.9-182145.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \cia0__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect[0:0] $5\wr_detect[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \nia0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect[0:0] 1'1 + case + assign $2\wr_detect[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \msr0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect[0:0] 1'1 + case + assign $3\wr_detect[0:0] $2\wr_detect[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \sv0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect[0:0] 1'1 + case + assign $4\wr_detect[0:0] $3\wr_detect[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \d_wr10__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\wr_detect[0:0] 1'1 + case + assign $5\wr_detect[0:0] $4\wr_detect[0:0] + end + case + assign $1\wr_detect[0:0] 1'0 + end + sync always + update \wr_detect $0\wr_detect[0:0] + end + attribute \src "libresoc.v:182180.3-182225.6" + process $proc$libresoc.v:182180$11099 + assign { } { } + assign { } { } + assign { } { } + assign $0\msr0__data_o$next[63:0]$11100 $7\msr0__data_o$next[63:0]$11107 + attribute \src "libresoc.v:182181.5-182181.29" + switch \initial + attribute \src "libresoc.v:182181.9-182181.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \msr0__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\msr0__data_o$next[63:0]$11101 $6\msr0__data_o$next[63:0]$11106 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \nia0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\msr0__data_o$next[63:0]$11102 \nia0__data_i + case + assign $2\msr0__data_o$next[63:0]$11102 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \msr0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\msr0__data_o$next[63:0]$11103 \msr0__data_i + case + assign $3\msr0__data_o$next[63:0]$11103 $2\msr0__data_o$next[63:0]$11102 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \sv0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\msr0__data_o$next[63:0]$11104 \sv0__data_i + case + assign $4\msr0__data_o$next[63:0]$11104 $3\msr0__data_o$next[63:0]$11103 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \d_wr10__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\msr0__data_o$next[63:0]$11105 \d_wr10__data_i + case + assign $5\msr0__data_o$next[63:0]$11105 $4\msr0__data_o$next[63:0]$11104 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\msr0__data_o$next[63:0]$11106 \reg + case + assign $6\msr0__data_o$next[63:0]$11106 $5\msr0__data_o$next[63:0]$11105 + end + case + assign $1\msr0__data_o$next[63:0]$11101 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\msr0__data_o$next[63:0]$11107 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $7\msr0__data_o$next[63:0]$11107 $1\msr0__data_o$next[63:0]$11101 + end + sync always + update \msr0__data_o$next $0\msr0__data_o$next[63:0]$11100 + end + attribute \src "libresoc.v:182226.3-182261.6" + process $proc$libresoc.v:182226$11108 + assign { } { } + assign { } { } + assign $0\wr_detect$4[0:0]$11109 $1\wr_detect$4[0:0]$11110 + attribute \src "libresoc.v:182227.5-182227.29" + switch \initial + attribute \src "libresoc.v:182227.9-182227.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \msr0__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$4[0:0]$11110 $5\wr_detect$4[0:0]$11114 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \nia0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$4[0:0]$11111 1'1 + case + assign $2\wr_detect$4[0:0]$11111 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \msr0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$4[0:0]$11112 1'1 + case + assign $3\wr_detect$4[0:0]$11112 $2\wr_detect$4[0:0]$11111 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \sv0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$4[0:0]$11113 1'1 + case + assign $4\wr_detect$4[0:0]$11113 $3\wr_detect$4[0:0]$11112 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \d_wr10__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\wr_detect$4[0:0]$11114 1'1 + case + assign $5\wr_detect$4[0:0]$11114 $4\wr_detect$4[0:0]$11113 + end + case + assign $1\wr_detect$4[0:0]$11110 1'0 + end + sync always + update \wr_detect$4 $0\wr_detect$4[0:0]$11109 + end + attribute \src "libresoc.v:182262.3-182307.6" + process $proc$libresoc.v:182262$11115 + assign { } { } + assign { } { } + assign { } { } + assign $0\sv0__data_o$next[63:0]$11116 $7\sv0__data_o$next[63:0]$11123 + attribute \src "libresoc.v:182263.5-182263.29" + switch \initial + attribute \src "libresoc.v:182263.9-182263.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \sv0__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\sv0__data_o$next[63:0]$11117 $6\sv0__data_o$next[63:0]$11122 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \nia0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\sv0__data_o$next[63:0]$11118 \nia0__data_i + case + assign $2\sv0__data_o$next[63:0]$11118 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \msr0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\sv0__data_o$next[63:0]$11119 \msr0__data_i + case + assign $3\sv0__data_o$next[63:0]$11119 $2\sv0__data_o$next[63:0]$11118 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \sv0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\sv0__data_o$next[63:0]$11120 \sv0__data_i + case + assign $4\sv0__data_o$next[63:0]$11120 $3\sv0__data_o$next[63:0]$11119 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \d_wr10__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\sv0__data_o$next[63:0]$11121 \d_wr10__data_i + case + assign $5\sv0__data_o$next[63:0]$11121 $4\sv0__data_o$next[63:0]$11120 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$6 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\sv0__data_o$next[63:0]$11122 \reg + case + assign $6\sv0__data_o$next[63:0]$11122 $5\sv0__data_o$next[63:0]$11121 + end + case + assign $1\sv0__data_o$next[63:0]$11117 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\sv0__data_o$next[63:0]$11123 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $7\sv0__data_o$next[63:0]$11123 $1\sv0__data_o$next[63:0]$11117 + end + sync always + update \sv0__data_o$next $0\sv0__data_o$next[63:0]$11116 + end + attribute \src "libresoc.v:182308.3-182343.6" + process $proc$libresoc.v:182308$11124 + assign { } { } + assign { } { } + assign $0\wr_detect$7[0:0]$11125 $1\wr_detect$7[0:0]$11126 + attribute \src "libresoc.v:182309.5-182309.29" + switch \initial + attribute \src "libresoc.v:182309.9-182309.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \sv0__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$7[0:0]$11126 $5\wr_detect$7[0:0]$11130 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \nia0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$7[0:0]$11127 1'1 + case + assign $2\wr_detect$7[0:0]$11127 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \msr0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$7[0:0]$11128 1'1 + case + assign $3\wr_detect$7[0:0]$11128 $2\wr_detect$7[0:0]$11127 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \sv0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$7[0:0]$11129 1'1 + case + assign $4\wr_detect$7[0:0]$11129 $3\wr_detect$7[0:0]$11128 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \d_wr10__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\wr_detect$7[0:0]$11130 1'1 + case + assign $5\wr_detect$7[0:0]$11130 $4\wr_detect$7[0:0]$11129 + end + case + assign $1\wr_detect$7[0:0]$11126 1'0 + end + sync always + update \wr_detect$7 $0\wr_detect$7[0:0]$11125 + end + attribute \src "libresoc.v:182344.3-182376.6" + process $proc$libresoc.v:182344$11131 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\reg$next[63:0]$11132 $5\reg$next[63:0]$11137 + attribute \src "libresoc.v:182345.5-182345.29" + switch \initial + attribute \src "libresoc.v:182345.9-182345.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \nia0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\reg$next[63:0]$11133 \nia0__data_i + case + assign $1\reg$next[63:0]$11133 \reg + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \msr0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\reg$next[63:0]$11134 \msr0__data_i + case + assign $2\reg$next[63:0]$11134 $1\reg$next[63:0]$11133 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \sv0__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\reg$next[63:0]$11135 \sv0__data_i + case + assign $3\reg$next[63:0]$11135 $2\reg$next[63:0]$11134 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \d_wr10__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\reg$next[63:0]$11136 \d_wr10__data_i + case + assign $4\reg$next[63:0]$11136 $3\reg$next[63:0]$11135 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\reg$next[63:0]$11137 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $5\reg$next[63:0]$11137 $4\reg$next[63:0]$11136 + end + sync always + update \reg$next $0\reg$next[63:0]$11132 + end + connect \$1 $not$libresoc.v:182087$11082_Y + connect \$3 $not$libresoc.v:182088$11083_Y + connect \$6 $not$libresoc.v:182089$11084_Y +end +attribute \src "libresoc.v:182381.1-182852.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.cr.reg_1" +attribute \generator "nMigen" +module \reg_1 + attribute \src "libresoc.v:182382.7-182382.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:182712.3-182751.6" + wire width 4 $0\r1__data_o$next[3:0]$11198 + attribute \src "libresoc.v:182467.3-182468.37" + wire width 4 $0\r1__data_o[3:0] + attribute \src "libresoc.v:182782.3-182821.6" + wire width 4 $0\r21__data_o$next[3:0]$11212 + attribute \src "libresoc.v:182465.3-182466.39" + wire width 4 $0\r21__data_o[3:0] + attribute \src "libresoc.v:182545.3-182571.6" + wire width 4 $0\reg$next[3:0]$11164 + attribute \src "libresoc.v:182463.3-182464.25" + wire width 4 $0\reg[3:0] + attribute \src "libresoc.v:182475.3-182514.6" + wire width 4 $0\src11__data_o$next[3:0]$11155 + attribute \src "libresoc.v:182473.3-182474.43" + wire width 4 $0\src11__data_o[3:0] + attribute \src "libresoc.v:182572.3-182611.6" + wire width 4 $0\src21__data_o$next[3:0]$11170 + attribute \src "libresoc.v:182471.3-182472.43" + wire width 4 $0\src21__data_o[3:0] + attribute \src "libresoc.v:182642.3-182681.6" + wire width 4 $0\src31__data_o$next[3:0]$11184 + attribute \src "libresoc.v:182469.3-182470.43" + wire width 4 $0\src31__data_o[3:0] + attribute \src "libresoc.v:182752.3-182781.6" + wire $0\wr_detect$10[0:0]$11206 + attribute \src "libresoc.v:182822.3-182851.6" + wire $0\wr_detect$13[0:0]$11220 + attribute \src "libresoc.v:182612.3-182641.6" + wire $0\wr_detect$4[0:0]$11178 + attribute \src "libresoc.v:182682.3-182711.6" + wire $0\wr_detect$7[0:0]$11192 + attribute \src "libresoc.v:182515.3-182544.6" + wire $0\wr_detect[0:0] + attribute \src "libresoc.v:182712.3-182751.6" + wire width 4 $1\r1__data_o$next[3:0]$11199 + attribute \src "libresoc.v:182407.13-182407.30" + wire width 4 $1\r1__data_o[3:0] + attribute \src "libresoc.v:182782.3-182821.6" + wire width 4 $1\r21__data_o$next[3:0]$11213 + attribute \src "libresoc.v:182414.13-182414.31" + wire width 4 $1\r21__data_o[3:0] + attribute \src "libresoc.v:182545.3-182571.6" + wire width 4 $1\reg$next[3:0]$11165 + attribute \src "libresoc.v:182420.13-182420.25" + wire width 4 $1\reg[3:0] + attribute \src "libresoc.v:182475.3-182514.6" + wire width 4 $1\src11__data_o$next[3:0]$11156 + attribute \src "libresoc.v:182425.13-182425.33" + wire width 4 $1\src11__data_o[3:0] + attribute \src "libresoc.v:182572.3-182611.6" + wire width 4 $1\src21__data_o$next[3:0]$11171 + attribute \src "libresoc.v:182432.13-182432.33" + wire width 4 $1\src21__data_o[3:0] + attribute \src "libresoc.v:182642.3-182681.6" + wire width 4 $1\src31__data_o$next[3:0]$11185 + attribute \src "libresoc.v:182439.13-182439.33" + wire width 4 $1\src31__data_o[3:0] + attribute \src "libresoc.v:182752.3-182781.6" + wire $1\wr_detect$10[0:0]$11207 + attribute \src "libresoc.v:182822.3-182851.6" + wire $1\wr_detect$13[0:0]$11221 + attribute \src "libresoc.v:182612.3-182641.6" + wire $1\wr_detect$4[0:0]$11179 + attribute \src "libresoc.v:182682.3-182711.6" + wire $1\wr_detect$7[0:0]$11193 + attribute \src "libresoc.v:182515.3-182544.6" + wire $1\wr_detect[0:0] + attribute \src "libresoc.v:182712.3-182751.6" + wire width 4 $2\r1__data_o$next[3:0]$11200 + attribute \src "libresoc.v:182782.3-182821.6" + wire width 4 $2\r21__data_o$next[3:0]$11214 + attribute \src "libresoc.v:182545.3-182571.6" + wire width 4 $2\reg$next[3:0]$11166 + attribute \src "libresoc.v:182475.3-182514.6" + wire width 4 $2\src11__data_o$next[3:0]$11157 + attribute \src "libresoc.v:182572.3-182611.6" + wire width 4 $2\src21__data_o$next[3:0]$11172 + attribute \src "libresoc.v:182642.3-182681.6" + wire width 4 $2\src31__data_o$next[3:0]$11186 + attribute \src "libresoc.v:182752.3-182781.6" + wire $2\wr_detect$10[0:0]$11208 + attribute \src "libresoc.v:182822.3-182851.6" + wire $2\wr_detect$13[0:0]$11222 + attribute \src "libresoc.v:182612.3-182641.6" + wire $2\wr_detect$4[0:0]$11180 + attribute \src "libresoc.v:182682.3-182711.6" + wire $2\wr_detect$7[0:0]$11194 + attribute \src "libresoc.v:182515.3-182544.6" + wire $2\wr_detect[0:0] + attribute \src "libresoc.v:182712.3-182751.6" + wire width 4 $3\r1__data_o$next[3:0]$11201 + attribute \src "libresoc.v:182782.3-182821.6" + wire width 4 $3\r21__data_o$next[3:0]$11215 + attribute \src "libresoc.v:182545.3-182571.6" + wire width 4 $3\reg$next[3:0]$11167 + attribute \src "libresoc.v:182475.3-182514.6" + wire width 4 $3\src11__data_o$next[3:0]$11158 + attribute \src "libresoc.v:182572.3-182611.6" + wire width 4 $3\src21__data_o$next[3:0]$11173 + attribute \src "libresoc.v:182642.3-182681.6" + wire width 4 $3\src31__data_o$next[3:0]$11187 + attribute \src "libresoc.v:182752.3-182781.6" + wire $3\wr_detect$10[0:0]$11209 + attribute \src "libresoc.v:182822.3-182851.6" + wire $3\wr_detect$13[0:0]$11223 + attribute \src "libresoc.v:182612.3-182641.6" + wire $3\wr_detect$4[0:0]$11181 + attribute \src "libresoc.v:182682.3-182711.6" + wire $3\wr_detect$7[0:0]$11195 + attribute \src "libresoc.v:182515.3-182544.6" + wire $3\wr_detect[0:0] + attribute \src "libresoc.v:182712.3-182751.6" + wire width 4 $4\r1__data_o$next[3:0]$11202 + attribute \src "libresoc.v:182782.3-182821.6" + wire width 4 $4\r21__data_o$next[3:0]$11216 + attribute \src "libresoc.v:182545.3-182571.6" + wire width 4 $4\reg$next[3:0]$11168 + attribute \src "libresoc.v:182475.3-182514.6" + wire width 4 $4\src11__data_o$next[3:0]$11159 + attribute \src "libresoc.v:182572.3-182611.6" + wire width 4 $4\src21__data_o$next[3:0]$11174 + attribute \src "libresoc.v:182642.3-182681.6" + wire width 4 $4\src31__data_o$next[3:0]$11188 + attribute \src "libresoc.v:182752.3-182781.6" + wire $4\wr_detect$10[0:0]$11210 + attribute \src "libresoc.v:182822.3-182851.6" + wire $4\wr_detect$13[0:0]$11224 + attribute \src "libresoc.v:182612.3-182641.6" + wire $4\wr_detect$4[0:0]$11182 + attribute \src "libresoc.v:182682.3-182711.6" + wire $4\wr_detect$7[0:0]$11196 + attribute \src "libresoc.v:182515.3-182544.6" + wire $4\wr_detect[0:0] + attribute \src "libresoc.v:182712.3-182751.6" + wire width 4 $5\r1__data_o$next[3:0]$11203 + attribute \src "libresoc.v:182782.3-182821.6" + wire width 4 $5\r21__data_o$next[3:0]$11217 + attribute \src "libresoc.v:182475.3-182514.6" + wire width 4 $5\src11__data_o$next[3:0]$11160 + attribute \src "libresoc.v:182572.3-182611.6" + wire width 4 $5\src21__data_o$next[3:0]$11175 + attribute \src "libresoc.v:182642.3-182681.6" + wire width 4 $5\src31__data_o$next[3:0]$11189 + attribute \src "libresoc.v:182712.3-182751.6" + wire width 4 $6\r1__data_o$next[3:0]$11204 + attribute \src "libresoc.v:182782.3-182821.6" + wire width 4 $6\r21__data_o$next[3:0]$11218 + attribute \src "libresoc.v:182475.3-182514.6" + wire width 4 $6\src11__data_o$next[3:0]$11161 + attribute \src "libresoc.v:182572.3-182611.6" + wire width 4 $6\src21__data_o$next[3:0]$11176 + attribute \src "libresoc.v:182642.3-182681.6" + wire width 4 $6\src31__data_o$next[3:0]$11190 + attribute \src "libresoc.v:182458.17-182458.104" + wire $not$libresoc.v:182458$11143_Y + attribute \src "libresoc.v:182459.18-182459.105" + wire $not$libresoc.v:182459$11144_Y + attribute \src "libresoc.v:182460.17-182460.100" + wire $not$libresoc.v:182460$11145_Y + attribute \src "libresoc.v:182461.17-182461.103" + wire $not$libresoc.v:182461$11146_Y + attribute \src "libresoc.v:182462.17-182462.103" + wire $not$libresoc.v:182462$11147_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 18 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 input 9 \dest11__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 8 \dest11__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 input 11 \dest21__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 10 \dest21__wen + attribute \src "libresoc.v:182382.7-182382.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 output 12 \r1__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 \r1__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 13 \r1__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 output 14 \r21__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 \r21__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 15 \r21__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 4 \reg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 4 \reg$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 output 3 \src11__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 \src11__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 2 \src11__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 output 5 \src21__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 \src21__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 4 \src21__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 output 7 \src31__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 \src31__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 6 \src31__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 input 16 \w1__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 17 \w1__wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:182458$11143 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$10 + connect \Y $not$libresoc.v:182458$11143_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:182459$11144 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$13 + connect \Y $not$libresoc.v:182459$11144_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:182460$11145 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect + connect \Y $not$libresoc.v:182460$11145_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:182461$11146 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$4 + connect \Y $not$libresoc.v:182461$11146_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:182462$11147 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$7 + connect \Y $not$libresoc.v:182462$11147_Y + end + attribute \src "libresoc.v:182382.7-182382.20" + process $proc$libresoc.v:182382$11225 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:182407.13-182407.30" + process $proc$libresoc.v:182407$11226 + assign { } { } + assign $1\r1__data_o[3:0] 4'0000 + sync always + sync init + update \r1__data_o $1\r1__data_o[3:0] + end + attribute \src "libresoc.v:182414.13-182414.31" + process $proc$libresoc.v:182414$11227 + assign { } { } + assign $1\r21__data_o[3:0] 4'0000 + sync always + sync init + update \r21__data_o $1\r21__data_o[3:0] + end + attribute \src "libresoc.v:182420.13-182420.25" + process $proc$libresoc.v:182420$11228 + assign { } { } + assign $1\reg[3:0] 4'0000 + sync always + sync init + update \reg $1\reg[3:0] + end + attribute \src "libresoc.v:182425.13-182425.33" + process $proc$libresoc.v:182425$11229 + assign { } { } + assign $1\src11__data_o[3:0] 4'0000 + sync always + sync init + update \src11__data_o $1\src11__data_o[3:0] + end + attribute \src "libresoc.v:182432.13-182432.33" + process $proc$libresoc.v:182432$11230 + assign { } { } + assign $1\src21__data_o[3:0] 4'0000 + sync always + sync init + update \src21__data_o $1\src21__data_o[3:0] + end + attribute \src "libresoc.v:182439.13-182439.33" + process $proc$libresoc.v:182439$11231 + assign { } { } + assign $1\src31__data_o[3:0] 4'0000 + sync always + sync init + update \src31__data_o $1\src31__data_o[3:0] + end + attribute \src "libresoc.v:182463.3-182464.25" + process $proc$libresoc.v:182463$11148 + assign { } { } + assign $0\reg[3:0] \reg$next + sync posedge \coresync_clk + update \reg $0\reg[3:0] + end + attribute \src "libresoc.v:182465.3-182466.39" + process $proc$libresoc.v:182465$11149 + assign { } { } + assign $0\r21__data_o[3:0] \r21__data_o$next + sync posedge \coresync_clk + update \r21__data_o $0\r21__data_o[3:0] + end + attribute \src "libresoc.v:182467.3-182468.37" + process $proc$libresoc.v:182467$11150 + assign { } { } + assign $0\r1__data_o[3:0] \r1__data_o$next + sync posedge \coresync_clk + update \r1__data_o $0\r1__data_o[3:0] + end + attribute \src "libresoc.v:182469.3-182470.43" + process $proc$libresoc.v:182469$11151 + assign { } { } + assign $0\src31__data_o[3:0] \src31__data_o$next + sync posedge \coresync_clk + update \src31__data_o $0\src31__data_o[3:0] + end + attribute \src "libresoc.v:182471.3-182472.43" + process $proc$libresoc.v:182471$11152 + assign { } { } + assign $0\src21__data_o[3:0] \src21__data_o$next + sync posedge \coresync_clk + update \src21__data_o $0\src21__data_o[3:0] + end + attribute \src "libresoc.v:182473.3-182474.43" + process $proc$libresoc.v:182473$11153 + assign { } { } + assign $0\src11__data_o[3:0] \src11__data_o$next + sync posedge \coresync_clk + update \src11__data_o $0\src11__data_o[3:0] + end + attribute \src "libresoc.v:182475.3-182514.6" + process $proc$libresoc.v:182475$11154 + assign { } { } + assign { } { } + assign { } { } + assign $0\src11__data_o$next[3:0]$11155 $6\src11__data_o$next[3:0]$11161 + attribute \src "libresoc.v:182476.5-182476.29" + switch \initial + attribute \src "libresoc.v:182476.9-182476.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src11__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src11__data_o$next[3:0]$11156 $5\src11__data_o$next[3:0]$11160 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest11__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src11__data_o$next[3:0]$11157 \dest11__data_i + case + assign $2\src11__data_o$next[3:0]$11157 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest21__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src11__data_o$next[3:0]$11158 \dest21__data_i + case + assign $3\src11__data_o$next[3:0]$11158 $2\src11__data_o$next[3:0]$11157 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src11__data_o$next[3:0]$11159 \w1__data_i + case + assign $4\src11__data_o$next[3:0]$11159 $3\src11__data_o$next[3:0]$11158 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src11__data_o$next[3:0]$11160 \reg + case + assign $5\src11__data_o$next[3:0]$11160 $4\src11__data_o$next[3:0]$11159 + end + case + assign $1\src11__data_o$next[3:0]$11156 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src11__data_o$next[3:0]$11161 4'0000 + case + assign $6\src11__data_o$next[3:0]$11161 $1\src11__data_o$next[3:0]$11156 + end + sync always + update \src11__data_o$next $0\src11__data_o$next[3:0]$11155 + end + attribute \src "libresoc.v:182515.3-182544.6" + process $proc$libresoc.v:182515$11162 + assign { } { } + assign { } { } + assign $0\wr_detect[0:0] $1\wr_detect[0:0] + attribute \src "libresoc.v:182516.5-182516.29" + switch \initial + attribute \src "libresoc.v:182516.9-182516.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src11__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect[0:0] $4\wr_detect[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest11__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect[0:0] 1'1 + case + assign $2\wr_detect[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest21__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect[0:0] 1'1 + case + assign $3\wr_detect[0:0] $2\wr_detect[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect[0:0] 1'1 + case + assign $4\wr_detect[0:0] $3\wr_detect[0:0] + end + case + assign $1\wr_detect[0:0] 1'0 + end + sync always + update \wr_detect $0\wr_detect[0:0] + end + attribute \src "libresoc.v:182545.3-182571.6" + process $proc$libresoc.v:182545$11163 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\reg$next[3:0]$11164 $4\reg$next[3:0]$11168 + attribute \src "libresoc.v:182546.5-182546.29" + switch \initial + attribute \src "libresoc.v:182546.9-182546.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest11__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\reg$next[3:0]$11165 \dest11__data_i + case + assign $1\reg$next[3:0]$11165 \reg + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest21__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\reg$next[3:0]$11166 \dest21__data_i + case + assign $2\reg$next[3:0]$11166 $1\reg$next[3:0]$11165 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \w1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\reg$next[3:0]$11167 \w1__data_i + case + assign $3\reg$next[3:0]$11167 $2\reg$next[3:0]$11166 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\reg$next[3:0]$11168 4'0000 + case + assign $4\reg$next[3:0]$11168 $3\reg$next[3:0]$11167 + end + sync always + update \reg$next $0\reg$next[3:0]$11164 + end + attribute \src "libresoc.v:182572.3-182611.6" + process $proc$libresoc.v:182572$11169 + assign { } { } + assign { } { } + assign { } { } + assign $0\src21__data_o$next[3:0]$11170 $6\src21__data_o$next[3:0]$11176 + attribute \src "libresoc.v:182573.5-182573.29" + switch \initial + attribute \src "libresoc.v:182573.9-182573.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src21__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src21__data_o$next[3:0]$11171 $5\src21__data_o$next[3:0]$11175 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest11__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src21__data_o$next[3:0]$11172 \dest11__data_i + case + assign $2\src21__data_o$next[3:0]$11172 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest21__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src21__data_o$next[3:0]$11173 \dest21__data_i + case + assign $3\src21__data_o$next[3:0]$11173 $2\src21__data_o$next[3:0]$11172 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src21__data_o$next[3:0]$11174 \w1__data_i + case + assign $4\src21__data_o$next[3:0]$11174 $3\src21__data_o$next[3:0]$11173 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src21__data_o$next[3:0]$11175 \reg + case + assign $5\src21__data_o$next[3:0]$11175 $4\src21__data_o$next[3:0]$11174 + end + case + assign $1\src21__data_o$next[3:0]$11171 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src21__data_o$next[3:0]$11176 4'0000 + case + assign $6\src21__data_o$next[3:0]$11176 $1\src21__data_o$next[3:0]$11171 + end + sync always + update \src21__data_o$next $0\src21__data_o$next[3:0]$11170 + end + attribute \src "libresoc.v:182612.3-182641.6" + process $proc$libresoc.v:182612$11177 + assign { } { } + assign { } { } + assign $0\wr_detect$4[0:0]$11178 $1\wr_detect$4[0:0]$11179 + attribute \src "libresoc.v:182613.5-182613.29" + switch \initial + attribute \src "libresoc.v:182613.9-182613.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src21__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$4[0:0]$11179 $4\wr_detect$4[0:0]$11182 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest11__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$4[0:0]$11180 1'1 + case + assign $2\wr_detect$4[0:0]$11180 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest21__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$4[0:0]$11181 1'1 + case + assign $3\wr_detect$4[0:0]$11181 $2\wr_detect$4[0:0]$11180 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$4[0:0]$11182 1'1 + case + assign $4\wr_detect$4[0:0]$11182 $3\wr_detect$4[0:0]$11181 + end + case + assign $1\wr_detect$4[0:0]$11179 1'0 + end + sync always + update \wr_detect$4 $0\wr_detect$4[0:0]$11178 + end + attribute \src "libresoc.v:182642.3-182681.6" + process $proc$libresoc.v:182642$11183 + assign { } { } + assign { } { } + assign { } { } + assign $0\src31__data_o$next[3:0]$11184 $6\src31__data_o$next[3:0]$11190 + attribute \src "libresoc.v:182643.5-182643.29" + switch \initial + attribute \src "libresoc.v:182643.9-182643.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src31__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src31__data_o$next[3:0]$11185 $5\src31__data_o$next[3:0]$11189 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest11__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src31__data_o$next[3:0]$11186 \dest11__data_i + case + assign $2\src31__data_o$next[3:0]$11186 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest21__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src31__data_o$next[3:0]$11187 \dest21__data_i + case + assign $3\src31__data_o$next[3:0]$11187 $2\src31__data_o$next[3:0]$11186 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src31__data_o$next[3:0]$11188 \w1__data_i + case + assign $4\src31__data_o$next[3:0]$11188 $3\src31__data_o$next[3:0]$11187 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$6 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src31__data_o$next[3:0]$11189 \reg + case + assign $5\src31__data_o$next[3:0]$11189 $4\src31__data_o$next[3:0]$11188 + end + case + assign $1\src31__data_o$next[3:0]$11185 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src31__data_o$next[3:0]$11190 4'0000 + case + assign $6\src31__data_o$next[3:0]$11190 $1\src31__data_o$next[3:0]$11185 + end + sync always + update \src31__data_o$next $0\src31__data_o$next[3:0]$11184 + end + attribute \src "libresoc.v:182682.3-182711.6" + process $proc$libresoc.v:182682$11191 + assign { } { } + assign { } { } + assign $0\wr_detect$7[0:0]$11192 $1\wr_detect$7[0:0]$11193 + attribute \src "libresoc.v:182683.5-182683.29" + switch \initial + attribute \src "libresoc.v:182683.9-182683.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src31__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$7[0:0]$11193 $4\wr_detect$7[0:0]$11196 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest11__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$7[0:0]$11194 1'1 + case + assign $2\wr_detect$7[0:0]$11194 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest21__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$7[0:0]$11195 1'1 + case + assign $3\wr_detect$7[0:0]$11195 $2\wr_detect$7[0:0]$11194 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$7[0:0]$11196 1'1 + case + assign $4\wr_detect$7[0:0]$11196 $3\wr_detect$7[0:0]$11195 + end + case + assign $1\wr_detect$7[0:0]$11193 1'0 + end + sync always + update \wr_detect$7 $0\wr_detect$7[0:0]$11192 + end + attribute \src "libresoc.v:182712.3-182751.6" + process $proc$libresoc.v:182712$11197 + assign { } { } + assign { } { } + assign { } { } + assign $0\r1__data_o$next[3:0]$11198 $6\r1__data_o$next[3:0]$11204 + attribute \src "libresoc.v:182713.5-182713.29" + switch \initial + attribute \src "libresoc.v:182713.9-182713.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r1__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\r1__data_o$next[3:0]$11199 $5\r1__data_o$next[3:0]$11203 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest11__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r1__data_o$next[3:0]$11200 \dest11__data_i + case + assign $2\r1__data_o$next[3:0]$11200 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest21__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\r1__data_o$next[3:0]$11201 \dest21__data_i + case + assign $3\r1__data_o$next[3:0]$11201 $2\r1__data_o$next[3:0]$11200 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\r1__data_o$next[3:0]$11202 \w1__data_i + case + assign $4\r1__data_o$next[3:0]$11202 $3\r1__data_o$next[3:0]$11201 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$9 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\r1__data_o$next[3:0]$11203 \reg + case + assign $5\r1__data_o$next[3:0]$11203 $4\r1__data_o$next[3:0]$11202 + end + case + assign $1\r1__data_o$next[3:0]$11199 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\r1__data_o$next[3:0]$11204 4'0000 + case + assign $6\r1__data_o$next[3:0]$11204 $1\r1__data_o$next[3:0]$11199 + end + sync always + update \r1__data_o$next $0\r1__data_o$next[3:0]$11198 + end + attribute \src "libresoc.v:182752.3-182781.6" + process $proc$libresoc.v:182752$11205 + assign { } { } + assign { } { } + assign $0\wr_detect$10[0:0]$11206 $1\wr_detect$10[0:0]$11207 + attribute \src "libresoc.v:182753.5-182753.29" + switch \initial + attribute \src "libresoc.v:182753.9-182753.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r1__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$10[0:0]$11207 $4\wr_detect$10[0:0]$11210 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest11__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$10[0:0]$11208 1'1 + case + assign $2\wr_detect$10[0:0]$11208 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest21__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$10[0:0]$11209 1'1 + case + assign $3\wr_detect$10[0:0]$11209 $2\wr_detect$10[0:0]$11208 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$10[0:0]$11210 1'1 + case + assign $4\wr_detect$10[0:0]$11210 $3\wr_detect$10[0:0]$11209 + end + case + assign $1\wr_detect$10[0:0]$11207 1'0 + end + sync always + update \wr_detect$10 $0\wr_detect$10[0:0]$11206 + end + attribute \src "libresoc.v:182782.3-182821.6" + process $proc$libresoc.v:182782$11211 + assign { } { } + assign { } { } + assign { } { } + assign $0\r21__data_o$next[3:0]$11212 $6\r21__data_o$next[3:0]$11218 + attribute \src "libresoc.v:182783.5-182783.29" + switch \initial + attribute \src "libresoc.v:182783.9-182783.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r21__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\r21__data_o$next[3:0]$11213 $5\r21__data_o$next[3:0]$11217 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest11__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r21__data_o$next[3:0]$11214 \dest11__data_i + case + assign $2\r21__data_o$next[3:0]$11214 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest21__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\r21__data_o$next[3:0]$11215 \dest21__data_i + case + assign $3\r21__data_o$next[3:0]$11215 $2\r21__data_o$next[3:0]$11214 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\r21__data_o$next[3:0]$11216 \w1__data_i + case + assign $4\r21__data_o$next[3:0]$11216 $3\r21__data_o$next[3:0]$11215 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$12 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\r21__data_o$next[3:0]$11217 \reg + case + assign $5\r21__data_o$next[3:0]$11217 $4\r21__data_o$next[3:0]$11216 + end + case + assign $1\r21__data_o$next[3:0]$11213 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\r21__data_o$next[3:0]$11218 4'0000 + case + assign $6\r21__data_o$next[3:0]$11218 $1\r21__data_o$next[3:0]$11213 + end + sync always + update \r21__data_o$next $0\r21__data_o$next[3:0]$11212 + end + attribute \src "libresoc.v:182822.3-182851.6" + process $proc$libresoc.v:182822$11219 + assign { } { } + assign { } { } + assign $0\wr_detect$13[0:0]$11220 $1\wr_detect$13[0:0]$11221 + attribute \src "libresoc.v:182823.5-182823.29" + switch \initial + attribute \src "libresoc.v:182823.9-182823.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r21__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$13[0:0]$11221 $4\wr_detect$13[0:0]$11224 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest11__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$13[0:0]$11222 1'1 + case + assign $2\wr_detect$13[0:0]$11222 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest21__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$13[0:0]$11223 1'1 + case + assign $3\wr_detect$13[0:0]$11223 $2\wr_detect$13[0:0]$11222 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$13[0:0]$11224 1'1 + case + assign $4\wr_detect$13[0:0]$11224 $3\wr_detect$13[0:0]$11223 + end + case + assign $1\wr_detect$13[0:0]$11221 1'0 + end + sync always + update \wr_detect$13 $0\wr_detect$13[0:0]$11220 + end + connect \$9 $not$libresoc.v:182458$11143_Y + connect \$12 $not$libresoc.v:182459$11144_Y + connect \$1 $not$libresoc.v:182460$11145_Y + connect \$3 $not$libresoc.v:182461$11146_Y + connect \$6 $not$libresoc.v:182462$11147_Y +end +attribute \src "libresoc.v:182856.1-183301.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.xer.reg_1" +attribute \generator "nMigen" +module \reg_1$133 + attribute \src "libresoc.v:182857.7-182857.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:183186.3-183231.6" + wire width 2 $0\r1__data_o$next[1:0]$11284 + attribute \src "libresoc.v:182932.3-182933.37" + wire width 2 $0\r1__data_o[1:0] + attribute \src "libresoc.v:183268.3-183300.6" + wire width 2 $0\reg$next[1:0]$11300 + attribute \src "libresoc.v:182930.3-182931.25" + wire width 2 $0\reg[1:0] + attribute \src "libresoc.v:182940.3-182985.6" + wire width 2 $0\src11__data_o$next[1:0]$11242 + attribute \src "libresoc.v:182938.3-182939.43" + wire width 2 $0\src11__data_o[1:0] + attribute \src "libresoc.v:183022.3-183067.6" + wire width 2 $0\src21__data_o$next[1:0]$11252 + attribute \src "libresoc.v:182936.3-182937.43" + wire width 2 $0\src21__data_o[1:0] + attribute \src "libresoc.v:183104.3-183149.6" + wire width 2 $0\src31__data_o$next[1:0]$11268 + attribute \src "libresoc.v:182934.3-182935.43" + wire width 2 $0\src31__data_o[1:0] + attribute \src "libresoc.v:183232.3-183267.6" + wire $0\wr_detect$10[0:0]$11293 + attribute \src "libresoc.v:183068.3-183103.6" + wire $0\wr_detect$4[0:0]$11261 + attribute \src "libresoc.v:183150.3-183185.6" + wire $0\wr_detect$7[0:0]$11277 + attribute \src "libresoc.v:182986.3-183021.6" + wire $0\wr_detect[0:0] + attribute \src "libresoc.v:183186.3-183231.6" + wire width 2 $1\r1__data_o$next[1:0]$11285 + attribute \src "libresoc.v:182884.13-182884.30" + wire width 2 $1\r1__data_o[1:0] + attribute \src "libresoc.v:183268.3-183300.6" + wire width 2 $1\reg$next[1:0]$11301 + attribute \src "libresoc.v:182890.13-182890.25" + wire width 2 $1\reg[1:0] + attribute \src "libresoc.v:182940.3-182985.6" + wire width 2 $1\src11__data_o$next[1:0]$11243 + attribute \src "libresoc.v:182895.13-182895.33" + wire width 2 $1\src11__data_o[1:0] + attribute \src "libresoc.v:183022.3-183067.6" + wire width 2 $1\src21__data_o$next[1:0]$11253 + attribute \src "libresoc.v:182902.13-182902.33" + wire width 2 $1\src21__data_o[1:0] + attribute \src "libresoc.v:183104.3-183149.6" + wire width 2 $1\src31__data_o$next[1:0]$11269 + attribute \src "libresoc.v:182909.13-182909.33" + wire width 2 $1\src31__data_o[1:0] + attribute \src "libresoc.v:183232.3-183267.6" + wire $1\wr_detect$10[0:0]$11294 + attribute \src "libresoc.v:183068.3-183103.6" + wire $1\wr_detect$4[0:0]$11262 + attribute \src "libresoc.v:183150.3-183185.6" + wire $1\wr_detect$7[0:0]$11278 + attribute \src "libresoc.v:182986.3-183021.6" + wire $1\wr_detect[0:0] + attribute \src "libresoc.v:183186.3-183231.6" + wire width 2 $2\r1__data_o$next[1:0]$11286 + attribute \src "libresoc.v:183268.3-183300.6" + wire width 2 $2\reg$next[1:0]$11302 + attribute \src "libresoc.v:182940.3-182985.6" + wire width 2 $2\src11__data_o$next[1:0]$11244 + attribute \src "libresoc.v:183022.3-183067.6" + wire width 2 $2\src21__data_o$next[1:0]$11254 + attribute \src "libresoc.v:183104.3-183149.6" + wire width 2 $2\src31__data_o$next[1:0]$11270 + attribute \src "libresoc.v:183232.3-183267.6" + wire $2\wr_detect$10[0:0]$11295 + attribute \src "libresoc.v:183068.3-183103.6" + wire $2\wr_detect$4[0:0]$11263 + attribute \src "libresoc.v:183150.3-183185.6" + wire $2\wr_detect$7[0:0]$11279 + attribute \src "libresoc.v:182986.3-183021.6" + wire $2\wr_detect[0:0] + attribute \src "libresoc.v:183186.3-183231.6" + wire width 2 $3\r1__data_o$next[1:0]$11287 + attribute \src "libresoc.v:183268.3-183300.6" + wire width 2 $3\reg$next[1:0]$11303 + attribute \src "libresoc.v:182940.3-182985.6" + wire width 2 $3\src11__data_o$next[1:0]$11245 + attribute \src "libresoc.v:183022.3-183067.6" + wire width 2 $3\src21__data_o$next[1:0]$11255 + attribute \src "libresoc.v:183104.3-183149.6" + wire width 2 $3\src31__data_o$next[1:0]$11271 + attribute \src "libresoc.v:183232.3-183267.6" + wire $3\wr_detect$10[0:0]$11296 + attribute \src "libresoc.v:183068.3-183103.6" + wire $3\wr_detect$4[0:0]$11264 + attribute \src "libresoc.v:183150.3-183185.6" + wire $3\wr_detect$7[0:0]$11280 + attribute \src "libresoc.v:182986.3-183021.6" + wire $3\wr_detect[0:0] + attribute \src "libresoc.v:183186.3-183231.6" + wire width 2 $4\r1__data_o$next[1:0]$11288 + attribute \src "libresoc.v:183268.3-183300.6" + wire width 2 $4\reg$next[1:0]$11304 + attribute \src "libresoc.v:182940.3-182985.6" + wire width 2 $4\src11__data_o$next[1:0]$11246 + attribute \src "libresoc.v:183022.3-183067.6" + wire width 2 $4\src21__data_o$next[1:0]$11256 + attribute \src "libresoc.v:183104.3-183149.6" + wire width 2 $4\src31__data_o$next[1:0]$11272 + attribute \src "libresoc.v:183232.3-183267.6" + wire $4\wr_detect$10[0:0]$11297 + attribute \src "libresoc.v:183068.3-183103.6" + wire $4\wr_detect$4[0:0]$11265 + attribute \src "libresoc.v:183150.3-183185.6" + wire $4\wr_detect$7[0:0]$11281 + attribute \src "libresoc.v:182986.3-183021.6" + wire $4\wr_detect[0:0] + attribute \src "libresoc.v:183186.3-183231.6" + wire width 2 $5\r1__data_o$next[1:0]$11289 + attribute \src "libresoc.v:183268.3-183300.6" + wire width 2 $5\reg$next[1:0]$11305 + attribute \src "libresoc.v:182940.3-182985.6" + wire width 2 $5\src11__data_o$next[1:0]$11247 + attribute \src "libresoc.v:183022.3-183067.6" + wire width 2 $5\src21__data_o$next[1:0]$11257 + attribute \src "libresoc.v:183104.3-183149.6" + wire width 2 $5\src31__data_o$next[1:0]$11273 + attribute \src "libresoc.v:183232.3-183267.6" + wire $5\wr_detect$10[0:0]$11298 + attribute \src "libresoc.v:183068.3-183103.6" + wire $5\wr_detect$4[0:0]$11266 + attribute \src "libresoc.v:183150.3-183185.6" + wire $5\wr_detect$7[0:0]$11282 + attribute \src "libresoc.v:182986.3-183021.6" + wire $5\wr_detect[0:0] + attribute \src "libresoc.v:183186.3-183231.6" + wire width 2 $6\r1__data_o$next[1:0]$11290 + attribute \src "libresoc.v:182940.3-182985.6" + wire width 2 $6\src11__data_o$next[1:0]$11248 + attribute \src "libresoc.v:183022.3-183067.6" + wire width 2 $6\src21__data_o$next[1:0]$11258 + attribute \src "libresoc.v:183104.3-183149.6" + wire width 2 $6\src31__data_o$next[1:0]$11274 + attribute \src "libresoc.v:183186.3-183231.6" + wire width 2 $7\r1__data_o$next[1:0]$11291 + attribute \src "libresoc.v:182940.3-182985.6" + wire width 2 $7\src11__data_o$next[1:0]$11249 + attribute \src "libresoc.v:183022.3-183067.6" + wire width 2 $7\src21__data_o$next[1:0]$11259 + attribute \src "libresoc.v:183104.3-183149.6" + wire width 2 $7\src31__data_o$next[1:0]$11275 + attribute \src "libresoc.v:182926.17-182926.104" + wire $not$libresoc.v:182926$11232_Y + attribute \src "libresoc.v:182927.17-182927.100" + wire $not$libresoc.v:182927$11233_Y + attribute \src "libresoc.v:182928.17-182928.103" + wire $not$libresoc.v:182928$11234_Y + attribute \src "libresoc.v:182929.17-182929.103" + wire $not$libresoc.v:182929$11235_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 18 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 2 input 9 \dest11__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 8 \dest11__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 2 input 11 \dest21__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 10 \dest21__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 2 input 13 \dest31__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 12 \dest31__wen + attribute \src "libresoc.v:182857.7-182857.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 2 output 14 \r1__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 2 \r1__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 15 \r1__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 2 \reg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 2 \reg$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 2 output 3 \src11__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 2 \src11__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 2 \src11__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 2 output 5 \src21__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 2 \src21__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 4 \src21__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 2 output 7 \src31__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 2 \src31__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 6 \src31__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 2 input 16 \w1__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 17 \w1__wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:182926$11232 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$10 + connect \Y $not$libresoc.v:182926$11232_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:182927$11233 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect + connect \Y $not$libresoc.v:182927$11233_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:182928$11234 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$4 + connect \Y $not$libresoc.v:182928$11234_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:182929$11235 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$7 + connect \Y $not$libresoc.v:182929$11235_Y + end + attribute \src "libresoc.v:182857.7-182857.20" + process $proc$libresoc.v:182857$11306 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:182884.13-182884.30" + process $proc$libresoc.v:182884$11307 + assign { } { } + assign $1\r1__data_o[1:0] 2'00 + sync always + sync init + update \r1__data_o $1\r1__data_o[1:0] + end + attribute \src "libresoc.v:182890.13-182890.25" + process $proc$libresoc.v:182890$11308 + assign { } { } + assign $1\reg[1:0] 2'00 + sync always + sync init + update \reg $1\reg[1:0] + end + attribute \src "libresoc.v:182895.13-182895.33" + process $proc$libresoc.v:182895$11309 + assign { } { } + assign $1\src11__data_o[1:0] 2'00 + sync always + sync init + update \src11__data_o $1\src11__data_o[1:0] + end + attribute \src "libresoc.v:182902.13-182902.33" + process $proc$libresoc.v:182902$11310 + assign { } { } + assign $1\src21__data_o[1:0] 2'00 + sync always + sync init + update \src21__data_o $1\src21__data_o[1:0] + end + attribute \src "libresoc.v:182909.13-182909.33" + process $proc$libresoc.v:182909$11311 + assign { } { } + assign $1\src31__data_o[1:0] 2'00 + sync always + sync init + update \src31__data_o $1\src31__data_o[1:0] + end + attribute \src "libresoc.v:182930.3-182931.25" + process $proc$libresoc.v:182930$11236 + assign { } { } + assign $0\reg[1:0] \reg$next + sync posedge \coresync_clk + update \reg $0\reg[1:0] + end + attribute \src "libresoc.v:182932.3-182933.37" + process $proc$libresoc.v:182932$11237 + assign { } { } + assign $0\r1__data_o[1:0] \r1__data_o$next + sync posedge \coresync_clk + update \r1__data_o $0\r1__data_o[1:0] + end + attribute \src "libresoc.v:182934.3-182935.43" + process $proc$libresoc.v:182934$11238 + assign { } { } + assign $0\src31__data_o[1:0] \src31__data_o$next + sync posedge \coresync_clk + update \src31__data_o $0\src31__data_o[1:0] + end + attribute \src "libresoc.v:182936.3-182937.43" + process $proc$libresoc.v:182936$11239 + assign { } { } + assign $0\src21__data_o[1:0] \src21__data_o$next + sync posedge \coresync_clk + update \src21__data_o $0\src21__data_o[1:0] + end + attribute \src "libresoc.v:182938.3-182939.43" + process $proc$libresoc.v:182938$11240 + assign { } { } + assign $0\src11__data_o[1:0] \src11__data_o$next + sync posedge \coresync_clk + update \src11__data_o $0\src11__data_o[1:0] + end + attribute \src "libresoc.v:182940.3-182985.6" + process $proc$libresoc.v:182940$11241 + assign { } { } + assign { } { } + assign { } { } + assign $0\src11__data_o$next[1:0]$11242 $7\src11__data_o$next[1:0]$11249 + attribute \src "libresoc.v:182941.5-182941.29" + switch \initial + attribute \src "libresoc.v:182941.9-182941.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src11__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src11__data_o$next[1:0]$11243 $6\src11__data_o$next[1:0]$11248 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest11__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src11__data_o$next[1:0]$11244 \dest11__data_i + case + assign $2\src11__data_o$next[1:0]$11244 2'00 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest21__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src11__data_o$next[1:0]$11245 \dest21__data_i + case + assign $3\src11__data_o$next[1:0]$11245 $2\src11__data_o$next[1:0]$11244 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest31__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src11__data_o$next[1:0]$11246 \dest31__data_i + case + assign $4\src11__data_o$next[1:0]$11246 $3\src11__data_o$next[1:0]$11245 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src11__data_o$next[1:0]$11247 \w1__data_i + case + assign $5\src11__data_o$next[1:0]$11247 $4\src11__data_o$next[1:0]$11246 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src11__data_o$next[1:0]$11248 \reg + case + assign $6\src11__data_o$next[1:0]$11248 $5\src11__data_o$next[1:0]$11247 + end + case + assign $1\src11__data_o$next[1:0]$11243 2'00 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\src11__data_o$next[1:0]$11249 2'00 + case + assign $7\src11__data_o$next[1:0]$11249 $1\src11__data_o$next[1:0]$11243 + end + sync always + update \src11__data_o$next $0\src11__data_o$next[1:0]$11242 + end + attribute \src "libresoc.v:182986.3-183021.6" + process $proc$libresoc.v:182986$11250 + assign { } { } + assign { } { } + assign $0\wr_detect[0:0] $1\wr_detect[0:0] + attribute \src "libresoc.v:182987.5-182987.29" + switch \initial + attribute \src "libresoc.v:182987.9-182987.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src11__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect[0:0] $5\wr_detect[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest11__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect[0:0] 1'1 + case + assign $2\wr_detect[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest21__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect[0:0] 1'1 + case + assign $3\wr_detect[0:0] $2\wr_detect[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest31__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect[0:0] 1'1 + case + assign $4\wr_detect[0:0] $3\wr_detect[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\wr_detect[0:0] 1'1 + case + assign $5\wr_detect[0:0] $4\wr_detect[0:0] + end + case + assign $1\wr_detect[0:0] 1'0 + end + sync always + update \wr_detect $0\wr_detect[0:0] + end + attribute \src "libresoc.v:183022.3-183067.6" + process $proc$libresoc.v:183022$11251 + assign { } { } + assign { } { } + assign { } { } + assign $0\src21__data_o$next[1:0]$11252 $7\src21__data_o$next[1:0]$11259 + attribute \src "libresoc.v:183023.5-183023.29" + switch \initial + attribute \src "libresoc.v:183023.9-183023.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src21__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src21__data_o$next[1:0]$11253 $6\src21__data_o$next[1:0]$11258 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest11__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src21__data_o$next[1:0]$11254 \dest11__data_i + case + assign $2\src21__data_o$next[1:0]$11254 2'00 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest21__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src21__data_o$next[1:0]$11255 \dest21__data_i + case + assign $3\src21__data_o$next[1:0]$11255 $2\src21__data_o$next[1:0]$11254 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest31__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src21__data_o$next[1:0]$11256 \dest31__data_i + case + assign $4\src21__data_o$next[1:0]$11256 $3\src21__data_o$next[1:0]$11255 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src21__data_o$next[1:0]$11257 \w1__data_i + case + assign $5\src21__data_o$next[1:0]$11257 $4\src21__data_o$next[1:0]$11256 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src21__data_o$next[1:0]$11258 \reg + case + assign $6\src21__data_o$next[1:0]$11258 $5\src21__data_o$next[1:0]$11257 + end + case + assign $1\src21__data_o$next[1:0]$11253 2'00 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\src21__data_o$next[1:0]$11259 2'00 + case + assign $7\src21__data_o$next[1:0]$11259 $1\src21__data_o$next[1:0]$11253 + end + sync always + update \src21__data_o$next $0\src21__data_o$next[1:0]$11252 + end + attribute \src "libresoc.v:183068.3-183103.6" + process $proc$libresoc.v:183068$11260 + assign { } { } + assign { } { } + assign $0\wr_detect$4[0:0]$11261 $1\wr_detect$4[0:0]$11262 + attribute \src "libresoc.v:183069.5-183069.29" + switch \initial + attribute \src "libresoc.v:183069.9-183069.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src21__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$4[0:0]$11262 $5\wr_detect$4[0:0]$11266 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest11__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$4[0:0]$11263 1'1 + case + assign $2\wr_detect$4[0:0]$11263 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest21__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$4[0:0]$11264 1'1 + case + assign $3\wr_detect$4[0:0]$11264 $2\wr_detect$4[0:0]$11263 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest31__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$4[0:0]$11265 1'1 + case + assign $4\wr_detect$4[0:0]$11265 $3\wr_detect$4[0:0]$11264 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\wr_detect$4[0:0]$11266 1'1 + case + assign $5\wr_detect$4[0:0]$11266 $4\wr_detect$4[0:0]$11265 + end + case + assign $1\wr_detect$4[0:0]$11262 1'0 + end + sync always + update \wr_detect$4 $0\wr_detect$4[0:0]$11261 + end + attribute \src "libresoc.v:183104.3-183149.6" + process $proc$libresoc.v:183104$11267 + assign { } { } + assign { } { } + assign { } { } + assign $0\src31__data_o$next[1:0]$11268 $7\src31__data_o$next[1:0]$11275 + attribute \src "libresoc.v:183105.5-183105.29" + switch \initial + attribute \src "libresoc.v:183105.9-183105.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src31__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src31__data_o$next[1:0]$11269 $6\src31__data_o$next[1:0]$11274 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest11__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src31__data_o$next[1:0]$11270 \dest11__data_i + case + assign $2\src31__data_o$next[1:0]$11270 2'00 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest21__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src31__data_o$next[1:0]$11271 \dest21__data_i + case + assign $3\src31__data_o$next[1:0]$11271 $2\src31__data_o$next[1:0]$11270 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest31__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src31__data_o$next[1:0]$11272 \dest31__data_i + case + assign $4\src31__data_o$next[1:0]$11272 $3\src31__data_o$next[1:0]$11271 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src31__data_o$next[1:0]$11273 \w1__data_i + case + assign $5\src31__data_o$next[1:0]$11273 $4\src31__data_o$next[1:0]$11272 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$6 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src31__data_o$next[1:0]$11274 \reg + case + assign $6\src31__data_o$next[1:0]$11274 $5\src31__data_o$next[1:0]$11273 + end + case + assign $1\src31__data_o$next[1:0]$11269 2'00 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\src31__data_o$next[1:0]$11275 2'00 + case + assign $7\src31__data_o$next[1:0]$11275 $1\src31__data_o$next[1:0]$11269 + end + sync always + update \src31__data_o$next $0\src31__data_o$next[1:0]$11268 + end + attribute \src "libresoc.v:183150.3-183185.6" + process $proc$libresoc.v:183150$11276 + assign { } { } + assign { } { } + assign $0\wr_detect$7[0:0]$11277 $1\wr_detect$7[0:0]$11278 + attribute \src "libresoc.v:183151.5-183151.29" + switch \initial + attribute \src "libresoc.v:183151.9-183151.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src31__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$7[0:0]$11278 $5\wr_detect$7[0:0]$11282 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest11__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$7[0:0]$11279 1'1 + case + assign $2\wr_detect$7[0:0]$11279 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest21__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$7[0:0]$11280 1'1 + case + assign $3\wr_detect$7[0:0]$11280 $2\wr_detect$7[0:0]$11279 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest31__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$7[0:0]$11281 1'1 + case + assign $4\wr_detect$7[0:0]$11281 $3\wr_detect$7[0:0]$11280 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\wr_detect$7[0:0]$11282 1'1 + case + assign $5\wr_detect$7[0:0]$11282 $4\wr_detect$7[0:0]$11281 + end + case + assign $1\wr_detect$7[0:0]$11278 1'0 + end + sync always + update \wr_detect$7 $0\wr_detect$7[0:0]$11277 + end + attribute \src "libresoc.v:183186.3-183231.6" + process $proc$libresoc.v:183186$11283 + assign { } { } + assign { } { } + assign { } { } + assign $0\r1__data_o$next[1:0]$11284 $7\r1__data_o$next[1:0]$11291 + attribute \src "libresoc.v:183187.5-183187.29" + switch \initial + attribute \src "libresoc.v:183187.9-183187.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r1__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\r1__data_o$next[1:0]$11285 $6\r1__data_o$next[1:0]$11290 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest11__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r1__data_o$next[1:0]$11286 \dest11__data_i + case + assign $2\r1__data_o$next[1:0]$11286 2'00 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest21__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\r1__data_o$next[1:0]$11287 \dest21__data_i + case + assign $3\r1__data_o$next[1:0]$11287 $2\r1__data_o$next[1:0]$11286 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest31__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\r1__data_o$next[1:0]$11288 \dest31__data_i + case + assign $4\r1__data_o$next[1:0]$11288 $3\r1__data_o$next[1:0]$11287 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\r1__data_o$next[1:0]$11289 \w1__data_i + case + assign $5\r1__data_o$next[1:0]$11289 $4\r1__data_o$next[1:0]$11288 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$9 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\r1__data_o$next[1:0]$11290 \reg + case + assign $6\r1__data_o$next[1:0]$11290 $5\r1__data_o$next[1:0]$11289 + end + case + assign $1\r1__data_o$next[1:0]$11285 2'00 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\r1__data_o$next[1:0]$11291 2'00 + case + assign $7\r1__data_o$next[1:0]$11291 $1\r1__data_o$next[1:0]$11285 + end + sync always + update \r1__data_o$next $0\r1__data_o$next[1:0]$11284 + end + attribute \src "libresoc.v:183232.3-183267.6" + process $proc$libresoc.v:183232$11292 + assign { } { } + assign { } { } + assign $0\wr_detect$10[0:0]$11293 $1\wr_detect$10[0:0]$11294 + attribute \src "libresoc.v:183233.5-183233.29" + switch \initial + attribute \src "libresoc.v:183233.9-183233.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r1__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$10[0:0]$11294 $5\wr_detect$10[0:0]$11298 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest11__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$10[0:0]$11295 1'1 + case + assign $2\wr_detect$10[0:0]$11295 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest21__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$10[0:0]$11296 1'1 + case + assign $3\wr_detect$10[0:0]$11296 $2\wr_detect$10[0:0]$11295 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest31__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$10[0:0]$11297 1'1 + case + assign $4\wr_detect$10[0:0]$11297 $3\wr_detect$10[0:0]$11296 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\wr_detect$10[0:0]$11298 1'1 + case + assign $5\wr_detect$10[0:0]$11298 $4\wr_detect$10[0:0]$11297 + end + case + assign $1\wr_detect$10[0:0]$11294 1'0 + end + sync always + update \wr_detect$10 $0\wr_detect$10[0:0]$11293 + end + attribute \src "libresoc.v:183268.3-183300.6" + process $proc$libresoc.v:183268$11299 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\reg$next[1:0]$11300 $5\reg$next[1:0]$11305 + attribute \src "libresoc.v:183269.5-183269.29" + switch \initial + attribute \src "libresoc.v:183269.9-183269.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest11__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\reg$next[1:0]$11301 \dest11__data_i + case + assign $1\reg$next[1:0]$11301 \reg + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest21__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\reg$next[1:0]$11302 \dest21__data_i + case + assign $2\reg$next[1:0]$11302 $1\reg$next[1:0]$11301 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest31__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\reg$next[1:0]$11303 \dest31__data_i + case + assign $3\reg$next[1:0]$11303 $2\reg$next[1:0]$11302 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \w1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\reg$next[1:0]$11304 \w1__data_i + case + assign $4\reg$next[1:0]$11304 $3\reg$next[1:0]$11303 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\reg$next[1:0]$11305 2'00 + case + assign $5\reg$next[1:0]$11305 $4\reg$next[1:0]$11304 + end + sync always + update \reg$next $0\reg$next[1:0]$11300 + end + connect \$9 $not$libresoc.v:182926$11232_Y + connect \$1 $not$libresoc.v:182927$11233_Y + connect \$3 $not$libresoc.v:182928$11234_Y + connect \$6 $not$libresoc.v:182929$11235_Y +end +attribute \src "libresoc.v:183305.1-183654.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.state.reg_1" +attribute \generator "nMigen" +module \reg_1$136 + attribute \src "libresoc.v:183375.3-183420.6" + wire width 64 $0\cia1__data_o$next[63:0]$11320 + attribute \src "libresoc.v:183373.3-183374.41" + wire width 64 $0\cia1__data_o[63:0] + attribute \src "libresoc.v:183306.7-183306.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:183457.3-183502.6" + wire width 64 $0\msr1__data_o$next[63:0]$11330 + attribute \src "libresoc.v:183371.3-183372.41" + wire width 64 $0\msr1__data_o[63:0] + attribute \src "libresoc.v:183621.3-183653.6" + wire width 64 $0\reg$next[63:0]$11362 + attribute \src "libresoc.v:183367.3-183368.25" + wire width 64 $0\reg[63:0] + attribute \src "libresoc.v:183539.3-183584.6" + wire width 64 $0\sv1__data_o$next[63:0]$11346 + attribute \src "libresoc.v:183369.3-183370.39" + wire width 64 $0\sv1__data_o[63:0] + attribute \src "libresoc.v:183503.3-183538.6" + wire $0\wr_detect$4[0:0]$11339 + attribute \src "libresoc.v:183585.3-183620.6" + wire $0\wr_detect$7[0:0]$11355 + attribute \src "libresoc.v:183421.3-183456.6" + wire $0\wr_detect[0:0] + attribute \src "libresoc.v:183375.3-183420.6" + wire width 64 $1\cia1__data_o$next[63:0]$11321 + attribute \src "libresoc.v:183315.14-183315.49" + wire width 64 $1\cia1__data_o[63:0] + attribute \src "libresoc.v:183457.3-183502.6" + wire width 64 $1\msr1__data_o$next[63:0]$11331 + attribute \src "libresoc.v:183332.14-183332.49" + wire width 64 $1\msr1__data_o[63:0] + attribute \src "libresoc.v:183621.3-183653.6" + wire width 64 $1\reg$next[63:0]$11363 + attribute \src "libresoc.v:183344.14-183344.42" + wire width 64 $1\reg[63:0] + attribute \src "libresoc.v:183539.3-183584.6" + wire width 64 $1\sv1__data_o$next[63:0]$11347 + attribute \src "libresoc.v:183351.14-183351.48" + wire width 64 $1\sv1__data_o[63:0] + attribute \src "libresoc.v:183503.3-183538.6" + wire $1\wr_detect$4[0:0]$11340 + attribute \src "libresoc.v:183585.3-183620.6" + wire $1\wr_detect$7[0:0]$11356 + attribute \src "libresoc.v:183421.3-183456.6" + wire $1\wr_detect[0:0] + attribute \src "libresoc.v:183375.3-183420.6" + wire width 64 $2\cia1__data_o$next[63:0]$11322 + attribute \src "libresoc.v:183457.3-183502.6" + wire width 64 $2\msr1__data_o$next[63:0]$11332 + attribute \src "libresoc.v:183621.3-183653.6" + wire width 64 $2\reg$next[63:0]$11364 + attribute \src "libresoc.v:183539.3-183584.6" + wire width 64 $2\sv1__data_o$next[63:0]$11348 + attribute \src "libresoc.v:183503.3-183538.6" + wire $2\wr_detect$4[0:0]$11341 + attribute \src "libresoc.v:183585.3-183620.6" + wire $2\wr_detect$7[0:0]$11357 + attribute \src "libresoc.v:183421.3-183456.6" + wire $2\wr_detect[0:0] + attribute \src "libresoc.v:183375.3-183420.6" + wire width 64 $3\cia1__data_o$next[63:0]$11323 + attribute \src "libresoc.v:183457.3-183502.6" + wire width 64 $3\msr1__data_o$next[63:0]$11333 + attribute \src "libresoc.v:183621.3-183653.6" + wire width 64 $3\reg$next[63:0]$11365 + attribute \src "libresoc.v:183539.3-183584.6" + wire width 64 $3\sv1__data_o$next[63:0]$11349 + attribute \src "libresoc.v:183503.3-183538.6" + wire $3\wr_detect$4[0:0]$11342 + attribute \src "libresoc.v:183585.3-183620.6" + wire $3\wr_detect$7[0:0]$11358 + attribute \src "libresoc.v:183421.3-183456.6" + wire $3\wr_detect[0:0] + attribute \src "libresoc.v:183375.3-183420.6" + wire width 64 $4\cia1__data_o$next[63:0]$11324 + attribute \src "libresoc.v:183457.3-183502.6" + wire width 64 $4\msr1__data_o$next[63:0]$11334 + attribute \src "libresoc.v:183621.3-183653.6" + wire width 64 $4\reg$next[63:0]$11366 + attribute \src "libresoc.v:183539.3-183584.6" + wire width 64 $4\sv1__data_o$next[63:0]$11350 + attribute \src "libresoc.v:183503.3-183538.6" + wire $4\wr_detect$4[0:0]$11343 + attribute \src "libresoc.v:183585.3-183620.6" + wire $4\wr_detect$7[0:0]$11359 + attribute \src "libresoc.v:183421.3-183456.6" + wire $4\wr_detect[0:0] + attribute \src "libresoc.v:183375.3-183420.6" + wire width 64 $5\cia1__data_o$next[63:0]$11325 + attribute \src "libresoc.v:183457.3-183502.6" + wire width 64 $5\msr1__data_o$next[63:0]$11335 + attribute \src "libresoc.v:183621.3-183653.6" + wire width 64 $5\reg$next[63:0]$11367 + attribute \src "libresoc.v:183539.3-183584.6" + wire width 64 $5\sv1__data_o$next[63:0]$11351 + attribute \src "libresoc.v:183503.3-183538.6" + wire $5\wr_detect$4[0:0]$11344 + attribute \src "libresoc.v:183585.3-183620.6" + wire $5\wr_detect$7[0:0]$11360 + attribute \src "libresoc.v:183421.3-183456.6" + wire $5\wr_detect[0:0] + attribute \src "libresoc.v:183375.3-183420.6" + wire width 64 $6\cia1__data_o$next[63:0]$11326 + attribute \src "libresoc.v:183457.3-183502.6" + wire width 64 $6\msr1__data_o$next[63:0]$11336 + attribute \src "libresoc.v:183539.3-183584.6" + wire width 64 $6\sv1__data_o$next[63:0]$11352 + attribute \src "libresoc.v:183375.3-183420.6" + wire width 64 $7\cia1__data_o$next[63:0]$11327 + attribute \src "libresoc.v:183457.3-183502.6" + wire width 64 $7\msr1__data_o$next[63:0]$11337 + attribute \src "libresoc.v:183539.3-183584.6" + wire width 64 $7\sv1__data_o$next[63:0]$11353 + attribute \src "libresoc.v:183364.17-183364.100" + wire $not$libresoc.v:183364$11312_Y + attribute \src "libresoc.v:183365.17-183365.103" + wire $not$libresoc.v:183365$11313_Y + attribute \src "libresoc.v:183366.17-183366.103" + wire $not$libresoc.v:183366$11314_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 output 3 \cia1__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 \cia1__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 2 \cia1__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 16 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 input 15 \d_wr11__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 14 \d_wr11__wen + attribute \src "libresoc.v:183306.7-183306.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 input 11 \msr1__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 output 5 \msr1__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 \msr1__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 4 \msr1__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 10 \msr1__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 input 9 \nia1__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 8 \nia1__wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 64 \reg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 64 \reg$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 input 13 \sv1__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 output 7 \sv1__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 \sv1__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 6 \sv1__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 12 \sv1__wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:183364$11312 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect + connect \Y $not$libresoc.v:183364$11312_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:183365$11313 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$4 + connect \Y $not$libresoc.v:183365$11313_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:183366$11314 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$7 + connect \Y $not$libresoc.v:183366$11314_Y + end + attribute \src "libresoc.v:183306.7-183306.20" + process $proc$libresoc.v:183306$11368 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:183315.14-183315.49" + process $proc$libresoc.v:183315$11369 + assign { } { } + assign $1\cia1__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \cia1__data_o $1\cia1__data_o[63:0] + end + attribute \src "libresoc.v:183332.14-183332.49" + process $proc$libresoc.v:183332$11370 + assign { } { } + assign $1\msr1__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \msr1__data_o $1\msr1__data_o[63:0] + end + attribute \src "libresoc.v:183344.14-183344.42" + process $proc$libresoc.v:183344$11371 + assign { } { } + assign $1\reg[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \reg $1\reg[63:0] + end + attribute \src "libresoc.v:183351.14-183351.48" + process $proc$libresoc.v:183351$11372 + assign { } { } + assign $1\sv1__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \sv1__data_o $1\sv1__data_o[63:0] + end + attribute \src "libresoc.v:183367.3-183368.25" + process $proc$libresoc.v:183367$11315 + assign { } { } + assign $0\reg[63:0] \reg$next + sync posedge \coresync_clk + update \reg $0\reg[63:0] + end + attribute \src "libresoc.v:183369.3-183370.39" + process $proc$libresoc.v:183369$11316 + assign { } { } + assign $0\sv1__data_o[63:0] \sv1__data_o$next + sync posedge \coresync_clk + update \sv1__data_o $0\sv1__data_o[63:0] + end + attribute \src "libresoc.v:183371.3-183372.41" + process $proc$libresoc.v:183371$11317 + assign { } { } + assign $0\msr1__data_o[63:0] \msr1__data_o$next + sync posedge \coresync_clk + update \msr1__data_o $0\msr1__data_o[63:0] + end + attribute \src "libresoc.v:183373.3-183374.41" + process $proc$libresoc.v:183373$11318 + assign { } { } + assign $0\cia1__data_o[63:0] \cia1__data_o$next + sync posedge \coresync_clk + update \cia1__data_o $0\cia1__data_o[63:0] + end + attribute \src "libresoc.v:183375.3-183420.6" + process $proc$libresoc.v:183375$11319 + assign { } { } + assign { } { } + assign { } { } + assign $0\cia1__data_o$next[63:0]$11320 $7\cia1__data_o$next[63:0]$11327 + attribute \src "libresoc.v:183376.5-183376.29" + switch \initial + attribute \src "libresoc.v:183376.9-183376.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \cia1__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\cia1__data_o$next[63:0]$11321 $6\cia1__data_o$next[63:0]$11326 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \nia1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cia1__data_o$next[63:0]$11322 \nia1__data_i + case + assign $2\cia1__data_o$next[63:0]$11322 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \msr1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\cia1__data_o$next[63:0]$11323 \msr1__data_i + case + assign $3\cia1__data_o$next[63:0]$11323 $2\cia1__data_o$next[63:0]$11322 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \sv1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\cia1__data_o$next[63:0]$11324 \sv1__data_i + case + assign $4\cia1__data_o$next[63:0]$11324 $3\cia1__data_o$next[63:0]$11323 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \d_wr11__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\cia1__data_o$next[63:0]$11325 \d_wr11__data_i + case + assign $5\cia1__data_o$next[63:0]$11325 $4\cia1__data_o$next[63:0]$11324 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\cia1__data_o$next[63:0]$11326 \reg + case + assign $6\cia1__data_o$next[63:0]$11326 $5\cia1__data_o$next[63:0]$11325 + end + case + assign $1\cia1__data_o$next[63:0]$11321 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\cia1__data_o$next[63:0]$11327 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $7\cia1__data_o$next[63:0]$11327 $1\cia1__data_o$next[63:0]$11321 + end + sync always + update \cia1__data_o$next $0\cia1__data_o$next[63:0]$11320 + end + attribute \src "libresoc.v:183421.3-183456.6" + process $proc$libresoc.v:183421$11328 + assign { } { } + assign { } { } + assign $0\wr_detect[0:0] $1\wr_detect[0:0] + attribute \src "libresoc.v:183422.5-183422.29" + switch \initial + attribute \src "libresoc.v:183422.9-183422.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \cia1__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect[0:0] $5\wr_detect[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \nia1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect[0:0] 1'1 + case + assign $2\wr_detect[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \msr1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect[0:0] 1'1 + case + assign $3\wr_detect[0:0] $2\wr_detect[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \sv1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect[0:0] 1'1 + case + assign $4\wr_detect[0:0] $3\wr_detect[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \d_wr11__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\wr_detect[0:0] 1'1 + case + assign $5\wr_detect[0:0] $4\wr_detect[0:0] + end + case + assign $1\wr_detect[0:0] 1'0 + end + sync always + update \wr_detect $0\wr_detect[0:0] + end + attribute \src "libresoc.v:183457.3-183502.6" + process $proc$libresoc.v:183457$11329 + assign { } { } + assign { } { } + assign { } { } + assign $0\msr1__data_o$next[63:0]$11330 $7\msr1__data_o$next[63:0]$11337 + attribute \src "libresoc.v:183458.5-183458.29" + switch \initial + attribute \src "libresoc.v:183458.9-183458.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \msr1__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\msr1__data_o$next[63:0]$11331 $6\msr1__data_o$next[63:0]$11336 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \nia1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\msr1__data_o$next[63:0]$11332 \nia1__data_i + case + assign $2\msr1__data_o$next[63:0]$11332 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \msr1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\msr1__data_o$next[63:0]$11333 \msr1__data_i + case + assign $3\msr1__data_o$next[63:0]$11333 $2\msr1__data_o$next[63:0]$11332 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \sv1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\msr1__data_o$next[63:0]$11334 \sv1__data_i + case + assign $4\msr1__data_o$next[63:0]$11334 $3\msr1__data_o$next[63:0]$11333 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \d_wr11__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\msr1__data_o$next[63:0]$11335 \d_wr11__data_i + case + assign $5\msr1__data_o$next[63:0]$11335 $4\msr1__data_o$next[63:0]$11334 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\msr1__data_o$next[63:0]$11336 \reg + case + assign $6\msr1__data_o$next[63:0]$11336 $5\msr1__data_o$next[63:0]$11335 + end + case + assign $1\msr1__data_o$next[63:0]$11331 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\msr1__data_o$next[63:0]$11337 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $7\msr1__data_o$next[63:0]$11337 $1\msr1__data_o$next[63:0]$11331 + end + sync always + update \msr1__data_o$next $0\msr1__data_o$next[63:0]$11330 + end + attribute \src "libresoc.v:183503.3-183538.6" + process $proc$libresoc.v:183503$11338 + assign { } { } + assign { } { } + assign $0\wr_detect$4[0:0]$11339 $1\wr_detect$4[0:0]$11340 + attribute \src "libresoc.v:183504.5-183504.29" + switch \initial + attribute \src "libresoc.v:183504.9-183504.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \msr1__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$4[0:0]$11340 $5\wr_detect$4[0:0]$11344 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \nia1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$4[0:0]$11341 1'1 + case + assign $2\wr_detect$4[0:0]$11341 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \msr1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$4[0:0]$11342 1'1 + case + assign $3\wr_detect$4[0:0]$11342 $2\wr_detect$4[0:0]$11341 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \sv1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$4[0:0]$11343 1'1 + case + assign $4\wr_detect$4[0:0]$11343 $3\wr_detect$4[0:0]$11342 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \d_wr11__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\wr_detect$4[0:0]$11344 1'1 + case + assign $5\wr_detect$4[0:0]$11344 $4\wr_detect$4[0:0]$11343 + end + case + assign $1\wr_detect$4[0:0]$11340 1'0 + end + sync always + update \wr_detect$4 $0\wr_detect$4[0:0]$11339 + end + attribute \src "libresoc.v:183539.3-183584.6" + process $proc$libresoc.v:183539$11345 + assign { } { } + assign { } { } + assign { } { } + assign $0\sv1__data_o$next[63:0]$11346 $7\sv1__data_o$next[63:0]$11353 + attribute \src "libresoc.v:183540.5-183540.29" + switch \initial + attribute \src "libresoc.v:183540.9-183540.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \sv1__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\sv1__data_o$next[63:0]$11347 $6\sv1__data_o$next[63:0]$11352 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \nia1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\sv1__data_o$next[63:0]$11348 \nia1__data_i + case + assign $2\sv1__data_o$next[63:0]$11348 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \msr1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\sv1__data_o$next[63:0]$11349 \msr1__data_i + case + assign $3\sv1__data_o$next[63:0]$11349 $2\sv1__data_o$next[63:0]$11348 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \sv1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\sv1__data_o$next[63:0]$11350 \sv1__data_i + case + assign $4\sv1__data_o$next[63:0]$11350 $3\sv1__data_o$next[63:0]$11349 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \d_wr11__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\sv1__data_o$next[63:0]$11351 \d_wr11__data_i + case + assign $5\sv1__data_o$next[63:0]$11351 $4\sv1__data_o$next[63:0]$11350 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$6 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\sv1__data_o$next[63:0]$11352 \reg + case + assign $6\sv1__data_o$next[63:0]$11352 $5\sv1__data_o$next[63:0]$11351 + end + case + assign $1\sv1__data_o$next[63:0]$11347 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\sv1__data_o$next[63:0]$11353 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $7\sv1__data_o$next[63:0]$11353 $1\sv1__data_o$next[63:0]$11347 + end + sync always + update \sv1__data_o$next $0\sv1__data_o$next[63:0]$11346 + end + attribute \src "libresoc.v:183585.3-183620.6" + process $proc$libresoc.v:183585$11354 + assign { } { } + assign { } { } + assign $0\wr_detect$7[0:0]$11355 $1\wr_detect$7[0:0]$11356 + attribute \src "libresoc.v:183586.5-183586.29" + switch \initial + attribute \src "libresoc.v:183586.9-183586.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \sv1__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$7[0:0]$11356 $5\wr_detect$7[0:0]$11360 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \nia1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$7[0:0]$11357 1'1 + case + assign $2\wr_detect$7[0:0]$11357 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \msr1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$7[0:0]$11358 1'1 + case + assign $3\wr_detect$7[0:0]$11358 $2\wr_detect$7[0:0]$11357 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \sv1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$7[0:0]$11359 1'1 + case + assign $4\wr_detect$7[0:0]$11359 $3\wr_detect$7[0:0]$11358 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \d_wr11__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\wr_detect$7[0:0]$11360 1'1 + case + assign $5\wr_detect$7[0:0]$11360 $4\wr_detect$7[0:0]$11359 + end + case + assign $1\wr_detect$7[0:0]$11356 1'0 + end + sync always + update \wr_detect$7 $0\wr_detect$7[0:0]$11355 + end + attribute \src "libresoc.v:183621.3-183653.6" + process $proc$libresoc.v:183621$11361 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\reg$next[63:0]$11362 $5\reg$next[63:0]$11367 + attribute \src "libresoc.v:183622.5-183622.29" + switch \initial + attribute \src "libresoc.v:183622.9-183622.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \nia1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\reg$next[63:0]$11363 \nia1__data_i + case + assign $1\reg$next[63:0]$11363 \reg + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \msr1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\reg$next[63:0]$11364 \msr1__data_i + case + assign $2\reg$next[63:0]$11364 $1\reg$next[63:0]$11363 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \sv1__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\reg$next[63:0]$11365 \sv1__data_i + case + assign $3\reg$next[63:0]$11365 $2\reg$next[63:0]$11364 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \d_wr11__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\reg$next[63:0]$11366 \d_wr11__data_i + case + assign $4\reg$next[63:0]$11366 $3\reg$next[63:0]$11365 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\reg$next[63:0]$11367 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $5\reg$next[63:0]$11367 $4\reg$next[63:0]$11366 + end + sync always + update \reg$next $0\reg$next[63:0]$11362 + end + connect \$1 $not$libresoc.v:183364$11312_Y + connect \$3 $not$libresoc.v:183365$11313_Y + connect \$6 $not$libresoc.v:183366$11314_Y +end +attribute \src "libresoc.v:183658.1-184129.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.cr.reg_2" +attribute \generator "nMigen" +module \reg_2 + attribute \src "libresoc.v:183659.7-183659.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:184059.3-184098.6" + wire width 4 $0\r22__data_o$next[3:0]$11442 + attribute \src "libresoc.v:183742.3-183743.39" + wire width 4 $0\r22__data_o[3:0] + attribute \src "libresoc.v:183989.3-184028.6" + wire width 4 $0\r2__data_o$next[3:0]$11428 + attribute \src "libresoc.v:183744.3-183745.37" + wire width 4 $0\r2__data_o[3:0] + attribute \src "libresoc.v:183822.3-183848.6" + wire width 4 $0\reg$next[3:0]$11394 + attribute \src "libresoc.v:183740.3-183741.25" + wire width 4 $0\reg[3:0] + attribute \src "libresoc.v:183752.3-183791.6" + wire width 4 $0\src12__data_o$next[3:0]$11385 + attribute \src "libresoc.v:183750.3-183751.43" + wire width 4 $0\src12__data_o[3:0] + attribute \src "libresoc.v:183849.3-183888.6" + wire width 4 $0\src22__data_o$next[3:0]$11400 + attribute \src "libresoc.v:183748.3-183749.43" + wire width 4 $0\src22__data_o[3:0] + attribute \src "libresoc.v:183919.3-183958.6" + wire width 4 $0\src32__data_o$next[3:0]$11414 + attribute \src "libresoc.v:183746.3-183747.43" + wire width 4 $0\src32__data_o[3:0] + attribute \src "libresoc.v:184029.3-184058.6" + wire $0\wr_detect$10[0:0]$11436 + attribute \src "libresoc.v:184099.3-184128.6" + wire $0\wr_detect$13[0:0]$11450 + attribute \src "libresoc.v:183889.3-183918.6" + wire $0\wr_detect$4[0:0]$11408 + attribute \src "libresoc.v:183959.3-183988.6" + wire $0\wr_detect$7[0:0]$11422 + attribute \src "libresoc.v:183792.3-183821.6" + wire $0\wr_detect[0:0] + attribute \src "libresoc.v:184059.3-184098.6" + wire width 4 $1\r22__data_o$next[3:0]$11443 + attribute \src "libresoc.v:183684.13-183684.31" + wire width 4 $1\r22__data_o[3:0] + attribute \src "libresoc.v:183989.3-184028.6" + wire width 4 $1\r2__data_o$next[3:0]$11429 + attribute \src "libresoc.v:183691.13-183691.30" + wire width 4 $1\r2__data_o[3:0] + attribute \src "libresoc.v:183822.3-183848.6" + wire width 4 $1\reg$next[3:0]$11395 + attribute \src "libresoc.v:183697.13-183697.25" + wire width 4 $1\reg[3:0] + attribute \src "libresoc.v:183752.3-183791.6" + wire width 4 $1\src12__data_o$next[3:0]$11386 + attribute \src "libresoc.v:183702.13-183702.33" + wire width 4 $1\src12__data_o[3:0] + attribute \src "libresoc.v:183849.3-183888.6" + wire width 4 $1\src22__data_o$next[3:0]$11401 + attribute \src "libresoc.v:183709.13-183709.33" + wire width 4 $1\src22__data_o[3:0] + attribute \src "libresoc.v:183919.3-183958.6" + wire width 4 $1\src32__data_o$next[3:0]$11415 + attribute \src "libresoc.v:183716.13-183716.33" + wire width 4 $1\src32__data_o[3:0] + attribute \src "libresoc.v:184029.3-184058.6" + wire $1\wr_detect$10[0:0]$11437 + attribute \src "libresoc.v:184099.3-184128.6" + wire $1\wr_detect$13[0:0]$11451 + attribute \src "libresoc.v:183889.3-183918.6" + wire $1\wr_detect$4[0:0]$11409 + attribute \src "libresoc.v:183959.3-183988.6" + wire $1\wr_detect$7[0:0]$11423 + attribute \src "libresoc.v:183792.3-183821.6" + wire $1\wr_detect[0:0] + attribute \src "libresoc.v:184059.3-184098.6" + wire width 4 $2\r22__data_o$next[3:0]$11444 + attribute \src "libresoc.v:183989.3-184028.6" + wire width 4 $2\r2__data_o$next[3:0]$11430 + attribute \src "libresoc.v:183822.3-183848.6" + wire width 4 $2\reg$next[3:0]$11396 + attribute \src "libresoc.v:183752.3-183791.6" + wire width 4 $2\src12__data_o$next[3:0]$11387 + attribute \src "libresoc.v:183849.3-183888.6" + wire width 4 $2\src22__data_o$next[3:0]$11402 + attribute \src "libresoc.v:183919.3-183958.6" + wire width 4 $2\src32__data_o$next[3:0]$11416 + attribute \src "libresoc.v:184029.3-184058.6" + wire $2\wr_detect$10[0:0]$11438 + attribute \src "libresoc.v:184099.3-184128.6" + wire $2\wr_detect$13[0:0]$11452 + attribute \src "libresoc.v:183889.3-183918.6" + wire $2\wr_detect$4[0:0]$11410 + attribute \src "libresoc.v:183959.3-183988.6" + wire $2\wr_detect$7[0:0]$11424 + attribute \src "libresoc.v:183792.3-183821.6" + wire $2\wr_detect[0:0] + attribute \src "libresoc.v:184059.3-184098.6" + wire width 4 $3\r22__data_o$next[3:0]$11445 + attribute \src "libresoc.v:183989.3-184028.6" + wire width 4 $3\r2__data_o$next[3:0]$11431 + attribute \src "libresoc.v:183822.3-183848.6" + wire width 4 $3\reg$next[3:0]$11397 + attribute \src "libresoc.v:183752.3-183791.6" + wire width 4 $3\src12__data_o$next[3:0]$11388 + attribute \src "libresoc.v:183849.3-183888.6" + wire width 4 $3\src22__data_o$next[3:0]$11403 + attribute \src "libresoc.v:183919.3-183958.6" + wire width 4 $3\src32__data_o$next[3:0]$11417 + attribute \src "libresoc.v:184029.3-184058.6" + wire $3\wr_detect$10[0:0]$11439 + attribute \src "libresoc.v:184099.3-184128.6" + wire $3\wr_detect$13[0:0]$11453 + attribute \src "libresoc.v:183889.3-183918.6" + wire $3\wr_detect$4[0:0]$11411 + attribute \src "libresoc.v:183959.3-183988.6" + wire $3\wr_detect$7[0:0]$11425 + attribute \src "libresoc.v:183792.3-183821.6" + wire $3\wr_detect[0:0] + attribute \src "libresoc.v:184059.3-184098.6" + wire width 4 $4\r22__data_o$next[3:0]$11446 + attribute \src "libresoc.v:183989.3-184028.6" + wire width 4 $4\r2__data_o$next[3:0]$11432 + attribute \src "libresoc.v:183822.3-183848.6" + wire width 4 $4\reg$next[3:0]$11398 + attribute \src "libresoc.v:183752.3-183791.6" + wire width 4 $4\src12__data_o$next[3:0]$11389 + attribute \src "libresoc.v:183849.3-183888.6" + wire width 4 $4\src22__data_o$next[3:0]$11404 + attribute \src "libresoc.v:183919.3-183958.6" + wire width 4 $4\src32__data_o$next[3:0]$11418 + attribute \src "libresoc.v:184029.3-184058.6" + wire $4\wr_detect$10[0:0]$11440 + attribute \src "libresoc.v:184099.3-184128.6" + wire $4\wr_detect$13[0:0]$11454 + attribute \src "libresoc.v:183889.3-183918.6" + wire $4\wr_detect$4[0:0]$11412 + attribute \src "libresoc.v:183959.3-183988.6" + wire $4\wr_detect$7[0:0]$11426 + attribute \src "libresoc.v:183792.3-183821.6" + wire $4\wr_detect[0:0] + attribute \src "libresoc.v:184059.3-184098.6" + wire width 4 $5\r22__data_o$next[3:0]$11447 + attribute \src "libresoc.v:183989.3-184028.6" + wire width 4 $5\r2__data_o$next[3:0]$11433 + attribute \src "libresoc.v:183752.3-183791.6" + wire width 4 $5\src12__data_o$next[3:0]$11390 + attribute \src "libresoc.v:183849.3-183888.6" + wire width 4 $5\src22__data_o$next[3:0]$11405 + attribute \src "libresoc.v:183919.3-183958.6" + wire width 4 $5\src32__data_o$next[3:0]$11419 + attribute \src "libresoc.v:184059.3-184098.6" + wire width 4 $6\r22__data_o$next[3:0]$11448 + attribute \src "libresoc.v:183989.3-184028.6" + wire width 4 $6\r2__data_o$next[3:0]$11434 + attribute \src "libresoc.v:183752.3-183791.6" + wire width 4 $6\src12__data_o$next[3:0]$11391 + attribute \src "libresoc.v:183849.3-183888.6" + wire width 4 $6\src22__data_o$next[3:0]$11406 + attribute \src "libresoc.v:183919.3-183958.6" + wire width 4 $6\src32__data_o$next[3:0]$11420 + attribute \src "libresoc.v:183735.17-183735.104" + wire $not$libresoc.v:183735$11373_Y + attribute \src "libresoc.v:183736.18-183736.105" + wire $not$libresoc.v:183736$11374_Y + attribute \src "libresoc.v:183737.17-183737.100" + wire $not$libresoc.v:183737$11375_Y + attribute \src "libresoc.v:183738.17-183738.103" + wire $not$libresoc.v:183738$11376_Y + attribute \src "libresoc.v:183739.17-183739.103" + wire $not$libresoc.v:183739$11377_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 18 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 input 9 \dest12__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 8 \dest12__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 input 11 \dest22__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 10 \dest22__wen + attribute \src "libresoc.v:183659.7-183659.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 output 14 \r22__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 \r22__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 15 \r22__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 output 12 \r2__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 \r2__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 13 \r2__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 4 \reg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 4 \reg$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 output 3 \src12__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 \src12__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 2 \src12__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 output 5 \src22__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 \src22__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 4 \src22__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 output 7 \src32__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 \src32__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 6 \src32__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 input 16 \w2__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 17 \w2__wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:183735$11373 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$10 + connect \Y $not$libresoc.v:183735$11373_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:183736$11374 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$13 + connect \Y $not$libresoc.v:183736$11374_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:183737$11375 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect + connect \Y $not$libresoc.v:183737$11375_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:183738$11376 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$4 + connect \Y $not$libresoc.v:183738$11376_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:183739$11377 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$7 + connect \Y $not$libresoc.v:183739$11377_Y + end + attribute \src "libresoc.v:183659.7-183659.20" + process $proc$libresoc.v:183659$11455 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:183684.13-183684.31" + process $proc$libresoc.v:183684$11456 + assign { } { } + assign $1\r22__data_o[3:0] 4'0000 + sync always + sync init + update \r22__data_o $1\r22__data_o[3:0] + end + attribute \src "libresoc.v:183691.13-183691.30" + process $proc$libresoc.v:183691$11457 + assign { } { } + assign $1\r2__data_o[3:0] 4'0000 + sync always + sync init + update \r2__data_o $1\r2__data_o[3:0] + end + attribute \src "libresoc.v:183697.13-183697.25" + process $proc$libresoc.v:183697$11458 + assign { } { } + assign $1\reg[3:0] 4'0000 + sync always + sync init + update \reg $1\reg[3:0] + end + attribute \src "libresoc.v:183702.13-183702.33" + process $proc$libresoc.v:183702$11459 + assign { } { } + assign $1\src12__data_o[3:0] 4'0000 + sync always + sync init + update \src12__data_o $1\src12__data_o[3:0] + end + attribute \src "libresoc.v:183709.13-183709.33" + process $proc$libresoc.v:183709$11460 + assign { } { } + assign $1\src22__data_o[3:0] 4'0000 + sync always + sync init + update \src22__data_o $1\src22__data_o[3:0] + end + attribute \src "libresoc.v:183716.13-183716.33" + process $proc$libresoc.v:183716$11461 + assign { } { } + assign $1\src32__data_o[3:0] 4'0000 + sync always + sync init + update \src32__data_o $1\src32__data_o[3:0] + end + attribute \src "libresoc.v:183740.3-183741.25" + process $proc$libresoc.v:183740$11378 + assign { } { } + assign $0\reg[3:0] \reg$next + sync posedge \coresync_clk + update \reg $0\reg[3:0] + end + attribute \src "libresoc.v:183742.3-183743.39" + process $proc$libresoc.v:183742$11379 + assign { } { } + assign $0\r22__data_o[3:0] \r22__data_o$next + sync posedge \coresync_clk + update \r22__data_o $0\r22__data_o[3:0] + end + attribute \src "libresoc.v:183744.3-183745.37" + process $proc$libresoc.v:183744$11380 + assign { } { } + assign $0\r2__data_o[3:0] \r2__data_o$next + sync posedge \coresync_clk + update \r2__data_o $0\r2__data_o[3:0] + end + attribute \src "libresoc.v:183746.3-183747.43" + process $proc$libresoc.v:183746$11381 + assign { } { } + assign $0\src32__data_o[3:0] \src32__data_o$next + sync posedge \coresync_clk + update \src32__data_o $0\src32__data_o[3:0] + end + attribute \src "libresoc.v:183748.3-183749.43" + process $proc$libresoc.v:183748$11382 + assign { } { } + assign $0\src22__data_o[3:0] \src22__data_o$next + sync posedge \coresync_clk + update \src22__data_o $0\src22__data_o[3:0] + end + attribute \src "libresoc.v:183750.3-183751.43" + process $proc$libresoc.v:183750$11383 + assign { } { } + assign $0\src12__data_o[3:0] \src12__data_o$next + sync posedge \coresync_clk + update \src12__data_o $0\src12__data_o[3:0] + end + attribute \src "libresoc.v:183752.3-183791.6" + process $proc$libresoc.v:183752$11384 + assign { } { } + assign { } { } + assign { } { } + assign $0\src12__data_o$next[3:0]$11385 $6\src12__data_o$next[3:0]$11391 + attribute \src "libresoc.v:183753.5-183753.29" + switch \initial + attribute \src "libresoc.v:183753.9-183753.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src12__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src12__data_o$next[3:0]$11386 $5\src12__data_o$next[3:0]$11390 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest12__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src12__data_o$next[3:0]$11387 \dest12__data_i + case + assign $2\src12__data_o$next[3:0]$11387 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest22__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src12__data_o$next[3:0]$11388 \dest22__data_i + case + assign $3\src12__data_o$next[3:0]$11388 $2\src12__data_o$next[3:0]$11387 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src12__data_o$next[3:0]$11389 \w2__data_i + case + assign $4\src12__data_o$next[3:0]$11389 $3\src12__data_o$next[3:0]$11388 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src12__data_o$next[3:0]$11390 \reg + case + assign $5\src12__data_o$next[3:0]$11390 $4\src12__data_o$next[3:0]$11389 + end + case + assign $1\src12__data_o$next[3:0]$11386 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src12__data_o$next[3:0]$11391 4'0000 + case + assign $6\src12__data_o$next[3:0]$11391 $1\src12__data_o$next[3:0]$11386 + end + sync always + update \src12__data_o$next $0\src12__data_o$next[3:0]$11385 + end + attribute \src "libresoc.v:183792.3-183821.6" + process $proc$libresoc.v:183792$11392 + assign { } { } + assign { } { } + assign $0\wr_detect[0:0] $1\wr_detect[0:0] + attribute \src "libresoc.v:183793.5-183793.29" + switch \initial + attribute \src "libresoc.v:183793.9-183793.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src12__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect[0:0] $4\wr_detect[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest12__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect[0:0] 1'1 + case + assign $2\wr_detect[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest22__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect[0:0] 1'1 + case + assign $3\wr_detect[0:0] $2\wr_detect[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect[0:0] 1'1 + case + assign $4\wr_detect[0:0] $3\wr_detect[0:0] + end + case + assign $1\wr_detect[0:0] 1'0 + end + sync always + update \wr_detect $0\wr_detect[0:0] + end + attribute \src "libresoc.v:183822.3-183848.6" + process $proc$libresoc.v:183822$11393 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\reg$next[3:0]$11394 $4\reg$next[3:0]$11398 + attribute \src "libresoc.v:183823.5-183823.29" + switch \initial + attribute \src "libresoc.v:183823.9-183823.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest12__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\reg$next[3:0]$11395 \dest12__data_i + case + assign $1\reg$next[3:0]$11395 \reg + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest22__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\reg$next[3:0]$11396 \dest22__data_i + case + assign $2\reg$next[3:0]$11396 $1\reg$next[3:0]$11395 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \w2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\reg$next[3:0]$11397 \w2__data_i + case + assign $3\reg$next[3:0]$11397 $2\reg$next[3:0]$11396 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\reg$next[3:0]$11398 4'0000 + case + assign $4\reg$next[3:0]$11398 $3\reg$next[3:0]$11397 + end + sync always + update \reg$next $0\reg$next[3:0]$11394 + end + attribute \src "libresoc.v:183849.3-183888.6" + process $proc$libresoc.v:183849$11399 + assign { } { } + assign { } { } + assign { } { } + assign $0\src22__data_o$next[3:0]$11400 $6\src22__data_o$next[3:0]$11406 + attribute \src "libresoc.v:183850.5-183850.29" + switch \initial + attribute \src "libresoc.v:183850.9-183850.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src22__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src22__data_o$next[3:0]$11401 $5\src22__data_o$next[3:0]$11405 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest12__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src22__data_o$next[3:0]$11402 \dest12__data_i + case + assign $2\src22__data_o$next[3:0]$11402 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest22__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src22__data_o$next[3:0]$11403 \dest22__data_i + case + assign $3\src22__data_o$next[3:0]$11403 $2\src22__data_o$next[3:0]$11402 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src22__data_o$next[3:0]$11404 \w2__data_i + case + assign $4\src22__data_o$next[3:0]$11404 $3\src22__data_o$next[3:0]$11403 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src22__data_o$next[3:0]$11405 \reg + case + assign $5\src22__data_o$next[3:0]$11405 $4\src22__data_o$next[3:0]$11404 + end + case + assign $1\src22__data_o$next[3:0]$11401 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src22__data_o$next[3:0]$11406 4'0000 + case + assign $6\src22__data_o$next[3:0]$11406 $1\src22__data_o$next[3:0]$11401 + end + sync always + update \src22__data_o$next $0\src22__data_o$next[3:0]$11400 + end + attribute \src "libresoc.v:183889.3-183918.6" + process $proc$libresoc.v:183889$11407 + assign { } { } + assign { } { } + assign $0\wr_detect$4[0:0]$11408 $1\wr_detect$4[0:0]$11409 + attribute \src "libresoc.v:183890.5-183890.29" + switch \initial + attribute \src "libresoc.v:183890.9-183890.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src22__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$4[0:0]$11409 $4\wr_detect$4[0:0]$11412 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest12__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$4[0:0]$11410 1'1 + case + assign $2\wr_detect$4[0:0]$11410 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest22__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$4[0:0]$11411 1'1 + case + assign $3\wr_detect$4[0:0]$11411 $2\wr_detect$4[0:0]$11410 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$4[0:0]$11412 1'1 + case + assign $4\wr_detect$4[0:0]$11412 $3\wr_detect$4[0:0]$11411 + end + case + assign $1\wr_detect$4[0:0]$11409 1'0 + end + sync always + update \wr_detect$4 $0\wr_detect$4[0:0]$11408 + end + attribute \src "libresoc.v:183919.3-183958.6" + process $proc$libresoc.v:183919$11413 + assign { } { } + assign { } { } + assign { } { } + assign $0\src32__data_o$next[3:0]$11414 $6\src32__data_o$next[3:0]$11420 + attribute \src "libresoc.v:183920.5-183920.29" + switch \initial + attribute \src "libresoc.v:183920.9-183920.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src32__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src32__data_o$next[3:0]$11415 $5\src32__data_o$next[3:0]$11419 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest12__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src32__data_o$next[3:0]$11416 \dest12__data_i + case + assign $2\src32__data_o$next[3:0]$11416 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest22__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src32__data_o$next[3:0]$11417 \dest22__data_i + case + assign $3\src32__data_o$next[3:0]$11417 $2\src32__data_o$next[3:0]$11416 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src32__data_o$next[3:0]$11418 \w2__data_i + case + assign $4\src32__data_o$next[3:0]$11418 $3\src32__data_o$next[3:0]$11417 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$6 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src32__data_o$next[3:0]$11419 \reg + case + assign $5\src32__data_o$next[3:0]$11419 $4\src32__data_o$next[3:0]$11418 + end + case + assign $1\src32__data_o$next[3:0]$11415 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src32__data_o$next[3:0]$11420 4'0000 + case + assign $6\src32__data_o$next[3:0]$11420 $1\src32__data_o$next[3:0]$11415 + end + sync always + update \src32__data_o$next $0\src32__data_o$next[3:0]$11414 + end + attribute \src "libresoc.v:183959.3-183988.6" + process $proc$libresoc.v:183959$11421 + assign { } { } + assign { } { } + assign $0\wr_detect$7[0:0]$11422 $1\wr_detect$7[0:0]$11423 + attribute \src "libresoc.v:183960.5-183960.29" + switch \initial + attribute \src "libresoc.v:183960.9-183960.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src32__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$7[0:0]$11423 $4\wr_detect$7[0:0]$11426 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest12__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$7[0:0]$11424 1'1 + case + assign $2\wr_detect$7[0:0]$11424 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest22__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$7[0:0]$11425 1'1 + case + assign $3\wr_detect$7[0:0]$11425 $2\wr_detect$7[0:0]$11424 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$7[0:0]$11426 1'1 + case + assign $4\wr_detect$7[0:0]$11426 $3\wr_detect$7[0:0]$11425 + end + case + assign $1\wr_detect$7[0:0]$11423 1'0 + end + sync always + update \wr_detect$7 $0\wr_detect$7[0:0]$11422 + end + attribute \src "libresoc.v:183989.3-184028.6" + process $proc$libresoc.v:183989$11427 + assign { } { } + assign { } { } + assign { } { } + assign $0\r2__data_o$next[3:0]$11428 $6\r2__data_o$next[3:0]$11434 + attribute \src "libresoc.v:183990.5-183990.29" + switch \initial + attribute \src "libresoc.v:183990.9-183990.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r2__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\r2__data_o$next[3:0]$11429 $5\r2__data_o$next[3:0]$11433 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest12__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r2__data_o$next[3:0]$11430 \dest12__data_i + case + assign $2\r2__data_o$next[3:0]$11430 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest22__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\r2__data_o$next[3:0]$11431 \dest22__data_i + case + assign $3\r2__data_o$next[3:0]$11431 $2\r2__data_o$next[3:0]$11430 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\r2__data_o$next[3:0]$11432 \w2__data_i + case + assign $4\r2__data_o$next[3:0]$11432 $3\r2__data_o$next[3:0]$11431 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$9 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\r2__data_o$next[3:0]$11433 \reg + case + assign $5\r2__data_o$next[3:0]$11433 $4\r2__data_o$next[3:0]$11432 + end + case + assign $1\r2__data_o$next[3:0]$11429 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\r2__data_o$next[3:0]$11434 4'0000 + case + assign $6\r2__data_o$next[3:0]$11434 $1\r2__data_o$next[3:0]$11429 + end + sync always + update \r2__data_o$next $0\r2__data_o$next[3:0]$11428 + end + attribute \src "libresoc.v:184029.3-184058.6" + process $proc$libresoc.v:184029$11435 + assign { } { } + assign { } { } + assign $0\wr_detect$10[0:0]$11436 $1\wr_detect$10[0:0]$11437 + attribute \src "libresoc.v:184030.5-184030.29" + switch \initial + attribute \src "libresoc.v:184030.9-184030.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r2__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$10[0:0]$11437 $4\wr_detect$10[0:0]$11440 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest12__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$10[0:0]$11438 1'1 + case + assign $2\wr_detect$10[0:0]$11438 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest22__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$10[0:0]$11439 1'1 + case + assign $3\wr_detect$10[0:0]$11439 $2\wr_detect$10[0:0]$11438 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$10[0:0]$11440 1'1 + case + assign $4\wr_detect$10[0:0]$11440 $3\wr_detect$10[0:0]$11439 + end + case + assign $1\wr_detect$10[0:0]$11437 1'0 + end + sync always + update \wr_detect$10 $0\wr_detect$10[0:0]$11436 + end + attribute \src "libresoc.v:184059.3-184098.6" + process $proc$libresoc.v:184059$11441 + assign { } { } + assign { } { } + assign { } { } + assign $0\r22__data_o$next[3:0]$11442 $6\r22__data_o$next[3:0]$11448 + attribute \src "libresoc.v:184060.5-184060.29" + switch \initial + attribute \src "libresoc.v:184060.9-184060.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r22__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\r22__data_o$next[3:0]$11443 $5\r22__data_o$next[3:0]$11447 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest12__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r22__data_o$next[3:0]$11444 \dest12__data_i + case + assign $2\r22__data_o$next[3:0]$11444 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest22__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\r22__data_o$next[3:0]$11445 \dest22__data_i + case + assign $3\r22__data_o$next[3:0]$11445 $2\r22__data_o$next[3:0]$11444 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\r22__data_o$next[3:0]$11446 \w2__data_i + case + assign $4\r22__data_o$next[3:0]$11446 $3\r22__data_o$next[3:0]$11445 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$12 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\r22__data_o$next[3:0]$11447 \reg + case + assign $5\r22__data_o$next[3:0]$11447 $4\r22__data_o$next[3:0]$11446 + end + case + assign $1\r22__data_o$next[3:0]$11443 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\r22__data_o$next[3:0]$11448 4'0000 + case + assign $6\r22__data_o$next[3:0]$11448 $1\r22__data_o$next[3:0]$11443 + end + sync always + update \r22__data_o$next $0\r22__data_o$next[3:0]$11442 + end + attribute \src "libresoc.v:184099.3-184128.6" + process $proc$libresoc.v:184099$11449 + assign { } { } + assign { } { } + assign $0\wr_detect$13[0:0]$11450 $1\wr_detect$13[0:0]$11451 + attribute \src "libresoc.v:184100.5-184100.29" + switch \initial + attribute \src "libresoc.v:184100.9-184100.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r22__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$13[0:0]$11451 $4\wr_detect$13[0:0]$11454 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest12__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$13[0:0]$11452 1'1 + case + assign $2\wr_detect$13[0:0]$11452 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest22__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$13[0:0]$11453 1'1 + case + assign $3\wr_detect$13[0:0]$11453 $2\wr_detect$13[0:0]$11452 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$13[0:0]$11454 1'1 + case + assign $4\wr_detect$13[0:0]$11454 $3\wr_detect$13[0:0]$11453 + end + case + assign $1\wr_detect$13[0:0]$11451 1'0 + end + sync always + update \wr_detect$13 $0\wr_detect$13[0:0]$11450 + end + connect \$9 $not$libresoc.v:183735$11373_Y + connect \$12 $not$libresoc.v:183736$11374_Y + connect \$1 $not$libresoc.v:183737$11375_Y + connect \$3 $not$libresoc.v:183738$11376_Y + connect \$6 $not$libresoc.v:183739$11377_Y +end +attribute \src "libresoc.v:184133.1-184578.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.xer.reg_2" +attribute \generator "nMigen" +module \reg_2$134 + attribute \src "libresoc.v:184134.7-184134.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:184463.3-184508.6" + wire width 2 $0\r2__data_o$next[1:0]$11514 + attribute \src "libresoc.v:184209.3-184210.37" + wire width 2 $0\r2__data_o[1:0] + attribute \src "libresoc.v:184545.3-184577.6" + wire width 2 $0\reg$next[1:0]$11530 + attribute \src "libresoc.v:184207.3-184208.25" + wire width 2 $0\reg[1:0] + attribute \src "libresoc.v:184217.3-184262.6" + wire width 2 $0\src12__data_o$next[1:0]$11472 + attribute \src "libresoc.v:184215.3-184216.43" + wire width 2 $0\src12__data_o[1:0] + attribute \src "libresoc.v:184299.3-184344.6" + wire width 2 $0\src22__data_o$next[1:0]$11482 + attribute \src "libresoc.v:184213.3-184214.43" + wire width 2 $0\src22__data_o[1:0] + attribute \src "libresoc.v:184381.3-184426.6" + wire width 2 $0\src32__data_o$next[1:0]$11498 + attribute \src "libresoc.v:184211.3-184212.43" + wire width 2 $0\src32__data_o[1:0] + attribute \src "libresoc.v:184509.3-184544.6" + wire $0\wr_detect$10[0:0]$11523 + attribute \src "libresoc.v:184345.3-184380.6" + wire $0\wr_detect$4[0:0]$11491 + attribute \src "libresoc.v:184427.3-184462.6" + wire $0\wr_detect$7[0:0]$11507 + attribute \src "libresoc.v:184263.3-184298.6" + wire $0\wr_detect[0:0] + attribute \src "libresoc.v:184463.3-184508.6" + wire width 2 $1\r2__data_o$next[1:0]$11515 + attribute \src "libresoc.v:184161.13-184161.30" + wire width 2 $1\r2__data_o[1:0] + attribute \src "libresoc.v:184545.3-184577.6" + wire width 2 $1\reg$next[1:0]$11531 + attribute \src "libresoc.v:184167.13-184167.25" + wire width 2 $1\reg[1:0] + attribute \src "libresoc.v:184217.3-184262.6" + wire width 2 $1\src12__data_o$next[1:0]$11473 + attribute \src "libresoc.v:184172.13-184172.33" + wire width 2 $1\src12__data_o[1:0] + attribute \src "libresoc.v:184299.3-184344.6" + wire width 2 $1\src22__data_o$next[1:0]$11483 + attribute \src "libresoc.v:184179.13-184179.33" + wire width 2 $1\src22__data_o[1:0] + attribute \src "libresoc.v:184381.3-184426.6" + wire width 2 $1\src32__data_o$next[1:0]$11499 + attribute \src "libresoc.v:184186.13-184186.33" + wire width 2 $1\src32__data_o[1:0] + attribute \src "libresoc.v:184509.3-184544.6" + wire $1\wr_detect$10[0:0]$11524 + attribute \src "libresoc.v:184345.3-184380.6" + wire $1\wr_detect$4[0:0]$11492 + attribute \src "libresoc.v:184427.3-184462.6" + wire $1\wr_detect$7[0:0]$11508 + attribute \src "libresoc.v:184263.3-184298.6" + wire $1\wr_detect[0:0] + attribute \src "libresoc.v:184463.3-184508.6" + wire width 2 $2\r2__data_o$next[1:0]$11516 + attribute \src "libresoc.v:184545.3-184577.6" + wire width 2 $2\reg$next[1:0]$11532 + attribute \src "libresoc.v:184217.3-184262.6" + wire width 2 $2\src12__data_o$next[1:0]$11474 + attribute \src "libresoc.v:184299.3-184344.6" + wire width 2 $2\src22__data_o$next[1:0]$11484 + attribute \src "libresoc.v:184381.3-184426.6" + wire width 2 $2\src32__data_o$next[1:0]$11500 + attribute \src "libresoc.v:184509.3-184544.6" + wire $2\wr_detect$10[0:0]$11525 + attribute \src "libresoc.v:184345.3-184380.6" + wire $2\wr_detect$4[0:0]$11493 + attribute \src "libresoc.v:184427.3-184462.6" + wire $2\wr_detect$7[0:0]$11509 + attribute \src "libresoc.v:184263.3-184298.6" + wire $2\wr_detect[0:0] + attribute \src "libresoc.v:184463.3-184508.6" + wire width 2 $3\r2__data_o$next[1:0]$11517 + attribute \src "libresoc.v:184545.3-184577.6" + wire width 2 $3\reg$next[1:0]$11533 + attribute \src "libresoc.v:184217.3-184262.6" + wire width 2 $3\src12__data_o$next[1:0]$11475 + attribute \src "libresoc.v:184299.3-184344.6" + wire width 2 $3\src22__data_o$next[1:0]$11485 + attribute \src "libresoc.v:184381.3-184426.6" + wire width 2 $3\src32__data_o$next[1:0]$11501 + attribute \src "libresoc.v:184509.3-184544.6" + wire $3\wr_detect$10[0:0]$11526 + attribute \src "libresoc.v:184345.3-184380.6" + wire $3\wr_detect$4[0:0]$11494 + attribute \src "libresoc.v:184427.3-184462.6" + wire $3\wr_detect$7[0:0]$11510 + attribute \src "libresoc.v:184263.3-184298.6" + wire $3\wr_detect[0:0] + attribute \src "libresoc.v:184463.3-184508.6" + wire width 2 $4\r2__data_o$next[1:0]$11518 + attribute \src "libresoc.v:184545.3-184577.6" + wire width 2 $4\reg$next[1:0]$11534 + attribute \src "libresoc.v:184217.3-184262.6" + wire width 2 $4\src12__data_o$next[1:0]$11476 + attribute \src "libresoc.v:184299.3-184344.6" + wire width 2 $4\src22__data_o$next[1:0]$11486 + attribute \src "libresoc.v:184381.3-184426.6" + wire width 2 $4\src32__data_o$next[1:0]$11502 + attribute \src "libresoc.v:184509.3-184544.6" + wire $4\wr_detect$10[0:0]$11527 + attribute \src "libresoc.v:184345.3-184380.6" + wire $4\wr_detect$4[0:0]$11495 + attribute \src "libresoc.v:184427.3-184462.6" + wire $4\wr_detect$7[0:0]$11511 + attribute \src "libresoc.v:184263.3-184298.6" + wire $4\wr_detect[0:0] + attribute \src "libresoc.v:184463.3-184508.6" + wire width 2 $5\r2__data_o$next[1:0]$11519 + attribute \src "libresoc.v:184545.3-184577.6" + wire width 2 $5\reg$next[1:0]$11535 + attribute \src "libresoc.v:184217.3-184262.6" + wire width 2 $5\src12__data_o$next[1:0]$11477 + attribute \src "libresoc.v:184299.3-184344.6" + wire width 2 $5\src22__data_o$next[1:0]$11487 + attribute \src "libresoc.v:184381.3-184426.6" + wire width 2 $5\src32__data_o$next[1:0]$11503 + attribute \src "libresoc.v:184509.3-184544.6" + wire $5\wr_detect$10[0:0]$11528 + attribute \src "libresoc.v:184345.3-184380.6" + wire $5\wr_detect$4[0:0]$11496 + attribute \src "libresoc.v:184427.3-184462.6" + wire $5\wr_detect$7[0:0]$11512 + attribute \src "libresoc.v:184263.3-184298.6" + wire $5\wr_detect[0:0] + attribute \src "libresoc.v:184463.3-184508.6" + wire width 2 $6\r2__data_o$next[1:0]$11520 + attribute \src "libresoc.v:184217.3-184262.6" + wire width 2 $6\src12__data_o$next[1:0]$11478 + attribute \src "libresoc.v:184299.3-184344.6" + wire width 2 $6\src22__data_o$next[1:0]$11488 + attribute \src "libresoc.v:184381.3-184426.6" + wire width 2 $6\src32__data_o$next[1:0]$11504 + attribute \src "libresoc.v:184463.3-184508.6" + wire width 2 $7\r2__data_o$next[1:0]$11521 + attribute \src "libresoc.v:184217.3-184262.6" + wire width 2 $7\src12__data_o$next[1:0]$11479 + attribute \src "libresoc.v:184299.3-184344.6" + wire width 2 $7\src22__data_o$next[1:0]$11489 + attribute \src "libresoc.v:184381.3-184426.6" + wire width 2 $7\src32__data_o$next[1:0]$11505 + attribute \src "libresoc.v:184203.17-184203.104" + wire $not$libresoc.v:184203$11462_Y + attribute \src "libresoc.v:184204.17-184204.100" + wire $not$libresoc.v:184204$11463_Y + attribute \src "libresoc.v:184205.17-184205.103" + wire $not$libresoc.v:184205$11464_Y + attribute \src "libresoc.v:184206.17-184206.103" + wire $not$libresoc.v:184206$11465_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 18 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 2 input 9 \dest12__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 8 \dest12__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 2 input 11 \dest22__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 10 \dest22__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 2 input 13 \dest32__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 12 \dest32__wen + attribute \src "libresoc.v:184134.7-184134.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 2 output 14 \r2__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 2 \r2__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 15 \r2__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 2 \reg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 2 \reg$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 2 output 3 \src12__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 2 \src12__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 2 \src12__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 2 output 5 \src22__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 2 \src22__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 4 \src22__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 2 output 7 \src32__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 2 \src32__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 6 \src32__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 2 input 16 \w2__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 17 \w2__wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:184203$11462 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$10 + connect \Y $not$libresoc.v:184203$11462_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:184204$11463 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect + connect \Y $not$libresoc.v:184204$11463_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:184205$11464 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$4 + connect \Y $not$libresoc.v:184205$11464_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:184206$11465 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$7 + connect \Y $not$libresoc.v:184206$11465_Y + end + attribute \src "libresoc.v:184134.7-184134.20" + process $proc$libresoc.v:184134$11536 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:184161.13-184161.30" + process $proc$libresoc.v:184161$11537 + assign { } { } + assign $1\r2__data_o[1:0] 2'00 + sync always + sync init + update \r2__data_o $1\r2__data_o[1:0] + end + attribute \src "libresoc.v:184167.13-184167.25" + process $proc$libresoc.v:184167$11538 + assign { } { } + assign $1\reg[1:0] 2'00 + sync always + sync init + update \reg $1\reg[1:0] + end + attribute \src "libresoc.v:184172.13-184172.33" + process $proc$libresoc.v:184172$11539 + assign { } { } + assign $1\src12__data_o[1:0] 2'00 + sync always + sync init + update \src12__data_o $1\src12__data_o[1:0] + end + attribute \src "libresoc.v:184179.13-184179.33" + process $proc$libresoc.v:184179$11540 + assign { } { } + assign $1\src22__data_o[1:0] 2'00 + sync always + sync init + update \src22__data_o $1\src22__data_o[1:0] + end + attribute \src "libresoc.v:184186.13-184186.33" + process $proc$libresoc.v:184186$11541 + assign { } { } + assign $1\src32__data_o[1:0] 2'00 + sync always + sync init + update \src32__data_o $1\src32__data_o[1:0] + end + attribute \src "libresoc.v:184207.3-184208.25" + process $proc$libresoc.v:184207$11466 + assign { } { } + assign $0\reg[1:0] \reg$next + sync posedge \coresync_clk + update \reg $0\reg[1:0] + end + attribute \src "libresoc.v:184209.3-184210.37" + process $proc$libresoc.v:184209$11467 + assign { } { } + assign $0\r2__data_o[1:0] \r2__data_o$next + sync posedge \coresync_clk + update \r2__data_o $0\r2__data_o[1:0] + end + attribute \src "libresoc.v:184211.3-184212.43" + process $proc$libresoc.v:184211$11468 + assign { } { } + assign $0\src32__data_o[1:0] \src32__data_o$next + sync posedge \coresync_clk + update \src32__data_o $0\src32__data_o[1:0] + end + attribute \src "libresoc.v:184213.3-184214.43" + process $proc$libresoc.v:184213$11469 + assign { } { } + assign $0\src22__data_o[1:0] \src22__data_o$next + sync posedge \coresync_clk + update \src22__data_o $0\src22__data_o[1:0] + end + attribute \src "libresoc.v:184215.3-184216.43" + process $proc$libresoc.v:184215$11470 + assign { } { } + assign $0\src12__data_o[1:0] \src12__data_o$next + sync posedge \coresync_clk + update \src12__data_o $0\src12__data_o[1:0] + end + attribute \src "libresoc.v:184217.3-184262.6" + process $proc$libresoc.v:184217$11471 + assign { } { } + assign { } { } + assign { } { } + assign $0\src12__data_o$next[1:0]$11472 $7\src12__data_o$next[1:0]$11479 + attribute \src "libresoc.v:184218.5-184218.29" + switch \initial + attribute \src "libresoc.v:184218.9-184218.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src12__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src12__data_o$next[1:0]$11473 $6\src12__data_o$next[1:0]$11478 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest12__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src12__data_o$next[1:0]$11474 \dest12__data_i + case + assign $2\src12__data_o$next[1:0]$11474 2'00 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest22__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src12__data_o$next[1:0]$11475 \dest22__data_i + case + assign $3\src12__data_o$next[1:0]$11475 $2\src12__data_o$next[1:0]$11474 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest32__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src12__data_o$next[1:0]$11476 \dest32__data_i + case + assign $4\src12__data_o$next[1:0]$11476 $3\src12__data_o$next[1:0]$11475 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src12__data_o$next[1:0]$11477 \w2__data_i + case + assign $5\src12__data_o$next[1:0]$11477 $4\src12__data_o$next[1:0]$11476 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src12__data_o$next[1:0]$11478 \reg + case + assign $6\src12__data_o$next[1:0]$11478 $5\src12__data_o$next[1:0]$11477 + end + case + assign $1\src12__data_o$next[1:0]$11473 2'00 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\src12__data_o$next[1:0]$11479 2'00 + case + assign $7\src12__data_o$next[1:0]$11479 $1\src12__data_o$next[1:0]$11473 + end + sync always + update \src12__data_o$next $0\src12__data_o$next[1:0]$11472 + end + attribute \src "libresoc.v:184263.3-184298.6" + process $proc$libresoc.v:184263$11480 + assign { } { } + assign { } { } + assign $0\wr_detect[0:0] $1\wr_detect[0:0] + attribute \src "libresoc.v:184264.5-184264.29" + switch \initial + attribute \src "libresoc.v:184264.9-184264.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src12__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect[0:0] $5\wr_detect[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest12__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect[0:0] 1'1 + case + assign $2\wr_detect[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest22__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect[0:0] 1'1 + case + assign $3\wr_detect[0:0] $2\wr_detect[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest32__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect[0:0] 1'1 + case + assign $4\wr_detect[0:0] $3\wr_detect[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\wr_detect[0:0] 1'1 + case + assign $5\wr_detect[0:0] $4\wr_detect[0:0] + end + case + assign $1\wr_detect[0:0] 1'0 + end + sync always + update \wr_detect $0\wr_detect[0:0] + end + attribute \src "libresoc.v:184299.3-184344.6" + process $proc$libresoc.v:184299$11481 + assign { } { } + assign { } { } + assign { } { } + assign $0\src22__data_o$next[1:0]$11482 $7\src22__data_o$next[1:0]$11489 + attribute \src "libresoc.v:184300.5-184300.29" + switch \initial + attribute \src "libresoc.v:184300.9-184300.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src22__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src22__data_o$next[1:0]$11483 $6\src22__data_o$next[1:0]$11488 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest12__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src22__data_o$next[1:0]$11484 \dest12__data_i + case + assign $2\src22__data_o$next[1:0]$11484 2'00 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest22__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src22__data_o$next[1:0]$11485 \dest22__data_i + case + assign $3\src22__data_o$next[1:0]$11485 $2\src22__data_o$next[1:0]$11484 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest32__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src22__data_o$next[1:0]$11486 \dest32__data_i + case + assign $4\src22__data_o$next[1:0]$11486 $3\src22__data_o$next[1:0]$11485 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src22__data_o$next[1:0]$11487 \w2__data_i + case + assign $5\src22__data_o$next[1:0]$11487 $4\src22__data_o$next[1:0]$11486 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src22__data_o$next[1:0]$11488 \reg + case + assign $6\src22__data_o$next[1:0]$11488 $5\src22__data_o$next[1:0]$11487 + end + case + assign $1\src22__data_o$next[1:0]$11483 2'00 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\src22__data_o$next[1:0]$11489 2'00 + case + assign $7\src22__data_o$next[1:0]$11489 $1\src22__data_o$next[1:0]$11483 + end + sync always + update \src22__data_o$next $0\src22__data_o$next[1:0]$11482 + end + attribute \src "libresoc.v:184345.3-184380.6" + process $proc$libresoc.v:184345$11490 + assign { } { } + assign { } { } + assign $0\wr_detect$4[0:0]$11491 $1\wr_detect$4[0:0]$11492 + attribute \src "libresoc.v:184346.5-184346.29" + switch \initial + attribute \src "libresoc.v:184346.9-184346.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src22__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$4[0:0]$11492 $5\wr_detect$4[0:0]$11496 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest12__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$4[0:0]$11493 1'1 + case + assign $2\wr_detect$4[0:0]$11493 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest22__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$4[0:0]$11494 1'1 + case + assign $3\wr_detect$4[0:0]$11494 $2\wr_detect$4[0:0]$11493 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest32__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$4[0:0]$11495 1'1 + case + assign $4\wr_detect$4[0:0]$11495 $3\wr_detect$4[0:0]$11494 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\wr_detect$4[0:0]$11496 1'1 + case + assign $5\wr_detect$4[0:0]$11496 $4\wr_detect$4[0:0]$11495 + end + case + assign $1\wr_detect$4[0:0]$11492 1'0 + end + sync always + update \wr_detect$4 $0\wr_detect$4[0:0]$11491 + end + attribute \src "libresoc.v:184381.3-184426.6" + process $proc$libresoc.v:184381$11497 + assign { } { } + assign { } { } + assign { } { } + assign $0\src32__data_o$next[1:0]$11498 $7\src32__data_o$next[1:0]$11505 + attribute \src "libresoc.v:184382.5-184382.29" + switch \initial + attribute \src "libresoc.v:184382.9-184382.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src32__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src32__data_o$next[1:0]$11499 $6\src32__data_o$next[1:0]$11504 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest12__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src32__data_o$next[1:0]$11500 \dest12__data_i + case + assign $2\src32__data_o$next[1:0]$11500 2'00 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest22__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src32__data_o$next[1:0]$11501 \dest22__data_i + case + assign $3\src32__data_o$next[1:0]$11501 $2\src32__data_o$next[1:0]$11500 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest32__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src32__data_o$next[1:0]$11502 \dest32__data_i + case + assign $4\src32__data_o$next[1:0]$11502 $3\src32__data_o$next[1:0]$11501 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src32__data_o$next[1:0]$11503 \w2__data_i + case + assign $5\src32__data_o$next[1:0]$11503 $4\src32__data_o$next[1:0]$11502 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$6 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src32__data_o$next[1:0]$11504 \reg + case + assign $6\src32__data_o$next[1:0]$11504 $5\src32__data_o$next[1:0]$11503 + end + case + assign $1\src32__data_o$next[1:0]$11499 2'00 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\src32__data_o$next[1:0]$11505 2'00 + case + assign $7\src32__data_o$next[1:0]$11505 $1\src32__data_o$next[1:0]$11499 + end + sync always + update \src32__data_o$next $0\src32__data_o$next[1:0]$11498 + end + attribute \src "libresoc.v:184427.3-184462.6" + process $proc$libresoc.v:184427$11506 + assign { } { } + assign { } { } + assign $0\wr_detect$7[0:0]$11507 $1\wr_detect$7[0:0]$11508 + attribute \src "libresoc.v:184428.5-184428.29" + switch \initial + attribute \src "libresoc.v:184428.9-184428.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src32__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$7[0:0]$11508 $5\wr_detect$7[0:0]$11512 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest12__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$7[0:0]$11509 1'1 + case + assign $2\wr_detect$7[0:0]$11509 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest22__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$7[0:0]$11510 1'1 + case + assign $3\wr_detect$7[0:0]$11510 $2\wr_detect$7[0:0]$11509 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest32__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$7[0:0]$11511 1'1 + case + assign $4\wr_detect$7[0:0]$11511 $3\wr_detect$7[0:0]$11510 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\wr_detect$7[0:0]$11512 1'1 + case + assign $5\wr_detect$7[0:0]$11512 $4\wr_detect$7[0:0]$11511 + end + case + assign $1\wr_detect$7[0:0]$11508 1'0 + end + sync always + update \wr_detect$7 $0\wr_detect$7[0:0]$11507 + end + attribute \src "libresoc.v:184463.3-184508.6" + process $proc$libresoc.v:184463$11513 + assign { } { } + assign { } { } + assign { } { } + assign $0\r2__data_o$next[1:0]$11514 $7\r2__data_o$next[1:0]$11521 + attribute \src "libresoc.v:184464.5-184464.29" + switch \initial + attribute \src "libresoc.v:184464.9-184464.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r2__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\r2__data_o$next[1:0]$11515 $6\r2__data_o$next[1:0]$11520 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest12__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r2__data_o$next[1:0]$11516 \dest12__data_i + case + assign $2\r2__data_o$next[1:0]$11516 2'00 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest22__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\r2__data_o$next[1:0]$11517 \dest22__data_i + case + assign $3\r2__data_o$next[1:0]$11517 $2\r2__data_o$next[1:0]$11516 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest32__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\r2__data_o$next[1:0]$11518 \dest32__data_i + case + assign $4\r2__data_o$next[1:0]$11518 $3\r2__data_o$next[1:0]$11517 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\r2__data_o$next[1:0]$11519 \w2__data_i + case + assign $5\r2__data_o$next[1:0]$11519 $4\r2__data_o$next[1:0]$11518 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$9 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\r2__data_o$next[1:0]$11520 \reg + case + assign $6\r2__data_o$next[1:0]$11520 $5\r2__data_o$next[1:0]$11519 + end + case + assign $1\r2__data_o$next[1:0]$11515 2'00 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\r2__data_o$next[1:0]$11521 2'00 + case + assign $7\r2__data_o$next[1:0]$11521 $1\r2__data_o$next[1:0]$11515 + end + sync always + update \r2__data_o$next $0\r2__data_o$next[1:0]$11514 + end + attribute \src "libresoc.v:184509.3-184544.6" + process $proc$libresoc.v:184509$11522 + assign { } { } + assign { } { } + assign $0\wr_detect$10[0:0]$11523 $1\wr_detect$10[0:0]$11524 + attribute \src "libresoc.v:184510.5-184510.29" + switch \initial + attribute \src "libresoc.v:184510.9-184510.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r2__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$10[0:0]$11524 $5\wr_detect$10[0:0]$11528 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest12__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$10[0:0]$11525 1'1 + case + assign $2\wr_detect$10[0:0]$11525 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest22__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$10[0:0]$11526 1'1 + case + assign $3\wr_detect$10[0:0]$11526 $2\wr_detect$10[0:0]$11525 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest32__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$10[0:0]$11527 1'1 + case + assign $4\wr_detect$10[0:0]$11527 $3\wr_detect$10[0:0]$11526 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\wr_detect$10[0:0]$11528 1'1 + case + assign $5\wr_detect$10[0:0]$11528 $4\wr_detect$10[0:0]$11527 + end + case + assign $1\wr_detect$10[0:0]$11524 1'0 + end + sync always + update \wr_detect$10 $0\wr_detect$10[0:0]$11523 + end + attribute \src "libresoc.v:184545.3-184577.6" + process $proc$libresoc.v:184545$11529 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\reg$next[1:0]$11530 $5\reg$next[1:0]$11535 + attribute \src "libresoc.v:184546.5-184546.29" + switch \initial + attribute \src "libresoc.v:184546.9-184546.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest12__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\reg$next[1:0]$11531 \dest12__data_i + case + assign $1\reg$next[1:0]$11531 \reg + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest22__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\reg$next[1:0]$11532 \dest22__data_i + case + assign $2\reg$next[1:0]$11532 $1\reg$next[1:0]$11531 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest32__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\reg$next[1:0]$11533 \dest32__data_i + case + assign $3\reg$next[1:0]$11533 $2\reg$next[1:0]$11532 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \w2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\reg$next[1:0]$11534 \w2__data_i + case + assign $4\reg$next[1:0]$11534 $3\reg$next[1:0]$11533 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\reg$next[1:0]$11535 2'00 + case + assign $5\reg$next[1:0]$11535 $4\reg$next[1:0]$11534 + end + sync always + update \reg$next $0\reg$next[1:0]$11530 + end + connect \$9 $not$libresoc.v:184203$11462_Y + connect \$1 $not$libresoc.v:184204$11463_Y + connect \$3 $not$libresoc.v:184205$11464_Y + connect \$6 $not$libresoc.v:184206$11465_Y +end +attribute \src "libresoc.v:184582.1-184931.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.state.reg_2" +attribute \generator "nMigen" +module \reg_2$137 + attribute \src "libresoc.v:184652.3-184697.6" + wire width 64 $0\cia2__data_o$next[63:0]$11550 + attribute \src "libresoc.v:184650.3-184651.41" + wire width 64 $0\cia2__data_o[63:0] + attribute \src "libresoc.v:184583.7-184583.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:184734.3-184779.6" + wire width 64 $0\msr2__data_o$next[63:0]$11560 + attribute \src "libresoc.v:184648.3-184649.41" + wire width 64 $0\msr2__data_o[63:0] + attribute \src "libresoc.v:184898.3-184930.6" + wire width 64 $0\reg$next[63:0]$11592 + attribute \src "libresoc.v:184644.3-184645.25" + wire width 64 $0\reg[63:0] + attribute \src "libresoc.v:184816.3-184861.6" + wire width 64 $0\sv2__data_o$next[63:0]$11576 + attribute \src "libresoc.v:184646.3-184647.39" + wire width 64 $0\sv2__data_o[63:0] + attribute \src "libresoc.v:184780.3-184815.6" + wire $0\wr_detect$4[0:0]$11569 + attribute \src "libresoc.v:184862.3-184897.6" + wire $0\wr_detect$7[0:0]$11585 + attribute \src "libresoc.v:184698.3-184733.6" + wire $0\wr_detect[0:0] + attribute \src "libresoc.v:184652.3-184697.6" + wire width 64 $1\cia2__data_o$next[63:0]$11551 + attribute \src "libresoc.v:184592.14-184592.49" + wire width 64 $1\cia2__data_o[63:0] + attribute \src "libresoc.v:184734.3-184779.6" + wire width 64 $1\msr2__data_o$next[63:0]$11561 + attribute \src "libresoc.v:184609.14-184609.49" + wire width 64 $1\msr2__data_o[63:0] + attribute \src "libresoc.v:184898.3-184930.6" + wire width 64 $1\reg$next[63:0]$11593 + attribute \src "libresoc.v:184621.14-184621.42" + wire width 64 $1\reg[63:0] + attribute \src "libresoc.v:184816.3-184861.6" + wire width 64 $1\sv2__data_o$next[63:0]$11577 + attribute \src "libresoc.v:184628.14-184628.48" + wire width 64 $1\sv2__data_o[63:0] + attribute \src "libresoc.v:184780.3-184815.6" + wire $1\wr_detect$4[0:0]$11570 + attribute \src "libresoc.v:184862.3-184897.6" + wire $1\wr_detect$7[0:0]$11586 + attribute \src "libresoc.v:184698.3-184733.6" + wire $1\wr_detect[0:0] + attribute \src "libresoc.v:184652.3-184697.6" + wire width 64 $2\cia2__data_o$next[63:0]$11552 + attribute \src "libresoc.v:184734.3-184779.6" + wire width 64 $2\msr2__data_o$next[63:0]$11562 + attribute \src "libresoc.v:184898.3-184930.6" + wire width 64 $2\reg$next[63:0]$11594 + attribute \src "libresoc.v:184816.3-184861.6" + wire width 64 $2\sv2__data_o$next[63:0]$11578 + attribute \src "libresoc.v:184780.3-184815.6" + wire $2\wr_detect$4[0:0]$11571 + attribute \src "libresoc.v:184862.3-184897.6" + wire $2\wr_detect$7[0:0]$11587 + attribute \src "libresoc.v:184698.3-184733.6" + wire $2\wr_detect[0:0] + attribute \src "libresoc.v:184652.3-184697.6" + wire width 64 $3\cia2__data_o$next[63:0]$11553 + attribute \src "libresoc.v:184734.3-184779.6" + wire width 64 $3\msr2__data_o$next[63:0]$11563 + attribute \src "libresoc.v:184898.3-184930.6" + wire width 64 $3\reg$next[63:0]$11595 + attribute \src "libresoc.v:184816.3-184861.6" + wire width 64 $3\sv2__data_o$next[63:0]$11579 + attribute \src "libresoc.v:184780.3-184815.6" + wire $3\wr_detect$4[0:0]$11572 + attribute \src "libresoc.v:184862.3-184897.6" + wire $3\wr_detect$7[0:0]$11588 + attribute \src "libresoc.v:184698.3-184733.6" + wire $3\wr_detect[0:0] + attribute \src "libresoc.v:184652.3-184697.6" + wire width 64 $4\cia2__data_o$next[63:0]$11554 + attribute \src "libresoc.v:184734.3-184779.6" + wire width 64 $4\msr2__data_o$next[63:0]$11564 + attribute \src "libresoc.v:184898.3-184930.6" + wire width 64 $4\reg$next[63:0]$11596 + attribute \src "libresoc.v:184816.3-184861.6" + wire width 64 $4\sv2__data_o$next[63:0]$11580 + attribute \src "libresoc.v:184780.3-184815.6" + wire $4\wr_detect$4[0:0]$11573 + attribute \src "libresoc.v:184862.3-184897.6" + wire $4\wr_detect$7[0:0]$11589 + attribute \src "libresoc.v:184698.3-184733.6" + wire $4\wr_detect[0:0] + attribute \src "libresoc.v:184652.3-184697.6" + wire width 64 $5\cia2__data_o$next[63:0]$11555 + attribute \src "libresoc.v:184734.3-184779.6" + wire width 64 $5\msr2__data_o$next[63:0]$11565 + attribute \src "libresoc.v:184898.3-184930.6" + wire width 64 $5\reg$next[63:0]$11597 + attribute \src "libresoc.v:184816.3-184861.6" + wire width 64 $5\sv2__data_o$next[63:0]$11581 + attribute \src "libresoc.v:184780.3-184815.6" + wire $5\wr_detect$4[0:0]$11574 + attribute \src "libresoc.v:184862.3-184897.6" + wire $5\wr_detect$7[0:0]$11590 + attribute \src "libresoc.v:184698.3-184733.6" + wire $5\wr_detect[0:0] + attribute \src "libresoc.v:184652.3-184697.6" + wire width 64 $6\cia2__data_o$next[63:0]$11556 + attribute \src "libresoc.v:184734.3-184779.6" + wire width 64 $6\msr2__data_o$next[63:0]$11566 + attribute \src "libresoc.v:184816.3-184861.6" + wire width 64 $6\sv2__data_o$next[63:0]$11582 + attribute \src "libresoc.v:184652.3-184697.6" + wire width 64 $7\cia2__data_o$next[63:0]$11557 + attribute \src "libresoc.v:184734.3-184779.6" + wire width 64 $7\msr2__data_o$next[63:0]$11567 + attribute \src "libresoc.v:184816.3-184861.6" + wire width 64 $7\sv2__data_o$next[63:0]$11583 + attribute \src "libresoc.v:184641.17-184641.100" + wire $not$libresoc.v:184641$11542_Y + attribute \src "libresoc.v:184642.17-184642.103" + wire $not$libresoc.v:184642$11543_Y + attribute \src "libresoc.v:184643.17-184643.103" + wire $not$libresoc.v:184643$11544_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 output 3 \cia2__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 \cia2__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 2 \cia2__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 16 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 input 15 \d_wr12__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 14 \d_wr12__wen + attribute \src "libresoc.v:184583.7-184583.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 input 11 \msr2__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 output 5 \msr2__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 \msr2__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 4 \msr2__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 10 \msr2__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 input 9 \nia2__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 8 \nia2__wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 64 \reg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 64 \reg$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 input 13 \sv2__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 output 7 \sv2__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 \sv2__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 6 \sv2__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 12 \sv2__wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:184641$11542 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect + connect \Y $not$libresoc.v:184641$11542_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:184642$11543 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$4 + connect \Y $not$libresoc.v:184642$11543_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:184643$11544 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$7 + connect \Y $not$libresoc.v:184643$11544_Y + end + attribute \src "libresoc.v:184583.7-184583.20" + process $proc$libresoc.v:184583$11598 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:184592.14-184592.49" + process $proc$libresoc.v:184592$11599 + assign { } { } + assign $1\cia2__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \cia2__data_o $1\cia2__data_o[63:0] + end + attribute \src "libresoc.v:184609.14-184609.49" + process $proc$libresoc.v:184609$11600 + assign { } { } + assign $1\msr2__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \msr2__data_o $1\msr2__data_o[63:0] + end + attribute \src "libresoc.v:184621.14-184621.42" + process $proc$libresoc.v:184621$11601 + assign { } { } + assign $1\reg[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \reg $1\reg[63:0] + end + attribute \src "libresoc.v:184628.14-184628.48" + process $proc$libresoc.v:184628$11602 + assign { } { } + assign $1\sv2__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \sv2__data_o $1\sv2__data_o[63:0] + end + attribute \src "libresoc.v:184644.3-184645.25" + process $proc$libresoc.v:184644$11545 + assign { } { } + assign $0\reg[63:0] \reg$next + sync posedge \coresync_clk + update \reg $0\reg[63:0] + end + attribute \src "libresoc.v:184646.3-184647.39" + process $proc$libresoc.v:184646$11546 + assign { } { } + assign $0\sv2__data_o[63:0] \sv2__data_o$next + sync posedge \coresync_clk + update \sv2__data_o $0\sv2__data_o[63:0] + end + attribute \src "libresoc.v:184648.3-184649.41" + process $proc$libresoc.v:184648$11547 + assign { } { } + assign $0\msr2__data_o[63:0] \msr2__data_o$next + sync posedge \coresync_clk + update \msr2__data_o $0\msr2__data_o[63:0] + end + attribute \src "libresoc.v:184650.3-184651.41" + process $proc$libresoc.v:184650$11548 + assign { } { } + assign $0\cia2__data_o[63:0] \cia2__data_o$next + sync posedge \coresync_clk + update \cia2__data_o $0\cia2__data_o[63:0] + end + attribute \src "libresoc.v:184652.3-184697.6" + process $proc$libresoc.v:184652$11549 + assign { } { } + assign { } { } + assign { } { } + assign $0\cia2__data_o$next[63:0]$11550 $7\cia2__data_o$next[63:0]$11557 + attribute \src "libresoc.v:184653.5-184653.29" + switch \initial + attribute \src "libresoc.v:184653.9-184653.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \cia2__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\cia2__data_o$next[63:0]$11551 $6\cia2__data_o$next[63:0]$11556 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \nia2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cia2__data_o$next[63:0]$11552 \nia2__data_i + case + assign $2\cia2__data_o$next[63:0]$11552 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \msr2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\cia2__data_o$next[63:0]$11553 \msr2__data_i + case + assign $3\cia2__data_o$next[63:0]$11553 $2\cia2__data_o$next[63:0]$11552 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \sv2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\cia2__data_o$next[63:0]$11554 \sv2__data_i + case + assign $4\cia2__data_o$next[63:0]$11554 $3\cia2__data_o$next[63:0]$11553 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \d_wr12__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\cia2__data_o$next[63:0]$11555 \d_wr12__data_i + case + assign $5\cia2__data_o$next[63:0]$11555 $4\cia2__data_o$next[63:0]$11554 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\cia2__data_o$next[63:0]$11556 \reg + case + assign $6\cia2__data_o$next[63:0]$11556 $5\cia2__data_o$next[63:0]$11555 + end + case + assign $1\cia2__data_o$next[63:0]$11551 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\cia2__data_o$next[63:0]$11557 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $7\cia2__data_o$next[63:0]$11557 $1\cia2__data_o$next[63:0]$11551 + end + sync always + update \cia2__data_o$next $0\cia2__data_o$next[63:0]$11550 + end + attribute \src "libresoc.v:184698.3-184733.6" + process $proc$libresoc.v:184698$11558 + assign { } { } + assign { } { } + assign $0\wr_detect[0:0] $1\wr_detect[0:0] + attribute \src "libresoc.v:184699.5-184699.29" + switch \initial + attribute \src "libresoc.v:184699.9-184699.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \cia2__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect[0:0] $5\wr_detect[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \nia2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect[0:0] 1'1 + case + assign $2\wr_detect[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \msr2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect[0:0] 1'1 + case + assign $3\wr_detect[0:0] $2\wr_detect[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \sv2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect[0:0] 1'1 + case + assign $4\wr_detect[0:0] $3\wr_detect[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \d_wr12__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\wr_detect[0:0] 1'1 + case + assign $5\wr_detect[0:0] $4\wr_detect[0:0] + end + case + assign $1\wr_detect[0:0] 1'0 + end + sync always + update \wr_detect $0\wr_detect[0:0] + end + attribute \src "libresoc.v:184734.3-184779.6" + process $proc$libresoc.v:184734$11559 + assign { } { } + assign { } { } + assign { } { } + assign $0\msr2__data_o$next[63:0]$11560 $7\msr2__data_o$next[63:0]$11567 + attribute \src "libresoc.v:184735.5-184735.29" + switch \initial + attribute \src "libresoc.v:184735.9-184735.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \msr2__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\msr2__data_o$next[63:0]$11561 $6\msr2__data_o$next[63:0]$11566 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \nia2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\msr2__data_o$next[63:0]$11562 \nia2__data_i + case + assign $2\msr2__data_o$next[63:0]$11562 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \msr2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\msr2__data_o$next[63:0]$11563 \msr2__data_i + case + assign $3\msr2__data_o$next[63:0]$11563 $2\msr2__data_o$next[63:0]$11562 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \sv2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\msr2__data_o$next[63:0]$11564 \sv2__data_i + case + assign $4\msr2__data_o$next[63:0]$11564 $3\msr2__data_o$next[63:0]$11563 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \d_wr12__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\msr2__data_o$next[63:0]$11565 \d_wr12__data_i + case + assign $5\msr2__data_o$next[63:0]$11565 $4\msr2__data_o$next[63:0]$11564 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\msr2__data_o$next[63:0]$11566 \reg + case + assign $6\msr2__data_o$next[63:0]$11566 $5\msr2__data_o$next[63:0]$11565 + end + case + assign $1\msr2__data_o$next[63:0]$11561 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\msr2__data_o$next[63:0]$11567 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $7\msr2__data_o$next[63:0]$11567 $1\msr2__data_o$next[63:0]$11561 + end + sync always + update \msr2__data_o$next $0\msr2__data_o$next[63:0]$11560 + end + attribute \src "libresoc.v:184780.3-184815.6" + process $proc$libresoc.v:184780$11568 + assign { } { } + assign { } { } + assign $0\wr_detect$4[0:0]$11569 $1\wr_detect$4[0:0]$11570 + attribute \src "libresoc.v:184781.5-184781.29" + switch \initial + attribute \src "libresoc.v:184781.9-184781.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \msr2__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$4[0:0]$11570 $5\wr_detect$4[0:0]$11574 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \nia2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$4[0:0]$11571 1'1 + case + assign $2\wr_detect$4[0:0]$11571 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \msr2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$4[0:0]$11572 1'1 + case + assign $3\wr_detect$4[0:0]$11572 $2\wr_detect$4[0:0]$11571 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \sv2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$4[0:0]$11573 1'1 + case + assign $4\wr_detect$4[0:0]$11573 $3\wr_detect$4[0:0]$11572 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \d_wr12__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\wr_detect$4[0:0]$11574 1'1 + case + assign $5\wr_detect$4[0:0]$11574 $4\wr_detect$4[0:0]$11573 + end + case + assign $1\wr_detect$4[0:0]$11570 1'0 + end + sync always + update \wr_detect$4 $0\wr_detect$4[0:0]$11569 + end + attribute \src "libresoc.v:184816.3-184861.6" + process $proc$libresoc.v:184816$11575 + assign { } { } + assign { } { } + assign { } { } + assign $0\sv2__data_o$next[63:0]$11576 $7\sv2__data_o$next[63:0]$11583 + attribute \src "libresoc.v:184817.5-184817.29" + switch \initial + attribute \src "libresoc.v:184817.9-184817.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \sv2__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\sv2__data_o$next[63:0]$11577 $6\sv2__data_o$next[63:0]$11582 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \nia2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\sv2__data_o$next[63:0]$11578 \nia2__data_i + case + assign $2\sv2__data_o$next[63:0]$11578 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \msr2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\sv2__data_o$next[63:0]$11579 \msr2__data_i + case + assign $3\sv2__data_o$next[63:0]$11579 $2\sv2__data_o$next[63:0]$11578 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \sv2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\sv2__data_o$next[63:0]$11580 \sv2__data_i + case + assign $4\sv2__data_o$next[63:0]$11580 $3\sv2__data_o$next[63:0]$11579 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \d_wr12__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\sv2__data_o$next[63:0]$11581 \d_wr12__data_i + case + assign $5\sv2__data_o$next[63:0]$11581 $4\sv2__data_o$next[63:0]$11580 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$6 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\sv2__data_o$next[63:0]$11582 \reg + case + assign $6\sv2__data_o$next[63:0]$11582 $5\sv2__data_o$next[63:0]$11581 + end + case + assign $1\sv2__data_o$next[63:0]$11577 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\sv2__data_o$next[63:0]$11583 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $7\sv2__data_o$next[63:0]$11583 $1\sv2__data_o$next[63:0]$11577 + end + sync always + update \sv2__data_o$next $0\sv2__data_o$next[63:0]$11576 + end + attribute \src "libresoc.v:184862.3-184897.6" + process $proc$libresoc.v:184862$11584 + assign { } { } + assign { } { } + assign $0\wr_detect$7[0:0]$11585 $1\wr_detect$7[0:0]$11586 + attribute \src "libresoc.v:184863.5-184863.29" + switch \initial + attribute \src "libresoc.v:184863.9-184863.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \sv2__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$7[0:0]$11586 $5\wr_detect$7[0:0]$11590 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \nia2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$7[0:0]$11587 1'1 + case + assign $2\wr_detect$7[0:0]$11587 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \msr2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$7[0:0]$11588 1'1 + case + assign $3\wr_detect$7[0:0]$11588 $2\wr_detect$7[0:0]$11587 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \sv2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$7[0:0]$11589 1'1 + case + assign $4\wr_detect$7[0:0]$11589 $3\wr_detect$7[0:0]$11588 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \d_wr12__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\wr_detect$7[0:0]$11590 1'1 + case + assign $5\wr_detect$7[0:0]$11590 $4\wr_detect$7[0:0]$11589 + end + case + assign $1\wr_detect$7[0:0]$11586 1'0 + end + sync always + update \wr_detect$7 $0\wr_detect$7[0:0]$11585 + end + attribute \src "libresoc.v:184898.3-184930.6" + process $proc$libresoc.v:184898$11591 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\reg$next[63:0]$11592 $5\reg$next[63:0]$11597 + attribute \src "libresoc.v:184899.5-184899.29" + switch \initial + attribute \src "libresoc.v:184899.9-184899.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \nia2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\reg$next[63:0]$11593 \nia2__data_i + case + assign $1\reg$next[63:0]$11593 \reg + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \msr2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\reg$next[63:0]$11594 \msr2__data_i + case + assign $2\reg$next[63:0]$11594 $1\reg$next[63:0]$11593 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \sv2__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\reg$next[63:0]$11595 \sv2__data_i + case + assign $3\reg$next[63:0]$11595 $2\reg$next[63:0]$11594 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \d_wr12__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\reg$next[63:0]$11596 \d_wr12__data_i + case + assign $4\reg$next[63:0]$11596 $3\reg$next[63:0]$11595 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\reg$next[63:0]$11597 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $5\reg$next[63:0]$11597 $4\reg$next[63:0]$11596 + end + sync always + update \reg$next $0\reg$next[63:0]$11592 + end + connect \$1 $not$libresoc.v:184641$11542_Y + connect \$3 $not$libresoc.v:184642$11543_Y + connect \$6 $not$libresoc.v:184643$11544_Y +end +attribute \src "libresoc.v:184935.1-185406.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.cr.reg_3" +attribute \generator "nMigen" +module \reg_3 + attribute \src "libresoc.v:184936.7-184936.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:185336.3-185375.6" + wire width 4 $0\r23__data_o$next[3:0]$11672 + attribute \src "libresoc.v:185019.3-185020.39" + wire width 4 $0\r23__data_o[3:0] + attribute \src "libresoc.v:185266.3-185305.6" + wire width 4 $0\r3__data_o$next[3:0]$11658 + attribute \src "libresoc.v:185021.3-185022.37" + wire width 4 $0\r3__data_o[3:0] + attribute \src "libresoc.v:185099.3-185125.6" + wire width 4 $0\reg$next[3:0]$11624 + attribute \src "libresoc.v:185017.3-185018.25" + wire width 4 $0\reg[3:0] + attribute \src "libresoc.v:185029.3-185068.6" + wire width 4 $0\src13__data_o$next[3:0]$11615 + attribute \src "libresoc.v:185027.3-185028.43" + wire width 4 $0\src13__data_o[3:0] + attribute \src "libresoc.v:185126.3-185165.6" + wire width 4 $0\src23__data_o$next[3:0]$11630 + attribute \src "libresoc.v:185025.3-185026.43" + wire width 4 $0\src23__data_o[3:0] + attribute \src "libresoc.v:185196.3-185235.6" + wire width 4 $0\src33__data_o$next[3:0]$11644 + attribute \src "libresoc.v:185023.3-185024.43" + wire width 4 $0\src33__data_o[3:0] + attribute \src "libresoc.v:185306.3-185335.6" + wire $0\wr_detect$10[0:0]$11666 + attribute \src "libresoc.v:185376.3-185405.6" + wire $0\wr_detect$13[0:0]$11680 + attribute \src "libresoc.v:185166.3-185195.6" + wire $0\wr_detect$4[0:0]$11638 + attribute \src "libresoc.v:185236.3-185265.6" + wire $0\wr_detect$7[0:0]$11652 + attribute \src "libresoc.v:185069.3-185098.6" + wire $0\wr_detect[0:0] + attribute \src "libresoc.v:185336.3-185375.6" + wire width 4 $1\r23__data_o$next[3:0]$11673 + attribute \src "libresoc.v:184961.13-184961.31" + wire width 4 $1\r23__data_o[3:0] + attribute \src "libresoc.v:185266.3-185305.6" + wire width 4 $1\r3__data_o$next[3:0]$11659 + attribute \src "libresoc.v:184968.13-184968.30" + wire width 4 $1\r3__data_o[3:0] + attribute \src "libresoc.v:185099.3-185125.6" + wire width 4 $1\reg$next[3:0]$11625 + attribute \src "libresoc.v:184974.13-184974.25" + wire width 4 $1\reg[3:0] + attribute \src "libresoc.v:185029.3-185068.6" + wire width 4 $1\src13__data_o$next[3:0]$11616 + attribute \src "libresoc.v:184979.13-184979.33" + wire width 4 $1\src13__data_o[3:0] + attribute \src "libresoc.v:185126.3-185165.6" + wire width 4 $1\src23__data_o$next[3:0]$11631 + attribute \src "libresoc.v:184986.13-184986.33" + wire width 4 $1\src23__data_o[3:0] + attribute \src "libresoc.v:185196.3-185235.6" + wire width 4 $1\src33__data_o$next[3:0]$11645 + attribute \src "libresoc.v:184993.13-184993.33" + wire width 4 $1\src33__data_o[3:0] + attribute \src "libresoc.v:185306.3-185335.6" + wire $1\wr_detect$10[0:0]$11667 + attribute \src "libresoc.v:185376.3-185405.6" + wire $1\wr_detect$13[0:0]$11681 + attribute \src "libresoc.v:185166.3-185195.6" + wire $1\wr_detect$4[0:0]$11639 + attribute \src "libresoc.v:185236.3-185265.6" + wire $1\wr_detect$7[0:0]$11653 + attribute \src "libresoc.v:185069.3-185098.6" + wire $1\wr_detect[0:0] + attribute \src "libresoc.v:185336.3-185375.6" + wire width 4 $2\r23__data_o$next[3:0]$11674 + attribute \src "libresoc.v:185266.3-185305.6" + wire width 4 $2\r3__data_o$next[3:0]$11660 + attribute \src "libresoc.v:185099.3-185125.6" + wire width 4 $2\reg$next[3:0]$11626 + attribute \src "libresoc.v:185029.3-185068.6" + wire width 4 $2\src13__data_o$next[3:0]$11617 + attribute \src "libresoc.v:185126.3-185165.6" + wire width 4 $2\src23__data_o$next[3:0]$11632 + attribute \src "libresoc.v:185196.3-185235.6" + wire width 4 $2\src33__data_o$next[3:0]$11646 + attribute \src "libresoc.v:185306.3-185335.6" + wire $2\wr_detect$10[0:0]$11668 + attribute \src "libresoc.v:185376.3-185405.6" + wire $2\wr_detect$13[0:0]$11682 + attribute \src "libresoc.v:185166.3-185195.6" + wire $2\wr_detect$4[0:0]$11640 + attribute \src "libresoc.v:185236.3-185265.6" + wire $2\wr_detect$7[0:0]$11654 + attribute \src "libresoc.v:185069.3-185098.6" + wire $2\wr_detect[0:0] + attribute \src "libresoc.v:185336.3-185375.6" + wire width 4 $3\r23__data_o$next[3:0]$11675 + attribute \src "libresoc.v:185266.3-185305.6" + wire width 4 $3\r3__data_o$next[3:0]$11661 + attribute \src "libresoc.v:185099.3-185125.6" + wire width 4 $3\reg$next[3:0]$11627 + attribute \src "libresoc.v:185029.3-185068.6" + wire width 4 $3\src13__data_o$next[3:0]$11618 + attribute \src "libresoc.v:185126.3-185165.6" + wire width 4 $3\src23__data_o$next[3:0]$11633 + attribute \src "libresoc.v:185196.3-185235.6" + wire width 4 $3\src33__data_o$next[3:0]$11647 + attribute \src "libresoc.v:185306.3-185335.6" + wire $3\wr_detect$10[0:0]$11669 + attribute \src "libresoc.v:185376.3-185405.6" + wire $3\wr_detect$13[0:0]$11683 + attribute \src "libresoc.v:185166.3-185195.6" + wire $3\wr_detect$4[0:0]$11641 + attribute \src "libresoc.v:185236.3-185265.6" + wire $3\wr_detect$7[0:0]$11655 + attribute \src "libresoc.v:185069.3-185098.6" + wire $3\wr_detect[0:0] + attribute \src "libresoc.v:185336.3-185375.6" + wire width 4 $4\r23__data_o$next[3:0]$11676 + attribute \src "libresoc.v:185266.3-185305.6" + wire width 4 $4\r3__data_o$next[3:0]$11662 + attribute \src "libresoc.v:185099.3-185125.6" + wire width 4 $4\reg$next[3:0]$11628 + attribute \src "libresoc.v:185029.3-185068.6" + wire width 4 $4\src13__data_o$next[3:0]$11619 + attribute \src "libresoc.v:185126.3-185165.6" + wire width 4 $4\src23__data_o$next[3:0]$11634 + attribute \src "libresoc.v:185196.3-185235.6" + wire width 4 $4\src33__data_o$next[3:0]$11648 + attribute \src "libresoc.v:185306.3-185335.6" + wire $4\wr_detect$10[0:0]$11670 + attribute \src "libresoc.v:185376.3-185405.6" + wire $4\wr_detect$13[0:0]$11684 + attribute \src "libresoc.v:185166.3-185195.6" + wire $4\wr_detect$4[0:0]$11642 + attribute \src "libresoc.v:185236.3-185265.6" + wire $4\wr_detect$7[0:0]$11656 + attribute \src "libresoc.v:185069.3-185098.6" + wire $4\wr_detect[0:0] + attribute \src "libresoc.v:185336.3-185375.6" + wire width 4 $5\r23__data_o$next[3:0]$11677 + attribute \src "libresoc.v:185266.3-185305.6" + wire width 4 $5\r3__data_o$next[3:0]$11663 + attribute \src "libresoc.v:185029.3-185068.6" + wire width 4 $5\src13__data_o$next[3:0]$11620 + attribute \src "libresoc.v:185126.3-185165.6" + wire width 4 $5\src23__data_o$next[3:0]$11635 + attribute \src "libresoc.v:185196.3-185235.6" + wire width 4 $5\src33__data_o$next[3:0]$11649 + attribute \src "libresoc.v:185336.3-185375.6" + wire width 4 $6\r23__data_o$next[3:0]$11678 + attribute \src "libresoc.v:185266.3-185305.6" + wire width 4 $6\r3__data_o$next[3:0]$11664 + attribute \src "libresoc.v:185029.3-185068.6" + wire width 4 $6\src13__data_o$next[3:0]$11621 + attribute \src "libresoc.v:185126.3-185165.6" + wire width 4 $6\src23__data_o$next[3:0]$11636 + attribute \src "libresoc.v:185196.3-185235.6" + wire width 4 $6\src33__data_o$next[3:0]$11650 + attribute \src "libresoc.v:185012.17-185012.104" + wire $not$libresoc.v:185012$11603_Y + attribute \src "libresoc.v:185013.18-185013.105" + wire $not$libresoc.v:185013$11604_Y + attribute \src "libresoc.v:185014.17-185014.100" + wire $not$libresoc.v:185014$11605_Y + attribute \src "libresoc.v:185015.17-185015.103" + wire $not$libresoc.v:185015$11606_Y + attribute \src "libresoc.v:185016.17-185016.103" + wire $not$libresoc.v:185016$11607_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 18 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 input 9 \dest13__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 8 \dest13__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 input 11 \dest23__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 10 \dest23__wen + attribute \src "libresoc.v:184936.7-184936.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 output 14 \r23__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 \r23__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 15 \r23__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 output 12 \r3__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 \r3__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 13 \r3__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 4 \reg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 4 \reg$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 output 3 \src13__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 \src13__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 2 \src13__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 output 5 \src23__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 \src23__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 4 \src23__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 output 7 \src33__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 \src33__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 6 \src33__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 input 16 \w3__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 17 \w3__wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:185012$11603 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$10 + connect \Y $not$libresoc.v:185012$11603_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:185013$11604 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$13 + connect \Y $not$libresoc.v:185013$11604_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:185014$11605 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect + connect \Y $not$libresoc.v:185014$11605_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:185015$11606 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$4 + connect \Y $not$libresoc.v:185015$11606_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:185016$11607 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$7 + connect \Y $not$libresoc.v:185016$11607_Y + end + attribute \src "libresoc.v:184936.7-184936.20" + process $proc$libresoc.v:184936$11685 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:184961.13-184961.31" + process $proc$libresoc.v:184961$11686 + assign { } { } + assign $1\r23__data_o[3:0] 4'0000 + sync always + sync init + update \r23__data_o $1\r23__data_o[3:0] + end + attribute \src "libresoc.v:184968.13-184968.30" + process $proc$libresoc.v:184968$11687 + assign { } { } + assign $1\r3__data_o[3:0] 4'0000 + sync always + sync init + update \r3__data_o $1\r3__data_o[3:0] + end + attribute \src "libresoc.v:184974.13-184974.25" + process $proc$libresoc.v:184974$11688 + assign { } { } + assign $1\reg[3:0] 4'0000 + sync always + sync init + update \reg $1\reg[3:0] + end + attribute \src "libresoc.v:184979.13-184979.33" + process $proc$libresoc.v:184979$11689 + assign { } { } + assign $1\src13__data_o[3:0] 4'0000 + sync always + sync init + update \src13__data_o $1\src13__data_o[3:0] + end + attribute \src "libresoc.v:184986.13-184986.33" + process $proc$libresoc.v:184986$11690 + assign { } { } + assign $1\src23__data_o[3:0] 4'0000 + sync always + sync init + update \src23__data_o $1\src23__data_o[3:0] + end + attribute \src "libresoc.v:184993.13-184993.33" + process $proc$libresoc.v:184993$11691 + assign { } { } + assign $1\src33__data_o[3:0] 4'0000 + sync always + sync init + update \src33__data_o $1\src33__data_o[3:0] + end + attribute \src "libresoc.v:185017.3-185018.25" + process $proc$libresoc.v:185017$11608 + assign { } { } + assign $0\reg[3:0] \reg$next + sync posedge \coresync_clk + update \reg $0\reg[3:0] + end + attribute \src "libresoc.v:185019.3-185020.39" + process $proc$libresoc.v:185019$11609 + assign { } { } + assign $0\r23__data_o[3:0] \r23__data_o$next + sync posedge \coresync_clk + update \r23__data_o $0\r23__data_o[3:0] + end + attribute \src "libresoc.v:185021.3-185022.37" + process $proc$libresoc.v:185021$11610 + assign { } { } + assign $0\r3__data_o[3:0] \r3__data_o$next + sync posedge \coresync_clk + update \r3__data_o $0\r3__data_o[3:0] + end + attribute \src "libresoc.v:185023.3-185024.43" + process $proc$libresoc.v:185023$11611 + assign { } { } + assign $0\src33__data_o[3:0] \src33__data_o$next + sync posedge \coresync_clk + update \src33__data_o $0\src33__data_o[3:0] + end + attribute \src "libresoc.v:185025.3-185026.43" + process $proc$libresoc.v:185025$11612 + assign { } { } + assign $0\src23__data_o[3:0] \src23__data_o$next + sync posedge \coresync_clk + update \src23__data_o $0\src23__data_o[3:0] + end + attribute \src "libresoc.v:185027.3-185028.43" + process $proc$libresoc.v:185027$11613 + assign { } { } + assign $0\src13__data_o[3:0] \src13__data_o$next + sync posedge \coresync_clk + update \src13__data_o $0\src13__data_o[3:0] + end + attribute \src "libresoc.v:185029.3-185068.6" + process $proc$libresoc.v:185029$11614 + assign { } { } + assign { } { } + assign { } { } + assign $0\src13__data_o$next[3:0]$11615 $6\src13__data_o$next[3:0]$11621 + attribute \src "libresoc.v:185030.5-185030.29" + switch \initial + attribute \src "libresoc.v:185030.9-185030.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src13__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src13__data_o$next[3:0]$11616 $5\src13__data_o$next[3:0]$11620 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest13__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src13__data_o$next[3:0]$11617 \dest13__data_i + case + assign $2\src13__data_o$next[3:0]$11617 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest23__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src13__data_o$next[3:0]$11618 \dest23__data_i + case + assign $3\src13__data_o$next[3:0]$11618 $2\src13__data_o$next[3:0]$11617 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w3__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src13__data_o$next[3:0]$11619 \w3__data_i + case + assign $4\src13__data_o$next[3:0]$11619 $3\src13__data_o$next[3:0]$11618 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src13__data_o$next[3:0]$11620 \reg + case + assign $5\src13__data_o$next[3:0]$11620 $4\src13__data_o$next[3:0]$11619 + end + case + assign $1\src13__data_o$next[3:0]$11616 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src13__data_o$next[3:0]$11621 4'0000 + case + assign $6\src13__data_o$next[3:0]$11621 $1\src13__data_o$next[3:0]$11616 + end + sync always + update \src13__data_o$next $0\src13__data_o$next[3:0]$11615 + end + attribute \src "libresoc.v:185069.3-185098.6" + process $proc$libresoc.v:185069$11622 + assign { } { } + assign { } { } + assign $0\wr_detect[0:0] $1\wr_detect[0:0] + attribute \src "libresoc.v:185070.5-185070.29" + switch \initial + attribute \src "libresoc.v:185070.9-185070.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src13__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect[0:0] $4\wr_detect[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest13__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect[0:0] 1'1 + case + assign $2\wr_detect[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest23__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect[0:0] 1'1 + case + assign $3\wr_detect[0:0] $2\wr_detect[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w3__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect[0:0] 1'1 + case + assign $4\wr_detect[0:0] $3\wr_detect[0:0] + end + case + assign $1\wr_detect[0:0] 1'0 + end + sync always + update \wr_detect $0\wr_detect[0:0] + end + attribute \src "libresoc.v:185099.3-185125.6" + process $proc$libresoc.v:185099$11623 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\reg$next[3:0]$11624 $4\reg$next[3:0]$11628 + attribute \src "libresoc.v:185100.5-185100.29" + switch \initial + attribute \src "libresoc.v:185100.9-185100.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest13__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\reg$next[3:0]$11625 \dest13__data_i + case + assign $1\reg$next[3:0]$11625 \reg + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest23__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\reg$next[3:0]$11626 \dest23__data_i + case + assign $2\reg$next[3:0]$11626 $1\reg$next[3:0]$11625 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \w3__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\reg$next[3:0]$11627 \w3__data_i + case + assign $3\reg$next[3:0]$11627 $2\reg$next[3:0]$11626 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\reg$next[3:0]$11628 4'0000 + case + assign $4\reg$next[3:0]$11628 $3\reg$next[3:0]$11627 + end + sync always + update \reg$next $0\reg$next[3:0]$11624 + end + attribute \src "libresoc.v:185126.3-185165.6" + process $proc$libresoc.v:185126$11629 + assign { } { } + assign { } { } + assign { } { } + assign $0\src23__data_o$next[3:0]$11630 $6\src23__data_o$next[3:0]$11636 + attribute \src "libresoc.v:185127.5-185127.29" + switch \initial + attribute \src "libresoc.v:185127.9-185127.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src23__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src23__data_o$next[3:0]$11631 $5\src23__data_o$next[3:0]$11635 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest13__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src23__data_o$next[3:0]$11632 \dest13__data_i + case + assign $2\src23__data_o$next[3:0]$11632 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest23__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src23__data_o$next[3:0]$11633 \dest23__data_i + case + assign $3\src23__data_o$next[3:0]$11633 $2\src23__data_o$next[3:0]$11632 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w3__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src23__data_o$next[3:0]$11634 \w3__data_i + case + assign $4\src23__data_o$next[3:0]$11634 $3\src23__data_o$next[3:0]$11633 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src23__data_o$next[3:0]$11635 \reg + case + assign $5\src23__data_o$next[3:0]$11635 $4\src23__data_o$next[3:0]$11634 + end + case + assign $1\src23__data_o$next[3:0]$11631 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src23__data_o$next[3:0]$11636 4'0000 + case + assign $6\src23__data_o$next[3:0]$11636 $1\src23__data_o$next[3:0]$11631 + end + sync always + update \src23__data_o$next $0\src23__data_o$next[3:0]$11630 + end + attribute \src "libresoc.v:185166.3-185195.6" + process $proc$libresoc.v:185166$11637 + assign { } { } + assign { } { } + assign $0\wr_detect$4[0:0]$11638 $1\wr_detect$4[0:0]$11639 + attribute \src "libresoc.v:185167.5-185167.29" + switch \initial + attribute \src "libresoc.v:185167.9-185167.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src23__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$4[0:0]$11639 $4\wr_detect$4[0:0]$11642 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest13__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$4[0:0]$11640 1'1 + case + assign $2\wr_detect$4[0:0]$11640 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest23__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$4[0:0]$11641 1'1 + case + assign $3\wr_detect$4[0:0]$11641 $2\wr_detect$4[0:0]$11640 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w3__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$4[0:0]$11642 1'1 + case + assign $4\wr_detect$4[0:0]$11642 $3\wr_detect$4[0:0]$11641 + end + case + assign $1\wr_detect$4[0:0]$11639 1'0 + end + sync always + update \wr_detect$4 $0\wr_detect$4[0:0]$11638 + end + attribute \src "libresoc.v:185196.3-185235.6" + process $proc$libresoc.v:185196$11643 + assign { } { } + assign { } { } + assign { } { } + assign $0\src33__data_o$next[3:0]$11644 $6\src33__data_o$next[3:0]$11650 + attribute \src "libresoc.v:185197.5-185197.29" + switch \initial + attribute \src "libresoc.v:185197.9-185197.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src33__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src33__data_o$next[3:0]$11645 $5\src33__data_o$next[3:0]$11649 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest13__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src33__data_o$next[3:0]$11646 \dest13__data_i + case + assign $2\src33__data_o$next[3:0]$11646 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest23__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src33__data_o$next[3:0]$11647 \dest23__data_i + case + assign $3\src33__data_o$next[3:0]$11647 $2\src33__data_o$next[3:0]$11646 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w3__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src33__data_o$next[3:0]$11648 \w3__data_i + case + assign $4\src33__data_o$next[3:0]$11648 $3\src33__data_o$next[3:0]$11647 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$6 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src33__data_o$next[3:0]$11649 \reg + case + assign $5\src33__data_o$next[3:0]$11649 $4\src33__data_o$next[3:0]$11648 + end + case + assign $1\src33__data_o$next[3:0]$11645 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src33__data_o$next[3:0]$11650 4'0000 + case + assign $6\src33__data_o$next[3:0]$11650 $1\src33__data_o$next[3:0]$11645 + end + sync always + update \src33__data_o$next $0\src33__data_o$next[3:0]$11644 + end + attribute \src "libresoc.v:185236.3-185265.6" + process $proc$libresoc.v:185236$11651 + assign { } { } + assign { } { } + assign $0\wr_detect$7[0:0]$11652 $1\wr_detect$7[0:0]$11653 + attribute \src "libresoc.v:185237.5-185237.29" + switch \initial + attribute \src "libresoc.v:185237.9-185237.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src33__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$7[0:0]$11653 $4\wr_detect$7[0:0]$11656 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest13__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$7[0:0]$11654 1'1 + case + assign $2\wr_detect$7[0:0]$11654 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest23__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$7[0:0]$11655 1'1 + case + assign $3\wr_detect$7[0:0]$11655 $2\wr_detect$7[0:0]$11654 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w3__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$7[0:0]$11656 1'1 + case + assign $4\wr_detect$7[0:0]$11656 $3\wr_detect$7[0:0]$11655 + end + case + assign $1\wr_detect$7[0:0]$11653 1'0 + end + sync always + update \wr_detect$7 $0\wr_detect$7[0:0]$11652 + end + attribute \src "libresoc.v:185266.3-185305.6" + process $proc$libresoc.v:185266$11657 + assign { } { } + assign { } { } + assign { } { } + assign $0\r3__data_o$next[3:0]$11658 $6\r3__data_o$next[3:0]$11664 + attribute \src "libresoc.v:185267.5-185267.29" + switch \initial + attribute \src "libresoc.v:185267.9-185267.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r3__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\r3__data_o$next[3:0]$11659 $5\r3__data_o$next[3:0]$11663 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest13__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r3__data_o$next[3:0]$11660 \dest13__data_i + case + assign $2\r3__data_o$next[3:0]$11660 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest23__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\r3__data_o$next[3:0]$11661 \dest23__data_i + case + assign $3\r3__data_o$next[3:0]$11661 $2\r3__data_o$next[3:0]$11660 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w3__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\r3__data_o$next[3:0]$11662 \w3__data_i + case + assign $4\r3__data_o$next[3:0]$11662 $3\r3__data_o$next[3:0]$11661 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$9 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\r3__data_o$next[3:0]$11663 \reg + case + assign $5\r3__data_o$next[3:0]$11663 $4\r3__data_o$next[3:0]$11662 + end + case + assign $1\r3__data_o$next[3:0]$11659 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\r3__data_o$next[3:0]$11664 4'0000 + case + assign $6\r3__data_o$next[3:0]$11664 $1\r3__data_o$next[3:0]$11659 + end + sync always + update \r3__data_o$next $0\r3__data_o$next[3:0]$11658 + end + attribute \src "libresoc.v:185306.3-185335.6" + process $proc$libresoc.v:185306$11665 + assign { } { } + assign { } { } + assign $0\wr_detect$10[0:0]$11666 $1\wr_detect$10[0:0]$11667 + attribute \src "libresoc.v:185307.5-185307.29" + switch \initial + attribute \src "libresoc.v:185307.9-185307.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r3__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$10[0:0]$11667 $4\wr_detect$10[0:0]$11670 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest13__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$10[0:0]$11668 1'1 + case + assign $2\wr_detect$10[0:0]$11668 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest23__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$10[0:0]$11669 1'1 + case + assign $3\wr_detect$10[0:0]$11669 $2\wr_detect$10[0:0]$11668 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w3__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$10[0:0]$11670 1'1 + case + assign $4\wr_detect$10[0:0]$11670 $3\wr_detect$10[0:0]$11669 + end + case + assign $1\wr_detect$10[0:0]$11667 1'0 + end + sync always + update \wr_detect$10 $0\wr_detect$10[0:0]$11666 + end + attribute \src "libresoc.v:185336.3-185375.6" + process $proc$libresoc.v:185336$11671 + assign { } { } + assign { } { } + assign { } { } + assign $0\r23__data_o$next[3:0]$11672 $6\r23__data_o$next[3:0]$11678 + attribute \src "libresoc.v:185337.5-185337.29" + switch \initial + attribute \src "libresoc.v:185337.9-185337.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r23__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\r23__data_o$next[3:0]$11673 $5\r23__data_o$next[3:0]$11677 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest13__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r23__data_o$next[3:0]$11674 \dest13__data_i + case + assign $2\r23__data_o$next[3:0]$11674 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest23__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\r23__data_o$next[3:0]$11675 \dest23__data_i + case + assign $3\r23__data_o$next[3:0]$11675 $2\r23__data_o$next[3:0]$11674 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w3__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\r23__data_o$next[3:0]$11676 \w3__data_i + case + assign $4\r23__data_o$next[3:0]$11676 $3\r23__data_o$next[3:0]$11675 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$12 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\r23__data_o$next[3:0]$11677 \reg + case + assign $5\r23__data_o$next[3:0]$11677 $4\r23__data_o$next[3:0]$11676 + end + case + assign $1\r23__data_o$next[3:0]$11673 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\r23__data_o$next[3:0]$11678 4'0000 + case + assign $6\r23__data_o$next[3:0]$11678 $1\r23__data_o$next[3:0]$11673 + end + sync always + update \r23__data_o$next $0\r23__data_o$next[3:0]$11672 + end + attribute \src "libresoc.v:185376.3-185405.6" + process $proc$libresoc.v:185376$11679 + assign { } { } + assign { } { } + assign $0\wr_detect$13[0:0]$11680 $1\wr_detect$13[0:0]$11681 + attribute \src "libresoc.v:185377.5-185377.29" + switch \initial + attribute \src "libresoc.v:185377.9-185377.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r23__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$13[0:0]$11681 $4\wr_detect$13[0:0]$11684 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest13__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$13[0:0]$11682 1'1 + case + assign $2\wr_detect$13[0:0]$11682 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest23__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$13[0:0]$11683 1'1 + case + assign $3\wr_detect$13[0:0]$11683 $2\wr_detect$13[0:0]$11682 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w3__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$13[0:0]$11684 1'1 + case + assign $4\wr_detect$13[0:0]$11684 $3\wr_detect$13[0:0]$11683 + end + case + assign $1\wr_detect$13[0:0]$11681 1'0 + end + sync always + update \wr_detect$13 $0\wr_detect$13[0:0]$11680 + end + connect \$9 $not$libresoc.v:185012$11603_Y + connect \$12 $not$libresoc.v:185013$11604_Y + connect \$1 $not$libresoc.v:185014$11605_Y + connect \$3 $not$libresoc.v:185015$11606_Y + connect \$6 $not$libresoc.v:185016$11607_Y +end +attribute \src "libresoc.v:185410.1-185881.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.cr.reg_4" +attribute \generator "nMigen" +module \reg_4 + attribute \src "libresoc.v:185411.7-185411.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:185811.3-185850.6" + wire width 4 $0\r24__data_o$next[3:0]$11761 + attribute \src "libresoc.v:185494.3-185495.39" + wire width 4 $0\r24__data_o[3:0] + attribute \src "libresoc.v:185741.3-185780.6" + wire width 4 $0\r4__data_o$next[3:0]$11747 + attribute \src "libresoc.v:185496.3-185497.37" + wire width 4 $0\r4__data_o[3:0] + attribute \src "libresoc.v:185574.3-185600.6" + wire width 4 $0\reg$next[3:0]$11713 + attribute \src "libresoc.v:185492.3-185493.25" + wire width 4 $0\reg[3:0] + attribute \src "libresoc.v:185504.3-185543.6" + wire width 4 $0\src14__data_o$next[3:0]$11704 + attribute \src "libresoc.v:185502.3-185503.43" + wire width 4 $0\src14__data_o[3:0] + attribute \src "libresoc.v:185601.3-185640.6" + wire width 4 $0\src24__data_o$next[3:0]$11719 + attribute \src "libresoc.v:185500.3-185501.43" + wire width 4 $0\src24__data_o[3:0] + attribute \src "libresoc.v:185671.3-185710.6" + wire width 4 $0\src34__data_o$next[3:0]$11733 + attribute \src "libresoc.v:185498.3-185499.43" + wire width 4 $0\src34__data_o[3:0] + attribute \src "libresoc.v:185781.3-185810.6" + wire $0\wr_detect$10[0:0]$11755 + attribute \src "libresoc.v:185851.3-185880.6" + wire $0\wr_detect$13[0:0]$11769 + attribute \src "libresoc.v:185641.3-185670.6" + wire $0\wr_detect$4[0:0]$11727 + attribute \src "libresoc.v:185711.3-185740.6" + wire $0\wr_detect$7[0:0]$11741 + attribute \src "libresoc.v:185544.3-185573.6" + wire $0\wr_detect[0:0] + attribute \src "libresoc.v:185811.3-185850.6" + wire width 4 $1\r24__data_o$next[3:0]$11762 + attribute \src "libresoc.v:185436.13-185436.31" + wire width 4 $1\r24__data_o[3:0] + attribute \src "libresoc.v:185741.3-185780.6" + wire width 4 $1\r4__data_o$next[3:0]$11748 + attribute \src "libresoc.v:185443.13-185443.30" + wire width 4 $1\r4__data_o[3:0] + attribute \src "libresoc.v:185574.3-185600.6" + wire width 4 $1\reg$next[3:0]$11714 + attribute \src "libresoc.v:185449.13-185449.25" + wire width 4 $1\reg[3:0] + attribute \src "libresoc.v:185504.3-185543.6" + wire width 4 $1\src14__data_o$next[3:0]$11705 + attribute \src "libresoc.v:185454.13-185454.33" + wire width 4 $1\src14__data_o[3:0] + attribute \src "libresoc.v:185601.3-185640.6" + wire width 4 $1\src24__data_o$next[3:0]$11720 + attribute \src "libresoc.v:185461.13-185461.33" + wire width 4 $1\src24__data_o[3:0] + attribute \src "libresoc.v:185671.3-185710.6" + wire width 4 $1\src34__data_o$next[3:0]$11734 + attribute \src "libresoc.v:185468.13-185468.33" + wire width 4 $1\src34__data_o[3:0] + attribute \src "libresoc.v:185781.3-185810.6" + wire $1\wr_detect$10[0:0]$11756 + attribute \src "libresoc.v:185851.3-185880.6" + wire $1\wr_detect$13[0:0]$11770 + attribute \src "libresoc.v:185641.3-185670.6" + wire $1\wr_detect$4[0:0]$11728 + attribute \src "libresoc.v:185711.3-185740.6" + wire $1\wr_detect$7[0:0]$11742 + attribute \src "libresoc.v:185544.3-185573.6" + wire $1\wr_detect[0:0] + attribute \src "libresoc.v:185811.3-185850.6" + wire width 4 $2\r24__data_o$next[3:0]$11763 + attribute \src "libresoc.v:185741.3-185780.6" + wire width 4 $2\r4__data_o$next[3:0]$11749 + attribute \src "libresoc.v:185574.3-185600.6" + wire width 4 $2\reg$next[3:0]$11715 + attribute \src "libresoc.v:185504.3-185543.6" + wire width 4 $2\src14__data_o$next[3:0]$11706 + attribute \src "libresoc.v:185601.3-185640.6" + wire width 4 $2\src24__data_o$next[3:0]$11721 + attribute \src "libresoc.v:185671.3-185710.6" + wire width 4 $2\src34__data_o$next[3:0]$11735 + attribute \src "libresoc.v:185781.3-185810.6" + wire $2\wr_detect$10[0:0]$11757 + attribute \src "libresoc.v:185851.3-185880.6" + wire $2\wr_detect$13[0:0]$11771 + attribute \src "libresoc.v:185641.3-185670.6" + wire $2\wr_detect$4[0:0]$11729 + attribute \src "libresoc.v:185711.3-185740.6" + wire $2\wr_detect$7[0:0]$11743 + attribute \src "libresoc.v:185544.3-185573.6" + wire $2\wr_detect[0:0] + attribute \src "libresoc.v:185811.3-185850.6" + wire width 4 $3\r24__data_o$next[3:0]$11764 + attribute \src "libresoc.v:185741.3-185780.6" + wire width 4 $3\r4__data_o$next[3:0]$11750 + attribute \src "libresoc.v:185574.3-185600.6" + wire width 4 $3\reg$next[3:0]$11716 + attribute \src "libresoc.v:185504.3-185543.6" + wire width 4 $3\src14__data_o$next[3:0]$11707 + attribute \src "libresoc.v:185601.3-185640.6" + wire width 4 $3\src24__data_o$next[3:0]$11722 + attribute \src "libresoc.v:185671.3-185710.6" + wire width 4 $3\src34__data_o$next[3:0]$11736 + attribute \src "libresoc.v:185781.3-185810.6" + wire $3\wr_detect$10[0:0]$11758 + attribute \src "libresoc.v:185851.3-185880.6" + wire $3\wr_detect$13[0:0]$11772 + attribute \src "libresoc.v:185641.3-185670.6" + wire $3\wr_detect$4[0:0]$11730 + attribute \src "libresoc.v:185711.3-185740.6" + wire $3\wr_detect$7[0:0]$11744 + attribute \src "libresoc.v:185544.3-185573.6" + wire $3\wr_detect[0:0] + attribute \src "libresoc.v:185811.3-185850.6" + wire width 4 $4\r24__data_o$next[3:0]$11765 + attribute \src "libresoc.v:185741.3-185780.6" + wire width 4 $4\r4__data_o$next[3:0]$11751 + attribute \src "libresoc.v:185574.3-185600.6" + wire width 4 $4\reg$next[3:0]$11717 + attribute \src "libresoc.v:185504.3-185543.6" + wire width 4 $4\src14__data_o$next[3:0]$11708 + attribute \src "libresoc.v:185601.3-185640.6" + wire width 4 $4\src24__data_o$next[3:0]$11723 + attribute \src "libresoc.v:185671.3-185710.6" + wire width 4 $4\src34__data_o$next[3:0]$11737 + attribute \src "libresoc.v:185781.3-185810.6" + wire $4\wr_detect$10[0:0]$11759 + attribute \src "libresoc.v:185851.3-185880.6" + wire $4\wr_detect$13[0:0]$11773 + attribute \src "libresoc.v:185641.3-185670.6" + wire $4\wr_detect$4[0:0]$11731 + attribute \src "libresoc.v:185711.3-185740.6" + wire $4\wr_detect$7[0:0]$11745 + attribute \src "libresoc.v:185544.3-185573.6" + wire $4\wr_detect[0:0] + attribute \src "libresoc.v:185811.3-185850.6" + wire width 4 $5\r24__data_o$next[3:0]$11766 + attribute \src "libresoc.v:185741.3-185780.6" + wire width 4 $5\r4__data_o$next[3:0]$11752 + attribute \src "libresoc.v:185504.3-185543.6" + wire width 4 $5\src14__data_o$next[3:0]$11709 + attribute \src "libresoc.v:185601.3-185640.6" + wire width 4 $5\src24__data_o$next[3:0]$11724 + attribute \src "libresoc.v:185671.3-185710.6" + wire width 4 $5\src34__data_o$next[3:0]$11738 + attribute \src "libresoc.v:185811.3-185850.6" + wire width 4 $6\r24__data_o$next[3:0]$11767 + attribute \src "libresoc.v:185741.3-185780.6" + wire width 4 $6\r4__data_o$next[3:0]$11753 + attribute \src "libresoc.v:185504.3-185543.6" + wire width 4 $6\src14__data_o$next[3:0]$11710 + attribute \src "libresoc.v:185601.3-185640.6" + wire width 4 $6\src24__data_o$next[3:0]$11725 + attribute \src "libresoc.v:185671.3-185710.6" + wire width 4 $6\src34__data_o$next[3:0]$11739 + attribute \src "libresoc.v:185487.17-185487.104" + wire $not$libresoc.v:185487$11692_Y + attribute \src "libresoc.v:185488.18-185488.105" + wire $not$libresoc.v:185488$11693_Y + attribute \src "libresoc.v:185489.17-185489.100" + wire $not$libresoc.v:185489$11694_Y + attribute \src "libresoc.v:185490.17-185490.103" + wire $not$libresoc.v:185490$11695_Y + attribute \src "libresoc.v:185491.17-185491.103" + wire $not$libresoc.v:185491$11696_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 18 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 input 9 \dest14__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 8 \dest14__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 input 11 \dest24__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 10 \dest24__wen + attribute \src "libresoc.v:185411.7-185411.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 output 14 \r24__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 \r24__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 15 \r24__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 output 12 \r4__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 \r4__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 13 \r4__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 4 \reg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 4 \reg$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 output 3 \src14__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 \src14__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 2 \src14__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 output 5 \src24__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 \src24__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 4 \src24__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 output 7 \src34__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 \src34__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 6 \src34__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 input 16 \w4__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 17 \w4__wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:185487$11692 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$10 + connect \Y $not$libresoc.v:185487$11692_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:185488$11693 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$13 + connect \Y $not$libresoc.v:185488$11693_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:185489$11694 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect + connect \Y $not$libresoc.v:185489$11694_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:185490$11695 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$4 + connect \Y $not$libresoc.v:185490$11695_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:185491$11696 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$7 + connect \Y $not$libresoc.v:185491$11696_Y + end + attribute \src "libresoc.v:185411.7-185411.20" + process $proc$libresoc.v:185411$11774 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:185436.13-185436.31" + process $proc$libresoc.v:185436$11775 + assign { } { } + assign $1\r24__data_o[3:0] 4'0000 + sync always + sync init + update \r24__data_o $1\r24__data_o[3:0] + end + attribute \src "libresoc.v:185443.13-185443.30" + process $proc$libresoc.v:185443$11776 + assign { } { } + assign $1\r4__data_o[3:0] 4'0000 + sync always + sync init + update \r4__data_o $1\r4__data_o[3:0] + end + attribute \src "libresoc.v:185449.13-185449.25" + process $proc$libresoc.v:185449$11777 + assign { } { } + assign $1\reg[3:0] 4'0000 + sync always + sync init + update \reg $1\reg[3:0] + end + attribute \src "libresoc.v:185454.13-185454.33" + process $proc$libresoc.v:185454$11778 + assign { } { } + assign $1\src14__data_o[3:0] 4'0000 + sync always + sync init + update \src14__data_o $1\src14__data_o[3:0] + end + attribute \src "libresoc.v:185461.13-185461.33" + process $proc$libresoc.v:185461$11779 + assign { } { } + assign $1\src24__data_o[3:0] 4'0000 + sync always + sync init + update \src24__data_o $1\src24__data_o[3:0] + end + attribute \src "libresoc.v:185468.13-185468.33" + process $proc$libresoc.v:185468$11780 + assign { } { } + assign $1\src34__data_o[3:0] 4'0000 + sync always + sync init + update \src34__data_o $1\src34__data_o[3:0] + end + attribute \src "libresoc.v:185492.3-185493.25" + process $proc$libresoc.v:185492$11697 + assign { } { } + assign $0\reg[3:0] \reg$next + sync posedge \coresync_clk + update \reg $0\reg[3:0] + end + attribute \src "libresoc.v:185494.3-185495.39" + process $proc$libresoc.v:185494$11698 + assign { } { } + assign $0\r24__data_o[3:0] \r24__data_o$next + sync posedge \coresync_clk + update \r24__data_o $0\r24__data_o[3:0] + end + attribute \src "libresoc.v:185496.3-185497.37" + process $proc$libresoc.v:185496$11699 + assign { } { } + assign $0\r4__data_o[3:0] \r4__data_o$next + sync posedge \coresync_clk + update \r4__data_o $0\r4__data_o[3:0] + end + attribute \src "libresoc.v:185498.3-185499.43" + process $proc$libresoc.v:185498$11700 + assign { } { } + assign $0\src34__data_o[3:0] \src34__data_o$next + sync posedge \coresync_clk + update \src34__data_o $0\src34__data_o[3:0] + end + attribute \src "libresoc.v:185500.3-185501.43" + process $proc$libresoc.v:185500$11701 + assign { } { } + assign $0\src24__data_o[3:0] \src24__data_o$next + sync posedge \coresync_clk + update \src24__data_o $0\src24__data_o[3:0] + end + attribute \src "libresoc.v:185502.3-185503.43" + process $proc$libresoc.v:185502$11702 + assign { } { } + assign $0\src14__data_o[3:0] \src14__data_o$next + sync posedge \coresync_clk + update \src14__data_o $0\src14__data_o[3:0] + end + attribute \src "libresoc.v:185504.3-185543.6" + process $proc$libresoc.v:185504$11703 + assign { } { } + assign { } { } + assign { } { } + assign $0\src14__data_o$next[3:0]$11704 $6\src14__data_o$next[3:0]$11710 + attribute \src "libresoc.v:185505.5-185505.29" + switch \initial + attribute \src "libresoc.v:185505.9-185505.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src14__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src14__data_o$next[3:0]$11705 $5\src14__data_o$next[3:0]$11709 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest14__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src14__data_o$next[3:0]$11706 \dest14__data_i + case + assign $2\src14__data_o$next[3:0]$11706 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest24__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src14__data_o$next[3:0]$11707 \dest24__data_i + case + assign $3\src14__data_o$next[3:0]$11707 $2\src14__data_o$next[3:0]$11706 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w4__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src14__data_o$next[3:0]$11708 \w4__data_i + case + assign $4\src14__data_o$next[3:0]$11708 $3\src14__data_o$next[3:0]$11707 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src14__data_o$next[3:0]$11709 \reg + case + assign $5\src14__data_o$next[3:0]$11709 $4\src14__data_o$next[3:0]$11708 + end + case + assign $1\src14__data_o$next[3:0]$11705 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src14__data_o$next[3:0]$11710 4'0000 + case + assign $6\src14__data_o$next[3:0]$11710 $1\src14__data_o$next[3:0]$11705 + end + sync always + update \src14__data_o$next $0\src14__data_o$next[3:0]$11704 + end + attribute \src "libresoc.v:185544.3-185573.6" + process $proc$libresoc.v:185544$11711 + assign { } { } + assign { } { } + assign $0\wr_detect[0:0] $1\wr_detect[0:0] + attribute \src "libresoc.v:185545.5-185545.29" + switch \initial + attribute \src "libresoc.v:185545.9-185545.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src14__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect[0:0] $4\wr_detect[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest14__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect[0:0] 1'1 + case + assign $2\wr_detect[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest24__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect[0:0] 1'1 + case + assign $3\wr_detect[0:0] $2\wr_detect[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w4__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect[0:0] 1'1 + case + assign $4\wr_detect[0:0] $3\wr_detect[0:0] + end + case + assign $1\wr_detect[0:0] 1'0 + end + sync always + update \wr_detect $0\wr_detect[0:0] + end + attribute \src "libresoc.v:185574.3-185600.6" + process $proc$libresoc.v:185574$11712 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\reg$next[3:0]$11713 $4\reg$next[3:0]$11717 + attribute \src "libresoc.v:185575.5-185575.29" + switch \initial + attribute \src "libresoc.v:185575.9-185575.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest14__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\reg$next[3:0]$11714 \dest14__data_i + case + assign $1\reg$next[3:0]$11714 \reg + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest24__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\reg$next[3:0]$11715 \dest24__data_i + case + assign $2\reg$next[3:0]$11715 $1\reg$next[3:0]$11714 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \w4__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\reg$next[3:0]$11716 \w4__data_i + case + assign $3\reg$next[3:0]$11716 $2\reg$next[3:0]$11715 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\reg$next[3:0]$11717 4'0000 + case + assign $4\reg$next[3:0]$11717 $3\reg$next[3:0]$11716 + end + sync always + update \reg$next $0\reg$next[3:0]$11713 + end + attribute \src "libresoc.v:185601.3-185640.6" + process $proc$libresoc.v:185601$11718 + assign { } { } + assign { } { } + assign { } { } + assign $0\src24__data_o$next[3:0]$11719 $6\src24__data_o$next[3:0]$11725 + attribute \src "libresoc.v:185602.5-185602.29" + switch \initial + attribute \src "libresoc.v:185602.9-185602.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src24__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src24__data_o$next[3:0]$11720 $5\src24__data_o$next[3:0]$11724 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest14__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src24__data_o$next[3:0]$11721 \dest14__data_i + case + assign $2\src24__data_o$next[3:0]$11721 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest24__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src24__data_o$next[3:0]$11722 \dest24__data_i + case + assign $3\src24__data_o$next[3:0]$11722 $2\src24__data_o$next[3:0]$11721 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w4__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src24__data_o$next[3:0]$11723 \w4__data_i + case + assign $4\src24__data_o$next[3:0]$11723 $3\src24__data_o$next[3:0]$11722 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src24__data_o$next[3:0]$11724 \reg + case + assign $5\src24__data_o$next[3:0]$11724 $4\src24__data_o$next[3:0]$11723 + end + case + assign $1\src24__data_o$next[3:0]$11720 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src24__data_o$next[3:0]$11725 4'0000 + case + assign $6\src24__data_o$next[3:0]$11725 $1\src24__data_o$next[3:0]$11720 + end + sync always + update \src24__data_o$next $0\src24__data_o$next[3:0]$11719 + end + attribute \src "libresoc.v:185641.3-185670.6" + process $proc$libresoc.v:185641$11726 + assign { } { } + assign { } { } + assign $0\wr_detect$4[0:0]$11727 $1\wr_detect$4[0:0]$11728 + attribute \src "libresoc.v:185642.5-185642.29" + switch \initial + attribute \src "libresoc.v:185642.9-185642.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src24__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$4[0:0]$11728 $4\wr_detect$4[0:0]$11731 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest14__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$4[0:0]$11729 1'1 + case + assign $2\wr_detect$4[0:0]$11729 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest24__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$4[0:0]$11730 1'1 + case + assign $3\wr_detect$4[0:0]$11730 $2\wr_detect$4[0:0]$11729 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w4__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$4[0:0]$11731 1'1 + case + assign $4\wr_detect$4[0:0]$11731 $3\wr_detect$4[0:0]$11730 + end + case + assign $1\wr_detect$4[0:0]$11728 1'0 + end + sync always + update \wr_detect$4 $0\wr_detect$4[0:0]$11727 + end + attribute \src "libresoc.v:185671.3-185710.6" + process $proc$libresoc.v:185671$11732 + assign { } { } + assign { } { } + assign { } { } + assign $0\src34__data_o$next[3:0]$11733 $6\src34__data_o$next[3:0]$11739 + attribute \src "libresoc.v:185672.5-185672.29" + switch \initial + attribute \src "libresoc.v:185672.9-185672.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src34__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src34__data_o$next[3:0]$11734 $5\src34__data_o$next[3:0]$11738 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest14__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src34__data_o$next[3:0]$11735 \dest14__data_i + case + assign $2\src34__data_o$next[3:0]$11735 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest24__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src34__data_o$next[3:0]$11736 \dest24__data_i + case + assign $3\src34__data_o$next[3:0]$11736 $2\src34__data_o$next[3:0]$11735 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w4__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src34__data_o$next[3:0]$11737 \w4__data_i + case + assign $4\src34__data_o$next[3:0]$11737 $3\src34__data_o$next[3:0]$11736 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$6 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src34__data_o$next[3:0]$11738 \reg + case + assign $5\src34__data_o$next[3:0]$11738 $4\src34__data_o$next[3:0]$11737 + end + case + assign $1\src34__data_o$next[3:0]$11734 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src34__data_o$next[3:0]$11739 4'0000 + case + assign $6\src34__data_o$next[3:0]$11739 $1\src34__data_o$next[3:0]$11734 + end + sync always + update \src34__data_o$next $0\src34__data_o$next[3:0]$11733 + end + attribute \src "libresoc.v:185711.3-185740.6" + process $proc$libresoc.v:185711$11740 + assign { } { } + assign { } { } + assign $0\wr_detect$7[0:0]$11741 $1\wr_detect$7[0:0]$11742 + attribute \src "libresoc.v:185712.5-185712.29" + switch \initial + attribute \src "libresoc.v:185712.9-185712.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src34__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$7[0:0]$11742 $4\wr_detect$7[0:0]$11745 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest14__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$7[0:0]$11743 1'1 + case + assign $2\wr_detect$7[0:0]$11743 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest24__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$7[0:0]$11744 1'1 + case + assign $3\wr_detect$7[0:0]$11744 $2\wr_detect$7[0:0]$11743 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w4__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$7[0:0]$11745 1'1 + case + assign $4\wr_detect$7[0:0]$11745 $3\wr_detect$7[0:0]$11744 + end + case + assign $1\wr_detect$7[0:0]$11742 1'0 + end + sync always + update \wr_detect$7 $0\wr_detect$7[0:0]$11741 + end + attribute \src "libresoc.v:185741.3-185780.6" + process $proc$libresoc.v:185741$11746 + assign { } { } + assign { } { } + assign { } { } + assign $0\r4__data_o$next[3:0]$11747 $6\r4__data_o$next[3:0]$11753 + attribute \src "libresoc.v:185742.5-185742.29" + switch \initial + attribute \src "libresoc.v:185742.9-185742.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r4__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\r4__data_o$next[3:0]$11748 $5\r4__data_o$next[3:0]$11752 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest14__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r4__data_o$next[3:0]$11749 \dest14__data_i + case + assign $2\r4__data_o$next[3:0]$11749 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest24__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\r4__data_o$next[3:0]$11750 \dest24__data_i + case + assign $3\r4__data_o$next[3:0]$11750 $2\r4__data_o$next[3:0]$11749 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w4__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\r4__data_o$next[3:0]$11751 \w4__data_i + case + assign $4\r4__data_o$next[3:0]$11751 $3\r4__data_o$next[3:0]$11750 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$9 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\r4__data_o$next[3:0]$11752 \reg + case + assign $5\r4__data_o$next[3:0]$11752 $4\r4__data_o$next[3:0]$11751 + end + case + assign $1\r4__data_o$next[3:0]$11748 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\r4__data_o$next[3:0]$11753 4'0000 + case + assign $6\r4__data_o$next[3:0]$11753 $1\r4__data_o$next[3:0]$11748 + end + sync always + update \r4__data_o$next $0\r4__data_o$next[3:0]$11747 + end + attribute \src "libresoc.v:185781.3-185810.6" + process $proc$libresoc.v:185781$11754 + assign { } { } + assign { } { } + assign $0\wr_detect$10[0:0]$11755 $1\wr_detect$10[0:0]$11756 + attribute \src "libresoc.v:185782.5-185782.29" + switch \initial + attribute \src "libresoc.v:185782.9-185782.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r4__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$10[0:0]$11756 $4\wr_detect$10[0:0]$11759 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest14__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$10[0:0]$11757 1'1 + case + assign $2\wr_detect$10[0:0]$11757 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest24__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$10[0:0]$11758 1'1 + case + assign $3\wr_detect$10[0:0]$11758 $2\wr_detect$10[0:0]$11757 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w4__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$10[0:0]$11759 1'1 + case + assign $4\wr_detect$10[0:0]$11759 $3\wr_detect$10[0:0]$11758 + end + case + assign $1\wr_detect$10[0:0]$11756 1'0 + end + sync always + update \wr_detect$10 $0\wr_detect$10[0:0]$11755 + end + attribute \src "libresoc.v:185811.3-185850.6" + process $proc$libresoc.v:185811$11760 + assign { } { } + assign { } { } + assign { } { } + assign $0\r24__data_o$next[3:0]$11761 $6\r24__data_o$next[3:0]$11767 + attribute \src "libresoc.v:185812.5-185812.29" + switch \initial + attribute \src "libresoc.v:185812.9-185812.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r24__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\r24__data_o$next[3:0]$11762 $5\r24__data_o$next[3:0]$11766 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest14__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r24__data_o$next[3:0]$11763 \dest14__data_i + case + assign $2\r24__data_o$next[3:0]$11763 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest24__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\r24__data_o$next[3:0]$11764 \dest24__data_i + case + assign $3\r24__data_o$next[3:0]$11764 $2\r24__data_o$next[3:0]$11763 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w4__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\r24__data_o$next[3:0]$11765 \w4__data_i + case + assign $4\r24__data_o$next[3:0]$11765 $3\r24__data_o$next[3:0]$11764 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$12 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\r24__data_o$next[3:0]$11766 \reg + case + assign $5\r24__data_o$next[3:0]$11766 $4\r24__data_o$next[3:0]$11765 + end + case + assign $1\r24__data_o$next[3:0]$11762 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\r24__data_o$next[3:0]$11767 4'0000 + case + assign $6\r24__data_o$next[3:0]$11767 $1\r24__data_o$next[3:0]$11762 + end + sync always + update \r24__data_o$next $0\r24__data_o$next[3:0]$11761 + end + attribute \src "libresoc.v:185851.3-185880.6" + process $proc$libresoc.v:185851$11768 + assign { } { } + assign { } { } + assign $0\wr_detect$13[0:0]$11769 $1\wr_detect$13[0:0]$11770 + attribute \src "libresoc.v:185852.5-185852.29" + switch \initial + attribute \src "libresoc.v:185852.9-185852.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r24__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$13[0:0]$11770 $4\wr_detect$13[0:0]$11773 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest14__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$13[0:0]$11771 1'1 + case + assign $2\wr_detect$13[0:0]$11771 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest24__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$13[0:0]$11772 1'1 + case + assign $3\wr_detect$13[0:0]$11772 $2\wr_detect$13[0:0]$11771 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w4__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$13[0:0]$11773 1'1 + case + assign $4\wr_detect$13[0:0]$11773 $3\wr_detect$13[0:0]$11772 + end + case + assign $1\wr_detect$13[0:0]$11770 1'0 + end + sync always + update \wr_detect$13 $0\wr_detect$13[0:0]$11769 + end + connect \$9 $not$libresoc.v:185487$11692_Y + connect \$12 $not$libresoc.v:185488$11693_Y + connect \$1 $not$libresoc.v:185489$11694_Y + connect \$3 $not$libresoc.v:185490$11695_Y + connect \$6 $not$libresoc.v:185491$11696_Y +end +attribute \src "libresoc.v:185885.1-186356.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.cr.reg_5" +attribute \generator "nMigen" +module \reg_5 + attribute \src "libresoc.v:185886.7-185886.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:186286.3-186325.6" + wire width 4 $0\r25__data_o$next[3:0]$11850 + attribute \src "libresoc.v:185969.3-185970.39" + wire width 4 $0\r25__data_o[3:0] + attribute \src "libresoc.v:186216.3-186255.6" + wire width 4 $0\r5__data_o$next[3:0]$11836 + attribute \src "libresoc.v:185971.3-185972.37" + wire width 4 $0\r5__data_o[3:0] + attribute \src "libresoc.v:186049.3-186075.6" + wire width 4 $0\reg$next[3:0]$11802 + attribute \src "libresoc.v:185967.3-185968.25" + wire width 4 $0\reg[3:0] + attribute \src "libresoc.v:185979.3-186018.6" + wire width 4 $0\src15__data_o$next[3:0]$11793 + attribute \src "libresoc.v:185977.3-185978.43" + wire width 4 $0\src15__data_o[3:0] + attribute \src "libresoc.v:186076.3-186115.6" + wire width 4 $0\src25__data_o$next[3:0]$11808 + attribute \src "libresoc.v:185975.3-185976.43" + wire width 4 $0\src25__data_o[3:0] + attribute \src "libresoc.v:186146.3-186185.6" + wire width 4 $0\src35__data_o$next[3:0]$11822 + attribute \src "libresoc.v:185973.3-185974.43" + wire width 4 $0\src35__data_o[3:0] + attribute \src "libresoc.v:186256.3-186285.6" + wire $0\wr_detect$10[0:0]$11844 + attribute \src "libresoc.v:186326.3-186355.6" + wire $0\wr_detect$13[0:0]$11858 + attribute \src "libresoc.v:186116.3-186145.6" + wire $0\wr_detect$4[0:0]$11816 + attribute \src "libresoc.v:186186.3-186215.6" + wire $0\wr_detect$7[0:0]$11830 + attribute \src "libresoc.v:186019.3-186048.6" + wire $0\wr_detect[0:0] + attribute \src "libresoc.v:186286.3-186325.6" + wire width 4 $1\r25__data_o$next[3:0]$11851 + attribute \src "libresoc.v:185911.13-185911.31" + wire width 4 $1\r25__data_o[3:0] + attribute \src "libresoc.v:186216.3-186255.6" + wire width 4 $1\r5__data_o$next[3:0]$11837 + attribute \src "libresoc.v:185918.13-185918.30" + wire width 4 $1\r5__data_o[3:0] + attribute \src "libresoc.v:186049.3-186075.6" + wire width 4 $1\reg$next[3:0]$11803 + attribute \src "libresoc.v:185924.13-185924.25" + wire width 4 $1\reg[3:0] + attribute \src "libresoc.v:185979.3-186018.6" + wire width 4 $1\src15__data_o$next[3:0]$11794 + attribute \src "libresoc.v:185929.13-185929.33" + wire width 4 $1\src15__data_o[3:0] + attribute \src "libresoc.v:186076.3-186115.6" + wire width 4 $1\src25__data_o$next[3:0]$11809 + attribute \src "libresoc.v:185936.13-185936.33" + wire width 4 $1\src25__data_o[3:0] + attribute \src "libresoc.v:186146.3-186185.6" + wire width 4 $1\src35__data_o$next[3:0]$11823 + attribute \src "libresoc.v:185943.13-185943.33" + wire width 4 $1\src35__data_o[3:0] + attribute \src "libresoc.v:186256.3-186285.6" + wire $1\wr_detect$10[0:0]$11845 + attribute \src "libresoc.v:186326.3-186355.6" + wire $1\wr_detect$13[0:0]$11859 + attribute \src "libresoc.v:186116.3-186145.6" + wire $1\wr_detect$4[0:0]$11817 + attribute \src "libresoc.v:186186.3-186215.6" + wire $1\wr_detect$7[0:0]$11831 + attribute \src "libresoc.v:186019.3-186048.6" + wire $1\wr_detect[0:0] + attribute \src "libresoc.v:186286.3-186325.6" + wire width 4 $2\r25__data_o$next[3:0]$11852 + attribute \src "libresoc.v:186216.3-186255.6" + wire width 4 $2\r5__data_o$next[3:0]$11838 + attribute \src "libresoc.v:186049.3-186075.6" + wire width 4 $2\reg$next[3:0]$11804 + attribute \src "libresoc.v:185979.3-186018.6" + wire width 4 $2\src15__data_o$next[3:0]$11795 + attribute \src "libresoc.v:186076.3-186115.6" + wire width 4 $2\src25__data_o$next[3:0]$11810 + attribute \src "libresoc.v:186146.3-186185.6" + wire width 4 $2\src35__data_o$next[3:0]$11824 + attribute \src "libresoc.v:186256.3-186285.6" + wire $2\wr_detect$10[0:0]$11846 + attribute \src "libresoc.v:186326.3-186355.6" + wire $2\wr_detect$13[0:0]$11860 + attribute \src "libresoc.v:186116.3-186145.6" + wire $2\wr_detect$4[0:0]$11818 + attribute \src "libresoc.v:186186.3-186215.6" + wire $2\wr_detect$7[0:0]$11832 + attribute \src "libresoc.v:186019.3-186048.6" + wire $2\wr_detect[0:0] + attribute \src "libresoc.v:186286.3-186325.6" + wire width 4 $3\r25__data_o$next[3:0]$11853 + attribute \src "libresoc.v:186216.3-186255.6" + wire width 4 $3\r5__data_o$next[3:0]$11839 + attribute \src "libresoc.v:186049.3-186075.6" + wire width 4 $3\reg$next[3:0]$11805 + attribute \src "libresoc.v:185979.3-186018.6" + wire width 4 $3\src15__data_o$next[3:0]$11796 + attribute \src "libresoc.v:186076.3-186115.6" + wire width 4 $3\src25__data_o$next[3:0]$11811 + attribute \src "libresoc.v:186146.3-186185.6" + wire width 4 $3\src35__data_o$next[3:0]$11825 + attribute \src "libresoc.v:186256.3-186285.6" + wire $3\wr_detect$10[0:0]$11847 + attribute \src "libresoc.v:186326.3-186355.6" + wire $3\wr_detect$13[0:0]$11861 + attribute \src "libresoc.v:186116.3-186145.6" + wire $3\wr_detect$4[0:0]$11819 + attribute \src "libresoc.v:186186.3-186215.6" + wire $3\wr_detect$7[0:0]$11833 + attribute \src "libresoc.v:186019.3-186048.6" + wire $3\wr_detect[0:0] + attribute \src "libresoc.v:186286.3-186325.6" + wire width 4 $4\r25__data_o$next[3:0]$11854 + attribute \src "libresoc.v:186216.3-186255.6" + wire width 4 $4\r5__data_o$next[3:0]$11840 + attribute \src "libresoc.v:186049.3-186075.6" + wire width 4 $4\reg$next[3:0]$11806 + attribute \src "libresoc.v:185979.3-186018.6" + wire width 4 $4\src15__data_o$next[3:0]$11797 + attribute \src "libresoc.v:186076.3-186115.6" + wire width 4 $4\src25__data_o$next[3:0]$11812 + attribute \src "libresoc.v:186146.3-186185.6" + wire width 4 $4\src35__data_o$next[3:0]$11826 + attribute \src "libresoc.v:186256.3-186285.6" + wire $4\wr_detect$10[0:0]$11848 + attribute \src "libresoc.v:186326.3-186355.6" + wire $4\wr_detect$13[0:0]$11862 + attribute \src "libresoc.v:186116.3-186145.6" + wire $4\wr_detect$4[0:0]$11820 + attribute \src "libresoc.v:186186.3-186215.6" + wire $4\wr_detect$7[0:0]$11834 + attribute \src "libresoc.v:186019.3-186048.6" + wire $4\wr_detect[0:0] + attribute \src "libresoc.v:186286.3-186325.6" + wire width 4 $5\r25__data_o$next[3:0]$11855 + attribute \src "libresoc.v:186216.3-186255.6" + wire width 4 $5\r5__data_o$next[3:0]$11841 + attribute \src "libresoc.v:185979.3-186018.6" + wire width 4 $5\src15__data_o$next[3:0]$11798 + attribute \src "libresoc.v:186076.3-186115.6" + wire width 4 $5\src25__data_o$next[3:0]$11813 + attribute \src "libresoc.v:186146.3-186185.6" + wire width 4 $5\src35__data_o$next[3:0]$11827 + attribute \src "libresoc.v:186286.3-186325.6" + wire width 4 $6\r25__data_o$next[3:0]$11856 + attribute \src "libresoc.v:186216.3-186255.6" + wire width 4 $6\r5__data_o$next[3:0]$11842 + attribute \src "libresoc.v:185979.3-186018.6" + wire width 4 $6\src15__data_o$next[3:0]$11799 + attribute \src "libresoc.v:186076.3-186115.6" + wire width 4 $6\src25__data_o$next[3:0]$11814 + attribute \src "libresoc.v:186146.3-186185.6" + wire width 4 $6\src35__data_o$next[3:0]$11828 + attribute \src "libresoc.v:185962.17-185962.104" + wire $not$libresoc.v:185962$11781_Y + attribute \src "libresoc.v:185963.18-185963.105" + wire $not$libresoc.v:185963$11782_Y + attribute \src "libresoc.v:185964.17-185964.100" + wire $not$libresoc.v:185964$11783_Y + attribute \src "libresoc.v:185965.17-185965.103" + wire $not$libresoc.v:185965$11784_Y + attribute \src "libresoc.v:185966.17-185966.103" + wire $not$libresoc.v:185966$11785_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 18 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 input 9 \dest15__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 8 \dest15__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 input 11 \dest25__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 10 \dest25__wen + attribute \src "libresoc.v:185886.7-185886.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 output 14 \r25__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 \r25__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 15 \r25__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 output 12 \r5__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 \r5__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 13 \r5__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 4 \reg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 4 \reg$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 output 3 \src15__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 \src15__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 2 \src15__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 output 5 \src25__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 \src25__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 4 \src25__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 output 7 \src35__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 \src35__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 6 \src35__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 input 16 \w5__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 17 \w5__wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:185962$11781 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$10 + connect \Y $not$libresoc.v:185962$11781_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:185963$11782 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$13 + connect \Y $not$libresoc.v:185963$11782_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:185964$11783 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect + connect \Y $not$libresoc.v:185964$11783_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:185965$11784 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$4 + connect \Y $not$libresoc.v:185965$11784_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:185966$11785 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$7 + connect \Y $not$libresoc.v:185966$11785_Y + end + attribute \src "libresoc.v:185886.7-185886.20" + process $proc$libresoc.v:185886$11863 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:185911.13-185911.31" + process $proc$libresoc.v:185911$11864 + assign { } { } + assign $1\r25__data_o[3:0] 4'0000 + sync always + sync init + update \r25__data_o $1\r25__data_o[3:0] + end + attribute \src "libresoc.v:185918.13-185918.30" + process $proc$libresoc.v:185918$11865 + assign { } { } + assign $1\r5__data_o[3:0] 4'0000 + sync always + sync init + update \r5__data_o $1\r5__data_o[3:0] + end + attribute \src "libresoc.v:185924.13-185924.25" + process $proc$libresoc.v:185924$11866 + assign { } { } + assign $1\reg[3:0] 4'0000 + sync always + sync init + update \reg $1\reg[3:0] + end + attribute \src "libresoc.v:185929.13-185929.33" + process $proc$libresoc.v:185929$11867 + assign { } { } + assign $1\src15__data_o[3:0] 4'0000 + sync always + sync init + update \src15__data_o $1\src15__data_o[3:0] + end + attribute \src "libresoc.v:185936.13-185936.33" + process $proc$libresoc.v:185936$11868 + assign { } { } + assign $1\src25__data_o[3:0] 4'0000 + sync always + sync init + update \src25__data_o $1\src25__data_o[3:0] + end + attribute \src "libresoc.v:185943.13-185943.33" + process $proc$libresoc.v:185943$11869 + assign { } { } + assign $1\src35__data_o[3:0] 4'0000 + sync always + sync init + update \src35__data_o $1\src35__data_o[3:0] + end + attribute \src "libresoc.v:185967.3-185968.25" + process $proc$libresoc.v:185967$11786 + assign { } { } + assign $0\reg[3:0] \reg$next + sync posedge \coresync_clk + update \reg $0\reg[3:0] + end + attribute \src "libresoc.v:185969.3-185970.39" + process $proc$libresoc.v:185969$11787 + assign { } { } + assign $0\r25__data_o[3:0] \r25__data_o$next + sync posedge \coresync_clk + update \r25__data_o $0\r25__data_o[3:0] + end + attribute \src "libresoc.v:185971.3-185972.37" + process $proc$libresoc.v:185971$11788 + assign { } { } + assign $0\r5__data_o[3:0] \r5__data_o$next + sync posedge \coresync_clk + update \r5__data_o $0\r5__data_o[3:0] + end + attribute \src "libresoc.v:185973.3-185974.43" + process $proc$libresoc.v:185973$11789 + assign { } { } + assign $0\src35__data_o[3:0] \src35__data_o$next + sync posedge \coresync_clk + update \src35__data_o $0\src35__data_o[3:0] + end + attribute \src "libresoc.v:185975.3-185976.43" + process $proc$libresoc.v:185975$11790 + assign { } { } + assign $0\src25__data_o[3:0] \src25__data_o$next + sync posedge \coresync_clk + update \src25__data_o $0\src25__data_o[3:0] + end + attribute \src "libresoc.v:185977.3-185978.43" + process $proc$libresoc.v:185977$11791 + assign { } { } + assign $0\src15__data_o[3:0] \src15__data_o$next + sync posedge \coresync_clk + update \src15__data_o $0\src15__data_o[3:0] + end + attribute \src "libresoc.v:185979.3-186018.6" + process $proc$libresoc.v:185979$11792 + assign { } { } + assign { } { } + assign { } { } + assign $0\src15__data_o$next[3:0]$11793 $6\src15__data_o$next[3:0]$11799 + attribute \src "libresoc.v:185980.5-185980.29" + switch \initial + attribute \src "libresoc.v:185980.9-185980.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src15__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src15__data_o$next[3:0]$11794 $5\src15__data_o$next[3:0]$11798 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest15__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src15__data_o$next[3:0]$11795 \dest15__data_i + case + assign $2\src15__data_o$next[3:0]$11795 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest25__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src15__data_o$next[3:0]$11796 \dest25__data_i + case + assign $3\src15__data_o$next[3:0]$11796 $2\src15__data_o$next[3:0]$11795 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w5__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src15__data_o$next[3:0]$11797 \w5__data_i + case + assign $4\src15__data_o$next[3:0]$11797 $3\src15__data_o$next[3:0]$11796 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src15__data_o$next[3:0]$11798 \reg + case + assign $5\src15__data_o$next[3:0]$11798 $4\src15__data_o$next[3:0]$11797 + end + case + assign $1\src15__data_o$next[3:0]$11794 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src15__data_o$next[3:0]$11799 4'0000 + case + assign $6\src15__data_o$next[3:0]$11799 $1\src15__data_o$next[3:0]$11794 + end + sync always + update \src15__data_o$next $0\src15__data_o$next[3:0]$11793 + end + attribute \src "libresoc.v:186019.3-186048.6" + process $proc$libresoc.v:186019$11800 + assign { } { } + assign { } { } + assign $0\wr_detect[0:0] $1\wr_detect[0:0] + attribute \src "libresoc.v:186020.5-186020.29" + switch \initial + attribute \src "libresoc.v:186020.9-186020.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src15__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect[0:0] $4\wr_detect[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest15__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect[0:0] 1'1 + case + assign $2\wr_detect[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest25__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect[0:0] 1'1 + case + assign $3\wr_detect[0:0] $2\wr_detect[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w5__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect[0:0] 1'1 + case + assign $4\wr_detect[0:0] $3\wr_detect[0:0] + end + case + assign $1\wr_detect[0:0] 1'0 + end + sync always + update \wr_detect $0\wr_detect[0:0] + end + attribute \src "libresoc.v:186049.3-186075.6" + process $proc$libresoc.v:186049$11801 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\reg$next[3:0]$11802 $4\reg$next[3:0]$11806 + attribute \src "libresoc.v:186050.5-186050.29" + switch \initial + attribute \src "libresoc.v:186050.9-186050.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest15__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\reg$next[3:0]$11803 \dest15__data_i + case + assign $1\reg$next[3:0]$11803 \reg + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest25__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\reg$next[3:0]$11804 \dest25__data_i + case + assign $2\reg$next[3:0]$11804 $1\reg$next[3:0]$11803 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \w5__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\reg$next[3:0]$11805 \w5__data_i + case + assign $3\reg$next[3:0]$11805 $2\reg$next[3:0]$11804 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\reg$next[3:0]$11806 4'0000 + case + assign $4\reg$next[3:0]$11806 $3\reg$next[3:0]$11805 + end + sync always + update \reg$next $0\reg$next[3:0]$11802 + end + attribute \src "libresoc.v:186076.3-186115.6" + process $proc$libresoc.v:186076$11807 + assign { } { } + assign { } { } + assign { } { } + assign $0\src25__data_o$next[3:0]$11808 $6\src25__data_o$next[3:0]$11814 + attribute \src "libresoc.v:186077.5-186077.29" + switch \initial + attribute \src "libresoc.v:186077.9-186077.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src25__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src25__data_o$next[3:0]$11809 $5\src25__data_o$next[3:0]$11813 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest15__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src25__data_o$next[3:0]$11810 \dest15__data_i + case + assign $2\src25__data_o$next[3:0]$11810 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest25__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src25__data_o$next[3:0]$11811 \dest25__data_i + case + assign $3\src25__data_o$next[3:0]$11811 $2\src25__data_o$next[3:0]$11810 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w5__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src25__data_o$next[3:0]$11812 \w5__data_i + case + assign $4\src25__data_o$next[3:0]$11812 $3\src25__data_o$next[3:0]$11811 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src25__data_o$next[3:0]$11813 \reg + case + assign $5\src25__data_o$next[3:0]$11813 $4\src25__data_o$next[3:0]$11812 + end + case + assign $1\src25__data_o$next[3:0]$11809 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src25__data_o$next[3:0]$11814 4'0000 + case + assign $6\src25__data_o$next[3:0]$11814 $1\src25__data_o$next[3:0]$11809 + end + sync always + update \src25__data_o$next $0\src25__data_o$next[3:0]$11808 + end + attribute \src "libresoc.v:186116.3-186145.6" + process $proc$libresoc.v:186116$11815 + assign { } { } + assign { } { } + assign $0\wr_detect$4[0:0]$11816 $1\wr_detect$4[0:0]$11817 + attribute \src "libresoc.v:186117.5-186117.29" + switch \initial + attribute \src "libresoc.v:186117.9-186117.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src25__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$4[0:0]$11817 $4\wr_detect$4[0:0]$11820 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest15__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$4[0:0]$11818 1'1 + case + assign $2\wr_detect$4[0:0]$11818 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest25__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$4[0:0]$11819 1'1 + case + assign $3\wr_detect$4[0:0]$11819 $2\wr_detect$4[0:0]$11818 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w5__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$4[0:0]$11820 1'1 + case + assign $4\wr_detect$4[0:0]$11820 $3\wr_detect$4[0:0]$11819 + end + case + assign $1\wr_detect$4[0:0]$11817 1'0 + end + sync always + update \wr_detect$4 $0\wr_detect$4[0:0]$11816 + end + attribute \src "libresoc.v:186146.3-186185.6" + process $proc$libresoc.v:186146$11821 + assign { } { } + assign { } { } + assign { } { } + assign $0\src35__data_o$next[3:0]$11822 $6\src35__data_o$next[3:0]$11828 + attribute \src "libresoc.v:186147.5-186147.29" + switch \initial + attribute \src "libresoc.v:186147.9-186147.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src35__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src35__data_o$next[3:0]$11823 $5\src35__data_o$next[3:0]$11827 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest15__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src35__data_o$next[3:0]$11824 \dest15__data_i + case + assign $2\src35__data_o$next[3:0]$11824 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest25__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src35__data_o$next[3:0]$11825 \dest25__data_i + case + assign $3\src35__data_o$next[3:0]$11825 $2\src35__data_o$next[3:0]$11824 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w5__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src35__data_o$next[3:0]$11826 \w5__data_i + case + assign $4\src35__data_o$next[3:0]$11826 $3\src35__data_o$next[3:0]$11825 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$6 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src35__data_o$next[3:0]$11827 \reg + case + assign $5\src35__data_o$next[3:0]$11827 $4\src35__data_o$next[3:0]$11826 + end + case + assign $1\src35__data_o$next[3:0]$11823 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src35__data_o$next[3:0]$11828 4'0000 + case + assign $6\src35__data_o$next[3:0]$11828 $1\src35__data_o$next[3:0]$11823 + end + sync always + update \src35__data_o$next $0\src35__data_o$next[3:0]$11822 + end + attribute \src "libresoc.v:186186.3-186215.6" + process $proc$libresoc.v:186186$11829 + assign { } { } + assign { } { } + assign $0\wr_detect$7[0:0]$11830 $1\wr_detect$7[0:0]$11831 + attribute \src "libresoc.v:186187.5-186187.29" + switch \initial + attribute \src "libresoc.v:186187.9-186187.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src35__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$7[0:0]$11831 $4\wr_detect$7[0:0]$11834 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest15__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$7[0:0]$11832 1'1 + case + assign $2\wr_detect$7[0:0]$11832 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest25__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$7[0:0]$11833 1'1 + case + assign $3\wr_detect$7[0:0]$11833 $2\wr_detect$7[0:0]$11832 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w5__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$7[0:0]$11834 1'1 + case + assign $4\wr_detect$7[0:0]$11834 $3\wr_detect$7[0:0]$11833 + end + case + assign $1\wr_detect$7[0:0]$11831 1'0 + end + sync always + update \wr_detect$7 $0\wr_detect$7[0:0]$11830 + end + attribute \src "libresoc.v:186216.3-186255.6" + process $proc$libresoc.v:186216$11835 + assign { } { } + assign { } { } + assign { } { } + assign $0\r5__data_o$next[3:0]$11836 $6\r5__data_o$next[3:0]$11842 + attribute \src "libresoc.v:186217.5-186217.29" + switch \initial + attribute \src "libresoc.v:186217.9-186217.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r5__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\r5__data_o$next[3:0]$11837 $5\r5__data_o$next[3:0]$11841 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest15__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r5__data_o$next[3:0]$11838 \dest15__data_i + case + assign $2\r5__data_o$next[3:0]$11838 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest25__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\r5__data_o$next[3:0]$11839 \dest25__data_i + case + assign $3\r5__data_o$next[3:0]$11839 $2\r5__data_o$next[3:0]$11838 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w5__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\r5__data_o$next[3:0]$11840 \w5__data_i + case + assign $4\r5__data_o$next[3:0]$11840 $3\r5__data_o$next[3:0]$11839 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$9 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\r5__data_o$next[3:0]$11841 \reg + case + assign $5\r5__data_o$next[3:0]$11841 $4\r5__data_o$next[3:0]$11840 + end + case + assign $1\r5__data_o$next[3:0]$11837 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\r5__data_o$next[3:0]$11842 4'0000 + case + assign $6\r5__data_o$next[3:0]$11842 $1\r5__data_o$next[3:0]$11837 + end + sync always + update \r5__data_o$next $0\r5__data_o$next[3:0]$11836 + end + attribute \src "libresoc.v:186256.3-186285.6" + process $proc$libresoc.v:186256$11843 + assign { } { } + assign { } { } + assign $0\wr_detect$10[0:0]$11844 $1\wr_detect$10[0:0]$11845 + attribute \src "libresoc.v:186257.5-186257.29" + switch \initial + attribute \src "libresoc.v:186257.9-186257.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r5__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$10[0:0]$11845 $4\wr_detect$10[0:0]$11848 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest15__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$10[0:0]$11846 1'1 + case + assign $2\wr_detect$10[0:0]$11846 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest25__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$10[0:0]$11847 1'1 + case + assign $3\wr_detect$10[0:0]$11847 $2\wr_detect$10[0:0]$11846 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w5__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$10[0:0]$11848 1'1 + case + assign $4\wr_detect$10[0:0]$11848 $3\wr_detect$10[0:0]$11847 + end + case + assign $1\wr_detect$10[0:0]$11845 1'0 + end + sync always + update \wr_detect$10 $0\wr_detect$10[0:0]$11844 + end + attribute \src "libresoc.v:186286.3-186325.6" + process $proc$libresoc.v:186286$11849 + assign { } { } + assign { } { } + assign { } { } + assign $0\r25__data_o$next[3:0]$11850 $6\r25__data_o$next[3:0]$11856 + attribute \src "libresoc.v:186287.5-186287.29" + switch \initial + attribute \src "libresoc.v:186287.9-186287.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r25__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\r25__data_o$next[3:0]$11851 $5\r25__data_o$next[3:0]$11855 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest15__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r25__data_o$next[3:0]$11852 \dest15__data_i + case + assign $2\r25__data_o$next[3:0]$11852 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest25__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\r25__data_o$next[3:0]$11853 \dest25__data_i + case + assign $3\r25__data_o$next[3:0]$11853 $2\r25__data_o$next[3:0]$11852 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w5__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\r25__data_o$next[3:0]$11854 \w5__data_i + case + assign $4\r25__data_o$next[3:0]$11854 $3\r25__data_o$next[3:0]$11853 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$12 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\r25__data_o$next[3:0]$11855 \reg + case + assign $5\r25__data_o$next[3:0]$11855 $4\r25__data_o$next[3:0]$11854 + end + case + assign $1\r25__data_o$next[3:0]$11851 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\r25__data_o$next[3:0]$11856 4'0000 + case + assign $6\r25__data_o$next[3:0]$11856 $1\r25__data_o$next[3:0]$11851 + end + sync always + update \r25__data_o$next $0\r25__data_o$next[3:0]$11850 + end + attribute \src "libresoc.v:186326.3-186355.6" + process $proc$libresoc.v:186326$11857 + assign { } { } + assign { } { } + assign $0\wr_detect$13[0:0]$11858 $1\wr_detect$13[0:0]$11859 + attribute \src "libresoc.v:186327.5-186327.29" + switch \initial + attribute \src "libresoc.v:186327.9-186327.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r25__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$13[0:0]$11859 $4\wr_detect$13[0:0]$11862 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest15__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$13[0:0]$11860 1'1 + case + assign $2\wr_detect$13[0:0]$11860 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest25__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$13[0:0]$11861 1'1 + case + assign $3\wr_detect$13[0:0]$11861 $2\wr_detect$13[0:0]$11860 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w5__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$13[0:0]$11862 1'1 + case + assign $4\wr_detect$13[0:0]$11862 $3\wr_detect$13[0:0]$11861 + end + case + assign $1\wr_detect$13[0:0]$11859 1'0 + end + sync always + update \wr_detect$13 $0\wr_detect$13[0:0]$11858 + end + connect \$9 $not$libresoc.v:185962$11781_Y + connect \$12 $not$libresoc.v:185963$11782_Y + connect \$1 $not$libresoc.v:185964$11783_Y + connect \$3 $not$libresoc.v:185965$11784_Y + connect \$6 $not$libresoc.v:185966$11785_Y +end +attribute \src "libresoc.v:186360.1-186831.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.cr.reg_6" +attribute \generator "nMigen" +module \reg_6 + attribute \src "libresoc.v:186361.7-186361.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:186761.3-186800.6" + wire width 4 $0\r26__data_o$next[3:0]$11939 + attribute \src "libresoc.v:186444.3-186445.39" + wire width 4 $0\r26__data_o[3:0] + attribute \src "libresoc.v:186691.3-186730.6" + wire width 4 $0\r6__data_o$next[3:0]$11925 + attribute \src "libresoc.v:186446.3-186447.37" + wire width 4 $0\r6__data_o[3:0] + attribute \src "libresoc.v:186524.3-186550.6" + wire width 4 $0\reg$next[3:0]$11891 + attribute \src "libresoc.v:186442.3-186443.25" + wire width 4 $0\reg[3:0] + attribute \src "libresoc.v:186454.3-186493.6" + wire width 4 $0\src16__data_o$next[3:0]$11882 + attribute \src "libresoc.v:186452.3-186453.43" + wire width 4 $0\src16__data_o[3:0] + attribute \src "libresoc.v:186551.3-186590.6" + wire width 4 $0\src26__data_o$next[3:0]$11897 + attribute \src "libresoc.v:186450.3-186451.43" + wire width 4 $0\src26__data_o[3:0] + attribute \src "libresoc.v:186621.3-186660.6" + wire width 4 $0\src36__data_o$next[3:0]$11911 + attribute \src "libresoc.v:186448.3-186449.43" + wire width 4 $0\src36__data_o[3:0] + attribute \src "libresoc.v:186731.3-186760.6" + wire $0\wr_detect$10[0:0]$11933 + attribute \src "libresoc.v:186801.3-186830.6" + wire $0\wr_detect$13[0:0]$11947 + attribute \src "libresoc.v:186591.3-186620.6" + wire $0\wr_detect$4[0:0]$11905 + attribute \src "libresoc.v:186661.3-186690.6" + wire $0\wr_detect$7[0:0]$11919 + attribute \src "libresoc.v:186494.3-186523.6" + wire $0\wr_detect[0:0] + attribute \src "libresoc.v:186761.3-186800.6" + wire width 4 $1\r26__data_o$next[3:0]$11940 + attribute \src "libresoc.v:186386.13-186386.31" + wire width 4 $1\r26__data_o[3:0] + attribute \src "libresoc.v:186691.3-186730.6" + wire width 4 $1\r6__data_o$next[3:0]$11926 + attribute \src "libresoc.v:186393.13-186393.30" + wire width 4 $1\r6__data_o[3:0] + attribute \src "libresoc.v:186524.3-186550.6" + wire width 4 $1\reg$next[3:0]$11892 + attribute \src "libresoc.v:186399.13-186399.25" + wire width 4 $1\reg[3:0] + attribute \src "libresoc.v:186454.3-186493.6" + wire width 4 $1\src16__data_o$next[3:0]$11883 + attribute \src "libresoc.v:186404.13-186404.33" + wire width 4 $1\src16__data_o[3:0] + attribute \src "libresoc.v:186551.3-186590.6" + wire width 4 $1\src26__data_o$next[3:0]$11898 + attribute \src "libresoc.v:186411.13-186411.33" + wire width 4 $1\src26__data_o[3:0] + attribute \src "libresoc.v:186621.3-186660.6" + wire width 4 $1\src36__data_o$next[3:0]$11912 + attribute \src "libresoc.v:186418.13-186418.33" + wire width 4 $1\src36__data_o[3:0] + attribute \src "libresoc.v:186731.3-186760.6" + wire $1\wr_detect$10[0:0]$11934 + attribute \src "libresoc.v:186801.3-186830.6" + wire $1\wr_detect$13[0:0]$11948 + attribute \src "libresoc.v:186591.3-186620.6" + wire $1\wr_detect$4[0:0]$11906 + attribute \src "libresoc.v:186661.3-186690.6" + wire $1\wr_detect$7[0:0]$11920 + attribute \src "libresoc.v:186494.3-186523.6" + wire $1\wr_detect[0:0] + attribute \src "libresoc.v:186761.3-186800.6" + wire width 4 $2\r26__data_o$next[3:0]$11941 + attribute \src "libresoc.v:186691.3-186730.6" + wire width 4 $2\r6__data_o$next[3:0]$11927 + attribute \src "libresoc.v:186524.3-186550.6" + wire width 4 $2\reg$next[3:0]$11893 + attribute \src "libresoc.v:186454.3-186493.6" + wire width 4 $2\src16__data_o$next[3:0]$11884 + attribute \src "libresoc.v:186551.3-186590.6" + wire width 4 $2\src26__data_o$next[3:0]$11899 + attribute \src "libresoc.v:186621.3-186660.6" + wire width 4 $2\src36__data_o$next[3:0]$11913 + attribute \src "libresoc.v:186731.3-186760.6" + wire $2\wr_detect$10[0:0]$11935 + attribute \src "libresoc.v:186801.3-186830.6" + wire $2\wr_detect$13[0:0]$11949 + attribute \src "libresoc.v:186591.3-186620.6" + wire $2\wr_detect$4[0:0]$11907 + attribute \src "libresoc.v:186661.3-186690.6" + wire $2\wr_detect$7[0:0]$11921 + attribute \src "libresoc.v:186494.3-186523.6" + wire $2\wr_detect[0:0] + attribute \src "libresoc.v:186761.3-186800.6" + wire width 4 $3\r26__data_o$next[3:0]$11942 + attribute \src "libresoc.v:186691.3-186730.6" + wire width 4 $3\r6__data_o$next[3:0]$11928 + attribute \src "libresoc.v:186524.3-186550.6" + wire width 4 $3\reg$next[3:0]$11894 + attribute \src "libresoc.v:186454.3-186493.6" + wire width 4 $3\src16__data_o$next[3:0]$11885 + attribute \src "libresoc.v:186551.3-186590.6" + wire width 4 $3\src26__data_o$next[3:0]$11900 + attribute \src "libresoc.v:186621.3-186660.6" + wire width 4 $3\src36__data_o$next[3:0]$11914 + attribute \src "libresoc.v:186731.3-186760.6" + wire $3\wr_detect$10[0:0]$11936 + attribute \src "libresoc.v:186801.3-186830.6" + wire $3\wr_detect$13[0:0]$11950 + attribute \src "libresoc.v:186591.3-186620.6" + wire $3\wr_detect$4[0:0]$11908 + attribute \src "libresoc.v:186661.3-186690.6" + wire $3\wr_detect$7[0:0]$11922 + attribute \src "libresoc.v:186494.3-186523.6" + wire $3\wr_detect[0:0] + attribute \src "libresoc.v:186761.3-186800.6" + wire width 4 $4\r26__data_o$next[3:0]$11943 + attribute \src "libresoc.v:186691.3-186730.6" + wire width 4 $4\r6__data_o$next[3:0]$11929 + attribute \src "libresoc.v:186524.3-186550.6" + wire width 4 $4\reg$next[3:0]$11895 + attribute \src "libresoc.v:186454.3-186493.6" + wire width 4 $4\src16__data_o$next[3:0]$11886 + attribute \src "libresoc.v:186551.3-186590.6" + wire width 4 $4\src26__data_o$next[3:0]$11901 + attribute \src "libresoc.v:186621.3-186660.6" + wire width 4 $4\src36__data_o$next[3:0]$11915 + attribute \src "libresoc.v:186731.3-186760.6" + wire $4\wr_detect$10[0:0]$11937 + attribute \src "libresoc.v:186801.3-186830.6" + wire $4\wr_detect$13[0:0]$11951 + attribute \src "libresoc.v:186591.3-186620.6" + wire $4\wr_detect$4[0:0]$11909 + attribute \src "libresoc.v:186661.3-186690.6" + wire $4\wr_detect$7[0:0]$11923 + attribute \src "libresoc.v:186494.3-186523.6" + wire $4\wr_detect[0:0] + attribute \src "libresoc.v:186761.3-186800.6" + wire width 4 $5\r26__data_o$next[3:0]$11944 + attribute \src "libresoc.v:186691.3-186730.6" + wire width 4 $5\r6__data_o$next[3:0]$11930 + attribute \src "libresoc.v:186454.3-186493.6" + wire width 4 $5\src16__data_o$next[3:0]$11887 + attribute \src "libresoc.v:186551.3-186590.6" + wire width 4 $5\src26__data_o$next[3:0]$11902 + attribute \src "libresoc.v:186621.3-186660.6" + wire width 4 $5\src36__data_o$next[3:0]$11916 + attribute \src "libresoc.v:186761.3-186800.6" + wire width 4 $6\r26__data_o$next[3:0]$11945 + attribute \src "libresoc.v:186691.3-186730.6" + wire width 4 $6\r6__data_o$next[3:0]$11931 + attribute \src "libresoc.v:186454.3-186493.6" + wire width 4 $6\src16__data_o$next[3:0]$11888 + attribute \src "libresoc.v:186551.3-186590.6" + wire width 4 $6\src26__data_o$next[3:0]$11903 + attribute \src "libresoc.v:186621.3-186660.6" + wire width 4 $6\src36__data_o$next[3:0]$11917 + attribute \src "libresoc.v:186437.17-186437.104" + wire $not$libresoc.v:186437$11870_Y + attribute \src "libresoc.v:186438.18-186438.105" + wire $not$libresoc.v:186438$11871_Y + attribute \src "libresoc.v:186439.17-186439.100" + wire $not$libresoc.v:186439$11872_Y + attribute \src "libresoc.v:186440.17-186440.103" + wire $not$libresoc.v:186440$11873_Y + attribute \src "libresoc.v:186441.17-186441.103" + wire $not$libresoc.v:186441$11874_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 18 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 input 9 \dest16__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 8 \dest16__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 input 11 \dest26__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 10 \dest26__wen + attribute \src "libresoc.v:186361.7-186361.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 output 14 \r26__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 \r26__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 15 \r26__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 output 12 \r6__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 \r6__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 13 \r6__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 4 \reg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 4 \reg$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 output 3 \src16__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 \src16__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 2 \src16__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 output 5 \src26__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 \src26__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 4 \src26__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 output 7 \src36__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 \src36__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 6 \src36__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 input 16 \w6__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 17 \w6__wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:186437$11870 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$10 + connect \Y $not$libresoc.v:186437$11870_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:186438$11871 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$13 + connect \Y $not$libresoc.v:186438$11871_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:186439$11872 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect + connect \Y $not$libresoc.v:186439$11872_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:186440$11873 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$4 + connect \Y $not$libresoc.v:186440$11873_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:186441$11874 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$7 + connect \Y $not$libresoc.v:186441$11874_Y + end + attribute \src "libresoc.v:186361.7-186361.20" + process $proc$libresoc.v:186361$11952 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:186386.13-186386.31" + process $proc$libresoc.v:186386$11953 + assign { } { } + assign $1\r26__data_o[3:0] 4'0000 + sync always + sync init + update \r26__data_o $1\r26__data_o[3:0] + end + attribute \src "libresoc.v:186393.13-186393.30" + process $proc$libresoc.v:186393$11954 + assign { } { } + assign $1\r6__data_o[3:0] 4'0000 + sync always + sync init + update \r6__data_o $1\r6__data_o[3:0] + end + attribute \src "libresoc.v:186399.13-186399.25" + process $proc$libresoc.v:186399$11955 + assign { } { } + assign $1\reg[3:0] 4'0000 + sync always + sync init + update \reg $1\reg[3:0] + end + attribute \src "libresoc.v:186404.13-186404.33" + process $proc$libresoc.v:186404$11956 + assign { } { } + assign $1\src16__data_o[3:0] 4'0000 + sync always + sync init + update \src16__data_o $1\src16__data_o[3:0] + end + attribute \src "libresoc.v:186411.13-186411.33" + process $proc$libresoc.v:186411$11957 + assign { } { } + assign $1\src26__data_o[3:0] 4'0000 + sync always + sync init + update \src26__data_o $1\src26__data_o[3:0] + end + attribute \src "libresoc.v:186418.13-186418.33" + process $proc$libresoc.v:186418$11958 + assign { } { } + assign $1\src36__data_o[3:0] 4'0000 + sync always + sync init + update \src36__data_o $1\src36__data_o[3:0] + end + attribute \src "libresoc.v:186442.3-186443.25" + process $proc$libresoc.v:186442$11875 + assign { } { } + assign $0\reg[3:0] \reg$next + sync posedge \coresync_clk + update \reg $0\reg[3:0] + end + attribute \src "libresoc.v:186444.3-186445.39" + process $proc$libresoc.v:186444$11876 + assign { } { } + assign $0\r26__data_o[3:0] \r26__data_o$next + sync posedge \coresync_clk + update \r26__data_o $0\r26__data_o[3:0] + end + attribute \src "libresoc.v:186446.3-186447.37" + process $proc$libresoc.v:186446$11877 + assign { } { } + assign $0\r6__data_o[3:0] \r6__data_o$next + sync posedge \coresync_clk + update \r6__data_o $0\r6__data_o[3:0] + end + attribute \src "libresoc.v:186448.3-186449.43" + process $proc$libresoc.v:186448$11878 + assign { } { } + assign $0\src36__data_o[3:0] \src36__data_o$next + sync posedge \coresync_clk + update \src36__data_o $0\src36__data_o[3:0] + end + attribute \src "libresoc.v:186450.3-186451.43" + process $proc$libresoc.v:186450$11879 + assign { } { } + assign $0\src26__data_o[3:0] \src26__data_o$next + sync posedge \coresync_clk + update \src26__data_o $0\src26__data_o[3:0] + end + attribute \src "libresoc.v:186452.3-186453.43" + process $proc$libresoc.v:186452$11880 + assign { } { } + assign $0\src16__data_o[3:0] \src16__data_o$next + sync posedge \coresync_clk + update \src16__data_o $0\src16__data_o[3:0] + end + attribute \src "libresoc.v:186454.3-186493.6" + process $proc$libresoc.v:186454$11881 + assign { } { } + assign { } { } + assign { } { } + assign $0\src16__data_o$next[3:0]$11882 $6\src16__data_o$next[3:0]$11888 + attribute \src "libresoc.v:186455.5-186455.29" + switch \initial + attribute \src "libresoc.v:186455.9-186455.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src16__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src16__data_o$next[3:0]$11883 $5\src16__data_o$next[3:0]$11887 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest16__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src16__data_o$next[3:0]$11884 \dest16__data_i + case + assign $2\src16__data_o$next[3:0]$11884 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest26__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src16__data_o$next[3:0]$11885 \dest26__data_i + case + assign $3\src16__data_o$next[3:0]$11885 $2\src16__data_o$next[3:0]$11884 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w6__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src16__data_o$next[3:0]$11886 \w6__data_i + case + assign $4\src16__data_o$next[3:0]$11886 $3\src16__data_o$next[3:0]$11885 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src16__data_o$next[3:0]$11887 \reg + case + assign $5\src16__data_o$next[3:0]$11887 $4\src16__data_o$next[3:0]$11886 + end + case + assign $1\src16__data_o$next[3:0]$11883 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src16__data_o$next[3:0]$11888 4'0000 + case + assign $6\src16__data_o$next[3:0]$11888 $1\src16__data_o$next[3:0]$11883 + end + sync always + update \src16__data_o$next $0\src16__data_o$next[3:0]$11882 + end + attribute \src "libresoc.v:186494.3-186523.6" + process $proc$libresoc.v:186494$11889 + assign { } { } + assign { } { } + assign $0\wr_detect[0:0] $1\wr_detect[0:0] + attribute \src "libresoc.v:186495.5-186495.29" + switch \initial + attribute \src "libresoc.v:186495.9-186495.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src16__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect[0:0] $4\wr_detect[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest16__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect[0:0] 1'1 + case + assign $2\wr_detect[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest26__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect[0:0] 1'1 + case + assign $3\wr_detect[0:0] $2\wr_detect[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w6__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect[0:0] 1'1 + case + assign $4\wr_detect[0:0] $3\wr_detect[0:0] + end + case + assign $1\wr_detect[0:0] 1'0 + end + sync always + update \wr_detect $0\wr_detect[0:0] + end + attribute \src "libresoc.v:186524.3-186550.6" + process $proc$libresoc.v:186524$11890 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\reg$next[3:0]$11891 $4\reg$next[3:0]$11895 + attribute \src "libresoc.v:186525.5-186525.29" + switch \initial + attribute \src "libresoc.v:186525.9-186525.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest16__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\reg$next[3:0]$11892 \dest16__data_i + case + assign $1\reg$next[3:0]$11892 \reg + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest26__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\reg$next[3:0]$11893 \dest26__data_i + case + assign $2\reg$next[3:0]$11893 $1\reg$next[3:0]$11892 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \w6__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\reg$next[3:0]$11894 \w6__data_i + case + assign $3\reg$next[3:0]$11894 $2\reg$next[3:0]$11893 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\reg$next[3:0]$11895 4'0000 + case + assign $4\reg$next[3:0]$11895 $3\reg$next[3:0]$11894 + end + sync always + update \reg$next $0\reg$next[3:0]$11891 + end + attribute \src "libresoc.v:186551.3-186590.6" + process $proc$libresoc.v:186551$11896 + assign { } { } + assign { } { } + assign { } { } + assign $0\src26__data_o$next[3:0]$11897 $6\src26__data_o$next[3:0]$11903 + attribute \src "libresoc.v:186552.5-186552.29" + switch \initial + attribute \src "libresoc.v:186552.9-186552.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src26__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src26__data_o$next[3:0]$11898 $5\src26__data_o$next[3:0]$11902 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest16__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src26__data_o$next[3:0]$11899 \dest16__data_i + case + assign $2\src26__data_o$next[3:0]$11899 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest26__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src26__data_o$next[3:0]$11900 \dest26__data_i + case + assign $3\src26__data_o$next[3:0]$11900 $2\src26__data_o$next[3:0]$11899 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w6__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src26__data_o$next[3:0]$11901 \w6__data_i + case + assign $4\src26__data_o$next[3:0]$11901 $3\src26__data_o$next[3:0]$11900 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src26__data_o$next[3:0]$11902 \reg + case + assign $5\src26__data_o$next[3:0]$11902 $4\src26__data_o$next[3:0]$11901 + end + case + assign $1\src26__data_o$next[3:0]$11898 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src26__data_o$next[3:0]$11903 4'0000 + case + assign $6\src26__data_o$next[3:0]$11903 $1\src26__data_o$next[3:0]$11898 + end + sync always + update \src26__data_o$next $0\src26__data_o$next[3:0]$11897 + end + attribute \src "libresoc.v:186591.3-186620.6" + process $proc$libresoc.v:186591$11904 + assign { } { } + assign { } { } + assign $0\wr_detect$4[0:0]$11905 $1\wr_detect$4[0:0]$11906 + attribute \src "libresoc.v:186592.5-186592.29" + switch \initial + attribute \src "libresoc.v:186592.9-186592.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src26__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$4[0:0]$11906 $4\wr_detect$4[0:0]$11909 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest16__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$4[0:0]$11907 1'1 + case + assign $2\wr_detect$4[0:0]$11907 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest26__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$4[0:0]$11908 1'1 + case + assign $3\wr_detect$4[0:0]$11908 $2\wr_detect$4[0:0]$11907 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w6__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$4[0:0]$11909 1'1 + case + assign $4\wr_detect$4[0:0]$11909 $3\wr_detect$4[0:0]$11908 + end + case + assign $1\wr_detect$4[0:0]$11906 1'0 + end + sync always + update \wr_detect$4 $0\wr_detect$4[0:0]$11905 + end + attribute \src "libresoc.v:186621.3-186660.6" + process $proc$libresoc.v:186621$11910 + assign { } { } + assign { } { } + assign { } { } + assign $0\src36__data_o$next[3:0]$11911 $6\src36__data_o$next[3:0]$11917 + attribute \src "libresoc.v:186622.5-186622.29" + switch \initial + attribute \src "libresoc.v:186622.9-186622.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src36__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src36__data_o$next[3:0]$11912 $5\src36__data_o$next[3:0]$11916 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest16__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src36__data_o$next[3:0]$11913 \dest16__data_i + case + assign $2\src36__data_o$next[3:0]$11913 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest26__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src36__data_o$next[3:0]$11914 \dest26__data_i + case + assign $3\src36__data_o$next[3:0]$11914 $2\src36__data_o$next[3:0]$11913 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w6__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src36__data_o$next[3:0]$11915 \w6__data_i + case + assign $4\src36__data_o$next[3:0]$11915 $3\src36__data_o$next[3:0]$11914 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$6 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src36__data_o$next[3:0]$11916 \reg + case + assign $5\src36__data_o$next[3:0]$11916 $4\src36__data_o$next[3:0]$11915 + end + case + assign $1\src36__data_o$next[3:0]$11912 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src36__data_o$next[3:0]$11917 4'0000 + case + assign $6\src36__data_o$next[3:0]$11917 $1\src36__data_o$next[3:0]$11912 + end + sync always + update \src36__data_o$next $0\src36__data_o$next[3:0]$11911 + end + attribute \src "libresoc.v:186661.3-186690.6" + process $proc$libresoc.v:186661$11918 + assign { } { } + assign { } { } + assign $0\wr_detect$7[0:0]$11919 $1\wr_detect$7[0:0]$11920 + attribute \src "libresoc.v:186662.5-186662.29" + switch \initial + attribute \src "libresoc.v:186662.9-186662.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src36__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$7[0:0]$11920 $4\wr_detect$7[0:0]$11923 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest16__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$7[0:0]$11921 1'1 + case + assign $2\wr_detect$7[0:0]$11921 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest26__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$7[0:0]$11922 1'1 + case + assign $3\wr_detect$7[0:0]$11922 $2\wr_detect$7[0:0]$11921 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w6__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$7[0:0]$11923 1'1 + case + assign $4\wr_detect$7[0:0]$11923 $3\wr_detect$7[0:0]$11922 + end + case + assign $1\wr_detect$7[0:0]$11920 1'0 + end + sync always + update \wr_detect$7 $0\wr_detect$7[0:0]$11919 + end + attribute \src "libresoc.v:186691.3-186730.6" + process $proc$libresoc.v:186691$11924 + assign { } { } + assign { } { } + assign { } { } + assign $0\r6__data_o$next[3:0]$11925 $6\r6__data_o$next[3:0]$11931 + attribute \src "libresoc.v:186692.5-186692.29" + switch \initial + attribute \src "libresoc.v:186692.9-186692.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r6__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\r6__data_o$next[3:0]$11926 $5\r6__data_o$next[3:0]$11930 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest16__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r6__data_o$next[3:0]$11927 \dest16__data_i + case + assign $2\r6__data_o$next[3:0]$11927 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest26__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\r6__data_o$next[3:0]$11928 \dest26__data_i + case + assign $3\r6__data_o$next[3:0]$11928 $2\r6__data_o$next[3:0]$11927 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w6__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\r6__data_o$next[3:0]$11929 \w6__data_i + case + assign $4\r6__data_o$next[3:0]$11929 $3\r6__data_o$next[3:0]$11928 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$9 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\r6__data_o$next[3:0]$11930 \reg + case + assign $5\r6__data_o$next[3:0]$11930 $4\r6__data_o$next[3:0]$11929 + end + case + assign $1\r6__data_o$next[3:0]$11926 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\r6__data_o$next[3:0]$11931 4'0000 + case + assign $6\r6__data_o$next[3:0]$11931 $1\r6__data_o$next[3:0]$11926 + end + sync always + update \r6__data_o$next $0\r6__data_o$next[3:0]$11925 + end + attribute \src "libresoc.v:186731.3-186760.6" + process $proc$libresoc.v:186731$11932 + assign { } { } + assign { } { } + assign $0\wr_detect$10[0:0]$11933 $1\wr_detect$10[0:0]$11934 + attribute \src "libresoc.v:186732.5-186732.29" + switch \initial + attribute \src "libresoc.v:186732.9-186732.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r6__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$10[0:0]$11934 $4\wr_detect$10[0:0]$11937 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest16__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$10[0:0]$11935 1'1 + case + assign $2\wr_detect$10[0:0]$11935 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest26__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$10[0:0]$11936 1'1 + case + assign $3\wr_detect$10[0:0]$11936 $2\wr_detect$10[0:0]$11935 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w6__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$10[0:0]$11937 1'1 + case + assign $4\wr_detect$10[0:0]$11937 $3\wr_detect$10[0:0]$11936 + end + case + assign $1\wr_detect$10[0:0]$11934 1'0 + end + sync always + update \wr_detect$10 $0\wr_detect$10[0:0]$11933 + end + attribute \src "libresoc.v:186761.3-186800.6" + process $proc$libresoc.v:186761$11938 + assign { } { } + assign { } { } + assign { } { } + assign $0\r26__data_o$next[3:0]$11939 $6\r26__data_o$next[3:0]$11945 + attribute \src "libresoc.v:186762.5-186762.29" + switch \initial + attribute \src "libresoc.v:186762.9-186762.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r26__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\r26__data_o$next[3:0]$11940 $5\r26__data_o$next[3:0]$11944 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest16__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r26__data_o$next[3:0]$11941 \dest16__data_i + case + assign $2\r26__data_o$next[3:0]$11941 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest26__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\r26__data_o$next[3:0]$11942 \dest26__data_i + case + assign $3\r26__data_o$next[3:0]$11942 $2\r26__data_o$next[3:0]$11941 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w6__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\r26__data_o$next[3:0]$11943 \w6__data_i + case + assign $4\r26__data_o$next[3:0]$11943 $3\r26__data_o$next[3:0]$11942 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$12 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\r26__data_o$next[3:0]$11944 \reg + case + assign $5\r26__data_o$next[3:0]$11944 $4\r26__data_o$next[3:0]$11943 + end + case + assign $1\r26__data_o$next[3:0]$11940 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\r26__data_o$next[3:0]$11945 4'0000 + case + assign $6\r26__data_o$next[3:0]$11945 $1\r26__data_o$next[3:0]$11940 + end + sync always + update \r26__data_o$next $0\r26__data_o$next[3:0]$11939 + end + attribute \src "libresoc.v:186801.3-186830.6" + process $proc$libresoc.v:186801$11946 + assign { } { } + assign { } { } + assign $0\wr_detect$13[0:0]$11947 $1\wr_detect$13[0:0]$11948 + attribute \src "libresoc.v:186802.5-186802.29" + switch \initial + attribute \src "libresoc.v:186802.9-186802.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r26__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$13[0:0]$11948 $4\wr_detect$13[0:0]$11951 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest16__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$13[0:0]$11949 1'1 + case + assign $2\wr_detect$13[0:0]$11949 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest26__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$13[0:0]$11950 1'1 + case + assign $3\wr_detect$13[0:0]$11950 $2\wr_detect$13[0:0]$11949 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w6__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$13[0:0]$11951 1'1 + case + assign $4\wr_detect$13[0:0]$11951 $3\wr_detect$13[0:0]$11950 + end + case + assign $1\wr_detect$13[0:0]$11948 1'0 + end + sync always + update \wr_detect$13 $0\wr_detect$13[0:0]$11947 + end + connect \$9 $not$libresoc.v:186437$11870_Y + connect \$12 $not$libresoc.v:186438$11871_Y + connect \$1 $not$libresoc.v:186439$11872_Y + connect \$3 $not$libresoc.v:186440$11873_Y + connect \$6 $not$libresoc.v:186441$11874_Y +end +attribute \src "libresoc.v:186835.1-187306.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.cr.reg_7" +attribute \generator "nMigen" +module \reg_7 + attribute \src "libresoc.v:186836.7-186836.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:187236.3-187275.6" + wire width 4 $0\r27__data_o$next[3:0]$12028 + attribute \src "libresoc.v:186919.3-186920.39" + wire width 4 $0\r27__data_o[3:0] + attribute \src "libresoc.v:187166.3-187205.6" + wire width 4 $0\r7__data_o$next[3:0]$12014 + attribute \src "libresoc.v:186921.3-186922.37" + wire width 4 $0\r7__data_o[3:0] + attribute \src "libresoc.v:186999.3-187025.6" + wire width 4 $0\reg$next[3:0]$11980 + attribute \src "libresoc.v:186917.3-186918.25" + wire width 4 $0\reg[3:0] + attribute \src "libresoc.v:186929.3-186968.6" + wire width 4 $0\src17__data_o$next[3:0]$11971 + attribute \src "libresoc.v:186927.3-186928.43" + wire width 4 $0\src17__data_o[3:0] + attribute \src "libresoc.v:187026.3-187065.6" + wire width 4 $0\src27__data_o$next[3:0]$11986 + attribute \src "libresoc.v:186925.3-186926.43" + wire width 4 $0\src27__data_o[3:0] + attribute \src "libresoc.v:187096.3-187135.6" + wire width 4 $0\src37__data_o$next[3:0]$12000 + attribute \src "libresoc.v:186923.3-186924.43" + wire width 4 $0\src37__data_o[3:0] + attribute \src "libresoc.v:187206.3-187235.6" + wire $0\wr_detect$10[0:0]$12022 + attribute \src "libresoc.v:187276.3-187305.6" + wire $0\wr_detect$13[0:0]$12036 + attribute \src "libresoc.v:187066.3-187095.6" + wire $0\wr_detect$4[0:0]$11994 + attribute \src "libresoc.v:187136.3-187165.6" + wire $0\wr_detect$7[0:0]$12008 + attribute \src "libresoc.v:186969.3-186998.6" + wire $0\wr_detect[0:0] + attribute \src "libresoc.v:187236.3-187275.6" + wire width 4 $1\r27__data_o$next[3:0]$12029 + attribute \src "libresoc.v:186861.13-186861.31" + wire width 4 $1\r27__data_o[3:0] + attribute \src "libresoc.v:187166.3-187205.6" + wire width 4 $1\r7__data_o$next[3:0]$12015 + attribute \src "libresoc.v:186868.13-186868.30" + wire width 4 $1\r7__data_o[3:0] + attribute \src "libresoc.v:186999.3-187025.6" + wire width 4 $1\reg$next[3:0]$11981 + attribute \src "libresoc.v:186874.13-186874.25" + wire width 4 $1\reg[3:0] + attribute \src "libresoc.v:186929.3-186968.6" + wire width 4 $1\src17__data_o$next[3:0]$11972 + attribute \src "libresoc.v:186879.13-186879.33" + wire width 4 $1\src17__data_o[3:0] + attribute \src "libresoc.v:187026.3-187065.6" + wire width 4 $1\src27__data_o$next[3:0]$11987 + attribute \src "libresoc.v:186886.13-186886.33" + wire width 4 $1\src27__data_o[3:0] + attribute \src "libresoc.v:187096.3-187135.6" + wire width 4 $1\src37__data_o$next[3:0]$12001 + attribute \src "libresoc.v:186893.13-186893.33" + wire width 4 $1\src37__data_o[3:0] + attribute \src "libresoc.v:187206.3-187235.6" + wire $1\wr_detect$10[0:0]$12023 + attribute \src "libresoc.v:187276.3-187305.6" + wire $1\wr_detect$13[0:0]$12037 + attribute \src "libresoc.v:187066.3-187095.6" + wire $1\wr_detect$4[0:0]$11995 + attribute \src "libresoc.v:187136.3-187165.6" + wire $1\wr_detect$7[0:0]$12009 + attribute \src "libresoc.v:186969.3-186998.6" + wire $1\wr_detect[0:0] + attribute \src "libresoc.v:187236.3-187275.6" + wire width 4 $2\r27__data_o$next[3:0]$12030 + attribute \src "libresoc.v:187166.3-187205.6" + wire width 4 $2\r7__data_o$next[3:0]$12016 + attribute \src "libresoc.v:186999.3-187025.6" + wire width 4 $2\reg$next[3:0]$11982 + attribute \src "libresoc.v:186929.3-186968.6" + wire width 4 $2\src17__data_o$next[3:0]$11973 + attribute \src "libresoc.v:187026.3-187065.6" + wire width 4 $2\src27__data_o$next[3:0]$11988 + attribute \src "libresoc.v:187096.3-187135.6" + wire width 4 $2\src37__data_o$next[3:0]$12002 + attribute \src "libresoc.v:187206.3-187235.6" + wire $2\wr_detect$10[0:0]$12024 + attribute \src "libresoc.v:187276.3-187305.6" + wire $2\wr_detect$13[0:0]$12038 + attribute \src "libresoc.v:187066.3-187095.6" + wire $2\wr_detect$4[0:0]$11996 + attribute \src "libresoc.v:187136.3-187165.6" + wire $2\wr_detect$7[0:0]$12010 + attribute \src "libresoc.v:186969.3-186998.6" + wire $2\wr_detect[0:0] + attribute \src "libresoc.v:187236.3-187275.6" + wire width 4 $3\r27__data_o$next[3:0]$12031 + attribute \src "libresoc.v:187166.3-187205.6" + wire width 4 $3\r7__data_o$next[3:0]$12017 + attribute \src "libresoc.v:186999.3-187025.6" + wire width 4 $3\reg$next[3:0]$11983 + attribute \src "libresoc.v:186929.3-186968.6" + wire width 4 $3\src17__data_o$next[3:0]$11974 + attribute \src "libresoc.v:187026.3-187065.6" + wire width 4 $3\src27__data_o$next[3:0]$11989 + attribute \src "libresoc.v:187096.3-187135.6" + wire width 4 $3\src37__data_o$next[3:0]$12003 + attribute \src "libresoc.v:187206.3-187235.6" + wire $3\wr_detect$10[0:0]$12025 + attribute \src "libresoc.v:187276.3-187305.6" + wire $3\wr_detect$13[0:0]$12039 + attribute \src "libresoc.v:187066.3-187095.6" + wire $3\wr_detect$4[0:0]$11997 + attribute \src "libresoc.v:187136.3-187165.6" + wire $3\wr_detect$7[0:0]$12011 + attribute \src "libresoc.v:186969.3-186998.6" + wire $3\wr_detect[0:0] + attribute \src "libresoc.v:187236.3-187275.6" + wire width 4 $4\r27__data_o$next[3:0]$12032 + attribute \src "libresoc.v:187166.3-187205.6" + wire width 4 $4\r7__data_o$next[3:0]$12018 + attribute \src "libresoc.v:186999.3-187025.6" + wire width 4 $4\reg$next[3:0]$11984 + attribute \src "libresoc.v:186929.3-186968.6" + wire width 4 $4\src17__data_o$next[3:0]$11975 + attribute \src "libresoc.v:187026.3-187065.6" + wire width 4 $4\src27__data_o$next[3:0]$11990 + attribute \src "libresoc.v:187096.3-187135.6" + wire width 4 $4\src37__data_o$next[3:0]$12004 + attribute \src "libresoc.v:187206.3-187235.6" + wire $4\wr_detect$10[0:0]$12026 + attribute \src "libresoc.v:187276.3-187305.6" + wire $4\wr_detect$13[0:0]$12040 + attribute \src "libresoc.v:187066.3-187095.6" + wire $4\wr_detect$4[0:0]$11998 + attribute \src "libresoc.v:187136.3-187165.6" + wire $4\wr_detect$7[0:0]$12012 + attribute \src "libresoc.v:186969.3-186998.6" + wire $4\wr_detect[0:0] + attribute \src "libresoc.v:187236.3-187275.6" + wire width 4 $5\r27__data_o$next[3:0]$12033 + attribute \src "libresoc.v:187166.3-187205.6" + wire width 4 $5\r7__data_o$next[3:0]$12019 + attribute \src "libresoc.v:186929.3-186968.6" + wire width 4 $5\src17__data_o$next[3:0]$11976 + attribute \src "libresoc.v:187026.3-187065.6" + wire width 4 $5\src27__data_o$next[3:0]$11991 + attribute \src "libresoc.v:187096.3-187135.6" + wire width 4 $5\src37__data_o$next[3:0]$12005 + attribute \src "libresoc.v:187236.3-187275.6" + wire width 4 $6\r27__data_o$next[3:0]$12034 + attribute \src "libresoc.v:187166.3-187205.6" + wire width 4 $6\r7__data_o$next[3:0]$12020 + attribute \src "libresoc.v:186929.3-186968.6" + wire width 4 $6\src17__data_o$next[3:0]$11977 + attribute \src "libresoc.v:187026.3-187065.6" + wire width 4 $6\src27__data_o$next[3:0]$11992 + attribute \src "libresoc.v:187096.3-187135.6" + wire width 4 $6\src37__data_o$next[3:0]$12006 + attribute \src "libresoc.v:186912.17-186912.104" + wire $not$libresoc.v:186912$11959_Y + attribute \src "libresoc.v:186913.18-186913.105" + wire $not$libresoc.v:186913$11960_Y + attribute \src "libresoc.v:186914.17-186914.100" + wire $not$libresoc.v:186914$11961_Y + attribute \src "libresoc.v:186915.17-186915.103" + wire $not$libresoc.v:186915$11962_Y + attribute \src "libresoc.v:186916.17-186916.103" + wire $not$libresoc.v:186916$11963_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 18 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 input 9 \dest17__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 8 \dest17__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 input 11 \dest27__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 10 \dest27__wen + attribute \src "libresoc.v:186836.7-186836.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 output 14 \r27__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 \r27__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 15 \r27__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 output 12 \r7__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 \r7__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 13 \r7__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 4 \reg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 4 \reg$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 output 3 \src17__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 \src17__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 2 \src17__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 output 5 \src27__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 \src27__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 4 \src27__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 output 7 \src37__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 \src37__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 6 \src37__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 4 input 16 \w7__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 17 \w7__wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:186912$11959 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$10 + connect \Y $not$libresoc.v:186912$11959_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:186913$11960 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$13 + connect \Y $not$libresoc.v:186913$11960_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:186914$11961 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect + connect \Y $not$libresoc.v:186914$11961_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:186915$11962 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$4 + connect \Y $not$libresoc.v:186915$11962_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$libresoc.v:186916$11963 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$7 + connect \Y $not$libresoc.v:186916$11963_Y + end + attribute \src "libresoc.v:186836.7-186836.20" + process $proc$libresoc.v:186836$12041 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:186861.13-186861.31" + process $proc$libresoc.v:186861$12042 + assign { } { } + assign $1\r27__data_o[3:0] 4'0000 + sync always + sync init + update \r27__data_o $1\r27__data_o[3:0] + end + attribute \src "libresoc.v:186868.13-186868.30" + process $proc$libresoc.v:186868$12043 + assign { } { } + assign $1\r7__data_o[3:0] 4'0000 + sync always + sync init + update \r7__data_o $1\r7__data_o[3:0] + end + attribute \src "libresoc.v:186874.13-186874.25" + process $proc$libresoc.v:186874$12044 + assign { } { } + assign $1\reg[3:0] 4'0000 + sync always + sync init + update \reg $1\reg[3:0] + end + attribute \src "libresoc.v:186879.13-186879.33" + process $proc$libresoc.v:186879$12045 + assign { } { } + assign $1\src17__data_o[3:0] 4'0000 + sync always + sync init + update \src17__data_o $1\src17__data_o[3:0] + end + attribute \src "libresoc.v:186886.13-186886.33" + process $proc$libresoc.v:186886$12046 + assign { } { } + assign $1\src27__data_o[3:0] 4'0000 + sync always + sync init + update \src27__data_o $1\src27__data_o[3:0] + end + attribute \src "libresoc.v:186893.13-186893.33" + process $proc$libresoc.v:186893$12047 + assign { } { } + assign $1\src37__data_o[3:0] 4'0000 + sync always + sync init + update \src37__data_o $1\src37__data_o[3:0] + end + attribute \src "libresoc.v:186917.3-186918.25" + process $proc$libresoc.v:186917$11964 + assign { } { } + assign $0\reg[3:0] \reg$next + sync posedge \coresync_clk + update \reg $0\reg[3:0] + end + attribute \src "libresoc.v:186919.3-186920.39" + process $proc$libresoc.v:186919$11965 + assign { } { } + assign $0\r27__data_o[3:0] \r27__data_o$next + sync posedge \coresync_clk + update \r27__data_o $0\r27__data_o[3:0] + end + attribute \src "libresoc.v:186921.3-186922.37" + process $proc$libresoc.v:186921$11966 + assign { } { } + assign $0\r7__data_o[3:0] \r7__data_o$next + sync posedge \coresync_clk + update \r7__data_o $0\r7__data_o[3:0] + end + attribute \src "libresoc.v:186923.3-186924.43" + process $proc$libresoc.v:186923$11967 + assign { } { } + assign $0\src37__data_o[3:0] \src37__data_o$next + sync posedge \coresync_clk + update \src37__data_o $0\src37__data_o[3:0] + end + attribute \src "libresoc.v:186925.3-186926.43" + process $proc$libresoc.v:186925$11968 + assign { } { } + assign $0\src27__data_o[3:0] \src27__data_o$next + sync posedge \coresync_clk + update \src27__data_o $0\src27__data_o[3:0] + end + attribute \src "libresoc.v:186927.3-186928.43" + process $proc$libresoc.v:186927$11969 + assign { } { } + assign $0\src17__data_o[3:0] \src17__data_o$next + sync posedge \coresync_clk + update \src17__data_o $0\src17__data_o[3:0] + end + attribute \src "libresoc.v:186929.3-186968.6" + process $proc$libresoc.v:186929$11970 + assign { } { } + assign { } { } + assign { } { } + assign $0\src17__data_o$next[3:0]$11971 $6\src17__data_o$next[3:0]$11977 + attribute \src "libresoc.v:186930.5-186930.29" + switch \initial + attribute \src "libresoc.v:186930.9-186930.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src17__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src17__data_o$next[3:0]$11972 $5\src17__data_o$next[3:0]$11976 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest17__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src17__data_o$next[3:0]$11973 \dest17__data_i + case + assign $2\src17__data_o$next[3:0]$11973 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest27__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src17__data_o$next[3:0]$11974 \dest27__data_i + case + assign $3\src17__data_o$next[3:0]$11974 $2\src17__data_o$next[3:0]$11973 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w7__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src17__data_o$next[3:0]$11975 \w7__data_i + case + assign $4\src17__data_o$next[3:0]$11975 $3\src17__data_o$next[3:0]$11974 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src17__data_o$next[3:0]$11976 \reg + case + assign $5\src17__data_o$next[3:0]$11976 $4\src17__data_o$next[3:0]$11975 + end + case + assign $1\src17__data_o$next[3:0]$11972 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src17__data_o$next[3:0]$11977 4'0000 + case + assign $6\src17__data_o$next[3:0]$11977 $1\src17__data_o$next[3:0]$11972 + end + sync always + update \src17__data_o$next $0\src17__data_o$next[3:0]$11971 + end + attribute \src "libresoc.v:186969.3-186998.6" + process $proc$libresoc.v:186969$11978 + assign { } { } + assign { } { } + assign $0\wr_detect[0:0] $1\wr_detect[0:0] + attribute \src "libresoc.v:186970.5-186970.29" + switch \initial + attribute \src "libresoc.v:186970.9-186970.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src17__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect[0:0] $4\wr_detect[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest17__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect[0:0] 1'1 + case + assign $2\wr_detect[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest27__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect[0:0] 1'1 + case + assign $3\wr_detect[0:0] $2\wr_detect[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w7__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect[0:0] 1'1 + case + assign $4\wr_detect[0:0] $3\wr_detect[0:0] + end + case + assign $1\wr_detect[0:0] 1'0 + end + sync always + update \wr_detect $0\wr_detect[0:0] + end + attribute \src "libresoc.v:186999.3-187025.6" + process $proc$libresoc.v:186999$11979 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\reg$next[3:0]$11980 $4\reg$next[3:0]$11984 + attribute \src "libresoc.v:187000.5-187000.29" + switch \initial + attribute \src "libresoc.v:187000.9-187000.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest17__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\reg$next[3:0]$11981 \dest17__data_i + case + assign $1\reg$next[3:0]$11981 \reg + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest27__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\reg$next[3:0]$11982 \dest27__data_i + case + assign $2\reg$next[3:0]$11982 $1\reg$next[3:0]$11981 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \w7__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\reg$next[3:0]$11983 \w7__data_i + case + assign $3\reg$next[3:0]$11983 $2\reg$next[3:0]$11982 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\reg$next[3:0]$11984 4'0000 + case + assign $4\reg$next[3:0]$11984 $3\reg$next[3:0]$11983 + end + sync always + update \reg$next $0\reg$next[3:0]$11980 + end + attribute \src "libresoc.v:187026.3-187065.6" + process $proc$libresoc.v:187026$11985 + assign { } { } + assign { } { } + assign { } { } + assign $0\src27__data_o$next[3:0]$11986 $6\src27__data_o$next[3:0]$11992 + attribute \src "libresoc.v:187027.5-187027.29" + switch \initial + attribute \src "libresoc.v:187027.9-187027.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src27__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src27__data_o$next[3:0]$11987 $5\src27__data_o$next[3:0]$11991 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest17__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src27__data_o$next[3:0]$11988 \dest17__data_i + case + assign $2\src27__data_o$next[3:0]$11988 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest27__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src27__data_o$next[3:0]$11989 \dest27__data_i + case + assign $3\src27__data_o$next[3:0]$11989 $2\src27__data_o$next[3:0]$11988 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w7__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src27__data_o$next[3:0]$11990 \w7__data_i + case + assign $4\src27__data_o$next[3:0]$11990 $3\src27__data_o$next[3:0]$11989 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src27__data_o$next[3:0]$11991 \reg + case + assign $5\src27__data_o$next[3:0]$11991 $4\src27__data_o$next[3:0]$11990 + end + case + assign $1\src27__data_o$next[3:0]$11987 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src27__data_o$next[3:0]$11992 4'0000 + case + assign $6\src27__data_o$next[3:0]$11992 $1\src27__data_o$next[3:0]$11987 + end + sync always + update \src27__data_o$next $0\src27__data_o$next[3:0]$11986 + end + attribute \src "libresoc.v:187066.3-187095.6" + process $proc$libresoc.v:187066$11993 + assign { } { } + assign { } { } + assign $0\wr_detect$4[0:0]$11994 $1\wr_detect$4[0:0]$11995 + attribute \src "libresoc.v:187067.5-187067.29" + switch \initial + attribute \src "libresoc.v:187067.9-187067.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src27__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$4[0:0]$11995 $4\wr_detect$4[0:0]$11998 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest17__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$4[0:0]$11996 1'1 + case + assign $2\wr_detect$4[0:0]$11996 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest27__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$4[0:0]$11997 1'1 + case + assign $3\wr_detect$4[0:0]$11997 $2\wr_detect$4[0:0]$11996 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w7__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$4[0:0]$11998 1'1 + case + assign $4\wr_detect$4[0:0]$11998 $3\wr_detect$4[0:0]$11997 + end + case + assign $1\wr_detect$4[0:0]$11995 1'0 + end + sync always + update \wr_detect$4 $0\wr_detect$4[0:0]$11994 + end + attribute \src "libresoc.v:187096.3-187135.6" + process $proc$libresoc.v:187096$11999 + assign { } { } + assign { } { } + assign { } { } + assign $0\src37__data_o$next[3:0]$12000 $6\src37__data_o$next[3:0]$12006 + attribute \src "libresoc.v:187097.5-187097.29" + switch \initial + attribute \src "libresoc.v:187097.9-187097.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src37__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src37__data_o$next[3:0]$12001 $5\src37__data_o$next[3:0]$12005 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest17__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src37__data_o$next[3:0]$12002 \dest17__data_i + case + assign $2\src37__data_o$next[3:0]$12002 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest27__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src37__data_o$next[3:0]$12003 \dest27__data_i + case + assign $3\src37__data_o$next[3:0]$12003 $2\src37__data_o$next[3:0]$12002 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w7__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src37__data_o$next[3:0]$12004 \w7__data_i + case + assign $4\src37__data_o$next[3:0]$12004 $3\src37__data_o$next[3:0]$12003 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$6 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src37__data_o$next[3:0]$12005 \reg + case + assign $5\src37__data_o$next[3:0]$12005 $4\src37__data_o$next[3:0]$12004 + end + case + assign $1\src37__data_o$next[3:0]$12001 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src37__data_o$next[3:0]$12006 4'0000 + case + assign $6\src37__data_o$next[3:0]$12006 $1\src37__data_o$next[3:0]$12001 + end + sync always + update \src37__data_o$next $0\src37__data_o$next[3:0]$12000 + end + attribute \src "libresoc.v:187136.3-187165.6" + process $proc$libresoc.v:187136$12007 + assign { } { } + assign { } { } + assign $0\wr_detect$7[0:0]$12008 $1\wr_detect$7[0:0]$12009 + attribute \src "libresoc.v:187137.5-187137.29" + switch \initial + attribute \src "libresoc.v:187137.9-187137.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src37__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$7[0:0]$12009 $4\wr_detect$7[0:0]$12012 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest17__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$7[0:0]$12010 1'1 + case + assign $2\wr_detect$7[0:0]$12010 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest27__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$7[0:0]$12011 1'1 + case + assign $3\wr_detect$7[0:0]$12011 $2\wr_detect$7[0:0]$12010 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w7__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$7[0:0]$12012 1'1 + case + assign $4\wr_detect$7[0:0]$12012 $3\wr_detect$7[0:0]$12011 + end + case + assign $1\wr_detect$7[0:0]$12009 1'0 + end + sync always + update \wr_detect$7 $0\wr_detect$7[0:0]$12008 + end + attribute \src "libresoc.v:187166.3-187205.6" + process $proc$libresoc.v:187166$12013 + assign { } { } + assign { } { } + assign { } { } + assign $0\r7__data_o$next[3:0]$12014 $6\r7__data_o$next[3:0]$12020 + attribute \src "libresoc.v:187167.5-187167.29" + switch \initial + attribute \src "libresoc.v:187167.9-187167.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r7__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\r7__data_o$next[3:0]$12015 $5\r7__data_o$next[3:0]$12019 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest17__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r7__data_o$next[3:0]$12016 \dest17__data_i + case + assign $2\r7__data_o$next[3:0]$12016 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest27__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\r7__data_o$next[3:0]$12017 \dest27__data_i + case + assign $3\r7__data_o$next[3:0]$12017 $2\r7__data_o$next[3:0]$12016 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w7__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\r7__data_o$next[3:0]$12018 \w7__data_i + case + assign $4\r7__data_o$next[3:0]$12018 $3\r7__data_o$next[3:0]$12017 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$9 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\r7__data_o$next[3:0]$12019 \reg + case + assign $5\r7__data_o$next[3:0]$12019 $4\r7__data_o$next[3:0]$12018 + end + case + assign $1\r7__data_o$next[3:0]$12015 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\r7__data_o$next[3:0]$12020 4'0000 + case + assign $6\r7__data_o$next[3:0]$12020 $1\r7__data_o$next[3:0]$12015 + end + sync always + update \r7__data_o$next $0\r7__data_o$next[3:0]$12014 + end + attribute \src "libresoc.v:187206.3-187235.6" + process $proc$libresoc.v:187206$12021 + assign { } { } + assign { } { } + assign $0\wr_detect$10[0:0]$12022 $1\wr_detect$10[0:0]$12023 + attribute \src "libresoc.v:187207.5-187207.29" + switch \initial + attribute \src "libresoc.v:187207.9-187207.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r7__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$10[0:0]$12023 $4\wr_detect$10[0:0]$12026 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest17__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$10[0:0]$12024 1'1 + case + assign $2\wr_detect$10[0:0]$12024 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest27__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$10[0:0]$12025 1'1 + case + assign $3\wr_detect$10[0:0]$12025 $2\wr_detect$10[0:0]$12024 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w7__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$10[0:0]$12026 1'1 + case + assign $4\wr_detect$10[0:0]$12026 $3\wr_detect$10[0:0]$12025 + end + case + assign $1\wr_detect$10[0:0]$12023 1'0 + end + sync always + update \wr_detect$10 $0\wr_detect$10[0:0]$12022 + end + attribute \src "libresoc.v:187236.3-187275.6" + process $proc$libresoc.v:187236$12027 + assign { } { } + assign { } { } + assign { } { } + assign $0\r27__data_o$next[3:0]$12028 $6\r27__data_o$next[3:0]$12034 + attribute \src "libresoc.v:187237.5-187237.29" + switch \initial + attribute \src "libresoc.v:187237.9-187237.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r27__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\r27__data_o$next[3:0]$12029 $5\r27__data_o$next[3:0]$12033 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest17__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r27__data_o$next[3:0]$12030 \dest17__data_i + case + assign $2\r27__data_o$next[3:0]$12030 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest27__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\r27__data_o$next[3:0]$12031 \dest27__data_i + case + assign $3\r27__data_o$next[3:0]$12031 $2\r27__data_o$next[3:0]$12030 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w7__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\r27__data_o$next[3:0]$12032 \w7__data_i + case + assign $4\r27__data_o$next[3:0]$12032 $3\r27__data_o$next[3:0]$12031 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$12 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\r27__data_o$next[3:0]$12033 \reg + case + assign $5\r27__data_o$next[3:0]$12033 $4\r27__data_o$next[3:0]$12032 + end + case + assign $1\r27__data_o$next[3:0]$12029 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\r27__data_o$next[3:0]$12034 4'0000 + case + assign $6\r27__data_o$next[3:0]$12034 $1\r27__data_o$next[3:0]$12029 + end + sync always + update \r27__data_o$next $0\r27__data_o$next[3:0]$12028 + end + attribute \src "libresoc.v:187276.3-187305.6" + process $proc$libresoc.v:187276$12035 + assign { } { } + assign { } { } + assign $0\wr_detect$13[0:0]$12036 $1\wr_detect$13[0:0]$12037 + attribute \src "libresoc.v:187277.5-187277.29" + switch \initial + attribute \src "libresoc.v:187277.9-187277.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r27__ren + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$13[0:0]$12037 $4\wr_detect$13[0:0]$12040 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest17__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$13[0:0]$12038 1'1 + case + assign $2\wr_detect$13[0:0]$12038 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest27__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$13[0:0]$12039 1'1 + case + assign $3\wr_detect$13[0:0]$12039 $2\wr_detect$13[0:0]$12038 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w7__wen + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$13[0:0]$12040 1'1 + case + assign $4\wr_detect$13[0:0]$12040 $3\wr_detect$13[0:0]$12039 + end + case + assign $1\wr_detect$13[0:0]$12037 1'0 + end + sync always + update \wr_detect$13 $0\wr_detect$13[0:0]$12036 + end + connect \$9 $not$libresoc.v:186912$11959_Y + connect \$12 $not$libresoc.v:186913$11960_Y + connect \$1 $not$libresoc.v:186914$11961_Y + connect \$3 $not$libresoc.v:186915$11962_Y + connect \$6 $not$libresoc.v:186916$11963_Y +end +attribute \src "libresoc.v:187310.1-187368.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.req_l" +attribute \generator "nMigen" +module \req_l + attribute \src "libresoc.v:187311.7-187311.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:187356.3-187364.6" + wire width 5 $0\q_int$next[4:0]$12058 + attribute \src "libresoc.v:187354.3-187355.27" + wire width 5 $0\q_int[4:0] + attribute \src "libresoc.v:187356.3-187364.6" + wire width 5 $1\q_int$next[4:0]$12059 + attribute \src "libresoc.v:187333.13-187333.26" + wire width 5 $1\q_int[4:0] + attribute \src "libresoc.v:187346.17-187346.96" + wire width 5 $and$libresoc.v:187346$12048_Y + attribute \src "libresoc.v:187351.17-187351.96" + wire width 5 $and$libresoc.v:187351$12053_Y + attribute \src "libresoc.v:187348.18-187348.93" + wire width 5 $not$libresoc.v:187348$12050_Y + attribute \src "libresoc.v:187350.17-187350.92" + wire width 5 $not$libresoc.v:187350$12052_Y + attribute \src "libresoc.v:187353.17-187353.92" + wire width 5 $not$libresoc.v:187353$12055_Y + attribute \src "libresoc.v:187347.18-187347.98" + wire width 5 $or$libresoc.v:187347$12049_Y + attribute \src "libresoc.v:187349.18-187349.99" + wire width 5 $or$libresoc.v:187349$12051_Y + attribute \src "libresoc.v:187352.17-187352.97" + wire width 5 $or$libresoc.v:187352$12054_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire width 5 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire width 5 \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + wire width 5 \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + wire width 5 \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire width 5 \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire width 5 \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire width 5 \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire width 5 \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 1 \coresync_rst + attribute \src "libresoc.v:187311.7-187311.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 5 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 5 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire width 5 output 2 \q_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" + wire width 5 \qlq_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 5 \qn_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 5 input 4 \r_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire width 5 input 3 \s_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:187346$12048 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:187346$12048_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:187351$12053 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:187351$12053_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:187348$12050 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \q_req + connect \Y $not$libresoc.v:187348$12050_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:187350$12052 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \r_req + connect \Y $not$libresoc.v:187350$12052_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:187353$12055 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \r_req + connect \Y $not$libresoc.v:187353$12055_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:187347$12049 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \$9 + connect \B \s_req + connect \Y $or$libresoc.v:187347$12049_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:187349$12051 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \q_req + connect \B \q_int + connect \Y $or$libresoc.v:187349$12051_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:187352$12054 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \$3 + connect \B \s_req + connect \Y $or$libresoc.v:187352$12054_Y + end + attribute \src "libresoc.v:187311.7-187311.20" + process $proc$libresoc.v:187311$12060 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:187333.13-187333.26" + process $proc$libresoc.v:187333$12061 + assign { } { } + assign $1\q_int[4:0] 5'00000 + sync always + sync init + update \q_int $1\q_int[4:0] + end + attribute \src "libresoc.v:187354.3-187355.27" + process $proc$libresoc.v:187354$12056 + assign { } { } + assign $0\q_int[4:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[4:0] + end + attribute \src "libresoc.v:187356.3-187364.6" + process $proc$libresoc.v:187356$12057 + assign { } { } + assign { } { } + assign $0\q_int$next[4:0]$12058 $1\q_int$next[4:0]$12059 + attribute \src "libresoc.v:187357.5-187357.29" + switch \initial + attribute \src "libresoc.v:187357.9-187357.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[4:0]$12059 5'00000 + case + assign $1\q_int$next[4:0]$12059 \$5 + end + sync always + update \q_int$next $0\q_int$next[4:0]$12058 + end + connect \$9 $and$libresoc.v:187346$12048_Y + connect \$11 $or$libresoc.v:187347$12049_Y + connect \$13 $not$libresoc.v:187348$12050_Y + connect \$15 $or$libresoc.v:187349$12051_Y + connect \$1 $not$libresoc.v:187350$12052_Y + connect \$3 $and$libresoc.v:187351$12053_Y + connect \$5 $or$libresoc.v:187352$12054_Y + connect \$7 $not$libresoc.v:187353$12055_Y + connect \qlq_req \$15 + connect \qn_req \$13 + connect \q_req \$11 +end +attribute \src "libresoc.v:187372.1-187430.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.req_l" +attribute \generator "nMigen" +module \req_l$103 + attribute \src "libresoc.v:187373.7-187373.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:187418.3-187426.6" + wire width 4 $0\q_int$next[3:0]$12072 + attribute \src "libresoc.v:187416.3-187417.27" + wire width 4 $0\q_int[3:0] + attribute \src "libresoc.v:187418.3-187426.6" + wire width 4 $1\q_int$next[3:0]$12073 + attribute \src "libresoc.v:187395.13-187395.25" + wire width 4 $1\q_int[3:0] + attribute \src "libresoc.v:187408.17-187408.96" + wire width 4 $and$libresoc.v:187408$12062_Y + attribute \src "libresoc.v:187413.17-187413.96" + wire width 4 $and$libresoc.v:187413$12067_Y + attribute \src "libresoc.v:187410.18-187410.93" + wire width 4 $not$libresoc.v:187410$12064_Y + attribute \src "libresoc.v:187412.17-187412.92" + wire width 4 $not$libresoc.v:187412$12066_Y + attribute \src "libresoc.v:187415.17-187415.92" + wire width 4 $not$libresoc.v:187415$12069_Y + attribute \src "libresoc.v:187409.18-187409.98" + wire width 4 $or$libresoc.v:187409$12063_Y + attribute \src "libresoc.v:187411.18-187411.99" + wire width 4 $or$libresoc.v:187411$12065_Y + attribute \src "libresoc.v:187414.17-187414.97" + wire width 4 $or$libresoc.v:187414$12068_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire width 4 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire width 4 \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + wire width 4 \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + wire width 4 \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire width 4 \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire width 4 \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire width 4 \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire width 4 \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 1 \coresync_rst + attribute \src "libresoc.v:187373.7-187373.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 4 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 4 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire width 4 output 2 \q_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" + wire width 4 \qlq_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 4 \qn_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 4 input 4 \r_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire width 4 input 3 \s_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:187408$12062 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:187408$12062_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:187413$12067 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:187413$12067_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:187410$12064 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \q_req + connect \Y $not$libresoc.v:187410$12064_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:187412$12066 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \r_req + connect \Y $not$libresoc.v:187412$12066_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:187415$12069 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \r_req + connect \Y $not$libresoc.v:187415$12069_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:187409$12063 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \$9 + connect \B \s_req + connect \Y $or$libresoc.v:187409$12063_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:187411$12065 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \q_req + connect \B \q_int + connect \Y $or$libresoc.v:187411$12065_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:187414$12068 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \$3 + connect \B \s_req + connect \Y $or$libresoc.v:187414$12068_Y + end + attribute \src "libresoc.v:187373.7-187373.20" + process $proc$libresoc.v:187373$12074 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:187395.13-187395.25" + process $proc$libresoc.v:187395$12075 + assign { } { } + assign $1\q_int[3:0] 4'0000 + sync always + sync init + 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$not$libresoc.v:187410$12064_Y + connect \$15 $or$libresoc.v:187411$12065_Y + connect \$1 $not$libresoc.v:187412$12066_Y + connect \$3 $and$libresoc.v:187413$12067_Y + connect \$5 $or$libresoc.v:187414$12068_Y + connect \$7 $not$libresoc.v:187415$12069_Y + connect \qlq_req \$15 + connect \qn_req \$13 + connect \q_req \$11 +end +attribute \src "libresoc.v:187434.1-187492.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.req_l" +attribute \generator "nMigen" +module \req_l$12 + attribute \src "libresoc.v:187435.7-187435.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:187480.3-187488.6" + wire width 3 $0\q_int$next[2:0]$12086 + attribute \src "libresoc.v:187478.3-187479.27" + wire width 3 $0\q_int[2:0] + attribute \src "libresoc.v:187480.3-187488.6" + wire width 3 $1\q_int$next[2:0]$12087 + attribute \src "libresoc.v:187457.13-187457.25" + wire width 3 $1\q_int[2:0] + attribute \src "libresoc.v:187470.17-187470.96" + wire width 3 $and$libresoc.v:187470$12076_Y + attribute \src "libresoc.v:187475.17-187475.96" + wire width 3 $and$libresoc.v:187475$12081_Y + attribute \src "libresoc.v:187472.18-187472.93" + wire width 3 $not$libresoc.v:187472$12078_Y + attribute \src "libresoc.v:187474.17-187474.92" + wire width 3 $not$libresoc.v:187474$12080_Y + attribute \src "libresoc.v:187477.17-187477.92" + wire width 3 $not$libresoc.v:187477$12083_Y + attribute \src "libresoc.v:187471.18-187471.98" + wire width 3 $or$libresoc.v:187471$12077_Y + attribute \src "libresoc.v:187473.18-187473.99" + wire width 3 $or$libresoc.v:187473$12079_Y + attribute \src "libresoc.v:187476.17-187476.97" + wire width 3 $or$libresoc.v:187476$12082_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire width 3 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire width 3 \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + wire width 3 \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + wire width 3 \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire width 3 \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire width 3 \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire width 3 \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire width 3 \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 1 \coresync_rst + attribute \src "libresoc.v:187435.7-187435.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 3 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 3 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire width 3 output 2 \q_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" + wire width 3 \qlq_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 3 \qn_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 3 input 4 \r_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire width 3 input 3 \s_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:187470$12076 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:187470$12076_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:187475$12081 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:187475$12081_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:187472$12078 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_req + connect \Y $not$libresoc.v:187472$12078_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:187474$12080 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \r_req + connect \Y $not$libresoc.v:187474$12080_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:187477$12083 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \r_req + connect \Y $not$libresoc.v:187477$12083_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:187471$12077 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \$9 + connect \B \s_req + connect \Y $or$libresoc.v:187471$12077_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:187473$12079 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_req + connect \B \q_int + connect \Y $or$libresoc.v:187473$12079_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:187476$12082 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \$3 + connect \B \s_req + connect \Y $or$libresoc.v:187476$12082_Y + end + attribute \src "libresoc.v:187435.7-187435.20" + process $proc$libresoc.v:187435$12088 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:187457.13-187457.25" + process $proc$libresoc.v:187457$12089 + assign { } { } + assign $1\q_int[2:0] 3'000 + sync always + sync init + update \q_int $1\q_int[2:0] + end + attribute \src "libresoc.v:187478.3-187479.27" + process $proc$libresoc.v:187478$12084 + assign { } { } + assign $0\q_int[2:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[2:0] + end + attribute \src "libresoc.v:187480.3-187488.6" + process $proc$libresoc.v:187480$12085 + assign { } { } + assign { } { } + assign $0\q_int$next[2:0]$12086 $1\q_int$next[2:0]$12087 + attribute \src "libresoc.v:187481.5-187481.29" + switch \initial + attribute \src "libresoc.v:187481.9-187481.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[2:0]$12087 3'000 + case + assign $1\q_int$next[2:0]$12087 \$5 + end + sync always + update \q_int$next $0\q_int$next[2:0]$12086 + end + connect \$9 $and$libresoc.v:187470$12076_Y + connect \$11 $or$libresoc.v:187471$12077_Y + connect \$13 $not$libresoc.v:187472$12078_Y + connect \$15 $or$libresoc.v:187473$12079_Y + connect \$1 $not$libresoc.v:187474$12080_Y + connect \$3 $and$libresoc.v:187475$12081_Y + connect \$5 $or$libresoc.v:187476$12082_Y + connect \$7 $not$libresoc.v:187477$12083_Y + connect \qlq_req \$15 + connect \qn_req \$13 + connect \q_req \$11 +end +attribute \src "libresoc.v:187496.1-187554.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.req_l" +attribute \generator "nMigen" +module \req_l$121 + attribute \src "libresoc.v:187497.7-187497.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:187542.3-187550.6" + wire width 3 $0\q_int$next[2:0]$12100 + attribute \src "libresoc.v:187540.3-187541.27" + wire width 3 $0\q_int[2:0] + attribute \src "libresoc.v:187542.3-187550.6" + wire width 3 $1\q_int$next[2:0]$12101 + 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"/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire width 3 \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + wire width 3 \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + wire width 3 \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire width 3 \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire width 3 \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire width 3 \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire width 3 \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 1 \coresync_rst + attribute \src "libresoc.v:187497.7-187497.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 3 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 3 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire width 3 output 2 \q_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" + wire width 3 \qlq_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 3 \qn_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 3 input 4 \r_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire width 3 input 3 \s_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:187532$12090 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:187532$12090_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:187537$12095 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:187537$12095_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:187534$12092 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_req + connect \Y $not$libresoc.v:187534$12092_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:187536$12094 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \r_req + connect \Y $not$libresoc.v:187536$12094_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:187539$12097 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \r_req + connect \Y $not$libresoc.v:187539$12097_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:187533$12091 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \$9 + connect \B \s_req + connect \Y $or$libresoc.v:187533$12091_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:187535$12093 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_req + connect \B \q_int + connect \Y $or$libresoc.v:187535$12093_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:187538$12096 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \$3 + connect \B \s_req + connect \Y $or$libresoc.v:187538$12096_Y + end + attribute \src "libresoc.v:187497.7-187497.20" + process $proc$libresoc.v:187497$12102 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:187519.13-187519.25" + process $proc$libresoc.v:187519$12103 + assign { } { } + assign $1\q_int[2:0] 3'000 + sync always + sync init + update \q_int $1\q_int[2:0] + end + attribute \src "libresoc.v:187540.3-187541.27" + process $proc$libresoc.v:187540$12098 + assign { } { } + assign $0\q_int[2:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[2:0] + end + attribute \src "libresoc.v:187542.3-187550.6" + process $proc$libresoc.v:187542$12099 + assign { } { } + assign { } { } + assign $0\q_int$next[2:0]$12100 $1\q_int$next[2:0]$12101 + attribute \src "libresoc.v:187543.5-187543.29" + switch \initial + attribute \src "libresoc.v:187543.9-187543.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[2:0]$12101 3'000 + case + assign $1\q_int$next[2:0]$12101 \$5 + end + sync always + update \q_int$next $0\q_int$next[2:0]$12100 + end + connect \$9 $and$libresoc.v:187532$12090_Y + connect \$11 $or$libresoc.v:187533$12091_Y + connect \$13 $not$libresoc.v:187534$12092_Y + connect \$15 $or$libresoc.v:187535$12093_Y + connect \$1 $not$libresoc.v:187536$12094_Y + connect \$3 $and$libresoc.v:187537$12095_Y + connect \$5 $or$libresoc.v:187538$12096_Y + connect \$7 $not$libresoc.v:187539$12097_Y + connect \qlq_req \$15 + connect \qn_req \$13 + connect \q_req \$11 +end +attribute \src "libresoc.v:187558.1-187616.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.req_l" +attribute \generator "nMigen" +module \req_l$25 + attribute \src "libresoc.v:187559.7-187559.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:187604.3-187612.6" + wire width 3 $0\q_int$next[2:0]$12114 + attribute \src "libresoc.v:187602.3-187603.27" + wire width 3 $0\q_int[2:0] + attribute \src "libresoc.v:187604.3-187612.6" + wire width 3 $1\q_int$next[2:0]$12115 + attribute \src "libresoc.v:187581.13-187581.25" + wire width 3 $1\q_int[2:0] + attribute \src "libresoc.v:187594.17-187594.96" + wire width 3 $and$libresoc.v:187594$12104_Y + attribute \src "libresoc.v:187599.17-187599.96" + wire width 3 $and$libresoc.v:187599$12109_Y + attribute \src "libresoc.v:187596.18-187596.93" + wire width 3 $not$libresoc.v:187596$12106_Y + attribute \src "libresoc.v:187598.17-187598.92" + wire width 3 $not$libresoc.v:187598$12108_Y + attribute \src "libresoc.v:187601.17-187601.92" + wire width 3 $not$libresoc.v:187601$12111_Y + attribute \src "libresoc.v:187595.18-187595.98" + wire width 3 $or$libresoc.v:187595$12105_Y + attribute \src "libresoc.v:187597.18-187597.99" + wire width 3 $or$libresoc.v:187597$12107_Y + attribute \src "libresoc.v:187600.17-187600.97" + wire width 3 $or$libresoc.v:187600$12110_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire width 3 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire width 3 \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + wire width 3 \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + wire width 3 \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire width 3 \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire width 3 \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire width 3 \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire width 3 \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 1 \coresync_rst + attribute \src "libresoc.v:187559.7-187559.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 3 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 3 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire width 3 output 2 \q_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" + wire width 3 \qlq_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 3 \qn_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 3 input 4 \r_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire width 3 input 3 \s_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:187594$12104 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:187594$12104_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:187599$12109 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:187599$12109_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:187596$12106 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_req + connect \Y $not$libresoc.v:187596$12106_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:187598$12108 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \r_req + connect \Y $not$libresoc.v:187598$12108_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:187601$12111 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \r_req + connect \Y $not$libresoc.v:187601$12111_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:187595$12105 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \$9 + connect \B \s_req + connect \Y $or$libresoc.v:187595$12105_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:187597$12107 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_req + connect \B \q_int + connect \Y $or$libresoc.v:187597$12107_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:187600$12110 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \$3 + connect \B \s_req + connect \Y $or$libresoc.v:187600$12110_Y + end + attribute \src "libresoc.v:187559.7-187559.20" + process $proc$libresoc.v:187559$12116 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:187581.13-187581.25" + process $proc$libresoc.v:187581$12117 + assign { } { } + assign $1\q_int[2:0] 3'000 + sync always + sync init + update \q_int $1\q_int[2:0] + end + attribute \src "libresoc.v:187602.3-187603.27" + process $proc$libresoc.v:187602$12112 + assign { } { } + assign $0\q_int[2:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[2:0] + end + attribute \src "libresoc.v:187604.3-187612.6" + process $proc$libresoc.v:187604$12113 + assign { } { } + assign { } { } + assign $0\q_int$next[2:0]$12114 $1\q_int$next[2:0]$12115 + attribute \src "libresoc.v:187605.5-187605.29" + switch \initial + attribute \src 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\req_l$41 + attribute \src "libresoc.v:187621.7-187621.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:187666.3-187674.6" + wire width 5 $0\q_int$next[4:0]$12128 + attribute \src "libresoc.v:187664.3-187665.27" + wire width 5 $0\q_int[4:0] + attribute \src "libresoc.v:187666.3-187674.6" + wire width 5 $1\q_int$next[4:0]$12129 + attribute \src "libresoc.v:187643.13-187643.26" + wire width 5 $1\q_int[4:0] + attribute \src "libresoc.v:187656.17-187656.96" + wire width 5 $and$libresoc.v:187656$12118_Y + attribute \src "libresoc.v:187661.17-187661.96" + wire width 5 $and$libresoc.v:187661$12123_Y + attribute \src "libresoc.v:187658.18-187658.93" + wire width 5 $not$libresoc.v:187658$12120_Y + attribute \src "libresoc.v:187660.17-187660.92" + wire width 5 $not$libresoc.v:187660$12122_Y + attribute \src "libresoc.v:187663.17-187663.92" + wire width 5 $not$libresoc.v:187663$12125_Y + attribute \src "libresoc.v:187657.18-187657.98" + wire width 5 $or$libresoc.v:187657$12119_Y + attribute \src "libresoc.v:187659.18-187659.99" + wire width 5 $or$libresoc.v:187659$12121_Y + attribute \src "libresoc.v:187662.17-187662.97" + wire width 5 $or$libresoc.v:187662$12124_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire width 5 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire width 5 \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + wire width 5 \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + wire width 5 \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire width 5 \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire width 5 \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire width 5 \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire width 5 \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 1 \coresync_rst + attribute \src "libresoc.v:187621.7-187621.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 5 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 5 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire width 5 output 2 \q_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" + wire width 5 \qlq_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 5 \qn_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 5 input 4 \r_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire width 5 input 3 \s_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:187656$12118 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:187656$12118_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:187661$12123 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:187661$12123_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:187658$12120 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \q_req + connect \Y $not$libresoc.v:187658$12120_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:187660$12122 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \r_req + connect \Y $not$libresoc.v:187660$12122_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:187663$12125 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \r_req + connect \Y $not$libresoc.v:187663$12125_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:187657$12119 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \$9 + connect \B \s_req + connect \Y $or$libresoc.v:187657$12119_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:187659$12121 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \q_req + connect \B \q_int + connect \Y $or$libresoc.v:187659$12121_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:187662$12124 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \$3 + connect \B \s_req + connect \Y $or$libresoc.v:187662$12124_Y + end + attribute \src "libresoc.v:187621.7-187621.20" + process $proc$libresoc.v:187621$12130 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:187643.13-187643.26" + process $proc$libresoc.v:187643$12131 + assign { } { } + assign $1\q_int[4:0] 5'00000 + sync always + sync init + update \q_int $1\q_int[4:0] + end + attribute \src "libresoc.v:187664.3-187665.27" + process $proc$libresoc.v:187664$12126 + assign { } { } + assign $0\q_int[4:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[4:0] + end + attribute \src "libresoc.v:187666.3-187674.6" + process $proc$libresoc.v:187666$12127 + assign { } { } + assign { } { } + assign $0\q_int$next[4:0]$12128 $1\q_int$next[4:0]$12129 + attribute \src "libresoc.v:187667.5-187667.29" + switch \initial + attribute \src "libresoc.v:187667.9-187667.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[4:0]$12129 5'00000 + case + assign $1\q_int$next[4:0]$12129 \$5 + end + sync always + update \q_int$next $0\q_int$next[4:0]$12128 + end + connect \$9 $and$libresoc.v:187656$12118_Y + connect \$11 $or$libresoc.v:187657$12119_Y + connect \$13 $not$libresoc.v:187658$12120_Y + connect \$15 $or$libresoc.v:187659$12121_Y + connect \$1 $not$libresoc.v:187660$12122_Y + connect \$3 $and$libresoc.v:187661$12123_Y + connect \$5 $or$libresoc.v:187662$12124_Y + connect \$7 $not$libresoc.v:187663$12125_Y + connect \qlq_req \$15 + connect \qn_req \$13 + connect \q_req \$11 +end +attribute \src "libresoc.v:187682.1-187740.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.req_l" +attribute \generator "nMigen" +module \req_l$57 + attribute \src "libresoc.v:187683.7-187683.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:187728.3-187736.6" + wire width 2 $0\q_int$next[1:0]$12142 + attribute \src "libresoc.v:187726.3-187727.27" + wire width 2 $0\q_int[1:0] + attribute \src "libresoc.v:187728.3-187736.6" + wire width 2 $1\q_int$next[1:0]$12143 + attribute \src "libresoc.v:187705.13-187705.25" + wire width 2 $1\q_int[1:0] + attribute \src "libresoc.v:187718.17-187718.96" + wire width 2 $and$libresoc.v:187718$12132_Y + attribute \src "libresoc.v:187723.17-187723.96" + wire width 2 $and$libresoc.v:187723$12137_Y + attribute \src "libresoc.v:187720.18-187720.93" + wire width 2 $not$libresoc.v:187720$12134_Y + attribute \src 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\Y_WIDTH 2 + connect \A \q_req + connect \Y $not$libresoc.v:187720$12134_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:187722$12136 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \r_req + connect \Y $not$libresoc.v:187722$12136_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:187725$12139 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \r_req + connect \Y $not$libresoc.v:187725$12139_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:187719$12133 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \$9 + connect \B \s_req + connect \Y $or$libresoc.v:187719$12133_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:187721$12135 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \q_req + connect \B \q_int + connect \Y $or$libresoc.v:187721$12135_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:187724$12138 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \$3 + connect \B \s_req + connect \Y $or$libresoc.v:187724$12138_Y + end + attribute \src "libresoc.v:187683.7-187683.20" + process $proc$libresoc.v:187683$12144 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:187705.13-187705.25" + process $proc$libresoc.v:187705$12145 + assign { } { } + assign $1\q_int[1:0] 2'00 + sync always + sync init + update \q_int $1\q_int[1:0] + end + attribute \src "libresoc.v:187726.3-187727.27" + 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wire width 6 \qlq_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 6 \qn_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 6 input 4 \r_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire width 6 input 3 \s_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:187780$12146 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:187780$12146_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:187785$12151 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:187785$12151_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:187782$12148 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \q_req + connect \Y $not$libresoc.v:187782$12148_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:187784$12150 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \r_req + connect \Y $not$libresoc.v:187784$12150_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:187787$12153 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \r_req + connect \Y $not$libresoc.v:187787$12153_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:187781$12147 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \$9 + connect \B \s_req + connect \Y $or$libresoc.v:187781$12147_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:187783$12149 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \q_req + connect \B \q_int + connect \Y $or$libresoc.v:187783$12149_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:187786$12152 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \$3 + connect \B \s_req + connect \Y $or$libresoc.v:187786$12152_Y + end + attribute \src "libresoc.v:187745.7-187745.20" + process $proc$libresoc.v:187745$12158 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:187767.13-187767.26" + process $proc$libresoc.v:187767$12159 + assign { } { } + assign $1\q_int[5:0] 6'000000 + sync always + sync init + update \q_int $1\q_int[5:0] + end + attribute \src "libresoc.v:187788.3-187789.27" + process $proc$libresoc.v:187788$12154 + assign { } { } + assign $0\q_int[5:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[5:0] + end + attribute \src "libresoc.v:187790.3-187798.6" + process $proc$libresoc.v:187790$12155 + assign { } { } + assign { } { } + assign $0\q_int$next[5:0]$12156 $1\q_int$next[5:0]$12157 + attribute \src "libresoc.v:187791.5-187791.29" + switch \initial + attribute \src "libresoc.v:187791.9-187791.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[5:0]$12157 6'000000 + case + assign $1\q_int$next[5:0]$12157 \$5 + end + sync always + update \q_int$next $0\q_int$next[5:0]$12156 + end + connect \$9 $and$libresoc.v:187780$12146_Y + connect \$11 $or$libresoc.v:187781$12147_Y + connect \$13 $not$libresoc.v:187782$12148_Y + connect \$15 $or$libresoc.v:187783$12149_Y + connect \$1 $not$libresoc.v:187784$12150_Y + connect \$3 $and$libresoc.v:187785$12151_Y + connect \$5 $or$libresoc.v:187786$12152_Y + connect \$7 $not$libresoc.v:187787$12153_Y + connect \qlq_req \$15 + connect \qn_req \$13 + connect \q_req \$11 +end +attribute \src "libresoc.v:187806.1-187864.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.req_l" +attribute \generator "nMigen" +module \req_l$86 + attribute \src "libresoc.v:187807.7-187807.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:187852.3-187860.6" + wire width 4 $0\q_int$next[3:0]$12170 + attribute \src "libresoc.v:187850.3-187851.27" + wire width 4 $0\q_int[3:0] + attribute \src "libresoc.v:187852.3-187860.6" + wire width 4 $1\q_int$next[3:0]$12171 + attribute \src "libresoc.v:187829.13-187829.25" + wire width 4 $1\q_int[3:0] + attribute \src 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\q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire width 4 output 2 \q_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" + wire width 4 \qlq_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 4 \qn_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 4 input 4 \r_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire width 4 input 3 \s_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:187842$12160 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:187842$12160_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:187847$12165 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:187847$12165_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:187844$12162 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \q_req + connect \Y $not$libresoc.v:187844$12162_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:187846$12164 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \r_req + connect \Y $not$libresoc.v:187846$12164_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:187849$12167 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \r_req + connect \Y $not$libresoc.v:187849$12167_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:187843$12161 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \$9 + connect \B \s_req + connect \Y $or$libresoc.v:187843$12161_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:187845$12163 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \q_req + connect \B \q_int + connect \Y $or$libresoc.v:187845$12163_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:187848$12166 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \$3 + connect \B \s_req + connect \Y $or$libresoc.v:187848$12166_Y + end + attribute \src "libresoc.v:187807.7-187807.20" + process $proc$libresoc.v:187807$12172 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:187829.13-187829.25" + process $proc$libresoc.v:187829$12173 + assign { } { } + assign $1\q_int[3:0] 4'0000 + sync always + sync init + update \q_int $1\q_int[3:0] + end + attribute \src "libresoc.v:187850.3-187851.27" + process $proc$libresoc.v:187850$12168 + assign { } { } + assign $0\q_int[3:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[3:0] + end + attribute \src "libresoc.v:187852.3-187860.6" + process $proc$libresoc.v:187852$12169 + assign { } { } + assign { } { } + assign $0\q_int$next[3:0]$12170 $1\q_int$next[3:0]$12171 + attribute \src "libresoc.v:187853.5-187853.29" + switch \initial + attribute \src "libresoc.v:187853.9-187853.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[3:0]$12171 4'0000 + case + assign $1\q_int$next[3:0]$12171 \$5 + end + sync always + update \q_int$next $0\q_int$next[3:0]$12170 + end + connect \$9 $and$libresoc.v:187842$12160_Y + connect \$11 $or$libresoc.v:187843$12161_Y + connect \$13 $not$libresoc.v:187844$12162_Y + connect \$15 $or$libresoc.v:187845$12163_Y + connect \$1 $not$libresoc.v:187846$12164_Y + connect \$3 $and$libresoc.v:187847$12165_Y + connect \$5 $or$libresoc.v:187848$12166_Y + connect \$7 $not$libresoc.v:187849$12167_Y + connect \qlq_req \$15 + connect \qn_req \$13 + connect \q_req \$11 +end +attribute \src "libresoc.v:187868.1-187917.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem.reset_l" +attribute \generator "nMigen" +module \reset_l + attribute \src "libresoc.v:187869.7-187869.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:187905.3-187913.6" + wire $0\q_int$next[0:0]$12181 + attribute \src "libresoc.v:187903.3-187904.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:187905.3-187913.6" + wire $1\q_int$next[0:0]$12182 + attribute \src "libresoc.v:187885.7-187885.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:187900.17-187900.96" + wire $and$libresoc.v:187900$12176_Y + attribute \src "libresoc.v:187899.17-187899.94" + wire $not$libresoc.v:187899$12175_Y + attribute \src "libresoc.v:187902.17-187902.94" + wire $not$libresoc.v:187902$12178_Y + attribute \src "libresoc.v:187898.17-187898.100" + wire $or$libresoc.v:187898$12174_Y + attribute \src "libresoc.v:187901.17-187901.99" + wire $or$libresoc.v:187901$12177_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 1 \coresync_rst + attribute \src "libresoc.v:187869.7-187869.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire output 4 \q_reset + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" + wire \qlq_reset + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \qn_reset + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire input 3 \r_reset + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire input 2 \s_reset + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:187900$12176 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:187900$12176_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:187899$12175 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_reset + connect \Y $not$libresoc.v:187899$12175_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:187902$12178 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_reset + connect \Y $not$libresoc.v:187902$12178_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:187898$12174 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_reset + connect \B \q_int + connect \Y $or$libresoc.v:187898$12174_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:187901$12177 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_reset + connect \Y $or$libresoc.v:187901$12177_Y + end + attribute \src "libresoc.v:187869.7-187869.20" + process $proc$libresoc.v:187869$12183 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:187885.7-187885.19" + process $proc$libresoc.v:187885$12184 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:187903.3-187904.27" + process $proc$libresoc.v:187903$12179 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:187905.3-187913.6" + process $proc$libresoc.v:187905$12180 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$12181 $1\q_int$next[0:0]$12182 + attribute \src "libresoc.v:187906.5-187906.29" + switch \initial + attribute \src "libresoc.v:187906.9-187906.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$12182 1'0 + case + assign $1\q_int$next[0:0]$12182 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$12181 + end + connect \$9 $or$libresoc.v:187898$12174_Y + connect \$1 $not$libresoc.v:187899$12175_Y + connect \$3 $and$libresoc.v:187900$12176_Y + connect \$5 $or$libresoc.v:187901$12177_Y + connect \$7 $not$libresoc.v:187902$12178_Y + connect \qlq_reset \$9 + connect \qn_reset \$7 + connect \q_reset \q_int +end +attribute \src "libresoc.v:187921.1-187970.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.l0.l0.reset_l" +attribute \generator "nMigen" +module \reset_l$131 + attribute \src "libresoc.v:187922.7-187922.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:187958.3-187966.6" + wire $0\q_int$next[0:0]$12192 + attribute \src "libresoc.v:187956.3-187957.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:187958.3-187966.6" + wire $1\q_int$next[0:0]$12193 + attribute \src "libresoc.v:187938.7-187938.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:187953.17-187953.96" + wire $and$libresoc.v:187953$12187_Y + attribute \src "libresoc.v:187952.17-187952.94" + wire $not$libresoc.v:187952$12186_Y + attribute \src "libresoc.v:187955.17-187955.94" + wire $not$libresoc.v:187955$12189_Y + attribute \src "libresoc.v:187951.17-187951.100" + wire $or$libresoc.v:187951$12185_Y + attribute \src "libresoc.v:187954.17-187954.99" + wire $or$libresoc.v:187954$12188_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 1 \coresync_rst + attribute \src "libresoc.v:187922.7-187922.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire output 4 \q_reset + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" + wire \qlq_reset + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \qn_reset + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire input 3 \r_reset + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire input 2 \s_reset + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:187953$12187 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:187953$12187_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:187952$12186 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_reset + connect \Y $not$libresoc.v:187952$12186_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:187955$12189 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_reset + connect \Y $not$libresoc.v:187955$12189_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:187951$12185 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_reset + connect \B \q_int + connect \Y $or$libresoc.v:187951$12185_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:187954$12188 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_reset + connect \Y $or$libresoc.v:187954$12188_Y + end + attribute \src "libresoc.v:187922.7-187922.20" + process $proc$libresoc.v:187922$12194 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:187938.7-187938.19" + process $proc$libresoc.v:187938$12195 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:187956.3-187957.27" + process $proc$libresoc.v:187956$12190 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:187958.3-187966.6" + process $proc$libresoc.v:187958$12191 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$12192 $1\q_int$next[0:0]$12193 + attribute \src "libresoc.v:187959.5-187959.29" + switch \initial + attribute \src "libresoc.v:187959.9-187959.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$12193 1'0 + case + assign $1\q_int$next[0:0]$12193 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$12192 + end + connect \$9 $or$libresoc.v:187951$12185_Y + connect \$1 $not$libresoc.v:187952$12186_Y + connect \$3 $and$libresoc.v:187953$12187_Y + connect \$5 $or$libresoc.v:187954$12188_Y + connect \$7 $not$libresoc.v:187955$12189_Y + connect \qlq_reset \$9 + connect \qn_reset \$7 + connect \q_reset \q_int +end +attribute \src "libresoc.v:187974.1-188561.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1.main.rotator.right_mask" +attribute \generator "nMigen" +module \right_mask + attribute \src "libresoc.v:187975.7-187975.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:188173.3-188560.6" + wire width 64 $0\mask[63:0] + attribute \src "libresoc.v:188173.3-188560.6" + wire $10\mask[9:9] + attribute \src "libresoc.v:188173.3-188560.6" + wire $11\mask[10:10] + attribute \src "libresoc.v:188173.3-188560.6" + wire $12\mask[11:11] + attribute \src "libresoc.v:188173.3-188560.6" + wire $13\mask[12:12] + attribute \src "libresoc.v:188173.3-188560.6" + wire $14\mask[13:13] + attribute \src "libresoc.v:188173.3-188560.6" + wire $15\mask[14:14] + attribute \src "libresoc.v:188173.3-188560.6" + wire $16\mask[15:15] + attribute \src "libresoc.v:188173.3-188560.6" + wire $17\mask[16:16] + attribute \src "libresoc.v:188173.3-188560.6" + wire $18\mask[17:17] + attribute \src "libresoc.v:188173.3-188560.6" + wire $19\mask[18:18] + attribute \src "libresoc.v:188173.3-188560.6" + wire $1\mask[0:0] + attribute \src "libresoc.v:188173.3-188560.6" + wire $20\mask[19:19] + attribute \src "libresoc.v:188173.3-188560.6" + wire $21\mask[20:20] + attribute \src "libresoc.v:188173.3-188560.6" + wire $22\mask[21:21] + attribute \src "libresoc.v:188173.3-188560.6" + wire $23\mask[22:22] + attribute \src "libresoc.v:188173.3-188560.6" + wire $24\mask[23:23] + attribute \src "libresoc.v:188173.3-188560.6" + wire $25\mask[24:24] + attribute \src "libresoc.v:188173.3-188560.6" + wire $26\mask[25:25] + attribute \src "libresoc.v:188173.3-188560.6" + wire $27\mask[26:26] + attribute \src "libresoc.v:188173.3-188560.6" + wire $28\mask[27:27] + attribute \src "libresoc.v:188173.3-188560.6" + wire $29\mask[28:28] + attribute \src "libresoc.v:188173.3-188560.6" + wire $2\mask[1:1] + attribute \src "libresoc.v:188173.3-188560.6" + wire $30\mask[29:29] + attribute \src "libresoc.v:188173.3-188560.6" + wire $31\mask[30:30] + attribute \src "libresoc.v:188173.3-188560.6" + wire $32\mask[31:31] + attribute \src "libresoc.v:188173.3-188560.6" + wire $33\mask[32:32] + attribute \src "libresoc.v:188173.3-188560.6" + wire $34\mask[33:33] + attribute \src "libresoc.v:188173.3-188560.6" + wire $35\mask[34:34] + attribute \src "libresoc.v:188173.3-188560.6" + wire $36\mask[35:35] + attribute \src "libresoc.v:188173.3-188560.6" + wire $37\mask[36:36] + attribute \src "libresoc.v:188173.3-188560.6" + wire $38\mask[37:37] + attribute \src "libresoc.v:188173.3-188560.6" + wire $39\mask[38:38] + attribute \src "libresoc.v:188173.3-188560.6" + wire $3\mask[2:2] + attribute \src "libresoc.v:188173.3-188560.6" + wire $40\mask[39:39] + attribute \src "libresoc.v:188173.3-188560.6" + wire $41\mask[40:40] + attribute \src "libresoc.v:188173.3-188560.6" + wire $42\mask[41:41] + attribute \src "libresoc.v:188173.3-188560.6" + wire $43\mask[42:42] + attribute \src "libresoc.v:188173.3-188560.6" + wire $44\mask[43:43] + attribute \src "libresoc.v:188173.3-188560.6" + wire $45\mask[44:44] + attribute \src "libresoc.v:188173.3-188560.6" + wire $46\mask[45:45] + attribute \src "libresoc.v:188173.3-188560.6" + wire $47\mask[46:46] + attribute \src "libresoc.v:188173.3-188560.6" + wire $48\mask[47:47] + attribute \src "libresoc.v:188173.3-188560.6" + wire $49\mask[48:48] + attribute \src "libresoc.v:188173.3-188560.6" + wire $4\mask[3:3] + attribute \src "libresoc.v:188173.3-188560.6" + wire $50\mask[49:49] + attribute \src "libresoc.v:188173.3-188560.6" + wire $51\mask[50:50] + attribute \src "libresoc.v:188173.3-188560.6" + wire $52\mask[51:51] + attribute \src "libresoc.v:188173.3-188560.6" + wire $53\mask[52:52] + attribute \src "libresoc.v:188173.3-188560.6" + wire $54\mask[53:53] + attribute \src "libresoc.v:188173.3-188560.6" + wire $55\mask[54:54] + attribute \src "libresoc.v:188173.3-188560.6" + wire $56\mask[55:55] + attribute \src "libresoc.v:188173.3-188560.6" + wire $57\mask[56:56] + attribute \src "libresoc.v:188173.3-188560.6" + wire $58\mask[57:57] + attribute \src "libresoc.v:188173.3-188560.6" + wire $59\mask[58:58] + attribute \src "libresoc.v:188173.3-188560.6" + wire $5\mask[4:4] + attribute \src "libresoc.v:188173.3-188560.6" + wire $60\mask[59:59] + attribute \src "libresoc.v:188173.3-188560.6" + wire $61\mask[60:60] + attribute \src "libresoc.v:188173.3-188560.6" + wire $62\mask[61:61] + attribute \src "libresoc.v:188173.3-188560.6" + wire $63\mask[62:62] + attribute \src "libresoc.v:188173.3-188560.6" + wire $64\mask[63:63] + attribute \src "libresoc.v:188173.3-188560.6" + wire $6\mask[5:5] + attribute \src "libresoc.v:188173.3-188560.6" + wire $7\mask[6:6] + attribute \src "libresoc.v:188173.3-188560.6" + wire $8\mask[7:7] + attribute \src "libresoc.v:188173.3-188560.6" + wire $9\mask[8:8] + attribute \src "libresoc.v:188109.17-188109.96" + wire $gt$libresoc.v:188109$12196_Y + attribute \src "libresoc.v:188110.18-188110.98" + wire $gt$libresoc.v:188110$12197_Y + attribute \src "libresoc.v:188111.19-188111.99" + wire $gt$libresoc.v:188111$12198_Y + attribute \src "libresoc.v:188112.19-188112.99" + wire $gt$libresoc.v:188112$12199_Y + attribute \src "libresoc.v:188113.19-188113.99" + wire $gt$libresoc.v:188113$12200_Y + attribute \src "libresoc.v:188114.19-188114.99" + wire $gt$libresoc.v:188114$12201_Y + attribute \src "libresoc.v:188115.19-188115.99" + wire $gt$libresoc.v:188115$12202_Y + attribute \src "libresoc.v:188116.19-188116.99" + wire $gt$libresoc.v:188116$12203_Y + attribute \src "libresoc.v:188117.19-188117.99" + wire $gt$libresoc.v:188117$12204_Y + attribute \src "libresoc.v:188118.19-188118.99" + wire $gt$libresoc.v:188118$12205_Y + attribute \src "libresoc.v:188119.19-188119.99" + wire $gt$libresoc.v:188119$12206_Y + attribute \src "libresoc.v:188120.18-188120.97" + wire $gt$libresoc.v:188120$12207_Y + attribute \src "libresoc.v:188121.19-188121.99" + wire $gt$libresoc.v:188121$12208_Y + attribute \src "libresoc.v:188122.19-188122.99" + wire $gt$libresoc.v:188122$12209_Y + attribute \src "libresoc.v:188123.19-188123.99" + wire $gt$libresoc.v:188123$12210_Y + attribute \src "libresoc.v:188124.19-188124.99" + wire $gt$libresoc.v:188124$12211_Y + attribute \src "libresoc.v:188125.19-188125.99" + wire $gt$libresoc.v:188125$12212_Y + attribute \src "libresoc.v:188126.18-188126.97" + wire $gt$libresoc.v:188126$12213_Y + attribute \src "libresoc.v:188127.18-188127.97" + wire $gt$libresoc.v:188127$12214_Y + attribute \src "libresoc.v:188128.18-188128.97" + wire $gt$libresoc.v:188128$12215_Y + attribute \src "libresoc.v:188129.17-188129.96" + wire $gt$libresoc.v:188129$12216_Y + attribute \src "libresoc.v:188130.18-188130.97" + wire $gt$libresoc.v:188130$12217_Y + attribute \src "libresoc.v:188131.18-188131.97" + wire $gt$libresoc.v:188131$12218_Y + attribute \src "libresoc.v:188132.18-188132.97" + wire $gt$libresoc.v:188132$12219_Y + attribute \src "libresoc.v:188133.18-188133.97" + wire $gt$libresoc.v:188133$12220_Y + attribute \src "libresoc.v:188134.18-188134.97" + wire $gt$libresoc.v:188134$12221_Y + attribute \src "libresoc.v:188135.18-188135.97" + wire $gt$libresoc.v:188135$12222_Y + attribute \src "libresoc.v:188136.18-188136.97" + wire $gt$libresoc.v:188136$12223_Y + attribute \src "libresoc.v:188137.18-188137.98" + wire $gt$libresoc.v:188137$12224_Y + attribute \src "libresoc.v:188138.18-188138.98" + wire $gt$libresoc.v:188138$12225_Y + attribute \src "libresoc.v:188139.18-188139.98" + wire $gt$libresoc.v:188139$12226_Y + attribute \src "libresoc.v:188140.17-188140.96" + wire $gt$libresoc.v:188140$12227_Y + attribute \src "libresoc.v:188141.18-188141.98" + wire $gt$libresoc.v:188141$12228_Y + attribute \src "libresoc.v:188142.18-188142.98" + wire $gt$libresoc.v:188142$12229_Y + attribute \src "libresoc.v:188143.18-188143.98" + wire $gt$libresoc.v:188143$12230_Y + attribute \src "libresoc.v:188144.18-188144.98" + wire $gt$libresoc.v:188144$12231_Y + attribute \src "libresoc.v:188145.18-188145.98" + wire $gt$libresoc.v:188145$12232_Y + attribute \src "libresoc.v:188146.18-188146.98" + wire $gt$libresoc.v:188146$12233_Y + attribute \src "libresoc.v:188147.18-188147.98" + wire $gt$libresoc.v:188147$12234_Y + attribute \src "libresoc.v:188148.18-188148.98" + wire $gt$libresoc.v:188148$12235_Y + attribute \src "libresoc.v:188149.18-188149.98" + wire $gt$libresoc.v:188149$12236_Y + attribute \src "libresoc.v:188150.18-188150.98" + wire $gt$libresoc.v:188150$12237_Y + attribute \src "libresoc.v:188151.17-188151.96" + wire $gt$libresoc.v:188151$12238_Y + attribute \src "libresoc.v:188152.18-188152.98" + wire $gt$libresoc.v:188152$12239_Y + attribute \src "libresoc.v:188153.18-188153.98" + wire $gt$libresoc.v:188153$12240_Y + attribute \src "libresoc.v:188154.18-188154.98" + wire $gt$libresoc.v:188154$12241_Y + attribute \src "libresoc.v:188155.18-188155.98" + wire $gt$libresoc.v:188155$12242_Y + attribute \src "libresoc.v:188156.18-188156.98" + wire $gt$libresoc.v:188156$12243_Y + attribute \src "libresoc.v:188157.18-188157.98" + wire $gt$libresoc.v:188157$12244_Y + attribute \src "libresoc.v:188158.18-188158.98" + wire $gt$libresoc.v:188158$12245_Y + attribute \src "libresoc.v:188159.18-188159.98" + wire $gt$libresoc.v:188159$12246_Y + attribute \src "libresoc.v:188160.18-188160.98" + wire $gt$libresoc.v:188160$12247_Y + attribute \src "libresoc.v:188161.18-188161.98" + wire $gt$libresoc.v:188161$12248_Y + attribute \src "libresoc.v:188162.17-188162.96" + wire $gt$libresoc.v:188162$12249_Y + attribute \src "libresoc.v:188163.18-188163.98" + wire $gt$libresoc.v:188163$12250_Y + attribute \src "libresoc.v:188164.18-188164.98" + wire $gt$libresoc.v:188164$12251_Y + attribute \src "libresoc.v:188165.18-188165.98" + wire $gt$libresoc.v:188165$12252_Y + attribute \src "libresoc.v:188166.18-188166.98" + wire $gt$libresoc.v:188166$12253_Y + attribute \src "libresoc.v:188167.18-188167.98" + wire $gt$libresoc.v:188167$12254_Y + attribute \src "libresoc.v:188168.18-188168.98" + wire $gt$libresoc.v:188168$12255_Y + attribute \src "libresoc.v:188169.18-188169.98" + wire $gt$libresoc.v:188169$12256_Y + attribute \src "libresoc.v:188170.18-188170.98" + wire $gt$libresoc.v:188170$12257_Y + attribute \src "libresoc.v:188171.18-188171.98" + wire $gt$libresoc.v:188171$12258_Y + attribute \src "libresoc.v:188172.18-188172.98" + wire $gt$libresoc.v:188172$12259_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$101 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$103 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$105 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$107 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$109 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$111 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$113 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$115 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$117 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$119 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$121 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$123 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$125 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$127 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$17 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$21 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$25 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$29 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$33 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$35 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$37 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$39 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$41 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$43 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$45 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$47 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$49 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$51 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$53 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$55 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$57 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$59 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$61 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$63 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$65 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$67 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$69 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$71 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$73 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$75 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$77 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$79 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$81 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$83 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$85 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$87 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$89 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$91 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$93 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$95 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$97 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + wire \$99 + attribute \src "libresoc.v:187975.7-187975.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:20" + wire width 64 output 1 \mask + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:19" + wire width 7 input 2 \shift + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:188109$12196 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 3'100 + connect \Y $gt$libresoc.v:188109$12196_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:188110$12197 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'110001 + connect \Y $gt$libresoc.v:188110$12197_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:188111$12198 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'110010 + connect \Y $gt$libresoc.v:188111$12198_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:188112$12199 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'110011 + connect \Y $gt$libresoc.v:188112$12199_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:188113$12200 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'110100 + connect \Y $gt$libresoc.v:188113$12200_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:188114$12201 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'110101 + connect \Y $gt$libresoc.v:188114$12201_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:188115$12202 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'110110 + connect \Y $gt$libresoc.v:188115$12202_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:188116$12203 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'110111 + connect \Y $gt$libresoc.v:188116$12203_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:188117$12204 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'111000 + connect \Y $gt$libresoc.v:188117$12204_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:188118$12205 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'111001 + connect \Y $gt$libresoc.v:188118$12205_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:188119$12206 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'111010 + connect \Y $gt$libresoc.v:188119$12206_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:188120$12207 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 3'101 + connect \Y $gt$libresoc.v:188120$12207_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:188121$12208 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'111011 + connect \Y $gt$libresoc.v:188121$12208_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:188122$12209 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'111100 + connect \Y $gt$libresoc.v:188122$12209_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:188123$12210 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'111101 + connect \Y $gt$libresoc.v:188123$12210_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:188124$12211 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'111110 + connect \Y $gt$libresoc.v:188124$12211_Y + end + attribute \src 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"/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:188158$12245 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'100011 + connect \Y $gt$libresoc.v:188158$12245_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:188159$12246 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'100100 + connect \Y $gt$libresoc.v:188159$12246_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:188160$12247 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'100101 + connect \Y $gt$libresoc.v:188160$12247_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:188161$12248 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'100110 + connect \Y $gt$libresoc.v:188161$12248_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:188162$12249 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 2'11 + connect \Y $gt$libresoc.v:188162$12249_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:188163$12250 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'100111 + connect \Y $gt$libresoc.v:188163$12250_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:188164$12251 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'101000 + connect \Y $gt$libresoc.v:188164$12251_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:188165$12252 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'101001 + connect \Y $gt$libresoc.v:188165$12252_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:188166$12253 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'101010 + connect \Y $gt$libresoc.v:188166$12253_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:188167$12254 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'101011 + connect \Y $gt$libresoc.v:188167$12254_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:188168$12255 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'101100 + connect \Y $gt$libresoc.v:188168$12255_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:188169$12256 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'101101 + connect \Y $gt$libresoc.v:188169$12256_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:188170$12257 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'101110 + connect \Y $gt$libresoc.v:188170$12257_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:188171$12258 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'101111 + connect \Y $gt$libresoc.v:188171$12258_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + cell $gt $gt$libresoc.v:188172$12259 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'110000 + connect \Y $gt$libresoc.v:188172$12259_Y + end + attribute \src "libresoc.v:187975.7-187975.20" + process $proc$libresoc.v:187975$12261 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:188173.3-188560.6" + process $proc$libresoc.v:188173$12260 + assign { } { } + assign { } { } + assign $0\mask[63:0] [0] $1\mask[0:0] + assign $0\mask[63:0] [1] $2\mask[1:1] + assign $0\mask[63:0] [2] $3\mask[2:2] + assign $0\mask[63:0] [3] $4\mask[3:3] + assign $0\mask[63:0] [4] $5\mask[4:4] + assign $0\mask[63:0] [5] $6\mask[5:5] + assign $0\mask[63:0] [6] $7\mask[6:6] + assign $0\mask[63:0] [7] $8\mask[7:7] + assign $0\mask[63:0] [8] $9\mask[8:8] + assign $0\mask[63:0] [9] $10\mask[9:9] + assign $0\mask[63:0] [10] $11\mask[10:10] + assign $0\mask[63:0] [11] $12\mask[11:11] + assign $0\mask[63:0] [12] $13\mask[12:12] + assign $0\mask[63:0] [13] $14\mask[13:13] + assign $0\mask[63:0] [14] $15\mask[14:14] + assign $0\mask[63:0] [15] $16\mask[15:15] + assign $0\mask[63:0] [16] $17\mask[16:16] + assign $0\mask[63:0] [17] $18\mask[17:17] + assign $0\mask[63:0] [18] $19\mask[18:18] + assign $0\mask[63:0] [19] $20\mask[19:19] + assign $0\mask[63:0] [20] $21\mask[20:20] + assign $0\mask[63:0] [21] $22\mask[21:21] + assign $0\mask[63:0] [22] $23\mask[22:22] + assign $0\mask[63:0] [23] $24\mask[23:23] + assign $0\mask[63:0] [24] $25\mask[24:24] + assign $0\mask[63:0] [25] $26\mask[25:25] + assign $0\mask[63:0] [26] $27\mask[26:26] + assign $0\mask[63:0] [27] $28\mask[27:27] + assign $0\mask[63:0] [28] $29\mask[28:28] + assign $0\mask[63:0] [29] $30\mask[29:29] + assign $0\mask[63:0] [30] $31\mask[30:30] + assign $0\mask[63:0] [31] $32\mask[31:31] + assign $0\mask[63:0] [32] $33\mask[32:32] + assign $0\mask[63:0] [33] $34\mask[33:33] + assign $0\mask[63:0] [34] $35\mask[34:34] + assign $0\mask[63:0] [35] $36\mask[35:35] + assign $0\mask[63:0] [36] $37\mask[36:36] + assign $0\mask[63:0] [37] $38\mask[37:37] + assign $0\mask[63:0] [38] $39\mask[38:38] + assign $0\mask[63:0] [39] $40\mask[39:39] + assign $0\mask[63:0] [40] $41\mask[40:40] + assign $0\mask[63:0] [41] $42\mask[41:41] + assign $0\mask[63:0] [42] $43\mask[42:42] + assign $0\mask[63:0] [43] $44\mask[43:43] + assign $0\mask[63:0] [44] $45\mask[44:44] + assign $0\mask[63:0] [45] $46\mask[45:45] + assign $0\mask[63:0] [46] $47\mask[46:46] + assign $0\mask[63:0] [47] $48\mask[47:47] + assign $0\mask[63:0] [48] $49\mask[48:48] + assign $0\mask[63:0] [49] $50\mask[49:49] + assign $0\mask[63:0] [50] $51\mask[50:50] + assign $0\mask[63:0] [51] $52\mask[51:51] + assign $0\mask[63:0] [52] $53\mask[52:52] + assign $0\mask[63:0] [53] $54\mask[53:53] + assign $0\mask[63:0] [54] $55\mask[54:54] + assign $0\mask[63:0] [55] $56\mask[55:55] + assign $0\mask[63:0] [56] $57\mask[56:56] + assign $0\mask[63:0] [57] $58\mask[57:57] + assign $0\mask[63:0] [58] $59\mask[58:58] + assign $0\mask[63:0] [59] $60\mask[59:59] + assign $0\mask[63:0] [60] $61\mask[60:60] + assign $0\mask[63:0] [61] $62\mask[61:61] + assign $0\mask[63:0] [62] $63\mask[62:62] + assign $0\mask[63:0] [63] $64\mask[63:63] + attribute \src "libresoc.v:188174.5-188174.29" + switch \initial + attribute \src "libresoc.v:188174.9-188174.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$1 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\mask[0:0] 1'1 + case + assign $1\mask[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\mask[1:1] 1'1 + case + assign $2\mask[1:1] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$5 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\mask[2:2] 1'1 + case + assign $3\mask[2:2] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$7 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\mask[3:3] 1'1 + case + assign $4\mask[3:3] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$9 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\mask[4:4] 1'1 + case + assign $5\mask[4:4] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$11 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\mask[5:5] 1'1 + case + assign $6\mask[5:5] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$13 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\mask[6:6] 1'1 + case + assign $7\mask[6:6] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$15 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $8\mask[7:7] 1'1 + case + assign $8\mask[7:7] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$17 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $9\mask[8:8] 1'1 + case + assign $9\mask[8:8] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$19 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $10\mask[9:9] 1'1 + case + assign $10\mask[9:9] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$21 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $11\mask[10:10] 1'1 + case + assign $11\mask[10:10] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$23 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $12\mask[11:11] 1'1 + case + assign $12\mask[11:11] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$25 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $13\mask[12:12] 1'1 + case + assign $13\mask[12:12] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$27 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $14\mask[13:13] 1'1 + case + assign $14\mask[13:13] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$29 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $15\mask[14:14] 1'1 + case + assign $15\mask[14:14] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$31 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $16\mask[15:15] 1'1 + case + assign $16\mask[15:15] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$33 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $17\mask[16:16] 1'1 + case + assign $17\mask[16:16] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$35 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $18\mask[17:17] 1'1 + case + assign $18\mask[17:17] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$37 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $19\mask[18:18] 1'1 + case + assign $19\mask[18:18] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$39 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $20\mask[19:19] 1'1 + case + assign $20\mask[19:19] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$41 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $21\mask[20:20] 1'1 + case + assign $21\mask[20:20] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$43 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $22\mask[21:21] 1'1 + case + assign $22\mask[21:21] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$45 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $23\mask[22:22] 1'1 + case + assign $23\mask[22:22] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$47 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $24\mask[23:23] 1'1 + case + assign $24\mask[23:23] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$49 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $25\mask[24:24] 1'1 + case + assign $25\mask[24:24] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$51 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $26\mask[25:25] 1'1 + case + assign $26\mask[25:25] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$53 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $27\mask[26:26] 1'1 + case + assign $27\mask[26:26] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$55 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $28\mask[27:27] 1'1 + case + assign $28\mask[27:27] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$57 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $29\mask[28:28] 1'1 + case + assign $29\mask[28:28] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$59 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $30\mask[29:29] 1'1 + case + assign $30\mask[29:29] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$61 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $31\mask[30:30] 1'1 + case + assign $31\mask[30:30] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$63 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $32\mask[31:31] 1'1 + case + assign $32\mask[31:31] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$65 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $33\mask[32:32] 1'1 + case + assign $33\mask[32:32] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$67 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $34\mask[33:33] 1'1 + case + assign $34\mask[33:33] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$69 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $35\mask[34:34] 1'1 + case + assign $35\mask[34:34] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$71 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $36\mask[35:35] 1'1 + case + assign $36\mask[35:35] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$73 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $37\mask[36:36] 1'1 + case + assign $37\mask[36:36] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$75 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $38\mask[37:37] 1'1 + case + assign $38\mask[37:37] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$77 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $39\mask[38:38] 1'1 + case + assign $39\mask[38:38] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$79 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $40\mask[39:39] 1'1 + case + assign $40\mask[39:39] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$81 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $41\mask[40:40] 1'1 + case + assign $41\mask[40:40] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$83 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $42\mask[41:41] 1'1 + case + assign $42\mask[41:41] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$85 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $43\mask[42:42] 1'1 + case + assign $43\mask[42:42] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$87 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $44\mask[43:43] 1'1 + case + assign $44\mask[43:43] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$89 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $45\mask[44:44] 1'1 + case + assign $45\mask[44:44] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$91 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $46\mask[45:45] 1'1 + case + assign $46\mask[45:45] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$93 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $47\mask[46:46] 1'1 + case + assign $47\mask[46:46] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$95 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $48\mask[47:47] 1'1 + case + assign $48\mask[47:47] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$97 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $49\mask[48:48] 1'1 + case + assign $49\mask[48:48] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$99 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $50\mask[49:49] 1'1 + case + assign $50\mask[49:49] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$101 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $51\mask[50:50] 1'1 + case + assign $51\mask[50:50] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$103 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $52\mask[51:51] 1'1 + case + assign $52\mask[51:51] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$105 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $53\mask[52:52] 1'1 + case + assign $53\mask[52:52] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$107 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $54\mask[53:53] 1'1 + case + assign $54\mask[53:53] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$109 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $55\mask[54:54] 1'1 + case + assign $55\mask[54:54] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$111 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $56\mask[55:55] 1'1 + case + assign $56\mask[55:55] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$113 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $57\mask[56:56] 1'1 + case + assign $57\mask[56:56] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$115 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $58\mask[57:57] 1'1 + case + assign $58\mask[57:57] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$117 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $59\mask[58:58] 1'1 + case + assign $59\mask[58:58] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$119 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $60\mask[59:59] 1'1 + case + assign $60\mask[59:59] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$121 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $61\mask[60:60] 1'1 + case + assign $61\mask[60:60] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$123 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $62\mask[61:61] 1'1 + case + assign $62\mask[61:61] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$125 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $63\mask[62:62] 1'1 + case + assign $63\mask[62:62] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" + switch \$127 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $64\mask[63:63] 1'1 + case + assign $64\mask[63:63] 1'0 + end + sync always + update \mask $0\mask[63:0] + end + connect \$9 $gt$libresoc.v:188109$12196_Y + connect \$99 $gt$libresoc.v:188110$12197_Y + connect \$101 $gt$libresoc.v:188111$12198_Y + connect \$103 $gt$libresoc.v:188112$12199_Y + connect \$105 $gt$libresoc.v:188113$12200_Y + connect \$107 $gt$libresoc.v:188114$12201_Y + connect \$109 $gt$libresoc.v:188115$12202_Y + connect \$111 $gt$libresoc.v:188116$12203_Y + connect \$113 $gt$libresoc.v:188117$12204_Y + connect \$115 $gt$libresoc.v:188118$12205_Y + connect \$117 $gt$libresoc.v:188119$12206_Y + connect \$11 $gt$libresoc.v:188120$12207_Y + connect \$119 $gt$libresoc.v:188121$12208_Y + connect \$121 $gt$libresoc.v:188122$12209_Y + connect \$123 $gt$libresoc.v:188123$12210_Y + connect \$125 $gt$libresoc.v:188124$12211_Y + connect \$127 $gt$libresoc.v:188125$12212_Y + connect \$13 $gt$libresoc.v:188126$12213_Y + connect \$15 $gt$libresoc.v:188127$12214_Y + connect \$17 $gt$libresoc.v:188128$12215_Y + connect \$1 $gt$libresoc.v:188129$12216_Y + connect \$19 $gt$libresoc.v:188130$12217_Y + connect \$21 $gt$libresoc.v:188131$12218_Y + connect \$23 $gt$libresoc.v:188132$12219_Y + connect \$25 $gt$libresoc.v:188133$12220_Y + connect \$27 $gt$libresoc.v:188134$12221_Y + connect \$29 $gt$libresoc.v:188135$12222_Y + connect \$31 $gt$libresoc.v:188136$12223_Y + connect \$33 $gt$libresoc.v:188137$12224_Y + connect \$35 $gt$libresoc.v:188138$12225_Y + connect \$37 $gt$libresoc.v:188139$12226_Y + connect \$3 $gt$libresoc.v:188140$12227_Y + connect \$39 $gt$libresoc.v:188141$12228_Y + connect \$41 $gt$libresoc.v:188142$12229_Y + connect \$43 $gt$libresoc.v:188143$12230_Y + connect \$45 $gt$libresoc.v:188144$12231_Y + connect \$47 $gt$libresoc.v:188145$12232_Y + connect \$49 $gt$libresoc.v:188146$12233_Y + connect \$51 $gt$libresoc.v:188147$12234_Y + connect \$53 $gt$libresoc.v:188148$12235_Y + connect \$55 $gt$libresoc.v:188149$12236_Y + connect \$57 $gt$libresoc.v:188150$12237_Y + connect \$5 $gt$libresoc.v:188151$12238_Y + connect \$59 $gt$libresoc.v:188152$12239_Y + connect \$61 $gt$libresoc.v:188153$12240_Y + connect \$63 $gt$libresoc.v:188154$12241_Y + connect \$65 $gt$libresoc.v:188155$12242_Y + connect \$67 $gt$libresoc.v:188156$12243_Y + connect \$69 $gt$libresoc.v:188157$12244_Y + connect \$71 $gt$libresoc.v:188158$12245_Y + connect \$73 $gt$libresoc.v:188159$12246_Y + connect \$75 $gt$libresoc.v:188160$12247_Y + connect \$77 $gt$libresoc.v:188161$12248_Y + connect \$7 $gt$libresoc.v:188162$12249_Y + connect \$79 $gt$libresoc.v:188163$12250_Y + connect \$81 $gt$libresoc.v:188164$12251_Y + connect \$83 $gt$libresoc.v:188165$12252_Y + connect \$85 $gt$libresoc.v:188166$12253_Y + connect \$87 $gt$libresoc.v:188167$12254_Y + connect \$89 $gt$libresoc.v:188168$12255_Y + connect \$91 $gt$libresoc.v:188169$12256_Y + connect \$93 $gt$libresoc.v:188170$12257_Y + connect \$95 $gt$libresoc.v:188171$12258_Y + connect \$97 $gt$libresoc.v:188172$12259_Y +end +attribute \src "libresoc.v:188565.1-188623.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.rok_l" +attribute \generator "nMigen" +module \rok_l + attribute \src "libresoc.v:188566.7-188566.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:188611.3-188619.6" + wire $0\q_int$next[0:0]$12272 + attribute \src "libresoc.v:188609.3-188610.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:188611.3-188619.6" + wire $1\q_int$next[0:0]$12273 + attribute \src "libresoc.v:188588.7-188588.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:188601.17-188601.96" + wire $and$libresoc.v:188601$12262_Y + attribute \src "libresoc.v:188606.17-188606.96" + wire $and$libresoc.v:188606$12267_Y + attribute \src "libresoc.v:188603.18-188603.94" + wire $not$libresoc.v:188603$12264_Y + attribute \src "libresoc.v:188605.17-188605.93" + wire $not$libresoc.v:188605$12266_Y + attribute \src "libresoc.v:188608.17-188608.93" + wire $not$libresoc.v:188608$12269_Y + attribute \src "libresoc.v:188602.18-188602.99" + wire $or$libresoc.v:188602$12263_Y + attribute \src "libresoc.v:188604.18-188604.100" + wire $or$libresoc.v:188604$12265_Y + attribute \src "libresoc.v:188607.17-188607.98" + wire $or$libresoc.v:188607$12268_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 1 \coresync_rst + attribute \src "libresoc.v:188566.7-188566.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire output 2 \q_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" + wire \qlq_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \qn_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire input 4 \r_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire input 3 \s_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:188601$12262 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:188601$12262_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:188606$12267 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:188606$12267_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:188603$12264 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rdok + connect \Y $not$libresoc.v:188603$12264_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:188605$12266 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rdok + connect \Y $not$libresoc.v:188605$12266_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:188608$12269 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rdok + connect \Y $not$libresoc.v:188608$12269_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:188602$12263 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_rdok + connect \Y $or$libresoc.v:188602$12263_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:188604$12265 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rdok + connect \B \q_int + connect \Y $or$libresoc.v:188604$12265_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:188607$12268 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_rdok + connect \Y $or$libresoc.v:188607$12268_Y + end + attribute \src "libresoc.v:188566.7-188566.20" + process $proc$libresoc.v:188566$12274 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:188588.7-188588.19" + process $proc$libresoc.v:188588$12275 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:188609.3-188610.27" + process $proc$libresoc.v:188609$12270 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:188611.3-188619.6" + process $proc$libresoc.v:188611$12271 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$12272 $1\q_int$next[0:0]$12273 + attribute \src "libresoc.v:188612.5-188612.29" + switch \initial + attribute \src "libresoc.v:188612.9-188612.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$12273 1'0 + case + assign $1\q_int$next[0:0]$12273 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$12272 + end + connect \$9 $and$libresoc.v:188601$12262_Y + connect \$11 $or$libresoc.v:188602$12263_Y + connect \$13 $not$libresoc.v:188603$12264_Y + connect \$15 $or$libresoc.v:188604$12265_Y + connect \$1 $not$libresoc.v:188605$12266_Y + connect \$3 $and$libresoc.v:188606$12267_Y + connect \$5 $or$libresoc.v:188607$12268_Y + connect \$7 $not$libresoc.v:188608$12269_Y + connect \qlq_rdok \$15 + connect \qn_rdok \$13 + connect \q_rdok \$11 +end +attribute \src "libresoc.v:188627.1-188685.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.rok_l" +attribute \generator "nMigen" +module \rok_l$105 + attribute \src "libresoc.v:188628.7-188628.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:188673.3-188681.6" + wire $0\q_int$next[0:0]$12286 + attribute \src "libresoc.v:188671.3-188672.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:188673.3-188681.6" + wire $1\q_int$next[0:0]$12287 + attribute \src "libresoc.v:188650.7-188650.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:188663.17-188663.96" + wire $and$libresoc.v:188663$12276_Y + attribute \src "libresoc.v:188668.17-188668.96" + wire $and$libresoc.v:188668$12281_Y + attribute \src "libresoc.v:188665.18-188665.94" + wire $not$libresoc.v:188665$12278_Y + attribute \src "libresoc.v:188667.17-188667.93" + wire $not$libresoc.v:188667$12280_Y + attribute \src "libresoc.v:188670.17-188670.93" + wire $not$libresoc.v:188670$12283_Y + attribute \src "libresoc.v:188664.18-188664.99" + wire $or$libresoc.v:188664$12277_Y + attribute \src "libresoc.v:188666.18-188666.100" + wire $or$libresoc.v:188666$12279_Y + attribute \src "libresoc.v:188669.17-188669.98" + wire $or$libresoc.v:188669$12282_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 1 \coresync_rst + attribute \src "libresoc.v:188628.7-188628.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire output 2 \q_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" + wire \qlq_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \qn_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire input 4 \r_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire input 3 \s_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:188663$12276 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:188663$12276_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:188668$12281 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:188668$12281_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:188665$12278 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rdok + connect \Y $not$libresoc.v:188665$12278_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:188667$12280 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rdok + connect \Y $not$libresoc.v:188667$12280_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:188670$12283 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rdok + connect \Y $not$libresoc.v:188670$12283_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:188664$12277 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_rdok + connect \Y $or$libresoc.v:188664$12277_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:188666$12279 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rdok + connect \B \q_int + connect \Y $or$libresoc.v:188666$12279_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:188669$12282 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_rdok + connect \Y $or$libresoc.v:188669$12282_Y + end + attribute \src "libresoc.v:188628.7-188628.20" + process $proc$libresoc.v:188628$12288 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:188650.7-188650.19" + process $proc$libresoc.v:188650$12289 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:188671.3-188672.27" + process $proc$libresoc.v:188671$12284 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:188673.3-188681.6" + process $proc$libresoc.v:188673$12285 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$12286 $1\q_int$next[0:0]$12287 + attribute \src "libresoc.v:188674.5-188674.29" + switch \initial + attribute \src "libresoc.v:188674.9-188674.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$12287 1'0 + case + assign $1\q_int$next[0:0]$12287 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$12286 + end + connect \$9 $and$libresoc.v:188663$12276_Y + connect \$11 $or$libresoc.v:188664$12277_Y + connect \$13 $not$libresoc.v:188665$12278_Y + connect \$15 $or$libresoc.v:188666$12279_Y + connect \$1 $not$libresoc.v:188667$12280_Y + connect \$3 $and$libresoc.v:188668$12281_Y + connect \$5 $or$libresoc.v:188669$12282_Y + connect \$7 $not$libresoc.v:188670$12283_Y + connect \qlq_rdok \$15 + connect \qn_rdok \$13 + connect \q_rdok \$11 +end +attribute \src "libresoc.v:188689.1-188747.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.rok_l" +attribute \generator "nMigen" +module \rok_l$123 + attribute \src "libresoc.v:188690.7-188690.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:188735.3-188743.6" + wire $0\q_int$next[0:0]$12300 + attribute \src "libresoc.v:188733.3-188734.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:188735.3-188743.6" + wire $1\q_int$next[0:0]$12301 + attribute \src "libresoc.v:188712.7-188712.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:188725.17-188725.96" + wire $and$libresoc.v:188725$12290_Y + attribute \src "libresoc.v:188730.17-188730.96" + wire $and$libresoc.v:188730$12295_Y + attribute \src "libresoc.v:188727.18-188727.94" + wire $not$libresoc.v:188727$12292_Y + attribute \src "libresoc.v:188729.17-188729.93" + wire $not$libresoc.v:188729$12294_Y + attribute \src "libresoc.v:188732.17-188732.93" + wire $not$libresoc.v:188732$12297_Y + attribute \src "libresoc.v:188726.18-188726.99" + wire $or$libresoc.v:188726$12291_Y + attribute \src "libresoc.v:188728.18-188728.100" + wire $or$libresoc.v:188728$12293_Y + attribute \src "libresoc.v:188731.17-188731.98" + wire $or$libresoc.v:188731$12296_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 1 \coresync_rst + attribute \src "libresoc.v:188690.7-188690.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire output 2 \q_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" + wire \qlq_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \qn_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire input 4 \r_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire input 3 \s_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:188725$12290 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:188725$12290_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:188730$12295 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:188730$12295_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:188727$12292 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rdok + connect \Y $not$libresoc.v:188727$12292_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:188729$12294 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rdok + connect \Y $not$libresoc.v:188729$12294_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:188732$12297 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rdok + connect \Y $not$libresoc.v:188732$12297_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:188726$12291 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_rdok + connect \Y $or$libresoc.v:188726$12291_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:188728$12293 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rdok + connect \B \q_int + connect \Y $or$libresoc.v:188728$12293_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:188731$12296 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_rdok + connect \Y $or$libresoc.v:188731$12296_Y + end + attribute \src "libresoc.v:188690.7-188690.20" + process $proc$libresoc.v:188690$12302 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:188712.7-188712.19" + process $proc$libresoc.v:188712$12303 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:188733.3-188734.27" + process $proc$libresoc.v:188733$12298 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:188735.3-188743.6" + process $proc$libresoc.v:188735$12299 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$12300 $1\q_int$next[0:0]$12301 + attribute \src "libresoc.v:188736.5-188736.29" + switch \initial + attribute \src "libresoc.v:188736.9-188736.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$12301 1'0 + case + assign $1\q_int$next[0:0]$12301 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$12300 + end + connect \$9 $and$libresoc.v:188725$12290_Y + connect \$11 $or$libresoc.v:188726$12291_Y + connect \$13 $not$libresoc.v:188727$12292_Y + connect \$15 $or$libresoc.v:188728$12293_Y + connect \$1 $not$libresoc.v:188729$12294_Y + connect \$3 $and$libresoc.v:188730$12295_Y + connect \$5 $or$libresoc.v:188731$12296_Y + connect \$7 $not$libresoc.v:188732$12297_Y + connect \qlq_rdok \$15 + connect \qn_rdok \$13 + connect \q_rdok \$11 +end +attribute \src "libresoc.v:188751.1-188809.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.rok_l" +attribute \generator "nMigen" +module \rok_l$14 + attribute \src "libresoc.v:188752.7-188752.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:188797.3-188805.6" + wire $0\q_int$next[0:0]$12314 + attribute \src "libresoc.v:188795.3-188796.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:188797.3-188805.6" + wire $1\q_int$next[0:0]$12315 + attribute \src "libresoc.v:188774.7-188774.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:188787.17-188787.96" + wire $and$libresoc.v:188787$12304_Y + attribute \src "libresoc.v:188792.17-188792.96" + wire $and$libresoc.v:188792$12309_Y + attribute \src "libresoc.v:188789.18-188789.94" + wire $not$libresoc.v:188789$12306_Y + attribute \src "libresoc.v:188791.17-188791.93" + wire $not$libresoc.v:188791$12308_Y + attribute \src "libresoc.v:188794.17-188794.93" + wire $not$libresoc.v:188794$12311_Y + attribute \src "libresoc.v:188788.18-188788.99" + wire $or$libresoc.v:188788$12305_Y + attribute \src "libresoc.v:188790.18-188790.100" + wire $or$libresoc.v:188790$12307_Y + attribute \src "libresoc.v:188793.17-188793.98" + wire $or$libresoc.v:188793$12310_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 1 \coresync_rst + attribute \src "libresoc.v:188752.7-188752.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire output 2 \q_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" + wire \qlq_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \qn_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire input 4 \r_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire input 3 \s_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:188787$12304 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:188787$12304_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:188792$12309 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:188792$12309_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:188789$12306 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rdok + connect \Y $not$libresoc.v:188789$12306_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:188791$12308 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rdok + connect \Y $not$libresoc.v:188791$12308_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:188794$12311 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rdok + connect \Y $not$libresoc.v:188794$12311_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:188788$12305 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_rdok + connect \Y $or$libresoc.v:188788$12305_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:188790$12307 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rdok + connect \B \q_int + connect \Y $or$libresoc.v:188790$12307_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:188793$12310 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_rdok + connect \Y $or$libresoc.v:188793$12310_Y + end + attribute \src "libresoc.v:188752.7-188752.20" + process $proc$libresoc.v:188752$12316 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:188774.7-188774.19" + process $proc$libresoc.v:188774$12317 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:188795.3-188796.27" + process $proc$libresoc.v:188795$12312 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:188797.3-188805.6" + process $proc$libresoc.v:188797$12313 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$12314 $1\q_int$next[0:0]$12315 + attribute \src "libresoc.v:188798.5-188798.29" + switch \initial + attribute \src "libresoc.v:188798.9-188798.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$12315 1'0 + case + assign $1\q_int$next[0:0]$12315 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$12314 + end + connect \$9 $and$libresoc.v:188787$12304_Y + connect \$11 $or$libresoc.v:188788$12305_Y + connect \$13 $not$libresoc.v:188789$12306_Y + connect \$15 $or$libresoc.v:188790$12307_Y + connect \$1 $not$libresoc.v:188791$12308_Y + connect \$3 $and$libresoc.v:188792$12309_Y + connect \$5 $or$libresoc.v:188793$12310_Y + connect \$7 $not$libresoc.v:188794$12311_Y + connect \qlq_rdok \$15 + connect \qn_rdok \$13 + connect \q_rdok \$11 +end +attribute \src "libresoc.v:188813.1-188871.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.rok_l" +attribute \generator "nMigen" +module \rok_l$27 + attribute \src "libresoc.v:188814.7-188814.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:188859.3-188867.6" + wire $0\q_int$next[0:0]$12328 + attribute \src "libresoc.v:188857.3-188858.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:188859.3-188867.6" + wire $1\q_int$next[0:0]$12329 + attribute \src "libresoc.v:188836.7-188836.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:188849.17-188849.96" + wire $and$libresoc.v:188849$12318_Y + attribute \src "libresoc.v:188854.17-188854.96" + wire $and$libresoc.v:188854$12323_Y + attribute \src "libresoc.v:188851.18-188851.94" + wire $not$libresoc.v:188851$12320_Y + attribute \src "libresoc.v:188853.17-188853.93" + wire $not$libresoc.v:188853$12322_Y + attribute \src "libresoc.v:188856.17-188856.93" + wire $not$libresoc.v:188856$12325_Y + attribute \src "libresoc.v:188850.18-188850.99" + wire $or$libresoc.v:188850$12319_Y + attribute \src "libresoc.v:188852.18-188852.100" + wire $or$libresoc.v:188852$12321_Y + attribute \src "libresoc.v:188855.17-188855.98" + wire $or$libresoc.v:188855$12324_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 1 \coresync_rst + attribute \src "libresoc.v:188814.7-188814.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire output 2 \q_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" + wire \qlq_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \qn_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire input 4 \r_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire input 3 \s_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:188849$12318 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:188849$12318_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:188854$12323 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:188854$12323_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:188851$12320 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rdok + connect \Y $not$libresoc.v:188851$12320_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:188853$12322 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rdok + connect \Y $not$libresoc.v:188853$12322_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:188856$12325 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rdok + connect \Y $not$libresoc.v:188856$12325_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:188850$12319 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_rdok + connect \Y $or$libresoc.v:188850$12319_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:188852$12321 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rdok + connect \B \q_int + connect \Y $or$libresoc.v:188852$12321_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:188855$12324 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_rdok + connect \Y $or$libresoc.v:188855$12324_Y + end + attribute \src "libresoc.v:188814.7-188814.20" + process $proc$libresoc.v:188814$12330 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:188836.7-188836.19" + process $proc$libresoc.v:188836$12331 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:188857.3-188858.27" + process $proc$libresoc.v:188857$12326 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:188859.3-188867.6" + process $proc$libresoc.v:188859$12327 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$12328 $1\q_int$next[0:0]$12329 + attribute \src "libresoc.v:188860.5-188860.29" + switch \initial + attribute \src "libresoc.v:188860.9-188860.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$12329 1'0 + case + assign $1\q_int$next[0:0]$12329 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$12328 + end + connect \$9 $and$libresoc.v:188849$12318_Y + connect \$11 $or$libresoc.v:188850$12319_Y + connect \$13 $not$libresoc.v:188851$12320_Y + connect \$15 $or$libresoc.v:188852$12321_Y + connect \$1 $not$libresoc.v:188853$12322_Y + connect \$3 $and$libresoc.v:188854$12323_Y + connect \$5 $or$libresoc.v:188855$12324_Y + connect \$7 $not$libresoc.v:188856$12325_Y + connect \qlq_rdok \$15 + connect \qn_rdok \$13 + connect \q_rdok \$11 +end +attribute \src "libresoc.v:188875.1-188933.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.rok_l" +attribute \generator "nMigen" +module \rok_l$43 + attribute \src "libresoc.v:188876.7-188876.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:188921.3-188929.6" + wire $0\q_int$next[0:0]$12342 + attribute \src "libresoc.v:188919.3-188920.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:188921.3-188929.6" + wire $1\q_int$next[0:0]$12343 + attribute \src "libresoc.v:188898.7-188898.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:188911.17-188911.96" + wire $and$libresoc.v:188911$12332_Y + attribute \src "libresoc.v:188916.17-188916.96" + wire $and$libresoc.v:188916$12337_Y + attribute \src "libresoc.v:188913.18-188913.94" + wire $not$libresoc.v:188913$12334_Y + attribute \src "libresoc.v:188915.17-188915.93" + wire $not$libresoc.v:188915$12336_Y + attribute \src "libresoc.v:188918.17-188918.93" + wire $not$libresoc.v:188918$12339_Y + attribute \src "libresoc.v:188912.18-188912.99" + wire $or$libresoc.v:188912$12333_Y + attribute \src "libresoc.v:188914.18-188914.100" + wire $or$libresoc.v:188914$12335_Y + attribute \src "libresoc.v:188917.17-188917.98" + wire $or$libresoc.v:188917$12338_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 1 \coresync_rst + attribute \src "libresoc.v:188876.7-188876.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire output 2 \q_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" + wire \qlq_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \qn_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire input 4 \r_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire input 3 \s_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:188911$12332 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:188911$12332_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:188916$12337 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:188916$12337_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:188913$12334 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rdok + connect \Y $not$libresoc.v:188913$12334_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:188915$12336 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rdok + connect \Y $not$libresoc.v:188915$12336_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:188918$12339 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rdok + connect \Y $not$libresoc.v:188918$12339_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:188912$12333 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_rdok + connect \Y $or$libresoc.v:188912$12333_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:188914$12335 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rdok + connect \B \q_int + connect \Y $or$libresoc.v:188914$12335_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:188917$12338 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_rdok + connect \Y $or$libresoc.v:188917$12338_Y + end + attribute \src "libresoc.v:188876.7-188876.20" + process $proc$libresoc.v:188876$12344 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:188898.7-188898.19" + process $proc$libresoc.v:188898$12345 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:188919.3-188920.27" + process $proc$libresoc.v:188919$12340 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:188921.3-188929.6" + process $proc$libresoc.v:188921$12341 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$12342 $1\q_int$next[0:0]$12343 + attribute \src "libresoc.v:188922.5-188922.29" + switch \initial + attribute \src "libresoc.v:188922.9-188922.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$12343 1'0 + case + assign $1\q_int$next[0:0]$12343 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$12342 + end + connect \$9 $and$libresoc.v:188911$12332_Y + connect \$11 $or$libresoc.v:188912$12333_Y + connect \$13 $not$libresoc.v:188913$12334_Y + connect \$15 $or$libresoc.v:188914$12335_Y + connect \$1 $not$libresoc.v:188915$12336_Y + connect \$3 $and$libresoc.v:188916$12337_Y + connect \$5 $or$libresoc.v:188917$12338_Y + connect \$7 $not$libresoc.v:188918$12339_Y + connect \qlq_rdok \$15 + connect \qn_rdok \$13 + connect \q_rdok \$11 +end +attribute \src "libresoc.v:188937.1-188995.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.rok_l" +attribute \generator "nMigen" +module \rok_l$59 + attribute \src "libresoc.v:188938.7-188938.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:188983.3-188991.6" + wire $0\q_int$next[0:0]$12356 + attribute \src "libresoc.v:188981.3-188982.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:188983.3-188991.6" + wire $1\q_int$next[0:0]$12357 + attribute \src "libresoc.v:188960.7-188960.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:188973.17-188973.96" + wire $and$libresoc.v:188973$12346_Y + attribute \src "libresoc.v:188978.17-188978.96" + wire $and$libresoc.v:188978$12351_Y + attribute \src "libresoc.v:188975.18-188975.94" + wire $not$libresoc.v:188975$12348_Y + attribute \src "libresoc.v:188977.17-188977.93" + wire $not$libresoc.v:188977$12350_Y + attribute \src "libresoc.v:188980.17-188980.93" + wire $not$libresoc.v:188980$12353_Y + attribute \src "libresoc.v:188974.18-188974.99" + wire $or$libresoc.v:188974$12347_Y + attribute \src "libresoc.v:188976.18-188976.100" + wire $or$libresoc.v:188976$12349_Y + attribute \src "libresoc.v:188979.17-188979.98" + wire $or$libresoc.v:188979$12352_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 1 \coresync_rst + attribute \src "libresoc.v:188938.7-188938.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire output 2 \q_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" + wire \qlq_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \qn_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire input 4 \r_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire input 3 \s_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:188973$12346 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:188973$12346_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:188978$12351 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:188978$12351_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:188975$12348 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rdok + connect \Y $not$libresoc.v:188975$12348_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:188977$12350 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rdok + connect \Y $not$libresoc.v:188977$12350_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:188980$12353 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rdok + connect \Y $not$libresoc.v:188980$12353_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:188974$12347 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_rdok + connect \Y $or$libresoc.v:188974$12347_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:188976$12349 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rdok + connect \B \q_int + connect \Y $or$libresoc.v:188976$12349_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:188979$12352 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_rdok + connect \Y $or$libresoc.v:188979$12352_Y + end + attribute \src "libresoc.v:188938.7-188938.20" + process $proc$libresoc.v:188938$12358 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:188960.7-188960.19" + process $proc$libresoc.v:188960$12359 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:188981.3-188982.27" + process $proc$libresoc.v:188981$12354 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:188983.3-188991.6" + process $proc$libresoc.v:188983$12355 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$12356 $1\q_int$next[0:0]$12357 + attribute \src "libresoc.v:188984.5-188984.29" + switch \initial + attribute \src "libresoc.v:188984.9-188984.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$12357 1'0 + case + assign $1\q_int$next[0:0]$12357 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$12356 + end + connect \$9 $and$libresoc.v:188973$12346_Y + connect \$11 $or$libresoc.v:188974$12347_Y + connect \$13 $not$libresoc.v:188975$12348_Y + connect \$15 $or$libresoc.v:188976$12349_Y + connect \$1 $not$libresoc.v:188977$12350_Y + connect \$3 $and$libresoc.v:188978$12351_Y + connect \$5 $or$libresoc.v:188979$12352_Y + connect \$7 $not$libresoc.v:188980$12353_Y + connect \qlq_rdok \$15 + connect \qn_rdok \$13 + connect \q_rdok \$11 +end +attribute \src "libresoc.v:188999.1-189057.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.rok_l" +attribute \generator "nMigen" +module \rok_l$71 + attribute \src "libresoc.v:189000.7-189000.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:189045.3-189053.6" + wire $0\q_int$next[0:0]$12370 + attribute \src "libresoc.v:189043.3-189044.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:189045.3-189053.6" + wire $1\q_int$next[0:0]$12371 + attribute \src "libresoc.v:189022.7-189022.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:189035.17-189035.96" + wire $and$libresoc.v:189035$12360_Y + attribute \src "libresoc.v:189040.17-189040.96" + wire $and$libresoc.v:189040$12365_Y + attribute \src "libresoc.v:189037.18-189037.94" + wire $not$libresoc.v:189037$12362_Y + attribute \src "libresoc.v:189039.17-189039.93" + wire $not$libresoc.v:189039$12364_Y + attribute \src "libresoc.v:189042.17-189042.93" + wire $not$libresoc.v:189042$12367_Y + attribute \src "libresoc.v:189036.18-189036.99" + wire $or$libresoc.v:189036$12361_Y + attribute \src "libresoc.v:189038.18-189038.100" + wire $or$libresoc.v:189038$12363_Y + attribute \src "libresoc.v:189041.17-189041.98" + wire $or$libresoc.v:189041$12366_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 1 \coresync_rst + attribute \src "libresoc.v:189000.7-189000.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire output 2 \q_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" + wire \qlq_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \qn_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire input 4 \r_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire input 3 \s_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:189035$12360 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:189035$12360_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:189040$12365 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:189040$12365_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:189037$12362 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rdok + connect \Y $not$libresoc.v:189037$12362_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:189039$12364 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rdok + connect \Y $not$libresoc.v:189039$12364_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:189042$12367 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rdok + connect \Y $not$libresoc.v:189042$12367_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:189036$12361 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_rdok + connect \Y $or$libresoc.v:189036$12361_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:189038$12363 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rdok + connect \B \q_int + connect \Y $or$libresoc.v:189038$12363_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:189041$12366 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_rdok + connect \Y $or$libresoc.v:189041$12366_Y + end + attribute \src "libresoc.v:189000.7-189000.20" + process $proc$libresoc.v:189000$12372 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:189022.7-189022.19" + process $proc$libresoc.v:189022$12373 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:189043.3-189044.27" + process $proc$libresoc.v:189043$12368 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:189045.3-189053.6" + process $proc$libresoc.v:189045$12369 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$12370 $1\q_int$next[0:0]$12371 + attribute \src "libresoc.v:189046.5-189046.29" + switch \initial + attribute \src "libresoc.v:189046.9-189046.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$12371 1'0 + case + assign $1\q_int$next[0:0]$12371 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$12370 + end + connect \$9 $and$libresoc.v:189035$12360_Y + connect \$11 $or$libresoc.v:189036$12361_Y + connect \$13 $not$libresoc.v:189037$12362_Y + connect \$15 $or$libresoc.v:189038$12363_Y + connect \$1 $not$libresoc.v:189039$12364_Y + connect \$3 $and$libresoc.v:189040$12365_Y + connect \$5 $or$libresoc.v:189041$12366_Y + connect \$7 $not$libresoc.v:189042$12367_Y + connect \qlq_rdok \$15 + connect \qn_rdok \$13 + connect \q_rdok \$11 +end +attribute \src "libresoc.v:189061.1-189119.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.rok_l" +attribute \generator "nMigen" +module \rok_l$88 + attribute \src "libresoc.v:189062.7-189062.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:189107.3-189115.6" + wire $0\q_int$next[0:0]$12384 + attribute \src "libresoc.v:189105.3-189106.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:189107.3-189115.6" + wire $1\q_int$next[0:0]$12385 + attribute \src "libresoc.v:189084.7-189084.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:189097.17-189097.96" + wire $and$libresoc.v:189097$12374_Y + attribute \src "libresoc.v:189102.17-189102.96" + wire $and$libresoc.v:189102$12379_Y + attribute \src "libresoc.v:189099.18-189099.94" + wire $not$libresoc.v:189099$12376_Y + attribute \src "libresoc.v:189101.17-189101.93" + wire $not$libresoc.v:189101$12378_Y + attribute \src "libresoc.v:189104.17-189104.93" + wire $not$libresoc.v:189104$12381_Y + attribute \src "libresoc.v:189098.18-189098.99" + wire $or$libresoc.v:189098$12375_Y + attribute \src "libresoc.v:189100.18-189100.100" + wire $or$libresoc.v:189100$12377_Y + attribute \src "libresoc.v:189103.17-189103.98" + wire $or$libresoc.v:189103$12380_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 1 \coresync_rst + attribute \src "libresoc.v:189062.7-189062.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire output 2 \q_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" + wire \qlq_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \qn_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire input 4 \r_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire input 3 \s_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:189097$12374 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:189097$12374_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:189102$12379 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:189102$12379_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:189099$12376 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rdok + connect \Y $not$libresoc.v:189099$12376_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:189101$12378 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rdok + connect \Y $not$libresoc.v:189101$12378_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:189104$12381 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rdok + connect \Y $not$libresoc.v:189104$12381_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:189098$12375 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_rdok + connect \Y $or$libresoc.v:189098$12375_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:189100$12377 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rdok + connect \B \q_int + connect \Y $or$libresoc.v:189100$12377_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:189103$12380 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_rdok + connect \Y $or$libresoc.v:189103$12380_Y + end + attribute \src "libresoc.v:189062.7-189062.20" + process $proc$libresoc.v:189062$12386 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:189084.7-189084.19" + process $proc$libresoc.v:189084$12387 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:189105.3-189106.27" + process $proc$libresoc.v:189105$12382 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:189107.3-189115.6" + process $proc$libresoc.v:189107$12383 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$12384 $1\q_int$next[0:0]$12385 + attribute \src "libresoc.v:189108.5-189108.29" + switch \initial + attribute \src "libresoc.v:189108.9-189108.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$12385 1'0 + case + assign $1\q_int$next[0:0]$12385 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$12384 + end + connect \$9 $and$libresoc.v:189097$12374_Y + connect \$11 $or$libresoc.v:189098$12375_Y + connect \$13 $not$libresoc.v:189099$12376_Y + connect \$15 $or$libresoc.v:189100$12377_Y + connect \$1 $not$libresoc.v:189101$12378_Y + connect \$3 $and$libresoc.v:189102$12379_Y + connect \$5 $or$libresoc.v:189103$12380_Y + connect \$7 $not$libresoc.v:189104$12381_Y + connect \qlq_rdok \$15 + connect \qn_rdok \$13 + connect \q_rdok \$11 +end +attribute \src "libresoc.v:189123.1-189474.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1.main.rotator" +attribute \generator "nMigen" +module \rotator + attribute \src "libresoc.v:189392.3-189401.6" + wire $0\carry_out_o[0:0] + attribute \src "libresoc.v:189324.3-189338.6" + wire width 32 $0\hi32[31:0] + attribute \src "libresoc.v:189124.7-189124.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:189414.3-189447.6" + wire width 7 $0\mb$8[6:0]$12435 + attribute \src "libresoc.v:189448.3-189462.6" + wire width 7 $0\me$13[6:0]$12440 + attribute \src "libresoc.v:189349.3-189360.6" + wire width 64 $0\mr[63:0] + attribute \src "libresoc.v:189361.3-189372.6" + wire width 2 $0\output_mode[1:0] + attribute \src "libresoc.v:189373.3-189391.6" + wire width 64 $0\result_o[63:0] + attribute \src "libresoc.v:189339.3-189348.6" + wire width 7 $0\right_mask_shift[6:0] + attribute \src "libresoc.v:189402.3-189413.6" + wire width 6 $0\rot_count[5:0] + attribute \src "libresoc.v:189392.3-189401.6" + wire $1\carry_out_o[0:0] + attribute \src "libresoc.v:189324.3-189338.6" + wire width 32 $1\hi32[31:0] + attribute \src "libresoc.v:189414.3-189447.6" + wire width 7 $1\mb$8[6:0]$12436 + attribute \src "libresoc.v:189448.3-189462.6" + wire width 7 $1\me$13[6:0]$12441 + attribute \src "libresoc.v:189349.3-189360.6" + wire width 64 $1\mr[63:0] + attribute \src "libresoc.v:189361.3-189372.6" + wire width 2 $1\output_mode[1:0] + attribute \src "libresoc.v:189373.3-189391.6" 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"/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:172" + cell $not $not$libresoc.v:189301$12417 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \$63 + connect \Y $not$libresoc.v:189301$12417_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:176" + cell $not $not$libresoc.v:189306$12422 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \mr + connect \Y $not$libresoc.v:189306$12422_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:178" + cell $not $not$libresoc.v:189308$12424 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \ml + connect \Y $not$libresoc.v:189308$12424_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:161" + cell $or $or$libresoc.v:189287$12403 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$36 + connect \B \right_shift + connect \Y $or$libresoc.v:189287$12403_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:170" + cell $or $or$libresoc.v:189297$12413 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \$48 + connect \B \$54 + connect \Y $or$libresoc.v:189297$12413_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:172" + cell $or $or$libresoc.v:189298$12414 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \mr + connect \B \ml + connect \Y $or$libresoc.v:189298$12414_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:172" + cell $or $or$libresoc.v:189300$12416 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \mr + connect \B \ml + connect \Y $or$libresoc.v:189300$12416_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:172" + cell $or $or$libresoc.v:189303$12419 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \$60 + connect \B \$66 + connect \Y $or$libresoc.v:189303$12419_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:176" + cell $or $or$libresoc.v:189307$12423 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \rot + connect \B \$72 + connect \Y $or$libresoc.v:189307$12423_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:51" + cell $pos $pos$libresoc.v:189273$12389 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 7 + connect \A $extend$libresoc.v:189273$12388_Y + connect \Y $pos$libresoc.v:189273$12389_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:178" + cell $reduce_or $reduce_or$libresoc.v:189310$12426 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 1 + connect \A \$79 + connect \Y $reduce_or$libresoc.v:189310$12426_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:144" + cell $sub $sub$libresoc.v:189280$12396 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 8 + connect \A 7'1000000 + connect \B \mb$8 + connect \Y $sub$libresoc.v:189280$12396_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:151" + cell $sub $sub$libresoc.v:189283$12399 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 8 + connect \A 6'111111 + connect \B \me$13 + connect \Y $sub$libresoc.v:189283$12399_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:189311.13-189314.4" + cell \left_mask \left_mask + connect \mask \left_mask_mask + connect \shift \left_mask_shift + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:189315.14-189318.4" + cell \right_mask \right_mask + connect \mask \right_mask_mask + connect \shift \right_mask_shift + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:189319.8-189323.4" + cell \rotl \rotl + connect \a \rotl_a + connect \b \rotl_b + connect \o \rotl_o + end + attribute \src "libresoc.v:189124.7-189124.20" + process $proc$libresoc.v:189124$12442 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:189324.3-189338.6" + process $proc$libresoc.v:189324$12427 + assign { } { } + assign $0\hi32[31:0] $1\hi32[31:0] + attribute \src "libresoc.v:189325.5-189325.29" + switch \initial + attribute \src "libresoc.v:189325.9-189325.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:85" + switch { \sign_ext_rs \is_32bit } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\hi32[31:0] \rs [31:0] + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\hi32[31:0] { \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] } + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\hi32[31:0] \rs [63:32] + end + sync always + update \hi32 $0\hi32[31:0] + end + attribute \src "libresoc.v:189339.3-189348.6" + process $proc$libresoc.v:189339$12428 + assign { } { } + assign { } { } + assign $0\right_mask_shift[6:0] $1\right_mask_shift[6:0] + attribute \src "libresoc.v:189340.5-189340.29" + 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64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \mr $0\mr[63:0] + end + attribute \src "libresoc.v:189361.3-189372.6" + process $proc$libresoc.v:189361$12430 + assign { } { } + assign $0\output_mode[1:0] $1\output_mode[1:0] + attribute \src "libresoc.v:189362.5-189362.29" + switch \initial + attribute \src "libresoc.v:189362.9-189362.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:161" + switch \$38 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\output_mode[1:0] { 1'1 \$40 } + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\output_mode[1:0] { 1'0 \$44 } + end + sync always + update \output_mode $0\output_mode[1:0] + end + attribute \src "libresoc.v:189373.3-189391.6" + process $proc$libresoc.v:189373$12431 + assign { } { } + assign { } { } + assign $0\result_o[63:0] $1\result_o[63:0] + attribute \src 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"libresoc.v:189393.5-189393.29" + switch \initial + attribute \src "libresoc.v:189393.9-189393.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:168" + switch \output_mode + attribute \src "libresoc.v:0.0-0.0" + case 2'11 + assign { } { } + assign $1\carry_out_o[0:0] \$76 + case + assign $1\carry_out_o[0:0] 1'0 + end + sync always + update \carry_out_o $0\carry_out_o[0:0] + end + attribute \src "libresoc.v:189402.3-189413.6" + process $proc$libresoc.v:189402$12433 + assign { } { } + assign $0\rot_count[5:0] $1\rot_count[5:0] + attribute \src "libresoc.v:189403.5-189403.29" + switch \initial + attribute \src "libresoc.v:189403.9-189403.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:98" + switch \right_shift + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rot_count[5:0] \$1 [5:0] + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + 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attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\mb$8[6:0]$12436 [4:0] \sh [4:0] + assign $1\mb$8[6:0]$12436 [6:5] $3\mb$8[6:5]$12438 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:125" + switch \is_32bit + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\mb$8[6:5]$12438 { \sh [5] \$11 } + case + assign $3\mb$8[6:5]$12438 \sh [6:5] + end + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\mb$8[6:0]$12436 { 1'0 \is_32bit 5'00000 } + end + sync always + update \mb$8 $0\mb$8[6:0]$12435 + end + attribute \src "libresoc.v:189448.3-189462.6" + process $proc$libresoc.v:189448$12439 + assign { } { } + assign $0\me$13[6:0]$12440 $1\me$13[6:0]$12441 + attribute \src "libresoc.v:189449.5-189449.29" + switch \initial + attribute \src "libresoc.v:189449.9-189449.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:131" + switch { \$18 \$14 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\me$13[6:0]$12441 { 2'01 \me } + attribute \src "libresoc.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\me$13[6:0]$12441 { 1'0 \mb_extra \mb } + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\me$13[6:0]$12441 { \sh [6] \$20 } + end + sync always + update \me$13 $0\me$13[6:0]$12440 + end + connect \$9 $pos$libresoc.v:189273$12389_Y + connect \$11 $not$libresoc.v:189274$12390_Y + connect \$14 $and$libresoc.v:189275$12391_Y + connect \$16 $not$libresoc.v:189276$12392_Y + connect \$18 $and$libresoc.v:189277$12393_Y + connect \$20 $not$libresoc.v:189278$12394_Y + connect \$22 $le$libresoc.v:189279$12395_Y + connect \$25 $sub$libresoc.v:189280$12396_Y + connect \$27 $le$libresoc.v:189281$12397_Y + connect \$2 $neg$libresoc.v:189282$12398_Y + connect \$30 $sub$libresoc.v:189283$12399_Y + connect \$32 $not$libresoc.v:189284$12400_Y + connect \$34 $not$libresoc.v:189285$12401_Y + connect \$36 $and$libresoc.v:189286$12402_Y + connect \$38 $or$libresoc.v:189287$12403_Y + connect \$40 $and$libresoc.v:189288$12404_Y + connect \$42 $gt$libresoc.v:189289$12405_Y + connect \$44 $and$libresoc.v:189290$12406_Y + connect \$46 $and$libresoc.v:189291$12407_Y + connect \$48 $and$libresoc.v:189292$12408_Y + connect \$4 $not$libresoc.v:189293$12409_Y + connect \$51 $and$libresoc.v:189294$12410_Y + connect \$50 $not$libresoc.v:189295$12411_Y + connect \$54 $and$libresoc.v:189296$12412_Y + connect \$56 $or$libresoc.v:189297$12413_Y + connect \$58 $or$libresoc.v:189298$12414_Y + connect \$60 $and$libresoc.v:189299$12415_Y + connect \$63 $or$libresoc.v:189300$12416_Y + connect \$62 $not$libresoc.v:189301$12417_Y + connect \$66 $and$libresoc.v:189302$12418_Y + connect \$68 $or$libresoc.v:189303$12419_Y + connect \$6 $and$libresoc.v:189304$12420_Y + connect \$70 $and$libresoc.v:189305$12421_Y + connect \$72 $not$libresoc.v:189306$12422_Y + connect \$74 $or$libresoc.v:189307$12423_Y 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"/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:18" + wire width 8 \$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:8" + wire width 64 input 3 \a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:9" + wire width 6 input 1 \b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:11" + wire width 64 output 2 \o + attribute \src "libresoc.v:189490.17-189490.32" + cell $shr $shr$libresoc.v:189490$12444 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 128 + connect \A { \a \a } + connect \B \$2 + connect \Y $shr$libresoc.v:189490$12444_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:18" + cell $sub $sub$libresoc.v:189489$12443 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 8 + connect \A 7'1000000 + connect \B \b + connect \Y $sub$libresoc.v:189489$12443_Y + end + connect \$2 $sub$libresoc.v:189489$12443_Y + connect \$1 $shr$libresoc.v:189490$12444_Y [63:0] + connect \o \$1 +end +attribute \src "libresoc.v:189496.1-189554.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.rst_l" +attribute \generator "nMigen" +module \rst_l + attribute \src "libresoc.v:189497.7-189497.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:189542.3-189550.6" + wire $0\q_int$next[0:0]$12455 + attribute \src "libresoc.v:189540.3-189541.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:189542.3-189550.6" + wire $1\q_int$next[0:0]$12456 + attribute \src "libresoc.v:189519.7-189519.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:189532.17-189532.96" + wire $and$libresoc.v:189532$12445_Y + attribute \src "libresoc.v:189537.17-189537.96" + wire $and$libresoc.v:189537$12450_Y + attribute \src "libresoc.v:189534.18-189534.93" + wire $not$libresoc.v:189534$12447_Y + attribute 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"/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire input 2 \s_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:189532$12445 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:189532$12445_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:189537$12450 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:189537$12450_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:189534$12447 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rst + connect \Y $not$libresoc.v:189534$12447_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:189536$12449 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rst + connect \Y $not$libresoc.v:189536$12449_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:189539$12452 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rst + connect \Y $not$libresoc.v:189539$12452_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:189533$12446 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_rst + connect \Y $or$libresoc.v:189533$12446_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:189535$12448 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rst + connect \B \q_int + connect \Y $or$libresoc.v:189535$12448_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:189538$12451 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_rst + connect \Y $or$libresoc.v:189538$12451_Y + end + attribute \src "libresoc.v:189497.7-189497.20" + process $proc$libresoc.v:189497$12457 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:189519.7-189519.19" + process $proc$libresoc.v:189519$12458 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:189540.3-189541.27" + process $proc$libresoc.v:189540$12453 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:189542.3-189550.6" + process $proc$libresoc.v:189542$12454 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$12455 $1\q_int$next[0:0]$12456 + attribute \src "libresoc.v:189543.5-189543.29" + switch \initial + attribute \src "libresoc.v:189543.9-189543.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$12456 1'0 + case + assign $1\q_int$next[0:0]$12456 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$12455 + end + connect \$9 $and$libresoc.v:189532$12445_Y + connect \$11 $or$libresoc.v:189533$12446_Y + connect \$13 $not$libresoc.v:189534$12447_Y + connect \$15 $or$libresoc.v:189535$12448_Y + connect \$1 $not$libresoc.v:189536$12449_Y + connect \$3 $and$libresoc.v:189537$12450_Y + connect \$5 $or$libresoc.v:189538$12451_Y + connect \$7 $not$libresoc.v:189539$12452_Y + connect \qlq_rst \$15 + connect \qn_rst \$13 + connect \q_rst \$11 +end +attribute \src "libresoc.v:189558.1-189616.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.rst_l" +attribute \generator "nMigen" +module \rst_l$104 + attribute \src "libresoc.v:189559.7-189559.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:189604.3-189612.6" + wire $0\q_int$next[0:0]$12469 + attribute \src "libresoc.v:189602.3-189603.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:189604.3-189612.6" + wire $1\q_int$next[0:0]$12470 + attribute \src "libresoc.v:189581.7-189581.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:189594.17-189594.96" + wire $and$libresoc.v:189594$12459_Y + attribute \src "libresoc.v:189599.17-189599.96" + wire $and$libresoc.v:189599$12464_Y + attribute \src "libresoc.v:189596.18-189596.93" + wire $not$libresoc.v:189596$12461_Y + attribute \src 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\s_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:189594$12459 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:189594$12459_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:189599$12464 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:189599$12464_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:189596$12461 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rst + connect \Y $not$libresoc.v:189596$12461_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:189598$12463 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rst + connect \Y $not$libresoc.v:189598$12463_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:189601$12466 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rst + connect \Y $not$libresoc.v:189601$12466_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:189595$12460 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_rst + connect \Y $or$libresoc.v:189595$12460_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:189597$12462 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rst + connect \B \q_int + connect \Y $or$libresoc.v:189597$12462_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:189600$12465 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_rst + connect \Y $or$libresoc.v:189600$12465_Y + end + attribute \src "libresoc.v:189559.7-189559.20" + process $proc$libresoc.v:189559$12471 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:189581.7-189581.19" + process $proc$libresoc.v:189581$12472 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:189602.3-189603.27" + process $proc$libresoc.v:189602$12467 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src 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$and $and$libresoc.v:189656$12473 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:189656$12473_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:189661$12478 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:189661$12478_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:189658$12475 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rst + connect \Y $not$libresoc.v:189658$12475_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:189660$12477 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rst + connect \Y $not$libresoc.v:189660$12477_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:189663$12480 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rst + connect \Y $not$libresoc.v:189663$12480_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:189657$12474 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_rst + connect \Y $or$libresoc.v:189657$12474_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:189659$12476 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rst + connect \B \q_int + connect \Y $or$libresoc.v:189659$12476_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:189662$12479 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_rst + connect \Y $or$libresoc.v:189662$12479_Y + end + attribute \src "libresoc.v:189621.7-189621.20" + process $proc$libresoc.v:189621$12485 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:189643.7-189643.19" + process $proc$libresoc.v:189643$12486 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:189664.3-189665.27" + process $proc$libresoc.v:189664$12481 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:189666.3-189674.6" + process $proc$libresoc.v:189666$12482 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$12483 $1\q_int$next[0:0]$12484 + attribute \src "libresoc.v:189667.5-189667.29" + switch \initial + attribute \src "libresoc.v:189667.9-189667.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$12484 1'0 + case + assign $1\q_int$next[0:0]$12484 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$12483 + end + connect \$9 $and$libresoc.v:189656$12473_Y + connect \$11 $or$libresoc.v:189657$12474_Y + connect \$13 $not$libresoc.v:189658$12475_Y + connect \$15 $or$libresoc.v:189659$12476_Y + connect \$1 $not$libresoc.v:189660$12477_Y + connect \$3 $and$libresoc.v:189661$12478_Y + connect \$5 $or$libresoc.v:189662$12479_Y + connect \$7 $not$libresoc.v:189663$12480_Y + connect \qlq_rst \$15 + connect \qn_rst \$13 + connect \q_rst \$11 +end +attribute \src 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$and$libresoc.v:189718$12487 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:189718$12487_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:189723$12492 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:189723$12492_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:189720$12489 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rst + connect \Y $not$libresoc.v:189720$12489_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:189722$12491 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rst + connect \Y $not$libresoc.v:189722$12491_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:189725$12494 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rst + connect \Y $not$libresoc.v:189725$12494_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:189719$12488 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_rst + connect \Y $or$libresoc.v:189719$12488_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:189721$12490 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rst + connect \B \q_int + connect \Y $or$libresoc.v:189721$12490_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:189724$12493 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_rst + connect \Y $or$libresoc.v:189724$12493_Y + end + attribute \src "libresoc.v:189683.7-189683.20" + process $proc$libresoc.v:189683$12499 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:189705.7-189705.19" + process $proc$libresoc.v:189705$12500 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:189726.3-189727.27" + process $proc$libresoc.v:189726$12495 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:189728.3-189736.6" + process $proc$libresoc.v:189728$12496 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$12497 $1\q_int$next[0:0]$12498 + attribute \src "libresoc.v:189729.5-189729.29" + switch \initial + attribute \src "libresoc.v:189729.9-189729.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$12498 1'0 + case + assign $1\q_int$next[0:0]$12498 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$12497 + end + connect \$9 $and$libresoc.v:189718$12487_Y + connect \$11 $or$libresoc.v:189719$12488_Y + connect \$13 $not$libresoc.v:189720$12489_Y + connect \$15 $or$libresoc.v:189721$12490_Y + connect \$1 $not$libresoc.v:189722$12491_Y + connect \$3 $and$libresoc.v:189723$12492_Y + connect \$5 $or$libresoc.v:189724$12493_Y + connect \$7 $not$libresoc.v:189725$12494_Y + connect \qlq_rst \$15 + connect \qn_rst \$13 + connect \q_rst \$11 +end +attribute \src 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$and$libresoc.v:189780$12501 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:189780$12501_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:189785$12506 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:189785$12506_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:189782$12503 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rst + connect \Y $not$libresoc.v:189782$12503_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:189784$12505 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rst + connect \Y $not$libresoc.v:189784$12505_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:189787$12508 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rst + connect \Y $not$libresoc.v:189787$12508_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:189781$12502 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_rst + connect \Y $or$libresoc.v:189781$12502_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:189783$12504 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rst + connect \B \q_int + connect \Y $or$libresoc.v:189783$12504_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:189786$12507 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_rst + connect \Y $or$libresoc.v:189786$12507_Y + end + attribute \src "libresoc.v:189745.7-189745.20" + process $proc$libresoc.v:189745$12513 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:189767.7-189767.19" + process $proc$libresoc.v:189767$12514 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:189788.3-189789.27" + process $proc$libresoc.v:189788$12509 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:189790.3-189798.6" + process $proc$libresoc.v:189790$12510 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$12511 $1\q_int$next[0:0]$12512 + attribute \src "libresoc.v:189791.5-189791.29" + switch \initial + attribute \src "libresoc.v:189791.9-189791.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$12512 1'0 + case + assign $1\q_int$next[0:0]$12512 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$12511 + end + connect \$9 $and$libresoc.v:189780$12501_Y + connect \$11 $or$libresoc.v:189781$12502_Y + connect \$13 $not$libresoc.v:189782$12503_Y + connect \$15 $or$libresoc.v:189783$12504_Y + connect \$1 $not$libresoc.v:189784$12505_Y + connect \$3 $and$libresoc.v:189785$12506_Y + connect \$5 $or$libresoc.v:189786$12507_Y + connect \$7 $not$libresoc.v:189787$12508_Y + connect \qlq_rst \$15 + connect \qn_rst \$13 + connect \q_rst \$11 +end +attribute \src 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$and$libresoc.v:189842$12515 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:189842$12515_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:189847$12520 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:189847$12520_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:189844$12517 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rst + connect \Y $not$libresoc.v:189844$12517_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:189846$12519 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rst + connect \Y $not$libresoc.v:189846$12519_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:189849$12522 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rst + connect \Y $not$libresoc.v:189849$12522_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:189843$12516 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_rst + connect \Y $or$libresoc.v:189843$12516_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:189845$12518 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rst + connect \B \q_int + connect \Y $or$libresoc.v:189845$12518_Y + end + attribute \src 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{ } + assign { } { } + assign $0\q_int$next[0:0]$12525 $1\q_int$next[0:0]$12526 + attribute \src "libresoc.v:189853.5-189853.29" + switch \initial + attribute \src "libresoc.v:189853.9-189853.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$12526 1'0 + case + assign $1\q_int$next[0:0]$12526 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$12525 + end + connect \$9 $and$libresoc.v:189842$12515_Y + connect \$11 $or$libresoc.v:189843$12516_Y + connect \$13 $not$libresoc.v:189844$12517_Y + connect \$15 $or$libresoc.v:189845$12518_Y + connect \$1 $not$libresoc.v:189846$12519_Y + connect \$3 $and$libresoc.v:189847$12520_Y + connect \$5 $or$libresoc.v:189848$12521_Y + connect \$7 $not$libresoc.v:189849$12522_Y + connect \qlq_rst \$15 + connect \qn_rst \$13 + connect \q_rst \$11 +end +attribute \src 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\A \r_rst + connect \Y $not$libresoc.v:189970$12547_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:189973$12550 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rst + connect \Y $not$libresoc.v:189973$12550_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:189967$12544 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_rst + connect \Y $or$libresoc.v:189967$12544_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:189969$12546 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rst + connect \B \q_int + connect \Y $or$libresoc.v:189969$12546_Y + end + attribute \src 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$and$libresoc.v:190028$12557 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:190028$12557_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:190033$12562 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:190033$12562_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:190030$12559 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rst + connect \Y $not$libresoc.v:190030$12559_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:190032$12561 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rst + connect \Y $not$libresoc.v:190032$12561_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:190035$12564 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rst + connect \Y $not$libresoc.v:190035$12564_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:190029$12558 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_rst + connect \Y $or$libresoc.v:190029$12558_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:190031$12560 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rst + connect \B \q_int + connect \Y $or$libresoc.v:190031$12560_Y + end + attribute \src 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{ } + assign { } { } + assign $0\q_int$next[0:0]$12567 $1\q_int$next[0:0]$12568 + attribute \src "libresoc.v:190039.5-190039.29" + switch \initial + attribute \src "libresoc.v:190039.9-190039.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$12568 1'0 + case + assign $1\q_int$next[0:0]$12568 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$12567 + end + connect \$9 $and$libresoc.v:190028$12557_Y + connect \$11 $or$libresoc.v:190029$12558_Y + connect \$13 $not$libresoc.v:190030$12559_Y + connect \$15 $or$libresoc.v:190031$12560_Y + connect \$1 $not$libresoc.v:190032$12561_Y + connect \$3 $and$libresoc.v:190033$12562_Y + connect \$5 $or$libresoc.v:190034$12563_Y + connect \$7 $not$libresoc.v:190035$12564_Y + connect \qlq_rst \$15 + connect \qn_rst \$13 + connect \q_rst \$11 +end +attribute \src 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$and$libresoc.v:190090$12571 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:190090$12571_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:190095$12576 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:190095$12576_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:190092$12573 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rst + connect \Y $not$libresoc.v:190092$12573_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:190094$12575 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect 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\enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 23 \logical_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 31 \logical_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 34 \logical_op__invert_out$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 15 \logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 37 \logical_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 16 \logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 38 \logical_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 7 \logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 29 \logical_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 30 \logical_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 36 \logical_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 6 \logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 28 \logical_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 5 \logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 27 \logical_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 35 \logical_op__write_cr0$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 32 \logical_op__zero_a$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 input 50 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 output 22 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" + wire width 2 output 49 \operation + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 19 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 20 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 21 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire output 41 \xer_so$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:45" + cell $and $and$libresoc.v:190458$12586 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$21 + connect \B \logical_op__is_signed + connect \Y $and$libresoc.v:190458$12586_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:46" + cell $and $and$libresoc.v:190460$12588 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$25 + connect \B \logical_op__is_signed + connect \Y $and$libresoc.v:190460$12588_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:58" + cell $and $and$libresoc.v:190469$12601 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$43 + connect \B \$45 + connect \Y $and$libresoc.v:190469$12601_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:61" + cell $and $and$libresoc.v:190472$12604 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$49 + connect \B \$51 + connect \Y $and$libresoc.v:190472$12604_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:58" + cell $eq $eq$libresoc.v:190468$12600 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \logical_op__insn_type + connect \B 7'0011110 + connect \Y $eq$libresoc.v:190468$12600_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:61" + cell $eq $eq$libresoc.v:190471$12603 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \logical_op__insn_type + connect \B 7'0011110 + connect \Y $eq$libresoc.v:190471$12603_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:67" + cell $eq $eq$libresoc.v:190474$12606 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \divisor_radicand + connect \B 1'0 + connect \Y $eq$libresoc.v:190474$12606_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:53" + cell $pos $extend$libresoc.v:190461$12589 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \rb + connect \Y $extend$libresoc.v:190461$12589_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + cell $pos $extend$libresoc.v:190462$12591 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \rb + connect \Y $extend$libresoc.v:190462$12591_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:54" + cell $pos $extend$libresoc.v:190464$12594 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \ra + connect \Y $extend$libresoc.v:190464$12594_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + cell $pos $extend$libresoc.v:190465$12596 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \ra + connect \Y $extend$libresoc.v:190465$12596_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:79" + cell $pos $extend$libresoc.v:190477$12609 + parameter \A_SIGNED 0 + parameter \A_WIDTH 95 + parameter \Y_WIDTH 128 + connect \A \$62 + connect \Y $extend$libresoc.v:190477$12609_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:57" + cell $ge $ge$libresoc.v:190467$12599 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 1 + connect \A \abs_dend + connect \B \abs_dor + connect \Y $ge$libresoc.v:190467$12599_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:60" + cell $ge $ge$libresoc.v:190470$12602 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 1 + connect \A \abs_dend [31:0] + connect \B \abs_dor [31:0] + connect \Y $ge$libresoc.v:190470$12602_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:53" + cell $neg $neg$libresoc.v:190461$12590 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \Y_WIDTH 65 + connect \A $extend$libresoc.v:190461$12589_Y + connect \Y $neg$libresoc.v:190461$12590_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:54" + cell $neg $neg$libresoc.v:190464$12595 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \Y_WIDTH 65 + connect \A $extend$libresoc.v:190464$12594_Y + connect \Y $neg$libresoc.v:190464$12595_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + cell $pos $pos$libresoc.v:190462$12592 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \Y_WIDTH 65 + connect \A $extend$libresoc.v:190462$12591_Y + connect \Y $pos$libresoc.v:190462$12592_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + cell $pos $pos$libresoc.v:190465$12597 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \Y_WIDTH 65 + connect \A $extend$libresoc.v:190465$12596_Y + connect \Y $pos$libresoc.v:190465$12597_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:79" + cell $pos $pos$libresoc.v:190477$12610 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \Y_WIDTH 128 + connect \A $extend$libresoc.v:190477$12609_Y + connect \Y $pos$libresoc.v:190477$12610_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:79" + cell $sshl $sshl$libresoc.v:190476$12608 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 95 + connect \A \abs_dend [31:0] + connect \B 6'100000 + connect \Y $sshl$libresoc.v:190476$12608_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:81" + cell $sshl $sshl$libresoc.v:190478$12611 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 191 + connect \A \abs_dend + connect \B 7'1000000 + connect \Y $sshl$libresoc.v:190478$12611_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:45" + cell $mux $ternary$libresoc.v:190457$12585 + parameter \WIDTH 1 + connect \A \ra [63] + connect \B \ra [31] + connect \S \logical_op__is_32bit + connect \Y $ternary$libresoc.v:190457$12585_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:46" + cell $mux $ternary$libresoc.v:190459$12587 + parameter \WIDTH 1 + connect \A \rb [63] + connect \B \rb [31] + connect \S \logical_op__is_32bit + connect \Y $ternary$libresoc.v:190459$12587_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:53" + cell $mux $ternary$libresoc.v:190463$12593 + parameter \WIDTH 65 + connect \A \$32 + connect \B \$30 + connect \S \divisor_neg + connect \Y $ternary$libresoc.v:190463$12593_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:54" + cell $mux $ternary$libresoc.v:190466$12598 + parameter \WIDTH 65 + connect \A \$39 + connect \B \$37 + connect \S \dividend_neg + connect \Y $ternary$libresoc.v:190466$12598_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:41" + cell $mux $ternary$libresoc.v:190473$12605 + parameter \WIDTH 32 + connect \A \abs_dor [63:32] + connect \B 0 + connect \S \logical_op__is_32bit + connect \Y $ternary$libresoc.v:190473$12605_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:41" + cell $mux $ternary$libresoc.v:190475$12607 + parameter \WIDTH 32 + connect \A \abs_dend [63:32] + connect \B 0 + connect \S \logical_op__is_32bit + connect \Y $ternary$libresoc.v:190475$12607_Y + end + attribute \src "libresoc.v:190117.7-190117.20" + process $proc$libresoc.v:190117$12613 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:190479.3-190504.6" + process $proc$libresoc.v:190479$12612 + assign { } { } + assign { } { } + assign $0\dividend[127:0] $1\dividend[127:0] + attribute \src "libresoc.v:190480.5-190480.29" + switch \initial + attribute \src "libresoc.v:190480.9-190480.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:72" + switch \logical_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0011101 , 7'0101111 + assign $1\dividend[127:0] [127:64] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\dividend[127:0] [31:0] \abs_dend [31:0] + assign $1\dividend[127:0] [63:32] \$59 + attribute \src "libresoc.v:0.0-0.0" + case 7'0011110 + assign { } { } + assign $1\dividend[127:0] $2\dividend[127:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:78" + switch \logical_op__is_32bit + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\dividend[127:0] \$61 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\dividend[127:0] \$65 [127:0] + end + case + assign $1\dividend[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \dividend $0\dividend[127:0] + end + connect \$21 $ternary$libresoc.v:190457$12585_Y + connect \$23 $and$libresoc.v:190458$12586_Y + connect \$25 $ternary$libresoc.v:190459$12587_Y + connect \$27 $and$libresoc.v:190460$12588_Y + connect \$30 $neg$libresoc.v:190461$12590_Y + connect \$32 $pos$libresoc.v:190462$12592_Y + connect \$34 $ternary$libresoc.v:190463$12593_Y + connect \$37 $neg$libresoc.v:190464$12595_Y + connect \$39 $pos$libresoc.v:190465$12597_Y + connect \$41 $ternary$libresoc.v:190466$12598_Y + connect \$43 $ge$libresoc.v:190467$12599_Y + connect \$45 $eq$libresoc.v:190468$12600_Y + connect \$47 $and$libresoc.v:190469$12601_Y + connect \$49 $ge$libresoc.v:190470$12602_Y + connect \$51 $eq$libresoc.v:190471$12603_Y + connect \$53 $and$libresoc.v:190472$12604_Y + connect \$55 $ternary$libresoc.v:190473$12605_Y + connect \$57 $eq$libresoc.v:190474$12606_Y + connect \$59 $ternary$libresoc.v:190475$12607_Y + connect \$62 $sshl$libresoc.v:190476$12608_Y + connect \$61 $pos$libresoc.v:190477$12610_Y + connect \$66 $sshl$libresoc.v:190478$12611_Y + connect \$29 \$34 + connect \$36 \$41 + connect \$65 \$66 + connect { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } + connect \muxid$1 \muxid + connect \xer_so$20 \xer_so + connect \div_by_zero \$57 + connect \divisor_radicand [63:32] \$55 + connect \divisor_radicand [31:0] \abs_dor [31:0] + connect \dive_abs_ov32 \$53 + connect \dive_abs_ov64 \$47 + connect \abs_dend \$41 [63:0] + connect \abs_dor \$34 [63:0] + connect \divisor_neg \$27 + connect \dividend_neg \$23 + connect \operation 2'01 +end +attribute \src "libresoc.v:190525.1-191728.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0" +attribute \generator "nMigen" +module \shiftrot0 + attribute \src "libresoc.v:191299.3-191300.25" + wire $0\all_rd_dly[0:0] + attribute \src "libresoc.v:191297.3-191298.46" + wire $0\alu_done_dly[0:0] + attribute \src "libresoc.v:191648.3-191656.6" + wire $0\alu_l_r_alu$next[0:0]$12831 + attribute \src "libresoc.v:191215.3-191216.39" + wire $0\alu_l_r_alu[0:0] + attribute \src "libresoc.v:191485.3-191522.6" + wire width 13 $0\alu_shift_rot0_sr_op__fn_unit$next[12:0]$12748 + attribute \src "libresoc.v:191243.3-191244.75" + wire width 13 $0\alu_shift_rot0_sr_op__fn_unit[12:0] + attribute \src "libresoc.v:191485.3-191522.6" + wire width 64 $0\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12749 + attribute \src "libresoc.v:191245.3-191246.89" + wire width 64 $0\alu_shift_rot0_sr_op__imm_data__data[63:0] + attribute \src "libresoc.v:191485.3-191522.6" + wire $0\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12750 + attribute \src "libresoc.v:191247.3-191248.85" + wire $0\alu_shift_rot0_sr_op__imm_data__ok[0:0] + attribute \src "libresoc.v:191485.3-191522.6" + wire width 2 $0\alu_shift_rot0_sr_op__input_carry$next[1:0]$12751 + attribute \src "libresoc.v:191261.3-191262.83" + wire width 2 $0\alu_shift_rot0_sr_op__input_carry[1:0] + attribute \src "libresoc.v:191485.3-191522.6" + wire $0\alu_shift_rot0_sr_op__input_cr$next[0:0]$12752 + attribute \src "libresoc.v:191265.3-191266.77" + wire $0\alu_shift_rot0_sr_op__input_cr[0:0] + attribute \src "libresoc.v:191485.3-191522.6" + wire width 32 $0\alu_shift_rot0_sr_op__insn$next[31:0]$12753 + attribute \src "libresoc.v:191273.3-191274.69" + wire width 32 $0\alu_shift_rot0_sr_op__insn[31:0] + attribute \src "libresoc.v:191485.3-191522.6" + wire width 7 $0\alu_shift_rot0_sr_op__insn_type$next[6:0]$12754 + attribute \src "libresoc.v:191241.3-191242.79" + wire width 7 $0\alu_shift_rot0_sr_op__insn_type[6:0] + attribute \src "libresoc.v:191485.3-191522.6" + wire $0\alu_shift_rot0_sr_op__invert_in$next[0:0]$12755 + attribute \src "libresoc.v:191259.3-191260.79" + wire $0\alu_shift_rot0_sr_op__invert_in[0:0] + attribute \src "libresoc.v:191485.3-191522.6" + wire $0\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12756 + attribute \src "libresoc.v:191269.3-191270.77" + wire $0\alu_shift_rot0_sr_op__is_32bit[0:0] + attribute \src "libresoc.v:191485.3-191522.6" + wire $0\alu_shift_rot0_sr_op__is_signed$next[0:0]$12757 + attribute \src "libresoc.v:191271.3-191272.79" + wire $0\alu_shift_rot0_sr_op__is_signed[0:0] + attribute \src "libresoc.v:191485.3-191522.6" + wire $0\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12758 + attribute \src "libresoc.v:191253.3-191254.73" + wire $0\alu_shift_rot0_sr_op__oe__oe[0:0] + attribute \src "libresoc.v:191485.3-191522.6" + wire $0\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12759 + attribute \src "libresoc.v:191255.3-191256.73" + wire $0\alu_shift_rot0_sr_op__oe__ok[0:0] + attribute \src "libresoc.v:191485.3-191522.6" + wire $0\alu_shift_rot0_sr_op__output_carry$next[0:0]$12760 + attribute \src "libresoc.v:191263.3-191264.85" + wire $0\alu_shift_rot0_sr_op__output_carry[0:0] + attribute \src "libresoc.v:191485.3-191522.6" + wire $0\alu_shift_rot0_sr_op__output_cr$next[0:0]$12761 + attribute \src "libresoc.v:191267.3-191268.79" + wire $0\alu_shift_rot0_sr_op__output_cr[0:0] + attribute \src "libresoc.v:191485.3-191522.6" + wire $0\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12762 + attribute \src "libresoc.v:191251.3-191252.73" + wire $0\alu_shift_rot0_sr_op__rc__ok[0:0] + attribute \src "libresoc.v:191485.3-191522.6" + wire $0\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12763 + attribute \src "libresoc.v:191249.3-191250.73" + wire $0\alu_shift_rot0_sr_op__rc__rc[0:0] + attribute \src "libresoc.v:191485.3-191522.6" + wire $0\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12764 + attribute \src "libresoc.v:191257.3-191258.79" + wire $0\alu_shift_rot0_sr_op__write_cr0[0:0] + attribute \src "libresoc.v:191639.3-191647.6" + wire $0\alui_l_r_alui$next[0:0]$12828 + attribute \src "libresoc.v:191217.3-191218.43" + wire $0\alui_l_r_alui[0:0] + attribute \src "libresoc.v:191523.3-191544.6" + wire width 64 $0\data_r0__o$next[63:0]$12789 + attribute \src "libresoc.v:191237.3-191238.37" + wire width 64 $0\data_r0__o[63:0] + attribute \src "libresoc.v:191523.3-191544.6" + wire $0\data_r0__o_ok$next[0:0]$12790 + attribute \src "libresoc.v:191239.3-191240.43" + wire $0\data_r0__o_ok[0:0] + attribute \src "libresoc.v:191545.3-191566.6" + wire width 4 $0\data_r1__cr_a$next[3:0]$12797 + attribute \src "libresoc.v:191233.3-191234.43" + wire width 4 $0\data_r1__cr_a[3:0] + attribute \src "libresoc.v:191545.3-191566.6" + wire $0\data_r1__cr_a_ok$next[0:0]$12798 + attribute \src "libresoc.v:191235.3-191236.49" + wire $0\data_r1__cr_a_ok[0:0] + attribute \src "libresoc.v:191567.3-191588.6" + wire width 2 $0\data_r2__xer_ca$next[1:0]$12805 + attribute \src "libresoc.v:191229.3-191230.47" + wire width 2 $0\data_r2__xer_ca[1:0] + attribute \src "libresoc.v:191567.3-191588.6" + wire $0\data_r2__xer_ca_ok$next[0:0]$12806 + attribute \src "libresoc.v:191231.3-191232.53" + wire $0\data_r2__xer_ca_ok[0:0] + attribute \src "libresoc.v:191657.3-191666.6" + wire width 64 $0\dest1_o[63:0] + attribute \src "libresoc.v:191667.3-191676.6" + wire width 4 $0\dest2_o[3:0] + attribute \src "libresoc.v:191677.3-191686.6" + wire width 2 $0\dest3_o[1:0] + attribute \src "libresoc.v:190526.7-190526.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:191440.3-191448.6" + wire $0\opc_l_r_opc$next[0:0]$12733 + attribute \src "libresoc.v:191283.3-191284.39" + wire $0\opc_l_r_opc[0:0] + attribute \src "libresoc.v:191431.3-191439.6" + wire $0\opc_l_s_opc$next[0:0]$12730 + attribute \src "libresoc.v:191285.3-191286.39" + wire $0\opc_l_s_opc[0:0] + attribute \src "libresoc.v:191687.3-191695.6" + wire width 3 $0\prev_wr_go$next[2:0]$12837 + attribute \src "libresoc.v:191295.3-191296.37" + wire width 3 $0\prev_wr_go[2:0] + attribute \src "libresoc.v:191385.3-191394.6" + wire $0\req_done[0:0] + attribute \src "libresoc.v:191476.3-191484.6" + wire width 3 $0\req_l_r_req$next[2:0]$12745 + attribute \src "libresoc.v:191275.3-191276.39" + wire width 3 $0\req_l_r_req[2:0] + attribute \src "libresoc.v:191467.3-191475.6" + wire width 3 $0\req_l_s_req$next[2:0]$12742 + attribute \src "libresoc.v:191277.3-191278.39" + wire width 3 $0\req_l_s_req[2:0] + attribute \src "libresoc.v:191404.3-191412.6" + wire $0\rok_l_r_rdok$next[0:0]$12721 + attribute \src "libresoc.v:191291.3-191292.41" + wire $0\rok_l_r_rdok[0:0] + attribute \src "libresoc.v:191395.3-191403.6" + wire $0\rok_l_s_rdok$next[0:0]$12718 + attribute \src "libresoc.v:191293.3-191294.41" + wire $0\rok_l_s_rdok[0:0] + attribute \src "libresoc.v:191422.3-191430.6" + wire $0\rst_l_r_rst$next[0:0]$12727 + attribute \src "libresoc.v:191287.3-191288.39" + wire $0\rst_l_r_rst[0:0] + attribute \src "libresoc.v:191413.3-191421.6" + wire $0\rst_l_s_rst$next[0:0]$12724 + attribute \src "libresoc.v:191289.3-191290.39" + wire $0\rst_l_s_rst[0:0] + attribute \src "libresoc.v:191458.3-191466.6" + wire width 5 $0\src_l_r_src$next[4:0]$12739 + attribute \src "libresoc.v:191279.3-191280.39" + wire width 5 $0\src_l_r_src[4:0] + attribute \src "libresoc.v:191449.3-191457.6" + wire width 5 $0\src_l_s_src$next[4:0]$12736 + attribute \src "libresoc.v:191281.3-191282.39" + wire width 5 $0\src_l_s_src[4:0] + attribute \src "libresoc.v:191589.3-191598.6" + wire width 64 $0\src_r0$next[63:0]$12813 + attribute \src "libresoc.v:191227.3-191228.29" + wire width 64 $0\src_r0[63:0] + attribute \src "libresoc.v:191599.3-191608.6" + wire width 64 $0\src_r1$next[63:0]$12816 + attribute \src "libresoc.v:191225.3-191226.29" + wire width 64 $0\src_r1[63:0] + attribute \src "libresoc.v:191609.3-191618.6" + wire width 64 $0\src_r2$next[63:0]$12819 + attribute \src "libresoc.v:191223.3-191224.29" + wire width 64 $0\src_r2[63:0] + attribute \src "libresoc.v:191619.3-191628.6" + wire $0\src_r3$next[0:0]$12822 + attribute \src "libresoc.v:191221.3-191222.29" + wire $0\src_r3[0:0] + attribute \src "libresoc.v:191629.3-191638.6" + wire width 2 $0\src_r4$next[1:0]$12825 + attribute \src "libresoc.v:191219.3-191220.29" + wire width 2 $0\src_r4[1:0] + attribute \src "libresoc.v:190648.7-190648.24" + wire $1\all_rd_dly[0:0] + attribute \src "libresoc.v:190658.7-190658.26" + wire $1\alu_done_dly[0:0] + attribute \src "libresoc.v:191648.3-191656.6" + wire $1\alu_l_r_alu$next[0:0]$12832 + attribute \src "libresoc.v:190666.7-190666.25" + wire $1\alu_l_r_alu[0:0] + attribute \src "libresoc.v:191485.3-191522.6" + wire width 13 $1\alu_shift_rot0_sr_op__fn_unit$next[12:0]$12765 + attribute \src "libresoc.v:190708.14-190708.54" + wire width 13 $1\alu_shift_rot0_sr_op__fn_unit[12:0] + attribute \src "libresoc.v:191485.3-191522.6" + wire width 64 $1\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12766 + attribute \src "libresoc.v:190712.14-190712.73" + wire width 64 $1\alu_shift_rot0_sr_op__imm_data__data[63:0] + attribute \src "libresoc.v:191485.3-191522.6" + wire $1\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12767 + attribute \src "libresoc.v:190716.7-190716.48" + wire $1\alu_shift_rot0_sr_op__imm_data__ok[0:0] + attribute \src "libresoc.v:191485.3-191522.6" + wire width 2 $1\alu_shift_rot0_sr_op__input_carry$next[1:0]$12768 + attribute \src "libresoc.v:190724.13-190724.53" + wire width 2 $1\alu_shift_rot0_sr_op__input_carry[1:0] + attribute \src "libresoc.v:191485.3-191522.6" + wire $1\alu_shift_rot0_sr_op__input_cr$next[0:0]$12769 + attribute \src "libresoc.v:190728.7-190728.44" + wire $1\alu_shift_rot0_sr_op__input_cr[0:0] + attribute \src "libresoc.v:191485.3-191522.6" + wire width 32 $1\alu_shift_rot0_sr_op__insn$next[31:0]$12770 + attribute \src "libresoc.v:190732.14-190732.48" + wire width 32 $1\alu_shift_rot0_sr_op__insn[31:0] + attribute \src "libresoc.v:191485.3-191522.6" + wire width 7 $1\alu_shift_rot0_sr_op__insn_type$next[6:0]$12771 + attribute \src "libresoc.v:190810.13-190810.52" + wire width 7 $1\alu_shift_rot0_sr_op__insn_type[6:0] + attribute \src "libresoc.v:191485.3-191522.6" + wire $1\alu_shift_rot0_sr_op__invert_in$next[0:0]$12772 + attribute \src "libresoc.v:190814.7-190814.45" + wire $1\alu_shift_rot0_sr_op__invert_in[0:0] + attribute \src "libresoc.v:191485.3-191522.6" + wire $1\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12773 + attribute \src "libresoc.v:190818.7-190818.44" + wire $1\alu_shift_rot0_sr_op__is_32bit[0:0] + attribute \src "libresoc.v:191485.3-191522.6" + wire $1\alu_shift_rot0_sr_op__is_signed$next[0:0]$12774 + attribute \src "libresoc.v:190822.7-190822.45" + wire $1\alu_shift_rot0_sr_op__is_signed[0:0] + attribute \src "libresoc.v:191485.3-191522.6" + wire $1\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12775 + attribute \src "libresoc.v:190826.7-190826.42" + wire $1\alu_shift_rot0_sr_op__oe__oe[0:0] + attribute \src "libresoc.v:191485.3-191522.6" + wire $1\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12776 + attribute \src "libresoc.v:190830.7-190830.42" + wire $1\alu_shift_rot0_sr_op__oe__ok[0:0] + attribute \src "libresoc.v:191485.3-191522.6" + wire $1\alu_shift_rot0_sr_op__output_carry$next[0:0]$12777 + attribute \src "libresoc.v:190834.7-190834.48" + wire $1\alu_shift_rot0_sr_op__output_carry[0:0] + attribute \src "libresoc.v:191485.3-191522.6" + wire $1\alu_shift_rot0_sr_op__output_cr$next[0:0]$12778 + attribute \src "libresoc.v:190838.7-190838.45" + wire $1\alu_shift_rot0_sr_op__output_cr[0:0] + attribute \src "libresoc.v:191485.3-191522.6" + wire $1\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12779 + attribute \src "libresoc.v:190842.7-190842.42" + wire $1\alu_shift_rot0_sr_op__rc__ok[0:0] + attribute \src "libresoc.v:191485.3-191522.6" + wire $1\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12780 + attribute \src "libresoc.v:190846.7-190846.42" + wire $1\alu_shift_rot0_sr_op__rc__rc[0:0] + attribute \src "libresoc.v:191485.3-191522.6" + wire $1\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12781 + attribute \src "libresoc.v:190850.7-190850.45" + wire $1\alu_shift_rot0_sr_op__write_cr0[0:0] + attribute \src "libresoc.v:191639.3-191647.6" + wire $1\alui_l_r_alui$next[0:0]$12829 + attribute \src "libresoc.v:190862.7-190862.27" + wire $1\alui_l_r_alui[0:0] + attribute \src "libresoc.v:191523.3-191544.6" + wire width 64 $1\data_r0__o$next[63:0]$12791 + attribute \src "libresoc.v:190896.14-190896.47" + wire width 64 $1\data_r0__o[63:0] + attribute \src "libresoc.v:191523.3-191544.6" + wire $1\data_r0__o_ok$next[0:0]$12792 + attribute \src "libresoc.v:190900.7-190900.27" + wire $1\data_r0__o_ok[0:0] + attribute \src "libresoc.v:191545.3-191566.6" + wire width 4 $1\data_r1__cr_a$next[3:0]$12799 + attribute \src "libresoc.v:190904.13-190904.33" + wire width 4 $1\data_r1__cr_a[3:0] + attribute \src "libresoc.v:191545.3-191566.6" + wire $1\data_r1__cr_a_ok$next[0:0]$12800 + attribute \src "libresoc.v:190908.7-190908.30" + wire $1\data_r1__cr_a_ok[0:0] + attribute \src "libresoc.v:191567.3-191588.6" + wire width 2 $1\data_r2__xer_ca$next[1:0]$12807 + attribute \src "libresoc.v:190912.13-190912.35" + wire width 2 $1\data_r2__xer_ca[1:0] + attribute \src "libresoc.v:191567.3-191588.6" + wire $1\data_r2__xer_ca_ok$next[0:0]$12808 + attribute \src "libresoc.v:190916.7-190916.32" + wire $1\data_r2__xer_ca_ok[0:0] + attribute \src "libresoc.v:191657.3-191666.6" + wire width 64 $1\dest1_o[63:0] + attribute \src "libresoc.v:191667.3-191676.6" + wire width 4 $1\dest2_o[3:0] + attribute \src "libresoc.v:191677.3-191686.6" + wire width 2 $1\dest3_o[1:0] + attribute \src "libresoc.v:191440.3-191448.6" + wire $1\opc_l_r_opc$next[0:0]$12734 + attribute \src "libresoc.v:190933.7-190933.25" + wire $1\opc_l_r_opc[0:0] + attribute \src "libresoc.v:191431.3-191439.6" + wire $1\opc_l_s_opc$next[0:0]$12731 + attribute \src "libresoc.v:190937.7-190937.25" + wire $1\opc_l_s_opc[0:0] + attribute \src "libresoc.v:191687.3-191695.6" + wire width 3 $1\prev_wr_go$next[2:0]$12838 + attribute \src "libresoc.v:191067.13-191067.30" + wire width 3 $1\prev_wr_go[2:0] + attribute \src "libresoc.v:191385.3-191394.6" + wire $1\req_done[0:0] + attribute \src "libresoc.v:191476.3-191484.6" + wire width 3 $1\req_l_r_req$next[2:0]$12746 + attribute \src "libresoc.v:191075.13-191075.31" + wire width 3 $1\req_l_r_req[2:0] + attribute \src "libresoc.v:191467.3-191475.6" + wire width 3 $1\req_l_s_req$next[2:0]$12743 + attribute \src "libresoc.v:191079.13-191079.31" + wire width 3 $1\req_l_s_req[2:0] + attribute \src "libresoc.v:191404.3-191412.6" + wire $1\rok_l_r_rdok$next[0:0]$12722 + attribute \src "libresoc.v:191091.7-191091.26" + wire $1\rok_l_r_rdok[0:0] + attribute \src "libresoc.v:191395.3-191403.6" + wire $1\rok_l_s_rdok$next[0:0]$12719 + attribute \src "libresoc.v:191095.7-191095.26" + wire $1\rok_l_s_rdok[0:0] + attribute \src "libresoc.v:191422.3-191430.6" + wire $1\rst_l_r_rst$next[0:0]$12728 + attribute \src "libresoc.v:191099.7-191099.25" + wire $1\rst_l_r_rst[0:0] + attribute \src "libresoc.v:191413.3-191421.6" + wire $1\rst_l_s_rst$next[0:0]$12725 + attribute \src "libresoc.v:191103.7-191103.25" + wire $1\rst_l_s_rst[0:0] + attribute \src "libresoc.v:191458.3-191466.6" + wire width 5 $1\src_l_r_src$next[4:0]$12740 + attribute \src "libresoc.v:191121.13-191121.32" + wire width 5 $1\src_l_r_src[4:0] + attribute \src "libresoc.v:191449.3-191457.6" + wire width 5 $1\src_l_s_src$next[4:0]$12737 + attribute \src "libresoc.v:191125.13-191125.32" + wire width 5 $1\src_l_s_src[4:0] + attribute \src "libresoc.v:191589.3-191598.6" + wire width 64 $1\src_r0$next[63:0]$12814 + attribute \src "libresoc.v:191131.14-191131.43" + wire width 64 $1\src_r0[63:0] + attribute \src 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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \alu_shift_rot0_sr_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \alu_shift_rot0_sr_op__imm_data__data$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_shift_rot0_sr_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_shift_rot0_sr_op__imm_data__ok$next + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \alu_shift_rot0_sr_op__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \alu_shift_rot0_sr_op__input_carry$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_shift_rot0_sr_op__input_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_shift_rot0_sr_op__input_cr$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \alu_shift_rot0_sr_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \alu_shift_rot0_sr_op__insn$next + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute 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\enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \alu_shift_rot0_sr_op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \alu_shift_rot0_sr_op__insn_type$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_shift_rot0_sr_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_shift_rot0_sr_op__invert_in$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_shift_rot0_sr_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_shift_rot0_sr_op__is_32bit$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_shift_rot0_sr_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_shift_rot0_sr_op__is_signed$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_shift_rot0_sr_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_shift_rot0_sr_op__oe__oe$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_shift_rot0_sr_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_shift_rot0_sr_op__oe__ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_shift_rot0_sr_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_shift_rot0_sr_op__output_carry$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_shift_rot0_sr_op__output_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_shift_rot0_sr_op__output_cr$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_shift_rot0_sr_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_shift_rot0_sr_op__rc__ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_shift_rot0_sr_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_shift_rot0_sr_op__rc__rc$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_shift_rot0_sr_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_shift_rot0_sr_op__write_cr0$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 \alu_shift_rot0_xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 \alu_shift_rot0_xer_ca$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \alu_shift_rot0_xer_so + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire \alui_l_q_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \alui_l_r_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \alui_l_r_alui$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire \alui_l_s_alui + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 37 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 33 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" + wire output 20 \cu_busy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:108" + wire \cu_done_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:104" + wire \cu_go_die_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" + wire input 19 \cu_issue_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 5 input 23 \cu_rd__go_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 5 output 22 \cu_rd__rel_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" + wire width 5 input 21 \cu_rdmaskn_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:102" + wire \cu_shadown_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 input 31 \cu_wr__go_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 output 30 \cu_wr__rel_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:97" + wire width 3 \cu_wrmask_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 64 \data_r0__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 64 \data_r0__o$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r0__o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r0__o_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 4 \data_r1__cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 4 \data_r1__cr_a$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r1__cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r1__cr_a_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 2 \data_r2__xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 2 \data_r2__xer_ca$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r2__xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r2__xer_ca_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 32 \dest1_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 4 output 34 \dest2_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 2 output 36 \dest3_o + attribute \src "libresoc.v:190526.7-190526.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 29 \o_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire \opc_l_q_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \opc_l_r_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \opc_l_r_opc$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire \opc_l_s_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire \opc_l_s_opc$next + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 input 3 \oper_i_alu_shift_rot0__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 4 \oper_i_alu_shift_rot0__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 5 \oper_i_alu_shift_rot0__imm_data__ok + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 12 \oper_i_alu_shift_rot0__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \oper_i_alu_shift_rot0__input_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 18 \oper_i_alu_shift_rot0__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute 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connect \B { 3'111 \$96 1'1 } + connect \Y $and$libresoc.v:191214$12672_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + cell $eq $eq$libresoc.v:191184$12642 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$42 + connect \B 1'0 + connect \Y $eq$libresoc.v:191184$12642_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + cell $eq $eq$libresoc.v:191186$12644 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_wrmask_o + connect \B 1'0 + connect \Y $eq$libresoc.v:191186$12644_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + cell $not $not$libresoc.v:191156$12614 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \cu_rdmaskn_i + connect \Y $not$libresoc.v:191156$12614_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $not $not$libresoc.v:191167$12625 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \all_rd_dly + connect \Y $not$libresoc.v:191167$12625_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $not $not$libresoc.v:191169$12627 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_done_dly + connect \Y $not$libresoc.v:191169$12627_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $not $not$libresoc.v:191172$12630 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \cu_wrmask_o + connect \Y $not$libresoc.v:191172$12630_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $not $not$libresoc.v:191175$12633 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$23 + connect \Y $not$libresoc.v:191175$12633_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + cell $not $not$libresoc.v:191181$12639 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_shift_rot0_n_ready_i + connect \Y $not$libresoc.v:191181$12639_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $not $not$libresoc.v:191192$12650 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \cu_rd__rel_o + connect \Y $not$libresoc.v:191192$12650_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" + cell $not $not$libresoc.v:191213$12671 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_shift_rot0_sr_op__imm_data__ok + connect \Y $not$libresoc.v:191213$12671_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $or $or$libresoc.v:191180$12638 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$32 + connect \B \$34 + connect \Y $or$libresoc.v:191180$12638_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" + cell $or $or$libresoc.v:191190$12648 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \req_done + connect \B \cu_go_die_i + connect \Y $or$libresoc.v:191190$12648_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" + cell $or $or$libresoc.v:191191$12649 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_issue_i + connect \B \cu_go_die_i + connect \Y $or$libresoc.v:191191$12649_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" + cell $or $or$libresoc.v:191193$12651 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \cu_wr__go_i + connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } + connect \Y $or$libresoc.v:191193$12651_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" + cell $or $or$libresoc.v:191194$12652 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \cu_rd__go_i + connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } + connect \Y $or$libresoc.v:191194$12652_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" + cell $or $or$libresoc.v:191197$12655 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \reset_w + connect \B \prev_wr_go + connect \Y $or$libresoc.v:191197$12655_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $or $or$libresoc.v:191203$12661 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \$5 + connect \B \cu_rd__go_i + connect \Y $or$libresoc.v:191203$12661_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $reduce_and $reduce_and$libresoc.v:191209$12667 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \$7 + connect \Y $reduce_and$libresoc.v:191209$12667_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $reduce_or $reduce_or$libresoc.v:191174$12632 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \$26 + connect \Y $reduce_or$libresoc.v:191174$12632_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $reduce_or $reduce_or$libresoc.v:191178$12636 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \cu_wr__go_i + connect \Y $reduce_or$libresoc.v:191178$12636_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $reduce_or $reduce_or$libresoc.v:191179$12637 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \prev_wr_go + connect \Y $reduce_or$libresoc.v:191179$12637_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" + cell $mux $ternary$libresoc.v:191201$12659 + parameter \WIDTH 1 + connect \A \src_l_q_src [1] + connect \B \opc_l_q_opc + connect \S \alu_shift_rot0_sr_op__imm_data__ok + connect \Y $ternary$libresoc.v:191201$12659_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" + cell $mux $ternary$libresoc.v:191202$12660 + parameter \WIDTH 64 + connect \A \src2_i + connect \B \alu_shift_rot0_sr_op__imm_data__data + connect \S \alu_shift_rot0_sr_op__imm_data__ok + connect \Y $ternary$libresoc.v:191202$12660_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" + cell $mux $ternary$libresoc.v:191204$12662 + parameter \WIDTH 64 + connect \A \src_r0 + connect \B \src1_i + connect \S \src_l_q_src [0] + connect \Y $ternary$libresoc.v:191204$12662_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" + cell $mux $ternary$libresoc.v:191205$12663 + parameter \WIDTH 64 + connect \A \src_r1 + connect \B \src_or_imm + connect \S \src_sel + connect \Y $ternary$libresoc.v:191205$12663_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" + cell $mux $ternary$libresoc.v:191206$12664 + parameter \WIDTH 64 + connect \A \src_r2 + connect \B \src3_i + connect \S \src_l_q_src [2] + connect \Y $ternary$libresoc.v:191206$12664_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" + cell $mux $ternary$libresoc.v:191207$12665 + parameter \WIDTH 1 + connect \A \src_r3 + connect \B \src4_i + connect \S \src_l_q_src [3] + connect \Y $ternary$libresoc.v:191207$12665_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" + cell $mux $ternary$libresoc.v:191208$12666 + parameter \WIDTH 2 + connect \A \src_r4 + connect \B \src5_i + connect \S \src_l_q_src [4] + connect \Y $ternary$libresoc.v:191208$12666_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:191301.15-191307.4" + cell \alu_l$125 \alu_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_alu \alu_l_q_alu + connect \r_alu \alu_l_r_alu + connect \s_alu \alu_l_s_alu + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:191308.18-191343.4" + cell \alu_shift_rot0 \alu_shift_rot0 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cr_a \alu_shift_rot0_cr_a + connect \cr_a_ok \cr_a_ok + connect \n_ready_i \alu_shift_rot0_n_ready_i + connect \n_valid_o \alu_shift_rot0_n_valid_o + connect \o \alu_shift_rot0_o + connect \o_ok \o_ok + connect \p_ready_o \alu_shift_rot0_p_ready_o + connect \p_valid_i \alu_shift_rot0_p_valid_i + connect \ra \alu_shift_rot0_ra + connect \rb \alu_shift_rot0_rb + connect \rc \alu_shift_rot0_rc + connect \sr_op__fn_unit \alu_shift_rot0_sr_op__fn_unit + connect \sr_op__imm_data__data \alu_shift_rot0_sr_op__imm_data__data + connect \sr_op__imm_data__ok \alu_shift_rot0_sr_op__imm_data__ok + connect \sr_op__input_carry \alu_shift_rot0_sr_op__input_carry + connect \sr_op__input_cr \alu_shift_rot0_sr_op__input_cr + connect \sr_op__insn \alu_shift_rot0_sr_op__insn + connect \sr_op__insn_type \alu_shift_rot0_sr_op__insn_type + connect \sr_op__invert_in \alu_shift_rot0_sr_op__invert_in + connect \sr_op__is_32bit \alu_shift_rot0_sr_op__is_32bit + connect \sr_op__is_signed \alu_shift_rot0_sr_op__is_signed + connect \sr_op__oe__oe \alu_shift_rot0_sr_op__oe__oe + connect \sr_op__oe__ok \alu_shift_rot0_sr_op__oe__ok + connect \sr_op__output_carry \alu_shift_rot0_sr_op__output_carry + connect \sr_op__output_cr \alu_shift_rot0_sr_op__output_cr + connect \sr_op__rc__ok \alu_shift_rot0_sr_op__rc__ok + connect \sr_op__rc__rc \alu_shift_rot0_sr_op__rc__rc + connect \sr_op__write_cr0 \alu_shift_rot0_sr_op__write_cr0 + connect \xer_ca \alu_shift_rot0_xer_ca + connect \xer_ca$1 \alu_shift_rot0_xer_ca$1 + connect \xer_ca_ok \xer_ca_ok + connect \xer_so \alu_shift_rot0_xer_so + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:191344.16-191350.4" + cell \alui_l$124 \alui_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_alui \alui_l_q_alui + connect \r_alui \alui_l_r_alui + connect \s_alui \alui_l_s_alui + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:191351.15-191357.4" + cell \opc_l$120 \opc_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_opc \opc_l_q_opc + connect \r_opc \opc_l_r_opc + connect \s_opc \opc_l_s_opc + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:191358.15-191364.4" + cell \req_l$121 \req_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_req \req_l_q_req + connect \r_req \req_l_r_req + connect \s_req \req_l_s_req + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:191365.15-191371.4" + cell \rok_l$123 \rok_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_rdok \rok_l_q_rdok + connect \r_rdok \rok_l_r_rdok + connect \s_rdok \rok_l_s_rdok + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:191372.15-191377.4" + cell \rst_l$122 \rst_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \r_rst \rst_l_r_rst + connect \s_rst \rst_l_s_rst + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:191378.15-191384.4" + cell \src_l$119 \src_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_src \src_l_q_src + connect \r_src \src_l_r_src + connect \s_src \src_l_s_src + end + attribute \src "libresoc.v:190526.7-190526.20" + process $proc$libresoc.v:190526$12839 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:190648.7-190648.24" + process $proc$libresoc.v:190648$12840 + assign { } { } + assign $1\all_rd_dly[0:0] 1'0 + sync always + sync init + update \all_rd_dly $1\all_rd_dly[0:0] + end + attribute \src "libresoc.v:190658.7-190658.26" + process $proc$libresoc.v:190658$12841 + assign { } { } + assign $1\alu_done_dly[0:0] 1'0 + sync always + sync init + update \alu_done_dly $1\alu_done_dly[0:0] + end + attribute \src "libresoc.v:190666.7-190666.25" + process $proc$libresoc.v:190666$12842 + assign { } { } + assign $1\alu_l_r_alu[0:0] 1'1 + sync always + sync init + update \alu_l_r_alu $1\alu_l_r_alu[0:0] + end + attribute \src "libresoc.v:190708.14-190708.54" + process $proc$libresoc.v:190708$12843 + assign { } { } + assign $1\alu_shift_rot0_sr_op__fn_unit[12:0] 13'0000000000000 + sync always + sync init + update \alu_shift_rot0_sr_op__fn_unit $1\alu_shift_rot0_sr_op__fn_unit[12:0] + end + attribute \src "libresoc.v:190712.14-190712.73" + process $proc$libresoc.v:190712$12844 + assign { } { } + assign $1\alu_shift_rot0_sr_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \alu_shift_rot0_sr_op__imm_data__data $1\alu_shift_rot0_sr_op__imm_data__data[63:0] + end + attribute \src "libresoc.v:190716.7-190716.48" + process $proc$libresoc.v:190716$12845 + assign { } { } + assign $1\alu_shift_rot0_sr_op__imm_data__ok[0:0] 1'0 + sync always + sync init + update \alu_shift_rot0_sr_op__imm_data__ok $1\alu_shift_rot0_sr_op__imm_data__ok[0:0] + end + attribute \src "libresoc.v:190724.13-190724.53" + process $proc$libresoc.v:190724$12846 + assign { } { } + assign $1\alu_shift_rot0_sr_op__input_carry[1:0] 2'00 + sync always + sync init + update \alu_shift_rot0_sr_op__input_carry $1\alu_shift_rot0_sr_op__input_carry[1:0] + end + attribute \src "libresoc.v:190728.7-190728.44" + process $proc$libresoc.v:190728$12847 + assign { } { } + assign $1\alu_shift_rot0_sr_op__input_cr[0:0] 1'0 + sync always + sync init + update \alu_shift_rot0_sr_op__input_cr $1\alu_shift_rot0_sr_op__input_cr[0:0] + end + attribute \src "libresoc.v:190732.14-190732.48" + process $proc$libresoc.v:190732$12848 + assign { } { } + assign $1\alu_shift_rot0_sr_op__insn[31:0] 0 + sync always + sync init + update \alu_shift_rot0_sr_op__insn $1\alu_shift_rot0_sr_op__insn[31:0] + end + attribute \src "libresoc.v:190810.13-190810.52" + process $proc$libresoc.v:190810$12849 + assign { } { } + assign $1\alu_shift_rot0_sr_op__insn_type[6:0] 7'0000000 + sync always + sync init + update \alu_shift_rot0_sr_op__insn_type $1\alu_shift_rot0_sr_op__insn_type[6:0] + end + attribute \src "libresoc.v:190814.7-190814.45" + process $proc$libresoc.v:190814$12850 + assign { } { } + assign $1\alu_shift_rot0_sr_op__invert_in[0:0] 1'0 + sync always + sync init + update \alu_shift_rot0_sr_op__invert_in $1\alu_shift_rot0_sr_op__invert_in[0:0] + end + attribute \src "libresoc.v:190818.7-190818.44" + process $proc$libresoc.v:190818$12851 + assign { } { } + assign $1\alu_shift_rot0_sr_op__is_32bit[0:0] 1'0 + sync always + sync init + update \alu_shift_rot0_sr_op__is_32bit $1\alu_shift_rot0_sr_op__is_32bit[0:0] + end + attribute \src "libresoc.v:190822.7-190822.45" + process $proc$libresoc.v:190822$12852 + assign { } { } + assign $1\alu_shift_rot0_sr_op__is_signed[0:0] 1'0 + sync always + sync init + update \alu_shift_rot0_sr_op__is_signed $1\alu_shift_rot0_sr_op__is_signed[0:0] + end + attribute \src "libresoc.v:190826.7-190826.42" + process $proc$libresoc.v:190826$12853 + assign { } { } + assign $1\alu_shift_rot0_sr_op__oe__oe[0:0] 1'0 + sync always + sync init + update \alu_shift_rot0_sr_op__oe__oe $1\alu_shift_rot0_sr_op__oe__oe[0:0] + end + attribute \src "libresoc.v:190830.7-190830.42" + process $proc$libresoc.v:190830$12854 + assign { } { } + assign $1\alu_shift_rot0_sr_op__oe__ok[0:0] 1'0 + sync always + sync init + update \alu_shift_rot0_sr_op__oe__ok $1\alu_shift_rot0_sr_op__oe__ok[0:0] + end + attribute \src "libresoc.v:190834.7-190834.48" + process $proc$libresoc.v:190834$12855 + assign { } { } + assign $1\alu_shift_rot0_sr_op__output_carry[0:0] 1'0 + sync always + sync init + update \alu_shift_rot0_sr_op__output_carry $1\alu_shift_rot0_sr_op__output_carry[0:0] + end + attribute \src "libresoc.v:190838.7-190838.45" + process $proc$libresoc.v:190838$12856 + assign { } { } + assign $1\alu_shift_rot0_sr_op__output_cr[0:0] 1'0 + sync always + sync init + update \alu_shift_rot0_sr_op__output_cr $1\alu_shift_rot0_sr_op__output_cr[0:0] + end + attribute \src "libresoc.v:190842.7-190842.42" + process $proc$libresoc.v:190842$12857 + assign { } { } + assign $1\alu_shift_rot0_sr_op__rc__ok[0:0] 1'0 + sync always + sync init + update \alu_shift_rot0_sr_op__rc__ok $1\alu_shift_rot0_sr_op__rc__ok[0:0] + end + attribute \src "libresoc.v:190846.7-190846.42" + process $proc$libresoc.v:190846$12858 + assign { } { } + assign $1\alu_shift_rot0_sr_op__rc__rc[0:0] 1'0 + sync always + sync init + update \alu_shift_rot0_sr_op__rc__rc $1\alu_shift_rot0_sr_op__rc__rc[0:0] + end + attribute \src "libresoc.v:190850.7-190850.45" + process $proc$libresoc.v:190850$12859 + assign { } { } + assign $1\alu_shift_rot0_sr_op__write_cr0[0:0] 1'0 + sync always + sync init + update \alu_shift_rot0_sr_op__write_cr0 $1\alu_shift_rot0_sr_op__write_cr0[0:0] + end + attribute \src "libresoc.v:190862.7-190862.27" + process $proc$libresoc.v:190862$12860 + assign { } { } + assign $1\alui_l_r_alui[0:0] 1'1 + sync always + sync init + update \alui_l_r_alui $1\alui_l_r_alui[0:0] + end + attribute \src "libresoc.v:190896.14-190896.47" + process $proc$libresoc.v:190896$12861 + assign { } { } + assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \data_r0__o $1\data_r0__o[63:0] + end + attribute \src "libresoc.v:190900.7-190900.27" + process $proc$libresoc.v:190900$12862 + assign { } { } + assign $1\data_r0__o_ok[0:0] 1'0 + sync always + sync init + update \data_r0__o_ok $1\data_r0__o_ok[0:0] + end + attribute \src "libresoc.v:190904.13-190904.33" + process $proc$libresoc.v:190904$12863 + assign { } { } + assign $1\data_r1__cr_a[3:0] 4'0000 + sync always + sync init + update \data_r1__cr_a $1\data_r1__cr_a[3:0] + end + attribute \src "libresoc.v:190908.7-190908.30" + process $proc$libresoc.v:190908$12864 + assign { } { } + assign $1\data_r1__cr_a_ok[0:0] 1'0 + sync always + sync init + update \data_r1__cr_a_ok $1\data_r1__cr_a_ok[0:0] + end + attribute \src "libresoc.v:190912.13-190912.35" + process $proc$libresoc.v:190912$12865 + assign { } { } + assign $1\data_r2__xer_ca[1:0] 2'00 + sync always + sync init + update \data_r2__xer_ca $1\data_r2__xer_ca[1:0] + end + attribute \src "libresoc.v:190916.7-190916.32" + process $proc$libresoc.v:190916$12866 + assign { } { } + assign $1\data_r2__xer_ca_ok[0:0] 1'0 + sync always + sync init + update \data_r2__xer_ca_ok $1\data_r2__xer_ca_ok[0:0] + end + attribute \src "libresoc.v:190933.7-190933.25" + process $proc$libresoc.v:190933$12867 + assign { } { } + assign $1\opc_l_r_opc[0:0] 1'1 + sync always + sync init + update \opc_l_r_opc $1\opc_l_r_opc[0:0] + end + attribute \src "libresoc.v:190937.7-190937.25" + process $proc$libresoc.v:190937$12868 + assign { } { } + assign $1\opc_l_s_opc[0:0] 1'0 + sync always + sync init + update \opc_l_s_opc $1\opc_l_s_opc[0:0] + end + attribute \src "libresoc.v:191067.13-191067.30" + process $proc$libresoc.v:191067$12869 + assign { } { } + assign $1\prev_wr_go[2:0] 3'000 + sync always + sync init + update \prev_wr_go $1\prev_wr_go[2:0] + end + attribute \src "libresoc.v:191075.13-191075.31" + process $proc$libresoc.v:191075$12870 + assign { } { } + assign $1\req_l_r_req[2:0] 3'111 + sync always + sync init + update \req_l_r_req $1\req_l_r_req[2:0] + end + attribute \src "libresoc.v:191079.13-191079.31" + process $proc$libresoc.v:191079$12871 + assign { } { } + assign $1\req_l_s_req[2:0] 3'000 + sync always + sync init + update \req_l_s_req $1\req_l_s_req[2:0] + end + attribute \src "libresoc.v:191091.7-191091.26" + process $proc$libresoc.v:191091$12872 + assign { } { } + assign $1\rok_l_r_rdok[0:0] 1'1 + sync always + sync init + update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] + end + attribute \src "libresoc.v:191095.7-191095.26" + process $proc$libresoc.v:191095$12873 + assign { } { } + assign $1\rok_l_s_rdok[0:0] 1'0 + sync always + sync init + update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] + end + attribute \src "libresoc.v:191099.7-191099.25" + process $proc$libresoc.v:191099$12874 + assign { } { } + assign $1\rst_l_r_rst[0:0] 1'1 + sync always + sync init + update \rst_l_r_rst $1\rst_l_r_rst[0:0] + end + attribute \src "libresoc.v:191103.7-191103.25" + process $proc$libresoc.v:191103$12875 + assign { } { } + assign $1\rst_l_s_rst[0:0] 1'0 + sync always + sync init + update \rst_l_s_rst $1\rst_l_s_rst[0:0] + end + attribute \src "libresoc.v:191121.13-191121.32" + process $proc$libresoc.v:191121$12876 + assign { } { } + assign $1\src_l_r_src[4:0] 5'11111 + sync always + sync init + update \src_l_r_src $1\src_l_r_src[4:0] + end + attribute \src "libresoc.v:191125.13-191125.32" + process $proc$libresoc.v:191125$12877 + assign { } { } + assign $1\src_l_s_src[4:0] 5'00000 + sync always + sync init + update \src_l_s_src $1\src_l_s_src[4:0] + end + attribute \src "libresoc.v:191131.14-191131.43" + process $proc$libresoc.v:191131$12878 + assign { } { } + assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \src_r0 $1\src_r0[63:0] + end + attribute \src "libresoc.v:191135.14-191135.43" + process $proc$libresoc.v:191135$12879 + assign { } { } + assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \src_r1 $1\src_r1[63:0] + end + attribute \src "libresoc.v:191139.14-191139.43" + process $proc$libresoc.v:191139$12880 + assign { } { } + assign $1\src_r2[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \src_r2 $1\src_r2[63:0] + end + attribute \src "libresoc.v:191143.7-191143.20" + process $proc$libresoc.v:191143$12881 + assign { } { } + assign $1\src_r3[0:0] 1'0 + sync always + sync init + update \src_r3 $1\src_r3[0:0] + end + attribute \src "libresoc.v:191147.13-191147.26" + process $proc$libresoc.v:191147$12882 + assign { } { } + assign $1\src_r4[1:0] 2'00 + sync always + sync init + update \src_r4 $1\src_r4[1:0] + end + attribute \src "libresoc.v:191215.3-191216.39" + process $proc$libresoc.v:191215$12673 + assign { } { } + assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next + sync posedge \coresync_clk + update \alu_l_r_alu $0\alu_l_r_alu[0:0] + end + attribute \src "libresoc.v:191217.3-191218.43" + process $proc$libresoc.v:191217$12674 + assign { } { } + assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next + sync posedge \coresync_clk + update \alui_l_r_alui $0\alui_l_r_alui[0:0] + end + attribute \src "libresoc.v:191219.3-191220.29" + process $proc$libresoc.v:191219$12675 + assign { } { } + assign $0\src_r4[1:0] \src_r4$next + sync posedge \coresync_clk + update \src_r4 $0\src_r4[1:0] + end + attribute \src "libresoc.v:191221.3-191222.29" + process $proc$libresoc.v:191221$12676 + assign { } { } + assign $0\src_r3[0:0] \src_r3$next + sync posedge \coresync_clk + update \src_r3 $0\src_r3[0:0] + end + attribute \src "libresoc.v:191223.3-191224.29" + process $proc$libresoc.v:191223$12677 + assign { } { } + assign $0\src_r2[63:0] \src_r2$next + sync posedge \coresync_clk + update \src_r2 $0\src_r2[63:0] + end + attribute \src "libresoc.v:191225.3-191226.29" + process $proc$libresoc.v:191225$12678 + assign { } { } + assign $0\src_r1[63:0] \src_r1$next + sync posedge \coresync_clk + update \src_r1 $0\src_r1[63:0] + end + attribute \src "libresoc.v:191227.3-191228.29" + process $proc$libresoc.v:191227$12679 + assign { } { } + assign $0\src_r0[63:0] \src_r0$next + sync posedge \coresync_clk + update \src_r0 $0\src_r0[63:0] + end + attribute \src "libresoc.v:191229.3-191230.47" + process $proc$libresoc.v:191229$12680 + assign { } { } + assign $0\data_r2__xer_ca[1:0] \data_r2__xer_ca$next + sync posedge \coresync_clk + update \data_r2__xer_ca $0\data_r2__xer_ca[1:0] + end + attribute \src "libresoc.v:191231.3-191232.53" + process $proc$libresoc.v:191231$12681 + assign { } { } + assign $0\data_r2__xer_ca_ok[0:0] \data_r2__xer_ca_ok$next + sync posedge \coresync_clk + update \data_r2__xer_ca_ok $0\data_r2__xer_ca_ok[0:0] + end + attribute \src "libresoc.v:191233.3-191234.43" + process $proc$libresoc.v:191233$12682 + assign { } { } + assign $0\data_r1__cr_a[3:0] \data_r1__cr_a$next + sync posedge \coresync_clk + update \data_r1__cr_a $0\data_r1__cr_a[3:0] + end + attribute \src "libresoc.v:191235.3-191236.49" + process $proc$libresoc.v:191235$12683 + assign { } { } + assign $0\data_r1__cr_a_ok[0:0] \data_r1__cr_a_ok$next + sync posedge \coresync_clk + update \data_r1__cr_a_ok $0\data_r1__cr_a_ok[0:0] + end + attribute \src "libresoc.v:191237.3-191238.37" + process $proc$libresoc.v:191237$12684 + assign { } { } + assign $0\data_r0__o[63:0] \data_r0__o$next + sync posedge \coresync_clk + update \data_r0__o $0\data_r0__o[63:0] + end + attribute \src "libresoc.v:191239.3-191240.43" + process $proc$libresoc.v:191239$12685 + assign { } { } + assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next + sync posedge \coresync_clk + update \data_r0__o_ok $0\data_r0__o_ok[0:0] + end + attribute \src "libresoc.v:191241.3-191242.79" + process $proc$libresoc.v:191241$12686 + assign { } { } + assign $0\alu_shift_rot0_sr_op__insn_type[6:0] \alu_shift_rot0_sr_op__insn_type$next + sync posedge \coresync_clk + update \alu_shift_rot0_sr_op__insn_type $0\alu_shift_rot0_sr_op__insn_type[6:0] + end + attribute \src "libresoc.v:191243.3-191244.75" + process $proc$libresoc.v:191243$12687 + assign { } { } + assign $0\alu_shift_rot0_sr_op__fn_unit[12:0] \alu_shift_rot0_sr_op__fn_unit$next + sync posedge \coresync_clk + update \alu_shift_rot0_sr_op__fn_unit $0\alu_shift_rot0_sr_op__fn_unit[12:0] + end + attribute \src "libresoc.v:191245.3-191246.89" + process $proc$libresoc.v:191245$12688 + assign { } { } + assign $0\alu_shift_rot0_sr_op__imm_data__data[63:0] \alu_shift_rot0_sr_op__imm_data__data$next + sync posedge \coresync_clk + update \alu_shift_rot0_sr_op__imm_data__data $0\alu_shift_rot0_sr_op__imm_data__data[63:0] + end + attribute \src "libresoc.v:191247.3-191248.85" + process $proc$libresoc.v:191247$12689 + assign { } { } + assign $0\alu_shift_rot0_sr_op__imm_data__ok[0:0] \alu_shift_rot0_sr_op__imm_data__ok$next + sync posedge \coresync_clk + update \alu_shift_rot0_sr_op__imm_data__ok $0\alu_shift_rot0_sr_op__imm_data__ok[0:0] + end + attribute \src "libresoc.v:191249.3-191250.73" + process $proc$libresoc.v:191249$12690 + assign { } { } + assign $0\alu_shift_rot0_sr_op__rc__rc[0:0] \alu_shift_rot0_sr_op__rc__rc$next + sync posedge \coresync_clk + update \alu_shift_rot0_sr_op__rc__rc $0\alu_shift_rot0_sr_op__rc__rc[0:0] + end + attribute \src "libresoc.v:191251.3-191252.73" + process $proc$libresoc.v:191251$12691 + assign { } { } + assign $0\alu_shift_rot0_sr_op__rc__ok[0:0] \alu_shift_rot0_sr_op__rc__ok$next + sync posedge \coresync_clk + update \alu_shift_rot0_sr_op__rc__ok $0\alu_shift_rot0_sr_op__rc__ok[0:0] + end + attribute \src "libresoc.v:191253.3-191254.73" + process $proc$libresoc.v:191253$12692 + assign { } { } + assign $0\alu_shift_rot0_sr_op__oe__oe[0:0] \alu_shift_rot0_sr_op__oe__oe$next + sync posedge \coresync_clk + update \alu_shift_rot0_sr_op__oe__oe $0\alu_shift_rot0_sr_op__oe__oe[0:0] + end + attribute \src "libresoc.v:191255.3-191256.73" + process $proc$libresoc.v:191255$12693 + assign { } { } + assign $0\alu_shift_rot0_sr_op__oe__ok[0:0] \alu_shift_rot0_sr_op__oe__ok$next + sync posedge \coresync_clk + update \alu_shift_rot0_sr_op__oe__ok $0\alu_shift_rot0_sr_op__oe__ok[0:0] + end + attribute \src "libresoc.v:191257.3-191258.79" + process $proc$libresoc.v:191257$12694 + assign { } { } + assign $0\alu_shift_rot0_sr_op__write_cr0[0:0] \alu_shift_rot0_sr_op__write_cr0$next + sync posedge \coresync_clk + update \alu_shift_rot0_sr_op__write_cr0 $0\alu_shift_rot0_sr_op__write_cr0[0:0] + end + attribute \src "libresoc.v:191259.3-191260.79" + process $proc$libresoc.v:191259$12695 + assign { } { } + assign $0\alu_shift_rot0_sr_op__invert_in[0:0] \alu_shift_rot0_sr_op__invert_in$next + sync posedge \coresync_clk + update \alu_shift_rot0_sr_op__invert_in $0\alu_shift_rot0_sr_op__invert_in[0:0] + end + attribute \src "libresoc.v:191261.3-191262.83" + process $proc$libresoc.v:191261$12696 + assign { } { } + assign $0\alu_shift_rot0_sr_op__input_carry[1:0] \alu_shift_rot0_sr_op__input_carry$next + sync posedge \coresync_clk + update \alu_shift_rot0_sr_op__input_carry $0\alu_shift_rot0_sr_op__input_carry[1:0] + end + attribute \src "libresoc.v:191263.3-191264.85" + process $proc$libresoc.v:191263$12697 + assign { } { } + assign $0\alu_shift_rot0_sr_op__output_carry[0:0] \alu_shift_rot0_sr_op__output_carry$next + sync posedge \coresync_clk + update \alu_shift_rot0_sr_op__output_carry $0\alu_shift_rot0_sr_op__output_carry[0:0] + end + attribute \src "libresoc.v:191265.3-191266.77" + process $proc$libresoc.v:191265$12698 + assign { } { } + assign $0\alu_shift_rot0_sr_op__input_cr[0:0] \alu_shift_rot0_sr_op__input_cr$next + sync posedge \coresync_clk + update \alu_shift_rot0_sr_op__input_cr $0\alu_shift_rot0_sr_op__input_cr[0:0] + end + attribute \src "libresoc.v:191267.3-191268.79" + process $proc$libresoc.v:191267$12699 + assign { } { } + assign $0\alu_shift_rot0_sr_op__output_cr[0:0] \alu_shift_rot0_sr_op__output_cr$next + sync posedge \coresync_clk + update \alu_shift_rot0_sr_op__output_cr $0\alu_shift_rot0_sr_op__output_cr[0:0] + end + attribute \src "libresoc.v:191269.3-191270.77" + process $proc$libresoc.v:191269$12700 + assign { } { } + assign $0\alu_shift_rot0_sr_op__is_32bit[0:0] \alu_shift_rot0_sr_op__is_32bit$next + sync posedge \coresync_clk + update \alu_shift_rot0_sr_op__is_32bit $0\alu_shift_rot0_sr_op__is_32bit[0:0] + end + attribute \src "libresoc.v:191271.3-191272.79" + process $proc$libresoc.v:191271$12701 + assign { } { } + assign $0\alu_shift_rot0_sr_op__is_signed[0:0] \alu_shift_rot0_sr_op__is_signed$next + sync posedge \coresync_clk + update \alu_shift_rot0_sr_op__is_signed $0\alu_shift_rot0_sr_op__is_signed[0:0] + end + attribute \src "libresoc.v:191273.3-191274.69" + process $proc$libresoc.v:191273$12702 + assign { } { } + assign $0\alu_shift_rot0_sr_op__insn[31:0] \alu_shift_rot0_sr_op__insn$next + sync posedge \coresync_clk + update \alu_shift_rot0_sr_op__insn $0\alu_shift_rot0_sr_op__insn[31:0] + end + attribute \src "libresoc.v:191275.3-191276.39" + process $proc$libresoc.v:191275$12703 + assign { } { } + assign $0\req_l_r_req[2:0] \req_l_r_req$next + sync posedge \coresync_clk + update \req_l_r_req $0\req_l_r_req[2:0] + end + attribute \src "libresoc.v:191277.3-191278.39" + process $proc$libresoc.v:191277$12704 + assign { } { } + assign $0\req_l_s_req[2:0] \req_l_s_req$next + sync posedge \coresync_clk + update \req_l_s_req $0\req_l_s_req[2:0] + end + attribute \src "libresoc.v:191279.3-191280.39" + process $proc$libresoc.v:191279$12705 + assign { } { } + assign $0\src_l_r_src[4:0] \src_l_r_src$next + sync posedge \coresync_clk + update \src_l_r_src $0\src_l_r_src[4:0] + end + attribute \src "libresoc.v:191281.3-191282.39" + process $proc$libresoc.v:191281$12706 + assign { } { } + assign $0\src_l_s_src[4:0] \src_l_s_src$next + sync posedge \coresync_clk + update \src_l_s_src $0\src_l_s_src[4:0] + end + attribute \src "libresoc.v:191283.3-191284.39" + process $proc$libresoc.v:191283$12707 + assign { } { } + assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next + sync posedge \coresync_clk + update \opc_l_r_opc $0\opc_l_r_opc[0:0] + end + attribute \src "libresoc.v:191285.3-191286.39" + process $proc$libresoc.v:191285$12708 + assign { } { } + assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next + sync posedge \coresync_clk + update \opc_l_s_opc $0\opc_l_s_opc[0:0] + end + attribute \src "libresoc.v:191287.3-191288.39" + process $proc$libresoc.v:191287$12709 + assign { } { } + assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next + sync posedge \coresync_clk + update \rst_l_r_rst $0\rst_l_r_rst[0:0] + end + attribute \src "libresoc.v:191289.3-191290.39" + process $proc$libresoc.v:191289$12710 + assign { } { } + assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next + sync posedge \coresync_clk + update \rst_l_s_rst $0\rst_l_s_rst[0:0] + end + attribute \src "libresoc.v:191291.3-191292.41" + process $proc$libresoc.v:191291$12711 + assign { } { } + assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next + sync posedge \coresync_clk + update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] + end + attribute \src "libresoc.v:191293.3-191294.41" + process $proc$libresoc.v:191293$12712 + assign { } { } + assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next + sync posedge \coresync_clk + update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] + end + attribute \src "libresoc.v:191295.3-191296.37" + process $proc$libresoc.v:191295$12713 + assign { } { } + assign $0\prev_wr_go[2:0] \prev_wr_go$next + sync posedge \coresync_clk + update \prev_wr_go $0\prev_wr_go[2:0] + end + attribute \src "libresoc.v:191297.3-191298.46" + process $proc$libresoc.v:191297$12714 + assign { } { } + assign $0\alu_done_dly[0:0] \alu_shift_rot0_n_valid_o + sync posedge \coresync_clk + update \alu_done_dly $0\alu_done_dly[0:0] + end + attribute \src "libresoc.v:191299.3-191300.25" + process $proc$libresoc.v:191299$12715 + assign { } { } + assign $0\all_rd_dly[0:0] \$10 + sync posedge \coresync_clk + update \all_rd_dly $0\all_rd_dly[0:0] + end + attribute \src "libresoc.v:191385.3-191394.6" + process $proc$libresoc.v:191385$12716 + assign { } { } + assign { } { } + assign $0\req_done[0:0] $1\req_done[0:0] + attribute \src "libresoc.v:191386.5-191386.29" + switch \initial + attribute \src "libresoc.v:191386.9-191386.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + switch \$54 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\req_done[0:0] 1'1 + case + assign $1\req_done[0:0] \$46 + end + sync always + update \req_done $0\req_done[0:0] + end + attribute \src "libresoc.v:191395.3-191403.6" + process $proc$libresoc.v:191395$12717 + assign { } { } + assign { } { } + assign $0\rok_l_s_rdok$next[0:0]$12718 $1\rok_l_s_rdok$next[0:0]$12719 + attribute \src "libresoc.v:191396.5-191396.29" + switch \initial + attribute \src "libresoc.v:191396.9-191396.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rok_l_s_rdok$next[0:0]$12719 1'0 + case + assign $1\rok_l_s_rdok$next[0:0]$12719 \cu_issue_i + end + sync always + update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$12718 + end + attribute \src "libresoc.v:191404.3-191412.6" + process $proc$libresoc.v:191404$12720 + assign { } { } + assign { } { } + assign $0\rok_l_r_rdok$next[0:0]$12721 $1\rok_l_r_rdok$next[0:0]$12722 + attribute \src "libresoc.v:191405.5-191405.29" + switch \initial + attribute \src "libresoc.v:191405.9-191405.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rok_l_r_rdok$next[0:0]$12722 1'1 + case + assign $1\rok_l_r_rdok$next[0:0]$12722 \$64 + end + sync always + update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$12721 + end + attribute \src "libresoc.v:191413.3-191421.6" + process $proc$libresoc.v:191413$12723 + assign { } { } + assign { } { } + assign $0\rst_l_s_rst$next[0:0]$12724 $1\rst_l_s_rst$next[0:0]$12725 + attribute \src "libresoc.v:191414.5-191414.29" + switch \initial + attribute \src "libresoc.v:191414.9-191414.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rst_l_s_rst$next[0:0]$12725 1'0 + case + assign $1\rst_l_s_rst$next[0:0]$12725 \all_rd + end + sync always + update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$12724 + end + attribute \src "libresoc.v:191422.3-191430.6" + process $proc$libresoc.v:191422$12726 + assign { } { } + assign { } { } + assign $0\rst_l_r_rst$next[0:0]$12727 $1\rst_l_r_rst$next[0:0]$12728 + attribute \src "libresoc.v:191423.5-191423.29" + switch \initial + attribute \src "libresoc.v:191423.9-191423.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rst_l_r_rst$next[0:0]$12728 1'1 + case + assign $1\rst_l_r_rst$next[0:0]$12728 \rst_r + end + sync always + update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$12727 + end + attribute \src "libresoc.v:191431.3-191439.6" + process $proc$libresoc.v:191431$12729 + assign { } { } + assign { } { } + assign $0\opc_l_s_opc$next[0:0]$12730 $1\opc_l_s_opc$next[0:0]$12731 + attribute \src "libresoc.v:191432.5-191432.29" + switch \initial + attribute \src "libresoc.v:191432.9-191432.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\opc_l_s_opc$next[0:0]$12731 1'0 + case + assign $1\opc_l_s_opc$next[0:0]$12731 \cu_issue_i + end + sync always + update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$12730 + end + attribute \src "libresoc.v:191440.3-191448.6" + process $proc$libresoc.v:191440$12732 + assign { } { } + assign { } { } + assign $0\opc_l_r_opc$next[0:0]$12733 $1\opc_l_r_opc$next[0:0]$12734 + attribute \src "libresoc.v:191441.5-191441.29" + switch \initial + attribute \src "libresoc.v:191441.9-191441.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\opc_l_r_opc$next[0:0]$12734 1'1 + case + assign $1\opc_l_r_opc$next[0:0]$12734 \req_done + end + sync always + update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$12733 + end + attribute \src "libresoc.v:191449.3-191457.6" + process $proc$libresoc.v:191449$12735 + assign { } { } + assign { } { } + assign $0\src_l_s_src$next[4:0]$12736 $1\src_l_s_src$next[4:0]$12737 + attribute \src "libresoc.v:191450.5-191450.29" + switch \initial + attribute \src "libresoc.v:191450.9-191450.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_l_s_src$next[4:0]$12737 5'00000 + case + assign $1\src_l_s_src$next[4:0]$12737 { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i } + end + sync always + update \src_l_s_src$next $0\src_l_s_src$next[4:0]$12736 + end + attribute \src "libresoc.v:191458.3-191466.6" + process $proc$libresoc.v:191458$12738 + assign { } { } + assign { } { } + assign $0\src_l_r_src$next[4:0]$12739 $1\src_l_r_src$next[4:0]$12740 + attribute \src "libresoc.v:191459.5-191459.29" + switch \initial + attribute \src "libresoc.v:191459.9-191459.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_l_r_src$next[4:0]$12740 5'11111 + case + assign $1\src_l_r_src$next[4:0]$12740 \reset_r + end + sync always + update \src_l_r_src$next $0\src_l_r_src$next[4:0]$12739 + end + attribute \src "libresoc.v:191467.3-191475.6" + process $proc$libresoc.v:191467$12741 + assign { } { } + assign { } { } + assign $0\req_l_s_req$next[2:0]$12742 $1\req_l_s_req$next[2:0]$12743 + attribute \src "libresoc.v:191468.5-191468.29" + switch \initial + attribute \src "libresoc.v:191468.9-191468.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\req_l_s_req$next[2:0]$12743 3'000 + case + assign $1\req_l_s_req$next[2:0]$12743 \$66 + end + sync always + update \req_l_s_req$next $0\req_l_s_req$next[2:0]$12742 + end + attribute \src "libresoc.v:191476.3-191484.6" + process $proc$libresoc.v:191476$12744 + assign { } { } + assign { } { } + assign $0\req_l_r_req$next[2:0]$12745 $1\req_l_r_req$next[2:0]$12746 + attribute \src "libresoc.v:191477.5-191477.29" + switch \initial + attribute \src "libresoc.v:191477.9-191477.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\req_l_r_req$next[2:0]$12746 3'111 + case + assign $1\req_l_r_req$next[2:0]$12746 \$68 + end + sync always + update \req_l_r_req$next $0\req_l_r_req$next[2:0]$12745 + end + attribute \src "libresoc.v:191485.3-191522.6" + process $proc$libresoc.v:191485$12747 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\alu_shift_rot0_sr_op__fn_unit$next[12:0]$12748 $1\alu_shift_rot0_sr_op__fn_unit$next[12:0]$12765 + assign { } { } + assign { } { } + assign $0\alu_shift_rot0_sr_op__input_carry$next[1:0]$12751 $1\alu_shift_rot0_sr_op__input_carry$next[1:0]$12768 + assign $0\alu_shift_rot0_sr_op__input_cr$next[0:0]$12752 $1\alu_shift_rot0_sr_op__input_cr$next[0:0]$12769 + assign $0\alu_shift_rot0_sr_op__insn$next[31:0]$12753 $1\alu_shift_rot0_sr_op__insn$next[31:0]$12770 + assign $0\alu_shift_rot0_sr_op__insn_type$next[6:0]$12754 $1\alu_shift_rot0_sr_op__insn_type$next[6:0]$12771 + assign $0\alu_shift_rot0_sr_op__invert_in$next[0:0]$12755 $1\alu_shift_rot0_sr_op__invert_in$next[0:0]$12772 + assign $0\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12756 $1\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12773 + assign $0\alu_shift_rot0_sr_op__is_signed$next[0:0]$12757 $1\alu_shift_rot0_sr_op__is_signed$next[0:0]$12774 + assign { } { } + assign { } { } + assign $0\alu_shift_rot0_sr_op__output_carry$next[0:0]$12760 $1\alu_shift_rot0_sr_op__output_carry$next[0:0]$12777 + assign $0\alu_shift_rot0_sr_op__output_cr$next[0:0]$12761 $1\alu_shift_rot0_sr_op__output_cr$next[0:0]$12778 + assign { } { } + assign { } { } + assign $0\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12764 $1\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12781 + assign $0\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12749 $2\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12782 + assign $0\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12750 $2\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12783 + assign $0\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12758 $2\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12784 + assign $0\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12759 $2\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12785 + assign $0\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12762 $2\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12786 + assign $0\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12763 $2\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12787 + attribute \src "libresoc.v:191486.5-191486.29" + switch \initial + attribute \src "libresoc.v:191486.9-191486.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\alu_shift_rot0_sr_op__insn$next[31:0]$12770 $1\alu_shift_rot0_sr_op__is_signed$next[0:0]$12774 $1\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12773 $1\alu_shift_rot0_sr_op__output_cr$next[0:0]$12778 $1\alu_shift_rot0_sr_op__input_cr$next[0:0]$12769 $1\alu_shift_rot0_sr_op__output_carry$next[0:0]$12777 $1\alu_shift_rot0_sr_op__input_carry$next[1:0]$12768 $1\alu_shift_rot0_sr_op__invert_in$next[0:0]$12772 $1\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12781 $1\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12776 $1\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12775 $1\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12779 $1\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12780 $1\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12767 $1\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12766 $1\alu_shift_rot0_sr_op__fn_unit$next[12:0]$12765 $1\alu_shift_rot0_sr_op__insn_type$next[6:0]$12771 } { \oper_i_alu_shift_rot0__insn \oper_i_alu_shift_rot0__is_signed \oper_i_alu_shift_rot0__is_32bit \oper_i_alu_shift_rot0__output_cr \oper_i_alu_shift_rot0__input_cr \oper_i_alu_shift_rot0__output_carry \oper_i_alu_shift_rot0__input_carry \oper_i_alu_shift_rot0__invert_in \oper_i_alu_shift_rot0__write_cr0 \oper_i_alu_shift_rot0__oe__ok \oper_i_alu_shift_rot0__oe__oe \oper_i_alu_shift_rot0__rc__ok \oper_i_alu_shift_rot0__rc__rc \oper_i_alu_shift_rot0__imm_data__ok \oper_i_alu_shift_rot0__imm_data__data \oper_i_alu_shift_rot0__fn_unit \oper_i_alu_shift_rot0__insn_type } + case + assign $1\alu_shift_rot0_sr_op__fn_unit$next[12:0]$12765 \alu_shift_rot0_sr_op__fn_unit + assign $1\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12766 \alu_shift_rot0_sr_op__imm_data__data + assign $1\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12767 \alu_shift_rot0_sr_op__imm_data__ok + assign $1\alu_shift_rot0_sr_op__input_carry$next[1:0]$12768 \alu_shift_rot0_sr_op__input_carry + assign $1\alu_shift_rot0_sr_op__input_cr$next[0:0]$12769 \alu_shift_rot0_sr_op__input_cr + assign $1\alu_shift_rot0_sr_op__insn$next[31:0]$12770 \alu_shift_rot0_sr_op__insn + assign $1\alu_shift_rot0_sr_op__insn_type$next[6:0]$12771 \alu_shift_rot0_sr_op__insn_type + assign $1\alu_shift_rot0_sr_op__invert_in$next[0:0]$12772 \alu_shift_rot0_sr_op__invert_in + assign $1\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12773 \alu_shift_rot0_sr_op__is_32bit + assign $1\alu_shift_rot0_sr_op__is_signed$next[0:0]$12774 \alu_shift_rot0_sr_op__is_signed + assign $1\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12775 \alu_shift_rot0_sr_op__oe__oe + assign $1\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12776 \alu_shift_rot0_sr_op__oe__ok + assign $1\alu_shift_rot0_sr_op__output_carry$next[0:0]$12777 \alu_shift_rot0_sr_op__output_carry + assign $1\alu_shift_rot0_sr_op__output_cr$next[0:0]$12778 \alu_shift_rot0_sr_op__output_cr + assign $1\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12779 \alu_shift_rot0_sr_op__rc__ok + assign $1\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12780 \alu_shift_rot0_sr_op__rc__rc + assign $1\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12781 \alu_shift_rot0_sr_op__write_cr0 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $2\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12782 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12783 1'0 + assign $2\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12787 1'0 + assign $2\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12786 1'0 + assign $2\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12784 1'0 + assign $2\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12785 1'0 + case + assign $2\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12782 $1\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12766 + assign $2\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12783 $1\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12767 + assign $2\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12784 $1\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12775 + assign $2\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12785 $1\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12776 + assign $2\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12786 $1\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12779 + assign $2\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12787 $1\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12780 + end + sync always + update \alu_shift_rot0_sr_op__fn_unit$next $0\alu_shift_rot0_sr_op__fn_unit$next[12:0]$12748 + update \alu_shift_rot0_sr_op__imm_data__data$next $0\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12749 + update \alu_shift_rot0_sr_op__imm_data__ok$next $0\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12750 + update \alu_shift_rot0_sr_op__input_carry$next $0\alu_shift_rot0_sr_op__input_carry$next[1:0]$12751 + update \alu_shift_rot0_sr_op__input_cr$next $0\alu_shift_rot0_sr_op__input_cr$next[0:0]$12752 + update \alu_shift_rot0_sr_op__insn$next $0\alu_shift_rot0_sr_op__insn$next[31:0]$12753 + update \alu_shift_rot0_sr_op__insn_type$next $0\alu_shift_rot0_sr_op__insn_type$next[6:0]$12754 + update \alu_shift_rot0_sr_op__invert_in$next $0\alu_shift_rot0_sr_op__invert_in$next[0:0]$12755 + update \alu_shift_rot0_sr_op__is_32bit$next $0\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12756 + update \alu_shift_rot0_sr_op__is_signed$next $0\alu_shift_rot0_sr_op__is_signed$next[0:0]$12757 + update \alu_shift_rot0_sr_op__oe__oe$next $0\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12758 + update \alu_shift_rot0_sr_op__oe__ok$next $0\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12759 + update \alu_shift_rot0_sr_op__output_carry$next $0\alu_shift_rot0_sr_op__output_carry$next[0:0]$12760 + update \alu_shift_rot0_sr_op__output_cr$next $0\alu_shift_rot0_sr_op__output_cr$next[0:0]$12761 + update \alu_shift_rot0_sr_op__rc__ok$next $0\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12762 + update \alu_shift_rot0_sr_op__rc__rc$next $0\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12763 + update \alu_shift_rot0_sr_op__write_cr0$next $0\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12764 + end + attribute \src "libresoc.v:191523.3-191544.6" + process $proc$libresoc.v:191523$12788 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r0__o$next[63:0]$12789 $2\data_r0__o$next[63:0]$12793 + assign { } { } + assign $0\data_r0__o_ok$next[0:0]$12790 $3\data_r0__o_ok$next[0:0]$12795 + attribute \src "libresoc.v:191524.5-191524.29" + switch \initial + attribute \src "libresoc.v:191524.9-191524.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r0__o_ok$next[0:0]$12792 $1\data_r0__o$next[63:0]$12791 } { \o_ok \alu_shift_rot0_o } + case + assign $1\data_r0__o$next[63:0]$12791 \data_r0__o + assign $1\data_r0__o_ok$next[0:0]$12792 \data_r0__o_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r0__o_ok$next[0:0]$12794 $2\data_r0__o$next[63:0]$12793 } 65'00000000000000000000000000000000000000000000000000000000000000000 + case + assign $2\data_r0__o$next[63:0]$12793 $1\data_r0__o$next[63:0]$12791 + assign $2\data_r0__o_ok$next[0:0]$12794 $1\data_r0__o_ok$next[0:0]$12792 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r0__o_ok$next[0:0]$12795 1'0 + case + assign $3\data_r0__o_ok$next[0:0]$12795 $2\data_r0__o_ok$next[0:0]$12794 + end + sync always + update \data_r0__o$next $0\data_r0__o$next[63:0]$12789 + update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$12790 + end + attribute \src "libresoc.v:191545.3-191566.6" + process $proc$libresoc.v:191545$12796 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r1__cr_a$next[3:0]$12797 $2\data_r1__cr_a$next[3:0]$12801 + assign { } { } + assign $0\data_r1__cr_a_ok$next[0:0]$12798 $3\data_r1__cr_a_ok$next[0:0]$12803 + attribute \src "libresoc.v:191546.5-191546.29" + switch \initial + attribute \src "libresoc.v:191546.9-191546.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r1__cr_a_ok$next[0:0]$12800 $1\data_r1__cr_a$next[3:0]$12799 } { \cr_a_ok \alu_shift_rot0_cr_a } + case + assign $1\data_r1__cr_a$next[3:0]$12799 \data_r1__cr_a + assign $1\data_r1__cr_a_ok$next[0:0]$12800 \data_r1__cr_a_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r1__cr_a_ok$next[0:0]$12802 $2\data_r1__cr_a$next[3:0]$12801 } 5'00000 + case + assign $2\data_r1__cr_a$next[3:0]$12801 $1\data_r1__cr_a$next[3:0]$12799 + assign $2\data_r1__cr_a_ok$next[0:0]$12802 $1\data_r1__cr_a_ok$next[0:0]$12800 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r1__cr_a_ok$next[0:0]$12803 1'0 + case + assign $3\data_r1__cr_a_ok$next[0:0]$12803 $2\data_r1__cr_a_ok$next[0:0]$12802 + end + sync always + update \data_r1__cr_a$next $0\data_r1__cr_a$next[3:0]$12797 + update \data_r1__cr_a_ok$next $0\data_r1__cr_a_ok$next[0:0]$12798 + end + attribute \src "libresoc.v:191567.3-191588.6" + process $proc$libresoc.v:191567$12804 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r2__xer_ca$next[1:0]$12805 $2\data_r2__xer_ca$next[1:0]$12809 + assign { } { } + assign $0\data_r2__xer_ca_ok$next[0:0]$12806 $3\data_r2__xer_ca_ok$next[0:0]$12811 + attribute \src "libresoc.v:191568.5-191568.29" + switch \initial + attribute \src "libresoc.v:191568.9-191568.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r2__xer_ca_ok$next[0:0]$12808 $1\data_r2__xer_ca$next[1:0]$12807 } { \xer_ca_ok \alu_shift_rot0_xer_ca } + case + assign $1\data_r2__xer_ca$next[1:0]$12807 \data_r2__xer_ca + assign $1\data_r2__xer_ca_ok$next[0:0]$12808 \data_r2__xer_ca_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r2__xer_ca_ok$next[0:0]$12810 $2\data_r2__xer_ca$next[1:0]$12809 } 3'000 + case + assign $2\data_r2__xer_ca$next[1:0]$12809 $1\data_r2__xer_ca$next[1:0]$12807 + assign $2\data_r2__xer_ca_ok$next[0:0]$12810 $1\data_r2__xer_ca_ok$next[0:0]$12808 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r2__xer_ca_ok$next[0:0]$12811 1'0 + case + assign $3\data_r2__xer_ca_ok$next[0:0]$12811 $2\data_r2__xer_ca_ok$next[0:0]$12810 + end + sync always + update \data_r2__xer_ca$next $0\data_r2__xer_ca$next[1:0]$12805 + update \data_r2__xer_ca_ok$next $0\data_r2__xer_ca_ok$next[0:0]$12806 + end + attribute \src "libresoc.v:191589.3-191598.6" + process $proc$libresoc.v:191589$12812 + assign { } { } + assign { } { } + assign $0\src_r0$next[63:0]$12813 $1\src_r0$next[63:0]$12814 + attribute \src "libresoc.v:191590.5-191590.29" + switch \initial + attribute \src "libresoc.v:191590.9-191590.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" + switch \src_l_q_src [0] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r0$next[63:0]$12814 \src1_i + case + assign $1\src_r0$next[63:0]$12814 \src_r0 + end + sync always + update \src_r0$next $0\src_r0$next[63:0]$12813 + end + attribute \src "libresoc.v:191599.3-191608.6" + process $proc$libresoc.v:191599$12815 + assign { } { } + assign { } { } + assign $0\src_r1$next[63:0]$12816 $1\src_r1$next[63:0]$12817 + attribute \src "libresoc.v:191600.5-191600.29" + switch \initial + attribute \src "libresoc.v:191600.9-191600.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" + switch \src_sel + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r1$next[63:0]$12817 \src_or_imm + case + assign $1\src_r1$next[63:0]$12817 \src_r1 + end + sync always + update \src_r1$next $0\src_r1$next[63:0]$12816 + end + attribute \src "libresoc.v:191609.3-191618.6" + process $proc$libresoc.v:191609$12818 + assign { } { } + assign { } { } + assign $0\src_r2$next[63:0]$12819 $1\src_r2$next[63:0]$12820 + attribute \src "libresoc.v:191610.5-191610.29" + switch \initial + attribute \src "libresoc.v:191610.9-191610.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" + switch \src_l_q_src [2] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r2$next[63:0]$12820 \src3_i + case + assign $1\src_r2$next[63:0]$12820 \src_r2 + end + sync always + update \src_r2$next $0\src_r2$next[63:0]$12819 + end + attribute \src "libresoc.v:191619.3-191628.6" + process $proc$libresoc.v:191619$12821 + assign { } { } + assign { } { } + assign $0\src_r3$next[0:0]$12822 $1\src_r3$next[0:0]$12823 + attribute \src "libresoc.v:191620.5-191620.29" + switch \initial + attribute \src "libresoc.v:191620.9-191620.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" + switch \src_l_q_src [3] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r3$next[0:0]$12823 \src4_i + case + assign $1\src_r3$next[0:0]$12823 \src_r3 + end + sync always + update \src_r3$next $0\src_r3$next[0:0]$12822 + end + attribute \src "libresoc.v:191629.3-191638.6" + process $proc$libresoc.v:191629$12824 + assign { } { } + assign { } { } + assign $0\src_r4$next[1:0]$12825 $1\src_r4$next[1:0]$12826 + attribute \src "libresoc.v:191630.5-191630.29" + switch \initial + attribute \src "libresoc.v:191630.9-191630.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" + switch \src_l_q_src [4] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r4$next[1:0]$12826 \src5_i + case + assign $1\src_r4$next[1:0]$12826 \src_r4 + end + sync always + update \src_r4$next $0\src_r4$next[1:0]$12825 + end + attribute \src "libresoc.v:191639.3-191647.6" + process $proc$libresoc.v:191639$12827 + assign { } { } + assign { } { } + assign $0\alui_l_r_alui$next[0:0]$12828 $1\alui_l_r_alui$next[0:0]$12829 + attribute \src "libresoc.v:191640.5-191640.29" + switch \initial + attribute \src "libresoc.v:191640.9-191640.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\alui_l_r_alui$next[0:0]$12829 1'1 + case + assign $1\alui_l_r_alui$next[0:0]$12829 \$90 + end + sync always + update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$12828 + end + attribute \src "libresoc.v:191648.3-191656.6" + process $proc$libresoc.v:191648$12830 + assign { } { } + assign { } { } + assign $0\alu_l_r_alu$next[0:0]$12831 $1\alu_l_r_alu$next[0:0]$12832 + attribute \src "libresoc.v:191649.5-191649.29" + switch \initial + attribute \src "libresoc.v:191649.9-191649.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\alu_l_r_alu$next[0:0]$12832 1'1 + case + assign $1\alu_l_r_alu$next[0:0]$12832 \$92 + end + sync always + update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$12831 + end + attribute \src "libresoc.v:191657.3-191666.6" + process $proc$libresoc.v:191657$12833 + assign { } { } + assign { } { } + assign $0\dest1_o[63:0] $1\dest1_o[63:0] + attribute \src "libresoc.v:191658.5-191658.29" + switch \initial + attribute \src "libresoc.v:191658.9-191658.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$114 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest1_o[63:0] \data_r0__o + case + assign $1\dest1_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \dest1_o $0\dest1_o[63:0] + end + attribute \src "libresoc.v:191667.3-191676.6" + process $proc$libresoc.v:191667$12834 + assign { } { } + assign { } { } + assign $0\dest2_o[3:0] $1\dest2_o[3:0] + attribute \src "libresoc.v:191668.5-191668.29" + switch \initial + attribute \src "libresoc.v:191668.9-191668.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$116 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest2_o[3:0] \data_r1__cr_a + case + assign $1\dest2_o[3:0] 4'0000 + end + sync always + update \dest2_o $0\dest2_o[3:0] + end + attribute \src "libresoc.v:191677.3-191686.6" + process $proc$libresoc.v:191677$12835 + assign { } { } + assign { } { } + assign $0\dest3_o[1:0] $1\dest3_o[1:0] + attribute \src "libresoc.v:191678.5-191678.29" + switch \initial + attribute \src "libresoc.v:191678.9-191678.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$118 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest3_o[1:0] \data_r2__xer_ca + case + assign $1\dest3_o[1:0] 2'00 + end + sync always + update \dest3_o $0\dest3_o[1:0] + end + attribute \src "libresoc.v:191687.3-191695.6" + process $proc$libresoc.v:191687$12836 + assign { } { } + assign { } { } + assign $0\prev_wr_go$next[2:0]$12837 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$ternary$libresoc.v:191208$12666_Y + connect \$4 $reduce_and$libresoc.v:191209$12667_Y + connect \$90 $and$libresoc.v:191210$12668_Y + connect \$92 $and$libresoc.v:191211$12669_Y + connect \$94 $and$libresoc.v:191212$12670_Y + connect \$96 $not$libresoc.v:191213$12671_Y + connect \$98 $and$libresoc.v:191214$12672_Y + connect \cu_go_die_i 1'0 + connect \cu_shadown_i 1'1 + connect \cu_wr__rel_o \$112 + connect \cu_rd__rel_o \$102 + connect \cu_busy_o \opc_l_q_opc + connect \alu_l_s_alu \all_rd_pulse + connect \alu_shift_rot0_n_ready_i \alu_l_q_alu + connect \alui_l_s_alui \all_rd_pulse + connect \alu_shift_rot0_p_valid_i \alui_l_q_alui + connect \alu_shift_rot0_xer_ca$1 \$88 + connect \alu_shift_rot0_xer_so \$86 + connect \alu_shift_rot0_rc \$84 + connect \alu_shift_rot0_rb \$82 + connect \alu_shift_rot0_ra \$80 + connect \src_or_imm \$78 + connect \src_sel \$76 + connect \cu_wrmask_o { \$74 \$72 \$70 } + connect \reset_r \$62 + connect \reset_w \$60 + connect \rst_r \$58 + connect \reset \$56 + connect \wr_any \$36 + connect \cu_done_o \$30 + connect \alu_pulsem { \alu_pulse \alu_pulse \alu_pulse } + connect \alu_pulse \alu_done_rise + connect \alu_done_rise \$18 + connect \alu_done_dly$next \alu_done + connect \alu_done \alu_shift_rot0_n_valid_o + connect \all_rd_pulse \all_rd_rise + connect \all_rd_rise \$14 + connect \all_rd_dly$next \all_rd + connect \all_rd \$10 +end +attribute \src "libresoc.v:191732.1-191911.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.spr" +attribute \generator "nMigen" +module \spr + attribute \src "libresoc.v:191883.3-191886.6" + wire width 7 $0$memwr$\memory$libresoc.v:191885$12995_ADDR[6:0]$12998 + attribute \src "libresoc.v:191883.3-191886.6" + wire width 64 $0$memwr$\memory$libresoc.v:191885$12995_DATA[63:0]$12999 + attribute \src "libresoc.v:191883.3-191886.6" + wire width 64 $0$memwr$\memory$libresoc.v:191885$12995_EN[63:0]$13000 + attribute \src "libresoc.v:191883.3-191886.6" + wire width 7 $0\_0_[6:0] + attribute \src "libresoc.v:191733.7-191733.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:191888.3-191896.6" + wire $0\ren_delay$next[0:0]$13003 + attribute \src "libresoc.v:191765.3-191766.35" + wire $0\ren_delay[0:0] + attribute \src "libresoc.v:191897.3-191906.6" + wire width 64 $0\spr1__data_o[63:0] + attribute \src "libresoc.v:191888.3-191896.6" + wire $1\ren_delay$next[0:0]$13004 + attribute \src "libresoc.v:191749.7-191749.23" + wire $1\ren_delay[0:0] + attribute \src "libresoc.v:191897.3-191906.6" + wire width 64 $1\spr1__data_o[63:0] + attribute \src "libresoc.v:191887.26-191887.32" + wire width 64 $memrd$\memory$libresoc.v:191887$13001_DATA + attribute \src "libresoc.v:0.0-0.0" + wire width 7 $memwr$\memory$libresoc.v:191885$12995_ADDR + attribute \src "libresoc.v:0.0-0.0" + wire width 64 $memwr$\memory$libresoc.v:191885$12995_DATA + attribute \src "libresoc.v:0.0-0.0" + wire width 64 $memwr$\memory$libresoc.v:191885$12995_EN + attribute \src "libresoc.v:191882.13-191882.16" + wire width 7 \_0_ + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 8 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 1 \coresync_rst + attribute \src "libresoc.v:191733.7-191733.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" + wire width 7 \memory_r_addr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" + wire width 64 \memory_r_data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" + wire width 7 \memory_w_addr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" + wire width 64 \memory_w_data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" + wire \memory_w_en + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" + wire \ren_delay + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" + wire \ren_delay$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 7 input 3 \spr1__addr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 7 input 6 \spr1__addr$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 input 5 \spr1__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 output 2 \spr1__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 4 \spr1__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire input 7 \spr1__wen + attribute \src "libresoc.v:191767.14-191767.20" + memory width 64 size 112 \memory + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$13006 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 13006 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 0 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$13007 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 13007 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 1 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$13008 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 13008 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 2 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$13009 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 13009 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 3 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$13010 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 13010 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 4 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$13011 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 13011 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 5 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$13012 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 13012 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 6 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$13013 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 13013 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 7 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$13014 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 13014 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 8 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$13015 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 13015 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 9 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$13016 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 13016 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 10 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$13017 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 13017 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 11 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$13018 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 13018 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 12 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$13019 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 13019 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 13 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$13020 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 13020 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 14 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$13021 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 13021 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 15 + connect \DATA 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64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$13037 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 13037 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 31 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$13038 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 13038 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 32 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$13039 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 13039 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 33 + connect \DATA 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64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$13043 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 13043 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 37 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$13044 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 13044 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 38 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$13045 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 13045 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 39 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$13046 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 13046 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 40 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$13047 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 13047 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 41 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$13048 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 13048 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 42 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$13049 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 13049 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 43 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$13050 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 13050 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 44 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$13051 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 13051 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 45 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$13052 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 13052 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 46 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$13053 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 13053 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 47 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$13054 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 13054 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 48 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$13055 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 13055 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 49 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$13056 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 13056 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 50 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$13057 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 13057 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 51 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$13058 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 13058 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 52 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$13059 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 13059 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 53 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$13060 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 13060 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 54 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$13061 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 13061 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 55 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$13062 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 13062 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 56 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$13063 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 13063 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 57 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$13064 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 13064 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 58 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$13065 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 13065 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 59 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$13066 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 13066 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 60 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$13067 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 13067 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 61 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$13068 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 13068 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 62 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$13069 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 13069 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 63 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$13070 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 13070 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 64 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$13071 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 13071 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 65 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$13072 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 13072 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 66 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$13073 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 13073 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 67 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$13074 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 13074 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 68 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$13075 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 13075 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 69 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$13076 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 13076 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 70 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$13077 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 13077 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 71 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$13078 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 13078 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 72 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$13079 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 13079 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 73 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$13080 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 13080 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 74 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$13081 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 13081 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 75 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$13082 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 13082 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 76 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$13083 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 13083 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 77 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$13084 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 13084 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 78 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$13085 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 13085 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 79 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$13086 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 13086 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 80 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$13087 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 13087 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 81 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$13088 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 13088 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 82 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$13089 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 13089 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 83 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$13090 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 13090 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 84 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$13091 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 13091 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 85 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$13092 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 13092 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 86 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$13093 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 13093 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 87 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$13094 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 13094 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 88 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$13095 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 13095 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 89 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$13096 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 13096 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 90 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$13097 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 13097 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 91 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$13098 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 13098 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 92 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$13099 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 13099 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 93 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$13100 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 13100 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 94 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$13101 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 13101 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 95 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$13102 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 13102 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 96 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$13103 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 13103 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 97 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$13104 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 13104 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 98 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$13105 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 13105 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 99 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$13106 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 13106 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 100 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$13107 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 13107 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 101 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$13108 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 13108 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 102 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$13109 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 13109 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 103 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$13110 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 13110 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 104 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$13111 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 13111 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 105 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$13112 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 13112 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 106 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$13113 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 13113 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 107 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$13114 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 13114 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 108 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$13115 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 13115 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 109 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$13116 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 13116 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 110 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + cell $meminit $meminit$\memory$libresoc.v:0$13117 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 13117 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 111 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:191887.26-191887.32" + cell $memrd $memrd$\memory$libresoc.v:191887$13001 + parameter \ABITS 7 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\memory" + parameter \TRANSPARENT 0 + parameter \WIDTH 64 + connect \ADDR \_0_ + connect \CLK 1'x + connect \DATA $memrd$\memory$libresoc.v:191887$13001_DATA + connect \EN 1'x + end + attribute \src "libresoc.v:0.0-0.0" + cell $memwr $memwr$\memory$libresoc.v:0$13118 + parameter \ABITS 7 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\memory" + parameter \PRIORITY 13118 + parameter \WIDTH 64 + connect \ADDR $memwr$\memory$libresoc.v:191885$12995_ADDR + connect \CLK 1'x + connect \DATA $memwr$\memory$libresoc.v:191885$12995_DATA + connect \EN $memwr$\memory$libresoc.v:191885$12995_EN + end + attribute \src "libresoc.v:0.0-0.0" + process $proc$libresoc.v:0$13121 + sync always + sync init + end + attribute \src "libresoc.v:191733.7-191733.20" + process $proc$libresoc.v:191733$13119 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:191749.7-191749.23" + process $proc$libresoc.v:191749$13120 + assign { } { } + assign $1\ren_delay[0:0] 1'0 + sync always + sync init + update \ren_delay $1\ren_delay[0:0] + end + attribute \src "libresoc.v:191765.3-191766.35" + process $proc$libresoc.v:191765$12996 + assign { } { } + assign $0\ren_delay[0:0] \ren_delay$next + sync posedge \coresync_clk + update \ren_delay $0\ren_delay[0:0] + end + attribute \src "libresoc.v:191883.3-191886.6" + process $proc$libresoc.v:191883$12997 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0$memwr$\memory$libresoc.v:191885$12995_ADDR[6:0]$12998 7'xxxxxxx + assign $0$memwr$\memory$libresoc.v:191885$12995_DATA[63:0]$12999 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\memory$libresoc.v:191885$12995_EN[63:0]$13000 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\_0_[6:0] \spr1__addr + attribute \src "libresoc.v:191885.5-191885.59" + switch \spr1__wen + attribute \src "libresoc.v:191885.9-191885.18" + case 1'1 + assign $0$memwr$\memory$libresoc.v:191885$12995_ADDR[6:0]$12998 \spr1__addr$1 + assign $0$memwr$\memory$libresoc.v:191885$12995_DATA[63:0]$12999 \spr1__data_i + assign $0$memwr$\memory$libresoc.v:191885$12995_EN[63:0]$13000 64'1111111111111111111111111111111111111111111111111111111111111111 + case + end + sync posedge \coresync_clk + update \_0_ $0\_0_[6:0] + update $memwr$\memory$libresoc.v:191885$12995_ADDR $0$memwr$\memory$libresoc.v:191885$12995_ADDR[6:0]$12998 + update $memwr$\memory$libresoc.v:191885$12995_DATA $0$memwr$\memory$libresoc.v:191885$12995_DATA[63:0]$12999 + update $memwr$\memory$libresoc.v:191885$12995_EN $0$memwr$\memory$libresoc.v:191885$12995_EN[63:0]$13000 + end + attribute \src "libresoc.v:191888.3-191896.6" + process $proc$libresoc.v:191888$13002 + assign { } { } + assign { } { } + assign $0\ren_delay$next[0:0]$13003 $1\ren_delay$next[0:0]$13004 + attribute \src "libresoc.v:191889.5-191889.29" + switch \initial + attribute \src "libresoc.v:191889.9-191889.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ren_delay$next[0:0]$13004 1'0 + case + assign $1\ren_delay$next[0:0]$13004 \spr1__ren + end + sync always + update \ren_delay$next $0\ren_delay$next[0:0]$13003 + end + attribute \src "libresoc.v:191897.3-191906.6" + process $proc$libresoc.v:191897$13005 + assign { } { } + assign { } { } + assign $0\spr1__data_o[63:0] $1\spr1__data_o[63:0] + attribute \src "libresoc.v:191898.5-191898.29" + switch \initial + attribute \src "libresoc.v:191898.9-191898.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" + switch \ren_delay + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\spr1__data_o[63:0] \memory_r_data + case + assign $1\spr1__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \spr1__data_o $0\spr1__data_o[63:0] + end + connect \memory_r_data $memrd$\memory$libresoc.v:191887$13001_DATA + connect \memory_w_data \spr1__data_i + connect \memory_w_en \spr1__wen + connect \memory_w_addr \spr1__addr$1 + connect \memory_r_addr \spr1__addr +end +attribute \src "libresoc.v:191915.1-193164.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0" +attribute \generator "nMigen" +module \spr0 + attribute \src "libresoc.v:192661.3-192662.25" + wire $0\all_rd_dly[0:0] + attribute \src "libresoc.v:192659.3-192660.40" + wire $0\alu_done_dly[0:0] + attribute \src "libresoc.v:193055.3-193063.6" + wire $0\alu_l_r_alu$next[0:0]$13335 + attribute \src "libresoc.v:192589.3-192590.39" + wire $0\alu_l_r_alu[0:0] + attribute \src "libresoc.v:192841.3-192853.6" + wire width 13 $0\alu_spr0_spr_op__fn_unit$next[12:0]$13257 + attribute \src "libresoc.v:192631.3-192632.65" + wire width 13 $0\alu_spr0_spr_op__fn_unit[12:0] + attribute \src "libresoc.v:192841.3-192853.6" + wire width 32 $0\alu_spr0_spr_op__insn$next[31:0]$13258 + attribute \src "libresoc.v:192633.3-192634.59" + wire width 32 $0\alu_spr0_spr_op__insn[31:0] + attribute \src "libresoc.v:192841.3-192853.6" + wire width 7 $0\alu_spr0_spr_op__insn_type$next[6:0]$13259 + attribute \src "libresoc.v:192629.3-192630.69" + wire width 7 $0\alu_spr0_spr_op__insn_type[6:0] + attribute \src "libresoc.v:192841.3-192853.6" + wire $0\alu_spr0_spr_op__is_32bit$next[0:0]$13260 + attribute \src "libresoc.v:192635.3-192636.67" + wire $0\alu_spr0_spr_op__is_32bit[0:0] + attribute \src "libresoc.v:193046.3-193054.6" + wire $0\alui_l_r_alui$next[0:0]$13332 + attribute \src "libresoc.v:192591.3-192592.43" + wire $0\alui_l_r_alui[0:0] + attribute \src "libresoc.v:192854.3-192875.6" + wire width 64 $0\data_r0__o$next[63:0]$13266 + attribute \src "libresoc.v:192625.3-192626.37" + wire width 64 $0\data_r0__o[63:0] + attribute \src "libresoc.v:192854.3-192875.6" + wire $0\data_r0__o_ok$next[0:0]$13267 + attribute \src "libresoc.v:192627.3-192628.43" + wire $0\data_r0__o_ok[0:0] + attribute \src "libresoc.v:192876.3-192897.6" + wire width 64 $0\data_r1__spr1$next[63:0]$13274 + attribute \src "libresoc.v:192621.3-192622.43" + wire width 64 $0\data_r1__spr1[63:0] + attribute \src "libresoc.v:192876.3-192897.6" + wire $0\data_r1__spr1_ok$next[0:0]$13275 + attribute \src "libresoc.v:192623.3-192624.49" + wire $0\data_r1__spr1_ok[0:0] + attribute \src "libresoc.v:192898.3-192919.6" + wire width 64 $0\data_r2__fast1$next[63:0]$13282 + attribute \src "libresoc.v:192617.3-192618.45" + wire width 64 $0\data_r2__fast1[63:0] + attribute \src "libresoc.v:192898.3-192919.6" + wire $0\data_r2__fast1_ok$next[0:0]$13283 + attribute \src "libresoc.v:192619.3-192620.51" + wire $0\data_r2__fast1_ok[0:0] + attribute \src "libresoc.v:192920.3-192941.6" + wire $0\data_r3__xer_so$next[0:0]$13290 + attribute \src "libresoc.v:192613.3-192614.47" + wire $0\data_r3__xer_so[0:0] + attribute \src "libresoc.v:192920.3-192941.6" + wire $0\data_r3__xer_so_ok$next[0:0]$13291 + attribute \src "libresoc.v:192615.3-192616.53" + wire $0\data_r3__xer_so_ok[0:0] + attribute \src "libresoc.v:192942.3-192963.6" + wire width 2 $0\data_r4__xer_ov$next[1:0]$13298 + attribute \src "libresoc.v:192609.3-192610.47" + wire width 2 $0\data_r4__xer_ov[1:0] + attribute \src "libresoc.v:192942.3-192963.6" + wire $0\data_r4__xer_ov_ok$next[0:0]$13299 + attribute \src "libresoc.v:192611.3-192612.53" + wire $0\data_r4__xer_ov_ok[0:0] + attribute \src "libresoc.v:192964.3-192985.6" + wire width 2 $0\data_r5__xer_ca$next[1:0]$13306 + attribute \src "libresoc.v:192605.3-192606.47" + wire width 2 $0\data_r5__xer_ca[1:0] + attribute \src "libresoc.v:192964.3-192985.6" + wire $0\data_r5__xer_ca_ok$next[0:0]$13307 + attribute \src "libresoc.v:192607.3-192608.53" + wire $0\data_r5__xer_ca_ok[0:0] + attribute \src "libresoc.v:193064.3-193073.6" + wire width 64 $0\dest1_o[63:0] + attribute \src "libresoc.v:193074.3-193083.6" + wire width 64 $0\dest2_o[63:0] + attribute \src "libresoc.v:193084.3-193093.6" + wire width 64 $0\dest3_o[63:0] + attribute \src "libresoc.v:193094.3-193103.6" + wire $0\dest4_o[0:0] + attribute \src "libresoc.v:193104.3-193113.6" + wire width 2 $0\dest5_o[1:0] + attribute \src "libresoc.v:193114.3-193123.6" + wire width 2 $0\dest6_o[1:0] + attribute \src "libresoc.v:191916.7-191916.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:192796.3-192804.6" + wire $0\opc_l_r_opc$next[0:0]$13242 + attribute \src "libresoc.v:192645.3-192646.39" + wire $0\opc_l_r_opc[0:0] + attribute \src "libresoc.v:192787.3-192795.6" + wire $0\opc_l_s_opc$next[0:0]$13239 + attribute \src "libresoc.v:192647.3-192648.39" + wire $0\opc_l_s_opc[0:0] + attribute \src "libresoc.v:193124.3-193132.6" + wire width 6 $0\prev_wr_go$next[5:0]$13344 + attribute \src "libresoc.v:192657.3-192658.37" + wire width 6 $0\prev_wr_go[5:0] + attribute \src "libresoc.v:192741.3-192750.6" + wire $0\req_done[0:0] + attribute \src "libresoc.v:192832.3-192840.6" + wire width 6 $0\req_l_r_req$next[5:0]$13254 + attribute \src "libresoc.v:192637.3-192638.39" + wire width 6 $0\req_l_r_req[5:0] + attribute \src "libresoc.v:192823.3-192831.6" + wire width 6 $0\req_l_s_req$next[5:0]$13251 + attribute \src "libresoc.v:192639.3-192640.39" + wire width 6 $0\req_l_s_req[5:0] + attribute \src "libresoc.v:192760.3-192768.6" + wire $0\rok_l_r_rdok$next[0:0]$13230 + attribute \src "libresoc.v:192653.3-192654.41" + wire $0\rok_l_r_rdok[0:0] + attribute \src "libresoc.v:192751.3-192759.6" + wire $0\rok_l_s_rdok$next[0:0]$13227 + attribute \src "libresoc.v:192655.3-192656.41" + wire $0\rok_l_s_rdok[0:0] + attribute \src "libresoc.v:192778.3-192786.6" + wire $0\rst_l_r_rst$next[0:0]$13236 + attribute \src "libresoc.v:192649.3-192650.39" + wire $0\rst_l_r_rst[0:0] + attribute \src "libresoc.v:192769.3-192777.6" + wire $0\rst_l_s_rst$next[0:0]$13233 + attribute \src "libresoc.v:192651.3-192652.39" + wire $0\rst_l_s_rst[0:0] + attribute \src "libresoc.v:192814.3-192822.6" + wire width 6 $0\src_l_r_src$next[5:0]$13248 + attribute \src "libresoc.v:192641.3-192642.39" + wire width 6 $0\src_l_r_src[5:0] + attribute \src "libresoc.v:192805.3-192813.6" + wire width 6 $0\src_l_s_src$next[5:0]$13245 + attribute \src "libresoc.v:192643.3-192644.39" + wire width 6 $0\src_l_s_src[5:0] + attribute \src "libresoc.v:192986.3-192995.6" + wire width 64 $0\src_r0$next[63:0]$13314 + attribute \src "libresoc.v:192603.3-192604.29" + wire width 64 $0\src_r0[63:0] + attribute \src "libresoc.v:192996.3-193005.6" + wire width 64 $0\src_r1$next[63:0]$13317 + attribute \src "libresoc.v:192601.3-192602.29" + wire width 64 $0\src_r1[63:0] + attribute \src "libresoc.v:193006.3-193015.6" + wire width 64 $0\src_r2$next[63:0]$13320 + attribute \src "libresoc.v:192599.3-192600.29" + wire width 64 $0\src_r2[63:0] + attribute \src "libresoc.v:193016.3-193025.6" + wire $0\src_r3$next[0:0]$13323 + attribute \src "libresoc.v:192597.3-192598.29" + wire $0\src_r3[0:0] + attribute \src "libresoc.v:193026.3-193035.6" + wire width 2 $0\src_r4$next[1:0]$13326 + attribute \src "libresoc.v:192595.3-192596.29" + wire width 2 $0\src_r4[1:0] + attribute \src "libresoc.v:193036.3-193045.6" + wire width 2 $0\src_r5$next[1:0]$13329 + attribute \src "libresoc.v:192593.3-192594.29" + wire width 2 $0\src_r5[1:0] + attribute \src "libresoc.v:192052.7-192052.24" + wire $1\all_rd_dly[0:0] + attribute \src "libresoc.v:192062.7-192062.26" + wire $1\alu_done_dly[0:0] + attribute \src "libresoc.v:193055.3-193063.6" + wire $1\alu_l_r_alu$next[0:0]$13336 + attribute \src "libresoc.v:192070.7-192070.25" + wire $1\alu_l_r_alu[0:0] + attribute \src "libresoc.v:192841.3-192853.6" + wire width 13 $1\alu_spr0_spr_op__fn_unit$next[12:0]$13261 + attribute \src "libresoc.v:192114.14-192114.49" + wire width 13 $1\alu_spr0_spr_op__fn_unit[12:0] + attribute \src "libresoc.v:192841.3-192853.6" + wire width 32 $1\alu_spr0_spr_op__insn$next[31:0]$13262 + attribute \src "libresoc.v:192118.14-192118.43" + wire width 32 $1\alu_spr0_spr_op__insn[31:0] + attribute \src "libresoc.v:192841.3-192853.6" + wire width 7 $1\alu_spr0_spr_op__insn_type$next[6:0]$13263 + attribute \src "libresoc.v:192196.13-192196.47" + wire width 7 $1\alu_spr0_spr_op__insn_type[6:0] + attribute \src "libresoc.v:192841.3-192853.6" + wire $1\alu_spr0_spr_op__is_32bit$next[0:0]$13264 + attribute \src "libresoc.v:192200.7-192200.39" + wire $1\alu_spr0_spr_op__is_32bit[0:0] + attribute \src "libresoc.v:193046.3-193054.6" + wire $1\alui_l_r_alui$next[0:0]$13333 + attribute \src "libresoc.v:192218.7-192218.27" + wire $1\alui_l_r_alui[0:0] + attribute \src "libresoc.v:192854.3-192875.6" + wire width 64 $1\data_r0__o$next[63:0]$13268 + attribute \src "libresoc.v:192250.14-192250.47" + wire width 64 $1\data_r0__o[63:0] + attribute \src "libresoc.v:192854.3-192875.6" + wire $1\data_r0__o_ok$next[0:0]$13269 + attribute \src "libresoc.v:192254.7-192254.27" + wire $1\data_r0__o_ok[0:0] + attribute \src "libresoc.v:192876.3-192897.6" + wire width 64 $1\data_r1__spr1$next[63:0]$13276 + attribute \src "libresoc.v:192258.14-192258.50" + wire width 64 $1\data_r1__spr1[63:0] + attribute \src "libresoc.v:192876.3-192897.6" + wire $1\data_r1__spr1_ok$next[0:0]$13277 + attribute \src "libresoc.v:192262.7-192262.30" + wire $1\data_r1__spr1_ok[0:0] + attribute \src "libresoc.v:192898.3-192919.6" + wire width 64 $1\data_r2__fast1$next[63:0]$13284 + attribute \src "libresoc.v:192266.14-192266.51" + wire width 64 $1\data_r2__fast1[63:0] + attribute \src "libresoc.v:192898.3-192919.6" + wire $1\data_r2__fast1_ok$next[0:0]$13285 + attribute \src "libresoc.v:192270.7-192270.31" + wire $1\data_r2__fast1_ok[0:0] + attribute \src "libresoc.v:192920.3-192941.6" + wire $1\data_r3__xer_so$next[0:0]$13292 + attribute \src "libresoc.v:192274.7-192274.29" + wire $1\data_r3__xer_so[0:0] + attribute \src "libresoc.v:192920.3-192941.6" + wire $1\data_r3__xer_so_ok$next[0:0]$13293 + attribute \src "libresoc.v:192278.7-192278.32" + wire $1\data_r3__xer_so_ok[0:0] + attribute \src "libresoc.v:192942.3-192963.6" + wire width 2 $1\data_r4__xer_ov$next[1:0]$13300 + attribute \src "libresoc.v:192282.13-192282.35" + wire width 2 $1\data_r4__xer_ov[1:0] + attribute \src "libresoc.v:192942.3-192963.6" + wire $1\data_r4__xer_ov_ok$next[0:0]$13301 + attribute \src "libresoc.v:192286.7-192286.32" + wire $1\data_r4__xer_ov_ok[0:0] + attribute \src "libresoc.v:192964.3-192985.6" + wire width 2 $1\data_r5__xer_ca$next[1:0]$13308 + attribute \src "libresoc.v:192290.13-192290.35" + wire width 2 $1\data_r5__xer_ca[1:0] + attribute \src "libresoc.v:192964.3-192985.6" + wire $1\data_r5__xer_ca_ok$next[0:0]$13309 + attribute \src "libresoc.v:192294.7-192294.32" + wire $1\data_r5__xer_ca_ok[0:0] + attribute \src "libresoc.v:193064.3-193073.6" + wire width 64 $1\dest1_o[63:0] + attribute \src "libresoc.v:193074.3-193083.6" + wire width 64 $1\dest2_o[63:0] + attribute \src "libresoc.v:193084.3-193093.6" + wire width 64 $1\dest3_o[63:0] + attribute \src "libresoc.v:193094.3-193103.6" + wire $1\dest4_o[0:0] + attribute \src "libresoc.v:193104.3-193113.6" + wire width 2 $1\dest5_o[1:0] + attribute \src "libresoc.v:193114.3-193123.6" + wire width 2 $1\dest6_o[1:0] + attribute \src "libresoc.v:192796.3-192804.6" + wire $1\opc_l_r_opc$next[0:0]$13243 + attribute \src "libresoc.v:192322.7-192322.25" + wire $1\opc_l_r_opc[0:0] + attribute \src "libresoc.v:192787.3-192795.6" + wire $1\opc_l_s_opc$next[0:0]$13240 + attribute \src "libresoc.v:192326.7-192326.25" + wire $1\opc_l_s_opc[0:0] + attribute \src "libresoc.v:193124.3-193132.6" + wire width 6 $1\prev_wr_go$next[5:0]$13345 + attribute \src "libresoc.v:192426.13-192426.31" + wire width 6 $1\prev_wr_go[5:0] + attribute \src "libresoc.v:192741.3-192750.6" + wire $1\req_done[0:0] + attribute \src "libresoc.v:192832.3-192840.6" + wire width 6 $1\req_l_r_req$next[5:0]$13255 + attribute \src "libresoc.v:192434.13-192434.32" + wire width 6 $1\req_l_r_req[5:0] + attribute \src "libresoc.v:192823.3-192831.6" + wire width 6 $1\req_l_s_req$next[5:0]$13252 + attribute \src "libresoc.v:192438.13-192438.32" + wire width 6 $1\req_l_s_req[5:0] + attribute \src "libresoc.v:192760.3-192768.6" + wire $1\rok_l_r_rdok$next[0:0]$13231 + attribute \src "libresoc.v:192450.7-192450.26" + wire $1\rok_l_r_rdok[0:0] + attribute \src "libresoc.v:192751.3-192759.6" + wire $1\rok_l_s_rdok$next[0:0]$13228 + attribute \src "libresoc.v:192454.7-192454.26" + wire $1\rok_l_s_rdok[0:0] + attribute \src "libresoc.v:192778.3-192786.6" + wire $1\rst_l_r_rst$next[0:0]$13237 + attribute \src "libresoc.v:192458.7-192458.25" + wire $1\rst_l_r_rst[0:0] + attribute \src "libresoc.v:192769.3-192777.6" + wire $1\rst_l_s_rst$next[0:0]$13234 + attribute \src "libresoc.v:192462.7-192462.25" + wire $1\rst_l_s_rst[0:0] + attribute \src "libresoc.v:192814.3-192822.6" + wire width 6 $1\src_l_r_src$next[5:0]$13249 + attribute \src "libresoc.v:192484.13-192484.32" + wire width 6 $1\src_l_r_src[5:0] + attribute \src "libresoc.v:192805.3-192813.6" + wire width 6 $1\src_l_s_src$next[5:0]$13246 + attribute \src "libresoc.v:192488.13-192488.32" + wire width 6 $1\src_l_s_src[5:0] + attribute \src "libresoc.v:192986.3-192995.6" + wire width 64 $1\src_r0$next[63:0]$13315 + attribute \src "libresoc.v:192492.14-192492.43" + wire width 64 $1\src_r0[63:0] + attribute \src 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$and$libresoc.v:192581$13180_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" + cell $and $and$libresoc.v:192588$13187 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_spr0_p_ready_o + connect \B \alui_l_q_alui + connect \Y $and$libresoc.v:192588$13187_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + cell $eq $eq$libresoc.v:192562$13161 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$46 + connect \B 1'0 + connect \Y $eq$libresoc.v:192562$13161_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + cell $eq $eq$libresoc.v:192564$13163 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_wrmask_o + connect \B 1'0 + connect \Y $eq$libresoc.v:192564$13163_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $not $not$libresoc.v:192523$13122 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \cu_rd__rel_o + connect \Y $not$libresoc.v:192523$13122_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + cell $not $not$libresoc.v:192527$13126 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \cu_rdmaskn_i + connect \Y $not$libresoc.v:192527$13126_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $not $not$libresoc.v:192546$13145 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \all_rd_dly + connect \Y $not$libresoc.v:192546$13145_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" + cell $not $not$libresoc.v:192548$13147 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_done_dly + connect \Y $not$libresoc.v:192548$13147_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $not $not$libresoc.v:192551$13150 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \cu_wrmask_o + connect \Y $not$libresoc.v:192551$13150_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $not $not$libresoc.v:192554$13153 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$27 + connect \Y $not$libresoc.v:192554$13153_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + cell $not $not$libresoc.v:192559$13158 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_spr0_n_ready_i + connect \Y $not$libresoc.v:192559$13158_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $or $or$libresoc.v:192534$13133 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \$9 + connect \B \cu_rd__go_i + connect \Y $or$libresoc.v:192534$13133_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $or $or$libresoc.v:192558$13157 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$36 + connect \B \$38 + connect \Y $or$libresoc.v:192558$13157_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" + cell $or $or$libresoc.v:192568$13167 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \req_done + connect \B \cu_go_die_i + connect \Y $or$libresoc.v:192568$13167_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" + cell $or $or$libresoc.v:192569$13168 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_issue_i + connect \B \cu_go_die_i + connect \Y $or$libresoc.v:192569$13168_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" + cell $or $or$libresoc.v:192570$13169 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \cu_wr__go_i + connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } + connect \Y $or$libresoc.v:192570$13169_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" + cell $or $or$libresoc.v:192571$13170 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \cu_rd__go_i + connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } + connect \Y $or$libresoc.v:192571$13170_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" + cell $or $or$libresoc.v:192575$13174 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \reset_w + connect \B \prev_wr_go + connect \Y $or$libresoc.v:192575$13174_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $reduce_and $reduce_and$libresoc.v:192540$13139 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \$11 + connect \Y $reduce_and$libresoc.v:192540$13139_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $reduce_or $reduce_or$libresoc.v:192553$13152 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \$30 + connect \Y $reduce_or$libresoc.v:192553$13152_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $reduce_or $reduce_or$libresoc.v:192556$13155 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \cu_wr__go_i + connect \Y $reduce_or$libresoc.v:192556$13155_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $reduce_or $reduce_or$libresoc.v:192557$13156 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \prev_wr_go + connect \Y $reduce_or$libresoc.v:192557$13156_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" + cell $mux $ternary$libresoc.v:192582$13181 + parameter \WIDTH 64 + connect \A \src_r0 + connect \B \src1_i + connect \S \src_l_q_src [0] + connect \Y $ternary$libresoc.v:192582$13181_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" + cell $mux $ternary$libresoc.v:192583$13182 + parameter \WIDTH 64 + connect \A \src_r1 + connect \B \src2_i + connect \S \src_l_q_src [1] + connect \Y $ternary$libresoc.v:192583$13182_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" + cell $mux $ternary$libresoc.v:192584$13183 + parameter \WIDTH 64 + connect \A \src_r2 + connect \B \src3_i + connect \S \src_l_q_src [2] + connect \Y $ternary$libresoc.v:192584$13183_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" + cell $mux $ternary$libresoc.v:192585$13184 + parameter \WIDTH 1 + connect \A \src_r3 + connect \B \src4_i + connect \S \src_l_q_src [3] + connect \Y $ternary$libresoc.v:192585$13184_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" + cell $mux $ternary$libresoc.v:192586$13185 + parameter \WIDTH 2 + connect \A \src_r4 + connect \B \src5_i + connect \S \src_l_q_src [4] + connect \Y $ternary$libresoc.v:192586$13185_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" + cell $mux $ternary$libresoc.v:192587$13186 + parameter \WIDTH 2 + connect \A \src_r5 + connect \B \src6_i + connect \S \src_l_q_src [5] + connect \Y $ternary$libresoc.v:192587$13186_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:192663.14-192669.4" + cell \alu_l$73 \alu_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_alu \alu_l_q_alu + connect \r_alu \alu_l_r_alu + connect \s_alu \alu_l_s_alu + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:192670.12-192699.4" + cell \alu_spr0 \alu_spr0 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \fast1 \alu_spr0_fast1 + connect \fast1$2 \alu_spr0_fast1$2 + connect \fast1_ok \fast1_ok + connect \n_ready_i \alu_spr0_n_ready_i + connect \n_valid_o \alu_spr0_n_valid_o + connect \o \alu_spr0_o + connect \o_ok \o_ok + connect \p_ready_o \alu_spr0_p_ready_o + connect \p_valid_i \alu_spr0_p_valid_i + connect \ra \alu_spr0_ra + connect \spr1 \alu_spr0_spr1 + connect \spr1$1 \alu_spr0_spr1$1 + connect \spr1_ok \spr1_ok + connect \spr_op__fn_unit \alu_spr0_spr_op__fn_unit + connect \spr_op__insn \alu_spr0_spr_op__insn + connect \spr_op__insn_type \alu_spr0_spr_op__insn_type + connect \spr_op__is_32bit \alu_spr0_spr_op__is_32bit + connect \xer_ca \alu_spr0_xer_ca + connect \xer_ca$5 \alu_spr0_xer_ca$5 + connect \xer_ca_ok \xer_ca_ok + connect \xer_ov \alu_spr0_xer_ov + connect \xer_ov$4 \alu_spr0_xer_ov$4 + connect \xer_ov_ok \xer_ov_ok + connect \xer_so \alu_spr0_xer_so + connect \xer_so$3 \alu_spr0_xer_so$3 + connect \xer_so_ok \xer_so_ok + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:192700.15-192706.4" + cell \alui_l$72 \alui_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_alui \alui_l_q_alui + connect \r_alui \alui_l_r_alui + connect \s_alui \alui_l_s_alui + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:192707.14-192713.4" + cell \opc_l$68 \opc_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_opc \opc_l_q_opc + connect \r_opc \opc_l_r_opc + connect \s_opc \opc_l_s_opc + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:192714.14-192720.4" + cell \req_l$69 \req_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_req \req_l_q_req + connect \r_req \req_l_r_req + connect \s_req \req_l_s_req + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:192721.14-192727.4" + cell \rok_l$71 \rok_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_rdok \rok_l_q_rdok + connect \r_rdok \rok_l_r_rdok + connect \s_rdok \rok_l_s_rdok + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:192728.14-192733.4" + cell \rst_l$70 \rst_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \r_rst \rst_l_r_rst + connect \s_rst \rst_l_s_rst + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:192734.14-192740.4" + cell \src_l$67 \src_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_src \src_l_q_src + connect \r_src \src_l_r_src + connect \s_src \src_l_s_src + end + attribute \src "libresoc.v:191916.7-191916.20" + process $proc$libresoc.v:191916$13346 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:192052.7-192052.24" + process $proc$libresoc.v:192052$13347 + assign { } { } + assign $1\all_rd_dly[0:0] 1'0 + sync always + sync init + update \all_rd_dly $1\all_rd_dly[0:0] + end + attribute \src "libresoc.v:192062.7-192062.26" + process $proc$libresoc.v:192062$13348 + assign { } { } + assign $1\alu_done_dly[0:0] 1'0 + sync always + sync init + update \alu_done_dly $1\alu_done_dly[0:0] + end + attribute \src "libresoc.v:192070.7-192070.25" + process $proc$libresoc.v:192070$13349 + assign { } { } + assign $1\alu_l_r_alu[0:0] 1'1 + sync always + sync init + update \alu_l_r_alu $1\alu_l_r_alu[0:0] + end + attribute \src "libresoc.v:192114.14-192114.49" + process $proc$libresoc.v:192114$13350 + assign { } { } + assign $1\alu_spr0_spr_op__fn_unit[12:0] 13'0000000000000 + sync always + sync init + update \alu_spr0_spr_op__fn_unit $1\alu_spr0_spr_op__fn_unit[12:0] + end + attribute \src "libresoc.v:192118.14-192118.43" + process $proc$libresoc.v:192118$13351 + assign { } { } + assign $1\alu_spr0_spr_op__insn[31:0] 0 + sync always + sync init + update \alu_spr0_spr_op__insn $1\alu_spr0_spr_op__insn[31:0] + end + attribute \src "libresoc.v:192196.13-192196.47" + process $proc$libresoc.v:192196$13352 + assign { } { } + assign $1\alu_spr0_spr_op__insn_type[6:0] 7'0000000 + sync always + sync init + update \alu_spr0_spr_op__insn_type $1\alu_spr0_spr_op__insn_type[6:0] + end + attribute \src "libresoc.v:192200.7-192200.39" + process $proc$libresoc.v:192200$13353 + assign { } { } + assign $1\alu_spr0_spr_op__is_32bit[0:0] 1'0 + sync always + sync init + update \alu_spr0_spr_op__is_32bit $1\alu_spr0_spr_op__is_32bit[0:0] + end + attribute \src "libresoc.v:192218.7-192218.27" + process $proc$libresoc.v:192218$13354 + assign { } { } + assign $1\alui_l_r_alui[0:0] 1'1 + sync always + sync init + update \alui_l_r_alui $1\alui_l_r_alui[0:0] + end + attribute \src "libresoc.v:192250.14-192250.47" + process $proc$libresoc.v:192250$13355 + assign { } { } + assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \data_r0__o $1\data_r0__o[63:0] + end + attribute \src "libresoc.v:192254.7-192254.27" + process $proc$libresoc.v:192254$13356 + assign { } { } + assign $1\data_r0__o_ok[0:0] 1'0 + sync always + sync init + update \data_r0__o_ok $1\data_r0__o_ok[0:0] + end + attribute \src "libresoc.v:192258.14-192258.50" + process $proc$libresoc.v:192258$13357 + assign { } { } + assign $1\data_r1__spr1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \data_r1__spr1 $1\data_r1__spr1[63:0] + end + attribute \src "libresoc.v:192262.7-192262.30" + process $proc$libresoc.v:192262$13358 + assign { } { } + assign $1\data_r1__spr1_ok[0:0] 1'0 + sync always + sync init + update \data_r1__spr1_ok $1\data_r1__spr1_ok[0:0] + end + attribute \src "libresoc.v:192266.14-192266.51" + process $proc$libresoc.v:192266$13359 + assign { } { } + assign $1\data_r2__fast1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \data_r2__fast1 $1\data_r2__fast1[63:0] + end + attribute \src "libresoc.v:192270.7-192270.31" + process $proc$libresoc.v:192270$13360 + assign { } { } + assign $1\data_r2__fast1_ok[0:0] 1'0 + sync always + sync init + update \data_r2__fast1_ok $1\data_r2__fast1_ok[0:0] + end + attribute \src "libresoc.v:192274.7-192274.29" + process $proc$libresoc.v:192274$13361 + assign { } { } + assign $1\data_r3__xer_so[0:0] 1'0 + sync always + sync init + update \data_r3__xer_so $1\data_r3__xer_so[0:0] + end + attribute \src "libresoc.v:192278.7-192278.32" + process $proc$libresoc.v:192278$13362 + assign { } { } + assign $1\data_r3__xer_so_ok[0:0] 1'0 + sync always + sync init + update \data_r3__xer_so_ok $1\data_r3__xer_so_ok[0:0] + end + attribute \src "libresoc.v:192282.13-192282.35" + process $proc$libresoc.v:192282$13363 + assign { } { } + assign $1\data_r4__xer_ov[1:0] 2'00 + sync always + sync init + update \data_r4__xer_ov $1\data_r4__xer_ov[1:0] + end + attribute \src "libresoc.v:192286.7-192286.32" + process $proc$libresoc.v:192286$13364 + assign { } { } + assign $1\data_r4__xer_ov_ok[0:0] 1'0 + sync always + sync init + update \data_r4__xer_ov_ok $1\data_r4__xer_ov_ok[0:0] + end + attribute \src "libresoc.v:192290.13-192290.35" + process $proc$libresoc.v:192290$13365 + assign { } { } + assign $1\data_r5__xer_ca[1:0] 2'00 + sync always + sync init + update \data_r5__xer_ca $1\data_r5__xer_ca[1:0] + end + attribute \src "libresoc.v:192294.7-192294.32" + process $proc$libresoc.v:192294$13366 + assign { } { } + assign $1\data_r5__xer_ca_ok[0:0] 1'0 + sync always + sync init + update \data_r5__xer_ca_ok $1\data_r5__xer_ca_ok[0:0] + end + attribute \src "libresoc.v:192322.7-192322.25" + process $proc$libresoc.v:192322$13367 + assign { } { } + assign $1\opc_l_r_opc[0:0] 1'1 + sync always + sync init + update \opc_l_r_opc $1\opc_l_r_opc[0:0] + end + attribute \src "libresoc.v:192326.7-192326.25" + process $proc$libresoc.v:192326$13368 + assign { } { } + assign $1\opc_l_s_opc[0:0] 1'0 + sync always + sync init + update \opc_l_s_opc $1\opc_l_s_opc[0:0] + end + attribute \src "libresoc.v:192426.13-192426.31" + process $proc$libresoc.v:192426$13369 + assign { } { } + assign $1\prev_wr_go[5:0] 6'000000 + sync always + sync init + update \prev_wr_go $1\prev_wr_go[5:0] + end + attribute \src "libresoc.v:192434.13-192434.32" + process $proc$libresoc.v:192434$13370 + assign { } { } + assign $1\req_l_r_req[5:0] 6'111111 + sync always + sync init + update \req_l_r_req $1\req_l_r_req[5:0] + end + attribute \src "libresoc.v:192438.13-192438.32" + process $proc$libresoc.v:192438$13371 + assign { } { } + assign $1\req_l_s_req[5:0] 6'000000 + sync always + sync init + update \req_l_s_req $1\req_l_s_req[5:0] + end + attribute \src "libresoc.v:192450.7-192450.26" + process $proc$libresoc.v:192450$13372 + assign { } { } + assign $1\rok_l_r_rdok[0:0] 1'1 + sync always + sync init + update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] + end + attribute \src "libresoc.v:192454.7-192454.26" + process $proc$libresoc.v:192454$13373 + assign { } { } + assign $1\rok_l_s_rdok[0:0] 1'0 + sync always + sync init + update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] + end + attribute \src "libresoc.v:192458.7-192458.25" + process $proc$libresoc.v:192458$13374 + assign { } { } + assign $1\rst_l_r_rst[0:0] 1'1 + sync always + sync init + update \rst_l_r_rst $1\rst_l_r_rst[0:0] + end + attribute \src "libresoc.v:192462.7-192462.25" + process $proc$libresoc.v:192462$13375 + assign { } { } + assign $1\rst_l_s_rst[0:0] 1'0 + sync always + sync init + update \rst_l_s_rst $1\rst_l_s_rst[0:0] + end + attribute \src "libresoc.v:192484.13-192484.32" + process $proc$libresoc.v:192484$13376 + assign { } { } + assign $1\src_l_r_src[5:0] 6'111111 + sync always + sync init + update \src_l_r_src $1\src_l_r_src[5:0] + end + attribute \src "libresoc.v:192488.13-192488.32" + process $proc$libresoc.v:192488$13377 + assign { } { } + assign $1\src_l_s_src[5:0] 6'000000 + sync always + sync init + update \src_l_s_src $1\src_l_s_src[5:0] + end + attribute \src "libresoc.v:192492.14-192492.43" + process $proc$libresoc.v:192492$13378 + assign { } { } + assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \src_r0 $1\src_r0[63:0] + end + attribute \src "libresoc.v:192496.14-192496.43" + process $proc$libresoc.v:192496$13379 + assign { } { } + assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \src_r1 $1\src_r1[63:0] + end + attribute \src "libresoc.v:192500.14-192500.43" + process $proc$libresoc.v:192500$13380 + assign { } { } + assign $1\src_r2[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \src_r2 $1\src_r2[63:0] + end + attribute \src "libresoc.v:192504.7-192504.20" + process $proc$libresoc.v:192504$13381 + assign { } { } + assign $1\src_r3[0:0] 1'0 + sync always + sync init + update \src_r3 $1\src_r3[0:0] + end + attribute \src "libresoc.v:192508.13-192508.26" + process $proc$libresoc.v:192508$13382 + assign { } { } + assign $1\src_r4[1:0] 2'00 + sync always + sync init + update \src_r4 $1\src_r4[1:0] + end + attribute \src "libresoc.v:192512.13-192512.26" + process $proc$libresoc.v:192512$13383 + assign { } { } + assign $1\src_r5[1:0] 2'00 + sync always + sync init + update \src_r5 $1\src_r5[1:0] + end + attribute \src "libresoc.v:192589.3-192590.39" + process $proc$libresoc.v:192589$13188 + assign { } { } + assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next + sync posedge \coresync_clk + update \alu_l_r_alu $0\alu_l_r_alu[0:0] + end + attribute \src "libresoc.v:192591.3-192592.43" + process $proc$libresoc.v:192591$13189 + assign { } { } + assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next + sync posedge \coresync_clk + update \alui_l_r_alui $0\alui_l_r_alui[0:0] + end + attribute \src "libresoc.v:192593.3-192594.29" + process $proc$libresoc.v:192593$13190 + assign { } { } + assign $0\src_r5[1:0] \src_r5$next + sync posedge \coresync_clk + update \src_r5 $0\src_r5[1:0] + end + attribute \src "libresoc.v:192595.3-192596.29" + process $proc$libresoc.v:192595$13191 + assign { } { } + assign $0\src_r4[1:0] \src_r4$next + sync posedge \coresync_clk + update \src_r4 $0\src_r4[1:0] + end + attribute \src "libresoc.v:192597.3-192598.29" + process $proc$libresoc.v:192597$13192 + assign { } { } + assign $0\src_r3[0:0] \src_r3$next + sync posedge \coresync_clk + update \src_r3 $0\src_r3[0:0] + end + attribute \src "libresoc.v:192599.3-192600.29" + process $proc$libresoc.v:192599$13193 + assign { } { } + assign $0\src_r2[63:0] \src_r2$next + sync posedge \coresync_clk + update \src_r2 $0\src_r2[63:0] + end + attribute \src "libresoc.v:192601.3-192602.29" + process $proc$libresoc.v:192601$13194 + assign { } { } + assign $0\src_r1[63:0] \src_r1$next + sync posedge \coresync_clk + update \src_r1 $0\src_r1[63:0] + end + attribute \src "libresoc.v:192603.3-192604.29" + process $proc$libresoc.v:192603$13195 + assign { } { } + assign $0\src_r0[63:0] \src_r0$next + sync posedge \coresync_clk + update \src_r0 $0\src_r0[63:0] + end + attribute \src "libresoc.v:192605.3-192606.47" + process $proc$libresoc.v:192605$13196 + assign { } { } + assign $0\data_r5__xer_ca[1:0] \data_r5__xer_ca$next + sync posedge \coresync_clk + update \data_r5__xer_ca $0\data_r5__xer_ca[1:0] + end + attribute \src "libresoc.v:192607.3-192608.53" + process $proc$libresoc.v:192607$13197 + assign { } { } + assign $0\data_r5__xer_ca_ok[0:0] \data_r5__xer_ca_ok$next + sync posedge \coresync_clk + update \data_r5__xer_ca_ok $0\data_r5__xer_ca_ok[0:0] + end + attribute \src "libresoc.v:192609.3-192610.47" + process $proc$libresoc.v:192609$13198 + assign { } { } + assign $0\data_r4__xer_ov[1:0] \data_r4__xer_ov$next + sync posedge \coresync_clk + update \data_r4__xer_ov $0\data_r4__xer_ov[1:0] + end + attribute \src "libresoc.v:192611.3-192612.53" + process $proc$libresoc.v:192611$13199 + assign { } { } + assign $0\data_r4__xer_ov_ok[0:0] \data_r4__xer_ov_ok$next + sync posedge \coresync_clk + update \data_r4__xer_ov_ok $0\data_r4__xer_ov_ok[0:0] + end + attribute \src "libresoc.v:192613.3-192614.47" + process $proc$libresoc.v:192613$13200 + assign { } { } + assign $0\data_r3__xer_so[0:0] \data_r3__xer_so$next + sync posedge \coresync_clk + update \data_r3__xer_so $0\data_r3__xer_so[0:0] + end + attribute \src "libresoc.v:192615.3-192616.53" + process $proc$libresoc.v:192615$13201 + assign { } { } + assign $0\data_r3__xer_so_ok[0:0] \data_r3__xer_so_ok$next + sync posedge \coresync_clk + update \data_r3__xer_so_ok $0\data_r3__xer_so_ok[0:0] + end + attribute \src "libresoc.v:192617.3-192618.45" + process $proc$libresoc.v:192617$13202 + assign { } { } + assign $0\data_r2__fast1[63:0] \data_r2__fast1$next + sync posedge \coresync_clk + update \data_r2__fast1 $0\data_r2__fast1[63:0] + end + attribute \src "libresoc.v:192619.3-192620.51" + process $proc$libresoc.v:192619$13203 + assign { } { } + assign $0\data_r2__fast1_ok[0:0] \data_r2__fast1_ok$next + sync posedge \coresync_clk + update \data_r2__fast1_ok $0\data_r2__fast1_ok[0:0] + end + attribute \src "libresoc.v:192621.3-192622.43" + process $proc$libresoc.v:192621$13204 + assign { } { } + assign $0\data_r1__spr1[63:0] \data_r1__spr1$next + sync posedge \coresync_clk + update \data_r1__spr1 $0\data_r1__spr1[63:0] + end + attribute \src "libresoc.v:192623.3-192624.49" + process $proc$libresoc.v:192623$13205 + assign { } { } + assign $0\data_r1__spr1_ok[0:0] \data_r1__spr1_ok$next + sync posedge \coresync_clk + update \data_r1__spr1_ok $0\data_r1__spr1_ok[0:0] + end + attribute \src "libresoc.v:192625.3-192626.37" + process $proc$libresoc.v:192625$13206 + assign { } { } + assign $0\data_r0__o[63:0] \data_r0__o$next + sync posedge \coresync_clk + update \data_r0__o $0\data_r0__o[63:0] + end + attribute \src "libresoc.v:192627.3-192628.43" + process $proc$libresoc.v:192627$13207 + assign { } { } + assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next + sync posedge \coresync_clk + update \data_r0__o_ok $0\data_r0__o_ok[0:0] + end + attribute \src "libresoc.v:192629.3-192630.69" + process $proc$libresoc.v:192629$13208 + assign { } { } + assign $0\alu_spr0_spr_op__insn_type[6:0] \alu_spr0_spr_op__insn_type$next + sync posedge \coresync_clk + update \alu_spr0_spr_op__insn_type $0\alu_spr0_spr_op__insn_type[6:0] + end + attribute \src "libresoc.v:192631.3-192632.65" + process $proc$libresoc.v:192631$13209 + assign { } { } + assign $0\alu_spr0_spr_op__fn_unit[12:0] \alu_spr0_spr_op__fn_unit$next + sync posedge \coresync_clk + update \alu_spr0_spr_op__fn_unit $0\alu_spr0_spr_op__fn_unit[12:0] + end + attribute \src "libresoc.v:192633.3-192634.59" + process $proc$libresoc.v:192633$13210 + assign { } { } + assign $0\alu_spr0_spr_op__insn[31:0] \alu_spr0_spr_op__insn$next + sync posedge \coresync_clk + update \alu_spr0_spr_op__insn $0\alu_spr0_spr_op__insn[31:0] + end + attribute \src "libresoc.v:192635.3-192636.67" + process $proc$libresoc.v:192635$13211 + assign { } { } + assign $0\alu_spr0_spr_op__is_32bit[0:0] \alu_spr0_spr_op__is_32bit$next + sync posedge \coresync_clk + update \alu_spr0_spr_op__is_32bit $0\alu_spr0_spr_op__is_32bit[0:0] + end + attribute \src "libresoc.v:192637.3-192638.39" + process $proc$libresoc.v:192637$13212 + assign { } { } + assign $0\req_l_r_req[5:0] \req_l_r_req$next + sync posedge \coresync_clk + update \req_l_r_req $0\req_l_r_req[5:0] + end + attribute \src "libresoc.v:192639.3-192640.39" + process $proc$libresoc.v:192639$13213 + assign { } { } + assign $0\req_l_s_req[5:0] \req_l_s_req$next + sync posedge \coresync_clk + update \req_l_s_req $0\req_l_s_req[5:0] + end + attribute \src "libresoc.v:192641.3-192642.39" + process $proc$libresoc.v:192641$13214 + assign { } { } + assign $0\src_l_r_src[5:0] \src_l_r_src$next + sync posedge \coresync_clk + update \src_l_r_src $0\src_l_r_src[5:0] + end + attribute \src "libresoc.v:192643.3-192644.39" + process $proc$libresoc.v:192643$13215 + assign { } { } + assign $0\src_l_s_src[5:0] \src_l_s_src$next + sync posedge \coresync_clk + update \src_l_s_src $0\src_l_s_src[5:0] + end + attribute \src "libresoc.v:192645.3-192646.39" + process $proc$libresoc.v:192645$13216 + assign { } { } + assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next + sync posedge \coresync_clk + update \opc_l_r_opc $0\opc_l_r_opc[0:0] + end + attribute \src "libresoc.v:192647.3-192648.39" + process $proc$libresoc.v:192647$13217 + assign { } { } + assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next + sync posedge \coresync_clk + update \opc_l_s_opc $0\opc_l_s_opc[0:0] + end + attribute \src "libresoc.v:192649.3-192650.39" + process $proc$libresoc.v:192649$13218 + assign { } { } + assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next + sync posedge \coresync_clk + update \rst_l_r_rst $0\rst_l_r_rst[0:0] + end + attribute \src "libresoc.v:192651.3-192652.39" + process $proc$libresoc.v:192651$13219 + assign { } { } + assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next + sync posedge \coresync_clk + update \rst_l_s_rst $0\rst_l_s_rst[0:0] + end + attribute \src "libresoc.v:192653.3-192654.41" + process $proc$libresoc.v:192653$13220 + assign { } { } + assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next + sync posedge \coresync_clk + update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] + end + attribute \src "libresoc.v:192655.3-192656.41" + process $proc$libresoc.v:192655$13221 + assign { } { } + assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next + sync posedge \coresync_clk + update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] + end + attribute \src "libresoc.v:192657.3-192658.37" + process $proc$libresoc.v:192657$13222 + assign { } { } + assign $0\prev_wr_go[5:0] \prev_wr_go$next + sync posedge \coresync_clk + update \prev_wr_go $0\prev_wr_go[5:0] + end + attribute \src "libresoc.v:192659.3-192660.40" + process $proc$libresoc.v:192659$13223 + assign { } { } + assign $0\alu_done_dly[0:0] \alu_spr0_n_valid_o + sync posedge \coresync_clk + update \alu_done_dly $0\alu_done_dly[0:0] + end + attribute \src "libresoc.v:192661.3-192662.25" + process $proc$libresoc.v:192661$13224 + assign { } { } + assign $0\all_rd_dly[0:0] \$14 + sync posedge \coresync_clk + update \all_rd_dly $0\all_rd_dly[0:0] + end + attribute \src "libresoc.v:192741.3-192750.6" + process $proc$libresoc.v:192741$13225 + assign { } { } + assign { } { } + assign $0\req_done[0:0] $1\req_done[0:0] + attribute \src "libresoc.v:192742.5-192742.29" + switch \initial + attribute \src "libresoc.v:192742.9-192742.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + switch \$58 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\req_done[0:0] 1'1 + case + assign $1\req_done[0:0] \$50 + end + sync always + update \req_done $0\req_done[0:0] + end + attribute \src "libresoc.v:192751.3-192759.6" + process $proc$libresoc.v:192751$13226 + assign { } { } + assign { } { } + assign $0\rok_l_s_rdok$next[0:0]$13227 $1\rok_l_s_rdok$next[0:0]$13228 + attribute \src "libresoc.v:192752.5-192752.29" + switch \initial + attribute \src "libresoc.v:192752.9-192752.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rok_l_s_rdok$next[0:0]$13228 1'0 + case + assign $1\rok_l_s_rdok$next[0:0]$13228 \cu_issue_i + end + sync always + update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$13227 + end + attribute \src "libresoc.v:192760.3-192768.6" + process $proc$libresoc.v:192760$13229 + assign { } { } + assign { } { } + assign $0\rok_l_r_rdok$next[0:0]$13230 $1\rok_l_r_rdok$next[0:0]$13231 + attribute \src "libresoc.v:192761.5-192761.29" + switch \initial + attribute \src "libresoc.v:192761.9-192761.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rok_l_r_rdok$next[0:0]$13231 1'1 + case + assign $1\rok_l_r_rdok$next[0:0]$13231 \$68 + end + sync always + update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$13230 + end + attribute \src "libresoc.v:192769.3-192777.6" + process $proc$libresoc.v:192769$13232 + assign { } { } + assign { } { } + assign $0\rst_l_s_rst$next[0:0]$13233 $1\rst_l_s_rst$next[0:0]$13234 + attribute \src "libresoc.v:192770.5-192770.29" + switch \initial + attribute \src "libresoc.v:192770.9-192770.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rst_l_s_rst$next[0:0]$13234 1'0 + case + assign $1\rst_l_s_rst$next[0:0]$13234 \all_rd + end + sync always + update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$13233 + end + attribute \src "libresoc.v:192778.3-192786.6" + process $proc$libresoc.v:192778$13235 + assign { } { } + assign { } { } + assign $0\rst_l_r_rst$next[0:0]$13236 $1\rst_l_r_rst$next[0:0]$13237 + attribute \src "libresoc.v:192779.5-192779.29" + switch \initial + attribute \src "libresoc.v:192779.9-192779.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rst_l_r_rst$next[0:0]$13237 1'1 + case + assign $1\rst_l_r_rst$next[0:0]$13237 \rst_r + end + sync always + update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$13236 + end + attribute \src "libresoc.v:192787.3-192795.6" + process $proc$libresoc.v:192787$13238 + assign { } { } + assign { } { } + assign $0\opc_l_s_opc$next[0:0]$13239 $1\opc_l_s_opc$next[0:0]$13240 + attribute \src "libresoc.v:192788.5-192788.29" + switch \initial + attribute \src "libresoc.v:192788.9-192788.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\opc_l_s_opc$next[0:0]$13240 1'0 + case + assign $1\opc_l_s_opc$next[0:0]$13240 \cu_issue_i + end + sync always + update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$13239 + end + attribute \src "libresoc.v:192796.3-192804.6" + process $proc$libresoc.v:192796$13241 + assign { } { } + assign { } { } + assign $0\opc_l_r_opc$next[0:0]$13242 $1\opc_l_r_opc$next[0:0]$13243 + attribute \src "libresoc.v:192797.5-192797.29" + switch \initial + attribute \src "libresoc.v:192797.9-192797.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\opc_l_r_opc$next[0:0]$13243 1'1 + case + assign $1\opc_l_r_opc$next[0:0]$13243 \req_done + end + sync always + update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$13242 + end + attribute \src "libresoc.v:192805.3-192813.6" + process $proc$libresoc.v:192805$13244 + assign { } { } + assign { } { } + assign $0\src_l_s_src$next[5:0]$13245 $1\src_l_s_src$next[5:0]$13246 + attribute \src "libresoc.v:192806.5-192806.29" + switch \initial + attribute \src "libresoc.v:192806.9-192806.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_l_s_src$next[5:0]$13246 6'000000 + case + assign $1\src_l_s_src$next[5:0]$13246 { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i } + end + sync always + update \src_l_s_src$next $0\src_l_s_src$next[5:0]$13245 + end + attribute \src "libresoc.v:192814.3-192822.6" + process $proc$libresoc.v:192814$13247 + assign { } { } + assign { } { } + assign $0\src_l_r_src$next[5:0]$13248 $1\src_l_r_src$next[5:0]$13249 + attribute \src "libresoc.v:192815.5-192815.29" + switch \initial + attribute \src "libresoc.v:192815.9-192815.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_l_r_src$next[5:0]$13249 6'111111 + case + assign $1\src_l_r_src$next[5:0]$13249 \reset_r + end + sync always + update \src_l_r_src$next $0\src_l_r_src$next[5:0]$13248 + end + attribute \src "libresoc.v:192823.3-192831.6" + process $proc$libresoc.v:192823$13250 + assign { } { } + assign { } { } + assign $0\req_l_s_req$next[5:0]$13251 $1\req_l_s_req$next[5:0]$13252 + attribute \src "libresoc.v:192824.5-192824.29" + switch \initial + attribute \src "libresoc.v:192824.9-192824.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\req_l_s_req$next[5:0]$13252 6'000000 + case + assign $1\req_l_s_req$next[5:0]$13252 \$70 + end + sync always + update \req_l_s_req$next $0\req_l_s_req$next[5:0]$13251 + end + attribute \src "libresoc.v:192832.3-192840.6" + process $proc$libresoc.v:192832$13253 + assign { } { } + assign { } { } + assign $0\req_l_r_req$next[5:0]$13254 $1\req_l_r_req$next[5:0]$13255 + attribute \src "libresoc.v:192833.5-192833.29" + switch \initial + attribute \src "libresoc.v:192833.9-192833.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\req_l_r_req$next[5:0]$13255 6'111111 + case + assign $1\req_l_r_req$next[5:0]$13255 \$72 + end + sync always + update \req_l_r_req$next $0\req_l_r_req$next[5:0]$13254 + end + attribute \src "libresoc.v:192841.3-192853.6" + process $proc$libresoc.v:192841$13256 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\alu_spr0_spr_op__fn_unit$next[12:0]$13257 $1\alu_spr0_spr_op__fn_unit$next[12:0]$13261 + assign $0\alu_spr0_spr_op__insn$next[31:0]$13258 $1\alu_spr0_spr_op__insn$next[31:0]$13262 + assign $0\alu_spr0_spr_op__insn_type$next[6:0]$13259 $1\alu_spr0_spr_op__insn_type$next[6:0]$13263 + assign $0\alu_spr0_spr_op__is_32bit$next[0:0]$13260 $1\alu_spr0_spr_op__is_32bit$next[0:0]$13264 + attribute \src "libresoc.v:192842.5-192842.29" + switch \initial + attribute \src "libresoc.v:192842.9-192842.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\alu_spr0_spr_op__is_32bit$next[0:0]$13264 $1\alu_spr0_spr_op__insn$next[31:0]$13262 $1\alu_spr0_spr_op__fn_unit$next[12:0]$13261 $1\alu_spr0_spr_op__insn_type$next[6:0]$13263 } { \oper_i_alu_spr0__is_32bit \oper_i_alu_spr0__insn \oper_i_alu_spr0__fn_unit \oper_i_alu_spr0__insn_type } + case + assign $1\alu_spr0_spr_op__fn_unit$next[12:0]$13261 \alu_spr0_spr_op__fn_unit + assign $1\alu_spr0_spr_op__insn$next[31:0]$13262 \alu_spr0_spr_op__insn + assign $1\alu_spr0_spr_op__insn_type$next[6:0]$13263 \alu_spr0_spr_op__insn_type + assign $1\alu_spr0_spr_op__is_32bit$next[0:0]$13264 \alu_spr0_spr_op__is_32bit + end + sync always + update \alu_spr0_spr_op__fn_unit$next $0\alu_spr0_spr_op__fn_unit$next[12:0]$13257 + update \alu_spr0_spr_op__insn$next $0\alu_spr0_spr_op__insn$next[31:0]$13258 + update \alu_spr0_spr_op__insn_type$next $0\alu_spr0_spr_op__insn_type$next[6:0]$13259 + update \alu_spr0_spr_op__is_32bit$next $0\alu_spr0_spr_op__is_32bit$next[0:0]$13260 + end + attribute \src "libresoc.v:192854.3-192875.6" + process $proc$libresoc.v:192854$13265 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r0__o$next[63:0]$13266 $2\data_r0__o$next[63:0]$13270 + assign { } { } + assign $0\data_r0__o_ok$next[0:0]$13267 $3\data_r0__o_ok$next[0:0]$13272 + attribute \src "libresoc.v:192855.5-192855.29" + switch \initial + attribute \src "libresoc.v:192855.9-192855.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r0__o_ok$next[0:0]$13269 $1\data_r0__o$next[63:0]$13268 } { \o_ok \alu_spr0_o } + case + assign $1\data_r0__o$next[63:0]$13268 \data_r0__o + assign $1\data_r0__o_ok$next[0:0]$13269 \data_r0__o_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r0__o_ok$next[0:0]$13271 $2\data_r0__o$next[63:0]$13270 } 65'00000000000000000000000000000000000000000000000000000000000000000 + case + assign $2\data_r0__o$next[63:0]$13270 $1\data_r0__o$next[63:0]$13268 + assign $2\data_r0__o_ok$next[0:0]$13271 $1\data_r0__o_ok$next[0:0]$13269 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r0__o_ok$next[0:0]$13272 1'0 + case + assign $3\data_r0__o_ok$next[0:0]$13272 $2\data_r0__o_ok$next[0:0]$13271 + end + sync always + update \data_r0__o$next $0\data_r0__o$next[63:0]$13266 + update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$13267 + end + attribute \src "libresoc.v:192876.3-192897.6" + process $proc$libresoc.v:192876$13273 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r1__spr1$next[63:0]$13274 $2\data_r1__spr1$next[63:0]$13278 + assign { } { } + assign $0\data_r1__spr1_ok$next[0:0]$13275 $3\data_r1__spr1_ok$next[0:0]$13280 + attribute \src "libresoc.v:192877.5-192877.29" + switch \initial + attribute \src "libresoc.v:192877.9-192877.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r1__spr1_ok$next[0:0]$13277 $1\data_r1__spr1$next[63:0]$13276 } { \spr1_ok \alu_spr0_spr1 } + case + assign $1\data_r1__spr1$next[63:0]$13276 \data_r1__spr1 + assign $1\data_r1__spr1_ok$next[0:0]$13277 \data_r1__spr1_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r1__spr1_ok$next[0:0]$13279 $2\data_r1__spr1$next[63:0]$13278 } 65'00000000000000000000000000000000000000000000000000000000000000000 + case + assign $2\data_r1__spr1$next[63:0]$13278 $1\data_r1__spr1$next[63:0]$13276 + assign $2\data_r1__spr1_ok$next[0:0]$13279 $1\data_r1__spr1_ok$next[0:0]$13277 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r1__spr1_ok$next[0:0]$13280 1'0 + case + assign $3\data_r1__spr1_ok$next[0:0]$13280 $2\data_r1__spr1_ok$next[0:0]$13279 + end + sync always + update \data_r1__spr1$next $0\data_r1__spr1$next[63:0]$13274 + update \data_r1__spr1_ok$next $0\data_r1__spr1_ok$next[0:0]$13275 + end + attribute \src "libresoc.v:192898.3-192919.6" + process $proc$libresoc.v:192898$13281 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r2__fast1$next[63:0]$13282 $2\data_r2__fast1$next[63:0]$13286 + assign { } { } + assign $0\data_r2__fast1_ok$next[0:0]$13283 $3\data_r2__fast1_ok$next[0:0]$13288 + attribute \src "libresoc.v:192899.5-192899.29" + switch \initial + attribute \src "libresoc.v:192899.9-192899.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r2__fast1_ok$next[0:0]$13285 $1\data_r2__fast1$next[63:0]$13284 } { \fast1_ok \alu_spr0_fast1 } + case + assign $1\data_r2__fast1$next[63:0]$13284 \data_r2__fast1 + assign $1\data_r2__fast1_ok$next[0:0]$13285 \data_r2__fast1_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r2__fast1_ok$next[0:0]$13287 $2\data_r2__fast1$next[63:0]$13286 } 65'00000000000000000000000000000000000000000000000000000000000000000 + case + assign $2\data_r2__fast1$next[63:0]$13286 $1\data_r2__fast1$next[63:0]$13284 + assign $2\data_r2__fast1_ok$next[0:0]$13287 $1\data_r2__fast1_ok$next[0:0]$13285 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r2__fast1_ok$next[0:0]$13288 1'0 + case + assign $3\data_r2__fast1_ok$next[0:0]$13288 $2\data_r2__fast1_ok$next[0:0]$13287 + end + sync always + update \data_r2__fast1$next $0\data_r2__fast1$next[63:0]$13282 + update \data_r2__fast1_ok$next $0\data_r2__fast1_ok$next[0:0]$13283 + end + attribute \src "libresoc.v:192920.3-192941.6" + process $proc$libresoc.v:192920$13289 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r3__xer_so$next[0:0]$13290 $2\data_r3__xer_so$next[0:0]$13294 + assign { } { } + assign $0\data_r3__xer_so_ok$next[0:0]$13291 $3\data_r3__xer_so_ok$next[0:0]$13296 + attribute \src "libresoc.v:192921.5-192921.29" + switch \initial + attribute \src "libresoc.v:192921.9-192921.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r3__xer_so_ok$next[0:0]$13293 $1\data_r3__xer_so$next[0:0]$13292 } { \xer_so_ok \alu_spr0_xer_so } + case + assign $1\data_r3__xer_so$next[0:0]$13292 \data_r3__xer_so + assign $1\data_r3__xer_so_ok$next[0:0]$13293 \data_r3__xer_so_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r3__xer_so_ok$next[0:0]$13295 $2\data_r3__xer_so$next[0:0]$13294 } 2'00 + case + assign $2\data_r3__xer_so$next[0:0]$13294 $1\data_r3__xer_so$next[0:0]$13292 + assign $2\data_r3__xer_so_ok$next[0:0]$13295 $1\data_r3__xer_so_ok$next[0:0]$13293 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r3__xer_so_ok$next[0:0]$13296 1'0 + case + assign $3\data_r3__xer_so_ok$next[0:0]$13296 $2\data_r3__xer_so_ok$next[0:0]$13295 + end + sync always + update \data_r3__xer_so$next $0\data_r3__xer_so$next[0:0]$13290 + update \data_r3__xer_so_ok$next $0\data_r3__xer_so_ok$next[0:0]$13291 + end + attribute \src "libresoc.v:192942.3-192963.6" + process $proc$libresoc.v:192942$13297 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r4__xer_ov$next[1:0]$13298 $2\data_r4__xer_ov$next[1:0]$13302 + assign { } { } + assign $0\data_r4__xer_ov_ok$next[0:0]$13299 $3\data_r4__xer_ov_ok$next[0:0]$13304 + attribute \src "libresoc.v:192943.5-192943.29" + switch \initial + attribute \src "libresoc.v:192943.9-192943.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r4__xer_ov_ok$next[0:0]$13301 $1\data_r4__xer_ov$next[1:0]$13300 } { \xer_ov_ok \alu_spr0_xer_ov } + case + assign $1\data_r4__xer_ov$next[1:0]$13300 \data_r4__xer_ov + assign $1\data_r4__xer_ov_ok$next[0:0]$13301 \data_r4__xer_ov_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r4__xer_ov_ok$next[0:0]$13303 $2\data_r4__xer_ov$next[1:0]$13302 } 3'000 + case + assign $2\data_r4__xer_ov$next[1:0]$13302 $1\data_r4__xer_ov$next[1:0]$13300 + assign $2\data_r4__xer_ov_ok$next[0:0]$13303 $1\data_r4__xer_ov_ok$next[0:0]$13301 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r4__xer_ov_ok$next[0:0]$13304 1'0 + case + assign $3\data_r4__xer_ov_ok$next[0:0]$13304 $2\data_r4__xer_ov_ok$next[0:0]$13303 + end + sync always + update \data_r4__xer_ov$next $0\data_r4__xer_ov$next[1:0]$13298 + update \data_r4__xer_ov_ok$next $0\data_r4__xer_ov_ok$next[0:0]$13299 + end + attribute \src "libresoc.v:192964.3-192985.6" + process $proc$libresoc.v:192964$13305 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r5__xer_ca$next[1:0]$13306 $2\data_r5__xer_ca$next[1:0]$13310 + assign { } { } + assign $0\data_r5__xer_ca_ok$next[0:0]$13307 $3\data_r5__xer_ca_ok$next[0:0]$13312 + attribute \src "libresoc.v:192965.5-192965.29" + switch \initial + attribute \src "libresoc.v:192965.9-192965.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r5__xer_ca_ok$next[0:0]$13309 $1\data_r5__xer_ca$next[1:0]$13308 } { \xer_ca_ok \alu_spr0_xer_ca } + case + assign $1\data_r5__xer_ca$next[1:0]$13308 \data_r5__xer_ca + assign $1\data_r5__xer_ca_ok$next[0:0]$13309 \data_r5__xer_ca_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r5__xer_ca_ok$next[0:0]$13311 $2\data_r5__xer_ca$next[1:0]$13310 } 3'000 + case + assign $2\data_r5__xer_ca$next[1:0]$13310 $1\data_r5__xer_ca$next[1:0]$13308 + assign $2\data_r5__xer_ca_ok$next[0:0]$13311 $1\data_r5__xer_ca_ok$next[0:0]$13309 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r5__xer_ca_ok$next[0:0]$13312 1'0 + case + assign $3\data_r5__xer_ca_ok$next[0:0]$13312 $2\data_r5__xer_ca_ok$next[0:0]$13311 + end + sync always + update \data_r5__xer_ca$next $0\data_r5__xer_ca$next[1:0]$13306 + update \data_r5__xer_ca_ok$next $0\data_r5__xer_ca_ok$next[0:0]$13307 + end + attribute \src "libresoc.v:192986.3-192995.6" + process $proc$libresoc.v:192986$13313 + assign { } { } + assign { } { } + assign $0\src_r0$next[63:0]$13314 $1\src_r0$next[63:0]$13315 + attribute \src "libresoc.v:192987.5-192987.29" + switch \initial + attribute \src "libresoc.v:192987.9-192987.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" + switch \src_l_q_src [0] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r0$next[63:0]$13315 \src1_i + case + assign $1\src_r0$next[63:0]$13315 \src_r0 + end + sync always + update \src_r0$next $0\src_r0$next[63:0]$13314 + end + attribute \src "libresoc.v:192996.3-193005.6" + process $proc$libresoc.v:192996$13316 + assign { } { } + assign { } { } + assign $0\src_r1$next[63:0]$13317 $1\src_r1$next[63:0]$13318 + attribute \src "libresoc.v:192997.5-192997.29" + switch \initial + attribute \src "libresoc.v:192997.9-192997.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" + switch \src_l_q_src [1] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r1$next[63:0]$13318 \src2_i + case + assign $1\src_r1$next[63:0]$13318 \src_r1 + end + sync always + update \src_r1$next $0\src_r1$next[63:0]$13317 + end + attribute \src "libresoc.v:193006.3-193015.6" + process $proc$libresoc.v:193006$13319 + assign { } { } + assign { } { } + assign $0\src_r2$next[63:0]$13320 $1\src_r2$next[63:0]$13321 + attribute \src "libresoc.v:193007.5-193007.29" + switch \initial + attribute \src "libresoc.v:193007.9-193007.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" + switch \src_l_q_src [2] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r2$next[63:0]$13321 \src3_i + case + assign $1\src_r2$next[63:0]$13321 \src_r2 + end + sync always + update \src_r2$next $0\src_r2$next[63:0]$13320 + end + attribute \src "libresoc.v:193016.3-193025.6" + process $proc$libresoc.v:193016$13322 + assign { } { } + assign { } { } + assign $0\src_r3$next[0:0]$13323 $1\src_r3$next[0:0]$13324 + attribute \src "libresoc.v:193017.5-193017.29" + switch \initial + attribute \src "libresoc.v:193017.9-193017.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" + switch \src_l_q_src [3] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r3$next[0:0]$13324 \src4_i + case + assign $1\src_r3$next[0:0]$13324 \src_r3 + end + sync always + update \src_r3$next $0\src_r3$next[0:0]$13323 + end + attribute \src "libresoc.v:193026.3-193035.6" + process $proc$libresoc.v:193026$13325 + assign { } { } + assign { } { } + assign $0\src_r4$next[1:0]$13326 $1\src_r4$next[1:0]$13327 + attribute \src "libresoc.v:193027.5-193027.29" + switch \initial + attribute \src "libresoc.v:193027.9-193027.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" + switch \src_l_q_src [4] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r4$next[1:0]$13327 \src5_i + case + assign $1\src_r4$next[1:0]$13327 \src_r4 + end + sync always + update \src_r4$next $0\src_r4$next[1:0]$13326 + end + attribute \src "libresoc.v:193036.3-193045.6" + process $proc$libresoc.v:193036$13328 + assign { } { } + assign { } { } + assign $0\src_r5$next[1:0]$13329 $1\src_r5$next[1:0]$13330 + attribute \src "libresoc.v:193037.5-193037.29" + switch \initial + attribute \src "libresoc.v:193037.9-193037.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" + switch \src_l_q_src [5] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r5$next[1:0]$13330 \src6_i + case + assign $1\src_r5$next[1:0]$13330 \src_r5 + end + sync always + update \src_r5$next $0\src_r5$next[1:0]$13329 + end + attribute \src "libresoc.v:193046.3-193054.6" + process $proc$libresoc.v:193046$13331 + assign { } { } + assign { } { } + assign $0\alui_l_r_alui$next[0:0]$13332 $1\alui_l_r_alui$next[0:0]$13333 + attribute \src "libresoc.v:193047.5-193047.29" + switch \initial + attribute \src "libresoc.v:193047.9-193047.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\alui_l_r_alui$next[0:0]$13333 1'1 + case + assign $1\alui_l_r_alui$next[0:0]$13333 \$98 + end + sync always + update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$13332 + end + attribute \src "libresoc.v:193055.3-193063.6" + process $proc$libresoc.v:193055$13334 + assign { } { } + assign { } { } + assign $0\alu_l_r_alu$next[0:0]$13335 $1\alu_l_r_alu$next[0:0]$13336 + attribute \src "libresoc.v:193056.5-193056.29" + switch \initial + attribute \src "libresoc.v:193056.9-193056.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\alu_l_r_alu$next[0:0]$13336 1'1 + case + assign $1\alu_l_r_alu$next[0:0]$13336 \$100 + end + sync always + update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$13335 + end + attribute \src "libresoc.v:193064.3-193073.6" + process $proc$libresoc.v:193064$13337 + assign { } { } + assign { } { } + assign $0\dest1_o[63:0] $1\dest1_o[63:0] + attribute \src "libresoc.v:193065.5-193065.29" + switch \initial + attribute \src "libresoc.v:193065.9-193065.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$126 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest1_o[63:0] \data_r0__o + case + assign $1\dest1_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \dest1_o $0\dest1_o[63:0] + end + attribute \src "libresoc.v:193074.3-193083.6" + process $proc$libresoc.v:193074$13338 + assign { } { } + assign { } { } + assign $0\dest2_o[63:0] $1\dest2_o[63:0] + attribute \src "libresoc.v:193075.5-193075.29" + switch \initial + attribute \src "libresoc.v:193075.9-193075.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$128 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest2_o[63:0] \data_r1__spr1 + case + assign $1\dest2_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \dest2_o $0\dest2_o[63:0] + end + attribute \src "libresoc.v:193084.3-193093.6" + process $proc$libresoc.v:193084$13339 + assign { } { } + assign { } { } + assign $0\dest3_o[63:0] $1\dest3_o[63:0] + attribute \src "libresoc.v:193085.5-193085.29" + switch \initial + attribute \src "libresoc.v:193085.9-193085.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$130 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest3_o[63:0] \data_r2__fast1 + case + assign $1\dest3_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \dest3_o $0\dest3_o[63:0] + end + attribute \src "libresoc.v:193094.3-193103.6" + process $proc$libresoc.v:193094$13340 + assign { } { } + assign { } { } + assign $0\dest4_o[0:0] $1\dest4_o[0:0] + attribute \src "libresoc.v:193095.5-193095.29" + switch \initial + attribute \src "libresoc.v:193095.9-193095.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$132 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest4_o[0:0] \data_r3__xer_so + case + assign $1\dest4_o[0:0] 1'0 + end + sync always + update \dest4_o $0\dest4_o[0:0] + end + attribute \src "libresoc.v:193104.3-193113.6" + process $proc$libresoc.v:193104$13341 + assign { } { } + assign { } { } + assign $0\dest5_o[1:0] $1\dest5_o[1:0] + attribute \src "libresoc.v:193105.5-193105.29" + switch \initial + attribute \src "libresoc.v:193105.9-193105.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$134 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest5_o[1:0] \data_r4__xer_ov + case + assign $1\dest5_o[1:0] 2'00 + end + sync always + update \dest5_o $0\dest5_o[1:0] + end + attribute \src "libresoc.v:193114.3-193123.6" + process $proc$libresoc.v:193114$13342 + assign { } { } + assign { } { } + assign $0\dest6_o[1:0] $1\dest6_o[1:0] + attribute \src "libresoc.v:193115.5-193115.29" + switch \initial + attribute \src "libresoc.v:193115.9-193115.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$136 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest6_o[1:0] \data_r5__xer_ca + case + assign $1\dest6_o[1:0] 2'00 + end + sync always + update \dest6_o $0\dest6_o[1:0] + end + attribute \src "libresoc.v:193124.3-193132.6" + process $proc$libresoc.v:193124$13343 + assign { } { } + assign { } { } + assign $0\prev_wr_go$next[5:0]$13344 $1\prev_wr_go$next[5:0]$13345 + attribute \src "libresoc.v:193125.5-193125.29" + switch \initial + attribute \src "libresoc.v:193125.9-193125.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\prev_wr_go$next[5:0]$13345 6'000000 + case + assign $1\prev_wr_go$next[5:0]$13345 \$24 + end + sync always + update \prev_wr_go$next $0\prev_wr_go$next[5:0]$13344 + end + connect \$9 $not$libresoc.v:192523$13122_Y + connect \$100 $and$libresoc.v:192524$13123_Y + connect \$102 $and$libresoc.v:192525$13124_Y + connect \$104 $and$libresoc.v:192526$13125_Y + connect \$106 $not$libresoc.v:192527$13126_Y + connect \$108 $and$libresoc.v:192528$13127_Y + connect \$110 $and$libresoc.v:192529$13128_Y + connect \$112 $and$libresoc.v:192530$13129_Y + connect \$114 $and$libresoc.v:192531$13130_Y + connect \$116 $and$libresoc.v:192532$13131_Y + connect \$118 $and$libresoc.v:192533$13132_Y + connect \$11 $or$libresoc.v:192534$13133_Y + connect \$120 $and$libresoc.v:192535$13134_Y + connect \$122 $and$libresoc.v:192536$13135_Y + connect \$124 $and$libresoc.v:192537$13136_Y + connect \$126 $and$libresoc.v:192538$13137_Y + connect \$128 $and$libresoc.v:192539$13138_Y + connect \$8 $reduce_and$libresoc.v:192540$13139_Y + connect \$130 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$eq$libresoc.v:192562$13161_Y + connect \$50 $and$libresoc.v:192563$13162_Y + connect \$52 $eq$libresoc.v:192564$13163_Y + connect \$54 $and$libresoc.v:192565$13164_Y + connect \$56 $and$libresoc.v:192566$13165_Y + connect \$58 $and$libresoc.v:192567$13166_Y + connect \$60 $or$libresoc.v:192568$13167_Y + connect \$62 $or$libresoc.v:192569$13168_Y + connect \$64 $or$libresoc.v:192570$13169_Y + connect \$66 $or$libresoc.v:192571$13170_Y + connect \$68 $and$libresoc.v:192572$13171_Y + connect \$6 $and$libresoc.v:192573$13172_Y + connect \$70 $and$libresoc.v:192574$13173_Y + connect \$72 $or$libresoc.v:192575$13174_Y + connect \$74 $and$libresoc.v:192576$13175_Y + connect \$76 $and$libresoc.v:192577$13176_Y + connect \$78 $and$libresoc.v:192578$13177_Y + connect \$80 $and$libresoc.v:192579$13178_Y + connect \$82 $and$libresoc.v:192580$13179_Y + connect \$84 $and$libresoc.v:192581$13180_Y + connect \$86 $ternary$libresoc.v:192582$13181_Y + connect \$88 $ternary$libresoc.v:192583$13182_Y + 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\alu_pulse \alu_pulse \alu_pulse \alu_pulse } + connect \alu_pulse \alu_done_rise + connect \alu_done_rise \$22 + connect \alu_done_dly$next \alu_done + connect \alu_done \alu_spr0_n_valid_o + connect \all_rd_pulse \all_rd_rise + connect \all_rd_rise \$18 + connect \all_rd_dly$next \all_rd + connect \all_rd \$14 +end +attribute \src "libresoc.v:193168.1-193684.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.alu_spr0.pipe.spr_main" +attribute \generator "nMigen" +module \spr_main + attribute \src "libresoc.v:193437.3-193452.6" + wire width 64 $0\fast1$7[63:0]$13392 + attribute \src "libresoc.v:193514.3-193529.6" + wire $0\fast1_ok[0:0] + attribute \src "libresoc.v:193169.7-193169.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:193472.3-193513.6" + wire width 64 $0\o[63:0] + attribute \src "libresoc.v:193472.3-193513.6" + wire $0\o_ok[0:0] + attribute \src "libresoc.v:193662.3-193680.6" + wire width 64 $0\spr1$6[63:0]$13417 + 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"/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" + wire \$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:82" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 7 \fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 20 \fast1$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 21 \fast1_ok + attribute \src "libresoc.v:193169.7-193169.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 input 28 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" + wire width 2 output 11 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 16 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 17 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 5 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:42" + wire width 10 \spr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 6 \spr1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 output 18 \spr1$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 19 \spr1_ok + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 input 2 \spr_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_0000000000000 "NONE" + attribute \enum_value_0000000000010 "ALU" + attribute \enum_value_0000000000100 "LDST" + attribute \enum_value_0000000001000 "SHIFT_ROT" + attribute \enum_value_0000000010000 "LOGICAL" + attribute \enum_value_0000000100000 "BRANCH" + attribute \enum_value_0000001000000 "CR" + attribute \enum_value_0000010000000 "TRAP" + attribute \enum_value_0000100000000 "MUL" + attribute \enum_value_0001000000000 "DIV" + attribute \enum_value_0010000000000 "SPR" + attribute \enum_value_0100000000000 "MMU" + attribute \enum_value_1000000000000 "SV" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 output 13 \spr_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 3 \spr_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 14 \spr_op__insn$4 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \spr_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 12 \spr_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 4 \spr_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 15 \spr_op__is_32bit$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 input 10 \xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 output 26 \xer_ca$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 27 \xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 input 9 \xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 2 output 24 \xer_ov$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 25 \xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 8 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 22 \xer_so$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 23 \xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" + cell $eq $eq$libresoc.v:193430$13384 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 10 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 10'0000000001 + connect \Y $eq$libresoc.v:193430$13384_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" + cell $eq $eq$libresoc.v:193431$13385 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 10 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 10'0000000001 + connect \Y $eq$libresoc.v:193431$13385_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" + cell $eq $eq$libresoc.v:193432$13386 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 10 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 10'0000000001 + connect \Y $eq$libresoc.v:193432$13386_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" + cell $eq $eq$libresoc.v:193433$13387 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 10 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 10'0000000001 + connect \Y $eq$libresoc.v:193433$13387_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" + cell $eq $eq$libresoc.v:193434$13388 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 10 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 10'0000000001 + connect \Y $eq$libresoc.v:193434$13388_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" + cell $eq $eq$libresoc.v:193435$13389 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 10 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 10'0000000001 + connect \Y $eq$libresoc.v:193435$13389_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:82" + cell $eq $eq$libresoc.v:193436$13390 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 10 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 10'0000000001 + connect \Y $eq$libresoc.v:193436$13390_Y + end + attribute \src "libresoc.v:193169.7-193169.20" + process $proc$libresoc.v:193169$13420 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:193437.3-193452.6" + process $proc$libresoc.v:193437$13391 + assign { } { } + assign { } { } + assign $0\fast1$7[63:0]$13392 $1\fast1$7[63:0]$13393 + attribute \src "libresoc.v:193438.5-193438.29" + switch \initial + attribute \src "libresoc.v:193438.9-193438.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46" + switch \spr_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0110001 + assign { } { } + assign $1\fast1$7[63:0]$13393 $2\fast1$7[63:0]$13394 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" + switch \spr + attribute \src "libresoc.v:0.0-0.0" + case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110 + assign { } { } + assign $2\fast1$7[63:0]$13394 \ra + case + assign $2\fast1$7[63:0]$13394 64'0000000000000000000000000000000000000000000000000000000000000000 + end + case + assign $1\fast1$7[63:0]$13393 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fast1$7 $0\fast1$7[63:0]$13392 + end + attribute \src "libresoc.v:193453.3-193471.6" + process $proc$libresoc.v:193453$13395 + assign { } { } + assign { } { } + assign $0\spr1_ok[0:0] $1\spr1_ok[0:0] + attribute \src "libresoc.v:193454.5-193454.29" + switch \initial + attribute \src "libresoc.v:193454.9-193454.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46" + switch \spr_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0110001 + assign { } { } + assign $1\spr1_ok[0:0] $2\spr1_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" + switch \spr + attribute \src "libresoc.v:0.0-0.0" + case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110 + assign $2\spr1_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\spr1_ok[0:0] 1'1 + end + case + assign $1\spr1_ok[0:0] 1'0 + end + sync always + update \spr1_ok $0\spr1_ok[0:0] + end + attribute \src "libresoc.v:193472.3-193513.6" + process $proc$libresoc.v:193472$13396 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\o_ok[0:0] $1\o_ok[0:0] + assign $0\o[63:0] $1\o[63:0] + attribute \src "libresoc.v:193473.5-193473.29" + switch \initial + attribute \src "libresoc.v:193473.9-193473.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46" + switch \spr_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0101110 + assign { } { } + assign { } { } + assign $1\o_ok[0:0] 1'1 + assign $1\o[63:0] $2\o[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:77" + switch \spr + attribute \src "libresoc.v:0.0-0.0" + case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110 , 10'0100001100 + assign { } { } + assign $2\o[63:0] [17:0] \fast1 [17:0] + assign $2\o[63:0] [63:18] $3\o[63:18] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:82" + switch \$23 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\o[63:18] [45:14] 0 + assign $3\o[63:18] [10:2] 9'000000000 + assign $3\o[63:18] [13] \xer_so + assign $3\o[63:18] [12] \xer_ov [0] + assign $3\o[63:18] [1] \xer_ov [1] + assign $3\o[63:18] [11] \xer_ca [0] + assign $3\o[63:18] [0] \xer_ca [1] + case + assign $3\o[63:18] \fast1 [63:18] + end + attribute \src "libresoc.v:0.0-0.0" + case 10'0100001101 + assign $2\o[63:0] [63:32] 0 + assign $2\o[63:0] [31:0] \fast1 [63:32] + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\o[63:0] \spr1 + end + case + assign $1\o_ok[0:0] 1'0 + assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \o_ok $0\o_ok[0:0] + update \o $0\o[63:0] + end + attribute \src "libresoc.v:193514.3-193529.6" + process $proc$libresoc.v:193514$13397 + assign { } { } + assign { } { } + assign $0\fast1_ok[0:0] $1\fast1_ok[0:0] + attribute \src "libresoc.v:193515.5-193515.29" + switch \initial + attribute \src "libresoc.v:193515.9-193515.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46" + switch \spr_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0110001 + assign { } { } + assign $1\fast1_ok[0:0] $2\fast1_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" + switch \spr + attribute \src "libresoc.v:0.0-0.0" + case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110 + assign { } { } + assign $2\fast1_ok[0:0] 1'1 + case + assign $2\fast1_ok[0:0] 1'0 + end + case + assign $1\fast1_ok[0:0] 1'0 + end + sync always + update \fast1_ok $0\fast1_ok[0:0] + end + attribute \src "libresoc.v:193530.3-193550.6" + process $proc$libresoc.v:193530$13398 + assign { } { } + assign { } { } + assign $0\xer_so$8[0:0]$13399 $1\xer_so$8[0:0]$13400 + attribute \src "libresoc.v:193531.5-193531.29" + switch \initial + attribute \src "libresoc.v:193531.9-193531.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46" + switch \spr_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0110001 + assign { } { } + assign $1\xer_so$8[0:0]$13400 $2\xer_so$8[0:0]$13401 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" + switch \spr + attribute \src "libresoc.v:0.0-0.0" + case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110 + assign { } { } + assign $2\xer_so$8[0:0]$13401 $3\xer_so$8[0:0]$13402 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" + switch \$11 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\xer_so$8[0:0]$13402 \ra [31] + case + assign $3\xer_so$8[0:0]$13402 1'0 + end + case + assign $2\xer_so$8[0:0]$13401 1'0 + end + case + assign $1\xer_so$8[0:0]$13400 1'0 + end + sync always + update \xer_so$8 $0\xer_so$8[0:0]$13399 + end + attribute \src "libresoc.v:193551.3-193571.6" + process $proc$libresoc.v:193551$13403 + assign { } { } + assign { } { } + assign $0\xer_so_ok[0:0] $1\xer_so_ok[0:0] + attribute \src "libresoc.v:193552.5-193552.29" + switch \initial + attribute \src "libresoc.v:193552.9-193552.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46" + switch \spr_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0110001 + assign { } { } + assign $1\xer_so_ok[0:0] $2\xer_so_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" + switch \spr + attribute \src "libresoc.v:0.0-0.0" + case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110 + assign { } { } + assign $2\xer_so_ok[0:0] $3\xer_so_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" + switch \$13 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\xer_so_ok[0:0] 1'1 + case + assign $3\xer_so_ok[0:0] 1'0 + end + case + assign $2\xer_so_ok[0:0] 1'0 + end + case + assign $1\xer_so_ok[0:0] 1'0 + end + sync always + update \xer_so_ok $0\xer_so_ok[0:0] + end + attribute \src "libresoc.v:193572.3-193595.6" + process $proc$libresoc.v:193572$13404 + assign { } { } + assign { } { } + assign $0\xer_ov$9[1:0]$13405 $1\xer_ov$9[1:0]$13406 + attribute \src "libresoc.v:193573.5-193573.29" + switch \initial + attribute \src "libresoc.v:193573.9-193573.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46" + switch \spr_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0110001 + assign { } { } + assign $1\xer_ov$9[1:0]$13406 $2\xer_ov$9[1:0]$13407 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" + switch \spr + attribute \src "libresoc.v:0.0-0.0" + case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110 + assign { } { } + assign $2\xer_ov$9[1:0]$13407 $3\xer_ov$9[1:0]$13408 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" + switch \$15 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\xer_ov$9[1:0]$13408 [0] \ra [30] + assign $3\xer_ov$9[1:0]$13408 [1] \ra [19] + case + assign $3\xer_ov$9[1:0]$13408 2'00 + end + case + assign $2\xer_ov$9[1:0]$13407 2'00 + end + case + assign $1\xer_ov$9[1:0]$13406 2'00 + end + sync always + update \xer_ov$9 $0\xer_ov$9[1:0]$13405 + end + attribute \src "libresoc.v:193596.3-193616.6" + process $proc$libresoc.v:193596$13409 + assign { } { } + assign { } { } + assign $0\xer_ov_ok[0:0] $1\xer_ov_ok[0:0] + attribute \src "libresoc.v:193597.5-193597.29" + switch \initial + attribute \src "libresoc.v:193597.9-193597.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46" + switch \spr_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0110001 + assign { } { } + assign $1\xer_ov_ok[0:0] $2\xer_ov_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" + switch \spr + attribute \src "libresoc.v:0.0-0.0" + case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110 + assign { } { } + assign $2\xer_ov_ok[0:0] $3\xer_ov_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" + switch \$17 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\xer_ov_ok[0:0] 1'1 + case + assign $3\xer_ov_ok[0:0] 1'0 + end + case + assign $2\xer_ov_ok[0:0] 1'0 + end + case + assign $1\xer_ov_ok[0:0] 1'0 + end + sync always + update \xer_ov_ok $0\xer_ov_ok[0:0] + end + attribute \src "libresoc.v:193617.3-193640.6" + process $proc$libresoc.v:193617$13410 + assign { } { } + assign { } { } + assign $0\xer_ca$10[1:0]$13411 $1\xer_ca$10[1:0]$13412 + attribute \src "libresoc.v:193618.5-193618.29" + switch \initial + attribute \src "libresoc.v:193618.9-193618.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46" + switch \spr_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0110001 + assign { } { } + assign $1\xer_ca$10[1:0]$13412 $2\xer_ca$10[1:0]$13413 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" + switch \spr + attribute \src "libresoc.v:0.0-0.0" + case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110 + assign { } { } + assign $2\xer_ca$10[1:0]$13413 $3\xer_ca$10[1:0]$13414 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" + switch \$19 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\xer_ca$10[1:0]$13414 [0] \ra [29] + assign $3\xer_ca$10[1:0]$13414 [1] \ra [18] + case + assign $3\xer_ca$10[1:0]$13414 2'00 + end + case + assign $2\xer_ca$10[1:0]$13413 2'00 + end + case + assign $1\xer_ca$10[1:0]$13412 2'00 + end + sync always + update \xer_ca$10 $0\xer_ca$10[1:0]$13411 + end + attribute \src "libresoc.v:193641.3-193661.6" + process $proc$libresoc.v:193641$13415 + assign { } { } + assign { } { } + assign $0\xer_ca_ok[0:0] $1\xer_ca_ok[0:0] + attribute \src "libresoc.v:193642.5-193642.29" + switch \initial + attribute \src "libresoc.v:193642.9-193642.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46" + switch \spr_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0110001 + assign { } { } + assign $1\xer_ca_ok[0:0] $2\xer_ca_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" + switch \spr + attribute \src "libresoc.v:0.0-0.0" + case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110 + assign { } { } + assign $2\xer_ca_ok[0:0] $3\xer_ca_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" + switch \$21 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\xer_ca_ok[0:0] 1'1 + case + assign $3\xer_ca_ok[0:0] 1'0 + end + case + assign $2\xer_ca_ok[0:0] 1'0 + end + case + assign $1\xer_ca_ok[0:0] 1'0 + end + sync always + update \xer_ca_ok $0\xer_ca_ok[0:0] + end + attribute \src "libresoc.v:193662.3-193680.6" + process $proc$libresoc.v:193662$13416 + assign { } { } + assign { } { } + assign $0\spr1$6[63:0]$13417 $1\spr1$6[63:0]$13418 + attribute \src "libresoc.v:193663.5-193663.29" + switch \initial + attribute \src "libresoc.v:193663.9-193663.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46" + switch \spr_op__insn_type + attribute \src "libresoc.v:0.0-0.0" + case 7'0110001 + assign { } { } + assign $1\spr1$6[63:0]$13418 $2\spr1$6[63:0]$13419 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" + switch \spr + attribute \src "libresoc.v:0.0-0.0" + case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110 + assign $2\spr1$6[63:0]$13419 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\spr1$6[63:0]$13419 \ra + end + case + assign $1\spr1$6[63:0]$13418 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \spr1$6 $0\spr1$6[63:0]$13417 + end + connect \$11 $eq$libresoc.v:193430$13384_Y + connect \$13 $eq$libresoc.v:193431$13385_Y + connect \$15 $eq$libresoc.v:193432$13386_Y + connect \$17 $eq$libresoc.v:193433$13387_Y + connect \$19 $eq$libresoc.v:193434$13388_Y + connect \$21 $eq$libresoc.v:193435$13389_Y + connect \$23 $eq$libresoc.v:193436$13390_Y + connect { \spr_op__is_32bit$5 \spr_op__insn$4 \spr_op__fn_unit$3 \spr_op__insn_type$2 } { \spr_op__is_32bit \spr_op__insn \spr_op__fn_unit \spr_op__insn_type } + connect \muxid$1 \muxid + connect \spr { \spr_op__insn [15:11] \spr_op__insn [20:16] } +end +attribute \src "libresoc.v:193688.1-194517.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_a.sprmap" +attribute \generator "nMigen" +module \sprmap + attribute \src "libresoc.v:193817.3-193847.6" + wire width 3 $0\fast_o[2:0] + attribute \src "libresoc.v:193848.3-193878.6" + wire $0\fast_o_ok[0:0] + attribute \src "libresoc.v:193689.7-193689.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:193879.3-194197.6" + wire width 10 $0\spr_o[9:0] + attribute \src "libresoc.v:194198.3-194516.6" + wire $0\spr_o_ok[0:0] + attribute \src "libresoc.v:193817.3-193847.6" + wire width 3 $1\fast_o[2:0] + attribute \src "libresoc.v:193848.3-193878.6" + wire $1\fast_o_ok[0:0] + attribute \src "libresoc.v:193879.3-194197.6" + wire width 10 $1\spr_o[9:0] + attribute \src "libresoc.v:194198.3-194516.6" + wire $1\spr_o_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 output 3 \fast_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 4 \fast_o_ok + attribute \src "libresoc.v:193689.7-193689.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + wire width 10 input 5 \spr_i + attribute \enum_base_type "SPR" + attribute \enum_value_0000000001 "XER" + attribute \enum_value_0000000011 "DSCR" + attribute \enum_value_0000001000 "LR" + attribute \enum_value_0000001001 "CTR" + attribute \enum_value_0000001101 "AMR" + attribute \enum_value_0000010001 "DSCR_priv" + attribute \enum_value_0000010010 "DSISR" + attribute \enum_value_0000010011 "DAR" + attribute \enum_value_0000010110 "DEC" + attribute \enum_value_0000011010 "SRR0" + attribute \enum_value_0000011011 "SRR1" + attribute \enum_value_0000011100 "CFAR" + attribute \enum_value_0000011101 "AMR_priv" + attribute \enum_value_0000110000 "PIDR" + attribute \enum_value_0000111101 "IAMR" + attribute \enum_value_0010000000 "TFHAR" + attribute \enum_value_0010000001 "TFIAR" + attribute \enum_value_0010000010 "TEXASR" + attribute \enum_value_0010000011 "TEXASRU" + attribute \enum_value_0010001000 "CTRL" + attribute \enum_value_0010010000 "TIDR" + attribute \enum_value_0010011000 "CTRL_priv" + attribute \enum_value_0010011001 "FSCR" + attribute \enum_value_0010011101 "UAMOR" + attribute \enum_value_0010011110 "GSR" + attribute \enum_value_0010011111 "PSPB" + attribute \enum_value_0010110000 "DPDES" + attribute \enum_value_0010110100 "DAWR0" + attribute \enum_value_0010111010 "RPR" + attribute \enum_value_0010111011 "CIABR" + attribute \enum_value_0010111100 "DAWRX0" + attribute \enum_value_0010111110 "HFSCR" + attribute \enum_value_0100000000 "VRSAVE" + attribute \enum_value_0100000011 "SPRG3" + attribute \enum_value_0100001100 "TB" + attribute \enum_value_0100001101 "TBU" + attribute \enum_value_0100010000 "SPRG0_priv" + attribute \enum_value_0100010001 "SPRG1_priv" + attribute \enum_value_0100010010 "SPRG2_priv" + attribute \enum_value_0100010011 "SPRG3_priv" + attribute \enum_value_0100011011 "CIR" + attribute \enum_value_0100011100 "TBL" + attribute \enum_value_0100011101 "TBU_hypv" + attribute \enum_value_0100011110 "TBU40" + attribute \enum_value_0100011111 "PVR" + attribute \enum_value_0100110000 "HSPRG0" + attribute \enum_value_0100110001 "HSPRG1" + attribute \enum_value_0100110010 "HDSISR" + attribute \enum_value_0100110011 "HDAR" + attribute \enum_value_0100110100 "SPURR" + attribute \enum_value_0100110101 "PURR" + attribute \enum_value_0100110110 "HDEC" + attribute \enum_value_0100111001 "HRMOR" + attribute \enum_value_0100111010 "HSRR0" + attribute \enum_value_0100111011 "HSRR1" + attribute \enum_value_0100111110 "LPCR" + attribute \enum_value_0100111111 "LPIDR" + attribute \enum_value_0101010000 "HMER" + attribute \enum_value_0101010001 "HMEER" + attribute \enum_value_0101010010 "PCR" + attribute \enum_value_0101010011 "HEIR" + attribute \enum_value_0101011101 "AMOR" + attribute \enum_value_0110111110 "TIR" + attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1011000000 "SVSTATE" + attribute \enum_value_1011010000 "SVSRR0" + attribute \enum_value_1100000000 "SIER" + attribute \enum_value_1100000001 "MMCR2" + attribute \enum_value_1100000010 "MMCRA" + attribute \enum_value_1100000011 "PMC1" + attribute \enum_value_1100000100 "PMC2" + attribute \enum_value_1100000101 "PMC3" + attribute \enum_value_1100000110 "PMC4" + attribute \enum_value_1100000111 "PMC5" + attribute \enum_value_1100001000 "PMC6" + attribute \enum_value_1100001011 "MMCR0" + attribute \enum_value_1100001100 "SIAR" + attribute \enum_value_1100001101 "SDAR" + attribute \enum_value_1100001110 "MMCR1" + attribute \enum_value_1100010000 "SIER_priv" + attribute \enum_value_1100010001 "MMCR2_priv" + attribute \enum_value_1100010010 "MMCRA_priv" + attribute \enum_value_1100010011 "PMC1_priv" + attribute \enum_value_1100010100 "PMC2_priv" + attribute \enum_value_1100010101 "PMC3_priv" + attribute \enum_value_1100010110 "PMC4_priv" + attribute \enum_value_1100010111 "PMC5_priv" + attribute \enum_value_1100011000 "PMC6_priv" + attribute \enum_value_1100011011 "MMCR0_priv" + attribute \enum_value_1100011100 "SIAR_priv" + attribute \enum_value_1100011101 "SDAR_priv" + attribute \enum_value_1100011110 "MMCR1_priv" + attribute \enum_value_1100100000 "BESCRS" + attribute \enum_value_1100100001 "BESCRSU" + attribute \enum_value_1100100010 "BESCRR" + attribute \enum_value_1100100011 "BESCRRU" + attribute \enum_value_1100100100 "EBBHR" + attribute \enum_value_1100100101 "EBBRR" + attribute \enum_value_1100100110 "BESCR" + attribute \enum_value_1100101000 "reserved808" + attribute \enum_value_1100101001 "reserved809" + attribute \enum_value_1100101010 "reserved810" + attribute \enum_value_1100101011 "reserved811" + attribute \enum_value_1100101111 "TAR" + attribute \enum_value_1100110000 "ASDR" + attribute \enum_value_1100110111 "PSSCR" + attribute \enum_value_1101010000 "IC" + attribute \enum_value_1101010001 "VTB" + attribute \enum_value_1101010111 "PSSCR_hypv" + attribute \enum_value_1110000000 "PPR" + attribute \enum_value_1110000010 "PPR32" + attribute \enum_value_1111111111 "PIR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 10 output 1 \spr_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 2 \spr_o_ok + attribute \src "libresoc.v:193689.7-193689.20" + process $proc$libresoc.v:193689$13425 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:193817.3-193847.6" + process $proc$libresoc.v:193817$13421 + assign { } { } + assign { } { } + assign $0\fast_o[2:0] $1\fast_o[2:0] + attribute \src "libresoc.v:193818.5-193818.29" + switch \initial + attribute \src "libresoc.v:193818.9-193818.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:69" + switch \spr_i + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000001 + assign { } { } + assign $1\fast_o[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000001000 + assign { } { } + assign $1\fast_o[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000001001 + assign { } { } + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010110 + assign { } { } + assign $1\fast_o[2:0] 3'110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011010 + assign { } { } + assign $1\fast_o[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011011 + assign { } { } + assign $1\fast_o[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100001100 + assign { } { } + assign $1\fast_o[2:0] 3'111 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101111 + assign { } { } + assign $1\fast_o[2:0] 3'010 + case + assign $1\fast_o[2:0] 3'000 + end + sync always + update \fast_o $0\fast_o[2:0] + end + attribute \src "libresoc.v:193848.3-193878.6" + process $proc$libresoc.v:193848$13422 + assign { } { } + assign { } { } + assign $0\fast_o_ok[0:0] $1\fast_o_ok[0:0] + attribute \src "libresoc.v:193849.5-193849.29" + switch \initial + attribute \src "libresoc.v:193849.9-193849.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:69" + switch \spr_i + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000001 + assign { } { } + assign $1\fast_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000001000 + assign { } { } + assign $1\fast_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000001001 + assign { } { } + assign $1\fast_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010110 + assign { } { } + assign $1\fast_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011010 + assign { } { } + assign $1\fast_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011011 + assign { } { } + assign $1\fast_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100001100 + assign { } { } + assign $1\fast_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101111 + assign { } { } + assign $1\fast_o_ok[0:0] 1'1 + case + assign $1\fast_o_ok[0:0] 1'0 + end + sync always + update \fast_o_ok $0\fast_o_ok[0:0] + end + attribute \src "libresoc.v:193879.3-194197.6" + process $proc$libresoc.v:193879$13423 + assign { } { } + assign { } { } + assign $0\spr_o[9:0] $1\spr_o[9:0] + attribute \src "libresoc.v:193880.5-193880.29" + switch \initial + attribute \src "libresoc.v:193880.9-193880.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:69" + switch \spr_i + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000011 + assign { } { } + assign $1\spr_o[9:0] 10'0000000001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000001101 + assign { } { } + assign $1\spr_o[9:0] 10'0000000100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010001 + assign { } { } + assign $1\spr_o[9:0] 10'0000000101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\spr_o[9:0] 10'0000000110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010011 + assign { } { } + assign $1\spr_o[9:0] 10'0000000111 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011100 + assign { } { } + assign $1\spr_o[9:0] 10'0000001011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011101 + assign { } { } + assign $1\spr_o[9:0] 10'0000001100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000110000 + assign { } { } + assign $1\spr_o[9:0] 10'0000001101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000111101 + assign { } { } + assign $1\spr_o[9:0] 10'0000001110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000000 + assign { } { } + assign $1\spr_o[9:0] 10'0000001111 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\spr_o[9:0] 10'0000010000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000010 + assign { } { } + assign $1\spr_o[9:0] 10'0000010001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000011 + assign { } { } + assign $1\spr_o[9:0] 10'0000010010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010001000 + assign { } { } + assign $1\spr_o[9:0] 10'0000010011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010000 + assign { } { } + assign $1\spr_o[9:0] 10'0000010100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011000 + assign { } { } + assign $1\spr_o[9:0] 10'0000010101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011001 + assign { } { } + assign $1\spr_o[9:0] 10'0000010110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011101 + assign { } { } + assign $1\spr_o[9:0] 10'0000010111 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011110 + assign { } { } + assign $1\spr_o[9:0] 10'0000011000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011111 + assign { } { } + assign $1\spr_o[9:0] 10'0000011001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010110000 + assign { } { } + assign $1\spr_o[9:0] 10'0000011010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010110100 + assign { } { } + assign $1\spr_o[9:0] 10'0000011011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111010 + assign { } { } + assign $1\spr_o[9:0] 10'0000011100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111011 + assign { } { } + assign $1\spr_o[9:0] 10'0000011101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111100 + assign { } { } + assign $1\spr_o[9:0] 10'0000011110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111110 + assign { } { } + assign $1\spr_o[9:0] 10'0000011111 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000000 + assign { } { } + assign $1\spr_o[9:0] 10'0000100000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000011 + assign { } { } + assign $1\spr_o[9:0] 10'0000100001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100001101 + assign { } { } + assign $1\spr_o[9:0] 10'0000100011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010000 + assign { } { } + assign $1\spr_o[9:0] 10'0000100100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010001 + assign { } { } + assign $1\spr_o[9:0] 10'0000100101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\spr_o[9:0] 10'0000100110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010011 + assign { } { } + assign $1\spr_o[9:0] 10'0000100111 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011011 + assign { } { } + assign $1\spr_o[9:0] 10'0000101000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011100 + assign { } { } + assign $1\spr_o[9:0] 10'0000101001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011101 + assign { } { } + assign $1\spr_o[9:0] 10'0000101010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011110 + assign { } { } + assign $1\spr_o[9:0] 10'0000101011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011111 + assign { } { } + assign $1\spr_o[9:0] 10'0000101100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110000 + assign { } { } + assign $1\spr_o[9:0] 10'0000101101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110001 + assign { } { } + assign $1\spr_o[9:0] 10'0000101110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110010 + assign { } { } + assign $1\spr_o[9:0] 10'0000101111 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110011 + assign { } { } + assign $1\spr_o[9:0] 10'0000110000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110100 + assign { } { } + assign $1\spr_o[9:0] 10'0000110001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110101 + assign { } { } + assign $1\spr_o[9:0] 10'0000110010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110110 + assign { } { } + assign $1\spr_o[9:0] 10'0000110011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111001 + assign { } { } + assign $1\spr_o[9:0] 10'0000110100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111010 + assign { } { } + assign $1\spr_o[9:0] 10'0000110101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111011 + assign { } { } + assign $1\spr_o[9:0] 10'0000110110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111110 + assign { } { } + assign $1\spr_o[9:0] 10'0000110111 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111111 + assign { } { } + assign $1\spr_o[9:0] 10'0000111000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010000 + assign { } { } + assign $1\spr_o[9:0] 10'0000111001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010001 + assign { } { } + assign $1\spr_o[9:0] 10'0000111010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010010 + assign { } { } + assign $1\spr_o[9:0] 10'0000111011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010011 + assign { } { } + assign $1\spr_o[9:0] 10'0000111100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101011101 + assign { } { } + assign $1\spr_o[9:0] 10'0000111101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110111110 + assign { } { } + assign $1\spr_o[9:0] 10'0000111110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111010000 + assign { } { } + assign $1\spr_o[9:0] 10'0000111111 + attribute \src "libresoc.v:0.0-0.0" + case 10'1011000000 + assign { } { } + assign $1\spr_o[9:0] 10'0001000000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1011010000 + assign { } { } + assign $1\spr_o[9:0] 10'0001000001 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000000 + assign { } { } + assign $1\spr_o[9:0] 10'0001000010 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000001 + assign { } { } + assign $1\spr_o[9:0] 10'0001000011 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000010 + assign { } { } + assign $1\spr_o[9:0] 10'0001000100 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000011 + assign { } { } + assign $1\spr_o[9:0] 10'0001000101 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000100 + assign { } { } + assign $1\spr_o[9:0] 10'0001000110 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000101 + assign { } { } + assign $1\spr_o[9:0] 10'0001000111 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000110 + assign { } { } + assign $1\spr_o[9:0] 10'0001001000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000111 + assign { } { } + assign $1\spr_o[9:0] 10'0001001001 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001000 + assign { } { } + assign $1\spr_o[9:0] 10'0001001010 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001011 + assign { } { } + assign $1\spr_o[9:0] 10'0001001011 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001100 + assign { } { } + assign $1\spr_o[9:0] 10'0001001100 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001101 + assign { } { } + assign $1\spr_o[9:0] 10'0001001101 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001110 + assign { } { } + assign $1\spr_o[9:0] 10'0001001110 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010000 + assign { } { } + assign $1\spr_o[9:0] 10'0001001111 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010001 + assign { } { } + assign $1\spr_o[9:0] 10'0001010000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010010 + assign { } { } + assign $1\spr_o[9:0] 10'0001010001 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010011 + assign { } { } + assign $1\spr_o[9:0] 10'0001010010 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010100 + assign { } { } + assign $1\spr_o[9:0] 10'0001010011 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010101 + assign { } { } + assign $1\spr_o[9:0] 10'0001010100 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010110 + assign { } { } + assign $1\spr_o[9:0] 10'0001010101 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010111 + assign { } { } + assign $1\spr_o[9:0] 10'0001010110 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011000 + assign { } { } + assign $1\spr_o[9:0] 10'0001010111 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011011 + assign { } { } + assign $1\spr_o[9:0] 10'0001011000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011100 + assign { } { } + assign $1\spr_o[9:0] 10'0001011001 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011101 + assign { } { } + assign $1\spr_o[9:0] 10'0001011010 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011110 + assign { } { } + assign $1\spr_o[9:0] 10'0001011011 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100000 + assign { } { } + assign $1\spr_o[9:0] 10'0001011100 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100001 + assign { } { } + assign $1\spr_o[9:0] 10'0001011101 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100010 + assign { } { } + assign $1\spr_o[9:0] 10'0001011110 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100011 + assign { } { } + assign $1\spr_o[9:0] 10'0001011111 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100100 + assign { } { } + assign $1\spr_o[9:0] 10'0001100000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100101 + assign { } { } + assign $1\spr_o[9:0] 10'0001100001 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100110 + assign { } { } + assign $1\spr_o[9:0] 10'0001100010 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101000 + assign { } { } + assign $1\spr_o[9:0] 10'0001100011 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101001 + assign { } { } + assign $1\spr_o[9:0] 10'0001100100 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101010 + assign { } { } + assign $1\spr_o[9:0] 10'0001100101 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101011 + assign { } { } + assign $1\spr_o[9:0] 10'0001100110 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100110000 + assign { } { } + assign $1\spr_o[9:0] 10'0001101000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100110111 + assign { } { } + assign $1\spr_o[9:0] 10'0001101001 + attribute \src "libresoc.v:0.0-0.0" + case 10'1101010000 + assign { } { } + assign $1\spr_o[9:0] 10'0001101010 + attribute \src "libresoc.v:0.0-0.0" + case 10'1101010001 + assign { } { } + assign $1\spr_o[9:0] 10'0001101011 + attribute \src "libresoc.v:0.0-0.0" + case 10'1101010111 + assign { } { } + assign $1\spr_o[9:0] 10'0001101100 + attribute \src "libresoc.v:0.0-0.0" + case 10'1110000000 + assign { } { } + assign $1\spr_o[9:0] 10'0001101101 + attribute \src "libresoc.v:0.0-0.0" + case 10'1110000010 + assign { } { } + assign $1\spr_o[9:0] 10'0001101110 + attribute \src "libresoc.v:0.0-0.0" + case 10'1111111111 + assign { } { } + assign $1\spr_o[9:0] 10'0001101111 + case + assign $1\spr_o[9:0] 10'0000000000 + end + sync always + update \spr_o $0\spr_o[9:0] + end + attribute \src "libresoc.v:194198.3-194516.6" + process $proc$libresoc.v:194198$13424 + assign { } { } + assign { } { } + assign $0\spr_o_ok[0:0] $1\spr_o_ok[0:0] + attribute \src "libresoc.v:194199.5-194199.29" + switch \initial + attribute \src "libresoc.v:194199.9-194199.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:69" + switch \spr_i + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000001101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000110000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000111101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010001000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011111 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010110000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010110100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100001101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011111 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111111 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101011101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110111110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111010000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1011000000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1011010000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000111 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010111 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100110000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100110111 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1101010000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1101010001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1101010111 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1110000000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1110000010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1111111111 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + case + assign $1\spr_o_ok[0:0] 1'0 + end + sync always + update \spr_o_ok $0\spr_o_ok[0:0] + end +end +attribute \src "libresoc.v:194521.1-195350.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_o.sprmap" +attribute \generator "nMigen" +module \sprmap$211 + attribute \src "libresoc.v:194650.3-194680.6" + wire width 3 $0\fast_o[2:0] + attribute \src "libresoc.v:194681.3-194711.6" + wire $0\fast_o_ok[0:0] + attribute \src "libresoc.v:194522.7-194522.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:194712.3-195030.6" + wire width 10 $0\spr_o[9:0] + attribute \src "libresoc.v:195031.3-195349.6" + wire $0\spr_o_ok[0:0] + attribute \src "libresoc.v:194650.3-194680.6" + wire width 3 $1\fast_o[2:0] + attribute \src "libresoc.v:194681.3-194711.6" + wire $1\fast_o_ok[0:0] + attribute \src "libresoc.v:194712.3-195030.6" + wire width 10 $1\spr_o[9:0] + attribute \src "libresoc.v:195031.3-195349.6" + wire $1\spr_o_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 3 output 3 \fast_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 4 \fast_o_ok + attribute \src "libresoc.v:194522.7-194522.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63" + wire width 10 input 5 \spr_i + attribute \enum_base_type "SPR" + attribute \enum_value_0000000001 "XER" + attribute \enum_value_0000000011 "DSCR" + attribute \enum_value_0000001000 "LR" + attribute \enum_value_0000001001 "CTR" + attribute \enum_value_0000001101 "AMR" + attribute \enum_value_0000010001 "DSCR_priv" + attribute \enum_value_0000010010 "DSISR" + attribute \enum_value_0000010011 "DAR" + attribute \enum_value_0000010110 "DEC" + attribute \enum_value_0000011010 "SRR0" + attribute \enum_value_0000011011 "SRR1" + attribute \enum_value_0000011100 "CFAR" + attribute \enum_value_0000011101 "AMR_priv" + attribute \enum_value_0000110000 "PIDR" + attribute \enum_value_0000111101 "IAMR" + attribute \enum_value_0010000000 "TFHAR" + attribute \enum_value_0010000001 "TFIAR" + attribute \enum_value_0010000010 "TEXASR" + attribute \enum_value_0010000011 "TEXASRU" + attribute \enum_value_0010001000 "CTRL" + attribute \enum_value_0010010000 "TIDR" + attribute \enum_value_0010011000 "CTRL_priv" + attribute \enum_value_0010011001 "FSCR" + attribute \enum_value_0010011101 "UAMOR" + attribute \enum_value_0010011110 "GSR" + attribute \enum_value_0010011111 "PSPB" + attribute \enum_value_0010110000 "DPDES" + attribute \enum_value_0010110100 "DAWR0" + attribute \enum_value_0010111010 "RPR" + attribute \enum_value_0010111011 "CIABR" + attribute \enum_value_0010111100 "DAWRX0" + attribute \enum_value_0010111110 "HFSCR" + attribute \enum_value_0100000000 "VRSAVE" + attribute \enum_value_0100000011 "SPRG3" + attribute \enum_value_0100001100 "TB" + attribute \enum_value_0100001101 "TBU" + attribute \enum_value_0100010000 "SPRG0_priv" + attribute \enum_value_0100010001 "SPRG1_priv" + attribute \enum_value_0100010010 "SPRG2_priv" + attribute \enum_value_0100010011 "SPRG3_priv" + attribute \enum_value_0100011011 "CIR" + attribute \enum_value_0100011100 "TBL" + attribute \enum_value_0100011101 "TBU_hypv" + attribute \enum_value_0100011110 "TBU40" + attribute \enum_value_0100011111 "PVR" + attribute \enum_value_0100110000 "HSPRG0" + attribute \enum_value_0100110001 "HSPRG1" + attribute \enum_value_0100110010 "HDSISR" + attribute \enum_value_0100110011 "HDAR" + attribute \enum_value_0100110100 "SPURR" + attribute \enum_value_0100110101 "PURR" + attribute \enum_value_0100110110 "HDEC" + attribute \enum_value_0100111001 "HRMOR" + attribute \enum_value_0100111010 "HSRR0" + attribute \enum_value_0100111011 "HSRR1" + attribute \enum_value_0100111110 "LPCR" + attribute \enum_value_0100111111 "LPIDR" + attribute \enum_value_0101010000 "HMER" + attribute \enum_value_0101010001 "HMEER" + attribute \enum_value_0101010010 "PCR" + attribute \enum_value_0101010011 "HEIR" + attribute \enum_value_0101011101 "AMOR" + attribute \enum_value_0110111110 "TIR" + attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1011000000 "SVSTATE" + attribute \enum_value_1011010000 "SVSRR0" + attribute \enum_value_1100000000 "SIER" + attribute \enum_value_1100000001 "MMCR2" + attribute \enum_value_1100000010 "MMCRA" + attribute \enum_value_1100000011 "PMC1" + attribute \enum_value_1100000100 "PMC2" + attribute \enum_value_1100000101 "PMC3" + attribute \enum_value_1100000110 "PMC4" + attribute \enum_value_1100000111 "PMC5" + attribute \enum_value_1100001000 "PMC6" + attribute \enum_value_1100001011 "MMCR0" + attribute \enum_value_1100001100 "SIAR" + attribute \enum_value_1100001101 "SDAR" + attribute \enum_value_1100001110 "MMCR1" + attribute \enum_value_1100010000 "SIER_priv" + attribute \enum_value_1100010001 "MMCR2_priv" + attribute \enum_value_1100010010 "MMCRA_priv" + attribute \enum_value_1100010011 "PMC1_priv" + attribute \enum_value_1100010100 "PMC2_priv" + attribute \enum_value_1100010101 "PMC3_priv" + attribute \enum_value_1100010110 "PMC4_priv" + attribute \enum_value_1100010111 "PMC5_priv" + attribute \enum_value_1100011000 "PMC6_priv" + attribute \enum_value_1100011011 "MMCR0_priv" + attribute \enum_value_1100011100 "SIAR_priv" + attribute \enum_value_1100011101 "SDAR_priv" + attribute \enum_value_1100011110 "MMCR1_priv" + attribute \enum_value_1100100000 "BESCRS" + attribute \enum_value_1100100001 "BESCRSU" + attribute \enum_value_1100100010 "BESCRR" + attribute \enum_value_1100100011 "BESCRRU" + attribute \enum_value_1100100100 "EBBHR" + attribute \enum_value_1100100101 "EBBRR" + attribute \enum_value_1100100110 "BESCR" + attribute \enum_value_1100101000 "reserved808" + attribute \enum_value_1100101001 "reserved809" + attribute \enum_value_1100101010 "reserved810" + attribute \enum_value_1100101011 "reserved811" + attribute \enum_value_1100101111 "TAR" + attribute \enum_value_1100110000 "ASDR" + attribute \enum_value_1100110111 "PSSCR" + attribute \enum_value_1101010000 "IC" + attribute \enum_value_1101010001 "VTB" + attribute \enum_value_1101010111 "PSSCR_hypv" + attribute \enum_value_1110000000 "PPR" + attribute \enum_value_1110000010 "PPR32" + attribute \enum_value_1111111111 "PIR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 10 output 1 \spr_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire output 2 \spr_o_ok + attribute \src "libresoc.v:194522.7-194522.20" + process $proc$libresoc.v:194522$13430 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:194650.3-194680.6" + process $proc$libresoc.v:194650$13426 + assign { } { } + assign { } { } + assign $0\fast_o[2:0] $1\fast_o[2:0] + attribute \src "libresoc.v:194651.5-194651.29" + switch \initial + attribute \src "libresoc.v:194651.9-194651.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:69" + switch \spr_i + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000001 + assign { } { } + assign $1\fast_o[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000001000 + assign { } { } + assign $1\fast_o[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000001001 + assign { } { } + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010110 + assign { } { } + assign $1\fast_o[2:0] 3'110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011010 + assign { } { } + assign $1\fast_o[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011011 + assign { } { } + assign $1\fast_o[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100001100 + assign { } { } + assign $1\fast_o[2:0] 3'111 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101111 + assign { } { } + assign $1\fast_o[2:0] 3'010 + case + assign $1\fast_o[2:0] 3'000 + end + sync always + update \fast_o $0\fast_o[2:0] + end + attribute \src "libresoc.v:194681.3-194711.6" + process $proc$libresoc.v:194681$13427 + assign { } { } + assign { } { } + assign $0\fast_o_ok[0:0] $1\fast_o_ok[0:0] + attribute \src "libresoc.v:194682.5-194682.29" + switch \initial + attribute \src "libresoc.v:194682.9-194682.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:69" + switch \spr_i + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000001 + assign { } { } + assign $1\fast_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000001000 + assign { } { } + assign $1\fast_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000001001 + assign { } { } + assign $1\fast_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010110 + assign { } { } + assign $1\fast_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011010 + assign { } { } + assign $1\fast_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011011 + assign { } { } + assign $1\fast_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100001100 + assign { } { } + assign $1\fast_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101111 + assign { } { } + assign $1\fast_o_ok[0:0] 1'1 + case + assign $1\fast_o_ok[0:0] 1'0 + end + sync always + update \fast_o_ok $0\fast_o_ok[0:0] + end + attribute \src "libresoc.v:194712.3-195030.6" + process $proc$libresoc.v:194712$13428 + assign { } { } + assign { } { } + assign $0\spr_o[9:0] $1\spr_o[9:0] + attribute \src "libresoc.v:194713.5-194713.29" + switch \initial + attribute \src "libresoc.v:194713.9-194713.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:69" + switch \spr_i + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000011 + assign { } { } + assign $1\spr_o[9:0] 10'0000000001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000001101 + assign { } { } + assign $1\spr_o[9:0] 10'0000000100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010001 + assign { } { } + assign $1\spr_o[9:0] 10'0000000101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\spr_o[9:0] 10'0000000110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010011 + assign { } { } + assign $1\spr_o[9:0] 10'0000000111 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011100 + assign { } { } + assign $1\spr_o[9:0] 10'0000001011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011101 + assign { } { } + assign $1\spr_o[9:0] 10'0000001100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000110000 + assign { } { } + assign $1\spr_o[9:0] 10'0000001101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000111101 + assign { } { } + assign $1\spr_o[9:0] 10'0000001110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000000 + assign { } { } + assign $1\spr_o[9:0] 10'0000001111 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\spr_o[9:0] 10'0000010000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000010 + assign { } { } + assign $1\spr_o[9:0] 10'0000010001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000011 + assign { } { } + assign $1\spr_o[9:0] 10'0000010010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010001000 + assign { } { } + assign $1\spr_o[9:0] 10'0000010011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010000 + assign { } { } + assign $1\spr_o[9:0] 10'0000010100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011000 + assign { } { } + assign $1\spr_o[9:0] 10'0000010101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011001 + assign { } { } + assign $1\spr_o[9:0] 10'0000010110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011101 + assign { } { } + assign $1\spr_o[9:0] 10'0000010111 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011110 + assign { } { } + assign $1\spr_o[9:0] 10'0000011000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011111 + assign { } { } + assign $1\spr_o[9:0] 10'0000011001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010110000 + assign { } { } + assign $1\spr_o[9:0] 10'0000011010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010110100 + assign { } { } + assign $1\spr_o[9:0] 10'0000011011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111010 + assign { } { } + assign $1\spr_o[9:0] 10'0000011100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111011 + assign { } { } + assign $1\spr_o[9:0] 10'0000011101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111100 + assign { } { } + assign $1\spr_o[9:0] 10'0000011110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111110 + assign { } { } + assign $1\spr_o[9:0] 10'0000011111 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000000 + assign { } { } + assign $1\spr_o[9:0] 10'0000100000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000011 + assign { } { } + assign $1\spr_o[9:0] 10'0000100001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100001101 + assign { } { } + assign $1\spr_o[9:0] 10'0000100011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010000 + assign { } { } + assign $1\spr_o[9:0] 10'0000100100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010001 + assign { } { } + assign $1\spr_o[9:0] 10'0000100101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\spr_o[9:0] 10'0000100110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010011 + assign { } { } + assign $1\spr_o[9:0] 10'0000100111 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011011 + assign { } { } + assign $1\spr_o[9:0] 10'0000101000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011100 + assign { } { } + assign $1\spr_o[9:0] 10'0000101001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011101 + assign { } { } + assign $1\spr_o[9:0] 10'0000101010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011110 + assign { } { } + assign $1\spr_o[9:0] 10'0000101011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011111 + assign { } { } + assign $1\spr_o[9:0] 10'0000101100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110000 + assign { } { } + assign $1\spr_o[9:0] 10'0000101101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110001 + assign { } { } + assign $1\spr_o[9:0] 10'0000101110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110010 + assign { } { } + assign $1\spr_o[9:0] 10'0000101111 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110011 + assign { } { } + assign $1\spr_o[9:0] 10'0000110000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110100 + assign { } { } + assign $1\spr_o[9:0] 10'0000110001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110101 + assign { } { } + assign $1\spr_o[9:0] 10'0000110010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110110 + assign { } { } + assign $1\spr_o[9:0] 10'0000110011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111001 + assign { } { } + assign $1\spr_o[9:0] 10'0000110100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111010 + assign { } { } + assign $1\spr_o[9:0] 10'0000110101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111011 + assign { } { } + assign $1\spr_o[9:0] 10'0000110110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111110 + assign { } { } + assign $1\spr_o[9:0] 10'0000110111 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111111 + assign { } { } + assign $1\spr_o[9:0] 10'0000111000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010000 + assign { } { } + assign $1\spr_o[9:0] 10'0000111001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010001 + assign { } { } + assign $1\spr_o[9:0] 10'0000111010 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010010 + assign { } { } + assign $1\spr_o[9:0] 10'0000111011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010011 + assign { } { } + assign $1\spr_o[9:0] 10'0000111100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101011101 + assign { } { } + assign $1\spr_o[9:0] 10'0000111101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110111110 + assign { } { } + assign $1\spr_o[9:0] 10'0000111110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111010000 + assign { } { } + assign $1\spr_o[9:0] 10'0000111111 + attribute \src "libresoc.v:0.0-0.0" + case 10'1011000000 + assign { } { } + assign $1\spr_o[9:0] 10'0001000000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1011010000 + assign { } { } + assign $1\spr_o[9:0] 10'0001000001 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000000 + assign { } { } + assign $1\spr_o[9:0] 10'0001000010 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000001 + assign { } { } + assign $1\spr_o[9:0] 10'0001000011 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000010 + assign { } { } + assign $1\spr_o[9:0] 10'0001000100 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000011 + assign { } { } + assign $1\spr_o[9:0] 10'0001000101 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000100 + assign { } { } + assign $1\spr_o[9:0] 10'0001000110 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000101 + assign { } { } + assign $1\spr_o[9:0] 10'0001000111 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000110 + assign { } { } + assign $1\spr_o[9:0] 10'0001001000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000111 + assign { } { } + assign $1\spr_o[9:0] 10'0001001001 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001000 + assign { } { } + assign $1\spr_o[9:0] 10'0001001010 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001011 + assign { } { } + assign $1\spr_o[9:0] 10'0001001011 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001100 + assign { } { } + assign $1\spr_o[9:0] 10'0001001100 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001101 + assign { } { } + assign $1\spr_o[9:0] 10'0001001101 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001110 + assign { } { } + assign $1\spr_o[9:0] 10'0001001110 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010000 + assign { } { } + assign $1\spr_o[9:0] 10'0001001111 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010001 + assign { } { } + assign $1\spr_o[9:0] 10'0001010000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010010 + assign { } { } + assign $1\spr_o[9:0] 10'0001010001 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010011 + assign { } { } + assign $1\spr_o[9:0] 10'0001010010 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010100 + assign { } { } + assign $1\spr_o[9:0] 10'0001010011 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010101 + assign { } { } + assign $1\spr_o[9:0] 10'0001010100 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010110 + assign { } { } + assign $1\spr_o[9:0] 10'0001010101 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010111 + assign { } { } + assign $1\spr_o[9:0] 10'0001010110 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011000 + assign { } { } + assign $1\spr_o[9:0] 10'0001010111 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011011 + assign { } { } + assign $1\spr_o[9:0] 10'0001011000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011100 + assign { } { } + assign $1\spr_o[9:0] 10'0001011001 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011101 + assign { } { } + assign $1\spr_o[9:0] 10'0001011010 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011110 + assign { } { } + assign $1\spr_o[9:0] 10'0001011011 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100000 + assign { } { } + assign $1\spr_o[9:0] 10'0001011100 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100001 + assign { } { } + assign $1\spr_o[9:0] 10'0001011101 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100010 + assign { } { } + assign $1\spr_o[9:0] 10'0001011110 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100011 + assign { } { } + assign $1\spr_o[9:0] 10'0001011111 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100100 + assign { } { } + assign $1\spr_o[9:0] 10'0001100000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100101 + assign { } { } + assign $1\spr_o[9:0] 10'0001100001 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100110 + assign { } { } + assign $1\spr_o[9:0] 10'0001100010 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101000 + assign { } { } + assign $1\spr_o[9:0] 10'0001100011 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101001 + assign { } { } + assign $1\spr_o[9:0] 10'0001100100 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101010 + assign { } { } + assign $1\spr_o[9:0] 10'0001100101 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101011 + assign { } { } + assign $1\spr_o[9:0] 10'0001100110 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100110000 + assign { } { } + assign $1\spr_o[9:0] 10'0001101000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100110111 + assign { } { } + assign $1\spr_o[9:0] 10'0001101001 + attribute \src "libresoc.v:0.0-0.0" + case 10'1101010000 + assign { } { } + assign $1\spr_o[9:0] 10'0001101010 + attribute \src "libresoc.v:0.0-0.0" + case 10'1101010001 + assign { } { } + assign $1\spr_o[9:0] 10'0001101011 + attribute \src "libresoc.v:0.0-0.0" + case 10'1101010111 + assign { } { } + assign $1\spr_o[9:0] 10'0001101100 + attribute \src "libresoc.v:0.0-0.0" + case 10'1110000000 + assign { } { } + assign $1\spr_o[9:0] 10'0001101101 + attribute \src "libresoc.v:0.0-0.0" + case 10'1110000010 + assign { } { } + assign $1\spr_o[9:0] 10'0001101110 + attribute \src "libresoc.v:0.0-0.0" + case 10'1111111111 + assign { } { } + assign $1\spr_o[9:0] 10'0001101111 + case + assign $1\spr_o[9:0] 10'0000000000 + end + sync always + update \spr_o $0\spr_o[9:0] + end + attribute \src "libresoc.v:195031.3-195349.6" + process $proc$libresoc.v:195031$13429 + assign { } { } + assign { } { } + assign $0\spr_o_ok[0:0] $1\spr_o_ok[0:0] + attribute \src "libresoc.v:195032.5-195032.29" + switch \initial + attribute \src "libresoc.v:195032.9-195032.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:69" + switch \spr_i + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000001101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000110000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000111101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010001000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011111 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010110000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010110100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100001101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011111 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111111 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101011101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110111110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111010000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1011000000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1011010000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000111 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010111 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100110000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100110111 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1101010000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1101010001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1101010111 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1110000000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1110000010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 10'1111111111 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + case + assign $1\spr_o_ok[0:0] 1'0 + end + sync always + update \spr_o_ok $0\spr_o_ok[0:0] + end +end +attribute \src "libresoc.v:195354.1-195466.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.sram4k_0" +attribute \generator "nMigen" +module \sram4k_0 + attribute \src "libresoc.v:195405.3-195414.6" + wire width 9 $0\a[8:0] + attribute \src "libresoc.v:195425.3-195434.6" + wire width 64 $0\d[63:0] + attribute \src "libresoc.v:195355.7-195355.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:195450.3-195464.6" + wire $0\sram4k_0__ack$next[0:0]$13439 + attribute \src "libresoc.v:195396.3-195397.43" + wire $0\sram4k_0__ack[0:0] + attribute \src "libresoc.v:195415.3-195424.6" + wire width 64 $0\sram4k_0__dat_r[63:0] + attribute \src "libresoc.v:195435.3-195449.6" + wire $0\we[0:0] + attribute \src "libresoc.v:195405.3-195414.6" + wire width 9 $1\a[8:0] + attribute \src "libresoc.v:195425.3-195434.6" + wire width 64 $1\d[63:0] + attribute \src "libresoc.v:195450.3-195464.6" + wire $1\sram4k_0__ack$next[0:0]$13440 + attribute \src "libresoc.v:195372.7-195372.27" + wire $1\sram4k_0__ack[0:0] + attribute \src "libresoc.v:195415.3-195424.6" + wire width 64 $1\sram4k_0__dat_r[63:0] + attribute \src "libresoc.v:195435.3-195449.6" + wire $1\we[0:0] + attribute \src "libresoc.v:195450.3-195464.6" + wire $2\sram4k_0__ack$next[0:0]$13441 + attribute \src "libresoc.v:195435.3-195449.6" + wire $2\we[0:0] + attribute \src "libresoc.v:195394.17-195394.123" + wire $and$libresoc.v:195394$13431_Y + attribute \src "libresoc.v:195395.17-195395.123" + wire $and$libresoc.v:195395$13432_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:49" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:64" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:39" + wire width 9 \a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:194" + wire input 10 \clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:42" + wire width 64 \d + attribute \src "libresoc.v:195355.7-195355.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:41" + wire width 64 \q + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:194" + wire input 1 \rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" + wire output 9 \sram4k_0__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" + wire \sram4k_0__ack$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" + wire width 9 input 4 \sram4k_0__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" + wire input 2 \sram4k_0__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" + wire width 64 output 5 \sram4k_0__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" + wire width 64 input 6 \sram4k_0__dat_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" + wire width 8 input 8 \sram4k_0__sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" + wire input 3 \sram4k_0__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" + wire input 7 \sram4k_0__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:48" + wire \wb_active + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:40" + wire \we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:49" + cell $and $and$libresoc.v:195394$13431 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \sram4k_0__cyc + connect \B \sram4k_0__stb + connect \Y $and$libresoc.v:195394$13431_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:64" + cell $and $and$libresoc.v:195395$13432 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \sram4k_0__cyc + connect \B \sram4k_0__stb + connect \Y $and$libresoc.v:195395$13432_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:195398.21-195404.4" + cell \SPBlock_512W64B8W \U$$0 + connect \a \a + connect \clk \clk + connect \d \d + connect \q \q + connect \we \we + end + attribute \src "libresoc.v:195355.7-195355.20" + process $proc$libresoc.v:195355$13442 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:195372.7-195372.27" + process $proc$libresoc.v:195372$13443 + assign { } { } + assign $1\sram4k_0__ack[0:0] 1'0 + sync always + sync init + update \sram4k_0__ack $1\sram4k_0__ack[0:0] + end + attribute \src "libresoc.v:195396.3-195397.43" + process $proc$libresoc.v:195396$13433 + assign { } { } + assign $0\sram4k_0__ack[0:0] \sram4k_0__ack$next + sync posedge \clk + update \sram4k_0__ack $0\sram4k_0__ack[0:0] + end + attribute \src "libresoc.v:195405.3-195414.6" + process $proc$libresoc.v:195405$13434 + assign { } { } + assign { } { } + assign $0\a[8:0] $1\a[8:0] + attribute \src "libresoc.v:195406.5-195406.29" + switch \initial + attribute \src "libresoc.v:195406.9-195406.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:50" + switch \wb_active + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\a[8:0] \sram4k_0__adr + case + assign $1\a[8:0] 9'000000000 + end + sync always + update \a $0\a[8:0] + end + attribute \src "libresoc.v:195415.3-195424.6" + process $proc$libresoc.v:195415$13435 + assign { } { } + assign { } { } + assign $0\sram4k_0__dat_r[63:0] $1\sram4k_0__dat_r[63:0] + attribute \src "libresoc.v:195416.5-195416.29" + switch \initial + attribute \src "libresoc.v:195416.9-195416.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:50" + switch \wb_active + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\sram4k_0__dat_r[63:0] \q + case + assign $1\sram4k_0__dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \sram4k_0__dat_r $0\sram4k_0__dat_r[63:0] + end + attribute \src "libresoc.v:195425.3-195434.6" + process $proc$libresoc.v:195425$13436 + assign { } { } + assign { } { } + assign $0\d[63:0] $1\d[63:0] + attribute \src "libresoc.v:195426.5-195426.29" + switch \initial + attribute \src "libresoc.v:195426.9-195426.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:50" + switch \wb_active + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\d[63:0] \sram4k_0__dat_w + case + assign $1\d[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \d $0\d[63:0] + end + attribute \src "libresoc.v:195435.3-195449.6" + process $proc$libresoc.v:195435$13437 + assign { } { } + assign { } { } + assign $0\we[0:0] $1\we[0:0] + attribute \src "libresoc.v:195436.5-195436.29" + switch \initial + attribute \src "libresoc.v:195436.9-195436.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:50" + switch \wb_active + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\we[0:0] $2\we[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:59" + switch \sram4k_0__we + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\we[0:0] \sram4k_0__sel [0] + case + assign $2\we[0:0] 1'0 + end + case + assign $1\we[0:0] 1'0 + end + sync always + update \we $0\we[0:0] + end + attribute \src "libresoc.v:195450.3-195464.6" + process $proc$libresoc.v:195450$13438 + assign { } { } + assign { } { } + assign { } { } + assign $0\sram4k_0__ack$next[0:0]$13439 $2\sram4k_0__ack$next[0:0]$13441 + attribute \src "libresoc.v:195451.5-195451.29" + switch \initial + attribute \src "libresoc.v:195451.9-195451.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:64" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\sram4k_0__ack$next[0:0]$13440 1'1 + case + assign $1\sram4k_0__ack$next[0:0]$13440 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\sram4k_0__ack$next[0:0]$13441 1'0 + case + assign $2\sram4k_0__ack$next[0:0]$13441 $1\sram4k_0__ack$next[0:0]$13440 + end + sync always + update \sram4k_0__ack$next $0\sram4k_0__ack$next[0:0]$13439 + end + connect \$1 $and$libresoc.v:195394$13431_Y + connect \$3 $and$libresoc.v:195395$13432_Y + connect \wb_active \$1 +end +attribute \src "libresoc.v:195470.1-195582.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.sram4k_1" +attribute \generator "nMigen" +module \sram4k_1 + attribute \src "libresoc.v:195521.3-195530.6" + wire width 9 $0\a[8:0] + attribute \src "libresoc.v:195541.3-195550.6" + wire width 64 $0\d[63:0] + attribute \src "libresoc.v:195471.7-195471.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:195566.3-195580.6" + wire $0\sram4k_1__ack$next[0:0]$13452 + attribute \src "libresoc.v:195512.3-195513.43" + wire $0\sram4k_1__ack[0:0] + attribute \src "libresoc.v:195531.3-195540.6" + wire width 64 $0\sram4k_1__dat_r[63:0] + attribute \src "libresoc.v:195551.3-195565.6" + wire $0\we[0:0] + attribute \src "libresoc.v:195521.3-195530.6" + wire width 9 $1\a[8:0] + attribute \src "libresoc.v:195541.3-195550.6" + wire width 64 $1\d[63:0] + attribute \src "libresoc.v:195566.3-195580.6" + wire $1\sram4k_1__ack$next[0:0]$13453 + attribute \src "libresoc.v:195488.7-195488.27" + wire $1\sram4k_1__ack[0:0] + attribute \src "libresoc.v:195531.3-195540.6" + wire width 64 $1\sram4k_1__dat_r[63:0] + attribute \src "libresoc.v:195551.3-195565.6" + wire $1\we[0:0] + attribute \src "libresoc.v:195566.3-195580.6" + wire $2\sram4k_1__ack$next[0:0]$13454 + attribute \src "libresoc.v:195551.3-195565.6" + wire $2\we[0:0] + attribute \src "libresoc.v:195510.17-195510.123" + wire $and$libresoc.v:195510$13444_Y + attribute \src "libresoc.v:195511.17-195511.123" + wire $and$libresoc.v:195511$13445_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:49" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:64" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:39" + wire width 9 \a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:194" + wire input 10 \clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:42" + wire width 64 \d + attribute \src "libresoc.v:195471.7-195471.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:41" + wire width 64 \q + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:194" + wire input 1 \rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" + wire output 9 \sram4k_1__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" + wire \sram4k_1__ack$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" + wire width 9 input 4 \sram4k_1__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" + wire input 2 \sram4k_1__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" + wire width 64 output 5 \sram4k_1__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" + wire width 64 input 6 \sram4k_1__dat_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" + wire width 8 input 8 \sram4k_1__sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" + wire input 3 \sram4k_1__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" + wire input 7 \sram4k_1__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:48" + wire \wb_active + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:40" + wire \we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:49" + cell $and $and$libresoc.v:195510$13444 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \sram4k_1__cyc + connect \B \sram4k_1__stb + connect \Y $and$libresoc.v:195510$13444_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:64" + cell $and $and$libresoc.v:195511$13445 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \sram4k_1__cyc + connect \B \sram4k_1__stb + connect \Y $and$libresoc.v:195511$13445_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:195514.21-195520.4" + cell \SPBlock_512W64B8W \U$$0 + connect \a \a + connect \clk \clk + connect \d \d + connect \q \q + connect \we \we + end + attribute \src "libresoc.v:195471.7-195471.20" + process $proc$libresoc.v:195471$13455 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:195488.7-195488.27" + process $proc$libresoc.v:195488$13456 + assign { } { } + assign $1\sram4k_1__ack[0:0] 1'0 + sync always + sync init + update \sram4k_1__ack $1\sram4k_1__ack[0:0] + end + attribute \src "libresoc.v:195512.3-195513.43" + process $proc$libresoc.v:195512$13446 + assign { } { } + assign $0\sram4k_1__ack[0:0] \sram4k_1__ack$next + sync posedge \clk + update \sram4k_1__ack $0\sram4k_1__ack[0:0] + end + attribute \src "libresoc.v:195521.3-195530.6" + process $proc$libresoc.v:195521$13447 + assign { } { } + assign { } { } + assign $0\a[8:0] $1\a[8:0] + attribute \src "libresoc.v:195522.5-195522.29" + switch \initial + attribute \src "libresoc.v:195522.9-195522.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:50" + switch \wb_active + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\a[8:0] \sram4k_1__adr + case + assign $1\a[8:0] 9'000000000 + end + sync always + update \a $0\a[8:0] + end + attribute \src "libresoc.v:195531.3-195540.6" + process $proc$libresoc.v:195531$13448 + assign { } { } + assign { } { } + assign $0\sram4k_1__dat_r[63:0] $1\sram4k_1__dat_r[63:0] + attribute \src "libresoc.v:195532.5-195532.29" + switch \initial + attribute \src "libresoc.v:195532.9-195532.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:50" + switch \wb_active + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\sram4k_1__dat_r[63:0] \q + case + assign $1\sram4k_1__dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \sram4k_1__dat_r $0\sram4k_1__dat_r[63:0] + end + attribute \src "libresoc.v:195541.3-195550.6" + process $proc$libresoc.v:195541$13449 + assign { } { } + assign { } { } + assign $0\d[63:0] $1\d[63:0] + attribute \src "libresoc.v:195542.5-195542.29" + switch \initial + attribute \src "libresoc.v:195542.9-195542.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:50" + switch \wb_active + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\d[63:0] \sram4k_1__dat_w + case + assign $1\d[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \d $0\d[63:0] + end + attribute \src "libresoc.v:195551.3-195565.6" + process $proc$libresoc.v:195551$13450 + assign { } { } + assign { } { } + assign $0\we[0:0] $1\we[0:0] + attribute \src "libresoc.v:195552.5-195552.29" + switch \initial + attribute \src "libresoc.v:195552.9-195552.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:50" + switch \wb_active + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\we[0:0] $2\we[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:59" + switch \sram4k_1__we + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\we[0:0] \sram4k_1__sel [0] + case + assign $2\we[0:0] 1'0 + end + case + assign $1\we[0:0] 1'0 + end + sync always + update \we $0\we[0:0] + end + attribute \src "libresoc.v:195566.3-195580.6" + process $proc$libresoc.v:195566$13451 + assign { } { } + assign { } { } + assign { } { } + assign $0\sram4k_1__ack$next[0:0]$13452 $2\sram4k_1__ack$next[0:0]$13454 + attribute \src "libresoc.v:195567.5-195567.29" + switch \initial + attribute \src "libresoc.v:195567.9-195567.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:64" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\sram4k_1__ack$next[0:0]$13453 1'1 + case + assign $1\sram4k_1__ack$next[0:0]$13453 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\sram4k_1__ack$next[0:0]$13454 1'0 + case + assign $2\sram4k_1__ack$next[0:0]$13454 $1\sram4k_1__ack$next[0:0]$13453 + end + sync always + update \sram4k_1__ack$next $0\sram4k_1__ack$next[0:0]$13452 + end + connect \$1 $and$libresoc.v:195510$13444_Y + connect \$3 $and$libresoc.v:195511$13445_Y + connect \wb_active \$1 +end +attribute \src "libresoc.v:195586.1-195698.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.sram4k_2" +attribute \generator "nMigen" +module \sram4k_2 + attribute \src "libresoc.v:195637.3-195646.6" + wire width 9 $0\a[8:0] + attribute \src "libresoc.v:195657.3-195666.6" + wire width 64 $0\d[63:0] + attribute \src "libresoc.v:195587.7-195587.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:195682.3-195696.6" + wire $0\sram4k_2__ack$next[0:0]$13465 + attribute \src "libresoc.v:195628.3-195629.43" + wire $0\sram4k_2__ack[0:0] + attribute \src "libresoc.v:195647.3-195656.6" + wire width 64 $0\sram4k_2__dat_r[63:0] + attribute \src "libresoc.v:195667.3-195681.6" + wire $0\we[0:0] + attribute \src "libresoc.v:195637.3-195646.6" + wire width 9 $1\a[8:0] + attribute \src "libresoc.v:195657.3-195666.6" + wire width 64 $1\d[63:0] + attribute \src "libresoc.v:195682.3-195696.6" + wire $1\sram4k_2__ack$next[0:0]$13466 + attribute \src "libresoc.v:195604.7-195604.27" + wire $1\sram4k_2__ack[0:0] + attribute \src "libresoc.v:195647.3-195656.6" + wire width 64 $1\sram4k_2__dat_r[63:0] + attribute \src "libresoc.v:195667.3-195681.6" + wire $1\we[0:0] + attribute \src "libresoc.v:195682.3-195696.6" + wire $2\sram4k_2__ack$next[0:0]$13467 + attribute \src "libresoc.v:195667.3-195681.6" + wire $2\we[0:0] + attribute \src "libresoc.v:195626.17-195626.123" + wire $and$libresoc.v:195626$13457_Y + attribute \src "libresoc.v:195627.17-195627.123" + wire $and$libresoc.v:195627$13458_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:49" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:64" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:39" + wire width 9 \a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:194" + wire input 10 \clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:42" + wire width 64 \d + attribute \src "libresoc.v:195587.7-195587.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:41" + wire width 64 \q + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:194" + wire input 1 \rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" + wire output 9 \sram4k_2__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" + wire \sram4k_2__ack$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" + wire width 9 input 4 \sram4k_2__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" + wire input 2 \sram4k_2__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" + wire width 64 output 5 \sram4k_2__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" + wire width 64 input 6 \sram4k_2__dat_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" + wire width 8 input 8 \sram4k_2__sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" + wire input 3 \sram4k_2__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" + wire input 7 \sram4k_2__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:48" + wire \wb_active + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:40" + wire \we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:49" + cell $and $and$libresoc.v:195626$13457 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \sram4k_2__cyc + connect \B \sram4k_2__stb + connect \Y $and$libresoc.v:195626$13457_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:64" + cell $and $and$libresoc.v:195627$13458 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \sram4k_2__cyc + connect \B \sram4k_2__stb + connect \Y $and$libresoc.v:195627$13458_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:195630.21-195636.4" + cell \SPBlock_512W64B8W \U$$0 + connect \a \a + connect \clk \clk + connect \d \d + connect \q \q + connect \we \we + end + attribute \src "libresoc.v:195587.7-195587.20" + process $proc$libresoc.v:195587$13468 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:195604.7-195604.27" + process $proc$libresoc.v:195604$13469 + assign { } { } + assign $1\sram4k_2__ack[0:0] 1'0 + sync always + sync init + update \sram4k_2__ack $1\sram4k_2__ack[0:0] + end + attribute \src "libresoc.v:195628.3-195629.43" + process $proc$libresoc.v:195628$13459 + assign { } { } + assign $0\sram4k_2__ack[0:0] \sram4k_2__ack$next + sync posedge \clk + update \sram4k_2__ack $0\sram4k_2__ack[0:0] + end + attribute \src "libresoc.v:195637.3-195646.6" + process $proc$libresoc.v:195637$13460 + assign { } { } + assign { } { } + assign $0\a[8:0] $1\a[8:0] + attribute \src "libresoc.v:195638.5-195638.29" + switch \initial + attribute \src "libresoc.v:195638.9-195638.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:50" + switch \wb_active + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\a[8:0] \sram4k_2__adr + case + assign $1\a[8:0] 9'000000000 + end + sync always + update \a $0\a[8:0] + end + attribute \src "libresoc.v:195647.3-195656.6" + process $proc$libresoc.v:195647$13461 + assign { } { } + assign { } { } + assign $0\sram4k_2__dat_r[63:0] $1\sram4k_2__dat_r[63:0] + attribute \src "libresoc.v:195648.5-195648.29" + switch \initial + attribute \src "libresoc.v:195648.9-195648.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:50" + switch \wb_active + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\sram4k_2__dat_r[63:0] \q + case + assign $1\sram4k_2__dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \sram4k_2__dat_r $0\sram4k_2__dat_r[63:0] + end + attribute \src "libresoc.v:195657.3-195666.6" + process $proc$libresoc.v:195657$13462 + assign { } { } + assign { } { } + assign $0\d[63:0] $1\d[63:0] + attribute \src "libresoc.v:195658.5-195658.29" + switch \initial + attribute \src "libresoc.v:195658.9-195658.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:50" + switch \wb_active + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\d[63:0] \sram4k_2__dat_w + case + assign $1\d[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \d $0\d[63:0] + end + attribute \src "libresoc.v:195667.3-195681.6" + process $proc$libresoc.v:195667$13463 + assign { } { } + assign { } { } + assign $0\we[0:0] $1\we[0:0] + attribute \src "libresoc.v:195668.5-195668.29" + switch \initial + attribute \src "libresoc.v:195668.9-195668.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:50" + switch \wb_active + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\we[0:0] $2\we[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:59" + switch \sram4k_2__we + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\we[0:0] \sram4k_2__sel [0] + case + assign $2\we[0:0] 1'0 + end + case + assign $1\we[0:0] 1'0 + end + sync always + update \we $0\we[0:0] + end + attribute \src "libresoc.v:195682.3-195696.6" + process $proc$libresoc.v:195682$13464 + assign { } { } + assign { } { } + assign { } { } + assign $0\sram4k_2__ack$next[0:0]$13465 $2\sram4k_2__ack$next[0:0]$13467 + attribute \src "libresoc.v:195683.5-195683.29" + switch \initial + attribute \src "libresoc.v:195683.9-195683.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:64" + switch \$3 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\sram4k_2__ack$next[0:0]$13466 1'1 + case + assign $1\sram4k_2__ack$next[0:0]$13466 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\sram4k_2__ack$next[0:0]$13467 1'0 + case + assign $2\sram4k_2__ack$next[0:0]$13467 $1\sram4k_2__ack$next[0:0]$13466 + end + sync always + update \sram4k_2__ack$next $0\sram4k_2__ack$next[0:0]$13465 + end + connect \$1 $and$libresoc.v:195626$13457_Y + connect \$3 $and$libresoc.v:195627$13458_Y + connect \wb_active \$1 +end +attribute \src "libresoc.v:195702.1-195814.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.sram4k_3" +attribute \generator "nMigen" +module \sram4k_3 + attribute \src "libresoc.v:195753.3-195762.6" + wire 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"libresoc.v:195798.3-195812.6" + wire $2\sram4k_3__ack$next[0:0]$13480 + attribute \src "libresoc.v:195783.3-195797.6" + wire $2\we[0:0] + attribute \src "libresoc.v:195742.17-195742.123" + wire $and$libresoc.v:195742$13470_Y + attribute \src "libresoc.v:195743.17-195743.123" + wire $and$libresoc.v:195743$13471_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:49" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:64" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:39" + wire width 9 \a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:194" + wire input 10 \clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:42" + wire width 64 \d + attribute \src "libresoc.v:195703.7-195703.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:41" + wire width 64 \q + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:194" + wire input 1 \rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" + wire output 9 \sram4k_3__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" + wire \sram4k_3__ack$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" + wire width 9 input 4 \sram4k_3__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" + wire input 2 \sram4k_3__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" + wire width 64 output 5 \sram4k_3__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" + wire width 64 input 6 \sram4k_3__dat_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" + wire width 8 input 8 \sram4k_3__sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" + wire input 3 \sram4k_3__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" + wire input 7 \sram4k_3__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:48" + wire \wb_active + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:40" + wire \we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:49" + cell $and $and$libresoc.v:195742$13470 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \sram4k_3__cyc + connect \B \sram4k_3__stb + connect \Y $and$libresoc.v:195742$13470_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:64" + cell $and $and$libresoc.v:195743$13471 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \sram4k_3__cyc + connect \B \sram4k_3__stb + connect \Y $and$libresoc.v:195743$13471_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:195746.21-195752.4" + cell \SPBlock_512W64B8W \U$$0 + connect \a \a + connect \clk \clk + connect \d \d + connect \q \q + connect \we \we + end + attribute \src "libresoc.v:195703.7-195703.20" + process $proc$libresoc.v:195703$13481 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:195720.7-195720.27" + process $proc$libresoc.v:195720$13482 + assign { } { } + assign $1\sram4k_3__ack[0:0] 1'0 + sync always + sync init + update \sram4k_3__ack $1\sram4k_3__ack[0:0] + end + attribute \src "libresoc.v:195744.3-195745.43" + process $proc$libresoc.v:195744$13472 + assign { } { } + assign $0\sram4k_3__ack[0:0] \sram4k_3__ack$next + sync posedge \clk + update \sram4k_3__ack $0\sram4k_3__ack[0:0] + end + attribute \src "libresoc.v:195753.3-195762.6" + process $proc$libresoc.v:195753$13473 + assign { } { } + assign { } { } + assign $0\a[8:0] $1\a[8:0] + attribute \src "libresoc.v:195754.5-195754.29" + switch \initial + attribute \src "libresoc.v:195754.9-195754.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:50" + switch \wb_active + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\a[8:0] \sram4k_3__adr + case + assign $1\a[8:0] 9'000000000 + end + sync always + update \a $0\a[8:0] + end + attribute \src "libresoc.v:195763.3-195772.6" + process $proc$libresoc.v:195763$13474 + assign { } { } + assign { } { } + assign $0\sram4k_3__dat_r[63:0] $1\sram4k_3__dat_r[63:0] + attribute \src "libresoc.v:195764.5-195764.29" + switch \initial + attribute \src "libresoc.v:195764.9-195764.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:50" + switch \wb_active + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\sram4k_3__dat_r[63:0] \q + case + assign $1\sram4k_3__dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \sram4k_3__dat_r $0\sram4k_3__dat_r[63:0] + end + attribute \src "libresoc.v:195773.3-195782.6" + process $proc$libresoc.v:195773$13475 + assign { } { } + assign { } { } + assign $0\d[63:0] $1\d[63:0] + attribute \src "libresoc.v:195774.5-195774.29" + switch \initial + attribute \src "libresoc.v:195774.9-195774.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:50" + switch \wb_active + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\d[63:0] \sram4k_3__dat_w + case + assign $1\d[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \d $0\d[63:0] + end + attribute \src "libresoc.v:195783.3-195797.6" + process $proc$libresoc.v:195783$13476 + assign { } { } + assign { } { } + assign $0\we[0:0] $1\we[0:0] + attribute \src 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5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 1 \coresync_rst + attribute \src "libresoc.v:195819.7-195819.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 4 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 4 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire width 4 output 4 \q_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" + wire width 4 \qlq_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 4 \qn_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 4 input 3 \r_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire width 4 input 2 \s_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:195854$13483 + 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$not$libresoc.v:195858$13487_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:195861$13490 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \r_src + connect \Y $not$libresoc.v:195861$13490_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:195855$13484 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \$9 + connect \B \s_src + connect \Y $or$libresoc.v:195855$13484_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:195857$13486 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \q_src + connect \B \q_int + connect \Y $or$libresoc.v:195857$13486_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + 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\B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \q_src + connect \B \q_int + connect \Y $or$libresoc.v:195919$13500_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:195922$13503 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \$3 + connect \B \s_src + connect \Y $or$libresoc.v:195922$13503_Y + end + attribute \src "libresoc.v:195881.7-195881.20" + process $proc$libresoc.v:195881$13509 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:195903.13-195903.26" + process $proc$libresoc.v:195903$13510 + assign { } { } + assign $1\q_int[5:0] 6'000000 + sync always + sync init + update \q_int $1\q_int[5:0] + end + attribute \src "libresoc.v:195924.3-195925.27" + process $proc$libresoc.v:195924$13505 + assign { } { } + assign $0\q_int[5:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[5:0] + end + attribute \src "libresoc.v:195926.3-195934.6" + process $proc$libresoc.v:195926$13506 + assign { } { } + assign { } { } + assign $0\q_int$next[5:0]$13507 $1\q_int$next[5:0]$13508 + attribute \src "libresoc.v:195927.5-195927.29" + switch \initial + attribute \src "libresoc.v:195927.9-195927.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[5:0]$13508 6'000000 + case + assign $1\q_int$next[5:0]$13508 \$5 + end + sync always + update \q_int$next $0\q_int$next[5:0]$13507 + end + connect \$9 $and$libresoc.v:195916$13497_Y + connect \$11 $or$libresoc.v:195917$13498_Y + connect \$13 $not$libresoc.v:195918$13499_Y + connect \$15 $or$libresoc.v:195919$13500_Y + connect \$1 $not$libresoc.v:195920$13501_Y + connect \$3 $and$libresoc.v:195921$13502_Y + connect \$5 $or$libresoc.v:195922$13503_Y + connect \$7 $not$libresoc.v:195923$13504_Y + connect \qlq_src \$15 + connect \qn_src \$13 + connect \q_src \$11 +end +attribute \src "libresoc.v:195942.1-196000.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.src_l" +attribute \generator "nMigen" +module \src_l$101 + attribute \src "libresoc.v:195943.7-195943.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:195988.3-195996.6" + wire width 3 $0\q_int$next[2:0]$13521 + attribute \src "libresoc.v:195986.3-195987.27" + wire width 3 $0\q_int[2:0] + attribute \src "libresoc.v:195988.3-195996.6" + wire width 3 $1\q_int$next[2:0]$13522 + attribute \src "libresoc.v:195965.13-195965.25" + wire width 3 $1\q_int[2:0] + attribute \src "libresoc.v:195978.17-195978.96" + wire width 3 $and$libresoc.v:195978$13511_Y + attribute \src "libresoc.v:195983.17-195983.96" + wire width 3 $and$libresoc.v:195983$13516_Y + attribute \src "libresoc.v:195980.18-195980.93" + wire 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"/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 3 \qn_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 3 input 3 \r_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire width 3 input 2 \s_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:195978$13511 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:195978$13511_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:195983$13516 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:195983$13516_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:195980$13513 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_src + connect \Y $not$libresoc.v:195980$13513_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:195982$13515 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \r_src + connect \Y $not$libresoc.v:195982$13515_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:195985$13518 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \r_src + connect \Y $not$libresoc.v:195985$13518_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:195979$13512 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \$9 + connect \B \s_src + connect \Y $or$libresoc.v:195979$13512_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:195981$13514 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_src + connect \B \q_int + connect \Y $or$libresoc.v:195981$13514_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:195984$13517 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \$3 + connect \B \s_src + connect \Y $or$libresoc.v:195984$13517_Y + end + attribute \src "libresoc.v:195943.7-195943.20" + process $proc$libresoc.v:195943$13523 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:195965.13-195965.25" + process $proc$libresoc.v:195965$13524 + assign { } { } + assign $1\q_int[2:0] 3'000 + sync always + sync init + update \q_int $1\q_int[2:0] + end + attribute \src "libresoc.v:195986.3-195987.27" + process $proc$libresoc.v:195986$13519 + assign { } { } + assign $0\q_int[2:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[2:0] + end + attribute \src "libresoc.v:195988.3-195996.6" + process $proc$libresoc.v:195988$13520 + assign { } { } + assign { } { } + assign $0\q_int$next[2:0]$13521 $1\q_int$next[2:0]$13522 + attribute \src "libresoc.v:195989.5-195989.29" + switch \initial + attribute \src "libresoc.v:195989.9-195989.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[2:0]$13522 3'000 + case + assign $1\q_int$next[2:0]$13522 \$5 + end + sync always + update \q_int$next $0\q_int$next[2:0]$13521 + end + connect \$9 $and$libresoc.v:195978$13511_Y + connect \$11 $or$libresoc.v:195979$13512_Y + connect \$13 $not$libresoc.v:195980$13513_Y + connect \$15 $or$libresoc.v:195981$13514_Y + connect \$1 $not$libresoc.v:195982$13515_Y + connect \$3 $and$libresoc.v:195983$13516_Y + connect \$5 $or$libresoc.v:195984$13517_Y + connect \$7 $not$libresoc.v:195985$13518_Y + connect \qlq_src \$15 + connect \qn_src \$13 + connect \q_src \$11 +end +attribute \src "libresoc.v:196004.1-196062.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.src_l" +attribute \generator "nMigen" +module \src_l$119 + attribute \src "libresoc.v:196005.7-196005.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:196050.3-196058.6" + wire width 5 $0\q_int$next[4:0]$13535 + attribute \src "libresoc.v:196048.3-196049.27" + wire width 5 $0\q_int[4:0] + attribute \src "libresoc.v:196050.3-196058.6" + wire width 5 $1\q_int$next[4:0]$13536 + attribute \src "libresoc.v:196027.13-196027.26" + wire width 5 $1\q_int[4:0] + attribute \src "libresoc.v:196040.17-196040.96" + wire width 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5 output 4 \q_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" + wire width 5 \qlq_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 5 \qn_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 5 input 3 \r_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire width 5 input 2 \s_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:196040$13525 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:196040$13525_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:196045$13530 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:196045$13530_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:196042$13527 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \q_src + connect \Y $not$libresoc.v:196042$13527_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:196044$13529 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \r_src + connect \Y $not$libresoc.v:196044$13529_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:196047$13532 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \r_src + connect \Y $not$libresoc.v:196047$13532_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:196041$13526 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + 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$0\q_int$next[4:0]$13535 + end + connect \$9 $and$libresoc.v:196040$13525_Y + connect \$11 $or$libresoc.v:196041$13526_Y + connect \$13 $not$libresoc.v:196042$13527_Y + connect \$15 $or$libresoc.v:196043$13528_Y + connect \$1 $not$libresoc.v:196044$13529_Y + connect \$3 $and$libresoc.v:196045$13530_Y + connect \$5 $or$libresoc.v:196046$13531_Y + connect \$7 $not$libresoc.v:196047$13532_Y + connect \qlq_src \$15 + connect \qn_src \$13 + connect \q_src \$11 +end +attribute \src "libresoc.v:196066.1-196124.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.src_l" +attribute \generator "nMigen" +module \src_l$127 + attribute \src "libresoc.v:196067.7-196067.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:196112.3-196120.6" + wire width 3 $0\q_int$next[2:0]$13549 + attribute \src "libresoc.v:196110.3-196111.27" + wire width 3 $0\q_int[2:0] + attribute \src "libresoc.v:196112.3-196120.6" + wire width 3 $1\q_int$next[2:0]$13550 + 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$and $and$libresoc.v:196107$13544 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:196107$13544_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:196104$13541 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_src + connect \Y $not$libresoc.v:196104$13541_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:196106$13543 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \r_src + connect \Y $not$libresoc.v:196106$13543_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:196109$13546 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \r_src + connect \Y $not$libresoc.v:196109$13546_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:196103$13540 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \$9 + connect \B \s_src + connect \Y $or$libresoc.v:196103$13540_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:196105$13542 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_src + connect \B \q_int + connect \Y $or$libresoc.v:196105$13542_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:196108$13545 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \$3 + connect \B \s_src + connect \Y $or$libresoc.v:196108$13545_Y + end + attribute \src "libresoc.v:196067.7-196067.20" + process $proc$libresoc.v:196067$13551 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:196089.13-196089.25" + process $proc$libresoc.v:196089$13552 + assign { } { } + assign $1\q_int[2:0] 3'000 + sync always + sync init + update \q_int $1\q_int[2:0] + end + attribute \src "libresoc.v:196110.3-196111.27" + process $proc$libresoc.v:196110$13547 + assign { } { } + assign $0\q_int[2:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[2:0] + end + attribute \src "libresoc.v:196112.3-196120.6" + process $proc$libresoc.v:196112$13548 + assign { } { } + assign { } { } + assign $0\q_int$next[2:0]$13549 $1\q_int$next[2:0]$13550 + attribute \src "libresoc.v:196113.5-196113.29" + switch \initial + attribute \src "libresoc.v:196113.9-196113.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[2:0]$13550 3'000 + case + assign $1\q_int$next[2:0]$13550 \$5 + end + sync always + update \q_int$next $0\q_int$next[2:0]$13549 + end + connect \$9 $and$libresoc.v:196102$13539_Y + connect \$11 $or$libresoc.v:196103$13540_Y + connect \$13 $not$libresoc.v:196104$13541_Y + connect \$15 $or$libresoc.v:196105$13542_Y + connect \$1 $not$libresoc.v:196106$13543_Y + connect \$3 $and$libresoc.v:196107$13544_Y + connect \$5 $or$libresoc.v:196108$13545_Y + connect \$7 $not$libresoc.v:196109$13546_Y + connect \qlq_src \$15 + connect \qn_src \$13 + connect \q_src \$11 +end +attribute \src "libresoc.v:196128.1-196186.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.src_l" +attribute \generator "nMigen" +module \src_l$23 + attribute \src "libresoc.v:196129.7-196129.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:196174.3-196182.6" + wire width 3 $0\q_int$next[2:0]$13563 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"/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 3 input 3 \r_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire width 3 input 2 \s_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:196288$13581 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:196288$13581_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:196293$13586 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:196293$13586_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:196290$13583 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_src + connect \Y $not$libresoc.v:196290$13583_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:196292$13585 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \r_src + connect \Y $not$libresoc.v:196292$13585_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:196295$13588 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \r_src + connect \Y $not$libresoc.v:196295$13588_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:196289$13582 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \$9 + connect \B \s_src + connect \Y $or$libresoc.v:196289$13582_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:196291$13584 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_src + connect \B \q_int + connect \Y $or$libresoc.v:196291$13584_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:196294$13587 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \$3 + connect \B \s_src + connect \Y $or$libresoc.v:196294$13587_Y + end + attribute \src "libresoc.v:196253.7-196253.20" + process $proc$libresoc.v:196253$13593 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:196275.13-196275.25" + process $proc$libresoc.v:196275$13594 + assign { } { } + assign $1\q_int[2:0] 3'000 + sync always + sync init + update \q_int $1\q_int[2:0] + end + attribute \src "libresoc.v:196296.3-196297.27" + process $proc$libresoc.v:196296$13589 + assign { } { } + assign $0\q_int[2:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[2:0] + end + attribute \src "libresoc.v:196298.3-196306.6" + process $proc$libresoc.v:196298$13590 + assign { } { } + assign { } { } + assign $0\q_int$next[2:0]$13591 $1\q_int$next[2:0]$13592 + attribute \src "libresoc.v:196299.5-196299.29" + switch \initial + attribute \src "libresoc.v:196299.9-196299.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[2:0]$13592 3'000 + case + assign $1\q_int$next[2:0]$13592 \$5 + end + sync always + update \q_int$next $0\q_int$next[2:0]$13591 + end + connect \$9 $and$libresoc.v:196288$13581_Y + connect \$11 $or$libresoc.v:196289$13582_Y + connect \$13 $not$libresoc.v:196290$13583_Y + connect \$15 $or$libresoc.v:196291$13584_Y + connect \$1 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wire width 6 \qlq_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 6 \qn_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 6 input 3 \r_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire width 6 input 2 \s_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:196350$13595 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:196350$13595_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:196355$13600 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:196355$13600_Y + end + attribute \src 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\B \s_src + connect \Y $or$libresoc.v:196351$13596_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:196353$13598 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \q_src + connect \B \q_int + connect \Y $or$libresoc.v:196353$13598_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:196356$13601 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \$3 + connect \B \s_src + connect \Y $or$libresoc.v:196356$13601_Y + end + attribute \src "libresoc.v:196315.7-196315.20" + process $proc$libresoc.v:196315$13607 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:196337.13-196337.26" + process $proc$libresoc.v:196337$13608 + assign { } { } + assign $1\q_int[5:0] 6'000000 + sync always + sync init + update \q_int $1\q_int[5:0] + end + attribute \src "libresoc.v:196358.3-196359.27" + process $proc$libresoc.v:196358$13603 + assign { } { } + assign $0\q_int[5:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[5:0] + end + attribute \src "libresoc.v:196360.3-196368.6" + process $proc$libresoc.v:196360$13604 + assign { } { } + assign { } { } + assign $0\q_int$next[5:0]$13605 $1\q_int$next[5:0]$13606 + attribute \src "libresoc.v:196361.5-196361.29" + switch \initial + attribute \src "libresoc.v:196361.9-196361.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[5:0]$13606 6'000000 + case + assign $1\q_int$next[5:0]$13606 \$5 + end + sync always + update \q_int$next $0\q_int$next[5:0]$13605 + end + connect \$9 $and$libresoc.v:196350$13595_Y + connect \$11 $or$libresoc.v:196351$13596_Y + connect \$13 $not$libresoc.v:196352$13597_Y + connect \$15 $or$libresoc.v:196353$13598_Y + connect \$1 $not$libresoc.v:196354$13599_Y + connect \$3 $and$libresoc.v:196355$13600_Y + connect \$5 $or$libresoc.v:196356$13601_Y + connect \$7 $not$libresoc.v:196357$13602_Y + connect \qlq_src \$15 + connect \qn_src \$13 + connect \q_src \$11 +end +attribute \src "libresoc.v:196376.1-196434.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.src_l" +attribute \generator "nMigen" +module \src_l$84 + attribute \src "libresoc.v:196377.7-196377.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:196422.3-196430.6" + wire width 3 $0\q_int$next[2:0]$13619 + attribute \src "libresoc.v:196420.3-196421.27" + wire width 3 $0\q_int[2:0] + attribute \src "libresoc.v:196422.3-196430.6" + wire width 3 $1\q_int$next[2:0]$13620 + attribute \src "libresoc.v:196399.13-196399.25" + wire width 3 $1\q_int[2:0] + attribute \src "libresoc.v:196412.17-196412.96" + wire width 3 $and$libresoc.v:196412$13609_Y + attribute \src "libresoc.v:196417.17-196417.96" + wire width 3 $and$libresoc.v:196417$13614_Y + attribute \src "libresoc.v:196414.18-196414.93" + wire width 3 $not$libresoc.v:196414$13611_Y + attribute \src "libresoc.v:196416.17-196416.92" + wire width 3 $not$libresoc.v:196416$13613_Y + attribute \src "libresoc.v:196419.17-196419.92" + wire width 3 $not$libresoc.v:196419$13616_Y + attribute \src "libresoc.v:196413.18-196413.98" + wire width 3 $or$libresoc.v:196413$13610_Y + attribute \src "libresoc.v:196415.18-196415.99" + wire width 3 $or$libresoc.v:196415$13612_Y + attribute \src "libresoc.v:196418.17-196418.97" + wire width 3 $or$libresoc.v:196418$13615_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire width 3 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire width 3 \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + wire width 3 \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + wire width 3 \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire width 3 \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire width 3 \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire width 3 \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire width 3 \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 1 \coresync_rst + attribute \src "libresoc.v:196377.7-196377.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 3 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 3 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire width 3 output 4 \q_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" + wire width 3 \qlq_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 3 \qn_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 3 input 3 \r_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire width 3 input 2 \s_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:196412$13609 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:196412$13609_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:196417$13614 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:196417$13614_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:196414$13611 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_src + connect \Y $not$libresoc.v:196414$13611_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:196416$13613 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \r_src + connect \Y $not$libresoc.v:196416$13613_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:196419$13616 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \r_src + connect \Y $not$libresoc.v:196419$13616_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:196413$13610 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \$9 + connect \B \s_src + connect \Y $or$libresoc.v:196413$13610_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:196415$13612 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_src + connect \B \q_int + connect \Y $or$libresoc.v:196415$13612_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:196418$13615 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \$3 + connect \B \s_src + connect \Y $or$libresoc.v:196418$13615_Y + end + attribute \src "libresoc.v:196377.7-196377.20" + process $proc$libresoc.v:196377$13621 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:196399.13-196399.25" + process $proc$libresoc.v:196399$13622 + assign { } { } + assign $1\q_int[2:0] 3'000 + sync always + sync init + update \q_int $1\q_int[2:0] + end + attribute \src "libresoc.v:196420.3-196421.27" + process $proc$libresoc.v:196420$13617 + assign { } { } + assign $0\q_int[2:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[2:0] + end + attribute \src "libresoc.v:196422.3-196430.6" + process $proc$libresoc.v:196422$13618 + assign { } { } + assign { } { } + assign $0\q_int$next[2:0]$13619 $1\q_int$next[2:0]$13620 + attribute \src "libresoc.v:196423.5-196423.29" + switch \initial + attribute \src "libresoc.v:196423.9-196423.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[2:0]$13620 3'000 + case + assign $1\q_int$next[2:0]$13620 \$5 + end + sync always + update \q_int$next $0\q_int$next[2:0]$13619 + end + connect \$9 $and$libresoc.v:196412$13609_Y + connect \$11 $or$libresoc.v:196413$13610_Y + connect \$13 $not$libresoc.v:196414$13611_Y + connect \$15 $or$libresoc.v:196415$13612_Y + connect \$1 $not$libresoc.v:196416$13613_Y + connect \$3 $and$libresoc.v:196417$13614_Y + connect \$5 $or$libresoc.v:196418$13615_Y + connect \$7 $not$libresoc.v:196419$13616_Y + connect \qlq_src \$15 + connect \qn_src \$13 + connect \q_src \$11 +end +attribute \src "libresoc.v:196438.1-196496.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem.st_active" +attribute \generator "nMigen" +module \st_active + attribute \src "libresoc.v:196439.7-196439.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:196484.3-196492.6" + wire $0\q_int$next[0:0]$13633 + attribute \src "libresoc.v:196482.3-196483.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:196484.3-196492.6" + wire $1\q_int$next[0:0]$13634 + attribute \src "libresoc.v:196461.7-196461.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:196474.17-196474.96" + wire $and$libresoc.v:196474$13623_Y + attribute \src "libresoc.v:196479.17-196479.96" + wire $and$libresoc.v:196479$13628_Y + attribute \src "libresoc.v:196476.18-196476.99" + wire $not$libresoc.v:196476$13625_Y + attribute \src "libresoc.v:196478.17-196478.98" + wire $not$libresoc.v:196478$13627_Y + attribute \src "libresoc.v:196481.17-196481.98" + wire $not$libresoc.v:196481$13630_Y + attribute \src "libresoc.v:196475.18-196475.104" + wire $or$libresoc.v:196475$13624_Y + attribute \src "libresoc.v:196477.18-196477.105" + wire $or$libresoc.v:196477$13626_Y + attribute \src "libresoc.v:196480.17-196480.103" + wire $or$libresoc.v:196480$13629_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 1 \coresync_rst + attribute \src "libresoc.v:196439.7-196439.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire output 4 \q_st_active + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" + wire \qlq_st_active + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \qn_st_active + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire input 2 \r_st_active + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire input 3 \s_st_active + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:196474$13623 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:196474$13623_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:196479$13628 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:196479$13628_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:196476$13625 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_st_active + connect \Y $not$libresoc.v:196476$13625_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:196478$13627 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_st_active + connect \Y $not$libresoc.v:196478$13627_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:196481$13630 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_st_active + connect \Y $not$libresoc.v:196481$13630_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:196475$13624 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_st_active + connect \Y $or$libresoc.v:196475$13624_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:196477$13626 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_st_active + connect \B \q_int + connect \Y $or$libresoc.v:196477$13626_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:196480$13629 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_st_active + connect \Y $or$libresoc.v:196480$13629_Y + end + attribute \src "libresoc.v:196439.7-196439.20" + process $proc$libresoc.v:196439$13635 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:196461.7-196461.19" + process $proc$libresoc.v:196461$13636 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:196482.3-196483.27" + process $proc$libresoc.v:196482$13631 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:196484.3-196492.6" + process $proc$libresoc.v:196484$13632 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$13633 $1\q_int$next[0:0]$13634 + attribute \src "libresoc.v:196485.5-196485.29" + switch \initial + attribute \src "libresoc.v:196485.9-196485.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$13634 1'0 + case + assign $1\q_int$next[0:0]$13634 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$13633 + end + connect \$9 $and$libresoc.v:196474$13623_Y + connect \$11 $or$libresoc.v:196475$13624_Y + connect \$13 $not$libresoc.v:196476$13625_Y + connect \$15 $or$libresoc.v:196477$13626_Y + connect \$1 $not$libresoc.v:196478$13627_Y + connect \$3 $and$libresoc.v:196479$13628_Y + connect \$5 $or$libresoc.v:196480$13629_Y + connect \$7 $not$libresoc.v:196481$13630_Y + connect \qlq_st_active \$15 + connect \qn_st_active \$13 + connect \q_st_active \$11 +end +attribute \src "libresoc.v:196500.1-196558.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem.st_done" +attribute \generator "nMigen" +module \st_done + attribute \src "libresoc.v:196501.7-196501.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:196546.3-196554.6" + wire $0\q_int$next[0:0]$13647 + attribute \src "libresoc.v:196544.3-196545.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:196546.3-196554.6" + wire $1\q_int$next[0:0]$13648 + attribute \src "libresoc.v:196523.7-196523.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:196536.17-196536.96" + wire $and$libresoc.v:196536$13637_Y + attribute \src "libresoc.v:196541.17-196541.96" + wire $and$libresoc.v:196541$13642_Y + attribute \src "libresoc.v:196538.18-196538.97" + wire $not$libresoc.v:196538$13639_Y + attribute \src "libresoc.v:196540.17-196540.96" + wire $not$libresoc.v:196540$13641_Y + attribute \src "libresoc.v:196543.17-196543.96" + wire $not$libresoc.v:196543$13644_Y + attribute \src "libresoc.v:196537.18-196537.102" + wire $or$libresoc.v:196537$13638_Y + attribute \src "libresoc.v:196539.18-196539.103" + wire $or$libresoc.v:196539$13640_Y + attribute \src "libresoc.v:196542.17-196542.101" + wire $or$libresoc.v:196542$13643_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 1 \coresync_rst + attribute \src "libresoc.v:196501.7-196501.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int + attribute \src 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parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:196541$13642_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:196538$13639 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_st_done + connect \Y $not$libresoc.v:196538$13639_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:196540$13641 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_st_done + connect \Y $not$libresoc.v:196540$13641_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:196543$13644 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_st_done + connect \Y $not$libresoc.v:196543$13644_Y + end + attribute \src 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"/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 \reg_1_cia1__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire \reg_1_cia1__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 \reg_1_d_wr11__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire \reg_1_d_wr11__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 \reg_1_msr1__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 \reg_1_msr1__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire \reg_1_msr1__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire \reg_1_msr1__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 \reg_1_nia1__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire \reg_1_nia1__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 \reg_1_sv1__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 \reg_1_sv1__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire \reg_1_sv1__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire \reg_1_sv1__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 \reg_2_cia2__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire \reg_2_cia2__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 64 \reg_2_d_wr12__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire \reg_2_d_wr12__wen + attribute \src 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"/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 3 input 6 \sv__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 3 input 4 \wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 3 input 11 \wen$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 3 input 15 \wen$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" + cell $or $or$libresoc.v:196713$13651 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \reg_0_cia0__data_o + connect \B \$8 + connect \Y $or$libresoc.v:196713$13651_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" + cell $or $or$libresoc.v:196715$13653 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \reg_1_msr1__data_o + connect \B \reg_2_msr2__data_o + connect \Y $or$libresoc.v:196715$13653_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" + cell $or $or$libresoc.v:196716$13654 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \reg_0_msr0__data_o + connect \B \$15 + connect \Y $or$libresoc.v:196716$13654_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" + cell $or $or$libresoc.v:196718$13656 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \reg_1_sv1__data_o + connect \B \reg_2_sv2__data_o + connect \Y $or$libresoc.v:196718$13656_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" + cell $or $or$libresoc.v:196719$13657 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \reg_0_sv0__data_o + connect \B \$22 + connect \Y $or$libresoc.v:196719$13657_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" + cell $or $or$libresoc.v:196721$13659 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \reg_1_cia1__data_o + connect \B \reg_2_cia2__data_o + connect \Y $or$libresoc.v:196721$13659_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + cell $reduce_or $reduce_or$libresoc.v:196714$13652 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \ren_delay$12 + connect \Y $reduce_or$libresoc.v:196714$13652_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + cell $reduce_or $reduce_or$libresoc.v:196717$13655 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \ren_delay$19 + connect \Y $reduce_or$libresoc.v:196717$13655_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + cell $reduce_or $reduce_or$libresoc.v:196720$13658 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \ren_delay + connect \Y $reduce_or$libresoc.v:196720$13658_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:196728.15-196745.4" + cell \reg_0$135 \reg_0 + connect \cia0__data_o \reg_0_cia0__data_o + connect \cia0__ren \reg_0_cia0__ren + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \d_wr10__data_i \reg_0_d_wr10__data_i + connect \d_wr10__wen \reg_0_d_wr10__wen + connect \msr0__data_i \reg_0_msr0__data_i + connect \msr0__data_o \reg_0_msr0__data_o + connect \msr0__ren \reg_0_msr0__ren + connect \msr0__wen \reg_0_msr0__wen + connect \nia0__data_i \reg_0_nia0__data_i + connect \nia0__wen \reg_0_nia0__wen + connect \sv0__data_i \reg_0_sv0__data_i + connect \sv0__data_o \reg_0_sv0__data_o + connect \sv0__ren \reg_0_sv0__ren + connect \sv0__wen \reg_0_sv0__wen + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:196746.15-196763.4" + cell \reg_1$136 \reg_1 + connect \cia1__data_o \reg_1_cia1__data_o + connect \cia1__ren \reg_1_cia1__ren + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \d_wr11__data_i \reg_1_d_wr11__data_i + connect \d_wr11__wen \reg_1_d_wr11__wen + connect \msr1__data_i \reg_1_msr1__data_i + connect \msr1__data_o \reg_1_msr1__data_o + connect \msr1__ren \reg_1_msr1__ren + connect \msr1__wen \reg_1_msr1__wen + connect \nia1__data_i \reg_1_nia1__data_i + connect \nia1__wen \reg_1_nia1__wen + connect \sv1__data_i \reg_1_sv1__data_i + connect \sv1__data_o \reg_1_sv1__data_o + connect \sv1__ren \reg_1_sv1__ren + connect \sv1__wen \reg_1_sv1__wen + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:196764.15-196781.4" + cell \reg_2$137 \reg_2 + connect \cia2__data_o \reg_2_cia2__data_o + connect \cia2__ren \reg_2_cia2__ren + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \d_wr12__data_i \reg_2_d_wr12__data_i + connect \d_wr12__wen \reg_2_d_wr12__wen + connect \msr2__data_i \reg_2_msr2__data_i + connect \msr2__data_o \reg_2_msr2__data_o + connect \msr2__ren \reg_2_msr2__ren + connect \msr2__wen \reg_2_msr2__wen + connect \nia2__data_i \reg_2_nia2__data_i + connect \nia2__wen \reg_2_nia2__wen + connect \sv2__data_i \reg_2_sv2__data_i + connect \sv2__data_o \reg_2_sv2__data_o + connect \sv2__ren \reg_2_sv2__ren + connect \sv2__wen \reg_2_sv2__wen + end + attribute \src "libresoc.v:196563.7-196563.20" + process $proc$libresoc.v:196563$13677 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:196689.13-196689.29" + process $proc$libresoc.v:196689$13678 + assign { } { } + assign $1\ren_delay[2:0] 3'000 + sync always + sync init + update \ren_delay $1\ren_delay[2:0] + end + attribute \src "libresoc.v:196691.13-196691.34" + process $proc$libresoc.v:196691$13679 + assign { } { } + assign $0\ren_delay$12[2:0]$13680 3'000 + sync always + sync init + update \ren_delay$12 $0\ren_delay$12[2:0]$13680 + end + attribute \src "libresoc.v:196695.13-196695.34" + process $proc$libresoc.v:196695$13681 + assign { } { } + assign $0\ren_delay$19[2:0]$13682 3'000 + sync always + sync init + update \ren_delay$19 $0\ren_delay$19[2:0]$13682 + end + attribute \src "libresoc.v:196722.3-196723.43" + process $proc$libresoc.v:196722$13660 + assign { } { } + assign $0\ren_delay$19[2:0]$13661 \ren_delay$19$next + sync posedge \coresync_clk + update \ren_delay$19 $0\ren_delay$19[2:0]$13661 + end + attribute \src "libresoc.v:196724.3-196725.43" + process $proc$libresoc.v:196724$13662 + assign { } { } + assign $0\ren_delay$12[2:0]$13663 \ren_delay$12$next + sync posedge \coresync_clk + update \ren_delay$12 $0\ren_delay$12[2:0]$13663 + end + attribute \src "libresoc.v:196726.3-196727.35" + process $proc$libresoc.v:196726$13664 + assign { } { } + assign $0\ren_delay[2:0] \ren_delay$next + sync posedge \coresync_clk + update \ren_delay $0\ren_delay[2:0] + end + attribute \src "libresoc.v:196782.3-196790.6" + process $proc$libresoc.v:196782$13665 + assign { } { } + assign { } { } + assign $0\ren_delay$19$next[2:0]$13666 $1\ren_delay$19$next[2:0]$13667 + attribute \src "libresoc.v:196783.5-196783.29" + switch \initial + attribute \src "libresoc.v:196783.9-196783.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ren_delay$19$next[2:0]$13667 3'000 + case + assign $1\ren_delay$19$next[2:0]$13667 \sv__ren + end + sync always + update \ren_delay$19$next $0\ren_delay$19$next[2:0]$13666 + end + attribute \src "libresoc.v:196791.3-196800.6" + process $proc$libresoc.v:196791$13668 + assign { } { } + assign { } { } + assign $0\sv__data_o[63:0] $1\sv__data_o[63:0] + attribute \src "libresoc.v:196792.5-196792.29" + switch \initial + attribute \src "libresoc.v:196792.9-196792.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" + switch \$20 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\sv__data_o[63:0] \$24 + case + assign $1\sv__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \sv__data_o $0\sv__data_o[63:0] + end + attribute \src "libresoc.v:196801.3-196809.6" + process $proc$libresoc.v:196801$13669 + assign { } { } + assign { } { } + assign $0\ren_delay$next[2:0]$13670 $1\ren_delay$next[2:0]$13671 + attribute \src "libresoc.v:196802.5-196802.29" + switch \initial + attribute \src "libresoc.v:196802.9-196802.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ren_delay$next[2:0]$13671 3'000 + case + assign $1\ren_delay$next[2:0]$13671 \cia__ren + end + sync always + update \ren_delay$next $0\ren_delay$next[2:0]$13670 + end + attribute \src "libresoc.v:196810.3-196819.6" + process $proc$libresoc.v:196810$13672 + assign { } { } + assign { } { } + assign $0\cia__data_o[63:0] $1\cia__data_o[63:0] + attribute \src "libresoc.v:196811.5-196811.29" + switch \initial + attribute \src "libresoc.v:196811.9-196811.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" + switch \$6 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cia__data_o[63:0] \$10 + case + assign $1\cia__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \cia__data_o $0\cia__data_o[63:0] + end + attribute \src "libresoc.v:196820.3-196828.6" + process $proc$libresoc.v:196820$13673 + assign { } { } + assign { } { } + assign $0\ren_delay$12$next[2:0]$13674 $1\ren_delay$12$next[2:0]$13675 + attribute \src "libresoc.v:196821.5-196821.29" + switch \initial + attribute \src "libresoc.v:196821.9-196821.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ren_delay$12$next[2:0]$13675 3'000 + case + assign $1\ren_delay$12$next[2:0]$13675 \msr__ren + end + sync always + update \ren_delay$12$next $0\ren_delay$12$next[2:0]$13674 + end + attribute \src "libresoc.v:196829.3-196838.6" + process $proc$libresoc.v:196829$13676 + assign { } { } + assign { } { } + assign $0\msr__data_o[63:0] $1\msr__data_o[63:0] + attribute \src "libresoc.v:196830.5-196830.29" + switch \initial + attribute \src "libresoc.v:196830.9-196830.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" + switch \$13 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\msr__data_o[63:0] \$17 + case + assign $1\msr__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \msr__data_o $0\msr__data_o[63:0] + end + connect \$10 $or$libresoc.v:196713$13651_Y + connect \$13 $reduce_or$libresoc.v:196714$13652_Y + connect \$15 $or$libresoc.v:196715$13653_Y + connect \$17 $or$libresoc.v:196716$13654_Y + connect \$20 $reduce_or$libresoc.v:196717$13655_Y + connect \$22 $or$libresoc.v:196718$13656_Y + connect \$24 $or$libresoc.v:196719$13657_Y + connect \$6 $reduce_or$libresoc.v:196720$13658_Y + connect \$8 $or$libresoc.v:196721$13659_Y + connect \reg_2_d_wr12__data_i \data_i + connect \reg_1_d_wr11__data_i \data_i + connect \reg_0_d_wr10__data_i \data_i + connect { \reg_2_d_wr12__wen \reg_1_d_wr11__wen \reg_0_d_wr10__wen } \wen + connect \reg_2_sv2__data_i \data_i$2 + connect \reg_1_sv1__data_i \data_i$2 + connect \reg_0_sv0__data_i \data_i$2 + connect { \reg_2_sv2__wen \reg_1_sv1__wen \reg_0_sv0__wen } \wen$1 + connect \reg_2_msr2__data_i \data_i$4 + connect \reg_1_msr1__data_i \data_i$4 + connect \reg_0_msr0__data_i \data_i$4 + connect { \reg_2_msr2__wen \reg_1_msr1__wen \reg_0_msr0__wen } \wen$5 + connect \reg_2_nia2__data_i \data_i$3 + connect \reg_1_nia1__data_i \data_i$3 + connect \reg_0_nia0__data_i \data_i$3 + connect { \reg_2_nia2__wen \reg_1_nia1__wen \reg_0_nia0__wen } \state_nia_wen + connect { \reg_2_sv2__ren \reg_1_sv1__ren \reg_0_sv0__ren } \sv__ren + connect { \reg_2_msr2__ren \reg_1_msr1__ren \reg_0_msr0__ren } \msr__ren + connect { \reg_2_cia2__ren \reg_1_cia1__ren \reg_0_cia0__ren } \cia__ren +end +attribute \src "libresoc.v:196862.1-196920.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.sto_l" +attribute \generator "nMigen" +module \sto_l + attribute \src "libresoc.v:196863.7-196863.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:196908.3-196916.6" + wire $0\q_int$next[0:0]$13693 + attribute \src "libresoc.v:196906.3-196907.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:196908.3-196916.6" + wire $1\q_int$next[0:0]$13694 + attribute \src "libresoc.v:196885.7-196885.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:196898.17-196898.96" + wire $and$libresoc.v:196898$13683_Y + attribute \src "libresoc.v:196903.17-196903.96" + wire $and$libresoc.v:196903$13688_Y + attribute \src "libresoc.v:196900.18-196900.93" + wire $not$libresoc.v:196900$13685_Y + attribute \src "libresoc.v:196902.17-196902.92" + wire $not$libresoc.v:196902$13687_Y + attribute \src "libresoc.v:196905.17-196905.92" + wire $not$libresoc.v:196905$13690_Y + attribute \src "libresoc.v:196899.18-196899.98" + wire $or$libresoc.v:196899$13684_Y + attribute \src "libresoc.v:196901.18-196901.99" + wire $or$libresoc.v:196901$13686_Y + attribute \src "libresoc.v:196904.17-196904.97" + wire $or$libresoc.v:196904$13689_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 1 \coresync_rst + attribute \src "libresoc.v:196863.7-196863.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire output 4 \q_sto + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" + wire \qlq_sto + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \qn_sto + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire input 3 \r_sto + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire input 2 \s_sto + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:196898$13683 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:196898$13683_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:196903$13688 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:196903$13688_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:196900$13685 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_sto + connect \Y $not$libresoc.v:196900$13685_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:196902$13687 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_sto + connect \Y $not$libresoc.v:196902$13687_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:196905$13690 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_sto + connect \Y $not$libresoc.v:196905$13690_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:196899$13684 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_sto + connect \Y $or$libresoc.v:196899$13684_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:196901$13686 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_sto + connect \B \q_int + connect \Y $or$libresoc.v:196901$13686_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:196904$13689 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_sto + connect \Y $or$libresoc.v:196904$13689_Y + end + attribute \src "libresoc.v:196863.7-196863.20" + process $proc$libresoc.v:196863$13695 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:196885.7-196885.19" + process $proc$libresoc.v:196885$13696 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:196906.3-196907.27" + process $proc$libresoc.v:196906$13691 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:196908.3-196916.6" + process $proc$libresoc.v:196908$13692 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$13693 $1\q_int$next[0:0]$13694 + attribute \src "libresoc.v:196909.5-196909.29" + switch \initial + attribute \src "libresoc.v:196909.9-196909.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$13694 1'0 + case + assign $1\q_int$next[0:0]$13694 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$13693 + end + connect \$9 $and$libresoc.v:196898$13683_Y + connect \$11 $or$libresoc.v:196899$13684_Y + connect \$13 $not$libresoc.v:196900$13685_Y + connect \$15 $or$libresoc.v:196901$13686_Y + connect \$1 $not$libresoc.v:196902$13687_Y + connect \$3 $and$libresoc.v:196903$13688_Y + connect \$5 $or$libresoc.v:196904$13689_Y + connect \$7 $not$libresoc.v:196905$13690_Y + connect \qlq_sto \$15 + connect \qn_sto \$13 + connect \q_sto \$11 +end +attribute \src "libresoc.v:196924.1-196967.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.svp64" +attribute \generator "nMigen" +module \svp64 + attribute \src "libresoc.v:196925.7-196925.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:196953.3-196962.6" + wire width 24 $0\svp64_rm[23:0] + attribute \src "libresoc.v:196953.3-196962.6" + wire width 24 $1\svp64_rm[23:0] + attribute \src "libresoc.v:196952.17-196952.108" + wire $and$libresoc.v:196952$13700_Y + attribute \src "libresoc.v:196950.17-196950.112" + wire $eq$libresoc.v:196950$13698_Y + attribute \src "libresoc.v:196951.17-196951.111" + wire $eq$libresoc.v:196951$13699_Y + attribute \src "libresoc.v:196949.17-196949.213" + wire width 32 $ternary$libresoc.v:196949$13697_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1325" + wire width 32 \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1335" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1336" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1336" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1311" + wire input 1 \bigendian + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1329" + wire width 2 \ident + attribute \src "libresoc.v:196925.7-196925.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1309" + wire output 3 \is_svp64_mode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1328" + wire width 6 \major + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1307" + wire width 32 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1308" + wire width 32 input 4 \raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1310" + wire width 24 output 2 \svp64_rm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1336" + cell $and $and$libresoc.v:196952$13700 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \$5 + connect \Y $and$libresoc.v:196952$13700_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1335" + cell $eq $eq$libresoc.v:196950$13698 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \major + connect \B 6'000001 + connect \Y $eq$libresoc.v:196950$13698_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1336" + cell $eq $eq$libresoc.v:196951$13699 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \ident + connect \B 2'11 + connect \Y $eq$libresoc.v:196951$13699_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1325" + cell $mux $ternary$libresoc.v:196949$13697 + parameter \WIDTH 32 + connect \A \raw_opcode_in + connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } + connect \S \bigendian + connect \Y $ternary$libresoc.v:196949$13697_Y + end + attribute \src "libresoc.v:196925.7-196925.20" + process $proc$libresoc.v:196925$13702 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:196953.3-196962.6" + process $proc$libresoc.v:196953$13701 + assign { } { } + assign { } { } + assign $0\svp64_rm[23:0] $1\svp64_rm[23:0] + attribute \src "libresoc.v:196954.5-196954.29" + switch \initial + attribute \src "libresoc.v:196954.9-196954.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1339" + switch \is_svp64_mode + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\svp64_rm[23:0] { \opcode_in [25] \opcode_in [23] \opcode_in [21:0] } + case + assign $1\svp64_rm[23:0] 24'000000000000000000000000 + end + sync always + update \svp64_rm $0\svp64_rm[23:0] + end + connect \$1 $ternary$libresoc.v:196949$13697_Y + connect \$3 $eq$libresoc.v:196950$13698_Y + connect \$5 $eq$libresoc.v:196951$13699_Y + connect \$7 $and$libresoc.v:196952$13700_Y + connect \is_svp64_mode \$7 + connect \ident { \opcode_in [24] \opcode_in [22] } + connect \major \opcode_in [31:26] + connect \opcode_in \$1 +end +attribute \src "libresoc.v:196972.1-198201.10" +attribute \cells_not_processed 1 +attribute \top 1 +attribute \nmigen.hierarchy "test_issuer" +attribute \generator "nMigen" +module \test_issuer + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" + wire input 9 \TAP_bus__tck + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" + wire input 7 \TAP_bus__tdi + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" + wire output 6 \TAP_bus__tdo + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" + wire input 8 \TAP_bus__tms + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:123" + wire output 5 \busy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:194" + wire input 400 \clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:10" + wire width 2 input 402 \clk_sel_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:122" + wire input 4 \core_bigendian_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire input 344 \dbus__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 45 output 338 \dbus__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 2 input 348 \dbus__bte + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 3 input 347 \dbus__cti + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire output 342 \dbus__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 64 input 340 \dbus__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 64 output 339 \dbus__dat_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire input 346 \dbus__err + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 8 output 341 \dbus__sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire output 343 \dbus__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire output 345 \dbus__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 19 \eint_0__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 20 \eint_0__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 21 \eint_1__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 22 \eint_1__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 23 \eint_2__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 24 \eint_2__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 37 \gpio_e10__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 38 \gpio_e10__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 39 \gpio_e10__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 40 \gpio_e10__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 41 \gpio_e10__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 42 \gpio_e10__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 43 \gpio_e11__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 44 \gpio_e11__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 45 \gpio_e11__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 46 \gpio_e11__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 47 \gpio_e11__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 48 \gpio_e11__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 49 \gpio_e12__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 50 \gpio_e12__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 51 \gpio_e12__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 52 \gpio_e12__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 53 \gpio_e12__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 54 \gpio_e12__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 55 \gpio_e13__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 56 \gpio_e13__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 57 \gpio_e13__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 58 \gpio_e13__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 59 \gpio_e13__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 60 \gpio_e13__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 61 \gpio_e14__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 62 \gpio_e14__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 63 \gpio_e14__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 64 \gpio_e14__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 65 \gpio_e14__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 66 \gpio_e14__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 67 \gpio_e15__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 68 \gpio_e15__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 69 \gpio_e15__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 70 \gpio_e15__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 71 \gpio_e15__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 72 \gpio_e15__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 25 \gpio_e8__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 26 \gpio_e8__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 27 \gpio_e8__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 28 \gpio_e8__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 29 \gpio_e8__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 30 \gpio_e8__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 31 \gpio_e9__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 32 \gpio_e9__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 33 \gpio_e9__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 34 \gpio_e9__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 35 \gpio_e9__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 36 \gpio_e9__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 73 \gpio_s0__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 74 \gpio_s0__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 75 \gpio_s0__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 76 \gpio_s0__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 77 \gpio_s0__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 78 \gpio_s0__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 79 \gpio_s1__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 80 \gpio_s1__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 81 \gpio_s1__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 82 \gpio_s1__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 83 \gpio_s1__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 84 \gpio_s1__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 85 \gpio_s2__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 86 \gpio_s2__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 87 \gpio_s2__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 88 \gpio_s2__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 89 \gpio_s2__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 90 \gpio_s2__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 91 \gpio_s3__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 92 \gpio_s3__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 93 \gpio_s3__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 94 \gpio_s3__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 95 \gpio_s3__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 96 \gpio_s3__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 97 \gpio_s4__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 98 \gpio_s4__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 99 \gpio_s4__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 100 \gpio_s4__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 101 \gpio_s4__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 102 \gpio_s4__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 103 \gpio_s5__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 104 \gpio_s5__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 105 \gpio_s5__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 106 \gpio_s5__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 107 \gpio_s5__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 108 \gpio_s5__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 109 \gpio_s6__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 110 \gpio_s6__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 111 \gpio_s6__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 112 \gpio_s6__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 113 \gpio_s6__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 114 \gpio_s6__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 115 \gpio_s7__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 116 \gpio_s7__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 117 \gpio_s7__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 118 \gpio_s7__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 119 \gpio_s7__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 120 \gpio_s7__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire input 333 \ibus__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire width 45 output 327 \ibus__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire width 2 input 337 \ibus__bte + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire width 3 input 336 \ibus__cti + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire output 331 \ibus__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire width 64 input 329 \ibus__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire width 64 input 328 \ibus__dat_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire input 335 \ibus__err + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire width 8 output 330 \ibus__sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire output 332 \ibus__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire input 334 \ibus__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire output 387 \icp_wb__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire width 28 input 381 \icp_wb__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire input 385 \icp_wb__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire width 32 output 383 \icp_wb__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire width 32 input 382 \icp_wb__dat_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire input 389 \icp_wb__err + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire width 4 input 384 \icp_wb__sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire input 386 \icp_wb__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire input 388 \icp_wb__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire output 396 \ics_wb__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire width 28 input 390 \ics_wb__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire input 394 \ics_wb__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire width 32 output 392 \ics_wb__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire width 32 input 391 \ics_wb__dat_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire input 398 \ics_wb__err + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire width 4 input 393 \ics_wb__sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire input 395 \ics_wb__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire input 397 \ics_wb__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:237" + wire width 16 input 399 \int_level_i + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire input 17 \jtag_wb__ack + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire width 29 output 10 \jtag_wb__adr + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire output 14 \jtag_wb__cyc + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire width 64 input 12 \jtag_wb__dat_r + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire width 64 output 11 \jtag_wb__dat_w + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire input 18 \jtag_wb__err + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire output 13 \jtag_wb__sel + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire output 15 \jtag_wb__stb + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire output 16 \jtag_wb__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:124" + wire input 3 \memerr_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 121 \mspi0_clk__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 122 \mspi0_clk__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 123 \mspi0_cs_n__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 124 \mspi0_cs_n__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 127 \mspi0_miso__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 128 \mspi0_miso__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 125 \mspi0_mosi__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 126 \mspi0_mosi__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 129 \mspi1_clk__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 130 \mspi1_clk__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 131 \mspi1_cs_n__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 132 \mspi1_cs_n__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 135 \mspi1_miso__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 136 \mspi1_miso__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 133 \mspi1_mosi__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 134 \mspi1_mosi__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 143 \mtwi_scl__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 144 \mtwi_scl__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 137 \mtwi_sda__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 138 \mtwi_sda__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 139 \mtwi_sda__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 140 \mtwi_sda__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 141 \mtwi_sda__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 142 \mtwi_sda__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 input 405 \pc_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire input 1 \pc_i_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:120" + wire width 64 output 2 \pc_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:582" + wire output 403 \pll_18_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:9" + wire \pll_clk_24_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:11" + wire \pll_clk_pll_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:13" + wire output 404 \pll_lck_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:12" + wire \pll_pll_18_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:597" + wire \pllclk_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:597" + wire \pllclk_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 145 \pwm_0__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 146 \pwm_0__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 147 \pwm_1__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 148 \pwm_1__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:194" + wire input 401 \rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 155 \sd0_clk__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 156 \sd0_clk__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 149 \sd0_cmd__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 150 \sd0_cmd__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 151 \sd0_cmd__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 152 \sd0_cmd__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 153 \sd0_cmd__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 154 \sd0_cmd__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 157 \sd0_data0__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 158 \sd0_data0__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 159 \sd0_data0__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 160 \sd0_data0__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 161 \sd0_data0__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 162 \sd0_data0__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 163 \sd0_data1__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 164 \sd0_data1__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 165 \sd0_data1__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 166 \sd0_data1__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 167 \sd0_data1__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 168 \sd0_data1__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 169 \sd0_data2__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 170 \sd0_data2__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 171 \sd0_data2__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 172 \sd0_data2__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 173 \sd0_data2__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 174 \sd0_data2__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 175 \sd0_data3__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 176 \sd0_data3__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 177 \sd0_data3__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 178 \sd0_data3__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 179 \sd0_data3__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 180 \sd0_data3__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 231 \sdr_a_0__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 232 \sdr_a_0__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 267 \sdr_a_10__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 268 \sdr_a_10__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 269 \sdr_a_11__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 270 \sdr_a_11__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 271 \sdr_a_12__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 272 \sdr_a_12__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 233 \sdr_a_1__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 234 \sdr_a_1__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 235 \sdr_a_2__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 236 \sdr_a_2__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 237 \sdr_a_3__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 238 \sdr_a_3__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 239 \sdr_a_4__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 240 \sdr_a_4__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 241 \sdr_a_5__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 242 \sdr_a_5__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 243 \sdr_a_6__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 244 \sdr_a_6__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 245 \sdr_a_7__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 246 \sdr_a_7__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 247 \sdr_a_8__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 248 \sdr_a_8__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 249 \sdr_a_9__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 250 \sdr_a_9__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 251 \sdr_ba_0__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 252 \sdr_ba_0__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 253 \sdr_ba_1__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 254 \sdr_ba_1__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 261 \sdr_cas_n__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 262 \sdr_cas_n__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 257 \sdr_cke__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 258 \sdr_cke__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 255 \sdr_clock__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 256 \sdr_clock__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 265 \sdr_cs_n__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 266 \sdr_cs_n__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 181 \sdr_dm_0__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 182 \sdr_dm_0__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 273 \sdr_dm_1__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 274 \sdr_dm_1__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 275 \sdr_dm_1__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 276 \sdr_dm_1__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 277 \sdr_dm_1__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 278 \sdr_dm_1__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 183 \sdr_dq_0__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 184 \sdr_dq_0__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 185 \sdr_dq_0__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 186 \sdr_dq_0__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 187 \sdr_dq_0__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 188 \sdr_dq_0__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 291 \sdr_dq_10__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 292 \sdr_dq_10__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 293 \sdr_dq_10__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 294 \sdr_dq_10__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 295 \sdr_dq_10__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 296 \sdr_dq_10__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 297 \sdr_dq_11__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 298 \sdr_dq_11__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 299 \sdr_dq_11__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 300 \sdr_dq_11__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 301 \sdr_dq_11__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 302 \sdr_dq_11__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 303 \sdr_dq_12__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 304 \sdr_dq_12__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 305 \sdr_dq_12__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 306 \sdr_dq_12__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 307 \sdr_dq_12__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 308 \sdr_dq_12__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 309 \sdr_dq_13__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 310 \sdr_dq_13__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 311 \sdr_dq_13__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 312 \sdr_dq_13__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 313 \sdr_dq_13__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 314 \sdr_dq_13__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 315 \sdr_dq_14__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 316 \sdr_dq_14__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 317 \sdr_dq_14__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 318 \sdr_dq_14__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 319 \sdr_dq_14__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 320 \sdr_dq_14__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 321 \sdr_dq_15__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 322 \sdr_dq_15__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 323 \sdr_dq_15__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 324 \sdr_dq_15__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 325 \sdr_dq_15__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 326 \sdr_dq_15__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 189 \sdr_dq_1__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 190 \sdr_dq_1__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 191 \sdr_dq_1__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 192 \sdr_dq_1__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 193 \sdr_dq_1__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 194 \sdr_dq_1__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 195 \sdr_dq_2__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 196 \sdr_dq_2__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 197 \sdr_dq_2__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 198 \sdr_dq_2__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 199 \sdr_dq_2__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 200 \sdr_dq_2__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 201 \sdr_dq_3__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 202 \sdr_dq_3__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 203 \sdr_dq_3__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 204 \sdr_dq_3__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 205 \sdr_dq_3__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 206 \sdr_dq_3__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 207 \sdr_dq_4__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 208 \sdr_dq_4__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 209 \sdr_dq_4__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 210 \sdr_dq_4__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 211 \sdr_dq_4__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 212 \sdr_dq_4__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 213 \sdr_dq_5__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 214 \sdr_dq_5__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 215 \sdr_dq_5__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 216 \sdr_dq_5__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 217 \sdr_dq_5__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 218 \sdr_dq_5__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 219 \sdr_dq_6__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 220 \sdr_dq_6__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 221 \sdr_dq_6__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 222 \sdr_dq_6__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 223 \sdr_dq_6__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 224 \sdr_dq_6__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 225 \sdr_dq_7__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 226 \sdr_dq_7__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 227 \sdr_dq_7__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 228 \sdr_dq_7__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 229 \sdr_dq_7__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 230 \sdr_dq_7__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 279 \sdr_dq_8__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 280 \sdr_dq_8__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 281 \sdr_dq_8__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 282 \sdr_dq_8__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 283 \sdr_dq_8__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 284 \sdr_dq_8__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 285 \sdr_dq_9__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 286 \sdr_dq_9__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 287 \sdr_dq_9__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 288 \sdr_dq_9__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 289 \sdr_dq_9__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 290 \sdr_dq_9__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 259 \sdr_ras_n__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 260 \sdr_ras_n__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 263 \sdr_we_n__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 264 \sdr_we_n__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" + wire output 356 \sram4k_0__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" + wire width 9 input 349 \sram4k_0__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" + wire input 353 \sram4k_0__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" + wire width 64 output 351 \sram4k_0__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" + wire width 64 input 350 \sram4k_0__dat_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" + wire width 8 input 352 \sram4k_0__sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" + wire input 354 \sram4k_0__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" + wire input 355 \sram4k_0__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" + wire output 364 \sram4k_1__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" + wire width 9 input 357 \sram4k_1__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" + wire input 361 \sram4k_1__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" + wire width 64 output 359 \sram4k_1__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" + wire width 64 input 358 \sram4k_1__dat_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" + wire width 8 input 360 \sram4k_1__sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" + wire input 362 \sram4k_1__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" + wire input 363 \sram4k_1__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" + wire output 372 \sram4k_2__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" + wire width 9 input 365 \sram4k_2__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" + wire input 369 \sram4k_2__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" + wire width 64 output 367 \sram4k_2__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" + wire width 64 input 366 \sram4k_2__dat_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" + wire width 8 input 368 \sram4k_2__sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" + wire input 370 \sram4k_2__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" + wire input 371 \sram4k_2__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" + wire output 380 \sram4k_3__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" + wire width 9 input 373 \sram4k_3__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" + wire input 377 \sram4k_3__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" + wire width 64 output 375 \sram4k_3__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" + wire width 64 input 374 \sram4k_3__dat_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" + wire width 8 input 376 \sram4k_3__sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" + wire input 378 \sram4k_3__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" + wire input 379 \sram4k_3__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire \ti_coresync_clk + attribute \module_not_derived 1 + attribute \src "libresoc.v:197795.7-197801.4" + cell \pll \pll + connect \clk_24_i \pll_clk_24_i + connect \clk_pll_o \pll_clk_pll_o + connect \clk_sel_i \clk_sel_i + connect \pll_18_o \pll_pll_18_o + connect \pll_lck_o \pll_lck_o + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:197802.6-198195.4" + cell \ti \ti + connect \TAP_bus__tck \TAP_bus__tck + connect \TAP_bus__tdi \TAP_bus__tdi + connect \TAP_bus__tdo \TAP_bus__tdo + connect \TAP_bus__tms \TAP_bus__tms + connect \busy_o \busy_o + connect \clk \clk + connect \core_bigendian_i \core_bigendian_i + connect \coresync_clk \ti_coresync_clk + connect \dbus__ack \dbus__ack + connect \dbus__adr \dbus__adr + connect \dbus__cyc \dbus__cyc + connect \dbus__dat_r \dbus__dat_r + connect \dbus__dat_w \dbus__dat_w + connect \dbus__err \dbus__err + connect \dbus__sel \dbus__sel + connect \dbus__stb \dbus__stb + connect \dbus__we \dbus__we + connect \eint_0__core__i \eint_0__core__i + connect \eint_0__pad__i \eint_0__pad__i + connect \eint_1__core__i \eint_1__core__i + connect \eint_1__pad__i \eint_1__pad__i + connect \eint_2__core__i \eint_2__core__i + connect \eint_2__pad__i \eint_2__pad__i + connect \gpio_e10__core__i \gpio_e10__core__i + connect \gpio_e10__core__o \gpio_e10__core__o + connect \gpio_e10__core__oe \gpio_e10__core__oe + connect \gpio_e10__pad__i \gpio_e10__pad__i + connect \gpio_e10__pad__o \gpio_e10__pad__o + connect \gpio_e10__pad__oe \gpio_e10__pad__oe + connect \gpio_e11__core__i \gpio_e11__core__i + connect \gpio_e11__core__o \gpio_e11__core__o + connect \gpio_e11__core__oe \gpio_e11__core__oe + connect \gpio_e11__pad__i \gpio_e11__pad__i + connect \gpio_e11__pad__o \gpio_e11__pad__o + connect \gpio_e11__pad__oe \gpio_e11__pad__oe + connect \gpio_e12__core__i \gpio_e12__core__i + connect \gpio_e12__core__o \gpio_e12__core__o + connect \gpio_e12__core__oe \gpio_e12__core__oe + connect \gpio_e12__pad__i \gpio_e12__pad__i + connect \gpio_e12__pad__o \gpio_e12__pad__o + connect \gpio_e12__pad__oe \gpio_e12__pad__oe + connect \gpio_e13__core__i \gpio_e13__core__i + connect \gpio_e13__core__o \gpio_e13__core__o + connect \gpio_e13__core__oe \gpio_e13__core__oe + connect \gpio_e13__pad__i \gpio_e13__pad__i + connect \gpio_e13__pad__o \gpio_e13__pad__o + connect \gpio_e13__pad__oe \gpio_e13__pad__oe + connect \gpio_e14__core__i \gpio_e14__core__i + connect \gpio_e14__core__o \gpio_e14__core__o + connect \gpio_e14__core__oe \gpio_e14__core__oe + connect \gpio_e14__pad__i \gpio_e14__pad__i + connect \gpio_e14__pad__o \gpio_e14__pad__o + connect \gpio_e14__pad__oe \gpio_e14__pad__oe + connect \gpio_e15__core__i \gpio_e15__core__i + connect \gpio_e15__core__o \gpio_e15__core__o + connect \gpio_e15__core__oe \gpio_e15__core__oe + connect \gpio_e15__pad__i \gpio_e15__pad__i + connect \gpio_e15__pad__o \gpio_e15__pad__o + connect \gpio_e15__pad__oe \gpio_e15__pad__oe + connect \gpio_e8__core__i \gpio_e8__core__i + connect \gpio_e8__core__o \gpio_e8__core__o + connect \gpio_e8__core__oe \gpio_e8__core__oe + connect \gpio_e8__pad__i \gpio_e8__pad__i + connect \gpio_e8__pad__o \gpio_e8__pad__o + connect \gpio_e8__pad__oe \gpio_e8__pad__oe + connect \gpio_e9__core__i \gpio_e9__core__i + connect \gpio_e9__core__o \gpio_e9__core__o + connect \gpio_e9__core__oe \gpio_e9__core__oe + connect \gpio_e9__pad__i \gpio_e9__pad__i + connect \gpio_e9__pad__o \gpio_e9__pad__o + connect \gpio_e9__pad__oe \gpio_e9__pad__oe + connect \gpio_s0__core__i \gpio_s0__core__i + connect \gpio_s0__core__o \gpio_s0__core__o + connect \gpio_s0__core__oe \gpio_s0__core__oe + connect \gpio_s0__pad__i \gpio_s0__pad__i + connect \gpio_s0__pad__o \gpio_s0__pad__o + connect \gpio_s0__pad__oe \gpio_s0__pad__oe + connect \gpio_s1__core__i \gpio_s1__core__i + connect \gpio_s1__core__o \gpio_s1__core__o + connect \gpio_s1__core__oe \gpio_s1__core__oe + connect \gpio_s1__pad__i \gpio_s1__pad__i + connect \gpio_s1__pad__o \gpio_s1__pad__o + connect \gpio_s1__pad__oe \gpio_s1__pad__oe + connect \gpio_s2__core__i \gpio_s2__core__i + connect \gpio_s2__core__o \gpio_s2__core__o + connect \gpio_s2__core__oe \gpio_s2__core__oe + connect \gpio_s2__pad__i \gpio_s2__pad__i + connect \gpio_s2__pad__o \gpio_s2__pad__o + connect \gpio_s2__pad__oe \gpio_s2__pad__oe + connect \gpio_s3__core__i \gpio_s3__core__i + connect \gpio_s3__core__o \gpio_s3__core__o + connect \gpio_s3__core__oe \gpio_s3__core__oe + connect \gpio_s3__pad__i \gpio_s3__pad__i + connect \gpio_s3__pad__o \gpio_s3__pad__o + connect \gpio_s3__pad__oe \gpio_s3__pad__oe + connect \gpio_s4__core__i \gpio_s4__core__i + connect \gpio_s4__core__o \gpio_s4__core__o + connect \gpio_s4__core__oe \gpio_s4__core__oe + connect \gpio_s4__pad__i \gpio_s4__pad__i + connect \gpio_s4__pad__o \gpio_s4__pad__o + connect \gpio_s4__pad__oe \gpio_s4__pad__oe + connect \gpio_s5__core__i \gpio_s5__core__i + connect \gpio_s5__core__o \gpio_s5__core__o + connect \gpio_s5__core__oe \gpio_s5__core__oe + connect \gpio_s5__pad__i \gpio_s5__pad__i + connect \gpio_s5__pad__o \gpio_s5__pad__o + connect \gpio_s5__pad__oe \gpio_s5__pad__oe + connect \gpio_s6__core__i \gpio_s6__core__i + connect \gpio_s6__core__o \gpio_s6__core__o + connect \gpio_s6__core__oe \gpio_s6__core__oe + connect \gpio_s6__pad__i \gpio_s6__pad__i + connect \gpio_s6__pad__o \gpio_s6__pad__o + connect \gpio_s6__pad__oe \gpio_s6__pad__oe + connect \gpio_s7__core__i \gpio_s7__core__i + connect \gpio_s7__core__o \gpio_s7__core__o + connect \gpio_s7__core__oe \gpio_s7__core__oe + connect \gpio_s7__pad__i \gpio_s7__pad__i + connect \gpio_s7__pad__o \gpio_s7__pad__o + connect \gpio_s7__pad__oe \gpio_s7__pad__oe + connect \ibus__ack \ibus__ack + connect \ibus__adr \ibus__adr + connect \ibus__cyc \ibus__cyc + connect \ibus__dat_r \ibus__dat_r + connect \ibus__err \ibus__err + connect \ibus__sel \ibus__sel + connect \ibus__stb \ibus__stb + connect \icp_wb__ack \icp_wb__ack + connect \icp_wb__adr \icp_wb__adr + connect \icp_wb__cyc \icp_wb__cyc + connect \icp_wb__dat_r \icp_wb__dat_r + connect \icp_wb__dat_w \icp_wb__dat_w + connect \icp_wb__sel \icp_wb__sel + connect \icp_wb__stb \icp_wb__stb + connect \icp_wb__we \icp_wb__we + connect \ics_wb__ack \ics_wb__ack + connect \ics_wb__adr \ics_wb__adr + connect \ics_wb__cyc \ics_wb__cyc + connect \ics_wb__dat_r \ics_wb__dat_r + connect \ics_wb__dat_w \ics_wb__dat_w + connect \ics_wb__stb \ics_wb__stb + connect \ics_wb__we \ics_wb__we + connect \int_level_i \int_level_i + connect \jtag_wb__ack \jtag_wb__ack + connect \jtag_wb__adr \jtag_wb__adr + connect \jtag_wb__cyc \jtag_wb__cyc + connect \jtag_wb__dat_r \jtag_wb__dat_r + connect \jtag_wb__dat_w \jtag_wb__dat_w + connect \jtag_wb__sel \jtag_wb__sel + connect \jtag_wb__stb \jtag_wb__stb + connect \jtag_wb__we \jtag_wb__we + connect \mspi0_clk__core__o \mspi0_clk__core__o + connect \mspi0_clk__pad__o \mspi0_clk__pad__o + connect \mspi0_cs_n__core__o \mspi0_cs_n__core__o + connect \mspi0_cs_n__pad__o \mspi0_cs_n__pad__o + connect \mspi0_miso__core__i \mspi0_miso__core__i + connect \mspi0_miso__pad__i \mspi0_miso__pad__i + connect \mspi0_mosi__core__o \mspi0_mosi__core__o + connect \mspi0_mosi__pad__o \mspi0_mosi__pad__o + connect \mspi1_clk__core__o \mspi1_clk__core__o + connect \mspi1_clk__pad__o \mspi1_clk__pad__o + connect \mspi1_cs_n__core__o \mspi1_cs_n__core__o + connect \mspi1_cs_n__pad__o \mspi1_cs_n__pad__o + connect \mspi1_miso__core__i \mspi1_miso__core__i + connect \mspi1_miso__pad__i \mspi1_miso__pad__i + connect \mspi1_mosi__core__o \mspi1_mosi__core__o + connect \mspi1_mosi__pad__o \mspi1_mosi__pad__o + connect \mtwi_scl__core__o \mtwi_scl__core__o + connect \mtwi_scl__pad__o \mtwi_scl__pad__o + connect \mtwi_sda__core__i \mtwi_sda__core__i + connect \mtwi_sda__core__o \mtwi_sda__core__o + connect \mtwi_sda__core__oe \mtwi_sda__core__oe + connect \mtwi_sda__pad__i \mtwi_sda__pad__i + connect \mtwi_sda__pad__o \mtwi_sda__pad__o + connect \mtwi_sda__pad__oe \mtwi_sda__pad__oe + connect \pc_i \pc_i + connect \pc_i_ok \pc_i_ok + connect \pc_o \pc_o + connect \pwm_0__core__o \pwm_0__core__o + connect \pwm_0__pad__o \pwm_0__pad__o + connect \pwm_1__core__o \pwm_1__core__o + connect \pwm_1__pad__o \pwm_1__pad__o + connect \rst \rst + connect \sd0_clk__core__o \sd0_clk__core__o + connect \sd0_clk__pad__o \sd0_clk__pad__o + connect \sd0_cmd__core__i \sd0_cmd__core__i + connect \sd0_cmd__core__o \sd0_cmd__core__o + connect \sd0_cmd__core__oe \sd0_cmd__core__oe + connect \sd0_cmd__pad__i \sd0_cmd__pad__i + connect \sd0_cmd__pad__o \sd0_cmd__pad__o + connect \sd0_cmd__pad__oe \sd0_cmd__pad__oe + connect \sd0_data0__core__i \sd0_data0__core__i + connect \sd0_data0__core__o \sd0_data0__core__o + connect \sd0_data0__core__oe \sd0_data0__core__oe + connect \sd0_data0__pad__i \sd0_data0__pad__i + connect \sd0_data0__pad__o \sd0_data0__pad__o + connect \sd0_data0__pad__oe \sd0_data0__pad__oe + connect \sd0_data1__core__i \sd0_data1__core__i + connect \sd0_data1__core__o \sd0_data1__core__o + connect \sd0_data1__core__oe \sd0_data1__core__oe + connect \sd0_data1__pad__i \sd0_data1__pad__i + connect \sd0_data1__pad__o \sd0_data1__pad__o + connect \sd0_data1__pad__oe \sd0_data1__pad__oe + connect \sd0_data2__core__i \sd0_data2__core__i + connect \sd0_data2__core__o \sd0_data2__core__o + connect \sd0_data2__core__oe \sd0_data2__core__oe + connect \sd0_data2__pad__i \sd0_data2__pad__i + connect \sd0_data2__pad__o \sd0_data2__pad__o + connect \sd0_data2__pad__oe \sd0_data2__pad__oe + connect \sd0_data3__core__i \sd0_data3__core__i + connect \sd0_data3__core__o \sd0_data3__core__o + connect \sd0_data3__core__oe \sd0_data3__core__oe + connect \sd0_data3__pad__i \sd0_data3__pad__i + connect \sd0_data3__pad__o \sd0_data3__pad__o + connect \sd0_data3__pad__oe \sd0_data3__pad__oe + connect \sdr_a_0__core__o \sdr_a_0__core__o + connect \sdr_a_0__pad__o \sdr_a_0__pad__o + connect \sdr_a_10__core__o \sdr_a_10__core__o + connect \sdr_a_10__pad__o \sdr_a_10__pad__o + connect \sdr_a_11__core__o \sdr_a_11__core__o + connect \sdr_a_11__pad__o \sdr_a_11__pad__o + connect \sdr_a_12__core__o \sdr_a_12__core__o + connect \sdr_a_12__pad__o \sdr_a_12__pad__o + connect \sdr_a_1__core__o \sdr_a_1__core__o + connect \sdr_a_1__pad__o \sdr_a_1__pad__o + connect \sdr_a_2__core__o \sdr_a_2__core__o + connect \sdr_a_2__pad__o \sdr_a_2__pad__o + connect \sdr_a_3__core__o \sdr_a_3__core__o + connect \sdr_a_3__pad__o \sdr_a_3__pad__o + connect \sdr_a_4__core__o \sdr_a_4__core__o + connect \sdr_a_4__pad__o \sdr_a_4__pad__o + connect \sdr_a_5__core__o \sdr_a_5__core__o + connect \sdr_a_5__pad__o \sdr_a_5__pad__o + connect \sdr_a_6__core__o \sdr_a_6__core__o + connect \sdr_a_6__pad__o \sdr_a_6__pad__o + connect \sdr_a_7__core__o \sdr_a_7__core__o + connect \sdr_a_7__pad__o \sdr_a_7__pad__o + connect \sdr_a_8__core__o \sdr_a_8__core__o + connect \sdr_a_8__pad__o \sdr_a_8__pad__o + connect \sdr_a_9__core__o \sdr_a_9__core__o + connect \sdr_a_9__pad__o \sdr_a_9__pad__o + connect \sdr_ba_0__core__o \sdr_ba_0__core__o + connect \sdr_ba_0__pad__o \sdr_ba_0__pad__o + connect \sdr_ba_1__core__o \sdr_ba_1__core__o + connect \sdr_ba_1__pad__o \sdr_ba_1__pad__o + connect \sdr_cas_n__core__o \sdr_cas_n__core__o + connect \sdr_cas_n__pad__o \sdr_cas_n__pad__o + connect \sdr_cke__core__o \sdr_cke__core__o + connect \sdr_cke__pad__o \sdr_cke__pad__o + connect \sdr_clock__core__o \sdr_clock__core__o + connect \sdr_clock__pad__o \sdr_clock__pad__o + connect \sdr_cs_n__core__o \sdr_cs_n__core__o + connect \sdr_cs_n__pad__o \sdr_cs_n__pad__o + connect \sdr_dm_0__core__o \sdr_dm_0__core__o + connect \sdr_dm_0__pad__o \sdr_dm_0__pad__o + connect \sdr_dm_1__core__i \sdr_dm_1__core__i + connect \sdr_dm_1__core__o \sdr_dm_1__core__o + connect \sdr_dm_1__core__oe \sdr_dm_1__core__oe + connect \sdr_dm_1__pad__i \sdr_dm_1__pad__i + connect \sdr_dm_1__pad__o \sdr_dm_1__pad__o + connect \sdr_dm_1__pad__oe \sdr_dm_1__pad__oe + connect \sdr_dq_0__core__i \sdr_dq_0__core__i + connect \sdr_dq_0__core__o \sdr_dq_0__core__o + connect \sdr_dq_0__core__oe \sdr_dq_0__core__oe + connect \sdr_dq_0__pad__i \sdr_dq_0__pad__i + connect \sdr_dq_0__pad__o \sdr_dq_0__pad__o + connect \sdr_dq_0__pad__oe \sdr_dq_0__pad__oe + connect \sdr_dq_10__core__i \sdr_dq_10__core__i + connect \sdr_dq_10__core__o \sdr_dq_10__core__o + connect \sdr_dq_10__core__oe \sdr_dq_10__core__oe + connect \sdr_dq_10__pad__i \sdr_dq_10__pad__i + connect \sdr_dq_10__pad__o \sdr_dq_10__pad__o + connect \sdr_dq_10__pad__oe \sdr_dq_10__pad__oe + connect \sdr_dq_11__core__i \sdr_dq_11__core__i + connect \sdr_dq_11__core__o \sdr_dq_11__core__o + connect \sdr_dq_11__core__oe \sdr_dq_11__core__oe + connect \sdr_dq_11__pad__i \sdr_dq_11__pad__i + connect \sdr_dq_11__pad__o \sdr_dq_11__pad__o + connect \sdr_dq_11__pad__oe \sdr_dq_11__pad__oe + connect \sdr_dq_12__core__i \sdr_dq_12__core__i + connect \sdr_dq_12__core__o \sdr_dq_12__core__o + connect \sdr_dq_12__core__oe \sdr_dq_12__core__oe + connect \sdr_dq_12__pad__i \sdr_dq_12__pad__i + connect \sdr_dq_12__pad__o \sdr_dq_12__pad__o + connect \sdr_dq_12__pad__oe \sdr_dq_12__pad__oe + connect \sdr_dq_13__core__i \sdr_dq_13__core__i + connect \sdr_dq_13__core__o \sdr_dq_13__core__o + connect \sdr_dq_13__core__oe \sdr_dq_13__core__oe + connect \sdr_dq_13__pad__i \sdr_dq_13__pad__i + connect \sdr_dq_13__pad__o \sdr_dq_13__pad__o + connect \sdr_dq_13__pad__oe \sdr_dq_13__pad__oe + connect \sdr_dq_14__core__i \sdr_dq_14__core__i + connect \sdr_dq_14__core__o \sdr_dq_14__core__o + connect \sdr_dq_14__core__oe \sdr_dq_14__core__oe + connect \sdr_dq_14__pad__i \sdr_dq_14__pad__i + connect \sdr_dq_14__pad__o \sdr_dq_14__pad__o + connect \sdr_dq_14__pad__oe \sdr_dq_14__pad__oe + connect \sdr_dq_15__core__i \sdr_dq_15__core__i + connect \sdr_dq_15__core__o \sdr_dq_15__core__o + connect \sdr_dq_15__core__oe \sdr_dq_15__core__oe + connect \sdr_dq_15__pad__i \sdr_dq_15__pad__i + connect \sdr_dq_15__pad__o \sdr_dq_15__pad__o + connect \sdr_dq_15__pad__oe \sdr_dq_15__pad__oe + connect \sdr_dq_1__core__i \sdr_dq_1__core__i + connect \sdr_dq_1__core__o \sdr_dq_1__core__o + connect \sdr_dq_1__core__oe \sdr_dq_1__core__oe + connect \sdr_dq_1__pad__i \sdr_dq_1__pad__i + connect \sdr_dq_1__pad__o \sdr_dq_1__pad__o + connect \sdr_dq_1__pad__oe \sdr_dq_1__pad__oe + connect \sdr_dq_2__core__i \sdr_dq_2__core__i + connect \sdr_dq_2__core__o \sdr_dq_2__core__o + connect \sdr_dq_2__core__oe \sdr_dq_2__core__oe + connect \sdr_dq_2__pad__i \sdr_dq_2__pad__i + connect \sdr_dq_2__pad__o \sdr_dq_2__pad__o + connect \sdr_dq_2__pad__oe \sdr_dq_2__pad__oe + connect \sdr_dq_3__core__i \sdr_dq_3__core__i + connect \sdr_dq_3__core__o \sdr_dq_3__core__o + connect \sdr_dq_3__core__oe \sdr_dq_3__core__oe + connect \sdr_dq_3__pad__i \sdr_dq_3__pad__i + connect \sdr_dq_3__pad__o \sdr_dq_3__pad__o + connect \sdr_dq_3__pad__oe \sdr_dq_3__pad__oe + connect \sdr_dq_4__core__i \sdr_dq_4__core__i + connect \sdr_dq_4__core__o \sdr_dq_4__core__o + connect \sdr_dq_4__core__oe \sdr_dq_4__core__oe + connect \sdr_dq_4__pad__i \sdr_dq_4__pad__i + connect \sdr_dq_4__pad__o \sdr_dq_4__pad__o + connect \sdr_dq_4__pad__oe \sdr_dq_4__pad__oe + connect \sdr_dq_5__core__i \sdr_dq_5__core__i + connect \sdr_dq_5__core__o \sdr_dq_5__core__o + connect \sdr_dq_5__core__oe \sdr_dq_5__core__oe + connect \sdr_dq_5__pad__i \sdr_dq_5__pad__i + connect \sdr_dq_5__pad__o \sdr_dq_5__pad__o + connect \sdr_dq_5__pad__oe \sdr_dq_5__pad__oe + connect \sdr_dq_6__core__i \sdr_dq_6__core__i + connect \sdr_dq_6__core__o \sdr_dq_6__core__o + connect \sdr_dq_6__core__oe \sdr_dq_6__core__oe + connect \sdr_dq_6__pad__i \sdr_dq_6__pad__i + connect \sdr_dq_6__pad__o \sdr_dq_6__pad__o + connect \sdr_dq_6__pad__oe \sdr_dq_6__pad__oe + connect \sdr_dq_7__core__i \sdr_dq_7__core__i + connect \sdr_dq_7__core__o \sdr_dq_7__core__o + connect \sdr_dq_7__core__oe \sdr_dq_7__core__oe + connect \sdr_dq_7__pad__i \sdr_dq_7__pad__i + connect \sdr_dq_7__pad__o \sdr_dq_7__pad__o + connect \sdr_dq_7__pad__oe \sdr_dq_7__pad__oe + connect \sdr_dq_8__core__i \sdr_dq_8__core__i + connect \sdr_dq_8__core__o \sdr_dq_8__core__o + connect \sdr_dq_8__core__oe \sdr_dq_8__core__oe + connect \sdr_dq_8__pad__i \sdr_dq_8__pad__i + connect \sdr_dq_8__pad__o \sdr_dq_8__pad__o + connect \sdr_dq_8__pad__oe \sdr_dq_8__pad__oe + connect \sdr_dq_9__core__i \sdr_dq_9__core__i + connect \sdr_dq_9__core__o \sdr_dq_9__core__o + connect \sdr_dq_9__core__oe \sdr_dq_9__core__oe + connect \sdr_dq_9__pad__i \sdr_dq_9__pad__i + connect \sdr_dq_9__pad__o \sdr_dq_9__pad__o + connect \sdr_dq_9__pad__oe \sdr_dq_9__pad__oe + connect \sdr_ras_n__core__o \sdr_ras_n__core__o + connect \sdr_ras_n__pad__o \sdr_ras_n__pad__o + connect \sdr_we_n__core__o \sdr_we_n__core__o + connect \sdr_we_n__pad__o \sdr_we_n__pad__o + connect \sram4k_0__ack \sram4k_0__ack + connect \sram4k_0__adr \sram4k_0__adr + connect \sram4k_0__cyc \sram4k_0__cyc + connect \sram4k_0__dat_r \sram4k_0__dat_r + connect \sram4k_0__dat_w \sram4k_0__dat_w + connect \sram4k_0__sel \sram4k_0__sel + connect \sram4k_0__stb \sram4k_0__stb + connect \sram4k_0__we \sram4k_0__we + connect \sram4k_1__ack \sram4k_1__ack + connect \sram4k_1__adr \sram4k_1__adr + connect \sram4k_1__cyc \sram4k_1__cyc + connect \sram4k_1__dat_r \sram4k_1__dat_r + connect \sram4k_1__dat_w \sram4k_1__dat_w + connect \sram4k_1__sel \sram4k_1__sel + connect \sram4k_1__stb \sram4k_1__stb + connect \sram4k_1__we \sram4k_1__we + connect \sram4k_2__ack \sram4k_2__ack + connect \sram4k_2__adr \sram4k_2__adr + connect \sram4k_2__cyc \sram4k_2__cyc + connect \sram4k_2__dat_r \sram4k_2__dat_r + connect \sram4k_2__dat_w \sram4k_2__dat_w + connect \sram4k_2__sel \sram4k_2__sel + connect \sram4k_2__stb \sram4k_2__stb + connect \sram4k_2__we \sram4k_2__we + connect \sram4k_3__ack \sram4k_3__ack + connect \sram4k_3__adr \sram4k_3__adr + connect \sram4k_3__cyc \sram4k_3__cyc + connect \sram4k_3__dat_r \sram4k_3__dat_r + connect \sram4k_3__dat_w \sram4k_3__dat_w + connect \sram4k_3__sel \sram4k_3__sel + connect \sram4k_3__stb \sram4k_3__stb + connect \sram4k_3__we \sram4k_3__we + end + connect \ti_coresync_clk \pll_clk_pll_o + connect \pllclk_rst \rst + connect \pll_18_o \pll_pll_18_o + connect \pll_clk_24_i \clk + connect \pllclk_clk \pll_clk_pll_o +end +attribute \src "libresoc.v:198205.1-202906.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti" +attribute \generator "nMigen" +module \ti + attribute \src "libresoc.v:202743.3-202858.6" + wire width 8 $0\core_asmcode$next[7:0]$14161 + attribute \src "libresoc.v:200667.3-200668.41" + wire width 8 $0\core_asmcode[7:0] + attribute \src "libresoc.v:201555.3-201584.6" + wire $0\core_bigendian_i$10$next[0:0]$13962 + attribute \src "libresoc.v:200797.3-200798.57" + wire $0\core_bigendian_i$10[0:0]$13886 + attribute \src "libresoc.v:198404.7-198404.35" + wire $0\core_bigendian_i$10[0:0]$14433 + attribute \src "libresoc.v:201984.3-201996.6" + wire width 3 $0\core_cia__ren[2:0] + attribute \src "libresoc.v:202743.3-202858.6" + wire width 64 $0\core_core_core_cia$next[63:0]$14162 + attribute \src "libresoc.v:200741.3-200742.53" + wire width 64 $0\core_core_core_cia[63:0] + attribute \src "libresoc.v:202743.3-202858.6" + wire width 8 $0\core_core_core_cr_rd$next[7:0]$14163 + attribute \src "libresoc.v:200785.3-200786.57" + wire width 8 $0\core_core_core_cr_rd[7:0] + attribute \src "libresoc.v:202743.3-202858.6" + wire $0\core_core_core_cr_rd_ok$next[0:0]$14164 + attribute \src "libresoc.v:200787.3-200788.63" + wire $0\core_core_core_cr_rd_ok[0:0] + attribute \src "libresoc.v:202743.3-202858.6" + wire width 8 $0\core_core_core_cr_wr$next[7:0]$14165 + attribute \src "libresoc.v:200789.3-200790.57" + wire width 8 $0\core_core_core_cr_wr[7:0] + attribute \src "libresoc.v:202743.3-202858.6" + wire $0\core_core_core_exc_$signal$3$next[0:0]$14166 + attribute \src "libresoc.v:200767.3-200768.75" + wire $0\core_core_core_exc_$signal$3[0:0]$13864 + attribute \src "libresoc.v:198430.7-198430.44" + wire $0\core_core_core_exc_$signal$3[0:0]$14441 + attribute \src "libresoc.v:202743.3-202858.6" + wire $0\core_core_core_exc_$signal$4$next[0:0]$14167 + attribute \src "libresoc.v:200769.3-200770.75" + wire $0\core_core_core_exc_$signal$4[0:0]$13866 + attribute \src "libresoc.v:198434.7-198434.44" + wire $0\core_core_core_exc_$signal$4[0:0]$14443 + attribute \src "libresoc.v:202743.3-202858.6" + wire $0\core_core_core_exc_$signal$5$next[0:0]$14168 + attribute \src "libresoc.v:200771.3-200772.75" + wire $0\core_core_core_exc_$signal$5[0:0]$13868 + attribute \src "libresoc.v:198438.7-198438.44" + wire $0\core_core_core_exc_$signal$5[0:0]$14445 + attribute \src "libresoc.v:202743.3-202858.6" + wire $0\core_core_core_exc_$signal$6$next[0:0]$14169 + attribute \src "libresoc.v:200773.3-200774.75" + wire $0\core_core_core_exc_$signal$6[0:0]$13870 + attribute \src "libresoc.v:198442.7-198442.44" + wire $0\core_core_core_exc_$signal$6[0:0]$14447 + attribute \src "libresoc.v:202743.3-202858.6" + wire $0\core_core_core_exc_$signal$7$next[0:0]$14170 + attribute \src "libresoc.v:200777.3-200778.75" + wire $0\core_core_core_exc_$signal$7[0:0]$13873 + attribute \src "libresoc.v:198446.7-198446.44" + wire $0\core_core_core_exc_$signal$7[0:0]$14449 + attribute \src "libresoc.v:202743.3-202858.6" + wire $0\core_core_core_exc_$signal$8$next[0:0]$14171 + attribute \src "libresoc.v:200779.3-200780.75" + wire $0\core_core_core_exc_$signal$8[0:0]$13875 + attribute \src "libresoc.v:198450.7-198450.44" + wire $0\core_core_core_exc_$signal$8[0:0]$14451 + attribute \src "libresoc.v:202743.3-202858.6" + wire $0\core_core_core_exc_$signal$9$next[0:0]$14172 + attribute \src "libresoc.v:200781.3-200782.75" + wire $0\core_core_core_exc_$signal$9[0:0]$13877 + attribute \src "libresoc.v:198454.7-198454.44" + wire $0\core_core_core_exc_$signal$9[0:0]$14453 + attribute \src "libresoc.v:202743.3-202858.6" + wire $0\core_core_core_exc_$signal$next[0:0]$14173 + attribute \src "libresoc.v:200765.3-200766.71" + wire $0\core_core_core_exc_$signal[0:0]$13862 + attribute \src "libresoc.v:198428.7-198428.42" + wire $0\core_core_core_exc_$signal[0:0]$14439 + attribute \src "libresoc.v:202743.3-202858.6" + wire width 13 $0\core_core_core_fn_unit$next[12:0]$14174 + attribute \src "libresoc.v:200747.3-200748.61" + wire width 13 $0\core_core_core_fn_unit[12:0] + attribute \src "libresoc.v:202743.3-202858.6" + wire width 2 $0\core_core_core_input_carry$next[1:0]$14175 + attribute \src "libresoc.v:200761.3-200762.69" + wire width 2 $0\core_core_core_input_carry[1:0] + attribute \src "libresoc.v:202743.3-202858.6" + wire width 32 $0\core_core_core_insn$next[31:0]$14176 + attribute \src "libresoc.v:200743.3-200744.55" + wire width 32 $0\core_core_core_insn[31:0] + attribute \src "libresoc.v:202743.3-202858.6" + wire width 7 $0\core_core_core_insn_type$next[6:0]$14177 + attribute \src "libresoc.v:200745.3-200746.65" + wire width 7 $0\core_core_core_insn_type[6:0] + attribute \src "libresoc.v:202743.3-202858.6" + wire $0\core_core_core_is_32bit$next[0:0]$14178 + attribute \src "libresoc.v:200793.3-200794.63" + wire $0\core_core_core_is_32bit[0:0] + attribute \src "libresoc.v:202743.3-202858.6" + wire width 64 $0\core_core_core_msr$next[63:0]$14179 + attribute \src "libresoc.v:200739.3-200740.53" + wire width 64 $0\core_core_core_msr[63:0] + attribute \src "libresoc.v:202743.3-202858.6" + wire $0\core_core_core_oe$next[0:0]$14180 + attribute \src "libresoc.v:200757.3-200758.51" + wire $0\core_core_core_oe[0:0] + attribute \src "libresoc.v:202743.3-202858.6" + wire $0\core_core_core_oe_ok$next[0:0]$14181 + attribute \src "libresoc.v:200759.3-200760.57" + wire $0\core_core_core_oe_ok[0:0] + attribute \src "libresoc.v:202743.3-202858.6" + wire $0\core_core_core_rc$next[0:0]$14182 + attribute \src "libresoc.v:200751.3-200752.51" + wire $0\core_core_core_rc[0:0] + attribute \src "libresoc.v:202743.3-202858.6" + wire $0\core_core_core_rc_ok$next[0:0]$14183 + attribute \src "libresoc.v:200755.3-200756.57" + wire $0\core_core_core_rc_ok[0:0] + attribute \src "libresoc.v:202743.3-202858.6" + wire width 13 $0\core_core_core_trapaddr$next[12:0]$14184 + attribute \src "libresoc.v:200783.3-200784.63" + wire width 13 $0\core_core_core_trapaddr[12:0] + attribute \src "libresoc.v:202743.3-202858.6" + wire width 8 $0\core_core_core_traptype$next[7:0]$14185 + attribute \src "libresoc.v:200763.3-200764.63" + wire width 8 $0\core_core_core_traptype[7:0] + attribute \src "libresoc.v:202743.3-202858.6" + wire width 7 $0\core_core_cr_in1$next[6:0]$14186 + attribute \src "libresoc.v:200721.3-200722.49" + wire width 7 $0\core_core_cr_in1[6:0] + attribute \src "libresoc.v:202743.3-202858.6" + wire $0\core_core_cr_in1_ok$next[0:0]$14187 + attribute \src "libresoc.v:200723.3-200724.55" + wire $0\core_core_cr_in1_ok[0:0] + attribute \src "libresoc.v:202743.3-202858.6" + wire width 7 $0\core_core_cr_in2$1$next[6:0]$14188 + attribute \src "libresoc.v:200729.3-200730.55" + wire width 7 $0\core_core_cr_in2$1[6:0]$13842 + attribute \src "libresoc.v:198610.13-198610.41" + wire width 7 $0\core_core_cr_in2$1[6:0]$14470 + attribute \src "libresoc.v:202743.3-202858.6" + wire width 7 $0\core_core_cr_in2$next[6:0]$14189 + attribute \src "libresoc.v:200725.3-200726.49" + wire width 7 $0\core_core_cr_in2[6:0] + attribute \src "libresoc.v:202743.3-202858.6" + wire $0\core_core_cr_in2_ok$2$next[0:0]$14190 + attribute \src "libresoc.v:200733.3-200734.61" + wire $0\core_core_cr_in2_ok$2[0:0]$13845 + attribute \src "libresoc.v:198618.7-198618.37" + wire $0\core_core_cr_in2_ok$2[0:0]$14473 + attribute \src "libresoc.v:202743.3-202858.6" + wire $0\core_core_cr_in2_ok$next[0:0]$14191 + attribute \src "libresoc.v:200727.3-200728.55" + wire $0\core_core_cr_in2_ok[0:0] + attribute \src "libresoc.v:202743.3-202858.6" + wire width 7 $0\core_core_cr_out$next[6:0]$14192 + attribute \src "libresoc.v:200735.3-200736.49" + wire width 7 $0\core_core_cr_out[6:0] + attribute \src "libresoc.v:202743.3-202858.6" + wire $0\core_core_cr_wr_ok$next[0:0]$14193 + attribute \src "libresoc.v:200791.3-200792.53" + wire $0\core_core_cr_wr_ok[0:0] + attribute \src "libresoc.v:201484.3-201524.6" + wire width 7 $0\core_core_dststep$next[6:0]$13915 + attribute \src "libresoc.v:200657.3-200658.51" + wire width 7 $0\core_core_dststep[6:0] + attribute \src "libresoc.v:202743.3-202858.6" + wire width 7 $0\core_core_ea$next[6:0]$14194 + attribute \src "libresoc.v:200673.3-200674.41" + wire width 7 $0\core_core_ea[6:0] + attribute \src "libresoc.v:202743.3-202858.6" + wire width 3 $0\core_core_fast1$next[2:0]$14195 + attribute \src "libresoc.v:200703.3-200704.47" + wire width 3 $0\core_core_fast1[2:0] + attribute \src "libresoc.v:202743.3-202858.6" + wire $0\core_core_fast1_ok$next[0:0]$14196 + attribute \src "libresoc.v:200705.3-200706.53" + wire $0\core_core_fast1_ok[0:0] + attribute \src "libresoc.v:202743.3-202858.6" + wire width 3 $0\core_core_fast2$next[2:0]$14197 + attribute \src "libresoc.v:200707.3-200708.47" + wire width 3 $0\core_core_fast2[2:0] + attribute \src "libresoc.v:202743.3-202858.6" + wire $0\core_core_fast2_ok$next[0:0]$14198 + attribute \src "libresoc.v:200711.3-200712.53" + wire $0\core_core_fast2_ok[0:0] + attribute \src "libresoc.v:202743.3-202858.6" + wire width 3 $0\core_core_fasto1$next[2:0]$14199 + attribute \src "libresoc.v:200713.3-200714.49" + wire width 3 $0\core_core_fasto1[2:0] + attribute \src "libresoc.v:202743.3-202858.6" + wire width 3 $0\core_core_fasto2$next[2:0]$14200 + attribute \src "libresoc.v:200717.3-200718.49" + wire width 3 $0\core_core_fasto2[2:0] + attribute \src "libresoc.v:202743.3-202858.6" + wire $0\core_core_lk$next[0:0]$14201 + attribute \src "libresoc.v:200749.3-200750.41" + wire $0\core_core_lk[0:0] + attribute \src "libresoc.v:201484.3-201524.6" + wire width 7 $0\core_core_maxvl$next[6:0]$13916 + attribute \src "libresoc.v:200663.3-200664.47" + wire width 7 $0\core_core_maxvl[6:0] + attribute \src "libresoc.v:201484.3-201524.6" + wire width 64 $0\core_core_pc$next[63:0]$13917 + attribute \src "libresoc.v:200625.3-200626.41" + wire width 64 $0\core_core_pc[63:0] + attribute \src "libresoc.v:202743.3-202858.6" + wire width 7 $0\core_core_reg1$next[6:0]$14202 + attribute \src "libresoc.v:200677.3-200678.45" + wire width 7 $0\core_core_reg1[6:0] + attribute \src "libresoc.v:202743.3-202858.6" + wire $0\core_core_reg1_ok$next[0:0]$14203 + attribute \src "libresoc.v:200679.3-200680.51" + wire $0\core_core_reg1_ok[0:0] + attribute \src "libresoc.v:202743.3-202858.6" + wire width 7 $0\core_core_reg2$next[6:0]$14204 + attribute \src "libresoc.v:200681.3-200682.45" + wire width 7 $0\core_core_reg2[6:0] + attribute \src "libresoc.v:202743.3-202858.6" + wire $0\core_core_reg2_ok$next[0:0]$14205 + attribute \src "libresoc.v:200683.3-200684.51" + wire $0\core_core_reg2_ok[0:0] + attribute \src "libresoc.v:202743.3-202858.6" + wire width 7 $0\core_core_reg3$next[6:0]$14206 + attribute \src "libresoc.v:200685.3-200686.45" + wire width 7 $0\core_core_reg3[6:0] + attribute \src "libresoc.v:202743.3-202858.6" + wire $0\core_core_reg3_ok$next[0:0]$14207 + attribute \src "libresoc.v:200689.3-200690.51" + wire $0\core_core_reg3_ok[0:0] + attribute \src "libresoc.v:202743.3-202858.6" + wire width 7 $0\core_core_rego$next[6:0]$14208 + attribute \src "libresoc.v:200669.3-200670.45" + wire width 7 $0\core_core_rego[6:0] + attribute \src "libresoc.v:202743.3-202858.6" + wire width 10 $0\core_core_spr1$next[9:0]$14209 + attribute \src "libresoc.v:200695.3-200696.45" + wire width 10 $0\core_core_spr1[9:0] + attribute \src "libresoc.v:202743.3-202858.6" + wire $0\core_core_spr1_ok$next[0:0]$14210 + attribute \src "libresoc.v:200697.3-200698.51" + wire $0\core_core_spr1_ok[0:0] + attribute \src "libresoc.v:202743.3-202858.6" + wire width 10 $0\core_core_spro$next[9:0]$14211 + attribute \src "libresoc.v:200691.3-200692.45" + wire width 10 $0\core_core_spro[9:0] + attribute \src "libresoc.v:201484.3-201524.6" + wire width 7 $0\core_core_srcstep$next[6:0]$13918 + attribute \src "libresoc.v:200659.3-200660.51" + wire width 7 $0\core_core_srcstep[6:0] + attribute \src "libresoc.v:201484.3-201524.6" + wire width 2 $0\core_core_subvl$next[1:0]$13919 + attribute \src "libresoc.v:200655.3-200656.47" + wire width 2 $0\core_core_subvl[1:0] + attribute \src "libresoc.v:201484.3-201524.6" + wire width 2 $0\core_core_svstep$next[1:0]$13920 + attribute \src "libresoc.v:200653.3-200654.49" + wire width 2 $0\core_core_svstep[1:0] + attribute \src "libresoc.v:201484.3-201524.6" + wire width 7 $0\core_core_vl$next[6:0]$13921 + attribute \src "libresoc.v:200661.3-200662.41" + wire width 7 $0\core_core_vl[6:0] + attribute \src "libresoc.v:202743.3-202858.6" + wire width 3 $0\core_core_xer_in$next[2:0]$14212 + attribute \src "libresoc.v:200699.3-200700.49" + wire width 3 $0\core_core_xer_in[2:0] + attribute \src "libresoc.v:202743.3-202858.6" + wire $0\core_cr_out_ok$next[0:0]$14213 + attribute \src "libresoc.v:200737.3-200738.45" + wire $0\core_cr_out_ok[0:0] + attribute \src "libresoc.v:201672.3-201681.6" + wire width 64 $0\core_data_i$12[63:0]$13983 + attribute \src "libresoc.v:202018.3-202038.6" + wire width 64 $0\core_data_i[63:0] + attribute \src "libresoc.v:201484.3-201524.6" + wire width 64 $0\core_dec$next[63:0]$13922 + attribute \src "libresoc.v:200651.3-200652.33" + wire width 64 $0\core_dec[63:0] + attribute \src "libresoc.v:201682.3-201691.6" + wire width 5 $0\core_dmi__addr[4:0] + attribute \src "libresoc.v:201692.3-201701.6" + wire $0\core_dmi__ren[0:0] + attribute \src "libresoc.v:202743.3-202858.6" + wire $0\core_ea_ok$next[0:0]$14214 + attribute \src "libresoc.v:200675.3-200676.37" + wire $0\core_ea_ok[0:0] + attribute \src "libresoc.v:201484.3-201524.6" + wire $0\core_eint$next[0:0]$13923 + attribute \src "libresoc.v:200649.3-200650.35" + wire $0\core_eint[0:0] + attribute \src "libresoc.v:202743.3-202858.6" + wire $0\core_fasto1_ok$next[0:0]$14215 + attribute \src "libresoc.v:200715.3-200716.45" + wire $0\core_fasto1_ok[0:0] + attribute \src "libresoc.v:202743.3-202858.6" + wire $0\core_fasto2_ok$next[0:0]$14216 + attribute \src "libresoc.v:200719.3-200720.45" + wire $0\core_fasto2_ok[0:0] + attribute \src "libresoc.v:201731.3-201740.6" + wire width 8 $0\core_full_rd2__ren[7:0] + attribute \src "libresoc.v:201770.3-201779.6" + wire width 3 $0\core_full_rd__ren[2:0] + attribute \src "libresoc.v:201878.3-201892.6" + wire width 3 $0\core_issue__addr$13[2:0]$14012 + attribute \src "libresoc.v:201809.3-201823.6" + wire width 3 $0\core_issue__addr[2:0] + attribute \src "libresoc.v:201908.3-201922.6" + wire width 64 $0\core_issue__data_i[63:0] + attribute \src "libresoc.v:201824.3-201838.6" + wire $0\core_issue__ren[0:0] + attribute \src "libresoc.v:201893.3-201907.6" + wire $0\core_issue__wen[0:0] + attribute \src "libresoc.v:201626.3-201636.6" + wire $0\core_issue_i[0:0] + attribute \src "libresoc.v:201606.3-201625.6" + wire $0\core_ivalid_i[0:0] + attribute \src "libresoc.v:201484.3-201524.6" + wire width 64 $0\core_msr$next[63:0]$13924 + attribute \src "libresoc.v:200647.3-200648.33" + wire width 64 $0\core_msr[63:0] + attribute \src "libresoc.v:202060.3-202080.6" + wire width 3 $0\core_msr__ren[2:0] + attribute \src "libresoc.v:201525.3-201554.6" + wire width 32 $0\core_raw_insn_i$next[31:0]$13956 + attribute \src "libresoc.v:200819.3-200820.47" + wire width 32 $0\core_raw_insn_i[31:0] + attribute \src "libresoc.v:202743.3-202858.6" + wire $0\core_rego_ok$next[0:0]$14217 + attribute \src "libresoc.v:200671.3-200672.41" + wire $0\core_rego_ok[0:0] + attribute \src "libresoc.v:202743.3-202858.6" + wire $0\core_spro_ok$next[0:0]$14218 + attribute \src "libresoc.v:200693.3-200694.41" + wire $0\core_spro_ok[0:0] + attribute \src "libresoc.v:202410.3-202428.6" + wire $0\core_stopped_i[0:0] + attribute \src "libresoc.v:202039.3-202059.6" + wire width 3 $0\core_sv__ren[2:0] + attribute \src "libresoc.v:201662.3-201671.6" + wire width 3 $0\core_wen$11[2:0]$13980 + attribute \src "libresoc.v:201997.3-202017.6" + wire width 3 $0\core_wen[2:0] + attribute \src "libresoc.v:202743.3-202858.6" + wire $0\core_xer_out$next[0:0]$14219 + attribute \src "libresoc.v:200701.3-200702.41" + wire $0\core_xer_out[0:0] + attribute \src "libresoc.v:200629.3-200630.43" + wire $0\cu_st__rel_o_dly[0:0] + attribute \src "libresoc.v:202478.3-202510.6" + wire width 7 $0\cur_cur_dststep$next[6:0]$14081 + attribute \src "libresoc.v:200823.3-200824.47" + wire width 7 $0\cur_cur_dststep[6:0] + attribute \src "libresoc.v:202478.3-202510.6" + wire width 7 $0\cur_cur_maxvl$next[6:0]$14082 + attribute \src "libresoc.v:200829.3-200830.43" + wire width 7 $0\cur_cur_maxvl[6:0] + attribute \src "libresoc.v:202478.3-202510.6" + wire width 2 $0\cur_cur_subvl$next[1:0]$14083 + attribute \src "libresoc.v:200821.3-200822.43" + wire width 2 $0\cur_cur_subvl[1:0] + attribute \src "libresoc.v:202478.3-202510.6" + wire width 2 $0\cur_cur_svstep$next[1:0]$14084 + attribute \src "libresoc.v:200817.3-200818.45" + wire width 2 $0\cur_cur_svstep[1:0] + attribute \src "libresoc.v:202478.3-202510.6" + wire width 7 $0\cur_cur_vl$next[6:0]$14085 + attribute \src "libresoc.v:200827.3-200828.37" + wire width 7 $0\cur_cur_vl[6:0] + attribute \src "libresoc.v:201741.3-201749.6" + wire $0\d_cr_delay$next[0:0]$13994 + attribute \src "libresoc.v:200709.3-200710.37" + wire $0\d_cr_delay[0:0] + attribute \src "libresoc.v:201702.3-201710.6" + wire $0\d_reg_delay$next[0:0]$13988 + attribute \src "libresoc.v:200731.3-200732.39" + wire $0\d_reg_delay[0:0] + attribute \src "libresoc.v:201780.3-201788.6" + wire $0\d_xer_delay$next[0:0]$14000 + attribute \src "libresoc.v:200687.3-200688.39" + wire $0\d_xer_delay[0:0] + attribute \src "libresoc.v:202429.3-202447.6" + wire $0\dbg_core_stopped_i[0:0] + attribute \src "libresoc.v:201760.3-201769.6" + wire $0\dbg_d_cr_ack[0:0] + attribute \src "libresoc.v:201750.3-201759.6" + wire width 64 $0\dbg_d_cr_data[63:0] + attribute \src "libresoc.v:201721.3-201730.6" + wire $0\dbg_d_gpr_ack[0:0] + attribute \src "libresoc.v:201711.3-201720.6" + wire width 64 $0\dbg_d_gpr_data[63:0] + attribute \src "libresoc.v:201799.3-201808.6" + wire $0\dbg_d_xer_ack[0:0] + attribute \src "libresoc.v:201789.3-201798.6" + wire width 64 $0\dbg_d_xer_data[63:0] + attribute \src "libresoc.v:201466.3-201474.6" + wire width 4 $0\dbg_dmi_addr_i$next[3:0]$13909 + attribute \src "libresoc.v:200645.3-200646.45" + wire width 4 $0\dbg_dmi_addr_i[3:0] + attribute \src "libresoc.v:202081.3-202089.6" + wire width 64 $0\dbg_dmi_din$next[63:0]$14034 + attribute \src "libresoc.v:200639.3-200640.39" + wire width 64 $0\dbg_dmi_din[63:0] + attribute \src "libresoc.v:201475.3-201483.6" + wire $0\dbg_dmi_req_i$next[0:0]$13912 + attribute \src "libresoc.v:200643.3-200644.43" + wire $0\dbg_dmi_req_i[0:0] + attribute \src "libresoc.v:201950.3-201958.6" + wire $0\dbg_dmi_we_i$next[0:0]$14022 + attribute \src "libresoc.v:200641.3-200642.41" + wire $0\dbg_dmi_we_i[0:0] + attribute \src "libresoc.v:202478.3-202510.6" + wire width 7 $0\dec2_cur_cur_srcstep$next[6:0]$14086 + attribute \src "libresoc.v:200825.3-200826.57" + wire width 7 $0\dec2_cur_cur_srcstep[6:0] + attribute \src "libresoc.v:201923.3-201938.6" + wire width 64 $0\dec2_cur_dec$next[63:0]$14017 + attribute \src "libresoc.v:200623.3-200624.41" + wire width 64 $0\dec2_cur_dec[63:0] + attribute \src "libresoc.v:202859.3-202867.6" + wire $0\dec2_cur_eint$next[0:0]$14425 + attribute \src "libresoc.v:200633.3-200634.43" + wire $0\dec2_cur_eint[0:0] + attribute \src "libresoc.v:202457.3-202477.6" + wire width 64 $0\dec2_cur_msr$next[63:0]$14076 + attribute \src "libresoc.v:200831.3-200832.41" + wire width 64 $0\dec2_cur_msr[63:0] + attribute \src "libresoc.v:202247.3-202272.6" + wire width 64 $0\dec2_cur_pc$next[63:0]$14041 + attribute \src "libresoc.v:200839.3-200840.39" + wire width 64 $0\dec2_cur_pc[63:0] + attribute \src "libresoc.v:202549.3-202586.6" + wire width 9 $0\dec2_dec_svp64__extra$next[8:0]$14108 + attribute \src "libresoc.v:200805.3-200806.59" + wire width 9 $0\dec2_dec_svp64__extra[8:0] + attribute \src "libresoc.v:202727.3-202742.6" + wire width 32 $0\dec2_raw_opcode_in[31:0] + attribute \src "libresoc.v:202549.3-202586.6" + wire width 2 $0\dec_svp64__elwidth$next[1:0]$14109 + attribute \src "libresoc.v:200811.3-200812.53" + wire width 2 $0\dec_svp64__elwidth[1:0] + attribute \src "libresoc.v:202549.3-202586.6" + wire width 2 $0\dec_svp64__ewsrc$next[1:0]$14110 + attribute \src "libresoc.v:200809.3-200810.49" + wire width 2 $0\dec_svp64__ewsrc[1:0] + attribute \src "libresoc.v:202549.3-202586.6" + wire width 3 $0\dec_svp64__mask$next[2:0]$14111 + attribute \src "libresoc.v:200813.3-200814.47" + wire width 3 $0\dec_svp64__mask[2:0] + attribute \src "libresoc.v:202549.3-202586.6" + wire $0\dec_svp64__mmode$next[0:0]$14112 + attribute \src "libresoc.v:200815.3-200816.49" + wire $0\dec_svp64__mmode[0:0] + attribute \src "libresoc.v:202549.3-202586.6" + wire width 5 $0\dec_svp64__mode$next[4:0]$14113 + attribute \src "libresoc.v:200803.3-200804.47" + wire width 5 $0\dec_svp64__mode[4:0] + attribute \src "libresoc.v:202549.3-202586.6" + wire width 2 $0\dec_svp64__subvl$next[1:0]$14114 + attribute \src "libresoc.v:200807.3-200808.49" + wire width 2 $0\dec_svp64__subvl[1:0] + attribute \src "libresoc.v:202868.3-202877.6" + wire width 2 $0\delay$next[1:0]$14428 + attribute \src "libresoc.v:200631.3-200632.27" + wire width 2 $0\delay[1:0] + attribute \src "libresoc.v:202343.3-202409.6" + wire width 2 $0\fetch_fsm_state$next[1:0]$14061 + attribute \src "libresoc.v:200833.3-200834.47" + wire width 2 $0\fetch_fsm_state[1:0] + attribute \src "libresoc.v:202615.3-202650.6" + wire width 32 $0\fetch_insn_o$next[31:0]$14144 + attribute \src "libresoc.v:200799.3-200800.41" + wire width 32 $0\fetch_insn_o[31:0] + attribute \src "libresoc.v:202716.3-202726.6" + wire $0\fetch_insn_ready_i[0:0] + attribute \src "libresoc.v:202651.3-202661.6" + wire $0\fetch_insn_valid_o[0:0] + attribute \src "libresoc.v:202090.3-202105.6" + wire $0\fetch_pc_ready_o[0:0] + attribute \src "libresoc.v:202662.3-202672.6" + wire $0\fetch_pc_valid_i[0:0] + attribute \src "libresoc.v:201839.3-201866.6" + wire width 2 $0\fsm_state$188$next[1:0]$14007 + attribute \src "libresoc.v:200665.3-200666.45" + wire width 2 $0\fsm_state$188[1:0]$13809 + attribute \src "libresoc.v:199704.13-199704.35" + wire width 2 $0\fsm_state$188[1:0]$14543 + attribute \src "libresoc.v:202673.3-202715.6" + wire width 2 $0\fsm_state$next[1:0]$14152 + attribute \src "libresoc.v:200795.3-200796.35" + wire width 2 $0\fsm_state[1:0] + attribute \src "libresoc.v:201585.3-201605.6" + wire width 32 $0\ilatch$next[31:0]$13968 + attribute \src "libresoc.v:200775.3-200776.29" + wire width 32 $0\ilatch[31:0] + attribute \src "libresoc.v:202106.3-202146.6" + wire width 48 $0\imem_a_pc_i[47:0] + attribute \src "libresoc.v:202147.3-202196.6" + wire $0\imem_a_valid_i[0:0] + attribute \src "libresoc.v:202197.3-202246.6" + wire $0\imem_f_valid_i[0:0] + attribute \src "libresoc.v:198206.7-198206.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:202448.3-202456.6" + wire $0\jtag_dmi0__ack_o$next[0:0]$14073 + attribute \src "libresoc.v:200637.3-200638.49" + wire $0\jtag_dmi0__ack_o[0:0] + attribute \src "libresoc.v:202587.3-202595.6" + wire width 64 $0\jtag_dmi0__dout$next[63:0]$14137 + attribute \src "libresoc.v:200635.3-200636.47" + wire width 64 $0\jtag_dmi0__dout[63:0] + attribute \src "libresoc.v:202273.3-202307.6" + wire $0\msr_read$next[0:0]$14047 + attribute \src "libresoc.v:200837.3-200838.33" + wire $0\msr_read[0:0] + attribute \src "libresoc.v:201867.3-201877.6" + wire width 64 $0\new_dec[63:0] + attribute \src "libresoc.v:201939.3-201949.6" + wire width 64 $0\new_tb[63:0] + attribute \src "libresoc.v:202596.3-202614.6" + wire width 64 $0\nia$next[63:0]$14140 + attribute \src "libresoc.v:200801.3-200802.23" + wire width 64 $0\nia[63:0] + attribute \src "libresoc.v:201968.3-201983.6" + wire width 64 $0\pc[63:0] + attribute \src "libresoc.v:201637.3-201661.6" + wire $0\pc_changed$next[0:0]$13975 + attribute \src "libresoc.v:200753.3-200754.37" + wire $0\pc_changed[0:0] + attribute \src "libresoc.v:201959.3-201967.6" + wire $0\pc_ok_delay$next[0:0]$14025 + attribute \src "libresoc.v:200627.3-200628.39" + wire $0\pc_ok_delay[0:0] + attribute \src "libresoc.v:202308.3-202342.6" + wire $0\sv_read$next[0:0]$14054 + attribute \src "libresoc.v:200835.3-200836.31" + wire $0\sv_read[0:0] + attribute \src "libresoc.v:202530.3-202548.6" + wire $0\svp64_bigendian[0:0] + attribute \src "libresoc.v:202511.3-202529.6" + wire width 32 $0\svp64_raw_opcode_in[31:0] + attribute \src "libresoc.v:202743.3-202858.6" + wire width 8 $1\core_asmcode$next[7:0]$14220 + attribute \src "libresoc.v:198398.13-198398.33" + wire width 8 $1\core_asmcode[7:0] + attribute \src "libresoc.v:201555.3-201584.6" + wire $1\core_bigendian_i$10$next[0:0]$13963 + attribute \src "libresoc.v:201984.3-201996.6" + wire width 3 $1\core_cia__ren[2:0] + attribute \src "libresoc.v:202743.3-202858.6" + wire width 64 $1\core_core_core_cia$next[63:0]$14221 + attribute \src "libresoc.v:198412.14-198412.55" + wire width 64 $1\core_core_core_cia[63:0] + attribute \src "libresoc.v:202743.3-202858.6" + wire width 8 $1\core_core_core_cr_rd$next[7:0]$14222 + attribute \src "libresoc.v:198416.13-198416.41" + wire width 8 $1\core_core_core_cr_rd[7:0] + attribute \src "libresoc.v:202743.3-202858.6" + wire $1\core_core_core_cr_rd_ok$next[0:0]$14223 + attribute \src "libresoc.v:198420.7-198420.37" + wire $1\core_core_core_cr_rd_ok[0:0] + attribute \src "libresoc.v:202743.3-202858.6" + wire width 8 $1\core_core_core_cr_wr$next[7:0]$14224 + attribute \src "libresoc.v:198424.13-198424.41" + wire width 8 $1\core_core_core_cr_wr[7:0] + attribute \src "libresoc.v:202743.3-202858.6" + wire $1\core_core_core_exc_$signal$3$next[0:0]$14225 + attribute \src "libresoc.v:202743.3-202858.6" + wire $1\core_core_core_exc_$signal$4$next[0:0]$14226 + attribute \src "libresoc.v:202743.3-202858.6" + wire $1\core_core_core_exc_$signal$5$next[0:0]$14227 + attribute \src "libresoc.v:202743.3-202858.6" + wire $1\core_core_core_exc_$signal$6$next[0:0]$14228 + attribute \src "libresoc.v:202743.3-202858.6" + wire $1\core_core_core_exc_$signal$7$next[0:0]$14229 + attribute \src "libresoc.v:202743.3-202858.6" + wire $1\core_core_core_exc_$signal$8$next[0:0]$14230 + attribute \src "libresoc.v:202743.3-202858.6" + wire $1\core_core_core_exc_$signal$9$next[0:0]$14231 + attribute \src "libresoc.v:202743.3-202858.6" + wire $1\core_core_core_exc_$signal$next[0:0]$14232 + attribute \src "libresoc.v:202743.3-202858.6" + wire width 13 $1\core_core_core_fn_unit$next[12:0]$14233 + attribute \src "libresoc.v:198474.14-198474.47" + wire width 13 $1\core_core_core_fn_unit[12:0] + attribute \src "libresoc.v:202743.3-202858.6" + wire width 2 $1\core_core_core_input_carry$next[1:0]$14234 + attribute \src "libresoc.v:198482.13-198482.46" + wire width 2 $1\core_core_core_input_carry[1:0] + attribute \src "libresoc.v:202743.3-202858.6" + wire width 32 $1\core_core_core_insn$next[31:0]$14235 + attribute \src "libresoc.v:198486.14-198486.41" + wire width 32 $1\core_core_core_insn[31:0] + attribute \src "libresoc.v:202743.3-202858.6" + wire width 7 $1\core_core_core_insn_type$next[6:0]$14236 + attribute \src "libresoc.v:198564.13-198564.45" + wire width 7 $1\core_core_core_insn_type[6:0] + attribute \src "libresoc.v:202743.3-202858.6" + wire $1\core_core_core_is_32bit$next[0:0]$14237 + attribute \src "libresoc.v:198568.7-198568.37" + wire $1\core_core_core_is_32bit[0:0] + attribute \src "libresoc.v:202743.3-202858.6" + wire width 64 $1\core_core_core_msr$next[63:0]$14238 + attribute \src "libresoc.v:198572.14-198572.55" + wire width 64 $1\core_core_core_msr[63:0] + attribute \src "libresoc.v:202743.3-202858.6" + wire $1\core_core_core_oe$next[0:0]$14239 + attribute \src "libresoc.v:198576.7-198576.31" + wire $1\core_core_core_oe[0:0] + attribute \src "libresoc.v:202743.3-202858.6" + wire $1\core_core_core_oe_ok$next[0:0]$14240 + attribute \src "libresoc.v:198580.7-198580.34" + wire $1\core_core_core_oe_ok[0:0] + attribute \src "libresoc.v:202743.3-202858.6" + wire $1\core_core_core_rc$next[0:0]$14241 + attribute \src "libresoc.v:198584.7-198584.31" + wire $1\core_core_core_rc[0:0] + attribute \src "libresoc.v:202743.3-202858.6" + wire $1\core_core_core_rc_ok$next[0:0]$14242 + attribute \src "libresoc.v:198588.7-198588.34" + wire $1\core_core_core_rc_ok[0:0] + attribute \src "libresoc.v:202743.3-202858.6" + wire width 13 $1\core_core_core_trapaddr$next[12:0]$14243 + attribute \src "libresoc.v:198592.14-198592.48" + wire width 13 $1\core_core_core_trapaddr[12:0] + attribute \src "libresoc.v:202743.3-202858.6" + wire width 8 $1\core_core_core_traptype$next[7:0]$14244 + attribute \src "libresoc.v:198596.13-198596.44" + wire width 8 $1\core_core_core_traptype[7:0] + attribute \src "libresoc.v:202743.3-202858.6" + wire width 7 $1\core_core_cr_in1$next[6:0]$14245 + attribute \src "libresoc.v:198600.13-198600.37" + wire width 7 $1\core_core_cr_in1[6:0] + attribute \src "libresoc.v:202743.3-202858.6" + wire $1\core_core_cr_in1_ok$next[0:0]$14246 + attribute \src "libresoc.v:198604.7-198604.33" + wire $1\core_core_cr_in1_ok[0:0] + attribute \src "libresoc.v:202743.3-202858.6" + wire width 7 $1\core_core_cr_in2$1$next[6:0]$14247 + attribute \src "libresoc.v:202743.3-202858.6" + wire width 7 $1\core_core_cr_in2$next[6:0]$14248 + attribute \src "libresoc.v:198608.13-198608.37" + wire width 7 $1\core_core_cr_in2[6:0] + attribute \src "libresoc.v:202743.3-202858.6" + wire $1\core_core_cr_in2_ok$2$next[0:0]$14249 + attribute \src "libresoc.v:202743.3-202858.6" + wire $1\core_core_cr_in2_ok$next[0:0]$14250 + attribute \src "libresoc.v:198616.7-198616.33" + wire $1\core_core_cr_in2_ok[0:0] + attribute \src "libresoc.v:202743.3-202858.6" + wire width 7 $1\core_core_cr_out$next[6:0]$14251 + attribute \src "libresoc.v:198624.13-198624.37" + wire width 7 $1\core_core_cr_out[6:0] + attribute \src "libresoc.v:202743.3-202858.6" + wire $1\core_core_cr_wr_ok$next[0:0]$14252 + attribute \src "libresoc.v:198628.7-198628.32" + wire $1\core_core_cr_wr_ok[0:0] + attribute \src "libresoc.v:201484.3-201524.6" + wire width 7 $1\core_core_dststep$next[6:0]$13925 + attribute \src "libresoc.v:198632.13-198632.38" + wire width 7 $1\core_core_dststep[6:0] + attribute \src "libresoc.v:202743.3-202858.6" + wire width 7 $1\core_core_ea$next[6:0]$14253 + attribute \src "libresoc.v:198636.13-198636.33" + wire width 7 $1\core_core_ea[6:0] + attribute \src "libresoc.v:202743.3-202858.6" + wire width 3 $1\core_core_fast1$next[2:0]$14254 + attribute \src "libresoc.v:198640.13-198640.35" + wire width 3 $1\core_core_fast1[2:0] + attribute \src "libresoc.v:202743.3-202858.6" + wire $1\core_core_fast1_ok$next[0:0]$14255 + attribute \src "libresoc.v:198644.7-198644.32" + wire $1\core_core_fast1_ok[0:0] + attribute \src "libresoc.v:202743.3-202858.6" + wire width 3 $1\core_core_fast2$next[2:0]$14256 + attribute \src "libresoc.v:198648.13-198648.35" + wire width 3 $1\core_core_fast2[2:0] + attribute \src "libresoc.v:202743.3-202858.6" + wire $1\core_core_fast2_ok$next[0:0]$14257 + attribute \src "libresoc.v:198652.7-198652.32" + wire $1\core_core_fast2_ok[0:0] + attribute \src "libresoc.v:202743.3-202858.6" + wire width 3 $1\core_core_fasto1$next[2:0]$14258 + attribute \src "libresoc.v:198656.13-198656.36" + wire width 3 $1\core_core_fasto1[2:0] + attribute \src "libresoc.v:202743.3-202858.6" + wire width 3 $1\core_core_fasto2$next[2:0]$14259 + attribute \src "libresoc.v:198660.13-198660.36" + wire width 3 $1\core_core_fasto2[2:0] + attribute \src "libresoc.v:202743.3-202858.6" + wire $1\core_core_lk$next[0:0]$14260 + attribute \src "libresoc.v:198664.7-198664.26" + wire $1\core_core_lk[0:0] + attribute \src "libresoc.v:201484.3-201524.6" + wire width 7 $1\core_core_maxvl$next[6:0]$13926 + attribute \src "libresoc.v:198668.13-198668.36" + wire width 7 $1\core_core_maxvl[6:0] + attribute \src "libresoc.v:201484.3-201524.6" + wire width 64 $1\core_core_pc$next[63:0]$13927 + attribute \src "libresoc.v:198672.14-198672.49" + wire width 64 $1\core_core_pc[63:0] + attribute \src "libresoc.v:202743.3-202858.6" + wire width 7 $1\core_core_reg1$next[6:0]$14261 + attribute \src "libresoc.v:198676.13-198676.35" + wire width 7 $1\core_core_reg1[6:0] + attribute \src "libresoc.v:202743.3-202858.6" + wire $1\core_core_reg1_ok$next[0:0]$14262 + attribute \src "libresoc.v:198680.7-198680.31" + wire $1\core_core_reg1_ok[0:0] + attribute \src "libresoc.v:202743.3-202858.6" + wire width 7 $1\core_core_reg2$next[6:0]$14263 + attribute \src "libresoc.v:198684.13-198684.35" + wire width 7 $1\core_core_reg2[6:0] + attribute \src "libresoc.v:202743.3-202858.6" + wire $1\core_core_reg2_ok$next[0:0]$14264 + attribute \src "libresoc.v:198688.7-198688.31" + wire $1\core_core_reg2_ok[0:0] + attribute \src "libresoc.v:202743.3-202858.6" + wire width 7 $1\core_core_reg3$next[6:0]$14265 + attribute \src "libresoc.v:198692.13-198692.35" + wire width 7 $1\core_core_reg3[6:0] + attribute \src "libresoc.v:202743.3-202858.6" + wire $1\core_core_reg3_ok$next[0:0]$14266 + attribute \src "libresoc.v:198696.7-198696.31" + wire $1\core_core_reg3_ok[0:0] + attribute \src "libresoc.v:202743.3-202858.6" + wire width 7 $1\core_core_rego$next[6:0]$14267 + attribute \src "libresoc.v:198700.13-198700.35" + wire width 7 $1\core_core_rego[6:0] + attribute \src "libresoc.v:202743.3-202858.6" + wire width 10 $1\core_core_spr1$next[9:0]$14268 + attribute \src "libresoc.v:198817.13-198817.37" + wire width 10 $1\core_core_spr1[9:0] + attribute \src "libresoc.v:202743.3-202858.6" + wire $1\core_core_spr1_ok$next[0:0]$14269 + attribute \src "libresoc.v:198821.7-198821.31" + wire $1\core_core_spr1_ok[0:0] + attribute \src "libresoc.v:202743.3-202858.6" + wire width 10 $1\core_core_spro$next[9:0]$14270 + attribute \src "libresoc.v:198938.13-198938.37" + wire width 10 $1\core_core_spro[9:0] + attribute \src "libresoc.v:201484.3-201524.6" + wire width 7 $1\core_core_srcstep$next[6:0]$13928 + attribute \src "libresoc.v:198942.13-198942.38" + wire width 7 $1\core_core_srcstep[6:0] + attribute \src "libresoc.v:201484.3-201524.6" + wire width 2 $1\core_core_subvl$next[1:0]$13929 + attribute \src "libresoc.v:198946.13-198946.35" + wire width 2 $1\core_core_subvl[1:0] + attribute \src "libresoc.v:201484.3-201524.6" + wire width 2 $1\core_core_svstep$next[1:0]$13930 + attribute \src "libresoc.v:198950.13-198950.36" + wire width 2 $1\core_core_svstep[1:0] + attribute \src "libresoc.v:201484.3-201524.6" + wire width 7 $1\core_core_vl$next[6:0]$13931 + attribute \src "libresoc.v:198956.13-198956.33" + wire width 7 $1\core_core_vl[6:0] + attribute \src "libresoc.v:202743.3-202858.6" + wire width 3 $1\core_core_xer_in$next[2:0]$14271 + attribute \src "libresoc.v:198960.13-198960.36" + wire width 3 $1\core_core_xer_in[2:0] + attribute \src "libresoc.v:202743.3-202858.6" + wire $1\core_cr_out_ok$next[0:0]$14272 + attribute \src "libresoc.v:198968.7-198968.28" + wire $1\core_cr_out_ok[0:0] + attribute \src "libresoc.v:201672.3-201681.6" + wire width 64 $1\core_data_i$12[63:0]$13984 + attribute \src "libresoc.v:202018.3-202038.6" + wire width 64 $1\core_data_i[63:0] + attribute \src "libresoc.v:201484.3-201524.6" + wire width 64 $1\core_dec$next[63:0]$13932 + attribute \src "libresoc.v:198984.14-198984.45" + wire width 64 $1\core_dec[63:0] + attribute \src "libresoc.v:201682.3-201691.6" + wire width 5 $1\core_dmi__addr[4:0] + attribute \src "libresoc.v:201692.3-201701.6" + wire $1\core_dmi__ren[0:0] + attribute \src "libresoc.v:202743.3-202858.6" + wire $1\core_ea_ok$next[0:0]$14273 + attribute \src "libresoc.v:198994.7-198994.24" + wire $1\core_ea_ok[0:0] + attribute \src "libresoc.v:201484.3-201524.6" + wire $1\core_eint$next[0:0]$13933 + attribute \src "libresoc.v:198998.7-198998.23" + wire $1\core_eint[0:0] + attribute \src "libresoc.v:202743.3-202858.6" + wire $1\core_fasto1_ok$next[0:0]$14274 + attribute \src "libresoc.v:199002.7-199002.28" + wire $1\core_fasto1_ok[0:0] + attribute \src "libresoc.v:202743.3-202858.6" + wire $1\core_fasto2_ok$next[0:0]$14275 + attribute \src "libresoc.v:199006.7-199006.28" + wire $1\core_fasto2_ok[0:0] + attribute \src "libresoc.v:201731.3-201740.6" + wire width 8 $1\core_full_rd2__ren[7:0] + attribute \src "libresoc.v:201770.3-201779.6" + wire width 3 $1\core_full_rd__ren[2:0] + attribute \src "libresoc.v:201878.3-201892.6" + wire width 3 $1\core_issue__addr$13[2:0]$14013 + attribute \src "libresoc.v:201809.3-201823.6" + wire width 3 $1\core_issue__addr[2:0] + attribute \src "libresoc.v:201908.3-201922.6" + wire width 64 $1\core_issue__data_i[63:0] + attribute \src "libresoc.v:201824.3-201838.6" + wire $1\core_issue__ren[0:0] + attribute \src "libresoc.v:201893.3-201907.6" + wire $1\core_issue__wen[0:0] + attribute \src "libresoc.v:201626.3-201636.6" + wire $1\core_issue_i[0:0] + attribute \src "libresoc.v:201606.3-201625.6" + wire $1\core_ivalid_i[0:0] + attribute \src "libresoc.v:201484.3-201524.6" + wire width 64 $1\core_msr$next[63:0]$13934 + attribute \src "libresoc.v:199034.14-199034.45" + wire width 64 $1\core_msr[63:0] + attribute \src "libresoc.v:202060.3-202080.6" + wire width 3 $1\core_msr__ren[2:0] + attribute \src "libresoc.v:201525.3-201554.6" + wire width 32 $1\core_raw_insn_i$next[31:0]$13957 + attribute \src "libresoc.v:199042.14-199042.37" + wire width 32 $1\core_raw_insn_i[31:0] + attribute \src "libresoc.v:202743.3-202858.6" + wire $1\core_rego_ok$next[0:0]$14276 + attribute \src "libresoc.v:199046.7-199046.26" + wire $1\core_rego_ok[0:0] + attribute \src "libresoc.v:202743.3-202858.6" + wire $1\core_spro_ok$next[0:0]$14277 + attribute \src "libresoc.v:199050.7-199050.26" + wire $1\core_spro_ok[0:0] + attribute \src "libresoc.v:202410.3-202428.6" + wire $1\core_stopped_i[0:0] + attribute \src "libresoc.v:202039.3-202059.6" + wire width 3 $1\core_sv__ren[2:0] + attribute \src "libresoc.v:201662.3-201671.6" + wire width 3 $1\core_wen$11[2:0]$13981 + attribute \src "libresoc.v:201997.3-202017.6" + wire width 3 $1\core_wen[2:0] + attribute \src "libresoc.v:202743.3-202858.6" + wire $1\core_xer_out$next[0:0]$14278 + attribute \src "libresoc.v:199068.7-199068.26" + wire $1\core_xer_out[0:0] + attribute \src "libresoc.v:199074.7-199074.30" + wire $1\cu_st__rel_o_dly[0:0] + attribute \src "libresoc.v:202478.3-202510.6" + wire width 7 $1\cur_cur_dststep$next[6:0]$14087 + attribute \src "libresoc.v:199080.13-199080.36" + wire width 7 $1\cur_cur_dststep[6:0] + attribute \src "libresoc.v:202478.3-202510.6" + wire width 7 $1\cur_cur_maxvl$next[6:0]$14088 + attribute \src "libresoc.v:199084.13-199084.34" + wire width 7 $1\cur_cur_maxvl[6:0] + attribute \src "libresoc.v:202478.3-202510.6" + wire width 2 $1\cur_cur_subvl$next[1:0]$14089 + attribute \src "libresoc.v:199088.13-199088.33" + wire width 2 $1\cur_cur_subvl[1:0] + attribute \src "libresoc.v:202478.3-202510.6" + wire width 2 $1\cur_cur_svstep$next[1:0]$14090 + attribute \src "libresoc.v:199092.13-199092.34" + wire width 2 $1\cur_cur_svstep[1:0] + attribute \src "libresoc.v:202478.3-202510.6" + wire width 7 $1\cur_cur_vl$next[6:0]$14091 + attribute \src "libresoc.v:199096.13-199096.31" + wire width 7 $1\cur_cur_vl[6:0] + attribute \src "libresoc.v:201741.3-201749.6" + wire $1\d_cr_delay$next[0:0]$13995 + attribute \src "libresoc.v:199100.7-199100.24" + wire $1\d_cr_delay[0:0] + attribute \src "libresoc.v:201702.3-201710.6" + wire $1\d_reg_delay$next[0:0]$13989 + attribute \src "libresoc.v:199104.7-199104.25" + wire $1\d_reg_delay[0:0] + attribute \src "libresoc.v:201780.3-201788.6" + wire $1\d_xer_delay$next[0:0]$14001 + attribute \src "libresoc.v:199108.7-199108.25" + wire $1\d_xer_delay[0:0] + attribute \src "libresoc.v:202429.3-202447.6" + wire $1\dbg_core_stopped_i[0:0] + attribute \src "libresoc.v:201760.3-201769.6" + wire $1\dbg_d_cr_ack[0:0] + attribute \src "libresoc.v:201750.3-201759.6" + wire width 64 $1\dbg_d_cr_data[63:0] + attribute \src "libresoc.v:201721.3-201730.6" + wire $1\dbg_d_gpr_ack[0:0] + attribute \src "libresoc.v:201711.3-201720.6" + wire width 64 $1\dbg_d_gpr_data[63:0] + attribute \src "libresoc.v:201799.3-201808.6" + wire $1\dbg_d_xer_ack[0:0] + attribute \src "libresoc.v:201789.3-201798.6" + wire width 64 $1\dbg_d_xer_data[63:0] + attribute \src "libresoc.v:201466.3-201474.6" + wire width 4 $1\dbg_dmi_addr_i$next[3:0]$13910 + attribute \src "libresoc.v:199144.13-199144.34" + wire width 4 $1\dbg_dmi_addr_i[3:0] + attribute \src "libresoc.v:202081.3-202089.6" + wire width 64 $1\dbg_dmi_din$next[63:0]$14035 + attribute \src "libresoc.v:199148.14-199148.48" + wire width 64 $1\dbg_dmi_din[63:0] + attribute \src "libresoc.v:201475.3-201483.6" + wire $1\dbg_dmi_req_i$next[0:0]$13913 + attribute \src "libresoc.v:199154.7-199154.27" + wire $1\dbg_dmi_req_i[0:0] + attribute \src "libresoc.v:201950.3-201958.6" + wire $1\dbg_dmi_we_i$next[0:0]$14023 + attribute \src "libresoc.v:199158.7-199158.26" + wire $1\dbg_dmi_we_i[0:0] + attribute \src "libresoc.v:202478.3-202510.6" + wire width 7 $1\dec2_cur_cur_srcstep$next[6:0]$14092 + attribute \src "libresoc.v:199212.13-199212.41" + wire width 7 $1\dec2_cur_cur_srcstep[6:0] + attribute \src "libresoc.v:201923.3-201938.6" + wire width 64 $1\dec2_cur_dec$next[63:0]$14018 + attribute \src "libresoc.v:199216.14-199216.49" + wire width 64 $1\dec2_cur_dec[63:0] + attribute \src "libresoc.v:202859.3-202867.6" + wire $1\dec2_cur_eint$next[0:0]$14426 + attribute \src "libresoc.v:199220.7-199220.27" + wire $1\dec2_cur_eint[0:0] + attribute \src "libresoc.v:202457.3-202477.6" + wire width 64 $1\dec2_cur_msr$next[63:0]$14077 + attribute \src "libresoc.v:199224.14-199224.49" + wire width 64 $1\dec2_cur_msr[63:0] + attribute \src "libresoc.v:202247.3-202272.6" + wire width 64 $1\dec2_cur_pc$next[63:0]$14042 + attribute \src "libresoc.v:199228.14-199228.48" + wire width 64 $1\dec2_cur_pc[63:0] + attribute \src "libresoc.v:202549.3-202586.6" + wire width 9 $1\dec2_dec_svp64__extra$next[8:0]$14115 + attribute \src "libresoc.v:199232.13-199232.43" + wire width 9 $1\dec2_dec_svp64__extra[8:0] + attribute \src "libresoc.v:202727.3-202742.6" + wire width 32 $1\dec2_raw_opcode_in[31:0] + attribute \src "libresoc.v:202549.3-202586.6" + wire width 2 $1\dec_svp64__elwidth$next[1:0]$14116 + attribute \src "libresoc.v:199646.13-199646.38" + wire width 2 $1\dec_svp64__elwidth[1:0] + attribute \src "libresoc.v:202549.3-202586.6" + wire width 2 $1\dec_svp64__ewsrc$next[1:0]$14117 + attribute \src "libresoc.v:199650.13-199650.36" + wire width 2 $1\dec_svp64__ewsrc[1:0] + attribute \src "libresoc.v:202549.3-202586.6" + wire width 3 $1\dec_svp64__mask$next[2:0]$14118 + attribute \src "libresoc.v:199654.13-199654.35" + wire width 3 $1\dec_svp64__mask[2:0] + attribute \src "libresoc.v:202549.3-202586.6" + wire $1\dec_svp64__mmode$next[0:0]$14119 + attribute \src "libresoc.v:199658.7-199658.30" + wire $1\dec_svp64__mmode[0:0] + attribute \src "libresoc.v:202549.3-202586.6" + wire width 5 $1\dec_svp64__mode$next[4:0]$14120 + attribute \src "libresoc.v:199662.13-199662.36" + wire width 5 $1\dec_svp64__mode[4:0] + attribute \src "libresoc.v:202549.3-202586.6" + wire width 2 $1\dec_svp64__subvl$next[1:0]$14121 + attribute \src "libresoc.v:199666.13-199666.36" + wire width 2 $1\dec_svp64__subvl[1:0] + attribute \src "libresoc.v:202868.3-202877.6" + wire width 2 $1\delay$next[1:0]$14429 + attribute \src "libresoc.v:199670.13-199670.25" + wire width 2 $1\delay[1:0] + attribute \src "libresoc.v:202343.3-202409.6" + wire width 2 $1\fetch_fsm_state$next[1:0]$14062 + attribute \src "libresoc.v:199686.13-199686.35" + wire width 2 $1\fetch_fsm_state[1:0] + attribute \src "libresoc.v:202615.3-202650.6" + wire width 32 $1\fetch_insn_o$next[31:0]$14145 + attribute \src "libresoc.v:199690.14-199690.34" + wire width 32 $1\fetch_insn_o[31:0] + attribute \src "libresoc.v:202716.3-202726.6" + wire $1\fetch_insn_ready_i[0:0] + attribute \src "libresoc.v:202651.3-202661.6" + wire $1\fetch_insn_valid_o[0:0] + attribute \src "libresoc.v:202090.3-202105.6" + wire $1\fetch_pc_ready_o[0:0] + attribute \src "libresoc.v:202662.3-202672.6" + wire $1\fetch_pc_valid_i[0:0] + attribute \src "libresoc.v:201839.3-201866.6" + wire width 2 $1\fsm_state$188$next[1:0]$14008 + attribute \src "libresoc.v:202673.3-202715.6" + wire width 2 $1\fsm_state$next[1:0]$14153 + attribute \src "libresoc.v:199702.13-199702.29" + wire width 2 $1\fsm_state[1:0] + attribute \src "libresoc.v:201585.3-201605.6" + wire width 32 $1\ilatch$next[31:0]$13969 + attribute \src "libresoc.v:199946.14-199946.28" + wire width 32 $1\ilatch[31:0] + attribute \src "libresoc.v:202106.3-202146.6" + wire width 48 $1\imem_a_pc_i[47:0] + attribute \src "libresoc.v:202147.3-202196.6" + wire $1\imem_a_valid_i[0:0] + attribute \src "libresoc.v:202197.3-202246.6" + wire $1\imem_f_valid_i[0:0] + attribute \src "libresoc.v:202448.3-202456.6" + wire $1\jtag_dmi0__ack_o$next[0:0]$14074 + attribute \src "libresoc.v:199964.7-199964.30" + wire $1\jtag_dmi0__ack_o[0:0] + attribute \src "libresoc.v:202587.3-202595.6" + wire width 64 $1\jtag_dmi0__dout$next[63:0]$14138 + attribute \src "libresoc.v:199972.14-199972.52" + wire width 64 $1\jtag_dmi0__dout[63:0] + attribute \src "libresoc.v:202273.3-202307.6" + wire $1\msr_read$next[0:0]$14048 + attribute \src "libresoc.v:200028.7-200028.22" + wire $1\msr_read[0:0] + attribute \src "libresoc.v:201867.3-201877.6" + wire width 64 $1\new_dec[63:0] + attribute \src "libresoc.v:201939.3-201949.6" + wire width 64 $1\new_tb[63:0] + attribute \src "libresoc.v:202596.3-202614.6" + wire width 64 $1\nia$next[63:0]$14141 + attribute \src "libresoc.v:200064.14-200064.40" + wire width 64 $1\nia[63:0] + attribute \src "libresoc.v:201968.3-201983.6" + wire width 64 $1\pc[63:0] + attribute \src "libresoc.v:201637.3-201661.6" + wire $1\pc_changed$next[0:0]$13976 + attribute \src "libresoc.v:200070.7-200070.24" + wire $1\pc_changed[0:0] + attribute \src "libresoc.v:201959.3-201967.6" + wire $1\pc_ok_delay$next[0:0]$14026 + attribute \src "libresoc.v:200080.7-200080.25" + wire $1\pc_ok_delay[0:0] + attribute \src "libresoc.v:202308.3-202342.6" + wire $1\sv_read$next[0:0]$14055 + attribute \src "libresoc.v:200516.7-200516.21" + wire $1\sv_read[0:0] + attribute \src "libresoc.v:202530.3-202548.6" + wire $1\svp64_bigendian[0:0] + attribute \src "libresoc.v:202511.3-202529.6" + wire width 32 $1\svp64_raw_opcode_in[31:0] + attribute \src "libresoc.v:202743.3-202858.6" + wire width 8 $2\core_asmcode$next[7:0]$14279 + attribute \src "libresoc.v:201555.3-201584.6" + wire $2\core_bigendian_i$10$next[0:0]$13964 + attribute \src "libresoc.v:202743.3-202858.6" + wire width 64 $2\core_core_core_cia$next[63:0]$14280 + attribute \src "libresoc.v:202743.3-202858.6" + wire width 8 $2\core_core_core_cr_rd$next[7:0]$14281 + attribute \src "libresoc.v:202743.3-202858.6" + wire $2\core_core_core_cr_rd_ok$next[0:0]$14282 + attribute \src "libresoc.v:202743.3-202858.6" + wire width 8 $2\core_core_core_cr_wr$next[7:0]$14283 + attribute \src "libresoc.v:202743.3-202858.6" + wire $2\core_core_core_exc_$signal$3$next[0:0]$14284 + attribute \src "libresoc.v:202743.3-202858.6" + wire $2\core_core_core_exc_$signal$4$next[0:0]$14285 + attribute \src "libresoc.v:202743.3-202858.6" + wire $2\core_core_core_exc_$signal$5$next[0:0]$14286 + attribute \src "libresoc.v:202743.3-202858.6" + wire $2\core_core_core_exc_$signal$6$next[0:0]$14287 + attribute \src "libresoc.v:202743.3-202858.6" + wire $2\core_core_core_exc_$signal$7$next[0:0]$14288 + attribute \src "libresoc.v:202743.3-202858.6" + wire $2\core_core_core_exc_$signal$8$next[0:0]$14289 + attribute \src "libresoc.v:202743.3-202858.6" + wire $2\core_core_core_exc_$signal$9$next[0:0]$14290 + attribute \src "libresoc.v:202743.3-202858.6" + wire $2\core_core_core_exc_$signal$next[0:0]$14291 + attribute \src "libresoc.v:202743.3-202858.6" + wire width 13 $2\core_core_core_fn_unit$next[12:0]$14292 + attribute \src "libresoc.v:202743.3-202858.6" + wire width 2 $2\core_core_core_input_carry$next[1:0]$14293 + attribute \src "libresoc.v:202743.3-202858.6" + wire width 32 $2\core_core_core_insn$next[31:0]$14294 + attribute \src "libresoc.v:202743.3-202858.6" + wire width 7 $2\core_core_core_insn_type$next[6:0]$14295 + attribute \src "libresoc.v:202743.3-202858.6" + wire $2\core_core_core_is_32bit$next[0:0]$14296 + attribute \src "libresoc.v:202743.3-202858.6" + wire width 64 $2\core_core_core_msr$next[63:0]$14297 + attribute \src "libresoc.v:202743.3-202858.6" + wire $2\core_core_core_oe$next[0:0]$14298 + attribute \src "libresoc.v:202743.3-202858.6" + wire $2\core_core_core_oe_ok$next[0:0]$14299 + attribute \src "libresoc.v:202743.3-202858.6" + wire $2\core_core_core_rc$next[0:0]$14300 + attribute \src "libresoc.v:202743.3-202858.6" + wire $2\core_core_core_rc_ok$next[0:0]$14301 + attribute \src "libresoc.v:202743.3-202858.6" + wire width 13 $2\core_core_core_trapaddr$next[12:0]$14302 + attribute \src "libresoc.v:202743.3-202858.6" + wire width 8 $2\core_core_core_traptype$next[7:0]$14303 + attribute \src "libresoc.v:202743.3-202858.6" + wire width 7 $2\core_core_cr_in1$next[6:0]$14304 + attribute \src "libresoc.v:202743.3-202858.6" + wire $2\core_core_cr_in1_ok$next[0:0]$14305 + attribute \src "libresoc.v:202743.3-202858.6" + wire width 7 $2\core_core_cr_in2$1$next[6:0]$14306 + attribute \src "libresoc.v:202743.3-202858.6" + wire width 7 $2\core_core_cr_in2$next[6:0]$14307 + attribute \src "libresoc.v:202743.3-202858.6" + wire $2\core_core_cr_in2_ok$2$next[0:0]$14308 + attribute \src "libresoc.v:202743.3-202858.6" + wire $2\core_core_cr_in2_ok$next[0:0]$14309 + attribute \src "libresoc.v:202743.3-202858.6" + wire width 7 $2\core_core_cr_out$next[6:0]$14310 + attribute \src "libresoc.v:202743.3-202858.6" + wire $2\core_core_cr_wr_ok$next[0:0]$14311 + attribute \src "libresoc.v:201484.3-201524.6" + wire width 7 $2\core_core_dststep$next[6:0]$13935 + attribute \src "libresoc.v:202743.3-202858.6" + wire width 7 $2\core_core_ea$next[6:0]$14312 + attribute \src "libresoc.v:202743.3-202858.6" + wire width 3 $2\core_core_fast1$next[2:0]$14313 + attribute \src "libresoc.v:202743.3-202858.6" + wire $2\core_core_fast1_ok$next[0:0]$14314 + attribute \src "libresoc.v:202743.3-202858.6" + wire width 3 $2\core_core_fast2$next[2:0]$14315 + attribute \src "libresoc.v:202743.3-202858.6" + wire $2\core_core_fast2_ok$next[0:0]$14316 + attribute \src "libresoc.v:202743.3-202858.6" + wire width 3 $2\core_core_fasto1$next[2:0]$14317 + attribute \src "libresoc.v:202743.3-202858.6" + wire width 3 $2\core_core_fasto2$next[2:0]$14318 + attribute \src "libresoc.v:202743.3-202858.6" + wire $2\core_core_lk$next[0:0]$14319 + attribute \src "libresoc.v:201484.3-201524.6" + wire width 7 $2\core_core_maxvl$next[6:0]$13936 + attribute \src "libresoc.v:201484.3-201524.6" + wire width 64 $2\core_core_pc$next[63:0]$13937 + attribute \src "libresoc.v:202743.3-202858.6" + wire width 7 $2\core_core_reg1$next[6:0]$14320 + attribute \src "libresoc.v:202743.3-202858.6" + wire $2\core_core_reg1_ok$next[0:0]$14321 + attribute \src "libresoc.v:202743.3-202858.6" + wire width 7 $2\core_core_reg2$next[6:0]$14322 + attribute \src "libresoc.v:202743.3-202858.6" + wire $2\core_core_reg2_ok$next[0:0]$14323 + attribute \src "libresoc.v:202743.3-202858.6" + wire width 7 $2\core_core_reg3$next[6:0]$14324 + attribute \src "libresoc.v:202743.3-202858.6" + wire $2\core_core_reg3_ok$next[0:0]$14325 + attribute \src "libresoc.v:202743.3-202858.6" + wire width 7 $2\core_core_rego$next[6:0]$14326 + attribute \src "libresoc.v:202743.3-202858.6" + wire width 10 $2\core_core_spr1$next[9:0]$14327 + attribute \src "libresoc.v:202743.3-202858.6" + wire $2\core_core_spr1_ok$next[0:0]$14328 + attribute \src "libresoc.v:202743.3-202858.6" + wire width 10 $2\core_core_spro$next[9:0]$14329 + attribute \src "libresoc.v:201484.3-201524.6" + wire width 7 $2\core_core_srcstep$next[6:0]$13938 + attribute \src "libresoc.v:201484.3-201524.6" + wire width 2 $2\core_core_subvl$next[1:0]$13939 + attribute \src "libresoc.v:201484.3-201524.6" + wire width 2 $2\core_core_svstep$next[1:0]$13940 + attribute \src "libresoc.v:201484.3-201524.6" + wire width 7 $2\core_core_vl$next[6:0]$13941 + attribute \src "libresoc.v:202743.3-202858.6" + wire width 3 $2\core_core_xer_in$next[2:0]$14330 + attribute \src "libresoc.v:202743.3-202858.6" + wire $2\core_cr_out_ok$next[0:0]$14331 + attribute \src "libresoc.v:202018.3-202038.6" + wire width 64 $2\core_data_i[63:0] + attribute \src "libresoc.v:201484.3-201524.6" + wire width 64 $2\core_dec$next[63:0]$13942 + attribute \src "libresoc.v:202743.3-202858.6" + wire $2\core_ea_ok$next[0:0]$14332 + attribute \src "libresoc.v:201484.3-201524.6" + wire $2\core_eint$next[0:0]$13943 + attribute \src "libresoc.v:202743.3-202858.6" + wire $2\core_fasto1_ok$next[0:0]$14333 + attribute \src "libresoc.v:202743.3-202858.6" + wire $2\core_fasto2_ok$next[0:0]$14334 + attribute \src "libresoc.v:201606.3-201625.6" + wire $2\core_ivalid_i[0:0] + attribute \src "libresoc.v:201484.3-201524.6" + wire width 64 $2\core_msr$next[63:0]$13944 + attribute \src "libresoc.v:202060.3-202080.6" + wire width 3 $2\core_msr__ren[2:0] + attribute \src "libresoc.v:201525.3-201554.6" + wire width 32 $2\core_raw_insn_i$next[31:0]$13958 + attribute \src "libresoc.v:202743.3-202858.6" + wire $2\core_rego_ok$next[0:0]$14335 + attribute \src "libresoc.v:202743.3-202858.6" + wire $2\core_spro_ok$next[0:0]$14336 + attribute \src "libresoc.v:202410.3-202428.6" + wire $2\core_stopped_i[0:0] + attribute \src "libresoc.v:202039.3-202059.6" + wire width 3 $2\core_sv__ren[2:0] + attribute \src "libresoc.v:201997.3-202017.6" + wire width 3 $2\core_wen[2:0] + attribute \src "libresoc.v:202743.3-202858.6" + wire $2\core_xer_out$next[0:0]$14337 + attribute \src "libresoc.v:202478.3-202510.6" + wire width 7 $2\cur_cur_dststep$next[6:0]$14093 + attribute \src "libresoc.v:202478.3-202510.6" + wire width 7 $2\cur_cur_maxvl$next[6:0]$14094 + attribute \src "libresoc.v:202478.3-202510.6" + wire width 2 $2\cur_cur_subvl$next[1:0]$14095 + attribute \src "libresoc.v:202478.3-202510.6" + wire width 2 $2\cur_cur_svstep$next[1:0]$14096 + attribute \src "libresoc.v:202478.3-202510.6" + wire width 7 $2\cur_cur_vl$next[6:0]$14097 + attribute \src "libresoc.v:202429.3-202447.6" + wire $2\dbg_core_stopped_i[0:0] + attribute \src "libresoc.v:202478.3-202510.6" + wire width 7 $2\dec2_cur_cur_srcstep$next[6:0]$14098 + attribute \src "libresoc.v:201923.3-201938.6" + wire width 64 $2\dec2_cur_dec$next[63:0]$14019 + attribute \src "libresoc.v:202457.3-202477.6" + wire width 64 $2\dec2_cur_msr$next[63:0]$14078 + attribute \src "libresoc.v:202247.3-202272.6" + wire width 64 $2\dec2_cur_pc$next[63:0]$14043 + attribute \src "libresoc.v:202549.3-202586.6" + wire width 9 $2\dec2_dec_svp64__extra$next[8:0]$14122 + attribute \src "libresoc.v:202727.3-202742.6" + wire width 32 $2\dec2_raw_opcode_in[31:0] + attribute \src "libresoc.v:202549.3-202586.6" + wire width 2 $2\dec_svp64__elwidth$next[1:0]$14123 + attribute \src "libresoc.v:202549.3-202586.6" + wire width 2 $2\dec_svp64__ewsrc$next[1:0]$14124 + attribute \src "libresoc.v:202549.3-202586.6" + wire width 3 $2\dec_svp64__mask$next[2:0]$14125 + attribute \src "libresoc.v:202549.3-202586.6" + wire $2\dec_svp64__mmode$next[0:0]$14126 + attribute \src "libresoc.v:202549.3-202586.6" + wire width 5 $2\dec_svp64__mode$next[4:0]$14127 + attribute \src "libresoc.v:202549.3-202586.6" + wire width 2 $2\dec_svp64__subvl$next[1:0]$14128 + attribute \src "libresoc.v:202343.3-202409.6" + wire width 2 $2\fetch_fsm_state$next[1:0]$14063 + attribute \src "libresoc.v:202615.3-202650.6" + wire width 32 $2\fetch_insn_o$next[31:0]$14146 + attribute \src "libresoc.v:202090.3-202105.6" + wire $2\fetch_pc_ready_o[0:0] + attribute \src "libresoc.v:201839.3-201866.6" + wire width 2 $2\fsm_state$188$next[1:0]$14009 + attribute \src "libresoc.v:202673.3-202715.6" + wire width 2 $2\fsm_state$next[1:0]$14154 + attribute \src "libresoc.v:201585.3-201605.6" + wire width 32 $2\ilatch$next[31:0]$13970 + attribute \src "libresoc.v:202106.3-202146.6" + wire width 48 $2\imem_a_pc_i[47:0] + attribute \src "libresoc.v:202147.3-202196.6" + wire $2\imem_a_valid_i[0:0] + attribute \src "libresoc.v:202197.3-202246.6" + wire $2\imem_f_valid_i[0:0] + attribute \src "libresoc.v:202273.3-202307.6" + wire $2\msr_read$next[0:0]$14049 + attribute \src "libresoc.v:202596.3-202614.6" + wire width 64 $2\nia$next[63:0]$14142 + attribute \src "libresoc.v:201968.3-201983.6" + wire width 64 $2\pc[63:0] + attribute \src "libresoc.v:201637.3-201661.6" + wire $2\pc_changed$next[0:0]$13977 + attribute \src "libresoc.v:202308.3-202342.6" + wire $2\sv_read$next[0:0]$14056 + attribute \src "libresoc.v:202530.3-202548.6" + wire $2\svp64_bigendian[0:0] + attribute \src "libresoc.v:202511.3-202529.6" + wire width 32 $2\svp64_raw_opcode_in[31:0] + attribute \src "libresoc.v:202743.3-202858.6" + wire width 8 $3\core_asmcode$next[7:0]$14338 + attribute \src "libresoc.v:201555.3-201584.6" + wire $3\core_bigendian_i$10$next[0:0]$13965 + attribute \src "libresoc.v:202743.3-202858.6" + wire width 64 $3\core_core_core_cia$next[63:0]$14339 + attribute \src "libresoc.v:202743.3-202858.6" + wire width 8 $3\core_core_core_cr_rd$next[7:0]$14340 + attribute \src "libresoc.v:202743.3-202858.6" + wire $3\core_core_core_cr_rd_ok$next[0:0]$14341 + attribute \src "libresoc.v:202743.3-202858.6" + wire width 8 $3\core_core_core_cr_wr$next[7:0]$14342 + attribute \src "libresoc.v:202743.3-202858.6" + wire $3\core_core_core_exc_$signal$3$next[0:0]$14343 + attribute \src "libresoc.v:202743.3-202858.6" + wire $3\core_core_core_exc_$signal$4$next[0:0]$14344 + attribute \src "libresoc.v:202743.3-202858.6" + wire $3\core_core_core_exc_$signal$5$next[0:0]$14345 + attribute \src "libresoc.v:202743.3-202858.6" + wire $3\core_core_core_exc_$signal$6$next[0:0]$14346 + attribute \src "libresoc.v:202743.3-202858.6" + wire $3\core_core_core_exc_$signal$7$next[0:0]$14347 + attribute \src "libresoc.v:202743.3-202858.6" + wire $3\core_core_core_exc_$signal$8$next[0:0]$14348 + attribute \src "libresoc.v:202743.3-202858.6" + wire $3\core_core_core_exc_$signal$9$next[0:0]$14349 + attribute \src "libresoc.v:202743.3-202858.6" + wire $3\core_core_core_exc_$signal$next[0:0]$14350 + attribute \src "libresoc.v:202743.3-202858.6" + wire width 13 $3\core_core_core_fn_unit$next[12:0]$14351 + attribute \src "libresoc.v:202743.3-202858.6" + wire width 2 $3\core_core_core_input_carry$next[1:0]$14352 + attribute \src "libresoc.v:202743.3-202858.6" + wire width 32 $3\core_core_core_insn$next[31:0]$14353 + attribute \src "libresoc.v:202743.3-202858.6" + wire width 7 $3\core_core_core_insn_type$next[6:0]$14354 + attribute \src "libresoc.v:202743.3-202858.6" + wire $3\core_core_core_is_32bit$next[0:0]$14355 + attribute \src "libresoc.v:202743.3-202858.6" + wire width 64 $3\core_core_core_msr$next[63:0]$14356 + attribute \src "libresoc.v:202743.3-202858.6" + wire $3\core_core_core_oe$next[0:0]$14357 + attribute \src "libresoc.v:202743.3-202858.6" + wire $3\core_core_core_oe_ok$next[0:0]$14358 + attribute \src "libresoc.v:202743.3-202858.6" + wire $3\core_core_core_rc$next[0:0]$14359 + attribute \src "libresoc.v:202743.3-202858.6" + wire $3\core_core_core_rc_ok$next[0:0]$14360 + attribute \src "libresoc.v:202743.3-202858.6" + wire width 13 $3\core_core_core_trapaddr$next[12:0]$14361 + attribute \src "libresoc.v:202743.3-202858.6" + wire width 8 $3\core_core_core_traptype$next[7:0]$14362 + attribute \src "libresoc.v:202743.3-202858.6" + wire width 7 $3\core_core_cr_in1$next[6:0]$14363 + attribute \src "libresoc.v:202743.3-202858.6" + wire $3\core_core_cr_in1_ok$next[0:0]$14364 + attribute \src "libresoc.v:202743.3-202858.6" + wire width 7 $3\core_core_cr_in2$1$next[6:0]$14365 + attribute \src "libresoc.v:202743.3-202858.6" + wire width 7 $3\core_core_cr_in2$next[6:0]$14366 + attribute \src "libresoc.v:202743.3-202858.6" + wire $3\core_core_cr_in2_ok$2$next[0:0]$14367 + attribute \src "libresoc.v:202743.3-202858.6" + wire $3\core_core_cr_in2_ok$next[0:0]$14368 + attribute \src "libresoc.v:202743.3-202858.6" + wire width 7 $3\core_core_cr_out$next[6:0]$14369 + attribute \src "libresoc.v:202743.3-202858.6" + wire $3\core_core_cr_wr_ok$next[0:0]$14370 + attribute \src "libresoc.v:201484.3-201524.6" + wire width 7 $3\core_core_dststep$next[6:0]$13945 + attribute \src "libresoc.v:202743.3-202858.6" + wire width 7 $3\core_core_ea$next[6:0]$14371 + attribute \src "libresoc.v:202743.3-202858.6" + wire width 3 $3\core_core_fast1$next[2:0]$14372 + attribute \src "libresoc.v:202743.3-202858.6" + wire $3\core_core_fast1_ok$next[0:0]$14373 + attribute \src "libresoc.v:202743.3-202858.6" + wire width 3 $3\core_core_fast2$next[2:0]$14374 + attribute \src "libresoc.v:202743.3-202858.6" + wire $3\core_core_fast2_ok$next[0:0]$14375 + attribute \src "libresoc.v:202743.3-202858.6" + wire width 3 $3\core_core_fasto1$next[2:0]$14376 + attribute \src "libresoc.v:202743.3-202858.6" + wire width 3 $3\core_core_fasto2$next[2:0]$14377 + attribute \src "libresoc.v:202743.3-202858.6" + wire $3\core_core_lk$next[0:0]$14378 + attribute \src "libresoc.v:201484.3-201524.6" + wire width 7 $3\core_core_maxvl$next[6:0]$13946 + attribute \src "libresoc.v:201484.3-201524.6" + wire width 64 $3\core_core_pc$next[63:0]$13947 + attribute \src "libresoc.v:202743.3-202858.6" + wire width 7 $3\core_core_reg1$next[6:0]$14379 + attribute \src "libresoc.v:202743.3-202858.6" + wire $3\core_core_reg1_ok$next[0:0]$14380 + attribute \src "libresoc.v:202743.3-202858.6" + wire width 7 $3\core_core_reg2$next[6:0]$14381 + attribute \src "libresoc.v:202743.3-202858.6" + wire $3\core_core_reg2_ok$next[0:0]$14382 + attribute \src "libresoc.v:202743.3-202858.6" + wire width 7 $3\core_core_reg3$next[6:0]$14383 + attribute \src "libresoc.v:202743.3-202858.6" + wire $3\core_core_reg3_ok$next[0:0]$14384 + attribute \src "libresoc.v:202743.3-202858.6" + wire width 7 $3\core_core_rego$next[6:0]$14385 + attribute \src "libresoc.v:202743.3-202858.6" + wire width 10 $3\core_core_spr1$next[9:0]$14386 + attribute \src "libresoc.v:202743.3-202858.6" + wire $3\core_core_spr1_ok$next[0:0]$14387 + attribute \src "libresoc.v:202743.3-202858.6" + wire width 10 $3\core_core_spro$next[9:0]$14388 + attribute \src "libresoc.v:201484.3-201524.6" + wire width 7 $3\core_core_srcstep$next[6:0]$13948 + attribute \src "libresoc.v:201484.3-201524.6" + wire width 2 $3\core_core_subvl$next[1:0]$13949 + attribute \src "libresoc.v:201484.3-201524.6" + wire width 2 $3\core_core_svstep$next[1:0]$13950 + attribute \src "libresoc.v:201484.3-201524.6" + wire width 7 $3\core_core_vl$next[6:0]$13951 + attribute \src "libresoc.v:202743.3-202858.6" + wire width 3 $3\core_core_xer_in$next[2:0]$14389 + attribute \src "libresoc.v:202743.3-202858.6" + wire $3\core_cr_out_ok$next[0:0]$14390 + attribute \src "libresoc.v:202018.3-202038.6" + wire width 64 $3\core_data_i[63:0] + attribute \src "libresoc.v:201484.3-201524.6" + wire width 64 $3\core_dec$next[63:0]$13952 + attribute \src "libresoc.v:202743.3-202858.6" + wire $3\core_ea_ok$next[0:0]$14391 + attribute \src "libresoc.v:201484.3-201524.6" + wire $3\core_eint$next[0:0]$13953 + attribute \src "libresoc.v:202743.3-202858.6" + wire $3\core_fasto1_ok$next[0:0]$14392 + attribute \src "libresoc.v:202743.3-202858.6" + wire $3\core_fasto2_ok$next[0:0]$14393 + attribute \src "libresoc.v:201484.3-201524.6" + wire width 64 $3\core_msr$next[63:0]$13954 + attribute \src "libresoc.v:202060.3-202080.6" + wire width 3 $3\core_msr__ren[2:0] + attribute \src "libresoc.v:201525.3-201554.6" + wire width 32 $3\core_raw_insn_i$next[31:0]$13959 + attribute \src "libresoc.v:202743.3-202858.6" + wire $3\core_rego_ok$next[0:0]$14394 + attribute \src "libresoc.v:202743.3-202858.6" + wire $3\core_spro_ok$next[0:0]$14395 + attribute \src "libresoc.v:202039.3-202059.6" + wire width 3 $3\core_sv__ren[2:0] + attribute \src "libresoc.v:201997.3-202017.6" + wire width 3 $3\core_wen[2:0] + attribute \src "libresoc.v:202743.3-202858.6" + wire $3\core_xer_out$next[0:0]$14396 + attribute \src "libresoc.v:202478.3-202510.6" + wire width 7 $3\cur_cur_dststep$next[6:0]$14099 + attribute \src "libresoc.v:202478.3-202510.6" + wire width 7 $3\cur_cur_maxvl$next[6:0]$14100 + attribute \src "libresoc.v:202478.3-202510.6" + wire width 2 $3\cur_cur_subvl$next[1:0]$14101 + attribute \src "libresoc.v:202478.3-202510.6" + wire width 2 $3\cur_cur_svstep$next[1:0]$14102 + attribute \src "libresoc.v:202478.3-202510.6" + wire width 7 $3\cur_cur_vl$next[6:0]$14103 + attribute \src "libresoc.v:202478.3-202510.6" + wire width 7 $3\dec2_cur_cur_srcstep$next[6:0]$14104 + attribute \src "libresoc.v:202457.3-202477.6" + wire width 64 $3\dec2_cur_msr$next[63:0]$14079 + attribute \src "libresoc.v:202247.3-202272.6" + wire width 64 $3\dec2_cur_pc$next[63:0]$14044 + attribute \src "libresoc.v:202549.3-202586.6" + wire width 9 $3\dec2_dec_svp64__extra$next[8:0]$14129 + attribute \src "libresoc.v:202549.3-202586.6" + wire width 2 $3\dec_svp64__elwidth$next[1:0]$14130 + attribute \src "libresoc.v:202549.3-202586.6" + wire width 2 $3\dec_svp64__ewsrc$next[1:0]$14131 + attribute \src "libresoc.v:202549.3-202586.6" + wire width 3 $3\dec_svp64__mask$next[2:0]$14132 + attribute \src "libresoc.v:202549.3-202586.6" + wire $3\dec_svp64__mmode$next[0:0]$14133 + attribute \src "libresoc.v:202549.3-202586.6" + wire width 5 $3\dec_svp64__mode$next[4:0]$14134 + attribute \src "libresoc.v:202549.3-202586.6" + wire width 2 $3\dec_svp64__subvl$next[1:0]$14135 + attribute \src "libresoc.v:202343.3-202409.6" + wire width 2 $3\fetch_fsm_state$next[1:0]$14064 + attribute \src "libresoc.v:202615.3-202650.6" + wire width 32 $3\fetch_insn_o$next[31:0]$14147 + attribute \src "libresoc.v:202673.3-202715.6" + wire width 2 $3\fsm_state$next[1:0]$14155 + attribute \src "libresoc.v:201585.3-201605.6" + wire width 32 $3\ilatch$next[31:0]$13971 + attribute \src "libresoc.v:202106.3-202146.6" + wire width 48 $3\imem_a_pc_i[47:0] + attribute \src "libresoc.v:202147.3-202196.6" + wire $3\imem_a_valid_i[0:0] + attribute \src "libresoc.v:202197.3-202246.6" + wire $3\imem_f_valid_i[0:0] + attribute \src "libresoc.v:202273.3-202307.6" + wire $3\msr_read$next[0:0]$14050 + attribute \src "libresoc.v:201637.3-201661.6" + wire $3\pc_changed$next[0:0]$13978 + attribute \src "libresoc.v:202308.3-202342.6" + wire $3\sv_read$next[0:0]$14057 + attribute \src "libresoc.v:201555.3-201584.6" + wire $4\core_bigendian_i$10$next[0:0]$13966 + attribute \src "libresoc.v:202743.3-202858.6" + wire $4\core_core_core_cr_rd_ok$next[0:0]$14397 + attribute \src "libresoc.v:202743.3-202858.6" + wire $4\core_core_core_exc_$signal$3$next[0:0]$14398 + attribute \src "libresoc.v:202743.3-202858.6" + wire $4\core_core_core_exc_$signal$4$next[0:0]$14399 + attribute \src "libresoc.v:202743.3-202858.6" + wire $4\core_core_core_exc_$signal$5$next[0:0]$14400 + attribute \src "libresoc.v:202743.3-202858.6" + wire $4\core_core_core_exc_$signal$6$next[0:0]$14401 + attribute \src "libresoc.v:202743.3-202858.6" + wire $4\core_core_core_exc_$signal$7$next[0:0]$14402 + attribute \src "libresoc.v:202743.3-202858.6" + wire $4\core_core_core_exc_$signal$8$next[0:0]$14403 + attribute \src "libresoc.v:202743.3-202858.6" + wire $4\core_core_core_exc_$signal$9$next[0:0]$14404 + attribute \src "libresoc.v:202743.3-202858.6" + wire $4\core_core_core_exc_$signal$next[0:0]$14405 + attribute \src "libresoc.v:202743.3-202858.6" + wire $4\core_core_core_oe_ok$next[0:0]$14406 + attribute \src "libresoc.v:202743.3-202858.6" + wire $4\core_core_core_rc_ok$next[0:0]$14407 + attribute \src "libresoc.v:202743.3-202858.6" + wire $4\core_core_cr_in1_ok$next[0:0]$14408 + attribute \src "libresoc.v:202743.3-202858.6" + wire $4\core_core_cr_in2_ok$2$next[0:0]$14409 + attribute \src "libresoc.v:202743.3-202858.6" + wire $4\core_core_cr_in2_ok$next[0:0]$14410 + attribute \src "libresoc.v:202743.3-202858.6" + wire $4\core_core_cr_wr_ok$next[0:0]$14411 + attribute \src "libresoc.v:202743.3-202858.6" + wire $4\core_core_fast1_ok$next[0:0]$14412 + attribute \src "libresoc.v:202743.3-202858.6" + wire $4\core_core_fast2_ok$next[0:0]$14413 + attribute \src "libresoc.v:202743.3-202858.6" + wire $4\core_core_reg1_ok$next[0:0]$14414 + attribute \src "libresoc.v:202743.3-202858.6" + wire $4\core_core_reg2_ok$next[0:0]$14415 + attribute \src "libresoc.v:202743.3-202858.6" + wire $4\core_core_reg3_ok$next[0:0]$14416 + attribute \src "libresoc.v:202743.3-202858.6" + wire $4\core_core_spr1_ok$next[0:0]$14417 + attribute \src "libresoc.v:202743.3-202858.6" + wire $4\core_cr_out_ok$next[0:0]$14418 + attribute \src "libresoc.v:202743.3-202858.6" + wire $4\core_ea_ok$next[0:0]$14419 + attribute \src "libresoc.v:202743.3-202858.6" + wire $4\core_fasto1_ok$next[0:0]$14420 + attribute \src "libresoc.v:202743.3-202858.6" + wire $4\core_fasto2_ok$next[0:0]$14421 + attribute \src "libresoc.v:201525.3-201554.6" + wire width 32 $4\core_raw_insn_i$next[31:0]$13960 + attribute \src "libresoc.v:202743.3-202858.6" + wire $4\core_rego_ok$next[0:0]$14422 + attribute \src "libresoc.v:202743.3-202858.6" + wire $4\core_spro_ok$next[0:0]$14423 + attribute \src "libresoc.v:202247.3-202272.6" + wire width 64 $4\dec2_cur_pc$next[63:0]$14045 + attribute \src "libresoc.v:202343.3-202409.6" + wire width 2 $4\fetch_fsm_state$next[1:0]$14065 + attribute \src "libresoc.v:202615.3-202650.6" + wire width 32 $4\fetch_insn_o$next[31:0]$14148 + attribute \src "libresoc.v:202673.3-202715.6" + wire width 2 $4\fsm_state$next[1:0]$14156 + attribute \src "libresoc.v:202106.3-202146.6" + wire width 48 $4\imem_a_pc_i[47:0] + attribute \src "libresoc.v:202147.3-202196.6" + wire $4\imem_a_valid_i[0:0] + attribute \src "libresoc.v:202197.3-202246.6" + wire $4\imem_f_valid_i[0:0] + attribute \src "libresoc.v:202273.3-202307.6" + wire $4\msr_read$next[0:0]$14051 + attribute \src "libresoc.v:202308.3-202342.6" + wire $4\sv_read$next[0:0]$14058 + attribute \src "libresoc.v:202343.3-202409.6" + wire width 2 $5\fetch_fsm_state$next[1:0]$14066 + attribute \src "libresoc.v:202673.3-202715.6" + wire width 2 $5\fsm_state$next[1:0]$14157 + attribute \src "libresoc.v:202106.3-202146.6" + wire width 48 $5\imem_a_pc_i[47:0] + attribute \src "libresoc.v:202147.3-202196.6" + wire $5\imem_a_valid_i[0:0] + attribute \src "libresoc.v:202197.3-202246.6" + wire $5\imem_f_valid_i[0:0] + attribute \src "libresoc.v:202273.3-202307.6" + wire $5\msr_read$next[0:0]$14052 + attribute \src "libresoc.v:202308.3-202342.6" + wire $5\sv_read$next[0:0]$14059 + attribute \src "libresoc.v:202343.3-202409.6" + wire width 2 $6\fetch_fsm_state$next[1:0]$14067 + attribute \src "libresoc.v:202147.3-202196.6" + wire $6\imem_a_valid_i[0:0] + attribute \src "libresoc.v:202197.3-202246.6" + wire $6\imem_f_valid_i[0:0] + attribute \src "libresoc.v:202343.3-202409.6" + wire width 2 $7\fetch_fsm_state$next[1:0]$14068 + attribute \src "libresoc.v:202343.3-202409.6" + wire width 2 $8\fetch_fsm_state$next[1:0]$14069 + attribute \src "libresoc.v:200564.19-200564.109" + wire width 65 $add$libresoc.v:200564$13726_Y + attribute \src "libresoc.v:200568.19-200568.108" + wire width 65 $add$libresoc.v:200568$13730_Y + attribute \src "libresoc.v:200575.19-200575.108" + wire width 65 $add$libresoc.v:200575$13737_Y + attribute \src "libresoc.v:200585.19-200585.115" + wire width 65 $add$libresoc.v:200585$13749_Y + attribute \src "libresoc.v:200611.18-200611.107" + wire width 65 $add$libresoc.v:200611$13775_Y + attribute \src "libresoc.v:200543.19-200543.103" + wire $and$libresoc.v:200543$13705_Y + attribute \src "libresoc.v:200547.19-200547.104" + wire $and$libresoc.v:200547$13709_Y + attribute \src "libresoc.v:200551.19-200551.104" + wire $and$libresoc.v:200551$13713_Y + attribute \src "libresoc.v:200555.19-200555.104" + wire $and$libresoc.v:200555$13717_Y + attribute \src "libresoc.v:200558.19-200558.104" + wire $and$libresoc.v:200558$13720_Y + attribute \src "libresoc.v:200579.19-200579.115" + wire width 3 $and$libresoc.v:200579$13741_Y + attribute \src "libresoc.v:200592.18-200592.109" + wire $and$libresoc.v:200592$13756_Y + attribute \src "libresoc.v:200600.18-200600.101" + wire $and$libresoc.v:200600$13764_Y + attribute \src "libresoc.v:200603.18-200603.101" + wire $and$libresoc.v:200603$13767_Y + attribute \src "libresoc.v:200606.18-200606.101" + wire $and$libresoc.v:200606$13770_Y + attribute \src "libresoc.v:200609.18-200609.101" + wire $and$libresoc.v:200609$13773_Y + attribute \src "libresoc.v:200614.18-200614.101" + wire $and$libresoc.v:200614$13778_Y + attribute \src "libresoc.v:200618.18-200618.101" + wire $and$libresoc.v:200618$13782_Y + attribute \src "libresoc.v:200622.18-200622.101" + wire $and$libresoc.v:200622$13786_Y + attribute \src "libresoc.v:200582.19-200582.114" + wire width 64 $extend$libresoc.v:200582$13744_Y + attribute \src "libresoc.v:200583.19-200583.113" + wire width 64 $extend$libresoc.v:200583$13746_Y + attribute \src "libresoc.v:200561.19-200561.111" + wire width 7 $mul$libresoc.v:200561$13723_Y + attribute \src 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attribute \enum_value_1100110111 "PSSCR" + attribute \enum_value_1101010000 "IC" + attribute \enum_value_1101010001 "VTB" + attribute \enum_value_1101010111 "PSSCR_hypv" + attribute \enum_value_1110000000 "PPR" + attribute \enum_value_1110000010 "PPR32" + attribute \enum_value_1111111111 "PIR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 10 \dec2_spro + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire \dec2_spro_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:55" + wire width 13 \dec2_trapaddr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:53" + wire width 8 \dec2_traptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:104" + wire width 3 \dec2_xer_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:105" + wire \dec2_xer_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svp64.py:31" + wire width 2 \dec_svp64__elwidth + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svp64.py:31" + wire width 2 \dec_svp64__elwidth$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svp64.py:31" + wire width 2 \dec_svp64__ewsrc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svp64.py:31" + wire width 2 \dec_svp64__ewsrc$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svp64.py:31" + wire width 3 \dec_svp64__mask + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svp64.py:31" + wire width 3 \dec_svp64__mask$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svp64.py:31" + wire \dec_svp64__mmode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svp64.py:31" + wire \dec_svp64__mmode$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svp64.py:31" + wire width 5 \dec_svp64__mode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svp64.py:31" + wire width 5 \dec_svp64__mode$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svp64.py:31" + wire width 2 \dec_svp64__subvl + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svp64.py:31" + wire width 2 \dec_svp64__subvl$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:199" + wire width 2 \delay + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:199" + wire width 2 \delay$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 179 \eint_0__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 24 \eint_0__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 180 \eint_1__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 25 \eint_1__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 181 \eint_2__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 26 \eint_2__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:290" + wire width 2 \fetch_fsm_state + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:290" + wire width 2 \fetch_fsm_state$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:278" + wire width 32 \fetch_insn_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:278" + wire width 32 \fetch_insn_o$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:275" + wire \fetch_insn_ready_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:274" + wire \fetch_insn_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:272" + wire \fetch_pc_ready_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:271" + wire \fetch_pc_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:375" + wire width 2 \fsm_state + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:492" + wire width 2 \fsm_state$188 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:492" + wire width 2 \fsm_state$188$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:375" + wire width 2 \fsm_state$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 188 \gpio_e10__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 34 \gpio_e10__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 35 \gpio_e10__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 33 \gpio_e10__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 189 \gpio_e10__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 190 \gpio_e10__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 191 \gpio_e11__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 37 \gpio_e11__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 38 \gpio_e11__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 36 \gpio_e11__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 192 \gpio_e11__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 193 \gpio_e11__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 194 \gpio_e12__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 40 \gpio_e12__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 41 \gpio_e12__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 39 \gpio_e12__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 195 \gpio_e12__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 196 \gpio_e12__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 197 \gpio_e13__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 43 \gpio_e13__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 44 \gpio_e13__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 42 \gpio_e13__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 198 \gpio_e13__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 199 \gpio_e13__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 200 \gpio_e14__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 46 \gpio_e14__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 47 \gpio_e14__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 45 \gpio_e14__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 201 \gpio_e14__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 202 \gpio_e14__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 203 \gpio_e15__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 49 \gpio_e15__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 50 \gpio_e15__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 48 \gpio_e15__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 204 \gpio_e15__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 205 \gpio_e15__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 182 \gpio_e8__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 28 \gpio_e8__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 29 \gpio_e8__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 27 \gpio_e8__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 183 \gpio_e8__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 184 \gpio_e8__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 185 \gpio_e9__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 31 \gpio_e9__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 32 \gpio_e9__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 30 \gpio_e9__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 186 \gpio_e9__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 187 \gpio_e9__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 206 \gpio_s0__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 52 \gpio_s0__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 53 \gpio_s0__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 51 \gpio_s0__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 207 \gpio_s0__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 208 \gpio_s0__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 209 \gpio_s1__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 55 \gpio_s1__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 56 \gpio_s1__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 54 \gpio_s1__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 210 \gpio_s1__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 211 \gpio_s1__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 212 \gpio_s2__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 58 \gpio_s2__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 59 \gpio_s2__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 57 \gpio_s2__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 213 \gpio_s2__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 214 \gpio_s2__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 215 \gpio_s3__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 61 \gpio_s3__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 62 \gpio_s3__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 60 \gpio_s3__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 216 \gpio_s3__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 217 \gpio_s3__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 218 \gpio_s4__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 64 \gpio_s4__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 65 \gpio_s4__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 63 \gpio_s4__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 219 \gpio_s4__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 220 \gpio_s4__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 221 \gpio_s5__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 67 \gpio_s5__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 68 \gpio_s5__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 66 \gpio_s5__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 222 \gpio_s5__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 223 \gpio_s5__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 224 \gpio_s6__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 70 \gpio_s6__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 71 \gpio_s6__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 69 \gpio_s6__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 225 \gpio_s6__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 226 \gpio_s6__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 227 \gpio_s7__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 73 \gpio_s7__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 74 \gpio_s7__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 72 \gpio_s7__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 228 \gpio_s7__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 229 \gpio_s7__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire input 18 \ibus__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire width 45 output 23 \ibus__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire output 17 \ibus__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire width 64 input 22 \ibus__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire input 19 \ibus__err + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire width 8 output 21 \ibus__sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire output 20 \ibus__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire output 376 \icp_wb__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire width 28 input 382 \icp_wb__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire input 377 \icp_wb__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire width 32 output 378 \icp_wb__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire width 32 input 379 \icp_wb__dat_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire width 4 input 383 \icp_wb__sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire input 380 \icp_wb__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire input 381 \icp_wb__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire output 389 \ics_wb__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire width 28 input 384 \ics_wb__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire input 386 \ics_wb__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire width 32 output 388 \ics_wb__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire width 32 input 390 \ics_wb__dat_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire input 387 \ics_wb__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire input 391 \ics_wb__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:223" + wire width 32 \ilatch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:223" + wire width 32 \ilatch$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:24" + wire width 48 \imem_a_pc_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:26" + wire \imem_a_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:32" + wire \imem_f_busy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:33" + wire width 64 \imem_f_instr_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:28" + wire \imem_f_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:92" + wire \imem_wb_icache_en + attribute \src "libresoc.v:198206.7-198206.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:237" + wire width 16 input 385 \int_level_i + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" + wire \jtag_dmi0__ack_o + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" + wire \jtag_dmi0__ack_o$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" + wire width 4 \jtag_dmi0__addr_i + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" + wire width 64 \jtag_dmi0__din + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" + wire width 64 \jtag_dmi0__dout + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" + wire width 64 \jtag_dmi0__dout$next + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" + wire \jtag_dmi0__req_i + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" + wire \jtag_dmi0__we_i + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire input 340 \jtag_wb__ack + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire width 29 output 334 \jtag_wb__adr + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire output 336 \jtag_wb__cyc + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire width 64 input 341 \jtag_wb__dat_r + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire width 64 output 339 \jtag_wb__dat_w + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire output 335 \jtag_wb__sel + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire output 337 \jtag_wb__stb + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" + wire output 338 \jtag_wb__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 75 \mspi0_clk__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 230 \mspi0_clk__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 76 \mspi0_cs_n__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 231 \mspi0_cs_n__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 233 \mspi0_miso__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 78 \mspi0_miso__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 77 \mspi0_mosi__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 232 \mspi0_mosi__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 79 \mspi1_clk__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 234 \mspi1_clk__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 80 \mspi1_cs_n__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 235 \mspi1_cs_n__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 237 \mspi1_miso__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 82 \mspi1_miso__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 81 \mspi1_mosi__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 236 \mspi1_mosi__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:250" + wire \msr_read + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:250" + wire \msr_read$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 86 \mtwi_scl__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 241 \mtwi_scl__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 238 \mtwi_sda__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 84 \mtwi_sda__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 85 \mtwi_sda__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 83 \mtwi_sda__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 239 \mtwi_sda__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 240 \mtwi_sda__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:502" + wire width 64 \new_dec + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:28" + wire width 7 \new_svstate_dststep + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:31" + wire width 7 \new_svstate_maxvl + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:29" + wire width 7 \new_svstate_srcstep + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:27" + wire width 2 \new_svstate_subvl + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:26" + wire width 2 \new_svstate_svstep + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:30" + wire width 7 \new_svstate_vl + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:519" + wire width 64 \new_tb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:227" + wire width 64 \nia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:227" + wire width 64 \nia$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:230" + wire width 64 \pc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:221" + wire \pc_changed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:221" + wire \pc_changed$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire width 64 input 7 \pc_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" + wire input 6 \pc_i_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:120" + wire width 64 output 5 \pc_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:231" + wire \pc_ok_delay + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:231" + wire \pc_ok_delay$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:193" + wire \por_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 87 \pwm_0__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 242 \pwm_0__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 88 \pwm_1__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 243 \pwm_1__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:194" + wire input 1 \rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 92 \sd0_clk__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 247 \sd0_clk__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 244 \sd0_cmd__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 90 \sd0_cmd__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 91 \sd0_cmd__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 89 \sd0_cmd__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 245 \sd0_cmd__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 246 \sd0_cmd__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 248 \sd0_data0__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 94 \sd0_data0__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 95 \sd0_data0__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 93 \sd0_data0__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 249 \sd0_data0__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 250 \sd0_data0__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 251 \sd0_data1__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 97 \sd0_data1__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 98 \sd0_data1__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 96 \sd0_data1__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 252 \sd0_data1__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 253 \sd0_data1__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 254 \sd0_data2__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 100 \sd0_data2__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 101 \sd0_data2__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 99 \sd0_data2__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 255 \sd0_data2__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 256 \sd0_data2__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 257 \sd0_data3__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 103 \sd0_data3__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 104 \sd0_data3__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 102 \sd0_data3__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 258 \sd0_data3__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 259 \sd0_data3__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 130 \sdr_a_0__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 285 \sdr_a_0__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 148 \sdr_a_10__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 303 \sdr_a_10__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 149 \sdr_a_11__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 304 \sdr_a_11__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 150 \sdr_a_12__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 305 \sdr_a_12__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 131 \sdr_a_1__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 286 \sdr_a_1__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 132 \sdr_a_2__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 287 \sdr_a_2__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 133 \sdr_a_3__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 288 \sdr_a_3__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 134 \sdr_a_4__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 289 \sdr_a_4__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 135 \sdr_a_5__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 290 \sdr_a_5__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 136 \sdr_a_6__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 291 \sdr_a_6__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 137 \sdr_a_7__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 292 \sdr_a_7__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 138 \sdr_a_8__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 293 \sdr_a_8__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 139 \sdr_a_9__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 294 \sdr_a_9__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 140 \sdr_ba_0__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 295 \sdr_ba_0__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 141 \sdr_ba_1__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 296 \sdr_ba_1__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 145 \sdr_cas_n__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 300 \sdr_cas_n__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 143 \sdr_cke__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 298 \sdr_cke__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 142 \sdr_clock__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 297 \sdr_clock__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 147 \sdr_cs_n__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 302 \sdr_cs_n__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 105 \sdr_dm_0__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 260 \sdr_dm_0__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 306 \sdr_dm_1__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 152 \sdr_dm_1__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 153 \sdr_dm_1__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 151 \sdr_dm_1__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 307 \sdr_dm_1__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 308 \sdr_dm_1__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 261 \sdr_dq_0__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 107 \sdr_dq_0__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 108 \sdr_dq_0__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 106 \sdr_dq_0__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 262 \sdr_dq_0__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 263 \sdr_dq_0__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 315 \sdr_dq_10__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 161 \sdr_dq_10__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 162 \sdr_dq_10__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 160 \sdr_dq_10__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 316 \sdr_dq_10__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 317 \sdr_dq_10__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 318 \sdr_dq_11__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 164 \sdr_dq_11__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 165 \sdr_dq_11__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 163 \sdr_dq_11__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 319 \sdr_dq_11__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 320 \sdr_dq_11__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 321 \sdr_dq_12__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 167 \sdr_dq_12__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 168 \sdr_dq_12__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 166 \sdr_dq_12__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 322 \sdr_dq_12__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 323 \sdr_dq_12__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 324 \sdr_dq_13__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 170 \sdr_dq_13__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 171 \sdr_dq_13__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 169 \sdr_dq_13__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 325 \sdr_dq_13__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 326 \sdr_dq_13__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 327 \sdr_dq_14__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 173 \sdr_dq_14__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 174 \sdr_dq_14__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 172 \sdr_dq_14__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 328 \sdr_dq_14__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 329 \sdr_dq_14__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 330 \sdr_dq_15__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 176 \sdr_dq_15__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 177 \sdr_dq_15__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 175 \sdr_dq_15__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 331 \sdr_dq_15__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 332 \sdr_dq_15__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 264 \sdr_dq_1__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 110 \sdr_dq_1__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 111 \sdr_dq_1__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 109 \sdr_dq_1__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 265 \sdr_dq_1__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 266 \sdr_dq_1__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 267 \sdr_dq_2__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 113 \sdr_dq_2__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 114 \sdr_dq_2__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 112 \sdr_dq_2__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 268 \sdr_dq_2__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 269 \sdr_dq_2__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 270 \sdr_dq_3__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 116 \sdr_dq_3__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 117 \sdr_dq_3__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 115 \sdr_dq_3__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 271 \sdr_dq_3__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 272 \sdr_dq_3__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 273 \sdr_dq_4__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 119 \sdr_dq_4__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 120 \sdr_dq_4__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 118 \sdr_dq_4__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 274 \sdr_dq_4__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 275 \sdr_dq_4__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 276 \sdr_dq_5__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 122 \sdr_dq_5__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 123 \sdr_dq_5__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 121 \sdr_dq_5__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 277 \sdr_dq_5__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 278 \sdr_dq_5__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 279 \sdr_dq_6__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 125 \sdr_dq_6__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 126 \sdr_dq_6__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 124 \sdr_dq_6__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 280 \sdr_dq_6__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 281 \sdr_dq_6__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 282 \sdr_dq_7__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 128 \sdr_dq_7__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 129 \sdr_dq_7__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 127 \sdr_dq_7__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 283 \sdr_dq_7__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 284 \sdr_dq_7__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 309 \sdr_dq_8__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 155 \sdr_dq_8__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 156 \sdr_dq_8__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 154 \sdr_dq_8__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 310 \sdr_dq_8__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 311 \sdr_dq_8__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 312 \sdr_dq_9__core__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 158 \sdr_dq_9__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 159 \sdr_dq_9__core__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 157 \sdr_dq_9__pad__i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 313 \sdr_dq_9__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 314 \sdr_dq_9__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 144 \sdr_ras_n__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 299 \sdr_ras_n__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire input 146 \sdr_we_n__core__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" + wire output 301 \sdr_we_n__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" + wire output 351 \sram4k_0__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" + wire width 9 input 346 \sram4k_0__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" + wire input 344 \sram4k_0__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" + wire width 64 output 347 \sram4k_0__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" + wire width 64 input 348 \sram4k_0__dat_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" + wire width 8 input 350 \sram4k_0__sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" + wire input 345 \sram4k_0__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" + wire input 349 \sram4k_0__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" + wire output 359 \sram4k_1__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" + wire width 9 input 354 \sram4k_1__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" + wire input 352 \sram4k_1__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" + wire width 64 output 355 \sram4k_1__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" + wire width 64 input 356 \sram4k_1__dat_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" + wire width 8 input 358 \sram4k_1__sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" + wire input 353 \sram4k_1__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" + wire input 357 \sram4k_1__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" + wire output 367 \sram4k_2__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" + wire width 9 input 362 \sram4k_2__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" + wire input 360 \sram4k_2__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" + wire width 64 output 363 \sram4k_2__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" + wire width 64 input 364 \sram4k_2__dat_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" + wire width 8 input 366 \sram4k_2__sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" + wire input 361 \sram4k_2__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" + wire input 365 \sram4k_2__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" + wire output 375 \sram4k_3__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" + wire width 9 input 370 \sram4k_3__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" + wire input 368 \sram4k_3__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" + wire width 64 output 371 \sram4k_3__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" + wire width 64 input 372 \sram4k_3__dat_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" + wire width 8 input 374 \sram4k_3__sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" + wire input 369 \sram4k_3__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:24" + wire input 373 \sram4k_3__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:251" + wire \sv_read + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:251" + wire \sv_read$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1311" + wire \svp64_bigendian + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1309" + wire \svp64_is_svp64_mode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1308" + wire width 32 \svp64_raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1310" + wire width 24 \svp64_svp64_rm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:198" + wire \ti_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:426" + wire \update_svstate + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:83" + wire \xics_icp_core_irq_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:46" + wire width 8 \xics_icp_ics_i_pri + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:45" + wire width 4 \xics_icp_ics_i_src + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:46" + wire width 8 \xics_ics_icp_o_pri + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:45" + wire width 4 \xics_ics_icp_o_src + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:340" + cell $add $add$libresoc.v:200564$13726 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 65 + connect \A \dec2_cur_pc + connect \B \$144 + connect \Y $add$libresoc.v:200564$13726_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:360" + cell $add $add$libresoc.v:200568$13730 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 65 + connect \A \dec2_cur_pc + connect \B 3'100 + connect \Y $add$libresoc.v:200568$13730_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:360" + cell $add $add$libresoc.v:200575$13737 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 65 + connect \A \dec2_cur_pc + connect \B 3'100 + connect \Y $add$libresoc.v:200575$13737_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:520" + cell $add $add$libresoc.v:200585$13749 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 65 + connect \A \core_issue__data_o + connect \B 1'1 + connect \Y $add$libresoc.v:200585$13749_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:348" + cell $add $add$libresoc.v:200611$13775 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 65 + connect \A \dec2_cur_pc + connect \B 3'100 + connect \Y $add$libresoc.v:200611$13775_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:294" + cell $and $and$libresoc.v:200543$13705 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$99 + connect \B \$101 + connect \Y $and$libresoc.v:200543$13705_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:294" + cell $and $and$libresoc.v:200547$13709 + parameter \A_SIGNED 0 + parameter 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\A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$28 + connect \B \rst + connect \Y $or$libresoc.v:200589$13753_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + cell $pos $pos$libresoc.v:200581$13743 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A { 32'00000000000000000000000000000000 \new_svstate_maxvl \new_svstate_vl \new_svstate_srcstep \new_svstate_dststep \new_svstate_subvl \new_svstate_svstep } + connect \Y $pos$libresoc.v:200581$13743_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + cell $pos $pos$libresoc.v:200582$13745 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:200582$13744_Y + connect \Y $pos$libresoc.v:200582$13745_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + cell $pos $pos$libresoc.v:200583$13747 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$libresoc.v:200583$13746_Y + connect \Y $pos$libresoc.v:200583$13747_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + cell $reduce_or $reduce_or$libresoc.v:200580$13742 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \$179 + connect \Y $reduce_or$libresoc.v:200580$13742_Y + end + attribute \src "libresoc.v:200562.19-200562.42" + cell $shr $shr$libresoc.v:200562$13724 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 64 + connect \A \imem_f_instr_o + connect \B \$140 + connect \Y $shr$libresoc.v:200562$13724_Y + end + attribute \src "libresoc.v:200567.19-200567.42" + cell $shr $shr$libresoc.v:200567$13729 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 64 + connect \A \imem_f_instr_o + connect \B \$151 + connect \Y $shr$libresoc.v:200567$13729_Y + end + attribute \src "libresoc.v:200570.19-200570.42" + cell $shr $shr$libresoc.v:200570$13732 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 64 + connect \A \imem_f_instr_o + connect \B \$158 + connect \Y $shr$libresoc.v:200570$13732_Y + end + attribute \src "libresoc.v:200577.19-200577.42" + cell $shr $shr$libresoc.v:200577$13739 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 64 + connect \A \imem_f_instr_o + connect \B \$173 + connect \Y $shr$libresoc.v:200577$13739_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:504" + cell $sub $sub$libresoc.v:200584$13748 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 65 + connect \A \core_issue__data_o + connect \B 1'1 + connect \Y $sub$libresoc.v:200584$13748_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:201" + cell $sub $sub$libresoc.v:200587$13751 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \delay + connect \B 1'1 + connect \Y $sub$libresoc.v:200587$13751_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:339" + cell $mux $ternary$libresoc.v:200563$13725 + parameter \WIDTH 4 + connect \A 4'0100 + connect \B 4'1000 + connect \S \svp64_is_svp64_mode + connect \Y $ternary$libresoc.v:200563$13725_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:200841.8-200938.4" + cell \core \core + connect \bigendian_i \core_bigendian_i$10 + connect \cia__data_o \core_cia__data_o + connect \cia__ren \core_cia__ren + connect \core_core_cia \core_core_core_cia + connect \core_core_cr_rd \core_core_core_cr_rd + connect \core_core_cr_rd_ok \core_core_core_cr_rd_ok + connect \core_core_cr_wr \core_core_core_cr_wr + connect \core_core_exc_$signal \core_core_core_exc_$signal + connect \core_core_exc_$signal$3 \core_core_core_exc_$signal$3 + connect \core_core_exc_$signal$4 \core_core_core_exc_$signal$4 + connect \core_core_exc_$signal$5 \core_core_core_exc_$signal$5 + connect \core_core_exc_$signal$6 \core_core_core_exc_$signal$6 + connect \core_core_exc_$signal$7 \core_core_core_exc_$signal$7 + connect \core_core_exc_$signal$8 \core_core_core_exc_$signal$8 + connect \core_core_exc_$signal$9 \core_core_core_exc_$signal$9 + connect \core_core_fn_unit \core_core_core_fn_unit + connect \core_core_input_carry \core_core_core_input_carry + connect \core_core_insn \core_core_core_insn + connect \core_core_insn_type \core_core_core_insn_type + connect \core_core_is_32bit \core_core_core_is_32bit + connect \core_core_msr \core_core_core_msr + connect \core_core_oe \core_core_core_oe + connect \core_core_oe_ok \core_core_core_oe_ok + connect \core_core_rc \core_core_core_rc + connect \core_core_rc_ok \core_core_core_rc_ok + connect \core_core_trapaddr \core_core_core_trapaddr + connect \core_core_traptype \core_core_core_traptype + connect \core_cr_in1 \core_core_cr_in1 + connect \core_cr_in1_ok \core_core_cr_in1_ok + connect \core_cr_in2 \core_core_cr_in2 + connect \core_cr_in2$1 \core_core_cr_in2$1 + connect \core_cr_in2_ok \core_core_cr_in2_ok + connect \core_cr_in2_ok$2 \core_core_cr_in2_ok$2 + connect \core_cr_out \core_core_cr_out + connect \core_ea \core_core_ea + connect \core_fast1 \core_core_fast1 + connect \core_fast1_ok \core_core_fast1_ok + connect \core_fast2 \core_core_fast2 + connect \core_fast2_ok \core_core_fast2_ok + connect \core_fasto1 \core_core_fasto1 + connect \core_fasto2 \core_core_fasto2 + connect \core_pc \core_core_pc + connect \core_reg1 \core_core_reg1 + connect \core_reg1_ok \core_core_reg1_ok + connect \core_reg2 \core_core_reg2 + connect \core_reg2_ok \core_core_reg2_ok + connect \core_reg3 \core_core_reg3 + connect \core_reg3_ok \core_core_reg3_ok + connect \core_rego \core_core_rego + connect \core_spr1 \core_core_spr1 + connect \core_spr1_ok \core_core_spr1_ok + connect \core_spro \core_core_spro + connect \core_terminate_o \core_core_terminate_o + connect \core_xer_in \core_core_xer_in + connect \corebusy_o \core_corebusy_o + connect \coresync_clk \coresync_clk + connect \coresync_rst \core_coresync_rst + connect \cu_ad__go_i \core_cu_ad__go_i + connect \cu_ad__rel_o \core_cu_ad__rel_o + connect \cu_st__go_i \core_cu_st__go_i + connect \cu_st__rel_o \core_cu_st__rel_o + connect \data_i \core_data_i + connect \data_i$11 \core_data_i$12 + connect \dbus__ack \dbus__ack + connect \dbus__adr \dbus__adr + connect \dbus__cyc \dbus__cyc + connect \dbus__dat_r \dbus__dat_r + connect \dbus__dat_w \dbus__dat_w + connect \dbus__err \dbus__err + connect \dbus__sel \dbus__sel + connect \dbus__stb \dbus__stb + connect \dbus__we \dbus__we + connect \dmi__addr \core_dmi__addr + connect \dmi__data_o \core_dmi__data_o + connect \dmi__ren \core_dmi__ren + connect \full_rd2__data_o \core_full_rd2__data_o + connect \full_rd2__ren \core_full_rd2__ren + connect \full_rd__data_o \core_full_rd__data_o + connect \full_rd__ren \core_full_rd__ren + connect \issue__addr \core_issue__addr + connect \issue__addr$12 \core_issue__addr$13 + connect \issue__data_i \core_issue__data_i + connect \issue__data_o \core_issue__data_o + connect \issue__ren \core_issue__ren + connect \issue__wen \core_issue__wen + connect \issue_i \core_issue_i + connect \ivalid_i \core_ivalid_i + connect \msr__data_o \core_msr__data_o + connect \msr__ren \core_msr__ren + connect \raw_insn_i \core_raw_insn_i + connect \state_nia_wen \core_state_nia_wen + connect \sv__data_o \core_sv__data_o + connect \sv__ren \core_sv__ren + connect \wb_dcache_en \core_wb_dcache_en + connect \wen \core_wen + connect \wen$10 \core_wen$11 + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:200939.7-200964.4" + cell \dbg \dbg + connect \clk \clk + connect \core_dbg_msr \dbg_core_dbg_msr + connect \core_dbg_pc \dbg_core_dbg_pc + connect \core_rst_o \dbg_core_rst_o + connect \core_stop_o \dbg_core_stop_o + connect \core_stopped_i \dbg_core_stopped_i + connect \d_cr_ack \dbg_d_cr_ack + connect \d_cr_data \dbg_d_cr_data + connect \d_cr_req \dbg_d_cr_req + connect \d_gpr_ack \dbg_d_gpr_ack + connect \d_gpr_addr \dbg_d_gpr_addr + connect \d_gpr_data \dbg_d_gpr_data + connect \d_gpr_req \dbg_d_gpr_req + connect \d_xer_ack \dbg_d_xer_ack + connect \d_xer_data \dbg_d_xer_data + connect \d_xer_req \dbg_d_xer_req + connect \dmi_ack_o \dbg_dmi_ack_o + connect \dmi_addr_i \dbg_dmi_addr_i + connect \dmi_din \dbg_dmi_din + connect \dmi_dout \dbg_dmi_dout + connect \dmi_req_i \dbg_dmi_req_i + connect \dmi_we_i \dbg_dmi_we_i + connect \rst \rst + connect \terminate_i \dbg_terminate_i + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:200965.8-201033.4" + cell \dec2 \dec2 + connect \asmcode \dec2_asmcode + connect \bigendian \dec2_bigendian + connect \cia \dec2_cia + connect \cr_in1 \dec2_cr_in1 + connect \cr_in1_ok \dec2_cr_in1_ok + connect \cr_in2 \dec2_cr_in2 + connect \cr_in2$1 \dec2_cr_in2$14 + connect \cr_in2_ok \dec2_cr_in2_ok + connect \cr_in2_ok$2 \dec2_cr_in2_ok$15 + connect \cr_out \dec2_cr_out + connect \cr_out_ok \dec2_cr_out_ok + connect \cr_rd \dec2_cr_rd + connect \cr_rd_ok \dec2_cr_rd_ok + connect \cr_wr \dec2_cr_wr + connect \cr_wr_ok \dec2_cr_wr_ok + connect \cur_cur_srcstep \dec2_cur_cur_srcstep + connect \cur_dec \dec2_cur_dec + connect \cur_eint \dec2_cur_eint + connect \cur_msr \dec2_cur_msr + connect \cur_pc \dec2_cur_pc + connect \dec_svp64__extra \dec2_dec_svp64__extra + connect \ea \dec2_ea + connect \ea_ok \dec2_ea_ok + connect \exc_$signal \dec2_exc_$signal + connect \exc_$signal$3 \dec2_exc_$signal$16 + connect \exc_$signal$4 \dec2_exc_$signal$17 + connect \exc_$signal$5 \dec2_exc_$signal$18 + connect \exc_$signal$6 \dec2_exc_$signal$19 + connect \exc_$signal$7 \dec2_exc_$signal$20 + connect \exc_$signal$8 \dec2_exc_$signal$21 + connect \exc_$signal$9 \dec2_exc_$signal$22 + connect \fast1 \dec2_fast1 + connect \fast1_ok \dec2_fast1_ok + connect \fast2 \dec2_fast2 + connect \fast2_ok \dec2_fast2_ok + connect \fasto1 \dec2_fasto1 + connect \fasto1_ok \dec2_fasto1_ok + connect \fasto2 \dec2_fasto2 + connect \fasto2_ok \dec2_fasto2_ok + connect \fn_unit \dec2_fn_unit + connect \input_carry \dec2_input_carry + connect \insn \dec2_insn + connect \insn_type \dec2_insn_type + connect \is_32bit \dec2_is_32bit + connect \lk \dec2_lk + connect \msr \dec2_msr + connect \oe \dec2_oe + connect \oe_ok \dec2_oe_ok + connect \raw_opcode_in \dec2_raw_opcode_in + connect \rc \dec2_rc + connect \rc_ok \dec2_rc_ok + connect \reg1 \dec2_reg1 + connect \reg1_ok \dec2_reg1_ok + connect \reg2 \dec2_reg2 + connect \reg2_ok \dec2_reg2_ok + connect \reg3 \dec2_reg3 + connect \reg3_ok \dec2_reg3_ok + connect \rego \dec2_rego + connect \rego_ok \dec2_rego_ok + connect \spr1 \dec2_spr1 + connect \spr1_ok \dec2_spr1_ok + connect \spro \dec2_spro + connect \spro_ok \dec2_spro_ok + connect \trapaddr \dec2_trapaddr + connect \traptype \dec2_traptype + connect \xer_in \dec2_xer_in + connect \xer_out \dec2_xer_out + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:201034.8-201050.4" + cell \imem \imem + connect \a_pc_i \imem_a_pc_i + connect \a_valid_i \imem_a_valid_i + connect \clk \clk + connect \f_busy_o \imem_f_busy_o + connect \f_instr_o \imem_f_instr_o + connect \f_valid_i \imem_f_valid_i + connect \ibus__ack \ibus__ack + connect \ibus__adr \ibus__adr + connect \ibus__cyc \ibus__cyc + connect \ibus__dat_r \ibus__dat_r + connect \ibus__err \ibus__err + connect \ibus__sel \ibus__sel + connect \ibus__stb \ibus__stb + connect \rst \rst + connect \wb_icache_en \imem_wb_icache_en + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:201051.8-201382.4" + cell \jtag \jtag + connect \TAP_bus__tck \TAP_bus__tck + connect \TAP_bus__tdi \TAP_bus__tdi + connect \TAP_bus__tdo \TAP_bus__tdo + connect \TAP_bus__tms \TAP_bus__tms + connect \clk \clk + connect \dmi0__ack_o \jtag_dmi0__ack_o + connect \dmi0__addr_i \jtag_dmi0__addr_i + connect \dmi0__din \jtag_dmi0__din + connect \dmi0__dout \jtag_dmi0__dout + connect \dmi0__req_i \jtag_dmi0__req_i + connect \dmi0__we_i \jtag_dmi0__we_i + connect \eint_0__core__i \eint_0__core__i + connect \eint_0__pad__i \eint_0__pad__i + connect \eint_1__core__i \eint_1__core__i + connect \eint_1__pad__i \eint_1__pad__i + connect \eint_2__core__i \eint_2__core__i + connect \eint_2__pad__i \eint_2__pad__i + connect \gpio_e10__core__i \gpio_e10__core__i + connect \gpio_e10__core__o \gpio_e10__core__o + connect \gpio_e10__core__oe \gpio_e10__core__oe + connect \gpio_e10__pad__i \gpio_e10__pad__i + connect \gpio_e10__pad__o \gpio_e10__pad__o + connect \gpio_e10__pad__oe \gpio_e10__pad__oe + connect \gpio_e11__core__i \gpio_e11__core__i + connect \gpio_e11__core__o \gpio_e11__core__o + connect \gpio_e11__core__oe \gpio_e11__core__oe + connect \gpio_e11__pad__i \gpio_e11__pad__i + connect \gpio_e11__pad__o \gpio_e11__pad__o + connect \gpio_e11__pad__oe \gpio_e11__pad__oe + connect \gpio_e12__core__i \gpio_e12__core__i + connect \gpio_e12__core__o \gpio_e12__core__o + connect \gpio_e12__core__oe \gpio_e12__core__oe + connect \gpio_e12__pad__i \gpio_e12__pad__i + connect \gpio_e12__pad__o \gpio_e12__pad__o + connect \gpio_e12__pad__oe \gpio_e12__pad__oe + connect \gpio_e13__core__i \gpio_e13__core__i + connect \gpio_e13__core__o \gpio_e13__core__o + connect \gpio_e13__core__oe \gpio_e13__core__oe + connect \gpio_e13__pad__i \gpio_e13__pad__i + connect \gpio_e13__pad__o \gpio_e13__pad__o + connect \gpio_e13__pad__oe \gpio_e13__pad__oe + connect \gpio_e14__core__i \gpio_e14__core__i + connect \gpio_e14__core__o \gpio_e14__core__o + connect \gpio_e14__core__oe \gpio_e14__core__oe + connect \gpio_e14__pad__i \gpio_e14__pad__i + connect \gpio_e14__pad__o \gpio_e14__pad__o + connect \gpio_e14__pad__oe \gpio_e14__pad__oe + connect \gpio_e15__core__i \gpio_e15__core__i + connect \gpio_e15__core__o \gpio_e15__core__o + connect \gpio_e15__core__oe \gpio_e15__core__oe + connect \gpio_e15__pad__i \gpio_e15__pad__i + connect \gpio_e15__pad__o \gpio_e15__pad__o + connect \gpio_e15__pad__oe \gpio_e15__pad__oe + connect \gpio_e8__core__i \gpio_e8__core__i + connect \gpio_e8__core__o \gpio_e8__core__o + connect \gpio_e8__core__oe \gpio_e8__core__oe + connect \gpio_e8__pad__i \gpio_e8__pad__i + connect \gpio_e8__pad__o \gpio_e8__pad__o + connect \gpio_e8__pad__oe \gpio_e8__pad__oe + connect \gpio_e9__core__i \gpio_e9__core__i + connect \gpio_e9__core__o \gpio_e9__core__o + connect \gpio_e9__core__oe \gpio_e9__core__oe + connect \gpio_e9__pad__i \gpio_e9__pad__i + connect \gpio_e9__pad__o \gpio_e9__pad__o + connect \gpio_e9__pad__oe \gpio_e9__pad__oe + connect \gpio_s0__core__i \gpio_s0__core__i + connect \gpio_s0__core__o \gpio_s0__core__o + connect \gpio_s0__core__oe \gpio_s0__core__oe + connect \gpio_s0__pad__i \gpio_s0__pad__i + connect \gpio_s0__pad__o \gpio_s0__pad__o + connect \gpio_s0__pad__oe \gpio_s0__pad__oe + connect \gpio_s1__core__i \gpio_s1__core__i + connect \gpio_s1__core__o \gpio_s1__core__o + connect \gpio_s1__core__oe \gpio_s1__core__oe + connect \gpio_s1__pad__i \gpio_s1__pad__i + connect \gpio_s1__pad__o \gpio_s1__pad__o + connect \gpio_s1__pad__oe \gpio_s1__pad__oe + connect \gpio_s2__core__i \gpio_s2__core__i + connect \gpio_s2__core__o \gpio_s2__core__o + connect \gpio_s2__core__oe \gpio_s2__core__oe + connect \gpio_s2__pad__i \gpio_s2__pad__i + connect \gpio_s2__pad__o \gpio_s2__pad__o + connect \gpio_s2__pad__oe \gpio_s2__pad__oe + connect \gpio_s3__core__i \gpio_s3__core__i + connect \gpio_s3__core__o \gpio_s3__core__o + connect \gpio_s3__core__oe \gpio_s3__core__oe + connect \gpio_s3__pad__i \gpio_s3__pad__i + connect \gpio_s3__pad__o \gpio_s3__pad__o + connect \gpio_s3__pad__oe \gpio_s3__pad__oe + connect \gpio_s4__core__i \gpio_s4__core__i + connect \gpio_s4__core__o \gpio_s4__core__o + connect \gpio_s4__core__oe \gpio_s4__core__oe + connect \gpio_s4__pad__i \gpio_s4__pad__i + connect \gpio_s4__pad__o \gpio_s4__pad__o + connect \gpio_s4__pad__oe \gpio_s4__pad__oe + connect \gpio_s5__core__i \gpio_s5__core__i + connect \gpio_s5__core__o \gpio_s5__core__o + connect \gpio_s5__core__oe \gpio_s5__core__oe + connect \gpio_s5__pad__i \gpio_s5__pad__i + connect \gpio_s5__pad__o \gpio_s5__pad__o + connect \gpio_s5__pad__oe \gpio_s5__pad__oe + connect \gpio_s6__core__i \gpio_s6__core__i + connect \gpio_s6__core__o \gpio_s6__core__o + connect \gpio_s6__core__oe \gpio_s6__core__oe + connect \gpio_s6__pad__i \gpio_s6__pad__i + connect \gpio_s6__pad__o \gpio_s6__pad__o + connect \gpio_s6__pad__oe \gpio_s6__pad__oe + connect \gpio_s7__core__i \gpio_s7__core__i + connect \gpio_s7__core__o \gpio_s7__core__o + connect \gpio_s7__core__oe \gpio_s7__core__oe + connect \gpio_s7__pad__i \gpio_s7__pad__i + connect \gpio_s7__pad__o \gpio_s7__pad__o + connect \gpio_s7__pad__oe \gpio_s7__pad__oe + connect \jtag_wb__ack \jtag_wb__ack + connect \jtag_wb__adr \jtag_wb__adr + connect \jtag_wb__cyc \jtag_wb__cyc + connect \jtag_wb__dat_r \jtag_wb__dat_r + connect \jtag_wb__dat_w \jtag_wb__dat_w + connect \jtag_wb__sel \jtag_wb__sel + connect \jtag_wb__stb \jtag_wb__stb + connect \jtag_wb__we \jtag_wb__we + connect \mspi0_clk__core__o \mspi0_clk__core__o + connect \mspi0_clk__pad__o \mspi0_clk__pad__o + connect \mspi0_cs_n__core__o \mspi0_cs_n__core__o + connect \mspi0_cs_n__pad__o \mspi0_cs_n__pad__o + connect \mspi0_miso__core__i \mspi0_miso__core__i + connect \mspi0_miso__pad__i \mspi0_miso__pad__i + connect \mspi0_mosi__core__o \mspi0_mosi__core__o + connect \mspi0_mosi__pad__o \mspi0_mosi__pad__o + connect \mspi1_clk__core__o \mspi1_clk__core__o + connect \mspi1_clk__pad__o \mspi1_clk__pad__o + connect \mspi1_cs_n__core__o \mspi1_cs_n__core__o + connect \mspi1_cs_n__pad__o \mspi1_cs_n__pad__o + connect \mspi1_miso__core__i \mspi1_miso__core__i + connect \mspi1_miso__pad__i \mspi1_miso__pad__i + connect \mspi1_mosi__core__o \mspi1_mosi__core__o + connect \mspi1_mosi__pad__o \mspi1_mosi__pad__o + connect \mtwi_scl__core__o \mtwi_scl__core__o + connect \mtwi_scl__pad__o \mtwi_scl__pad__o + connect \mtwi_sda__core__i \mtwi_sda__core__i + connect \mtwi_sda__core__o \mtwi_sda__core__o + connect \mtwi_sda__core__oe \mtwi_sda__core__oe + connect \mtwi_sda__pad__i \mtwi_sda__pad__i + connect \mtwi_sda__pad__o \mtwi_sda__pad__o + connect \mtwi_sda__pad__oe \mtwi_sda__pad__oe + connect \pwm_0__core__o \pwm_0__core__o + connect \pwm_0__pad__o \pwm_0__pad__o + connect \pwm_1__core__o \pwm_1__core__o + connect \pwm_1__pad__o \pwm_1__pad__o + connect \rst \rst + connect \sd0_clk__core__o \sd0_clk__core__o + connect \sd0_clk__pad__o \sd0_clk__pad__o + connect \sd0_cmd__core__i \sd0_cmd__core__i + connect \sd0_cmd__core__o \sd0_cmd__core__o + connect \sd0_cmd__core__oe \sd0_cmd__core__oe + connect \sd0_cmd__pad__i \sd0_cmd__pad__i + connect \sd0_cmd__pad__o \sd0_cmd__pad__o + connect \sd0_cmd__pad__oe \sd0_cmd__pad__oe + connect \sd0_data0__core__i \sd0_data0__core__i + connect \sd0_data0__core__o \sd0_data0__core__o + connect \sd0_data0__core__oe \sd0_data0__core__oe + connect \sd0_data0__pad__i \sd0_data0__pad__i + connect \sd0_data0__pad__o \sd0_data0__pad__o + connect \sd0_data0__pad__oe \sd0_data0__pad__oe + connect \sd0_data1__core__i \sd0_data1__core__i + connect \sd0_data1__core__o \sd0_data1__core__o + connect \sd0_data1__core__oe \sd0_data1__core__oe + connect \sd0_data1__pad__i \sd0_data1__pad__i + connect \sd0_data1__pad__o \sd0_data1__pad__o + connect \sd0_data1__pad__oe \sd0_data1__pad__oe + connect \sd0_data2__core__i \sd0_data2__core__i + connect \sd0_data2__core__o \sd0_data2__core__o + connect \sd0_data2__core__oe \sd0_data2__core__oe + connect \sd0_data2__pad__i \sd0_data2__pad__i + connect \sd0_data2__pad__o \sd0_data2__pad__o + connect \sd0_data2__pad__oe \sd0_data2__pad__oe + connect \sd0_data3__core__i \sd0_data3__core__i + connect \sd0_data3__core__o \sd0_data3__core__o + connect \sd0_data3__core__oe \sd0_data3__core__oe + connect \sd0_data3__pad__i \sd0_data3__pad__i + connect \sd0_data3__pad__o \sd0_data3__pad__o + connect \sd0_data3__pad__oe \sd0_data3__pad__oe + connect \sdr_a_0__core__o \sdr_a_0__core__o + connect \sdr_a_0__pad__o \sdr_a_0__pad__o + connect \sdr_a_10__core__o \sdr_a_10__core__o + connect \sdr_a_10__pad__o \sdr_a_10__pad__o + connect \sdr_a_11__core__o \sdr_a_11__core__o + connect \sdr_a_11__pad__o \sdr_a_11__pad__o + connect \sdr_a_12__core__o \sdr_a_12__core__o + connect \sdr_a_12__pad__o \sdr_a_12__pad__o + connect \sdr_a_1__core__o \sdr_a_1__core__o + connect \sdr_a_1__pad__o \sdr_a_1__pad__o + connect \sdr_a_2__core__o \sdr_a_2__core__o + connect \sdr_a_2__pad__o \sdr_a_2__pad__o + connect \sdr_a_3__core__o \sdr_a_3__core__o + connect \sdr_a_3__pad__o \sdr_a_3__pad__o + connect \sdr_a_4__core__o \sdr_a_4__core__o + connect \sdr_a_4__pad__o \sdr_a_4__pad__o + connect \sdr_a_5__core__o \sdr_a_5__core__o + connect \sdr_a_5__pad__o \sdr_a_5__pad__o + connect \sdr_a_6__core__o \sdr_a_6__core__o + connect \sdr_a_6__pad__o \sdr_a_6__pad__o + connect \sdr_a_7__core__o \sdr_a_7__core__o + connect \sdr_a_7__pad__o \sdr_a_7__pad__o + connect \sdr_a_8__core__o \sdr_a_8__core__o + connect \sdr_a_8__pad__o \sdr_a_8__pad__o + connect \sdr_a_9__core__o \sdr_a_9__core__o + connect \sdr_a_9__pad__o \sdr_a_9__pad__o + connect \sdr_ba_0__core__o \sdr_ba_0__core__o + connect \sdr_ba_0__pad__o \sdr_ba_0__pad__o + connect \sdr_ba_1__core__o \sdr_ba_1__core__o + connect \sdr_ba_1__pad__o \sdr_ba_1__pad__o + connect \sdr_cas_n__core__o \sdr_cas_n__core__o + connect \sdr_cas_n__pad__o \sdr_cas_n__pad__o + connect \sdr_cke__core__o \sdr_cke__core__o + connect \sdr_cke__pad__o \sdr_cke__pad__o + connect \sdr_clock__core__o \sdr_clock__core__o + connect \sdr_clock__pad__o \sdr_clock__pad__o + connect \sdr_cs_n__core__o \sdr_cs_n__core__o + connect \sdr_cs_n__pad__o \sdr_cs_n__pad__o + connect \sdr_dm_0__core__o \sdr_dm_0__core__o + connect \sdr_dm_0__pad__o \sdr_dm_0__pad__o + connect \sdr_dm_1__core__i \sdr_dm_1__core__i + connect \sdr_dm_1__core__o \sdr_dm_1__core__o + connect \sdr_dm_1__core__oe \sdr_dm_1__core__oe + connect \sdr_dm_1__pad__i \sdr_dm_1__pad__i + connect \sdr_dm_1__pad__o \sdr_dm_1__pad__o + connect \sdr_dm_1__pad__oe \sdr_dm_1__pad__oe + connect \sdr_dq_0__core__i \sdr_dq_0__core__i + connect \sdr_dq_0__core__o \sdr_dq_0__core__o + connect \sdr_dq_0__core__oe \sdr_dq_0__core__oe + connect \sdr_dq_0__pad__i \sdr_dq_0__pad__i + connect \sdr_dq_0__pad__o \sdr_dq_0__pad__o + connect \sdr_dq_0__pad__oe \sdr_dq_0__pad__oe + connect \sdr_dq_10__core__i \sdr_dq_10__core__i + connect \sdr_dq_10__core__o \sdr_dq_10__core__o + connect \sdr_dq_10__core__oe \sdr_dq_10__core__oe + connect \sdr_dq_10__pad__i \sdr_dq_10__pad__i + connect \sdr_dq_10__pad__o \sdr_dq_10__pad__o + connect \sdr_dq_10__pad__oe \sdr_dq_10__pad__oe + connect \sdr_dq_11__core__i \sdr_dq_11__core__i + connect \sdr_dq_11__core__o \sdr_dq_11__core__o + connect \sdr_dq_11__core__oe \sdr_dq_11__core__oe + connect \sdr_dq_11__pad__i \sdr_dq_11__pad__i + connect \sdr_dq_11__pad__o \sdr_dq_11__pad__o + connect \sdr_dq_11__pad__oe \sdr_dq_11__pad__oe + connect \sdr_dq_12__core__i \sdr_dq_12__core__i + connect \sdr_dq_12__core__o \sdr_dq_12__core__o + connect \sdr_dq_12__core__oe \sdr_dq_12__core__oe + connect \sdr_dq_12__pad__i \sdr_dq_12__pad__i + connect \sdr_dq_12__pad__o \sdr_dq_12__pad__o + connect \sdr_dq_12__pad__oe \sdr_dq_12__pad__oe + connect \sdr_dq_13__core__i \sdr_dq_13__core__i + connect \sdr_dq_13__core__o \sdr_dq_13__core__o + connect \sdr_dq_13__core__oe \sdr_dq_13__core__oe + connect \sdr_dq_13__pad__i \sdr_dq_13__pad__i + connect \sdr_dq_13__pad__o \sdr_dq_13__pad__o + connect \sdr_dq_13__pad__oe \sdr_dq_13__pad__oe + connect \sdr_dq_14__core__i \sdr_dq_14__core__i + connect \sdr_dq_14__core__o \sdr_dq_14__core__o + connect \sdr_dq_14__core__oe \sdr_dq_14__core__oe + connect \sdr_dq_14__pad__i \sdr_dq_14__pad__i + connect \sdr_dq_14__pad__o \sdr_dq_14__pad__o + connect \sdr_dq_14__pad__oe \sdr_dq_14__pad__oe + connect \sdr_dq_15__core__i \sdr_dq_15__core__i + connect \sdr_dq_15__core__o \sdr_dq_15__core__o + connect \sdr_dq_15__core__oe \sdr_dq_15__core__oe + connect \sdr_dq_15__pad__i \sdr_dq_15__pad__i + connect \sdr_dq_15__pad__o \sdr_dq_15__pad__o + connect \sdr_dq_15__pad__oe \sdr_dq_15__pad__oe + connect \sdr_dq_1__core__i \sdr_dq_1__core__i + connect \sdr_dq_1__core__o \sdr_dq_1__core__o + connect \sdr_dq_1__core__oe \sdr_dq_1__core__oe + connect \sdr_dq_1__pad__i \sdr_dq_1__pad__i + connect \sdr_dq_1__pad__o \sdr_dq_1__pad__o + connect \sdr_dq_1__pad__oe \sdr_dq_1__pad__oe + connect \sdr_dq_2__core__i \sdr_dq_2__core__i + connect \sdr_dq_2__core__o \sdr_dq_2__core__o + connect \sdr_dq_2__core__oe \sdr_dq_2__core__oe + connect \sdr_dq_2__pad__i \sdr_dq_2__pad__i + connect \sdr_dq_2__pad__o \sdr_dq_2__pad__o + connect \sdr_dq_2__pad__oe \sdr_dq_2__pad__oe + connect \sdr_dq_3__core__i \sdr_dq_3__core__i + connect \sdr_dq_3__core__o \sdr_dq_3__core__o + connect \sdr_dq_3__core__oe \sdr_dq_3__core__oe + connect \sdr_dq_3__pad__i \sdr_dq_3__pad__i + connect \sdr_dq_3__pad__o \sdr_dq_3__pad__o + connect \sdr_dq_3__pad__oe \sdr_dq_3__pad__oe + connect \sdr_dq_4__core__i \sdr_dq_4__core__i + connect \sdr_dq_4__core__o \sdr_dq_4__core__o + connect \sdr_dq_4__core__oe \sdr_dq_4__core__oe + connect \sdr_dq_4__pad__i \sdr_dq_4__pad__i + connect \sdr_dq_4__pad__o \sdr_dq_4__pad__o + connect \sdr_dq_4__pad__oe \sdr_dq_4__pad__oe + connect \sdr_dq_5__core__i \sdr_dq_5__core__i + connect \sdr_dq_5__core__o \sdr_dq_5__core__o + connect \sdr_dq_5__core__oe \sdr_dq_5__core__oe + connect \sdr_dq_5__pad__i \sdr_dq_5__pad__i + connect \sdr_dq_5__pad__o \sdr_dq_5__pad__o + connect \sdr_dq_5__pad__oe \sdr_dq_5__pad__oe + connect \sdr_dq_6__core__i \sdr_dq_6__core__i + connect \sdr_dq_6__core__o \sdr_dq_6__core__o + connect \sdr_dq_6__core__oe \sdr_dq_6__core__oe + connect \sdr_dq_6__pad__i \sdr_dq_6__pad__i + connect \sdr_dq_6__pad__o \sdr_dq_6__pad__o + connect \sdr_dq_6__pad__oe \sdr_dq_6__pad__oe + connect \sdr_dq_7__core__i \sdr_dq_7__core__i + connect \sdr_dq_7__core__o \sdr_dq_7__core__o + connect \sdr_dq_7__core__oe \sdr_dq_7__core__oe + connect \sdr_dq_7__pad__i \sdr_dq_7__pad__i + connect \sdr_dq_7__pad__o \sdr_dq_7__pad__o + connect \sdr_dq_7__pad__oe \sdr_dq_7__pad__oe + connect \sdr_dq_8__core__i \sdr_dq_8__core__i + connect \sdr_dq_8__core__o \sdr_dq_8__core__o + connect \sdr_dq_8__core__oe \sdr_dq_8__core__oe + connect \sdr_dq_8__pad__i \sdr_dq_8__pad__i + connect \sdr_dq_8__pad__o \sdr_dq_8__pad__o + connect \sdr_dq_8__pad__oe \sdr_dq_8__pad__oe + connect \sdr_dq_9__core__i \sdr_dq_9__core__i + connect \sdr_dq_9__core__o \sdr_dq_9__core__o + connect \sdr_dq_9__core__oe \sdr_dq_9__core__oe + connect \sdr_dq_9__pad__i \sdr_dq_9__pad__i + connect \sdr_dq_9__pad__o \sdr_dq_9__pad__o + connect \sdr_dq_9__pad__oe \sdr_dq_9__pad__oe + connect \sdr_ras_n__core__o \sdr_ras_n__core__o + connect \sdr_ras_n__pad__o \sdr_ras_n__pad__o + connect \sdr_we_n__core__o \sdr_we_n__core__o + connect \sdr_we_n__pad__o \sdr_we_n__pad__o + connect \wb_dcache_en \core_wb_dcache_en + connect \wb_icache_en \imem_wb_icache_en + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:201383.12-201394.4" + cell \sram4k_0 \sram4k_0 + connect \clk \clk + connect \rst \rst + connect \sram4k_0__ack \sram4k_0__ack + connect \sram4k_0__adr \sram4k_0__adr + connect \sram4k_0__cyc \sram4k_0__cyc + connect \sram4k_0__dat_r \sram4k_0__dat_r + connect \sram4k_0__dat_w \sram4k_0__dat_w + connect \sram4k_0__sel \sram4k_0__sel + connect \sram4k_0__stb \sram4k_0__stb + connect \sram4k_0__we \sram4k_0__we + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:201395.12-201406.4" + cell \sram4k_1 \sram4k_1 + connect \clk \clk + connect \rst \rst + connect \sram4k_1__ack \sram4k_1__ack + connect \sram4k_1__adr \sram4k_1__adr + connect \sram4k_1__cyc \sram4k_1__cyc + connect \sram4k_1__dat_r \sram4k_1__dat_r + connect \sram4k_1__dat_w \sram4k_1__dat_w + connect \sram4k_1__sel \sram4k_1__sel + connect \sram4k_1__stb \sram4k_1__stb + connect \sram4k_1__we \sram4k_1__we + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:201407.12-201418.4" + cell \sram4k_2 \sram4k_2 + connect \clk \clk + connect \rst \rst + connect \sram4k_2__ack \sram4k_2__ack + connect \sram4k_2__adr \sram4k_2__adr + connect \sram4k_2__cyc \sram4k_2__cyc + connect \sram4k_2__dat_r \sram4k_2__dat_r + connect \sram4k_2__dat_w \sram4k_2__dat_w + connect \sram4k_2__sel \sram4k_2__sel + connect \sram4k_2__stb \sram4k_2__stb + connect \sram4k_2__we \sram4k_2__we + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:201419.12-201430.4" + cell \sram4k_3 \sram4k_3 + connect \clk \clk + connect \rst \rst + connect \sram4k_3__ack \sram4k_3__ack + connect \sram4k_3__adr \sram4k_3__adr + connect \sram4k_3__cyc \sram4k_3__cyc + connect \sram4k_3__dat_r \sram4k_3__dat_r + connect \sram4k_3__dat_w \sram4k_3__dat_w + connect \sram4k_3__sel \sram4k_3__sel + connect \sram4k_3__stb \sram4k_3__stb + connect \sram4k_3__we \sram4k_3__we + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:201431.9-201436.4" + cell \svp64 \svp64 + connect \bigendian \svp64_bigendian + connect \is_svp64_mode \svp64_is_svp64_mode + connect \raw_opcode_in \svp64_raw_opcode_in + connect \svp64_rm \svp64_svp64_rm + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:201437.12-201451.4" + cell \xics_icp \xics_icp + connect \clk \clk + connect \core_irq_o \xics_icp_core_irq_o + connect \icp_wb__ack \icp_wb__ack + connect \icp_wb__adr \icp_wb__adr + connect \icp_wb__cyc \icp_wb__cyc + connect \icp_wb__dat_r \icp_wb__dat_r + connect \icp_wb__dat_w \icp_wb__dat_w + connect \icp_wb__sel \icp_wb__sel + connect \icp_wb__stb \icp_wb__stb + connect \icp_wb__we \icp_wb__we + connect \ics_i_pri \xics_icp_ics_i_pri + connect \ics_i_src \xics_icp_ics_i_src + connect \rst \rst + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:201452.12-201465.4" + cell \xics_ics \xics_ics + connect \clk \clk + connect \icp_o_pri \xics_ics_icp_o_pri + connect \icp_o_src \xics_ics_icp_o_src + connect \ics_wb__ack \ics_wb__ack + connect \ics_wb__adr \ics_wb__adr + connect \ics_wb__cyc \ics_wb__cyc + connect \ics_wb__dat_r \ics_wb__dat_r + connect \ics_wb__dat_w \ics_wb__dat_w + connect \ics_wb__stb \ics_wb__stb + connect \ics_wb__we \ics_wb__we + connect \int_level_i \int_level_i + connect \rst \rst + end + attribute \src "libresoc.v:198206.7-198206.20" + process $proc$libresoc.v:198206$14430 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:198398.13-198398.33" + process $proc$libresoc.v:198398$14431 + assign { } { } + assign $1\core_asmcode[7:0] 8'00000000 + sync always + sync init + update \core_asmcode $1\core_asmcode[7:0] + end + attribute \src "libresoc.v:198404.7-198404.35" + process $proc$libresoc.v:198404$14432 + assign { } { } + assign $0\core_bigendian_i$10[0:0]$14433 1'0 + sync always + sync init + update \core_bigendian_i$10 $0\core_bigendian_i$10[0:0]$14433 + end + attribute \src "libresoc.v:198412.14-198412.55" + process $proc$libresoc.v:198412$14434 + assign { } { } + assign $1\core_core_core_cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \core_core_core_cia $1\core_core_core_cia[63:0] + end + attribute \src "libresoc.v:198416.13-198416.41" + process $proc$libresoc.v:198416$14435 + assign { } { } + assign $1\core_core_core_cr_rd[7:0] 8'00000000 + sync always + sync init + update \core_core_core_cr_rd $1\core_core_core_cr_rd[7:0] + end + attribute \src "libresoc.v:198420.7-198420.37" + process $proc$libresoc.v:198420$14436 + assign { } { } + assign $1\core_core_core_cr_rd_ok[0:0] 1'0 + sync always + sync init + update \core_core_core_cr_rd_ok $1\core_core_core_cr_rd_ok[0:0] + end + attribute \src "libresoc.v:198424.13-198424.41" + process $proc$libresoc.v:198424$14437 + assign { } { } + assign $1\core_core_core_cr_wr[7:0] 8'00000000 + sync always + sync init + update \core_core_core_cr_wr $1\core_core_core_cr_wr[7:0] + end + attribute \src "libresoc.v:198428.7-198428.42" + process $proc$libresoc.v:198428$14438 + assign { } { } + assign $0\core_core_core_exc_$signal[0:0]$14439 1'0 + sync always + sync init + update \core_core_core_exc_$signal $0\core_core_core_exc_$signal[0:0]$14439 + end + attribute \src "libresoc.v:198430.7-198430.44" + process $proc$libresoc.v:198430$14440 + assign { } { } + assign $0\core_core_core_exc_$signal$3[0:0]$14441 1'0 + sync always + sync init + update \core_core_core_exc_$signal$3 $0\core_core_core_exc_$signal$3[0:0]$14441 + end + attribute \src "libresoc.v:198434.7-198434.44" + process $proc$libresoc.v:198434$14442 + assign { } { } + assign $0\core_core_core_exc_$signal$4[0:0]$14443 1'0 + sync always + sync init + update \core_core_core_exc_$signal$4 $0\core_core_core_exc_$signal$4[0:0]$14443 + end + attribute \src "libresoc.v:198438.7-198438.44" + process $proc$libresoc.v:198438$14444 + assign { } { } + assign $0\core_core_core_exc_$signal$5[0:0]$14445 1'0 + sync always + sync init + update \core_core_core_exc_$signal$5 $0\core_core_core_exc_$signal$5[0:0]$14445 + end + attribute \src "libresoc.v:198442.7-198442.44" + process $proc$libresoc.v:198442$14446 + assign { } { } + assign $0\core_core_core_exc_$signal$6[0:0]$14447 1'0 + sync always + sync init + update \core_core_core_exc_$signal$6 $0\core_core_core_exc_$signal$6[0:0]$14447 + end + attribute \src "libresoc.v:198446.7-198446.44" + process $proc$libresoc.v:198446$14448 + assign { } { } + assign $0\core_core_core_exc_$signal$7[0:0]$14449 1'0 + sync always + sync init + update \core_core_core_exc_$signal$7 $0\core_core_core_exc_$signal$7[0:0]$14449 + end + attribute \src "libresoc.v:198450.7-198450.44" + process $proc$libresoc.v:198450$14450 + assign { } { } + assign $0\core_core_core_exc_$signal$8[0:0]$14451 1'0 + sync always + sync init + update \core_core_core_exc_$signal$8 $0\core_core_core_exc_$signal$8[0:0]$14451 + end + attribute \src "libresoc.v:198454.7-198454.44" + process $proc$libresoc.v:198454$14452 + assign { } { } + assign $0\core_core_core_exc_$signal$9[0:0]$14453 1'0 + sync always + sync init + update \core_core_core_exc_$signal$9 $0\core_core_core_exc_$signal$9[0:0]$14453 + end + attribute \src "libresoc.v:198474.14-198474.47" + process $proc$libresoc.v:198474$14454 + assign { } { } + assign $1\core_core_core_fn_unit[12:0] 13'0000000000000 + sync always + sync init + update \core_core_core_fn_unit $1\core_core_core_fn_unit[12:0] + end + attribute \src "libresoc.v:198482.13-198482.46" + process $proc$libresoc.v:198482$14455 + assign { } { } + assign $1\core_core_core_input_carry[1:0] 2'00 + sync always + sync init + update \core_core_core_input_carry $1\core_core_core_input_carry[1:0] + end + attribute \src "libresoc.v:198486.14-198486.41" + process $proc$libresoc.v:198486$14456 + assign { } { } + assign $1\core_core_core_insn[31:0] 0 + sync always + sync init + update \core_core_core_insn $1\core_core_core_insn[31:0] + end + attribute \src "libresoc.v:198564.13-198564.45" + process $proc$libresoc.v:198564$14457 + assign { } { } + assign $1\core_core_core_insn_type[6:0] 7'0000000 + sync always + sync init + update \core_core_core_insn_type $1\core_core_core_insn_type[6:0] + end + attribute \src "libresoc.v:198568.7-198568.37" + process $proc$libresoc.v:198568$14458 + assign { } { } + assign $1\core_core_core_is_32bit[0:0] 1'0 + sync always + sync init + update \core_core_core_is_32bit $1\core_core_core_is_32bit[0:0] + end + attribute \src "libresoc.v:198572.14-198572.55" + process $proc$libresoc.v:198572$14459 + assign { } { } + assign $1\core_core_core_msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \core_core_core_msr $1\core_core_core_msr[63:0] + end + attribute \src "libresoc.v:198576.7-198576.31" + process $proc$libresoc.v:198576$14460 + assign { } { } + assign $1\core_core_core_oe[0:0] 1'0 + sync always + sync init + update \core_core_core_oe $1\core_core_core_oe[0:0] + end + attribute \src "libresoc.v:198580.7-198580.34" + process $proc$libresoc.v:198580$14461 + assign { } { } + assign $1\core_core_core_oe_ok[0:0] 1'0 + sync always + sync init + update \core_core_core_oe_ok $1\core_core_core_oe_ok[0:0] + end + attribute \src "libresoc.v:198584.7-198584.31" + process $proc$libresoc.v:198584$14462 + assign { } { } + assign $1\core_core_core_rc[0:0] 1'0 + sync always + sync init + update \core_core_core_rc $1\core_core_core_rc[0:0] + end + attribute \src "libresoc.v:198588.7-198588.34" + process $proc$libresoc.v:198588$14463 + assign { } { } + assign $1\core_core_core_rc_ok[0:0] 1'0 + sync always + sync init + update \core_core_core_rc_ok $1\core_core_core_rc_ok[0:0] + end + attribute \src "libresoc.v:198592.14-198592.48" + process $proc$libresoc.v:198592$14464 + assign { } { } + assign $1\core_core_core_trapaddr[12:0] 13'0000000000000 + sync always + sync init + update \core_core_core_trapaddr $1\core_core_core_trapaddr[12:0] + end + attribute \src "libresoc.v:198596.13-198596.44" + process $proc$libresoc.v:198596$14465 + assign { } { } + assign $1\core_core_core_traptype[7:0] 8'00000000 + sync always + sync init + update \core_core_core_traptype $1\core_core_core_traptype[7:0] + end + attribute \src "libresoc.v:198600.13-198600.37" + process $proc$libresoc.v:198600$14466 + assign { } { } + assign $1\core_core_cr_in1[6:0] 7'0000000 + sync always + sync init + update \core_core_cr_in1 $1\core_core_cr_in1[6:0] + end + attribute \src "libresoc.v:198604.7-198604.33" + process $proc$libresoc.v:198604$14467 + assign { } { } + assign $1\core_core_cr_in1_ok[0:0] 1'0 + sync always + sync init + update \core_core_cr_in1_ok $1\core_core_cr_in1_ok[0:0] + end + attribute \src "libresoc.v:198608.13-198608.37" + process $proc$libresoc.v:198608$14468 + assign { } { } + assign $1\core_core_cr_in2[6:0] 7'0000000 + sync always + sync init + update \core_core_cr_in2 $1\core_core_cr_in2[6:0] + end + attribute \src "libresoc.v:198610.13-198610.41" + process $proc$libresoc.v:198610$14469 + assign { } { } + assign $0\core_core_cr_in2$1[6:0]$14470 7'0000000 + sync always + sync init + update \core_core_cr_in2$1 $0\core_core_cr_in2$1[6:0]$14470 + end + attribute \src "libresoc.v:198616.7-198616.33" + process $proc$libresoc.v:198616$14471 + assign { } { } + assign $1\core_core_cr_in2_ok[0:0] 1'0 + sync always + sync init + update \core_core_cr_in2_ok $1\core_core_cr_in2_ok[0:0] + end + attribute \src "libresoc.v:198618.7-198618.37" + process $proc$libresoc.v:198618$14472 + assign { } { } + assign $0\core_core_cr_in2_ok$2[0:0]$14473 1'0 + sync always + sync init + update \core_core_cr_in2_ok$2 $0\core_core_cr_in2_ok$2[0:0]$14473 + end + attribute \src "libresoc.v:198624.13-198624.37" + process $proc$libresoc.v:198624$14474 + assign { } { } + assign $1\core_core_cr_out[6:0] 7'0000000 + sync always + sync init + update \core_core_cr_out $1\core_core_cr_out[6:0] + end + attribute \src "libresoc.v:198628.7-198628.32" + process $proc$libresoc.v:198628$14475 + assign { } { } + assign $1\core_core_cr_wr_ok[0:0] 1'0 + sync always + sync init + update \core_core_cr_wr_ok $1\core_core_cr_wr_ok[0:0] + end + attribute \src "libresoc.v:198632.13-198632.38" + process $proc$libresoc.v:198632$14476 + assign { } { } + assign $1\core_core_dststep[6:0] 7'0000000 + sync always + sync init + update \core_core_dststep $1\core_core_dststep[6:0] + end + attribute \src "libresoc.v:198636.13-198636.33" + process $proc$libresoc.v:198636$14477 + assign { } { } + assign $1\core_core_ea[6:0] 7'0000000 + sync always + sync init + update \core_core_ea $1\core_core_ea[6:0] + end + attribute \src "libresoc.v:198640.13-198640.35" + process $proc$libresoc.v:198640$14478 + assign { } { } + assign $1\core_core_fast1[2:0] 3'000 + sync always + sync init + update \core_core_fast1 $1\core_core_fast1[2:0] + end + attribute \src "libresoc.v:198644.7-198644.32" + process $proc$libresoc.v:198644$14479 + assign { } { } + assign $1\core_core_fast1_ok[0:0] 1'0 + sync always + sync init + update \core_core_fast1_ok $1\core_core_fast1_ok[0:0] + end + attribute \src "libresoc.v:198648.13-198648.35" + process $proc$libresoc.v:198648$14480 + assign { } { } + assign $1\core_core_fast2[2:0] 3'000 + sync always + sync init + update \core_core_fast2 $1\core_core_fast2[2:0] + end + attribute \src "libresoc.v:198652.7-198652.32" + process $proc$libresoc.v:198652$14481 + assign { } { } + assign $1\core_core_fast2_ok[0:0] 1'0 + sync always + sync init + update \core_core_fast2_ok $1\core_core_fast2_ok[0:0] + end + attribute \src "libresoc.v:198656.13-198656.36" + process $proc$libresoc.v:198656$14482 + assign { } { } + assign $1\core_core_fasto1[2:0] 3'000 + sync always + sync init + update \core_core_fasto1 $1\core_core_fasto1[2:0] + end + attribute \src "libresoc.v:198660.13-198660.36" + process $proc$libresoc.v:198660$14483 + assign { } { } + assign $1\core_core_fasto2[2:0] 3'000 + sync always + sync init + update \core_core_fasto2 $1\core_core_fasto2[2:0] + end + attribute \src "libresoc.v:198664.7-198664.26" + process $proc$libresoc.v:198664$14484 + assign { } { } + assign $1\core_core_lk[0:0] 1'0 + sync always + sync init + update \core_core_lk $1\core_core_lk[0:0] + end + attribute \src "libresoc.v:198668.13-198668.36" + process $proc$libresoc.v:198668$14485 + assign { } { } + assign $1\core_core_maxvl[6:0] 7'0000000 + sync always + sync init + update \core_core_maxvl $1\core_core_maxvl[6:0] + end + attribute \src "libresoc.v:198672.14-198672.49" + process $proc$libresoc.v:198672$14486 + assign { } { } + assign $1\core_core_pc[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \core_core_pc $1\core_core_pc[63:0] + end + attribute \src "libresoc.v:198676.13-198676.35" + process $proc$libresoc.v:198676$14487 + assign { } { } + assign $1\core_core_reg1[6:0] 7'0000000 + sync always + sync init + update \core_core_reg1 $1\core_core_reg1[6:0] + end + attribute \src "libresoc.v:198680.7-198680.31" + process $proc$libresoc.v:198680$14488 + assign { } { } + assign $1\core_core_reg1_ok[0:0] 1'0 + sync always + sync init + update \core_core_reg1_ok $1\core_core_reg1_ok[0:0] + end + attribute \src "libresoc.v:198684.13-198684.35" + process $proc$libresoc.v:198684$14489 + assign { } { } + assign $1\core_core_reg2[6:0] 7'0000000 + sync always + sync init + update \core_core_reg2 $1\core_core_reg2[6:0] + end + attribute \src "libresoc.v:198688.7-198688.31" + process $proc$libresoc.v:198688$14490 + assign { } { } + assign $1\core_core_reg2_ok[0:0] 1'0 + sync always + sync init + update \core_core_reg2_ok $1\core_core_reg2_ok[0:0] + end + attribute \src "libresoc.v:198692.13-198692.35" + process $proc$libresoc.v:198692$14491 + assign { } { } + assign $1\core_core_reg3[6:0] 7'0000000 + sync always + sync init + update \core_core_reg3 $1\core_core_reg3[6:0] + end + attribute \src "libresoc.v:198696.7-198696.31" + process $proc$libresoc.v:198696$14492 + assign { } { } + assign $1\core_core_reg3_ok[0:0] 1'0 + sync always + sync init + update \core_core_reg3_ok $1\core_core_reg3_ok[0:0] + end + attribute \src "libresoc.v:198700.13-198700.35" + process $proc$libresoc.v:198700$14493 + assign { } { } + assign $1\core_core_rego[6:0] 7'0000000 + sync always + sync init + update \core_core_rego $1\core_core_rego[6:0] + end + attribute \src "libresoc.v:198817.13-198817.37" + process $proc$libresoc.v:198817$14494 + assign { } { } + assign $1\core_core_spr1[9:0] 10'0000000000 + sync always + sync init + update \core_core_spr1 $1\core_core_spr1[9:0] + end + attribute \src "libresoc.v:198821.7-198821.31" + process $proc$libresoc.v:198821$14495 + assign { } { } + assign $1\core_core_spr1_ok[0:0] 1'0 + sync always + sync init + update \core_core_spr1_ok $1\core_core_spr1_ok[0:0] + end + attribute \src "libresoc.v:198938.13-198938.37" + process $proc$libresoc.v:198938$14496 + assign { } { } + assign $1\core_core_spro[9:0] 10'0000000000 + sync always + sync init + update \core_core_spro $1\core_core_spro[9:0] + end + attribute \src "libresoc.v:198942.13-198942.38" + process $proc$libresoc.v:198942$14497 + assign { } { } + assign $1\core_core_srcstep[6:0] 7'0000000 + sync always + sync init + update \core_core_srcstep $1\core_core_srcstep[6:0] + end + attribute \src "libresoc.v:198946.13-198946.35" + process $proc$libresoc.v:198946$14498 + assign { } { } + assign $1\core_core_subvl[1:0] 2'00 + sync always + sync init + update \core_core_subvl $1\core_core_subvl[1:0] + end + attribute \src "libresoc.v:198950.13-198950.36" + process $proc$libresoc.v:198950$14499 + assign { } { } + assign $1\core_core_svstep[1:0] 2'00 + sync always + sync init + update \core_core_svstep $1\core_core_svstep[1:0] + end + attribute \src "libresoc.v:198956.13-198956.33" + process $proc$libresoc.v:198956$14500 + assign { } { } + assign $1\core_core_vl[6:0] 7'0000000 + sync always + sync init + update \core_core_vl $1\core_core_vl[6:0] + end + attribute \src "libresoc.v:198960.13-198960.36" + process $proc$libresoc.v:198960$14501 + assign { } { } + assign $1\core_core_xer_in[2:0] 3'000 + sync always + sync init + update \core_core_xer_in $1\core_core_xer_in[2:0] + end + attribute \src "libresoc.v:198968.7-198968.28" + process $proc$libresoc.v:198968$14502 + assign { } { } + assign $1\core_cr_out_ok[0:0] 1'0 + sync always + sync init + update \core_cr_out_ok $1\core_cr_out_ok[0:0] + end + attribute \src "libresoc.v:198984.14-198984.45" + process $proc$libresoc.v:198984$14503 + assign { } { } + assign $1\core_dec[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \core_dec $1\core_dec[63:0] + end + attribute \src "libresoc.v:198994.7-198994.24" + process $proc$libresoc.v:198994$14504 + assign { } { } + assign $1\core_ea_ok[0:0] 1'0 + sync always + sync init + update \core_ea_ok $1\core_ea_ok[0:0] + end + attribute \src "libresoc.v:198998.7-198998.23" + process $proc$libresoc.v:198998$14505 + assign { } { } + assign $1\core_eint[0:0] 1'0 + sync always + sync init + update \core_eint $1\core_eint[0:0] + end + attribute \src "libresoc.v:199002.7-199002.28" + process $proc$libresoc.v:199002$14506 + assign { } { } + assign $1\core_fasto1_ok[0:0] 1'0 + sync always + sync init + update \core_fasto1_ok $1\core_fasto1_ok[0:0] + end + attribute \src "libresoc.v:199006.7-199006.28" + process $proc$libresoc.v:199006$14507 + assign { } { } + assign $1\core_fasto2_ok[0:0] 1'0 + sync always + sync init + update \core_fasto2_ok $1\core_fasto2_ok[0:0] + end + attribute \src "libresoc.v:199034.14-199034.45" + process $proc$libresoc.v:199034$14508 + assign { } { } + assign $1\core_msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \core_msr $1\core_msr[63:0] + end + attribute \src "libresoc.v:199042.14-199042.37" + process $proc$libresoc.v:199042$14509 + assign { } { } + assign $1\core_raw_insn_i[31:0] 0 + sync always + sync init + update \core_raw_insn_i $1\core_raw_insn_i[31:0] + end + attribute \src "libresoc.v:199046.7-199046.26" + process $proc$libresoc.v:199046$14510 + assign { } { } + assign $1\core_rego_ok[0:0] 1'0 + sync always + sync init + update \core_rego_ok $1\core_rego_ok[0:0] + end + attribute \src "libresoc.v:199050.7-199050.26" + process $proc$libresoc.v:199050$14511 + assign { } { } + assign $1\core_spro_ok[0:0] 1'0 + sync always + sync init + update \core_spro_ok $1\core_spro_ok[0:0] + end + attribute \src "libresoc.v:199068.7-199068.26" + process $proc$libresoc.v:199068$14512 + assign { } { } + assign $1\core_xer_out[0:0] 1'0 + sync always + sync init + update \core_xer_out $1\core_xer_out[0:0] + end + attribute \src "libresoc.v:199074.7-199074.30" + process $proc$libresoc.v:199074$14513 + assign { } { } + assign $1\cu_st__rel_o_dly[0:0] 1'0 + sync always + sync init + update \cu_st__rel_o_dly $1\cu_st__rel_o_dly[0:0] + end + attribute \src "libresoc.v:199080.13-199080.36" + process $proc$libresoc.v:199080$14514 + assign { } { } + assign $1\cur_cur_dststep[6:0] 7'0000000 + sync always + sync init + update \cur_cur_dststep $1\cur_cur_dststep[6:0] + end + attribute \src "libresoc.v:199084.13-199084.34" + process $proc$libresoc.v:199084$14515 + assign { } { } + assign $1\cur_cur_maxvl[6:0] 7'0000000 + sync always + sync init + update \cur_cur_maxvl $1\cur_cur_maxvl[6:0] + end + attribute \src "libresoc.v:199088.13-199088.33" + process $proc$libresoc.v:199088$14516 + assign { } { } + assign $1\cur_cur_subvl[1:0] 2'00 + sync always + sync init + update \cur_cur_subvl $1\cur_cur_subvl[1:0] + end + attribute \src "libresoc.v:199092.13-199092.34" + process $proc$libresoc.v:199092$14517 + assign { } { } + assign $1\cur_cur_svstep[1:0] 2'00 + sync always + sync init + update \cur_cur_svstep $1\cur_cur_svstep[1:0] + end + attribute \src "libresoc.v:199096.13-199096.31" + process $proc$libresoc.v:199096$14518 + assign { } { } + assign $1\cur_cur_vl[6:0] 7'0000000 + sync always + sync init + update \cur_cur_vl $1\cur_cur_vl[6:0] + end + attribute \src "libresoc.v:199100.7-199100.24" + process $proc$libresoc.v:199100$14519 + assign { } { } + assign $1\d_cr_delay[0:0] 1'0 + sync always + sync init + update \d_cr_delay $1\d_cr_delay[0:0] + end + attribute \src "libresoc.v:199104.7-199104.25" + process $proc$libresoc.v:199104$14520 + assign { } { } + assign $1\d_reg_delay[0:0] 1'0 + sync always + sync init + update \d_reg_delay $1\d_reg_delay[0:0] + end + attribute \src "libresoc.v:199108.7-199108.25" + process $proc$libresoc.v:199108$14521 + assign { } { } + assign $1\d_xer_delay[0:0] 1'0 + sync always + sync init + update \d_xer_delay $1\d_xer_delay[0:0] + end + attribute \src "libresoc.v:199144.13-199144.34" + process $proc$libresoc.v:199144$14522 + assign { } { } + assign $1\dbg_dmi_addr_i[3:0] 4'0000 + sync always + sync init + update \dbg_dmi_addr_i $1\dbg_dmi_addr_i[3:0] + end + attribute \src "libresoc.v:199148.14-199148.48" + process $proc$libresoc.v:199148$14523 + assign { } { } + assign $1\dbg_dmi_din[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \dbg_dmi_din $1\dbg_dmi_din[63:0] + end + attribute \src "libresoc.v:199154.7-199154.27" + process $proc$libresoc.v:199154$14524 + assign { } { } + assign $1\dbg_dmi_req_i[0:0] 1'0 + sync always + sync init + update \dbg_dmi_req_i $1\dbg_dmi_req_i[0:0] + end + attribute \src "libresoc.v:199158.7-199158.26" + process $proc$libresoc.v:199158$14525 + assign { } { } + assign $1\dbg_dmi_we_i[0:0] 1'0 + sync always + sync init + update \dbg_dmi_we_i $1\dbg_dmi_we_i[0:0] + end + attribute \src "libresoc.v:199212.13-199212.41" + process $proc$libresoc.v:199212$14526 + assign { } { } + assign $1\dec2_cur_cur_srcstep[6:0] 7'0000000 + sync always + sync init + update \dec2_cur_cur_srcstep $1\dec2_cur_cur_srcstep[6:0] + end + attribute \src "libresoc.v:199216.14-199216.49" + process $proc$libresoc.v:199216$14527 + assign { } { } + assign $1\dec2_cur_dec[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \dec2_cur_dec $1\dec2_cur_dec[63:0] + end + attribute \src "libresoc.v:199220.7-199220.27" + process $proc$libresoc.v:199220$14528 + assign { } { } + assign $1\dec2_cur_eint[0:0] 1'0 + sync always + sync init + update \dec2_cur_eint $1\dec2_cur_eint[0:0] + end + attribute \src "libresoc.v:199224.14-199224.49" + process $proc$libresoc.v:199224$14529 + assign { } { } + assign $1\dec2_cur_msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \dec2_cur_msr $1\dec2_cur_msr[63:0] + end + attribute \src "libresoc.v:199228.14-199228.48" + process $proc$libresoc.v:199228$14530 + assign { } { } + assign $1\dec2_cur_pc[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \dec2_cur_pc $1\dec2_cur_pc[63:0] + end + attribute \src "libresoc.v:199232.13-199232.43" + process $proc$libresoc.v:199232$14531 + assign { } { } + assign $1\dec2_dec_svp64__extra[8:0] 9'000000000 + sync always + sync init + update \dec2_dec_svp64__extra $1\dec2_dec_svp64__extra[8:0] + end + attribute \src "libresoc.v:199646.13-199646.38" + process $proc$libresoc.v:199646$14532 + assign { } { } + assign $1\dec_svp64__elwidth[1:0] 2'00 + sync always + sync init + update \dec_svp64__elwidth $1\dec_svp64__elwidth[1:0] + end + attribute \src "libresoc.v:199650.13-199650.36" + process $proc$libresoc.v:199650$14533 + assign { } { } + assign $1\dec_svp64__ewsrc[1:0] 2'00 + sync always + sync init + update \dec_svp64__ewsrc $1\dec_svp64__ewsrc[1:0] + end + attribute \src "libresoc.v:199654.13-199654.35" + process $proc$libresoc.v:199654$14534 + assign { } { } + assign $1\dec_svp64__mask[2:0] 3'000 + sync always + sync init + update \dec_svp64__mask $1\dec_svp64__mask[2:0] + end + attribute \src "libresoc.v:199658.7-199658.30" + process $proc$libresoc.v:199658$14535 + assign { } { } + assign $1\dec_svp64__mmode[0:0] 1'0 + sync always + sync init + update \dec_svp64__mmode $1\dec_svp64__mmode[0:0] + end + attribute \src "libresoc.v:199662.13-199662.36" + process $proc$libresoc.v:199662$14536 + assign { } { } + assign $1\dec_svp64__mode[4:0] 5'00000 + sync always + sync init + update \dec_svp64__mode $1\dec_svp64__mode[4:0] + end + attribute \src "libresoc.v:199666.13-199666.36" + process $proc$libresoc.v:199666$14537 + assign { } { } + assign $1\dec_svp64__subvl[1:0] 2'00 + sync always + sync init + update \dec_svp64__subvl $1\dec_svp64__subvl[1:0] + end + attribute \src "libresoc.v:199670.13-199670.25" + process $proc$libresoc.v:199670$14538 + assign { } { } + assign $1\delay[1:0] 2'11 + sync always + sync init + update \delay $1\delay[1:0] + end + attribute \src "libresoc.v:199686.13-199686.35" + process $proc$libresoc.v:199686$14539 + assign { } { } + assign $1\fetch_fsm_state[1:0] 2'00 + sync always + sync init + update \fetch_fsm_state $1\fetch_fsm_state[1:0] + end + attribute \src "libresoc.v:199690.14-199690.34" + process $proc$libresoc.v:199690$14540 + assign { } { } + assign $1\fetch_insn_o[31:0] 0 + sync always + sync init + update \fetch_insn_o $1\fetch_insn_o[31:0] + end + attribute \src "libresoc.v:199702.13-199702.29" + process $proc$libresoc.v:199702$14541 + assign { } { } + assign $1\fsm_state[1:0] 2'00 + sync always + sync init + update \fsm_state $1\fsm_state[1:0] + end + attribute \src "libresoc.v:199704.13-199704.35" + process $proc$libresoc.v:199704$14542 + assign { } { } + assign $0\fsm_state$188[1:0]$14543 2'00 + sync always + sync init + update \fsm_state$188 $0\fsm_state$188[1:0]$14543 + end + attribute \src "libresoc.v:199946.14-199946.28" + process $proc$libresoc.v:199946$14544 + assign { } { } + assign $1\ilatch[31:0] 0 + sync always + sync init + update \ilatch $1\ilatch[31:0] + end + attribute \src "libresoc.v:199964.7-199964.30" + process $proc$libresoc.v:199964$14545 + assign { } { } + assign $1\jtag_dmi0__ack_o[0:0] 1'0 + sync always + sync init + update \jtag_dmi0__ack_o $1\jtag_dmi0__ack_o[0:0] + end + attribute \src "libresoc.v:199972.14-199972.52" + process $proc$libresoc.v:199972$14546 + assign { } { } + assign $1\jtag_dmi0__dout[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \jtag_dmi0__dout $1\jtag_dmi0__dout[63:0] + end + attribute \src "libresoc.v:200028.7-200028.22" + process $proc$libresoc.v:200028$14547 + assign { } { } + assign $1\msr_read[0:0] 1'1 + sync always + sync init + update \msr_read $1\msr_read[0:0] + end + attribute \src "libresoc.v:200064.14-200064.40" + process $proc$libresoc.v:200064$14548 + assign { } { } + assign $1\nia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \nia $1\nia[63:0] + end + attribute \src "libresoc.v:200070.7-200070.24" + process $proc$libresoc.v:200070$14549 + assign { } { } + assign $1\pc_changed[0:0] 1'0 + sync always + sync init + update \pc_changed $1\pc_changed[0:0] + end + attribute \src "libresoc.v:200080.7-200080.25" + process $proc$libresoc.v:200080$14550 + assign { } { } + assign $1\pc_ok_delay[0:0] 1'0 + sync always + sync init + update \pc_ok_delay $1\pc_ok_delay[0:0] + end + attribute \src "libresoc.v:200516.7-200516.21" + process $proc$libresoc.v:200516$14551 + assign { } { } + assign $1\sv_read[0:0] 1'1 + sync always + sync init + update \sv_read $1\sv_read[0:0] + end + attribute \src "libresoc.v:200623.3-200624.41" + process $proc$libresoc.v:200623$13787 + assign { } { } + assign $0\dec2_cur_dec[63:0] \dec2_cur_dec$next + sync posedge \clk + update \dec2_cur_dec $0\dec2_cur_dec[63:0] + end + attribute \src "libresoc.v:200625.3-200626.41" + process $proc$libresoc.v:200625$13788 + assign { } { } + assign $0\core_core_pc[63:0] \core_core_pc$next + sync posedge \clk + update \core_core_pc $0\core_core_pc[63:0] + end + attribute \src "libresoc.v:200627.3-200628.39" + process $proc$libresoc.v:200627$13789 + assign { } { } + assign $0\pc_ok_delay[0:0] \pc_ok_delay$next + sync posedge \clk + update \pc_ok_delay $0\pc_ok_delay[0:0] + end + attribute \src "libresoc.v:200629.3-200630.43" + process $proc$libresoc.v:200629$13790 + assign { } { } + assign $0\cu_st__rel_o_dly[0:0] \core_cu_st__rel_o + sync posedge \clk + update \cu_st__rel_o_dly $0\cu_st__rel_o_dly[0:0] + end + attribute \src "libresoc.v:200631.3-200632.27" + process $proc$libresoc.v:200631$13791 + assign { } { } + assign $0\delay[1:0] \delay$next + sync posedge \por_clk + update \delay $0\delay[1:0] + end + attribute \src "libresoc.v:200633.3-200634.43" + process $proc$libresoc.v:200633$13792 + assign { } { } + assign $0\dec2_cur_eint[0:0] \dec2_cur_eint$next + sync posedge \clk + update \dec2_cur_eint $0\dec2_cur_eint[0:0] + end + attribute \src "libresoc.v:200635.3-200636.47" + process $proc$libresoc.v:200635$13793 + assign { } { } + assign $0\jtag_dmi0__dout[63:0] \jtag_dmi0__dout$next + sync posedge \clk + update \jtag_dmi0__dout $0\jtag_dmi0__dout[63:0] + end + attribute \src "libresoc.v:200637.3-200638.49" + process $proc$libresoc.v:200637$13794 + assign { } { } + assign $0\jtag_dmi0__ack_o[0:0] \jtag_dmi0__ack_o$next + sync posedge \clk + update \jtag_dmi0__ack_o $0\jtag_dmi0__ack_o[0:0] + end + attribute \src "libresoc.v:200639.3-200640.39" + process $proc$libresoc.v:200639$13795 + assign { } { } + assign $0\dbg_dmi_din[63:0] \dbg_dmi_din$next + sync posedge \clk + update \dbg_dmi_din $0\dbg_dmi_din[63:0] + end + attribute \src "libresoc.v:200641.3-200642.41" + process $proc$libresoc.v:200641$13796 + assign { } { } + assign $0\dbg_dmi_we_i[0:0] \dbg_dmi_we_i$next + sync posedge \clk + update \dbg_dmi_we_i $0\dbg_dmi_we_i[0:0] + end + attribute \src "libresoc.v:200643.3-200644.43" + process $proc$libresoc.v:200643$13797 + assign { } { } + assign $0\dbg_dmi_req_i[0:0] \dbg_dmi_req_i$next + sync posedge \clk + update \dbg_dmi_req_i $0\dbg_dmi_req_i[0:0] + end + attribute \src "libresoc.v:200645.3-200646.45" + process $proc$libresoc.v:200645$13798 + assign { } { } + assign $0\dbg_dmi_addr_i[3:0] \dbg_dmi_addr_i$next + sync posedge \clk + update \dbg_dmi_addr_i $0\dbg_dmi_addr_i[3:0] + end + attribute \src "libresoc.v:200647.3-200648.33" + process $proc$libresoc.v:200647$13799 + assign { } { } + assign $0\core_msr[63:0] \core_msr$next + sync posedge \clk + update \core_msr $0\core_msr[63:0] + end + attribute \src "libresoc.v:200649.3-200650.35" + process $proc$libresoc.v:200649$13800 + assign { } { } + assign $0\core_eint[0:0] \core_eint$next + sync posedge \clk + update \core_eint $0\core_eint[0:0] + end + attribute \src "libresoc.v:200651.3-200652.33" + process $proc$libresoc.v:200651$13801 + assign { } { } + assign $0\core_dec[63:0] \core_dec$next + sync posedge \clk + update \core_dec $0\core_dec[63:0] + end + attribute \src "libresoc.v:200653.3-200654.49" + process $proc$libresoc.v:200653$13802 + assign { } { } + assign $0\core_core_svstep[1:0] \core_core_svstep$next + sync posedge \clk + update \core_core_svstep $0\core_core_svstep[1:0] + end + attribute \src "libresoc.v:200655.3-200656.47" + process $proc$libresoc.v:200655$13803 + assign { } { } + assign $0\core_core_subvl[1:0] \core_core_subvl$next + sync posedge \clk + update \core_core_subvl $0\core_core_subvl[1:0] + end + attribute \src "libresoc.v:200657.3-200658.51" + process $proc$libresoc.v:200657$13804 + assign { } { } + assign $0\core_core_dststep[6:0] \core_core_dststep$next + sync posedge \clk + update \core_core_dststep $0\core_core_dststep[6:0] + end + attribute \src "libresoc.v:200659.3-200660.51" + process $proc$libresoc.v:200659$13805 + assign { } { } + assign $0\core_core_srcstep[6:0] \core_core_srcstep$next + sync posedge \clk + update \core_core_srcstep $0\core_core_srcstep[6:0] + end + attribute \src "libresoc.v:200661.3-200662.41" + process $proc$libresoc.v:200661$13806 + assign { } { } + assign $0\core_core_vl[6:0] \core_core_vl$next + sync posedge \clk + update \core_core_vl $0\core_core_vl[6:0] + end + attribute \src "libresoc.v:200663.3-200664.47" + process $proc$libresoc.v:200663$13807 + assign { } { } + assign $0\core_core_maxvl[6:0] \core_core_maxvl$next + sync posedge \clk + update \core_core_maxvl $0\core_core_maxvl[6:0] + end + attribute \src "libresoc.v:200665.3-200666.45" + process $proc$libresoc.v:200665$13808 + assign { } { } + assign $0\fsm_state$188[1:0]$13809 \fsm_state$188$next + sync posedge \clk + update \fsm_state$188 $0\fsm_state$188[1:0]$13809 + end + attribute \src "libresoc.v:200667.3-200668.41" + process $proc$libresoc.v:200667$13810 + assign { } { } + assign $0\core_asmcode[7:0] \core_asmcode$next + sync posedge \clk + update \core_asmcode $0\core_asmcode[7:0] + end + attribute \src "libresoc.v:200669.3-200670.45" + process $proc$libresoc.v:200669$13811 + assign { } { } + assign $0\core_core_rego[6:0] \core_core_rego$next + sync posedge \clk + update \core_core_rego $0\core_core_rego[6:0] + end + attribute \src "libresoc.v:200671.3-200672.41" + process $proc$libresoc.v:200671$13812 + assign { } { } + assign $0\core_rego_ok[0:0] \core_rego_ok$next + sync posedge \clk + update \core_rego_ok $0\core_rego_ok[0:0] + end + attribute \src "libresoc.v:200673.3-200674.41" + process $proc$libresoc.v:200673$13813 + assign { } { } + assign $0\core_core_ea[6:0] \core_core_ea$next + sync posedge \clk + update \core_core_ea $0\core_core_ea[6:0] + end + attribute \src "libresoc.v:200675.3-200676.37" + process $proc$libresoc.v:200675$13814 + assign { } { } + assign $0\core_ea_ok[0:0] \core_ea_ok$next + sync posedge \clk + update \core_ea_ok $0\core_ea_ok[0:0] + end + attribute \src "libresoc.v:200677.3-200678.45" + process $proc$libresoc.v:200677$13815 + assign { } { } + assign $0\core_core_reg1[6:0] \core_core_reg1$next + sync posedge \clk + update \core_core_reg1 $0\core_core_reg1[6:0] + end + attribute \src "libresoc.v:200679.3-200680.51" + process $proc$libresoc.v:200679$13816 + assign { } { } + assign $0\core_core_reg1_ok[0:0] \core_core_reg1_ok$next + sync posedge \clk + update \core_core_reg1_ok $0\core_core_reg1_ok[0:0] + end + attribute \src "libresoc.v:200681.3-200682.45" + process $proc$libresoc.v:200681$13817 + assign { } { } + assign $0\core_core_reg2[6:0] \core_core_reg2$next + sync posedge \clk + update \core_core_reg2 $0\core_core_reg2[6:0] + end + attribute \src "libresoc.v:200683.3-200684.51" + process $proc$libresoc.v:200683$13818 + assign { } { } + assign $0\core_core_reg2_ok[0:0] \core_core_reg2_ok$next + sync posedge \clk + update \core_core_reg2_ok $0\core_core_reg2_ok[0:0] + end + attribute \src "libresoc.v:200685.3-200686.45" + process $proc$libresoc.v:200685$13819 + assign { } { } + assign $0\core_core_reg3[6:0] \core_core_reg3$next + sync posedge \clk + update \core_core_reg3 $0\core_core_reg3[6:0] + end + attribute \src "libresoc.v:200687.3-200688.39" + process $proc$libresoc.v:200687$13820 + assign { } { } + assign $0\d_xer_delay[0:0] \d_xer_delay$next + sync posedge \clk + update \d_xer_delay $0\d_xer_delay[0:0] + end + attribute \src "libresoc.v:200689.3-200690.51" + process $proc$libresoc.v:200689$13821 + assign { } { } + assign $0\core_core_reg3_ok[0:0] \core_core_reg3_ok$next + sync posedge \clk + update \core_core_reg3_ok $0\core_core_reg3_ok[0:0] + end + attribute \src "libresoc.v:200691.3-200692.45" + process $proc$libresoc.v:200691$13822 + assign { } { } + assign $0\core_core_spro[9:0] \core_core_spro$next + sync posedge \clk + update \core_core_spro $0\core_core_spro[9:0] + end + attribute \src "libresoc.v:200693.3-200694.41" + process $proc$libresoc.v:200693$13823 + assign { } { } + assign $0\core_spro_ok[0:0] \core_spro_ok$next + sync posedge \clk + update \core_spro_ok $0\core_spro_ok[0:0] + end + attribute \src "libresoc.v:200695.3-200696.45" + process $proc$libresoc.v:200695$13824 + assign { } { } + assign $0\core_core_spr1[9:0] \core_core_spr1$next + sync posedge \clk + update \core_core_spr1 $0\core_core_spr1[9:0] + end + attribute \src "libresoc.v:200697.3-200698.51" + process $proc$libresoc.v:200697$13825 + assign { } { } + assign $0\core_core_spr1_ok[0:0] \core_core_spr1_ok$next + sync posedge \clk + update \core_core_spr1_ok $0\core_core_spr1_ok[0:0] + end + attribute \src "libresoc.v:200699.3-200700.49" + process $proc$libresoc.v:200699$13826 + assign { } { } + assign $0\core_core_xer_in[2:0] \core_core_xer_in$next + sync posedge \clk + update \core_core_xer_in $0\core_core_xer_in[2:0] + end + attribute \src "libresoc.v:200701.3-200702.41" + process $proc$libresoc.v:200701$13827 + assign { } { } + assign $0\core_xer_out[0:0] \core_xer_out$next + sync posedge \clk + update \core_xer_out $0\core_xer_out[0:0] + end + attribute \src "libresoc.v:200703.3-200704.47" + process $proc$libresoc.v:200703$13828 + assign { } { } + assign $0\core_core_fast1[2:0] \core_core_fast1$next + sync posedge \clk + update \core_core_fast1 $0\core_core_fast1[2:0] + end + attribute \src "libresoc.v:200705.3-200706.53" + process $proc$libresoc.v:200705$13829 + assign { } { } + assign $0\core_core_fast1_ok[0:0] \core_core_fast1_ok$next + sync posedge \clk + update \core_core_fast1_ok $0\core_core_fast1_ok[0:0] + end + attribute \src "libresoc.v:200707.3-200708.47" + process $proc$libresoc.v:200707$13830 + assign { } { } + assign $0\core_core_fast2[2:0] \core_core_fast2$next + sync posedge \clk + update \core_core_fast2 $0\core_core_fast2[2:0] + end + attribute \src "libresoc.v:200709.3-200710.37" + process $proc$libresoc.v:200709$13831 + assign { } { } + assign $0\d_cr_delay[0:0] \d_cr_delay$next + sync posedge \clk + update \d_cr_delay $0\d_cr_delay[0:0] + end + attribute \src "libresoc.v:200711.3-200712.53" + process $proc$libresoc.v:200711$13832 + assign { } { } + assign $0\core_core_fast2_ok[0:0] \core_core_fast2_ok$next + sync posedge \clk + update \core_core_fast2_ok $0\core_core_fast2_ok[0:0] + end + attribute \src "libresoc.v:200713.3-200714.49" + process $proc$libresoc.v:200713$13833 + assign { } { } + assign $0\core_core_fasto1[2:0] \core_core_fasto1$next + sync posedge \clk + update \core_core_fasto1 $0\core_core_fasto1[2:0] + end + attribute \src "libresoc.v:200715.3-200716.45" + process $proc$libresoc.v:200715$13834 + assign { } { } + assign $0\core_fasto1_ok[0:0] \core_fasto1_ok$next + sync posedge \clk + update \core_fasto1_ok $0\core_fasto1_ok[0:0] + end + attribute \src "libresoc.v:200717.3-200718.49" + process $proc$libresoc.v:200717$13835 + assign { } { } + assign $0\core_core_fasto2[2:0] \core_core_fasto2$next + sync posedge \clk + update \core_core_fasto2 $0\core_core_fasto2[2:0] + end + attribute \src "libresoc.v:200719.3-200720.45" + process $proc$libresoc.v:200719$13836 + assign { } { } + assign $0\core_fasto2_ok[0:0] \core_fasto2_ok$next + sync posedge \clk + update \core_fasto2_ok $0\core_fasto2_ok[0:0] + end + attribute \src "libresoc.v:200721.3-200722.49" + process $proc$libresoc.v:200721$13837 + assign { } { } + assign $0\core_core_cr_in1[6:0] \core_core_cr_in1$next + sync posedge \clk + update \core_core_cr_in1 $0\core_core_cr_in1[6:0] + end + attribute \src "libresoc.v:200723.3-200724.55" + process $proc$libresoc.v:200723$13838 + assign { } { } + assign $0\core_core_cr_in1_ok[0:0] \core_core_cr_in1_ok$next + sync posedge \clk + update \core_core_cr_in1_ok $0\core_core_cr_in1_ok[0:0] + end + attribute \src "libresoc.v:200725.3-200726.49" + process $proc$libresoc.v:200725$13839 + assign { } { } + assign $0\core_core_cr_in2[6:0] \core_core_cr_in2$next + sync posedge \clk + update \core_core_cr_in2 $0\core_core_cr_in2[6:0] + end + attribute \src "libresoc.v:200727.3-200728.55" + process $proc$libresoc.v:200727$13840 + assign { } { } + assign $0\core_core_cr_in2_ok[0:0] \core_core_cr_in2_ok$next + sync posedge \clk + update \core_core_cr_in2_ok $0\core_core_cr_in2_ok[0:0] + end + attribute \src "libresoc.v:200729.3-200730.55" + process $proc$libresoc.v:200729$13841 + assign { } { } + assign $0\core_core_cr_in2$1[6:0]$13842 \core_core_cr_in2$1$next + sync posedge \clk + update \core_core_cr_in2$1 $0\core_core_cr_in2$1[6:0]$13842 + end + attribute \src "libresoc.v:200731.3-200732.39" + process $proc$libresoc.v:200731$13843 + assign { } { } + assign $0\d_reg_delay[0:0] \d_reg_delay$next + sync posedge \clk + update \d_reg_delay $0\d_reg_delay[0:0] + end + attribute \src "libresoc.v:200733.3-200734.61" + process $proc$libresoc.v:200733$13844 + assign { } { } + assign $0\core_core_cr_in2_ok$2[0:0]$13845 \core_core_cr_in2_ok$2$next + sync posedge \clk + update \core_core_cr_in2_ok$2 $0\core_core_cr_in2_ok$2[0:0]$13845 + end + attribute \src "libresoc.v:200735.3-200736.49" + process $proc$libresoc.v:200735$13846 + assign { } { } + assign $0\core_core_cr_out[6:0] \core_core_cr_out$next + sync posedge \clk + update \core_core_cr_out $0\core_core_cr_out[6:0] + end + attribute \src "libresoc.v:200737.3-200738.45" + process $proc$libresoc.v:200737$13847 + assign { } { } + assign $0\core_cr_out_ok[0:0] \core_cr_out_ok$next + sync posedge \clk + update \core_cr_out_ok $0\core_cr_out_ok[0:0] + end + attribute \src "libresoc.v:200739.3-200740.53" + process $proc$libresoc.v:200739$13848 + assign { } { } + assign $0\core_core_core_msr[63:0] \core_core_core_msr$next + sync posedge \clk + update \core_core_core_msr $0\core_core_core_msr[63:0] + end + attribute \src "libresoc.v:200741.3-200742.53" + process $proc$libresoc.v:200741$13849 + assign { } { } + assign $0\core_core_core_cia[63:0] \core_core_core_cia$next + sync posedge \clk + update \core_core_core_cia $0\core_core_core_cia[63:0] + end + attribute \src "libresoc.v:200743.3-200744.55" + process $proc$libresoc.v:200743$13850 + assign { } { } + assign $0\core_core_core_insn[31:0] \core_core_core_insn$next + sync posedge \clk + update \core_core_core_insn $0\core_core_core_insn[31:0] + end + attribute \src "libresoc.v:200745.3-200746.65" + process $proc$libresoc.v:200745$13851 + assign { } { } + assign $0\core_core_core_insn_type[6:0] \core_core_core_insn_type$next + sync posedge \clk + update \core_core_core_insn_type $0\core_core_core_insn_type[6:0] + end + attribute \src "libresoc.v:200747.3-200748.61" + process $proc$libresoc.v:200747$13852 + assign { } { } + assign $0\core_core_core_fn_unit[12:0] \core_core_core_fn_unit$next + sync posedge \clk + update \core_core_core_fn_unit $0\core_core_core_fn_unit[12:0] + end + attribute \src "libresoc.v:200749.3-200750.41" + process $proc$libresoc.v:200749$13853 + assign { } { } + assign $0\core_core_lk[0:0] \core_core_lk$next + sync posedge \clk + update \core_core_lk $0\core_core_lk[0:0] + end + attribute \src "libresoc.v:200751.3-200752.51" + process $proc$libresoc.v:200751$13854 + assign { } { } + assign $0\core_core_core_rc[0:0] \core_core_core_rc$next + sync posedge \clk + update \core_core_core_rc $0\core_core_core_rc[0:0] + end + attribute \src "libresoc.v:200753.3-200754.37" + process $proc$libresoc.v:200753$13855 + assign { } { } + assign $0\pc_changed[0:0] \pc_changed$next + sync posedge \clk + update \pc_changed $0\pc_changed[0:0] + end + attribute \src "libresoc.v:200755.3-200756.57" + process $proc$libresoc.v:200755$13856 + assign { } { } + assign $0\core_core_core_rc_ok[0:0] \core_core_core_rc_ok$next + sync posedge \clk + update \core_core_core_rc_ok $0\core_core_core_rc_ok[0:0] + end + attribute \src "libresoc.v:200757.3-200758.51" + process $proc$libresoc.v:200757$13857 + assign { } { } + assign $0\core_core_core_oe[0:0] \core_core_core_oe$next + sync posedge \clk + update \core_core_core_oe $0\core_core_core_oe[0:0] + end + attribute \src "libresoc.v:200759.3-200760.57" + process $proc$libresoc.v:200759$13858 + assign { } { } + assign $0\core_core_core_oe_ok[0:0] \core_core_core_oe_ok$next + sync posedge \clk + update \core_core_core_oe_ok $0\core_core_core_oe_ok[0:0] + end + attribute \src "libresoc.v:200761.3-200762.69" + process $proc$libresoc.v:200761$13859 + assign { } { } + assign $0\core_core_core_input_carry[1:0] \core_core_core_input_carry$next + sync posedge \clk + update \core_core_core_input_carry $0\core_core_core_input_carry[1:0] + end + attribute \src "libresoc.v:200763.3-200764.63" + process $proc$libresoc.v:200763$13860 + assign { } { } + assign $0\core_core_core_traptype[7:0] \core_core_core_traptype$next + sync posedge \clk + update \core_core_core_traptype $0\core_core_core_traptype[7:0] + end + attribute \src "libresoc.v:200765.3-200766.71" + process $proc$libresoc.v:200765$13861 + assign { } { } + assign $0\core_core_core_exc_$signal[0:0]$13862 \core_core_core_exc_$signal$next + sync posedge \clk + update \core_core_core_exc_$signal $0\core_core_core_exc_$signal[0:0]$13862 + end + attribute \src "libresoc.v:200767.3-200768.75" + process $proc$libresoc.v:200767$13863 + assign { } { } + assign $0\core_core_core_exc_$signal$3[0:0]$13864 \core_core_core_exc_$signal$3$next + sync posedge \clk + update \core_core_core_exc_$signal$3 $0\core_core_core_exc_$signal$3[0:0]$13864 + end + attribute \src "libresoc.v:200769.3-200770.75" + process $proc$libresoc.v:200769$13865 + assign { } { } + assign $0\core_core_core_exc_$signal$4[0:0]$13866 \core_core_core_exc_$signal$4$next + sync posedge \clk + update \core_core_core_exc_$signal$4 $0\core_core_core_exc_$signal$4[0:0]$13866 + end + attribute \src "libresoc.v:200771.3-200772.75" + process $proc$libresoc.v:200771$13867 + assign { } { } + assign $0\core_core_core_exc_$signal$5[0:0]$13868 \core_core_core_exc_$signal$5$next + sync posedge \clk + update \core_core_core_exc_$signal$5 $0\core_core_core_exc_$signal$5[0:0]$13868 + end + attribute \src "libresoc.v:200773.3-200774.75" + process $proc$libresoc.v:200773$13869 + assign { } { } + assign $0\core_core_core_exc_$signal$6[0:0]$13870 \core_core_core_exc_$signal$6$next + sync posedge \clk + update \core_core_core_exc_$signal$6 $0\core_core_core_exc_$signal$6[0:0]$13870 + end + attribute \src "libresoc.v:200775.3-200776.29" + process $proc$libresoc.v:200775$13871 + assign { } { } + assign $0\ilatch[31:0] \ilatch$next + sync posedge \clk + update \ilatch $0\ilatch[31:0] + end + attribute \src "libresoc.v:200777.3-200778.75" + process $proc$libresoc.v:200777$13872 + assign { } { } + assign $0\core_core_core_exc_$signal$7[0:0]$13873 \core_core_core_exc_$signal$7$next + sync posedge \clk + update \core_core_core_exc_$signal$7 $0\core_core_core_exc_$signal$7[0:0]$13873 + end + attribute \src "libresoc.v:200779.3-200780.75" + process $proc$libresoc.v:200779$13874 + assign { } { } + assign $0\core_core_core_exc_$signal$8[0:0]$13875 \core_core_core_exc_$signal$8$next + sync posedge \clk + update \core_core_core_exc_$signal$8 $0\core_core_core_exc_$signal$8[0:0]$13875 + end + attribute \src "libresoc.v:200781.3-200782.75" + process $proc$libresoc.v:200781$13876 + assign { } { } + assign $0\core_core_core_exc_$signal$9[0:0]$13877 \core_core_core_exc_$signal$9$next + sync posedge \clk + update \core_core_core_exc_$signal$9 $0\core_core_core_exc_$signal$9[0:0]$13877 + end + attribute \src "libresoc.v:200783.3-200784.63" + process $proc$libresoc.v:200783$13878 + assign { } { } + assign $0\core_core_core_trapaddr[12:0] \core_core_core_trapaddr$next + sync posedge \clk + update \core_core_core_trapaddr $0\core_core_core_trapaddr[12:0] + end + attribute \src "libresoc.v:200785.3-200786.57" + process $proc$libresoc.v:200785$13879 + assign { } { } + assign $0\core_core_core_cr_rd[7:0] \core_core_core_cr_rd$next + sync posedge \clk + update \core_core_core_cr_rd $0\core_core_core_cr_rd[7:0] + end + attribute \src "libresoc.v:200787.3-200788.63" + process $proc$libresoc.v:200787$13880 + assign { } { } + assign $0\core_core_core_cr_rd_ok[0:0] \core_core_core_cr_rd_ok$next + sync posedge \clk + update \core_core_core_cr_rd_ok $0\core_core_core_cr_rd_ok[0:0] + end + attribute \src "libresoc.v:200789.3-200790.57" + process $proc$libresoc.v:200789$13881 + assign { } { } + assign $0\core_core_core_cr_wr[7:0] \core_core_core_cr_wr$next + sync posedge \clk + update \core_core_core_cr_wr $0\core_core_core_cr_wr[7:0] + end + attribute \src "libresoc.v:200791.3-200792.53" + process $proc$libresoc.v:200791$13882 + assign { } { } + assign $0\core_core_cr_wr_ok[0:0] \core_core_cr_wr_ok$next + sync posedge \clk + update \core_core_cr_wr_ok $0\core_core_cr_wr_ok[0:0] + end + attribute \src "libresoc.v:200793.3-200794.63" + process $proc$libresoc.v:200793$13883 + assign { } { } + assign $0\core_core_core_is_32bit[0:0] \core_core_core_is_32bit$next + sync posedge \clk + update \core_core_core_is_32bit $0\core_core_core_is_32bit[0:0] + end + attribute \src "libresoc.v:200795.3-200796.35" + process $proc$libresoc.v:200795$13884 + assign { } { } + assign $0\fsm_state[1:0] \fsm_state$next + sync posedge \clk + update \fsm_state $0\fsm_state[1:0] + end + attribute \src "libresoc.v:200797.3-200798.57" + process $proc$libresoc.v:200797$13885 + assign { } { } + assign $0\core_bigendian_i$10[0:0]$13886 \core_bigendian_i$10$next + sync posedge \clk + update \core_bigendian_i$10 $0\core_bigendian_i$10[0:0]$13886 + end + attribute \src "libresoc.v:200799.3-200800.41" + process $proc$libresoc.v:200799$13887 + assign { } { } + assign $0\fetch_insn_o[31:0] \fetch_insn_o$next + sync posedge \clk + update \fetch_insn_o $0\fetch_insn_o[31:0] + end + attribute \src "libresoc.v:200801.3-200802.23" + process $proc$libresoc.v:200801$13888 + assign { } { } + assign $0\nia[63:0] \nia$next + sync posedge \clk + update \nia $0\nia[63:0] + end + attribute \src "libresoc.v:200803.3-200804.47" + process $proc$libresoc.v:200803$13889 + assign { } { } + assign $0\dec_svp64__mode[4:0] \dec_svp64__mode$next + sync posedge \clk + update \dec_svp64__mode $0\dec_svp64__mode[4:0] + end + attribute \src "libresoc.v:200805.3-200806.59" + process $proc$libresoc.v:200805$13890 + assign { } { } + assign $0\dec2_dec_svp64__extra[8:0] \dec2_dec_svp64__extra$next + sync posedge \clk + update \dec2_dec_svp64__extra $0\dec2_dec_svp64__extra[8:0] + end + attribute \src "libresoc.v:200807.3-200808.49" + process $proc$libresoc.v:200807$13891 + assign { } { } + assign $0\dec_svp64__subvl[1:0] \dec_svp64__subvl$next + sync posedge \clk + update \dec_svp64__subvl $0\dec_svp64__subvl[1:0] + end + attribute \src "libresoc.v:200809.3-200810.49" + process $proc$libresoc.v:200809$13892 + assign { } { } + assign $0\dec_svp64__ewsrc[1:0] \dec_svp64__ewsrc$next + sync posedge \clk + update \dec_svp64__ewsrc $0\dec_svp64__ewsrc[1:0] + end + attribute \src "libresoc.v:200811.3-200812.53" + process $proc$libresoc.v:200811$13893 + assign { } { } + assign $0\dec_svp64__elwidth[1:0] \dec_svp64__elwidth$next + sync posedge \clk + update \dec_svp64__elwidth $0\dec_svp64__elwidth[1:0] + end + attribute \src "libresoc.v:200813.3-200814.47" + process $proc$libresoc.v:200813$13894 + assign { } { } + assign $0\dec_svp64__mask[2:0] \dec_svp64__mask$next + sync posedge \clk + update \dec_svp64__mask $0\dec_svp64__mask[2:0] + end + attribute \src "libresoc.v:200815.3-200816.49" + process $proc$libresoc.v:200815$13895 + assign { } { } + assign $0\dec_svp64__mmode[0:0] \dec_svp64__mmode$next + sync posedge \clk + update \dec_svp64__mmode $0\dec_svp64__mmode[0:0] + end + attribute \src "libresoc.v:200817.3-200818.45" + process $proc$libresoc.v:200817$13896 + assign { } { } + assign $0\cur_cur_svstep[1:0] \cur_cur_svstep$next + sync posedge \clk + update \cur_cur_svstep $0\cur_cur_svstep[1:0] + end + attribute \src "libresoc.v:200819.3-200820.47" + process $proc$libresoc.v:200819$13897 + assign { } { } + assign $0\core_raw_insn_i[31:0] \core_raw_insn_i$next + sync posedge \clk + update \core_raw_insn_i $0\core_raw_insn_i[31:0] + end + attribute \src "libresoc.v:200821.3-200822.43" + process $proc$libresoc.v:200821$13898 + assign { } { } + assign $0\cur_cur_subvl[1:0] \cur_cur_subvl$next + sync posedge \clk + update \cur_cur_subvl $0\cur_cur_subvl[1:0] + end + attribute \src "libresoc.v:200823.3-200824.47" + process $proc$libresoc.v:200823$13899 + assign { } { } + assign $0\cur_cur_dststep[6:0] \cur_cur_dststep$next + sync posedge \clk + update \cur_cur_dststep $0\cur_cur_dststep[6:0] + end + attribute \src "libresoc.v:200825.3-200826.57" + process $proc$libresoc.v:200825$13900 + assign { } { } + assign $0\dec2_cur_cur_srcstep[6:0] \dec2_cur_cur_srcstep$next + sync posedge \clk + update \dec2_cur_cur_srcstep $0\dec2_cur_cur_srcstep[6:0] + end + attribute \src "libresoc.v:200827.3-200828.37" + process $proc$libresoc.v:200827$13901 + assign { } { } + assign $0\cur_cur_vl[6:0] \cur_cur_vl$next + sync posedge \clk + update \cur_cur_vl $0\cur_cur_vl[6:0] + end + attribute \src "libresoc.v:200829.3-200830.43" + process $proc$libresoc.v:200829$13902 + assign { } { } + assign $0\cur_cur_maxvl[6:0] \cur_cur_maxvl$next + sync posedge \clk + update \cur_cur_maxvl $0\cur_cur_maxvl[6:0] + end + attribute \src "libresoc.v:200831.3-200832.41" + process $proc$libresoc.v:200831$13903 + assign { } { } + assign $0\dec2_cur_msr[63:0] \dec2_cur_msr$next + sync posedge \clk + update \dec2_cur_msr $0\dec2_cur_msr[63:0] + end + attribute \src "libresoc.v:200833.3-200834.47" + process $proc$libresoc.v:200833$13904 + assign { } { } + assign $0\fetch_fsm_state[1:0] \fetch_fsm_state$next + sync posedge \clk + update \fetch_fsm_state $0\fetch_fsm_state[1:0] + end + attribute \src "libresoc.v:200835.3-200836.31" + process $proc$libresoc.v:200835$13905 + assign { } { } + assign $0\sv_read[0:0] \sv_read$next + sync posedge \clk + update \sv_read $0\sv_read[0:0] + end + attribute \src "libresoc.v:200837.3-200838.33" + process $proc$libresoc.v:200837$13906 + assign { } { } + assign $0\msr_read[0:0] \msr_read$next + sync posedge \clk + update \msr_read $0\msr_read[0:0] + end + attribute \src "libresoc.v:200839.3-200840.39" + process $proc$libresoc.v:200839$13907 + assign { } { } + assign $0\dec2_cur_pc[63:0] \dec2_cur_pc$next + sync posedge \clk + update \dec2_cur_pc $0\dec2_cur_pc[63:0] + end + attribute \src "libresoc.v:201466.3-201474.6" + process $proc$libresoc.v:201466$13908 + assign { } { } + assign { } { } + assign $0\dbg_dmi_addr_i$next[3:0]$13909 $1\dbg_dmi_addr_i$next[3:0]$13910 + attribute \src "libresoc.v:201467.5-201467.29" + switch \initial + attribute \src "libresoc.v:201467.9-201467.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dbg_dmi_addr_i$next[3:0]$13910 4'0000 + case + assign $1\dbg_dmi_addr_i$next[3:0]$13910 \jtag_dmi0__addr_i + end + sync always + update \dbg_dmi_addr_i$next $0\dbg_dmi_addr_i$next[3:0]$13909 + end + attribute \src "libresoc.v:201475.3-201483.6" + process $proc$libresoc.v:201475$13911 + assign { } { } + assign { } { } + assign $0\dbg_dmi_req_i$next[0:0]$13912 $1\dbg_dmi_req_i$next[0:0]$13913 + attribute \src "libresoc.v:201476.5-201476.29" + switch \initial + attribute \src "libresoc.v:201476.9-201476.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dbg_dmi_req_i$next[0:0]$13913 1'0 + case + assign $1\dbg_dmi_req_i$next[0:0]$13913 \jtag_dmi0__req_i + end + sync always + update \dbg_dmi_req_i$next $0\dbg_dmi_req_i$next[0:0]$13912 + end + attribute \src "libresoc.v:201484.3-201524.6" + process $proc$libresoc.v:201484$13914 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\core_core_dststep$next[6:0]$13915 $3\core_core_dststep$next[6:0]$13945 + assign $0\core_core_maxvl$next[6:0]$13916 $3\core_core_maxvl$next[6:0]$13946 + assign $0\core_core_pc$next[63:0]$13917 $3\core_core_pc$next[63:0]$13947 + assign $0\core_core_srcstep$next[6:0]$13918 $3\core_core_srcstep$next[6:0]$13948 + assign $0\core_core_subvl$next[1:0]$13919 $3\core_core_subvl$next[1:0]$13949 + assign $0\core_core_svstep$next[1:0]$13920 $3\core_core_svstep$next[1:0]$13950 + assign $0\core_core_vl$next[6:0]$13921 $3\core_core_vl$next[6:0]$13951 + assign $0\core_dec$next[63:0]$13922 $3\core_dec$next[63:0]$13952 + assign $0\core_eint$next[0:0]$13923 $3\core_eint$next[0:0]$13953 + assign $0\core_msr$next[63:0]$13924 $3\core_msr$next[63:0]$13954 + attribute \src "libresoc.v:201485.5-201485.29" + switch \initial + attribute \src "libresoc.v:201485.9-201485.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:375" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\core_core_dststep$next[6:0]$13925 $2\core_core_dststep$next[6:0]$13935 + assign $1\core_core_maxvl$next[6:0]$13926 $2\core_core_maxvl$next[6:0]$13936 + assign $1\core_core_pc$next[63:0]$13927 $2\core_core_pc$next[63:0]$13937 + assign $1\core_core_srcstep$next[6:0]$13928 $2\core_core_srcstep$next[6:0]$13938 + assign $1\core_core_subvl$next[1:0]$13929 $2\core_core_subvl$next[1:0]$13939 + assign $1\core_core_svstep$next[1:0]$13930 $2\core_core_svstep$next[1:0]$13940 + assign $1\core_core_vl$next[6:0]$13931 $2\core_core_vl$next[6:0]$13941 + assign $1\core_dec$next[63:0]$13932 $2\core_dec$next[63:0]$13942 + assign $1\core_eint$next[0:0]$13933 $2\core_eint$next[0:0]$13943 + assign $1\core_msr$next[63:0]$13934 $2\core_msr$next[63:0]$13944 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:388" + switch \fetch_insn_valid_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $2\core_core_maxvl$next[6:0]$13936 $2\core_core_vl$next[6:0]$13941 $2\core_core_srcstep$next[6:0]$13938 $2\core_core_dststep$next[6:0]$13935 $2\core_core_subvl$next[1:0]$13939 $2\core_core_svstep$next[1:0]$13940 $2\core_dec$next[63:0]$13942 $2\core_eint$next[0:0]$13943 $2\core_msr$next[63:0]$13944 $2\core_core_pc$next[63:0]$13937 } { \cur_cur_maxvl \cur_cur_vl \dec2_cur_cur_srcstep \cur_cur_dststep \cur_cur_subvl \cur_cur_svstep \dec2_cur_dec \dec2_cur_eint \dec2_cur_msr \dec2_cur_pc } + case + assign $2\core_core_dststep$next[6:0]$13935 \core_core_dststep + assign $2\core_core_maxvl$next[6:0]$13936 \core_core_maxvl + assign $2\core_core_pc$next[63:0]$13937 \core_core_pc + assign $2\core_core_srcstep$next[6:0]$13938 \core_core_srcstep + assign $2\core_core_subvl$next[1:0]$13939 \core_core_subvl + assign $2\core_core_svstep$next[1:0]$13940 \core_core_svstep + assign $2\core_core_vl$next[6:0]$13941 \core_core_vl + assign $2\core_dec$next[63:0]$13942 \core_dec + assign $2\core_eint$next[0:0]$13943 \core_eint + assign $2\core_msr$next[63:0]$13944 \core_msr + end + case + assign $1\core_core_dststep$next[6:0]$13925 \core_core_dststep + assign $1\core_core_maxvl$next[6:0]$13926 \core_core_maxvl + assign $1\core_core_pc$next[63:0]$13927 \core_core_pc + assign $1\core_core_srcstep$next[6:0]$13928 \core_core_srcstep + assign $1\core_core_subvl$next[1:0]$13929 \core_core_subvl + assign $1\core_core_svstep$next[1:0]$13930 \core_core_svstep + assign $1\core_core_vl$next[6:0]$13931 \core_core_vl + assign $1\core_dec$next[63:0]$13932 \core_dec + assign $1\core_eint$next[0:0]$13933 \core_eint + assign $1\core_msr$next[63:0]$13934 \core_msr + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $3\core_core_pc$next[63:0]$13947 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\core_msr$next[63:0]$13954 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\core_eint$next[0:0]$13953 1'0 + assign $3\core_dec$next[63:0]$13952 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\core_core_svstep$next[1:0]$13950 2'00 + assign $3\core_core_subvl$next[1:0]$13949 2'00 + assign $3\core_core_dststep$next[6:0]$13945 7'0000000 + assign $3\core_core_srcstep$next[6:0]$13948 7'0000000 + assign $3\core_core_vl$next[6:0]$13951 7'0000000 + assign $3\core_core_maxvl$next[6:0]$13946 7'0000000 + case + assign $3\core_core_dststep$next[6:0]$13945 $1\core_core_dststep$next[6:0]$13925 + assign $3\core_core_maxvl$next[6:0]$13946 $1\core_core_maxvl$next[6:0]$13926 + assign $3\core_core_pc$next[63:0]$13947 $1\core_core_pc$next[63:0]$13927 + assign $3\core_core_srcstep$next[6:0]$13948 $1\core_core_srcstep$next[6:0]$13928 + assign $3\core_core_subvl$next[1:0]$13949 $1\core_core_subvl$next[1:0]$13929 + assign $3\core_core_svstep$next[1:0]$13950 $1\core_core_svstep$next[1:0]$13930 + assign $3\core_core_vl$next[6:0]$13951 $1\core_core_vl$next[6:0]$13931 + assign $3\core_dec$next[63:0]$13952 $1\core_dec$next[63:0]$13932 + assign $3\core_eint$next[0:0]$13953 $1\core_eint$next[0:0]$13933 + assign $3\core_msr$next[63:0]$13954 $1\core_msr$next[63:0]$13934 + end + sync always + update \core_core_dststep$next $0\core_core_dststep$next[6:0]$13915 + update \core_core_maxvl$next $0\core_core_maxvl$next[6:0]$13916 + update \core_core_pc$next $0\core_core_pc$next[63:0]$13917 + update \core_core_srcstep$next $0\core_core_srcstep$next[6:0]$13918 + update \core_core_subvl$next $0\core_core_subvl$next[1:0]$13919 + update \core_core_svstep$next $0\core_core_svstep$next[1:0]$13920 + update \core_core_vl$next $0\core_core_vl$next[6:0]$13921 + update \core_dec$next $0\core_dec$next[63:0]$13922 + update \core_eint$next $0\core_eint$next[0:0]$13923 + update \core_msr$next $0\core_msr$next[63:0]$13924 + end + attribute \src "libresoc.v:201525.3-201554.6" + process $proc$libresoc.v:201525$13955 + assign { } { } + assign { } { } + assign { } { } + assign $0\core_raw_insn_i$next[31:0]$13956 $4\core_raw_insn_i$next[31:0]$13960 + attribute \src "libresoc.v:201526.5-201526.29" + switch \initial + attribute \src "libresoc.v:201526.9-201526.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:375" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\core_raw_insn_i$next[31:0]$13957 $2\core_raw_insn_i$next[31:0]$13958 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:388" + switch \fetch_insn_valid_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\core_raw_insn_i$next[31:0]$13958 \dec2_raw_opcode_in + case + assign $2\core_raw_insn_i$next[31:0]$13958 \core_raw_insn_i + end + attribute \src "libresoc.v:0.0-0.0" + case 2'11 + assign { } { } + assign $1\core_raw_insn_i$next[31:0]$13957 $3\core_raw_insn_i$next[31:0]$13959 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:413" + switch \$165 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\core_raw_insn_i$next[31:0]$13959 0 + case + assign $3\core_raw_insn_i$next[31:0]$13959 \core_raw_insn_i + end + case + assign $1\core_raw_insn_i$next[31:0]$13957 \core_raw_insn_i + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\core_raw_insn_i$next[31:0]$13960 0 + case + assign $4\core_raw_insn_i$next[31:0]$13960 $1\core_raw_insn_i$next[31:0]$13957 + end + sync always + update \core_raw_insn_i$next $0\core_raw_insn_i$next[31:0]$13956 + end + attribute \src "libresoc.v:201555.3-201584.6" + process $proc$libresoc.v:201555$13961 + assign { } { } + assign { } { } + assign { } { } + assign $0\core_bigendian_i$10$next[0:0]$13962 $4\core_bigendian_i$10$next[0:0]$13966 + attribute \src "libresoc.v:201556.5-201556.29" + switch \initial + attribute \src "libresoc.v:201556.9-201556.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:375" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\core_bigendian_i$10$next[0:0]$13963 $2\core_bigendian_i$10$next[0:0]$13964 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:388" + switch \fetch_insn_valid_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\core_bigendian_i$10$next[0:0]$13964 \core_bigendian_i + case + assign $2\core_bigendian_i$10$next[0:0]$13964 \core_bigendian_i$10 + end + attribute \src "libresoc.v:0.0-0.0" + case 2'11 + assign { } { } + assign $1\core_bigendian_i$10$next[0:0]$13963 $3\core_bigendian_i$10$next[0:0]$13965 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:413" + switch \$167 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\core_bigendian_i$10$next[0:0]$13965 1'0 + case + assign $3\core_bigendian_i$10$next[0:0]$13965 \core_bigendian_i$10 + end + case + assign $1\core_bigendian_i$10$next[0:0]$13963 \core_bigendian_i$10 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\core_bigendian_i$10$next[0:0]$13966 1'0 + case + assign $4\core_bigendian_i$10$next[0:0]$13966 $1\core_bigendian_i$10$next[0:0]$13963 + end + sync always + update \core_bigendian_i$10$next $0\core_bigendian_i$10$next[0:0]$13962 + end + attribute \src "libresoc.v:201585.3-201605.6" + process $proc$libresoc.v:201585$13967 + assign { } { } + assign { } { } + assign { } { } + assign $0\ilatch$next[31:0]$13968 $3\ilatch$next[31:0]$13971 + attribute \src "libresoc.v:201586.5-201586.29" + switch \initial + attribute \src "libresoc.v:201586.9-201586.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:375" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\ilatch$next[31:0]$13969 $2\ilatch$next[31:0]$13970 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:388" + switch \fetch_insn_valid_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ilatch$next[31:0]$13970 \$169 + case + assign $2\ilatch$next[31:0]$13970 \ilatch + end + case + assign $1\ilatch$next[31:0]$13969 \ilatch + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\ilatch$next[31:0]$13971 0 + case + assign $3\ilatch$next[31:0]$13971 $1\ilatch$next[31:0]$13969 + end + sync always + update \ilatch$next $0\ilatch$next[31:0]$13968 + end + attribute \src "libresoc.v:201606.3-201625.6" + process $proc$libresoc.v:201606$13972 + assign { } { } + assign { } { } + assign $0\core_ivalid_i[0:0] $1\core_ivalid_i[0:0] + attribute \src "libresoc.v:201607.5-201607.29" + switch \initial + attribute \src "libresoc.v:201607.9-201607.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:375" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\core_ivalid_i[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'11 + assign { } { } + assign $1\core_ivalid_i[0:0] $2\core_ivalid_i[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:409" + switch \$176 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\core_ivalid_i[0:0] 1'1 + case + assign $2\core_ivalid_i[0:0] 1'0 + end + case + assign $1\core_ivalid_i[0:0] 1'0 + end + sync always + update \core_ivalid_i $0\core_ivalid_i[0:0] + end + attribute \src "libresoc.v:201626.3-201636.6" + process $proc$libresoc.v:201626$13973 + assign { } { } + assign { } { } + assign $0\core_issue_i[0:0] $1\core_issue_i[0:0] + attribute \src "libresoc.v:201627.5-201627.29" + switch \initial + attribute \src "libresoc.v:201627.9-201627.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:375" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\core_issue_i[0:0] 1'1 + case + assign $1\core_issue_i[0:0] 1'0 + end + sync always + update \core_issue_i $0\core_issue_i[0:0] + end + attribute \src "libresoc.v:201637.3-201661.6" + process $proc$libresoc.v:201637$13974 + assign { } { } + assign { } { } + assign { } { } + assign $0\pc_changed$next[0:0]$13975 $3\pc_changed$next[0:0]$13978 + attribute \src "libresoc.v:201638.5-201638.29" + switch \initial + attribute \src "libresoc.v:201638.9-201638.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:375" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\pc_changed$next[0:0]$13976 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'11 + assign { } { } + assign $1\pc_changed$next[0:0]$13976 $2\pc_changed$next[0:0]$13977 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:411" + switch \$178 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\pc_changed$next[0:0]$13977 1'1 + case + assign $2\pc_changed$next[0:0]$13977 \pc_changed + end + case + assign $1\pc_changed$next[0:0]$13976 \pc_changed + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\pc_changed$next[0:0]$13978 1'0 + case + assign $3\pc_changed$next[0:0]$13978 $1\pc_changed$next[0:0]$13976 + end + sync always + update \pc_changed$next $0\pc_changed$next[0:0]$13975 + end + attribute \src "libresoc.v:201662.3-201671.6" + process $proc$libresoc.v:201662$13979 + assign { } { } + assign { } { } + assign $0\core_wen$11[2:0]$13980 $1\core_wen$11[2:0]$13981 + attribute \src "libresoc.v:201663.5-201663.29" + switch \initial + attribute \src "libresoc.v:201663.9-201663.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:429" + switch \update_svstate + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\core_wen$11[2:0]$13981 3'100 + case + assign $1\core_wen$11[2:0]$13981 3'000 + end + sync always + update \core_wen$11 $0\core_wen$11[2:0]$13980 + end + attribute \src "libresoc.v:201672.3-201681.6" + process $proc$libresoc.v:201672$13982 + assign { } { } + assign { } { } + assign $0\core_data_i$12[63:0]$13983 $1\core_data_i$12[63:0]$13984 + attribute \src "libresoc.v:201673.5-201673.29" + switch \initial + attribute \src "libresoc.v:201673.9-201673.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:429" + switch \update_svstate + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\core_data_i$12[63:0]$13984 \$182 + case + assign $1\core_data_i$12[63:0]$13984 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \core_data_i$12 $0\core_data_i$12[63:0]$13983 + end + attribute \src "libresoc.v:201682.3-201691.6" + process $proc$libresoc.v:201682$13985 + assign { } { } + assign { } { } + assign $0\core_dmi__addr[4:0] $1\core_dmi__addr[4:0] + attribute \src "libresoc.v:201683.5-201683.29" + switch \initial + attribute \src "libresoc.v:201683.9-201683.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:435" + switch \dbg_d_gpr_req + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\core_dmi__addr[4:0] \dbg_d_gpr_addr [4:0] + case + assign $1\core_dmi__addr[4:0] 5'00000 + end + sync always + update \core_dmi__addr $0\core_dmi__addr[4:0] + end + attribute \src "libresoc.v:201692.3-201701.6" + process $proc$libresoc.v:201692$13986 + assign { } { } + assign { } { } + assign $0\core_dmi__ren[0:0] $1\core_dmi__ren[0:0] + attribute \src "libresoc.v:201693.5-201693.29" + switch \initial + attribute \src "libresoc.v:201693.9-201693.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:435" + switch \dbg_d_gpr_req + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\core_dmi__ren[0:0] 1'1 + case + assign $1\core_dmi__ren[0:0] 1'0 + end + sync always + update \core_dmi__ren $0\core_dmi__ren[0:0] + end + attribute \src "libresoc.v:201702.3-201710.6" + process $proc$libresoc.v:201702$13987 + assign { } { } + assign { } { } + assign $0\d_reg_delay$next[0:0]$13988 $1\d_reg_delay$next[0:0]$13989 + attribute \src "libresoc.v:201703.5-201703.29" + switch \initial + attribute \src "libresoc.v:201703.9-201703.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\d_reg_delay$next[0:0]$13989 1'0 + case + assign $1\d_reg_delay$next[0:0]$13989 \dbg_d_gpr_req + end + sync always + update \d_reg_delay$next $0\d_reg_delay$next[0:0]$13988 + end + attribute \src "libresoc.v:201711.3-201720.6" + process $proc$libresoc.v:201711$13990 + assign { } { } + assign { } { } + assign $0\dbg_d_gpr_data[63:0] $1\dbg_d_gpr_data[63:0] + attribute \src "libresoc.v:201712.5-201712.29" + switch \initial + attribute \src "libresoc.v:201712.9-201712.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:445" + switch \d_reg_delay + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dbg_d_gpr_data[63:0] \core_dmi__data_o + case + assign $1\dbg_d_gpr_data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \dbg_d_gpr_data $0\dbg_d_gpr_data[63:0] + end + attribute \src "libresoc.v:201721.3-201730.6" + process $proc$libresoc.v:201721$13991 + assign { } { } + assign { } { } + assign $0\dbg_d_gpr_ack[0:0] $1\dbg_d_gpr_ack[0:0] + attribute \src "libresoc.v:201722.5-201722.29" + switch \initial + attribute \src "libresoc.v:201722.9-201722.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:445" + switch \d_reg_delay + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dbg_d_gpr_ack[0:0] 1'1 + case + assign $1\dbg_d_gpr_ack[0:0] 1'0 + end + sync always + update \dbg_d_gpr_ack $0\dbg_d_gpr_ack[0:0] + end + attribute \src "libresoc.v:201731.3-201740.6" + process $proc$libresoc.v:201731$13992 + assign { } { } + assign { } { } + assign $0\core_full_rd2__ren[7:0] $1\core_full_rd2__ren[7:0] + attribute \src "libresoc.v:201732.5-201732.29" + switch \initial + attribute \src "libresoc.v:201732.9-201732.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:451" + switch \dbg_d_cr_req + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\core_full_rd2__ren[7:0] 8'11111111 + case + assign $1\core_full_rd2__ren[7:0] 8'00000000 + end + sync always + update \core_full_rd2__ren $0\core_full_rd2__ren[7:0] + end + attribute \src "libresoc.v:201741.3-201749.6" + process $proc$libresoc.v:201741$13993 + assign { } { } + assign { } { } + assign $0\d_cr_delay$next[0:0]$13994 $1\d_cr_delay$next[0:0]$13995 + attribute \src "libresoc.v:201742.5-201742.29" + switch \initial + attribute \src "libresoc.v:201742.9-201742.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\d_cr_delay$next[0:0]$13995 1'0 + case + assign $1\d_cr_delay$next[0:0]$13995 \dbg_d_cr_req + end + sync always + update \d_cr_delay$next $0\d_cr_delay$next[0:0]$13994 + end + attribute \src "libresoc.v:201750.3-201759.6" + process $proc$libresoc.v:201750$13996 + assign { } { } + assign { } { } + assign $0\dbg_d_cr_data[63:0] $1\dbg_d_cr_data[63:0] + attribute \src "libresoc.v:201751.5-201751.29" + switch \initial + attribute \src "libresoc.v:201751.9-201751.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:455" + switch \d_cr_delay + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dbg_d_cr_data[63:0] \$184 + case + assign $1\dbg_d_cr_data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \dbg_d_cr_data $0\dbg_d_cr_data[63:0] + end + attribute \src "libresoc.v:201760.3-201769.6" + process $proc$libresoc.v:201760$13997 + assign { } { } + assign { } { } + assign $0\dbg_d_cr_ack[0:0] $1\dbg_d_cr_ack[0:0] + attribute \src "libresoc.v:201761.5-201761.29" + switch \initial + attribute \src "libresoc.v:201761.9-201761.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:455" + switch \d_cr_delay + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dbg_d_cr_ack[0:0] 1'1 + case + assign $1\dbg_d_cr_ack[0:0] 1'0 + end + sync always + update \dbg_d_cr_ack $0\dbg_d_cr_ack[0:0] + end + attribute \src "libresoc.v:201770.3-201779.6" + process $proc$libresoc.v:201770$13998 + assign { } { } + assign { } { } + assign $0\core_full_rd__ren[2:0] $1\core_full_rd__ren[2:0] + attribute \src "libresoc.v:201771.5-201771.29" + switch \initial + attribute \src "libresoc.v:201771.9-201771.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:461" + switch \dbg_d_xer_req + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\core_full_rd__ren[2:0] 3'111 + case + assign $1\core_full_rd__ren[2:0] 3'000 + end + sync always + update \core_full_rd__ren $0\core_full_rd__ren[2:0] + end + attribute \src "libresoc.v:201780.3-201788.6" + process $proc$libresoc.v:201780$13999 + assign { } { } + assign { } { } + assign $0\d_xer_delay$next[0:0]$14000 $1\d_xer_delay$next[0:0]$14001 + attribute \src "libresoc.v:201781.5-201781.29" + switch \initial + attribute \src "libresoc.v:201781.9-201781.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\d_xer_delay$next[0:0]$14001 1'0 + case + assign $1\d_xer_delay$next[0:0]$14001 \dbg_d_xer_req + end + sync always + update \d_xer_delay$next $0\d_xer_delay$next[0:0]$14000 + end + attribute \src "libresoc.v:201789.3-201798.6" + process $proc$libresoc.v:201789$14002 + assign { } { } + assign { } { } + assign $0\dbg_d_xer_data[63:0] $1\dbg_d_xer_data[63:0] + attribute \src "libresoc.v:201790.5-201790.29" + switch \initial + attribute \src "libresoc.v:201790.9-201790.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:465" + switch \d_xer_delay + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dbg_d_xer_data[63:0] \$186 + case + assign $1\dbg_d_xer_data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \dbg_d_xer_data $0\dbg_d_xer_data[63:0] + end + attribute \src "libresoc.v:201799.3-201808.6" + process $proc$libresoc.v:201799$14003 + assign { } { } + assign { } { } + assign $0\dbg_d_xer_ack[0:0] $1\dbg_d_xer_ack[0:0] + attribute \src "libresoc.v:201800.5-201800.29" + switch \initial + attribute \src "libresoc.v:201800.9-201800.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:465" + switch \d_xer_delay + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dbg_d_xer_ack[0:0] 1'1 + case + assign $1\dbg_d_xer_ack[0:0] 1'0 + end + sync always + update \dbg_d_xer_ack $0\dbg_d_xer_ack[0:0] + end + attribute \src "libresoc.v:201809.3-201823.6" + process $proc$libresoc.v:201809$14004 + assign { } { } + assign { } { } + assign $0\core_issue__addr[2:0] $1\core_issue__addr[2:0] + attribute \src "libresoc.v:201810.5-201810.29" + switch \initial + attribute \src "libresoc.v:201810.9-201810.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:492" + switch \fsm_state$188 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\core_issue__addr[2:0] 3'110 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\core_issue__addr[2:0] 3'111 + case + assign $1\core_issue__addr[2:0] 3'000 + end + sync always + update \core_issue__addr $0\core_issue__addr[2:0] + end + attribute \src "libresoc.v:201824.3-201838.6" + process $proc$libresoc.v:201824$14005 + assign { } { } + assign { } { } + assign $0\core_issue__ren[0:0] $1\core_issue__ren[0:0] + attribute \src "libresoc.v:201825.5-201825.29" + switch \initial + attribute \src "libresoc.v:201825.9-201825.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:492" + switch \fsm_state$188 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\core_issue__ren[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\core_issue__ren[0:0] 1'1 + case + assign $1\core_issue__ren[0:0] 1'0 + end + sync always + update \core_issue__ren $0\core_issue__ren[0:0] + end + attribute \src "libresoc.v:201839.3-201866.6" + process $proc$libresoc.v:201839$14006 + assign { } { } + assign { } { } + assign { } { } + assign $0\fsm_state$188$next[1:0]$14007 $2\fsm_state$188$next[1:0]$14009 + attribute \src "libresoc.v:201840.5-201840.29" + switch \initial + attribute \src "libresoc.v:201840.9-201840.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:492" + switch \fsm_state$188 + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\fsm_state$188$next[1:0]$14008 2'01 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\fsm_state$188$next[1:0]$14008 2'10 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\fsm_state$188$next[1:0]$14008 2'11 + attribute \src "libresoc.v:0.0-0.0" + case 2'11 + assign { } { } + assign $1\fsm_state$188$next[1:0]$14008 2'00 + case + assign $1\fsm_state$188$next[1:0]$14008 \fsm_state$188 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\fsm_state$188$next[1:0]$14009 2'00 + case + assign $2\fsm_state$188$next[1:0]$14009 $1\fsm_state$188$next[1:0]$14008 + end + sync always + update \fsm_state$188$next $0\fsm_state$188$next[1:0]$14007 + end + attribute \src "libresoc.v:201867.3-201877.6" + process $proc$libresoc.v:201867$14010 + assign { } { } + assign { } { } + assign $0\new_dec[63:0] $1\new_dec[63:0] + attribute \src "libresoc.v:201868.5-201868.29" + switch \initial + attribute \src "libresoc.v:201868.9-201868.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:492" + switch \fsm_state$188 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\new_dec[63:0] \$189 [63:0] + case + assign $1\new_dec[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \new_dec $0\new_dec[63:0] + end + attribute \src "libresoc.v:201878.3-201892.6" + process $proc$libresoc.v:201878$14011 + assign { } { } + assign { } { } + assign $0\core_issue__addr$13[2:0]$14012 $1\core_issue__addr$13[2:0]$14013 + attribute \src "libresoc.v:201879.5-201879.29" + switch \initial + attribute \src "libresoc.v:201879.9-201879.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:492" + switch \fsm_state$188 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\core_issue__addr$13[2:0]$14013 3'110 + attribute \src "libresoc.v:0.0-0.0" + case 2'11 + assign { } { } + assign $1\core_issue__addr$13[2:0]$14013 3'111 + case + assign $1\core_issue__addr$13[2:0]$14013 3'000 + end + sync always + update \core_issue__addr$13 $0\core_issue__addr$13[2:0]$14012 + end + attribute \src "libresoc.v:201893.3-201907.6" + process $proc$libresoc.v:201893$14014 + assign { } { } + assign { } { } + assign $0\core_issue__wen[0:0] $1\core_issue__wen[0:0] + attribute \src "libresoc.v:201894.5-201894.29" + switch \initial + attribute \src "libresoc.v:201894.9-201894.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:492" + switch \fsm_state$188 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\core_issue__wen[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case 2'11 + assign { } { } + assign $1\core_issue__wen[0:0] 1'1 + case + assign $1\core_issue__wen[0:0] 1'0 + end + sync always + update \core_issue__wen $0\core_issue__wen[0:0] + end + attribute \src "libresoc.v:201908.3-201922.6" + process $proc$libresoc.v:201908$14015 + assign { } { } + assign { } { } + assign $0\core_issue__data_i[63:0] $1\core_issue__data_i[63:0] + attribute \src "libresoc.v:201909.5-201909.29" + switch \initial + attribute \src "libresoc.v:201909.9-201909.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:492" + switch \fsm_state$188 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\core_issue__data_i[63:0] \new_dec + attribute \src "libresoc.v:0.0-0.0" + case 2'11 + assign { } { } + assign $1\core_issue__data_i[63:0] \new_tb + case + assign $1\core_issue__data_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \core_issue__data_i $0\core_issue__data_i[63:0] + end + attribute \src "libresoc.v:201923.3-201938.6" + process $proc$libresoc.v:201923$14016 + assign { } { } + assign { } { } + assign { } { } + assign $0\dec2_cur_dec$next[63:0]$14017 $2\dec2_cur_dec$next[63:0]$14019 + attribute \src "libresoc.v:201924.5-201924.29" + switch \initial + attribute \src "libresoc.v:201924.9-201924.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:492" + switch \fsm_state$188 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec2_cur_dec$next[63:0]$14018 \new_dec + case + assign $1\dec2_cur_dec$next[63:0]$14018 \dec2_cur_dec + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\dec2_cur_dec$next[63:0]$14019 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $2\dec2_cur_dec$next[63:0]$14019 $1\dec2_cur_dec$next[63:0]$14018 + end + sync always + update \dec2_cur_dec$next $0\dec2_cur_dec$next[63:0]$14017 + end + attribute \src "libresoc.v:201939.3-201949.6" + process $proc$libresoc.v:201939$14020 + assign { } { } + assign { } { } + assign $0\new_tb[63:0] $1\new_tb[63:0] + attribute \src "libresoc.v:201940.5-201940.29" + switch \initial + attribute \src "libresoc.v:201940.9-201940.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:492" + switch \fsm_state$188 + attribute \src "libresoc.v:0.0-0.0" + case 2'11 + assign { } { } + assign $1\new_tb[63:0] \$192 [63:0] + case + assign $1\new_tb[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \new_tb $0\new_tb[63:0] + end + attribute \src "libresoc.v:201950.3-201958.6" + process $proc$libresoc.v:201950$14021 + assign { } { } + assign { } { } + assign $0\dbg_dmi_we_i$next[0:0]$14022 $1\dbg_dmi_we_i$next[0:0]$14023 + attribute \src "libresoc.v:201951.5-201951.29" + switch \initial + attribute \src "libresoc.v:201951.9-201951.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dbg_dmi_we_i$next[0:0]$14023 1'0 + case + assign $1\dbg_dmi_we_i$next[0:0]$14023 \jtag_dmi0__we_i + end + sync always + update \dbg_dmi_we_i$next $0\dbg_dmi_we_i$next[0:0]$14022 + end + attribute \src "libresoc.v:201959.3-201967.6" + process $proc$libresoc.v:201959$14024 + assign { } { } + assign { } { } + assign $0\pc_ok_delay$next[0:0]$14025 $1\pc_ok_delay$next[0:0]$14026 + attribute \src "libresoc.v:201960.5-201960.29" + switch \initial + attribute \src "libresoc.v:201960.9-201960.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\pc_ok_delay$next[0:0]$14026 1'0 + case + assign $1\pc_ok_delay$next[0:0]$14026 \$38 + end + sync always + update \pc_ok_delay$next $0\pc_ok_delay$next[0:0]$14025 + end + attribute \src "libresoc.v:201968.3-201983.6" + process $proc$libresoc.v:201968$14027 + assign { } { } + assign { } { } + assign { } { } + assign $0\pc[63:0] $2\pc[63:0] + attribute \src "libresoc.v:201969.5-201969.29" + switch \initial + attribute \src "libresoc.v:201969.9-201969.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" + switch \pc_i_ok + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\pc[63:0] \pc_i + case + assign $1\pc[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:240" + switch \pc_ok_delay + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\pc[63:0] \core_cia__data_o + case + assign $2\pc[63:0] $1\pc[63:0] + end + sync always + update \pc $0\pc[63:0] + end + attribute \src "libresoc.v:201984.3-201996.6" + process $proc$libresoc.v:201984$14028 + assign { } { } + assign { } { } + assign $0\core_cia__ren[2:0] $1\core_cia__ren[2:0] + attribute \src "libresoc.v:201985.5-201985.29" + switch \initial + attribute \src "libresoc.v:201985.9-201985.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:233" + switch \pc_i_ok + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $1\core_cia__ren[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\core_cia__ren[2:0] 3'001 + end + sync always + update \core_cia__ren $0\core_cia__ren[2:0] + end + attribute \src "libresoc.v:201997.3-202017.6" + process $proc$libresoc.v:201997$14029 + assign { } { } + assign { } { } + assign $0\core_wen[2:0] $1\core_wen[2:0] + attribute \src "libresoc.v:201998.5-201998.29" + switch \initial + attribute \src "libresoc.v:201998.9-201998.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:375" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'11 + assign { } { } + assign $1\core_wen[2:0] $2\core_wen[2:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:413" + switch \$40 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\core_wen[2:0] $3\core_wen[2:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:417" + switch \$42 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\core_wen[2:0] 3'001 + case + assign $3\core_wen[2:0] 3'000 + end + case + assign $2\core_wen[2:0] 3'000 + end + case + assign $1\core_wen[2:0] 3'000 + end + sync always + update \core_wen $0\core_wen[2:0] + end + attribute \src "libresoc.v:202018.3-202038.6" + process $proc$libresoc.v:202018$14030 + assign { } { } + assign { } { } + assign $0\core_data_i[63:0] $1\core_data_i[63:0] + attribute \src "libresoc.v:202019.5-202019.29" + switch \initial + attribute \src "libresoc.v:202019.9-202019.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:375" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'11 + assign { } { } + assign $1\core_data_i[63:0] $2\core_data_i[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:413" + switch \$44 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\core_data_i[63:0] $3\core_data_i[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:417" + switch \$46 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\core_data_i[63:0] \nia + case + assign $3\core_data_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + case + assign $2\core_data_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + case + assign $1\core_data_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \core_data_i $0\core_data_i[63:0] + end + attribute \src "libresoc.v:202039.3-202059.6" + process $proc$libresoc.v:202039$14031 + assign { } { } + assign { } { } + assign $0\core_sv__ren[2:0] $1\core_sv__ren[2:0] + attribute \src "libresoc.v:202040.5-202040.29" + switch \initial + attribute \src "libresoc.v:202040.9-202040.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:290" + switch \fetch_fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\core_sv__ren[2:0] $2\core_sv__ren[2:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:294" + switch \$52 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\core_sv__ren[2:0] $3\core_sv__ren[2:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:296" + switch \fetch_pc_valid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\core_sv__ren[2:0] 3'100 + case + assign $3\core_sv__ren[2:0] 3'000 + end + case + assign $2\core_sv__ren[2:0] 3'000 + end + case + assign $1\core_sv__ren[2:0] 3'000 + end + sync always + update \core_sv__ren $0\core_sv__ren[2:0] + end + attribute \src "libresoc.v:202060.3-202080.6" + process $proc$libresoc.v:202060$14032 + assign { } { } + assign { } { } + assign $0\core_msr__ren[2:0] $1\core_msr__ren[2:0] + attribute \src "libresoc.v:202061.5-202061.29" + switch \initial + attribute \src "libresoc.v:202061.9-202061.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:290" + switch \fetch_fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\core_msr__ren[2:0] $2\core_msr__ren[2:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:294" + switch \$58 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\core_msr__ren[2:0] $3\core_msr__ren[2:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:296" + switch \fetch_pc_valid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\core_msr__ren[2:0] 3'010 + case + assign $3\core_msr__ren[2:0] 3'000 + end + case + assign $2\core_msr__ren[2:0] 3'000 + end + case + assign $1\core_msr__ren[2:0] 3'000 + end + sync always + update \core_msr__ren $0\core_msr__ren[2:0] + end + attribute \src "libresoc.v:202081.3-202089.6" + process $proc$libresoc.v:202081$14033 + assign { } { } + assign { } { } + assign $0\dbg_dmi_din$next[63:0]$14034 $1\dbg_dmi_din$next[63:0]$14035 + attribute \src "libresoc.v:202082.5-202082.29" + switch \initial + attribute \src "libresoc.v:202082.9-202082.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dbg_dmi_din$next[63:0]$14035 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $1\dbg_dmi_din$next[63:0]$14035 \jtag_dmi0__din + end + sync always + update \dbg_dmi_din$next $0\dbg_dmi_din$next[63:0]$14034 + end + attribute \src "libresoc.v:202090.3-202105.6" + process $proc$libresoc.v:202090$14036 + assign { } { } + assign { } { } + assign $0\fetch_pc_ready_o[0:0] $1\fetch_pc_ready_o[0:0] + attribute \src "libresoc.v:202091.5-202091.29" + switch \initial + attribute \src "libresoc.v:202091.9-202091.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:290" + switch \fetch_fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\fetch_pc_ready_o[0:0] $2\fetch_pc_ready_o[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:294" + switch \$64 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\fetch_pc_ready_o[0:0] 1'1 + case + assign $2\fetch_pc_ready_o[0:0] 1'0 + end + case + assign $1\fetch_pc_ready_o[0:0] 1'0 + end + sync always + update \fetch_pc_ready_o $0\fetch_pc_ready_o[0:0] + end + attribute \src "libresoc.v:202106.3-202146.6" + process $proc$libresoc.v:202106$14037 + assign { } { } + assign { } { } + assign $0\imem_a_pc_i[47:0] $1\imem_a_pc_i[47:0] + attribute \src "libresoc.v:202107.5-202107.29" + switch \initial + attribute \src "libresoc.v:202107.9-202107.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:290" + switch \fetch_fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\imem_a_pc_i[47:0] $2\imem_a_pc_i[47:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:294" + switch \$70 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\imem_a_pc_i[47:0] $3\imem_a_pc_i[47:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:296" + switch \fetch_pc_valid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\imem_a_pc_i[47:0] \pc [47:0] + case + assign $3\imem_a_pc_i[47:0] 48'000000000000000000000000000000000000000000000000 + end + case + assign $2\imem_a_pc_i[47:0] 48'000000000000000000000000000000000000000000000000 + end + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\imem_a_pc_i[47:0] $4\imem_a_pc_i[47:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:326" + switch \imem_f_busy_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $4\imem_a_pc_i[47:0] 48'000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $4\imem_a_pc_i[47:0] $5\imem_a_pc_i[47:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:341" + switch \$72 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $5\imem_a_pc_i[47:0] 48'000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $5\imem_a_pc_i[47:0] \$74 [47:0] + end + end + case + assign $1\imem_a_pc_i[47:0] 48'000000000000000000000000000000000000000000000000 + end + sync always + update \imem_a_pc_i $0\imem_a_pc_i[47:0] + end + attribute \src "libresoc.v:202147.3-202196.6" + process $proc$libresoc.v:202147$14038 + assign { } { } + assign { } { } + assign $0\imem_a_valid_i[0:0] $1\imem_a_valid_i[0:0] + attribute \src "libresoc.v:202148.5-202148.29" + switch \initial + attribute \src "libresoc.v:202148.9-202148.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:290" + switch \fetch_fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\imem_a_valid_i[0:0] $2\imem_a_valid_i[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:294" + switch \$81 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\imem_a_valid_i[0:0] $3\imem_a_valid_i[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:296" + switch \fetch_pc_valid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\imem_a_valid_i[0:0] 1'1 + case + assign $3\imem_a_valid_i[0:0] 1'0 + end + case + assign $2\imem_a_valid_i[0:0] 1'0 + end + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\imem_a_valid_i[0:0] $4\imem_a_valid_i[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:326" + switch \imem_f_busy_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\imem_a_valid_i[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $4\imem_a_valid_i[0:0] $5\imem_a_valid_i[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:341" + switch \$83 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $5\imem_a_valid_i[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $5\imem_a_valid_i[0:0] 1'1 + end + end + attribute \src "libresoc.v:0.0-0.0" + case 2'11 + assign { } { } + assign $1\imem_a_valid_i[0:0] $6\imem_a_valid_i[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:354" + switch \imem_f_busy_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\imem_a_valid_i[0:0] 1'1 + case + assign $6\imem_a_valid_i[0:0] 1'0 + end + case + assign $1\imem_a_valid_i[0:0] 1'0 + end + sync always + update \imem_a_valid_i $0\imem_a_valid_i[0:0] + end + attribute \src "libresoc.v:202197.3-202246.6" + process $proc$libresoc.v:202197$14039 + assign { } { } + assign { } { } + assign $0\imem_f_valid_i[0:0] $1\imem_f_valid_i[0:0] + attribute \src "libresoc.v:202198.5-202198.29" + switch \initial + attribute \src "libresoc.v:202198.9-202198.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:290" + switch \fetch_fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\imem_f_valid_i[0:0] $2\imem_f_valid_i[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:294" + switch \$89 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\imem_f_valid_i[0:0] $3\imem_f_valid_i[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:296" + switch \fetch_pc_valid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\imem_f_valid_i[0:0] 1'1 + case + assign $3\imem_f_valid_i[0:0] 1'0 + end + case + assign $2\imem_f_valid_i[0:0] 1'0 + end + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\imem_f_valid_i[0:0] $4\imem_f_valid_i[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:326" + switch \imem_f_busy_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\imem_f_valid_i[0:0] 1'1 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $4\imem_f_valid_i[0:0] $5\imem_f_valid_i[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:341" + switch \$91 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $5\imem_f_valid_i[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $5\imem_f_valid_i[0:0] 1'1 + end + end + attribute \src "libresoc.v:0.0-0.0" + case 2'11 + assign { } { } + assign $1\imem_f_valid_i[0:0] $6\imem_f_valid_i[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:354" + switch \imem_f_busy_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\imem_f_valid_i[0:0] 1'1 + case + assign $6\imem_f_valid_i[0:0] 1'0 + end + case + assign $1\imem_f_valid_i[0:0] 1'0 + end + sync always + update \imem_f_valid_i $0\imem_f_valid_i[0:0] + end + attribute \src "libresoc.v:202247.3-202272.6" + process $proc$libresoc.v:202247$14040 + assign { } { } + assign { } { } + assign { } { } + assign $0\dec2_cur_pc$next[63:0]$14041 $4\dec2_cur_pc$next[63:0]$14045 + attribute \src "libresoc.v:202248.5-202248.29" + switch \initial + attribute \src "libresoc.v:202248.9-202248.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:290" + switch \fetch_fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec2_cur_pc$next[63:0]$14042 $2\dec2_cur_pc$next[63:0]$14043 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:294" + switch \$97 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\dec2_cur_pc$next[63:0]$14043 $3\dec2_cur_pc$next[63:0]$14044 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:296" + switch \fetch_pc_valid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\dec2_cur_pc$next[63:0]$14044 \pc + case + assign $3\dec2_cur_pc$next[63:0]$14044 \dec2_cur_pc + end + case + assign $2\dec2_cur_pc$next[63:0]$14043 \dec2_cur_pc + end + case + assign $1\dec2_cur_pc$next[63:0]$14042 \dec2_cur_pc + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\dec2_cur_pc$next[63:0]$14045 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $4\dec2_cur_pc$next[63:0]$14045 $1\dec2_cur_pc$next[63:0]$14042 + end + sync always + update \dec2_cur_pc$next $0\dec2_cur_pc$next[63:0]$14041 + end + attribute \src "libresoc.v:202273.3-202307.6" + process $proc$libresoc.v:202273$14046 + assign { } { } + assign { } { } + assign { } { } + assign $0\msr_read$next[0:0]$14047 $5\msr_read$next[0:0]$14052 + attribute \src "libresoc.v:202274.5-202274.29" + switch \initial + attribute \src "libresoc.v:202274.9-202274.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:290" + switch \fetch_fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\msr_read$next[0:0]$14048 $2\msr_read$next[0:0]$14049 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:294" + switch \$103 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\msr_read$next[0:0]$14049 $3\msr_read$next[0:0]$14050 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:296" + switch \fetch_pc_valid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\msr_read$next[0:0]$14050 1'0 + case + assign $3\msr_read$next[0:0]$14050 \msr_read + end + case + assign $2\msr_read$next[0:0]$14049 \msr_read + end + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\msr_read$next[0:0]$14048 $4\msr_read$next[0:0]$14051 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:320" + switch \$105 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\msr_read$next[0:0]$14051 1'1 + case + assign $4\msr_read$next[0:0]$14051 \msr_read + end + case + assign $1\msr_read$next[0:0]$14048 \msr_read + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\msr_read$next[0:0]$14052 1'1 + case + assign $5\msr_read$next[0:0]$14052 $1\msr_read$next[0:0]$14048 + end + sync always + update \msr_read$next $0\msr_read$next[0:0]$14047 + end + attribute \src "libresoc.v:202308.3-202342.6" + process $proc$libresoc.v:202308$14053 + assign { } { } + assign { } { } + assign { } { } + assign $0\sv_read$next[0:0]$14054 $5\sv_read$next[0:0]$14059 + attribute \src "libresoc.v:202309.5-202309.29" + switch \initial + attribute \src "libresoc.v:202309.9-202309.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:290" + switch \fetch_fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\sv_read$next[0:0]$14055 $2\sv_read$next[0:0]$14056 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:294" + switch \$111 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\sv_read$next[0:0]$14056 $3\sv_read$next[0:0]$14057 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:296" + switch \fetch_pc_valid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\sv_read$next[0:0]$14057 1'0 + case + assign $3\sv_read$next[0:0]$14057 \sv_read + end + case + assign $2\sv_read$next[0:0]$14056 \sv_read + end + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\sv_read$next[0:0]$14055 $4\sv_read$next[0:0]$14058 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:323" + switch \$113 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\sv_read$next[0:0]$14058 1'1 + case + assign $4\sv_read$next[0:0]$14058 \sv_read + end + case + assign $1\sv_read$next[0:0]$14055 \sv_read + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\sv_read$next[0:0]$14059 1'1 + case + assign $5\sv_read$next[0:0]$14059 $1\sv_read$next[0:0]$14055 + end + sync always + update \sv_read$next $0\sv_read$next[0:0]$14054 + end + attribute \src "libresoc.v:202343.3-202409.6" + process $proc$libresoc.v:202343$14060 + assign { } { } + assign { } { } + assign { } { } + assign $0\fetch_fsm_state$next[1:0]$14061 $8\fetch_fsm_state$next[1:0]$14069 + attribute \src "libresoc.v:202344.5-202344.29" + switch \initial + attribute \src "libresoc.v:202344.9-202344.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:290" + switch \fetch_fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\fetch_fsm_state$next[1:0]$14062 $2\fetch_fsm_state$next[1:0]$14063 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:294" + switch \$119 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\fetch_fsm_state$next[1:0]$14063 $3\fetch_fsm_state$next[1:0]$14064 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:296" + switch \fetch_pc_valid_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fetch_fsm_state$next[1:0]$14064 2'01 + case + assign $3\fetch_fsm_state$next[1:0]$14064 \fetch_fsm_state + end + case + assign $2\fetch_fsm_state$next[1:0]$14063 \fetch_fsm_state + end + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\fetch_fsm_state$next[1:0]$14062 $4\fetch_fsm_state$next[1:0]$14065 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:326" + switch \imem_f_busy_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $4\fetch_fsm_state$next[1:0]$14065 \fetch_fsm_state + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $4\fetch_fsm_state$next[1:0]$14065 $5\fetch_fsm_state$next[1:0]$14066 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:341" + switch \$121 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\fetch_fsm_state$next[1:0]$14066 2'10 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $5\fetch_fsm_state$next[1:0]$14066 2'11 + end + end + attribute \src "libresoc.v:0.0-0.0" + case 2'11 + assign { } { } + assign $1\fetch_fsm_state$next[1:0]$14062 $6\fetch_fsm_state$next[1:0]$14067 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:354" + switch \imem_f_busy_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $6\fetch_fsm_state$next[1:0]$14067 \fetch_fsm_state + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $6\fetch_fsm_state$next[1:0]$14067 2'10 + end + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\fetch_fsm_state$next[1:0]$14062 $7\fetch_fsm_state$next[1:0]$14068 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:367" + switch \fetch_insn_ready_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\fetch_fsm_state$next[1:0]$14068 2'00 + case + assign $7\fetch_fsm_state$next[1:0]$14068 \fetch_fsm_state + end + case + assign $1\fetch_fsm_state$next[1:0]$14062 \fetch_fsm_state + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $8\fetch_fsm_state$next[1:0]$14069 2'00 + case + assign $8\fetch_fsm_state$next[1:0]$14069 $1\fetch_fsm_state$next[1:0]$14062 + end + sync always + update \fetch_fsm_state$next $0\fetch_fsm_state$next[1:0]$14061 + end + attribute \src "libresoc.v:202410.3-202428.6" + process $proc$libresoc.v:202410$14070 + assign { } { } + assign { } { } + assign $0\core_stopped_i[0:0] $1\core_stopped_i[0:0] + attribute \src "libresoc.v:202411.5-202411.29" + switch \initial + attribute \src "libresoc.v:202411.9-202411.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:290" + switch \fetch_fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\core_stopped_i[0:0] $2\core_stopped_i[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:294" + switch \$127 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $2\core_stopped_i[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\core_stopped_i[0:0] 1'1 + end + case + assign $1\core_stopped_i[0:0] 1'0 + end + sync always + update \core_stopped_i $0\core_stopped_i[0:0] + end + attribute \src "libresoc.v:202429.3-202447.6" + process $proc$libresoc.v:202429$14071 + assign { } { } + assign { } { } + assign $0\dbg_core_stopped_i[0:0] $1\dbg_core_stopped_i[0:0] + attribute \src "libresoc.v:202430.5-202430.29" + switch \initial + attribute \src "libresoc.v:202430.9-202430.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:290" + switch \fetch_fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dbg_core_stopped_i[0:0] $2\dbg_core_stopped_i[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:294" + switch \$133 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $2\dbg_core_stopped_i[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\dbg_core_stopped_i[0:0] 1'1 + end + case + assign $1\dbg_core_stopped_i[0:0] 1'0 + end + sync always + update \dbg_core_stopped_i $0\dbg_core_stopped_i[0:0] + end + attribute \src "libresoc.v:202448.3-202456.6" + process $proc$libresoc.v:202448$14072 + assign { } { } + assign { } { } + assign $0\jtag_dmi0__ack_o$next[0:0]$14073 $1\jtag_dmi0__ack_o$next[0:0]$14074 + attribute \src "libresoc.v:202449.5-202449.29" + switch \initial + attribute \src "libresoc.v:202449.9-202449.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\jtag_dmi0__ack_o$next[0:0]$14074 1'0 + case + assign $1\jtag_dmi0__ack_o$next[0:0]$14074 \dbg_dmi_ack_o + end + sync always + update \jtag_dmi0__ack_o$next $0\jtag_dmi0__ack_o$next[0:0]$14073 + end + attribute \src "libresoc.v:202457.3-202477.6" + process $proc$libresoc.v:202457$14075 + assign { } { } + assign { } { } + assign { } { } + assign $0\dec2_cur_msr$next[63:0]$14076 $3\dec2_cur_msr$next[63:0]$14079 + attribute \src "libresoc.v:202458.5-202458.29" + switch \initial + attribute \src "libresoc.v:202458.9-202458.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:290" + switch \fetch_fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec2_cur_msr$next[63:0]$14077 $2\dec2_cur_msr$next[63:0]$14078 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:320" + switch \$135 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\dec2_cur_msr$next[63:0]$14078 \core_msr__data_o + case + assign $2\dec2_cur_msr$next[63:0]$14078 \dec2_cur_msr + end + case + assign $1\dec2_cur_msr$next[63:0]$14077 \dec2_cur_msr + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\dec2_cur_msr$next[63:0]$14079 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $3\dec2_cur_msr$next[63:0]$14079 $1\dec2_cur_msr$next[63:0]$14077 + end + sync always + update \dec2_cur_msr$next $0\dec2_cur_msr$next[63:0]$14076 + end + attribute \src "libresoc.v:202478.3-202510.6" + process $proc$libresoc.v:202478$14080 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\cur_cur_dststep$next[6:0]$14081 $3\cur_cur_dststep$next[6:0]$14099 + assign $0\cur_cur_maxvl$next[6:0]$14082 $3\cur_cur_maxvl$next[6:0]$14100 + assign $0\cur_cur_subvl$next[1:0]$14083 $3\cur_cur_subvl$next[1:0]$14101 + assign $0\cur_cur_svstep$next[1:0]$14084 $3\cur_cur_svstep$next[1:0]$14102 + assign $0\cur_cur_vl$next[6:0]$14085 $3\cur_cur_vl$next[6:0]$14103 + assign $0\dec2_cur_cur_srcstep$next[6:0]$14086 $3\dec2_cur_cur_srcstep$next[6:0]$14104 + attribute \src "libresoc.v:202479.5-202479.29" + switch \initial + attribute \src "libresoc.v:202479.9-202479.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:290" + switch \fetch_fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\cur_cur_dststep$next[6:0]$14087 $2\cur_cur_dststep$next[6:0]$14093 + assign $1\cur_cur_maxvl$next[6:0]$14088 $2\cur_cur_maxvl$next[6:0]$14094 + assign $1\cur_cur_subvl$next[1:0]$14089 $2\cur_cur_subvl$next[1:0]$14095 + assign $1\cur_cur_svstep$next[1:0]$14090 $2\cur_cur_svstep$next[1:0]$14096 + assign $1\cur_cur_vl$next[6:0]$14091 $2\cur_cur_vl$next[6:0]$14097 + assign $1\dec2_cur_cur_srcstep$next[6:0]$14092 $2\dec2_cur_cur_srcstep$next[6:0]$14098 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:323" + switch \$137 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $2\cur_cur_maxvl$next[6:0]$14094 $2\cur_cur_vl$next[6:0]$14097 $2\dec2_cur_cur_srcstep$next[6:0]$14098 $2\cur_cur_dststep$next[6:0]$14093 $2\cur_cur_subvl$next[1:0]$14095 $2\cur_cur_svstep$next[1:0]$14096 } \core_sv__data_o [31:0] + case + assign $2\cur_cur_dststep$next[6:0]$14093 \cur_cur_dststep + assign $2\cur_cur_maxvl$next[6:0]$14094 \cur_cur_maxvl + assign $2\cur_cur_subvl$next[1:0]$14095 \cur_cur_subvl + assign $2\cur_cur_svstep$next[1:0]$14096 \cur_cur_svstep + assign $2\cur_cur_vl$next[6:0]$14097 \cur_cur_vl + assign $2\dec2_cur_cur_srcstep$next[6:0]$14098 \dec2_cur_cur_srcstep + end + case + assign $1\cur_cur_dststep$next[6:0]$14087 \cur_cur_dststep + assign $1\cur_cur_maxvl$next[6:0]$14088 \cur_cur_maxvl + assign $1\cur_cur_subvl$next[1:0]$14089 \cur_cur_subvl + assign $1\cur_cur_svstep$next[1:0]$14090 \cur_cur_svstep + assign $1\cur_cur_vl$next[6:0]$14091 \cur_cur_vl + assign $1\dec2_cur_cur_srcstep$next[6:0]$14092 \dec2_cur_cur_srcstep + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $3\cur_cur_svstep$next[1:0]$14102 2'00 + assign $3\cur_cur_subvl$next[1:0]$14101 2'00 + assign $3\cur_cur_dststep$next[6:0]$14099 7'0000000 + assign $3\dec2_cur_cur_srcstep$next[6:0]$14104 7'0000000 + assign $3\cur_cur_vl$next[6:0]$14103 7'0000000 + assign $3\cur_cur_maxvl$next[6:0]$14100 7'0000000 + case + assign $3\cur_cur_dststep$next[6:0]$14099 $1\cur_cur_dststep$next[6:0]$14087 + assign $3\cur_cur_maxvl$next[6:0]$14100 $1\cur_cur_maxvl$next[6:0]$14088 + assign $3\cur_cur_subvl$next[1:0]$14101 $1\cur_cur_subvl$next[1:0]$14089 + assign $3\cur_cur_svstep$next[1:0]$14102 $1\cur_cur_svstep$next[1:0]$14090 + assign $3\cur_cur_vl$next[6:0]$14103 $1\cur_cur_vl$next[6:0]$14091 + assign $3\dec2_cur_cur_srcstep$next[6:0]$14104 $1\dec2_cur_cur_srcstep$next[6:0]$14092 + end + sync always + update \cur_cur_dststep$next $0\cur_cur_dststep$next[6:0]$14081 + update \cur_cur_maxvl$next $0\cur_cur_maxvl$next[6:0]$14082 + update \cur_cur_subvl$next $0\cur_cur_subvl$next[1:0]$14083 + update \cur_cur_svstep$next $0\cur_cur_svstep$next[1:0]$14084 + update \cur_cur_vl$next $0\cur_cur_vl$next[6:0]$14085 + update \dec2_cur_cur_srcstep$next $0\dec2_cur_cur_srcstep$next[6:0]$14086 + end + attribute \src "libresoc.v:202511.3-202529.6" + process $proc$libresoc.v:202511$14105 + assign { } { } + assign { } { } + assign $0\svp64_raw_opcode_in[31:0] $1\svp64_raw_opcode_in[31:0] + attribute \src "libresoc.v:202512.5-202512.29" + switch \initial + attribute \src "libresoc.v:202512.9-202512.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:290" + switch \fetch_fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\svp64_raw_opcode_in[31:0] $2\svp64_raw_opcode_in[31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:326" + switch \imem_f_busy_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $2\svp64_raw_opcode_in[31:0] 0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\svp64_raw_opcode_in[31:0] \$139 + end + case + assign $1\svp64_raw_opcode_in[31:0] 0 + end + sync always + update \svp64_raw_opcode_in $0\svp64_raw_opcode_in[31:0] + end + attribute \src "libresoc.v:202530.3-202548.6" + process $proc$libresoc.v:202530$14106 + assign { } { } + assign { } { } + assign $0\svp64_bigendian[0:0] $1\svp64_bigendian[0:0] + attribute \src "libresoc.v:202531.5-202531.29" + switch \initial + attribute \src "libresoc.v:202531.9-202531.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:290" + switch \fetch_fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\svp64_bigendian[0:0] $2\svp64_bigendian[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:326" + switch \imem_f_busy_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $2\svp64_bigendian[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\svp64_bigendian[0:0] \core_bigendian_i + end + case + assign $1\svp64_bigendian[0:0] 1'0 + end + sync always + update \svp64_bigendian $0\svp64_bigendian[0:0] + end + attribute \src "libresoc.v:202549.3-202586.6" + process $proc$libresoc.v:202549$14107 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\dec2_dec_svp64__extra$next[8:0]$14108 $3\dec2_dec_svp64__extra$next[8:0]$14129 + assign $0\dec_svp64__elwidth$next[1:0]$14109 $3\dec_svp64__elwidth$next[1:0]$14130 + assign $0\dec_svp64__ewsrc$next[1:0]$14110 $3\dec_svp64__ewsrc$next[1:0]$14131 + assign $0\dec_svp64__mask$next[2:0]$14111 $3\dec_svp64__mask$next[2:0]$14132 + assign $0\dec_svp64__mmode$next[0:0]$14112 $3\dec_svp64__mmode$next[0:0]$14133 + assign $0\dec_svp64__mode$next[4:0]$14113 $3\dec_svp64__mode$next[4:0]$14134 + assign $0\dec_svp64__subvl$next[1:0]$14114 $3\dec_svp64__subvl$next[1:0]$14135 + attribute \src "libresoc.v:202550.5-202550.29" + switch \initial + attribute \src "libresoc.v:202550.9-202550.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:290" + switch \fetch_fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\dec2_dec_svp64__extra$next[8:0]$14115 $2\dec2_dec_svp64__extra$next[8:0]$14122 + assign $1\dec_svp64__elwidth$next[1:0]$14116 $2\dec_svp64__elwidth$next[1:0]$14123 + assign $1\dec_svp64__ewsrc$next[1:0]$14117 $2\dec_svp64__ewsrc$next[1:0]$14124 + assign $1\dec_svp64__mask$next[2:0]$14118 $2\dec_svp64__mask$next[2:0]$14125 + assign $1\dec_svp64__mmode$next[0:0]$14119 $2\dec_svp64__mmode$next[0:0]$14126 + assign $1\dec_svp64__mode$next[4:0]$14120 $2\dec_svp64__mode$next[4:0]$14127 + assign $1\dec_svp64__subvl$next[1:0]$14121 $2\dec_svp64__subvl$next[1:0]$14128 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:326" + switch \imem_f_busy_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $2\dec2_dec_svp64__extra$next[8:0]$14122 \dec2_dec_svp64__extra + assign $2\dec_svp64__elwidth$next[1:0]$14123 \dec_svp64__elwidth + assign $2\dec_svp64__ewsrc$next[1:0]$14124 \dec_svp64__ewsrc + assign $2\dec_svp64__mask$next[2:0]$14125 \dec_svp64__mask + assign $2\dec_svp64__mmode$next[0:0]$14126 \dec_svp64__mmode + assign $2\dec_svp64__mode$next[4:0]$14127 \dec_svp64__mode + assign $2\dec_svp64__subvl$next[1:0]$14128 \dec_svp64__subvl + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $2\dec_svp64__mmode$next[0:0]$14126 $2\dec_svp64__mask$next[2:0]$14125 $2\dec_svp64__elwidth$next[1:0]$14123 $2\dec_svp64__ewsrc$next[1:0]$14124 $2\dec_svp64__subvl$next[1:0]$14128 $2\dec2_dec_svp64__extra$next[8:0]$14122 $2\dec_svp64__mode$next[4:0]$14127 } \svp64_svp64_rm + end + case + assign $1\dec2_dec_svp64__extra$next[8:0]$14115 \dec2_dec_svp64__extra + assign $1\dec_svp64__elwidth$next[1:0]$14116 \dec_svp64__elwidth + assign $1\dec_svp64__ewsrc$next[1:0]$14117 \dec_svp64__ewsrc + assign $1\dec_svp64__mask$next[2:0]$14118 \dec_svp64__mask + assign $1\dec_svp64__mmode$next[0:0]$14119 \dec_svp64__mmode + assign $1\dec_svp64__mode$next[4:0]$14120 \dec_svp64__mode + assign $1\dec_svp64__subvl$next[1:0]$14121 \dec_svp64__subvl + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $3\dec_svp64__mode$next[4:0]$14134 5'00000 + assign $3\dec2_dec_svp64__extra$next[8:0]$14129 9'000000000 + assign $3\dec_svp64__subvl$next[1:0]$14135 2'00 + assign $3\dec_svp64__ewsrc$next[1:0]$14131 2'00 + assign $3\dec_svp64__elwidth$next[1:0]$14130 2'00 + assign $3\dec_svp64__mask$next[2:0]$14132 3'000 + assign $3\dec_svp64__mmode$next[0:0]$14133 1'0 + case + assign $3\dec2_dec_svp64__extra$next[8:0]$14129 $1\dec2_dec_svp64__extra$next[8:0]$14115 + assign $3\dec_svp64__elwidth$next[1:0]$14130 $1\dec_svp64__elwidth$next[1:0]$14116 + assign $3\dec_svp64__ewsrc$next[1:0]$14131 $1\dec_svp64__ewsrc$next[1:0]$14117 + assign $3\dec_svp64__mask$next[2:0]$14132 $1\dec_svp64__mask$next[2:0]$14118 + assign $3\dec_svp64__mmode$next[0:0]$14133 $1\dec_svp64__mmode$next[0:0]$14119 + assign $3\dec_svp64__mode$next[4:0]$14134 $1\dec_svp64__mode$next[4:0]$14120 + assign $3\dec_svp64__subvl$next[1:0]$14135 $1\dec_svp64__subvl$next[1:0]$14121 + end + sync always + update \dec2_dec_svp64__extra$next $0\dec2_dec_svp64__extra$next[8:0]$14108 + update \dec_svp64__elwidth$next $0\dec_svp64__elwidth$next[1:0]$14109 + update \dec_svp64__ewsrc$next $0\dec_svp64__ewsrc$next[1:0]$14110 + update \dec_svp64__mask$next $0\dec_svp64__mask$next[2:0]$14111 + update \dec_svp64__mmode$next $0\dec_svp64__mmode$next[0:0]$14112 + update \dec_svp64__mode$next $0\dec_svp64__mode$next[4:0]$14113 + update \dec_svp64__subvl$next $0\dec_svp64__subvl$next[1:0]$14114 + end + attribute \src "libresoc.v:202587.3-202595.6" + process $proc$libresoc.v:202587$14136 + assign { } { } + assign { } { } + assign $0\jtag_dmi0__dout$next[63:0]$14137 $1\jtag_dmi0__dout$next[63:0]$14138 + attribute \src "libresoc.v:202588.5-202588.29" + switch \initial + attribute \src "libresoc.v:202588.9-202588.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\jtag_dmi0__dout$next[63:0]$14138 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $1\jtag_dmi0__dout$next[63:0]$14138 \dbg_dmi_dout + end + sync always + update \jtag_dmi0__dout$next $0\jtag_dmi0__dout$next[63:0]$14137 + end + attribute \src "libresoc.v:202596.3-202614.6" + process $proc$libresoc.v:202596$14139 + assign { } { } + assign { } { } + assign $0\nia$next[63:0]$14140 $1\nia$next[63:0]$14141 + attribute \src "libresoc.v:202597.5-202597.29" + switch \initial + attribute \src "libresoc.v:202597.9-202597.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:290" + switch \fetch_fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\nia$next[63:0]$14141 $2\nia$next[63:0]$14142 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:326" + switch \imem_f_busy_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $2\nia$next[63:0]$14142 \nia + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\nia$next[63:0]$14142 \$143 [63:0] + end + case + assign $1\nia$next[63:0]$14141 \nia + end + sync always + update \nia$next $0\nia$next[63:0]$14140 + end + attribute \src "libresoc.v:202615.3-202650.6" + process $proc$libresoc.v:202615$14143 + assign { } { } + assign { } { } + assign $0\fetch_insn_o$next[31:0]$14144 $1\fetch_insn_o$next[31:0]$14145 + attribute \src "libresoc.v:202616.5-202616.29" + switch \initial + attribute \src "libresoc.v:202616.9-202616.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:290" + switch \fetch_fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\fetch_insn_o$next[31:0]$14145 $2\fetch_insn_o$next[31:0]$14146 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:326" + switch \imem_f_busy_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $2\fetch_insn_o$next[31:0]$14146 \fetch_insn_o + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\fetch_insn_o$next[31:0]$14146 $3\fetch_insn_o$next[31:0]$14147 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:341" + switch \$148 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fetch_insn_o$next[31:0]$14147 \$150 + case + assign $3\fetch_insn_o$next[31:0]$14147 \fetch_insn_o + end + end + attribute \src "libresoc.v:0.0-0.0" + case 2'11 + assign { } { } + assign $1\fetch_insn_o$next[31:0]$14145 $4\fetch_insn_o$next[31:0]$14148 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:354" + switch \imem_f_busy_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $4\fetch_insn_o$next[31:0]$14148 \fetch_insn_o + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $4\fetch_insn_o$next[31:0]$14148 \$154 + end + case + assign $1\fetch_insn_o$next[31:0]$14145 \fetch_insn_o + end + sync always + update \fetch_insn_o$next $0\fetch_insn_o$next[31:0]$14144 + end + attribute \src "libresoc.v:202651.3-202661.6" + process $proc$libresoc.v:202651$14149 + assign { } { } + assign { } { } + assign $0\fetch_insn_valid_o[0:0] $1\fetch_insn_valid_o[0:0] + attribute \src "libresoc.v:202652.5-202652.29" + switch \initial + attribute \src "libresoc.v:202652.9-202652.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:290" + switch \fetch_fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\fetch_insn_valid_o[0:0] 1'1 + case + assign $1\fetch_insn_valid_o[0:0] 1'0 + end + sync always + update \fetch_insn_valid_o $0\fetch_insn_valid_o[0:0] + end + attribute \src "libresoc.v:202662.3-202672.6" + process $proc$libresoc.v:202662$14150 + assign { } { } + assign { } { } + assign $0\fetch_pc_valid_i[0:0] $1\fetch_pc_valid_i[0:0] + attribute \src "libresoc.v:202663.5-202663.29" + switch \initial + attribute \src "libresoc.v:202663.9-202663.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:375" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\fetch_pc_valid_i[0:0] 1'1 + case + assign $1\fetch_pc_valid_i[0:0] 1'0 + end + sync always + update \fetch_pc_valid_i $0\fetch_pc_valid_i[0:0] + end + attribute \src "libresoc.v:202673.3-202715.6" + process $proc$libresoc.v:202673$14151 + assign { } { } + assign { } { } + assign { } { } + assign $0\fsm_state$next[1:0]$14152 $5\fsm_state$next[1:0]$14157 + attribute \src "libresoc.v:202674.5-202674.29" + switch \initial + attribute \src "libresoc.v:202674.9-202674.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:375" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\fsm_state$next[1:0]$14153 $2\fsm_state$next[1:0]$14154 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:382" + switch \fetch_pc_ready_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\fsm_state$next[1:0]$14154 2'01 + case + assign $2\fsm_state$next[1:0]$14154 \fsm_state + end + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\fsm_state$next[1:0]$14153 $3\fsm_state$next[1:0]$14155 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:388" + switch \fetch_insn_valid_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fsm_state$next[1:0]$14155 2'10 + case + assign $3\fsm_state$next[1:0]$14155 \fsm_state + end + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\fsm_state$next[1:0]$14153 2'11 + attribute \src "libresoc.v:0.0-0.0" + case 2'11 + assign { } { } + assign $1\fsm_state$next[1:0]$14153 $4\fsm_state$next[1:0]$14156 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:413" + switch \$161 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\fsm_state$next[1:0]$14156 2'00 + case + assign $4\fsm_state$next[1:0]$14156 \fsm_state + end + case + assign $1\fsm_state$next[1:0]$14153 \fsm_state + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\fsm_state$next[1:0]$14157 2'00 + case + assign $5\fsm_state$next[1:0]$14157 $1\fsm_state$next[1:0]$14153 + end + sync always + update \fsm_state$next $0\fsm_state$next[1:0]$14152 + end + attribute \src "libresoc.v:202716.3-202726.6" + process $proc$libresoc.v:202716$14158 + assign { } { } + assign { } { } + assign $0\fetch_insn_ready_i[0:0] $1\fetch_insn_ready_i[0:0] + attribute \src "libresoc.v:202717.5-202717.29" + switch \initial + attribute \src "libresoc.v:202717.9-202717.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:375" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\fetch_insn_ready_i[0:0] 1'1 + case + assign $1\fetch_insn_ready_i[0:0] 1'0 + end + sync always + update \fetch_insn_ready_i $0\fetch_insn_ready_i[0:0] + end + attribute \src "libresoc.v:202727.3-202742.6" + process $proc$libresoc.v:202727$14159 + assign { } { } + assign { } { } + assign $0\dec2_raw_opcode_in[31:0] $1\dec2_raw_opcode_in[31:0] + attribute \src "libresoc.v:202728.5-202728.29" + switch \initial + attribute \src "libresoc.v:202728.9-202728.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:375" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec2_raw_opcode_in[31:0] $2\dec2_raw_opcode_in[31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:388" + switch \fetch_insn_valid_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\dec2_raw_opcode_in[31:0] \fetch_insn_o + case + assign $2\dec2_raw_opcode_in[31:0] 0 + end + case + assign $1\dec2_raw_opcode_in[31:0] 0 + end + sync always + update \dec2_raw_opcode_in $0\dec2_raw_opcode_in[31:0] + end + attribute \src "libresoc.v:202743.3-202858.6" + process $proc$libresoc.v:202743$14160 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\core_asmcode$next[7:0]$14161 $1\core_asmcode$next[7:0]$14220 + assign $0\core_core_core_cia$next[63:0]$14162 $1\core_core_core_cia$next[63:0]$14221 + assign $0\core_core_core_cr_rd$next[7:0]$14163 $1\core_core_core_cr_rd$next[7:0]$14222 + assign { } { } + assign $0\core_core_core_cr_wr$next[7:0]$14165 $1\core_core_core_cr_wr$next[7:0]$14224 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\core_core_core_fn_unit$next[12:0]$14174 $1\core_core_core_fn_unit$next[12:0]$14233 + assign $0\core_core_core_input_carry$next[1:0]$14175 $1\core_core_core_input_carry$next[1:0]$14234 + assign $0\core_core_core_insn$next[31:0]$14176 $1\core_core_core_insn$next[31:0]$14235 + assign $0\core_core_core_insn_type$next[6:0]$14177 $1\core_core_core_insn_type$next[6:0]$14236 + assign $0\core_core_core_is_32bit$next[0:0]$14178 $1\core_core_core_is_32bit$next[0:0]$14237 + assign $0\core_core_core_msr$next[63:0]$14179 $1\core_core_core_msr$next[63:0]$14238 + assign $0\core_core_core_oe$next[0:0]$14180 $1\core_core_core_oe$next[0:0]$14239 + assign { } { } + assign $0\core_core_core_rc$next[0:0]$14182 $1\core_core_core_rc$next[0:0]$14241 + assign { } { } + assign $0\core_core_core_trapaddr$next[12:0]$14184 $1\core_core_core_trapaddr$next[12:0]$14243 + assign $0\core_core_core_traptype$next[7:0]$14185 $1\core_core_core_traptype$next[7:0]$14244 + assign $0\core_core_cr_in1$next[6:0]$14186 $1\core_core_cr_in1$next[6:0]$14245 + assign { } { } + assign $0\core_core_cr_in2$1$next[6:0]$14188 $1\core_core_cr_in2$1$next[6:0]$14247 + assign $0\core_core_cr_in2$next[6:0]$14189 $1\core_core_cr_in2$next[6:0]$14248 + assign { } { } + assign { } { } + assign $0\core_core_cr_out$next[6:0]$14192 $1\core_core_cr_out$next[6:0]$14251 + assign { } { } + assign $0\core_core_ea$next[6:0]$14194 $1\core_core_ea$next[6:0]$14253 + assign $0\core_core_fast1$next[2:0]$14195 $1\core_core_fast1$next[2:0]$14254 + assign { } { } + assign $0\core_core_fast2$next[2:0]$14197 $1\core_core_fast2$next[2:0]$14256 + assign { } { } + assign $0\core_core_fasto1$next[2:0]$14199 $1\core_core_fasto1$next[2:0]$14258 + assign $0\core_core_fasto2$next[2:0]$14200 $1\core_core_fasto2$next[2:0]$14259 + assign $0\core_core_lk$next[0:0]$14201 $1\core_core_lk$next[0:0]$14260 + assign $0\core_core_reg1$next[6:0]$14202 $1\core_core_reg1$next[6:0]$14261 + assign { } { } + assign $0\core_core_reg2$next[6:0]$14204 $1\core_core_reg2$next[6:0]$14263 + assign { } { } + assign $0\core_core_reg3$next[6:0]$14206 $1\core_core_reg3$next[6:0]$14265 + assign { } { } + assign $0\core_core_rego$next[6:0]$14208 $1\core_core_rego$next[6:0]$14267 + assign $0\core_core_spr1$next[9:0]$14209 $1\core_core_spr1$next[9:0]$14268 + assign { } { } + assign $0\core_core_spro$next[9:0]$14211 $1\core_core_spro$next[9:0]$14270 + assign $0\core_core_xer_in$next[2:0]$14212 $1\core_core_xer_in$next[2:0]$14271 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\core_xer_out$next[0:0]$14219 $1\core_xer_out$next[0:0]$14278 + assign $0\core_core_core_cr_rd_ok$next[0:0]$14164 $4\core_core_core_cr_rd_ok$next[0:0]$14397 + assign $0\core_core_core_exc_$signal$3$next[0:0]$14166 $4\core_core_core_exc_$signal$3$next[0:0]$14398 + assign $0\core_core_core_exc_$signal$4$next[0:0]$14167 $4\core_core_core_exc_$signal$4$next[0:0]$14399 + assign $0\core_core_core_exc_$signal$5$next[0:0]$14168 $4\core_core_core_exc_$signal$5$next[0:0]$14400 + assign $0\core_core_core_exc_$signal$6$next[0:0]$14169 $4\core_core_core_exc_$signal$6$next[0:0]$14401 + assign $0\core_core_core_exc_$signal$7$next[0:0]$14170 $4\core_core_core_exc_$signal$7$next[0:0]$14402 + assign $0\core_core_core_exc_$signal$8$next[0:0]$14171 $4\core_core_core_exc_$signal$8$next[0:0]$14403 + assign $0\core_core_core_exc_$signal$9$next[0:0]$14172 $4\core_core_core_exc_$signal$9$next[0:0]$14404 + assign $0\core_core_core_exc_$signal$next[0:0]$14173 $4\core_core_core_exc_$signal$next[0:0]$14405 + assign $0\core_core_core_oe_ok$next[0:0]$14181 $4\core_core_core_oe_ok$next[0:0]$14406 + assign $0\core_core_core_rc_ok$next[0:0]$14183 $4\core_core_core_rc_ok$next[0:0]$14407 + assign $0\core_core_cr_in1_ok$next[0:0]$14187 $4\core_core_cr_in1_ok$next[0:0]$14408 + assign $0\core_core_cr_in2_ok$2$next[0:0]$14190 $4\core_core_cr_in2_ok$2$next[0:0]$14409 + assign $0\core_core_cr_in2_ok$next[0:0]$14191 $4\core_core_cr_in2_ok$next[0:0]$14410 + assign $0\core_core_cr_wr_ok$next[0:0]$14193 $4\core_core_cr_wr_ok$next[0:0]$14411 + assign $0\core_core_fast1_ok$next[0:0]$14196 $4\core_core_fast1_ok$next[0:0]$14412 + assign $0\core_core_fast2_ok$next[0:0]$14198 $4\core_core_fast2_ok$next[0:0]$14413 + assign $0\core_core_reg1_ok$next[0:0]$14203 $4\core_core_reg1_ok$next[0:0]$14414 + assign $0\core_core_reg2_ok$next[0:0]$14205 $4\core_core_reg2_ok$next[0:0]$14415 + assign $0\core_core_reg3_ok$next[0:0]$14207 $4\core_core_reg3_ok$next[0:0]$14416 + assign $0\core_core_spr1_ok$next[0:0]$14210 $4\core_core_spr1_ok$next[0:0]$14417 + assign $0\core_cr_out_ok$next[0:0]$14213 $4\core_cr_out_ok$next[0:0]$14418 + assign $0\core_ea_ok$next[0:0]$14214 $4\core_ea_ok$next[0:0]$14419 + assign $0\core_fasto1_ok$next[0:0]$14215 $4\core_fasto1_ok$next[0:0]$14420 + assign $0\core_fasto2_ok$next[0:0]$14216 $4\core_fasto2_ok$next[0:0]$14421 + assign $0\core_rego_ok$next[0:0]$14217 $4\core_rego_ok$next[0:0]$14422 + assign $0\core_spro_ok$next[0:0]$14218 $4\core_spro_ok$next[0:0]$14423 + attribute \src "libresoc.v:202744.5-202744.29" + switch \initial + attribute \src "libresoc.v:202744.9-202744.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:375" + switch \fsm_state + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\core_asmcode$next[7:0]$14220 $2\core_asmcode$next[7:0]$14279 + assign $1\core_core_core_cia$next[63:0]$14221 $2\core_core_core_cia$next[63:0]$14280 + assign $1\core_core_core_cr_rd$next[7:0]$14222 $2\core_core_core_cr_rd$next[7:0]$14281 + assign $1\core_core_core_cr_rd_ok$next[0:0]$14223 $2\core_core_core_cr_rd_ok$next[0:0]$14282 + assign $1\core_core_core_cr_wr$next[7:0]$14224 $2\core_core_core_cr_wr$next[7:0]$14283 + assign $1\core_core_core_exc_$signal$3$next[0:0]$14225 $2\core_core_core_exc_$signal$3$next[0:0]$14284 + assign $1\core_core_core_exc_$signal$4$next[0:0]$14226 $2\core_core_core_exc_$signal$4$next[0:0]$14285 + assign $1\core_core_core_exc_$signal$5$next[0:0]$14227 $2\core_core_core_exc_$signal$5$next[0:0]$14286 + assign $1\core_core_core_exc_$signal$6$next[0:0]$14228 $2\core_core_core_exc_$signal$6$next[0:0]$14287 + assign $1\core_core_core_exc_$signal$7$next[0:0]$14229 $2\core_core_core_exc_$signal$7$next[0:0]$14288 + assign $1\core_core_core_exc_$signal$8$next[0:0]$14230 $2\core_core_core_exc_$signal$8$next[0:0]$14289 + assign $1\core_core_core_exc_$signal$9$next[0:0]$14231 $2\core_core_core_exc_$signal$9$next[0:0]$14290 + assign $1\core_core_core_exc_$signal$next[0:0]$14232 $2\core_core_core_exc_$signal$next[0:0]$14291 + assign $1\core_core_core_fn_unit$next[12:0]$14233 $2\core_core_core_fn_unit$next[12:0]$14292 + assign $1\core_core_core_input_carry$next[1:0]$14234 $2\core_core_core_input_carry$next[1:0]$14293 + assign $1\core_core_core_insn$next[31:0]$14235 $2\core_core_core_insn$next[31:0]$14294 + assign $1\core_core_core_insn_type$next[6:0]$14236 $2\core_core_core_insn_type$next[6:0]$14295 + assign $1\core_core_core_is_32bit$next[0:0]$14237 $2\core_core_core_is_32bit$next[0:0]$14296 + assign $1\core_core_core_msr$next[63:0]$14238 $2\core_core_core_msr$next[63:0]$14297 + assign $1\core_core_core_oe$next[0:0]$14239 $2\core_core_core_oe$next[0:0]$14298 + assign $1\core_core_core_oe_ok$next[0:0]$14240 $2\core_core_core_oe_ok$next[0:0]$14299 + assign $1\core_core_core_rc$next[0:0]$14241 $2\core_core_core_rc$next[0:0]$14300 + assign $1\core_core_core_rc_ok$next[0:0]$14242 $2\core_core_core_rc_ok$next[0:0]$14301 + assign $1\core_core_core_trapaddr$next[12:0]$14243 $2\core_core_core_trapaddr$next[12:0]$14302 + assign $1\core_core_core_traptype$next[7:0]$14244 $2\core_core_core_traptype$next[7:0]$14303 + assign $1\core_core_cr_in1$next[6:0]$14245 $2\core_core_cr_in1$next[6:0]$14304 + assign $1\core_core_cr_in1_ok$next[0:0]$14246 $2\core_core_cr_in1_ok$next[0:0]$14305 + assign $1\core_core_cr_in2$1$next[6:0]$14247 $2\core_core_cr_in2$1$next[6:0]$14306 + assign $1\core_core_cr_in2$next[6:0]$14248 $2\core_core_cr_in2$next[6:0]$14307 + assign $1\core_core_cr_in2_ok$2$next[0:0]$14249 $2\core_core_cr_in2_ok$2$next[0:0]$14308 + assign $1\core_core_cr_in2_ok$next[0:0]$14250 $2\core_core_cr_in2_ok$next[0:0]$14309 + assign $1\core_core_cr_out$next[6:0]$14251 $2\core_core_cr_out$next[6:0]$14310 + assign $1\core_core_cr_wr_ok$next[0:0]$14252 $2\core_core_cr_wr_ok$next[0:0]$14311 + assign $1\core_core_ea$next[6:0]$14253 $2\core_core_ea$next[6:0]$14312 + assign $1\core_core_fast1$next[2:0]$14254 $2\core_core_fast1$next[2:0]$14313 + assign $1\core_core_fast1_ok$next[0:0]$14255 $2\core_core_fast1_ok$next[0:0]$14314 + assign $1\core_core_fast2$next[2:0]$14256 $2\core_core_fast2$next[2:0]$14315 + assign $1\core_core_fast2_ok$next[0:0]$14257 $2\core_core_fast2_ok$next[0:0]$14316 + assign $1\core_core_fasto1$next[2:0]$14258 $2\core_core_fasto1$next[2:0]$14317 + assign $1\core_core_fasto2$next[2:0]$14259 $2\core_core_fasto2$next[2:0]$14318 + assign $1\core_core_lk$next[0:0]$14260 $2\core_core_lk$next[0:0]$14319 + assign $1\core_core_reg1$next[6:0]$14261 $2\core_core_reg1$next[6:0]$14320 + assign $1\core_core_reg1_ok$next[0:0]$14262 $2\core_core_reg1_ok$next[0:0]$14321 + assign $1\core_core_reg2$next[6:0]$14263 $2\core_core_reg2$next[6:0]$14322 + assign $1\core_core_reg2_ok$next[0:0]$14264 $2\core_core_reg2_ok$next[0:0]$14323 + assign $1\core_core_reg3$next[6:0]$14265 $2\core_core_reg3$next[6:0]$14324 + assign $1\core_core_reg3_ok$next[0:0]$14266 $2\core_core_reg3_ok$next[0:0]$14325 + assign $1\core_core_rego$next[6:0]$14267 $2\core_core_rego$next[6:0]$14326 + assign $1\core_core_spr1$next[9:0]$14268 $2\core_core_spr1$next[9:0]$14327 + assign $1\core_core_spr1_ok$next[0:0]$14269 $2\core_core_spr1_ok$next[0:0]$14328 + assign $1\core_core_spro$next[9:0]$14270 $2\core_core_spro$next[9:0]$14329 + assign $1\core_core_xer_in$next[2:0]$14271 $2\core_core_xer_in$next[2:0]$14330 + assign $1\core_cr_out_ok$next[0:0]$14272 $2\core_cr_out_ok$next[0:0]$14331 + assign $1\core_ea_ok$next[0:0]$14273 $2\core_ea_ok$next[0:0]$14332 + assign $1\core_fasto1_ok$next[0:0]$14274 $2\core_fasto1_ok$next[0:0]$14333 + assign $1\core_fasto2_ok$next[0:0]$14275 $2\core_fasto2_ok$next[0:0]$14334 + assign $1\core_rego_ok$next[0:0]$14276 $2\core_rego_ok$next[0:0]$14335 + assign $1\core_spro_ok$next[0:0]$14277 $2\core_spro_ok$next[0:0]$14336 + assign $1\core_xer_out$next[0:0]$14278 $2\core_xer_out$next[0:0]$14337 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:388" + switch \fetch_insn_valid_o + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $2\core_core_core_is_32bit$next[0:0]$14296 $2\core_core_cr_wr_ok$next[0:0]$14311 $2\core_core_core_cr_wr$next[7:0]$14283 $2\core_core_core_cr_rd_ok$next[0:0]$14282 $2\core_core_core_cr_rd$next[7:0]$14281 $2\core_core_core_trapaddr$next[12:0]$14302 $2\core_core_core_exc_$signal$9$next[0:0]$14290 $2\core_core_core_exc_$signal$8$next[0:0]$14289 $2\core_core_core_exc_$signal$7$next[0:0]$14288 $2\core_core_core_exc_$signal$6$next[0:0]$14287 $2\core_core_core_exc_$signal$5$next[0:0]$14286 $2\core_core_core_exc_$signal$4$next[0:0]$14285 $2\core_core_core_exc_$signal$3$next[0:0]$14284 $2\core_core_core_exc_$signal$next[0:0]$14291 $2\core_core_core_traptype$next[7:0]$14303 $2\core_core_core_input_carry$next[1:0]$14293 $2\core_core_core_oe_ok$next[0:0]$14299 $2\core_core_core_oe$next[0:0]$14298 $2\core_core_core_rc_ok$next[0:0]$14301 $2\core_core_core_rc$next[0:0]$14300 $2\core_core_lk$next[0:0]$14319 $2\core_core_core_fn_unit$next[12:0]$14292 $2\core_core_core_insn_type$next[6:0]$14295 $2\core_core_core_insn$next[31:0]$14294 $2\core_core_core_cia$next[63:0]$14280 $2\core_core_core_msr$next[63:0]$14297 $2\core_cr_out_ok$next[0:0]$14331 $2\core_core_cr_out$next[6:0]$14310 $2\core_core_cr_in2_ok$2$next[0:0]$14308 $2\core_core_cr_in2$1$next[6:0]$14306 $2\core_core_cr_in2_ok$next[0:0]$14309 $2\core_core_cr_in2$next[6:0]$14307 $2\core_core_cr_in1_ok$next[0:0]$14305 $2\core_core_cr_in1$next[6:0]$14304 $2\core_fasto2_ok$next[0:0]$14334 $2\core_core_fasto2$next[2:0]$14318 $2\core_fasto1_ok$next[0:0]$14333 $2\core_core_fasto1$next[2:0]$14317 $2\core_core_fast2_ok$next[0:0]$14316 $2\core_core_fast2$next[2:0]$14315 $2\core_core_fast1_ok$next[0:0]$14314 $2\core_core_fast1$next[2:0]$14313 $2\core_xer_out$next[0:0]$14337 $2\core_core_xer_in$next[2:0]$14330 $2\core_core_spr1_ok$next[0:0]$14328 $2\core_core_spr1$next[9:0]$14327 $2\core_spro_ok$next[0:0]$14336 $2\core_core_spro$next[9:0]$14329 $2\core_core_reg3_ok$next[0:0]$14325 $2\core_core_reg3$next[6:0]$14324 $2\core_core_reg2_ok$next[0:0]$14323 $2\core_core_reg2$next[6:0]$14322 $2\core_core_reg1_ok$next[0:0]$14321 $2\core_core_reg1$next[6:0]$14320 $2\core_ea_ok$next[0:0]$14332 $2\core_core_ea$next[6:0]$14312 $2\core_rego_ok$next[0:0]$14335 $2\core_core_rego$next[6:0]$14326 $2\core_asmcode$next[7:0]$14279 } { \dec2_is_32bit \dec2_cr_wr_ok \dec2_cr_wr \dec2_cr_rd_ok \dec2_cr_rd \dec2_trapaddr \dec2_exc_$signal$22 \dec2_exc_$signal$21 \dec2_exc_$signal$20 \dec2_exc_$signal$19 \dec2_exc_$signal$18 \dec2_exc_$signal$17 \dec2_exc_$signal$16 \dec2_exc_$signal \dec2_traptype \dec2_input_carry \dec2_oe_ok \dec2_oe \dec2_rc_ok \dec2_rc \dec2_lk \dec2_fn_unit \dec2_insn_type \dec2_insn \dec2_cia \dec2_msr \dec2_cr_out_ok \dec2_cr_out \dec2_cr_in2_ok$15 \dec2_cr_in2$14 \dec2_cr_in2_ok \dec2_cr_in2 \dec2_cr_in1_ok \dec2_cr_in1 \dec2_fasto2_ok \dec2_fasto2 \dec2_fasto1_ok \dec2_fasto1 \dec2_fast2_ok \dec2_fast2 \dec2_fast1_ok \dec2_fast1 \dec2_xer_out \dec2_xer_in \dec2_spr1_ok \dec2_spr1 \dec2_spro_ok \dec2_spro \dec2_reg3_ok \dec2_reg3 \dec2_reg2_ok \dec2_reg2 \dec2_reg1_ok \dec2_reg1 \dec2_ea_ok \dec2_ea \dec2_rego_ok \dec2_rego \dec2_asmcode } + case + assign $2\core_asmcode$next[7:0]$14279 \core_asmcode + assign $2\core_core_core_cia$next[63:0]$14280 \core_core_core_cia + assign $2\core_core_core_cr_rd$next[7:0]$14281 \core_core_core_cr_rd + assign $2\core_core_core_cr_rd_ok$next[0:0]$14282 \core_core_core_cr_rd_ok + assign $2\core_core_core_cr_wr$next[7:0]$14283 \core_core_core_cr_wr + assign $2\core_core_core_exc_$signal$3$next[0:0]$14284 \core_core_core_exc_$signal$3 + assign $2\core_core_core_exc_$signal$4$next[0:0]$14285 \core_core_core_exc_$signal$4 + assign $2\core_core_core_exc_$signal$5$next[0:0]$14286 \core_core_core_exc_$signal$5 + assign $2\core_core_core_exc_$signal$6$next[0:0]$14287 \core_core_core_exc_$signal$6 + assign $2\core_core_core_exc_$signal$7$next[0:0]$14288 \core_core_core_exc_$signal$7 + assign $2\core_core_core_exc_$signal$8$next[0:0]$14289 \core_core_core_exc_$signal$8 + assign $2\core_core_core_exc_$signal$9$next[0:0]$14290 \core_core_core_exc_$signal$9 + assign $2\core_core_core_exc_$signal$next[0:0]$14291 \core_core_core_exc_$signal + assign $2\core_core_core_fn_unit$next[12:0]$14292 \core_core_core_fn_unit + assign $2\core_core_core_input_carry$next[1:0]$14293 \core_core_core_input_carry + assign $2\core_core_core_insn$next[31:0]$14294 \core_core_core_insn + assign $2\core_core_core_insn_type$next[6:0]$14295 \core_core_core_insn_type + assign $2\core_core_core_is_32bit$next[0:0]$14296 \core_core_core_is_32bit + assign $2\core_core_core_msr$next[63:0]$14297 \core_core_core_msr + assign $2\core_core_core_oe$next[0:0]$14298 \core_core_core_oe + assign $2\core_core_core_oe_ok$next[0:0]$14299 \core_core_core_oe_ok + assign $2\core_core_core_rc$next[0:0]$14300 \core_core_core_rc + assign $2\core_core_core_rc_ok$next[0:0]$14301 \core_core_core_rc_ok + assign $2\core_core_core_trapaddr$next[12:0]$14302 \core_core_core_trapaddr + assign $2\core_core_core_traptype$next[7:0]$14303 \core_core_core_traptype + assign $2\core_core_cr_in1$next[6:0]$14304 \core_core_cr_in1 + assign $2\core_core_cr_in1_ok$next[0:0]$14305 \core_core_cr_in1_ok + assign $2\core_core_cr_in2$1$next[6:0]$14306 \core_core_cr_in2$1 + assign $2\core_core_cr_in2$next[6:0]$14307 \core_core_cr_in2 + assign $2\core_core_cr_in2_ok$2$next[0:0]$14308 \core_core_cr_in2_ok$2 + assign $2\core_core_cr_in2_ok$next[0:0]$14309 \core_core_cr_in2_ok + assign $2\core_core_cr_out$next[6:0]$14310 \core_core_cr_out + assign $2\core_core_cr_wr_ok$next[0:0]$14311 \core_core_cr_wr_ok + assign $2\core_core_ea$next[6:0]$14312 \core_core_ea + assign $2\core_core_fast1$next[2:0]$14313 \core_core_fast1 + assign $2\core_core_fast1_ok$next[0:0]$14314 \core_core_fast1_ok + assign $2\core_core_fast2$next[2:0]$14315 \core_core_fast2 + assign $2\core_core_fast2_ok$next[0:0]$14316 \core_core_fast2_ok + assign $2\core_core_fasto1$next[2:0]$14317 \core_core_fasto1 + assign $2\core_core_fasto2$next[2:0]$14318 \core_core_fasto2 + assign $2\core_core_lk$next[0:0]$14319 \core_core_lk + assign $2\core_core_reg1$next[6:0]$14320 \core_core_reg1 + assign $2\core_core_reg1_ok$next[0:0]$14321 \core_core_reg1_ok + assign $2\core_core_reg2$next[6:0]$14322 \core_core_reg2 + assign $2\core_core_reg2_ok$next[0:0]$14323 \core_core_reg2_ok + assign $2\core_core_reg3$next[6:0]$14324 \core_core_reg3 + assign $2\core_core_reg3_ok$next[0:0]$14325 \core_core_reg3_ok + assign $2\core_core_rego$next[6:0]$14326 \core_core_rego + assign $2\core_core_spr1$next[9:0]$14327 \core_core_spr1 + assign $2\core_core_spr1_ok$next[0:0]$14328 \core_core_spr1_ok + assign $2\core_core_spro$next[9:0]$14329 \core_core_spro + assign $2\core_core_xer_in$next[2:0]$14330 \core_core_xer_in + assign $2\core_cr_out_ok$next[0:0]$14331 \core_cr_out_ok + assign $2\core_ea_ok$next[0:0]$14332 \core_ea_ok + assign $2\core_fasto1_ok$next[0:0]$14333 \core_fasto1_ok + assign $2\core_fasto2_ok$next[0:0]$14334 \core_fasto2_ok + assign $2\core_rego_ok$next[0:0]$14335 \core_rego_ok + assign $2\core_spro_ok$next[0:0]$14336 \core_spro_ok + assign $2\core_xer_out$next[0:0]$14337 \core_xer_out + end + attribute \src "libresoc.v:0.0-0.0" + case 2'11 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\core_asmcode$next[7:0]$14220 $3\core_asmcode$next[7:0]$14338 + assign $1\core_core_core_cia$next[63:0]$14221 $3\core_core_core_cia$next[63:0]$14339 + assign $1\core_core_core_cr_rd$next[7:0]$14222 $3\core_core_core_cr_rd$next[7:0]$14340 + assign $1\core_core_core_cr_rd_ok$next[0:0]$14223 $3\core_core_core_cr_rd_ok$next[0:0]$14341 + assign $1\core_core_core_cr_wr$next[7:0]$14224 $3\core_core_core_cr_wr$next[7:0]$14342 + assign $1\core_core_core_exc_$signal$3$next[0:0]$14225 $3\core_core_core_exc_$signal$3$next[0:0]$14343 + assign $1\core_core_core_exc_$signal$4$next[0:0]$14226 $3\core_core_core_exc_$signal$4$next[0:0]$14344 + assign $1\core_core_core_exc_$signal$5$next[0:0]$14227 $3\core_core_core_exc_$signal$5$next[0:0]$14345 + assign $1\core_core_core_exc_$signal$6$next[0:0]$14228 $3\core_core_core_exc_$signal$6$next[0:0]$14346 + assign $1\core_core_core_exc_$signal$7$next[0:0]$14229 $3\core_core_core_exc_$signal$7$next[0:0]$14347 + assign $1\core_core_core_exc_$signal$8$next[0:0]$14230 $3\core_core_core_exc_$signal$8$next[0:0]$14348 + assign $1\core_core_core_exc_$signal$9$next[0:0]$14231 $3\core_core_core_exc_$signal$9$next[0:0]$14349 + assign $1\core_core_core_exc_$signal$next[0:0]$14232 $3\core_core_core_exc_$signal$next[0:0]$14350 + assign $1\core_core_core_fn_unit$next[12:0]$14233 $3\core_core_core_fn_unit$next[12:0]$14351 + assign $1\core_core_core_input_carry$next[1:0]$14234 $3\core_core_core_input_carry$next[1:0]$14352 + assign $1\core_core_core_insn$next[31:0]$14235 $3\core_core_core_insn$next[31:0]$14353 + assign $1\core_core_core_insn_type$next[6:0]$14236 $3\core_core_core_insn_type$next[6:0]$14354 + assign $1\core_core_core_is_32bit$next[0:0]$14237 $3\core_core_core_is_32bit$next[0:0]$14355 + assign $1\core_core_core_msr$next[63:0]$14238 $3\core_core_core_msr$next[63:0]$14356 + assign $1\core_core_core_oe$next[0:0]$14239 $3\core_core_core_oe$next[0:0]$14357 + assign $1\core_core_core_oe_ok$next[0:0]$14240 $3\core_core_core_oe_ok$next[0:0]$14358 + assign $1\core_core_core_rc$next[0:0]$14241 $3\core_core_core_rc$next[0:0]$14359 + assign $1\core_core_core_rc_ok$next[0:0]$14242 $3\core_core_core_rc_ok$next[0:0]$14360 + assign $1\core_core_core_trapaddr$next[12:0]$14243 $3\core_core_core_trapaddr$next[12:0]$14361 + assign $1\core_core_core_traptype$next[7:0]$14244 $3\core_core_core_traptype$next[7:0]$14362 + assign $1\core_core_cr_in1$next[6:0]$14245 $3\core_core_cr_in1$next[6:0]$14363 + assign $1\core_core_cr_in1_ok$next[0:0]$14246 $3\core_core_cr_in1_ok$next[0:0]$14364 + assign $1\core_core_cr_in2$1$next[6:0]$14247 $3\core_core_cr_in2$1$next[6:0]$14365 + assign $1\core_core_cr_in2$next[6:0]$14248 $3\core_core_cr_in2$next[6:0]$14366 + assign $1\core_core_cr_in2_ok$2$next[0:0]$14249 $3\core_core_cr_in2_ok$2$next[0:0]$14367 + assign $1\core_core_cr_in2_ok$next[0:0]$14250 $3\core_core_cr_in2_ok$next[0:0]$14368 + assign $1\core_core_cr_out$next[6:0]$14251 $3\core_core_cr_out$next[6:0]$14369 + assign $1\core_core_cr_wr_ok$next[0:0]$14252 $3\core_core_cr_wr_ok$next[0:0]$14370 + assign $1\core_core_ea$next[6:0]$14253 $3\core_core_ea$next[6:0]$14371 + assign $1\core_core_fast1$next[2:0]$14254 $3\core_core_fast1$next[2:0]$14372 + assign $1\core_core_fast1_ok$next[0:0]$14255 $3\core_core_fast1_ok$next[0:0]$14373 + assign $1\core_core_fast2$next[2:0]$14256 $3\core_core_fast2$next[2:0]$14374 + assign $1\core_core_fast2_ok$next[0:0]$14257 $3\core_core_fast2_ok$next[0:0]$14375 + assign $1\core_core_fasto1$next[2:0]$14258 $3\core_core_fasto1$next[2:0]$14376 + assign $1\core_core_fasto2$next[2:0]$14259 $3\core_core_fasto2$next[2:0]$14377 + assign $1\core_core_lk$next[0:0]$14260 $3\core_core_lk$next[0:0]$14378 + assign $1\core_core_reg1$next[6:0]$14261 $3\core_core_reg1$next[6:0]$14379 + assign $1\core_core_reg1_ok$next[0:0]$14262 $3\core_core_reg1_ok$next[0:0]$14380 + assign $1\core_core_reg2$next[6:0]$14263 $3\core_core_reg2$next[6:0]$14381 + assign $1\core_core_reg2_ok$next[0:0]$14264 $3\core_core_reg2_ok$next[0:0]$14382 + assign $1\core_core_reg3$next[6:0]$14265 $3\core_core_reg3$next[6:0]$14383 + assign $1\core_core_reg3_ok$next[0:0]$14266 $3\core_core_reg3_ok$next[0:0]$14384 + assign $1\core_core_rego$next[6:0]$14267 $3\core_core_rego$next[6:0]$14385 + assign $1\core_core_spr1$next[9:0]$14268 $3\core_core_spr1$next[9:0]$14386 + assign $1\core_core_spr1_ok$next[0:0]$14269 $3\core_core_spr1_ok$next[0:0]$14387 + assign $1\core_core_spro$next[9:0]$14270 $3\core_core_spro$next[9:0]$14388 + assign $1\core_core_xer_in$next[2:0]$14271 $3\core_core_xer_in$next[2:0]$14389 + assign $1\core_cr_out_ok$next[0:0]$14272 $3\core_cr_out_ok$next[0:0]$14390 + assign $1\core_ea_ok$next[0:0]$14273 $3\core_ea_ok$next[0:0]$14391 + assign $1\core_fasto1_ok$next[0:0]$14274 $3\core_fasto1_ok$next[0:0]$14392 + assign $1\core_fasto2_ok$next[0:0]$14275 $3\core_fasto2_ok$next[0:0]$14393 + assign $1\core_rego_ok$next[0:0]$14276 $3\core_rego_ok$next[0:0]$14394 + assign $1\core_spro_ok$next[0:0]$14277 $3\core_spro_ok$next[0:0]$14395 + assign $1\core_xer_out$next[0:0]$14278 $3\core_xer_out$next[0:0]$14396 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:413" + switch \$163 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $3\core_core_core_is_32bit$next[0:0]$14355 $3\core_core_cr_wr_ok$next[0:0]$14370 $3\core_core_core_cr_wr$next[7:0]$14342 $3\core_core_core_cr_rd_ok$next[0:0]$14341 $3\core_core_core_cr_rd$next[7:0]$14340 $3\core_core_core_trapaddr$next[12:0]$14361 $3\core_core_core_exc_$signal$9$next[0:0]$14349 $3\core_core_core_exc_$signal$8$next[0:0]$14348 $3\core_core_core_exc_$signal$7$next[0:0]$14347 $3\core_core_core_exc_$signal$6$next[0:0]$14346 $3\core_core_core_exc_$signal$5$next[0:0]$14345 $3\core_core_core_exc_$signal$4$next[0:0]$14344 $3\core_core_core_exc_$signal$3$next[0:0]$14343 $3\core_core_core_exc_$signal$next[0:0]$14350 $3\core_core_core_traptype$next[7:0]$14362 $3\core_core_core_input_carry$next[1:0]$14352 $3\core_core_core_oe_ok$next[0:0]$14358 $3\core_core_core_oe$next[0:0]$14357 $3\core_core_core_rc_ok$next[0:0]$14360 $3\core_core_core_rc$next[0:0]$14359 $3\core_core_lk$next[0:0]$14378 $3\core_core_core_fn_unit$next[12:0]$14351 $3\core_core_core_insn_type$next[6:0]$14354 $3\core_core_core_insn$next[31:0]$14353 $3\core_core_core_cia$next[63:0]$14339 $3\core_core_core_msr$next[63:0]$14356 $3\core_cr_out_ok$next[0:0]$14390 $3\core_core_cr_out$next[6:0]$14369 $3\core_core_cr_in2_ok$2$next[0:0]$14367 $3\core_core_cr_in2$1$next[6:0]$14365 $3\core_core_cr_in2_ok$next[0:0]$14368 $3\core_core_cr_in2$next[6:0]$14366 $3\core_core_cr_in1_ok$next[0:0]$14364 $3\core_core_cr_in1$next[6:0]$14363 $3\core_fasto2_ok$next[0:0]$14393 $3\core_core_fasto2$next[2:0]$14377 $3\core_fasto1_ok$next[0:0]$14392 $3\core_core_fasto1$next[2:0]$14376 $3\core_core_fast2_ok$next[0:0]$14375 $3\core_core_fast2$next[2:0]$14374 $3\core_core_fast1_ok$next[0:0]$14373 $3\core_core_fast1$next[2:0]$14372 $3\core_xer_out$next[0:0]$14396 $3\core_core_xer_in$next[2:0]$14389 $3\core_core_spr1_ok$next[0:0]$14387 $3\core_core_spr1$next[9:0]$14386 $3\core_spro_ok$next[0:0]$14395 $3\core_core_spro$next[9:0]$14388 $3\core_core_reg3_ok$next[0:0]$14384 $3\core_core_reg3$next[6:0]$14383 $3\core_core_reg2_ok$next[0:0]$14382 $3\core_core_reg2$next[6:0]$14381 $3\core_core_reg1_ok$next[0:0]$14380 $3\core_core_reg1$next[6:0]$14379 $3\core_ea_ok$next[0:0]$14391 $3\core_core_ea$next[6:0]$14371 $3\core_rego_ok$next[0:0]$14394 $3\core_core_rego$next[6:0]$14385 $3\core_asmcode$next[7:0]$14338 } 357'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + case + assign $3\core_asmcode$next[7:0]$14338 \core_asmcode + assign $3\core_core_core_cia$next[63:0]$14339 \core_core_core_cia + assign $3\core_core_core_cr_rd$next[7:0]$14340 \core_core_core_cr_rd + assign $3\core_core_core_cr_rd_ok$next[0:0]$14341 \core_core_core_cr_rd_ok + assign $3\core_core_core_cr_wr$next[7:0]$14342 \core_core_core_cr_wr + assign $3\core_core_core_exc_$signal$3$next[0:0]$14343 \core_core_core_exc_$signal$3 + assign $3\core_core_core_exc_$signal$4$next[0:0]$14344 \core_core_core_exc_$signal$4 + assign $3\core_core_core_exc_$signal$5$next[0:0]$14345 \core_core_core_exc_$signal$5 + assign $3\core_core_core_exc_$signal$6$next[0:0]$14346 \core_core_core_exc_$signal$6 + assign $3\core_core_core_exc_$signal$7$next[0:0]$14347 \core_core_core_exc_$signal$7 + assign $3\core_core_core_exc_$signal$8$next[0:0]$14348 \core_core_core_exc_$signal$8 + assign $3\core_core_core_exc_$signal$9$next[0:0]$14349 \core_core_core_exc_$signal$9 + assign $3\core_core_core_exc_$signal$next[0:0]$14350 \core_core_core_exc_$signal + assign $3\core_core_core_fn_unit$next[12:0]$14351 \core_core_core_fn_unit + assign $3\core_core_core_input_carry$next[1:0]$14352 \core_core_core_input_carry + assign $3\core_core_core_insn$next[31:0]$14353 \core_core_core_insn + assign $3\core_core_core_insn_type$next[6:0]$14354 \core_core_core_insn_type + assign $3\core_core_core_is_32bit$next[0:0]$14355 \core_core_core_is_32bit + assign $3\core_core_core_msr$next[63:0]$14356 \core_core_core_msr + assign $3\core_core_core_oe$next[0:0]$14357 \core_core_core_oe + assign $3\core_core_core_oe_ok$next[0:0]$14358 \core_core_core_oe_ok + assign $3\core_core_core_rc$next[0:0]$14359 \core_core_core_rc + assign $3\core_core_core_rc_ok$next[0:0]$14360 \core_core_core_rc_ok + assign $3\core_core_core_trapaddr$next[12:0]$14361 \core_core_core_trapaddr + assign $3\core_core_core_traptype$next[7:0]$14362 \core_core_core_traptype + assign $3\core_core_cr_in1$next[6:0]$14363 \core_core_cr_in1 + assign $3\core_core_cr_in1_ok$next[0:0]$14364 \core_core_cr_in1_ok + assign $3\core_core_cr_in2$1$next[6:0]$14365 \core_core_cr_in2$1 + assign $3\core_core_cr_in2$next[6:0]$14366 \core_core_cr_in2 + assign $3\core_core_cr_in2_ok$2$next[0:0]$14367 \core_core_cr_in2_ok$2 + assign $3\core_core_cr_in2_ok$next[0:0]$14368 \core_core_cr_in2_ok + assign $3\core_core_cr_out$next[6:0]$14369 \core_core_cr_out + assign $3\core_core_cr_wr_ok$next[0:0]$14370 \core_core_cr_wr_ok + assign $3\core_core_ea$next[6:0]$14371 \core_core_ea + assign $3\core_core_fast1$next[2:0]$14372 \core_core_fast1 + assign $3\core_core_fast1_ok$next[0:0]$14373 \core_core_fast1_ok + assign $3\core_core_fast2$next[2:0]$14374 \core_core_fast2 + assign $3\core_core_fast2_ok$next[0:0]$14375 \core_core_fast2_ok + assign $3\core_core_fasto1$next[2:0]$14376 \core_core_fasto1 + assign $3\core_core_fasto2$next[2:0]$14377 \core_core_fasto2 + assign $3\core_core_lk$next[0:0]$14378 \core_core_lk + assign $3\core_core_reg1$next[6:0]$14379 \core_core_reg1 + assign $3\core_core_reg1_ok$next[0:0]$14380 \core_core_reg1_ok + assign $3\core_core_reg2$next[6:0]$14381 \core_core_reg2 + assign $3\core_core_reg2_ok$next[0:0]$14382 \core_core_reg2_ok + assign $3\core_core_reg3$next[6:0]$14383 \core_core_reg3 + assign $3\core_core_reg3_ok$next[0:0]$14384 \core_core_reg3_ok + assign $3\core_core_rego$next[6:0]$14385 \core_core_rego + assign $3\core_core_spr1$next[9:0]$14386 \core_core_spr1 + assign $3\core_core_spr1_ok$next[0:0]$14387 \core_core_spr1_ok + assign $3\core_core_spro$next[9:0]$14388 \core_core_spro + assign $3\core_core_xer_in$next[2:0]$14389 \core_core_xer_in + assign $3\core_cr_out_ok$next[0:0]$14390 \core_cr_out_ok + assign $3\core_ea_ok$next[0:0]$14391 \core_ea_ok + assign $3\core_fasto1_ok$next[0:0]$14392 \core_fasto1_ok + assign $3\core_fasto2_ok$next[0:0]$14393 \core_fasto2_ok + assign $3\core_rego_ok$next[0:0]$14394 \core_rego_ok + assign $3\core_spro_ok$next[0:0]$14395 \core_spro_ok + assign $3\core_xer_out$next[0:0]$14396 \core_xer_out + end + case + assign $1\core_asmcode$next[7:0]$14220 \core_asmcode + assign $1\core_core_core_cia$next[63:0]$14221 \core_core_core_cia + assign $1\core_core_core_cr_rd$next[7:0]$14222 \core_core_core_cr_rd + assign $1\core_core_core_cr_rd_ok$next[0:0]$14223 \core_core_core_cr_rd_ok + assign $1\core_core_core_cr_wr$next[7:0]$14224 \core_core_core_cr_wr + assign $1\core_core_core_exc_$signal$3$next[0:0]$14225 \core_core_core_exc_$signal$3 + assign $1\core_core_core_exc_$signal$4$next[0:0]$14226 \core_core_core_exc_$signal$4 + assign $1\core_core_core_exc_$signal$5$next[0:0]$14227 \core_core_core_exc_$signal$5 + assign $1\core_core_core_exc_$signal$6$next[0:0]$14228 \core_core_core_exc_$signal$6 + assign $1\core_core_core_exc_$signal$7$next[0:0]$14229 \core_core_core_exc_$signal$7 + assign $1\core_core_core_exc_$signal$8$next[0:0]$14230 \core_core_core_exc_$signal$8 + assign $1\core_core_core_exc_$signal$9$next[0:0]$14231 \core_core_core_exc_$signal$9 + assign $1\core_core_core_exc_$signal$next[0:0]$14232 \core_core_core_exc_$signal + assign $1\core_core_core_fn_unit$next[12:0]$14233 \core_core_core_fn_unit + assign $1\core_core_core_input_carry$next[1:0]$14234 \core_core_core_input_carry + assign $1\core_core_core_insn$next[31:0]$14235 \core_core_core_insn + assign $1\core_core_core_insn_type$next[6:0]$14236 \core_core_core_insn_type + assign $1\core_core_core_is_32bit$next[0:0]$14237 \core_core_core_is_32bit + assign $1\core_core_core_msr$next[63:0]$14238 \core_core_core_msr + assign $1\core_core_core_oe$next[0:0]$14239 \core_core_core_oe + assign $1\core_core_core_oe_ok$next[0:0]$14240 \core_core_core_oe_ok + assign $1\core_core_core_rc$next[0:0]$14241 \core_core_core_rc + assign $1\core_core_core_rc_ok$next[0:0]$14242 \core_core_core_rc_ok + assign $1\core_core_core_trapaddr$next[12:0]$14243 \core_core_core_trapaddr + assign $1\core_core_core_traptype$next[7:0]$14244 \core_core_core_traptype + assign $1\core_core_cr_in1$next[6:0]$14245 \core_core_cr_in1 + assign $1\core_core_cr_in1_ok$next[0:0]$14246 \core_core_cr_in1_ok + assign $1\core_core_cr_in2$1$next[6:0]$14247 \core_core_cr_in2$1 + assign $1\core_core_cr_in2$next[6:0]$14248 \core_core_cr_in2 + assign $1\core_core_cr_in2_ok$2$next[0:0]$14249 \core_core_cr_in2_ok$2 + assign $1\core_core_cr_in2_ok$next[0:0]$14250 \core_core_cr_in2_ok + assign $1\core_core_cr_out$next[6:0]$14251 \core_core_cr_out + assign $1\core_core_cr_wr_ok$next[0:0]$14252 \core_core_cr_wr_ok + assign $1\core_core_ea$next[6:0]$14253 \core_core_ea + assign $1\core_core_fast1$next[2:0]$14254 \core_core_fast1 + assign $1\core_core_fast1_ok$next[0:0]$14255 \core_core_fast1_ok + assign $1\core_core_fast2$next[2:0]$14256 \core_core_fast2 + assign $1\core_core_fast2_ok$next[0:0]$14257 \core_core_fast2_ok + assign $1\core_core_fasto1$next[2:0]$14258 \core_core_fasto1 + assign $1\core_core_fasto2$next[2:0]$14259 \core_core_fasto2 + assign $1\core_core_lk$next[0:0]$14260 \core_core_lk + assign $1\core_core_reg1$next[6:0]$14261 \core_core_reg1 + assign $1\core_core_reg1_ok$next[0:0]$14262 \core_core_reg1_ok + assign $1\core_core_reg2$next[6:0]$14263 \core_core_reg2 + assign $1\core_core_reg2_ok$next[0:0]$14264 \core_core_reg2_ok + assign $1\core_core_reg3$next[6:0]$14265 \core_core_reg3 + assign $1\core_core_reg3_ok$next[0:0]$14266 \core_core_reg3_ok + assign $1\core_core_rego$next[6:0]$14267 \core_core_rego + assign $1\core_core_spr1$next[9:0]$14268 \core_core_spr1 + assign $1\core_core_spr1_ok$next[0:0]$14269 \core_core_spr1_ok + assign $1\core_core_spro$next[9:0]$14270 \core_core_spro + assign $1\core_core_xer_in$next[2:0]$14271 \core_core_xer_in + assign $1\core_cr_out_ok$next[0:0]$14272 \core_cr_out_ok + assign $1\core_ea_ok$next[0:0]$14273 \core_ea_ok + assign $1\core_fasto1_ok$next[0:0]$14274 \core_fasto1_ok + assign $1\core_fasto2_ok$next[0:0]$14275 \core_fasto2_ok + assign $1\core_rego_ok$next[0:0]$14276 \core_rego_ok + assign $1\core_spro_ok$next[0:0]$14277 \core_spro_ok + assign $1\core_xer_out$next[0:0]$14278 \core_xer_out + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $4\core_rego_ok$next[0:0]$14422 1'0 + assign $4\core_ea_ok$next[0:0]$14419 1'0 + assign $4\core_core_reg1_ok$next[0:0]$14414 1'0 + assign $4\core_core_reg2_ok$next[0:0]$14415 1'0 + assign $4\core_core_reg3_ok$next[0:0]$14416 1'0 + assign $4\core_spro_ok$next[0:0]$14423 1'0 + assign $4\core_core_spr1_ok$next[0:0]$14417 1'0 + assign $4\core_core_fast1_ok$next[0:0]$14412 1'0 + assign $4\core_core_fast2_ok$next[0:0]$14413 1'0 + assign $4\core_fasto1_ok$next[0:0]$14420 1'0 + assign $4\core_fasto2_ok$next[0:0]$14421 1'0 + assign $4\core_core_cr_in1_ok$next[0:0]$14408 1'0 + assign $4\core_core_cr_in2_ok$next[0:0]$14410 1'0 + assign $4\core_core_cr_in2_ok$2$next[0:0]$14409 1'0 + assign $4\core_cr_out_ok$next[0:0]$14418 1'0 + assign $4\core_core_core_rc_ok$next[0:0]$14407 1'0 + assign $4\core_core_core_oe_ok$next[0:0]$14406 1'0 + assign $4\core_core_core_exc_$signal$next[0:0]$14405 1'0 + assign $4\core_core_core_exc_$signal$3$next[0:0]$14398 1'0 + assign $4\core_core_core_exc_$signal$4$next[0:0]$14399 1'0 + assign $4\core_core_core_exc_$signal$5$next[0:0]$14400 1'0 + assign $4\core_core_core_exc_$signal$6$next[0:0]$14401 1'0 + assign $4\core_core_core_exc_$signal$7$next[0:0]$14402 1'0 + assign $4\core_core_core_exc_$signal$8$next[0:0]$14403 1'0 + assign $4\core_core_core_exc_$signal$9$next[0:0]$14404 1'0 + assign $4\core_core_core_cr_rd_ok$next[0:0]$14397 1'0 + assign $4\core_core_cr_wr_ok$next[0:0]$14411 1'0 + case + assign $4\core_core_core_cr_rd_ok$next[0:0]$14397 $1\core_core_core_cr_rd_ok$next[0:0]$14223 + assign $4\core_core_core_exc_$signal$3$next[0:0]$14398 $1\core_core_core_exc_$signal$3$next[0:0]$14225 + assign $4\core_core_core_exc_$signal$4$next[0:0]$14399 $1\core_core_core_exc_$signal$4$next[0:0]$14226 + assign $4\core_core_core_exc_$signal$5$next[0:0]$14400 $1\core_core_core_exc_$signal$5$next[0:0]$14227 + assign $4\core_core_core_exc_$signal$6$next[0:0]$14401 $1\core_core_core_exc_$signal$6$next[0:0]$14228 + assign $4\core_core_core_exc_$signal$7$next[0:0]$14402 $1\core_core_core_exc_$signal$7$next[0:0]$14229 + assign $4\core_core_core_exc_$signal$8$next[0:0]$14403 $1\core_core_core_exc_$signal$8$next[0:0]$14230 + assign $4\core_core_core_exc_$signal$9$next[0:0]$14404 $1\core_core_core_exc_$signal$9$next[0:0]$14231 + assign $4\core_core_core_exc_$signal$next[0:0]$14405 $1\core_core_core_exc_$signal$next[0:0]$14232 + assign $4\core_core_core_oe_ok$next[0:0]$14406 $1\core_core_core_oe_ok$next[0:0]$14240 + assign $4\core_core_core_rc_ok$next[0:0]$14407 $1\core_core_core_rc_ok$next[0:0]$14242 + assign $4\core_core_cr_in1_ok$next[0:0]$14408 $1\core_core_cr_in1_ok$next[0:0]$14246 + assign $4\core_core_cr_in2_ok$2$next[0:0]$14409 $1\core_core_cr_in2_ok$2$next[0:0]$14249 + assign $4\core_core_cr_in2_ok$next[0:0]$14410 $1\core_core_cr_in2_ok$next[0:0]$14250 + assign $4\core_core_cr_wr_ok$next[0:0]$14411 $1\core_core_cr_wr_ok$next[0:0]$14252 + assign $4\core_core_fast1_ok$next[0:0]$14412 $1\core_core_fast1_ok$next[0:0]$14255 + assign $4\core_core_fast2_ok$next[0:0]$14413 $1\core_core_fast2_ok$next[0:0]$14257 + assign $4\core_core_reg1_ok$next[0:0]$14414 $1\core_core_reg1_ok$next[0:0]$14262 + assign $4\core_core_reg2_ok$next[0:0]$14415 $1\core_core_reg2_ok$next[0:0]$14264 + assign $4\core_core_reg3_ok$next[0:0]$14416 $1\core_core_reg3_ok$next[0:0]$14266 + assign $4\core_core_spr1_ok$next[0:0]$14417 $1\core_core_spr1_ok$next[0:0]$14269 + assign $4\core_cr_out_ok$next[0:0]$14418 $1\core_cr_out_ok$next[0:0]$14272 + assign $4\core_ea_ok$next[0:0]$14419 $1\core_ea_ok$next[0:0]$14273 + assign $4\core_fasto1_ok$next[0:0]$14420 $1\core_fasto1_ok$next[0:0]$14274 + assign $4\core_fasto2_ok$next[0:0]$14421 $1\core_fasto2_ok$next[0:0]$14275 + assign $4\core_rego_ok$next[0:0]$14422 $1\core_rego_ok$next[0:0]$14276 + assign $4\core_spro_ok$next[0:0]$14423 $1\core_spro_ok$next[0:0]$14277 + end + sync always + update \core_asmcode$next $0\core_asmcode$next[7:0]$14161 + update \core_core_core_cia$next $0\core_core_core_cia$next[63:0]$14162 + update \core_core_core_cr_rd$next $0\core_core_core_cr_rd$next[7:0]$14163 + update \core_core_core_cr_rd_ok$next $0\core_core_core_cr_rd_ok$next[0:0]$14164 + update \core_core_core_cr_wr$next $0\core_core_core_cr_wr$next[7:0]$14165 + update \core_core_core_exc_$signal$3$next $0\core_core_core_exc_$signal$3$next[0:0]$14166 + update \core_core_core_exc_$signal$4$next $0\core_core_core_exc_$signal$4$next[0:0]$14167 + update \core_core_core_exc_$signal$5$next $0\core_core_core_exc_$signal$5$next[0:0]$14168 + update \core_core_core_exc_$signal$6$next $0\core_core_core_exc_$signal$6$next[0:0]$14169 + update \core_core_core_exc_$signal$7$next $0\core_core_core_exc_$signal$7$next[0:0]$14170 + update \core_core_core_exc_$signal$8$next $0\core_core_core_exc_$signal$8$next[0:0]$14171 + update \core_core_core_exc_$signal$9$next $0\core_core_core_exc_$signal$9$next[0:0]$14172 + update \core_core_core_exc_$signal$next $0\core_core_core_exc_$signal$next[0:0]$14173 + update \core_core_core_fn_unit$next $0\core_core_core_fn_unit$next[12:0]$14174 + update \core_core_core_input_carry$next $0\core_core_core_input_carry$next[1:0]$14175 + update \core_core_core_insn$next $0\core_core_core_insn$next[31:0]$14176 + update \core_core_core_insn_type$next $0\core_core_core_insn_type$next[6:0]$14177 + update \core_core_core_is_32bit$next $0\core_core_core_is_32bit$next[0:0]$14178 + update \core_core_core_msr$next $0\core_core_core_msr$next[63:0]$14179 + update \core_core_core_oe$next $0\core_core_core_oe$next[0:0]$14180 + update \core_core_core_oe_ok$next $0\core_core_core_oe_ok$next[0:0]$14181 + update \core_core_core_rc$next $0\core_core_core_rc$next[0:0]$14182 + update \core_core_core_rc_ok$next $0\core_core_core_rc_ok$next[0:0]$14183 + update \core_core_core_trapaddr$next $0\core_core_core_trapaddr$next[12:0]$14184 + update \core_core_core_traptype$next $0\core_core_core_traptype$next[7:0]$14185 + update \core_core_cr_in1$next $0\core_core_cr_in1$next[6:0]$14186 + update \core_core_cr_in1_ok$next $0\core_core_cr_in1_ok$next[0:0]$14187 + update \core_core_cr_in2$1$next $0\core_core_cr_in2$1$next[6:0]$14188 + update \core_core_cr_in2$next $0\core_core_cr_in2$next[6:0]$14189 + update \core_core_cr_in2_ok$2$next $0\core_core_cr_in2_ok$2$next[0:0]$14190 + update \core_core_cr_in2_ok$next $0\core_core_cr_in2_ok$next[0:0]$14191 + update \core_core_cr_out$next $0\core_core_cr_out$next[6:0]$14192 + update \core_core_cr_wr_ok$next $0\core_core_cr_wr_ok$next[0:0]$14193 + update \core_core_ea$next $0\core_core_ea$next[6:0]$14194 + update \core_core_fast1$next $0\core_core_fast1$next[2:0]$14195 + update \core_core_fast1_ok$next $0\core_core_fast1_ok$next[0:0]$14196 + update \core_core_fast2$next $0\core_core_fast2$next[2:0]$14197 + update \core_core_fast2_ok$next $0\core_core_fast2_ok$next[0:0]$14198 + update \core_core_fasto1$next $0\core_core_fasto1$next[2:0]$14199 + update \core_core_fasto2$next $0\core_core_fasto2$next[2:0]$14200 + update \core_core_lk$next $0\core_core_lk$next[0:0]$14201 + update \core_core_reg1$next $0\core_core_reg1$next[6:0]$14202 + update \core_core_reg1_ok$next $0\core_core_reg1_ok$next[0:0]$14203 + update \core_core_reg2$next $0\core_core_reg2$next[6:0]$14204 + update \core_core_reg2_ok$next $0\core_core_reg2_ok$next[0:0]$14205 + update \core_core_reg3$next $0\core_core_reg3$next[6:0]$14206 + update \core_core_reg3_ok$next $0\core_core_reg3_ok$next[0:0]$14207 + update \core_core_rego$next $0\core_core_rego$next[6:0]$14208 + update \core_core_spr1$next $0\core_core_spr1$next[9:0]$14209 + update \core_core_spr1_ok$next $0\core_core_spr1_ok$next[0:0]$14210 + update \core_core_spro$next $0\core_core_spro$next[9:0]$14211 + update \core_core_xer_in$next $0\core_core_xer_in$next[2:0]$14212 + update \core_cr_out_ok$next $0\core_cr_out_ok$next[0:0]$14213 + update \core_ea_ok$next $0\core_ea_ok$next[0:0]$14214 + update \core_fasto1_ok$next $0\core_fasto1_ok$next[0:0]$14215 + update \core_fasto2_ok$next $0\core_fasto2_ok$next[0:0]$14216 + update \core_rego_ok$next $0\core_rego_ok$next[0:0]$14217 + update \core_spro_ok$next $0\core_spro_ok$next[0:0]$14218 + update \core_xer_out$next $0\core_xer_out$next[0:0]$14219 + end + attribute \src "libresoc.v:202859.3-202867.6" + process $proc$libresoc.v:202859$14424 + assign { } { } + assign { } { } + assign $0\dec2_cur_eint$next[0:0]$14425 $1\dec2_cur_eint$next[0:0]$14426 + attribute \src "libresoc.v:202860.5-202860.29" + switch \initial + attribute \src "libresoc.v:202860.9-202860.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dec2_cur_eint$next[0:0]$14426 1'0 + case + assign $1\dec2_cur_eint$next[0:0]$14426 \xics_icp_core_irq_o + end + sync always + update \dec2_cur_eint$next $0\dec2_cur_eint$next[0:0]$14425 + end + attribute \src "libresoc.v:202868.3-202877.6" + process $proc$libresoc.v:202868$14427 + assign { } { } + assign { } { } + assign $0\delay$next[1:0]$14428 $1\delay$next[1:0]$14429 + attribute \src "libresoc.v:202869.5-202869.29" + switch \initial + attribute \src "libresoc.v:202869.9-202869.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:200" + switch \$23 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\delay$next[1:0]$14429 \$25 [1:0] + case + assign $1\delay$next[1:0]$14429 \delay + end + sync always + update \delay$next $0\delay$next[1:0]$14428 + end + connect \$99 $not$libresoc.v:200541$13703_Y + connect \$101 $not$libresoc.v:200542$13704_Y + connect \$103 $and$libresoc.v:200543$13705_Y + connect \$105 $not$libresoc.v:200544$13706_Y + connect \$107 $not$libresoc.v:200545$13707_Y + connect \$109 $not$libresoc.v:200546$13708_Y + connect \$111 $and$libresoc.v:200547$13709_Y + connect \$113 $not$libresoc.v:200548$13710_Y + connect \$115 $not$libresoc.v:200549$13711_Y + connect \$117 $not$libresoc.v:200550$13712_Y + connect \$119 $and$libresoc.v:200551$13713_Y + connect \$121 $not$libresoc.v:200552$13714_Y + connect \$123 $not$libresoc.v:200553$13715_Y + connect \$125 $not$libresoc.v:200554$13716_Y + connect \$127 $and$libresoc.v:200555$13717_Y + connect \$129 $not$libresoc.v:200556$13718_Y + connect \$131 $not$libresoc.v:200557$13719_Y + connect \$133 $and$libresoc.v:200558$13720_Y + connect \$135 $not$libresoc.v:200559$13721_Y + connect \$137 $not$libresoc.v:200560$13722_Y + connect \$140 $mul$libresoc.v:200561$13723_Y + connect \$139 $shr$libresoc.v:200562$13724_Y [31:0] + connect \$144 $ternary$libresoc.v:200563$13725_Y + connect \$146 $add$libresoc.v:200564$13726_Y + connect \$148 $not$libresoc.v:200565$13727_Y + connect \$151 $mul$libresoc.v:200566$13728_Y + connect \$150 $shr$libresoc.v:200567$13729_Y [31:0] + connect \$156 $add$libresoc.v:200568$13730_Y + connect \$158 $mul$libresoc.v:200569$13731_Y + connect \$154 $shr$libresoc.v:200570$13732_Y [31:0] + connect \$161 $not$libresoc.v:200571$13733_Y + connect \$163 $not$libresoc.v:200572$13734_Y + connect \$165 $not$libresoc.v:200573$13735_Y + connect \$167 $not$libresoc.v:200574$13736_Y + connect \$171 $add$libresoc.v:200575$13737_Y + connect \$173 $mul$libresoc.v:200576$13738_Y + connect \$169 $shr$libresoc.v:200577$13739_Y [31:0] + connect \$176 $ne$libresoc.v:200578$13740_Y + connect \$179 $and$libresoc.v:200579$13741_Y + connect \$178 $reduce_or$libresoc.v:200580$13742_Y + connect \$182 $pos$libresoc.v:200581$13743_Y + connect \$184 $pos$libresoc.v:200582$13745_Y + connect \$186 $pos$libresoc.v:200583$13747_Y + connect \$190 $sub$libresoc.v:200584$13748_Y + connect \$193 $add$libresoc.v:200585$13749_Y + connect \$23 $ne$libresoc.v:200586$13750_Y + connect \$26 $sub$libresoc.v:200587$13751_Y + connect \$28 $or$libresoc.v:200588$13752_Y + connect \$30 $or$libresoc.v:200589$13753_Y + connect \$32 $ne$libresoc.v:200590$13754_Y + connect \$34 $not$libresoc.v:200591$13755_Y + connect \$36 $and$libresoc.v:200592$13756_Y + connect \$38 $not$libresoc.v:200593$13757_Y + connect \$40 $not$libresoc.v:200594$13758_Y + connect \$42 $not$libresoc.v:200595$13759_Y + connect \$44 $not$libresoc.v:200596$13760_Y + connect \$46 $not$libresoc.v:200597$13761_Y + connect \$48 $not$libresoc.v:200598$13762_Y + connect \$50 $not$libresoc.v:200599$13763_Y + connect \$52 $and$libresoc.v:200600$13764_Y + connect \$54 $not$libresoc.v:200601$13765_Y + connect \$56 $not$libresoc.v:200602$13766_Y + connect \$58 $and$libresoc.v:200603$13767_Y + connect \$60 $not$libresoc.v:200604$13768_Y + connect \$62 $not$libresoc.v:200605$13769_Y + connect \$64 $and$libresoc.v:200606$13770_Y + connect \$66 $not$libresoc.v:200607$13771_Y + connect \$68 $not$libresoc.v:200608$13772_Y + connect \$70 $and$libresoc.v:200609$13773_Y + connect \$72 $not$libresoc.v:200610$13774_Y + connect \$75 $add$libresoc.v:200611$13775_Y + connect \$77 $not$libresoc.v:200612$13776_Y + connect \$79 $not$libresoc.v:200613$13777_Y + connect \$81 $and$libresoc.v:200614$13778_Y + connect \$83 $not$libresoc.v:200615$13779_Y + connect \$85 $not$libresoc.v:200616$13780_Y + connect \$87 $not$libresoc.v:200617$13781_Y + connect \$89 $and$libresoc.v:200618$13782_Y + connect \$91 $not$libresoc.v:200619$13783_Y + connect \$93 $not$libresoc.v:200620$13784_Y + connect \$95 $not$libresoc.v:200621$13785_Y + connect \$97 $and$libresoc.v:200622$13786_Y + connect \$25 \$26 + connect \$74 \$75 + connect \$143 \$146 + connect \$155 \$156 + connect \$170 \$171 + connect \$189 \$190 + connect \$192 \$193 + connect \update_svstate 1'0 + connect \new_svstate_svstep 2'00 + connect \new_svstate_subvl 2'00 + connect \new_svstate_dststep 7'0000000 + connect \new_svstate_srcstep 7'0000000 + connect \new_svstate_vl 7'0000000 + connect \new_svstate_maxvl 7'0000000 + connect \dbg_core_dbg_msr \dec2_cur_msr + connect \dbg_core_dbg_pc \pc + connect \dbg_terminate_i \core_core_terminate_o + connect \pc_o \dec2_cur_pc + connect \core_cu_st__go_i \cu_st__rel_o_rise + connect \core_cu_ad__go_i \core_cu_ad__rel_o + connect \cu_st__rel_o_rise \$36 + connect \cu_st__rel_o_dly$next \core_cu_st__rel_o + connect \dec2_bigendian \core_bigendian_i + connect \busy_o \core_corebusy_o + connect \core_coresync_rst \ti_rst + connect \ti_rst \$32 + connect \por_clk \clk + connect { \xics_icp_ics_i_pri \xics_icp_ics_i_src } { \xics_ics_icp_o_pri \xics_ics_icp_o_src } +end +attribute \src "libresoc.v:202910.1-204097.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0" +attribute \generator "nMigen" +module \trap0 + attribute \src "libresoc.v:203642.3-203643.25" + wire $0\all_rd_dly[0:0] + attribute \src "libresoc.v:203640.3-203641.41" + wire $0\alu_done_dly[0:0] + attribute \src "libresoc.v:204000.3-204008.6" + wire $0\alu_l_r_alu$next[0:0]$14757 + attribute \src "libresoc.v:203568.3-203569.39" + wire $0\alu_l_r_alu[0:0] + attribute \src "libresoc.v:203823.3-203840.6" + wire width 64 $0\alu_trap0_trap_op__cia$next[63:0]$14683 + attribute \src "libresoc.v:203608.3-203609.61" + wire width 64 $0\alu_trap0_trap_op__cia[63:0] + attribute \src "libresoc.v:203823.3-203840.6" + wire width 13 $0\alu_trap0_trap_op__fn_unit$next[12:0]$14684 + attribute \src "libresoc.v:203602.3-203603.69" + wire width 13 $0\alu_trap0_trap_op__fn_unit[12:0] + attribute \src "libresoc.v:203823.3-203840.6" + wire width 32 $0\alu_trap0_trap_op__insn$next[31:0]$14685 + attribute \src "libresoc.v:203604.3-203605.63" + wire width 32 $0\alu_trap0_trap_op__insn[31:0] + attribute \src "libresoc.v:203823.3-203840.6" + wire width 7 $0\alu_trap0_trap_op__insn_type$next[6:0]$14686 + attribute \src "libresoc.v:203600.3-203601.73" + wire width 7 $0\alu_trap0_trap_op__insn_type[6:0] + attribute \src "libresoc.v:203823.3-203840.6" + wire $0\alu_trap0_trap_op__is_32bit$next[0:0]$14687 + attribute \src "libresoc.v:203610.3-203611.71" + wire $0\alu_trap0_trap_op__is_32bit[0:0] + attribute \src "libresoc.v:203823.3-203840.6" + wire width 8 $0\alu_trap0_trap_op__ldst_exc$next[7:0]$14688 + attribute \src "libresoc.v:203616.3-203617.71" + wire width 8 $0\alu_trap0_trap_op__ldst_exc[7:0] + attribute \src "libresoc.v:203823.3-203840.6" + wire width 64 $0\alu_trap0_trap_op__msr$next[63:0]$14689 + attribute \src "libresoc.v:203606.3-203607.61" + wire width 64 $0\alu_trap0_trap_op__msr[63:0] + attribute \src "libresoc.v:203823.3-203840.6" + wire width 13 $0\alu_trap0_trap_op__trapaddr$next[12:0]$14690 + attribute \src "libresoc.v:203614.3-203615.71" + wire width 13 $0\alu_trap0_trap_op__trapaddr[12:0] + attribute \src "libresoc.v:203823.3-203840.6" + wire width 8 $0\alu_trap0_trap_op__traptype$next[7:0]$14691 + attribute \src "libresoc.v:203612.3-203613.71" + wire width 8 $0\alu_trap0_trap_op__traptype[7:0] + attribute \src "libresoc.v:203991.3-203999.6" + wire $0\alui_l_r_alui$next[0:0]$14754 + attribute \src "libresoc.v:203570.3-203571.43" + wire $0\alui_l_r_alui[0:0] + attribute \src "libresoc.v:203841.3-203862.6" + wire width 64 $0\data_r0__o$next[63:0]$14702 + attribute \src "libresoc.v:203596.3-203597.37" + wire width 64 $0\data_r0__o[63:0] + attribute \src "libresoc.v:203841.3-203862.6" + wire $0\data_r0__o_ok$next[0:0]$14703 + attribute \src "libresoc.v:203598.3-203599.43" + wire $0\data_r0__o_ok[0:0] + attribute \src "libresoc.v:203863.3-203884.6" + wire width 64 $0\data_r1__fast1$next[63:0]$14710 + attribute \src "libresoc.v:203592.3-203593.45" + wire width 64 $0\data_r1__fast1[63:0] + attribute \src "libresoc.v:203863.3-203884.6" + wire $0\data_r1__fast1_ok$next[0:0]$14711 + attribute \src "libresoc.v:203594.3-203595.51" + wire $0\data_r1__fast1_ok[0:0] + attribute \src "libresoc.v:203885.3-203906.6" + wire width 64 $0\data_r2__fast2$next[63:0]$14718 + attribute \src "libresoc.v:203588.3-203589.45" + wire width 64 $0\data_r2__fast2[63:0] + attribute \src "libresoc.v:203885.3-203906.6" + wire $0\data_r2__fast2_ok$next[0:0]$14719 + attribute \src "libresoc.v:203590.3-203591.51" + wire $0\data_r2__fast2_ok[0:0] + attribute \src "libresoc.v:203907.3-203928.6" + wire width 64 $0\data_r3__nia$next[63:0]$14726 + attribute \src "libresoc.v:203584.3-203585.41" + wire width 64 $0\data_r3__nia[63:0] + attribute \src "libresoc.v:203907.3-203928.6" + wire $0\data_r3__nia_ok$next[0:0]$14727 + attribute \src "libresoc.v:203586.3-203587.47" + wire $0\data_r3__nia_ok[0:0] + attribute \src "libresoc.v:203929.3-203950.6" + wire width 64 $0\data_r4__msr$next[63:0]$14734 + attribute \src "libresoc.v:203580.3-203581.41" + wire width 64 $0\data_r4__msr[63:0] + attribute \src "libresoc.v:203929.3-203950.6" + wire $0\data_r4__msr_ok$next[0:0]$14735 + attribute \src "libresoc.v:203582.3-203583.47" + wire $0\data_r4__msr_ok[0:0] + attribute \src "libresoc.v:204009.3-204018.6" + wire width 64 $0\dest1_o[63:0] + attribute \src "libresoc.v:204019.3-204028.6" + wire width 64 $0\dest2_o[63:0] + attribute \src "libresoc.v:204029.3-204038.6" + wire width 64 $0\dest3_o[63:0] + attribute \src "libresoc.v:204039.3-204048.6" + wire width 64 $0\dest4_o[63:0] + attribute \src "libresoc.v:204049.3-204058.6" + wire width 64 $0\dest5_o[63:0] + attribute \src "libresoc.v:202911.7-202911.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:203778.3-203786.6" + wire $0\opc_l_r_opc$next[0:0]$14668 + attribute \src "libresoc.v:203626.3-203627.39" + wire $0\opc_l_r_opc[0:0] + attribute \src "libresoc.v:203769.3-203777.6" + wire $0\opc_l_s_opc$next[0:0]$14665 + attribute \src "libresoc.v:203628.3-203629.39" + wire $0\opc_l_s_opc[0:0] + attribute \src "libresoc.v:204059.3-204067.6" + wire width 5 $0\prev_wr_go$next[4:0]$14765 + attribute \src "libresoc.v:203638.3-203639.37" + wire width 5 $0\prev_wr_go[4:0] + attribute \src "libresoc.v:203723.3-203732.6" + wire $0\req_done[0:0] + attribute \src "libresoc.v:203814.3-203822.6" + wire width 5 $0\req_l_r_req$next[4:0]$14680 + attribute \src "libresoc.v:203618.3-203619.39" + wire width 5 $0\req_l_r_req[4:0] + attribute \src "libresoc.v:203805.3-203813.6" + wire width 5 $0\req_l_s_req$next[4:0]$14677 + attribute \src "libresoc.v:203620.3-203621.39" + wire width 5 $0\req_l_s_req[4:0] + attribute \src "libresoc.v:203742.3-203750.6" + wire $0\rok_l_r_rdok$next[0:0]$14656 + attribute \src "libresoc.v:203634.3-203635.41" + wire $0\rok_l_r_rdok[0:0] + attribute \src "libresoc.v:203733.3-203741.6" + wire $0\rok_l_s_rdok$next[0:0]$14653 + attribute \src "libresoc.v:203636.3-203637.41" + wire $0\rok_l_s_rdok[0:0] + attribute \src "libresoc.v:203760.3-203768.6" + wire $0\rst_l_r_rst$next[0:0]$14662 + attribute \src "libresoc.v:203630.3-203631.39" + wire $0\rst_l_r_rst[0:0] + attribute \src "libresoc.v:203751.3-203759.6" + wire $0\rst_l_s_rst$next[0:0]$14659 + attribute \src "libresoc.v:203632.3-203633.39" + wire $0\rst_l_s_rst[0:0] + attribute \src "libresoc.v:203796.3-203804.6" + wire width 4 $0\src_l_r_src$next[3:0]$14674 + attribute \src "libresoc.v:203622.3-203623.39" + wire width 4 $0\src_l_r_src[3:0] + attribute \src "libresoc.v:203787.3-203795.6" + wire width 4 $0\src_l_s_src$next[3:0]$14671 + attribute \src "libresoc.v:203624.3-203625.39" + wire width 4 $0\src_l_s_src[3:0] + attribute \src "libresoc.v:203951.3-203960.6" + wire width 64 $0\src_r0$next[63:0]$14742 + attribute \src "libresoc.v:203578.3-203579.29" + wire width 64 $0\src_r0[63:0] + attribute \src "libresoc.v:203961.3-203970.6" + wire width 64 $0\src_r1$next[63:0]$14745 + attribute \src "libresoc.v:203576.3-203577.29" + wire width 64 $0\src_r1[63:0] + attribute \src "libresoc.v:203971.3-203980.6" + wire width 64 $0\src_r2$next[63:0]$14748 + attribute \src "libresoc.v:203574.3-203575.29" + wire width 64 $0\src_r2[63:0] + attribute \src "libresoc.v:203981.3-203990.6" + wire width 64 $0\src_r3$next[63:0]$14751 + attribute \src "libresoc.v:203572.3-203573.29" + wire width 64 $0\src_r3[63:0] + attribute \src "libresoc.v:203037.7-203037.24" + wire $1\all_rd_dly[0:0] + attribute \src "libresoc.v:203047.7-203047.26" + wire $1\alu_done_dly[0:0] + attribute \src "libresoc.v:204000.3-204008.6" + wire $1\alu_l_r_alu$next[0:0]$14758 + attribute \src "libresoc.v:203055.7-203055.25" + wire $1\alu_l_r_alu[0:0] + attribute \src "libresoc.v:203823.3-203840.6" + wire width 64 $1\alu_trap0_trap_op__cia$next[63:0]$14692 + attribute \src "libresoc.v:203091.14-203091.59" + wire width 64 $1\alu_trap0_trap_op__cia[63:0] + attribute \src "libresoc.v:203823.3-203840.6" + wire width 13 $1\alu_trap0_trap_op__fn_unit$next[12:0]$14693 + attribute \src "libresoc.v:203109.14-203109.51" + wire width 13 $1\alu_trap0_trap_op__fn_unit[12:0] + attribute \src "libresoc.v:203823.3-203840.6" + wire width 32 $1\alu_trap0_trap_op__insn$next[31:0]$14694 + attribute \src "libresoc.v:203113.14-203113.45" + wire width 32 $1\alu_trap0_trap_op__insn[31:0] + attribute \src "libresoc.v:203823.3-203840.6" + wire width 7 $1\alu_trap0_trap_op__insn_type$next[6:0]$14695 + attribute \src "libresoc.v:203191.13-203191.49" + wire width 7 $1\alu_trap0_trap_op__insn_type[6:0] + attribute \src "libresoc.v:203823.3-203840.6" + wire $1\alu_trap0_trap_op__is_32bit$next[0:0]$14696 + attribute \src "libresoc.v:203195.7-203195.41" + wire $1\alu_trap0_trap_op__is_32bit[0:0] + attribute \src "libresoc.v:203823.3-203840.6" + wire width 8 $1\alu_trap0_trap_op__ldst_exc$next[7:0]$14697 + attribute \src "libresoc.v:203199.13-203199.48" + wire width 8 $1\alu_trap0_trap_op__ldst_exc[7:0] + attribute \src "libresoc.v:203823.3-203840.6" + wire width 64 $1\alu_trap0_trap_op__msr$next[63:0]$14698 + attribute \src "libresoc.v:203203.14-203203.59" + wire width 64 $1\alu_trap0_trap_op__msr[63:0] + attribute \src "libresoc.v:203823.3-203840.6" + wire width 13 $1\alu_trap0_trap_op__trapaddr$next[12:0]$14699 + attribute \src "libresoc.v:203207.14-203207.52" + wire width 13 $1\alu_trap0_trap_op__trapaddr[12:0] + attribute \src "libresoc.v:203823.3-203840.6" + wire width 8 $1\alu_trap0_trap_op__traptype$next[7:0]$14700 + attribute \src "libresoc.v:203211.13-203211.48" + wire width 8 $1\alu_trap0_trap_op__traptype[7:0] + attribute \src "libresoc.v:203991.3-203999.6" + wire $1\alui_l_r_alui$next[0:0]$14755 + attribute \src "libresoc.v:203217.7-203217.27" + wire $1\alui_l_r_alui[0:0] + attribute \src "libresoc.v:203841.3-203862.6" + wire width 64 $1\data_r0__o$next[63:0]$14704 + attribute \src "libresoc.v:203249.14-203249.47" + wire width 64 $1\data_r0__o[63:0] + attribute \src "libresoc.v:203841.3-203862.6" + wire $1\data_r0__o_ok$next[0:0]$14705 + attribute \src "libresoc.v:203253.7-203253.27" + wire $1\data_r0__o_ok[0:0] + attribute \src "libresoc.v:203863.3-203884.6" + wire width 64 $1\data_r1__fast1$next[63:0]$14712 + attribute \src "libresoc.v:203257.14-203257.51" + wire width 64 $1\data_r1__fast1[63:0] + attribute \src "libresoc.v:203863.3-203884.6" + wire $1\data_r1__fast1_ok$next[0:0]$14713 + attribute \src "libresoc.v:203261.7-203261.31" + wire $1\data_r1__fast1_ok[0:0] + attribute \src "libresoc.v:203885.3-203906.6" + wire width 64 $1\data_r2__fast2$next[63:0]$14720 + attribute \src "libresoc.v:203265.14-203265.51" + wire width 64 $1\data_r2__fast2[63:0] + attribute \src "libresoc.v:203885.3-203906.6" + wire $1\data_r2__fast2_ok$next[0:0]$14721 + attribute \src "libresoc.v:203269.7-203269.31" + wire $1\data_r2__fast2_ok[0:0] + attribute \src "libresoc.v:203907.3-203928.6" + wire width 64 $1\data_r3__nia$next[63:0]$14728 + attribute \src "libresoc.v:203273.14-203273.49" + wire width 64 $1\data_r3__nia[63:0] + attribute \src "libresoc.v:203907.3-203928.6" + wire $1\data_r3__nia_ok$next[0:0]$14729 + attribute \src "libresoc.v:203277.7-203277.29" + wire $1\data_r3__nia_ok[0:0] + attribute \src "libresoc.v:203929.3-203950.6" + wire width 64 $1\data_r4__msr$next[63:0]$14736 + attribute \src "libresoc.v:203281.14-203281.49" + wire width 64 $1\data_r4__msr[63:0] + attribute \src "libresoc.v:203929.3-203950.6" + wire $1\data_r4__msr_ok$next[0:0]$14737 + attribute \src "libresoc.v:203285.7-203285.29" + wire $1\data_r4__msr_ok[0:0] + attribute \src "libresoc.v:204009.3-204018.6" + wire width 64 $1\dest1_o[63:0] + attribute \src "libresoc.v:204019.3-204028.6" + wire width 64 $1\dest2_o[63:0] + attribute \src "libresoc.v:204029.3-204038.6" + wire width 64 $1\dest3_o[63:0] + attribute \src "libresoc.v:204039.3-204048.6" + wire width 64 $1\dest4_o[63:0] + attribute \src "libresoc.v:204049.3-204058.6" + wire width 64 $1\dest5_o[63:0] + attribute \src "libresoc.v:203778.3-203786.6" + wire $1\opc_l_r_opc$next[0:0]$14669 + attribute \src "libresoc.v:203316.7-203316.25" + wire $1\opc_l_r_opc[0:0] + attribute \src "libresoc.v:203769.3-203777.6" + wire $1\opc_l_s_opc$next[0:0]$14666 + attribute \src "libresoc.v:203320.7-203320.25" + wire $1\opc_l_s_opc[0:0] + attribute \src "libresoc.v:204059.3-204067.6" + wire width 5 $1\prev_wr_go$next[4:0]$14766 + attribute \src "libresoc.v:203430.13-203430.31" + wire width 5 $1\prev_wr_go[4:0] + attribute \src "libresoc.v:203723.3-203732.6" + wire $1\req_done[0:0] + attribute \src "libresoc.v:203814.3-203822.6" + wire width 5 $1\req_l_r_req$next[4:0]$14681 + attribute \src "libresoc.v:203438.13-203438.32" + wire width 5 $1\req_l_r_req[4:0] + attribute \src "libresoc.v:203805.3-203813.6" + wire width 5 $1\req_l_s_req$next[4:0]$14678 + attribute \src "libresoc.v:203442.13-203442.32" + wire width 5 $1\req_l_s_req[4:0] + attribute \src "libresoc.v:203742.3-203750.6" + wire $1\rok_l_r_rdok$next[0:0]$14657 + attribute \src "libresoc.v:203454.7-203454.26" + wire $1\rok_l_r_rdok[0:0] + attribute \src "libresoc.v:203733.3-203741.6" + wire $1\rok_l_s_rdok$next[0:0]$14654 + attribute \src "libresoc.v:203458.7-203458.26" + wire $1\rok_l_s_rdok[0:0] + attribute \src "libresoc.v:203760.3-203768.6" + wire $1\rst_l_r_rst$next[0:0]$14663 + attribute \src "libresoc.v:203462.7-203462.25" + wire $1\rst_l_r_rst[0:0] + attribute \src "libresoc.v:203751.3-203759.6" + wire $1\rst_l_s_rst$next[0:0]$14660 + attribute \src "libresoc.v:203466.7-203466.25" + wire $1\rst_l_s_rst[0:0] + attribute \src "libresoc.v:203796.3-203804.6" + wire width 4 $1\src_l_r_src$next[3:0]$14675 + attribute \src "libresoc.v:203482.13-203482.31" + wire width 4 $1\src_l_r_src[3:0] + attribute \src "libresoc.v:203787.3-203795.6" + wire width 4 $1\src_l_s_src$next[3:0]$14672 + attribute \src "libresoc.v:203486.13-203486.31" + wire width 4 $1\src_l_s_src[3:0] + attribute \src "libresoc.v:203951.3-203960.6" + wire width 64 $1\src_r0$next[63:0]$14743 + attribute \src "libresoc.v:203490.14-203490.43" + wire width 64 $1\src_r0[63:0] + attribute \src "libresoc.v:203961.3-203970.6" + wire width 64 $1\src_r1$next[63:0]$14746 + attribute \src "libresoc.v:203494.14-203494.43" + wire width 64 $1\src_r1[63:0] + attribute \src "libresoc.v:203971.3-203980.6" + wire width 64 $1\src_r2$next[63:0]$14749 + attribute \src "libresoc.v:203498.14-203498.43" + wire width 64 $1\src_r2[63:0] + attribute \src "libresoc.v:203981.3-203990.6" + wire width 64 $1\src_r3$next[63:0]$14752 + attribute \src "libresoc.v:203502.14-203502.43" + wire width 64 $1\src_r3[63:0] + attribute \src "libresoc.v:203841.3-203862.6" + wire width 64 $2\data_r0__o$next[63:0]$14706 + attribute \src "libresoc.v:203841.3-203862.6" + wire $2\data_r0__o_ok$next[0:0]$14707 + attribute \src "libresoc.v:203863.3-203884.6" + wire width 64 $2\data_r1__fast1$next[63:0]$14714 + attribute \src "libresoc.v:203863.3-203884.6" + wire $2\data_r1__fast1_ok$next[0:0]$14715 + attribute \src "libresoc.v:203885.3-203906.6" + wire width 64 $2\data_r2__fast2$next[63:0]$14722 + attribute \src "libresoc.v:203885.3-203906.6" + wire $2\data_r2__fast2_ok$next[0:0]$14723 + attribute \src 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connect \Y $or$libresoc.v:203545$14590_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" + cell $or $or$libresoc.v:203546$14591 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_issue_i + connect \B \cu_go_die_i + connect \Y $or$libresoc.v:203546$14591_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" + cell $or $or$libresoc.v:203547$14592 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \cu_wr__go_i + connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } + connect \Y $or$libresoc.v:203547$14592_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" + cell $or $or$libresoc.v:203548$14593 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \cu_rd__go_i + connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } + connect \Y $or$libresoc.v:203548$14593_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" + cell $or $or$libresoc.v:203552$14597 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \reset_w + connect \B \prev_wr_go + connect \Y $or$libresoc.v:203552$14597_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $or $or$libresoc.v:203562$14607 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \$6 + connect \B \cu_rd__go_i + connect \Y $or$libresoc.v:203562$14607_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $reduce_and $reduce_and$libresoc.v:203507$14552 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $reduce_and$libresoc.v:203507$14552_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $reduce_or $reduce_or$libresoc.v:203529$14574 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \$27 + connect \Y $reduce_or$libresoc.v:203529$14574_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $reduce_or $reduce_or$libresoc.v:203532$14577 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \cu_wr__go_i + connect \Y $reduce_or$libresoc.v:203532$14577_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $reduce_or $reduce_or$libresoc.v:203533$14578 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \prev_wr_go + connect \Y $reduce_or$libresoc.v:203533$14578_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" + cell $mux $ternary$libresoc.v:203558$14603 + parameter \WIDTH 64 + connect \A \src_r0 + connect \B \src1_i + connect \S \src_l_q_src [0] + connect \Y $ternary$libresoc.v:203558$14603_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" + cell $mux $ternary$libresoc.v:203559$14604 + parameter \WIDTH 64 + connect \A \src_r1 + connect \B \src2_i + connect \S \src_l_q_src [1] + connect \Y $ternary$libresoc.v:203559$14604_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" + cell $mux $ternary$libresoc.v:203560$14605 + parameter \WIDTH 64 + connect \A \src_r2 + connect \B \src3_i + connect \S \src_l_q_src [2] + connect \Y $ternary$libresoc.v:203560$14605_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" + cell $mux $ternary$libresoc.v:203561$14606 + parameter \WIDTH 64 + connect \A \src_r3 + connect \B \src4_i + connect \S \src_l_q_src [3] + connect \Y $ternary$libresoc.v:203561$14606_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:203644.14-203650.4" + cell \alu_l$45 \alu_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_alu \alu_l_q_alu + connect \r_alu \alu_l_r_alu + connect \s_alu \alu_l_s_alu + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:203651.13-203681.4" + cell \alu_trap0 \alu_trap0 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \fast1 \alu_trap0_fast1 + connect \fast1$1 \alu_trap0_fast1$1 + connect \fast1_ok \fast1_ok + connect \fast2 \alu_trap0_fast2 + connect \fast2$2 \alu_trap0_fast2$2 + connect \fast2_ok \fast2_ok + connect \msr \alu_trap0_msr + connect \msr_ok \msr_ok + connect \n_ready_i \alu_trap0_n_ready_i + connect \n_valid_o \alu_trap0_n_valid_o + connect \nia \alu_trap0_nia + connect \nia_ok \nia_ok + connect \o \alu_trap0_o + connect \o_ok \o_ok + connect \p_ready_o \alu_trap0_p_ready_o + connect \p_valid_i \alu_trap0_p_valid_i + connect \ra \alu_trap0_ra + connect \rb \alu_trap0_rb + connect \trap_op__cia \alu_trap0_trap_op__cia + connect \trap_op__fn_unit \alu_trap0_trap_op__fn_unit + connect \trap_op__insn \alu_trap0_trap_op__insn + connect \trap_op__insn_type \alu_trap0_trap_op__insn_type + connect \trap_op__is_32bit \alu_trap0_trap_op__is_32bit + connect \trap_op__ldst_exc \alu_trap0_trap_op__ldst_exc + connect \trap_op__msr \alu_trap0_trap_op__msr + connect \trap_op__trapaddr \alu_trap0_trap_op__trapaddr + connect \trap_op__traptype \alu_trap0_trap_op__traptype + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:203682.15-203688.4" + cell \alui_l$44 \alui_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_alui \alui_l_q_alui + connect \r_alui \alui_l_r_alui + connect \s_alui \alui_l_s_alui + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:203689.14-203695.4" + cell \opc_l$40 \opc_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_opc \opc_l_q_opc + connect \r_opc \opc_l_r_opc + connect \s_opc \opc_l_s_opc + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:203696.14-203702.4" + cell \req_l$41 \req_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_req \req_l_q_req + connect \r_req \req_l_r_req + connect \s_req \req_l_s_req + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:203703.14-203709.4" + cell \rok_l$43 \rok_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_rdok \rok_l_q_rdok + connect \r_rdok \rok_l_r_rdok + connect \s_rdok \rok_l_s_rdok + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:203710.14-203715.4" + cell \rst_l$42 \rst_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \r_rst \rst_l_r_rst + connect \s_rst \rst_l_s_rst + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:203716.14-203722.4" + cell \src_l$39 \src_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_src \src_l_q_src + connect \r_src \src_l_r_src + connect \s_src \src_l_s_src + end + attribute \src "libresoc.v:202911.7-202911.20" + process $proc$libresoc.v:202911$14767 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:203037.7-203037.24" + process $proc$libresoc.v:203037$14768 + assign { } { } + assign $1\all_rd_dly[0:0] 1'0 + sync always + sync init + update \all_rd_dly $1\all_rd_dly[0:0] + end + attribute \src "libresoc.v:203047.7-203047.26" + process $proc$libresoc.v:203047$14769 + assign { } { } + assign $1\alu_done_dly[0:0] 1'0 + sync always + sync init + update \alu_done_dly $1\alu_done_dly[0:0] + end + attribute \src "libresoc.v:203055.7-203055.25" + process $proc$libresoc.v:203055$14770 + assign { } { } + assign $1\alu_l_r_alu[0:0] 1'1 + sync always + sync init + update \alu_l_r_alu $1\alu_l_r_alu[0:0] + end + attribute \src "libresoc.v:203091.14-203091.59" + process $proc$libresoc.v:203091$14771 + assign { } { } + assign $1\alu_trap0_trap_op__cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \alu_trap0_trap_op__cia $1\alu_trap0_trap_op__cia[63:0] + end + attribute \src "libresoc.v:203109.14-203109.51" + process $proc$libresoc.v:203109$14772 + assign { } { } + assign $1\alu_trap0_trap_op__fn_unit[12:0] 13'0000000000000 + sync always + sync init + update \alu_trap0_trap_op__fn_unit $1\alu_trap0_trap_op__fn_unit[12:0] + end + attribute \src "libresoc.v:203113.14-203113.45" + process $proc$libresoc.v:203113$14773 + assign { } { } + assign $1\alu_trap0_trap_op__insn[31:0] 0 + sync always + sync init + update \alu_trap0_trap_op__insn $1\alu_trap0_trap_op__insn[31:0] + end + attribute \src "libresoc.v:203191.13-203191.49" + process $proc$libresoc.v:203191$14774 + assign { } { } + assign $1\alu_trap0_trap_op__insn_type[6:0] 7'0000000 + sync always + sync init + update \alu_trap0_trap_op__insn_type $1\alu_trap0_trap_op__insn_type[6:0] + end + attribute \src "libresoc.v:203195.7-203195.41" + process $proc$libresoc.v:203195$14775 + assign { } { } + assign $1\alu_trap0_trap_op__is_32bit[0:0] 1'0 + sync always + sync init + update \alu_trap0_trap_op__is_32bit $1\alu_trap0_trap_op__is_32bit[0:0] + end + attribute \src "libresoc.v:203199.13-203199.48" + process $proc$libresoc.v:203199$14776 + assign { } { } + assign $1\alu_trap0_trap_op__ldst_exc[7:0] 8'00000000 + sync always + sync init + update \alu_trap0_trap_op__ldst_exc $1\alu_trap0_trap_op__ldst_exc[7:0] + end + attribute \src "libresoc.v:203203.14-203203.59" + process $proc$libresoc.v:203203$14777 + assign { } { } + assign $1\alu_trap0_trap_op__msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \alu_trap0_trap_op__msr $1\alu_trap0_trap_op__msr[63:0] + end + attribute \src "libresoc.v:203207.14-203207.52" + process $proc$libresoc.v:203207$14778 + assign { } { } + assign $1\alu_trap0_trap_op__trapaddr[12:0] 13'0000000000000 + sync always + sync init + update \alu_trap0_trap_op__trapaddr $1\alu_trap0_trap_op__trapaddr[12:0] + end + attribute \src "libresoc.v:203211.13-203211.48" + process $proc$libresoc.v:203211$14779 + assign { } { } + assign $1\alu_trap0_trap_op__traptype[7:0] 8'00000000 + sync always + sync init + update \alu_trap0_trap_op__traptype $1\alu_trap0_trap_op__traptype[7:0] + end + attribute \src "libresoc.v:203217.7-203217.27" + process $proc$libresoc.v:203217$14780 + assign { } { } + assign $1\alui_l_r_alui[0:0] 1'1 + sync always + sync init + update \alui_l_r_alui $1\alui_l_r_alui[0:0] + end + attribute \src "libresoc.v:203249.14-203249.47" + process $proc$libresoc.v:203249$14781 + assign { } { } + assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \data_r0__o $1\data_r0__o[63:0] + end + attribute \src "libresoc.v:203253.7-203253.27" + process $proc$libresoc.v:203253$14782 + assign { } { } + assign $1\data_r0__o_ok[0:0] 1'0 + sync always + sync init + update \data_r0__o_ok $1\data_r0__o_ok[0:0] + end + attribute \src "libresoc.v:203257.14-203257.51" + process $proc$libresoc.v:203257$14783 + assign { } { } + assign $1\data_r1__fast1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \data_r1__fast1 $1\data_r1__fast1[63:0] + end + attribute \src "libresoc.v:203261.7-203261.31" + process $proc$libresoc.v:203261$14784 + assign { } { } + assign $1\data_r1__fast1_ok[0:0] 1'0 + sync always + sync init + update \data_r1__fast1_ok $1\data_r1__fast1_ok[0:0] + end + attribute \src "libresoc.v:203265.14-203265.51" + process $proc$libresoc.v:203265$14785 + assign { } { } + assign $1\data_r2__fast2[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \data_r2__fast2 $1\data_r2__fast2[63:0] + end + attribute \src "libresoc.v:203269.7-203269.31" + process $proc$libresoc.v:203269$14786 + assign { } { } + assign $1\data_r2__fast2_ok[0:0] 1'0 + sync always + sync init + update \data_r2__fast2_ok $1\data_r2__fast2_ok[0:0] + end + attribute \src "libresoc.v:203273.14-203273.49" + process $proc$libresoc.v:203273$14787 + assign { } { } + assign $1\data_r3__nia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \data_r3__nia $1\data_r3__nia[63:0] + end + attribute \src "libresoc.v:203277.7-203277.29" + process $proc$libresoc.v:203277$14788 + assign { } { } + assign $1\data_r3__nia_ok[0:0] 1'0 + sync always + sync init + update \data_r3__nia_ok $1\data_r3__nia_ok[0:0] + end + attribute \src "libresoc.v:203281.14-203281.49" + process $proc$libresoc.v:203281$14789 + assign { } { } + assign $1\data_r4__msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \data_r4__msr $1\data_r4__msr[63:0] + end + attribute \src "libresoc.v:203285.7-203285.29" + process $proc$libresoc.v:203285$14790 + assign { } { } + assign $1\data_r4__msr_ok[0:0] 1'0 + sync always + sync init + update \data_r4__msr_ok $1\data_r4__msr_ok[0:0] + end + attribute \src "libresoc.v:203316.7-203316.25" + process $proc$libresoc.v:203316$14791 + assign { } { } + assign $1\opc_l_r_opc[0:0] 1'1 + sync always + sync init + update \opc_l_r_opc $1\opc_l_r_opc[0:0] + end + attribute \src "libresoc.v:203320.7-203320.25" + process $proc$libresoc.v:203320$14792 + assign { } { } + assign $1\opc_l_s_opc[0:0] 1'0 + sync always + sync init + update \opc_l_s_opc $1\opc_l_s_opc[0:0] + end + attribute \src "libresoc.v:203430.13-203430.31" + process $proc$libresoc.v:203430$14793 + assign { } { } + assign $1\prev_wr_go[4:0] 5'00000 + sync always + sync init + update \prev_wr_go $1\prev_wr_go[4:0] + end + attribute \src "libresoc.v:203438.13-203438.32" + process $proc$libresoc.v:203438$14794 + assign { } { } + assign $1\req_l_r_req[4:0] 5'11111 + sync always + sync init + update \req_l_r_req $1\req_l_r_req[4:0] + end + attribute \src "libresoc.v:203442.13-203442.32" + process $proc$libresoc.v:203442$14795 + assign { } { } + assign $1\req_l_s_req[4:0] 5'00000 + sync always + sync init + update \req_l_s_req $1\req_l_s_req[4:0] + end + attribute \src "libresoc.v:203454.7-203454.26" + process $proc$libresoc.v:203454$14796 + assign { } { } + assign $1\rok_l_r_rdok[0:0] 1'1 + sync always + sync init + update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] + end + attribute \src "libresoc.v:203458.7-203458.26" + process $proc$libresoc.v:203458$14797 + assign { } { } + assign $1\rok_l_s_rdok[0:0] 1'0 + sync always + sync init + update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] + end + attribute \src "libresoc.v:203462.7-203462.25" + process $proc$libresoc.v:203462$14798 + assign { } { } + assign $1\rst_l_r_rst[0:0] 1'1 + sync always + sync init + update \rst_l_r_rst $1\rst_l_r_rst[0:0] + end + attribute \src "libresoc.v:203466.7-203466.25" + process $proc$libresoc.v:203466$14799 + assign { } { } + assign $1\rst_l_s_rst[0:0] 1'0 + sync always + sync init + update \rst_l_s_rst $1\rst_l_s_rst[0:0] + end + attribute \src "libresoc.v:203482.13-203482.31" + process $proc$libresoc.v:203482$14800 + assign { } { } + assign $1\src_l_r_src[3:0] 4'1111 + sync always + sync init + update \src_l_r_src $1\src_l_r_src[3:0] + end + attribute \src "libresoc.v:203486.13-203486.31" + process $proc$libresoc.v:203486$14801 + assign { } { } + assign $1\src_l_s_src[3:0] 4'0000 + sync always + sync init + update \src_l_s_src $1\src_l_s_src[3:0] + end + attribute \src "libresoc.v:203490.14-203490.43" + process $proc$libresoc.v:203490$14802 + assign { } { } + assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \src_r0 $1\src_r0[63:0] + end + attribute \src "libresoc.v:203494.14-203494.43" + process $proc$libresoc.v:203494$14803 + assign { } { } + assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \src_r1 $1\src_r1[63:0] + end + attribute \src "libresoc.v:203498.14-203498.43" + process $proc$libresoc.v:203498$14804 + assign { } { } + assign $1\src_r2[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \src_r2 $1\src_r2[63:0] + end + attribute \src "libresoc.v:203502.14-203502.43" + process $proc$libresoc.v:203502$14805 + assign { } { } + assign $1\src_r3[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \src_r3 $1\src_r3[63:0] + end + attribute \src "libresoc.v:203568.3-203569.39" + process $proc$libresoc.v:203568$14613 + assign { } { } + assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next + sync posedge \coresync_clk + update \alu_l_r_alu $0\alu_l_r_alu[0:0] + end + attribute \src "libresoc.v:203570.3-203571.43" + process $proc$libresoc.v:203570$14614 + assign { } { } + assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next + sync posedge \coresync_clk + update \alui_l_r_alui $0\alui_l_r_alui[0:0] + end + attribute \src "libresoc.v:203572.3-203573.29" + process $proc$libresoc.v:203572$14615 + assign { } { } + assign $0\src_r3[63:0] \src_r3$next + sync posedge \coresync_clk + update \src_r3 $0\src_r3[63:0] + end + attribute \src "libresoc.v:203574.3-203575.29" + process $proc$libresoc.v:203574$14616 + assign { } { } + assign $0\src_r2[63:0] \src_r2$next + sync posedge \coresync_clk + update \src_r2 $0\src_r2[63:0] + end + attribute \src "libresoc.v:203576.3-203577.29" + process $proc$libresoc.v:203576$14617 + assign { } { } + assign $0\src_r1[63:0] \src_r1$next + sync posedge \coresync_clk + update \src_r1 $0\src_r1[63:0] + end + attribute \src "libresoc.v:203578.3-203579.29" + process $proc$libresoc.v:203578$14618 + assign { } { } + assign $0\src_r0[63:0] \src_r0$next + sync posedge \coresync_clk + update \src_r0 $0\src_r0[63:0] + end + attribute \src "libresoc.v:203580.3-203581.41" + process $proc$libresoc.v:203580$14619 + assign { } { } + assign $0\data_r4__msr[63:0] \data_r4__msr$next + sync posedge \coresync_clk + update \data_r4__msr $0\data_r4__msr[63:0] + end + attribute \src "libresoc.v:203582.3-203583.47" + process $proc$libresoc.v:203582$14620 + assign { } { } + assign $0\data_r4__msr_ok[0:0] \data_r4__msr_ok$next + sync posedge \coresync_clk + update \data_r4__msr_ok $0\data_r4__msr_ok[0:0] + end + attribute \src "libresoc.v:203584.3-203585.41" + process $proc$libresoc.v:203584$14621 + assign { } { } + assign $0\data_r3__nia[63:0] \data_r3__nia$next + sync posedge \coresync_clk + update \data_r3__nia $0\data_r3__nia[63:0] + end + attribute \src "libresoc.v:203586.3-203587.47" + process $proc$libresoc.v:203586$14622 + assign { } { } + assign $0\data_r3__nia_ok[0:0] \data_r3__nia_ok$next + sync posedge \coresync_clk + update \data_r3__nia_ok $0\data_r3__nia_ok[0:0] + end + attribute \src "libresoc.v:203588.3-203589.45" + process $proc$libresoc.v:203588$14623 + assign { } { } + assign $0\data_r2__fast2[63:0] \data_r2__fast2$next + sync posedge \coresync_clk + update \data_r2__fast2 $0\data_r2__fast2[63:0] + end + attribute \src "libresoc.v:203590.3-203591.51" + process $proc$libresoc.v:203590$14624 + assign { } { } + assign $0\data_r2__fast2_ok[0:0] \data_r2__fast2_ok$next + sync posedge \coresync_clk + update \data_r2__fast2_ok $0\data_r2__fast2_ok[0:0] + end + attribute \src "libresoc.v:203592.3-203593.45" + process $proc$libresoc.v:203592$14625 + assign { } { } + assign $0\data_r1__fast1[63:0] \data_r1__fast1$next + sync posedge \coresync_clk + update \data_r1__fast1 $0\data_r1__fast1[63:0] + end + attribute \src "libresoc.v:203594.3-203595.51" + process $proc$libresoc.v:203594$14626 + assign { } { } + assign $0\data_r1__fast1_ok[0:0] \data_r1__fast1_ok$next + sync posedge \coresync_clk + update \data_r1__fast1_ok $0\data_r1__fast1_ok[0:0] + end + attribute \src "libresoc.v:203596.3-203597.37" + process $proc$libresoc.v:203596$14627 + assign { } { } + assign $0\data_r0__o[63:0] \data_r0__o$next + sync posedge \coresync_clk + update \data_r0__o $0\data_r0__o[63:0] + end + attribute \src "libresoc.v:203598.3-203599.43" + process $proc$libresoc.v:203598$14628 + assign { } { } + assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next + sync posedge \coresync_clk + update \data_r0__o_ok $0\data_r0__o_ok[0:0] + end + attribute \src "libresoc.v:203600.3-203601.73" + process $proc$libresoc.v:203600$14629 + assign { } { } + assign $0\alu_trap0_trap_op__insn_type[6:0] \alu_trap0_trap_op__insn_type$next + sync posedge \coresync_clk + update \alu_trap0_trap_op__insn_type $0\alu_trap0_trap_op__insn_type[6:0] + end + attribute \src "libresoc.v:203602.3-203603.69" + process $proc$libresoc.v:203602$14630 + assign { } { } + assign $0\alu_trap0_trap_op__fn_unit[12:0] \alu_trap0_trap_op__fn_unit$next + sync posedge \coresync_clk + update \alu_trap0_trap_op__fn_unit $0\alu_trap0_trap_op__fn_unit[12:0] + end + attribute \src "libresoc.v:203604.3-203605.63" + process $proc$libresoc.v:203604$14631 + assign { } { } + assign $0\alu_trap0_trap_op__insn[31:0] \alu_trap0_trap_op__insn$next + sync posedge \coresync_clk + update \alu_trap0_trap_op__insn $0\alu_trap0_trap_op__insn[31:0] + end + attribute \src "libresoc.v:203606.3-203607.61" + process $proc$libresoc.v:203606$14632 + assign { } { } + assign $0\alu_trap0_trap_op__msr[63:0] \alu_trap0_trap_op__msr$next + sync posedge \coresync_clk + update \alu_trap0_trap_op__msr $0\alu_trap0_trap_op__msr[63:0] + end + attribute \src "libresoc.v:203608.3-203609.61" + process $proc$libresoc.v:203608$14633 + assign { } { } + assign $0\alu_trap0_trap_op__cia[63:0] \alu_trap0_trap_op__cia$next + sync posedge \coresync_clk + update \alu_trap0_trap_op__cia $0\alu_trap0_trap_op__cia[63:0] + end + attribute \src "libresoc.v:203610.3-203611.71" + process $proc$libresoc.v:203610$14634 + assign { } { } + assign $0\alu_trap0_trap_op__is_32bit[0:0] \alu_trap0_trap_op__is_32bit$next + sync posedge \coresync_clk + update \alu_trap0_trap_op__is_32bit $0\alu_trap0_trap_op__is_32bit[0:0] + end + attribute \src "libresoc.v:203612.3-203613.71" + process $proc$libresoc.v:203612$14635 + assign { } { } + assign $0\alu_trap0_trap_op__traptype[7:0] \alu_trap0_trap_op__traptype$next + sync posedge \coresync_clk + update \alu_trap0_trap_op__traptype $0\alu_trap0_trap_op__traptype[7:0] + end + attribute \src "libresoc.v:203614.3-203615.71" + process $proc$libresoc.v:203614$14636 + assign { } { } + assign $0\alu_trap0_trap_op__trapaddr[12:0] \alu_trap0_trap_op__trapaddr$next + sync posedge \coresync_clk + update \alu_trap0_trap_op__trapaddr $0\alu_trap0_trap_op__trapaddr[12:0] + end + attribute \src "libresoc.v:203616.3-203617.71" + process $proc$libresoc.v:203616$14637 + assign { } { } + assign $0\alu_trap0_trap_op__ldst_exc[7:0] \alu_trap0_trap_op__ldst_exc$next + sync posedge \coresync_clk + update \alu_trap0_trap_op__ldst_exc $0\alu_trap0_trap_op__ldst_exc[7:0] + end + attribute \src "libresoc.v:203618.3-203619.39" + process $proc$libresoc.v:203618$14638 + assign { } { } + assign $0\req_l_r_req[4:0] \req_l_r_req$next + sync posedge \coresync_clk + update \req_l_r_req $0\req_l_r_req[4:0] + end + attribute \src "libresoc.v:203620.3-203621.39" + process $proc$libresoc.v:203620$14639 + assign { } { } + assign $0\req_l_s_req[4:0] \req_l_s_req$next + sync posedge \coresync_clk + update \req_l_s_req $0\req_l_s_req[4:0] + end + attribute \src "libresoc.v:203622.3-203623.39" + process $proc$libresoc.v:203622$14640 + assign { } { } + assign $0\src_l_r_src[3:0] \src_l_r_src$next + sync posedge \coresync_clk + update \src_l_r_src $0\src_l_r_src[3:0] + end + attribute \src "libresoc.v:203624.3-203625.39" + process $proc$libresoc.v:203624$14641 + assign { } { } + assign $0\src_l_s_src[3:0] \src_l_s_src$next + sync posedge \coresync_clk + update \src_l_s_src $0\src_l_s_src[3:0] + end + attribute \src "libresoc.v:203626.3-203627.39" + process $proc$libresoc.v:203626$14642 + assign { } { } + assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next + sync posedge \coresync_clk + update \opc_l_r_opc $0\opc_l_r_opc[0:0] + end + attribute \src "libresoc.v:203628.3-203629.39" + process $proc$libresoc.v:203628$14643 + assign { } { } + assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next + sync posedge \coresync_clk + update \opc_l_s_opc $0\opc_l_s_opc[0:0] + end + attribute \src "libresoc.v:203630.3-203631.39" + process $proc$libresoc.v:203630$14644 + assign { } { } + assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next + sync posedge \coresync_clk + update \rst_l_r_rst $0\rst_l_r_rst[0:0] + end + attribute \src "libresoc.v:203632.3-203633.39" + process $proc$libresoc.v:203632$14645 + assign { } { } + assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next + sync posedge \coresync_clk + update \rst_l_s_rst $0\rst_l_s_rst[0:0] + end + attribute \src "libresoc.v:203634.3-203635.41" + process $proc$libresoc.v:203634$14646 + assign { } { } + assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next + sync posedge \coresync_clk + update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] + end + attribute \src "libresoc.v:203636.3-203637.41" + process $proc$libresoc.v:203636$14647 + assign { } { } + assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next + sync posedge \coresync_clk + update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] + end + attribute \src "libresoc.v:203638.3-203639.37" + process $proc$libresoc.v:203638$14648 + assign { } { } + assign $0\prev_wr_go[4:0] \prev_wr_go$next + sync posedge \coresync_clk + update \prev_wr_go $0\prev_wr_go[4:0] + end + attribute \src "libresoc.v:203640.3-203641.41" + process $proc$libresoc.v:203640$14649 + assign { } { } + assign $0\alu_done_dly[0:0] \alu_trap0_n_valid_o + sync posedge \coresync_clk + update \alu_done_dly $0\alu_done_dly[0:0] + end + attribute \src "libresoc.v:203642.3-203643.25" + process $proc$libresoc.v:203642$14650 + assign { } { } + assign $0\all_rd_dly[0:0] \$11 + sync posedge \coresync_clk + update \all_rd_dly $0\all_rd_dly[0:0] + end + attribute \src "libresoc.v:203723.3-203732.6" + process $proc$libresoc.v:203723$14651 + assign { } { } + assign { } { } + assign $0\req_done[0:0] $1\req_done[0:0] + attribute \src "libresoc.v:203724.5-203724.29" + switch \initial + attribute \src "libresoc.v:203724.9-203724.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + switch \$55 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\req_done[0:0] 1'1 + case + assign $1\req_done[0:0] \$47 + end + sync always + update \req_done $0\req_done[0:0] + end + attribute \src "libresoc.v:203733.3-203741.6" + process $proc$libresoc.v:203733$14652 + assign { } { } + assign { } { } + assign $0\rok_l_s_rdok$next[0:0]$14653 $1\rok_l_s_rdok$next[0:0]$14654 + attribute \src "libresoc.v:203734.5-203734.29" + switch \initial + attribute \src "libresoc.v:203734.9-203734.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rok_l_s_rdok$next[0:0]$14654 1'0 + case + assign $1\rok_l_s_rdok$next[0:0]$14654 \cu_issue_i + end + sync always + update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$14653 + end + attribute \src "libresoc.v:203742.3-203750.6" + process $proc$libresoc.v:203742$14655 + assign { } { } + assign { } { } + assign $0\rok_l_r_rdok$next[0:0]$14656 $1\rok_l_r_rdok$next[0:0]$14657 + attribute \src "libresoc.v:203743.5-203743.29" + switch \initial + attribute \src "libresoc.v:203743.9-203743.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rok_l_r_rdok$next[0:0]$14657 1'1 + case + assign $1\rok_l_r_rdok$next[0:0]$14657 \$65 + end + sync always + update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$14656 + end + attribute \src "libresoc.v:203751.3-203759.6" + process $proc$libresoc.v:203751$14658 + assign { } { } + assign { } { } + assign $0\rst_l_s_rst$next[0:0]$14659 $1\rst_l_s_rst$next[0:0]$14660 + attribute \src "libresoc.v:203752.5-203752.29" + switch \initial + attribute \src "libresoc.v:203752.9-203752.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rst_l_s_rst$next[0:0]$14660 1'0 + case + assign $1\rst_l_s_rst$next[0:0]$14660 \all_rd + end + sync always + update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$14659 + end + attribute \src "libresoc.v:203760.3-203768.6" + process $proc$libresoc.v:203760$14661 + assign { } { } + assign { } { } + assign $0\rst_l_r_rst$next[0:0]$14662 $1\rst_l_r_rst$next[0:0]$14663 + attribute \src "libresoc.v:203761.5-203761.29" + switch \initial + attribute \src "libresoc.v:203761.9-203761.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rst_l_r_rst$next[0:0]$14663 1'1 + case + assign $1\rst_l_r_rst$next[0:0]$14663 \rst_r + end + sync always + update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$14662 + end + attribute \src "libresoc.v:203769.3-203777.6" + process $proc$libresoc.v:203769$14664 + assign { } { } + assign { } { } + assign $0\opc_l_s_opc$next[0:0]$14665 $1\opc_l_s_opc$next[0:0]$14666 + attribute \src "libresoc.v:203770.5-203770.29" + switch \initial + attribute \src "libresoc.v:203770.9-203770.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\opc_l_s_opc$next[0:0]$14666 1'0 + case + assign $1\opc_l_s_opc$next[0:0]$14666 \cu_issue_i + end + sync always + update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$14665 + end + attribute \src "libresoc.v:203778.3-203786.6" + process $proc$libresoc.v:203778$14667 + assign { } { } + assign { } { } + assign $0\opc_l_r_opc$next[0:0]$14668 $1\opc_l_r_opc$next[0:0]$14669 + attribute \src "libresoc.v:203779.5-203779.29" + switch \initial + attribute \src "libresoc.v:203779.9-203779.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\opc_l_r_opc$next[0:0]$14669 1'1 + case + assign $1\opc_l_r_opc$next[0:0]$14669 \req_done + end + sync always + update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$14668 + end + attribute \src "libresoc.v:203787.3-203795.6" + process $proc$libresoc.v:203787$14670 + assign { } { } + assign { } { } + assign $0\src_l_s_src$next[3:0]$14671 $1\src_l_s_src$next[3:0]$14672 + attribute \src "libresoc.v:203788.5-203788.29" + switch \initial + attribute \src "libresoc.v:203788.9-203788.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_l_s_src$next[3:0]$14672 4'0000 + case + assign $1\src_l_s_src$next[3:0]$14672 { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i } + end + sync always + update \src_l_s_src$next $0\src_l_s_src$next[3:0]$14671 + end + attribute \src "libresoc.v:203796.3-203804.6" + process $proc$libresoc.v:203796$14673 + assign { } { } + assign { } { } + assign $0\src_l_r_src$next[3:0]$14674 $1\src_l_r_src$next[3:0]$14675 + attribute \src "libresoc.v:203797.5-203797.29" + switch \initial + attribute \src "libresoc.v:203797.9-203797.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_l_r_src$next[3:0]$14675 4'1111 + case + assign $1\src_l_r_src$next[3:0]$14675 \reset_r + end + sync always + update \src_l_r_src$next $0\src_l_r_src$next[3:0]$14674 + end + attribute \src "libresoc.v:203805.3-203813.6" + process $proc$libresoc.v:203805$14676 + assign { } { } + assign { } { } + assign $0\req_l_s_req$next[4:0]$14677 $1\req_l_s_req$next[4:0]$14678 + attribute \src "libresoc.v:203806.5-203806.29" + switch \initial + attribute \src "libresoc.v:203806.9-203806.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\req_l_s_req$next[4:0]$14678 5'00000 + case + assign $1\req_l_s_req$next[4:0]$14678 \$67 + end + sync always + update \req_l_s_req$next $0\req_l_s_req$next[4:0]$14677 + end + attribute \src "libresoc.v:203814.3-203822.6" + process $proc$libresoc.v:203814$14679 + assign { } { } + assign { } { } + assign $0\req_l_r_req$next[4:0]$14680 $1\req_l_r_req$next[4:0]$14681 + attribute \src "libresoc.v:203815.5-203815.29" + switch \initial + attribute \src "libresoc.v:203815.9-203815.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\req_l_r_req$next[4:0]$14681 5'11111 + case + assign $1\req_l_r_req$next[4:0]$14681 \$69 + end + sync always + update \req_l_r_req$next $0\req_l_r_req$next[4:0]$14680 + end + attribute \src "libresoc.v:203823.3-203840.6" + process $proc$libresoc.v:203823$14682 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\alu_trap0_trap_op__cia$next[63:0]$14683 $1\alu_trap0_trap_op__cia$next[63:0]$14692 + assign $0\alu_trap0_trap_op__fn_unit$next[12:0]$14684 $1\alu_trap0_trap_op__fn_unit$next[12:0]$14693 + assign $0\alu_trap0_trap_op__insn$next[31:0]$14685 $1\alu_trap0_trap_op__insn$next[31:0]$14694 + assign $0\alu_trap0_trap_op__insn_type$next[6:0]$14686 $1\alu_trap0_trap_op__insn_type$next[6:0]$14695 + assign $0\alu_trap0_trap_op__is_32bit$next[0:0]$14687 $1\alu_trap0_trap_op__is_32bit$next[0:0]$14696 + assign $0\alu_trap0_trap_op__ldst_exc$next[7:0]$14688 $1\alu_trap0_trap_op__ldst_exc$next[7:0]$14697 + assign $0\alu_trap0_trap_op__msr$next[63:0]$14689 $1\alu_trap0_trap_op__msr$next[63:0]$14698 + assign $0\alu_trap0_trap_op__trapaddr$next[12:0]$14690 $1\alu_trap0_trap_op__trapaddr$next[12:0]$14699 + assign $0\alu_trap0_trap_op__traptype$next[7:0]$14691 $1\alu_trap0_trap_op__traptype$next[7:0]$14700 + attribute \src "libresoc.v:203824.5-203824.29" + switch \initial + attribute \src "libresoc.v:203824.9-203824.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\alu_trap0_trap_op__ldst_exc$next[7:0]$14697 $1\alu_trap0_trap_op__trapaddr$next[12:0]$14699 $1\alu_trap0_trap_op__traptype$next[7:0]$14700 $1\alu_trap0_trap_op__is_32bit$next[0:0]$14696 $1\alu_trap0_trap_op__cia$next[63:0]$14692 $1\alu_trap0_trap_op__msr$next[63:0]$14698 $1\alu_trap0_trap_op__insn$next[31:0]$14694 $1\alu_trap0_trap_op__fn_unit$next[12:0]$14693 $1\alu_trap0_trap_op__insn_type$next[6:0]$14695 } { \oper_i_alu_trap0__ldst_exc \oper_i_alu_trap0__trapaddr \oper_i_alu_trap0__traptype \oper_i_alu_trap0__is_32bit \oper_i_alu_trap0__cia \oper_i_alu_trap0__msr \oper_i_alu_trap0__insn \oper_i_alu_trap0__fn_unit \oper_i_alu_trap0__insn_type } + case + assign $1\alu_trap0_trap_op__cia$next[63:0]$14692 \alu_trap0_trap_op__cia + assign $1\alu_trap0_trap_op__fn_unit$next[12:0]$14693 \alu_trap0_trap_op__fn_unit + assign $1\alu_trap0_trap_op__insn$next[31:0]$14694 \alu_trap0_trap_op__insn + assign $1\alu_trap0_trap_op__insn_type$next[6:0]$14695 \alu_trap0_trap_op__insn_type + assign $1\alu_trap0_trap_op__is_32bit$next[0:0]$14696 \alu_trap0_trap_op__is_32bit + assign $1\alu_trap0_trap_op__ldst_exc$next[7:0]$14697 \alu_trap0_trap_op__ldst_exc + assign $1\alu_trap0_trap_op__msr$next[63:0]$14698 \alu_trap0_trap_op__msr + assign $1\alu_trap0_trap_op__trapaddr$next[12:0]$14699 \alu_trap0_trap_op__trapaddr + assign $1\alu_trap0_trap_op__traptype$next[7:0]$14700 \alu_trap0_trap_op__traptype + end + sync always + update \alu_trap0_trap_op__cia$next $0\alu_trap0_trap_op__cia$next[63:0]$14683 + update \alu_trap0_trap_op__fn_unit$next $0\alu_trap0_trap_op__fn_unit$next[12:0]$14684 + update \alu_trap0_trap_op__insn$next $0\alu_trap0_trap_op__insn$next[31:0]$14685 + update \alu_trap0_trap_op__insn_type$next $0\alu_trap0_trap_op__insn_type$next[6:0]$14686 + update \alu_trap0_trap_op__is_32bit$next $0\alu_trap0_trap_op__is_32bit$next[0:0]$14687 + update \alu_trap0_trap_op__ldst_exc$next $0\alu_trap0_trap_op__ldst_exc$next[7:0]$14688 + update \alu_trap0_trap_op__msr$next $0\alu_trap0_trap_op__msr$next[63:0]$14689 + update \alu_trap0_trap_op__trapaddr$next $0\alu_trap0_trap_op__trapaddr$next[12:0]$14690 + update \alu_trap0_trap_op__traptype$next $0\alu_trap0_trap_op__traptype$next[7:0]$14691 + end + attribute \src "libresoc.v:203841.3-203862.6" + process $proc$libresoc.v:203841$14701 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r0__o$next[63:0]$14702 $2\data_r0__o$next[63:0]$14706 + assign { } { } + assign $0\data_r0__o_ok$next[0:0]$14703 $3\data_r0__o_ok$next[0:0]$14708 + attribute \src "libresoc.v:203842.5-203842.29" + switch \initial + attribute \src "libresoc.v:203842.9-203842.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r0__o_ok$next[0:0]$14705 $1\data_r0__o$next[63:0]$14704 } { \o_ok \alu_trap0_o } + case + assign $1\data_r0__o$next[63:0]$14704 \data_r0__o + assign $1\data_r0__o_ok$next[0:0]$14705 \data_r0__o_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r0__o_ok$next[0:0]$14707 $2\data_r0__o$next[63:0]$14706 } 65'00000000000000000000000000000000000000000000000000000000000000000 + case + assign $2\data_r0__o$next[63:0]$14706 $1\data_r0__o$next[63:0]$14704 + assign $2\data_r0__o_ok$next[0:0]$14707 $1\data_r0__o_ok$next[0:0]$14705 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r0__o_ok$next[0:0]$14708 1'0 + case + assign $3\data_r0__o_ok$next[0:0]$14708 $2\data_r0__o_ok$next[0:0]$14707 + end + sync always + update \data_r0__o$next $0\data_r0__o$next[63:0]$14702 + update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$14703 + end + attribute \src "libresoc.v:203863.3-203884.6" + process $proc$libresoc.v:203863$14709 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r1__fast1$next[63:0]$14710 $2\data_r1__fast1$next[63:0]$14714 + assign { } { } + assign $0\data_r1__fast1_ok$next[0:0]$14711 $3\data_r1__fast1_ok$next[0:0]$14716 + attribute \src "libresoc.v:203864.5-203864.29" + switch \initial + attribute \src "libresoc.v:203864.9-203864.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r1__fast1_ok$next[0:0]$14713 $1\data_r1__fast1$next[63:0]$14712 } { \fast1_ok \alu_trap0_fast1 } + case + assign $1\data_r1__fast1$next[63:0]$14712 \data_r1__fast1 + assign $1\data_r1__fast1_ok$next[0:0]$14713 \data_r1__fast1_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r1__fast1_ok$next[0:0]$14715 $2\data_r1__fast1$next[63:0]$14714 } 65'00000000000000000000000000000000000000000000000000000000000000000 + case + assign $2\data_r1__fast1$next[63:0]$14714 $1\data_r1__fast1$next[63:0]$14712 + assign $2\data_r1__fast1_ok$next[0:0]$14715 $1\data_r1__fast1_ok$next[0:0]$14713 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r1__fast1_ok$next[0:0]$14716 1'0 + case + assign $3\data_r1__fast1_ok$next[0:0]$14716 $2\data_r1__fast1_ok$next[0:0]$14715 + end + sync always + update \data_r1__fast1$next $0\data_r1__fast1$next[63:0]$14710 + update \data_r1__fast1_ok$next $0\data_r1__fast1_ok$next[0:0]$14711 + end + attribute \src "libresoc.v:203885.3-203906.6" + process $proc$libresoc.v:203885$14717 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r2__fast2$next[63:0]$14718 $2\data_r2__fast2$next[63:0]$14722 + assign { } { } + assign $0\data_r2__fast2_ok$next[0:0]$14719 $3\data_r2__fast2_ok$next[0:0]$14724 + attribute \src "libresoc.v:203886.5-203886.29" + switch \initial + attribute \src "libresoc.v:203886.9-203886.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r2__fast2_ok$next[0:0]$14721 $1\data_r2__fast2$next[63:0]$14720 } { \fast2_ok \alu_trap0_fast2 } + case + assign $1\data_r2__fast2$next[63:0]$14720 \data_r2__fast2 + assign $1\data_r2__fast2_ok$next[0:0]$14721 \data_r2__fast2_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r2__fast2_ok$next[0:0]$14723 $2\data_r2__fast2$next[63:0]$14722 } 65'00000000000000000000000000000000000000000000000000000000000000000 + case + assign $2\data_r2__fast2$next[63:0]$14722 $1\data_r2__fast2$next[63:0]$14720 + assign $2\data_r2__fast2_ok$next[0:0]$14723 $1\data_r2__fast2_ok$next[0:0]$14721 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r2__fast2_ok$next[0:0]$14724 1'0 + case + assign $3\data_r2__fast2_ok$next[0:0]$14724 $2\data_r2__fast2_ok$next[0:0]$14723 + end + sync always + update \data_r2__fast2$next $0\data_r2__fast2$next[63:0]$14718 + update \data_r2__fast2_ok$next $0\data_r2__fast2_ok$next[0:0]$14719 + end + attribute \src "libresoc.v:203907.3-203928.6" + process $proc$libresoc.v:203907$14725 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r3__nia$next[63:0]$14726 $2\data_r3__nia$next[63:0]$14730 + assign { } { } + assign $0\data_r3__nia_ok$next[0:0]$14727 $3\data_r3__nia_ok$next[0:0]$14732 + attribute \src "libresoc.v:203908.5-203908.29" + switch \initial + attribute \src "libresoc.v:203908.9-203908.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r3__nia_ok$next[0:0]$14729 $1\data_r3__nia$next[63:0]$14728 } { \nia_ok \alu_trap0_nia } + case + assign $1\data_r3__nia$next[63:0]$14728 \data_r3__nia + assign $1\data_r3__nia_ok$next[0:0]$14729 \data_r3__nia_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r3__nia_ok$next[0:0]$14731 $2\data_r3__nia$next[63:0]$14730 } 65'00000000000000000000000000000000000000000000000000000000000000000 + case + assign $2\data_r3__nia$next[63:0]$14730 $1\data_r3__nia$next[63:0]$14728 + assign $2\data_r3__nia_ok$next[0:0]$14731 $1\data_r3__nia_ok$next[0:0]$14729 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r3__nia_ok$next[0:0]$14732 1'0 + case + assign $3\data_r3__nia_ok$next[0:0]$14732 $2\data_r3__nia_ok$next[0:0]$14731 + end + sync always + update \data_r3__nia$next $0\data_r3__nia$next[63:0]$14726 + update \data_r3__nia_ok$next $0\data_r3__nia_ok$next[0:0]$14727 + end + attribute \src "libresoc.v:203929.3-203950.6" + process $proc$libresoc.v:203929$14733 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r4__msr$next[63:0]$14734 $2\data_r4__msr$next[63:0]$14738 + assign { } { } + assign $0\data_r4__msr_ok$next[0:0]$14735 $3\data_r4__msr_ok$next[0:0]$14740 + attribute \src "libresoc.v:203930.5-203930.29" + switch \initial + attribute \src "libresoc.v:203930.9-203930.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r4__msr_ok$next[0:0]$14737 $1\data_r4__msr$next[63:0]$14736 } { \msr_ok \alu_trap0_msr } + case + assign $1\data_r4__msr$next[63:0]$14736 \data_r4__msr + assign $1\data_r4__msr_ok$next[0:0]$14737 \data_r4__msr_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r4__msr_ok$next[0:0]$14739 $2\data_r4__msr$next[63:0]$14738 } 65'00000000000000000000000000000000000000000000000000000000000000000 + case + assign $2\data_r4__msr$next[63:0]$14738 $1\data_r4__msr$next[63:0]$14736 + assign $2\data_r4__msr_ok$next[0:0]$14739 $1\data_r4__msr_ok$next[0:0]$14737 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r4__msr_ok$next[0:0]$14740 1'0 + case + assign $3\data_r4__msr_ok$next[0:0]$14740 $2\data_r4__msr_ok$next[0:0]$14739 + end + sync always + update \data_r4__msr$next $0\data_r4__msr$next[63:0]$14734 + update \data_r4__msr_ok$next $0\data_r4__msr_ok$next[0:0]$14735 + end + attribute \src "libresoc.v:203951.3-203960.6" + process $proc$libresoc.v:203951$14741 + assign { } { } + assign { } { } + assign $0\src_r0$next[63:0]$14742 $1\src_r0$next[63:0]$14743 + attribute \src "libresoc.v:203952.5-203952.29" + switch \initial + attribute \src "libresoc.v:203952.9-203952.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" + switch \src_l_q_src [0] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r0$next[63:0]$14743 \src1_i + case + assign $1\src_r0$next[63:0]$14743 \src_r0 + end + sync always + update \src_r0$next $0\src_r0$next[63:0]$14742 + end + attribute \src "libresoc.v:203961.3-203970.6" + process $proc$libresoc.v:203961$14744 + assign { } { } + assign { } { } + assign $0\src_r1$next[63:0]$14745 $1\src_r1$next[63:0]$14746 + attribute \src "libresoc.v:203962.5-203962.29" + switch \initial + attribute \src "libresoc.v:203962.9-203962.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" + switch \src_l_q_src [1] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r1$next[63:0]$14746 \src2_i + case + assign $1\src_r1$next[63:0]$14746 \src_r1 + end + sync always + update \src_r1$next $0\src_r1$next[63:0]$14745 + end + attribute \src "libresoc.v:203971.3-203980.6" + process $proc$libresoc.v:203971$14747 + assign { } { } + assign { } { } + assign $0\src_r2$next[63:0]$14748 $1\src_r2$next[63:0]$14749 + attribute \src "libresoc.v:203972.5-203972.29" + switch \initial + attribute \src "libresoc.v:203972.9-203972.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" + switch \src_l_q_src [2] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r2$next[63:0]$14749 \src3_i + case + assign $1\src_r2$next[63:0]$14749 \src_r2 + end + sync always + update \src_r2$next $0\src_r2$next[63:0]$14748 + end + attribute \src "libresoc.v:203981.3-203990.6" + process $proc$libresoc.v:203981$14750 + assign { } { } + assign { } { } + assign $0\src_r3$next[63:0]$14751 $1\src_r3$next[63:0]$14752 + attribute \src "libresoc.v:203982.5-203982.29" + switch \initial + attribute \src "libresoc.v:203982.9-203982.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" + switch \src_l_q_src [3] + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r3$next[63:0]$14752 \src4_i + case + assign $1\src_r3$next[63:0]$14752 \src_r3 + end + sync always + update \src_r3$next $0\src_r3$next[63:0]$14751 + end + attribute \src "libresoc.v:203991.3-203999.6" + process $proc$libresoc.v:203991$14753 + assign { } { } + assign { } { } + assign $0\alui_l_r_alui$next[0:0]$14754 $1\alui_l_r_alui$next[0:0]$14755 + attribute \src "libresoc.v:203992.5-203992.29" + switch \initial + attribute \src "libresoc.v:203992.9-203992.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\alui_l_r_alui$next[0:0]$14755 1'1 + case + assign $1\alui_l_r_alui$next[0:0]$14755 \$89 + end + sync always + update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$14754 + end + attribute \src "libresoc.v:204000.3-204008.6" + process $proc$libresoc.v:204000$14756 + assign { } { } + assign { } { } + assign $0\alu_l_r_alu$next[0:0]$14757 $1\alu_l_r_alu$next[0:0]$14758 + attribute \src "libresoc.v:204001.5-204001.29" + switch \initial + attribute \src "libresoc.v:204001.9-204001.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\alu_l_r_alu$next[0:0]$14758 1'1 + case + assign $1\alu_l_r_alu$next[0:0]$14758 \$91 + end + sync always + update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$14757 + end + attribute \src "libresoc.v:204009.3-204018.6" + process $proc$libresoc.v:204009$14759 + assign { } { } + assign { } { } + assign $0\dest1_o[63:0] $1\dest1_o[63:0] + attribute \src "libresoc.v:204010.5-204010.29" + switch \initial + attribute \src "libresoc.v:204010.9-204010.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$115 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest1_o[63:0] \data_r0__o + case + assign $1\dest1_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \dest1_o $0\dest1_o[63:0] + end + attribute \src "libresoc.v:204019.3-204028.6" + process $proc$libresoc.v:204019$14760 + assign { } { } + assign { } { } + assign $0\dest2_o[63:0] $1\dest2_o[63:0] + attribute \src "libresoc.v:204020.5-204020.29" + switch \initial + attribute \src "libresoc.v:204020.9-204020.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$117 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest2_o[63:0] \data_r1__fast1 + case + assign $1\dest2_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \dest2_o $0\dest2_o[63:0] + end + attribute \src "libresoc.v:204029.3-204038.6" + process $proc$libresoc.v:204029$14761 + assign { } { } + assign { } { } + assign $0\dest3_o[63:0] $1\dest3_o[63:0] + attribute \src "libresoc.v:204030.5-204030.29" + switch \initial + attribute \src "libresoc.v:204030.9-204030.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$119 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest3_o[63:0] \data_r2__fast2 + case + assign $1\dest3_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \dest3_o $0\dest3_o[63:0] + end + attribute \src "libresoc.v:204039.3-204048.6" + process $proc$libresoc.v:204039$14762 + assign { } { } + assign { } { } + assign $0\dest4_o[63:0] $1\dest4_o[63:0] + attribute \src "libresoc.v:204040.5-204040.29" + switch \initial + attribute \src "libresoc.v:204040.9-204040.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$121 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest4_o[63:0] \data_r3__nia + case + assign $1\dest4_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \dest4_o $0\dest4_o[63:0] + end + attribute \src "libresoc.v:204049.3-204058.6" + process $proc$libresoc.v:204049$14763 + assign { } { } + assign { } { } + assign $0\dest5_o[63:0] $1\dest5_o[63:0] + attribute \src "libresoc.v:204050.5-204050.29" + switch \initial + attribute \src "libresoc.v:204050.9-204050.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$123 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest5_o[63:0] \data_r4__msr + case + assign $1\dest5_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \dest5_o $0\dest5_o[63:0] + end + attribute \src "libresoc.v:204059.3-204067.6" + process $proc$libresoc.v:204059$14764 + assign { } { } + assign { } { } + assign $0\prev_wr_go$next[4:0]$14765 $1\prev_wr_go$next[4:0]$14766 + attribute \src "libresoc.v:204060.5-204060.29" + switch \initial + attribute \src "libresoc.v:204060.9-204060.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\prev_wr_go$next[4:0]$14766 5'00000 + case + assign $1\prev_wr_go$next[4:0]$14766 \$21 + end + sync always + update \prev_wr_go$next $0\prev_wr_go$next[4:0]$14765 + end + connect \$5 $reduce_and$libresoc.v:203507$14552_Y + connect \$99 $and$libresoc.v:203508$14553_Y + connect \$101 $and$libresoc.v:203509$14554_Y + connect \$103 $and$libresoc.v:203510$14555_Y + connect \$105 $and$libresoc.v:203511$14556_Y + connect \$107 $and$libresoc.v:203512$14557_Y + connect \$109 $and$libresoc.v:203513$14558_Y + connect \$111 $and$libresoc.v:203514$14559_Y + connect \$113 $and$libresoc.v:203515$14560_Y + connect \$115 $and$libresoc.v:203516$14561_Y + connect \$117 $and$libresoc.v:203517$14562_Y + connect \$11 $and$libresoc.v:203518$14563_Y + connect \$119 $and$libresoc.v:203519$14564_Y + connect \$121 $and$libresoc.v:203520$14565_Y + connect \$123 $and$libresoc.v:203521$14566_Y + connect \$13 $not$libresoc.v:203522$14567_Y + connect \$15 $and$libresoc.v:203523$14568_Y + connect \$17 $not$libresoc.v:203524$14569_Y + connect \$19 $and$libresoc.v:203525$14570_Y + connect \$21 $and$libresoc.v:203526$14571_Y + connect \$25 $not$libresoc.v:203527$14572_Y + connect \$27 $and$libresoc.v:203528$14573_Y + connect \$24 $reduce_or$libresoc.v:203529$14574_Y + connect \$23 $not$libresoc.v:203530$14575_Y + connect \$31 $and$libresoc.v:203531$14576_Y + connect \$33 $reduce_or$libresoc.v:203532$14577_Y + connect \$35 $reduce_or$libresoc.v:203533$14578_Y + connect \$37 $or$libresoc.v:203534$14579_Y + connect \$3 $and$libresoc.v:203535$14580_Y + connect \$39 $not$libresoc.v:203536$14581_Y + connect \$41 $and$libresoc.v:203537$14582_Y + connect \$43 $and$libresoc.v:203538$14583_Y + connect \$45 $eq$libresoc.v:203539$14584_Y + connect \$47 $and$libresoc.v:203540$14585_Y + connect \$49 $eq$libresoc.v:203541$14586_Y + connect \$51 $and$libresoc.v:203542$14587_Y + connect \$53 $and$libresoc.v:203543$14588_Y + connect \$55 $and$libresoc.v:203544$14589_Y + connect \$57 $or$libresoc.v:203545$14590_Y + connect \$59 $or$libresoc.v:203546$14591_Y + connect \$61 $or$libresoc.v:203547$14592_Y + connect \$63 $or$libresoc.v:203548$14593_Y + connect \$65 $and$libresoc.v:203549$14594_Y + connect \$67 $and$libresoc.v:203550$14595_Y + connect \$6 $not$libresoc.v:203551$14596_Y + connect \$69 $or$libresoc.v:203552$14597_Y + connect \$71 $and$libresoc.v:203553$14598_Y + connect \$73 $and$libresoc.v:203554$14599_Y + connect \$75 $and$libresoc.v:203555$14600_Y + connect \$77 $and$libresoc.v:203556$14601_Y + connect \$79 $and$libresoc.v:203557$14602_Y + connect \$81 $ternary$libresoc.v:203558$14603_Y + connect \$83 $ternary$libresoc.v:203559$14604_Y + connect \$85 $ternary$libresoc.v:203560$14605_Y + connect \$87 $ternary$libresoc.v:203561$14606_Y + connect \$8 $or$libresoc.v:203562$14607_Y + connect \$89 $and$libresoc.v:203563$14608_Y + connect \$91 $and$libresoc.v:203564$14609_Y + connect \$93 $and$libresoc.v:203565$14610_Y + connect \$95 $and$libresoc.v:203566$14611_Y + connect \$97 $not$libresoc.v:203567$14612_Y + connect \cu_go_die_i 1'0 + connect \cu_shadown_i 1'1 + connect \cu_wr__rel_o \$113 + connect \cu_rd__rel_o \$99 + connect \cu_busy_o \opc_l_q_opc + connect \alu_l_s_alu \all_rd_pulse + connect \alu_trap0_n_ready_i \alu_l_q_alu + connect \alui_l_s_alui \all_rd_pulse + connect \alu_trap0_p_valid_i \alui_l_q_alui + connect \alu_trap0_fast2$2 \$87 + connect \alu_trap0_fast1$1 \$85 + connect \alu_trap0_rb \$83 + connect \alu_trap0_ra \$81 + connect \cu_wrmask_o { \$79 \$77 \$75 \$73 \$71 } + connect \reset_r \$63 + connect \reset_w \$61 + connect \rst_r \$59 + connect \reset \$57 + connect \wr_any \$37 + connect \cu_done_o \$31 + connect \alu_pulsem { \alu_pulse \alu_pulse \alu_pulse \alu_pulse \alu_pulse } + connect \alu_pulse \alu_done_rise + connect \alu_done_rise \$19 + connect \alu_done_dly$next \alu_done + connect \alu_done \alu_trap0_n_valid_o + connect \all_rd_pulse \all_rd_rise + connect \all_rd_rise \$15 + connect \all_rd_dly$next \all_rd + connect \all_rd \$11 +end +attribute \src "libresoc.v:204101.1-204159.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.upd_l" +attribute \generator "nMigen" +module \upd_l + attribute \src "libresoc.v:204102.7-204102.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:204147.3-204155.6" + wire $0\q_int$next[0:0]$14816 + attribute \src "libresoc.v:204145.3-204146.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:204147.3-204155.6" + wire $1\q_int$next[0:0]$14817 + attribute \src "libresoc.v:204124.7-204124.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:204137.17-204137.96" + wire $and$libresoc.v:204137$14806_Y + attribute \src "libresoc.v:204142.17-204142.96" + wire $and$libresoc.v:204142$14811_Y + attribute \src "libresoc.v:204139.18-204139.93" + wire $not$libresoc.v:204139$14808_Y + attribute \src "libresoc.v:204141.17-204141.92" + wire $not$libresoc.v:204141$14810_Y + attribute \src "libresoc.v:204144.17-204144.92" + wire $not$libresoc.v:204144$14813_Y + attribute \src "libresoc.v:204138.18-204138.98" + wire $or$libresoc.v:204138$14807_Y + attribute \src "libresoc.v:204140.18-204140.99" + wire $or$libresoc.v:204140$14809_Y + attribute \src "libresoc.v:204143.17-204143.97" + wire $or$libresoc.v:204143$14812_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 1 \coresync_rst + attribute \src "libresoc.v:204102.7-204102.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire output 4 \q_upd + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" + wire \qlq_upd + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \qn_upd + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire input 3 \r_upd + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire input 2 \s_upd + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:204137$14806 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:204137$14806_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:204142$14811 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:204142$14811_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:204139$14808 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_upd + connect \Y $not$libresoc.v:204139$14808_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:204141$14810 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_upd + connect \Y $not$libresoc.v:204141$14810_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:204144$14813 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_upd + connect \Y $not$libresoc.v:204144$14813_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:204138$14807 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_upd + connect \Y $or$libresoc.v:204138$14807_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:204140$14809 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_upd + connect \B \q_int + connect \Y $or$libresoc.v:204140$14809_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:204143$14812 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_upd + connect \Y $or$libresoc.v:204143$14812_Y + end + attribute \src "libresoc.v:204102.7-204102.20" + process $proc$libresoc.v:204102$14818 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:204124.7-204124.19" + process $proc$libresoc.v:204124$14819 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:204145.3-204146.27" + process $proc$libresoc.v:204145$14814 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:204147.3-204155.6" + process $proc$libresoc.v:204147$14815 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$14816 $1\q_int$next[0:0]$14817 + attribute \src "libresoc.v:204148.5-204148.29" + switch \initial + attribute \src "libresoc.v:204148.9-204148.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$14817 1'0 + case + assign $1\q_int$next[0:0]$14817 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$14816 + end + connect \$9 $and$libresoc.v:204137$14806_Y + connect \$11 $or$libresoc.v:204138$14807_Y + connect \$13 $not$libresoc.v:204139$14808_Y + connect \$15 $or$libresoc.v:204140$14809_Y + connect \$1 $not$libresoc.v:204141$14810_Y + connect \$3 $and$libresoc.v:204142$14811_Y + connect \$5 $or$libresoc.v:204143$14812_Y + connect \$7 $not$libresoc.v:204144$14813_Y + connect \qlq_upd \$15 + connect \qn_upd \$13 + connect \q_upd \$11 +end +attribute \src "libresoc.v:204163.1-204221.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem.valid_l" +attribute \generator "nMigen" +module \valid_l + attribute \src "libresoc.v:204164.7-204164.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:204209.3-204217.6" + wire $0\q_int$next[0:0]$14830 + attribute \src "libresoc.v:204207.3-204208.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:204209.3-204217.6" + wire $1\q_int$next[0:0]$14831 + attribute \src "libresoc.v:204186.7-204186.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:204199.17-204199.96" + wire $and$libresoc.v:204199$14820_Y + attribute \src "libresoc.v:204204.17-204204.96" + wire $and$libresoc.v:204204$14825_Y + attribute \src "libresoc.v:204201.18-204201.95" + wire $not$libresoc.v:204201$14822_Y + attribute \src "libresoc.v:204203.17-204203.94" + wire $not$libresoc.v:204203$14824_Y + attribute \src "libresoc.v:204206.17-204206.94" + wire $not$libresoc.v:204206$14827_Y + attribute \src "libresoc.v:204200.18-204200.100" + wire $or$libresoc.v:204200$14821_Y + attribute \src "libresoc.v:204202.18-204202.101" + wire $or$libresoc.v:204202$14823_Y + attribute \src "libresoc.v:204205.17-204205.99" + wire $or$libresoc.v:204205$14826_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 1 \coresync_rst + attribute \src "libresoc.v:204164.7-204164.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire output 3 \q_valid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" + wire \qlq_valid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \qn_valid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire input 4 \r_valid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire input 2 \s_valid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:204199$14820 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:204199$14820_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:204204$14825 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:204204$14825_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:204201$14822 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_valid + connect \Y $not$libresoc.v:204201$14822_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:204203$14824 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_valid + connect \Y $not$libresoc.v:204203$14824_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:204206$14827 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_valid + connect \Y $not$libresoc.v:204206$14827_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:204200$14821 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_valid + connect \Y $or$libresoc.v:204200$14821_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:204202$14823 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_valid + connect \B \q_int + connect \Y $or$libresoc.v:204202$14823_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:204205$14826 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_valid + connect \Y $or$libresoc.v:204205$14826_Y + end + attribute \src "libresoc.v:204164.7-204164.20" + process $proc$libresoc.v:204164$14832 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:204186.7-204186.19" + process $proc$libresoc.v:204186$14833 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:204207.3-204208.27" + process $proc$libresoc.v:204207$14828 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:204209.3-204217.6" + process $proc$libresoc.v:204209$14829 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$14830 $1\q_int$next[0:0]$14831 + attribute \src "libresoc.v:204210.5-204210.29" + switch \initial + attribute \src "libresoc.v:204210.9-204210.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$14831 1'0 + case + assign $1\q_int$next[0:0]$14831 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$14830 + end + connect \$9 $and$libresoc.v:204199$14820_Y + connect \$11 $or$libresoc.v:204200$14821_Y + connect \$13 $not$libresoc.v:204201$14822_Y + connect \$15 $or$libresoc.v:204202$14823_Y + connect \$1 $not$libresoc.v:204203$14824_Y + connect \$3 $and$libresoc.v:204204$14825_Y + connect \$5 $or$libresoc.v:204205$14826_Y + connect \$7 $not$libresoc.v:204206$14827_Y + connect \qlq_valid \$15 + connect \qn_valid \$13 + connect \q_valid \$11 +end +attribute \src "libresoc.v:204225.1-204283.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.wri_l" +attribute \generator "nMigen" +module \wri_l + attribute \src "libresoc.v:204226.7-204226.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:204271.3-204279.6" + wire $0\q_int$next[0:0]$14844 + attribute \src "libresoc.v:204269.3-204270.27" + wire $0\q_int[0:0] + attribute \src "libresoc.v:204271.3-204279.6" + wire $1\q_int$next[0:0]$14845 + attribute \src "libresoc.v:204248.7-204248.19" + wire $1\q_int[0:0] + attribute \src "libresoc.v:204261.17-204261.96" + wire $and$libresoc.v:204261$14834_Y + attribute \src "libresoc.v:204266.17-204266.96" + wire $and$libresoc.v:204266$14839_Y + attribute \src "libresoc.v:204263.18-204263.93" + wire $not$libresoc.v:204263$14836_Y + attribute \src "libresoc.v:204265.17-204265.92" + wire $not$libresoc.v:204265$14838_Y + attribute \src "libresoc.v:204268.17-204268.92" + wire $not$libresoc.v:204268$14841_Y + attribute \src "libresoc.v:204262.18-204262.98" + wire $or$libresoc.v:204262$14835_Y + attribute \src "libresoc.v:204264.18-204264.99" + wire $or$libresoc.v:204264$14837_Y + attribute \src "libresoc.v:204267.17-204267.97" + wire $or$libresoc.v:204267$14840_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:195" + wire input 1 \coresync_rst + attribute \src "libresoc.v:204226.7-204226.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" + wire output 4 \q_wri + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" + wire \qlq_wri + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \qn_wri + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire input 3 \r_wri + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" + wire input 2 \s_wri + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $and $and$libresoc.v:204261$14834 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$libresoc.v:204261$14834_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $and $and$libresoc.v:204266$14839 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$libresoc.v:204266$14839_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" + cell $not $not$libresoc.v:204263$14836 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_wri + connect \Y $not$libresoc.v:204263$14836_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $not $not$libresoc.v:204265$14838 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_wri + connect \Y $not$libresoc.v:204265$14838_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $not $not$libresoc.v:204268$14841 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_wri + connect \Y $not$libresoc.v:204268$14841_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" + cell $or $or$libresoc.v:204262$14835 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_wri + connect \Y $or$libresoc.v:204262$14835_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" + cell $or $or$libresoc.v:204264$14837 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_wri + connect \B \q_int + connect \Y $or$libresoc.v:204264$14837_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" + cell $or $or$libresoc.v:204267$14840 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_wri + connect \Y $or$libresoc.v:204267$14840_Y + end + attribute \src "libresoc.v:204226.7-204226.20" + process $proc$libresoc.v:204226$14846 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:204248.7-204248.19" + process $proc$libresoc.v:204248$14847 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "libresoc.v:204269.3-204270.27" + process $proc$libresoc.v:204269$14842 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "libresoc.v:204271.3-204279.6" + process $proc$libresoc.v:204271$14843 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$14844 $1\q_int$next[0:0]$14845 + attribute \src "libresoc.v:204272.5-204272.29" + switch \initial + attribute \src "libresoc.v:204272.9-204272.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$14845 1'0 + case + assign $1\q_int$next[0:0]$14845 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$14844 + end + connect \$9 $and$libresoc.v:204261$14834_Y + connect \$11 $or$libresoc.v:204262$14835_Y + connect \$13 $not$libresoc.v:204263$14836_Y + connect \$15 $or$libresoc.v:204264$14837_Y + connect \$1 $not$libresoc.v:204265$14838_Y + connect \$3 $and$libresoc.v:204266$14839_Y + connect \$5 $or$libresoc.v:204267$14840_Y + connect \$7 $not$libresoc.v:204268$14841_Y + connect \qlq_wri \$15 + connect \qn_wri \$13 + connect \q_wri \$11 +end +attribute \src "libresoc.v:204287.1-204353.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_CR_cr_a" +attribute \generator "nMigen" +module \wrpick_CR_cr_a + attribute \src "libresoc.v:204332.17-204332.91" + wire $not$libresoc.v:204332$14848_Y + attribute \src "libresoc.v:204334.18-204334.93" + wire $not$libresoc.v:204334$14850_Y + attribute \src "libresoc.v:204336.18-204336.93" + wire $not$libresoc.v:204336$14852_Y + attribute \src "libresoc.v:204337.17-204337.89" + wire width 6 $not$libresoc.v:204337$14853_Y + attribute \src "libresoc.v:204339.18-204339.93" + wire $not$libresoc.v:204339$14855_Y + attribute \src "libresoc.v:204342.17-204342.91" + wire $not$libresoc.v:204342$14858_Y + attribute \src "libresoc.v:204333.18-204333.106" + wire $reduce_or$libresoc.v:204333$14849_Y + attribute \src "libresoc.v:204335.18-204335.106" + wire $reduce_or$libresoc.v:204335$14851_Y + attribute \src "libresoc.v:204338.18-204338.106" + wire $reduce_or$libresoc.v:204338$14854_Y + attribute \src "libresoc.v:204340.18-204340.90" + wire $reduce_or$libresoc.v:204340$14856_Y + attribute \src "libresoc.v:204341.17-204341.103" + wire $reduce_or$libresoc.v:204341$14857_Y + attribute \src "libresoc.v:204343.17-204343.105" + wire $reduce_or$libresoc.v:204343$14859_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 6 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" + wire output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 6 input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" + wire width 6 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" + wire width 6 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:204332$14848 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $not$libresoc.v:204332$14848_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:204334$14850 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$12 + connect \Y $not$libresoc.v:204334$14850_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:204336$14852 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$16 + connect \Y $not$libresoc.v:204336$14852_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + cell $not $not$libresoc.v:204337$14853 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \i + connect \Y $not$libresoc.v:204337$14853_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:204339$14855 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$20 + connect \Y $not$libresoc.v:204339$14855_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:204342$14858 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$libresoc.v:204342$14858_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:204333$14849 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [2:0] \ni [3] } + connect \Y $reduce_or$libresoc.v:204333$14849_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:204335$14851 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [3:0] \ni [4] } + connect \Y $reduce_or$libresoc.v:204335$14851_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:204338$14854 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A { \i [4:0] \ni [5] } + connect \Y $reduce_or$libresoc.v:204338$14854_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" + cell $reduce_or $reduce_or$libresoc.v:204340$14856 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:204340$14856_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:204341$14857 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [0] \ni [1] } + connect \Y $reduce_or$libresoc.v:204341$14857_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:204343$14859 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [1:0] \ni [2] } + connect \Y $reduce_or$libresoc.v:204343$14859_Y + end + connect \$7 $not$libresoc.v:204332$14848_Y + connect \$12 $reduce_or$libresoc.v:204333$14849_Y + connect \$11 $not$libresoc.v:204334$14850_Y + connect \$16 $reduce_or$libresoc.v:204335$14851_Y + connect \$15 $not$libresoc.v:204336$14852_Y + connect \$1 $not$libresoc.v:204337$14853_Y + connect \$20 $reduce_or$libresoc.v:204338$14854_Y + connect \$19 $not$libresoc.v:204339$14855_Y + connect \$23 $reduce_or$libresoc.v:204340$14856_Y + connect \$4 $reduce_or$libresoc.v:204341$14857_Y + connect \$3 $not$libresoc.v:204342$14858_Y + connect \$8 $reduce_or$libresoc.v:204343$14859_Y + connect \en_o \$23 + connect \o { \t5 \t4 \t3 \t2 \t1 \t0 } + connect \t5 \$19 + connect \t4 \$15 + connect \t3 \$11 + connect \t2 \$7 + connect \t1 \$3 + connect \t0 \i [0] + connect \ni \$1 +end +attribute \src "libresoc.v:204357.1-204378.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_CR_full_cr" +attribute \generator "nMigen" +module \wrpick_CR_full_cr + attribute \src "libresoc.v:204372.17-204372.89" + wire $not$libresoc.v:204372$14860_Y + attribute \src "libresoc.v:204373.17-204373.89" + wire $reduce_or$libresoc.v:204373$14861_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" + wire output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" + wire \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" + wire output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + cell $not $not$libresoc.v:204372$14860 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \i + connect \Y $not$libresoc.v:204372$14860_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" + cell $reduce_or $reduce_or$libresoc.v:204373$14861 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:204373$14861_Y + end + connect \$1 $not$libresoc.v:204372$14860_Y + connect \$3 $reduce_or$libresoc.v:204373$14861_Y + connect \en_o \$3 + connect \o \t0 + connect \t0 \i + connect \ni \$1 +end +attribute \src "libresoc.v:204382.1-204439.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_FAST_fast1" +attribute \generator "nMigen" +module \wrpick_FAST_fast1 + attribute \src "libresoc.v:204421.17-204421.91" + wire $not$libresoc.v:204421$14862_Y + attribute \src "libresoc.v:204423.18-204423.93" + wire $not$libresoc.v:204423$14864_Y + attribute \src "libresoc.v:204425.18-204425.93" + wire $not$libresoc.v:204425$14866_Y + attribute \src "libresoc.v:204426.17-204426.89" + wire width 5 $not$libresoc.v:204426$14867_Y + attribute \src "libresoc.v:204429.17-204429.91" + wire $not$libresoc.v:204429$14870_Y + attribute \src "libresoc.v:204422.18-204422.106" + wire $reduce_or$libresoc.v:204422$14863_Y + attribute \src "libresoc.v:204424.18-204424.106" + wire $reduce_or$libresoc.v:204424$14865_Y + attribute \src "libresoc.v:204427.18-204427.90" + wire $reduce_or$libresoc.v:204427$14868_Y + attribute \src "libresoc.v:204428.17-204428.103" + wire $reduce_or$libresoc.v:204428$14869_Y + attribute \src "libresoc.v:204430.17-204430.105" + wire $reduce_or$libresoc.v:204430$14871_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 5 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" + wire output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 5 input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" + wire width 5 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" + wire width 5 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:204421$14862 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $not$libresoc.v:204421$14862_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:204423$14864 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$12 + connect \Y $not$libresoc.v:204423$14864_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:204425$14866 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$16 + connect \Y $not$libresoc.v:204425$14866_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + cell $not $not$libresoc.v:204426$14867 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \i + connect \Y $not$libresoc.v:204426$14867_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:204429$14870 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$libresoc.v:204429$14870_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:204422$14863 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [2:0] \ni [3] } + connect \Y $reduce_or$libresoc.v:204422$14863_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:204424$14865 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [3:0] \ni [4] } + connect \Y $reduce_or$libresoc.v:204424$14865_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" + cell $reduce_or $reduce_or$libresoc.v:204427$14868 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:204427$14868_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:204428$14869 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [0] \ni [1] } + connect \Y $reduce_or$libresoc.v:204428$14869_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:204430$14871 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [1:0] \ni [2] } + connect \Y $reduce_or$libresoc.v:204430$14871_Y + end + connect \$7 $not$libresoc.v:204421$14862_Y + connect \$12 $reduce_or$libresoc.v:204422$14863_Y + connect \$11 $not$libresoc.v:204423$14864_Y + connect \$16 $reduce_or$libresoc.v:204424$14865_Y + connect \$15 $not$libresoc.v:204425$14866_Y + connect \$1 $not$libresoc.v:204426$14867_Y + connect \$19 $reduce_or$libresoc.v:204427$14868_Y + connect \$4 $reduce_or$libresoc.v:204428$14869_Y + connect \$3 $not$libresoc.v:204429$14870_Y + connect \$8 $reduce_or$libresoc.v:204430$14871_Y + connect \en_o \$19 + connect \o { \t4 \t3 \t2 \t1 \t0 } + connect \t4 \$15 + connect \t3 \$11 + connect \t2 \$7 + connect \t1 \$3 + connect \t0 \i [0] + connect \ni \$1 +end +attribute \src "libresoc.v:204443.1-204545.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_INT_o" +attribute \generator "nMigen" +module \wrpick_INT_o + attribute \src "libresoc.v:204512.17-204512.91" + wire $not$libresoc.v:204512$14872_Y + attribute \src "libresoc.v:204514.18-204514.93" + wire $not$libresoc.v:204514$14874_Y + attribute \src "libresoc.v:204516.18-204516.93" + wire $not$libresoc.v:204516$14876_Y + attribute \src "libresoc.v:204517.17-204517.89" + wire width 10 $not$libresoc.v:204517$14877_Y + attribute \src "libresoc.v:204519.18-204519.93" + wire $not$libresoc.v:204519$14879_Y + attribute \src "libresoc.v:204521.18-204521.93" + wire $not$libresoc.v:204521$14881_Y + attribute \src "libresoc.v:204523.18-204523.93" + wire $not$libresoc.v:204523$14883_Y + attribute \src "libresoc.v:204525.18-204525.93" + wire $not$libresoc.v:204525$14885_Y + attribute \src "libresoc.v:204527.18-204527.93" + wire $not$libresoc.v:204527$14887_Y + attribute \src "libresoc.v:204530.17-204530.91" + wire $not$libresoc.v:204530$14890_Y + attribute \src "libresoc.v:204513.18-204513.106" + wire $reduce_or$libresoc.v:204513$14873_Y + attribute \src "libresoc.v:204515.18-204515.106" + wire $reduce_or$libresoc.v:204515$14875_Y + attribute \src "libresoc.v:204518.18-204518.106" + wire $reduce_or$libresoc.v:204518$14878_Y + attribute \src "libresoc.v:204520.18-204520.106" + wire $reduce_or$libresoc.v:204520$14880_Y + attribute \src "libresoc.v:204522.18-204522.106" + wire $reduce_or$libresoc.v:204522$14882_Y + attribute \src "libresoc.v:204524.18-204524.106" + wire $reduce_or$libresoc.v:204524$14884_Y + attribute \src "libresoc.v:204526.18-204526.106" + wire $reduce_or$libresoc.v:204526$14886_Y + attribute \src "libresoc.v:204528.18-204528.90" + wire $reduce_or$libresoc.v:204528$14888_Y + attribute \src "libresoc.v:204529.17-204529.103" + wire $reduce_or$libresoc.v:204529$14889_Y + attribute \src "libresoc.v:204531.17-204531.105" + wire $reduce_or$libresoc.v:204531$14891_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 10 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$32 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$35 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$36 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" + wire \$39 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" + wire output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 10 input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" + wire width 10 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" + wire width 10 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t8 + attribute \src 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$reduce_or$libresoc.v:204515$14875 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [3:0] \ni [4] } + connect \Y $reduce_or$libresoc.v:204515$14875_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:204518$14878 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A { \i [4:0] \ni [5] } + connect \Y $reduce_or$libresoc.v:204518$14878_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:204520$14880 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A { \i [5:0] \ni [6] } + connect \Y $reduce_or$libresoc.v:204520$14880_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:204522$14882 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A { \i [6:0] \ni [7] } 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$reduce_or$libresoc.v:204529$14889 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [0] \ni [1] } + connect \Y $reduce_or$libresoc.v:204529$14889_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:204531$14891 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [1:0] \ni [2] } + connect \Y $reduce_or$libresoc.v:204531$14891_Y + end + connect \$7 $not$libresoc.v:204512$14872_Y + connect \$12 $reduce_or$libresoc.v:204513$14873_Y + connect \$11 $not$libresoc.v:204514$14874_Y + connect \$16 $reduce_or$libresoc.v:204515$14875_Y + connect \$15 $not$libresoc.v:204516$14876_Y + connect \$1 $not$libresoc.v:204517$14877_Y + connect \$20 $reduce_or$libresoc.v:204518$14878_Y + connect \$19 $not$libresoc.v:204519$14879_Y + connect \$24 $reduce_or$libresoc.v:204520$14880_Y + connect \$23 $not$libresoc.v:204521$14881_Y + connect \$28 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$not$libresoc.v:204564$14892_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" + cell $reduce_or $reduce_or$libresoc.v:204565$14893 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:204565$14893_Y + end + connect \$1 $not$libresoc.v:204564$14892_Y + connect \$3 $reduce_or$libresoc.v:204565$14893_Y + connect \en_o \$3 + connect \o \t0 + connect \t0 \i + connect \ni \$1 +end +attribute \src "libresoc.v:204574.1-204595.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_STATE_msr" +attribute \generator "nMigen" +module \wrpick_STATE_msr + attribute \src "libresoc.v:204589.17-204589.89" + wire $not$libresoc.v:204589$14894_Y + attribute \src "libresoc.v:204590.17-204590.89" + wire $reduce_or$libresoc.v:204590$14895_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \$1 + attribute \src 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$reduce_or$libresoc.v:204590$14895_Y + end + connect \$1 $not$libresoc.v:204589$14894_Y + connect \$3 $reduce_or$libresoc.v:204590$14895_Y + connect \en_o \$3 + connect \o \t0 + connect \t0 \i + connect \ni \$1 +end +attribute \src "libresoc.v:204599.1-204629.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_STATE_nia" +attribute \generator "nMigen" +module \wrpick_STATE_nia + attribute \src "libresoc.v:204620.17-204620.89" + wire width 2 $not$libresoc.v:204620$14896_Y + attribute \src "libresoc.v:204622.17-204622.91" + wire $not$libresoc.v:204622$14898_Y + attribute \src "libresoc.v:204621.17-204621.103" + wire $reduce_or$libresoc.v:204621$14897_Y + attribute \src "libresoc.v:204623.17-204623.89" + wire $reduce_or$libresoc.v:204623$14899_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 2 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" + wire output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 2 input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" + wire width 2 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" + wire width 2 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + cell $not $not$libresoc.v:204620$14896 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \i + connect \Y $not$libresoc.v:204620$14896_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:204622$14898 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$libresoc.v:204622$14898_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:204621$14897 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [0] \ni [1] } + connect \Y $reduce_or$libresoc.v:204621$14897_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" + cell $reduce_or $reduce_or$libresoc.v:204623$14899 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:204623$14899_Y + end + connect \$1 $not$libresoc.v:204620$14896_Y + connect \$4 $reduce_or$libresoc.v:204621$14897_Y + connect \$3 $not$libresoc.v:204622$14898_Y + connect \$7 $reduce_or$libresoc.v:204623$14899_Y + connect \en_o \$7 + connect \o { \t1 \t0 } + connect \t1 \$3 + connect \t0 \i [0] + connect \ni \$1 +end +attribute \src "libresoc.v:204633.1-204672.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_XER_xer_ca" +attribute \generator "nMigen" +module \wrpick_XER_xer_ca + attribute \src "libresoc.v:204660.17-204660.91" + wire $not$libresoc.v:204660$14900_Y + attribute \src "libresoc.v:204662.17-204662.89" + wire width 3 $not$libresoc.v:204662$14902_Y + attribute \src "libresoc.v:204664.17-204664.91" + wire $not$libresoc.v:204664$14904_Y + attribute \src "libresoc.v:204661.18-204661.90" + wire $reduce_or$libresoc.v:204661$14901_Y + attribute \src "libresoc.v:204663.17-204663.103" + wire $reduce_or$libresoc.v:204663$14903_Y + attribute \src "libresoc.v:204665.17-204665.105" + wire $reduce_or$libresoc.v:204665$14905_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 3 \$1 + attribute \src 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parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:204661$14901_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:204663$14903 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [0] \ni [1] } + connect \Y $reduce_or$libresoc.v:204663$14903_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:204665$14905 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [1:0] \ni [2] } + connect \Y $reduce_or$libresoc.v:204665$14905_Y + end + connect \$7 $not$libresoc.v:204660$14900_Y + connect \$11 $reduce_or$libresoc.v:204661$14901_Y + connect \$1 $not$libresoc.v:204662$14902_Y + connect \$4 $reduce_or$libresoc.v:204663$14903_Y + connect \$3 $not$libresoc.v:204664$14904_Y + connect \$8 $reduce_or$libresoc.v:204665$14905_Y + connect \en_o \$11 + connect \o { \t2 \t1 \t0 } + connect \t2 \$7 + connect \t1 \$3 + connect \t0 \i [0] + connect \ni \$1 +end +attribute \src "libresoc.v:204676.1-204724.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_XER_xer_ov" +attribute \generator "nMigen" +module \wrpick_XER_xer_ov + attribute \src "libresoc.v:204709.17-204709.91" + wire $not$libresoc.v:204709$14906_Y + attribute \src "libresoc.v:204711.18-204711.93" + wire $not$libresoc.v:204711$14908_Y + attribute \src "libresoc.v:204713.17-204713.89" + wire width 4 $not$libresoc.v:204713$14910_Y + attribute \src "libresoc.v:204715.17-204715.91" + wire $not$libresoc.v:204715$14912_Y + attribute \src "libresoc.v:204710.18-204710.106" + wire $reduce_or$libresoc.v:204710$14907_Y + attribute \src "libresoc.v:204712.18-204712.90" + wire $reduce_or$libresoc.v:204712$14909_Y + attribute \src "libresoc.v:204714.17-204714.103" + wire $reduce_or$libresoc.v:204714$14911_Y + attribute \src "libresoc.v:204716.17-204716.105" + wire $reduce_or$libresoc.v:204716$14913_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 4 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" + wire output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 4 input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" + wire width 4 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" + wire width 4 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:204709$14906 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $not$libresoc.v:204709$14906_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:204711$14908 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$12 + connect \Y $not$libresoc.v:204711$14908_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + cell $not $not$libresoc.v:204713$14910 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \i + connect \Y $not$libresoc.v:204713$14910_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:204715$14912 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$libresoc.v:204715$14912_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:204710$14907 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [2:0] \ni [3] } + connect \Y $reduce_or$libresoc.v:204710$14907_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" + cell $reduce_or $reduce_or$libresoc.v:204712$14909 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:204712$14909_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:204714$14911 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [0] \ni [1] } + connect \Y $reduce_or$libresoc.v:204714$14911_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:204716$14913 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [1:0] \ni [2] } + connect \Y $reduce_or$libresoc.v:204716$14913_Y + end + connect \$7 $not$libresoc.v:204709$14906_Y + connect \$12 $reduce_or$libresoc.v:204710$14907_Y + connect \$11 $not$libresoc.v:204711$14908_Y + connect \$15 $reduce_or$libresoc.v:204712$14909_Y + connect \$1 $not$libresoc.v:204713$14910_Y + connect \$4 $reduce_or$libresoc.v:204714$14911_Y + connect \$3 $not$libresoc.v:204715$14912_Y + connect \$8 $reduce_or$libresoc.v:204716$14913_Y + connect \en_o \$15 + connect \o { \t3 \t2 \t1 \t0 } + connect \t3 \$11 + connect \t2 \$7 + connect \t1 \$3 + connect \t0 \i [0] + connect \ni \$1 +end +attribute \src "libresoc.v:204728.1-204776.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_XER_xer_so" +attribute \generator "nMigen" +module \wrpick_XER_xer_so + attribute \src "libresoc.v:204761.17-204761.91" + wire $not$libresoc.v:204761$14914_Y + attribute \src "libresoc.v:204763.18-204763.93" + wire $not$libresoc.v:204763$14916_Y + attribute \src "libresoc.v:204765.17-204765.89" + wire width 4 $not$libresoc.v:204765$14918_Y + attribute \src "libresoc.v:204767.17-204767.91" + wire $not$libresoc.v:204767$14920_Y + attribute \src "libresoc.v:204762.18-204762.106" + wire $reduce_or$libresoc.v:204762$14915_Y + attribute \src "libresoc.v:204764.18-204764.90" + wire $reduce_or$libresoc.v:204764$14917_Y + attribute \src "libresoc.v:204766.17-204766.103" + wire $reduce_or$libresoc.v:204766$14919_Y + attribute \src "libresoc.v:204768.17-204768.105" + wire $reduce_or$libresoc.v:204768$14921_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire width 4 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" + wire output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" + wire width 4 input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" + wire width 4 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" + wire width 4 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:204761$14914 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $not$libresoc.v:204761$14914_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $not $not$libresoc.v:204763$14916 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + 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\A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$libresoc.v:204764$14917_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:204766$14919 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [0] \ni [1] } + connect \Y $reduce_or$libresoc.v:204766$14919_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" + cell $reduce_or $reduce_or$libresoc.v:204768$14921 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [1:0] \ni [2] } + connect \Y $reduce_or$libresoc.v:204768$14921_Y + end + connect \$7 $not$libresoc.v:204761$14914_Y + connect \$12 $reduce_or$libresoc.v:204762$14915_Y + connect \$11 $not$libresoc.v:204763$14916_Y + connect \$15 $reduce_or$libresoc.v:204764$14917_Y + connect \$1 $not$libresoc.v:204765$14918_Y + connect \$4 $reduce_or$libresoc.v:204766$14919_Y + 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wire width 2 $1\src2__data_o[1:0] + attribute \src "libresoc.v:205031.3-205040.6" + wire width 2 $1\src3__data_o[1:0] + attribute \src "libresoc.v:204947.17-204947.109" + wire width 2 $or$libresoc.v:204947$14922_Y + attribute \src "libresoc.v:204949.18-204949.126" + wire width 2 $or$libresoc.v:204949$14924_Y + attribute \src "libresoc.v:204950.18-204950.111" + wire width 2 $or$libresoc.v:204950$14925_Y + attribute \src "libresoc.v:204952.18-204952.126" + wire width 2 $or$libresoc.v:204952$14927_Y + attribute \src "libresoc.v:204953.18-204953.111" + wire width 2 $or$libresoc.v:204953$14928_Y + attribute \src "libresoc.v:204955.17-204955.125" + wire width 2 $or$libresoc.v:204955$14930_Y + attribute \src "libresoc.v:204948.18-204948.100" + wire $reduce_or$libresoc.v:204948$14923_Y + attribute \src "libresoc.v:204951.18-204951.100" + wire $reduce_or$libresoc.v:204951$14926_Y + attribute \src "libresoc.v:204954.17-204954.95" + wire $reduce_or$libresoc.v:204954$14929_Y + attribute \src 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"/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 2 \reg_0_src20__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire \reg_0_src20__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 2 \reg_0_src30__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire \reg_0_src30__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 2 \reg_0_w0__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire \reg_0_w0__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 2 \reg_1_dest11__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire \reg_1_dest11__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 2 \reg_1_dest21__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire \reg_1_dest21__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 2 \reg_1_dest31__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire \reg_1_dest31__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 2 \reg_1_r1__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire \reg_1_r1__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 2 \reg_1_src11__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire \reg_1_src11__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 2 \reg_1_src21__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire \reg_1_src21__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 2 \reg_1_src31__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire \reg_1_src31__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 2 \reg_1_w1__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire \reg_1_w1__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 2 \reg_2_dest12__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire \reg_2_dest12__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 2 \reg_2_dest22__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire \reg_2_dest22__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 2 \reg_2_dest32__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire \reg_2_dest32__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 2 \reg_2_r2__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire \reg_2_r2__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 2 \reg_2_src12__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire \reg_2_src12__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 2 \reg_2_src22__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire \reg_2_src22__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 2 \reg_2_src32__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire \reg_2_src32__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 2 \reg_2_w2__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire \reg_2_w2__wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" + wire width 3 \ren_delay + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" + wire width 3 \ren_delay$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" + wire width 3 \ren_delay$11$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" + wire width 3 \ren_delay$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" + wire width 3 \ren_delay$18$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" + wire width 3 \ren_delay$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 2 output 4 \src1__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 3 input 5 \src1__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 2 output 6 \src2__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 3 input 7 \src2__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 2 output 8 \src3__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 3 input 9 \src3__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 3 input 11 \wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 3 input 13 \wen$2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" + wire width 3 input 15 \wen$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" + cell $or $or$libresoc.v:204947$14922 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \reg_0_src10__data_o + connect \B \$7 + connect \Y $or$libresoc.v:204947$14922_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" + cell $or $or$libresoc.v:204949$14924 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \reg_1_src21__data_o + connect \B \reg_2_src22__data_o + connect \Y $or$libresoc.v:204949$14924_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" + cell $or $or$libresoc.v:204950$14925 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \reg_0_src20__data_o + connect \B \$14 + connect \Y $or$libresoc.v:204950$14925_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" + cell $or $or$libresoc.v:204952$14927 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \reg_1_src31__data_o + connect \B \reg_2_src32__data_o + connect \Y $or$libresoc.v:204952$14927_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" + cell $or $or$libresoc.v:204953$14928 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \reg_0_src30__data_o + connect \B \$21 + connect \Y $or$libresoc.v:204953$14928_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" + cell $or $or$libresoc.v:204955$14930 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \reg_1_src11__data_o + connect \B \reg_2_src12__data_o + connect \Y $or$libresoc.v:204955$14930_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + cell $reduce_or $reduce_or$libresoc.v:204948$14923 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \ren_delay$11 + connect \Y $reduce_or$libresoc.v:204948$14923_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + cell $reduce_or $reduce_or$libresoc.v:204951$14926 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \ren_delay$18 + connect \Y $reduce_or$libresoc.v:204951$14926_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + cell $reduce_or $reduce_or$libresoc.v:204954$14929 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \ren_delay + connect \Y $reduce_or$libresoc.v:204954$14929_Y + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:204962.15-204981.4" + cell \reg_0$132 \reg_0 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \dest10__data_i \reg_0_dest10__data_i + connect \dest10__wen \reg_0_dest10__wen + connect \dest20__data_i \reg_0_dest20__data_i + connect \dest20__wen \reg_0_dest20__wen + connect \dest30__data_i \reg_0_dest30__data_i + connect \dest30__wen \reg_0_dest30__wen + connect \r0__data_o \reg_0_r0__data_o + connect \r0__ren \reg_0_r0__ren + connect \src10__data_o \reg_0_src10__data_o + connect \src10__ren \reg_0_src10__ren + connect \src20__data_o \reg_0_src20__data_o + connect \src20__ren \reg_0_src20__ren + connect \src30__data_o \reg_0_src30__data_o + connect \src30__ren \reg_0_src30__ren + connect \w0__data_i \reg_0_w0__data_i + connect \w0__wen \reg_0_w0__wen + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:204982.15-205001.4" + cell \reg_1$133 \reg_1 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \dest11__data_i \reg_1_dest11__data_i + connect \dest11__wen \reg_1_dest11__wen + connect \dest21__data_i \reg_1_dest21__data_i + connect \dest21__wen \reg_1_dest21__wen + connect \dest31__data_i \reg_1_dest31__data_i + connect \dest31__wen \reg_1_dest31__wen + connect \r1__data_o \reg_1_r1__data_o + connect \r1__ren \reg_1_r1__ren + connect \src11__data_o \reg_1_src11__data_o + connect \src11__ren \reg_1_src11__ren + connect \src21__data_o \reg_1_src21__data_o + connect \src21__ren \reg_1_src21__ren + connect \src31__data_o \reg_1_src31__data_o + connect \src31__ren \reg_1_src31__ren + connect \w1__data_i \reg_1_w1__data_i + connect \w1__wen \reg_1_w1__wen + end + attribute \module_not_derived 1 + attribute \src "libresoc.v:205002.15-205021.4" + cell \reg_2$134 \reg_2 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \dest12__data_i \reg_2_dest12__data_i + connect \dest12__wen \reg_2_dest12__wen + connect \dest22__data_i \reg_2_dest22__data_i + connect \dest22__wen \reg_2_dest22__wen + connect \dest32__data_i \reg_2_dest32__data_i + connect \dest32__wen \reg_2_dest32__wen + connect \r2__data_o \reg_2_r2__data_o + connect \r2__ren \reg_2_r2__ren + connect \src12__data_o \reg_2_src12__data_o + connect \src12__ren \reg_2_src12__ren + connect \src22__data_o \reg_2_src22__data_o + connect \src22__ren \reg_2_src22__ren + connect \src32__data_o \reg_2_src32__data_o + connect \src32__ren \reg_2_src32__ren + connect \w2__data_i \reg_2_w2__data_i + connect \w2__wen \reg_2_w2__wen + end + attribute \src "libresoc.v:204781.7-204781.20" + process $proc$libresoc.v:204781$14948 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:204915.13-204915.29" + process $proc$libresoc.v:204915$14949 + assign { } { } + assign $1\ren_delay[2:0] 3'000 + sync always + sync init + update \ren_delay $1\ren_delay[2:0] + end + attribute \src "libresoc.v:204917.13-204917.34" + process $proc$libresoc.v:204917$14950 + assign { } { } + assign $0\ren_delay$11[2:0]$14951 3'000 + sync always + sync init + update \ren_delay$11 $0\ren_delay$11[2:0]$14951 + end + attribute \src "libresoc.v:204921.13-204921.34" + process $proc$libresoc.v:204921$14952 + assign { } { } + assign $0\ren_delay$18[2:0]$14953 3'000 + sync always + sync init + update \ren_delay$18 $0\ren_delay$18[2:0]$14953 + end + attribute \src "libresoc.v:204956.3-204957.43" + process $proc$libresoc.v:204956$14931 + assign { } { } + assign $0\ren_delay$18[2:0]$14932 \ren_delay$18$next + sync posedge \coresync_clk + update \ren_delay$18 $0\ren_delay$18[2:0]$14932 + end + attribute \src "libresoc.v:204958.3-204959.43" + process $proc$libresoc.v:204958$14933 + assign { } { } + assign $0\ren_delay$11[2:0]$14934 \ren_delay$11$next + sync posedge \coresync_clk + update \ren_delay$11 $0\ren_delay$11[2:0]$14934 + end + attribute \src "libresoc.v:204960.3-204961.35" + process $proc$libresoc.v:204960$14935 + assign { } { } + assign $0\ren_delay[2:0] \ren_delay$next + sync posedge \coresync_clk + update \ren_delay $0\ren_delay[2:0] + end + attribute \src "libresoc.v:205022.3-205030.6" + process $proc$libresoc.v:205022$14936 + assign { } { } + assign { } { } + assign $0\ren_delay$18$next[2:0]$14937 $1\ren_delay$18$next[2:0]$14938 + attribute \src "libresoc.v:205023.5-205023.29" + switch \initial + attribute \src "libresoc.v:205023.9-205023.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ren_delay$18$next[2:0]$14938 3'000 + case + assign $1\ren_delay$18$next[2:0]$14938 \src3__ren + end + sync always + update \ren_delay$18$next $0\ren_delay$18$next[2:0]$14937 + end + attribute \src "libresoc.v:205031.3-205040.6" + process $proc$libresoc.v:205031$14939 + assign { } { } + assign { } { } + assign $0\src3__data_o[1:0] $1\src3__data_o[1:0] + attribute \src "libresoc.v:205032.5-205032.29" + switch \initial + attribute \src "libresoc.v:205032.9-205032.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" + switch \$19 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src3__data_o[1:0] \$23 + case + assign $1\src3__data_o[1:0] 2'00 + end + sync always + update \src3__data_o $0\src3__data_o[1:0] + end + attribute \src "libresoc.v:205041.3-205049.6" + process $proc$libresoc.v:205041$14940 + assign { } { } + assign { } { } + assign $0\ren_delay$next[2:0]$14941 $1\ren_delay$next[2:0]$14942 + attribute \src "libresoc.v:205042.5-205042.29" + switch \initial + attribute \src "libresoc.v:205042.9-205042.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ren_delay$next[2:0]$14942 3'000 + case + assign $1\ren_delay$next[2:0]$14942 \src1__ren + end + sync always + update \ren_delay$next $0\ren_delay$next[2:0]$14941 + end + attribute \src "libresoc.v:205050.3-205059.6" + process $proc$libresoc.v:205050$14943 + assign { } { } + assign { } { } + assign $0\src1__data_o[1:0] $1\src1__data_o[1:0] + attribute \src "libresoc.v:205051.5-205051.29" + switch \initial + attribute \src "libresoc.v:205051.9-205051.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" + switch \$5 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src1__data_o[1:0] \$9 + case + assign $1\src1__data_o[1:0] 2'00 + end + sync always + update \src1__data_o $0\src1__data_o[1:0] + end + attribute \src "libresoc.v:205060.3-205068.6" + process $proc$libresoc.v:205060$14944 + assign { } { } + assign { } { } + assign $0\ren_delay$11$next[2:0]$14945 $1\ren_delay$11$next[2:0]$14946 + attribute \src "libresoc.v:205061.5-205061.29" + switch \initial + attribute \src "libresoc.v:205061.9-205061.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ren_delay$11$next[2:0]$14946 3'000 + case + assign $1\ren_delay$11$next[2:0]$14946 \src2__ren + end + sync always + update \ren_delay$11$next $0\ren_delay$11$next[2:0]$14945 + end + attribute \src "libresoc.v:205069.3-205078.6" + process $proc$libresoc.v:205069$14947 + assign { } { } + assign { } { } + assign $0\src2__data_o[1:0] $1\src2__data_o[1:0] + attribute \src "libresoc.v:205070.5-205070.29" + switch \initial + attribute \src "libresoc.v:205070.9-205070.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" + switch \$12 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src2__data_o[1:0] \$16 + case + assign $1\src2__data_o[1:0] 2'00 + end + sync always + update \src2__data_o $0\src2__data_o[1:0] + end + connect \$9 $or$libresoc.v:204947$14922_Y + connect \$12 $reduce_or$libresoc.v:204948$14923_Y + connect \$14 $or$libresoc.v:204949$14924_Y + connect \$16 $or$libresoc.v:204950$14925_Y + connect \$19 $reduce_or$libresoc.v:204951$14926_Y + connect \$21 $or$libresoc.v:204952$14927_Y + connect \$23 $or$libresoc.v:204953$14928_Y + connect \$5 $reduce_or$libresoc.v:204954$14929_Y + connect \$7 $or$libresoc.v:204955$14930_Y + connect \full_wr__data_i 6'000000 + connect \full_wr__wen 3'000 + connect { \reg_2_w2__wen \reg_1_w1__wen \reg_0_w0__wen } 3'000 + connect { \reg_2_w2__data_i \reg_1_w1__data_i \reg_0_w0__data_i } 6'000000 + connect { \reg_2_r2__ren \reg_1_r1__ren \reg_0_r0__ren } \full_rd__ren + connect \full_rd__data_o { \reg_2_r2__data_o \reg_1_r1__data_o \reg_0_r0__data_o } + connect \reg_2_dest32__data_i \data_i$1 + connect \reg_1_dest31__data_i \data_i$1 + connect \reg_0_dest30__data_i \data_i$1 + connect { \reg_2_dest32__wen \reg_1_dest31__wen \reg_0_dest30__wen } \wen$2 + connect \reg_2_dest22__data_i \data_i + connect \reg_1_dest21__data_i \data_i + connect \reg_0_dest20__data_i \data_i + connect { \reg_2_dest22__wen \reg_1_dest21__wen \reg_0_dest20__wen } \wen + connect \reg_2_dest12__data_i \data_i$3 + connect \reg_1_dest11__data_i \data_i$3 + connect \reg_0_dest10__data_i \data_i$3 + connect { \reg_2_dest12__wen \reg_1_dest11__wen \reg_0_dest10__wen } \wen$4 + connect { \reg_2_src32__ren \reg_1_src31__ren \reg_0_src30__ren } \src3__ren + connect { \reg_2_src22__ren \reg_1_src21__ren \reg_0_src20__ren } \src2__ren + connect { \reg_2_src12__ren \reg_1_src11__ren \reg_0_src10__ren } \src1__ren +end +attribute \src "libresoc.v:205104.1-205418.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.xics_icp" +attribute \generator "nMigen" +module \xics_icp + attribute \src "libresoc.v:205282.3-205310.6" + wire width 32 $0\be_out[31:0] + attribute \src "libresoc.v:205333.3-205341.6" + wire $0\core_irq_o$next[0:0]$14989 + attribute \src "libresoc.v:205224.3-205225.37" + wire $0\core_irq_o[0:0] + attribute \src "libresoc.v:205352.3-205414.6" + wire width 8 $0\cppr$10[7:0]$14993 + attribute \src "libresoc.v:205238.3-205253.6" + wire width 8 $0\cppr$next[7:0]$14972 + attribute \src "libresoc.v:205228.3-205229.25" + wire width 8 $0\cppr[7:0] + attribute \src "libresoc.v:205342.3-205351.6" + wire width 32 $0\icp_wb__dat_r[31:0] + attribute \src "libresoc.v:205105.7-205105.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:205352.3-205414.6" + wire $0\irq$12[0:0]$14994 + attribute \src "libresoc.v:205238.3-205253.6" + wire $0\irq$next[0:0]$14973 + attribute \src "libresoc.v:205232.3-205233.23" + wire $0\irq[0:0] + attribute \src "libresoc.v:205352.3-205414.6" + wire width 8 $0\mfrr$11[7:0]$14995 + attribute \src "libresoc.v:205238.3-205253.6" + wire width 8 $0\mfrr$next[7:0]$14974 + attribute \src "libresoc.v:205230.3-205231.25" + wire width 8 $0\mfrr[7:0] + attribute \src "libresoc.v:205321.3-205332.6" + wire width 8 $0\min_pri[7:0] + attribute \src "libresoc.v:205311.3-205320.6" + wire width 8 $0\pending_priority[7:0] + attribute \src "libresoc.v:205352.3-205414.6" + wire $0\wb_ack$14[0:0]$14996 + attribute \src "libresoc.v:205238.3-205253.6" + wire $0\wb_ack$next[0:0]$14975 + attribute \src "libresoc.v:205236.3-205237.29" + wire $0\wb_ack[0:0] + attribute \src "libresoc.v:205352.3-205414.6" + wire width 32 $0\wb_rd_data$13[31:0]$14997 + attribute \src "libresoc.v:205238.3-205253.6" + wire width 32 $0\wb_rd_data$next[31:0]$14976 + attribute \src "libresoc.v:205234.3-205235.37" + wire width 32 $0\wb_rd_data[31:0] + attribute \src "libresoc.v:205254.3-205281.6" + wire $0\xirr_accept_rd[0:0] + attribute \src "libresoc.v:205352.3-205414.6" + wire width 24 $0\xisr$9[23:0]$14998 + attribute \src "libresoc.v:205238.3-205253.6" + wire width 24 $0\xisr$next[23:0]$14977 + attribute \src "libresoc.v:205226.3-205227.25" + wire width 24 $0\xisr[23:0] + attribute \src "libresoc.v:205282.3-205310.6" + wire width 32 $1\be_out[31:0] + attribute \src "libresoc.v:205333.3-205341.6" + wire $1\core_irq_o$next[0:0]$14990 + attribute \src "libresoc.v:205134.7-205134.24" + wire $1\core_irq_o[0:0] + attribute \src "libresoc.v:205352.3-205414.6" + wire width 8 $1\cppr$10[7:0]$14999 + attribute \src "libresoc.v:205238.3-205253.6" + wire width 8 $1\cppr$next[7:0]$14978 + attribute \src "libresoc.v:205138.13-205138.25" + wire width 8 $1\cppr[7:0] + attribute \src "libresoc.v:205342.3-205351.6" + wire width 32 $1\icp_wb__dat_r[31:0] + attribute \src "libresoc.v:205352.3-205414.6" + wire $1\irq$12[0:0]$15009 + attribute \src "libresoc.v:205238.3-205253.6" + wire $1\irq$next[0:0]$14979 + attribute \src "libresoc.v:205167.7-205167.17" + wire $1\irq[0:0] + attribute \src "libresoc.v:205352.3-205414.6" + wire width 8 $1\mfrr$11[7:0]$15000 + attribute \src "libresoc.v:205238.3-205253.6" + wire width 8 $1\mfrr$next[7:0]$14980 + attribute \src "libresoc.v:205175.13-205175.25" + wire width 8 $1\mfrr[7:0] + attribute \src "libresoc.v:205321.3-205332.6" + wire width 8 $1\min_pri[7:0] + attribute \src "libresoc.v:205311.3-205320.6" + wire width 8 $1\pending_priority[7:0] + attribute \src "libresoc.v:205352.3-205414.6" + wire $1\wb_ack$14[0:0]$15001 + attribute \src "libresoc.v:205238.3-205253.6" + wire $1\wb_ack$next[0:0]$14981 + attribute \src "libresoc.v:205189.7-205189.20" + wire $1\wb_ack[0:0] + attribute \src "libresoc.v:205238.3-205253.6" + wire width 32 $1\wb_rd_data$next[31:0]$14982 + attribute \src "libresoc.v:205197.14-205197.32" + wire width 32 $1\wb_rd_data[31:0] + attribute \src "libresoc.v:205254.3-205281.6" + wire $1\xirr_accept_rd[0:0] + attribute \src "libresoc.v:205352.3-205414.6" + wire width 24 $1\xisr$9[23:0]$15006 + attribute \src "libresoc.v:205238.3-205253.6" + wire width 24 $1\xisr$next[23:0]$14983 + attribute \src "libresoc.v:205207.14-205207.31" + wire width 24 $1\xisr[23:0] + attribute \src "libresoc.v:205282.3-205310.6" + wire width 32 $2\be_out[31:0] + attribute \src "libresoc.v:205352.3-205414.6" + wire width 8 $2\cppr$10[7:0]$15002 + attribute \src "libresoc.v:205352.3-205414.6" + wire width 8 $2\mfrr$11[7:0]$15003 + attribute \src "libresoc.v:205254.3-205281.6" + wire $2\xirr_accept_rd[0:0] + attribute \src "libresoc.v:205352.3-205414.6" + wire width 24 $2\xisr$9[23:0]$15007 + attribute \src "libresoc.v:205282.3-205310.6" + wire width 32 $3\be_out[31:0] + attribute \src "libresoc.v:205352.3-205414.6" + wire width 8 $3\cppr$10[7:0]$15004 + attribute \src "libresoc.v:205352.3-205414.6" + wire width 8 $3\mfrr$11[7:0]$15005 + attribute \src "libresoc.v:205254.3-205281.6" + wire $3\xirr_accept_rd[0:0] + attribute \src "libresoc.v:205352.3-205414.6" + wire width 8 $4\cppr$10[7:0]$15008 + attribute \src "libresoc.v:205254.3-205281.6" + wire $4\xirr_accept_rd[0:0] + attribute \src "libresoc.v:205214.18-205214.116" + wire $and$libresoc.v:205214$14954_Y + attribute \src "libresoc.v:205218.18-205218.116" + wire $and$libresoc.v:205218$14958_Y + attribute \src "libresoc.v:205220.18-205220.116" + wire $and$libresoc.v:205220$14960_Y + attribute \src "libresoc.v:205223.17-205223.109" + wire $and$libresoc.v:205223$14963_Y + attribute \src "libresoc.v:205219.18-205219.110" + wire $eq$libresoc.v:205219$14959_Y + attribute \src "libresoc.v:205216.18-205216.114" + wire $lt$libresoc.v:205216$14956_Y + attribute \src "libresoc.v:205217.18-205217.109" + wire $lt$libresoc.v:205217$14957_Y + attribute \src "libresoc.v:205222.18-205222.114" + wire $lt$libresoc.v:205222$14962_Y + attribute \src "libresoc.v:205215.18-205215.109" + wire $ne$libresoc.v:205215$14955_Y + attribute \src "libresoc.v:205221.18-205221.109" + wire $ne$libresoc.v:205221$14961_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173" + wire \$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:178" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:195" + wire \$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:162" + wire \$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173" + wire \$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:178" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:96" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:103" + wire width 32 \be_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:104" + wire width 32 \be_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:194" + wire input 13 \clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:83" + wire output 4 \core_irq_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:83" + wire \core_irq_o$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:62" + wire width 8 \cppr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:62" + wire width 8 \cppr$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:62" + wire width 8 \cppr$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:62" + wire width 8 \cppr$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire output 5 \icp_wb__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire width 28 input 11 \icp_wb__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire input 6 \icp_wb__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire width 32 output 7 \icp_wb__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire width 32 input 8 \icp_wb__dat_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire width 4 input 12 \icp_wb__sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire input 9 \icp_wb__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire input 10 \icp_wb__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:46" + wire width 8 input 3 \ics_i_pri + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:45" + wire width 4 input 2 \ics_i_src + attribute \src "libresoc.v:205105.7-205105.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:64" + wire \irq + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:64" + wire \irq$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:64" + wire \irq$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:64" + wire \irq$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:63" + wire width 8 \mfrr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:63" + wire width 8 \mfrr$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:63" + wire width 8 \mfrr$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:63" + wire width 8 \mfrr$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:107" + wire width 8 \min_pri + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:106" + wire width 8 \pending_priority + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:194" + wire input 1 \rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:66" + wire \wb_ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:66" + wire \wb_ack$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:66" + wire \wb_ack$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:66" + wire \wb_ack$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:65" + wire width 32 \wb_rd_data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:65" + wire width 32 \wb_rd_data$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:65" + wire width 32 \wb_rd_data$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:65" + wire width 32 \wb_rd_data$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:101" + wire \xirr_accept_rd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:61" + wire width 24 \xisr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:61" + wire width 24 \xisr$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:61" + wire width 24 \xisr$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:61" + wire width 24 \xisr$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" + cell $and $and$libresoc.v:205214$14954 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \icp_wb__cyc + connect \B \icp_wb__stb + connect \Y $and$libresoc.v:205214$14954_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" + cell $and $and$libresoc.v:205218$14958 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \icp_wb__cyc + connect \B \icp_wb__stb + connect \Y $and$libresoc.v:205218$14958_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" + cell $and $and$libresoc.v:205220$14960 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \icp_wb__cyc + connect \B \icp_wb__stb + connect \Y $and$libresoc.v:205220$14960_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:96" + cell $and $and$libresoc.v:205223$14963 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wb_ack + connect \B \icp_wb__cyc + connect \Y $and$libresoc.v:205223$14963_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:162" + cell $eq $eq$libresoc.v:205219$14959 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \icp_wb__sel + connect \B 4'1111 + connect \Y $eq$libresoc.v:205219$14959_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:178" + cell $lt $lt$libresoc.v:205216$14956 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \mfrr + connect \B \pending_priority + connect \Y $lt$libresoc.v:205216$14956_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:195" + cell $lt $lt$libresoc.v:205217$14957 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \min_pri + connect \B \cppr$10 + connect \Y $lt$libresoc.v:205217$14957_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:178" + cell $lt $lt$libresoc.v:205222$14962 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \mfrr + connect \B \pending_priority + connect \Y $lt$libresoc.v:205222$14962_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173" + cell $ne $ne$libresoc.v:205215$14955 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ics_i_pri + connect \B 8'11111111 + connect \Y $ne$libresoc.v:205215$14955_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173" + cell $ne $ne$libresoc.v:205221$14961 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ics_i_pri + connect \B 8'11111111 + connect \Y $ne$libresoc.v:205221$14961_Y + end + attribute \src "libresoc.v:205105.7-205105.20" + process $proc$libresoc.v:205105$15010 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:205134.7-205134.24" + process $proc$libresoc.v:205134$15011 + assign { } { } + assign $1\core_irq_o[0:0] 1'0 + sync always + sync init + update \core_irq_o $1\core_irq_o[0:0] + end + attribute \src "libresoc.v:205138.13-205138.25" + process $proc$libresoc.v:205138$15012 + assign { } { } + assign $1\cppr[7:0] 8'00000000 + sync always + sync init + update \cppr $1\cppr[7:0] + end + attribute \src "libresoc.v:205167.7-205167.17" + process $proc$libresoc.v:205167$15013 + assign { } { } + assign $1\irq[0:0] 1'0 + sync always + sync init + update \irq $1\irq[0:0] + end + attribute \src "libresoc.v:205175.13-205175.25" + process $proc$libresoc.v:205175$15014 + assign { } { } + assign $1\mfrr[7:0] 8'11111111 + sync always + sync init + update \mfrr $1\mfrr[7:0] + end + attribute \src "libresoc.v:205189.7-205189.20" + process $proc$libresoc.v:205189$15015 + assign { } { } + assign $1\wb_ack[0:0] 1'0 + sync always + sync init + update \wb_ack $1\wb_ack[0:0] + end + attribute \src "libresoc.v:205197.14-205197.32" + process $proc$libresoc.v:205197$15016 + assign { } { } + assign $1\wb_rd_data[31:0] 0 + sync always + sync init + update \wb_rd_data $1\wb_rd_data[31:0] + end + attribute \src "libresoc.v:205207.14-205207.31" + process $proc$libresoc.v:205207$15017 + assign { } { } + assign $1\xisr[23:0] 24'000000000000000000000000 + sync always + sync init + update \xisr $1\xisr[23:0] + end + attribute \src "libresoc.v:205224.3-205225.37" + process $proc$libresoc.v:205224$14964 + assign { } { } + assign $0\core_irq_o[0:0] \core_irq_o$next + sync posedge \clk + update \core_irq_o $0\core_irq_o[0:0] + end + attribute \src "libresoc.v:205226.3-205227.25" + process $proc$libresoc.v:205226$14965 + assign { } { } + assign $0\xisr[23:0] \xisr$next + sync posedge \clk + update \xisr $0\xisr[23:0] + end + attribute \src "libresoc.v:205228.3-205229.25" + process $proc$libresoc.v:205228$14966 + assign { } { } + assign $0\cppr[7:0] \cppr$next + sync posedge \clk + update \cppr $0\cppr[7:0] + end + attribute \src "libresoc.v:205230.3-205231.25" + process $proc$libresoc.v:205230$14967 + assign { } { } + assign $0\mfrr[7:0] \mfrr$next + sync posedge \clk + update \mfrr $0\mfrr[7:0] + end + attribute \src "libresoc.v:205232.3-205233.23" + process $proc$libresoc.v:205232$14968 + assign { } { } + assign $0\irq[0:0] \irq$next + sync posedge \clk + update \irq $0\irq[0:0] + end + attribute \src "libresoc.v:205234.3-205235.37" + process $proc$libresoc.v:205234$14969 + assign { } { } + assign $0\wb_rd_data[31:0] \wb_rd_data$next + sync posedge \clk + update \wb_rd_data $0\wb_rd_data[31:0] + end + attribute \src "libresoc.v:205236.3-205237.29" + process $proc$libresoc.v:205236$14970 + assign { } { } + assign $0\wb_ack[0:0] \wb_ack$next + sync posedge \clk + update \wb_ack $0\wb_ack[0:0] + end + attribute \src "libresoc.v:205238.3-205253.6" + process $proc$libresoc.v:205238$14971 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\cppr$next[7:0]$14972 $1\cppr$next[7:0]$14978 + assign $0\irq$next[0:0]$14973 $1\irq$next[0:0]$14979 + assign $0\mfrr$next[7:0]$14974 $1\mfrr$next[7:0]$14980 + assign $0\wb_ack$next[0:0]$14975 $1\wb_ack$next[0:0]$14981 + assign $0\wb_rd_data$next[31:0]$14976 $1\wb_rd_data$next[31:0]$14982 + assign $0\xisr$next[23:0]$14977 $1\xisr$next[23:0]$14983 + attribute \src "libresoc.v:205239.5-205239.29" + switch \initial + attribute \src "libresoc.v:205239.9-205239.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\xisr$next[23:0]$14983 24'000000000000000000000000 + assign $1\cppr$next[7:0]$14978 8'00000000 + assign $1\mfrr$next[7:0]$14980 8'11111111 + assign $1\irq$next[0:0]$14979 1'0 + assign $1\wb_rd_data$next[31:0]$14982 0 + assign $1\wb_ack$next[0:0]$14981 1'0 + case + assign $1\cppr$next[7:0]$14978 \cppr$2 + assign $1\irq$next[0:0]$14979 \irq$4 + assign $1\mfrr$next[7:0]$14980 \mfrr$3 + assign $1\wb_ack$next[0:0]$14981 \wb_ack$6 + assign $1\wb_rd_data$next[31:0]$14982 \wb_rd_data$5 + assign $1\xisr$next[23:0]$14983 \xisr$1 + end + sync always + update \cppr$next $0\cppr$next[7:0]$14972 + update \irq$next $0\irq$next[0:0]$14973 + update \mfrr$next $0\mfrr$next[7:0]$14974 + update \wb_ack$next $0\wb_ack$next[0:0]$14975 + update \wb_rd_data$next $0\wb_rd_data$next[31:0]$14976 + update \xisr$next $0\xisr$next[23:0]$14977 + end + attribute \src "libresoc.v:205254.3-205281.6" + process $proc$libresoc.v:205254$14984 + assign { } { } + assign { } { } + assign $0\xirr_accept_rd[0:0] $1\xirr_accept_rd[0:0] + attribute \src "libresoc.v:205255.5-205255.29" + switch \initial + attribute \src "libresoc.v:205255.9-205255.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" + switch \$23 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\xirr_accept_rd[0:0] $2\xirr_accept_rd[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:119" + switch \icp_wb__we + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $2\xirr_accept_rd[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\xirr_accept_rd[0:0] $3\xirr_accept_rd[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:155" + switch \icp_wb__adr [5:0] + attribute \src "libresoc.v:0.0-0.0" + case 6'000001 + assign { } { } + assign $3\xirr_accept_rd[0:0] $4\xirr_accept_rd[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:162" + switch \$25 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\xirr_accept_rd[0:0] 1'1 + case + assign $4\xirr_accept_rd[0:0] 1'0 + end + case + assign $3\xirr_accept_rd[0:0] 1'0 + end + end + case + assign $1\xirr_accept_rd[0:0] 1'0 + end + sync always + update \xirr_accept_rd $0\xirr_accept_rd[0:0] + end + attribute \src "libresoc.v:205282.3-205310.6" + process $proc$libresoc.v:205282$14985 + assign { } { } + assign { } { } + assign $0\be_out[31:0] $1\be_out[31:0] + attribute \src "libresoc.v:205283.5-205283.29" + switch \initial + attribute \src "libresoc.v:205283.9-205283.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" + switch \$27 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\be_out[31:0] $2\be_out[31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:119" + switch \icp_wb__we + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign $2\be_out[31:0] 0 + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $2\be_out[31:0] $3\be_out[31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:155" + switch \icp_wb__adr [5:0] + attribute \src "libresoc.v:0.0-0.0" + case 6'000000 + assign { } { } + assign $3\be_out[31:0] { \cppr \xisr } + attribute \src "libresoc.v:0.0-0.0" + case 6'000001 + assign { } { } + assign $3\be_out[31:0] { \cppr \xisr } + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign $3\be_out[31:0] [23:0] 24'000000000000000000000000 + assign $3\be_out[31:0] [31:24] \mfrr + case + assign $3\be_out[31:0] 0 + end + end + case + assign $1\be_out[31:0] 0 + end + sync always + update \be_out $0\be_out[31:0] + end + attribute \src "libresoc.v:205311.3-205320.6" + process $proc$libresoc.v:205311$14986 + assign { } { } + assign { } { } + assign $0\pending_priority[7:0] $1\pending_priority[7:0] + attribute \src "libresoc.v:205312.5-205312.29" + switch \initial + attribute \src "libresoc.v:205312.9-205312.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173" + switch \$29 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\pending_priority[7:0] \ics_i_pri + case + assign $1\pending_priority[7:0] 8'11111111 + end + sync always + update \pending_priority $0\pending_priority[7:0] + end + attribute \src "libresoc.v:205321.3-205332.6" + process $proc$libresoc.v:205321$14987 + assign { } { } + assign $0\min_pri[7:0] $1\min_pri[7:0] + attribute \src "libresoc.v:205322.5-205322.29" + switch \initial + attribute \src "libresoc.v:205322.9-205322.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:178" + switch \$31 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\min_pri[7:0] \mfrr + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\min_pri[7:0] \pending_priority + end + sync always + update \min_pri $0\min_pri[7:0] + end + attribute \src "libresoc.v:205333.3-205341.6" + process $proc$libresoc.v:205333$14988 + assign { } { } + assign { } { } + assign $0\core_irq_o$next[0:0]$14989 $1\core_irq_o$next[0:0]$14990 + attribute \src "libresoc.v:205334.5-205334.29" + switch \initial + attribute \src "libresoc.v:205334.9-205334.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\core_irq_o$next[0:0]$14990 1'0 + case + assign $1\core_irq_o$next[0:0]$14990 \irq + end + sync always + update \core_irq_o$next $0\core_irq_o$next[0:0]$14989 + end + attribute \src "libresoc.v:205342.3-205351.6" + process $proc$libresoc.v:205342$14991 + assign { } { } + assign { } { } + assign $0\icp_wb__dat_r[31:0] $1\icp_wb__dat_r[31:0] + attribute \src "libresoc.v:205343.5-205343.29" + switch \initial + attribute \src "libresoc.v:205343.9-205343.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:97" + switch \icp_wb__ack + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\icp_wb__dat_r[31:0] \wb_rd_data + case + assign $1\icp_wb__dat_r[31:0] 0 + end + sync always + update \icp_wb__dat_r $0\icp_wb__dat_r[31:0] + end + attribute \src "libresoc.v:205352.3-205414.6" + process $proc$libresoc.v:205352$14992 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\mfrr$11[7:0]$14995 $1\mfrr$11[7:0]$15000 + assign $0\wb_ack$14[0:0]$14996 $1\wb_ack$14[0:0]$15001 + assign { } { } + assign { } { } + assign { } { } + assign $0\xisr$9[23:0]$14998 $2\xisr$9[23:0]$15007 + assign $0\cppr$10[7:0]$14993 $4\cppr$10[7:0]$15008 + assign $0\wb_rd_data$13[31:0]$14997 { \be_out [7:0] \be_out [15:8] \be_out [23:16] \be_out [31:24] } + assign $0\irq$12[0:0]$14994 $1\irq$12[0:0]$15009 + attribute \src "libresoc.v:205353.5-205353.29" + switch \initial + attribute \src "libresoc.v:205353.9-205353.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" + switch \$15 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign $1\wb_ack$14[0:0]$15001 1'1 + assign $1\cppr$10[7:0]$14999 $2\cppr$10[7:0]$15002 + assign $1\mfrr$11[7:0]$15000 $2\mfrr$11[7:0]$15003 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:119" + switch \icp_wb__we + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $2\cppr$10[7:0]$15002 $3\cppr$10[7:0]$15004 + assign $2\mfrr$11[7:0]$15003 $3\mfrr$11[7:0]$15005 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:121" + switch \icp_wb__adr [5:0] + attribute \src "libresoc.v:0.0-0.0" + case 6'000000 + assign { } { } + assign $3\mfrr$11[7:0]$15005 \mfrr + assign $3\cppr$10[7:0]$15004 \be_in [31:24] + attribute \src "libresoc.v:0.0-0.0" + case 6'000001 + assign { } { } + assign $3\mfrr$11[7:0]$15005 \mfrr + assign $3\cppr$10[7:0]$15004 \be_in [31:24] + attribute \src "libresoc.v:0.0-0.0" + case 6'000011 + assign $3\cppr$10[7:0]$15004 \cppr + assign { } { } + assign $3\mfrr$11[7:0]$15005 \be_in [31:24] + case + assign $3\cppr$10[7:0]$15004 \cppr + assign $3\mfrr$11[7:0]$15005 \mfrr + end + case + assign $2\cppr$10[7:0]$15002 \cppr + assign $2\mfrr$11[7:0]$15003 \mfrr + end + case + assign $1\cppr$10[7:0]$14999 \cppr + assign $1\mfrr$11[7:0]$15000 \mfrr + assign $1\wb_ack$14[0:0]$15001 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173" + switch \$17 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\xisr$9[23:0]$15006 { 20'00000000000000000001 \ics_i_src } + case + assign $1\xisr$9[23:0]$15006 24'000000000000000000000000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:178" + switch \$19 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\xisr$9[23:0]$15007 24'000000000000000000000010 + case + assign $2\xisr$9[23:0]$15007 $1\xisr$9[23:0]$15006 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:185" + switch \xirr_accept_rd + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\cppr$10[7:0]$15008 \min_pri + case + assign $4\cppr$10[7:0]$15008 $1\cppr$10[7:0]$14999 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:195" + switch { \irq \$21 } + attribute \src "libresoc.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\irq$12[0:0]$15009 1'1 + case + assign $1\irq$12[0:0]$15009 1'0 + end + sync always + update \cppr$10 $0\cppr$10[7:0]$14993 + update \irq$12 $0\irq$12[0:0]$14994 + update \mfrr$11 $0\mfrr$11[7:0]$14995 + update \wb_ack$14 $0\wb_ack$14[0:0]$14996 + update \wb_rd_data$13 $0\wb_rd_data$13[31:0]$14997 + update \xisr$9 $0\xisr$9[23:0]$14998 + end + connect \$15 $and$libresoc.v:205214$14954_Y + connect \$17 $ne$libresoc.v:205215$14955_Y + connect \$19 $lt$libresoc.v:205216$14956_Y + connect \$21 $lt$libresoc.v:205217$14957_Y + connect \$23 $and$libresoc.v:205218$14958_Y + connect \$25 $eq$libresoc.v:205219$14959_Y + connect \$27 $and$libresoc.v:205220$14960_Y + connect \$29 $ne$libresoc.v:205221$14961_Y + connect \$31 $lt$libresoc.v:205222$14962_Y + connect \$7 $and$libresoc.v:205223$14963_Y + connect { \wb_ack$6 \wb_rd_data$5 \irq$4 \mfrr$3 \cppr$2 \xisr$1 } { \wb_ack$14 \wb_rd_data$13 \irq$12 \mfrr$11 \cppr$10 \xisr$9 } + connect \be_in { \icp_wb__dat_w [7:0] \icp_wb__dat_w [15:8] \icp_wb__dat_w [23:16] \icp_wb__dat_w [31:24] } + connect \icp_wb__ack \$7 +end +attribute \src "libresoc.v:205422.1-206471.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.ti.xics_ics" +attribute \generator "nMigen" +module \xics_ics + attribute \src "libresoc.v:206352.3-206401.6" + wire width 32 $0\be_out[31:0] + attribute \src "libresoc.v:206063.3-206072.6" + wire width 4 $0\cur_idx0[3:0] + attribute \src "libresoc.v:206272.3-206281.6" + wire width 4 $0\cur_idx10[3:0] + attribute \src "libresoc.v:206292.3-206301.6" + wire width 4 $0\cur_idx11[3:0] + attribute \src "libresoc.v:206312.3-206321.6" + wire width 4 $0\cur_idx12[3:0] + attribute \src "libresoc.v:206332.3-206341.6" + wire width 4 $0\cur_idx13[3:0] + attribute \src "libresoc.v:206402.3-206411.6" + wire width 4 $0\cur_idx14[3:0] + attribute \src "libresoc.v:206422.3-206431.6" + wire width 4 $0\cur_idx15[3:0] + attribute \src "libresoc.v:206083.3-206092.6" + wire width 4 $0\cur_idx1[3:0] + attribute \src "libresoc.v:206103.3-206112.6" + wire width 4 $0\cur_idx2[3:0] + attribute \src "libresoc.v:206123.3-206132.6" + wire width 4 $0\cur_idx3[3:0] + attribute \src "libresoc.v:206152.3-206161.6" + wire width 4 $0\cur_idx4[3:0] + attribute \src "libresoc.v:206172.3-206181.6" + wire width 4 $0\cur_idx5[3:0] + attribute \src "libresoc.v:206192.3-206201.6" + wire width 4 $0\cur_idx6[3:0] + attribute \src "libresoc.v:206212.3-206221.6" + wire width 4 $0\cur_idx7[3:0] + attribute \src "libresoc.v:206232.3-206241.6" + wire width 4 $0\cur_idx8[3:0] + attribute \src "libresoc.v:206252.3-206261.6" + wire width 4 $0\cur_idx9[3:0] + attribute \src "libresoc.v:206053.3-206062.6" + wire width 8 $0\cur_pri0[7:0] + attribute \src "libresoc.v:206262.3-206271.6" + wire width 8 $0\cur_pri10[7:0] + attribute \src "libresoc.v:206282.3-206291.6" + wire width 8 $0\cur_pri11[7:0] + attribute \src "libresoc.v:206302.3-206311.6" + wire width 8 $0\cur_pri12[7:0] + attribute \src "libresoc.v:206322.3-206331.6" + wire width 8 $0\cur_pri13[7:0] + attribute \src "libresoc.v:206342.3-206351.6" + wire width 8 $0\cur_pri14[7:0] + attribute \src "libresoc.v:206412.3-206421.6" + wire width 8 $0\cur_pri15[7:0] + attribute \src "libresoc.v:206073.3-206082.6" + wire width 8 $0\cur_pri1[7:0] + attribute \src "libresoc.v:206093.3-206102.6" + wire width 8 $0\cur_pri2[7:0] + attribute \src "libresoc.v:206113.3-206122.6" + wire width 8 $0\cur_pri3[7:0] + attribute \src "libresoc.v:206133.3-206142.6" + wire width 8 $0\cur_pri4[7:0] + attribute \src "libresoc.v:206162.3-206171.6" + wire width 8 $0\cur_pri5[7:0] + attribute \src "libresoc.v:206182.3-206191.6" + wire width 8 $0\cur_pri6[7:0] + attribute \src "libresoc.v:206202.3-206211.6" + wire width 8 $0\cur_pri7[7:0] + attribute \src "libresoc.v:206222.3-206231.6" + wire width 8 $0\cur_pri8[7:0] + attribute \src "libresoc.v:206242.3-206251.6" + wire width 8 $0\cur_pri9[7:0] + attribute \src "libresoc.v:206432.3-206441.6" + wire $0\ibit[0:0] + attribute \src "libresoc.v:205927.3-205928.25" + wire width 8 $0\icp_o_pri[7:0] + attribute \src "libresoc.v:205925.3-205926.28" + wire width 4 $0\icp_o_src[3:0] + attribute \src "libresoc.v:206451.3-206459.6" + wire $0\ics_wb__ack$next[0:0]$15264 + attribute \src "libresoc.v:205961.3-205962.39" + wire $0\ics_wb__ack[0:0] + attribute \src "libresoc.v:206442.3-206450.6" + wire width 32 $0\ics_wb__dat_r$next[31:0]$15261 + attribute \src "libresoc.v:205963.3-205964.43" + wire width 32 $0\ics_wb__dat_r[31:0] + attribute \src "libresoc.v:205423.7-205423.20" + wire $0\initial[0:0] + attribute \src "libresoc.v:206143.3-206151.6" + wire width 16 $0\int_level_l$next[15:0]$15233 + attribute \src "libresoc.v:205965.3-205966.39" + wire width 16 $0\int_level_l[15:0] + attribute \src "libresoc.v:205967.3-206052.6" + wire width 8 $0\xive0_pri$next[7:0]$15143 + attribute \src "libresoc.v:205929.3-205930.35" + wire width 8 $0\xive0_pri[7:0] + attribute \src "libresoc.v:205967.3-206052.6" + wire width 8 $0\xive10_pri$next[7:0]$15144 + attribute \src "libresoc.v:205949.3-205950.37" + wire width 8 $0\xive10_pri[7:0] + attribute \src "libresoc.v:205967.3-206052.6" + wire width 8 $0\xive11_pri$next[7:0]$15145 + attribute \src "libresoc.v:205951.3-205952.37" + wire width 8 $0\xive11_pri[7:0] + attribute \src "libresoc.v:205967.3-206052.6" + wire width 8 $0\xive12_pri$next[7:0]$15146 + attribute \src "libresoc.v:205953.3-205954.37" + wire width 8 $0\xive12_pri[7:0] + attribute \src "libresoc.v:205967.3-206052.6" + wire width 8 $0\xive13_pri$next[7:0]$15147 + attribute \src "libresoc.v:205955.3-205956.37" + wire width 8 $0\xive13_pri[7:0] + attribute \src "libresoc.v:205967.3-206052.6" + wire width 8 $0\xive14_pri$next[7:0]$15148 + attribute \src "libresoc.v:205957.3-205958.37" + wire width 8 $0\xive14_pri[7:0] + attribute \src "libresoc.v:205967.3-206052.6" + wire width 8 $0\xive15_pri$next[7:0]$15149 + attribute \src "libresoc.v:205959.3-205960.37" + wire width 8 $0\xive15_pri[7:0] + attribute \src "libresoc.v:205967.3-206052.6" + wire width 8 $0\xive1_pri$next[7:0]$15150 + attribute \src "libresoc.v:205931.3-205932.35" + wire width 8 $0\xive1_pri[7:0] + attribute \src "libresoc.v:205967.3-206052.6" + wire width 8 $0\xive2_pri$next[7:0]$15151 + attribute \src "libresoc.v:205933.3-205934.35" + wire width 8 $0\xive2_pri[7:0] + attribute \src "libresoc.v:205967.3-206052.6" + wire width 8 $0\xive3_pri$next[7:0]$15152 + attribute \src "libresoc.v:205935.3-205936.35" + wire width 8 $0\xive3_pri[7:0] + attribute \src "libresoc.v:205967.3-206052.6" + wire width 8 $0\xive4_pri$next[7:0]$15153 + attribute \src "libresoc.v:205937.3-205938.35" + wire width 8 $0\xive4_pri[7:0] + attribute \src "libresoc.v:205967.3-206052.6" + wire width 8 $0\xive5_pri$next[7:0]$15154 + attribute \src "libresoc.v:205939.3-205940.35" + wire width 8 $0\xive5_pri[7:0] + attribute \src "libresoc.v:205967.3-206052.6" + wire width 8 $0\xive6_pri$next[7:0]$15155 + attribute \src "libresoc.v:205941.3-205942.35" + wire width 8 $0\xive6_pri[7:0] + attribute \src "libresoc.v:205967.3-206052.6" + wire width 8 $0\xive7_pri$next[7:0]$15156 + attribute \src "libresoc.v:205943.3-205944.35" + wire width 8 $0\xive7_pri[7:0] + attribute \src "libresoc.v:205967.3-206052.6" + wire width 8 $0\xive8_pri$next[7:0]$15157 + attribute \src "libresoc.v:205945.3-205946.35" + wire width 8 $0\xive8_pri[7:0] + attribute \src "libresoc.v:205967.3-206052.6" + wire width 8 $0\xive9_pri$next[7:0]$15158 + attribute \src "libresoc.v:205947.3-205948.35" + wire width 8 $0\xive9_pri[7:0] + attribute \src "libresoc.v:206352.3-206401.6" + wire width 32 $1\be_out[31:0] + attribute \src "libresoc.v:206063.3-206072.6" + wire width 4 $1\cur_idx0[3:0] + attribute \src "libresoc.v:206272.3-206281.6" + wire width 4 $1\cur_idx10[3:0] + attribute \src "libresoc.v:206292.3-206301.6" + wire width 4 $1\cur_idx11[3:0] + attribute \src "libresoc.v:206312.3-206321.6" + wire width 4 $1\cur_idx12[3:0] + attribute \src "libresoc.v:206332.3-206341.6" + wire width 4 $1\cur_idx13[3:0] + attribute \src "libresoc.v:206402.3-206411.6" + wire width 4 $1\cur_idx14[3:0] + attribute \src "libresoc.v:206422.3-206431.6" + wire width 4 $1\cur_idx15[3:0] + attribute \src "libresoc.v:206083.3-206092.6" + wire width 4 $1\cur_idx1[3:0] + attribute \src "libresoc.v:206103.3-206112.6" + wire width 4 $1\cur_idx2[3:0] + attribute \src "libresoc.v:206123.3-206132.6" + wire width 4 $1\cur_idx3[3:0] + attribute \src "libresoc.v:206152.3-206161.6" + wire width 4 $1\cur_idx4[3:0] + attribute \src "libresoc.v:206172.3-206181.6" + wire width 4 $1\cur_idx5[3:0] + attribute \src "libresoc.v:206192.3-206201.6" + wire width 4 $1\cur_idx6[3:0] + attribute \src "libresoc.v:206212.3-206221.6" + wire width 4 $1\cur_idx7[3:0] + attribute \src "libresoc.v:206232.3-206241.6" + wire width 4 $1\cur_idx8[3:0] + attribute \src "libresoc.v:206252.3-206261.6" + wire width 4 $1\cur_idx9[3:0] + attribute \src "libresoc.v:206053.3-206062.6" + wire width 8 $1\cur_pri0[7:0] + attribute \src "libresoc.v:206262.3-206271.6" + wire width 8 $1\cur_pri10[7:0] + attribute \src "libresoc.v:206282.3-206291.6" + wire width 8 $1\cur_pri11[7:0] + attribute \src "libresoc.v:206302.3-206311.6" + wire width 8 $1\cur_pri12[7:0] + attribute \src "libresoc.v:206322.3-206331.6" + wire width 8 $1\cur_pri13[7:0] + attribute \src "libresoc.v:206342.3-206351.6" + wire width 8 $1\cur_pri14[7:0] + attribute \src "libresoc.v:206412.3-206421.6" + wire width 8 $1\cur_pri15[7:0] + attribute \src "libresoc.v:206073.3-206082.6" + wire width 8 $1\cur_pri1[7:0] + attribute \src "libresoc.v:206093.3-206102.6" + wire width 8 $1\cur_pri2[7:0] + attribute \src "libresoc.v:206113.3-206122.6" + wire width 8 $1\cur_pri3[7:0] + attribute \src "libresoc.v:206133.3-206142.6" + wire width 8 $1\cur_pri4[7:0] + attribute \src "libresoc.v:206162.3-206171.6" + wire width 8 $1\cur_pri5[7:0] + attribute \src "libresoc.v:206182.3-206191.6" + wire width 8 $1\cur_pri6[7:0] + attribute \src "libresoc.v:206202.3-206211.6" + wire width 8 $1\cur_pri7[7:0] + attribute \src "libresoc.v:206222.3-206231.6" + wire width 8 $1\cur_pri8[7:0] + attribute \src "libresoc.v:206242.3-206251.6" + wire width 8 $1\cur_pri9[7:0] + attribute \src "libresoc.v:206432.3-206441.6" + wire $1\ibit[0:0] + attribute \src "libresoc.v:205704.13-205704.30" + wire width 8 $1\icp_o_pri[7:0] + attribute \src "libresoc.v:205709.13-205709.29" + wire width 4 $1\icp_o_src[3:0] + attribute \src "libresoc.v:206451.3-206459.6" + wire $1\ics_wb__ack$next[0:0]$15265 + attribute \src "libresoc.v:205718.7-205718.25" + wire $1\ics_wb__ack[0:0] + attribute \src "libresoc.v:206442.3-206450.6" + wire width 32 $1\ics_wb__dat_r$next[31:0]$15262 + attribute \src "libresoc.v:205727.14-205727.35" + wire width 32 $1\ics_wb__dat_r[31:0] + attribute \src "libresoc.v:206143.3-206151.6" + wire width 16 $1\int_level_l$next[15:0]$15234 + attribute \src "libresoc.v:205739.14-205739.36" + wire width 16 $1\int_level_l[15:0] + attribute \src "libresoc.v:205967.3-206052.6" + wire width 8 $1\xive0_pri$next[7:0]$15159 + attribute \src "libresoc.v:205759.13-205759.30" + wire width 8 $1\xive0_pri[7:0] + attribute \src "libresoc.v:205967.3-206052.6" + wire width 8 $1\xive10_pri$next[7:0]$15160 + attribute \src "libresoc.v:205763.13-205763.31" + wire width 8 $1\xive10_pri[7:0] + attribute \src "libresoc.v:205967.3-206052.6" + wire width 8 $1\xive11_pri$next[7:0]$15161 + attribute \src "libresoc.v:205767.13-205767.31" + wire width 8 $1\xive11_pri[7:0] + attribute \src "libresoc.v:205967.3-206052.6" + wire width 8 $1\xive12_pri$next[7:0]$15162 + attribute \src "libresoc.v:205771.13-205771.31" + wire width 8 $1\xive12_pri[7:0] + attribute \src "libresoc.v:205967.3-206052.6" + wire width 8 $1\xive13_pri$next[7:0]$15163 + attribute \src "libresoc.v:205775.13-205775.31" + wire width 8 $1\xive13_pri[7:0] + attribute \src "libresoc.v:205967.3-206052.6" + wire width 8 $1\xive14_pri$next[7:0]$15164 + attribute \src "libresoc.v:205779.13-205779.31" + wire width 8 $1\xive14_pri[7:0] + attribute \src "libresoc.v:205967.3-206052.6" + wire width 8 $1\xive15_pri$next[7:0]$15165 + attribute \src "libresoc.v:205783.13-205783.31" + wire width 8 $1\xive15_pri[7:0] + attribute \src "libresoc.v:205967.3-206052.6" + wire width 8 $1\xive1_pri$next[7:0]$15166 + attribute \src "libresoc.v:205787.13-205787.30" + wire width 8 $1\xive1_pri[7:0] + attribute \src "libresoc.v:205967.3-206052.6" + wire width 8 $1\xive2_pri$next[7:0]$15167 + attribute \src "libresoc.v:205791.13-205791.30" + wire width 8 $1\xive2_pri[7:0] + attribute \src "libresoc.v:205967.3-206052.6" + wire width 8 $1\xive3_pri$next[7:0]$15168 + attribute \src "libresoc.v:205795.13-205795.30" + wire width 8 $1\xive3_pri[7:0] + attribute \src "libresoc.v:205967.3-206052.6" + wire width 8 $1\xive4_pri$next[7:0]$15169 + attribute \src "libresoc.v:205799.13-205799.30" + wire width 8 $1\xive4_pri[7:0] + attribute \src "libresoc.v:205967.3-206052.6" + wire width 8 $1\xive5_pri$next[7:0]$15170 + attribute \src "libresoc.v:205803.13-205803.30" + wire width 8 $1\xive5_pri[7:0] + attribute \src "libresoc.v:205967.3-206052.6" + wire width 8 $1\xive6_pri$next[7:0]$15171 + attribute \src "libresoc.v:205807.13-205807.30" + wire width 8 $1\xive6_pri[7:0] + attribute \src "libresoc.v:205967.3-206052.6" + wire width 8 $1\xive7_pri$next[7:0]$15172 + attribute \src "libresoc.v:205811.13-205811.30" + wire width 8 $1\xive7_pri[7:0] + attribute \src "libresoc.v:205967.3-206052.6" + wire width 8 $1\xive8_pri$next[7:0]$15173 + attribute \src "libresoc.v:205815.13-205815.30" + wire width 8 $1\xive8_pri[7:0] + attribute \src "libresoc.v:205967.3-206052.6" + wire width 8 $1\xive9_pri$next[7:0]$15174 + attribute \src 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attribute \src "libresoc.v:205967.3-206052.6" + wire width 8 $3\xive13_pri$next[7:0]$15195 + attribute \src "libresoc.v:205967.3-206052.6" + wire width 8 $3\xive14_pri$next[7:0]$15196 + attribute \src "libresoc.v:205967.3-206052.6" + wire width 8 $3\xive15_pri$next[7:0]$15197 + attribute \src "libresoc.v:205967.3-206052.6" + wire width 8 $3\xive1_pri$next[7:0]$15198 + attribute \src "libresoc.v:205967.3-206052.6" + wire width 8 $3\xive2_pri$next[7:0]$15199 + attribute \src "libresoc.v:205967.3-206052.6" + wire width 8 $3\xive3_pri$next[7:0]$15200 + attribute \src "libresoc.v:205967.3-206052.6" + wire width 8 $3\xive4_pri$next[7:0]$15201 + attribute \src "libresoc.v:205967.3-206052.6" + wire width 8 $3\xive5_pri$next[7:0]$15202 + attribute \src "libresoc.v:205967.3-206052.6" + wire width 8 $3\xive6_pri$next[7:0]$15203 + attribute \src "libresoc.v:205967.3-206052.6" + wire width 8 $3\xive7_pri$next[7:0]$15204 + attribute \src "libresoc.v:205967.3-206052.6" + wire width 8 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"/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + cell $lt $lt$libresoc.v:205871$15067 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive14_pri + connect \B \cur_pri13 + connect \Y $lt$libresoc.v:205871$15067_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + cell $lt $lt$libresoc.v:205873$15069 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive14_pri + connect \B \cur_pri13 + connect \Y $lt$libresoc.v:205873$15069_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + cell $lt $lt$libresoc.v:205875$15071 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive15_pri + connect \B \cur_pri14 + connect \Y $lt$libresoc.v:205875$15071_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + cell $lt $lt$libresoc.v:205878$15074 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive15_pri + connect \B \cur_pri14 + connect \Y $lt$libresoc.v:205878$15074_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + cell $lt $lt$libresoc.v:205912$15108 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive0_pri + connect \B \max_pri + connect \Y $lt$libresoc.v:205912$15108_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + cell $lt $lt$libresoc.v:205914$15110 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive0_pri + connect \B \max_pri + connect \Y $lt$libresoc.v:205914$15110_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + cell $lt $lt$libresoc.v:205916$15112 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive1_pri + connect \B \cur_pri0 + connect \Y $lt$libresoc.v:205916$15112_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + cell $lt $lt$libresoc.v:205918$15114 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive1_pri + connect \B \cur_pri0 + connect \Y $lt$libresoc.v:205918$15114_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + cell $lt $lt$libresoc.v:205921$15117 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive2_pri + connect \B \cur_pri1 + connect \Y $lt$libresoc.v:205921$15117_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + cell $lt $lt$libresoc.v:205923$15119 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive2_pri + connect \B \cur_pri1 + connect \Y $lt$libresoc.v:205923$15119_Y + end + attribute \src "libresoc.v:205910.18-205910.40" + cell $shr $shr$libresoc.v:205910$15106 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 16 + connect \A \int_level_l + connect \B \reg_idx + connect \Y $shr$libresoc.v:205910$15106_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + cell $mux $ternary$libresoc.v:205822$15018 + parameter \WIDTH 8 + connect \A \xive0_pri + connect \B 8'11111111 + connect \S \$8 + connect \Y $ternary$libresoc.v:205822$15018_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + cell $mux $ternary$libresoc.v:205844$15040 + parameter \WIDTH 8 + connect \A \xive1_pri + connect \B 8'11111111 + connect \S \$12 + connect \Y $ternary$libresoc.v:205844$15040_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + cell $mux $ternary$libresoc.v:205866$15062 + parameter \WIDTH 8 + connect \A \xive2_pri + connect \B 8'11111111 + connect \S \$16 + connect \Y $ternary$libresoc.v:205866$15062_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + cell $mux $ternary$libresoc.v:205881$15077 + parameter \WIDTH 8 + connect \A \cur_pri15 + connect \B 8'11111111 + connect \S \$204 + connect \Y $ternary$libresoc.v:205881$15077_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + cell $mux $ternary$libresoc.v:205883$15079 + parameter \WIDTH 8 + connect \A \xive3_pri + connect \B 8'11111111 + connect \S \$20 + connect \Y $ternary$libresoc.v:205883$15079_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + cell $mux $ternary$libresoc.v:205885$15081 + parameter \WIDTH 8 + connect \A \xive4_pri + connect \B 8'11111111 + connect \S \$24 + connect \Y $ternary$libresoc.v:205885$15081_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + cell $mux $ternary$libresoc.v:205887$15083 + parameter \WIDTH 8 + connect \A \xive5_pri + connect \B 8'11111111 + connect \S \$28 + connect \Y $ternary$libresoc.v:205887$15083_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + cell $mux $ternary$libresoc.v:205889$15085 + parameter \WIDTH 8 + connect \A \xive6_pri + connect \B 8'11111111 + connect \S \$32 + connect \Y $ternary$libresoc.v:205889$15085_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + cell $mux $ternary$libresoc.v:205891$15087 + parameter \WIDTH 8 + connect \A \xive7_pri + connect \B 8'11111111 + connect \S \$36 + connect \Y $ternary$libresoc.v:205891$15087_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + cell $mux $ternary$libresoc.v:205894$15090 + parameter \WIDTH 8 + connect \A \xive8_pri + connect \B 8'11111111 + connect \S \$40 + connect \Y $ternary$libresoc.v:205894$15090_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + cell $mux $ternary$libresoc.v:205896$15092 + parameter \WIDTH 8 + connect \A \xive9_pri + connect \B 8'11111111 + connect \S \$44 + connect \Y $ternary$libresoc.v:205896$15092_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + cell $mux $ternary$libresoc.v:205898$15094 + parameter \WIDTH 8 + connect \A \xive10_pri + connect \B 8'11111111 + connect \S \$48 + connect \Y $ternary$libresoc.v:205898$15094_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + cell $mux $ternary$libresoc.v:205900$15096 + parameter \WIDTH 8 + connect \A \xive11_pri + connect \B 8'11111111 + connect \S \$52 + connect \Y $ternary$libresoc.v:205900$15096_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + cell $mux $ternary$libresoc.v:205902$15098 + parameter \WIDTH 8 + connect \A \xive12_pri + connect \B 8'11111111 + connect \S \$56 + connect \Y $ternary$libresoc.v:205902$15098_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + cell $mux $ternary$libresoc.v:205905$15101 + parameter \WIDTH 8 + connect \A \xive13_pri + connect \B 8'11111111 + connect \S \$60 + connect \Y $ternary$libresoc.v:205905$15101_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + cell $mux $ternary$libresoc.v:205907$15103 + parameter \WIDTH 8 + connect \A \xive14_pri + connect \B 8'11111111 + connect \S \$64 + connect \Y $ternary$libresoc.v:205907$15103_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + cell $mux $ternary$libresoc.v:205909$15105 + parameter \WIDTH 8 + connect \A \xive15_pri + connect \B 8'11111111 + connect \S \$68 + connect \Y $ternary$libresoc.v:205909$15105_Y + end + attribute \src "libresoc.v:205423.7-205423.20" + process $proc$libresoc.v:205423$15266 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "libresoc.v:205704.13-205704.30" + process $proc$libresoc.v:205704$15267 + assign { } { } + assign $1\icp_o_pri[7:0] 8'00000000 + sync always + sync init + update \icp_o_pri $1\icp_o_pri[7:0] + end + attribute \src "libresoc.v:205709.13-205709.29" + process $proc$libresoc.v:205709$15268 + assign { } { } + assign $1\icp_o_src[3:0] 4'0000 + sync always + sync init + update \icp_o_src $1\icp_o_src[3:0] + end + attribute \src "libresoc.v:205718.7-205718.25" + process $proc$libresoc.v:205718$15269 + assign { } { } + assign $1\ics_wb__ack[0:0] 1'0 + sync always + sync init + update \ics_wb__ack $1\ics_wb__ack[0:0] + end + attribute \src "libresoc.v:205727.14-205727.35" + process $proc$libresoc.v:205727$15270 + assign { } { } + assign $1\ics_wb__dat_r[31:0] 0 + sync always + sync init + update \ics_wb__dat_r $1\ics_wb__dat_r[31:0] + end + attribute \src "libresoc.v:205739.14-205739.36" + process $proc$libresoc.v:205739$15271 + assign { } { } + assign $1\int_level_l[15:0] 16'0000000000000000 + sync always + sync init + update \int_level_l $1\int_level_l[15:0] + end + attribute \src "libresoc.v:205759.13-205759.30" + process $proc$libresoc.v:205759$15272 + assign { } { } + assign $1\xive0_pri[7:0] 8'11111111 + sync always + sync init + update \xive0_pri $1\xive0_pri[7:0] + end + attribute \src "libresoc.v:205763.13-205763.31" + process $proc$libresoc.v:205763$15273 + assign { } { } + assign $1\xive10_pri[7:0] 8'11111111 + sync always + sync init + update \xive10_pri $1\xive10_pri[7:0] + end + attribute \src "libresoc.v:205767.13-205767.31" + process $proc$libresoc.v:205767$15274 + assign { } { } + assign $1\xive11_pri[7:0] 8'11111111 + sync always + sync init + update \xive11_pri $1\xive11_pri[7:0] + end + attribute \src "libresoc.v:205771.13-205771.31" + process $proc$libresoc.v:205771$15275 + assign { } { } + assign $1\xive12_pri[7:0] 8'11111111 + sync always + sync init + update \xive12_pri $1\xive12_pri[7:0] + end + attribute \src "libresoc.v:205775.13-205775.31" + process $proc$libresoc.v:205775$15276 + assign { } { } + assign $1\xive13_pri[7:0] 8'11111111 + sync always + sync init + update \xive13_pri $1\xive13_pri[7:0] + end + attribute \src "libresoc.v:205779.13-205779.31" + process $proc$libresoc.v:205779$15277 + assign { } { } + assign $1\xive14_pri[7:0] 8'11111111 + sync always + sync init + update \xive14_pri $1\xive14_pri[7:0] + end + attribute \src "libresoc.v:205783.13-205783.31" + process $proc$libresoc.v:205783$15278 + assign { } { } + assign $1\xive15_pri[7:0] 8'11111111 + sync always + sync init + update \xive15_pri $1\xive15_pri[7:0] + end + attribute \src "libresoc.v:205787.13-205787.30" + process $proc$libresoc.v:205787$15279 + assign { } { } + assign $1\xive1_pri[7:0] 8'11111111 + sync always + sync init + update \xive1_pri $1\xive1_pri[7:0] + end + attribute \src "libresoc.v:205791.13-205791.30" + process $proc$libresoc.v:205791$15280 + assign { } { } + assign $1\xive2_pri[7:0] 8'11111111 + sync always + sync init + update \xive2_pri $1\xive2_pri[7:0] + end + attribute \src "libresoc.v:205795.13-205795.30" + process $proc$libresoc.v:205795$15281 + assign { } { } + assign $1\xive3_pri[7:0] 8'11111111 + sync always + sync init + update \xive3_pri $1\xive3_pri[7:0] + end + attribute \src "libresoc.v:205799.13-205799.30" + process $proc$libresoc.v:205799$15282 + assign { } { } + assign $1\xive4_pri[7:0] 8'11111111 + sync always + sync init + update \xive4_pri $1\xive4_pri[7:0] + end + attribute \src "libresoc.v:205803.13-205803.30" + process $proc$libresoc.v:205803$15283 + assign { } { } + assign $1\xive5_pri[7:0] 8'11111111 + sync always + sync init + update \xive5_pri $1\xive5_pri[7:0] + end + attribute \src "libresoc.v:205807.13-205807.30" + process $proc$libresoc.v:205807$15284 + assign { } { } + assign $1\xive6_pri[7:0] 8'11111111 + sync always + sync init + update \xive6_pri $1\xive6_pri[7:0] + end + attribute \src "libresoc.v:205811.13-205811.30" + process $proc$libresoc.v:205811$15285 + assign { } { } + assign $1\xive7_pri[7:0] 8'11111111 + sync always + sync init + update \xive7_pri $1\xive7_pri[7:0] + end + attribute \src "libresoc.v:205815.13-205815.30" + process $proc$libresoc.v:205815$15286 + assign { } { } + assign $1\xive8_pri[7:0] 8'11111111 + sync always + sync init + update \xive8_pri $1\xive8_pri[7:0] + end + attribute \src "libresoc.v:205819.13-205819.30" + process $proc$libresoc.v:205819$15287 + assign { } { } + assign $1\xive9_pri[7:0] 8'11111111 + sync always + sync init + update \xive9_pri $1\xive9_pri[7:0] + end + attribute \src "libresoc.v:205925.3-205926.28" + process $proc$libresoc.v:205925$15121 + assign { } { } + assign $0\icp_o_src[3:0] \cur_idx15 + sync posedge \clk + update \icp_o_src $0\icp_o_src[3:0] + end + attribute \src "libresoc.v:205927.3-205928.25" + process $proc$libresoc.v:205927$15122 + assign { } { } + assign $0\icp_o_pri[7:0] \$203 + sync posedge \clk + update \icp_o_pri $0\icp_o_pri[7:0] + end + attribute \src "libresoc.v:205929.3-205930.35" + process $proc$libresoc.v:205929$15123 + assign { } { } + assign $0\xive0_pri[7:0] \xive0_pri$next + sync posedge \clk + update \xive0_pri $0\xive0_pri[7:0] + end + attribute \src "libresoc.v:205931.3-205932.35" + process $proc$libresoc.v:205931$15124 + assign { } { } + assign $0\xive1_pri[7:0] \xive1_pri$next + sync posedge \clk + update \xive1_pri $0\xive1_pri[7:0] + end + attribute \src "libresoc.v:205933.3-205934.35" + process $proc$libresoc.v:205933$15125 + assign { } { } + assign $0\xive2_pri[7:0] \xive2_pri$next + sync posedge \clk + update \xive2_pri $0\xive2_pri[7:0] + end + attribute \src "libresoc.v:205935.3-205936.35" + process $proc$libresoc.v:205935$15126 + assign { } { } + assign $0\xive3_pri[7:0] \xive3_pri$next + sync posedge \clk + update \xive3_pri $0\xive3_pri[7:0] + end + attribute \src "libresoc.v:205937.3-205938.35" + process $proc$libresoc.v:205937$15127 + assign { } { } + assign $0\xive4_pri[7:0] \xive4_pri$next + sync posedge \clk + update \xive4_pri $0\xive4_pri[7:0] + end + attribute \src "libresoc.v:205939.3-205940.35" + process $proc$libresoc.v:205939$15128 + assign { } { } + assign $0\xive5_pri[7:0] \xive5_pri$next + sync posedge \clk + update \xive5_pri $0\xive5_pri[7:0] + end + attribute \src "libresoc.v:205941.3-205942.35" + process $proc$libresoc.v:205941$15129 + assign { } { } + assign $0\xive6_pri[7:0] \xive6_pri$next + sync posedge \clk + update \xive6_pri $0\xive6_pri[7:0] + end + attribute \src "libresoc.v:205943.3-205944.35" + process $proc$libresoc.v:205943$15130 + assign { } { } + assign $0\xive7_pri[7:0] \xive7_pri$next + sync posedge \clk + update \xive7_pri $0\xive7_pri[7:0] + end + attribute \src "libresoc.v:205945.3-205946.35" + process $proc$libresoc.v:205945$15131 + assign { } { } + assign $0\xive8_pri[7:0] \xive8_pri$next + sync posedge \clk + update \xive8_pri $0\xive8_pri[7:0] + end + attribute \src "libresoc.v:205947.3-205948.35" + process $proc$libresoc.v:205947$15132 + assign { } { } + assign $0\xive9_pri[7:0] \xive9_pri$next + sync posedge \clk + update \xive9_pri $0\xive9_pri[7:0] + end + attribute \src "libresoc.v:205949.3-205950.37" + process $proc$libresoc.v:205949$15133 + assign { } { } + assign $0\xive10_pri[7:0] \xive10_pri$next + sync posedge \clk + update \xive10_pri $0\xive10_pri[7:0] + end + attribute \src "libresoc.v:205951.3-205952.37" + process $proc$libresoc.v:205951$15134 + assign { } { } + assign $0\xive11_pri[7:0] \xive11_pri$next + sync posedge \clk + update \xive11_pri $0\xive11_pri[7:0] + end + attribute \src "libresoc.v:205953.3-205954.37" + process $proc$libresoc.v:205953$15135 + assign { } { } + assign $0\xive12_pri[7:0] \xive12_pri$next + sync posedge \clk + update \xive12_pri $0\xive12_pri[7:0] + end + attribute \src "libresoc.v:205955.3-205956.37" + process $proc$libresoc.v:205955$15136 + assign { } { } + assign $0\xive13_pri[7:0] \xive13_pri$next + sync posedge \clk + update \xive13_pri $0\xive13_pri[7:0] + end + attribute \src "libresoc.v:205957.3-205958.37" + process $proc$libresoc.v:205957$15137 + assign { } { } + assign $0\xive14_pri[7:0] \xive14_pri$next + sync posedge \clk + update \xive14_pri $0\xive14_pri[7:0] + end + attribute \src "libresoc.v:205959.3-205960.37" + process $proc$libresoc.v:205959$15138 + assign { } { } + assign $0\xive15_pri[7:0] \xive15_pri$next + sync posedge \clk + update \xive15_pri $0\xive15_pri[7:0] + end + attribute \src "libresoc.v:205961.3-205962.39" + process $proc$libresoc.v:205961$15139 + assign { } { } + assign $0\ics_wb__ack[0:0] \ics_wb__ack$next + sync posedge \clk + update \ics_wb__ack $0\ics_wb__ack[0:0] + end + attribute \src "libresoc.v:205963.3-205964.43" + process $proc$libresoc.v:205963$15140 + assign { } { } + assign $0\ics_wb__dat_r[31:0] \ics_wb__dat_r$next + sync posedge \clk + update \ics_wb__dat_r $0\ics_wb__dat_r[31:0] + end + attribute \src "libresoc.v:205965.3-205966.39" + process $proc$libresoc.v:205965$15141 + assign { } { } + assign $0\int_level_l[15:0] \int_level_l$next + sync posedge \clk + update \int_level_l $0\int_level_l[15:0] + end + attribute \src "libresoc.v:205967.3-206052.6" + process $proc$libresoc.v:205967$15142 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\xive0_pri$next[7:0]$15143 $4\xive0_pri$next[7:0]$15207 + assign $0\xive10_pri$next[7:0]$15144 $4\xive10_pri$next[7:0]$15208 + assign $0\xive11_pri$next[7:0]$15145 $4\xive11_pri$next[7:0]$15209 + assign $0\xive12_pri$next[7:0]$15146 $4\xive12_pri$next[7:0]$15210 + assign $0\xive13_pri$next[7:0]$15147 $4\xive13_pri$next[7:0]$15211 + assign $0\xive14_pri$next[7:0]$15148 $4\xive14_pri$next[7:0]$15212 + assign $0\xive15_pri$next[7:0]$15149 $4\xive15_pri$next[7:0]$15213 + assign $0\xive1_pri$next[7:0]$15150 $4\xive1_pri$next[7:0]$15214 + assign $0\xive2_pri$next[7:0]$15151 $4\xive2_pri$next[7:0]$15215 + assign $0\xive3_pri$next[7:0]$15152 $4\xive3_pri$next[7:0]$15216 + assign $0\xive4_pri$next[7:0]$15153 $4\xive4_pri$next[7:0]$15217 + assign $0\xive5_pri$next[7:0]$15154 $4\xive5_pri$next[7:0]$15218 + assign $0\xive6_pri$next[7:0]$15155 $4\xive6_pri$next[7:0]$15219 + assign $0\xive7_pri$next[7:0]$15156 $4\xive7_pri$next[7:0]$15220 + assign $0\xive8_pri$next[7:0]$15157 $4\xive8_pri$next[7:0]$15221 + assign $0\xive9_pri$next[7:0]$15158 $4\xive9_pri$next[7:0]$15222 + attribute \src "libresoc.v:205968.5-205968.29" + switch \initial + attribute \src "libresoc.v:205968.9-205968.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:341" + switch \$73 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\xive0_pri$next[7:0]$15159 $2\xive0_pri$next[7:0]$15175 + assign $1\xive10_pri$next[7:0]$15160 $2\xive10_pri$next[7:0]$15176 + assign $1\xive11_pri$next[7:0]$15161 $2\xive11_pri$next[7:0]$15177 + assign $1\xive12_pri$next[7:0]$15162 $2\xive12_pri$next[7:0]$15178 + assign $1\xive13_pri$next[7:0]$15163 $2\xive13_pri$next[7:0]$15179 + assign $1\xive14_pri$next[7:0]$15164 $2\xive14_pri$next[7:0]$15180 + assign $1\xive15_pri$next[7:0]$15165 $2\xive15_pri$next[7:0]$15181 + assign $1\xive1_pri$next[7:0]$15166 $2\xive1_pri$next[7:0]$15182 + assign $1\xive2_pri$next[7:0]$15167 $2\xive2_pri$next[7:0]$15183 + assign $1\xive3_pri$next[7:0]$15168 $2\xive3_pri$next[7:0]$15184 + assign $1\xive4_pri$next[7:0]$15169 $2\xive4_pri$next[7:0]$15185 + assign $1\xive5_pri$next[7:0]$15170 $2\xive5_pri$next[7:0]$15186 + assign $1\xive6_pri$next[7:0]$15171 $2\xive6_pri$next[7:0]$15187 + assign $1\xive7_pri$next[7:0]$15172 $2\xive7_pri$next[7:0]$15188 + assign $1\xive8_pri$next[7:0]$15173 $2\xive8_pri$next[7:0]$15189 + assign $1\xive9_pri$next[7:0]$15174 $2\xive9_pri$next[7:0]$15190 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:342" + switch \reg_is_xive + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $2\xive0_pri$next[7:0]$15175 $3\xive0_pri$next[7:0]$15191 + assign $2\xive10_pri$next[7:0]$15176 $3\xive10_pri$next[7:0]$15192 + assign $2\xive11_pri$next[7:0]$15177 $3\xive11_pri$next[7:0]$15193 + assign $2\xive12_pri$next[7:0]$15178 $3\xive12_pri$next[7:0]$15194 + assign $2\xive13_pri$next[7:0]$15179 $3\xive13_pri$next[7:0]$15195 + assign $2\xive14_pri$next[7:0]$15180 $3\xive14_pri$next[7:0]$15196 + assign $2\xive15_pri$next[7:0]$15181 $3\xive15_pri$next[7:0]$15197 + assign $2\xive1_pri$next[7:0]$15182 $3\xive1_pri$next[7:0]$15198 + assign $2\xive2_pri$next[7:0]$15183 $3\xive2_pri$next[7:0]$15199 + assign $2\xive3_pri$next[7:0]$15184 $3\xive3_pri$next[7:0]$15200 + assign $2\xive4_pri$next[7:0]$15185 $3\xive4_pri$next[7:0]$15201 + assign $2\xive5_pri$next[7:0]$15186 $3\xive5_pri$next[7:0]$15202 + assign $2\xive6_pri$next[7:0]$15187 $3\xive6_pri$next[7:0]$15203 + assign $2\xive7_pri$next[7:0]$15188 $3\xive7_pri$next[7:0]$15204 + assign $2\xive8_pri$next[7:0]$15189 $3\xive8_pri$next[7:0]$15205 + assign $2\xive9_pri$next[7:0]$15190 $3\xive9_pri$next[7:0]$15206 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:345" + switch \reg_idx + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $3\xive10_pri$next[7:0]$15192 \xive10_pri + assign $3\xive11_pri$next[7:0]$15193 \xive11_pri + assign $3\xive12_pri$next[7:0]$15194 \xive12_pri + assign $3\xive13_pri$next[7:0]$15195 \xive13_pri + assign $3\xive14_pri$next[7:0]$15196 \xive14_pri + assign $3\xive15_pri$next[7:0]$15197 \xive15_pri + assign $3\xive1_pri$next[7:0]$15198 \xive1_pri + assign $3\xive2_pri$next[7:0]$15199 \xive2_pri + assign $3\xive3_pri$next[7:0]$15200 \xive3_pri + assign $3\xive4_pri$next[7:0]$15201 \xive4_pri + assign $3\xive5_pri$next[7:0]$15202 \xive5_pri + assign $3\xive6_pri$next[7:0]$15203 \xive6_pri + assign $3\xive7_pri$next[7:0]$15204 \xive7_pri + assign $3\xive8_pri$next[7:0]$15205 \xive8_pri + assign $3\xive9_pri$next[7:0]$15206 \xive9_pri + assign $3\xive0_pri$next[7:0]$15191 \be_in [7:0] + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign $3\xive0_pri$next[7:0]$15191 \xive0_pri + assign $3\xive10_pri$next[7:0]$15192 \xive10_pri + assign $3\xive11_pri$next[7:0]$15193 \xive11_pri + assign $3\xive12_pri$next[7:0]$15194 \xive12_pri + assign $3\xive13_pri$next[7:0]$15195 \xive13_pri + assign $3\xive14_pri$next[7:0]$15196 \xive14_pri + assign $3\xive15_pri$next[7:0]$15197 \xive15_pri + assign { } { } + assign $3\xive2_pri$next[7:0]$15199 \xive2_pri + assign $3\xive3_pri$next[7:0]$15200 \xive3_pri + assign $3\xive4_pri$next[7:0]$15201 \xive4_pri + assign $3\xive5_pri$next[7:0]$15202 \xive5_pri + assign $3\xive6_pri$next[7:0]$15203 \xive6_pri + assign $3\xive7_pri$next[7:0]$15204 \xive7_pri + assign $3\xive8_pri$next[7:0]$15205 \xive8_pri + assign $3\xive9_pri$next[7:0]$15206 \xive9_pri + assign $3\xive1_pri$next[7:0]$15198 \be_in [7:0] + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign $3\xive0_pri$next[7:0]$15191 \xive0_pri + assign $3\xive10_pri$next[7:0]$15192 \xive10_pri + assign $3\xive11_pri$next[7:0]$15193 \xive11_pri + assign $3\xive12_pri$next[7:0]$15194 \xive12_pri + assign $3\xive13_pri$next[7:0]$15195 \xive13_pri + assign $3\xive14_pri$next[7:0]$15196 \xive14_pri + assign $3\xive15_pri$next[7:0]$15197 \xive15_pri + assign $3\xive1_pri$next[7:0]$15198 \xive1_pri + assign { } { } + assign $3\xive3_pri$next[7:0]$15200 \xive3_pri + assign $3\xive4_pri$next[7:0]$15201 \xive4_pri + assign $3\xive5_pri$next[7:0]$15202 \xive5_pri + assign $3\xive6_pri$next[7:0]$15203 \xive6_pri + assign $3\xive7_pri$next[7:0]$15204 \xive7_pri + assign $3\xive8_pri$next[7:0]$15205 \xive8_pri + assign $3\xive9_pri$next[7:0]$15206 \xive9_pri + assign $3\xive2_pri$next[7:0]$15199 \be_in [7:0] + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign $3\xive0_pri$next[7:0]$15191 \xive0_pri + assign $3\xive10_pri$next[7:0]$15192 \xive10_pri + assign $3\xive11_pri$next[7:0]$15193 \xive11_pri + assign $3\xive12_pri$next[7:0]$15194 \xive12_pri + assign $3\xive13_pri$next[7:0]$15195 \xive13_pri + assign $3\xive14_pri$next[7:0]$15196 \xive14_pri + assign $3\xive15_pri$next[7:0]$15197 \xive15_pri + assign $3\xive1_pri$next[7:0]$15198 \xive1_pri + assign $3\xive2_pri$next[7:0]$15199 \xive2_pri + assign { } { } + assign $3\xive4_pri$next[7:0]$15201 \xive4_pri + assign $3\xive5_pri$next[7:0]$15202 \xive5_pri + assign $3\xive6_pri$next[7:0]$15203 \xive6_pri + assign $3\xive7_pri$next[7:0]$15204 \xive7_pri + assign $3\xive8_pri$next[7:0]$15205 \xive8_pri + assign $3\xive9_pri$next[7:0]$15206 \xive9_pri + assign $3\xive3_pri$next[7:0]$15200 \be_in [7:0] + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign $3\xive0_pri$next[7:0]$15191 \xive0_pri + assign $3\xive10_pri$next[7:0]$15192 \xive10_pri + assign $3\xive11_pri$next[7:0]$15193 \xive11_pri + assign $3\xive12_pri$next[7:0]$15194 \xive12_pri + assign $3\xive13_pri$next[7:0]$15195 \xive13_pri + assign $3\xive14_pri$next[7:0]$15196 \xive14_pri + assign $3\xive15_pri$next[7:0]$15197 \xive15_pri + assign $3\xive1_pri$next[7:0]$15198 \xive1_pri + assign $3\xive2_pri$next[7:0]$15199 \xive2_pri + assign $3\xive3_pri$next[7:0]$15200 \xive3_pri + assign { } { } + assign $3\xive5_pri$next[7:0]$15202 \xive5_pri + assign $3\xive6_pri$next[7:0]$15203 \xive6_pri + assign $3\xive7_pri$next[7:0]$15204 \xive7_pri + assign $3\xive8_pri$next[7:0]$15205 \xive8_pri + assign $3\xive9_pri$next[7:0]$15206 \xive9_pri + assign $3\xive4_pri$next[7:0]$15201 \be_in [7:0] + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign $3\xive0_pri$next[7:0]$15191 \xive0_pri + assign $3\xive10_pri$next[7:0]$15192 \xive10_pri + assign $3\xive11_pri$next[7:0]$15193 \xive11_pri + assign $3\xive12_pri$next[7:0]$15194 \xive12_pri + assign $3\xive13_pri$next[7:0]$15195 \xive13_pri + assign $3\xive14_pri$next[7:0]$15196 \xive14_pri + assign $3\xive15_pri$next[7:0]$15197 \xive15_pri + assign $3\xive1_pri$next[7:0]$15198 \xive1_pri + assign $3\xive2_pri$next[7:0]$15199 \xive2_pri + assign $3\xive3_pri$next[7:0]$15200 \xive3_pri + assign $3\xive4_pri$next[7:0]$15201 \xive4_pri + assign { } { } + assign $3\xive6_pri$next[7:0]$15203 \xive6_pri + assign $3\xive7_pri$next[7:0]$15204 \xive7_pri + assign $3\xive8_pri$next[7:0]$15205 \xive8_pri + assign $3\xive9_pri$next[7:0]$15206 \xive9_pri + assign $3\xive5_pri$next[7:0]$15202 \be_in [7:0] + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign $3\xive0_pri$next[7:0]$15191 \xive0_pri + assign $3\xive10_pri$next[7:0]$15192 \xive10_pri + assign $3\xive11_pri$next[7:0]$15193 \xive11_pri + assign $3\xive12_pri$next[7:0]$15194 \xive12_pri + assign $3\xive13_pri$next[7:0]$15195 \xive13_pri + assign $3\xive14_pri$next[7:0]$15196 \xive14_pri + assign $3\xive15_pri$next[7:0]$15197 \xive15_pri + assign $3\xive1_pri$next[7:0]$15198 \xive1_pri + assign $3\xive2_pri$next[7:0]$15199 \xive2_pri + assign $3\xive3_pri$next[7:0]$15200 \xive3_pri + assign $3\xive4_pri$next[7:0]$15201 \xive4_pri + assign $3\xive5_pri$next[7:0]$15202 \xive5_pri + assign { } { } + assign $3\xive7_pri$next[7:0]$15204 \xive7_pri + assign $3\xive8_pri$next[7:0]$15205 \xive8_pri + assign $3\xive9_pri$next[7:0]$15206 \xive9_pri + assign $3\xive6_pri$next[7:0]$15203 \be_in [7:0] + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign $3\xive0_pri$next[7:0]$15191 \xive0_pri + assign $3\xive10_pri$next[7:0]$15192 \xive10_pri + assign $3\xive11_pri$next[7:0]$15193 \xive11_pri + assign $3\xive12_pri$next[7:0]$15194 \xive12_pri + assign $3\xive13_pri$next[7:0]$15195 \xive13_pri + assign $3\xive14_pri$next[7:0]$15196 \xive14_pri + assign $3\xive15_pri$next[7:0]$15197 \xive15_pri + assign $3\xive1_pri$next[7:0]$15198 \xive1_pri + assign $3\xive2_pri$next[7:0]$15199 \xive2_pri + assign $3\xive3_pri$next[7:0]$15200 \xive3_pri + assign $3\xive4_pri$next[7:0]$15201 \xive4_pri + assign $3\xive5_pri$next[7:0]$15202 \xive5_pri + assign $3\xive6_pri$next[7:0]$15203 \xive6_pri + assign { } { } + assign $3\xive8_pri$next[7:0]$15205 \xive8_pri + assign $3\xive9_pri$next[7:0]$15206 \xive9_pri + assign $3\xive7_pri$next[7:0]$15204 \be_in [7:0] + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign $3\xive0_pri$next[7:0]$15191 \xive0_pri + assign $3\xive10_pri$next[7:0]$15192 \xive10_pri + assign $3\xive11_pri$next[7:0]$15193 \xive11_pri + assign $3\xive12_pri$next[7:0]$15194 \xive12_pri + assign $3\xive13_pri$next[7:0]$15195 \xive13_pri + assign $3\xive14_pri$next[7:0]$15196 \xive14_pri + assign $3\xive15_pri$next[7:0]$15197 \xive15_pri + assign $3\xive1_pri$next[7:0]$15198 \xive1_pri + assign $3\xive2_pri$next[7:0]$15199 \xive2_pri + assign $3\xive3_pri$next[7:0]$15200 \xive3_pri + assign $3\xive4_pri$next[7:0]$15201 \xive4_pri + assign $3\xive5_pri$next[7:0]$15202 \xive5_pri + assign $3\xive6_pri$next[7:0]$15203 \xive6_pri + assign $3\xive7_pri$next[7:0]$15204 \xive7_pri + assign { } { } + assign $3\xive9_pri$next[7:0]$15206 \xive9_pri + assign $3\xive8_pri$next[7:0]$15205 \be_in [7:0] + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign $3\xive0_pri$next[7:0]$15191 \xive0_pri + assign $3\xive10_pri$next[7:0]$15192 \xive10_pri + assign $3\xive11_pri$next[7:0]$15193 \xive11_pri + assign $3\xive12_pri$next[7:0]$15194 \xive12_pri + assign $3\xive13_pri$next[7:0]$15195 \xive13_pri + assign $3\xive14_pri$next[7:0]$15196 \xive14_pri + assign $3\xive15_pri$next[7:0]$15197 \xive15_pri + assign $3\xive1_pri$next[7:0]$15198 \xive1_pri + assign $3\xive2_pri$next[7:0]$15199 \xive2_pri + assign $3\xive3_pri$next[7:0]$15200 \xive3_pri + assign $3\xive4_pri$next[7:0]$15201 \xive4_pri + assign $3\xive5_pri$next[7:0]$15202 \xive5_pri + assign $3\xive6_pri$next[7:0]$15203 \xive6_pri + assign $3\xive7_pri$next[7:0]$15204 \xive7_pri + assign $3\xive8_pri$next[7:0]$15205 \xive8_pri + assign { } { } + assign $3\xive9_pri$next[7:0]$15206 \be_in [7:0] + attribute \src "libresoc.v:0.0-0.0" + case 4'1010 + assign $3\xive0_pri$next[7:0]$15191 \xive0_pri + assign { } { } + assign $3\xive11_pri$next[7:0]$15193 \xive11_pri + assign $3\xive12_pri$next[7:0]$15194 \xive12_pri + assign $3\xive13_pri$next[7:0]$15195 \xive13_pri + assign $3\xive14_pri$next[7:0]$15196 \xive14_pri + assign $3\xive15_pri$next[7:0]$15197 \xive15_pri + assign $3\xive1_pri$next[7:0]$15198 \xive1_pri + assign $3\xive2_pri$next[7:0]$15199 \xive2_pri + assign $3\xive3_pri$next[7:0]$15200 \xive3_pri + assign $3\xive4_pri$next[7:0]$15201 \xive4_pri + assign $3\xive5_pri$next[7:0]$15202 \xive5_pri + assign $3\xive6_pri$next[7:0]$15203 \xive6_pri + assign $3\xive7_pri$next[7:0]$15204 \xive7_pri + assign $3\xive8_pri$next[7:0]$15205 \xive8_pri + assign $3\xive9_pri$next[7:0]$15206 \xive9_pri + assign $3\xive10_pri$next[7:0]$15192 \be_in [7:0] + attribute \src "libresoc.v:0.0-0.0" + case 4'1011 + assign $3\xive0_pri$next[7:0]$15191 \xive0_pri + assign $3\xive10_pri$next[7:0]$15192 \xive10_pri + assign { } { } + assign $3\xive12_pri$next[7:0]$15194 \xive12_pri + assign $3\xive13_pri$next[7:0]$15195 \xive13_pri + assign $3\xive14_pri$next[7:0]$15196 \xive14_pri + assign $3\xive15_pri$next[7:0]$15197 \xive15_pri + assign $3\xive1_pri$next[7:0]$15198 \xive1_pri + assign $3\xive2_pri$next[7:0]$15199 \xive2_pri + assign $3\xive3_pri$next[7:0]$15200 \xive3_pri + assign $3\xive4_pri$next[7:0]$15201 \xive4_pri + assign $3\xive5_pri$next[7:0]$15202 \xive5_pri + assign $3\xive6_pri$next[7:0]$15203 \xive6_pri + assign $3\xive7_pri$next[7:0]$15204 \xive7_pri + assign $3\xive8_pri$next[7:0]$15205 \xive8_pri + assign $3\xive9_pri$next[7:0]$15206 \xive9_pri + assign $3\xive11_pri$next[7:0]$15193 \be_in [7:0] + attribute \src "libresoc.v:0.0-0.0" + case 4'1100 + assign $3\xive0_pri$next[7:0]$15191 \xive0_pri + assign $3\xive10_pri$next[7:0]$15192 \xive10_pri + assign $3\xive11_pri$next[7:0]$15193 \xive11_pri + assign { } { } + assign $3\xive13_pri$next[7:0]$15195 \xive13_pri + assign $3\xive14_pri$next[7:0]$15196 \xive14_pri + assign $3\xive15_pri$next[7:0]$15197 \xive15_pri + assign $3\xive1_pri$next[7:0]$15198 \xive1_pri + assign $3\xive2_pri$next[7:0]$15199 \xive2_pri + assign $3\xive3_pri$next[7:0]$15200 \xive3_pri + assign $3\xive4_pri$next[7:0]$15201 \xive4_pri + assign $3\xive5_pri$next[7:0]$15202 \xive5_pri + assign $3\xive6_pri$next[7:0]$15203 \xive6_pri + assign $3\xive7_pri$next[7:0]$15204 \xive7_pri + assign $3\xive8_pri$next[7:0]$15205 \xive8_pri + assign $3\xive9_pri$next[7:0]$15206 \xive9_pri + assign $3\xive12_pri$next[7:0]$15194 \be_in [7:0] + attribute \src "libresoc.v:0.0-0.0" + case 4'1101 + assign $3\xive0_pri$next[7:0]$15191 \xive0_pri + assign $3\xive10_pri$next[7:0]$15192 \xive10_pri + assign $3\xive11_pri$next[7:0]$15193 \xive11_pri + assign $3\xive12_pri$next[7:0]$15194 \xive12_pri + assign { } { } + assign $3\xive14_pri$next[7:0]$15196 \xive14_pri + assign $3\xive15_pri$next[7:0]$15197 \xive15_pri + assign $3\xive1_pri$next[7:0]$15198 \xive1_pri + assign $3\xive2_pri$next[7:0]$15199 \xive2_pri + assign $3\xive3_pri$next[7:0]$15200 \xive3_pri + assign $3\xive4_pri$next[7:0]$15201 \xive4_pri + assign $3\xive5_pri$next[7:0]$15202 \xive5_pri + assign $3\xive6_pri$next[7:0]$15203 \xive6_pri + assign $3\xive7_pri$next[7:0]$15204 \xive7_pri + assign $3\xive8_pri$next[7:0]$15205 \xive8_pri + assign $3\xive9_pri$next[7:0]$15206 \xive9_pri + assign $3\xive13_pri$next[7:0]$15195 \be_in [7:0] + attribute \src "libresoc.v:0.0-0.0" + case 4'1110 + assign $3\xive0_pri$next[7:0]$15191 \xive0_pri + assign $3\xive10_pri$next[7:0]$15192 \xive10_pri + assign $3\xive11_pri$next[7:0]$15193 \xive11_pri + assign $3\xive12_pri$next[7:0]$15194 \xive12_pri + assign $3\xive13_pri$next[7:0]$15195 \xive13_pri + assign { } { } + assign $3\xive15_pri$next[7:0]$15197 \xive15_pri + assign $3\xive1_pri$next[7:0]$15198 \xive1_pri + assign $3\xive2_pri$next[7:0]$15199 \xive2_pri + assign $3\xive3_pri$next[7:0]$15200 \xive3_pri + assign $3\xive4_pri$next[7:0]$15201 \xive4_pri + assign $3\xive5_pri$next[7:0]$15202 \xive5_pri + assign $3\xive6_pri$next[7:0]$15203 \xive6_pri + assign $3\xive7_pri$next[7:0]$15204 \xive7_pri + assign $3\xive8_pri$next[7:0]$15205 \xive8_pri + assign $3\xive9_pri$next[7:0]$15206 \xive9_pri + assign $3\xive14_pri$next[7:0]$15196 \be_in [7:0] + attribute \src "libresoc.v:0.0-0.0" + case 4'---- + assign $3\xive0_pri$next[7:0]$15191 \xive0_pri + assign $3\xive10_pri$next[7:0]$15192 \xive10_pri + assign $3\xive11_pri$next[7:0]$15193 \xive11_pri + assign $3\xive12_pri$next[7:0]$15194 \xive12_pri + assign $3\xive13_pri$next[7:0]$15195 \xive13_pri + assign $3\xive14_pri$next[7:0]$15196 \xive14_pri + assign { } { } + assign $3\xive1_pri$next[7:0]$15198 \xive1_pri + assign $3\xive2_pri$next[7:0]$15199 \xive2_pri + assign $3\xive3_pri$next[7:0]$15200 \xive3_pri + assign $3\xive4_pri$next[7:0]$15201 \xive4_pri + assign $3\xive5_pri$next[7:0]$15202 \xive5_pri + assign $3\xive6_pri$next[7:0]$15203 \xive6_pri + assign $3\xive7_pri$next[7:0]$15204 \xive7_pri + assign $3\xive8_pri$next[7:0]$15205 \xive8_pri + assign $3\xive9_pri$next[7:0]$15206 \xive9_pri + assign $3\xive15_pri$next[7:0]$15197 \be_in [7:0] + case + assign $3\xive0_pri$next[7:0]$15191 \xive0_pri + assign $3\xive10_pri$next[7:0]$15192 \xive10_pri + assign $3\xive11_pri$next[7:0]$15193 \xive11_pri + assign $3\xive12_pri$next[7:0]$15194 \xive12_pri + assign $3\xive13_pri$next[7:0]$15195 \xive13_pri + assign $3\xive14_pri$next[7:0]$15196 \xive14_pri + assign $3\xive15_pri$next[7:0]$15197 \xive15_pri + assign $3\xive1_pri$next[7:0]$15198 \xive1_pri + assign $3\xive2_pri$next[7:0]$15199 \xive2_pri + assign $3\xive3_pri$next[7:0]$15200 \xive3_pri + assign $3\xive4_pri$next[7:0]$15201 \xive4_pri + assign $3\xive5_pri$next[7:0]$15202 \xive5_pri + assign $3\xive6_pri$next[7:0]$15203 \xive6_pri + assign $3\xive7_pri$next[7:0]$15204 \xive7_pri + assign $3\xive8_pri$next[7:0]$15205 \xive8_pri + assign $3\xive9_pri$next[7:0]$15206 \xive9_pri + end + case + assign $2\xive0_pri$next[7:0]$15175 \xive0_pri + assign $2\xive10_pri$next[7:0]$15176 \xive10_pri + assign $2\xive11_pri$next[7:0]$15177 \xive11_pri + assign $2\xive12_pri$next[7:0]$15178 \xive12_pri + assign $2\xive13_pri$next[7:0]$15179 \xive13_pri + assign $2\xive14_pri$next[7:0]$15180 \xive14_pri + assign $2\xive15_pri$next[7:0]$15181 \xive15_pri + assign $2\xive1_pri$next[7:0]$15182 \xive1_pri + assign $2\xive2_pri$next[7:0]$15183 \xive2_pri + assign $2\xive3_pri$next[7:0]$15184 \xive3_pri + assign $2\xive4_pri$next[7:0]$15185 \xive4_pri + assign $2\xive5_pri$next[7:0]$15186 \xive5_pri + assign $2\xive6_pri$next[7:0]$15187 \xive6_pri + assign $2\xive7_pri$next[7:0]$15188 \xive7_pri + assign $2\xive8_pri$next[7:0]$15189 \xive8_pri + assign $2\xive9_pri$next[7:0]$15190 \xive9_pri + end + case + assign $1\xive0_pri$next[7:0]$15159 \xive0_pri + assign $1\xive10_pri$next[7:0]$15160 \xive10_pri + assign $1\xive11_pri$next[7:0]$15161 \xive11_pri + assign $1\xive12_pri$next[7:0]$15162 \xive12_pri + assign $1\xive13_pri$next[7:0]$15163 \xive13_pri + assign $1\xive14_pri$next[7:0]$15164 \xive14_pri + assign $1\xive15_pri$next[7:0]$15165 \xive15_pri + assign $1\xive1_pri$next[7:0]$15166 \xive1_pri + assign $1\xive2_pri$next[7:0]$15167 \xive2_pri + assign $1\xive3_pri$next[7:0]$15168 \xive3_pri + assign $1\xive4_pri$next[7:0]$15169 \xive4_pri + assign $1\xive5_pri$next[7:0]$15170 \xive5_pri + assign $1\xive6_pri$next[7:0]$15171 \xive6_pri + assign $1\xive7_pri$next[7:0]$15172 \xive7_pri + assign $1\xive8_pri$next[7:0]$15173 \xive8_pri + assign $1\xive9_pri$next[7:0]$15174 \xive9_pri + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $4\xive0_pri$next[7:0]$15207 8'11111111 + assign $4\xive1_pri$next[7:0]$15214 8'11111111 + assign $4\xive2_pri$next[7:0]$15215 8'11111111 + assign $4\xive3_pri$next[7:0]$15216 8'11111111 + assign $4\xive4_pri$next[7:0]$15217 8'11111111 + assign $4\xive5_pri$next[7:0]$15218 8'11111111 + assign $4\xive6_pri$next[7:0]$15219 8'11111111 + assign $4\xive7_pri$next[7:0]$15220 8'11111111 + assign $4\xive8_pri$next[7:0]$15221 8'11111111 + assign $4\xive9_pri$next[7:0]$15222 8'11111111 + assign $4\xive10_pri$next[7:0]$15208 8'11111111 + assign $4\xive11_pri$next[7:0]$15209 8'11111111 + assign $4\xive12_pri$next[7:0]$15210 8'11111111 + assign $4\xive13_pri$next[7:0]$15211 8'11111111 + assign $4\xive14_pri$next[7:0]$15212 8'11111111 + assign $4\xive15_pri$next[7:0]$15213 8'11111111 + case + assign $4\xive0_pri$next[7:0]$15207 $1\xive0_pri$next[7:0]$15159 + assign $4\xive10_pri$next[7:0]$15208 $1\xive10_pri$next[7:0]$15160 + assign $4\xive11_pri$next[7:0]$15209 $1\xive11_pri$next[7:0]$15161 + assign $4\xive12_pri$next[7:0]$15210 $1\xive12_pri$next[7:0]$15162 + assign $4\xive13_pri$next[7:0]$15211 $1\xive13_pri$next[7:0]$15163 + assign $4\xive14_pri$next[7:0]$15212 $1\xive14_pri$next[7:0]$15164 + assign $4\xive15_pri$next[7:0]$15213 $1\xive15_pri$next[7:0]$15165 + assign $4\xive1_pri$next[7:0]$15214 $1\xive1_pri$next[7:0]$15166 + assign $4\xive2_pri$next[7:0]$15215 $1\xive2_pri$next[7:0]$15167 + assign $4\xive3_pri$next[7:0]$15216 $1\xive3_pri$next[7:0]$15168 + assign $4\xive4_pri$next[7:0]$15217 $1\xive4_pri$next[7:0]$15169 + assign $4\xive5_pri$next[7:0]$15218 $1\xive5_pri$next[7:0]$15170 + assign $4\xive6_pri$next[7:0]$15219 $1\xive6_pri$next[7:0]$15171 + assign $4\xive7_pri$next[7:0]$15220 $1\xive7_pri$next[7:0]$15172 + assign $4\xive8_pri$next[7:0]$15221 $1\xive8_pri$next[7:0]$15173 + assign $4\xive9_pri$next[7:0]$15222 $1\xive9_pri$next[7:0]$15174 + end + sync always + update \xive0_pri$next $0\xive0_pri$next[7:0]$15143 + update \xive10_pri$next $0\xive10_pri$next[7:0]$15144 + update \xive11_pri$next $0\xive11_pri$next[7:0]$15145 + update \xive12_pri$next $0\xive12_pri$next[7:0]$15146 + update \xive13_pri$next $0\xive13_pri$next[7:0]$15147 + update \xive14_pri$next $0\xive14_pri$next[7:0]$15148 + update \xive15_pri$next $0\xive15_pri$next[7:0]$15149 + update \xive1_pri$next $0\xive1_pri$next[7:0]$15150 + update \xive2_pri$next $0\xive2_pri$next[7:0]$15151 + update \xive3_pri$next $0\xive3_pri$next[7:0]$15152 + update \xive4_pri$next $0\xive4_pri$next[7:0]$15153 + update \xive5_pri$next $0\xive5_pri$next[7:0]$15154 + update \xive6_pri$next $0\xive6_pri$next[7:0]$15155 + update \xive7_pri$next $0\xive7_pri$next[7:0]$15156 + update \xive8_pri$next $0\xive8_pri$next[7:0]$15157 + update \xive9_pri$next $0\xive9_pri$next[7:0]$15158 + end + attribute \src "libresoc.v:206053.3-206062.6" + process $proc$libresoc.v:206053$15223 + assign { } { } + assign { } { } + assign $0\cur_pri0[7:0] $1\cur_pri0[7:0] + attribute \src "libresoc.v:206054.5-206054.29" + switch \initial + attribute \src "libresoc.v:206054.9-206054.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$77 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_pri0[7:0] \xive0_pri + case + assign $1\cur_pri0[7:0] \max_pri + end + sync always + update \cur_pri0 $0\cur_pri0[7:0] + end + attribute \src "libresoc.v:206063.3-206072.6" + process $proc$libresoc.v:206063$15224 + assign { } { } + assign { } { } + assign $0\cur_idx0[3:0] $1\cur_idx0[3:0] + attribute \src "libresoc.v:206064.5-206064.29" + switch \initial + attribute \src "libresoc.v:206064.9-206064.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$81 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_idx0[3:0] 4'0000 + case + assign $1\cur_idx0[3:0] \max_idx + end + sync always + update \cur_idx0 $0\cur_idx0[3:0] + end + attribute \src "libresoc.v:206073.3-206082.6" + process $proc$libresoc.v:206073$15225 + assign { } { } + assign { } { } + assign $0\cur_pri1[7:0] $1\cur_pri1[7:0] + attribute \src "libresoc.v:206074.5-206074.29" + switch \initial + attribute \src "libresoc.v:206074.9-206074.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$85 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_pri1[7:0] \xive1_pri + case + assign $1\cur_pri1[7:0] \cur_pri0 + end + sync always + update \cur_pri1 $0\cur_pri1[7:0] + end + attribute \src "libresoc.v:206083.3-206092.6" + process $proc$libresoc.v:206083$15226 + assign { } { } + assign { } { } + assign $0\cur_idx1[3:0] $1\cur_idx1[3:0] + attribute \src "libresoc.v:206084.5-206084.29" + switch \initial + attribute \src "libresoc.v:206084.9-206084.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$89 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_idx1[3:0] 4'0001 + case + assign $1\cur_idx1[3:0] \cur_idx0 + end + sync always + update \cur_idx1 $0\cur_idx1[3:0] + end + attribute \src "libresoc.v:206093.3-206102.6" + process $proc$libresoc.v:206093$15227 + assign { } { } + assign { } { } + assign $0\cur_pri2[7:0] $1\cur_pri2[7:0] + attribute \src "libresoc.v:206094.5-206094.29" + switch \initial + attribute \src "libresoc.v:206094.9-206094.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$93 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_pri2[7:0] \xive2_pri + case + assign $1\cur_pri2[7:0] \cur_pri1 + end + sync always + update \cur_pri2 $0\cur_pri2[7:0] + end + attribute \src "libresoc.v:206103.3-206112.6" + process $proc$libresoc.v:206103$15228 + assign { } { } + assign { } { } + assign $0\cur_idx2[3:0] $1\cur_idx2[3:0] + attribute \src "libresoc.v:206104.5-206104.29" + switch \initial + attribute \src "libresoc.v:206104.9-206104.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$97 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_idx2[3:0] 4'0010 + case + assign $1\cur_idx2[3:0] \cur_idx1 + end + sync always + update \cur_idx2 $0\cur_idx2[3:0] + end + attribute \src "libresoc.v:206113.3-206122.6" + process $proc$libresoc.v:206113$15229 + assign { } { } + assign { } { } + assign $0\cur_pri3[7:0] $1\cur_pri3[7:0] + attribute \src "libresoc.v:206114.5-206114.29" + switch \initial + attribute \src "libresoc.v:206114.9-206114.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$101 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_pri3[7:0] \xive3_pri + case + assign $1\cur_pri3[7:0] \cur_pri2 + end + sync always + update \cur_pri3 $0\cur_pri3[7:0] + end + attribute \src "libresoc.v:206123.3-206132.6" + process $proc$libresoc.v:206123$15230 + assign { } { } + assign { } { } + assign $0\cur_idx3[3:0] $1\cur_idx3[3:0] + attribute \src "libresoc.v:206124.5-206124.29" + switch \initial + attribute \src "libresoc.v:206124.9-206124.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$105 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_idx3[3:0] 4'0011 + case + assign $1\cur_idx3[3:0] \cur_idx2 + end + sync always + update \cur_idx3 $0\cur_idx3[3:0] + end + attribute \src "libresoc.v:206133.3-206142.6" + process $proc$libresoc.v:206133$15231 + assign { } { } + assign { } { } + assign $0\cur_pri4[7:0] $1\cur_pri4[7:0] + attribute \src "libresoc.v:206134.5-206134.29" + switch \initial + attribute \src "libresoc.v:206134.9-206134.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$109 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_pri4[7:0] \xive4_pri + case + assign $1\cur_pri4[7:0] \cur_pri3 + end + sync always + update \cur_pri4 $0\cur_pri4[7:0] + end + attribute \src "libresoc.v:206143.3-206151.6" + process $proc$libresoc.v:206143$15232 + assign { } { } + assign { } { } + assign $0\int_level_l$next[15:0]$15233 $1\int_level_l$next[15:0]$15234 + attribute \src "libresoc.v:206144.5-206144.29" + switch \initial + attribute \src "libresoc.v:206144.9-206144.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\int_level_l$next[15:0]$15234 16'0000000000000000 + case + assign $1\int_level_l$next[15:0]$15234 \int_level_i + end + sync always + update \int_level_l$next $0\int_level_l$next[15:0]$15233 + end + attribute \src "libresoc.v:206152.3-206161.6" + process $proc$libresoc.v:206152$15235 + assign { } { } + assign { } { } + assign $0\cur_idx4[3:0] $1\cur_idx4[3:0] + attribute \src "libresoc.v:206153.5-206153.29" + switch \initial + attribute \src "libresoc.v:206153.9-206153.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$113 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_idx4[3:0] 4'0100 + case + assign $1\cur_idx4[3:0] \cur_idx3 + end + sync always + update \cur_idx4 $0\cur_idx4[3:0] + end + attribute \src "libresoc.v:206162.3-206171.6" + process $proc$libresoc.v:206162$15236 + assign { } { } + assign { } { } + assign $0\cur_pri5[7:0] $1\cur_pri5[7:0] + attribute \src "libresoc.v:206163.5-206163.29" + switch \initial + attribute \src "libresoc.v:206163.9-206163.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$117 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_pri5[7:0] \xive5_pri + case + assign $1\cur_pri5[7:0] \cur_pri4 + end + sync always + update \cur_pri5 $0\cur_pri5[7:0] + end + attribute \src "libresoc.v:206172.3-206181.6" + process $proc$libresoc.v:206172$15237 + assign { } { } + assign { } { } + assign $0\cur_idx5[3:0] $1\cur_idx5[3:0] + attribute \src "libresoc.v:206173.5-206173.29" + switch \initial + attribute \src "libresoc.v:206173.9-206173.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$121 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_idx5[3:0] 4'0101 + case + assign $1\cur_idx5[3:0] \cur_idx4 + end + sync always + update \cur_idx5 $0\cur_idx5[3:0] + end + attribute \src "libresoc.v:206182.3-206191.6" + process $proc$libresoc.v:206182$15238 + assign { } { } + assign { } { } + assign $0\cur_pri6[7:0] $1\cur_pri6[7:0] + attribute \src "libresoc.v:206183.5-206183.29" + switch \initial + attribute \src "libresoc.v:206183.9-206183.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$125 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_pri6[7:0] \xive6_pri + case + assign $1\cur_pri6[7:0] \cur_pri5 + end + sync always + update \cur_pri6 $0\cur_pri6[7:0] + end + attribute \src "libresoc.v:206192.3-206201.6" + process $proc$libresoc.v:206192$15239 + assign { } { } + assign { } { } + assign $0\cur_idx6[3:0] $1\cur_idx6[3:0] + attribute \src "libresoc.v:206193.5-206193.29" + switch \initial + attribute \src "libresoc.v:206193.9-206193.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$129 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_idx6[3:0] 4'0110 + case + assign $1\cur_idx6[3:0] \cur_idx5 + end + sync always + update \cur_idx6 $0\cur_idx6[3:0] + end + attribute \src "libresoc.v:206202.3-206211.6" + process $proc$libresoc.v:206202$15240 + assign { } { } + assign { } { } + assign $0\cur_pri7[7:0] $1\cur_pri7[7:0] + attribute \src "libresoc.v:206203.5-206203.29" + switch \initial + attribute \src "libresoc.v:206203.9-206203.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$133 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_pri7[7:0] \xive7_pri + case + assign $1\cur_pri7[7:0] \cur_pri6 + end + sync always + update \cur_pri7 $0\cur_pri7[7:0] + end + attribute \src "libresoc.v:206212.3-206221.6" + process $proc$libresoc.v:206212$15241 + assign { } { } + assign { } { } + assign $0\cur_idx7[3:0] $1\cur_idx7[3:0] + attribute \src "libresoc.v:206213.5-206213.29" + switch \initial + attribute \src "libresoc.v:206213.9-206213.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$137 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_idx7[3:0] 4'0111 + case + assign $1\cur_idx7[3:0] \cur_idx6 + end + sync always + update \cur_idx7 $0\cur_idx7[3:0] + end + attribute \src "libresoc.v:206222.3-206231.6" + process $proc$libresoc.v:206222$15242 + assign { } { } + assign { } { } + assign $0\cur_pri8[7:0] $1\cur_pri8[7:0] + attribute \src "libresoc.v:206223.5-206223.29" + switch \initial + attribute \src "libresoc.v:206223.9-206223.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$141 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_pri8[7:0] \xive8_pri + case + assign $1\cur_pri8[7:0] \cur_pri7 + end + sync always + update \cur_pri8 $0\cur_pri8[7:0] + end + attribute \src "libresoc.v:206232.3-206241.6" + process $proc$libresoc.v:206232$15243 + assign { } { } + assign { } { } + assign $0\cur_idx8[3:0] $1\cur_idx8[3:0] + attribute \src "libresoc.v:206233.5-206233.29" + switch \initial + attribute \src "libresoc.v:206233.9-206233.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$145 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_idx8[3:0] 4'1000 + case + assign $1\cur_idx8[3:0] \cur_idx7 + end + sync always + update \cur_idx8 $0\cur_idx8[3:0] + end + attribute \src "libresoc.v:206242.3-206251.6" + process $proc$libresoc.v:206242$15244 + assign { } { } + assign { } { } + assign $0\cur_pri9[7:0] $1\cur_pri9[7:0] + attribute \src "libresoc.v:206243.5-206243.29" + switch \initial + attribute \src "libresoc.v:206243.9-206243.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$149 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_pri9[7:0] \xive9_pri + case + assign $1\cur_pri9[7:0] \cur_pri8 + end + sync always + update \cur_pri9 $0\cur_pri9[7:0] + end + attribute \src "libresoc.v:206252.3-206261.6" + process $proc$libresoc.v:206252$15245 + assign { } { } + assign { } { } + assign $0\cur_idx9[3:0] $1\cur_idx9[3:0] + attribute \src "libresoc.v:206253.5-206253.29" + switch \initial + attribute \src "libresoc.v:206253.9-206253.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$153 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_idx9[3:0] 4'1001 + case + assign $1\cur_idx9[3:0] \cur_idx8 + end + sync always + update \cur_idx9 $0\cur_idx9[3:0] + end + attribute \src "libresoc.v:206262.3-206271.6" + process $proc$libresoc.v:206262$15246 + assign { } { } + assign { } { } + assign $0\cur_pri10[7:0] $1\cur_pri10[7:0] + attribute \src "libresoc.v:206263.5-206263.29" + switch \initial + attribute \src "libresoc.v:206263.9-206263.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$157 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_pri10[7:0] \xive10_pri + case + assign $1\cur_pri10[7:0] \cur_pri9 + end + sync always + update \cur_pri10 $0\cur_pri10[7:0] + end + attribute \src "libresoc.v:206272.3-206281.6" + process $proc$libresoc.v:206272$15247 + assign { } { } + assign { } { } + assign $0\cur_idx10[3:0] $1\cur_idx10[3:0] + attribute \src "libresoc.v:206273.5-206273.29" + switch \initial + attribute \src "libresoc.v:206273.9-206273.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$161 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_idx10[3:0] 4'1010 + case + assign $1\cur_idx10[3:0] \cur_idx9 + end + sync always + update \cur_idx10 $0\cur_idx10[3:0] + end + attribute \src "libresoc.v:206282.3-206291.6" + process $proc$libresoc.v:206282$15248 + assign { } { } + assign { } { } + assign $0\cur_pri11[7:0] $1\cur_pri11[7:0] + attribute \src "libresoc.v:206283.5-206283.29" + switch \initial + attribute \src "libresoc.v:206283.9-206283.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$165 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_pri11[7:0] \xive11_pri + case + assign $1\cur_pri11[7:0] \cur_pri10 + end + sync always + update \cur_pri11 $0\cur_pri11[7:0] + end + attribute \src "libresoc.v:206292.3-206301.6" + process $proc$libresoc.v:206292$15249 + assign { } { } + assign { } { } + assign $0\cur_idx11[3:0] $1\cur_idx11[3:0] + attribute \src "libresoc.v:206293.5-206293.29" + switch \initial + attribute \src "libresoc.v:206293.9-206293.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$169 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_idx11[3:0] 4'1011 + case + assign $1\cur_idx11[3:0] \cur_idx10 + end + sync always + update \cur_idx11 $0\cur_idx11[3:0] + end + attribute \src "libresoc.v:206302.3-206311.6" + process $proc$libresoc.v:206302$15250 + assign { } { } + assign { } { } + assign $0\cur_pri12[7:0] $1\cur_pri12[7:0] + attribute \src "libresoc.v:206303.5-206303.29" + switch \initial + attribute \src "libresoc.v:206303.9-206303.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$173 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_pri12[7:0] \xive12_pri + case + assign $1\cur_pri12[7:0] \cur_pri11 + end + sync always + update \cur_pri12 $0\cur_pri12[7:0] + end + attribute \src "libresoc.v:206312.3-206321.6" + process $proc$libresoc.v:206312$15251 + assign { } { } + assign { } { } + assign $0\cur_idx12[3:0] $1\cur_idx12[3:0] + attribute \src "libresoc.v:206313.5-206313.29" + switch \initial + attribute \src "libresoc.v:206313.9-206313.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$177 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_idx12[3:0] 4'1100 + case + assign $1\cur_idx12[3:0] \cur_idx11 + end + sync always + update \cur_idx12 $0\cur_idx12[3:0] + end + attribute \src "libresoc.v:206322.3-206331.6" + process $proc$libresoc.v:206322$15252 + assign { } { } + assign { } { } + assign $0\cur_pri13[7:0] $1\cur_pri13[7:0] + attribute \src "libresoc.v:206323.5-206323.29" + switch \initial + attribute \src "libresoc.v:206323.9-206323.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$181 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_pri13[7:0] \xive13_pri + case + assign $1\cur_pri13[7:0] \cur_pri12 + end + sync always + update \cur_pri13 $0\cur_pri13[7:0] + end + attribute \src "libresoc.v:206332.3-206341.6" + process $proc$libresoc.v:206332$15253 + assign { } { } + assign { } { } + assign $0\cur_idx13[3:0] $1\cur_idx13[3:0] + attribute \src "libresoc.v:206333.5-206333.29" + switch \initial + attribute \src "libresoc.v:206333.9-206333.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$185 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_idx13[3:0] 4'1101 + case + assign $1\cur_idx13[3:0] \cur_idx12 + end + sync always + update \cur_idx13 $0\cur_idx13[3:0] + end + attribute \src "libresoc.v:206342.3-206351.6" + process $proc$libresoc.v:206342$15254 + assign { } { } + assign { } { } + assign $0\cur_pri14[7:0] $1\cur_pri14[7:0] + attribute \src "libresoc.v:206343.5-206343.29" + switch \initial + attribute \src "libresoc.v:206343.9-206343.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$189 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_pri14[7:0] \xive14_pri + case + assign $1\cur_pri14[7:0] \cur_pri13 + end + sync always + update \cur_pri14 $0\cur_pri14[7:0] + end + attribute \src "libresoc.v:206352.3-206401.6" + process $proc$libresoc.v:206352$15255 + assign { } { } + assign { } { } + assign $0\be_out[31:0] $1\be_out[31:0] + attribute \src "libresoc.v:206353.5-206353.29" + switch \initial + attribute \src "libresoc.v:206353.9-206353.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:312" + switch { \reg_is_debug \reg_is_config \reg_is_xive } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign { } { } + assign $1\be_out[31:0] $2\be_out[31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + switch \reg_idx + attribute \src "libresoc.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$7 } + attribute \src "libresoc.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$11 } + attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$15 } + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$19 } + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$23 } + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$27 } + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$31 } + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$35 } + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$39 } + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$43 } + attribute \src "libresoc.v:0.0-0.0" + case 4'1010 + assign { } { } + assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$47 } + attribute \src "libresoc.v:0.0-0.0" + case 4'1011 + assign { } { } + assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$51 } + attribute \src "libresoc.v:0.0-0.0" + case 4'1100 + assign { } { } + assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$55 } + attribute \src "libresoc.v:0.0-0.0" + case 4'1101 + assign { } { } + assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$59 } + attribute \src "libresoc.v:0.0-0.0" + case 4'1110 + assign { } { } + assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$63 } + attribute \src "libresoc.v:0.0-0.0" + case 4'---- + assign { } { } + assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$67 } + case + assign $2\be_out[31:0] 0 + end + attribute \src "libresoc.v:0.0-0.0" + case 3'-1- + assign { } { } + assign $1\be_out[31:0] 134217744 + attribute \src "libresoc.v:0.0-0.0" + case 3'1-- + assign { } { } + assign $1\be_out[31:0] { \icp_r_src 20'00000000000000000000 \icp_r_pri } + case + assign $1\be_out[31:0] 0 + end + sync always + update \be_out $0\be_out[31:0] + end + attribute \src "libresoc.v:206402.3-206411.6" + process $proc$libresoc.v:206402$15256 + assign { } { } + assign { } { } + assign $0\cur_idx14[3:0] $1\cur_idx14[3:0] + attribute \src "libresoc.v:206403.5-206403.29" + switch \initial + attribute \src "libresoc.v:206403.9-206403.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$193 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_idx14[3:0] 4'1110 + case + assign $1\cur_idx14[3:0] \cur_idx13 + end + sync always + update \cur_idx14 $0\cur_idx14[3:0] + end + attribute \src "libresoc.v:206412.3-206421.6" + process $proc$libresoc.v:206412$15257 + assign { } { } + assign { } { } + assign $0\cur_pri15[7:0] $1\cur_pri15[7:0] + attribute \src "libresoc.v:206413.5-206413.29" + switch \initial + attribute \src "libresoc.v:206413.9-206413.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$197 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_pri15[7:0] \xive15_pri + case + assign $1\cur_pri15[7:0] \cur_pri14 + end + sync always + update \cur_pri15 $0\cur_pri15[7:0] + end + attribute \src "libresoc.v:206422.3-206431.6" + process $proc$libresoc.v:206422$15258 + assign { } { } + assign { } { } + assign $0\cur_idx15[3:0] $1\cur_idx15[3:0] + attribute \src "libresoc.v:206423.5-206423.29" + switch \initial + attribute \src "libresoc.v:206423.9-206423.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$201 + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_idx15[3:0] 4'1111 + case + assign $1\cur_idx15[3:0] \cur_idx14 + end + sync always + update \cur_idx15 $0\cur_idx15[3:0] + end + attribute \src "libresoc.v:206432.3-206441.6" + process $proc$libresoc.v:206432$15259 + assign { } { } + assign { } { } + assign $0\ibit[0:0] $1\ibit[0:0] + attribute \src "libresoc.v:206433.5-206433.29" + switch \initial + attribute \src "libresoc.v:206433.9-206433.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:312" + switch { \reg_is_debug \reg_is_config \reg_is_xive } + attribute \src "libresoc.v:0.0-0.0" + case 3'--1 + assign { } { } + assign $1\ibit[0:0] \$71 + case + assign $1\ibit[0:0] 1'0 + end + sync always + update \ibit $0\ibit[0:0] + end + attribute \src "libresoc.v:206442.3-206450.6" + process $proc$libresoc.v:206442$15260 + assign { } { } + assign { } { } + assign $0\ics_wb__dat_r$next[31:0]$15261 $1\ics_wb__dat_r$next[31:0]$15262 + attribute \src "libresoc.v:206443.5-206443.29" + switch \initial + attribute \src "libresoc.v:206443.9-206443.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ics_wb__dat_r$next[31:0]$15262 0 + case + assign $1\ics_wb__dat_r$next[31:0]$15262 { \be_out [7:0] \be_out [15:8] \be_out [23:16] \be_out [31:24] } + end + sync always + update \ics_wb__dat_r$next $0\ics_wb__dat_r$next[31:0]$15261 + end + attribute \src "libresoc.v:206451.3-206459.6" + process $proc$libresoc.v:206451$15263 + assign { } { } + assign { } { } + assign $0\ics_wb__ack$next[0:0]$15264 $1\ics_wb__ack$next[0:0]$15265 + attribute \src "libresoc.v:206452.5-206452.29" + switch \initial + attribute \src "libresoc.v:206452.9-206452.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "libresoc.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ics_wb__ack$next[0:0]$15265 1'0 + case + assign $1\ics_wb__ack$next[0:0]$15265 \wb_valid + end + sync always + update \ics_wb__ack$next $0\ics_wb__ack$next[0:0]$15264 + end + connect \$7 $ternary$libresoc.v:205822$15018_Y + connect \$99 $lt$libresoc.v:205823$15019_Y + connect \$101 $and$libresoc.v:205824$15020_Y + connect \$103 $lt$libresoc.v:205825$15021_Y + connect \$105 $and$libresoc.v:205826$15022_Y + connect \$107 $lt$libresoc.v:205827$15023_Y + connect \$109 $and$libresoc.v:205828$15024_Y + connect \$111 $lt$libresoc.v:205829$15025_Y + connect \$113 $and$libresoc.v:205830$15026_Y + connect \$115 $lt$libresoc.v:205831$15027_Y + connect \$117 $and$libresoc.v:205832$15028_Y + connect \$119 $lt$libresoc.v:205833$15029_Y + connect \$121 $and$libresoc.v:205834$15030_Y + connect \$123 $lt$libresoc.v:205835$15031_Y + connect \$125 $and$libresoc.v:205836$15032_Y + connect \$127 $lt$libresoc.v:205837$15033_Y + connect \$12 $eq$libresoc.v:205838$15034_Y + connect \$129 $and$libresoc.v:205839$15035_Y + connect \$131 $lt$libresoc.v:205840$15036_Y + connect \$133 $and$libresoc.v:205841$15037_Y + connect \$135 $lt$libresoc.v:205842$15038_Y + connect \$137 $and$libresoc.v:205843$15039_Y + connect \$11 $ternary$libresoc.v:205844$15040_Y + connect \$139 $lt$libresoc.v:205845$15041_Y + connect \$141 $and$libresoc.v:205846$15042_Y + connect \$143 $lt$libresoc.v:205847$15043_Y + connect \$145 $and$libresoc.v:205848$15044_Y + connect \$147 $lt$libresoc.v:205849$15045_Y + connect \$149 $and$libresoc.v:205850$15046_Y + connect \$151 $lt$libresoc.v:205851$15047_Y + connect \$153 $and$libresoc.v:205852$15048_Y + connect \$155 $lt$libresoc.v:205853$15049_Y + connect \$157 $and$libresoc.v:205854$15050_Y + connect \$159 $lt$libresoc.v:205855$15051_Y + connect \$161 $and$libresoc.v:205856$15052_Y + connect \$163 $lt$libresoc.v:205857$15053_Y + connect \$165 $and$libresoc.v:205858$15054_Y + connect \$167 $lt$libresoc.v:205859$15055_Y + connect \$16 $eq$libresoc.v:205860$15056_Y + connect \$169 $and$libresoc.v:205861$15057_Y + connect \$171 $lt$libresoc.v:205862$15058_Y + connect \$173 $and$libresoc.v:205863$15059_Y + connect \$175 $lt$libresoc.v:205864$15060_Y + connect \$177 $and$libresoc.v:205865$15061_Y + connect \$15 $ternary$libresoc.v:205866$15062_Y + connect \$179 $lt$libresoc.v:205867$15063_Y + connect \$181 $and$libresoc.v:205868$15064_Y + connect \$183 $lt$libresoc.v:205869$15065_Y + connect \$185 $and$libresoc.v:205870$15066_Y + connect \$187 $lt$libresoc.v:205871$15067_Y + connect \$189 $and$libresoc.v:205872$15068_Y + connect \$191 $lt$libresoc.v:205873$15069_Y + connect \$193 $and$libresoc.v:205874$15070_Y + connect \$195 $lt$libresoc.v:205875$15071_Y + connect \$197 $and$libresoc.v:205876$15072_Y + connect \$1 $eq$libresoc.v:205877$15073_Y + connect \$199 $lt$libresoc.v:205878$15074_Y + connect \$201 $and$libresoc.v:205879$15075_Y + connect \$204 $eq$libresoc.v:205880$15076_Y + connect \$203 $ternary$libresoc.v:205881$15077_Y + connect \$20 $eq$libresoc.v:205882$15078_Y + connect \$19 $ternary$libresoc.v:205883$15079_Y + connect \$24 $eq$libresoc.v:205884$15080_Y + connect \$23 $ternary$libresoc.v:205885$15081_Y + connect \$28 $eq$libresoc.v:205886$15082_Y + connect \$27 $ternary$libresoc.v:205887$15083_Y + connect \$32 $eq$libresoc.v:205888$15084_Y + connect \$31 $ternary$libresoc.v:205889$15085_Y + connect \$36 $eq$libresoc.v:205890$15086_Y + connect \$35 $ternary$libresoc.v:205891$15087_Y + connect \$3 $eq$libresoc.v:205892$15088_Y + connect \$40 $eq$libresoc.v:205893$15089_Y + connect \$39 $ternary$libresoc.v:205894$15090_Y + connect \$44 $eq$libresoc.v:205895$15091_Y + connect \$43 $ternary$libresoc.v:205896$15092_Y + connect \$48 $eq$libresoc.v:205897$15093_Y + connect \$47 $ternary$libresoc.v:205898$15094_Y + connect \$52 $eq$libresoc.v:205899$15095_Y + connect \$51 $ternary$libresoc.v:205900$15096_Y + connect \$56 $eq$libresoc.v:205901$15097_Y + connect \$55 $ternary$libresoc.v:205902$15098_Y + connect \$5 $and$libresoc.v:205903$15099_Y + connect \$60 $eq$libresoc.v:205904$15100_Y + connect \$59 $ternary$libresoc.v:205905$15101_Y + connect \$64 $eq$libresoc.v:205906$15102_Y + connect \$63 $ternary$libresoc.v:205907$15103_Y + connect \$68 $eq$libresoc.v:205908$15104_Y + connect \$67 $ternary$libresoc.v:205909$15105_Y + connect \$71 $shr$libresoc.v:205910$15106_Y [0] + connect \$73 $and$libresoc.v:205911$15107_Y + connect \$75 $lt$libresoc.v:205912$15108_Y + connect \$77 $and$libresoc.v:205913$15109_Y + connect \$79 $lt$libresoc.v:205914$15110_Y + connect \$81 $and$libresoc.v:205915$15111_Y + connect \$83 $lt$libresoc.v:205916$15112_Y + connect \$85 $and$libresoc.v:205917$15113_Y + connect \$87 $lt$libresoc.v:205918$15114_Y + connect \$8 $eq$libresoc.v:205919$15115_Y + connect \$89 $and$libresoc.v:205920$15116_Y + connect \$91 $lt$libresoc.v:205921$15117_Y + connect \$93 $and$libresoc.v:205922$15118_Y + connect \$95 $lt$libresoc.v:205923$15119_Y + connect \$97 $and$libresoc.v:205924$15120_Y + connect \icp_r_pri \$203 + connect \icp_r_src \cur_idx15 + connect \max_idx 4'0000 + connect \max_pri 8'11111111 + connect { \icp_o_pri$next \icp_o_src$next } { \icp_r_pri \icp_r_src } + connect \be_in { \ics_wb__dat_w [7:0] \ics_wb__dat_w [15:8] \ics_wb__dat_w [23:16] \ics_wb__dat_w [31:24] } + connect \wb_valid \$5 + connect \reg_idx \ics_wb__adr [3:0] + connect \reg_is_debug \$3 + connect \reg_is_config \$1 + connect \reg_is_xive \ics_wb__adr [9] +end